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authorYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>2007-10-22 06:43:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-22 17:09:00 -0400
commit1097c6ac33defae6cf501b7919c23faf240601f0 (patch)
tree326fdeb21a0b0b67a569e74117c63d74620a0fb2 /arch
parentd04533650f64fe3367e180f3e488d92205152cd3 (diff)
[MIPS] time: Add GT641xx timer0 clockevent driver
And make use of it for Cobalt. A few others such as the Malta could make use of it as well. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig4
-rw-r--r--arch/mips/cobalt/Makefile2
-rw-r--r--arch/mips/cobalt/setup.c24
-rw-r--r--arch/mips/cobalt/time.c35
-rw-r--r--arch/mips/kernel/Makefile1
-rw-r--r--arch/mips/kernel/cevt-gt641xx.c144
6 files changed, 188 insertions, 22 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3ecff5e9e4f3..61262c5f9c62 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -66,6 +66,7 @@ config BCM47XX
66config MIPS_COBALT 66config MIPS_COBALT
67 bool "Cobalt Server" 67 bool "Cobalt Server"
68 select CEVT_R4K 68 select CEVT_R4K
69 select CEVT_GT641XX
69 select DMA_NONCOHERENT 70 select DMA_NONCOHERENT
70 select HW_HAS_PCI 71 select HW_HAS_PCI
71 select I8253 72 select I8253
@@ -729,6 +730,9 @@ config ARCH_MAY_HAVE_PC_FDC
729config BOOT_RAW 730config BOOT_RAW
730 bool 731 bool
731 732
733config CEVT_GT641XX
734 bool
735
732config CEVT_R4K 736config CEVT_R4K
733 bool 737 bool
734 738
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index 6b83f4ddc8fc..d73833b7c781 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the Cobalt micro systems family specific parts of the kernel 2# Makefile for the Cobalt micro systems family specific parts of the kernel
3# 3#
4 4
5obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o 5obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o time.o
6 6
7obj-$(CONFIG_PCI) += pci.o 7obj-$(CONFIG_PCI) += pci.o
8obj-$(CONFIG_EARLY_PRINTK) += console.o 8obj-$(CONFIG_EARLY_PRINTK) += console.o
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index d11bb1bc7b6b..dd23beb8604f 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -9,19 +9,17 @@
9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 9 * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10 * 10 *
11 */ 11 */
12#include <linux/interrupt.h>
13#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
14#include <linux/pm.h> 16#include <linux/pm.h>
15 17
16#include <asm/bootinfo.h> 18#include <asm/bootinfo.h>
17#include <asm/time.h>
18#include <asm/i8253.h>
19#include <asm/io.h>
20#include <asm/reboot.h> 19#include <asm/reboot.h>
21#include <asm/gt64120.h> 20#include <asm/gt64120.h>
22 21
23#include <cobalt.h> 22#include <cobalt.h>
24#include <irq.h>
25 23
26extern void cobalt_machine_restart(char *command); 24extern void cobalt_machine_restart(char *command);
27extern void cobalt_machine_halt(void); 25extern void cobalt_machine_halt(void);
@@ -41,17 +39,6 @@ const char *get_system_type(void)
41 return "MIPS Cobalt"; 39 return "MIPS Cobalt";
42} 40}
43 41
44void __init plat_timer_setup(struct irqaction *irq)
45{
46 /* Load timer value for HZ (TCLK is 50MHz) */
47 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
48
49 /* Enable timer0 */
50 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
51
52 setup_irq(GT641XX_TIMER0_IRQ, irq);
53}
54
55/* 42/*
56 * Cobalt doesn't have PS/2 keyboard/mouse interfaces, 43 * Cobalt doesn't have PS/2 keyboard/mouse interfaces,
57 * keyboard conntroller is never used. 44 * keyboard conntroller is never used.
@@ -84,11 +71,6 @@ static struct resource cobalt_reserved_resources[] = {
84 }, 71 },
85}; 72};
86 73
87void __init plat_time_init(void)
88{
89 setup_pit_timer();
90}
91
92void __init plat_mem_setup(void) 74void __init plat_mem_setup(void)
93{ 75{
94 int i; 76 int i;
diff --git a/arch/mips/cobalt/time.c b/arch/mips/cobalt/time.c
new file mode 100644
index 000000000000..fa819fccd5db
--- /dev/null
+++ b/arch/mips/cobalt/time.c
@@ -0,0 +1,35 @@
1/*
2 * Cobalt time initialization.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21
22#include <asm/gt64120.h>
23#include <asm/i8253.h>
24#include <asm/time.h>
25
26#define GT641XX_BASE_CLOCK 50000000 /* 50MHz */
27
28void __init plat_time_init(void)
29{
30 setup_pit_timer();
31
32 gt641xx_set_base_clock(GT641XX_BASE_CLOCK);
33
34 mips_timer_state = gt641xx_timer0_state;
35}
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index a3afa39faae5..d7745c8976f6 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -9,6 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
9 time.o topology.o traps.o unaligned.o 9 time.o topology.o traps.o unaligned.o
10 10
11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 11obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
12obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
12 13
13binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \ 14binfmt_irix-objs := irixelf.o irixinv.o irixioctl.o irixsig.o \
14 irix5sys.o sysirix.o 15 irix5sys.o sysirix.o
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
new file mode 100644
index 000000000000..4c651b2680f9
--- /dev/null
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -0,0 +1,144 @@
1/*
2 * GT641xx clockevent routines.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/clockchips.h>
21#include <linux/init.h>
22#include <linux/interrupt.h>
23#include <linux/spinlock.h>
24
25#include <asm/gt64120.h>
26#include <asm/time.h>
27
28#include <irq.h>
29
30static DEFINE_SPINLOCK(gt641xx_timer_lock);
31static unsigned int gt641xx_base_clock;
32
33void gt641xx_set_base_clock(unsigned int clock)
34{
35 gt641xx_base_clock = clock;
36}
37
38int gt641xx_timer0_state(void)
39{
40 if (GT_READ(GT_TC0_OFS))
41 return 0;
42
43 GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
44 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK);
45
46 return 1;
47}
48
49static int gt641xx_timer0_set_next_event(unsigned long delta,
50 struct clock_event_device *evt)
51{
52 unsigned long flags;
53 u32 ctrl;
54
55 spin_lock_irqsave(&gt641xx_timer_lock, flags);
56
57 ctrl = GT_READ(GT_TC_CONTROL_OFS);
58 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
59 ctrl |= GT_TC_CONTROL_ENTC0_MSK;
60
61 GT_WRITE(GT_TC0_OFS, delta);
62 GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
63
64 spin_unlock_irqrestore(&gt641xx_timer_lock, flags);
65
66 return 0;
67}
68
69static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *evt)
71{
72 unsigned long flags;
73 u32 ctrl;
74
75 spin_lock_irqsave(&gt641xx_timer_lock, flags);
76
77 ctrl = GT_READ(GT_TC_CONTROL_OFS);
78 ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
79
80 switch (mode) {
81 case CLOCK_EVT_MODE_PERIODIC:
82 ctrl |= GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK;
83 break;
84 case CLOCK_EVT_MODE_ONESHOT:
85 ctrl |= GT_TC_CONTROL_ENTC0_MSK;
86 break;
87 default:
88 break;
89 }
90
91 GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
92
93 spin_unlock_irqrestore(&gt641xx_timer_lock, flags);
94}
95
96static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
97{
98}
99
100static struct clock_event_device gt641xx_timer0_clockevent = {
101 .name = "gt641xx-timer0",
102 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
103 .cpumask = CPU_MASK_CPU0,
104 .irq = GT641XX_TIMER0_IRQ,
105 .set_next_event = gt641xx_timer0_set_next_event,
106 .set_mode = gt641xx_timer0_set_mode,
107 .event_handler = gt641xx_timer0_event_handler,
108};
109
110static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id)
111{
112 struct clock_event_device *cd = &gt641xx_timer0_clockevent;
113
114 cd->event_handler(cd);
115
116 return IRQ_HANDLED;
117}
118
119static struct irqaction gt641xx_timer0_irqaction = {
120 .handler = gt641xx_timer0_interrupt,
121 .flags = IRQF_DISABLED | IRQF_PERCPU,
122 .name = "gt641xx_timer0",
123};
124
125static int __init gt641xx_timer0_clockevent_init(void)
126{
127 struct clock_event_device *cd;
128
129 if (!gt641xx_base_clock)
130 return 0;
131
132 GT_WRITE(GT_TC0_OFS, gt641xx_base_clock / HZ);
133
134 cd = &gt641xx_timer0_clockevent;
135 cd->rating = 200 + gt641xx_base_clock / 10000000;
136 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
137 cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
138 clockevent_set_clock(cd, gt641xx_base_clock);
139
140 clockevents_register_device(&gt641xx_timer0_clockevent);
141
142 return setup_irq(GT641XX_TIMER0_IRQ, &gt641xx_timer0_irqaction);
143}
144arch_initcall(gt641xx_timer0_clockevent_init);