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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2009-05-25 11:39:03 -0400
committerIngo Molnar <mingo@elte.hu>2009-05-25 15:41:11 -0400
commitff99be573e02e9f7edc23b472c7f9a5ddba12795 (patch)
tree88ccf6923681021eac1bc4c0951005ea587958e4 /arch
parent10989fb2451763fae6f42d85fa6106c8fd010cf5 (diff)
perf_counter: x86: Expose INV and EDGE bits
Expose the INV and EDGE bits of the PMU to raw configs. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: John Kacur <jkacur@redhat.com> LKML-Reference: <20090525153931.494709027@chello.nl> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 6cc1660db8d6..c14437faf5d2 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -87,11 +87,15 @@ static u64 intel_pmu_raw_event(u64 event)
87{ 87{
88#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL 88#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
89#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL 89#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
90#define CORE_EVNTSEL_EDGE_MASK 0x00040000ULL
91#define CORE_EVNTSEL_INV_MASK 0x00800000ULL
90#define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL 92#define CORE_EVNTSEL_COUNTER_MASK 0xFF000000ULL
91 93
92#define CORE_EVNTSEL_MASK \ 94#define CORE_EVNTSEL_MASK \
93 (CORE_EVNTSEL_EVENT_MASK | \ 95 (CORE_EVNTSEL_EVENT_MASK | \
94 CORE_EVNTSEL_UNIT_MASK | \ 96 CORE_EVNTSEL_UNIT_MASK | \
97 CORE_EVNTSEL_EDGE_MASK | \
98 CORE_EVNTSEL_INV_MASK | \
95 CORE_EVNTSEL_COUNTER_MASK) 99 CORE_EVNTSEL_COUNTER_MASK)
96 100
97 return event & CORE_EVNTSEL_MASK; 101 return event & CORE_EVNTSEL_MASK;
@@ -119,11 +123,15 @@ static u64 amd_pmu_raw_event(u64 event)
119{ 123{
120#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL 124#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
121#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL 125#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
126#define K7_EVNTSEL_EDGE_MASK 0x000040000ULL
127#define K7_EVNTSEL_INV_MASK 0x000800000ULL
122#define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL 128#define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
123 129
124#define K7_EVNTSEL_MASK \ 130#define K7_EVNTSEL_MASK \
125 (K7_EVNTSEL_EVENT_MASK | \ 131 (K7_EVNTSEL_EVENT_MASK | \
126 K7_EVNTSEL_UNIT_MASK | \ 132 K7_EVNTSEL_UNIT_MASK | \
133 K7_EVNTSEL_EDGE_MASK | \
134 K7_EVNTSEL_INV_MASK | \
127 K7_EVNTSEL_COUNTER_MASK) 135 K7_EVNTSEL_COUNTER_MASK)
128 136
129 return event & K7_EVNTSEL_MASK; 137 return event & K7_EVNTSEL_MASK;