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authorKukjin Kim <kgene.kim@samsung.com>2011-03-10 21:05:46 -0500
committerKukjin Kim <kgene.kim@samsung.com>2011-03-10 21:05:46 -0500
commitf4612798a1ca33e4c9b5b9152f4b9b3b23a2da58 (patch)
tree852f617cf2d5329f6c0511190806516e026a56d8 /arch
parenta5abba989deceb731047425812d268daf7536575 (diff)
parent30d8bead5a309492d1dae2f6511a0465fe6ad05e (diff)
Merge branch 'next-exynos4' into for-next
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig14
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/exynos4_defconfig70
-rw-r--r--arch/arm/mach-exynos4/Kconfig182
-rw-r--r--arch/arm/mach-exynos4/Makefile52
-rw-r--r--arch/arm/mach-exynos4/Makefile.boot (renamed from arch/arm/mach-s5pv310/Makefile.boot)0
-rw-r--r--arch/arm/mach-exynos4/clock.c (renamed from arch/arm/mach-s5pv310/clock.c)191
-rw-r--r--arch/arm/mach-exynos4/cpu.c (renamed from arch/arm/mach-s5pv310/cpu.c)92
-rw-r--r--arch/arm/mach-exynos4/cpufreq.c (renamed from arch/arm/mach-s5pv310/cpufreq.c)110
-rw-r--r--arch/arm/mach-exynos4/dev-audio.c (renamed from arch/arm/mach-s5pv310/dev-audio.c)143
-rw-r--r--arch/arm/mach-exynos4/dev-pd.c (renamed from arch/arm/mach-s5pv310/dev-pd.c)40
-rw-r--r--arch/arm/mach-exynos4/dev-sysmmu.c (renamed from arch/arm/mach-s5pv310/dev-sysmmu.c)78
-rw-r--r--arch/arm/mach-exynos4/dma.c (renamed from arch/arm/mach-s5pv310/dma.c)50
-rw-r--r--arch/arm/mach-exynos4/gpiolib.c (renamed from arch/arm/mach-s5pv310/gpiolib.c)154
-rw-r--r--arch/arm/mach-exynos4/headsmp.S (renamed from arch/arm/mach-s5pv310/headsmp.S)6
-rw-r--r--arch/arm/mach-exynos4/hotplug.c (renamed from arch/arm/mach-s5pv310/hotplug.c)10
-rw-r--r--arch/arm/mach-exynos4/include/mach/debug-macro.S (renamed from arch/arm/mach-s5pv310/include/mach/debug-macro.S)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/dma.h (renamed from arch/arm/mach-s5pv310/include/mach/dma.h)0
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S (renamed from arch/arm/mach-s5pv310/include/mach/entry-macro.S)4
-rw-r--r--arch/arm/mach-exynos4/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-exynos4/include/mach/hardware.h (renamed from arch/arm/mach-s5pv310/include/mach/hardware.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/io.h (renamed from arch/arm/mach-s5pv310/include/mach/io.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h (renamed from arch/arm/mach-s5pv310/include/mach/irqs.h)9
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h145
-rw-r--r--arch/arm/mach-exynos4/include/mach/memory.h (renamed from arch/arm/mach-s5pv310/include/mach/memory.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/pwm-clock.h (renamed from arch/arm/mach-s5pv310/include/mach/pwm-clock.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-clock.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-irq.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-irq.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-mct.h52
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-mem.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-mem.h)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-pmu.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-sysmmu.h (renamed from arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h)6
-rw-r--r--arch/arm/mach-exynos4/include/mach/smp.h (renamed from arch/arm/mach-s5pv310/include/mach/smp.h)2
-rw-r--r--arch/arm/mach-exynos4/include/mach/sysmmu.h (renamed from arch/arm/mach-s5pv310/include/mach/sysmmu.h)18
-rw-r--r--arch/arm/mach-exynos4/include/mach/system.h (renamed from arch/arm/mach-s5pv310/include/mach/system.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/timex.h (renamed from arch/arm/mach-s5pv310/include/mach/timex.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/uncompress.h (renamed from arch/arm/mach-s5pv310/include/mach/uncompress.h)8
-rw-r--r--arch/arm/mach-exynos4/include/mach/vmalloc.h (renamed from arch/arm/mach-s5pv310/include/mach/vmalloc.h)8
-rw-r--r--arch/arm/mach-exynos4/init.c (renamed from arch/arm/mach-s5pv310/init.c)10
-rw-r--r--arch/arm/mach-exynos4/irq-combiner.c (renamed from arch/arm/mach-s5pv310/irq-combiner.c)4
-rw-r--r--arch/arm/mach-exynos4/irq-eint.c (renamed from arch/arm/mach-s5pv310/irq-eint.c)62
-rw-r--r--arch/arm/mach-exynos4/localtimer.c (renamed from arch/arm/mach-s5pv310/localtimer.c)2
-rw-r--r--arch/arm/mach-exynos4/mach-armlex4210.c214
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c305
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c (renamed from arch/arm/mach-s5pv310/mach-smdkc210.c)48
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c (renamed from arch/arm/mach-s5pv310/mach-smdkv310.c)48
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c650
-rw-r--r--arch/arm/mach-exynos4/mct.c421
-rw-r--r--arch/arm/mach-exynos4/platsmp.c (renamed from arch/arm/mach-s5pv310/platsmp.c)12
-rw-r--r--arch/arm/mach-exynos4/setup-i2c0.c (renamed from arch/arm/mach-s5pv310/setup-i2c0.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c1.c (renamed from arch/arm/mach-s5pv310/setup-i2c1.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c2.c (renamed from arch/arm/mach-s5pv310/setup-i2c2.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c3.c (renamed from arch/arm/mach-s5pv310/setup-i2c3.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c4.c (renamed from arch/arm/mach-s5pv310/setup-i2c4.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c5.c (renamed from arch/arm/mach-s5pv310/setup-i2c5.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c6.c (renamed from arch/arm/mach-s5pv310/setup-i2c6.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-i2c7.c (renamed from arch/arm/mach-s5pv310/setup-i2c7.c)4
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci-gpio.c (renamed from arch/arm/mach-s5pv310/setup-sdhci-gpio.c)52
-rw-r--r--arch/arm/mach-exynos4/setup-sdhci.c (renamed from arch/arm/mach-s5pv310/setup-sdhci.c)12
-rw-r--r--arch/arm/mach-exynos4/time.c (renamed from arch/arm/mach-s5pv310/time.c)64
-rw-r--r--arch/arm/mach-s5pv310/Kconfig151
-rw-r--r--arch/arm/mach-s5pv310/Makefile43
-rw-r--r--arch/arm/mach-s5pv310/include/mach/gpio.h135
-rw-r--r--arch/arm/mach-s5pv310/include/mach/map.h144
-rw-r--r--arch/arm/mach-s5pv310/include/mach/regs-gpio.h42
-rw-r--r--arch/arm/mach-s5pv310/mach-universal_c210.c237
-rw-r--r--arch/arm/mm/Kconfig2
-rw-r--r--arch/arm/plat-s5p/Kconfig8
-rw-r--r--arch/arm/plat-s5p/cpu.c25
-rw-r--r--arch/arm/plat-s5p/include/plat/exynos4.h34
-rw-r--r--arch/arm/plat-s5p/include/plat/s5pv310.h34
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h23
-rw-r--r--arch/arm/plat-samsung/include/plat/pd.h4
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h63
75 files changed, 3060 insertions, 1528 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 166efa2a19cd..b4db99bb4f85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -760,8 +760,8 @@ config ARCH_S5PV210
760 help 760 help
761 Samsung S5PV210/S5PC110 series based systems 761 Samsung S5PV210/S5PC110 series based systems
762 762
763config ARCH_S5PV310 763config ARCH_EXYNOS4
764 bool "Samsung S5PV310/S5PC210" 764 bool "Samsung EXYNOS4"
765 select CPU_V7 765 select CPU_V7
766 select ARCH_SPARSEMEM_ENABLE 766 select ARCH_SPARSEMEM_ENABLE
767 select GENERIC_GPIO 767 select GENERIC_GPIO
@@ -772,7 +772,7 @@ config ARCH_S5PV310
772 select HAVE_S3C2410_I2C if I2C 772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG 773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 help 774 help
775 Samsung S5PV310 series based systems 775 Samsung EXYNOS4 series based systems
776 776
777config ARCH_SHARK 777config ARCH_SHARK
778 bool "Shark" 778 bool "Shark"
@@ -991,7 +991,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
991 991
992source "arch/arm/mach-s5pv210/Kconfig" 992source "arch/arm/mach-s5pv210/Kconfig"
993 993
994source "arch/arm/mach-s5pv310/Kconfig" 994source "arch/arm/mach-exynos4/Kconfig"
995 995
996source "arch/arm/mach-shmobile/Kconfig" 996source "arch/arm/mach-shmobile/Kconfig"
997 997
@@ -1278,7 +1278,7 @@ config SMP
1278 depends on GENERIC_CLOCKEVENTS 1278 depends on GENERIC_CLOCKEVENTS
1279 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \ 1279 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1280 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ 1280 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1281 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ 1281 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1282 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE 1282 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1283 select USE_GENERIC_SMP_HELPERS 1283 select USE_GENERIC_SMP_HELPERS
1284 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP 1284 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
@@ -1366,7 +1366,7 @@ config LOCAL_TIMERS
1366 bool "Use local timer interrupts" 1366 bool "Use local timer interrupts"
1367 depends on SMP 1367 depends on SMP
1368 default y 1368 default y
1369 select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP 1369 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1370 help 1370 help
1371 Enable support for local timers on SMP platforms, rather then the 1371 Enable support for local timers on SMP platforms, rather then the
1372 legacy IPI broadcast method. Local timers allows the system 1372 legacy IPI broadcast method. Local timers allows the system
@@ -1378,7 +1378,7 @@ source kernel/Kconfig.preempt
1378config HZ 1378config HZ
1379 int 1379 int
1380 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \ 1380 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1381 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310 1381 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
1382 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER 1382 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1383 default AT91_TIMER_HZ if ARCH_AT91 1383 default AT91_TIMER_HZ if ARCH_AT91
1384 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1384 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f7b29294c80..40aa0225877f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -178,7 +178,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
178machine-$(CONFIG_ARCH_S5P6442) := s5p6442 178machine-$(CONFIG_ARCH_S5P6442) := s5p6442
179machine-$(CONFIG_ARCH_S5PC100) := s5pc100 179machine-$(CONFIG_ARCH_S5PC100) := s5pc100
180machine-$(CONFIG_ARCH_S5PV210) := s5pv210 180machine-$(CONFIG_ARCH_S5PV210) := s5pv210
181machine-$(CONFIG_ARCH_S5PV310) := s5pv310 181machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
182machine-$(CONFIG_ARCH_SA1100) := sa1100 182machine-$(CONFIG_ARCH_SA1100) := sa1100
183machine-$(CONFIG_ARCH_SHARK) := shark 183machine-$(CONFIG_ARCH_SHARK) := shark
184machine-$(CONFIG_ARCH_SHMOBILE) := shmobile 184machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
new file mode 100644
index 000000000000..2ffba24d2e2a
--- /dev/null
+++ b/arch/arm/configs/exynos4_defconfig
@@ -0,0 +1,70 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_BLK_DEV_INITRD=y
3CONFIG_KALLSYMS_ALL=y
4CONFIG_MODULES=y
5CONFIG_MODULE_UNLOAD=y
6# CONFIG_BLK_DEV_BSG is not set
7CONFIG_ARCH_EXYNOS4=y
8CONFIG_S3C_LOWLEVEL_UART_PORT=1
9CONFIG_MACH_SMDKC210=y
10CONFIG_MACH_SMDKV310=y
11CONFIG_MACH_UNIVERSAL_C210=y
12CONFIG_NO_HZ=y
13CONFIG_HIGH_RES_TIMERS=y
14CONFIG_SMP=y
15CONFIG_NR_CPUS=2
16CONFIG_HOTPLUG_CPU=y
17CONFIG_PREEMPT=y
18CONFIG_AEABI=y
19CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
20CONFIG_VFP=y
21CONFIG_NEON=y
22CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
23CONFIG_BLK_DEV_LOOP=y
24CONFIG_BLK_DEV_RAM=y
25CONFIG_BLK_DEV_RAM_SIZE=8192
26CONFIG_SCSI=y
27CONFIG_BLK_DEV_SD=y
28CONFIG_CHR_DEV_SG=y
29CONFIG_INPUT_EVDEV=y
30# CONFIG_INPUT_KEYBOARD is not set
31# CONFIG_INPUT_MOUSE is not set
32CONFIG_INPUT_TOUCHSCREEN=y
33CONFIG_SERIAL_8250=y
34CONFIG_SERIAL_SAMSUNG=y
35CONFIG_SERIAL_SAMSUNG_CONSOLE=y
36CONFIG_HW_RANDOM=y
37CONFIG_I2C=y
38# CONFIG_HWMON is not set
39# CONFIG_MFD_SUPPORT is not set
40# CONFIG_HID_SUPPORT is not set
41# CONFIG_USB_SUPPORT is not set
42CONFIG_EXT2_FS=y
43CONFIG_MSDOS_FS=y
44CONFIG_VFAT_FS=y
45CONFIG_TMPFS=y
46CONFIG_TMPFS_POSIX_ACL=y
47CONFIG_CRAMFS=y
48CONFIG_ROMFS_FS=y
49CONFIG_PARTITION_ADVANCED=y
50CONFIG_BSD_DISKLABEL=y
51CONFIG_SOLARIS_X86_PARTITION=y
52CONFIG_NLS_CODEPAGE_437=y
53CONFIG_NLS_ASCII=y
54CONFIG_NLS_ISO8859_1=y
55CONFIG_MAGIC_SYSRQ=y
56CONFIG_DEBUG_KERNEL=y
57CONFIG_DETECT_HUNG_TASK=y
58CONFIG_DEBUG_RT_MUTEXES=y
59CONFIG_DEBUG_SPINLOCK=y
60CONFIG_DEBUG_MUTEXES=y
61CONFIG_DEBUG_SPINLOCK_SLEEP=y
62CONFIG_DEBUG_INFO=y
63# CONFIG_RCU_CPU_STALL_DETECTOR is not set
64CONFIG_SYSCTL_SYSCALL_CHECK=y
65CONFIG_DEBUG_USER=y
66CONFIG_DEBUG_ERRORS=y
67CONFIG_DEBUG_LL=y
68CONFIG_EARLY_PRINTK=y
69CONFIG_DEBUG_S3C_UART=1
70CONFIG_CRC_CCITT=y
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
new file mode 100644
index 000000000000..82195a9a4c61
--- /dev/null
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -0,0 +1,182 @@
1# arch/arm/mach-exynos4/Kconfig
2#
3# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the EXYNOS4
9
10if ARCH_EXYNOS4
11
12config CPU_EXYNOS4210
13 bool
14 select S3C_PL330_DMA
15 help
16 Enable EXYNOS4210 CPU support
17
18config EXYNOS4_MCT
19 bool "Kernel timer support by MCT"
20 help
21 Use MCT (Multi Core Timer) as kernel timers
22
23config EXYNOS4_DEV_PD
24 bool
25 help
26 Compile in platform device definitions for Power Domain
27
28config EXYNOS4_DEV_SYSMMU
29 bool
30 help
31 Common setup code for SYSTEM MMU in EXYNOS4
32
33config EXYNOS4_SETUP_I2C1
34 bool
35 help
36 Common setup code for i2c bus 1.
37
38config EXYNOS4_SETUP_I2C2
39 bool
40 help
41 Common setup code for i2c bus 2.
42
43config EXYNOS4_SETUP_I2C3
44 bool
45 help
46 Common setup code for i2c bus 3.
47
48config EXYNOS4_SETUP_I2C4
49 bool
50 help
51 Common setup code for i2c bus 4.
52
53config EXYNOS4_SETUP_I2C5
54 bool
55 help
56 Common setup code for i2c bus 5.
57
58config EXYNOS4_SETUP_I2C6
59 bool
60 help
61 Common setup code for i2c bus 6.
62
63config EXYNOS4_SETUP_I2C7
64 bool
65 help
66 Common setup code for i2c bus 7.
67
68config EXYNOS4_SETUP_SDHCI
69 bool
70 select EXYNOS4_SETUP_SDHCI_GPIO
71 help
72 Internal helper functions for EXYNOS4 based SDHCI systems.
73
74config EXYNOS4_SETUP_SDHCI_GPIO
75 bool
76 help
77 Common setup code for SDHCI gpio.
78
79# machine support
80
81menu "EXYNOS4 Machines"
82
83config MACH_SMDKC210
84 bool "SMDKC210"
85 select CPU_EXYNOS4210
86 select S3C_DEV_RTC
87 select S3C_DEV_WDT
88 select S3C_DEV_I2C1
89 select S3C_DEV_HSMMC
90 select S3C_DEV_HSMMC1
91 select S3C_DEV_HSMMC2
92 select S3C_DEV_HSMMC3
93 select EXYNOS4_DEV_PD
94 select EXYNOS4_DEV_SYSMMU
95 select EXYNOS4_SETUP_I2C1
96 select EXYNOS4_SETUP_SDHCI
97 help
98 Machine support for Samsung SMDKC210
99
100config MACH_SMDKV310
101 bool "SMDKV310"
102 select CPU_EXYNOS4210
103 select S3C_DEV_RTC
104 select S3C_DEV_WDT
105 select S3C_DEV_I2C1
106 select S3C_DEV_HSMMC
107 select S3C_DEV_HSMMC1
108 select S3C_DEV_HSMMC2
109 select S3C_DEV_HSMMC3
110 select EXYNOS4_DEV_PD
111 select EXYNOS4_DEV_SYSMMU
112 select EXYNOS4_SETUP_I2C1
113 select EXYNOS4_SETUP_SDHCI
114 help
115 Machine support for Samsung SMDKV310
116
117config MACH_ARMLEX4210
118 bool "ARMLEX4210"
119 select CPU_EXYNOS4210
120 select S3C_DEV_RTC
121 select S3C_DEV_WDT
122 select S3C_DEV_HSMMC
123 select S3C_DEV_HSMMC2
124 select S3C_DEV_HSMMC3
125 select EXYNOS4_DEV_SYSMMU
126 select EXYNOS4_SETUP_SDHCI
127 help
128 Machine support for Samsung ARMLEX4210 based on EXYNOS4210
129
130config MACH_UNIVERSAL_C210
131 bool "Mobile UNIVERSAL_C210 Board"
132 select CPU_EXYNOS4210
133 select S3C_DEV_HSMMC
134 select S3C_DEV_HSMMC2
135 select S3C_DEV_HSMMC3
136 select S3C_DEV_I2C1
137 select S3C_DEV_I2C5
138 select S5P_DEV_ONENAND
139 select EXYNOS4_SETUP_I2C1
140 select EXYNOS4_SETUP_I2C5
141 select EXYNOS4_SETUP_SDHCI
142 help
143 Machine support for Samsung Mobile Universal S5PC210 Reference
144 Board.
145
146config MACH_NURI
147 bool "Mobile NURI Board"
148 select CPU_EXYNOS4210
149 select S3C_DEV_WDT
150 select S3C_DEV_HSMMC
151 select S3C_DEV_HSMMC2
152 select S3C_DEV_HSMMC3
153 select S3C_DEV_I2C1
154 select S3C_DEV_I2C5
155 select EXYNOS4_SETUP_I2C1
156 select EXYNOS4_SETUP_I2C5
157 select EXYNOS4_SETUP_SDHCI
158 select SAMSUNG_DEV_PWM
159 help
160 Machine support for Samsung Mobile NURI Board.
161
162endmenu
163
164comment "Configuration for HSMMC bus width"
165
166menu "Use 8-bit bus width"
167
168config EXYNOS4_SDHCI_CH0_8BIT
169 bool "Channel 0 with 8-bit bus"
170 help
171 Support HSMMC Channel 0 8-bit bus.
172 If selected, Channel 1 is disabled.
173
174config EXYNOS4_SDHCI_CH2_8BIT
175 bool "Channel 2 with 8-bit bus"
176 help
177 Support HSMMC Channel 2 8-bit bus.
178 If selected, Channel 3 is disabled.
179
180endmenu
181
182endif
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
new file mode 100644
index 000000000000..56e367b48fbb
--- /dev/null
+++ b/arch/arm/mach-exynos4/Makefile
@@ -0,0 +1,52 @@
1# arch/arm/mach-exynos4/Makefile
2#
3# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for EXYNOS4 system
14
15obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o
18
19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
20
21ifeq ($(CONFIG_EXYNOS4_MCT),y)
22obj-y += mct.o
23else
24obj-y += time.o
25obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
26endif
27
28obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
29
30# machine support
31
32obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
33obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
34obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
35obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
36obj-$(CONFIG_MACH_NURI) += mach-nuri.o
37
38# device support
39
40obj-y += dev-audio.o
41obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
42obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
43
44obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
45obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
46obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
47obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
48obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
49obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
50obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
51obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
52obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/Makefile.boot b/arch/arm/mach-exynos4/Makefile.boot
index d65956ffb43d..d65956ffb43d 100644
--- a/arch/arm/mach-s5pv310/Makefile.boot
+++ b/arch/arm/mach-exynos4/Makefile.boot
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-exynos4/clock.c
index fc7c2f8d165e..7bf3c4e35d26 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/clock.c 1/* linux/arch/arm/mach-exynos4/clock.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Clock support 6 * EXYNOS4 - Clock support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -46,72 +46,72 @@ static struct clk clk_sclk_usbphy1 = {
46 .id = -1, 46 .id = -1,
47}; 47};
48 48
49static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable) 49static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
50{ 50{
51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable); 51 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
52} 52}
53 53
54static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable) 54static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
55{ 55{
56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable); 56 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
57} 57}
58 58
59static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable) 59static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
60{ 60{
61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable); 61 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
62} 62}
63 63
64static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable) 64static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
65{ 65{
66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable); 66 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
67} 67}
68 68
69static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable) 69static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
70{ 70{
71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable); 71 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
72} 72}
73 73
74static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable) 74static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
75{ 75{
76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable); 76 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
77} 77}
78 78
79static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable) 79static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
80{ 80{
81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable); 81 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
82} 82}
83 83
84static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable) 84static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
85{ 85{
86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable); 86 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
87} 87}
88 88
89static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable) 89static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
90{ 90{
91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable); 91 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
92} 92}
93 93
94static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable) 94static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
95{ 95{
96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable); 96 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
97} 97}
98 98
99static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable) 99static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
100{ 100{
101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable); 101 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
102} 102}
103 103
104static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable) 104static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
105{ 105{
106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable); 106 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
107} 107}
108 108
109static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable) 109static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
110{ 110{
111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable); 111 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
112} 112}
113 113
114static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable) 114static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
115{ 115{
116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable); 116 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
117} 117}
@@ -358,7 +358,7 @@ static struct clksrc_clk clk_vpllsrc = {
358 .clk = { 358 .clk = {
359 .name = "vpll_src", 359 .name = "vpll_src",
360 .id = -1, 360 .id = -1,
361 .enable = s5pv310_clksrc_mask_top_ctrl, 361 .enable = exynos4_clksrc_mask_top_ctrl,
362 .ctrlbit = (1 << 0), 362 .ctrlbit = (1 << 0),
363 }, 363 },
364 .sources = &clkset_vpllsrc, 364 .sources = &clkset_vpllsrc,
@@ -389,205 +389,206 @@ static struct clk init_clocks_off[] = {
389 .name = "timers", 389 .name = "timers",
390 .id = -1, 390 .id = -1,
391 .parent = &clk_aclk_100.clk, 391 .parent = &clk_aclk_100.clk,
392 .enable = s5pv310_clk_ip_peril_ctrl, 392 .enable = exynos4_clk_ip_peril_ctrl,
393 .ctrlbit = (1<<24), 393 .ctrlbit = (1<<24),
394 }, { 394 }, {
395 .name = "csis", 395 .name = "csis",
396 .id = 0, 396 .id = 0,
397 .enable = s5pv310_clk_ip_cam_ctrl, 397 .enable = exynos4_clk_ip_cam_ctrl,
398 .ctrlbit = (1 << 4), 398 .ctrlbit = (1 << 4),
399 }, { 399 }, {
400 .name = "csis", 400 .name = "csis",
401 .id = 1, 401 .id = 1,
402 .enable = s5pv310_clk_ip_cam_ctrl, 402 .enable = exynos4_clk_ip_cam_ctrl,
403 .ctrlbit = (1 << 5), 403 .ctrlbit = (1 << 5),
404 }, { 404 }, {
405 .name = "fimc", 405 .name = "fimc",
406 .id = 0, 406 .id = 0,
407 .enable = s5pv310_clk_ip_cam_ctrl, 407 .enable = exynos4_clk_ip_cam_ctrl,
408 .ctrlbit = (1 << 0), 408 .ctrlbit = (1 << 0),
409 }, { 409 }, {
410 .name = "fimc", 410 .name = "fimc",
411 .id = 1, 411 .id = 1,
412 .enable = s5pv310_clk_ip_cam_ctrl, 412 .enable = exynos4_clk_ip_cam_ctrl,
413 .ctrlbit = (1 << 1), 413 .ctrlbit = (1 << 1),
414 }, { 414 }, {
415 .name = "fimc", 415 .name = "fimc",
416 .id = 2, 416 .id = 2,
417 .enable = s5pv310_clk_ip_cam_ctrl, 417 .enable = exynos4_clk_ip_cam_ctrl,
418 .ctrlbit = (1 << 2), 418 .ctrlbit = (1 << 2),
419 }, { 419 }, {
420 .name = "fimc", 420 .name = "fimc",
421 .id = 3, 421 .id = 3,
422 .enable = s5pv310_clk_ip_cam_ctrl, 422 .enable = exynos4_clk_ip_cam_ctrl,
423 .ctrlbit = (1 << 3), 423 .ctrlbit = (1 << 3),
424 }, { 424 }, {
425 .name = "fimd", 425 .name = "fimd",
426 .id = 0, 426 .id = 0,
427 .enable = s5pv310_clk_ip_lcd0_ctrl, 427 .enable = exynos4_clk_ip_lcd0_ctrl,
428 .ctrlbit = (1 << 0), 428 .ctrlbit = (1 << 0),
429 }, { 429 }, {
430 .name = "fimd", 430 .name = "fimd",
431 .id = 1, 431 .id = 1,
432 .enable = s5pv310_clk_ip_lcd1_ctrl, 432 .enable = exynos4_clk_ip_lcd1_ctrl,
433 .ctrlbit = (1 << 0), 433 .ctrlbit = (1 << 0),
434 }, { 434 }, {
435 .name = "hsmmc", 435 .name = "hsmmc",
436 .id = 0, 436 .id = 0,
437 .parent = &clk_aclk_133.clk, 437 .parent = &clk_aclk_133.clk,
438 .enable = s5pv310_clk_ip_fsys_ctrl, 438 .enable = exynos4_clk_ip_fsys_ctrl,
439 .ctrlbit = (1 << 5), 439 .ctrlbit = (1 << 5),
440 }, { 440 }, {
441 .name = "hsmmc", 441 .name = "hsmmc",
442 .id = 1, 442 .id = 1,
443 .parent = &clk_aclk_133.clk, 443 .parent = &clk_aclk_133.clk,
444 .enable = s5pv310_clk_ip_fsys_ctrl, 444 .enable = exynos4_clk_ip_fsys_ctrl,
445 .ctrlbit = (1 << 6), 445 .ctrlbit = (1 << 6),
446 }, { 446 }, {
447 .name = "hsmmc", 447 .name = "hsmmc",
448 .id = 2, 448 .id = 2,
449 .parent = &clk_aclk_133.clk, 449 .parent = &clk_aclk_133.clk,
450 .enable = s5pv310_clk_ip_fsys_ctrl, 450 .enable = exynos4_clk_ip_fsys_ctrl,
451 .ctrlbit = (1 << 7), 451 .ctrlbit = (1 << 7),
452 }, { 452 }, {
453 .name = "hsmmc", 453 .name = "hsmmc",
454 .id = 3, 454 .id = 3,
455 .parent = &clk_aclk_133.clk, 455 .parent = &clk_aclk_133.clk,
456 .enable = s5pv310_clk_ip_fsys_ctrl, 456 .enable = exynos4_clk_ip_fsys_ctrl,
457 .ctrlbit = (1 << 8), 457 .ctrlbit = (1 << 8),
458 }, { 458 }, {
459 .name = "hsmmc", 459 .name = "hsmmc",
460 .id = 4, 460 .id = 4,
461 .parent = &clk_aclk_133.clk, 461 .parent = &clk_aclk_133.clk,
462 .enable = s5pv310_clk_ip_fsys_ctrl, 462 .enable = exynos4_clk_ip_fsys_ctrl,
463 .ctrlbit = (1 << 9), 463 .ctrlbit = (1 << 9),
464 }, { 464 }, {
465 .name = "sata", 465 .name = "sata",
466 .id = -1, 466 .id = -1,
467 .enable = s5pv310_clk_ip_fsys_ctrl, 467 .enable = exynos4_clk_ip_fsys_ctrl,
468 .ctrlbit = (1 << 10), 468 .ctrlbit = (1 << 10),
469 }, { 469 }, {
470 .name = "pdma", 470 .name = "pdma",
471 .id = 0, 471 .id = 0,
472 .enable = s5pv310_clk_ip_fsys_ctrl, 472 .enable = exynos4_clk_ip_fsys_ctrl,
473 .ctrlbit = (1 << 0), 473 .ctrlbit = (1 << 0),
474 }, { 474 }, {
475 .name = "pdma", 475 .name = "pdma",
476 .id = 1, 476 .id = 1,
477 .enable = s5pv310_clk_ip_fsys_ctrl, 477 .enable = exynos4_clk_ip_fsys_ctrl,
478 .ctrlbit = (1 << 1), 478 .ctrlbit = (1 << 1),
479 }, { 479 }, {
480 .name = "adc", 480 .name = "adc",
481 .id = -1, 481 .id = -1,
482 .enable = s5pv310_clk_ip_peril_ctrl, 482 .enable = exynos4_clk_ip_peril_ctrl,
483 .ctrlbit = (1 << 15), 483 .ctrlbit = (1 << 15),
484 }, { 484 }, {
485 .name = "rtc", 485 .name = "rtc",
486 .id = -1, 486 .id = -1,
487 .enable = s5pv310_clk_ip_perir_ctrl, 487 .enable = exynos4_clk_ip_perir_ctrl,
488 .ctrlbit = (1 << 15), 488 .ctrlbit = (1 << 15),
489 }, { 489 }, {
490 .name = "watchdog", 490 .name = "watchdog",
491 .id = -1, 491 .id = -1,
492 .enable = s5pv310_clk_ip_perir_ctrl, 492 .parent = &clk_aclk_100.clk,
493 .enable = exynos4_clk_ip_perir_ctrl,
493 .ctrlbit = (1 << 14), 494 .ctrlbit = (1 << 14),
494 }, { 495 }, {
495 .name = "usbhost", 496 .name = "usbhost",
496 .id = -1, 497 .id = -1,
497 .enable = s5pv310_clk_ip_fsys_ctrl , 498 .enable = exynos4_clk_ip_fsys_ctrl ,
498 .ctrlbit = (1 << 12), 499 .ctrlbit = (1 << 12),
499 }, { 500 }, {
500 .name = "otg", 501 .name = "otg",
501 .id = -1, 502 .id = -1,
502 .enable = s5pv310_clk_ip_fsys_ctrl, 503 .enable = exynos4_clk_ip_fsys_ctrl,
503 .ctrlbit = (1 << 13), 504 .ctrlbit = (1 << 13),
504 }, { 505 }, {
505 .name = "spi", 506 .name = "spi",
506 .id = 0, 507 .id = 0,
507 .enable = s5pv310_clk_ip_peril_ctrl, 508 .enable = exynos4_clk_ip_peril_ctrl,
508 .ctrlbit = (1 << 16), 509 .ctrlbit = (1 << 16),
509 }, { 510 }, {
510 .name = "spi", 511 .name = "spi",
511 .id = 1, 512 .id = 1,
512 .enable = s5pv310_clk_ip_peril_ctrl, 513 .enable = exynos4_clk_ip_peril_ctrl,
513 .ctrlbit = (1 << 17), 514 .ctrlbit = (1 << 17),
514 }, { 515 }, {
515 .name = "spi", 516 .name = "spi",
516 .id = 2, 517 .id = 2,
517 .enable = s5pv310_clk_ip_peril_ctrl, 518 .enable = exynos4_clk_ip_peril_ctrl,
518 .ctrlbit = (1 << 18), 519 .ctrlbit = (1 << 18),
519 }, { 520 }, {
520 .name = "iis", 521 .name = "iis",
521 .id = 0, 522 .id = 0,
522 .enable = s5pv310_clk_ip_peril_ctrl, 523 .enable = exynos4_clk_ip_peril_ctrl,
523 .ctrlbit = (1 << 19), 524 .ctrlbit = (1 << 19),
524 }, { 525 }, {
525 .name = "iis", 526 .name = "iis",
526 .id = 1, 527 .id = 1,
527 .enable = s5pv310_clk_ip_peril_ctrl, 528 .enable = exynos4_clk_ip_peril_ctrl,
528 .ctrlbit = (1 << 20), 529 .ctrlbit = (1 << 20),
529 }, { 530 }, {
530 .name = "iis", 531 .name = "iis",
531 .id = 2, 532 .id = 2,
532 .enable = s5pv310_clk_ip_peril_ctrl, 533 .enable = exynos4_clk_ip_peril_ctrl,
533 .ctrlbit = (1 << 21), 534 .ctrlbit = (1 << 21),
534 }, { 535 }, {
535 .name = "ac97", 536 .name = "ac97",
536 .id = -1, 537 .id = -1,
537 .enable = s5pv310_clk_ip_peril_ctrl, 538 .enable = exynos4_clk_ip_peril_ctrl,
538 .ctrlbit = (1 << 27), 539 .ctrlbit = (1 << 27),
539 }, { 540 }, {
540 .name = "fimg2d", 541 .name = "fimg2d",
541 .id = -1, 542 .id = -1,
542 .enable = s5pv310_clk_ip_image_ctrl, 543 .enable = exynos4_clk_ip_image_ctrl,
543 .ctrlbit = (1 << 0), 544 .ctrlbit = (1 << 0),
544 }, { 545 }, {
545 .name = "i2c", 546 .name = "i2c",
546 .id = 0, 547 .id = 0,
547 .parent = &clk_aclk_100.clk, 548 .parent = &clk_aclk_100.clk,
548 .enable = s5pv310_clk_ip_peril_ctrl, 549 .enable = exynos4_clk_ip_peril_ctrl,
549 .ctrlbit = (1 << 6), 550 .ctrlbit = (1 << 6),
550 }, { 551 }, {
551 .name = "i2c", 552 .name = "i2c",
552 .id = 1, 553 .id = 1,
553 .parent = &clk_aclk_100.clk, 554 .parent = &clk_aclk_100.clk,
554 .enable = s5pv310_clk_ip_peril_ctrl, 555 .enable = exynos4_clk_ip_peril_ctrl,
555 .ctrlbit = (1 << 7), 556 .ctrlbit = (1 << 7),
556 }, { 557 }, {
557 .name = "i2c", 558 .name = "i2c",
558 .id = 2, 559 .id = 2,
559 .parent = &clk_aclk_100.clk, 560 .parent = &clk_aclk_100.clk,
560 .enable = s5pv310_clk_ip_peril_ctrl, 561 .enable = exynos4_clk_ip_peril_ctrl,
561 .ctrlbit = (1 << 8), 562 .ctrlbit = (1 << 8),
562 }, { 563 }, {
563 .name = "i2c", 564 .name = "i2c",
564 .id = 3, 565 .id = 3,
565 .parent = &clk_aclk_100.clk, 566 .parent = &clk_aclk_100.clk,
566 .enable = s5pv310_clk_ip_peril_ctrl, 567 .enable = exynos4_clk_ip_peril_ctrl,
567 .ctrlbit = (1 << 9), 568 .ctrlbit = (1 << 9),
568 }, { 569 }, {
569 .name = "i2c", 570 .name = "i2c",
570 .id = 4, 571 .id = 4,
571 .parent = &clk_aclk_100.clk, 572 .parent = &clk_aclk_100.clk,
572 .enable = s5pv310_clk_ip_peril_ctrl, 573 .enable = exynos4_clk_ip_peril_ctrl,
573 .ctrlbit = (1 << 10), 574 .ctrlbit = (1 << 10),
574 }, { 575 }, {
575 .name = "i2c", 576 .name = "i2c",
576 .id = 5, 577 .id = 5,
577 .parent = &clk_aclk_100.clk, 578 .parent = &clk_aclk_100.clk,
578 .enable = s5pv310_clk_ip_peril_ctrl, 579 .enable = exynos4_clk_ip_peril_ctrl,
579 .ctrlbit = (1 << 11), 580 .ctrlbit = (1 << 11),
580 }, { 581 }, {
581 .name = "i2c", 582 .name = "i2c",
582 .id = 6, 583 .id = 6,
583 .parent = &clk_aclk_100.clk, 584 .parent = &clk_aclk_100.clk,
584 .enable = s5pv310_clk_ip_peril_ctrl, 585 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 12), 586 .ctrlbit = (1 << 12),
586 }, { 587 }, {
587 .name = "i2c", 588 .name = "i2c",
588 .id = 7, 589 .id = 7,
589 .parent = &clk_aclk_100.clk, 590 .parent = &clk_aclk_100.clk,
590 .enable = s5pv310_clk_ip_peril_ctrl, 591 .enable = exynos4_clk_ip_peril_ctrl,
591 .ctrlbit = (1 << 13), 592 .ctrlbit = (1 << 13),
592 }, 593 },
593}; 594};
@@ -596,32 +597,32 @@ static struct clk init_clocks[] = {
596 { 597 {
597 .name = "uart", 598 .name = "uart",
598 .id = 0, 599 .id = 0,
599 .enable = s5pv310_clk_ip_peril_ctrl, 600 .enable = exynos4_clk_ip_peril_ctrl,
600 .ctrlbit = (1 << 0), 601 .ctrlbit = (1 << 0),
601 }, { 602 }, {
602 .name = "uart", 603 .name = "uart",
603 .id = 1, 604 .id = 1,
604 .enable = s5pv310_clk_ip_peril_ctrl, 605 .enable = exynos4_clk_ip_peril_ctrl,
605 .ctrlbit = (1 << 1), 606 .ctrlbit = (1 << 1),
606 }, { 607 }, {
607 .name = "uart", 608 .name = "uart",
608 .id = 2, 609 .id = 2,
609 .enable = s5pv310_clk_ip_peril_ctrl, 610 .enable = exynos4_clk_ip_peril_ctrl,
610 .ctrlbit = (1 << 2), 611 .ctrlbit = (1 << 2),
611 }, { 612 }, {
612 .name = "uart", 613 .name = "uart",
613 .id = 3, 614 .id = 3,
614 .enable = s5pv310_clk_ip_peril_ctrl, 615 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 3), 616 .ctrlbit = (1 << 3),
616 }, { 617 }, {
617 .name = "uart", 618 .name = "uart",
618 .id = 4, 619 .id = 4,
619 .enable = s5pv310_clk_ip_peril_ctrl, 620 .enable = exynos4_clk_ip_peril_ctrl,
620 .ctrlbit = (1 << 4), 621 .ctrlbit = (1 << 4),
621 }, { 622 }, {
622 .name = "uart", 623 .name = "uart",
623 .id = 5, 624 .id = 5,
624 .enable = s5pv310_clk_ip_peril_ctrl, 625 .enable = exynos4_clk_ip_peril_ctrl,
625 .ctrlbit = (1 << 5), 626 .ctrlbit = (1 << 5),
626 } 627 }
627}; 628};
@@ -746,7 +747,7 @@ static struct clksrc_clk clksrcs[] = {
746 .clk = { 747 .clk = {
747 .name = "uclk1", 748 .name = "uclk1",
748 .id = 0, 749 .id = 0,
749 .enable = s5pv310_clksrc_mask_peril0_ctrl, 750 .enable = exynos4_clksrc_mask_peril0_ctrl,
750 .ctrlbit = (1 << 0), 751 .ctrlbit = (1 << 0),
751 }, 752 },
752 .sources = &clkset_group, 753 .sources = &clkset_group,
@@ -756,7 +757,7 @@ static struct clksrc_clk clksrcs[] = {
756 .clk = { 757 .clk = {
757 .name = "uclk1", 758 .name = "uclk1",
758 .id = 1, 759 .id = 1,
759 .enable = s5pv310_clksrc_mask_peril0_ctrl, 760 .enable = exynos4_clksrc_mask_peril0_ctrl,
760 .ctrlbit = (1 << 4), 761 .ctrlbit = (1 << 4),
761 }, 762 },
762 .sources = &clkset_group, 763 .sources = &clkset_group,
@@ -766,7 +767,7 @@ static struct clksrc_clk clksrcs[] = {
766 .clk = { 767 .clk = {
767 .name = "uclk1", 768 .name = "uclk1",
768 .id = 2, 769 .id = 2,
769 .enable = s5pv310_clksrc_mask_peril0_ctrl, 770 .enable = exynos4_clksrc_mask_peril0_ctrl,
770 .ctrlbit = (1 << 8), 771 .ctrlbit = (1 << 8),
771 }, 772 },
772 .sources = &clkset_group, 773 .sources = &clkset_group,
@@ -776,7 +777,7 @@ static struct clksrc_clk clksrcs[] = {
776 .clk = { 777 .clk = {
777 .name = "uclk1", 778 .name = "uclk1",
778 .id = 3, 779 .id = 3,
779 .enable = s5pv310_clksrc_mask_peril0_ctrl, 780 .enable = exynos4_clksrc_mask_peril0_ctrl,
780 .ctrlbit = (1 << 12), 781 .ctrlbit = (1 << 12),
781 }, 782 },
782 .sources = &clkset_group, 783 .sources = &clkset_group,
@@ -786,7 +787,7 @@ static struct clksrc_clk clksrcs[] = {
786 .clk = { 787 .clk = {
787 .name = "sclk_pwm", 788 .name = "sclk_pwm",
788 .id = -1, 789 .id = -1,
789 .enable = s5pv310_clksrc_mask_peril0_ctrl, 790 .enable = exynos4_clksrc_mask_peril0_ctrl,
790 .ctrlbit = (1 << 24), 791 .ctrlbit = (1 << 24),
791 }, 792 },
792 .sources = &clkset_group, 793 .sources = &clkset_group,
@@ -796,7 +797,7 @@ static struct clksrc_clk clksrcs[] = {
796 .clk = { 797 .clk = {
797 .name = "sclk_csis", 798 .name = "sclk_csis",
798 .id = 0, 799 .id = 0,
799 .enable = s5pv310_clksrc_mask_cam_ctrl, 800 .enable = exynos4_clksrc_mask_cam_ctrl,
800 .ctrlbit = (1 << 24), 801 .ctrlbit = (1 << 24),
801 }, 802 },
802 .sources = &clkset_group, 803 .sources = &clkset_group,
@@ -806,7 +807,7 @@ static struct clksrc_clk clksrcs[] = {
806 .clk = { 807 .clk = {
807 .name = "sclk_csis", 808 .name = "sclk_csis",
808 .id = 1, 809 .id = 1,
809 .enable = s5pv310_clksrc_mask_cam_ctrl, 810 .enable = exynos4_clksrc_mask_cam_ctrl,
810 .ctrlbit = (1 << 28), 811 .ctrlbit = (1 << 28),
811 }, 812 },
812 .sources = &clkset_group, 813 .sources = &clkset_group,
@@ -816,7 +817,7 @@ static struct clksrc_clk clksrcs[] = {
816 .clk = { 817 .clk = {
817 .name = "sclk_cam", 818 .name = "sclk_cam",
818 .id = 0, 819 .id = 0,
819 .enable = s5pv310_clksrc_mask_cam_ctrl, 820 .enable = exynos4_clksrc_mask_cam_ctrl,
820 .ctrlbit = (1 << 16), 821 .ctrlbit = (1 << 16),
821 }, 822 },
822 .sources = &clkset_group, 823 .sources = &clkset_group,
@@ -826,7 +827,7 @@ static struct clksrc_clk clksrcs[] = {
826 .clk = { 827 .clk = {
827 .name = "sclk_cam", 828 .name = "sclk_cam",
828 .id = 1, 829 .id = 1,
829 .enable = s5pv310_clksrc_mask_cam_ctrl, 830 .enable = exynos4_clksrc_mask_cam_ctrl,
830 .ctrlbit = (1 << 20), 831 .ctrlbit = (1 << 20),
831 }, 832 },
832 .sources = &clkset_group, 833 .sources = &clkset_group,
@@ -836,7 +837,7 @@ static struct clksrc_clk clksrcs[] = {
836 .clk = { 837 .clk = {
837 .name = "sclk_fimc", 838 .name = "sclk_fimc",
838 .id = 0, 839 .id = 0,
839 .enable = s5pv310_clksrc_mask_cam_ctrl, 840 .enable = exynos4_clksrc_mask_cam_ctrl,
840 .ctrlbit = (1 << 0), 841 .ctrlbit = (1 << 0),
841 }, 842 },
842 .sources = &clkset_group, 843 .sources = &clkset_group,
@@ -846,7 +847,7 @@ static struct clksrc_clk clksrcs[] = {
846 .clk = { 847 .clk = {
847 .name = "sclk_fimc", 848 .name = "sclk_fimc",
848 .id = 1, 849 .id = 1,
849 .enable = s5pv310_clksrc_mask_cam_ctrl, 850 .enable = exynos4_clksrc_mask_cam_ctrl,
850 .ctrlbit = (1 << 4), 851 .ctrlbit = (1 << 4),
851 }, 852 },
852 .sources = &clkset_group, 853 .sources = &clkset_group,
@@ -856,7 +857,7 @@ static struct clksrc_clk clksrcs[] = {
856 .clk = { 857 .clk = {
857 .name = "sclk_fimc", 858 .name = "sclk_fimc",
858 .id = 2, 859 .id = 2,
859 .enable = s5pv310_clksrc_mask_cam_ctrl, 860 .enable = exynos4_clksrc_mask_cam_ctrl,
860 .ctrlbit = (1 << 8), 861 .ctrlbit = (1 << 8),
861 }, 862 },
862 .sources = &clkset_group, 863 .sources = &clkset_group,
@@ -866,7 +867,7 @@ static struct clksrc_clk clksrcs[] = {
866 .clk = { 867 .clk = {
867 .name = "sclk_fimc", 868 .name = "sclk_fimc",
868 .id = 3, 869 .id = 3,
869 .enable = s5pv310_clksrc_mask_cam_ctrl, 870 .enable = exynos4_clksrc_mask_cam_ctrl,
870 .ctrlbit = (1 << 12), 871 .ctrlbit = (1 << 12),
871 }, 872 },
872 .sources = &clkset_group, 873 .sources = &clkset_group,
@@ -876,7 +877,7 @@ static struct clksrc_clk clksrcs[] = {
876 .clk = { 877 .clk = {
877 .name = "sclk_fimd", 878 .name = "sclk_fimd",
878 .id = 0, 879 .id = 0,
879 .enable = s5pv310_clksrc_mask_lcd0_ctrl, 880 .enable = exynos4_clksrc_mask_lcd0_ctrl,
880 .ctrlbit = (1 << 0), 881 .ctrlbit = (1 << 0),
881 }, 882 },
882 .sources = &clkset_group, 883 .sources = &clkset_group,
@@ -886,7 +887,7 @@ static struct clksrc_clk clksrcs[] = {
886 .clk = { 887 .clk = {
887 .name = "sclk_fimd", 888 .name = "sclk_fimd",
888 .id = 1, 889 .id = 1,
889 .enable = s5pv310_clksrc_mask_lcd1_ctrl, 890 .enable = exynos4_clksrc_mask_lcd1_ctrl,
890 .ctrlbit = (1 << 0), 891 .ctrlbit = (1 << 0),
891 }, 892 },
892 .sources = &clkset_group, 893 .sources = &clkset_group,
@@ -896,7 +897,7 @@ static struct clksrc_clk clksrcs[] = {
896 .clk = { 897 .clk = {
897 .name = "sclk_sata", 898 .name = "sclk_sata",
898 .id = -1, 899 .id = -1,
899 .enable = s5pv310_clksrc_mask_fsys_ctrl, 900 .enable = exynos4_clksrc_mask_fsys_ctrl,
900 .ctrlbit = (1 << 24), 901 .ctrlbit = (1 << 24),
901 }, 902 },
902 .sources = &clkset_mout_corebus, 903 .sources = &clkset_mout_corebus,
@@ -906,7 +907,7 @@ static struct clksrc_clk clksrcs[] = {
906 .clk = { 907 .clk = {
907 .name = "sclk_spi", 908 .name = "sclk_spi",
908 .id = 0, 909 .id = 0,
909 .enable = s5pv310_clksrc_mask_peril1_ctrl, 910 .enable = exynos4_clksrc_mask_peril1_ctrl,
910 .ctrlbit = (1 << 16), 911 .ctrlbit = (1 << 16),
911 }, 912 },
912 .sources = &clkset_group, 913 .sources = &clkset_group,
@@ -916,7 +917,7 @@ static struct clksrc_clk clksrcs[] = {
916 .clk = { 917 .clk = {
917 .name = "sclk_spi", 918 .name = "sclk_spi",
918 .id = 1, 919 .id = 1,
919 .enable = s5pv310_clksrc_mask_peril1_ctrl, 920 .enable = exynos4_clksrc_mask_peril1_ctrl,
920 .ctrlbit = (1 << 20), 921 .ctrlbit = (1 << 20),
921 }, 922 },
922 .sources = &clkset_group, 923 .sources = &clkset_group,
@@ -926,7 +927,7 @@ static struct clksrc_clk clksrcs[] = {
926 .clk = { 927 .clk = {
927 .name = "sclk_spi", 928 .name = "sclk_spi",
928 .id = 2, 929 .id = 2,
929 .enable = s5pv310_clksrc_mask_peril1_ctrl, 930 .enable = exynos4_clksrc_mask_peril1_ctrl,
930 .ctrlbit = (1 << 24), 931 .ctrlbit = (1 << 24),
931 }, 932 },
932 .sources = &clkset_group, 933 .sources = &clkset_group,
@@ -945,7 +946,7 @@ static struct clksrc_clk clksrcs[] = {
945 .name = "sclk_mmc", 946 .name = "sclk_mmc",
946 .id = 0, 947 .id = 0,
947 .parent = &clk_dout_mmc0.clk, 948 .parent = &clk_dout_mmc0.clk,
948 .enable = s5pv310_clksrc_mask_fsys_ctrl, 949 .enable = exynos4_clksrc_mask_fsys_ctrl,
949 .ctrlbit = (1 << 0), 950 .ctrlbit = (1 << 0),
950 }, 951 },
951 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 }, 952 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
@@ -954,7 +955,7 @@ static struct clksrc_clk clksrcs[] = {
954 .name = "sclk_mmc", 955 .name = "sclk_mmc",
955 .id = 1, 956 .id = 1,
956 .parent = &clk_dout_mmc1.clk, 957 .parent = &clk_dout_mmc1.clk,
957 .enable = s5pv310_clksrc_mask_fsys_ctrl, 958 .enable = exynos4_clksrc_mask_fsys_ctrl,
958 .ctrlbit = (1 << 4), 959 .ctrlbit = (1 << 4),
959 }, 960 },
960 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 }, 961 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
@@ -963,7 +964,7 @@ static struct clksrc_clk clksrcs[] = {
963 .name = "sclk_mmc", 964 .name = "sclk_mmc",
964 .id = 2, 965 .id = 2,
965 .parent = &clk_dout_mmc2.clk, 966 .parent = &clk_dout_mmc2.clk,
966 .enable = s5pv310_clksrc_mask_fsys_ctrl, 967 .enable = exynos4_clksrc_mask_fsys_ctrl,
967 .ctrlbit = (1 << 8), 968 .ctrlbit = (1 << 8),
968 }, 969 },
969 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 }, 970 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
@@ -972,7 +973,7 @@ static struct clksrc_clk clksrcs[] = {
972 .name = "sclk_mmc", 973 .name = "sclk_mmc",
973 .id = 3, 974 .id = 3,
974 .parent = &clk_dout_mmc3.clk, 975 .parent = &clk_dout_mmc3.clk,
975 .enable = s5pv310_clksrc_mask_fsys_ctrl, 976 .enable = exynos4_clksrc_mask_fsys_ctrl,
976 .ctrlbit = (1 << 12), 977 .ctrlbit = (1 << 12),
977 }, 978 },
978 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 }, 979 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
@@ -981,7 +982,7 @@ static struct clksrc_clk clksrcs[] = {
981 .name = "sclk_mmc", 982 .name = "sclk_mmc",
982 .id = 4, 983 .id = 4,
983 .parent = &clk_dout_mmc4.clk, 984 .parent = &clk_dout_mmc4.clk,
984 .enable = s5pv310_clksrc_mask_fsys_ctrl, 985 .enable = exynos4_clksrc_mask_fsys_ctrl,
985 .ctrlbit = (1 << 16), 986 .ctrlbit = (1 << 16),
986 }, 987 },
987 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 }, 988 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
@@ -1022,16 +1023,16 @@ static struct clksrc_clk *sysclks[] = {
1022 1023
1023static int xtal_rate; 1024static int xtal_rate;
1024 1025
1025static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk) 1026static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1026{ 1027{
1027 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508); 1028 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
1028} 1029}
1029 1030
1030static struct clk_ops s5pv310_fout_apll_ops = { 1031static struct clk_ops exynos4_fout_apll_ops = {
1031 .get_rate = s5pv310_fout_apll_get_rate, 1032 .get_rate = exynos4_fout_apll_get_rate,
1032}; 1033};
1033 1034
1034void __init_or_cpufreq s5pv310_setup_clocks(void) 1035void __init_or_cpufreq exynos4_setup_clocks(void)
1035{ 1036{
1036 struct clk *xtal_clk; 1037 struct clk *xtal_clk;
1037 unsigned long apll; 1038 unsigned long apll;
@@ -1070,12 +1071,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1070 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0), 1071 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1071 __raw_readl(S5P_VPLL_CON1), pll_4650); 1072 __raw_readl(S5P_VPLL_CON1), pll_4650);
1072 1073
1073 clk_fout_apll.ops = &s5pv310_fout_apll_ops; 1074 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1074 clk_fout_mpll.rate = mpll; 1075 clk_fout_mpll.rate = mpll;
1075 clk_fout_epll.rate = epll; 1076 clk_fout_epll.rate = epll;
1076 clk_fout_vpll.rate = vpll; 1077 clk_fout_vpll.rate = vpll;
1077 1078
1078 printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", 1079 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1079 apll, mpll, epll, vpll); 1080 apll, mpll, epll, vpll);
1080 1081
1081 armclk = clk_get_rate(&clk_armclk.clk); 1082 armclk = clk_get_rate(&clk_armclk.clk);
@@ -1086,7 +1087,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
1086 aclk_160 = clk_get_rate(&clk_aclk_160.clk); 1087 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1087 aclk_133 = clk_get_rate(&clk_aclk_133.clk); 1088 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1088 1089
1089 printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n" 1090 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1090 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n", 1091 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1091 armclk, sclk_dmc, aclk_200, 1092 armclk, sclk_dmc, aclk_200,
1092 aclk_100, aclk_160, aclk_133); 1093 aclk_100, aclk_160, aclk_133);
@@ -1103,7 +1104,7 @@ static struct clk *clks[] __initdata = {
1103 /* Nothing here yet */ 1104 /* Nothing here yet */
1104}; 1105};
1105 1106
1106void __init s5pv310_register_clocks(void) 1107void __init exynos4_register_clocks(void)
1107{ 1108{
1108 int ptr; 1109 int ptr;
1109 1110
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 0db0fb65bd70..479dfa1951c8 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/cpu.c 1/* linux/arch/arm/mach-exynos4/cpu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
19 19
20#include <plat/cpu.h> 20#include <plat/cpu.h>
21#include <plat/clock.h> 21#include <plat/clock.h>
22#include <plat/s5pv310.h> 22#include <plat/exynos4.h>
23#include <plat/sdhci.h> 23#include <plat/sdhci.h>
24 24
25#include <mach/regs-irq.h> 25#include <mach/regs-irq.h>
@@ -29,55 +29,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); 29extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
30 30
31/* Initial IO mappings */ 31/* Initial IO mappings */
32static struct map_desc s5pv310_iodesc[] __initdata = { 32static struct map_desc exynos4_iodesc[] __initdata = {
33 { 33 {
34 .virtual = (unsigned long)S5P_VA_SYSTIMER,
35 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
36 .length = SZ_4K,
37 .type = MT_DEVICE,
38 }, {
34 .virtual = (unsigned long)S5P_VA_SYSRAM, 39 .virtual = (unsigned long)S5P_VA_SYSRAM,
35 .pfn = __phys_to_pfn(S5PV310_PA_SYSRAM), 40 .pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
36 .length = SZ_4K, 41 .length = SZ_4K,
37 .type = MT_DEVICE, 42 .type = MT_DEVICE,
38 }, { 43 }, {
39 .virtual = (unsigned long)S5P_VA_CMU, 44 .virtual = (unsigned long)S5P_VA_CMU,
40 .pfn = __phys_to_pfn(S5PV310_PA_CMU), 45 .pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
41 .length = SZ_128K, 46 .length = SZ_128K,
42 .type = MT_DEVICE, 47 .type = MT_DEVICE,
43 }, { 48 }, {
44 .virtual = (unsigned long)S5P_VA_PMU, 49 .virtual = (unsigned long)S5P_VA_PMU,
45 .pfn = __phys_to_pfn(S5PV310_PA_PMU), 50 .pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
46 .length = SZ_64K, 51 .length = SZ_64K,
47 .type = MT_DEVICE, 52 .type = MT_DEVICE,
48 }, { 53 }, {
49 .virtual = (unsigned long)S5P_VA_COMBINER_BASE, 54 .virtual = (unsigned long)S5P_VA_COMBINER_BASE,
50 .pfn = __phys_to_pfn(S5PV310_PA_COMBINER), 55 .pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
51 .length = SZ_4K, 56 .length = SZ_4K,
52 .type = MT_DEVICE, 57 .type = MT_DEVICE,
53 }, { 58 }, {
54 .virtual = (unsigned long)S5P_VA_COREPERI_BASE, 59 .virtual = (unsigned long)S5P_VA_COREPERI_BASE,
55 .pfn = __phys_to_pfn(S5PV310_PA_COREPERI), 60 .pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
56 .length = SZ_8K, 61 .length = SZ_8K,
57 .type = MT_DEVICE, 62 .type = MT_DEVICE,
58 }, { 63 }, {
59 .virtual = (unsigned long)S5P_VA_L2CC, 64 .virtual = (unsigned long)S5P_VA_L2CC,
60 .pfn = __phys_to_pfn(S5PV310_PA_L2CC), 65 .pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
61 .length = SZ_4K, 66 .length = SZ_4K,
62 .type = MT_DEVICE, 67 .type = MT_DEVICE,
63 }, { 68 }, {
64 .virtual = (unsigned long)S5P_VA_GPIO1, 69 .virtual = (unsigned long)S5P_VA_GPIO1,
65 .pfn = __phys_to_pfn(S5PV310_PA_GPIO1), 70 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
66 .length = SZ_4K, 71 .length = SZ_4K,
67 .type = MT_DEVICE, 72 .type = MT_DEVICE,
68 }, { 73 }, {
69 .virtual = (unsigned long)S5P_VA_GPIO2, 74 .virtual = (unsigned long)S5P_VA_GPIO2,
70 .pfn = __phys_to_pfn(S5PV310_PA_GPIO2), 75 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
71 .length = SZ_4K, 76 .length = SZ_4K,
72 .type = MT_DEVICE, 77 .type = MT_DEVICE,
73 }, { 78 }, {
74 .virtual = (unsigned long)S5P_VA_GPIO3, 79 .virtual = (unsigned long)S5P_VA_GPIO3,
75 .pfn = __phys_to_pfn(S5PV310_PA_GPIO3), 80 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
76 .length = SZ_256, 81 .length = SZ_256,
77 .type = MT_DEVICE, 82 .type = MT_DEVICE,
78 }, { 83 }, {
79 .virtual = (unsigned long)S5P_VA_DMC0, 84 .virtual = (unsigned long)S5P_VA_DMC0,
80 .pfn = __phys_to_pfn(S5PV310_PA_DMC0), 85 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
81 .length = SZ_4K, 86 .length = SZ_4K,
82 .type = MT_DEVICE, 87 .type = MT_DEVICE,
83 }, { 88 }, {
@@ -87,13 +92,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
87 .type = MT_DEVICE, 92 .type = MT_DEVICE,
88 }, { 93 }, {
89 .virtual = (unsigned long)S5P_VA_SROMC, 94 .virtual = (unsigned long)S5P_VA_SROMC,
90 .pfn = __phys_to_pfn(S5PV310_PA_SROMC), 95 .pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
91 .length = SZ_4K, 96 .length = SZ_4K,
92 .type = MT_DEVICE, 97 .type = MT_DEVICE,
93 }, 98 },
94}; 99};
95 100
96static void s5pv310_idle(void) 101static void exynos4_idle(void)
97{ 102{
98 if (!need_resched()) 103 if (!need_resched())
99 cpu_do_idle(); 104 cpu_do_idle();
@@ -101,32 +106,33 @@ static void s5pv310_idle(void)
101 local_irq_enable(); 106 local_irq_enable();
102} 107}
103 108
104/* s5pv310_map_io 109/*
110 * exynos4_map_io
105 * 111 *
106 * register the standard cpu IO areas 112 * register the standard cpu IO areas
107*/ 113 */
108void __init s5pv310_map_io(void) 114void __init exynos4_map_io(void)
109{ 115{
110 iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc)); 116 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
111 117
112 /* initialize device information early */ 118 /* initialize device information early */
113 s5pv310_default_sdhci0(); 119 exynos4_default_sdhci0();
114 s5pv310_default_sdhci1(); 120 exynos4_default_sdhci1();
115 s5pv310_default_sdhci2(); 121 exynos4_default_sdhci2();
116 s5pv310_default_sdhci3(); 122 exynos4_default_sdhci3();
117} 123}
118 124
119void __init s5pv310_init_clocks(int xtal) 125void __init exynos4_init_clocks(int xtal)
120{ 126{
121 printk(KERN_DEBUG "%s: initializing clocks\n", __func__); 127 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
122 128
123 s3c24xx_register_baseclocks(xtal); 129 s3c24xx_register_baseclocks(xtal);
124 s5p_register_clocks(xtal); 130 s5p_register_clocks(xtal);
125 s5pv310_register_clocks(); 131 exynos4_register_clocks();
126 s5pv310_setup_clocks(); 132 exynos4_setup_clocks();
127} 133}
128 134
129void __init s5pv310_init_irq(void) 135void __init exynos4_init_irq(void)
130{ 136{
131 int irq; 137 int irq;
132 138
@@ -148,29 +154,29 @@ void __init s5pv310_init_irq(void)
148 } 154 }
149 155
150 /* The parameters of s5p_init_irq() are for VIC init. 156 /* The parameters of s5p_init_irq() are for VIC init.
151 * Theses parameters should be NULL and 0 because S5PV310 157 * Theses parameters should be NULL and 0 because EXYNOS4
152 * uses GIC instead of VIC. 158 * uses GIC instead of VIC.
153 */ 159 */
154 s5p_init_irq(NULL, 0); 160 s5p_init_irq(NULL, 0);
155} 161}
156 162
157struct sysdev_class s5pv310_sysclass = { 163struct sysdev_class exynos4_sysclass = {
158 .name = "s5pv310-core", 164 .name = "exynos4-core",
159}; 165};
160 166
161static struct sys_device s5pv310_sysdev = { 167static struct sys_device exynos4_sysdev = {
162 .cls = &s5pv310_sysclass, 168 .cls = &exynos4_sysclass,
163}; 169};
164 170
165static int __init s5pv310_core_init(void) 171static int __init exynos4_core_init(void)
166{ 172{
167 return sysdev_class_register(&s5pv310_sysclass); 173 return sysdev_class_register(&exynos4_sysclass);
168} 174}
169 175
170core_initcall(s5pv310_core_init); 176core_initcall(exynos4_core_init);
171 177
172#ifdef CONFIG_CACHE_L2X0 178#ifdef CONFIG_CACHE_L2X0
173static int __init s5pv310_l2x0_cache_init(void) 179static int __init exynos4_l2x0_cache_init(void)
174{ 180{
175 /* TAG, Data Latency Control: 2cycle */ 181 /* TAG, Data Latency Control: 2cycle */
176 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL); 182 __raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
@@ -188,15 +194,15 @@ static int __init s5pv310_l2x0_cache_init(void)
188 return 0; 194 return 0;
189} 195}
190 196
191early_initcall(s5pv310_l2x0_cache_init); 197early_initcall(exynos4_l2x0_cache_init);
192#endif 198#endif
193 199
194int __init s5pv310_init(void) 200int __init exynos4_init(void)
195{ 201{
196 printk(KERN_INFO "S5PV310: Initializing architecture\n"); 202 printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
197 203
198 /* set idle function */ 204 /* set idle function */
199 pm_idle = s5pv310_idle; 205 pm_idle = exynos4_idle;
200 206
201 return sysdev_register(&s5pv310_sysdev); 207 return sysdev_register(&exynos4_sysdev);
202} 208}
diff --git a/arch/arm/mach-s5pv310/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
index b04cbc731128..a16ac35747a9 100644
--- a/arch/arm/mach-s5pv310/cpufreq.c
+++ b/arch/arm/mach-exynos4/cpufreq.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/cpufreq.c 1/* linux/arch/arm/mach-exynos4/cpufreq.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - CPU frequency scaling support 6 * EXYNOS4 - CPU frequency scaling support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -31,15 +31,13 @@ static struct clk *moutcore;
31static struct clk *mout_mpll; 31static struct clk *mout_mpll;
32static struct clk *mout_apll; 32static struct clk *mout_apll;
33 33
34#ifdef CONFIG_REGULATOR
35static struct regulator *arm_regulator; 34static struct regulator *arm_regulator;
36static struct regulator *int_regulator; 35static struct regulator *int_regulator;
37#endif
38 36
39static struct cpufreq_freqs freqs; 37static struct cpufreq_freqs freqs;
40static unsigned int memtype; 38static unsigned int memtype;
41 39
42enum s5pv310_memory_type { 40enum exynos4_memory_type {
43 DDR2 = 4, 41 DDR2 = 4,
44 LPDDR2, 42 LPDDR2,
45 DDR3, 43 DDR3,
@@ -49,7 +47,7 @@ enum cpufreq_level_index {
49 L0, L1, L2, L3, CPUFREQ_LEVEL_END, 47 L0, L1, L2, L3, CPUFREQ_LEVEL_END,
50}; 48};
51 49
52static struct cpufreq_frequency_table s5pv310_freq_table[] = { 50static struct cpufreq_frequency_table exynos4_freq_table[] = {
53 {L0, 1000*1000}, 51 {L0, 1000*1000},
54 {L1, 800*1000}, 52 {L1, 800*1000},
55 {L2, 400*1000}, 53 {L2, 400*1000},
@@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
160 unsigned int int_volt; 158 unsigned int int_volt;
161}; 159};
162 160
163static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = { 161static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
164 { 162 {
165 .index = L0, 163 .index = L0,
166 .arm_volt = 1200000, 164 .arm_volt = 1200000,
@@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
180 }, 178 },
181}; 179};
182 180
183static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = { 181static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
184 /* APLL FOUT L0: 1000MHz */ 182 /* APLL FOUT L0: 1000MHz */
185 ((250 << 16) | (6 << 8) | 1), 183 ((250 << 16) | (6 << 8) | 1),
186 184
@@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
194 ((200 << 16) | (6 << 8) | 4), 192 ((200 << 16) | (6 << 8) | 4),
195}; 193};
196 194
197int s5pv310_verify_speed(struct cpufreq_policy *policy) 195int exynos4_verify_speed(struct cpufreq_policy *policy)
198{ 196{
199 return cpufreq_frequency_table_verify(policy, s5pv310_freq_table); 197 return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
200} 198}
201 199
202unsigned int s5pv310_getspeed(unsigned int cpu) 200unsigned int exynos4_getspeed(unsigned int cpu)
203{ 201{
204 return clk_get_rate(cpu_clk) / 1000; 202 return clk_get_rate(cpu_clk) / 1000;
205} 203}
206 204
207void s5pv310_set_clkdiv(unsigned int div_index) 205void exynos4_set_clkdiv(unsigned int div_index)
208{ 206{
209 unsigned int tmp; 207 unsigned int tmp;
210 208
@@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
321 } while (tmp & 0x11); 319 } while (tmp & 0x11);
322} 320}
323 321
324static void s5pv310_set_apll(unsigned int index) 322static void exynos4_set_apll(unsigned int index)
325{ 323{
326 unsigned int tmp; 324 unsigned int tmp;
327 325
@@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
340 /* 3. Change PLL PMS values */ 338 /* 3. Change PLL PMS values */
341 tmp = __raw_readl(S5P_APLL_CON0); 339 tmp = __raw_readl(S5P_APLL_CON0);
342 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 340 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
343 tmp |= s5pv310_apll_pms_table[index]; 341 tmp |= exynos4_apll_pms_table[index];
344 __raw_writel(tmp, S5P_APLL_CON0); 342 __raw_writel(tmp, S5P_APLL_CON0);
345 343
346 /* 4. wait_lock_time */ 344 /* 4. wait_lock_time */
@@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
357 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)); 355 } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
358} 356}
359 357
360static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index) 358static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
361{ 359{
362 unsigned int tmp; 360 unsigned int tmp;
363 361
364 if (old_index > new_index) { 362 if (old_index > new_index) {
365 /* The frequency changing to L0 needs to change apll */ 363 /* The frequency changing to L0 needs to change apll */
366 if (freqs.new == s5pv310_freq_table[L0].frequency) { 364 if (freqs.new == exynos4_freq_table[L0].frequency) {
367 /* 1. Change the system clock divider values */ 365 /* 1. Change the system clock divider values */
368 s5pv310_set_clkdiv(new_index); 366 exynos4_set_clkdiv(new_index);
369 367
370 /* 2. Change the apll m,p,s value */ 368 /* 2. Change the apll m,p,s value */
371 s5pv310_set_apll(new_index); 369 exynos4_set_apll(new_index);
372 } else { 370 } else {
373 /* 1. Change the system clock divider values */ 371 /* 1. Change the system clock divider values */
374 s5pv310_set_clkdiv(new_index); 372 exynos4_set_clkdiv(new_index);
375 373
376 /* 2. Change just s value in apll m,p,s value */ 374 /* 2. Change just s value in apll m,p,s value */
377 tmp = __raw_readl(S5P_APLL_CON0); 375 tmp = __raw_readl(S5P_APLL_CON0);
378 tmp &= ~(0x7 << 0); 376 tmp &= ~(0x7 << 0);
379 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); 377 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
380 __raw_writel(tmp, S5P_APLL_CON0); 378 __raw_writel(tmp, S5P_APLL_CON0);
381 } 379 }
382 } 380 }
383 381
384 else if (old_index < new_index) { 382 else if (old_index < new_index) {
385 /* The frequency changing from L0 needs to change apll */ 383 /* The frequency changing from L0 needs to change apll */
386 if (freqs.old == s5pv310_freq_table[L0].frequency) { 384 if (freqs.old == exynos4_freq_table[L0].frequency) {
387 /* 1. Change the apll m,p,s value */ 385 /* 1. Change the apll m,p,s value */
388 s5pv310_set_apll(new_index); 386 exynos4_set_apll(new_index);
389 387
390 /* 2. Change the system clock divider values */ 388 /* 2. Change the system clock divider values */
391 s5pv310_set_clkdiv(new_index); 389 exynos4_set_clkdiv(new_index);
392 } else { 390 } else {
393 /* 1. Change just s value in apll m,p,s value */ 391 /* 1. Change just s value in apll m,p,s value */
394 tmp = __raw_readl(S5P_APLL_CON0); 392 tmp = __raw_readl(S5P_APLL_CON0);
395 tmp &= ~(0x7 << 0); 393 tmp &= ~(0x7 << 0);
396 tmp |= (s5pv310_apll_pms_table[new_index] & 0x7); 394 tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
397 __raw_writel(tmp, S5P_APLL_CON0); 395 __raw_writel(tmp, S5P_APLL_CON0);
398 396
399 /* 2. Change the system clock divider values */ 397 /* 2. Change the system clock divider values */
400 s5pv310_set_clkdiv(new_index); 398 exynos4_set_clkdiv(new_index);
401 } 399 }
402 } 400 }
403} 401}
404 402
405static int s5pv310_target(struct cpufreq_policy *policy, 403static int exynos4_target(struct cpufreq_policy *policy,
406 unsigned int target_freq, 404 unsigned int target_freq,
407 unsigned int relation) 405 unsigned int relation)
408{ 406{
409 unsigned int index, old_index; 407 unsigned int index, old_index;
410 unsigned int arm_volt, int_volt; 408 unsigned int arm_volt, int_volt;
411 409
412 freqs.old = s5pv310_getspeed(policy->cpu); 410 freqs.old = exynos4_getspeed(policy->cpu);
413 411
414 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, 412 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
415 freqs.old, relation, &old_index)) 413 freqs.old, relation, &old_index))
416 return -EINVAL; 414 return -EINVAL;
417 415
418 if (cpufreq_frequency_table_target(policy, s5pv310_freq_table, 416 if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
419 target_freq, relation, &index)) 417 target_freq, relation, &index))
420 return -EINVAL; 418 return -EINVAL;
421 419
422 freqs.new = s5pv310_freq_table[index].frequency; 420 freqs.new = exynos4_freq_table[index].frequency;
423 freqs.cpu = policy->cpu; 421 freqs.cpu = policy->cpu;
424 422
425 if (freqs.new == freqs.old) 423 if (freqs.new == freqs.old)
426 return 0; 424 return 0;
427 425
428 /* get the voltage value */ 426 /* get the voltage value */
429 arm_volt = s5pv310_volt_table[index].arm_volt; 427 arm_volt = exynos4_volt_table[index].arm_volt;
430 int_volt = s5pv310_volt_table[index].int_volt; 428 int_volt = exynos4_volt_table[index].int_volt;
431 429
432 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 430 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
433 431
434 /* control regulator */ 432 /* control regulator */
435 if (freqs.new > freqs.old) { 433 if (freqs.new > freqs.old) {
436 /* Voltage up */ 434 /* Voltage up */
437#ifdef CONFIG_REGULATOR
438 regulator_set_voltage(arm_regulator, arm_volt, arm_volt); 435 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
439 regulator_set_voltage(int_regulator, int_volt, int_volt); 436 regulator_set_voltage(int_regulator, int_volt, int_volt);
440#endif
441 } 437 }
442 438
443 /* Clock Configuration Procedure */ 439 /* Clock Configuration Procedure */
444 s5pv310_set_frequency(old_index, index); 440 exynos4_set_frequency(old_index, index);
445 441
446 /* control regulator */ 442 /* control regulator */
447 if (freqs.new < freqs.old) { 443 if (freqs.new < freqs.old) {
448 /* Voltage down */ 444 /* Voltage down */
449#ifdef CONFIG_REGULATOR
450 regulator_set_voltage(arm_regulator, arm_volt, arm_volt); 445 regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
451 regulator_set_voltage(int_regulator, int_volt, int_volt); 446 regulator_set_voltage(int_regulator, int_volt, int_volt);
452#endif
453 } 447 }
454 448
455 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 449 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
@@ -458,52 +452,52 @@ static int s5pv310_target(struct cpufreq_policy *policy,
458} 452}
459 453
460#ifdef CONFIG_PM 454#ifdef CONFIG_PM
461static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy, 455static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,
462 pm_message_t pmsg) 456 pm_message_t pmsg)
463{ 457{
464 return 0; 458 return 0;
465} 459}
466 460
467static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy) 461static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
468{ 462{
469 return 0; 463 return 0;
470} 464}
471#endif 465#endif
472 466
473static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy) 467static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
474{ 468{
475 policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu); 469 policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
476 470
477 cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu); 471 cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
478 472
479 /* set the transition latency value */ 473 /* set the transition latency value */
480 policy->cpuinfo.transition_latency = 100000; 474 policy->cpuinfo.transition_latency = 100000;
481 475
482 /* 476 /*
483 * S5PV310 multi-core processors has 2 cores 477 * EXYNOS4 multi-core processors has 2 cores
484 * that the frequency cannot be set independently. 478 * that the frequency cannot be set independently.
485 * Each cpu is bound to the same speed. 479 * Each cpu is bound to the same speed.
486 * So the affected cpu is all of the cpus. 480 * So the affected cpu is all of the cpus.
487 */ 481 */
488 cpumask_setall(policy->cpus); 482 cpumask_setall(policy->cpus);
489 483
490 return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table); 484 return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
491} 485}
492 486
493static struct cpufreq_driver s5pv310_driver = { 487static struct cpufreq_driver exynos4_driver = {
494 .flags = CPUFREQ_STICKY, 488 .flags = CPUFREQ_STICKY,
495 .verify = s5pv310_verify_speed, 489 .verify = exynos4_verify_speed,
496 .target = s5pv310_target, 490 .target = exynos4_target,
497 .get = s5pv310_getspeed, 491 .get = exynos4_getspeed,
498 .init = s5pv310_cpufreq_cpu_init, 492 .init = exynos4_cpufreq_cpu_init,
499 .name = "s5pv310_cpufreq", 493 .name = "exynos4_cpufreq",
500#ifdef CONFIG_PM 494#ifdef CONFIG_PM
501 .suspend = s5pv310_cpufreq_suspend, 495 .suspend = exynos4_cpufreq_suspend,
502 .resume = s5pv310_cpufreq_resume, 496 .resume = exynos4_cpufreq_resume,
503#endif 497#endif
504}; 498};
505 499
506static int __init s5pv310_cpufreq_init(void) 500static int __init exynos4_cpufreq_init(void)
507{ 501{
508 cpu_clk = clk_get(NULL, "armclk"); 502 cpu_clk = clk_get(NULL, "armclk");
509 if (IS_ERR(cpu_clk)) 503 if (IS_ERR(cpu_clk))
@@ -521,7 +515,6 @@ static int __init s5pv310_cpufreq_init(void)
521 if (IS_ERR(mout_apll)) 515 if (IS_ERR(mout_apll))
522 goto out; 516 goto out;
523 517
524#ifdef CONFIG_REGULATOR
525 arm_regulator = regulator_get(NULL, "vdd_arm"); 518 arm_regulator = regulator_get(NULL, "vdd_arm");
526 if (IS_ERR(arm_regulator)) { 519 if (IS_ERR(arm_regulator)) {
527 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm"); 520 printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
@@ -533,7 +526,6 @@ static int __init s5pv310_cpufreq_init(void)
533 printk(KERN_ERR "failed to get resource %s\n", "vdd_int"); 526 printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
534 goto out; 527 goto out;
535 } 528 }
536#endif
537 529
538 /* 530 /*
539 * Check DRAM type. 531 * Check DRAM type.
@@ -550,7 +542,7 @@ static int __init s5pv310_cpufreq_init(void)
550 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype); 542 printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
551 } 543 }
552 544
553 return cpufreq_register_driver(&s5pv310_driver); 545 return cpufreq_register_driver(&exynos4_driver);
554 546
555out: 547out:
556 if (!IS_ERR(cpu_clk)) 548 if (!IS_ERR(cpu_clk))
@@ -565,16 +557,14 @@ out:
565 if (!IS_ERR(mout_apll)) 557 if (!IS_ERR(mout_apll))
566 clk_put(mout_apll); 558 clk_put(mout_apll);
567 559
568#ifdef CONFIG_REGULATOR
569 if (!IS_ERR(arm_regulator)) 560 if (!IS_ERR(arm_regulator))
570 regulator_put(arm_regulator); 561 regulator_put(arm_regulator);
571 562
572 if (!IS_ERR(int_regulator)) 563 if (!IS_ERR(int_regulator))
573 regulator_put(int_regulator); 564 regulator_put(int_regulator);
574#endif
575 565
576 printk(KERN_ERR "%s: failed initialization\n", __func__); 566 printk(KERN_ERR "%s: failed initialization\n", __func__);
577 567
578 return -EINVAL; 568 return -EINVAL;
579} 569}
580late_initcall(s5pv310_cpufreq_init); 570late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-s5pv310/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index a1964242f0fa..1eed5f9f7bd3 100644
--- a/arch/arm/mach-s5pv310/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -1,4 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/dev-audio.c 1/* linux/arch/arm/mach-exynos4/dev-audio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd 6 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
@@ -24,18 +27,18 @@ static const char *rclksrc[] = {
24 [1] = "i2sclk", 27 [1] = "i2sclk",
25}; 28};
26 29
27static int s5pv310_cfg_i2s(struct platform_device *pdev) 30static int exynos4_cfg_i2s(struct platform_device *pdev)
28{ 31{
29 /* configure GPIO for i2s port */ 32 /* configure GPIO for i2s port */
30 switch (pdev->id) { 33 switch (pdev->id) {
31 case 0: 34 case 0:
32 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2)); 35 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
33 break; 36 break;
34 case 1: 37 case 1:
35 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2)); 38 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
36 break; 39 break;
37 case 2: 40 case 2:
38 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4)); 41 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
39 break; 42 break;
40 default: 43 default:
41 printk(KERN_ERR "Invalid Device %d\n", pdev->id); 44 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
@@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
46} 49}
47 50
48static struct s3c_audio_pdata i2sv5_pdata = { 51static struct s3c_audio_pdata i2sv5_pdata = {
49 .cfg_gpio = s5pv310_cfg_i2s, 52 .cfg_gpio = exynos4_cfg_i2s,
50 .type = { 53 .type = {
51 .i2s = { 54 .i2s = {
52 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI 55 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
@@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
56 }, 59 },
57}; 60};
58 61
59static struct resource s5pv310_i2s0_resource[] = { 62static struct resource exynos4_i2s0_resource[] = {
60 [0] = { 63 [0] = {
61 .start = S5PV310_PA_I2S0, 64 .start = EXYNOS4_PA_I2S0,
62 .end = S5PV310_PA_I2S0 + 0x100 - 1, 65 .end = EXYNOS4_PA_I2S0 + 0x100 - 1,
63 .flags = IORESOURCE_MEM, 66 .flags = IORESOURCE_MEM,
64 }, 67 },
65 [1] = { 68 [1] = {
@@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
79 }, 82 },
80}; 83};
81 84
82struct platform_device s5pv310_device_i2s0 = { 85struct platform_device exynos4_device_i2s0 = {
83 .name = "samsung-i2s", 86 .name = "samsung-i2s",
84 .id = 0, 87 .id = 0,
85 .num_resources = ARRAY_SIZE(s5pv310_i2s0_resource), 88 .num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
86 .resource = s5pv310_i2s0_resource, 89 .resource = exynos4_i2s0_resource,
87 .dev = { 90 .dev = {
88 .platform_data = &i2sv5_pdata, 91 .platform_data = &i2sv5_pdata,
89 }, 92 },
@@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
95}; 98};
96 99
97static struct s3c_audio_pdata i2sv3_pdata = { 100static struct s3c_audio_pdata i2sv3_pdata = {
98 .cfg_gpio = s5pv310_cfg_i2s, 101 .cfg_gpio = exynos4_cfg_i2s,
99 .type = { 102 .type = {
100 .i2s = { 103 .i2s = {
101 .quirks = QUIRK_NO_MUXPSR, 104 .quirks = QUIRK_NO_MUXPSR,
@@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
104 }, 107 },
105}; 108};
106 109
107static struct resource s5pv310_i2s1_resource[] = { 110static struct resource exynos4_i2s1_resource[] = {
108 [0] = { 111 [0] = {
109 .start = S5PV310_PA_I2S1, 112 .start = EXYNOS4_PA_I2S1,
110 .end = S5PV310_PA_I2S1 + 0x100 - 1, 113 .end = EXYNOS4_PA_I2S1 + 0x100 - 1,
111 .flags = IORESOURCE_MEM, 114 .flags = IORESOURCE_MEM,
112 }, 115 },
113 [1] = { 116 [1] = {
@@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
122 }, 125 },
123}; 126};
124 127
125struct platform_device s5pv310_device_i2s1 = { 128struct platform_device exynos4_device_i2s1 = {
126 .name = "samsung-i2s", 129 .name = "samsung-i2s",
127 .id = 1, 130 .id = 1,
128 .num_resources = ARRAY_SIZE(s5pv310_i2s1_resource), 131 .num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
129 .resource = s5pv310_i2s1_resource, 132 .resource = exynos4_i2s1_resource,
130 .dev = { 133 .dev = {
131 .platform_data = &i2sv3_pdata, 134 .platform_data = &i2sv3_pdata,
132 }, 135 },
133}; 136};
134 137
135static struct resource s5pv310_i2s2_resource[] = { 138static struct resource exynos4_i2s2_resource[] = {
136 [0] = { 139 [0] = {
137 .start = S5PV310_PA_I2S2, 140 .start = EXYNOS4_PA_I2S2,
138 .end = S5PV310_PA_I2S2 + 0x100 - 1, 141 .end = EXYNOS4_PA_I2S2 + 0x100 - 1,
139 .flags = IORESOURCE_MEM, 142 .flags = IORESOURCE_MEM,
140 }, 143 },
141 [1] = { 144 [1] = {
@@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
150 }, 153 },
151}; 154};
152 155
153struct platform_device s5pv310_device_i2s2 = { 156struct platform_device exynos4_device_i2s2 = {
154 .name = "samsung-i2s", 157 .name = "samsung-i2s",
155 .id = 2, 158 .id = 2,
156 .num_resources = ARRAY_SIZE(s5pv310_i2s2_resource), 159 .num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
157 .resource = s5pv310_i2s2_resource, 160 .resource = exynos4_i2s2_resource,
158 .dev = { 161 .dev = {
159 .platform_data = &i2sv3_pdata, 162 .platform_data = &i2sv3_pdata,
160 }, 163 },
@@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
162 165
163/* PCM Controller platform_devices */ 166/* PCM Controller platform_devices */
164 167
165static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev) 168static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
166{ 169{
167 switch (pdev->id) { 170 switch (pdev->id) {
168 case 0: 171 case 0:
169 s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3)); 172 s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
170 break; 173 break;
171 case 1: 174 case 1:
172 s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3)); 175 s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
173 break; 176 break;
174 case 2: 177 case 2:
175 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3)); 178 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
176 break; 179 break;
177 default: 180 default:
178 printk(KERN_DEBUG "Invalid PCM Controller number!"); 181 printk(KERN_DEBUG "Invalid PCM Controller number!");
@@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
183} 186}
184 187
185static struct s3c_audio_pdata s3c_pcm_pdata = { 188static struct s3c_audio_pdata s3c_pcm_pdata = {
186 .cfg_gpio = s5pv310_pcm_cfg_gpio, 189 .cfg_gpio = exynos4_pcm_cfg_gpio,
187}; 190};
188 191
189static struct resource s5pv310_pcm0_resource[] = { 192static struct resource exynos4_pcm0_resource[] = {
190 [0] = { 193 [0] = {
191 .start = S5PV310_PA_PCM0, 194 .start = EXYNOS4_PA_PCM0,
192 .end = S5PV310_PA_PCM0 + 0x100 - 1, 195 .end = EXYNOS4_PA_PCM0 + 0x100 - 1,
193 .flags = IORESOURCE_MEM, 196 .flags = IORESOURCE_MEM,
194 }, 197 },
195 [1] = { 198 [1] = {
@@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
204 }, 207 },
205}; 208};
206 209
207struct platform_device s5pv310_device_pcm0 = { 210struct platform_device exynos4_device_pcm0 = {
208 .name = "samsung-pcm", 211 .name = "samsung-pcm",
209 .id = 0, 212 .id = 0,
210 .num_resources = ARRAY_SIZE(s5pv310_pcm0_resource), 213 .num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
211 .resource = s5pv310_pcm0_resource, 214 .resource = exynos4_pcm0_resource,
212 .dev = { 215 .dev = {
213 .platform_data = &s3c_pcm_pdata, 216 .platform_data = &s3c_pcm_pdata,
214 }, 217 },
215}; 218};
216 219
217static struct resource s5pv310_pcm1_resource[] = { 220static struct resource exynos4_pcm1_resource[] = {
218 [0] = { 221 [0] = {
219 .start = S5PV310_PA_PCM1, 222 .start = EXYNOS4_PA_PCM1,
220 .end = S5PV310_PA_PCM1 + 0x100 - 1, 223 .end = EXYNOS4_PA_PCM1 + 0x100 - 1,
221 .flags = IORESOURCE_MEM, 224 .flags = IORESOURCE_MEM,
222 }, 225 },
223 [1] = { 226 [1] = {
@@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
232 }, 235 },
233}; 236};
234 237
235struct platform_device s5pv310_device_pcm1 = { 238struct platform_device exynos4_device_pcm1 = {
236 .name = "samsung-pcm", 239 .name = "samsung-pcm",
237 .id = 1, 240 .id = 1,
238 .num_resources = ARRAY_SIZE(s5pv310_pcm1_resource), 241 .num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
239 .resource = s5pv310_pcm1_resource, 242 .resource = exynos4_pcm1_resource,
240 .dev = { 243 .dev = {
241 .platform_data = &s3c_pcm_pdata, 244 .platform_data = &s3c_pcm_pdata,
242 }, 245 },
243}; 246};
244 247
245static struct resource s5pv310_pcm2_resource[] = { 248static struct resource exynos4_pcm2_resource[] = {
246 [0] = { 249 [0] = {
247 .start = S5PV310_PA_PCM2, 250 .start = EXYNOS4_PA_PCM2,
248 .end = S5PV310_PA_PCM2 + 0x100 - 1, 251 .end = EXYNOS4_PA_PCM2 + 0x100 - 1,
249 .flags = IORESOURCE_MEM, 252 .flags = IORESOURCE_MEM,
250 }, 253 },
251 [1] = { 254 [1] = {
@@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
260 }, 263 },
261}; 264};
262 265
263struct platform_device s5pv310_device_pcm2 = { 266struct platform_device exynos4_device_pcm2 = {
264 .name = "samsung-pcm", 267 .name = "samsung-pcm",
265 .id = 2, 268 .id = 2,
266 .num_resources = ARRAY_SIZE(s5pv310_pcm2_resource), 269 .num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
267 .resource = s5pv310_pcm2_resource, 270 .resource = exynos4_pcm2_resource,
268 .dev = { 271 .dev = {
269 .platform_data = &s3c_pcm_pdata, 272 .platform_data = &s3c_pcm_pdata,
270 }, 273 },
@@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
272 275
273/* AC97 Controller platform devices */ 276/* AC97 Controller platform devices */
274 277
275static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev) 278static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
276{ 279{
277 return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4)); 280 return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
278} 281}
279 282
280static struct resource s5pv310_ac97_resource[] = { 283static struct resource exynos4_ac97_resource[] = {
281 [0] = { 284 [0] = {
282 .start = S5PV310_PA_AC97, 285 .start = EXYNOS4_PA_AC97,
283 .end = S5PV310_PA_AC97 + 0x100 - 1, 286 .end = EXYNOS4_PA_AC97 + 0x100 - 1,
284 .flags = IORESOURCE_MEM, 287 .flags = IORESOURCE_MEM,
285 }, 288 },
286 [1] = { 289 [1] = {
@@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
306}; 309};
307 310
308static struct s3c_audio_pdata s3c_ac97_pdata = { 311static struct s3c_audio_pdata s3c_ac97_pdata = {
309 .cfg_gpio = s5pv310_ac97_cfg_gpio, 312 .cfg_gpio = exynos4_ac97_cfg_gpio,
310}; 313};
311 314
312static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32); 315static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
313 316
314struct platform_device s5pv310_device_ac97 = { 317struct platform_device exynos4_device_ac97 = {
315 .name = "samsung-ac97", 318 .name = "samsung-ac97",
316 .id = -1, 319 .id = -1,
317 .num_resources = ARRAY_SIZE(s5pv310_ac97_resource), 320 .num_resources = ARRAY_SIZE(exynos4_ac97_resource),
318 .resource = s5pv310_ac97_resource, 321 .resource = exynos4_ac97_resource,
319 .dev = { 322 .dev = {
320 .platform_data = &s3c_ac97_pdata, 323 .platform_data = &s3c_ac97_pdata,
321 .dma_mask = &s5pv310_ac97_dmamask, 324 .dma_mask = &exynos4_ac97_dmamask,
322 .coherent_dma_mask = DMA_BIT_MASK(32), 325 .coherent_dma_mask = DMA_BIT_MASK(32),
323 }, 326 },
324}; 327};
325 328
326/* S/PDIF Controller platform_device */ 329/* S/PDIF Controller platform_device */
327 330
328static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev) 331static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
329{ 332{
330 s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3)); 333 s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
331 334
332 return 0; 335 return 0;
333} 336}
334 337
335static struct resource s5pv310_spdif_resource[] = { 338static struct resource exynos4_spdif_resource[] = {
336 [0] = { 339 [0] = {
337 .start = S5PV310_PA_SPDIF, 340 .start = EXYNOS4_PA_SPDIF,
338 .end = S5PV310_PA_SPDIF + 0x100 - 1, 341 .end = EXYNOS4_PA_SPDIF + 0x100 - 1,
339 .flags = IORESOURCE_MEM, 342 .flags = IORESOURCE_MEM,
340 }, 343 },
341 [1] = { 344 [1] = {
@@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
346}; 349};
347 350
348static struct s3c_audio_pdata samsung_spdif_pdata = { 351static struct s3c_audio_pdata samsung_spdif_pdata = {
349 .cfg_gpio = s5pv310_spdif_cfg_gpio, 352 .cfg_gpio = exynos4_spdif_cfg_gpio,
350}; 353};
351 354
352static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32); 355static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
353 356
354struct platform_device s5pv310_device_spdif = { 357struct platform_device exynos4_device_spdif = {
355 .name = "samsung-spdif", 358 .name = "samsung-spdif",
356 .id = -1, 359 .id = -1,
357 .num_resources = ARRAY_SIZE(s5pv310_spdif_resource), 360 .num_resources = ARRAY_SIZE(exynos4_spdif_resource),
358 .resource = s5pv310_spdif_resource, 361 .resource = exynos4_spdif_resource,
359 .dev = { 362 .dev = {
360 .platform_data = &samsung_spdif_pdata, 363 .platform_data = &samsung_spdif_pdata,
361 .dma_mask = &s5pv310_spdif_dmamask, 364 .dma_mask = &exynos4_spdif_dmamask,
362 .coherent_dma_mask = DMA_BIT_MASK(32), 365 .coherent_dma_mask = DMA_BIT_MASK(32),
363 }, 366 },
364}; 367};
diff --git a/arch/arm/mach-s5pv310/dev-pd.c b/arch/arm/mach-exynos4/dev-pd.c
index 58a50c2d0b67..3273f25d6a75 100644
--- a/arch/arm/mach-s5pv310/dev-pd.c
+++ b/arch/arm/mach-exynos4/dev-pd.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/dev-pd.c 1/* linux/arch/arm/mach-exynos4/dev-pd.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Power Domain support 6 * EXYNOS4 - Power Domain support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,7 @@
19 19
20#include <plat/pd.h> 20#include <plat/pd.h>
21 21
22static int s5pv310_pd_enable(struct device *dev) 22static int exynos4_pd_enable(struct device *dev)
23{ 23{
24 struct samsung_pd_info *pdata = dev->platform_data; 24 struct samsung_pd_info *pdata = dev->platform_data;
25 u32 timeout; 25 u32 timeout;
@@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
42 return 0; 42 return 0;
43} 43}
44 44
45static int s5pv310_pd_disable(struct device *dev) 45static int exynos4_pd_disable(struct device *dev)
46{ 46{
47 struct samsung_pd_info *pdata = dev->platform_data; 47 struct samsung_pd_info *pdata = dev->platform_data;
48 u32 timeout; 48 u32 timeout;
@@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
64 return 0; 64 return 0;
65} 65}
66 66
67struct platform_device s5pv310_device_pd[] = { 67struct platform_device exynos4_device_pd[] = {
68 { 68 {
69 .name = "samsung-pd", 69 .name = "samsung-pd",
70 .id = 0, 70 .id = 0,
71 .dev = { 71 .dev = {
72 .platform_data = &(struct samsung_pd_info) { 72 .platform_data = &(struct samsung_pd_info) {
73 .enable = s5pv310_pd_enable, 73 .enable = exynos4_pd_enable,
74 .disable = s5pv310_pd_disable, 74 .disable = exynos4_pd_disable,
75 .base = S5P_PMU_MFC_CONF, 75 .base = S5P_PMU_MFC_CONF,
76 }, 76 },
77 }, 77 },
@@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
80 .id = 1, 80 .id = 1,
81 .dev = { 81 .dev = {
82 .platform_data = &(struct samsung_pd_info) { 82 .platform_data = &(struct samsung_pd_info) {
83 .enable = s5pv310_pd_enable, 83 .enable = exynos4_pd_enable,
84 .disable = s5pv310_pd_disable, 84 .disable = exynos4_pd_disable,
85 .base = S5P_PMU_G3D_CONF, 85 .base = S5P_PMU_G3D_CONF,
86 }, 86 },
87 }, 87 },
@@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
90 .id = 2, 90 .id = 2,
91 .dev = { 91 .dev = {
92 .platform_data = &(struct samsung_pd_info) { 92 .platform_data = &(struct samsung_pd_info) {
93 .enable = s5pv310_pd_enable, 93 .enable = exynos4_pd_enable,
94 .disable = s5pv310_pd_disable, 94 .disable = exynos4_pd_disable,
95 .base = S5P_PMU_LCD0_CONF, 95 .base = S5P_PMU_LCD0_CONF,
96 }, 96 },
97 }, 97 },
@@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
100 .id = 3, 100 .id = 3,
101 .dev = { 101 .dev = {
102 .platform_data = &(struct samsung_pd_info) { 102 .platform_data = &(struct samsung_pd_info) {
103 .enable = s5pv310_pd_enable, 103 .enable = exynos4_pd_enable,
104 .disable = s5pv310_pd_disable, 104 .disable = exynos4_pd_disable,
105 .base = S5P_PMU_LCD1_CONF, 105 .base = S5P_PMU_LCD1_CONF,
106 }, 106 },
107 }, 107 },
@@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
110 .id = 4, 110 .id = 4,
111 .dev = { 111 .dev = {
112 .platform_data = &(struct samsung_pd_info) { 112 .platform_data = &(struct samsung_pd_info) {
113 .enable = s5pv310_pd_enable, 113 .enable = exynos4_pd_enable,
114 .disable = s5pv310_pd_disable, 114 .disable = exynos4_pd_disable,
115 .base = S5P_PMU_TV_CONF, 115 .base = S5P_PMU_TV_CONF,
116 }, 116 },
117 }, 117 },
@@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
120 .id = 5, 120 .id = 5,
121 .dev = { 121 .dev = {
122 .platform_data = &(struct samsung_pd_info) { 122 .platform_data = &(struct samsung_pd_info) {
123 .enable = s5pv310_pd_enable, 123 .enable = exynos4_pd_enable,
124 .disable = s5pv310_pd_disable, 124 .disable = exynos4_pd_disable,
125 .base = S5P_PMU_CAM_CONF, 125 .base = S5P_PMU_CAM_CONF,
126 }, 126 },
127 }, 127 },
@@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
130 .id = 6, 130 .id = 6,
131 .dev = { 131 .dev = {
132 .platform_data = &(struct samsung_pd_info) { 132 .platform_data = &(struct samsung_pd_info) {
133 .enable = s5pv310_pd_enable, 133 .enable = exynos4_pd_enable,
134 .disable = s5pv310_pd_disable, 134 .disable = exynos4_pd_disable,
135 .base = S5P_PMU_GPS_CONF, 135 .base = S5P_PMU_GPS_CONF,
136 }, 136 },
137 }, 137 },
diff --git a/arch/arm/mach-s5pv310/dev-sysmmu.c b/arch/arm/mach-exynos4/dev-sysmmu.c
index e1bb200ac0f0..a10790a614ec 100644
--- a/arch/arm/mach-s5pv310/dev-sysmmu.c
+++ b/arch/arm/mach-exynos4/dev-sysmmu.c
@@ -1,8 +1,10 @@
1/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c 1/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * EXYNOS4 - System MMU support
7 *
6 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
@@ -14,10 +16,10 @@
14#include <mach/map.h> 16#include <mach/map.h>
15#include <mach/irqs.h> 17#include <mach/irqs.h>
16 18
17static struct resource s5pv310_sysmmu_resource[] = { 19static struct resource exynos4_sysmmu_resource[] = {
18 [0] = { 20 [0] = {
19 .start = S5PV310_PA_SYSMMU_MDMA, 21 .start = EXYNOS4_PA_SYSMMU_MDMA,
20 .end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1, 22 .end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
21 .flags = IORESOURCE_MEM, 23 .flags = IORESOURCE_MEM,
22 }, 24 },
23 [1] = { 25 [1] = {
@@ -26,8 +28,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
26 .flags = IORESOURCE_IRQ, 28 .flags = IORESOURCE_IRQ,
27 }, 29 },
28 [2] = { 30 [2] = {
29 .start = S5PV310_PA_SYSMMU_SSS, 31 .start = EXYNOS4_PA_SYSMMU_SSS,
30 .end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1, 32 .end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
31 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
32 }, 34 },
33 [3] = { 35 [3] = {
@@ -36,8 +38,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
36 .flags = IORESOURCE_IRQ, 38 .flags = IORESOURCE_IRQ,
37 }, 39 },
38 [4] = { 40 [4] = {
39 .start = S5PV310_PA_SYSMMU_FIMC0, 41 .start = EXYNOS4_PA_SYSMMU_FIMC0,
40 .end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1, 42 .end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
41 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM,
42 }, 44 },
43 [5] = { 45 [5] = {
@@ -46,8 +48,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
46 .flags = IORESOURCE_IRQ, 48 .flags = IORESOURCE_IRQ,
47 }, 49 },
48 [6] = { 50 [6] = {
49 .start = S5PV310_PA_SYSMMU_FIMC1, 51 .start = EXYNOS4_PA_SYSMMU_FIMC1,
50 .end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1, 52 .end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
51 .flags = IORESOURCE_MEM, 53 .flags = IORESOURCE_MEM,
52 }, 54 },
53 [7] = { 55 [7] = {
@@ -56,8 +58,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
56 .flags = IORESOURCE_IRQ, 58 .flags = IORESOURCE_IRQ,
57 }, 59 },
58 [8] = { 60 [8] = {
59 .start = S5PV310_PA_SYSMMU_FIMC2, 61 .start = EXYNOS4_PA_SYSMMU_FIMC2,
60 .end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1, 62 .end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
61 .flags = IORESOURCE_MEM, 63 .flags = IORESOURCE_MEM,
62 }, 64 },
63 [9] = { 65 [9] = {
@@ -66,8 +68,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
66 .flags = IORESOURCE_IRQ, 68 .flags = IORESOURCE_IRQ,
67 }, 69 },
68 [10] = { 70 [10] = {
69 .start = S5PV310_PA_SYSMMU_FIMC3, 71 .start = EXYNOS4_PA_SYSMMU_FIMC3,
70 .end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1, 72 .end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
71 .flags = IORESOURCE_MEM, 73 .flags = IORESOURCE_MEM,
72 }, 74 },
73 [11] = { 75 [11] = {
@@ -76,8 +78,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
76 .flags = IORESOURCE_IRQ, 78 .flags = IORESOURCE_IRQ,
77 }, 79 },
78 [12] = { 80 [12] = {
79 .start = S5PV310_PA_SYSMMU_JPEG, 81 .start = EXYNOS4_PA_SYSMMU_JPEG,
80 .end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1, 82 .end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
81 .flags = IORESOURCE_MEM, 83 .flags = IORESOURCE_MEM,
82 }, 84 },
83 [13] = { 85 [13] = {
@@ -86,8 +88,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
86 .flags = IORESOURCE_IRQ, 88 .flags = IORESOURCE_IRQ,
87 }, 89 },
88 [14] = { 90 [14] = {
89 .start = S5PV310_PA_SYSMMU_FIMD0, 91 .start = EXYNOS4_PA_SYSMMU_FIMD0,
90 .end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1, 92 .end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
91 .flags = IORESOURCE_MEM, 93 .flags = IORESOURCE_MEM,
92 }, 94 },
93 [15] = { 95 [15] = {
@@ -96,8 +98,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
96 .flags = IORESOURCE_IRQ, 98 .flags = IORESOURCE_IRQ,
97 }, 99 },
98 [16] = { 100 [16] = {
99 .start = S5PV310_PA_SYSMMU_FIMD1, 101 .start = EXYNOS4_PA_SYSMMU_FIMD1,
100 .end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1, 102 .end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
101 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
102 }, 104 },
103 [17] = { 105 [17] = {
@@ -106,8 +108,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
106 .flags = IORESOURCE_IRQ, 108 .flags = IORESOURCE_IRQ,
107 }, 109 },
108 [18] = { 110 [18] = {
109 .start = S5PV310_PA_SYSMMU_PCIe, 111 .start = EXYNOS4_PA_SYSMMU_PCIe,
110 .end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1, 112 .end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
111 .flags = IORESOURCE_MEM, 113 .flags = IORESOURCE_MEM,
112 }, 114 },
113 [19] = { 115 [19] = {
@@ -116,8 +118,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
116 .flags = IORESOURCE_IRQ, 118 .flags = IORESOURCE_IRQ,
117 }, 119 },
118 [20] = { 120 [20] = {
119 .start = S5PV310_PA_SYSMMU_G2D, 121 .start = EXYNOS4_PA_SYSMMU_G2D,
120 .end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1, 122 .end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
121 .flags = IORESOURCE_MEM, 123 .flags = IORESOURCE_MEM,
122 }, 124 },
123 [21] = { 125 [21] = {
@@ -126,8 +128,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
126 .flags = IORESOURCE_IRQ, 128 .flags = IORESOURCE_IRQ,
127 }, 129 },
128 [22] = { 130 [22] = {
129 .start = S5PV310_PA_SYSMMU_ROTATOR, 131 .start = EXYNOS4_PA_SYSMMU_ROTATOR,
130 .end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1, 132 .end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
131 .flags = IORESOURCE_MEM, 133 .flags = IORESOURCE_MEM,
132 }, 134 },
133 [23] = { 135 [23] = {
@@ -136,8 +138,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
136 .flags = IORESOURCE_IRQ, 138 .flags = IORESOURCE_IRQ,
137 }, 139 },
138 [24] = { 140 [24] = {
139 .start = S5PV310_PA_SYSMMU_MDMA2, 141 .start = EXYNOS4_PA_SYSMMU_MDMA2,
140 .end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1, 142 .end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
141 .flags = IORESOURCE_MEM, 143 .flags = IORESOURCE_MEM,
142 }, 144 },
143 [25] = { 145 [25] = {
@@ -146,8 +148,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
146 .flags = IORESOURCE_IRQ, 148 .flags = IORESOURCE_IRQ,
147 }, 149 },
148 [26] = { 150 [26] = {
149 .start = S5PV310_PA_SYSMMU_TV, 151 .start = EXYNOS4_PA_SYSMMU_TV,
150 .end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1, 152 .end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
151 .flags = IORESOURCE_MEM, 153 .flags = IORESOURCE_MEM,
152 }, 154 },
153 [27] = { 155 [27] = {
@@ -156,8 +158,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
156 .flags = IORESOURCE_IRQ, 158 .flags = IORESOURCE_IRQ,
157 }, 159 },
158 [28] = { 160 [28] = {
159 .start = S5PV310_PA_SYSMMU_MFC_L, 161 .start = EXYNOS4_PA_SYSMMU_MFC_L,
160 .end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1, 162 .end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
161 .flags = IORESOURCE_MEM, 163 .flags = IORESOURCE_MEM,
162 }, 164 },
163 [29] = { 165 [29] = {
@@ -166,8 +168,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
166 .flags = IORESOURCE_IRQ, 168 .flags = IORESOURCE_IRQ,
167 }, 169 },
168 [30] = { 170 [30] = {
169 .start = S5PV310_PA_SYSMMU_MFC_R, 171 .start = EXYNOS4_PA_SYSMMU_MFC_R,
170 .end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1, 172 .end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
171 .flags = IORESOURCE_MEM, 173 .flags = IORESOURCE_MEM,
172 }, 174 },
173 [31] = { 175 [31] = {
@@ -177,11 +179,11 @@ static struct resource s5pv310_sysmmu_resource[] = {
177 }, 179 },
178}; 180};
179 181
180struct platform_device s5pv310_device_sysmmu = { 182struct platform_device exynos4_device_sysmmu = {
181 .name = "s5p-sysmmu", 183 .name = "s5p-sysmmu",
182 .id = 32, 184 .id = 32,
183 .num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource), 185 .num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
184 .resource = s5pv310_sysmmu_resource, 186 .resource = exynos4_sysmmu_resource,
185}; 187};
186 188
187EXPORT_SYMBOL(s5pv310_device_sysmmu); 189EXPORT_SYMBOL(exynos4_device_sysmmu);
diff --git a/arch/arm/mach-s5pv310/dma.c b/arch/arm/mach-exynos4/dma.c
index 20066c7c9e56..564bb530f332 100644
--- a/arch/arm/mach-s5pv310/dma.c
+++ b/arch/arm/mach-exynos4/dma.c
@@ -1,4 +1,8 @@
1/* 1/* linux/arch/arm/mach-exynos4/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com> 7 * Jaswinder Singh <jassi.brar@samsung.com>
4 * 8 *
@@ -30,10 +34,10 @@
30 34
31static u64 dma_dmamask = DMA_BIT_MASK(32); 35static u64 dma_dmamask = DMA_BIT_MASK(32);
32 36
33static struct resource s5pv310_pdma0_resource[] = { 37static struct resource exynos4_pdma0_resource[] = {
34 [0] = { 38 [0] = {
35 .start = S5PV310_PA_PDMA0, 39 .start = EXYNOS4_PA_PDMA0,
36 .end = S5PV310_PA_PDMA0 + SZ_4K, 40 .end = EXYNOS4_PA_PDMA0 + SZ_4K,
37 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
38 }, 42 },
39 [1] = { 43 [1] = {
@@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
43 }, 47 },
44}; 48};
45 49
46static struct s3c_pl330_platdata s5pv310_pdma0_pdata = { 50static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
47 .peri = { 51 .peri = {
48 [0] = DMACH_PCM0_RX, 52 [0] = DMACH_PCM0_RX,
49 [1] = DMACH_PCM0_TX, 53 [1] = DMACH_PCM0_TX,
@@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
80 }, 84 },
81}; 85};
82 86
83static struct platform_device s5pv310_device_pdma0 = { 87static struct platform_device exynos4_device_pdma0 = {
84 .name = "s3c-pl330", 88 .name = "s3c-pl330",
85 .id = 0, 89 .id = 0,
86 .num_resources = ARRAY_SIZE(s5pv310_pdma0_resource), 90 .num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
87 .resource = s5pv310_pdma0_resource, 91 .resource = exynos4_pdma0_resource,
88 .dev = { 92 .dev = {
89 .dma_mask = &dma_dmamask, 93 .dma_mask = &dma_dmamask,
90 .coherent_dma_mask = DMA_BIT_MASK(32), 94 .coherent_dma_mask = DMA_BIT_MASK(32),
91 .platform_data = &s5pv310_pdma0_pdata, 95 .platform_data = &exynos4_pdma0_pdata,
92 }, 96 },
93}; 97};
94 98
95static struct resource s5pv310_pdma1_resource[] = { 99static struct resource exynos4_pdma1_resource[] = {
96 [0] = { 100 [0] = {
97 .start = S5PV310_PA_PDMA1, 101 .start = EXYNOS4_PA_PDMA1,
98 .end = S5PV310_PA_PDMA1 + SZ_4K, 102 .end = EXYNOS4_PA_PDMA1 + SZ_4K,
99 .flags = IORESOURCE_MEM, 103 .flags = IORESOURCE_MEM,
100 }, 104 },
101 [1] = { 105 [1] = {
@@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
105 }, 109 },
106}; 110};
107 111
108static struct s3c_pl330_platdata s5pv310_pdma1_pdata = { 112static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
109 .peri = { 113 .peri = {
110 [0] = DMACH_PCM0_RX, 114 [0] = DMACH_PCM0_RX,
111 [1] = DMACH_PCM0_TX, 115 [1] = DMACH_PCM0_TX,
@@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
142 }, 146 },
143}; 147};
144 148
145static struct platform_device s5pv310_device_pdma1 = { 149static struct platform_device exynos4_device_pdma1 = {
146 .name = "s3c-pl330", 150 .name = "s3c-pl330",
147 .id = 1, 151 .id = 1,
148 .num_resources = ARRAY_SIZE(s5pv310_pdma1_resource), 152 .num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
149 .resource = s5pv310_pdma1_resource, 153 .resource = exynos4_pdma1_resource,
150 .dev = { 154 .dev = {
151 .dma_mask = &dma_dmamask, 155 .dma_mask = &dma_dmamask,
152 .coherent_dma_mask = DMA_BIT_MASK(32), 156 .coherent_dma_mask = DMA_BIT_MASK(32),
153 .platform_data = &s5pv310_pdma1_pdata, 157 .platform_data = &exynos4_pdma1_pdata,
154 }, 158 },
155}; 159};
156 160
157static struct platform_device *s5pv310_dmacs[] __initdata = { 161static struct platform_device *exynos4_dmacs[] __initdata = {
158 &s5pv310_device_pdma0, 162 &exynos4_device_pdma0,
159 &s5pv310_device_pdma1, 163 &exynos4_device_pdma1,
160}; 164};
161 165
162static int __init s5pv310_dma_init(void) 166static int __init exynos4_dma_init(void)
163{ 167{
164 platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs)); 168 platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
165 169
166 return 0; 170 return 0;
167} 171}
168arch_initcall(s5pv310_dma_init); 172arch_initcall(exynos4_dma_init);
diff --git a/arch/arm/mach-s5pv310/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
index 55217b8923ec..c46fdc57d94c 100644
--- a/arch/arm/mach-s5pv310/gpiolib.c
+++ b/arch/arm/mach-exynos4/gpiolib.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/gpiolib.c 1/* linux/arch/arm/mach-exynos4/gpiolib.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - GPIOlib support 6 * EXYNOS4 - GPIOlib support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -43,159 +43,159 @@ static struct s3c_gpio_cfg gpio_cfg_noint = {
43 * Note: The initialization of 'base' member of s3c_gpio_chip structure 43 * Note: The initialization of 'base' member of s3c_gpio_chip structure
44 * uses the above macro and depends on the banks being listed in order here. 44 * uses the above macro and depends on the banks being listed in order here.
45 */ 45 */
46static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = { 46static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
47 { 47 {
48 .chip = { 48 .chip = {
49 .base = S5PV310_GPA0(0), 49 .base = EXYNOS4_GPA0(0),
50 .ngpio = S5PV310_GPIO_A0_NR, 50 .ngpio = EXYNOS4_GPIO_A0_NR,
51 .label = "GPA0", 51 .label = "GPA0",
52 }, 52 },
53 }, { 53 }, {
54 .chip = { 54 .chip = {
55 .base = S5PV310_GPA1(0), 55 .base = EXYNOS4_GPA1(0),
56 .ngpio = S5PV310_GPIO_A1_NR, 56 .ngpio = EXYNOS4_GPIO_A1_NR,
57 .label = "GPA1", 57 .label = "GPA1",
58 }, 58 },
59 }, { 59 }, {
60 .chip = { 60 .chip = {
61 .base = S5PV310_GPB(0), 61 .base = EXYNOS4_GPB(0),
62 .ngpio = S5PV310_GPIO_B_NR, 62 .ngpio = EXYNOS4_GPIO_B_NR,
63 .label = "GPB", 63 .label = "GPB",
64 }, 64 },
65 }, { 65 }, {
66 .chip = { 66 .chip = {
67 .base = S5PV310_GPC0(0), 67 .base = EXYNOS4_GPC0(0),
68 .ngpio = S5PV310_GPIO_C0_NR, 68 .ngpio = EXYNOS4_GPIO_C0_NR,
69 .label = "GPC0", 69 .label = "GPC0",
70 }, 70 },
71 }, { 71 }, {
72 .chip = { 72 .chip = {
73 .base = S5PV310_GPC1(0), 73 .base = EXYNOS4_GPC1(0),
74 .ngpio = S5PV310_GPIO_C1_NR, 74 .ngpio = EXYNOS4_GPIO_C1_NR,
75 .label = "GPC1", 75 .label = "GPC1",
76 }, 76 },
77 }, { 77 }, {
78 .chip = { 78 .chip = {
79 .base = S5PV310_GPD0(0), 79 .base = EXYNOS4_GPD0(0),
80 .ngpio = S5PV310_GPIO_D0_NR, 80 .ngpio = EXYNOS4_GPIO_D0_NR,
81 .label = "GPD0", 81 .label = "GPD0",
82 }, 82 },
83 }, { 83 }, {
84 .chip = { 84 .chip = {
85 .base = S5PV310_GPD1(0), 85 .base = EXYNOS4_GPD1(0),
86 .ngpio = S5PV310_GPIO_D1_NR, 86 .ngpio = EXYNOS4_GPIO_D1_NR,
87 .label = "GPD1", 87 .label = "GPD1",
88 }, 88 },
89 }, { 89 }, {
90 .chip = { 90 .chip = {
91 .base = S5PV310_GPE0(0), 91 .base = EXYNOS4_GPE0(0),
92 .ngpio = S5PV310_GPIO_E0_NR, 92 .ngpio = EXYNOS4_GPIO_E0_NR,
93 .label = "GPE0", 93 .label = "GPE0",
94 }, 94 },
95 }, { 95 }, {
96 .chip = { 96 .chip = {
97 .base = S5PV310_GPE1(0), 97 .base = EXYNOS4_GPE1(0),
98 .ngpio = S5PV310_GPIO_E1_NR, 98 .ngpio = EXYNOS4_GPIO_E1_NR,
99 .label = "GPE1", 99 .label = "GPE1",
100 }, 100 },
101 }, { 101 }, {
102 .chip = { 102 .chip = {
103 .base = S5PV310_GPE2(0), 103 .base = EXYNOS4_GPE2(0),
104 .ngpio = S5PV310_GPIO_E2_NR, 104 .ngpio = EXYNOS4_GPIO_E2_NR,
105 .label = "GPE2", 105 .label = "GPE2",
106 }, 106 },
107 }, { 107 }, {
108 .chip = { 108 .chip = {
109 .base = S5PV310_GPE3(0), 109 .base = EXYNOS4_GPE3(0),
110 .ngpio = S5PV310_GPIO_E3_NR, 110 .ngpio = EXYNOS4_GPIO_E3_NR,
111 .label = "GPE3", 111 .label = "GPE3",
112 }, 112 },
113 }, { 113 }, {
114 .chip = { 114 .chip = {
115 .base = S5PV310_GPE4(0), 115 .base = EXYNOS4_GPE4(0),
116 .ngpio = S5PV310_GPIO_E4_NR, 116 .ngpio = EXYNOS4_GPIO_E4_NR,
117 .label = "GPE4", 117 .label = "GPE4",
118 }, 118 },
119 }, { 119 }, {
120 .chip = { 120 .chip = {
121 .base = S5PV310_GPF0(0), 121 .base = EXYNOS4_GPF0(0),
122 .ngpio = S5PV310_GPIO_F0_NR, 122 .ngpio = EXYNOS4_GPIO_F0_NR,
123 .label = "GPF0", 123 .label = "GPF0",
124 }, 124 },
125 }, { 125 }, {
126 .chip = { 126 .chip = {
127 .base = S5PV310_GPF1(0), 127 .base = EXYNOS4_GPF1(0),
128 .ngpio = S5PV310_GPIO_F1_NR, 128 .ngpio = EXYNOS4_GPIO_F1_NR,
129 .label = "GPF1", 129 .label = "GPF1",
130 }, 130 },
131 }, { 131 }, {
132 .chip = { 132 .chip = {
133 .base = S5PV310_GPF2(0), 133 .base = EXYNOS4_GPF2(0),
134 .ngpio = S5PV310_GPIO_F2_NR, 134 .ngpio = EXYNOS4_GPIO_F2_NR,
135 .label = "GPF2", 135 .label = "GPF2",
136 }, 136 },
137 }, { 137 }, {
138 .chip = { 138 .chip = {
139 .base = S5PV310_GPF3(0), 139 .base = EXYNOS4_GPF3(0),
140 .ngpio = S5PV310_GPIO_F3_NR, 140 .ngpio = EXYNOS4_GPIO_F3_NR,
141 .label = "GPF3", 141 .label = "GPF3",
142 }, 142 },
143 }, 143 },
144}; 144};
145 145
146static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = { 146static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
147 { 147 {
148 .chip = { 148 .chip = {
149 .base = S5PV310_GPJ0(0), 149 .base = EXYNOS4_GPJ0(0),
150 .ngpio = S5PV310_GPIO_J0_NR, 150 .ngpio = EXYNOS4_GPIO_J0_NR,
151 .label = "GPJ0", 151 .label = "GPJ0",
152 }, 152 },
153 }, { 153 }, {
154 .chip = { 154 .chip = {
155 .base = S5PV310_GPJ1(0), 155 .base = EXYNOS4_GPJ1(0),
156 .ngpio = S5PV310_GPIO_J1_NR, 156 .ngpio = EXYNOS4_GPIO_J1_NR,
157 .label = "GPJ1", 157 .label = "GPJ1",
158 }, 158 },
159 }, { 159 }, {
160 .chip = { 160 .chip = {
161 .base = S5PV310_GPK0(0), 161 .base = EXYNOS4_GPK0(0),
162 .ngpio = S5PV310_GPIO_K0_NR, 162 .ngpio = EXYNOS4_GPIO_K0_NR,
163 .label = "GPK0", 163 .label = "GPK0",
164 }, 164 },
165 }, { 165 }, {
166 .chip = { 166 .chip = {
167 .base = S5PV310_GPK1(0), 167 .base = EXYNOS4_GPK1(0),
168 .ngpio = S5PV310_GPIO_K1_NR, 168 .ngpio = EXYNOS4_GPIO_K1_NR,
169 .label = "GPK1", 169 .label = "GPK1",
170 }, 170 },
171 }, { 171 }, {
172 .chip = { 172 .chip = {
173 .base = S5PV310_GPK2(0), 173 .base = EXYNOS4_GPK2(0),
174 .ngpio = S5PV310_GPIO_K2_NR, 174 .ngpio = EXYNOS4_GPIO_K2_NR,
175 .label = "GPK2", 175 .label = "GPK2",
176 }, 176 },
177 }, { 177 }, {
178 .chip = { 178 .chip = {
179 .base = S5PV310_GPK3(0), 179 .base = EXYNOS4_GPK3(0),
180 .ngpio = S5PV310_GPIO_K3_NR, 180 .ngpio = EXYNOS4_GPIO_K3_NR,
181 .label = "GPK3", 181 .label = "GPK3",
182 }, 182 },
183 }, { 183 }, {
184 .chip = { 184 .chip = {
185 .base = S5PV310_GPL0(0), 185 .base = EXYNOS4_GPL0(0),
186 .ngpio = S5PV310_GPIO_L0_NR, 186 .ngpio = EXYNOS4_GPIO_L0_NR,
187 .label = "GPL0", 187 .label = "GPL0",
188 }, 188 },
189 }, { 189 }, {
190 .chip = { 190 .chip = {
191 .base = S5PV310_GPL1(0), 191 .base = EXYNOS4_GPL1(0),
192 .ngpio = S5PV310_GPIO_L1_NR, 192 .ngpio = EXYNOS4_GPIO_L1_NR,
193 .label = "GPL1", 193 .label = "GPL1",
194 }, 194 },
195 }, { 195 }, {
196 .chip = { 196 .chip = {
197 .base = S5PV310_GPL2(0), 197 .base = EXYNOS4_GPL2(0),
198 .ngpio = S5PV310_GPIO_L2_NR, 198 .ngpio = EXYNOS4_GPIO_L2_NR,
199 .label = "GPL2", 199 .label = "GPL2",
200 }, 200 },
201 }, { 201 }, {
@@ -203,8 +203,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
203 .config = &gpio_cfg_noint, 203 .config = &gpio_cfg_noint,
204 .irq_base = IRQ_EINT(0), 204 .irq_base = IRQ_EINT(0),
205 .chip = { 205 .chip = {
206 .base = S5PV310_GPX0(0), 206 .base = EXYNOS4_GPX0(0),
207 .ngpio = S5PV310_GPIO_X0_NR, 207 .ngpio = EXYNOS4_GPIO_X0_NR,
208 .label = "GPX0", 208 .label = "GPX0",
209 .to_irq = samsung_gpiolib_to_irq, 209 .to_irq = samsung_gpiolib_to_irq,
210 }, 210 },
@@ -213,8 +213,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
213 .config = &gpio_cfg_noint, 213 .config = &gpio_cfg_noint,
214 .irq_base = IRQ_EINT(8), 214 .irq_base = IRQ_EINT(8),
215 .chip = { 215 .chip = {
216 .base = S5PV310_GPX1(0), 216 .base = EXYNOS4_GPX1(0),
217 .ngpio = S5PV310_GPIO_X1_NR, 217 .ngpio = EXYNOS4_GPIO_X1_NR,
218 .label = "GPX1", 218 .label = "GPX1",
219 .to_irq = samsung_gpiolib_to_irq, 219 .to_irq = samsung_gpiolib_to_irq,
220 }, 220 },
@@ -223,8 +223,8 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
223 .config = &gpio_cfg_noint, 223 .config = &gpio_cfg_noint,
224 .irq_base = IRQ_EINT(16), 224 .irq_base = IRQ_EINT(16),
225 .chip = { 225 .chip = {
226 .base = S5PV310_GPX2(0), 226 .base = EXYNOS4_GPX2(0),
227 .ngpio = S5PV310_GPIO_X2_NR, 227 .ngpio = EXYNOS4_GPIO_X2_NR,
228 .label = "GPX2", 228 .label = "GPX2",
229 .to_irq = samsung_gpiolib_to_irq, 229 .to_irq = samsung_gpiolib_to_irq,
230 }, 230 },
@@ -233,25 +233,25 @@ static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
233 .config = &gpio_cfg_noint, 233 .config = &gpio_cfg_noint,
234 .irq_base = IRQ_EINT(24), 234 .irq_base = IRQ_EINT(24),
235 .chip = { 235 .chip = {
236 .base = S5PV310_GPX3(0), 236 .base = EXYNOS4_GPX3(0),
237 .ngpio = S5PV310_GPIO_X3_NR, 237 .ngpio = EXYNOS4_GPIO_X3_NR,
238 .label = "GPX3", 238 .label = "GPX3",
239 .to_irq = samsung_gpiolib_to_irq, 239 .to_irq = samsung_gpiolib_to_irq,
240 }, 240 },
241 }, 241 },
242}; 242};
243 243
244static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = { 244static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
245 { 245 {
246 .chip = { 246 .chip = {
247 .base = S5PV310_GPZ(0), 247 .base = EXYNOS4_GPZ(0),
248 .ngpio = S5PV310_GPIO_Z_NR, 248 .ngpio = EXYNOS4_GPIO_Z_NR,
249 .label = "GPZ", 249 .label = "GPZ",
250 }, 250 },
251 }, 251 },
252}; 252};
253 253
254static __init int s5pv310_gpiolib_init(void) 254static __init int exynos4_gpiolib_init(void)
255{ 255{
256 struct s3c_gpio_chip *chip; 256 struct s3c_gpio_chip *chip;
257 int i; 257 int i;
@@ -259,8 +259,8 @@ static __init int s5pv310_gpiolib_init(void)
259 259
260 /* GPIO part 1 */ 260 /* GPIO part 1 */
261 261
262 chip = s5pv310_gpio_part1_4bit; 262 chip = exynos4_gpio_part1_4bit;
263 nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit); 263 nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
264 264
265 for (i = 0; i < nr_chips; i++, chip++) { 265 for (i = 0; i < nr_chips; i++, chip++) {
266 if (chip->config == NULL) 266 if (chip->config == NULL)
@@ -269,12 +269,12 @@ static __init int s5pv310_gpiolib_init(void)
269 chip->base = S5P_VA_GPIO1 + (i) * 0x20; 269 chip->base = S5P_VA_GPIO1 + (i) * 0x20;
270 } 270 }
271 271
272 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips); 272 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
273 273
274 /* GPIO part 2 */ 274 /* GPIO part 2 */
275 275
276 chip = s5pv310_gpio_part2_4bit; 276 chip = exynos4_gpio_part2_4bit;
277 nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit); 277 nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
278 278
279 for (i = 0; i < nr_chips; i++, chip++) { 279 for (i = 0; i < nr_chips; i++, chip++) {
280 if (chip->config == NULL) 280 if (chip->config == NULL)
@@ -283,12 +283,12 @@ static __init int s5pv310_gpiolib_init(void)
283 chip->base = S5P_VA_GPIO2 + (i) * 0x20; 283 chip->base = S5P_VA_GPIO2 + (i) * 0x20;
284 } 284 }
285 285
286 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips); 286 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
287 287
288 /* GPIO part 3 */ 288 /* GPIO part 3 */
289 289
290 chip = s5pv310_gpio_part3_4bit; 290 chip = exynos4_gpio_part3_4bit;
291 nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit); 291 nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
292 292
293 for (i = 0; i < nr_chips; i++, chip++) { 293 for (i = 0; i < nr_chips; i++, chip++) {
294 if (chip->config == NULL) 294 if (chip->config == NULL)
@@ -297,8 +297,8 @@ static __init int s5pv310_gpiolib_init(void)
297 chip->base = S5P_VA_GPIO3 + (i) * 0x20; 297 chip->base = S5P_VA_GPIO3 + (i) * 0x20;
298 } 298 }
299 299
300 samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips); 300 samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
301 301
302 return 0; 302 return 0;
303} 303}
304core_initcall(s5pv310_gpiolib_init); 304core_initcall(exynos4_gpiolib_init);
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-exynos4/headsmp.S
index 164b7b045713..6c6cfc50c46b 100644
--- a/arch/arm/mach-s5pv310/headsmp.S
+++ b/arch/arm/mach-exynos4/headsmp.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/headsmp.S 2 * linux/arch/arm/mach-exynos4/headsmp.S
3 * 3 *
4 * Cloned from linux/arch/arm/mach-realview/headsmp.S 4 * Cloned from linux/arch/arm/mach-realview/headsmp.S
5 * 5 *
@@ -16,11 +16,11 @@
16 __INIT 16 __INIT
17 17
18/* 18/*
19 * s5pv310 specific entry point for secondary CPUs. This provides 19 * exynos4 specific entry point for secondary CPUs. This provides
20 * a "holding pen" into which all secondary cores are held until we're 20 * a "holding pen" into which all secondary cores are held until we're
21 * ready for them to initialise. 21 * ready for them to initialise.
22 */ 22 */
23ENTRY(s5pv310_secondary_startup) 23ENTRY(exynos4_secondary_startup)
24 mrc p15, 0, r0, c0, c0, 5 24 mrc p15, 0, r0, c0, c0, 5
25 and r0, r0, #15 25 and r0, r0, #15
26 adr r4, 1f 26 adr r4, 1f
diff --git a/arch/arm/mach-s5pv310/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index c24235c89eed..2b5909e2ccd3 100644
--- a/arch/arm/mach-s5pv310/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -1,4 +1,4 @@
1/* linux arch/arm/mach-s5pv310/hotplug.c 1/* linux arch/arm/mach-exynos4/hotplug.c
2 * 2 *
3 * Cloned from linux/arch/arm/mach-realview/hotplug.c 3 * Cloned from linux/arch/arm/mach-realview/hotplug.c
4 * 4 *
@@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
30 * Turn off coherency 30 * Turn off coherency
31 */ 31 */
32 " mrc p15, 0, %0, c1, c0, 1\n" 32 " mrc p15, 0, %0, c1, c0, 1\n"
33 " bic %0, %0, #0x20\n" 33 " bic %0, %0, %3\n"
34 " mcr p15, 0, %0, c1, c0, 1\n" 34 " mcr p15, 0, %0, c1, c0, 1\n"
35 " mrc p15, 0, %0, c1, c0, 0\n" 35 " mrc p15, 0, %0, c1, c0, 0\n"
36 " bic %0, %0, %2\n" 36 " bic %0, %0, %2\n"
37 " mcr p15, 0, %0, c1, c0, 0\n" 37 " mcr p15, 0, %0, c1, c0, 0\n"
38 : "=&r" (v) 38 : "=&r" (v)
39 : "r" (0), "Ir" (CR_C) 39 : "r" (0), "Ir" (CR_C), "Ir" (0x40)
40 : "cc"); 40 : "cc");
41} 41}
42 42
@@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
49 " orr %0, %0, %1\n" 49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n" 50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n" 51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x20\n" 52 " orr %0, %0, %2\n"
53 " mcr p15, 0, %0, c1, c0, 1\n" 53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v) 54 : "=&r" (v)
55 : "Ir" (CR_C) 55 : "Ir" (CR_C), "Ir" (0x40)
56 : "cc"); 56 : "cc");
57} 57}
58 58
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
index b0d920c474d3..58bbd049a6c4 100644
--- a/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S 1/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S 6 * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
7 * 7 *
diff --git a/arch/arm/mach-s5pv310/include/mach/dma.h b/arch/arm/mach-exynos4/include/mach/dma.h
index 81209eb1409b..81209eb1409b 100644
--- a/arch/arm/mach-s5pv310/include/mach/dma.h
+++ b/arch/arm/mach-exynos4/include/mach/dma.h
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index e600e1d522df..d8f38c2e5654 100644
--- a/arch/arm/mach-s5pv310/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -1,8 +1,8 @@
1/* arch/arm/mach-s5pv310/include/mach/entry-macro.S 1/* arch/arm/mach-exynos4/include/mach/entry-macro.S
2 * 2 *
3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S 3 * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
4 * 4 *
5 * Low-level IRQ helper macros for S5PV310 platforms 5 * Low-level IRQ helper macros for EXYNOS4 platforms
6 * 6 *
7 * This file is licensed under the terms of the GNU General Public 7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any 8 * License version 2. This program is licensed "as is" without any
diff --git a/arch/arm/mach-exynos4/include/mach/gpio.h b/arch/arm/mach-exynos4/include/mach/gpio.h
new file mode 100644
index 000000000000..16082998bcd8
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/gpio.h
@@ -0,0 +1,135 @@
1/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define EXYNOS4_GPIO_A0_NR (8)
25#define EXYNOS4_GPIO_A1_NR (6)
26#define EXYNOS4_GPIO_B_NR (8)
27#define EXYNOS4_GPIO_C0_NR (5)
28#define EXYNOS4_GPIO_C1_NR (5)
29#define EXYNOS4_GPIO_D0_NR (4)
30#define EXYNOS4_GPIO_D1_NR (4)
31#define EXYNOS4_GPIO_E0_NR (5)
32#define EXYNOS4_GPIO_E1_NR (8)
33#define EXYNOS4_GPIO_E2_NR (6)
34#define EXYNOS4_GPIO_E3_NR (8)
35#define EXYNOS4_GPIO_E4_NR (8)
36#define EXYNOS4_GPIO_F0_NR (8)
37#define EXYNOS4_GPIO_F1_NR (8)
38#define EXYNOS4_GPIO_F2_NR (8)
39#define EXYNOS4_GPIO_F3_NR (6)
40#define EXYNOS4_GPIO_J0_NR (8)
41#define EXYNOS4_GPIO_J1_NR (5)
42#define EXYNOS4_GPIO_K0_NR (7)
43#define EXYNOS4_GPIO_K1_NR (7)
44#define EXYNOS4_GPIO_K2_NR (7)
45#define EXYNOS4_GPIO_K3_NR (7)
46#define EXYNOS4_GPIO_L0_NR (8)
47#define EXYNOS4_GPIO_L1_NR (3)
48#define EXYNOS4_GPIO_L2_NR (8)
49#define EXYNOS4_GPIO_X0_NR (8)
50#define EXYNOS4_GPIO_X1_NR (8)
51#define EXYNOS4_GPIO_X2_NR (8)
52#define EXYNOS4_GPIO_X3_NR (8)
53#define EXYNOS4_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define EXYNOS4_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 EXYNOS4_GPIO_A0_START = 0,
62 EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
63 EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
64 EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
65 EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
66 EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
67 EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
68 EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
69 EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
70 EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
71 EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
72 EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
73 EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
74 EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
75 EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
76 EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
77 EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
78 EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
79 EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
80 EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
81 EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
82 EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
83 EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
84 EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
85 EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
86 EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
87 EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
88 EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
89 EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
90 EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
91};
92
93/* EXYNOS4 GPIO number definitions */
94#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
95#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
96#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
97#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
98#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
99#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
100#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
101#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
102#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
103#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
104#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
105#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
106#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
107#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
108#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
109#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
110#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
111#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
112#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
113#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
114#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
115#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
116#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
117#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
118#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
119#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
120#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
121#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
122#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
123#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
124
125/* the end of the EXYNOS4 specific gpios */
126#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END EXYNOS4_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-exynos4/include/mach/hardware.h
index 28ff9881f1a6..5109eb232f23 100644
--- a/arch/arm/mach-s5pv310/include/mach/hardware.h
+++ b/arch/arm/mach-exynos4/include/mach/hardware.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h 1/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Hardware support 6 * EXYNOS4 - Hardware support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-exynos4/include/mach/io.h
index 8a7f9128391f..d5478d247535 100644
--- a/arch/arm/mach-s5pv310/include/mach/io.h
+++ b/arch/arm/mach-exynos4/include/mach/io.h
@@ -1,13 +1,13 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/io.h 1/* linux/arch/arm/mach-exynos4/include/mach/io.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
7 * 7 *
8 * Based on arch/arm/mach-s5p6442/include/mach/io.h 8 * Based on arch/arm/mach-s5p6442/include/mach/io.h
9 * 9 *
10 * Default IO routines for S5PV310 10 * Default IO routines for EXYNOS4
11 * 11 *
12 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 536b0b59fc83..e3556d45c75b 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h 1/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - IRQ definitions 6 * EXYNOS4 - IRQ definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -131,6 +131,7 @@
131#define IRQ_MCT_L0 COMBINER_IRQ(51, 0) 131#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
132 132
133#define IRQ_WDT COMBINER_IRQ(53, 0) 133#define IRQ_WDT COMBINER_IRQ(53, 0)
134#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
134 135
135#define MAX_COMBINER_NR 54 136#define MAX_COMBINER_NR 54
136 137
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
new file mode 100644
index 000000000000..89ab6f75776c
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -0,0 +1,145 @@
1/* linux/arch/arm/mach-exynos4/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * EXYNOS4 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define EXYNOS4_PA_SYSRAM 0x02020000
27
28#define EXYNOS4_PA_I2S0 0x03830000
29#define EXYNOS4_PA_I2S1 0xE3100000
30#define EXYNOS4_PA_I2S2 0xE2A00000
31
32#define EXYNOS4_PA_PCM0 0x03840000
33#define EXYNOS4_PA_PCM1 0x13980000
34#define EXYNOS4_PA_PCM2 0x13990000
35
36#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define EXYNOS4_PA_ONENAND 0x0C000000
39#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
40
41#define EXYNOS4_PA_CHIPID 0x10000000
42
43#define EXYNOS4_PA_SYSCON 0x10010000
44#define EXYNOS4_PA_PMU 0x10020000
45#define EXYNOS4_PA_CMU 0x10030000
46
47#define EXYNOS4_PA_SYSTIMER 0x10050000
48#define EXYNOS4_PA_WATCHDOG 0x10060000
49#define EXYNOS4_PA_RTC 0x10070000
50
51#define EXYNOS4_PA_DMC0 0x10400000
52
53#define EXYNOS4_PA_COMBINER 0x10448000
54
55#define EXYNOS4_PA_COREPERI 0x10500000
56#define EXYNOS4_PA_GIC_CPU 0x10500100
57#define EXYNOS4_PA_TWD 0x10500600
58#define EXYNOS4_PA_GIC_DIST 0x10501000
59#define EXYNOS4_PA_L2CC 0x10502000
60
61#define EXYNOS4_PA_MDMA 0x10810000
62#define EXYNOS4_PA_PDMA0 0x12680000
63#define EXYNOS4_PA_PDMA1 0x12690000
64
65#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
66#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
67#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
68#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
69#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
70#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
71#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
72#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
73#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
74#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
75#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
76#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
77#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
78#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
79#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
80#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
81
82#define EXYNOS4_PA_GPIO1 0x11400000
83#define EXYNOS4_PA_GPIO2 0x11000000
84#define EXYNOS4_PA_GPIO3 0x03860000
85
86#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
87#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
88
89#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
90
91#define EXYNOS4_PA_SROMC 0x12570000
92
93#define EXYNOS4_PA_UART 0x13800000
94
95#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
96
97#define EXYNOS4_PA_AC97 0x139A0000
98
99#define EXYNOS4_PA_SPDIF 0x139B0000
100
101#define EXYNOS4_PA_TIMER 0x139D0000
102
103#define EXYNOS4_PA_SDRAM 0x40000000
104
105/* Compatibiltiy Defines */
106
107#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
108#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
109#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
110#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
111#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
112#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
113#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
114#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
115#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
116#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
117#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
118#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
119#define S3C_PA_RTC EXYNOS4_PA_RTC
120#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
121
122#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
123#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
124#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
125#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
126#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
127#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
128#define S5P_PA_SROMC EXYNOS4_PA_SROMC
129#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
130#define S5P_PA_TIMER EXYNOS4_PA_TIMER
131
132/* UART */
133
134#define S3C_PA_UART EXYNOS4_PA_UART
135
136#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
137#define S5P_PA_UART0 S5P_PA_UART(0)
138#define S5P_PA_UART1 S5P_PA_UART(1)
139#define S5P_PA_UART2 S5P_PA_UART(2)
140#define S5P_PA_UART3 S5P_PA_UART(3)
141#define S5P_PA_UART4 S5P_PA_UART(4)
142
143#define S5P_SZ_UART SZ_256
144
145#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-exynos4/include/mach/memory.h
index 1dffb4823245..39b47d06f9bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/memory.h
+++ b/arch/arm/mach-exynos4/include/mach/memory.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/memory.h 1/* linux/arch/arm/mach-exynos4/include/mach/memory.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Memory definitions 6 * EXYNOS4 - Memory definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
index 7e6da2701088..8e12090287bb 100644
--- a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/pwm-clock.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2008 Openmoko, Inc. 6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
@@ -10,7 +10,7 @@
10 * 10 *
11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h 11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
12 * 12 *
13 * S5PV310 - pwm clock and timer support 13 * EXYNOS4 - pwm clock and timer support
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify 15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as 16 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index b5c4ada1cff5..ba8f91c04e19 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Clock register definitions 6 * EXYNOS4 - Clock register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-gpio.h b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
new file mode 100644
index 000000000000..1401b21663a5
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-gpio.h
@@ -0,0 +1,42 @@
1/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
21
22#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
24
25#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
27
28#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
38#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
39#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
40#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-irq.h b/arch/arm/mach-exynos4/include/mach/regs-irq.h
index c6e09c7f9161..9c7b4bfd546f 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-irq.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-irq.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - IRQ register definitions 6 * EXYNOS4 - IRQ register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-exynos4/include/mach/regs-mct.h b/arch/arm/mach-exynos4/include/mach/regs-mct.h
new file mode 100644
index 000000000000..ca9c8434b023
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-mct.h
@@ -0,0 +1,52 @@
1/* arch/arm/mach-exynos4/include/mach/regs-mct.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT configutation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_MCT_H
14#define __ASM_ARCH_REGS_MCT_H __FILE__
15
16#include <mach/map.h>
17
18#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
19
20#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
21#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
22#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
23
24#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
25#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
26#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
27
28#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
29
30#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
31#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
32#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
33
34#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
35#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
36
37#define MCT_L_TCNTB_OFFSET (0x00)
38#define MCT_L_ICNTB_OFFSET (0x08)
39#define MCT_L_TCON_OFFSET (0x20)
40#define MCT_L_INT_CSTAT_OFFSET (0x30)
41#define MCT_L_INT_ENB_OFFSET (0x34)
42#define MCT_L_WSTAT_OFFSET (0x40)
43
44#define MCT_G_TCON_START (1 << 8)
45#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
46#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
47
48#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
49#define MCT_L_TCON_INT_START (1 << 1)
50#define MCT_L_TCON_TIMER_START (1 << 0)
51
52#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-mem.h b/arch/arm/mach-exynos4/include/mach/regs-mem.h
index 834227140eaa..0368b5a27252 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-mem.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-mem.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - SROMC and DMC register definitions 6 * EXYNOS4 - SROMC and DMC register definitions
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index fb333d0f6073..2ddd6175dfa0 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Power management unit definition 6 * EXYNOS4 - Power management unit definition
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -18,7 +18,7 @@
18#define S5P_PMUREG(x) (S5P_VA_PMU + (x)) 18#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
19 19
20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) 20#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) 21#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) 22#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) 23#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) 24#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
index 0b28e81a16f7..b6aef863b9d6 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - System MMU register 6 * EXYNOS4 - System MMU register
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
index 393ccbd52c4a..a463dcebcfd3 100644
--- a/arch/arm/mach-s5pv310/include/mach/smp.h
+++ b/arch/arm/mach-exynos4/include/mach/smp.h
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/smp.h 1/* linux/arch/arm/mach-exynos4/include/mach/smp.h
2 * 2 *
3 * Cloned from arch/arm/mach-realview/include/mach/smp.h 3 * Cloned from arch/arm/mach-realview/include/mach/smp.h
4*/ 4*/
diff --git a/arch/arm/mach-s5pv310/include/mach/sysmmu.h b/arch/arm/mach-exynos4/include/mach/sysmmu.h
index 598fc5c9211b..1428adad8379 100644
--- a/arch/arm/mach-s5pv310/include/mach/sysmmu.h
+++ b/arch/arm/mach-exynos4/include/mach/sysmmu.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h 1/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Samsung sysmmu driver for S5PV310 6 * Samsung sysmmu driver for EXYNOS4
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -13,10 +13,10 @@
13#ifndef __ASM_ARM_ARCH_SYSMMU_H 13#ifndef __ASM_ARM_ARCH_SYSMMU_H
14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__ 14#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
15 15
16#define S5PV310_SYSMMU_TOTAL_IPNUM 16 16#define EXYNOS4_SYSMMU_TOTAL_IPNUM 16
17#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM 17#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
18 18
19enum s5pv310_sysmmu_ips { 19enum exynos4_sysmmu_ips {
20 SYSMMU_MDMA, 20 SYSMMU_MDMA,
21 SYSMMU_SSS, 21 SYSMMU_SSS,
22 SYSMMU_FIMC0, 22 SYSMMU_FIMC0,
@@ -35,7 +35,7 @@ enum s5pv310_sysmmu_ips {
35 SYSMMU_MFC_R, 35 SYSMMU_MFC_R,
36}; 36};
37 37
38static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = { 38static char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
39 "SYSMMU_MDMA" , 39 "SYSMMU_MDMA" ,
40 "SYSMMU_SSS" , 40 "SYSMMU_SSS" ,
41 "SYSMMU_FIMC0" , 41 "SYSMMU_FIMC0" ,
@@ -54,7 +54,7 @@ static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
54 "SYSMMU_MFC_R" , 54 "SYSMMU_MFC_R" ,
55}; 55};
56 56
57typedef enum s5pv310_sysmmu_ips sysmmu_ips; 57typedef enum exynos4_sysmmu_ips sysmmu_ips;
58 58
59struct sysmmu_tt_info { 59struct sysmmu_tt_info {
60 unsigned long *pgd; 60 unsigned long *pgd;
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-exynos4/include/mach/system.h
index d10c009cf0f1..5e3220c18fc7 100644
--- a/arch/arm/mach-s5pv310/include/mach/system.h
+++ b/arch/arm/mach-exynos4/include/mach/system.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/system.h 1/* linux/arch/arm/mach-exynos4/include/mach/system.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - system support header 6 * EXYNOS4 - system support header
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-exynos4/include/mach/timex.h
index bd2359b952b4..6d138750a708 100644
--- a/arch/arm/mach-s5pv310/include/mach/timex.h
+++ b/arch/arm/mach-exynos4/include/mach/timex.h
@@ -1,14 +1,14 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/timex.h 1/* linux/arch/arm/mach-exynos4/include/mach/timex.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright (c) 2003-2010 Simtec Electronics 6 * Copyright (c) 2003-2010 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
8 * 8 *
9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h 9 * Based on arch/arm/mach-s5p6442/include/mach/timex.h
10 * 10 *
11 * S5PV310 - time parameters 11 * EXYNOS4 - time parameters
12 * 12 *
13 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-exynos4/include/mach/uncompress.h
index 59593c1e2416..21d97bcd9acb 100644
--- a/arch/arm/mach-s5pv310/include/mach/uncompress.h
+++ b/arch/arm/mach-exynos4/include/mach/uncompress.h
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h 1/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - uncompress code 6 * EXYNOS4 - uncompress code
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-exynos4/include/mach/vmalloc.h
index 65759fb97581..284330e571d2 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-exynos4/include/mach/vmalloc.h
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h 1/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org> 6 * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
7 * 7 *
@@ -11,7 +11,7 @@
11 * it under the terms of the GNU General Public License version 2 as 11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation. 12 * published by the Free Software Foundation.
13 * 13 *
14 * S5PV310 vmalloc definition 14 * EXYNOS4 vmalloc definition
15*/ 15*/
16 16
17#ifndef __ASM_ARCH_VMALLOC_H 17#ifndef __ASM_ARCH_VMALLOC_H
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-exynos4/init.c
index 182dcf42cfb4..cf91f50e43ab 100644
--- a/arch/arm/mach-s5pv310/init.c
+++ b/arch/arm/mach-exynos4/init.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/init.c 1/* linux/arch/arm/mach-exynos4/init.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com/
@@ -14,7 +14,7 @@
14#include <plat/devs.h> 14#include <plat/devs.h>
15#include <plat/regs-serial.h> 15#include <plat/regs-serial.h>
16 16
17static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = { 17static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
18 [0] = { 18 [0] = {
19 .name = "uclk1", 19 .name = "uclk1",
20 .divisor = 1, 20 .divisor = 1,
@@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
24}; 24};
25 25
26/* uart registration process */ 26/* uart registration process */
27void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) 27void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
28{ 28{
29 struct s3c2410_uartcfg *tcfg = cfg; 29 struct s3c2410_uartcfg *tcfg = cfg;
30 u32 ucnt; 30 u32 ucnt;
@@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) { 32 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
33 if (!tcfg->clocks) { 33 if (!tcfg->clocks) {
34 tcfg->has_fracval = 1; 34 tcfg->has_fracval = 1;
35 tcfg->clocks = s5pv310_serial_clocks; 35 tcfg->clocks = exynos4_serial_clocks;
36 tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks); 36 tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
37 } 37 }
38 } 38 }
39 39
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 1ea4a9e83bbe..31618d91ce15 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s5pv310/irq-combiner.c 1/* linux/arch/arm/mach-exynos4/irq-combiner.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * Based on arch/arm/common/gic.c 6 * Based on arch/arm/common/gic.c
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 477bd9e97f0f..4f7ad4a796e4 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/irq-eint.c 1/* linux/arch/arm/mach-exynos4/irq-eint.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - IRQ EINT support 6 * EXYNOS4 - IRQ EINT support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock);
27 27
28static unsigned int eint0_15_data[16]; 28static unsigned int eint0_15_data[16];
29 29
30static unsigned int s5pv310_get_irq_nr(unsigned int number) 30static unsigned int exynos4_get_irq_nr(unsigned int number)
31{ 31{
32 u32 ret = 0; 32 u32 ret = 0;
33 33
@@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
48 return ret; 48 return ret;
49} 49}
50 50
51static inline void s5pv310_irq_eint_mask(struct irq_data *data) 51static inline void exynos4_irq_eint_mask(struct irq_data *data)
52{ 52{
53 u32 mask; 53 u32 mask;
54 54
@@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data)
59 spin_unlock(&eint_lock); 59 spin_unlock(&eint_lock);
60} 60}
61 61
62static void s5pv310_irq_eint_unmask(struct irq_data *data) 62static void exynos4_irq_eint_unmask(struct irq_data *data)
63{ 63{
64 u32 mask; 64 u32 mask;
65 65
@@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data)
70 spin_unlock(&eint_lock); 70 spin_unlock(&eint_lock);
71} 71}
72 72
73static inline void s5pv310_irq_eint_ack(struct irq_data *data) 73static inline void exynos4_irq_eint_ack(struct irq_data *data)
74{ 74{
75 __raw_writel(eint_irq_to_bit(data->irq), 75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq))); 76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
77} 77}
78 78
79static void s5pv310_irq_eint_maskack(struct irq_data *data) 79static void exynos4_irq_eint_maskack(struct irq_data *data)
80{ 80{
81 s5pv310_irq_eint_mask(data); 81 exynos4_irq_eint_mask(data);
82 s5pv310_irq_eint_ack(data); 82 exynos4_irq_eint_ack(data);
83} 83}
84 84
85static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type) 85static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
86{ 86{
87 int offs = EINT_OFFSET(data->irq); 87 int offs = EINT_OFFSET(data->irq);
88 int shift; 88 int shift;
@@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
145 return 0; 145 return 0;
146} 146}
147 147
148static struct irq_chip s5pv310_irq_eint = { 148static struct irq_chip exynos4_irq_eint = {
149 .name = "s5pv310-eint", 149 .name = "exynos4-eint",
150 .irq_mask = s5pv310_irq_eint_mask, 150 .irq_mask = exynos4_irq_eint_mask,
151 .irq_unmask = s5pv310_irq_eint_unmask, 151 .irq_unmask = exynos4_irq_eint_unmask,
152 .irq_mask_ack = s5pv310_irq_eint_maskack, 152 .irq_mask_ack = exynos4_irq_eint_maskack,
153 .irq_ack = s5pv310_irq_eint_ack, 153 .irq_ack = exynos4_irq_eint_ack,
154 .irq_set_type = s5pv310_irq_eint_set_type, 154 .irq_set_type = exynos4_irq_eint_set_type,
155#ifdef CONFIG_PM 155#ifdef CONFIG_PM
156 .irq_set_wake = s3c_irqext_wake, 156 .irq_set_wake = s3c_irqext_wake,
157#endif 157#endif
158}; 158};
159 159
160/* s5pv310_irq_demux_eint 160/* exynos4_irq_demux_eint
161 * 161 *
162 * This function demuxes the IRQ from from EINTs 16 to 31. 162 * This function demuxes the IRQ from from EINTs 16 to 31.
163 * It is designed to be inlined into the specific handler 163 * It is designed to be inlined into the specific handler
@@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = {
165 * 165 *
166 * Each EINT pend/mask registers handle eight of them. 166 * Each EINT pend/mask registers handle eight of them.
167 */ 167 */
168static inline void s5pv310_irq_demux_eint(unsigned int start) 168static inline void exynos4_irq_demux_eint(unsigned int start)
169{ 169{
170 unsigned int irq; 170 unsigned int irq;
171 171
@@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start)
182 } 182 }
183} 183}
184 184
185static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) 185static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
186{ 186{
187 s5pv310_irq_demux_eint(IRQ_EINT(16)); 187 exynos4_irq_demux_eint(IRQ_EINT(16));
188 s5pv310_irq_demux_eint(IRQ_EINT(24)); 188 exynos4_irq_demux_eint(IRQ_EINT(24));
189} 189}
190 190
191static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc) 191static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192{ 192{
193 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = get_irq_data(irq);
194 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = get_irq_chip(irq);
@@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
203 chip->irq_unmask(&desc->irq_data); 203 chip->irq_unmask(&desc->irq_data);
204} 204}
205 205
206int __init s5pv310_init_irq_eint(void) 206int __init exynos4_init_irq_eint(void)
207{ 207{
208 int irq; 208 int irq;
209 209
210 for (irq = 0 ; irq <= 31 ; irq++) { 210 for (irq = 0 ; irq <= 31 ; irq++) {
211 set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint); 211 set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
212 set_irq_handler(IRQ_EINT(irq), handle_level_irq); 212 set_irq_handler(IRQ_EINT(irq), handle_level_irq);
213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID); 213 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
214 } 214 }
215 215
216 set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31); 216 set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
217 217
218 for (irq = 0 ; irq <= 15 ; irq++) { 218 for (irq = 0 ; irq <= 15 ; irq++) {
219 eint0_15_data[irq] = IRQ_EINT(irq); 219 eint0_15_data[irq] = IRQ_EINT(irq);
220 220
221 set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]); 221 set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
222 set_irq_chained_handler(s5pv310_get_irq_nr(irq), 222 set_irq_chained_handler(exynos4_get_irq_nr(irq),
223 s5pv310_irq_eint0_15); 223 exynos4_irq_eint0_15);
224 } 224 }
225 225
226 return 0; 226 return 0;
227} 227}
228 228
229arch_initcall(s5pv310_init_irq_eint); 229arch_initcall(exynos4_init_irq_eint);
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
index 2784036cd8b1..2a2993ae8d86 100644
--- a/arch/arm/mach-s5pv310/localtimer.c
+++ b/arch/arm/mach-exynos4/localtimer.c
@@ -1,4 +1,4 @@
1/* linux/arch/arm/mach-s5pv310/localtimer.c 1/* linux/arch/arm/mach-exynos4/localtimer.c
2 * 2 *
3 * Cloned from linux/arch/arm/mach-realview/localtimer.c 3 * Cloned from linux/arch/arm/mach-realview/localtimer.c
4 * 4 *
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
new file mode 100644
index 000000000000..1ec7e77bed82
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -0,0 +1,214 @@
1/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/gpio.h>
12#include <linux/io.h>
13#include <linux/mmc/host.h>
14#include <linux/platform_device.h>
15#include <linux/serial_core.h>
16#include <linux/smsc911x.h>
17
18#include <asm/mach/arch.h>
19#include <asm/mach-types.h>
20
21#include <plat/cpu.h>
22#include <plat/devs.h>
23#include <plat/exynos4.h>
24#include <plat/gpio-cfg.h>
25#include <plat/regs-serial.h>
26#include <plat/regs-srom.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG4 | \
43 S5PV210_UFCON_RXTRIG4)
44
45static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .flags = 0,
49 .ucon = ARMLEX4210_UCON_DEFAULT,
50 .ulcon = ARMLEX4210_ULCON_DEFAULT,
51 .ufcon = ARMLEX4210_UFCON_DEFAULT,
52 },
53 [1] = {
54 .hwport = 1,
55 .flags = 0,
56 .ucon = ARMLEX4210_UCON_DEFAULT,
57 .ulcon = ARMLEX4210_ULCON_DEFAULT,
58 .ufcon = ARMLEX4210_UFCON_DEFAULT,
59 },
60 [2] = {
61 .hwport = 2,
62 .flags = 0,
63 .ucon = ARMLEX4210_UCON_DEFAULT,
64 .ulcon = ARMLEX4210_ULCON_DEFAULT,
65 .ufcon = ARMLEX4210_UFCON_DEFAULT,
66 },
67 [3] = {
68 .hwport = 3,
69 .flags = 0,
70 .ucon = ARMLEX4210_UCON_DEFAULT,
71 .ulcon = ARMLEX4210_ULCON_DEFAULT,
72 .ufcon = ARMLEX4210_UFCON_DEFAULT,
73 },
74};
75
76static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
77 .cd_type = S3C_SDHCI_CD_PERMANENT,
78 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
79#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
80 .max_width = 8,
81 .host_caps = MMC_CAP_8_BIT_DATA,
82#endif
83};
84
85static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
86 .cd_type = S3C_SDHCI_CD_GPIO,
87 .ext_cd_gpio = EXYNOS4_GPX2(5),
88 .ext_cd_gpio_invert = 1,
89 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
90 .max_width = 4,
91};
92
93static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
94 .cd_type = S3C_SDHCI_CD_PERMANENT,
95 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
96 .max_width = 4,
97};
98
99static void __init armlex4210_sdhci_init(void)
100{
101 s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
102 s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
103 s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
104}
105
106static void __init armlex4210_wlan_init(void)
107{
108 /* enable */
109 s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
110 s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
111
112 /* reset */
113 s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
114 s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
115
116 /* wakeup */
117 s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
118 s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
119}
120
121static struct resource armlex4210_smsc911x_resources[] = {
122 [0] = {
123 .start = EXYNOS4_PA_SROM_BANK(3),
124 .end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
125 .flags = IORESOURCE_MEM,
126 },
127 [1] = {
128 .start = IRQ_EINT(27),
129 .end = IRQ_EINT(27),
130 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
131 },
132};
133
134static struct smsc911x_platform_config smsc9215_config = {
135 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
136 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
137 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
138 .phy_interface = PHY_INTERFACE_MODE_MII,
139 .mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
140};
141
142static struct platform_device armlex4210_smsc911x = {
143 .name = "smsc911x",
144 .id = -1,
145 .num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
146 .resource = armlex4210_smsc911x_resources,
147 .dev = {
148 .platform_data = &smsc9215_config,
149 },
150};
151
152static struct platform_device *armlex4210_devices[] __initdata = {
153 &s3c_device_hsmmc0,
154 &s3c_device_hsmmc2,
155 &s3c_device_hsmmc3,
156 &s3c_device_rtc,
157 &s3c_device_wdt,
158 &exynos4_device_sysmmu,
159 &samsung_asoc_dma,
160 &armlex4210_smsc911x,
161};
162
163static void __init armlex4210_smsc911x_init(void)
164{
165 u32 cs1;
166
167 /* configure nCS1 width to 16 bits */
168 cs1 = __raw_readl(S5P_SROM_BW) &
169 ~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
170 cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
171 (0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
172 (1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
173 (1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
174 S5P_SROM_BW__NCS1__SHIFT;
175 __raw_writel(cs1, S5P_SROM_BW);
176
177 /* set timing for nCS1 suitable for ethernet chip */
178 __raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
179 (0x9 << S5P_SROM_BCX__TACP__SHIFT) |
180 (0xc << S5P_SROM_BCX__TCAH__SHIFT) |
181 (0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
182 (0x6 << S5P_SROM_BCX__TACC__SHIFT) |
183 (0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
184 (0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
185}
186
187static void __init armlex4210_map_io(void)
188{
189 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
190 s3c24xx_init_clocks(24000000);
191 s3c24xx_init_uarts(armlex4210_uartcfgs,
192 ARRAY_SIZE(armlex4210_uartcfgs));
193}
194
195static void __init armlex4210_machine_init(void)
196{
197 armlex4210_smsc911x_init();
198
199 armlex4210_sdhci_init();
200
201 armlex4210_wlan_init();
202
203 platform_add_devices(armlex4210_devices,
204 ARRAY_SIZE(armlex4210_devices));
205}
206
207MACHINE_START(ARMLEX4210, "ARMLEX4210")
208 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
209 .boot_params = S5P_PA_SDRAM + 0x100,
210 .init_irq = exynos4_init_irq,
211 .map_io = armlex4210_map_io,
212 .init_machine = armlex4210_machine_init,
213 .timer = &exynos4_timer,
214MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
new file mode 100644
index 000000000000..b79ad010d194
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -0,0 +1,305 @@
1/*
2 * linux/arch/arm/mach-exynos4/mach-nuri.c
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/serial_core.h>
13#include <linux/input.h>
14#include <linux/i2c.h>
15#include <linux/gpio_keys.h>
16#include <linux/gpio.h>
17#include <linux/regulator/machine.h>
18#include <linux/regulator/fixed.h>
19#include <linux/mmc/host.h>
20#include <linux/fb.h>
21#include <linux/pwm_backlight.h>
22
23#include <video/platform_lcd.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach-types.h>
27
28#include <plat/regs-serial.h>
29#include <plat/exynos4.h>
30#include <plat/cpu.h>
31#include <plat/devs.h>
32#include <plat/sdhci.h>
33
34#include <mach/map.h>
35
36/* Following are default values for UCON, ULCON and UFCON UART registers */
37#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
38 S3C2410_UCON_RXILEVEL | \
39 S3C2410_UCON_TXIRQMODE | \
40 S3C2410_UCON_RXIRQMODE | \
41 S3C2410_UCON_RXFIFO_TOI | \
42 S3C2443_UCON_RXERR_IRQEN)
43
44#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8
45
46#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
47 S5PV210_UFCON_TXTRIG256 | \
48 S5PV210_UFCON_RXTRIG256)
49
50enum fixed_regulator_id {
51 FIXED_REG_ID_MMC = 0,
52};
53
54static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
55 {
56 .hwport = 0,
57 .ucon = NURI_UCON_DEFAULT,
58 .ulcon = NURI_ULCON_DEFAULT,
59 .ufcon = NURI_UFCON_DEFAULT,
60 },
61 {
62 .hwport = 1,
63 .ucon = NURI_UCON_DEFAULT,
64 .ulcon = NURI_ULCON_DEFAULT,
65 .ufcon = NURI_UFCON_DEFAULT,
66 },
67 {
68 .hwport = 2,
69 .ucon = NURI_UCON_DEFAULT,
70 .ulcon = NURI_ULCON_DEFAULT,
71 .ufcon = NURI_UFCON_DEFAULT,
72 },
73 {
74 .hwport = 3,
75 .ucon = NURI_UCON_DEFAULT,
76 .ulcon = NURI_ULCON_DEFAULT,
77 .ufcon = NURI_UFCON_DEFAULT,
78 },
79};
80
81/* eMMC */
82static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
83 .max_width = 8,
84 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
85 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
86 MMC_CAP_DISABLE | MMC_CAP_ERASE),
87 .cd_type = S3C_SDHCI_CD_PERMANENT,
88 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
89};
90
91static struct regulator_consumer_supply emmc_supplies[] = {
92 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
93 REGULATOR_SUPPLY("vmmc", "dw_mmc"),
94};
95
96static struct regulator_init_data emmc_fixed_voltage_init_data = {
97 .constraints = {
98 .name = "VMEM_VDD_2.8V",
99 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
100 },
101 .num_consumer_supplies = ARRAY_SIZE(emmc_supplies),
102 .consumer_supplies = emmc_supplies,
103};
104
105static struct fixed_voltage_config emmc_fixed_voltage_config = {
106 .supply_name = "MASSMEMORY_EN (inverted)",
107 .microvolts = 2800000,
108 .gpio = EXYNOS4_GPL1(1),
109 .enable_high = false,
110 .init_data = &emmc_fixed_voltage_init_data,
111};
112
113static struct platform_device emmc_fixed_voltage = {
114 .name = "reg-fixed-voltage",
115 .id = FIXED_REG_ID_MMC,
116 .dev = {
117 .platform_data = &emmc_fixed_voltage_config,
118 },
119};
120
121/* SD */
122static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
123 .max_width = 4,
124 .host_caps = MMC_CAP_4_BIT_DATA |
125 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
126 MMC_CAP_DISABLE,
127 .ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
128 .ext_cd_gpio_invert = 1,
129 .cd_type = S3C_SDHCI_CD_GPIO,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133/* WLAN */
134static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
135 .max_width = 4,
136 .host_caps = MMC_CAP_4_BIT_DATA |
137 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
138 .cd_type = S3C_SDHCI_CD_EXTERNAL,
139 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
140};
141
142static void __init nuri_sdhci_init(void)
143{
144 s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
145 s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
146 s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
147}
148
149/* GPIO KEYS */
150static struct gpio_keys_button nuri_gpio_keys_tables[] = {
151 {
152 .code = KEY_VOLUMEUP,
153 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
154 .desc = "gpio-keys: KEY_VOLUMEUP",
155 .type = EV_KEY,
156 .active_low = 1,
157 .debounce_interval = 1,
158 }, {
159 .code = KEY_VOLUMEDOWN,
160 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
161 .desc = "gpio-keys: KEY_VOLUMEDOWN",
162 .type = EV_KEY,
163 .active_low = 1,
164 .debounce_interval = 1,
165 }, {
166 .code = KEY_POWER,
167 .gpio = EXYNOS4_GPX2(7), /* XEINT23 */
168 .desc = "gpio-keys: KEY_POWER",
169 .type = EV_KEY,
170 .active_low = 1,
171 .wakeup = 1,
172 .debounce_interval = 1,
173 },
174};
175
176static struct gpio_keys_platform_data nuri_gpio_keys_data = {
177 .buttons = nuri_gpio_keys_tables,
178 .nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables),
179};
180
181static struct platform_device nuri_gpio_keys = {
182 .name = "gpio-keys",
183 .dev = {
184 .platform_data = &nuri_gpio_keys_data,
185 },
186};
187
188static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
189{
190 int gpio = EXYNOS4_GPE1(5);
191
192 gpio_request(gpio, "LVDS_nSHDN");
193 gpio_direction_output(gpio, power);
194 gpio_free(gpio);
195}
196
197static int nuri_bl_init(struct device *dev)
198{
199 int ret, gpio = EXYNOS4_GPE2(3);
200
201 ret = gpio_request(gpio, "LCD_LDO_EN");
202 if (!ret)
203 gpio_direction_output(gpio, 0);
204
205 return ret;
206}
207
208static int nuri_bl_notify(struct device *dev, int brightness)
209{
210 if (brightness < 1)
211 brightness = 0;
212
213 gpio_set_value(EXYNOS4_GPE2(3), 1);
214
215 return brightness;
216}
217
218static void nuri_bl_exit(struct device *dev)
219{
220 gpio_free(EXYNOS4_GPE2(3));
221}
222
223/* nuri pwm backlight */
224static struct platform_pwm_backlight_data nuri_backlight_data = {
225 .pwm_id = 0,
226 .pwm_period_ns = 30000,
227 .max_brightness = 100,
228 .dft_brightness = 50,
229 .init = nuri_bl_init,
230 .notify = nuri_bl_notify,
231 .exit = nuri_bl_exit,
232};
233
234static struct platform_device nuri_backlight_device = {
235 .name = "pwm-backlight",
236 .id = -1,
237 .dev = {
238 .parent = &s3c_device_timer[0].dev,
239 .platform_data = &nuri_backlight_data,
240 },
241};
242
243static struct plat_lcd_data nuri_lcd_platform_data = {
244 .set_power = nuri_lcd_power_on,
245};
246
247static struct platform_device nuri_lcd_device = {
248 .name = "platform-lcd",
249 .id = -1,
250 .dev = {
251 .platform_data = &nuri_lcd_platform_data,
252 },
253};
254
255/* I2C1 */
256static struct i2c_board_info i2c1_devs[] __initdata = {
257 /* Gyro, To be updated */
258};
259
260/* GPIO I2C 5 (PMIC) */
261static struct i2c_board_info i2c5_devs[] __initdata = {
262 /* max8997, To be updated */
263};
264
265static struct platform_device *nuri_devices[] __initdata = {
266 /* Samsung Platform Devices */
267 &emmc_fixed_voltage,
268 &s3c_device_hsmmc0,
269 &s3c_device_hsmmc2,
270 &s3c_device_hsmmc3,
271 &s3c_device_wdt,
272 &s3c_device_timer[0],
273
274 /* NURI Devices */
275 &nuri_gpio_keys,
276 &nuri_lcd_device,
277 &nuri_backlight_device,
278};
279
280static void __init nuri_map_io(void)
281{
282 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
283 s3c24xx_init_clocks(24000000);
284 s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
285}
286
287static void __init nuri_machine_init(void)
288{
289 nuri_sdhci_init();
290
291 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
292 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
293
294 /* Last */
295 platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
296}
297
298MACHINE_START(NURI, "NURI")
299 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
300 .boot_params = S5P_PA_SDRAM + 0x100,
301 .init_irq = exynos4_init_irq,
302 .map_io = nuri_map_io,
303 .init_machine = nuri_machine_init,
304 .timer = &exynos4_timer,
305MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index d9cab02e23ca..25a256818122 100644
--- a/arch/arm/mach-s5pv310/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c 1/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +21,7 @@
21 21
22#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h> 23#include <plat/regs-srom.h>
24#include <plat/s5pv310.h> 24#include <plat/exynos4.h>
25#include <plat/cpu.h> 25#include <plat/cpu.h>
26#include <plat/devs.h> 26#include <plat/devs.h>
27#include <plat/sdhci.h> 27#include <plat/sdhci.h>
@@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
77 77
78static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = { 78static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO, 79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = S5PV310_GPK0(2), 80 .ext_cd_gpio = EXYNOS4_GPK0(2),
81 .ext_cd_gpio_invert = 1, 81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT 83#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
84 .max_width = 8, 84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA, 85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif 86#endif
@@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
88 88
89static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = { 89static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO, 90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = S5PV310_GPK0(2), 91 .ext_cd_gpio = EXYNOS4_GPK0(2),
92 .ext_cd_gpio_invert = 1, 92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94}; 94};
95 95
96static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = { 96static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO, 97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = S5PV310_GPK2(2), 98 .ext_cd_gpio = EXYNOS4_GPK2(2),
99 .ext_cd_gpio_invert = 1, 99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT 101#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102 .max_width = 8, 102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA, 103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif 104#endif
@@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
106 106
107static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = { 107static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO, 108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = S5PV310_GPK2(2), 109 .ext_cd_gpio = EXYNOS4_GPK2(2),
110 .ext_cd_gpio_invert = 1, 110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112}; 112};
113 113
114static struct resource smdkc210_smsc911x_resources[] = { 114static struct resource smdkc210_smsc911x_resources[] = {
115 [0] = { 115 [0] = {
116 .start = S5PV310_PA_SROM_BANK(1), 116 .start = EXYNOS4_PA_SROM_BANK(1),
117 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, 117 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
119 }, 119 },
120 [1] = { 120 [1] = {
@@ -154,16 +154,16 @@ static struct platform_device *smdkc210_devices[] __initdata = {
154 &s3c_device_i2c1, 154 &s3c_device_i2c1,
155 &s3c_device_rtc, 155 &s3c_device_rtc,
156 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97, 157 &exynos4_device_ac97,
158 &s5pv310_device_i2s0, 158 &exynos4_device_i2s0,
159 &s5pv310_device_pd[PD_MFC], 159 &exynos4_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D], 160 &exynos4_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0], 161 &exynos4_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1], 162 &exynos4_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM], 163 &exynos4_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV], 164 &exynos4_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS], 165 &exynos4_device_pd[PD_GPS],
166 &s5pv310_device_sysmmu, 166 &exynos4_device_sysmmu,
167 &samsung_asoc_dma, 167 &samsung_asoc_dma,
168 &smdkc210_smsc911x, 168 &smdkc210_smsc911x,
169}; 169};
@@ -216,8 +216,8 @@ static void __init smdkc210_machine_init(void)
216MACHINE_START(SMDKC210, "SMDKC210") 216MACHINE_START(SMDKC210, "SMDKC210")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 .boot_params = S5P_PA_SDRAM + 0x100, 218 .boot_params = S5P_PA_SDRAM + 0x100,
219 .init_irq = s5pv310_init_irq, 219 .init_irq = exynos4_init_irq,
220 .map_io = smdkc210_map_io, 220 .map_io = smdkc210_map_io,
221 .init_machine = smdkc210_machine_init, 221 .init_machine = smdkc210_machine_init,
222 .timer = &s5pv310_timer, 222 .timer = &exynos4_timer,
223MACHINE_END 223MACHINE_END
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index b1cddbf3c616..07860a5b2f5d 100644
--- a/arch/arm/mach-s5pv310/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c 1/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -21,7 +21,7 @@
21 21
22#include <plat/regs-serial.h> 22#include <plat/regs-serial.h>
23#include <plat/regs-srom.h> 23#include <plat/regs-srom.h>
24#include <plat/s5pv310.h> 24#include <plat/exynos4.h>
25#include <plat/cpu.h> 25#include <plat/cpu.h>
26#include <plat/devs.h> 26#include <plat/devs.h>
27#include <plat/sdhci.h> 27#include <plat/sdhci.h>
@@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
77 77
78static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = { 78static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
79 .cd_type = S3C_SDHCI_CD_GPIO, 79 .cd_type = S3C_SDHCI_CD_GPIO,
80 .ext_cd_gpio = S5PV310_GPK0(2), 80 .ext_cd_gpio = EXYNOS4_GPK0(2),
81 .ext_cd_gpio_invert = 1, 81 .ext_cd_gpio_invert = 1,
82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 82 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
83#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT 83#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
84 .max_width = 8, 84 .max_width = 8,
85 .host_caps = MMC_CAP_8_BIT_DATA, 85 .host_caps = MMC_CAP_8_BIT_DATA,
86#endif 86#endif
@@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
88 88
89static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = { 89static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
90 .cd_type = S3C_SDHCI_CD_GPIO, 90 .cd_type = S3C_SDHCI_CD_GPIO,
91 .ext_cd_gpio = S5PV310_GPK0(2), 91 .ext_cd_gpio = EXYNOS4_GPK0(2),
92 .ext_cd_gpio_invert = 1, 92 .ext_cd_gpio_invert = 1,
93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 93 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
94}; 94};
95 95
96static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = { 96static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
97 .cd_type = S3C_SDHCI_CD_GPIO, 97 .cd_type = S3C_SDHCI_CD_GPIO,
98 .ext_cd_gpio = S5PV310_GPK2(2), 98 .ext_cd_gpio = EXYNOS4_GPK2(2),
99 .ext_cd_gpio_invert = 1, 99 .ext_cd_gpio_invert = 1,
100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 100 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
101#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT 101#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
102 .max_width = 8, 102 .max_width = 8,
103 .host_caps = MMC_CAP_8_BIT_DATA, 103 .host_caps = MMC_CAP_8_BIT_DATA,
104#endif 104#endif
@@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
106 106
107static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = { 107static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
108 .cd_type = S3C_SDHCI_CD_GPIO, 108 .cd_type = S3C_SDHCI_CD_GPIO,
109 .ext_cd_gpio = S5PV310_GPK2(2), 109 .ext_cd_gpio = EXYNOS4_GPK2(2),
110 .ext_cd_gpio_invert = 1, 110 .ext_cd_gpio_invert = 1,
111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, 111 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
112}; 112};
113 113
114static struct resource smdkv310_smsc911x_resources[] = { 114static struct resource smdkv310_smsc911x_resources[] = {
115 [0] = { 115 [0] = {
116 .start = S5PV310_PA_SROM_BANK(1), 116 .start = EXYNOS4_PA_SROM_BANK(1),
117 .end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1, 117 .end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
118 .flags = IORESOURCE_MEM, 118 .flags = IORESOURCE_MEM,
119 }, 119 },
120 [1] = { 120 [1] = {
@@ -154,16 +154,16 @@ static struct platform_device *smdkv310_devices[] __initdata = {
154 &s3c_device_i2c1, 154 &s3c_device_i2c1,
155 &s3c_device_rtc, 155 &s3c_device_rtc,
156 &s3c_device_wdt, 156 &s3c_device_wdt,
157 &s5pv310_device_ac97, 157 &exynos4_device_ac97,
158 &s5pv310_device_i2s0, 158 &exynos4_device_i2s0,
159 &s5pv310_device_pd[PD_MFC], 159 &exynos4_device_pd[PD_MFC],
160 &s5pv310_device_pd[PD_G3D], 160 &exynos4_device_pd[PD_G3D],
161 &s5pv310_device_pd[PD_LCD0], 161 &exynos4_device_pd[PD_LCD0],
162 &s5pv310_device_pd[PD_LCD1], 162 &exynos4_device_pd[PD_LCD1],
163 &s5pv310_device_pd[PD_CAM], 163 &exynos4_device_pd[PD_CAM],
164 &s5pv310_device_pd[PD_TV], 164 &exynos4_device_pd[PD_TV],
165 &s5pv310_device_pd[PD_GPS], 165 &exynos4_device_pd[PD_GPS],
166 &s5pv310_device_sysmmu, 166 &exynos4_device_sysmmu,
167 &samsung_asoc_dma, 167 &samsung_asoc_dma,
168 &smdkv310_smsc911x, 168 &smdkv310_smsc911x,
169}; 169};
@@ -217,8 +217,8 @@ MACHINE_START(SMDKV310, "SMDKV310")
217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 217 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
218 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ 218 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
219 .boot_params = S5P_PA_SDRAM + 0x100, 219 .boot_params = S5P_PA_SDRAM + 0x100,
220 .init_irq = s5pv310_init_irq, 220 .init_irq = exynos4_init_irq,
221 .map_io = smdkv310_map_io, 221 .map_io = smdkv310_map_io,
222 .init_machine = smdkv310_machine_init, 222 .init_machine = smdkv310_machine_init,
223 .timer = &s5pv310_timer, 223 .timer = &exynos4_timer,
224MACHINE_END 224MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
new file mode 100644
index 000000000000..97d329fff2cf
--- /dev/null
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -0,0 +1,650 @@
1/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/mfd/max8998.h>
17#include <linux/regulator/machine.h>
18#include <linux/regulator/fixed.h>
19#include <linux/regulator/max8952.h>
20#include <linux/mmc/host.h>
21
22#include <asm/mach/arch.h>
23#include <asm/mach-types.h>
24
25#include <plat/regs-serial.h>
26#include <plat/exynos4.h>
27#include <plat/cpu.h>
28#include <plat/devs.h>
29#include <plat/iic.h>
30#include <plat/sdhci.h>
31
32#include <mach/map.h>
33
34/* Following are default values for UCON, ULCON and UFCON UART registers */
35#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
36 S3C2410_UCON_RXILEVEL | \
37 S3C2410_UCON_TXIRQMODE | \
38 S3C2410_UCON_RXIRQMODE | \
39 S3C2410_UCON_RXFIFO_TOI | \
40 S3C2443_UCON_RXERR_IRQEN)
41
42#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
43
44#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
45 S5PV210_UFCON_TXTRIG256 | \
46 S5PV210_UFCON_RXTRIG256)
47
48static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
49 [0] = {
50 .hwport = 0,
51 .ucon = UNIVERSAL_UCON_DEFAULT,
52 .ulcon = UNIVERSAL_ULCON_DEFAULT,
53 .ufcon = UNIVERSAL_UFCON_DEFAULT,
54 },
55 [1] = {
56 .hwport = 1,
57 .ucon = UNIVERSAL_UCON_DEFAULT,
58 .ulcon = UNIVERSAL_ULCON_DEFAULT,
59 .ufcon = UNIVERSAL_UFCON_DEFAULT,
60 },
61 [2] = {
62 .hwport = 2,
63 .ucon = UNIVERSAL_UCON_DEFAULT,
64 .ulcon = UNIVERSAL_ULCON_DEFAULT,
65 .ufcon = UNIVERSAL_UFCON_DEFAULT,
66 },
67 [3] = {
68 .hwport = 3,
69 .ucon = UNIVERSAL_UCON_DEFAULT,
70 .ulcon = UNIVERSAL_ULCON_DEFAULT,
71 .ufcon = UNIVERSAL_UFCON_DEFAULT,
72 },
73};
74
75static struct regulator_consumer_supply max8952_consumer =
76 REGULATOR_SUPPLY("vddarm", NULL);
77
78static struct max8952_platform_data universal_max8952_pdata __initdata = {
79 .gpio_vid0 = EXYNOS4_GPX0(3),
80 .gpio_vid1 = EXYNOS4_GPX0(4),
81 .gpio_en = -1, /* Not controllable, set "Always High" */
82 .default_mode = 0, /* vid0 = 0, vid1 = 0 */
83 .dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
84 .sync_freq = 0, /* default: fastest */
85 .ramp_speed = 0, /* default: fastest */
86
87 .reg_data = {
88 .constraints = {
89 .name = "VARM_1.2V",
90 .min_uV = 770000,
91 .max_uV = 1400000,
92 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
93 .always_on = 1,
94 .boot_on = 1,
95 },
96 .num_consumer_supplies = 1,
97 .consumer_supplies = &max8952_consumer,
98 },
99};
100
101static struct regulator_consumer_supply lp3974_buck1_consumer =
102 REGULATOR_SUPPLY("vddint", NULL);
103
104static struct regulator_consumer_supply lp3974_buck2_consumer =
105 REGULATOR_SUPPLY("vddg3d", NULL);
106
107static struct regulator_init_data lp3974_buck1_data = {
108 .constraints = {
109 .name = "VINT_1.1V",
110 .min_uV = 750000,
111 .max_uV = 1500000,
112 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
113 REGULATOR_CHANGE_STATUS,
114 .boot_on = 1,
115 .state_mem = {
116 .disabled = 1,
117 },
118 },
119 .num_consumer_supplies = 1,
120 .consumer_supplies = &lp3974_buck1_consumer,
121};
122
123static struct regulator_init_data lp3974_buck2_data = {
124 .constraints = {
125 .name = "VG3D_1.1V",
126 .min_uV = 750000,
127 .max_uV = 1500000,
128 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
129 REGULATOR_CHANGE_STATUS,
130 .boot_on = 1,
131 .state_mem = {
132 .disabled = 1,
133 },
134 },
135 .num_consumer_supplies = 1,
136 .consumer_supplies = &lp3974_buck2_consumer,
137};
138
139static struct regulator_init_data lp3974_buck3_data = {
140 .constraints = {
141 .name = "VCC_1.8V",
142 .min_uV = 1800000,
143 .max_uV = 1800000,
144 .apply_uV = 1,
145 .always_on = 1,
146 .state_mem = {
147 .enabled = 1,
148 },
149 },
150};
151
152static struct regulator_init_data lp3974_buck4_data = {
153 .constraints = {
154 .name = "VMEM_1.2V",
155 .min_uV = 1200000,
156 .max_uV = 1200000,
157 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
158 .apply_uV = 1,
159 .state_mem = {
160 .disabled = 1,
161 },
162 },
163};
164
165static struct regulator_init_data lp3974_ldo2_data = {
166 .constraints = {
167 .name = "VALIVE_1.2V",
168 .min_uV = 1200000,
169 .max_uV = 1200000,
170 .apply_uV = 1,
171 .always_on = 1,
172 .state_mem = {
173 .enabled = 1,
174 },
175 },
176};
177
178static struct regulator_init_data lp3974_ldo3_data = {
179 .constraints = {
180 .name = "VUSB+MIPI_1.1V",
181 .min_uV = 1100000,
182 .max_uV = 1100000,
183 .apply_uV = 1,
184 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
185 .state_mem = {
186 .disabled = 1,
187 },
188 },
189};
190
191static struct regulator_init_data lp3974_ldo4_data = {
192 .constraints = {
193 .name = "VADC_3.3V",
194 .min_uV = 3300000,
195 .max_uV = 3300000,
196 .apply_uV = 1,
197 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
198 .state_mem = {
199 .disabled = 1,
200 },
201 },
202};
203
204static struct regulator_init_data lp3974_ldo5_data = {
205 .constraints = {
206 .name = "VTF_2.8V",
207 .min_uV = 2800000,
208 .max_uV = 2800000,
209 .apply_uV = 1,
210 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
211 .state_mem = {
212 .disabled = 1,
213 },
214 },
215};
216
217static struct regulator_init_data lp3974_ldo6_data = {
218 .constraints = {
219 .name = "LDO6",
220 .min_uV = 2000000,
221 .max_uV = 2000000,
222 .apply_uV = 1,
223 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
224 .state_mem = {
225 .disabled = 1,
226 },
227 },
228};
229
230static struct regulator_init_data lp3974_ldo7_data = {
231 .constraints = {
232 .name = "VLCD+VMIPI_1.8V",
233 .min_uV = 1800000,
234 .max_uV = 1800000,
235 .apply_uV = 1,
236 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
237 .state_mem = {
238 .disabled = 1,
239 },
240 },
241};
242
243static struct regulator_init_data lp3974_ldo8_data = {
244 .constraints = {
245 .name = "VUSB+VDAC_3.3V",
246 .min_uV = 3300000,
247 .max_uV = 3300000,
248 .apply_uV = 1,
249 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
250 .state_mem = {
251 .disabled = 1,
252 },
253 },
254};
255
256static struct regulator_init_data lp3974_ldo9_data = {
257 .constraints = {
258 .name = "VCC_2.8V",
259 .min_uV = 2800000,
260 .max_uV = 2800000,
261 .apply_uV = 1,
262 .always_on = 1,
263 .state_mem = {
264 .enabled = 1,
265 },
266 },
267};
268
269static struct regulator_init_data lp3974_ldo10_data = {
270 .constraints = {
271 .name = "VPLL_1.1V",
272 .min_uV = 1100000,
273 .max_uV = 1100000,
274 .boot_on = 1,
275 .apply_uV = 1,
276 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
277 .state_mem = {
278 .disabled = 1,
279 },
280 },
281};
282
283static struct regulator_init_data lp3974_ldo11_data = {
284 .constraints = {
285 .name = "CAM_AF_3.3V",
286 .min_uV = 3300000,
287 .max_uV = 3300000,
288 .apply_uV = 1,
289 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
290 .state_mem = {
291 .disabled = 1,
292 },
293 },
294};
295
296static struct regulator_init_data lp3974_ldo12_data = {
297 .constraints = {
298 .name = "PS_2.8V",
299 .min_uV = 2800000,
300 .max_uV = 2800000,
301 .apply_uV = 1,
302 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
303 .state_mem = {
304 .disabled = 1,
305 },
306 },
307};
308
309static struct regulator_init_data lp3974_ldo13_data = {
310 .constraints = {
311 .name = "VHIC_1.2V",
312 .min_uV = 1200000,
313 .max_uV = 1200000,
314 .apply_uV = 1,
315 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
316 .state_mem = {
317 .disabled = 1,
318 },
319 },
320};
321
322static struct regulator_init_data lp3974_ldo14_data = {
323 .constraints = {
324 .name = "CAM_I_HOST_1.8V",
325 .min_uV = 1800000,
326 .max_uV = 1800000,
327 .apply_uV = 1,
328 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
329 .state_mem = {
330 .disabled = 1,
331 },
332 },
333};
334
335static struct regulator_init_data lp3974_ldo15_data = {
336 .constraints = {
337 .name = "CAM_S_DIG+FM33_CORE_1.2V",
338 .min_uV = 1200000,
339 .max_uV = 1200000,
340 .apply_uV = 1,
341 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
342 .state_mem = {
343 .disabled = 1,
344 },
345 },
346};
347
348static struct regulator_init_data lp3974_ldo16_data = {
349 .constraints = {
350 .name = "CAM_S_ANA_2.8V",
351 .min_uV = 2800000,
352 .max_uV = 2800000,
353 .apply_uV = 1,
354 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
355 .state_mem = {
356 .disabled = 1,
357 },
358 },
359};
360
361static struct regulator_init_data lp3974_ldo17_data = {
362 .constraints = {
363 .name = "VCC_3.0V_LCD",
364 .min_uV = 3000000,
365 .max_uV = 3000000,
366 .apply_uV = 1,
367 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
368 .boot_on = 1,
369 .state_mem = {
370 .disabled = 1,
371 },
372 },
373};
374
375static struct regulator_init_data lp3974_32khz_ap_data = {
376 .constraints = {
377 .name = "32KHz AP",
378 .always_on = 1,
379 .state_mem = {
380 .enabled = 1,
381 },
382 },
383};
384
385static struct regulator_init_data lp3974_32khz_cp_data = {
386 .constraints = {
387 .name = "32KHz CP",
388 .state_mem = {
389 .disabled = 1,
390 },
391 },
392};
393
394static struct regulator_init_data lp3974_vichg_data = {
395 .constraints = {
396 .name = "VICHG",
397 .state_mem = {
398 .disabled = 1,
399 },
400 },
401};
402
403static struct regulator_init_data lp3974_esafeout1_data = {
404 .constraints = {
405 .name = "SAFEOUT1",
406 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
407 .state_mem = {
408 .enabled = 1,
409 },
410 },
411};
412
413static struct regulator_init_data lp3974_esafeout2_data = {
414 .constraints = {
415 .name = "SAFEOUT2",
416 .boot_on = 1,
417 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
418 .state_mem = {
419 .enabled = 1,
420 },
421 },
422};
423
424static struct max8998_regulator_data lp3974_regulators[] = {
425 { MAX8998_LDO2, &lp3974_ldo2_data },
426 { MAX8998_LDO3, &lp3974_ldo3_data },
427 { MAX8998_LDO4, &lp3974_ldo4_data },
428 { MAX8998_LDO5, &lp3974_ldo5_data },
429 { MAX8998_LDO6, &lp3974_ldo6_data },
430 { MAX8998_LDO7, &lp3974_ldo7_data },
431 { MAX8998_LDO8, &lp3974_ldo8_data },
432 { MAX8998_LDO9, &lp3974_ldo9_data },
433 { MAX8998_LDO10, &lp3974_ldo10_data },
434 { MAX8998_LDO11, &lp3974_ldo11_data },
435 { MAX8998_LDO12, &lp3974_ldo12_data },
436 { MAX8998_LDO13, &lp3974_ldo13_data },
437 { MAX8998_LDO14, &lp3974_ldo14_data },
438 { MAX8998_LDO15, &lp3974_ldo15_data },
439 { MAX8998_LDO16, &lp3974_ldo16_data },
440 { MAX8998_LDO17, &lp3974_ldo17_data },
441 { MAX8998_BUCK1, &lp3974_buck1_data },
442 { MAX8998_BUCK2, &lp3974_buck2_data },
443 { MAX8998_BUCK3, &lp3974_buck3_data },
444 { MAX8998_BUCK4, &lp3974_buck4_data },
445 { MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
446 { MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
447 { MAX8998_ENVICHG, &lp3974_vichg_data },
448 { MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
449 { MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
450};
451
452static struct max8998_platform_data universal_lp3974_pdata = {
453 .num_regulators = ARRAY_SIZE(lp3974_regulators),
454 .regulators = lp3974_regulators,
455 .buck1_voltage1 = 1100000, /* INT */
456 .buck1_voltage2 = 1000000,
457 .buck1_voltage3 = 1100000,
458 .buck1_voltage4 = 1000000,
459 .buck1_set1 = EXYNOS4_GPX0(5),
460 .buck1_set2 = EXYNOS4_GPX0(6),
461 .buck2_voltage1 = 1200000, /* G3D */
462 .buck2_voltage2 = 1100000,
463 .buck1_default_idx = 0,
464 .buck2_set3 = EXYNOS4_GPE2(0),
465 .buck2_default_idx = 0,
466 .wakeup = true,
467};
468
469/* GPIO I2C 5 (PMIC) */
470static struct i2c_board_info i2c5_devs[] __initdata = {
471 {
472 I2C_BOARD_INFO("max8952", 0xC0 >> 1),
473 .platform_data = &universal_max8952_pdata,
474 }, {
475 I2C_BOARD_INFO("lp3974", 0xCC >> 1),
476 .platform_data = &universal_lp3974_pdata,
477 },
478};
479
480/* GPIO KEYS */
481static struct gpio_keys_button universal_gpio_keys_tables[] = {
482 {
483 .code = KEY_VOLUMEUP,
484 .gpio = EXYNOS4_GPX2(0), /* XEINT16 */
485 .desc = "gpio-keys: KEY_VOLUMEUP",
486 .type = EV_KEY,
487 .active_low = 1,
488 .debounce_interval = 1,
489 }, {
490 .code = KEY_VOLUMEDOWN,
491 .gpio = EXYNOS4_GPX2(1), /* XEINT17 */
492 .desc = "gpio-keys: KEY_VOLUMEDOWN",
493 .type = EV_KEY,
494 .active_low = 1,
495 .debounce_interval = 1,
496 }, {
497 .code = KEY_CONFIG,
498 .gpio = EXYNOS4_GPX2(2), /* XEINT18 */
499 .desc = "gpio-keys: KEY_CONFIG",
500 .type = EV_KEY,
501 .active_low = 1,
502 .debounce_interval = 1,
503 }, {
504 .code = KEY_CAMERA,
505 .gpio = EXYNOS4_GPX2(3), /* XEINT19 */
506 .desc = "gpio-keys: KEY_CAMERA",
507 .type = EV_KEY,
508 .active_low = 1,
509 .debounce_interval = 1,
510 }, {
511 .code = KEY_OK,
512 .gpio = EXYNOS4_GPX3(5), /* XEINT29 */
513 .desc = "gpio-keys: KEY_OK",
514 .type = EV_KEY,
515 .active_low = 1,
516 .debounce_interval = 1,
517 },
518};
519
520static struct gpio_keys_platform_data universal_gpio_keys_data = {
521 .buttons = universal_gpio_keys_tables,
522 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
523};
524
525static struct platform_device universal_gpio_keys = {
526 .name = "gpio-keys",
527 .dev = {
528 .platform_data = &universal_gpio_keys_data,
529 },
530};
531
532/* eMMC */
533static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
534 .max_width = 8,
535 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
536 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
537 MMC_CAP_DISABLE),
538 .cd_type = S3C_SDHCI_CD_PERMANENT,
539 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
540};
541
542static struct regulator_consumer_supply mmc0_supplies[] = {
543 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
544};
545
546static struct regulator_init_data mmc0_fixed_voltage_init_data = {
547 .constraints = {
548 .name = "VMEM_VDD_2.8V",
549 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
550 },
551 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
552 .consumer_supplies = mmc0_supplies,
553};
554
555static struct fixed_voltage_config mmc0_fixed_voltage_config = {
556 .supply_name = "MASSMEMORY_EN",
557 .microvolts = 2800000,
558 .gpio = EXYNOS4_GPE1(3),
559 .enable_high = true,
560 .init_data = &mmc0_fixed_voltage_init_data,
561};
562
563static struct platform_device mmc0_fixed_voltage = {
564 .name = "reg-fixed-voltage",
565 .id = 0,
566 .dev = {
567 .platform_data = &mmc0_fixed_voltage_config,
568 },
569};
570
571/* SD */
572static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
573 .max_width = 4,
574 .host_caps = MMC_CAP_4_BIT_DATA |
575 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
576 MMC_CAP_DISABLE,
577 .ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
578 .ext_cd_gpio_invert = 1,
579 .cd_type = S3C_SDHCI_CD_GPIO,
580 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
581};
582
583/* WiFi */
584static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
585 .max_width = 4,
586 .host_caps = MMC_CAP_4_BIT_DATA |
587 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
588 MMC_CAP_DISABLE,
589 .cd_type = S3C_SDHCI_CD_EXTERNAL,
590};
591
592static void __init universal_sdhci_init(void)
593{
594 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
595 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
596 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
597}
598
599/* I2C0 */
600static struct i2c_board_info i2c0_devs[] __initdata = {
601 /* Camera, To be updated */
602};
603
604/* I2C1 */
605static struct i2c_board_info i2c1_devs[] __initdata = {
606 /* Gyro, To be updated */
607};
608
609static struct platform_device *universal_devices[] __initdata = {
610 /* Samsung Platform Devices */
611 &mmc0_fixed_voltage,
612 &s3c_device_hsmmc0,
613 &s3c_device_hsmmc2,
614 &s3c_device_hsmmc3,
615 &s3c_device_i2c5,
616
617 /* Universal Devices */
618 &universal_gpio_keys,
619 &s5p_device_onenand,
620};
621
622static void __init universal_map_io(void)
623{
624 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
625 s3c24xx_init_clocks(24000000);
626 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
627}
628
629static void __init universal_machine_init(void)
630{
631 universal_sdhci_init();
632
633 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
634 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
635
636 s3c_i2c5_set_platdata(NULL);
637 i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
638
639 /* Last */
640 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
641}
642
643MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
644 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
645 .boot_params = S5P_PA_SDRAM + 0x100,
646 .init_irq = exynos4_init_irq,
647 .map_io = universal_map_io,
648 .init_machine = universal_machine_init,
649 .timer = &exynos4_timer,
650MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
new file mode 100644
index 000000000000..af82a8fbb68b
--- /dev/null
+++ b/arch/arm/mach-exynos4/mct.c
@@ -0,0 +1,421 @@
1/* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/sched.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/clockchips.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/percpu.h>
22
23#include <mach/map.h>
24#include <mach/regs-mct.h>
25#include <asm/mach/time.h>
26
27static unsigned long clk_cnt_per_tick;
28static unsigned long clk_rate;
29
30struct mct_clock_event_device {
31 struct clock_event_device *evt;
32 void __iomem *base;
33};
34
35struct mct_clock_event_device mct_tick[2];
36
37static void exynos4_mct_write(unsigned int value, void *addr)
38{
39 void __iomem *stat_addr;
40 u32 mask;
41 u32 i;
42
43 __raw_writel(value, addr);
44
45 switch ((u32) addr) {
46 case (u32) EXYNOS4_MCT_G_TCON:
47 stat_addr = EXYNOS4_MCT_G_WSTAT;
48 mask = 1 << 16; /* G_TCON write status */
49 break;
50 case (u32) EXYNOS4_MCT_G_COMP0_L:
51 stat_addr = EXYNOS4_MCT_G_WSTAT;
52 mask = 1 << 0; /* G_COMP0_L write status */
53 break;
54 case (u32) EXYNOS4_MCT_G_COMP0_U:
55 stat_addr = EXYNOS4_MCT_G_WSTAT;
56 mask = 1 << 1; /* G_COMP0_U write status */
57 break;
58 case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
59 stat_addr = EXYNOS4_MCT_G_WSTAT;
60 mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
61 break;
62 case (u32) EXYNOS4_MCT_G_CNT_L:
63 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
64 mask = 1 << 0; /* G_CNT_L write status */
65 break;
66 case (u32) EXYNOS4_MCT_G_CNT_U:
67 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
68 mask = 1 << 1; /* G_CNT_U write status */
69 break;
70 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
71 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
72 mask = 1 << 3; /* L0_TCON write status */
73 break;
74 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
75 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
76 mask = 1 << 3; /* L1_TCON write status */
77 break;
78 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
79 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
80 mask = 1 << 0; /* L0_TCNTB write status */
81 break;
82 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
83 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
84 mask = 1 << 0; /* L1_TCNTB write status */
85 break;
86 case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
87 stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
88 mask = 1 << 1; /* L0_ICNTB write status */
89 break;
90 case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
91 stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
92 mask = 1 << 1; /* L1_ICNTB write status */
93 break;
94 default:
95 return;
96 }
97
98 /* Wait maximum 1 ms until written values are applied */
99 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
100 if (__raw_readl(stat_addr) & mask) {
101 __raw_writel(mask, stat_addr);
102 return;
103 }
104
105 panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
106}
107
108/* Clocksource handling */
109static void exynos4_mct_frc_start(u32 hi, u32 lo)
110{
111 u32 reg;
112
113 exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
114 exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
115
116 reg = __raw_readl(EXYNOS4_MCT_G_TCON);
117 reg |= MCT_G_TCON_START;
118 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
119}
120
121static cycle_t exynos4_frc_read(struct clocksource *cs)
122{
123 unsigned int lo, hi;
124 u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
125
126 do {
127 hi = hi2;
128 lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
129 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
130 } while (hi != hi2);
131
132 return ((cycle_t)hi << 32) | lo;
133}
134
135struct clocksource mct_frc = {
136 .name = "mct-frc",
137 .rating = 400,
138 .read = exynos4_frc_read,
139 .mask = CLOCKSOURCE_MASK(64),
140 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
141};
142
143static void __init exynos4_clocksource_init(void)
144{
145 exynos4_mct_frc_start(0, 0);
146
147 if (clocksource_register_hz(&mct_frc, clk_rate))
148 panic("%s: can't register clocksource\n", mct_frc.name);
149}
150
151static void exynos4_mct_comp0_stop(void)
152{
153 unsigned int tcon;
154
155 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
156 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
157
158 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
159 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
160}
161
162static void exynos4_mct_comp0_start(enum clock_event_mode mode,
163 unsigned long cycles)
164{
165 unsigned int tcon;
166 cycle_t comp_cycle;
167
168 tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
169
170 if (mode == CLOCK_EVT_MODE_PERIODIC) {
171 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
172 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
173 }
174
175 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
176 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
177 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
178
179 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
180
181 tcon |= MCT_G_TCON_COMP0_ENABLE;
182 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
183}
184
185static int exynos4_comp_set_next_event(unsigned long cycles,
186 struct clock_event_device *evt)
187{
188 exynos4_mct_comp0_start(evt->mode, cycles);
189
190 return 0;
191}
192
193static void exynos4_comp_set_mode(enum clock_event_mode mode,
194 struct clock_event_device *evt)
195{
196 exynos4_mct_comp0_stop();
197
198 switch (mode) {
199 case CLOCK_EVT_MODE_PERIODIC:
200 exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
201 break;
202
203 case CLOCK_EVT_MODE_ONESHOT:
204 case CLOCK_EVT_MODE_UNUSED:
205 case CLOCK_EVT_MODE_SHUTDOWN:
206 case CLOCK_EVT_MODE_RESUME:
207 break;
208 }
209}
210
211static struct clock_event_device mct_comp_device = {
212 .name = "mct-comp",
213 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
214 .rating = 250,
215 .set_next_event = exynos4_comp_set_next_event,
216 .set_mode = exynos4_comp_set_mode,
217};
218
219static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
220{
221 struct clock_event_device *evt = dev_id;
222
223 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
224
225 evt->event_handler(evt);
226
227 return IRQ_HANDLED;
228}
229
230static struct irqaction mct_comp_event_irq = {
231 .name = "mct_comp_irq",
232 .flags = IRQF_TIMER | IRQF_IRQPOLL,
233 .handler = exynos4_mct_comp_isr,
234 .dev_id = &mct_comp_device,
235};
236
237static void exynos4_clockevent_init(void)
238{
239 clk_cnt_per_tick = clk_rate / 2 / HZ;
240
241 clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
242 mct_comp_device.max_delta_ns =
243 clockevent_delta2ns(0xffffffff, &mct_comp_device);
244 mct_comp_device.min_delta_ns =
245 clockevent_delta2ns(0xf, &mct_comp_device);
246 mct_comp_device.cpumask = cpumask_of(0);
247 clockevents_register_device(&mct_comp_device);
248
249 setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
250}
251
252#ifdef CONFIG_LOCAL_TIMERS
253/* Clock event handling */
254static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
255{
256 unsigned long tmp;
257 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
258 void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
259
260 tmp = __raw_readl(addr);
261 if (tmp & mask) {
262 tmp &= ~mask;
263 exynos4_mct_write(tmp, addr);
264 }
265}
266
267static void exynos4_mct_tick_start(unsigned long cycles,
268 struct mct_clock_event_device *mevt)
269{
270 unsigned long tmp;
271
272 exynos4_mct_tick_stop(mevt);
273
274 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
275
276 /* update interrupt count buffer */
277 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
278
279 /* enable MCT tick interupt */
280 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
281
282 tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
283 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
284 MCT_L_TCON_INTERVAL_MODE;
285 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
286}
287
288static int exynos4_tick_set_next_event(unsigned long cycles,
289 struct clock_event_device *evt)
290{
291 struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
292
293 exynos4_mct_tick_start(cycles, mevt);
294
295 return 0;
296}
297
298static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
299 struct clock_event_device *evt)
300{
301 struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
302
303 exynos4_mct_tick_stop(mevt);
304
305 switch (mode) {
306 case CLOCK_EVT_MODE_PERIODIC:
307 exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
308 break;
309
310 case CLOCK_EVT_MODE_ONESHOT:
311 case CLOCK_EVT_MODE_UNUSED:
312 case CLOCK_EVT_MODE_SHUTDOWN:
313 case CLOCK_EVT_MODE_RESUME:
314 break;
315 }
316}
317
318static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
319{
320 struct mct_clock_event_device *mevt = dev_id;
321 struct clock_event_device *evt = mevt->evt;
322
323 /*
324 * This is for supporting oneshot mode.
325 * Mct would generate interrupt periodically
326 * without explicit stopping.
327 */
328 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
329 exynos4_mct_tick_stop(mevt);
330
331 /* Clear the MCT tick interrupt */
332 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
333
334 evt->event_handler(evt);
335
336 return IRQ_HANDLED;
337}
338
339static struct irqaction mct_tick0_event_irq = {
340 .name = "mct_tick0_irq",
341 .flags = IRQF_TIMER | IRQF_NOBALANCING,
342 .handler = exynos4_mct_tick_isr,
343};
344
345static struct irqaction mct_tick1_event_irq = {
346 .name = "mct_tick1_irq",
347 .flags = IRQF_TIMER | IRQF_NOBALANCING,
348 .handler = exynos4_mct_tick_isr,
349};
350
351static void exynos4_mct_tick_init(struct clock_event_device *evt)
352{
353 unsigned int cpu = smp_processor_id();
354
355 mct_tick[cpu].evt = evt;
356
357 if (cpu == 0) {
358 mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
359 evt->name = "mct_tick0";
360 } else {
361 mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
362 evt->name = "mct_tick1";
363 }
364
365 evt->cpumask = cpumask_of(cpu);
366 evt->set_next_event = exynos4_tick_set_next_event;
367 evt->set_mode = exynos4_tick_set_mode;
368 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
369 evt->rating = 450;
370
371 clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
372 evt->max_delta_ns =
373 clockevent_delta2ns(0x7fffffff, evt);
374 evt->min_delta_ns =
375 clockevent_delta2ns(0xf, evt);
376
377 clockevents_register_device(evt);
378
379 exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
380
381 if (cpu == 0) {
382 mct_tick0_event_irq.dev_id = &mct_tick[cpu];
383 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
384 } else {
385 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
386 irq_set_affinity(IRQ_MCT1, cpumask_of(1));
387 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
388 }
389}
390
391/* Setup the local clock events for a CPU */
392void __cpuinit local_timer_setup(struct clock_event_device *evt)
393{
394 exynos4_mct_tick_init(evt);
395}
396
397int local_timer_ack(void)
398{
399 return 0;
400}
401
402#endif /* CONFIG_LOCAL_TIMERS */
403
404static void __init exynos4_timer_resources(void)
405{
406 struct clk *mct_clk;
407 mct_clk = clk_get(NULL, "xtal");
408
409 clk_rate = clk_get_rate(mct_clk);
410}
411
412static void __init exynos4_timer_init(void)
413{
414 exynos4_timer_resources();
415 exynos4_clocksource_init();
416 exynos4_clockevent_init();
417}
418
419struct sys_timer exynos4_timer = {
420 .init = exynos4_timer_init,
421};
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 34093b069f67..6d35878ec1aa 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/mach-s5pv310/platsmp.c 1/* linux/arch/arm/mach-exynos4/platsmp.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c 6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * 7 *
@@ -28,7 +28,7 @@
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <mach/regs-clock.h> 29#include <mach/regs-clock.h>
30 30
31extern void s5pv310_secondary_startup(void); 31extern void exynos4_secondary_startup(void);
32 32
33/* 33/*
34 * control for which core is the next to come out of the secondary 34 * control for which core is the next to come out of the secondary
@@ -139,7 +139,7 @@ void __init smp_init_cpus(void)
139 /* sanity check */ 139 /* sanity check */
140 if (ncores > NR_CPUS) { 140 if (ncores > NR_CPUS) {
141 printk(KERN_WARNING 141 printk(KERN_WARNING
142 "S5PV310: no. of cores (%d) greater than configured " 142 "EXYNOS4: no. of cores (%d) greater than configured "
143 "maximum of %d - clipping\n", 143 "maximum of %d - clipping\n",
144 ncores, NR_CPUS); 144 ncores, NR_CPUS);
145 ncores = NR_CPUS; 145 ncores = NR_CPUS;
@@ -168,5 +168,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
168 * until it receives a soft interrupt, and then the 168 * until it receives a soft interrupt, and then the
169 * secondary CPU branches to this address. 169 * secondary CPU branches to this address.
170 */ 170 */
171 __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM); 171 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
172} 172}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-exynos4/setup-i2c0.c
index f47f8f3152ec..d395bd17c38b 100644
--- a/arch/arm/mach-s5pv310/setup-i2c0.c
+++ b/arch/arm/mach-exynos4/setup-i2c0.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c0.c 2 * linux/arch/arm/mach-exynos4/setup-i2c0.c
3 * 3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/ 5 * http://www.samsung.com/
@@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
21 21
22void s3c_i2c0_cfg_gpio(struct platform_device *dev) 22void s3c_i2c0_cfg_gpio(struct platform_device *dev)
23{ 23{
24 s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2, 24 s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 25 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
26} 26}
diff --git a/arch/arm/mach-s5pv310/setup-i2c1.c b/arch/arm/mach-exynos4/setup-i2c1.c
index 9d07e4e2f14c..fd7235a43f6e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c1.c
+++ b/arch/arm/mach-exynos4/setup-i2c1.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c1.c 2 * linux/arch/arm/mach-exynos4/setup-i2c1.c
3 * 3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (C) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c1_cfg_gpio(struct platform_device *dev) 19void s3c_i2c1_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c2.c b/arch/arm/mach-exynos4/setup-i2c2.c
index 4163b1233daf..2694b19e8b37 100644
--- a/arch/arm/mach-s5pv310/setup-i2c2.c
+++ b/arch/arm/mach-exynos4/setup-i2c2.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c2.c 2 * linux/arch/arm/mach-exynos4/setup-i2c2.c
3 * 3 *
4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c2_cfg_gpio(struct platform_device *dev) 19void s3c_i2c2_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c3.c b/arch/arm/mach-exynos4/setup-i2c3.c
index 180f153d2a20..379bd306993f 100644
--- a/arch/arm/mach-s5pv310/setup-i2c3.c
+++ b/arch/arm/mach-exynos4/setup-i2c3.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c3.c 2 * linux/arch/arm/mach-exynos4/setup-i2c3.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c3_cfg_gpio(struct platform_device *dev) 19void s3c_i2c3_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c4.c b/arch/arm/mach-exynos4/setup-i2c4.c
index 909e8dfc5316..9f3c04855b76 100644
--- a/arch/arm/mach-s5pv310/setup-i2c4.c
+++ b/arch/arm/mach-exynos4/setup-i2c4.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c4.c 2 * linux/arch/arm/mach-exynos4/setup-i2c4.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c4_cfg_gpio(struct platform_device *dev) 19void s3c_i2c4_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c5.c b/arch/arm/mach-exynos4/setup-i2c5.c
index 5d0fa4ac0283..77e1a1e57c76 100644
--- a/arch/arm/mach-s5pv310/setup-i2c5.c
+++ b/arch/arm/mach-exynos4/setup-i2c5.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c5.c 2 * linux/arch/arm/mach-exynos4/setup-i2c5.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c5_cfg_gpio(struct platform_device *dev) 19void s3c_i2c5_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPB(6), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c6.c b/arch/arm/mach-exynos4/setup-i2c6.c
index 34aafab92ac4..284d12b7af0e 100644
--- a/arch/arm/mach-s5pv310/setup-i2c6.c
+++ b/arch/arm/mach-exynos4/setup-i2c6.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c6.c 2 * linux/arch/arm/mach-exynos4/setup-i2c6.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c6_cfg_gpio(struct platform_device *dev) 19void s3c_i2c6_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-i2c7.c b/arch/arm/mach-exynos4/setup-i2c7.c
index 9b25b8d18920..b7611ee359a2 100644
--- a/arch/arm/mach-s5pv310/setup-i2c7.c
+++ b/arch/arm/mach-exynos4/setup-i2c7.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-s5pv310/setup-i2c7.c 2 * linux/arch/arm/mach-exynos4/setup-i2c7.c
3 * 3 *
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * 5 *
@@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
18 18
19void s3c_i2c7_cfg_gpio(struct platform_device *dev) 19void s3c_i2c7_cfg_gpio(struct platform_device *dev)
20{ 20{
21 s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2, 21 s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); 22 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
23} 23}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
index 86d38cc49135..1b3d3a2de95c 100644
--- a/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
+++ b/arch/arm/mach-exynos4/setup-sdhci-gpio.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c 1/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) 6 * EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -23,13 +23,13 @@
23#include <plat/regs-sdhci.h> 23#include <plat/regs-sdhci.h>
24#include <plat/sdhci.h> 24#include <plat/sdhci.h>
25 25
26void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) 26void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
27{ 27{
28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 28 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
29 unsigned int gpio; 29 unsigned int gpio;
30 30
31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */ 31 /* Set all the necessary GPK0[0:1] pins to special-function 2 */
32 for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) { 32 for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 33 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 34 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 35 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@@ -37,14 +37,14 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
37 37
38 switch (width) { 38 switch (width) {
39 case 8: 39 case 8:
40 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { 40 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
41 /* Data pin GPK1[3:6] to special-funtion 3 */ 41 /* Data pin GPK1[3:6] to special-funtion 3 */
42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); 42 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 43 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 44 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
45 } 45 }
46 case 4: 46 case 4:
47 for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) { 47 for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
48 /* Data pin GPK0[3:6] to special-funtion 2 */ 48 /* Data pin GPK0[3:6] to special-funtion 2 */
49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 49 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 50 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -55,25 +55,25 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
55 } 55 }
56 56
57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 57 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
58 s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2)); 58 s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
59 s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP); 59 s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 60 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
61 } 61 }
62} 62}
63 63
64void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) 64void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
65{ 65{
66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 66 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
67 unsigned int gpio; 67 unsigned int gpio;
68 68
69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */ 69 /* Set all the necessary GPK1[0:1] pins to special-function 2 */
70 for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) { 70 for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 71 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 72 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 73 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
74 } 74 }
75 75
76 for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) { 76 for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
77 /* Data pin GPK1[3:6] to special-function 2 */ 77 /* Data pin GPK1[3:6] to special-function 2 */
78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 78 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 79 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -81,19 +81,19 @@ void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
81 } 81 }
82 82
83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 83 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
84 s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2)); 84 s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
85 s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP); 85 s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 86 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
87 } 87 }
88} 88}
89 89
90void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) 90void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
91{ 91{
92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 92 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
93 unsigned int gpio; 93 unsigned int gpio;
94 94
95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */ 95 /* Set all the necessary GPK2[0:1] pins to special-function 2 */
96 for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) { 96 for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 97 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 98 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 99 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
@@ -101,14 +101,14 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
101 101
102 switch (width) { 102 switch (width) {
103 case 8: 103 case 8:
104 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { 104 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
105 /* Data pin GPK3[3:6] to special-function 3 */ 105 /* Data pin GPK3[3:6] to special-function 3 */
106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); 106 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 107 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 108 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
109 } 109 }
110 case 4: 110 case 4:
111 for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) { 111 for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
112 /* Data pin GPK2[3:6] to special-function 2 */ 112 /* Data pin GPK2[3:6] to special-function 2 */
113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 113 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 114 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -119,25 +119,25 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
119 } 119 }
120 120
121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 121 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
122 s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2)); 122 s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
123 s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP); 123 s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 124 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
125 } 125 }
126} 126}
127 127
128void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width) 128void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
129{ 129{
130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; 130 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
131 unsigned int gpio; 131 unsigned int gpio;
132 132
133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */ 133 /* Set all the necessary GPK3[0:1] pins to special-function 2 */
134 for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) { 134 for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 135 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); 136 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 137 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
138 } 138 }
139 139
140 for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) { 140 for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
141 /* Data pin GPK3[3:6] to special-function 2 */ 141 /* Data pin GPK3[3:6] to special-function 2 */
142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); 142 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP); 143 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
@@ -145,8 +145,8 @@ void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
145 } 145 }
146 146
147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { 147 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
148 s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2)); 148 s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
149 s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP); 149 s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); 150 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
151 } 151 }
152} 152}
diff --git a/arch/arm/mach-s5pv310/setup-sdhci.c b/arch/arm/mach-exynos4/setup-sdhci.c
index db8358fc4662..85f9433d4836 100644
--- a/arch/arm/mach-s5pv310/setup-sdhci.c
+++ b/arch/arm/mach-exynos4/setup-sdhci.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/setup-sdhci.c 1/* linux/arch/arm/mach-exynos4/setup-sdhci.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC) 6 * EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -23,14 +23,14 @@
23 23
24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ 24/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
25 25
26char *s5pv310_hsmmc_clksrcs[4] = { 26char *exynos4_hsmmc_clksrcs[4] = {
27 [0] = NULL, 27 [0] = NULL,
28 [1] = NULL, 28 [1] = NULL,
29 [2] = "sclk_mmc", /* mmc_bus */ 29 [2] = "sclk_mmc", /* mmc_bus */
30 [3] = NULL, 30 [3] = NULL,
31}; 31};
32 32
33void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r, 33void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
34 struct mmc_ios *ios, struct mmc_card *card) 34 struct mmc_ios *ios, struct mmc_card *card)
35{ 35{
36 u32 ctrl2, ctrl3; 36 u32 ctrl2, ctrl3;
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-exynos4/time.c
index b262d4615331..e30ac7043095 100644
--- a/arch/arm/mach-s5pv310/time.c
+++ b/arch/arm/mach-exynos4/time.c
@@ -1,9 +1,9 @@
1/* linux/arch/arm/mach-s5pv310/time.c 1/* linux/arch/arm/mach-exynos4/time.c
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * S5PV310 (and compatible) HRT support 6 * EXYNOS4 (and compatible) HRT support
7 * PWM 2/4 is used for this feature 7 * PWM 2/4 is used for this feature
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
@@ -33,7 +33,7 @@ static struct clk *tdiv2;
33static struct clk *tdiv4; 33static struct clk *tdiv4;
34static struct clk *timerclk; 34static struct clk *timerclk;
35 35
36static void s5pv310_pwm_stop(unsigned int pwm_id) 36static void exynos4_pwm_stop(unsigned int pwm_id)
37{ 37{
38 unsigned long tcon; 38 unsigned long tcon;
39 39
@@ -52,7 +52,7 @@ static void s5pv310_pwm_stop(unsigned int pwm_id)
52 __raw_writel(tcon, S3C2410_TCON); 52 __raw_writel(tcon, S3C2410_TCON);
53} 53}
54 54
55static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt) 55static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
56{ 56{
57 unsigned long tcon; 57 unsigned long tcon;
58 58
@@ -86,7 +86,7 @@ static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
86 } 86 }
87} 87}
88 88
89static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic) 89static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
90{ 90{
91 unsigned long tcon; 91 unsigned long tcon;
92 92
@@ -117,23 +117,23 @@ static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
117 __raw_writel(tcon, S3C2410_TCON); 117 __raw_writel(tcon, S3C2410_TCON);
118} 118}
119 119
120static int s5pv310_pwm_set_next_event(unsigned long cycles, 120static int exynos4_pwm_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt) 121 struct clock_event_device *evt)
122{ 122{
123 s5pv310_pwm_init(2, cycles); 123 exynos4_pwm_init(2, cycles);
124 s5pv310_pwm_start(2, 0); 124 exynos4_pwm_start(2, 0);
125 return 0; 125 return 0;
126} 126}
127 127
128static void s5pv310_pwm_set_mode(enum clock_event_mode mode, 128static void exynos4_pwm_set_mode(enum clock_event_mode mode,
129 struct clock_event_device *evt) 129 struct clock_event_device *evt)
130{ 130{
131 s5pv310_pwm_stop(2); 131 exynos4_pwm_stop(2);
132 132
133 switch (mode) { 133 switch (mode) {
134 case CLOCK_EVT_MODE_PERIODIC: 134 case CLOCK_EVT_MODE_PERIODIC:
135 s5pv310_pwm_init(2, clock_count_per_tick); 135 exynos4_pwm_init(2, clock_count_per_tick);
136 s5pv310_pwm_start(2, 1); 136 exynos4_pwm_start(2, 1);
137 break; 137 break;
138 case CLOCK_EVT_MODE_ONESHOT: 138 case CLOCK_EVT_MODE_ONESHOT:
139 break; 139 break;
@@ -149,11 +149,11 @@ static struct clock_event_device pwm_event_device = {
149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 149 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
150 .rating = 200, 150 .rating = 200,
151 .shift = 32, 151 .shift = 32,
152 .set_next_event = s5pv310_pwm_set_next_event, 152 .set_next_event = exynos4_pwm_set_next_event,
153 .set_mode = s5pv310_pwm_set_mode, 153 .set_mode = exynos4_pwm_set_mode,
154}; 154};
155 155
156irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id) 156irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
157{ 157{
158 struct clock_event_device *evt = &pwm_event_device; 158 struct clock_event_device *evt = &pwm_event_device;
159 159
@@ -162,13 +162,13 @@ irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
162 return IRQ_HANDLED; 162 return IRQ_HANDLED;
163} 163}
164 164
165static struct irqaction s5pv310_clock_event_irq = { 165static struct irqaction exynos4_clock_event_irq = {
166 .name = "pwm_timer2_irq", 166 .name = "pwm_timer2_irq",
167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, 167 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
168 .handler = s5pv310_clock_event_isr, 168 .handler = exynos4_clock_event_isr,
169}; 169};
170 170
171static void __init s5pv310_clockevent_init(void) 171static void __init exynos4_clockevent_init(void)
172{ 172{
173 unsigned long pclk; 173 unsigned long pclk;
174 unsigned long clock_rate; 174 unsigned long clock_rate;
@@ -198,10 +198,10 @@ static void __init s5pv310_clockevent_init(void)
198 pwm_event_device.cpumask = cpumask_of(0); 198 pwm_event_device.cpumask = cpumask_of(0);
199 clockevents_register_device(&pwm_event_device); 199 clockevents_register_device(&pwm_event_device);
200 200
201 setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq); 201 setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
202} 202}
203 203
204static cycle_t s5pv310_pwm4_read(struct clocksource *cs) 204static cycle_t exynos4_pwm4_read(struct clocksource *cs)
205{ 205{
206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40)); 206 return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
207} 207}
@@ -209,12 +209,12 @@ static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
209struct clocksource pwm_clocksource = { 209struct clocksource pwm_clocksource = {
210 .name = "pwm_timer4", 210 .name = "pwm_timer4",
211 .rating = 250, 211 .rating = 250,
212 .read = s5pv310_pwm4_read, 212 .read = exynos4_pwm4_read,
213 .mask = CLOCKSOURCE_MASK(32), 213 .mask = CLOCKSOURCE_MASK(32),
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS , 214 .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
215}; 215};
216 216
217static void __init s5pv310_clocksource_init(void) 217static void __init exynos4_clocksource_init(void)
218{ 218{
219 unsigned long pclk; 219 unsigned long pclk;
220 unsigned long clock_rate; 220 unsigned long clock_rate;
@@ -226,14 +226,14 @@ static void __init s5pv310_clocksource_init(void)
226 226
227 clock_rate = clk_get_rate(tin4); 227 clock_rate = clk_get_rate(tin4);
228 228
229 s5pv310_pwm_init(4, ~0); 229 exynos4_pwm_init(4, ~0);
230 s5pv310_pwm_start(4, 1); 230 exynos4_pwm_start(4, 1);
231 231
232 if (clocksource_register_hz(&pwm_clocksource, clock_rate)) 232 if (clocksource_register_hz(&pwm_clocksource, clock_rate))
233 panic("%s: can't register clocksource\n", pwm_clocksource.name); 233 panic("%s: can't register clocksource\n", pwm_clocksource.name);
234} 234}
235 235
236static void __init s5pv310_timer_resources(void) 236static void __init exynos4_timer_resources(void)
237{ 237{
238 struct platform_device tmpdev; 238 struct platform_device tmpdev;
239 239
@@ -267,17 +267,17 @@ static void __init s5pv310_timer_resources(void)
267 clk_enable(tin4); 267 clk_enable(tin4);
268} 268}
269 269
270static void __init s5pv310_timer_init(void) 270static void __init exynos4_timer_init(void)
271{ 271{
272#ifdef CONFIG_LOCAL_TIMERS 272#ifdef CONFIG_LOCAL_TIMERS
273 twd_base = S5P_VA_TWD; 273 twd_base = S5P_VA_TWD;
274#endif 274#endif
275 275
276 s5pv310_timer_resources(); 276 exynos4_timer_resources();
277 s5pv310_clockevent_init(); 277 exynos4_clockevent_init();
278 s5pv310_clocksource_init(); 278 exynos4_clocksource_init();
279} 279}
280 280
281struct sys_timer s5pv310_timer = { 281struct sys_timer exynos4_timer = {
282 .init = s5pv310_timer_init, 282 .init = exynos4_timer_init,
283}; 283};
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
deleted file mode 100644
index b2a9acc5185f..000000000000
--- a/arch/arm/mach-s5pv310/Kconfig
+++ /dev/null
@@ -1,151 +0,0 @@
1# arch/arm/mach-s5pv310/Kconfig
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8# Configuration options for the S5PV310
9
10if ARCH_S5PV310
11
12config CPU_S5PV310
13 bool
14 select S3C_PL330_DMA
15 help
16 Enable S5PV310 CPU support
17
18config S5PV310_DEV_PD
19 bool
20 help
21 Compile in platform device definitions for Power Domain
22
23config S5PV310_SETUP_I2C1
24 bool
25 help
26 Common setup code for i2c bus 1.
27
28config S5PV310_SETUP_I2C2
29 bool
30 help
31 Common setup code for i2c bus 2.
32
33config S5PV310_SETUP_I2C3
34 bool
35 help
36 Common setup code for i2c bus 3.
37
38config S5PV310_SETUP_I2C4
39 bool
40 help
41 Common setup code for i2c bus 4.
42
43config S5PV310_SETUP_I2C5
44 bool
45 help
46 Common setup code for i2c bus 5.
47
48config S5PV310_SETUP_I2C6
49 bool
50 help
51 Common setup code for i2c bus 6.
52
53config S5PV310_SETUP_I2C7
54 bool
55 help
56 Common setup code for i2c bus 7.
57
58config S5PV310_SETUP_SDHCI
59 bool
60 select S5PV310_SETUP_SDHCI_GPIO
61 help
62 Internal helper functions for S5PV310 based SDHCI systems.
63
64config S5PV310_SETUP_SDHCI_GPIO
65 bool
66 help
67 Common setup code for SDHCI gpio.
68
69config S5PV310_DEV_SYSMMU
70 bool
71 help
72 Common setup code for SYSTEM MMU in S5PV310
73
74# machine support
75
76menu "S5PC210 Machines"
77
78config MACH_SMDKC210
79 bool "SMDKC210"
80 select CPU_S5PV310
81 select S3C_DEV_RTC
82 select S3C_DEV_WDT
83 select S3C_DEV_I2C1
84 select S3C_DEV_HSMMC
85 select S3C_DEV_HSMMC1
86 select S3C_DEV_HSMMC2
87 select S3C_DEV_HSMMC3
88 select S5PV310_DEV_PD
89 select S5PV310_SETUP_I2C1
90 select S5PV310_SETUP_SDHCI
91 select S5PV310_DEV_SYSMMU
92 help
93 Machine support for Samsung SMDKC210
94 S5PC210(MCP) is one of package option of S5PV310
95
96config MACH_UNIVERSAL_C210
97 bool "Mobile UNIVERSAL_C210 Board"
98 select CPU_S5PV310
99 select S5P_DEV_ONENAND
100 select S3C_DEV_HSMMC
101 select S3C_DEV_HSMMC2
102 select S3C_DEV_HSMMC3
103 select S5PV310_SETUP_SDHCI
104 select S3C_DEV_I2C1
105 select S5PV310_SETUP_I2C1
106 help
107 Machine support for Samsung Mobile Universal S5PC210 Reference
108 Board. S5PC210(MCP) is one of package option of S5PV310
109
110endmenu
111
112menu "S5PV310 Machines"
113
114config MACH_SMDKV310
115 bool "SMDKV310"
116 select CPU_S5PV310
117 select S3C_DEV_RTC
118 select S3C_DEV_WDT
119 select S3C_DEV_I2C1
120 select S3C_DEV_HSMMC
121 select S3C_DEV_HSMMC1
122 select S3C_DEV_HSMMC2
123 select S3C_DEV_HSMMC3
124 select S5PV310_DEV_PD
125 select S5PV310_DEV_SYSMMU
126 select S5PV310_SETUP_I2C1
127 select S5PV310_SETUP_SDHCI
128 help
129 Machine support for Samsung SMDKV310
130
131endmenu
132
133comment "Configuration for HSMMC bus width"
134
135menu "Use 8-bit bus width"
136
137config S5PV310_SDHCI_CH0_8BIT
138 bool "Channel 0 with 8-bit bus"
139 help
140 Support HSMMC Channel 0 8-bit bus.
141 If selected, Channel 1 is disabled.
142
143config S5PV310_SDHCI_CH2_8BIT
144 bool "Channel 2 with 8-bit bus"
145 help
146 Support HSMMC Channel 2 8-bit bus.
147 If selected, Channel 3 is disabled.
148
149endmenu
150
151endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
deleted file mode 100644
index 036fb383b830..000000000000
--- a/arch/arm/mach-s5pv310/Makefile
+++ /dev/null
@@ -1,43 +0,0 @@
1# arch/arm/mach-s5pv310/Makefile
2#
3# Copyright (c) 2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core support for S5PV310 system
14
15obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
16obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
17obj-$(CONFIG_CPU_FREQ) += cpufreq.o
18
19obj-$(CONFIG_SMP) += platsmp.o headsmp.o
20obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
21obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
22
23# machine support
24
25obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
26obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
27obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
28
29# device support
30
31obj-y += dev-audio.o
32obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
33obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
34
35obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
36obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
37obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
38obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
39obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
40obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
41obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
42obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
43obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
deleted file mode 100644
index 20cb80c23466..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/gpio.h
+++ /dev/null
@@ -1,135 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16#define gpio_get_value __gpio_get_value
17#define gpio_set_value __gpio_set_value
18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq
20
21/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
22
23/* GPIO bank sizes */
24#define S5PV310_GPIO_A0_NR (8)
25#define S5PV310_GPIO_A1_NR (6)
26#define S5PV310_GPIO_B_NR (8)
27#define S5PV310_GPIO_C0_NR (5)
28#define S5PV310_GPIO_C1_NR (5)
29#define S5PV310_GPIO_D0_NR (4)
30#define S5PV310_GPIO_D1_NR (4)
31#define S5PV310_GPIO_E0_NR (5)
32#define S5PV310_GPIO_E1_NR (8)
33#define S5PV310_GPIO_E2_NR (6)
34#define S5PV310_GPIO_E3_NR (8)
35#define S5PV310_GPIO_E4_NR (8)
36#define S5PV310_GPIO_F0_NR (8)
37#define S5PV310_GPIO_F1_NR (8)
38#define S5PV310_GPIO_F2_NR (8)
39#define S5PV310_GPIO_F3_NR (6)
40#define S5PV310_GPIO_J0_NR (8)
41#define S5PV310_GPIO_J1_NR (5)
42#define S5PV310_GPIO_K0_NR (7)
43#define S5PV310_GPIO_K1_NR (7)
44#define S5PV310_GPIO_K2_NR (7)
45#define S5PV310_GPIO_K3_NR (7)
46#define S5PV310_GPIO_L0_NR (8)
47#define S5PV310_GPIO_L1_NR (3)
48#define S5PV310_GPIO_L2_NR (8)
49#define S5PV310_GPIO_X0_NR (8)
50#define S5PV310_GPIO_X1_NR (8)
51#define S5PV310_GPIO_X2_NR (8)
52#define S5PV310_GPIO_X3_NR (8)
53#define S5PV310_GPIO_Z_NR (7)
54
55/* GPIO bank numbers */
56
57#define S5PV310_GPIO_NEXT(__gpio) \
58 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
59
60enum s5p_gpio_number {
61 S5PV310_GPIO_A0_START = 0,
62 S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
63 S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
64 S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
65 S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
66 S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
67 S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
68 S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
69 S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
70 S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
71 S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
72 S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
73 S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
74 S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
75 S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
76 S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
77 S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
78 S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
79 S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
80 S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
81 S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
82 S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
83 S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
84 S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
85 S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
86 S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
87 S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
88 S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
89 S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
90 S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
91};
92
93/* S5PV310 GPIO number definitions */
94#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
95#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
96#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
97#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
98#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
99#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
100#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
101#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
102#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
103#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
104#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
105#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
106#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
107#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
108#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
109#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
110#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
111#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
112#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
113#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
114#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
115#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
116#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
117#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
118#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
119#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
120#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
121#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
122#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
123#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
124
125/* the end of the S5PV310 specific gpios */
126#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
127#define S3C_GPIO_END S5PV310_GPIO_END
128
129/* define the number of gpios we need to the one after the GPZ() range */
130#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
131 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
132
133#include <asm-generic/gpio.h>
134
135#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
deleted file mode 100644
index 901657fa7a12..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/map.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV310 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17
18/*
19 * S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
20 * So need to define it, and here is to avoid redefinition warning.
21 */
22#define S3C_UART_OFFSET (0x10000)
23
24#include <plat/map-s5p.h>
25
26#define S5PV310_PA_SYSRAM 0x02025000
27
28#define S5PV310_PA_I2S0 0x03830000
29#define S5PV310_PA_I2S1 0xE3100000
30#define S5PV310_PA_I2S2 0xE2A00000
31
32#define S5PV310_PA_PCM0 0x03840000
33#define S5PV310_PA_PCM1 0x13980000
34#define S5PV310_PA_PCM2 0x13990000
35
36#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
37
38#define S5PC210_PA_ONENAND 0x0C000000
39#define S5PC210_PA_ONENAND_DMA 0x0C600000
40
41#define S5PV310_PA_CHIPID 0x10000000
42
43#define S5PV310_PA_SYSCON 0x10010000
44#define S5PV310_PA_PMU 0x10020000
45#define S5PV310_PA_CMU 0x10030000
46
47#define S5PV310_PA_WATCHDOG 0x10060000
48#define S5PV310_PA_RTC 0x10070000
49
50#define S5PV310_PA_DMC0 0x10400000
51
52#define S5PV310_PA_COMBINER 0x10448000
53
54#define S5PV310_PA_COREPERI 0x10500000
55#define S5PV310_PA_GIC_CPU 0x10500100
56#define S5PV310_PA_TWD 0x10500600
57#define S5PV310_PA_GIC_DIST 0x10501000
58#define S5PV310_PA_L2CC 0x10502000
59
60#define S5PV310_PA_MDMA 0x10810000
61#define S5PV310_PA_PDMA0 0x12680000
62#define S5PV310_PA_PDMA1 0x12690000
63
64#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
65#define S5PV310_PA_SYSMMU_SSS 0x10A50000
66#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
67#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
68#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
69#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
70#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
71#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
72#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
73#define S5PV310_PA_SYSMMU_PCIe 0x12620000
74#define S5PV310_PA_SYSMMU_G2D 0x12A20000
75#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
76#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
77#define S5PV310_PA_SYSMMU_TV 0x12E20000
78#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
79#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
80
81#define S5PV310_PA_GPIO1 0x11400000
82#define S5PV310_PA_GPIO2 0x11000000
83#define S5PV310_PA_GPIO3 0x03860000
84
85#define S5PV310_PA_MIPI_CSIS0 0x11880000
86#define S5PV310_PA_MIPI_CSIS1 0x11890000
87
88#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
89
90#define S5PV310_PA_SROMC 0x12570000
91
92#define S5PV310_PA_UART 0x13800000
93
94#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
95
96#define S5PV310_PA_AC97 0x139A0000
97
98#define S5PV310_PA_TIMER 0x139D0000
99
100#define S5PV310_PA_SDRAM 0x40000000
101
102#define S5PV310_PA_SPDIF 0xE1100000
103
104/* Compatibiltiy Defines */
105
106#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
107#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
108#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
109#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
110#define S3C_PA_IIC S5PV310_PA_IIC(0)
111#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
112#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
113#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
114#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
115#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
116#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
117#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
118#define S3C_PA_RTC S5PV310_PA_RTC
119#define S3C_PA_WDT S5PV310_PA_WATCHDOG
120
121#define S5P_PA_CHIPID S5PV310_PA_CHIPID
122#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
123#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
124#define S5P_PA_ONENAND S5PC210_PA_ONENAND
125#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
126#define S5P_PA_SDRAM S5PV310_PA_SDRAM
127#define S5P_PA_SROMC S5PV310_PA_SROMC
128#define S5P_PA_SYSCON S5PV310_PA_SYSCON
129#define S5P_PA_TIMER S5PV310_PA_TIMER
130
131/* UART */
132
133#define S3C_PA_UART S5PV310_PA_UART
134
135#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
136#define S5P_PA_UART0 S5P_PA_UART(0)
137#define S5P_PA_UART1 S5P_PA_UART(1)
138#define S5P_PA_UART2 S5P_PA_UART(2)
139#define S5P_PA_UART3 S5P_PA_UART(3)
140#define S5P_PA_UART4 S5P_PA_UART(4)
141
142#define S5P_SZ_UART SZ_256
143
144#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h b/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
deleted file mode 100644
index 82e9e0c9d452..000000000000
--- a/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PV310 - GPIO (including EINT) register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17#include <mach/irqs.h>
18
19#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
20#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
21
22#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
23#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
24
25#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
26#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
27
28#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
29#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
30
31#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
32
33#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
34
35#define EINT_MODE S3C_GPIO_SFN(0xf)
36
37#define EINT_GPIO_0(x) S5PV310_GPX0(x)
38#define EINT_GPIO_1(x) S5PV310_GPX1(x)
39#define EINT_GPIO_2(x) S5PV310_GPX2(x)
40#define EINT_GPIO_3(x) S5PV310_GPX3(x)
41
42#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/mach-universal_c210.c b/arch/arm/mach-s5pv310/mach-universal_c210.c
deleted file mode 100644
index 36bc3cf825e3..000000000000
--- a/arch/arm/mach-s5pv310/mach-universal_c210.c
+++ /dev/null
@@ -1,237 +0,0 @@
1/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <linux/platform_device.h>
11#include <linux/serial_core.h>
12#include <linux/input.h>
13#include <linux/i2c.h>
14#include <linux/gpio_keys.h>
15#include <linux/gpio.h>
16#include <linux/regulator/machine.h>
17#include <linux/regulator/fixed.h>
18#include <linux/mmc/host.h>
19
20#include <asm/mach/arch.h>
21#include <asm/mach-types.h>
22
23#include <plat/regs-serial.h>
24#include <plat/s5pv310.h>
25#include <plat/cpu.h>
26#include <plat/devs.h>
27#include <plat/sdhci.h>
28
29#include <mach/map.h>
30
31/* Following are default values for UCON, ULCON and UFCON UART registers */
32#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
33 S3C2410_UCON_RXILEVEL | \
34 S3C2410_UCON_TXIRQMODE | \
35 S3C2410_UCON_RXIRQMODE | \
36 S3C2410_UCON_RXFIFO_TOI | \
37 S3C2443_UCON_RXERR_IRQEN)
38
39#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
40
41#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
42 S5PV210_UFCON_TXTRIG256 | \
43 S5PV210_UFCON_RXTRIG256)
44
45static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
46 [0] = {
47 .hwport = 0,
48 .ucon = UNIVERSAL_UCON_DEFAULT,
49 .ulcon = UNIVERSAL_ULCON_DEFAULT,
50 .ufcon = UNIVERSAL_UFCON_DEFAULT,
51 },
52 [1] = {
53 .hwport = 1,
54 .ucon = UNIVERSAL_UCON_DEFAULT,
55 .ulcon = UNIVERSAL_ULCON_DEFAULT,
56 .ufcon = UNIVERSAL_UFCON_DEFAULT,
57 },
58 [2] = {
59 .hwport = 2,
60 .ucon = UNIVERSAL_UCON_DEFAULT,
61 .ulcon = UNIVERSAL_ULCON_DEFAULT,
62 .ufcon = UNIVERSAL_UFCON_DEFAULT,
63 },
64 [3] = {
65 .hwport = 3,
66 .ucon = UNIVERSAL_UCON_DEFAULT,
67 .ulcon = UNIVERSAL_ULCON_DEFAULT,
68 .ufcon = UNIVERSAL_UFCON_DEFAULT,
69 },
70};
71
72static struct gpio_keys_button universal_gpio_keys_tables[] = {
73 {
74 .code = KEY_VOLUMEUP,
75 .gpio = S5PV310_GPX2(0), /* XEINT16 */
76 .desc = "gpio-keys: KEY_VOLUMEUP",
77 .type = EV_KEY,
78 .active_low = 1,
79 .debounce_interval = 1,
80 }, {
81 .code = KEY_VOLUMEDOWN,
82 .gpio = S5PV310_GPX2(1), /* XEINT17 */
83 .desc = "gpio-keys: KEY_VOLUMEDOWN",
84 .type = EV_KEY,
85 .active_low = 1,
86 .debounce_interval = 1,
87 }, {
88 .code = KEY_CONFIG,
89 .gpio = S5PV310_GPX2(2), /* XEINT18 */
90 .desc = "gpio-keys: KEY_CONFIG",
91 .type = EV_KEY,
92 .active_low = 1,
93 .debounce_interval = 1,
94 }, {
95 .code = KEY_CAMERA,
96 .gpio = S5PV310_GPX2(3), /* XEINT19 */
97 .desc = "gpio-keys: KEY_CAMERA",
98 .type = EV_KEY,
99 .active_low = 1,
100 .debounce_interval = 1,
101 }, {
102 .code = KEY_OK,
103 .gpio = S5PV310_GPX3(5), /* XEINT29 */
104 .desc = "gpio-keys: KEY_OK",
105 .type = EV_KEY,
106 .active_low = 1,
107 .debounce_interval = 1,
108 },
109};
110
111static struct gpio_keys_platform_data universal_gpio_keys_data = {
112 .buttons = universal_gpio_keys_tables,
113 .nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
114};
115
116static struct platform_device universal_gpio_keys = {
117 .name = "gpio-keys",
118 .dev = {
119 .platform_data = &universal_gpio_keys_data,
120 },
121};
122
123/* eMMC */
124static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
125 .max_width = 8,
126 .host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
127 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
128 MMC_CAP_DISABLE),
129 .cd_type = S3C_SDHCI_CD_PERMANENT,
130 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
131};
132
133static struct regulator_consumer_supply mmc0_supplies[] = {
134 REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
135};
136
137static struct regulator_init_data mmc0_fixed_voltage_init_data = {
138 .constraints = {
139 .name = "VMEM_VDD_2.8V",
140 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
141 },
142 .num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
143 .consumer_supplies = mmc0_supplies,
144};
145
146static struct fixed_voltage_config mmc0_fixed_voltage_config = {
147 .supply_name = "MASSMEMORY_EN",
148 .microvolts = 2800000,
149 .gpio = S5PV310_GPE1(3),
150 .enable_high = true,
151 .init_data = &mmc0_fixed_voltage_init_data,
152};
153
154static struct platform_device mmc0_fixed_voltage = {
155 .name = "reg-fixed-voltage",
156 .id = 0,
157 .dev = {
158 .platform_data = &mmc0_fixed_voltage_config,
159 },
160};
161
162/* SD */
163static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
164 .max_width = 4,
165 .host_caps = MMC_CAP_4_BIT_DATA |
166 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
167 MMC_CAP_DISABLE,
168 .ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
169 .ext_cd_gpio_invert = 1,
170 .cd_type = S3C_SDHCI_CD_GPIO,
171 .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
172};
173
174/* WiFi */
175static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
176 .max_width = 4,
177 .host_caps = MMC_CAP_4_BIT_DATA |
178 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
179 MMC_CAP_DISABLE,
180 .cd_type = S3C_SDHCI_CD_EXTERNAL,
181};
182
183static void __init universal_sdhci_init(void)
184{
185 s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
186 s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
187 s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
188}
189
190/* I2C0 */
191static struct i2c_board_info i2c0_devs[] __initdata = {
192 /* Camera, To be updated */
193};
194
195/* I2C1 */
196static struct i2c_board_info i2c1_devs[] __initdata = {
197 /* Gyro, To be updated */
198};
199
200static struct platform_device *universal_devices[] __initdata = {
201 /* Samsung Platform Devices */
202 &mmc0_fixed_voltage,
203 &s3c_device_hsmmc0,
204 &s3c_device_hsmmc2,
205 &s3c_device_hsmmc3,
206
207 /* Universal Devices */
208 &universal_gpio_keys,
209 &s5p_device_onenand,
210};
211
212static void __init universal_map_io(void)
213{
214 s5p_init_io(NULL, 0, S5P_VA_CHIPID);
215 s3c24xx_init_clocks(24000000);
216 s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
217}
218
219static void __init universal_machine_init(void)
220{
221 universal_sdhci_init();
222
223 i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
224 i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
225
226 /* Last */
227 platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
228}
229
230MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
231 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
232 .boot_params = S5P_PA_SDRAM + 0x100,
233 .init_irq = s5pv310_init_irq,
234 .map_io = universal_map_io,
235 .init_machine = universal_machine_init,
236 .timer = &s5pv310_timer,
237MACHINE_END
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index e4509bae8fc4..0f59e54e9398 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -812,7 +812,7 @@ config CACHE_L2X0
812 bool "Enable the L2x0 outer cache controller" 812 bool "Enable the L2x0 outer cache controller"
813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ 813 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
814 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \ 814 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \ 815 ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE 816 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
817 default y 817 default y
818 select OUTER_CACHE 818 select OUTER_CACHE
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 557f8c507f6d..6390ac728b35 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,10 +7,10 @@
7 7
8config PLAT_S5P 8config PLAT_S5P
9 bool 9 bool
10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310) 10 depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
11 default y 11 default y
12 select ARM_VIC if !ARCH_S5PV310 12 select ARM_VIC if !ARCH_EXYNOS4
13 select ARM_GIC if ARCH_S5PV310 13 select ARM_GIC if ARCH_EXYNOS4
14 select NO_IOPORT 14 select NO_IOPORT
15 select ARCH_REQUIRE_GPIOLIB 15 select ARCH_REQUIRE_GPIOLIB
16 select S3C_GPIO_TRACK 16 select S3C_GPIO_TRACK
@@ -41,7 +41,7 @@ comment "System MMU"
41 41
42config S5P_SYSTEM_MMU 42config S5P_SYSTEM_MMU
43 bool "S5P SYSTEM MMU" 43 bool "S5P SYSTEM MMU"
44 depends on ARCH_S5PV310 44 depends on ARCH_EXYNOS4
45 help 45 help
46 Say Y here if you want to enable System MMU 46 Say Y here if you want to enable System MMU
47 47
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 047d31c1bbd8..c3bfe9b13acf 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -1,7 +1,7 @@
1/* linux/arch/arm/plat-s5p/cpu.c 1/* linux/arch/arm/plat-s5p/cpu.c
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/ 4 * http://www.samsung.com
5 * 5 *
6 * S5P CPU Support 6 * S5P CPU Support
7 * 7 *
@@ -12,17 +12,20 @@
12 12
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <mach/map.h> 15
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
17#include <asm/mach/map.h> 17#include <asm/mach/map.h>
18
19#include <mach/map.h>
18#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21
19#include <plat/cpu.h> 22#include <plat/cpu.h>
20#include <plat/s5p6440.h> 23#include <plat/s5p6440.h>
21#include <plat/s5p6442.h> 24#include <plat/s5p6442.h>
22#include <plat/s5p6450.h> 25#include <plat/s5p6450.h>
23#include <plat/s5pc100.h> 26#include <plat/s5pc100.h>
24#include <plat/s5pv210.h> 27#include <plat/s5pv210.h>
25#include <plat/s5pv310.h> 28#include <plat/exynos4.h>
26 29
27/* table of supported CPUs */ 30/* table of supported CPUs */
28 31
@@ -31,7 +34,7 @@ static const char name_s5p6442[] = "S5P6442";
31static const char name_s5p6450[] = "S5P6450"; 34static const char name_s5p6450[] = "S5P6450";
32static const char name_s5pc100[] = "S5PC100"; 35static const char name_s5pc100[] = "S5PC100";
33static const char name_s5pv210[] = "S5PV210/S5PC110"; 36static const char name_s5pv210[] = "S5PV210/S5PC110";
34static const char name_s5pv310[] = "S5PV310"; 37static const char name_exynos4210[] = "EXYNOS4210";
35 38
36static struct cpu_table cpu_ids[] __initdata = { 39static struct cpu_table cpu_ids[] __initdata = {
37 { 40 {
@@ -75,13 +78,13 @@ static struct cpu_table cpu_ids[] __initdata = {
75 .init = s5pv210_init, 78 .init = s5pv210_init,
76 .name = name_s5pv210, 79 .name = name_s5pv210,
77 }, { 80 }, {
78 .idcode = 0x43200000, 81 .idcode = 0x43210000,
79 .idmask = 0xfffff000, 82 .idmask = 0xfffff000,
80 .map_io = s5pv310_map_io, 83 .map_io = exynos4_map_io,
81 .init_clocks = s5pv310_init_clocks, 84 .init_clocks = exynos4_init_clocks,
82 .init_uarts = s5pv310_init_uarts, 85 .init_uarts = exynos4_init_uarts,
83 .init = s5pv310_init, 86 .init = exynos4_init,
84 .name = name_s5pv310, 87 .name = name_exynos4210,
85 }, 88 },
86}; 89};
87 90
diff --git a/arch/arm/plat-s5p/include/plat/exynos4.h b/arch/arm/plat-s5p/include/plat/exynos4.h
new file mode 100644
index 000000000000..907caab53dcf
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/exynos4.h
@@ -0,0 +1,34 @@
1/* linux/arch/arm/plat-s5p/include/plat/exynos4.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Header file for exynos4 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for EXYNOS4 related SoCs */
14
15extern void exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void exynos4_register_clocks(void);
17extern void exynos4_setup_clocks(void);
18
19#ifdef CONFIG_CPU_EXYNOS4210
20
21extern int exynos4_init(void);
22extern void exynos4_init_irq(void);
23extern void exynos4_map_io(void);
24extern void exynos4_init_clocks(int xtal);
25extern struct sys_timer exynos4_timer;
26
27#define exynos4_init_uarts exynos4_common_init_uarts
28
29#else
30#define exynos4_init_clocks NULL
31#define exynos4_init_uarts NULL
32#define exynos4_map_io NULL
33#define exynos4_init NULL
34#endif
diff --git a/arch/arm/plat-s5p/include/plat/s5pv310.h b/arch/arm/plat-s5p/include/plat/s5pv310.h
deleted file mode 100644
index 769c991ceb37..000000000000
--- a/arch/arm/plat-s5p/include/plat/s5pv310.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Header file for s5pv310 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Common init code for S5PV310 related SoCs */
14
15extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
16extern void s5pv310_register_clocks(void);
17extern void s5pv310_setup_clocks(void);
18
19#ifdef CONFIG_CPU_S5PV310
20
21extern int s5pv310_init(void);
22extern void s5pv310_init_irq(void);
23extern void s5pv310_map_io(void);
24extern void s5pv310_init_clocks(int xtal);
25extern struct sys_timer s5pv310_timer;
26
27#define s5pv310_init_uarts s5pv310_common_init_uarts
28
29#else
30#define s5pv310_init_clocks NULL
31#define s5pv310_init_uarts NULL
32#define s5pv310_map_io NULL
33#define s5pv310_init NULL
34#endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index b4d208b42957..e2b3ab997cff 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -1,5 +1,8 @@
1/* arch/arm/plat-samsung/include/plat/devs.h 1/* arch/arm/plat-samsung/include/plat/devs.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
3 * Copyright (c) 2004 Simtec Electronics 6 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
@@ -96,15 +99,15 @@ extern struct platform_device s5pv210_device_iis1;
96extern struct platform_device s5pv210_device_iis2; 99extern struct platform_device s5pv210_device_iis2;
97extern struct platform_device s5pv210_device_spdif; 100extern struct platform_device s5pv210_device_spdif;
98 101
99extern struct platform_device s5pv310_device_ac97; 102extern struct platform_device exynos4_device_ac97;
100extern struct platform_device s5pv310_device_pcm0; 103extern struct platform_device exynos4_device_pcm0;
101extern struct platform_device s5pv310_device_pcm1; 104extern struct platform_device exynos4_device_pcm1;
102extern struct platform_device s5pv310_device_pcm2; 105extern struct platform_device exynos4_device_pcm2;
103extern struct platform_device s5pv310_device_i2s0; 106extern struct platform_device exynos4_device_i2s0;
104extern struct platform_device s5pv310_device_i2s1; 107extern struct platform_device exynos4_device_i2s1;
105extern struct platform_device s5pv310_device_i2s2; 108extern struct platform_device exynos4_device_i2s2;
106extern struct platform_device s5pv310_device_spdif; 109extern struct platform_device exynos4_device_spdif;
107extern struct platform_device s5pv310_device_pd[]; 110extern struct platform_device exynos4_device_pd[];
108 111
109extern struct platform_device s5p6442_device_pcm0; 112extern struct platform_device s5p6442_device_pcm0;
110extern struct platform_device s5p6442_device_pcm1; 113extern struct platform_device s5p6442_device_pcm1;
@@ -137,7 +140,7 @@ extern struct platform_device s5p_device_fimc2;
137extern struct platform_device s5p_device_mipi_csis0; 140extern struct platform_device s5p_device_mipi_csis0;
138extern struct platform_device s5p_device_mipi_csis1; 141extern struct platform_device s5p_device_mipi_csis1;
139 142
140extern struct platform_device s5pv310_device_sysmmu; 143extern struct platform_device exynos4_device_sysmmu;
141 144
142/* s3c2440 specific devices */ 145/* s3c2440 specific devices */
143 146
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
index 5f0ad85783db..abb4bc32716a 100644
--- a/arch/arm/plat-samsung/include/plat/pd.h
+++ b/arch/arm/plat-samsung/include/plat/pd.h
@@ -1,6 +1,6 @@
1/* linux/arch/arm/plat-samsung/include/plat/pd.h 1/* linux/arch/arm/plat-samsung/include/plat/pd.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 4 * http://www.samsung.com
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
@@ -17,7 +17,7 @@ struct samsung_pd_info {
17 void __iomem *base; 17 void __iomem *base;
18}; 18};
19 19
20enum s5pv310_pd_block { 20enum exynos4_pd_block {
21 PD_MFC, 21 PD_MFC,
22 PD_G3D, 22 PD_G3D,
23 PD_LCD0, 23 PD_LCD0,
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 5a41a0b69eec..b0bdf16549d5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -1,4 +1,7 @@
1/* linux/arch/arm/plat-s3c/include/plat/sdhci.h 1/* linux/arch/arm/plat-samsung/include/plat/sdhci.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
2 * 5 *
3 * Copyright 2008 Openmoko, Inc. 6 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
@@ -119,10 +122,10 @@ extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
119extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 122extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
120extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 123extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
121extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 124extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
122extern void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 125extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
123extern void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 126extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
124extern void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 127extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
125extern void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 128extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
126 129
127/* S3C2416 SDHCI setup */ 130/* S3C2416 SDHCI setup */
128 131
@@ -334,57 +337,57 @@ static inline void s5pv210_default_sdhci3(void) { }
334 337
335#endif /* CONFIG_S5PV210_SETUP_SDHCI */ 338#endif /* CONFIG_S5PV210_SETUP_SDHCI */
336 339
337/* S5PV310 SDHCI setup */ 340/* EXYNOS4 SDHCI setup */
338#ifdef CONFIG_S5PV310_SETUP_SDHCI 341#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
339extern char *s5pv310_hsmmc_clksrcs[4]; 342extern char *exynos4_hsmmc_clksrcs[4];
340 343
341extern void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, 344extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
342 void __iomem *r, 345 void __iomem *r,
343 struct mmc_ios *ios, 346 struct mmc_ios *ios,
344 struct mmc_card *card); 347 struct mmc_card *card);
345 348
346static inline void s5pv310_default_sdhci0(void) 349static inline void exynos4_default_sdhci0(void)
347{ 350{
348#ifdef CONFIG_S3C_DEV_HSMMC 351#ifdef CONFIG_S3C_DEV_HSMMC
349 s3c_hsmmc0_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 352 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
350 s3c_hsmmc0_def_platdata.cfg_gpio = s5pv310_setup_sdhci0_cfg_gpio; 353 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
351 s3c_hsmmc0_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 354 s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
352#endif 355#endif
353} 356}
354 357
355static inline void s5pv310_default_sdhci1(void) 358static inline void exynos4_default_sdhci1(void)
356{ 359{
357#ifdef CONFIG_S3C_DEV_HSMMC1 360#ifdef CONFIG_S3C_DEV_HSMMC1
358 s3c_hsmmc1_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 361 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
359 s3c_hsmmc1_def_platdata.cfg_gpio = s5pv310_setup_sdhci1_cfg_gpio; 362 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
360 s3c_hsmmc1_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 363 s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
361#endif 364#endif
362} 365}
363 366
364static inline void s5pv310_default_sdhci2(void) 367static inline void exynos4_default_sdhci2(void)
365{ 368{
366#ifdef CONFIG_S3C_DEV_HSMMC2 369#ifdef CONFIG_S3C_DEV_HSMMC2
367 s3c_hsmmc2_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 370 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
368 s3c_hsmmc2_def_platdata.cfg_gpio = s5pv310_setup_sdhci2_cfg_gpio; 371 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
369 s3c_hsmmc2_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 372 s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
370#endif 373#endif
371} 374}
372 375
373static inline void s5pv310_default_sdhci3(void) 376static inline void exynos4_default_sdhci3(void)
374{ 377{
375#ifdef CONFIG_S3C_DEV_HSMMC3 378#ifdef CONFIG_S3C_DEV_HSMMC3
376 s3c_hsmmc3_def_platdata.clocks = s5pv310_hsmmc_clksrcs; 379 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
377 s3c_hsmmc3_def_platdata.cfg_gpio = s5pv310_setup_sdhci3_cfg_gpio; 380 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
378 s3c_hsmmc3_def_platdata.cfg_card = s5pv310_setup_sdhci_cfg_card; 381 s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
379#endif 382#endif
380} 383}
381 384
382#else 385#else
383static inline void s5pv310_default_sdhci0(void) { } 386static inline void exynos4_default_sdhci0(void) { }
384static inline void s5pv310_default_sdhci1(void) { } 387static inline void exynos4_default_sdhci1(void) { }
385static inline void s5pv310_default_sdhci2(void) { } 388static inline void exynos4_default_sdhci2(void) { }
386static inline void s5pv310_default_sdhci3(void) { } 389static inline void exynos4_default_sdhci3(void) { }
387 390
388#endif /* CONFIG_S5PV310_SETUP_SDHCI */ 391#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
389 392
390#endif /* __PLAT_S3C_SDHCI_H */ 393#endif /* __PLAT_S3C_SDHCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 01:44:43 -0500