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authorArnd Bergmann <arnd@arndb.de>2013-06-19 20:14:59 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-19 20:15:45 -0400
commite5051b8472c2fde91e44d906c9a2e516a10b60b2 (patch)
treeb7c27378ca981a7bcf86639db7b0cde834feb0b6 /arch
parentc3b693d1d63444afe4fbf809d8a311b63741e503 (diff)
parent3bfbc6cd9b41f937a134ba65a4a1eefba062b9a8 (diff)
Merge tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo: imx soc changes for 3.11: * New SoCs i.MX6 Sololite and Vybrid VF610 support * imx5 and imx6 clock fixes and additions * Update clock driver to use of_clk_init() function * Refactor restart routine mxc_restart() to get it work for DT boot as well * Clean up mxc specific ulpi access ops * imx defconfig updates * tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: (29 commits) ARM: imx_v6_v7_defconfig: Enable Vybrid VF610 ARM: imx_v6_v7_defconfig: Enable imx-wm8962 by default ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresd ARM: imx_v6_v7_defconfig: Enable PWM and backlight options ARM: imx: Remove mxc specific ulpi access ops ARM: imx: add initial support for VF610 ARM: imx: add VF610 clock support ARM: imx_v6_v7_defconfig: enable parallel display ARM: imx: clk: No need to initialize phandle struct ARM: imx: irq-common: Include header to avoid sparse warning ARM: imx: Enable mx6 solo-lite support ARM: imx6: use common of_clk_init() call to initialize clocks ARM: imx6q: call of_clk_init() to register fixed rate clocks ARM: imx: imx_v6_v7_defconfig: Select CONFIG_DRM_IMX_TVE ARM: i.MX6: clk: add different DualLite MLB clock config ARM i.MX5: Add S/PDIF clocks ARM i.MX53: Add SATA clock ARM: imx6q: clk: add the eim_slow clock ARM: imx: remove MLB PLL from pllv3 ARM: imx: disable pll8_mlb in mx6q_clks ... Conflicts: arch/arm/Kconfig.debug (simple add/add conflict) Includes an update to 3.10-rc6 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig.debug13
-rw-r--r--arch/arm/boot/compressed/Makefile2
-rw-r--r--arch/arm/boot/compressed/debug.S28
-rw-r--r--arch/arm/boot/compressed/head-sa1100.S1
-rw-r--r--arch/arm/boot/compressed/head-shark.S1
-rw-r--r--arch/arm/boot/compressed/head.S5
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi4
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts5
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts5
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi20
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts20
-rw-r--r--arch/arm/boot/dts/omap5.dtsi3
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig10
-rw-r--r--arch/arm/include/asm/percpu.h11
-rw-r--r--arch/arm/include/debug/imx-uart.h10
-rw-r--r--arch/arm/kernel/topology.c2
-rw-r--r--arch/arm/mach-imx/Kconfig63
-rw-r--r--arch/arm/mach-imx/Makefile4
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c73
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c48
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c267
-rw-r--r--arch/arm/mach-imx/clk-pllv3.c10
-rw-r--r--arch/arm/mach-imx/clk-vf610.c319
-rw-r--r--arch/arm/mach-imx/clk.c35
-rw-r--r--arch/arm/mach-imx/clk.h4
-rw-r--r--arch/arm/mach-imx/common.h2
-rw-r--r--arch/arm/mach-imx/hardware.h1
-rw-r--r--arch/arm/mach-imx/imx25-dt.c2
-rw-r--r--arch/arm/mach-imx/imx27-dt.c2
-rw-r--r--arch/arm/mach-imx/imx31-dt.c2
-rw-r--r--arch/arm/mach-imx/imx51-dt.c2
-rw-r--r--arch/arm/mach-imx/irq-common.c1
-rw-r--r--arch/arm/mach-imx/mach-imx53.c3
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c81
-rw-r--r--arch/arm/mach-imx/mach-imx6sl.c52
-rw-r--r--arch/arm/mach-imx/mach-pca100.c4
-rw-r--r--arch/arm/mach-imx/mach-vf610.c48
-rw-r--r--arch/arm/mach-imx/mm-imx1.c2
-rw-r--r--arch/arm/mach-imx/mm-imx21.c2
-rw-r--r--arch/arm/mach-imx/mm-imx25.c2
-rw-r--r--arch/arm/mach-imx/mm-imx27.c2
-rw-r--r--arch/arm/mach-imx/mm-imx3.c4
-rw-r--r--arch/arm/mach-imx/mm-imx5.c3
-rw-r--r--arch/arm/mach-imx/system.c47
-rw-r--r--arch/arm/mach-imx/ulpi.c118
-rw-r--r--arch/arm/mach-imx/ulpi.h11
-rw-r--r--arch/arm/mach-kirkwood/mpp.c5
-rw-r--r--arch/arm/mach-omap2/clock36xx.c18
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c9
-rw-r--r--arch/arm/mach-omap2/pm34xx.c6
-rw-r--r--arch/arm/mach-prima2/pm.c6
-rw-r--r--arch/arm/mach-prima2/rstc.c6
-rw-r--r--arch/arm/plat-samsung/pm.c18
-rw-r--r--arch/mips/include/asm/mmu_context.h2
-rw-r--r--arch/mips/include/uapi/asm/kvm.h81
-rw-r--r--arch/mips/kernel/ftrace.c4
-rw-r--r--arch/mips/kernel/idle.c13
-rw-r--r--arch/mips/kvm/kvm_mips.c83
-rw-r--r--arch/powerpc/include/asm/cputable.h17
-rw-r--r--arch/powerpc/include/asm/exception-64s.h2
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h16
-rw-r--r--arch/powerpc/kernel/cputable.c8
-rw-r--r--arch/powerpc/kernel/entry_64.S28
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S92
-rw-r--r--arch/powerpc/kernel/irq.c2
-rw-r--r--arch/powerpc/kernel/pci-common.c4
-rw-r--r--arch/powerpc/kernel/process.c7
-rw-r--r--arch/powerpc/kernel/traps.c10
-rw-r--r--arch/powerpc/kvm/44x_tlb.c5
-rw-r--r--arch/powerpc/kvm/booke.c18
-rw-r--r--arch/powerpc/kvm/e500_mmu.c5
-rw-r--r--arch/powerpc/kvm/e500mc.c2
-rw-r--r--arch/powerpc/perf/core-book3s.c2
-rw-r--r--arch/powerpc/platforms/pseries/eeh_pseries.c12
-rw-r--r--arch/s390/include/asm/pgtable.h32
-rw-r--r--arch/s390/kernel/dumpstack.c12
-rw-r--r--arch/s390/kernel/irq.c64
-rw-r--r--arch/s390/kernel/sclp.S2
-rw-r--r--arch/s390/pci/pci.c33
-rw-r--r--arch/sparc/kernel/prom_common.c5
-rw-r--r--arch/x86/boot/compressed/eboot.c47
-rw-r--r--arch/x86/include/asm/efi.h7
-rw-r--r--arch/x86/include/uapi/asm/bootparam.h1
-rw-r--r--arch/x86/kernel/relocate_kernel_64.S2
-rw-r--r--arch/x86/mm/init.c6
-rw-r--r--arch/x86/platform/efi/efi.c188
-rw-r--r--arch/x86/tools/relocs.c4
-rw-r--r--arch/x86/xen/smp.c8
88 files changed, 1539 insertions, 707 deletions
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 7ef6f145f964..394d2a4064e1 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -251,6 +251,13 @@ choice
251 Say Y here if you want kernel low-level debugging support 251 Say Y here if you want kernel low-level debugging support
252 on i.MX6Q/DL. 252 on i.MX6Q/DL.
253 253
254 config DEBUG_IMX6SL_UART
255 bool "i.MX6SL Debug UART"
256 depends on SOC_IMX6SL
257 help
258 Say Y here if you want kernel low-level debugging support
259 on i.MX6SL.
260
254 config DEBUG_KEYSTONE_UART0 261 config DEBUG_KEYSTONE_UART0
255 bool "Kernel low-level debugging on KEYSTONE2 using UART0" 262 bool "Kernel low-level debugging on KEYSTONE2 using UART0"
256 depends on ARCH_KEYSTONE 263 depends on ARCH_KEYSTONE
@@ -578,7 +585,8 @@ config DEBUG_IMX_UART_PORT
578 DEBUG_IMX35_UART || \ 585 DEBUG_IMX35_UART || \
579 DEBUG_IMX51_UART || \ 586 DEBUG_IMX51_UART || \
580 DEBUG_IMX53_UART || \ 587 DEBUG_IMX53_UART || \
581 DEBUG_IMX6Q_UART 588 DEBUG_IMX6Q_UART || \
589 DEBUG_IMX6SL_UART
582 default 1 590 default 1
583 depends on ARCH_MXC 591 depends on ARCH_MXC
584 help 592 help
@@ -677,7 +685,8 @@ config DEBUG_LL_INCLUDE
677 DEBUG_IMX35_UART || \ 685 DEBUG_IMX35_UART || \
678 DEBUG_IMX51_UART || \ 686 DEBUG_IMX51_UART || \
679 DEBUG_IMX53_UART ||\ 687 DEBUG_IMX53_UART ||\
680 DEBUG_IMX6Q_UART 688 DEBUG_IMX6Q_UART || \
689 DEBUG_IMX6SL_UART
681 default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \ 690 default "debug/keystone.S" if DEBUG_KEYSTONE_UART0 || \
682 DEBUG_KEYSTONE_UART1 691 DEBUG_KEYSTONE_UART1
683 default "debug/mvebu.S" if DEBUG_MVEBU_UART || \ 692 default "debug/mvebu.S" if DEBUG_MVEBU_UART || \
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3580d57ea218..79e9bdbfc491 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -124,7 +124,7 @@ KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
124endif 124endif
125 125
126ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj) 126ccflags-y := -fpic -mno-single-pic-base -fno-builtin -I$(obj)
127asflags-y := -Wa,-march=all -DZIMAGE 127asflags-y := -DZIMAGE
128 128
129# Supply kernel BSS size to the decompressor via a linker symbol. 129# Supply kernel BSS size to the decompressor via a linker symbol.
130KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \ 130KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6e8382d5b7a4..5392ee63338f 100644
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -1,6 +1,8 @@
1#include <linux/linkage.h> 1#include <linux/linkage.h>
2#include <asm/assembler.h> 2#include <asm/assembler.h>
3 3
4#ifndef CONFIG_DEBUG_SEMIHOSTING
5
4#include CONFIG_DEBUG_LL_INCLUDE 6#include CONFIG_DEBUG_LL_INCLUDE
5 7
6ENTRY(putc) 8ENTRY(putc)
@@ -10,3 +12,29 @@ ENTRY(putc)
10 busyuart r3, r1 12 busyuart r3, r1
11 mov pc, lr 13 mov pc, lr
12ENDPROC(putc) 14ENDPROC(putc)
15
16#else
17
18ENTRY(putc)
19 adr r1, 1f
20 ldmia r1, {r2, r3}
21 add r2, r2, r1
22 ldr r1, [r2, r3]
23 strb r0, [r1]
24 mov r0, #0x03 @ SYS_WRITEC
25 ARM( svc #0x123456 )
26 THUMB( svc #0xab )
27 mov pc, lr
28 .align 2
291: .word _GLOBAL_OFFSET_TABLE_ - .
30 .word semi_writec_buf(GOT)
31ENDPROC(putc)
32
33 .bss
34 .global semi_writec_buf
35 .type semi_writec_buf, %object
36semi_writec_buf:
37 .space 4
38 .size semi_writec_buf, 4
39
40#endif
diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S
index 6179d94dd5c6..3115e313d9f6 100644
--- a/arch/arm/boot/compressed/head-sa1100.S
+++ b/arch/arm/boot/compressed/head-sa1100.S
@@ -11,6 +11,7 @@
11#include <asm/mach-types.h> 11#include <asm/mach-types.h>
12 12
13 .section ".start", "ax" 13 .section ".start", "ax"
14 .arch armv4
14 15
15__SA1100_start: 16__SA1100_start:
16 17
diff --git a/arch/arm/boot/compressed/head-shark.S b/arch/arm/boot/compressed/head-shark.S
index 089c560e07f1..92b56897ed64 100644
--- a/arch/arm/boot/compressed/head-shark.S
+++ b/arch/arm/boot/compressed/head-shark.S
@@ -18,6 +18,7 @@
18 18
19 .section ".start", "ax" 19 .section ".start", "ax"
20 20
21 .arch armv4
21 b __beginning 22 b __beginning
22 23
23__ofw_data: .long 0 @ the number of memory blocks 24__ofw_data: .long 0 @ the number of memory blocks
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index fe4d9c3ad761..032a8d987148 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -11,6 +11,7 @@
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <asm/assembler.h> 12#include <asm/assembler.h>
13 13
14 .arch armv7-a
14/* 15/*
15 * Debugging stuff 16 * Debugging stuff
16 * 17 *
@@ -805,8 +806,8 @@ call_cache_fn: adr r12, proc_types
805 .align 2 806 .align 2
806 .type proc_types,#object 807 .type proc_types,#object
807proc_types: 808proc_types:
808 .word 0x00000000 @ old ARM ID 809 .word 0x41000000 @ old ARM ID
809 .word 0x0000f000 810 .word 0xff00f000
810 mov pc, lr 811 mov pc, lr
811 THUMB( nop ) 812 THUMB( nop )
812 mov pc, lr 813 mov pc, lr
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 1460d9b88adf..8e1248f01fab 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -409,8 +409,8 @@
409 ti,hwmods = "gpmc"; 409 ti,hwmods = "gpmc";
410 reg = <0x50000000 0x2000>; 410 reg = <0x50000000 0x2000>;
411 interrupts = <100>; 411 interrupts = <100>;
412 num-cs = <7>; 412 gpmc,num-cs = <7>;
413 num-waitpins = <2>; 413 gpmc,num-waitpins = <2>;
414 #address-cells = <2>; 414 #address-cells = <2>;
415 #size-cells = <1>; 415 #size-cells = <1>;
416 status = "disabled"; 416 status = "disabled";
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 3ee63d128e27..76db557adbe7 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -39,8 +39,9 @@
39 }; 39 };
40 40
41 soc { 41 soc {
42 ranges = <0 0 0xd0000000 0x100000 42 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
43 0xf0000000 0 0xf0000000 0x1000000>; 43 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
44 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>;
44 45
45 internal-regs { 46 internal-regs {
46 serial@12000 { 47 serial@12000 {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 46b785064dd8..fdea75c73411 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -27,8 +27,9 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 ranges = <0 0 0xd0000000 0x100000 30 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
31 0xf0000000 0 0xf0000000 0x8000000>; 31 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
32 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
32 33
33 internal-regs { 34 internal-regs {
34 serial@12000 { 35 serial@12000 {
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 03bd60deb52b..eeb734e25709 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -56,9 +56,23 @@
56 }; 56 };
57}; 57};
58 58
59&omap4_pmx_wkup {
60 pinctrl-names = "default";
61 pinctrl-0 = <
62 &twl6030_wkup_pins
63 >;
64
65 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
66 pinctrl-single,pins = <
67 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
68 >;
69 };
70};
71
59&omap4_pmx_core { 72&omap4_pmx_core {
60 pinctrl-names = "default"; 73 pinctrl-names = "default";
61 pinctrl-0 = < 74 pinctrl-0 = <
75 &twl6030_pins
62 &twl6040_pins 76 &twl6040_pins
63 &mcpdm_pins 77 &mcpdm_pins
64 &mcbsp1_pins 78 &mcbsp1_pins
@@ -66,6 +80,12 @@
66 &tpd12s015_pins 80 &tpd12s015_pins
67 >; 81 >;
68 82
83 twl6030_pins: pinmux_twl6030_pins {
84 pinctrl-single,pins = <
85 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
86 >;
87 };
88
69 twl6040_pins: pinmux_twl6040_pins { 89 twl6040_pins: pinmux_twl6040_pins {
70 pinctrl-single,pins = < 90 pinctrl-single,pins = <
71 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ 91 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index a35d9cd58063..98505a2ef162 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -142,9 +142,23 @@
142 }; 142 };
143}; 143};
144 144
145&omap4_pmx_wkup {
146 pinctrl-names = "default";
147 pinctrl-0 = <
148 &twl6030_wkup_pins
149 >;
150
151 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
152 pinctrl-single,pins = <
153 0x14 0x2 /* fref_clk0_out.sys_drm_msecure OUTPUT | MODE2 */
154 >;
155 };
156};
157
145&omap4_pmx_core { 158&omap4_pmx_core {
146 pinctrl-names = "default"; 159 pinctrl-names = "default";
147 pinctrl-0 = < 160 pinctrl-0 = <
161 &twl6030_pins
148 &twl6040_pins 162 &twl6040_pins
149 &mcpdm_pins 163 &mcpdm_pins
150 &dmic_pins 164 &dmic_pins
@@ -179,6 +193,12 @@
179 >; 193 >;
180 }; 194 };
181 195
196 twl6030_pins: pinmux_twl6030_pins {
197 pinctrl-single,pins = <
198 0x15e 0x4118 /* sys_nirq1.sys_nirq1 OMAP_WAKEUP_EN | INPUT_PULLUP | MODE0 */
199 >;
200 };
201
182 twl6040_pins: pinmux_twl6040_pins { 202 twl6040_pins: pinmux_twl6040_pins {
183 pinctrl-single,pins = < 203 pinctrl-single,pins = <
184 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */ 204 0xe0 0x3 /* hdq_sio.gpio_127 OUTPUT | MODE3 */
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 3dd7ff825828..635cae283011 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -538,6 +538,7 @@
538 interrupts = <0 41 0x4>; 538 interrupts = <0 41 0x4>;
539 ti,hwmods = "timer5"; 539 ti,hwmods = "timer5";
540 ti,timer-dsp; 540 ti,timer-dsp;
541 ti,timer-pwm;
541 }; 542 };
542 543
543 timer6: timer@4013a000 { 544 timer6: timer@4013a000 {
@@ -574,6 +575,7 @@
574 reg = <0x4803e000 0x80>; 575 reg = <0x4803e000 0x80>;
575 interrupts = <0 45 0x4>; 576 interrupts = <0 45 0x4>;
576 ti,hwmods = "timer9"; 577 ti,hwmods = "timer9";
578 ti,timer-pwm;
577 }; 579 };
578 580
579 timer10: timer@48086000 { 581 timer10: timer@48086000 {
@@ -581,6 +583,7 @@
581 reg = <0x48086000 0x80>; 583 reg = <0x48086000 0x80>;
582 interrupts = <0 46 0x4>; 584 interrupts = <0 46 0x4>;
583 ti,hwmods = "timer10"; 585 ti,hwmods = "timer10";
586 ti,timer-pwm;
584 }; 587 };
585 588
586 timer11: timer@48088000 { 589 timer11: timer@48088000 {
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 6ec010f248b5..06686e7303a9 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -37,6 +37,8 @@ CONFIG_MACH_IMX51_DT=y
37CONFIG_MACH_EUKREA_CPUIMX51SD=y 37CONFIG_MACH_EUKREA_CPUIMX51SD=y
38CONFIG_SOC_IMX53=y 38CONFIG_SOC_IMX53=y
39CONFIG_SOC_IMX6Q=y 39CONFIG_SOC_IMX6Q=y
40CONFIG_SOC_IMX6SL=y
41CONFIG_SOC_VF610=y
40CONFIG_MXC_PWM=y 42CONFIG_MXC_PWM=y
41CONFIG_SMP=y 43CONFIG_SMP=y
42CONFIG_VMSPLIT_2G=y 44CONFIG_VMSPLIT_2G=y
@@ -47,6 +49,7 @@ CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
47CONFIG_VFP=y 49CONFIG_VFP=y
48CONFIG_NEON=y 50CONFIG_NEON=y
49CONFIG_BINFMT_MISC=m 51CONFIG_BINFMT_MISC=m
52CONFIG_PM_RUNTIME=y
50CONFIG_PM_DEBUG=y 53CONFIG_PM_DEBUG=y
51CONFIG_PM_TEST_SUSPEND=y 54CONFIG_PM_TEST_SUSPEND=y
52CONFIG_NET=y 55CONFIG_NET=y
@@ -170,6 +173,7 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
170CONFIG_LCD_CLASS_DEVICE=y 173CONFIG_LCD_CLASS_DEVICE=y
171CONFIG_LCD_L4F00242T03=y 174CONFIG_LCD_L4F00242T03=y
172CONFIG_BACKLIGHT_CLASS_DEVICE=y 175CONFIG_BACKLIGHT_CLASS_DEVICE=y
176CONFIG_BACKLIGHT_PWM=y
173CONFIG_FRAMEBUFFER_CONSOLE=y 177CONFIG_FRAMEBUFFER_CONSOLE=y
174CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y 178CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
175CONFIG_FONTS=y 179CONFIG_FONTS=y
@@ -182,6 +186,7 @@ CONFIG_SND_SOC=y
182CONFIG_SND_IMX_SOC=y 186CONFIG_SND_IMX_SOC=y
183CONFIG_SND_SOC_PHYCORE_AC97=y 187CONFIG_SND_SOC_PHYCORE_AC97=y
184CONFIG_SND_SOC_EUKREA_TLV320=y 188CONFIG_SND_SOC_EUKREA_TLV320=y
189CONFIG_SND_SOC_IMX_WM8962=y
185CONFIG_SND_SOC_IMX_SGTL5000=y 190CONFIG_SND_SOC_IMX_SGTL5000=y
186CONFIG_SND_SOC_IMX_MC13783=y 191CONFIG_SND_SOC_IMX_MC13783=y
187CONFIG_USB=y 192CONFIG_USB=y
@@ -208,10 +213,15 @@ CONFIG_IMX_SDMA=y
208CONFIG_MXS_DMA=y 213CONFIG_MXS_DMA=y
209CONFIG_STAGING=y 214CONFIG_STAGING=y
210CONFIG_DRM_IMX=y 215CONFIG_DRM_IMX=y
216CONFIG_DRM_IMX_TVE=y
217CONFIG_DRM_IMX_FB_HELPER=y
218CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
211CONFIG_DRM_IMX_IPUV3_CORE=y 219CONFIG_DRM_IMX_IPUV3_CORE=y
212CONFIG_DRM_IMX_IPUV3=y 220CONFIG_DRM_IMX_IPUV3=y
213CONFIG_COMMON_CLK_DEBUG=y 221CONFIG_COMMON_CLK_DEBUG=y
214# CONFIG_IOMMU_SUPPORT is not set 222# CONFIG_IOMMU_SUPPORT is not set
223CONFIG_PWM=y
224CONFIG_PWM_IMX=y
215CONFIG_EXT2_FS=y 225CONFIG_EXT2_FS=y
216CONFIG_EXT2_FS_XATTR=y 226CONFIG_EXT2_FS_XATTR=y
217CONFIG_EXT2_FS_POSIX_ACL=y 227CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/include/asm/percpu.h b/arch/arm/include/asm/percpu.h
index 968c0a14e0a3..209e6504922e 100644
--- a/arch/arm/include/asm/percpu.h
+++ b/arch/arm/include/asm/percpu.h
@@ -30,8 +30,15 @@ static inline void set_my_cpu_offset(unsigned long off)
30static inline unsigned long __my_cpu_offset(void) 30static inline unsigned long __my_cpu_offset(void)
31{ 31{
32 unsigned long off; 32 unsigned long off;
33 /* Read TPIDRPRW */ 33 register unsigned long *sp asm ("sp");
34 asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : : "memory"); 34
35 /*
36 * Read TPIDRPRW.
37 * We want to allow caching the value, so avoid using volatile and
38 * instead use a fake stack read to hazard against barrier().
39 */
40 asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) : "Q" (*sp));
41
35 return off; 42 return off;
36} 43}
37#define __my_cpu_offset __my_cpu_offset() 44#define __my_cpu_offset __my_cpu_offset()
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 91d38e38a0b4..29da84e183f4 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -65,6 +65,14 @@
65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR 65#define IMX6Q_UART_BASE_ADDR(n) IMX6Q_UART##n##_BASE_ADDR
66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n) 66#define IMX6Q_UART_BASE(n) IMX6Q_UART_BASE_ADDR(n)
67 67
68#define IMX6SL_UART1_BASE_ADDR 0x02020000
69#define IMX6SL_UART2_BASE_ADDR 0x02024000
70#define IMX6SL_UART3_BASE_ADDR 0x02034000
71#define IMX6SL_UART4_BASE_ADDR 0x02038000
72#define IMX6SL_UART5_BASE_ADDR 0x02018000
73#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
74#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
75
68#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 76#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
69 77
70#ifdef CONFIG_DEBUG_IMX1_UART 78#ifdef CONFIG_DEBUG_IMX1_UART
@@ -83,6 +91,8 @@
83#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53) 91#define UART_PADDR IMX_DEBUG_UART_BASE(IMX53)
84#elif defined(CONFIG_DEBUG_IMX6Q_UART) 92#elif defined(CONFIG_DEBUG_IMX6Q_UART)
85#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 93#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
94#elif defined(CONFIG_DEBUG_IMX6SL_UART)
95#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
86#endif 96#endif
87 97
88#endif /* __DEBUG_IMX_UART_H */ 98#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index f10316b4ecdc..c5a59546a256 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -13,6 +13,7 @@
13 13
14#include <linux/cpu.h> 14#include <linux/cpu.h>
15#include <linux/cpumask.h> 15#include <linux/cpumask.h>
16#include <linux/export.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/percpu.h> 18#include <linux/percpu.h>
18#include <linux/node.h> 19#include <linux/node.h>
@@ -200,6 +201,7 @@ static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
200 * cpu topology table 201 * cpu topology table
201 */ 202 */
202struct cputopo_arm cpu_topology[NR_CPUS]; 203struct cputopo_arm cpu_topology[NR_CPUS];
204EXPORT_SYMBOL_GPL(cpu_topology);
203 205
204const struct cpumask *cpu_coregroup_mask(int cpu) 206const struct cpumask *cpu_coregroup_mask(int cpu)
205{ 207{
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index ba44328464f3..f25cf888f3d4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -56,9 +56,6 @@ config MXC_USE_EPIT
56 uses the same clocks as the GPT. Anyway, on some systems the GPT 56 uses the same clocks as the GPT. Anyway, on some systems the GPT
57 may be in use for other purposes. 57 may be in use for other purposes.
58 58
59config MXC_ULPI
60 bool
61
62config ARCH_HAS_RNGA 59config ARCH_HAS_RNGA
63 bool 60 bool
64 61
@@ -233,7 +230,7 @@ config MACH_EUKREA_CPUIMX25SD
233 select IMX_HAVE_PLATFORM_MXC_EHCI 230 select IMX_HAVE_PLATFORM_MXC_EHCI
234 select IMX_HAVE_PLATFORM_MXC_NAND 231 select IMX_HAVE_PLATFORM_MXC_NAND
235 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 232 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
236 select MXC_ULPI if USB_ULPI 233 select USB_ULPI_VIEWPORT if USB_ULPI
237 select SOC_IMX25 234 select SOC_IMX25
238 235
239choice 236choice
@@ -284,7 +281,7 @@ config MACH_PCM038
284 select IMX_HAVE_PLATFORM_MXC_NAND 281 select IMX_HAVE_PLATFORM_MXC_NAND
285 select IMX_HAVE_PLATFORM_MXC_W1 282 select IMX_HAVE_PLATFORM_MXC_W1
286 select IMX_HAVE_PLATFORM_SPI_IMX 283 select IMX_HAVE_PLATFORM_SPI_IMX
287 select MXC_ULPI if USB_ULPI 284 select USB_ULPI_VIEWPORT if USB_ULPI
288 select SOC_IMX27 285 select SOC_IMX27
289 help 286 help
290 Include support for phyCORE-i.MX27 (aka pcm038) platform. This 287 Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -314,7 +311,7 @@ config MACH_CPUIMX27
314 select IMX_HAVE_PLATFORM_MXC_EHCI 311 select IMX_HAVE_PLATFORM_MXC_EHCI
315 select IMX_HAVE_PLATFORM_MXC_NAND 312 select IMX_HAVE_PLATFORM_MXC_NAND
316 select IMX_HAVE_PLATFORM_MXC_W1 313 select IMX_HAVE_PLATFORM_MXC_W1
317 select MXC_ULPI if USB_ULPI 314 select USB_ULPI_VIEWPORT if USB_ULPI
318 select SOC_IMX27 315 select SOC_IMX27
319 help 316 help
320 Include support for Eukrea CPUIMX27 platform. This includes 317 Include support for Eukrea CPUIMX27 platform. This includes
@@ -369,7 +366,7 @@ config MACH_MX27_3DS
369 select IMX_HAVE_PLATFORM_MXC_MMC 366 select IMX_HAVE_PLATFORM_MXC_MMC
370 select IMX_HAVE_PLATFORM_SPI_IMX 367 select IMX_HAVE_PLATFORM_SPI_IMX
371 select MXC_DEBUG_BOARD 368 select MXC_DEBUG_BOARD
372 select MXC_ULPI if USB_ULPI 369 select USB_ULPI_VIEWPORT if USB_ULPI
373 select SOC_IMX27 370 select SOC_IMX27
374 help 371 help
375 Include support for MX27PDK platform. This includes specific 372 Include support for MX27PDK platform. This includes specific
@@ -414,7 +411,7 @@ config MACH_PCA100
414 select IMX_HAVE_PLATFORM_MXC_NAND 411 select IMX_HAVE_PLATFORM_MXC_NAND
415 select IMX_HAVE_PLATFORM_MXC_W1 412 select IMX_HAVE_PLATFORM_MXC_W1
416 select IMX_HAVE_PLATFORM_SPI_IMX 413 select IMX_HAVE_PLATFORM_SPI_IMX
417 select MXC_ULPI if USB_ULPI 414 select USB_ULPI_VIEWPORT if USB_ULPI
418 select SOC_IMX27 415 select SOC_IMX27
419 help 416 help
420 Include support for phyCARD-s (aka pca100) platform. This 417 Include support for phyCARD-s (aka pca100) platform. This
@@ -481,7 +478,7 @@ config MACH_MX31LILLY
481 select IMX_HAVE_PLATFORM_MXC_EHCI 478 select IMX_HAVE_PLATFORM_MXC_EHCI
482 select IMX_HAVE_PLATFORM_MXC_MMC 479 select IMX_HAVE_PLATFORM_MXC_MMC
483 select IMX_HAVE_PLATFORM_SPI_IMX 480 select IMX_HAVE_PLATFORM_SPI_IMX
484 select MXC_ULPI if USB_ULPI 481 select USB_ULPI_VIEWPORT if USB_ULPI
485 select SOC_IMX31 482 select SOC_IMX31
486 help 483 help
487 Include support for mx31 based LILLY1131 modules. This includes 484 Include support for mx31 based LILLY1131 modules. This includes
@@ -497,7 +494,7 @@ config MACH_MX31LITE
497 select IMX_HAVE_PLATFORM_MXC_RTC 494 select IMX_HAVE_PLATFORM_MXC_RTC
498 select IMX_HAVE_PLATFORM_SPI_IMX 495 select IMX_HAVE_PLATFORM_SPI_IMX
499 select LEDS_GPIO_REGISTER 496 select LEDS_GPIO_REGISTER
500 select MXC_ULPI if USB_ULPI 497 select USB_ULPI_VIEWPORT if USB_ULPI
501 select SOC_IMX31 498 select SOC_IMX31
502 help 499 help
503 Include support for MX31 LITEKIT platform. This includes specific 500 Include support for MX31 LITEKIT platform. This includes specific
@@ -514,7 +511,7 @@ config MACH_PCM037
514 select IMX_HAVE_PLATFORM_MXC_MMC 511 select IMX_HAVE_PLATFORM_MXC_MMC
515 select IMX_HAVE_PLATFORM_MXC_NAND 512 select IMX_HAVE_PLATFORM_MXC_NAND
516 select IMX_HAVE_PLATFORM_MXC_W1 513 select IMX_HAVE_PLATFORM_MXC_W1
517 select MXC_ULPI if USB_ULPI 514 select USB_ULPI_VIEWPORT if USB_ULPI
518 select SOC_IMX31 515 select SOC_IMX31
519 help 516 help
520 Include support for Phytec pcm037 platform. This includes 517 Include support for Phytec pcm037 platform. This includes
@@ -544,7 +541,7 @@ config MACH_MX31_3DS
544 select IMX_HAVE_PLATFORM_MXC_NAND 541 select IMX_HAVE_PLATFORM_MXC_NAND
545 select IMX_HAVE_PLATFORM_SPI_IMX 542 select IMX_HAVE_PLATFORM_SPI_IMX
546 select MXC_DEBUG_BOARD 543 select MXC_DEBUG_BOARD
547 select MXC_ULPI if USB_ULPI 544 select USB_ULPI_VIEWPORT if USB_ULPI
548 select SOC_IMX31 545 select SOC_IMX31
549 help 546 help
550 Include support for MX31PDK (3DS) platform. This includes specific 547 Include support for MX31PDK (3DS) platform. This includes specific
@@ -571,7 +568,7 @@ config MACH_MX31MOBOARD
571 select IMX_HAVE_PLATFORM_MXC_MMC 568 select IMX_HAVE_PLATFORM_MXC_MMC
572 select IMX_HAVE_PLATFORM_SPI_IMX 569 select IMX_HAVE_PLATFORM_SPI_IMX
573 select LEDS_GPIO_REGISTER 570 select LEDS_GPIO_REGISTER
574 select MXC_ULPI if USB_ULPI 571 select USB_ULPI_VIEWPORT if USB_ULPI
575 select SOC_IMX31 572 select SOC_IMX31
576 help 573 help
577 Include support for mx31moboard platform. This includes specific 574 Include support for mx31moboard platform. This includes specific
@@ -595,7 +592,7 @@ config MACH_ARMADILLO5X0
595 select IMX_HAVE_PLATFORM_MXC_EHCI 592 select IMX_HAVE_PLATFORM_MXC_EHCI
596 select IMX_HAVE_PLATFORM_MXC_MMC 593 select IMX_HAVE_PLATFORM_MXC_MMC
597 select IMX_HAVE_PLATFORM_MXC_NAND 594 select IMX_HAVE_PLATFORM_MXC_NAND
598 select MXC_ULPI if USB_ULPI 595 select USB_ULPI_VIEWPORT if USB_ULPI
599 select SOC_IMX31 596 select SOC_IMX31
600 help 597 help
601 Include support for Atmark Armadillo-500 platform. This includes 598 Include support for Atmark Armadillo-500 platform. This includes
@@ -639,7 +636,7 @@ config MACH_PCM043
639 select IMX_HAVE_PLATFORM_MXC_EHCI 636 select IMX_HAVE_PLATFORM_MXC_EHCI
640 select IMX_HAVE_PLATFORM_MXC_NAND 637 select IMX_HAVE_PLATFORM_MXC_NAND
641 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 638 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
642 select MXC_ULPI if USB_ULPI 639 select USB_ULPI_VIEWPORT if USB_ULPI
643 select SOC_IMX35 640 select SOC_IMX35
644 help 641 help
645 Include support for Phytec pcm043 platform. This includes 642 Include support for Phytec pcm043 platform. This includes
@@ -673,7 +670,7 @@ config MACH_EUKREA_CPUIMX35SD
673 select IMX_HAVE_PLATFORM_MXC_EHCI 670 select IMX_HAVE_PLATFORM_MXC_EHCI
674 select IMX_HAVE_PLATFORM_MXC_NAND 671 select IMX_HAVE_PLATFORM_MXC_NAND
675 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX 672 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
676 select MXC_ULPI if USB_ULPI 673 select USB_ULPI_VIEWPORT if USB_ULPI
677 select SOC_IMX35 674 select SOC_IMX35
678 help 675 help
679 Include support for Eukrea CPUIMX35 platform. This includes 676 Include support for Eukrea CPUIMX35 platform. This includes
@@ -816,6 +813,40 @@ config SOC_IMX6Q
816 help 813 help
817 This enables support for Freescale i.MX6 Quad processor. 814 This enables support for Freescale i.MX6 Quad processor.
818 815
816config SOC_IMX6SL
817 bool "i.MX6 SoloLite support"
818 select ARM_ERRATA_754322
819 select ARM_ERRATA_775420
820 select ARM_GIC
821 select CPU_V7
822 select HAVE_IMX_ANATOP
823 select HAVE_IMX_GPC
824 select HAVE_IMX_MMDC
825 select HAVE_IMX_SRC
826 select PINCTRL
827 select PINCTRL_IMX6SL
828 select PL310_ERRATA_588369 if CACHE_PL310
829 select PL310_ERRATA_727915 if CACHE_PL310
830 select PL310_ERRATA_769419 if CACHE_PL310
831
832 help
833 This enables support for Freescale i.MX6 SoloLite processor.
834
835config SOC_VF610
836 bool "Vybrid Family VF610 support"
837 select CPU_V7
838 select ARM_GIC
839 select CLKSRC_OF
840 select PINCTRL
841 select PINCTRL_VF610
842 select VF_PIT_TIMER
843 select PL310_ERRATA_588369 if CACHE_PL310
844 select PL310_ERRATA_727915 if CACHE_PL310
845 select PL310_ERRATA_769419 if CACHE_PL310
846
847 help
848 This enable support for Freescale Vybrid VF610 processor.
849
819endif 850endif
820 851
821source "arch/arm/mach-imx/devices/Kconfig" 852source "arch/arm/mach-imx/devices/Kconfig"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 70ae7c490ac0..e20f22d58fd8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -23,7 +23,6 @@ obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
23obj-$(CONFIG_MXC_TZIC) += tzic.o 23obj-$(CONFIG_MXC_TZIC) += tzic.o
24obj-$(CONFIG_MXC_AVIC) += avic.o 24obj-$(CONFIG_MXC_AVIC) += avic.o
25 25
26obj-$(CONFIG_MXC_ULPI) += ulpi.o
27obj-$(CONFIG_MXC_USE_EPIT) += epit.o 26obj-$(CONFIG_MXC_USE_EPIT) += epit.o
28obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o 27obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
29 28
@@ -98,6 +97,7 @@ AFLAGS_headsmp.o :=-Wa,-march=armv7-a
98obj-$(CONFIG_SMP) += headsmp.o platsmp.o 97obj-$(CONFIG_SMP) += headsmp.o platsmp.o
99obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 98obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
100obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 99obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
100obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
101 101
102ifeq ($(CONFIG_PM),y) 102ifeq ($(CONFIG_PM),y)
103obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o 103obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o headsmp.o
@@ -111,4 +111,6 @@ obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
111obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 111obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
112obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 112obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
113 113
114obj-$(CONFIG_SOC_VF610) += clk-vf610.o mach-vf610.o
115
114obj-y += devices/ 116obj-y += devices/
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 6fc486b6a3c6..04b1bad68350 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -73,6 +73,12 @@ static const char *mx53_cko2_sel[] = {
73 "tve_sel", "lp_apm", 73 "tve_sel", "lp_apm",
74 "uart_root", "dummy"/* spdif0_clk_root */, 74 "uart_root", "dummy"/* spdif0_clk_root */,
75 "dummy", "dummy", }; 75 "dummy", "dummy", };
76static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
77static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
78static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
79static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
80static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
81
76 82
77enum imx5_clks { 83enum imx5_clks {
78 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred, 84 dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -110,7 +116,9 @@ enum imx5_clks {
110 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate, 116 owire_gate, gpu3d_s, gpu2d_s, gpu3d_gate, gpu2d_gate, garb_gate,
111 cko1_sel, cko1_podf, cko1, 117 cko1_sel, cko1_podf, cko1,
112 cko2_sel, cko2_podf, cko2, 118 cko2_sel, cko2_podf, cko2,
113 srtc_gate, pata_gate, 119 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
120 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
121 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
114 clk_max 122 clk_max
115}; 123};
116 124
@@ -123,11 +131,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
123{ 131{
124 int i; 132 int i;
125 133
134 of_clk_init(NULL);
135
126 clk[dummy] = imx_clk_fixed("dummy", 0); 136 clk[dummy] = imx_clk_fixed("dummy", 0);
127 clk[ckil] = imx_clk_fixed("ckil", rate_ckil); 137 clk[ckil] = imx_obtain_fixed_clock("ckil", rate_ckil);
128 clk[osc] = imx_clk_fixed("osc", rate_osc); 138 clk[osc] = imx_obtain_fixed_clock("osc", rate_osc);
129 clk[ckih1] = imx_clk_fixed("ckih1", rate_ckih1); 139 clk[ckih1] = imx_obtain_fixed_clock("ckih1", rate_ckih1);
130 clk[ckih2] = imx_clk_fixed("ckih2", rate_ckih2); 140 clk[ckih2] = imx_obtain_fixed_clock("ckih2", rate_ckih2);
131 141
132 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, 142 clk[lp_apm] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
133 lp_apm_sel, ARRAY_SIZE(lp_apm_sel)); 143 lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
@@ -267,6 +277,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
267 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); 277 clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
268 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); 278 clk[srtc_gate] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
269 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); 279 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
280 clk[spdif0_sel] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
281 clk[spdif0_pred] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
282 clk[spdif0_podf] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
283 clk[spdif0_com_s] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
284 spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
285 clk[spdif0_gate] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
286 clk[spdif_ipg_gate] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
270 287
271 for (i = 0; i < ARRAY_SIZE(clk); i++) 288 for (i = 0; i < ARRAY_SIZE(clk); i++)
272 if (IS_ERR(clk[i])) 289 if (IS_ERR(clk[i]))
@@ -378,6 +395,15 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
378 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); 395 clk[mipi_hsc2_gate] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8);
379 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); 396 clk[mipi_esc_gate] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10);
380 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); 397 clk[mipi_hsp_gate] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12);
398 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
399 mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
400 clk[spdif1_sel] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
401 spdif_sel, ARRAY_SIZE(spdif_sel));
402 clk[spdif1_pred] = imx_clk_divider("spdif1_podf", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
403 clk[spdif1_podf] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
404 clk[spdif1_com_sel] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
405 mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
406 clk[spdif1_gate] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
381 407
382 for (i = 0; i < ARRAY_SIZE(clk); i++) 408 for (i = 0; i < ARRAY_SIZE(clk); i++)
383 if (IS_ERR(clk[i])) 409 if (IS_ERR(clk[i]))
@@ -485,6 +511,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
485 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); 511 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
486 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); 512 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
487 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 513 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
514 clk[sata_gate] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
488 515
489 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, 516 clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
490 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel)); 517 mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
@@ -495,6 +522,8 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
495 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel)); 522 mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
496 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); 523 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
497 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); 524 clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
525 clk[spdif_xtal_sel] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
526 mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
498 527
499 for (i = 0; i < ARRAY_SIZE(clk); i++) 528 for (i = 0; i < ARRAY_SIZE(clk); i++)
500 if (IS_ERR(clk[i])) 529 if (IS_ERR(clk[i]))
@@ -542,42 +571,12 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
542 return 0; 571 return 0;
543} 572}
544 573
545#ifdef CONFIG_OF
546static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
547 unsigned long *ckih1, unsigned long *ckih2)
548{
549 struct device_node *np;
550
551 /* retrieve the freqency of fixed clocks from device tree */
552 for_each_compatible_node(np, NULL, "fixed-clock") {
553 u32 rate;
554 if (of_property_read_u32(np, "clock-frequency", &rate))
555 continue;
556
557 if (of_device_is_compatible(np, "fsl,imx-ckil"))
558 *ckil = rate;
559 else if (of_device_is_compatible(np, "fsl,imx-osc"))
560 *osc = rate;
561 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
562 *ckih1 = rate;
563 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
564 *ckih2 = rate;
565 }
566}
567
568int __init mx51_clocks_init_dt(void) 574int __init mx51_clocks_init_dt(void)
569{ 575{
570 unsigned long ckil, osc, ckih1, ckih2; 576 return mx51_clocks_init(0, 0, 0, 0);
571
572 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
573 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
574} 577}
575 578
576int __init mx53_clocks_init_dt(void) 579int __init mx53_clocks_init_dt(void)
577{ 580{
578 unsigned long ckil, osc, ckih1, ckih2; 581 return mx53_clocks_init(0, 0, 0, 0);
579
580 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
581 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
582} 582}
583#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 4e3148ce852d..4282e99f5ca1 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -238,7 +238,7 @@ enum mx6q_clks {
238 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 238 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
239 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 239 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
240 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 240 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
241 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, clk_max 241 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max
242}; 242};
243 243
244static struct clk *clk[clk_max]; 244static struct clk *clk[clk_max];
@@ -270,27 +270,16 @@ static struct clk_div_table video_div_table[] = {
270 { } 270 { }
271}; 271};
272 272
273int __init mx6q_clocks_init(void) 273static void __init imx6q_clocks_init(struct device_node *ccm_node)
274{ 274{
275 struct device_node *np; 275 struct device_node *np;
276 void __iomem *base; 276 void __iomem *base;
277 int i, irq; 277 int i, irq;
278 278
279 clk[dummy] = imx_clk_fixed("dummy", 0); 279 clk[dummy] = imx_clk_fixed("dummy", 0);
280 280 clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
281 /* retrieve the freqency of fixed clocks from device tree */ 281 clk[ckih] = imx_obtain_fixed_clock("ckih1", 0);
282 for_each_compatible_node(np, NULL, "fixed-clock") { 282 clk[osc] = imx_obtain_fixed_clock("osc", 0);
283 u32 rate;
284 if (of_property_read_u32(np, "clock-frequency", &rate))
285 continue;
286
287 if (of_device_is_compatible(np, "fsl,imx-ckil"))
288 clk[ckil] = imx_clk_fixed("ckil", rate);
289 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
290 clk[ckih] = imx_clk_fixed("ckih", rate);
291 else if (of_device_is_compatible(np, "fsl,imx-osc"))
292 clk[osc] = imx_clk_fixed("osc", rate);
293 }
294 283
295 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop"); 284 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
296 base = of_iomap(np, 0); 285 base = of_iomap(np, 0);
@@ -312,7 +301,6 @@ int __init mx6q_clocks_init(void)
312 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f); 301 clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
313 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3); 302 clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
314 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3); 303 clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
315 clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
316 304
317 /* 305 /*
318 * Bit 20 is the reserved and read-only bit, we do this only for: 306 * Bit 20 is the reserved and read-only bit, we do this only for:
@@ -360,7 +348,7 @@ int __init mx6q_clocks_init(void)
360 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); 348 clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
361 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); 349 clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
362 350
363 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ccm"); 351 np = ccm_node;
364 base = of_iomap(np, 0); 352 base = of_iomap(np, 0);
365 WARN_ON(!base); 353 WARN_ON(!base);
366 ccm_base = base; 354 ccm_base = base;
@@ -481,7 +469,14 @@ int __init mx6q_clocks_init(void)
481 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); 469 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16);
482 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 470 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
483 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 471 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
484 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); 472 if (cpu_is_imx6dl())
473 /*
474 * The multiplexer and divider of imx6q clock gpu3d_shader get
475 * redefined/reused as gpu2d_core_sel and gpu2d_core_podf on imx6dl.
476 */
477 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24);
478 else
479 clk[gpu2d_core] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
485 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); 480 clk[gpu3d_core] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
486 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); 481 clk[hdmi_iahb] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
487 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4); 482 clk[hdmi_isfr] = imx_clk_gate2("hdmi_isfr", "pll3_pfd1_540m", base + 0x70, 4);
@@ -499,7 +494,14 @@ int __init mx6q_clocks_init(void)
499 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); 494 clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
500 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); 495 clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
501 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16); 496 clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
502 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); 497 if (cpu_is_imx6dl())
498 /*
499 * The multiplexer and divider of the imx6q clock gpu2d get
500 * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
501 */
502 clk[mlb] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18);
503 else
504 clk[mlb] = imx_clk_gate2("mlb", "axi", base + 0x74, 18);
503 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); 505 clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
504 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); 506 clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
505 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); 507 clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
@@ -528,6 +530,7 @@ int __init mx6q_clocks_init(void)
528 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); 530 clk[usdhc2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
529 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); 531 clk[usdhc3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
530 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); 532 clk[usdhc4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
533 clk[eim_slow] = imx_clk_gate2("eim_slow", "emi_slow_podf", base + 0x80, 10);
531 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 534 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
532 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 535 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
533 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 536 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
@@ -547,6 +550,8 @@ int __init mx6q_clocks_init(void)
547 clk_register_clkdev(clk[ahb], "ahb", NULL); 550 clk_register_clkdev(clk[ahb], "ahb", NULL);
548 clk_register_clkdev(clk[cko1], "cko1", NULL); 551 clk_register_clkdev(clk[cko1], "cko1", NULL);
549 clk_register_clkdev(clk[arm], NULL, "cpu0"); 552 clk_register_clkdev(clk[arm], NULL, "cpu0");
553 clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
554 clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
550 555
551 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { 556 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) {
552 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); 557 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
@@ -576,6 +581,5 @@ int __init mx6q_clocks_init(void)
576 WARN_ON(!base); 581 WARN_ON(!base);
577 irq = irq_of_parse_and_map(np, 0); 582 irq = irq_of_parse_and_map(np, 0);
578 mxc_timer_init(base, irq); 583 mxc_timer_init(base, irq);
579
580 return 0;
581} 584}
585CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
new file mode 100644
index 000000000000..a307ac22dffe
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -0,0 +1,267 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/err.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/of_irq.h>
16#include <dt-bindings/clock/imx6sl-clock.h>
17
18#include "clk.h"
19#include "common.h"
20
21static const char const *step_sels[] = { "osc", "pll2_pfd2", };
22static const char const *pll1_sw_sels[] = { "pll1_sys", "step", };
23static const char const *ocram_alt_sels[] = { "pll2_pfd2", "pll3_pfd1", };
24static const char const *ocram_sels[] = { "periph", "ocram_alt_sels", };
25static const char const *pre_periph_sels[] = { "pll2_bus", "pll2_pfd2", "pll2_pfd0", "pll2_198m", };
26static const char const *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
27static const char const *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
28static const char const *periph_sels[] = { "pre_periph_sel", "periph_clk2_podf", };
29static const char const *periph2_sels[] = { "pre_periph2_sel", "periph2_clk2_podf", };
30static const char const *csi_lcdif_sels[] = { "mmdc", "pll2_pfd2", "pll3_120m", "pll3_pfd1", };
31static const char const *usdhc_sels[] = { "pll2_pfd2", "pll2_pfd0", };
32static const char const *ssi_sels[] = { "pll3_pfd2", "pll3_pfd3", "pll4_post_div", "dummy", };
33static const char const *perclk_sels[] = { "ipg", "osc", };
34static const char const *epdc_pxp_sels[] = { "mmdc", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd2", "pll3_pfd1", };
35static const char const *gpu2d_ovg_sels[] = { "pll3_pfd1", "pll3_usb_otg", "pll2_bus", "pll2_pfd2", };
36static const char const *gpu2d_sels[] = { "pll2_pfd2", "pll3_usb_otg", "pll3_pfd1", "pll2_bus", };
37static const char const *lcdif_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll3_pfd0", "pll3_pfd1", };
38static const char const *epdc_pix_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0", "pll2_pfd1", "pll3_pfd1", };
39static const char const *audio_sels[] = { "pll4_post_div", "pll3_pfd2", "pll3_pfd3", "pll3_usb_otg", };
40static const char const *ecspi_sels[] = { "pll3_60m", "osc", };
41static const char const *uart_sels[] = { "pll3_80m", "osc", };
42
43static struct clk_div_table clk_enet_ref_table[] = {
44 { .val = 0, .div = 20, },
45 { .val = 1, .div = 10, },
46 { .val = 2, .div = 5, },
47 { .val = 3, .div = 4, },
48 { }
49};
50
51static struct clk_div_table post_div_table[] = {
52 { .val = 2, .div = 1, },
53 { .val = 1, .div = 2, },
54 { .val = 0, .div = 4, },
55 { }
56};
57
58static struct clk_div_table video_div_table[] = {
59 { .val = 0, .div = 1, },
60 { .val = 1, .div = 2, },
61 { .val = 2, .div = 1, },
62 { .val = 3, .div = 4, },
63 { }
64};
65
66static struct clk *clks[IMX6SL_CLK_CLK_END];
67static struct clk_onecell_data clk_data;
68
69static void __init imx6sl_clocks_init(struct device_node *ccm_node)
70{
71 struct device_node *np;
72 void __iomem *base;
73 int irq;
74 int i;
75
76 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
77 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0);
78 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0);
79
80 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-anatop");
81 base = of_iomap(np, 0);
82 WARN_ON(!base);
83
84 /* type name parent base div_mask */
85 clks[IMX6SL_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
86 clks[IMX6SL_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
87 clks[IMX6SL_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
88 clks[IMX6SL_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
89 clks[IMX6SL_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
90 clks[IMX6SL_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
91 clks[IMX6SL_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
92
93 /*
94 * usbphy1 and usbphy2 are implemented as dummy gates using reserve
95 * bit 20. They are used by phy driver to keep the refcount of
96 * parent PLL correct. usbphy1_gate and usbphy2_gate only needs to be
97 * turned on during boot, and software will not need to control it
98 * anymore after that.
99 */
100 clks[IMX6SL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
101 clks[IMX6SL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
102 clks[IMX6SL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
103 clks[IMX6SL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
104
105 /* dev name parent_name flags reg shift width div: flags, div_table lock */
106 clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
107 clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
108 clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
109 clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
110
111 /* name parent_name reg idx */
112 clks[IMX6SL_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0", "pll2_bus", base + 0x100, 0);
113 clks[IMX6SL_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", base + 0x100, 1);
114 clks[IMX6SL_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", base + 0x100, 2);
115 clks[IMX6SL_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0", "pll3_usb_otg", base + 0xf0, 0);
116 clks[IMX6SL_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", base + 0xf0, 1);
117 clks[IMX6SL_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", base + 0xf0, 2);
118 clks[IMX6SL_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", base + 0xf0, 3);
119
120 /* name parent_name mult div */
121 clks[IMX6SL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2", 1, 2);
122 clks[IMX6SL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
123 clks[IMX6SL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
124 clks[IMX6SL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
125
126 np = ccm_node;
127 base = of_iomap(np, 0);
128 WARN_ON(!base);
129
130 /* name reg shift width parent_names num_parents */
131 clks[IMX6SL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
132 clks[IMX6SL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
133 clks[IMX6SL_CLK_OCRAM_ALT_SEL] = imx_clk_mux("ocram_alt_sel", base + 0x14, 7, 1, ocram_alt_sels, ARRAY_SIZE(ocram_alt_sels));
134 clks[IMX6SL_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 1, ocram_sels, ARRAY_SIZE(ocram_sels));
135 clks[IMX6SL_CLK_PRE_PERIPH2_SEL] = imx_clk_mux("pre_periph2_sel", base + 0x18, 21, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
136 clks[IMX6SL_CLK_PRE_PERIPH_SEL] = imx_clk_mux("pre_periph_sel", base + 0x18, 18, 2, pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
137 clks[IMX6SL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
138 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
139 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
140 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
141 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
142 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
143 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
144 clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
145 clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
146 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
147 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
148 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
149 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
150 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
151 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
152 clks[IMX6SL_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", base + 0x18, 8, 2, gpu2d_sels, ARRAY_SIZE(gpu2d_sels));
153 clks[IMX6SL_CLK_LCDIF_PIX_SEL] = imx_clk_mux("lcdif_pix_sel", base + 0x38, 6, 3, lcdif_pix_sels, ARRAY_SIZE(lcdif_pix_sels));
154 clks[IMX6SL_CLK_EPDC_PIX_SEL] = imx_clk_mux("epdc_pix_sel", base + 0x38, 15, 3, epdc_pix_sels, ARRAY_SIZE(epdc_pix_sels));
155 clks[IMX6SL_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
156 clks[IMX6SL_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
157 clks[IMX6SL_CLK_EXTERN_AUDIO_SEL] = imx_clk_mux("extern_audio_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
158 clks[IMX6SL_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
159 clks[IMX6SL_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
160
161 /* name reg shift width busy: reg, shift parent_names num_parents */
162 clks[IMX6SL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
163 clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
164
165 /* name parent_name reg shift width */
166 clks[IMX6SL_CLK_OCRAM_PODF] = imx_clk_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3);
167 clks[IMX6SL_CLK_PERIPH_CLK2_PODF] = imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
168 clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] = imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
169 clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
170 clks[IMX6SL_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
171 clks[IMX6SL_CLK_LCDIF_AXI_PODF] = imx_clk_divider("lcdif_axi_podf", "lcdif_axi_sel", base + 0x3c, 16, 3);
172 clks[IMX6SL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
173 clks[IMX6SL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
174 clks[IMX6SL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
175 clks[IMX6SL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
176 clks[IMX6SL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
177 clks[IMX6SL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
178 clks[IMX6SL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
179 clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
180 clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
181 clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
182 clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
183 clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
184 clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
185 clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
186 clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
187 clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
188 clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
189 clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3);
190 clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
191 clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
192 clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
193 clks[IMX6SL_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", base + 0x30, 12, 3);
194 clks[IMX6SL_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", base + 0x30, 9, 3);
195 clks[IMX6SL_CLK_EXTERN_AUDIO_PRED] = imx_clk_divider("extern_audio_pred", "extern_audio_sel", base + 0x28, 9, 3);
196 clks[IMX6SL_CLK_EXTERN_AUDIO_PODF] = imx_clk_divider("extern_audio_podf", "extern_audio_pred", base + 0x28, 25, 3);
197 clks[IMX6SL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
198 clks[IMX6SL_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_sel", base + 0x24, 0, 6);
199
200 /* name parent_name reg shift width busy: reg, shift */
201 clks[IMX6SL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
202 clks[IMX6SL_CLK_MMDC_ROOT] = imx_clk_busy_divider("mmdc", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
203 clks[IMX6SL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
204
205 /* name parent_name reg shift */
206 clks[IMX6SL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
207 clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
208 clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
209 clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
210 clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
211 clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
212 clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16);
213 clks[IMX6SL_CLK_GPT] = imx_clk_gate2("gpt", "perclk", base + 0x6c, 20);
214 clks[IMX6SL_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
215 clks[IMX6SL_CLK_GPU2D_OVG] = imx_clk_gate2("gpu2d_ovg", "gpu2d_ovg_podf", base + 0x6c, 26);
216 clks[IMX6SL_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
217 clks[IMX6SL_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
218 clks[IMX6SL_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
219 clks[IMX6SL_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
220 clks[IMX6SL_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x74, 0);
221 clks[IMX6SL_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "pxp_axi_podf", base + 0x74, 2);
222 clks[IMX6SL_CLK_EPDC_AXI] = imx_clk_gate2("epdc_axi", "epdc_axi_podf", base + 0x74, 4);
223 clks[IMX6SL_CLK_LCDIF_AXI] = imx_clk_gate2("lcdif_axi", "lcdif_axi_podf", base + 0x74, 6);
224 clks[IMX6SL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix", "lcdif_pix_podf", base + 0x74, 8);
225 clks[IMX6SL_CLK_EPDC_PIX] = imx_clk_gate2("epdc_pix", "epdc_pix_podf", base + 0x74, 10);
226 clks[IMX6SL_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
227 clks[IMX6SL_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
228 clks[IMX6SL_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
229 clks[IMX6SL_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
230 clks[IMX6SL_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
231 clks[IMX6SL_CLK_SDMA] = imx_clk_gate2("sdma", "ipg", base + 0x7c, 6);
232 clks[IMX6SL_CLK_SPDIF] = imx_clk_gate2("spdif", "spdif0_podf", base + 0x7c, 14);
233 clks[IMX6SL_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
234 clks[IMX6SL_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
235 clks[IMX6SL_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
236 clks[IMX6SL_CLK_UART] = imx_clk_gate2("uart", "ipg", base + 0x7c, 24);
237 clks[IMX6SL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_root", base + 0x7c, 26);
238 clks[IMX6SL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
239 clks[IMX6SL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
240 clks[IMX6SL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
241 clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
242 clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
243
244 for (i = 0; i < ARRAY_SIZE(clks); i++)
245 if (IS_ERR(clks[i]))
246 pr_err("i.MX6SL clk %d: register failed with %ld\n",
247 i, PTR_ERR(clks[i]));
248
249 clk_data.clks = clks;
250 clk_data.clk_num = ARRAY_SIZE(clks);
251 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
252
253 clk_register_clkdev(clks[IMX6SL_CLK_GPT], "ipg", "imx-gpt.0");
254 clk_register_clkdev(clks[IMX6SL_CLK_GPT_SERIAL], "per", "imx-gpt.0");
255
256 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
257 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY1_GATE]);
258 clk_prepare_enable(clks[IMX6SL_CLK_USBPHY2_GATE]);
259 }
260
261 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
262 base = of_iomap(np, 0);
263 WARN_ON(!base);
264 irq = irq_of_parse_and_map(np, 0);
265 mxc_timer_init(base, irq);
266}
267CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index d09bc3df9a7a..a9fad5f8d340 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -296,13 +296,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
296 .recalc_rate = clk_pllv3_enet_recalc_rate, 296 .recalc_rate = clk_pllv3_enet_recalc_rate,
297}; 297};
298 298
299static const struct clk_ops clk_pllv3_mlb_ops = {
300 .prepare = clk_pllv3_prepare,
301 .unprepare = clk_pllv3_unprepare,
302 .enable = clk_pllv3_enable,
303 .disable = clk_pllv3_disable,
304};
305
306struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 299struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
307 const char *parent_name, void __iomem *base, 300 const char *parent_name, void __iomem *base,
308 u32 div_mask) 301 u32 div_mask)
@@ -330,9 +323,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
330 case IMX_PLLV3_ENET: 323 case IMX_PLLV3_ENET:
331 ops = &clk_pllv3_enet_ops; 324 ops = &clk_pllv3_enet_ops;
332 break; 325 break;
333 case IMX_PLLV3_MLB:
334 ops = &clk_pllv3_mlb_ops;
335 break;
336 default: 326 default:
337 ops = &clk_pllv3_ops; 327 ops = &clk_pllv3_ops;
338 } 328 }
diff --git a/arch/arm/mach-imx/clk-vf610.c b/arch/arm/mach-imx/clk-vf610.c
new file mode 100644
index 000000000000..d617c0b7c809
--- /dev/null
+++ b/arch/arm/mach-imx/clk-vf610.c
@@ -0,0 +1,319 @@
1/*
2 * Copyright 2012-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/of_address.h>
12#include <linux/clk.h>
13#include <dt-bindings/clock/vf610-clock.h>
14
15#include "clk.h"
16
17#define CCM_CCR (ccm_base + 0x00)
18#define CCM_CSR (ccm_base + 0x04)
19#define CCM_CCSR (ccm_base + 0x08)
20#define CCM_CACRR (ccm_base + 0x0c)
21#define CCM_CSCMR1 (ccm_base + 0x10)
22#define CCM_CSCDR1 (ccm_base + 0x14)
23#define CCM_CSCDR2 (ccm_base + 0x18)
24#define CCM_CSCDR3 (ccm_base + 0x1c)
25#define CCM_CSCMR2 (ccm_base + 0x20)
26#define CCM_CSCDR4 (ccm_base + 0x24)
27#define CCM_CLPCR (ccm_base + 0x2c)
28#define CCM_CISR (ccm_base + 0x30)
29#define CCM_CIMR (ccm_base + 0x34)
30#define CCM_CGPR (ccm_base + 0x3c)
31#define CCM_CCGR0 (ccm_base + 0x40)
32#define CCM_CCGR1 (ccm_base + 0x44)
33#define CCM_CCGR2 (ccm_base + 0x48)
34#define CCM_CCGR3 (ccm_base + 0x4c)
35#define CCM_CCGR4 (ccm_base + 0x50)
36#define CCM_CCGR5 (ccm_base + 0x54)
37#define CCM_CCGR6 (ccm_base + 0x58)
38#define CCM_CCGR7 (ccm_base + 0x5c)
39#define CCM_CCGR8 (ccm_base + 0x60)
40#define CCM_CCGR9 (ccm_base + 0x64)
41#define CCM_CCGR10 (ccm_base + 0x68)
42#define CCM_CCGR11 (ccm_base + 0x6c)
43#define CCM_CMEOR0 (ccm_base + 0x70)
44#define CCM_CMEOR1 (ccm_base + 0x74)
45#define CCM_CMEOR2 (ccm_base + 0x78)
46#define CCM_CMEOR3 (ccm_base + 0x7c)
47#define CCM_CMEOR4 (ccm_base + 0x80)
48#define CCM_CMEOR5 (ccm_base + 0x84)
49#define CCM_CPPDSR (ccm_base + 0x88)
50#define CCM_CCOWR (ccm_base + 0x8c)
51#define CCM_CCPGR0 (ccm_base + 0x90)
52#define CCM_CCPGR1 (ccm_base + 0x94)
53#define CCM_CCPGR2 (ccm_base + 0x98)
54#define CCM_CCPGR3 (ccm_base + 0x9c)
55
56#define CCM_CCGRx_CGn(n) ((n) * 2)
57
58#define PFD_PLL1_BASE (anatop_base + 0x2b0)
59#define PFD_PLL2_BASE (anatop_base + 0x100)
60#define PFD_PLL3_BASE (anatop_base + 0xf0)
61
62static void __iomem *anatop_base;
63static void __iomem *ccm_base;
64
65/* sources for multiplexer clocks, this is used multiple times */
66static const char const *fast_sels[] = { "firc", "fxosc", };
67static const char const *slow_sels[] = { "sirc_32k", "sxosc", };
68static const char const *pll1_sels[] = { "pll1_main", "pll1_pfd1", "pll1_pfd2", "pll1_pfd3", "pll1_pfd4", };
69static const char const *pll2_sels[] = { "pll2_main", "pll2_pfd1", "pll2_pfd2", "pll2_pfd3", "pll2_pfd4", };
70static const char const *sys_sels[] = { "fast_clk_sel", "slow_clk_sel", "pll2_pfd_sel", "pll2_main", "pll1_pfd_sel", "pll3_main", };
71static const char const *ddr_sels[] = { "pll2_pfd2", "sys_sel", };
72static const char const *rmii_sels[] = { "enet_ext", "audio_ext", "enet_50m", "enet_25m", };
73static const char const *enet_ts_sels[] = { "enet_ext", "fxosc", "audio_ext", "usb", "enet_ts", "enet_25m", "enet_50m", };
74static const char const *esai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
75static const char const *sai_sels[] = { "audio_ext", "mlb", "spdif_rx", "pll4_main_div", };
76static const char const *nfc_sels[] = { "platform_bus", "pll1_pfd1", "pll3_pfd1", "pll3_pfd3", };
77static const char const *qspi_sels[] = { "pll3_main", "pll3_pfd4", "pll2_pfd4", "pll1_pfd4", };
78static const char const *esdhc_sels[] = { "pll3_main", "pll3_pfd3", "pll1_pfd3", "platform_bus", };
79static const char const *dcu_sels[] = { "pll1_pfd2", "pll3_main", };
80static const char const *gpu_sels[] = { "pll2_pfd2", "pll3_pfd2", };
81static const char const *vadc_sels[] = { "pll6_main_div", "pll3_main_div", "pll3_main", };
82/* FTM counter clock source, not module clock */
83static const char const *ftm_ext_sels[] = {"sirc_128k", "sxosc", "fxosc_half", "audio_ext", };
84static const char const *ftm_fix_sels[] = { "sxosc", "ipg_bus", };
85
86static struct clk_div_table pll4_main_div_table[] = {
87 { .val = 0, .div = 1 },
88 { .val = 1, .div = 2 },
89 { .val = 2, .div = 6 },
90 { .val = 3, .div = 8 },
91 { .val = 4, .div = 10 },
92 { .val = 5, .div = 12 },
93 { .val = 6, .div = 14 },
94 { .val = 7, .div = 16 },
95 { }
96};
97
98static struct clk *clk[VF610_CLK_END];
99static struct clk_onecell_data clk_data;
100
101static void __init vf610_clocks_init(struct device_node *ccm_node)
102{
103 struct device_node *np;
104
105 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
106 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000);
107 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000);
108 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000);
109
110 clk[VF610_CLK_SXOSC] = imx_obtain_fixed_clock("sxosc", 0);
111 clk[VF610_CLK_FXOSC] = imx_obtain_fixed_clock("fxosc", 0);
112 clk[VF610_CLK_AUDIO_EXT] = imx_obtain_fixed_clock("audio_ext", 0);
113 clk[VF610_CLK_ENET_EXT] = imx_obtain_fixed_clock("enet_ext", 0);
114
115 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2);
116
117 np = of_find_compatible_node(NULL, NULL, "fsl,vf610-anatop");
118 anatop_base = of_iomap(np, 0);
119 BUG_ON(!anatop_base);
120
121 np = ccm_node;
122 ccm_base = of_iomap(np, 0);
123 BUG_ON(!ccm_base);
124
125 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels));
126 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels));
127
128 clk[VF610_CLK_PLL1_MAIN] = imx_clk_fixed_factor("pll1_main", "fast_clk_sel", 22, 1);
129 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_main", PFD_PLL1_BASE, 0);
130 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_main", PFD_PLL1_BASE, 1);
131 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_main", PFD_PLL1_BASE, 2);
132 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_main", PFD_PLL1_BASE, 3);
133
134 clk[VF610_CLK_PLL2_MAIN] = imx_clk_fixed_factor("pll2_main", "fast_clk_sel", 22, 1);
135 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_main", PFD_PLL2_BASE, 0);
136 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_main", PFD_PLL2_BASE, 1);
137 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_main", PFD_PLL2_BASE, 2);
138 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_main", PFD_PLL2_BASE, 3);
139
140 clk[VF610_CLK_PLL3_MAIN] = imx_clk_fixed_factor("pll3_main", "fast_clk_sel", 20, 1);
141 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_main", PFD_PLL3_BASE, 0);
142 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_main", PFD_PLL3_BASE, 1);
143 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_main", PFD_PLL3_BASE, 2);
144 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_main", PFD_PLL3_BASE, 3);
145
146 clk[VF610_CLK_PLL4_MAIN] = imx_clk_fixed_factor("pll4_main", "fast_clk_sel", 25, 1);
147 /* Enet pll: fixed 50Mhz */
148 clk[VF610_CLK_PLL5_MAIN] = imx_clk_fixed_factor("pll5_main", "fast_clk_sel", 125, 6);
149 /* pll6: default 960Mhz */
150 clk[VF610_CLK_PLL6_MAIN] = imx_clk_fixed_factor("pll6_main", "fast_clk_sel", 40, 1);
151 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5);
152 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5);
153 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels));
154 clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels));
155 clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3);
156 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3);
157 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2);
158
159 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_main_div", "pll3_main", CCM_CACRR, 20, 1);
160 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_main_div", "pll4_main", 0, CCM_CACRR, 6, 3, 0, pll4_main_div_table, &imx_ccm_lock);
161 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_main_div", "pll6_main", CCM_CACRR, 21, 1);
162
163 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "pll3_main", CCM_CCGR1, CCM_CCGRx_CGn(4));
164 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "pll3_main", CCM_CCGR7, CCM_CCGRx_CGn(4));
165
166 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4);
167 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4);
168 clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2);
169 clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1);
170 clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1);
171 clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4));
172
173 clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4);
174 clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12);
175 clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2);
176 clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1);
177 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1);
178 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4));
179
180 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_main", 1, 10);
181 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_main", 1, 20);
182 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4);
183 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
184 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
185 clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
186
187 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
188
189 clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7));
190 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8));
191 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9));
192 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10));
193
194 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6));
195 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7));
196
197 clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12));
198 clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13));
199 clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12));
200 clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13));
201
202 clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14));
203
204 clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4);
205 clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28);
206 clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4);
207 clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1));
208
209 clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4);
210 clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29);
211 clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4);
212 clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2));
213
214 /*
215 * ftm_ext_clk and ftm_fix_clk are FTM timer counter's
216 * selectable clock sources, both use a common enable bit
217 * in CCM_CSCDR1, selecting "dummy" clock as parent of
218 * "ftm0_ext_fix" make it serve only for enable/disable.
219 */
220 clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4);
221 clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2);
222 clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25);
223 clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4);
224 clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2);
225 clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26);
226 clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4);
227 clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2);
228 clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27);
229 clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4);
230 clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2);
231 clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28);
232
233 /* ftm(n)_clk are FTM module operation clock */
234 clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8));
235 clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9));
236 clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8));
237 clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9));
238
239 clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
240 clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
241 clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
242 clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8));
243 clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
244 clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
245 clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
246 clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8));
247
248 clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
249 clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
250 clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4);
251 clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2));
252
253 clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4);
254 clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16);
255 clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4);
256 clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "sai0_div", CCM_CCGR0, CCM_CCGRx_CGn(15));
257
258 clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4);
259 clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17);
260 clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4);
261 clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "sai1_div", CCM_CCGR1, CCM_CCGRx_CGn(0));
262
263 clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4);
264 clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18);
265 clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4);
266 clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "sai2_div", CCM_CCGR1, CCM_CCGRx_CGn(1));
267
268 clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4);
269 clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19);
270 clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4);
271 clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "sai3_div", CCM_CCGR1, CCM_CCGRx_CGn(2));
272
273 clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4);
274 clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9);
275 clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3);
276 clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4);
277 clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0));
278
279 clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2);
280 clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10);
281 clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15));
282
283 clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3);
284 clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22);
285 clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2);
286 clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2);
287 clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7));
288
289 clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11));
290 clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11));
291 clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12));
292 clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13));
293
294 clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1));
295
296 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(0));
297 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(4));
298
299 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]);
300 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2);
301 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2);
302 clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2);
303
304 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]);
305 clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2);
306 clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2);
307 clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2);
308
309 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]);
310 clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]);
311 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]);
312 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]);
313
314 /* Add the clocks to provider list */
315 clk_data.clks = clk;
316 clk_data.clk_num = ARRAY_SIZE(clk);
317 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
318}
319CLK_OF_DECLARE(vf610, "fsl,vf610-ccm", vf610_clocks_init);
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 37e884ed1cd4..55bc80a00666 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -1,4 +1,39 @@
1#include <linux/clk.h>
2#include <linux/err.h>
3#include <linux/of.h>
4#include <linux/slab.h>
1#include <linux/spinlock.h> 5#include <linux/spinlock.h>
2#include "clk.h" 6#include "clk.h"
3 7
4DEFINE_SPINLOCK(imx_ccm_lock); 8DEFINE_SPINLOCK(imx_ccm_lock);
9
10static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
11{
12 struct of_phandle_args phandle;
13 struct clk *clk = ERR_PTR(-ENODEV);
14 char *path;
15
16 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
17 if (!path)
18 return ERR_PTR(-ENOMEM);
19
20 phandle.np = of_find_node_by_path(path);
21 kfree(path);
22
23 if (phandle.np) {
24 clk = of_clk_get_from_provider(&phandle);
25 of_node_put(phandle.np);
26 }
27 return clk;
28}
29
30struct clk * __init imx_obtain_fixed_clock(
31 const char *name, unsigned long rate)
32{
33 struct clk *clk;
34
35 clk = imx_obtain_fixed_clock_from_dt(name);
36 if (IS_ERR(clk))
37 clk = imx_clk_fixed(name, rate);
38 return clk;
39}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index d9d9d9c66dff..0e4e8bb261b9 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -18,7 +18,6 @@ enum imx_pllv3_type {
18 IMX_PLLV3_USB, 18 IMX_PLLV3_USB,
19 IMX_PLLV3_AV, 19 IMX_PLLV3_AV,
20 IMX_PLLV3_ENET, 20 IMX_PLLV3_ENET,
21 IMX_PLLV3_MLB,
22}; 21};
23 22
24struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 23struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
@@ -29,6 +28,9 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
29 void __iomem *reg, u8 bit_idx, 28 void __iomem *reg, u8 bit_idx,
30 u8 clk_gate_flags, spinlock_t *lock); 29 u8 clk_gate_flags, spinlock_t *lock);
31 30
31struct clk * imx_obtain_fixed_clock(
32 const char *name, unsigned long rate);
33
32static inline struct clk *imx_clk_gate2(const char *name, const char *parent, 34static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
33 void __iomem *reg, u8 shift) 35 void __iomem *reg, u8 shift)
34{ 36{
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c08ae3f99cee..ee78847abf47 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -68,12 +68,12 @@ extern int mx27_clocks_init_dt(void);
68extern int mx31_clocks_init_dt(void); 68extern int mx31_clocks_init_dt(void);
69extern int mx51_clocks_init_dt(void); 69extern int mx51_clocks_init_dt(void);
70extern int mx53_clocks_init_dt(void); 70extern int mx53_clocks_init_dt(void);
71extern int mx6q_clocks_init(void);
72extern struct platform_device *mxc_register_gpio(char *name, int id, 71extern struct platform_device *mxc_register_gpio(char *name, int id,
73 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); 72 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
74extern void mxc_set_cpu_type(unsigned int type); 73extern void mxc_set_cpu_type(unsigned int type);
75extern void mxc_restart(char, const char *); 74extern void mxc_restart(char, const char *);
76extern void mxc_arch_reset_init(void __iomem *); 75extern void mxc_arch_reset_init(void __iomem *);
76extern void mxc_arch_reset_init_dt(void);
77extern int mx53_revision(void); 77extern int mx53_revision(void);
78extern int imx6q_revision(void); 78extern int imx6q_revision(void);
79extern int mx53_display_revision(void); 79extern int mx53_display_revision(void);
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 356131f7b591..a3b0b04b45c9 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -20,6 +20,7 @@
20#ifndef __ASM_ARCH_MXC_HARDWARE_H__ 20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
21#define __ASM_ARCH_MXC_HARDWARE_H__ 21#define __ASM_ARCH_MXC_HARDWARE_H__
22 22
23#include <asm/io.h>
23#include <asm/sizes.h> 24#include <asm/sizes.h>
24 25
25#define addr_in_module(addr, mod) \ 26#define addr_in_module(addr, mod) \
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 82348391582a..3e1ec5ffe630 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -19,6 +19,8 @@
19 19
20static void __init imx25_dt_init(void) 20static void __init imx25_dt_init(void)
21{ 21{
22 mxc_arch_reset_init_dt();
23
22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23} 25}
24 26
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4aaead0a77ff..4e235ecb4021 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -22,6 +22,8 @@ static void __init imx27_dt_init(void)
22{ 22{
23 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 23 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
24 24
25 mxc_arch_reset_init_dt();
26
25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 27 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
26 28
27 platform_device_register_full(&devinfo); 29 platform_device_register_full(&devinfo);
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index 67de611e29ab..818a1cc2fe45 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -20,6 +20,8 @@
20 20
21static void __init imx31_dt_init(void) 21static void __init imx31_dt_init(void)
22{ 22{
23 mxc_arch_reset_init_dt();
24
23 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 25 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
24} 26}
25 27
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index ab24cc322111..53e43e579dd7 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -23,6 +23,8 @@ static void __init imx51_dt_init(void)
23{ 23{
24 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", }; 24 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
25 25
26 mxc_arch_reset_init_dt();
27
26 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 28 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
27 platform_device_register_full(&devinfo); 29 platform_device_register_full(&devinfo);
28} 30}
diff --git a/arch/arm/mach-imx/irq-common.c b/arch/arm/mach-imx/irq-common.c
index 4b34f52dc46b..0a920d184867 100644
--- a/arch/arm/mach-imx/irq-common.c
+++ b/arch/arm/mach-imx/irq-common.c
@@ -18,6 +18,7 @@
18 18
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/platform_data/asoc-imx-ssi.h>
21 22
22#include "irq-common.h" 23#include "irq-common.h"
23 24
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index f579c616feed..74e7b94c22e7 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -21,6 +21,7 @@
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22 22
23#include "common.h" 23#include "common.h"
24#include "hardware.h"
24#include "mx53.h" 25#include "mx53.h"
25 26
26static void __init imx53_qsb_init(void) 27static void __init imx53_qsb_init(void)
@@ -38,6 +39,8 @@ static void __init imx53_qsb_init(void)
38 39
39static void __init imx53_dt_init(void) 40static void __init imx53_dt_init(void)
40{ 41{
42 mxc_arch_reset_init_dt();
43
41 if (of_machine_is_compatible("fsl,imx53-qsb")) 44 if (of_machine_is_compatible("fsl,imx53-qsb"))
42 imx53_qsb_init(); 45 imx53_qsb_init();
43 46
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 5536fd81379a..f5965220a4d8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/clk-provider.h>
14#include <linux/clkdev.h> 15#include <linux/clkdev.h>
15#include <linux/clocksource.h> 16#include <linux/clocksource.h>
16#include <linux/cpu.h> 17#include <linux/cpu.h>
@@ -145,6 +146,45 @@ static void __init imx6q_sabrelite_init(void)
145 imx6q_sabrelite_cko1_setup(); 146 imx6q_sabrelite_cko1_setup();
146} 147}
147 148
149static void __init imx6q_sabresd_cko1_setup(void)
150{
151 struct clk *cko1_sel, *pll4, *pll4_post, *cko1;
152 unsigned long rate;
153
154 cko1_sel = clk_get_sys(NULL, "cko1_sel");
155 pll4 = clk_get_sys(NULL, "pll4_audio");
156 pll4_post = clk_get_sys(NULL, "pll4_post_div");
157 cko1 = clk_get_sys(NULL, "cko1");
158 if (IS_ERR(cko1_sel) || IS_ERR(pll4)
159 || IS_ERR(pll4_post) || IS_ERR(cko1)) {
160 pr_err("cko1 setup failed!\n");
161 goto put_clk;
162 }
163 /*
164 * Setting pll4 at 768MHz (24MHz * 32)
165 * So its child clock can get 24MHz easily
166 */
167 clk_set_rate(pll4, 768000000);
168
169 clk_set_parent(cko1_sel, pll4_post);
170 rate = clk_round_rate(cko1, 24000000);
171 clk_set_rate(cko1, rate);
172put_clk:
173 if (!IS_ERR(cko1_sel))
174 clk_put(cko1_sel);
175 if (!IS_ERR(pll4_post))
176 clk_put(pll4_post);
177 if (!IS_ERR(pll4))
178 clk_put(pll4);
179 if (!IS_ERR(cko1))
180 clk_put(cko1);
181}
182
183static void __init imx6q_sabresd_init(void)
184{
185 imx6q_sabresd_cko1_setup();
186}
187
148static void __init imx6q_1588_init(void) 188static void __init imx6q_1588_init(void)
149{ 189{
150 struct regmap *gpr; 190 struct regmap *gpr;
@@ -165,6 +205,9 @@ static void __init imx6q_init_machine(void)
165{ 205{
166 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 206 if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
167 imx6q_sabrelite_init(); 207 imx6q_sabrelite_init();
208 else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
209 of_machine_is_compatible("fsl,imx6dl-sabresd"))
210 imx6q_sabresd_init();
168 211
169 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 212 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
170 213
@@ -253,10 +296,44 @@ static void __init imx6q_map_io(void)
253 imx_scu_map_io(); 296 imx_scu_map_io();
254} 297}
255 298
299#ifdef CONFIG_CACHE_L2X0
300static void __init imx6q_init_l2cache(void)
301{
302 void __iomem *l2x0_base;
303 struct device_node *np;
304 unsigned int val;
305
306 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
307 if (!np)
308 goto out;
309
310 l2x0_base = of_iomap(np, 0);
311 if (!l2x0_base) {
312 of_node_put(np);
313 goto out;
314 }
315
316 /* Configure the L2 PREFETCH and POWER registers */
317 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
318 val |= 0x70800000;
319 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
320 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
321 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
322
323 iounmap(l2x0_base);
324 of_node_put(np);
325
326out:
327 l2x0_of_init(0, ~0UL);
328}
329#else
330static inline void imx6q_init_l2cache(void) {}
331#endif
332
256static void __init imx6q_init_irq(void) 333static void __init imx6q_init_irq(void)
257{ 334{
258 imx6q_init_revision(); 335 imx6q_init_revision();
259 l2x0_of_init(0, ~0UL); 336 imx6q_init_l2cache();
260 imx_src_init(); 337 imx_src_init();
261 imx_gpc_init(); 338 imx_gpc_init();
262 irqchip_init(); 339 irqchip_init();
@@ -264,7 +341,7 @@ static void __init imx6q_init_irq(void)
264 341
265static void __init imx6q_timer_init(void) 342static void __init imx6q_timer_init(void)
266{ 343{
267 mx6q_clocks_init(); 344 of_clk_init(NULL);
268 clocksource_of_init(); 345 clocksource_of_init();
269 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", 346 imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q",
270 imx6q_revision()); 347 imx6q_revision());
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
new file mode 100644
index 000000000000..132db2609507
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -0,0 +1,52 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/irqchip.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <asm/hardware/cache-l2x0.h>
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17
18#include "common.h"
19
20static void __init imx6sl_init_machine(void)
21{
22 mxc_arch_reset_init_dt();
23
24 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
25}
26
27static void __init imx6sl_init_irq(void)
28{
29 l2x0_of_init(0, ~0UL);
30 imx_src_init();
31 imx_gpc_init();
32 irqchip_init();
33}
34
35static void __init imx6sl_timer_init(void)
36{
37 of_clk_init(NULL);
38}
39
40static const char *imx6sl_dt_compat[] __initdata = {
41 "fsl,imx6sl",
42 NULL,
43};
44
45DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)")
46 .map_io = debug_ll_io_init,
47 .init_irq = imx6sl_init_irq,
48 .init_time = imx6sl_timer_init,
49 .init_machine = imx6sl_init_machine,
50 .dt_compat = imx6sl_dt_compat,
51 .restart = mxc_restart,
52MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index b8b15bb1ffdf..19bb6441a7d4 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -398,8 +398,8 @@ static void __init pca100_init(void)
398 imx27_add_fsl_usb2_udc(&otg_device_pdata); 398 imx27_add_fsl_usb2_udc(&otg_device_pdata);
399 } 399 }
400 400
401 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 401 usbh2_pdata.otg = imx_otg_ulpi_create(
402 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 402 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
403 403
404 if (usbh2_pdata.otg) 404 if (usbh2_pdata.otg)
405 imx27_add_mxc_ehci_hs(2, &usbh2_pdata); 405 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
new file mode 100644
index 000000000000..816991deb9b8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright 2012-2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/of_platform.h>
11#include <linux/clocksource.h>
12#include <linux/irqchip.h>
13#include <linux/clk-provider.h>
14#include <asm/mach/arch.h>
15#include <asm/hardware/cache-l2x0.h>
16
17#include "common.h"
18
19static void __init vf610_init_machine(void)
20{
21 mxc_arch_reset_init_dt();
22 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
23}
24
25static void __init vf610_init_irq(void)
26{
27 l2x0_of_init(0, ~0UL);
28 irqchip_init();
29}
30
31static void __init vf610_init_time(void)
32{
33 of_clk_init(NULL);
34 clocksource_of_init();
35}
36
37static const char *vf610_dt_compat[] __initdata = {
38 "fsl,vf610",
39 NULL,
40};
41
42DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
43 .init_irq = vf610_init_irq,
44 .init_time = vf610_init_time,
45 .init_machine = vf610_init_machine,
46 .dt_compat = vf610_dt_compat,
47 .restart = mxc_restart,
48MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 3c609c52d3eb..e065fedb3ad4 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -39,7 +39,6 @@ void __init mx1_map_io(void)
39void __init imx1_init_early(void) 39void __init imx1_init_early(void)
40{ 40{
41 mxc_set_cpu_type(MXC_CPU_MX1); 41 mxc_set_cpu_type(MXC_CPU_MX1);
42 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
43 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR), 42 imx_iomuxv1_init(MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
44 MX1_NUM_GPIO_PORT); 43 MX1_NUM_GPIO_PORT);
45} 44}
@@ -51,6 +50,7 @@ void __init mx1_init_irq(void)
51 50
52void __init imx1_soc_init(void) 51void __init imx1_soc_init(void)
53{ 52{
53 mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
54 mxc_device_init(); 54 mxc_device_init();
55 55
56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, 56 mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index d8ccd3a8ec53..2e91ab2ca378 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -66,7 +66,6 @@ void __init mx21_map_io(void)
66void __init imx21_init_early(void) 66void __init imx21_init_early(void)
67{ 67{
68 mxc_set_cpu_type(MXC_CPU_MX21); 68 mxc_set_cpu_type(MXC_CPU_MX21);
69 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
70 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR), 69 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
71 MX21_NUM_GPIO_PORT); 70 MX21_NUM_GPIO_PORT);
72} 71}
@@ -82,6 +81,7 @@ static const struct resource imx21_audmux_res[] __initconst = {
82 81
83void __init imx21_soc_init(void) 82void __init imx21_soc_init(void)
84{ 83{
84 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
85 mxc_device_init(); 85 mxc_device_init();
86 86
87 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); 87 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9357707bb7af..e065c117f5a6 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -54,7 +54,6 @@ void __init imx25_init_early(void)
54{ 54{
55 mxc_set_cpu_type(MXC_CPU_MX25); 55 mxc_set_cpu_type(MXC_CPU_MX25);
56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); 56 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
57 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
58} 57}
59 58
60void __init mx25_init_irq(void) 59void __init mx25_init_irq(void)
@@ -89,6 +88,7 @@ static const struct resource imx25_audmux_res[] __initconst = {
89 88
90void __init imx25_soc_init(void) 89void __init imx25_soc_init(void)
91{ 90{
91 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
92 mxc_device_init(); 92 mxc_device_init();
93 93
94 /* i.mx25 has the i.mx35 type gpio */ 94 /* i.mx25 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 4f1be65a7b5f..7d82a5a5b16b 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -66,7 +66,6 @@ void __init mx27_map_io(void)
66void __init imx27_init_early(void) 66void __init imx27_init_early(void)
67{ 67{
68 mxc_set_cpu_type(MXC_CPU_MX27); 68 mxc_set_cpu_type(MXC_CPU_MX27);
69 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
70 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), 69 imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR),
71 MX27_NUM_GPIO_PORT); 70 MX27_NUM_GPIO_PORT);
72} 71}
@@ -82,6 +81,7 @@ static const struct resource imx27_audmux_res[] __initconst = {
82 81
83void __init imx27_soc_init(void) 82void __init imx27_soc_init(void)
84{ 83{
84 mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR));
85 mxc_device_init(); 85 mxc_device_init();
86 86
87 /* i.mx27 has the i.mx21 type gpio */ 87 /* i.mx27 has the i.mx21 type gpio */
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
index e0e69a682174..8f0f60697f55 100644
--- a/arch/arm/mach-imx/mm-imx3.c
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -138,7 +138,6 @@ void __init mx31_map_io(void)
138void __init imx31_init_early(void) 138void __init imx31_init_early(void)
139{ 139{
140 mxc_set_cpu_type(MXC_CPU_MX31); 140 mxc_set_cpu_type(MXC_CPU_MX31);
141 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
142 arch_ioremap_caller = imx3_ioremap_caller; 141 arch_ioremap_caller = imx3_ioremap_caller;
143 arm_pm_idle = imx3_idle; 142 arm_pm_idle = imx3_idle;
144 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); 143 mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
@@ -174,6 +173,7 @@ void __init imx31_soc_init(void)
174 173
175 imx3_init_l2x0(); 174 imx3_init_l2x0();
176 175
176 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
177 mxc_device_init(); 177 mxc_device_init();
178 178
179 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0); 179 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
@@ -216,7 +216,6 @@ void __init imx35_init_early(void)
216{ 216{
217 mxc_set_cpu_type(MXC_CPU_MX35); 217 mxc_set_cpu_type(MXC_CPU_MX35);
218 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR)); 218 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
219 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
220 arm_pm_idle = imx3_idle; 219 arm_pm_idle = imx3_idle;
221 arch_ioremap_caller = imx3_ioremap_caller; 220 arch_ioremap_caller = imx3_ioremap_caller;
222 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); 221 mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
@@ -272,6 +271,7 @@ void __init imx35_soc_init(void)
272 271
273 imx3_init_l2x0(); 272 imx3_init_l2x0();
274 273
274 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
275 mxc_device_init(); 275 mxc_device_init();
276 276
277 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0); 277 mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index b7c4e70e5081..cf193d87274a 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -83,7 +83,6 @@ void __init imx51_init_early(void)
83 imx51_ipu_mipi_setup(); 83 imx51_ipu_mipi_setup();
84 mxc_set_cpu_type(MXC_CPU_MX51); 84 mxc_set_cpu_type(MXC_CPU_MX51);
85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
86 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
87 imx_src_init(); 86 imx_src_init();
88} 87}
89 88
@@ -91,7 +90,6 @@ void __init imx53_init_early(void)
91{ 90{
92 mxc_set_cpu_type(MXC_CPU_MX53); 91 mxc_set_cpu_type(MXC_CPU_MX53);
93 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); 92 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
94 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
95 imx_src_init(); 93 imx_src_init();
96} 94}
97 95
@@ -129,6 +127,7 @@ static const struct resource imx51_audmux_res[] __initconst = {
129 127
130void __init imx51_soc_init(void) 128void __init imx51_soc_init(void)
131{ 129{
130 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
132 mxc_device_init(); 131 mxc_device_init();
133 132
134 /* i.mx51 has the i.mx35 type gpio */ 133 /* i.mx51 has the i.mx35 type gpio */
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 695e0d73bf85..7cdc79a9657c 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
24 26
25#include <asm/system_misc.h> 27#include <asm/system_misc.h>
26#include <asm/proc-fns.h> 28#include <asm/proc-fns.h>
@@ -30,6 +32,7 @@
30#include "hardware.h" 32#include "hardware.h"
31 33
32static void __iomem *wdog_base; 34static void __iomem *wdog_base;
35static struct clk *wdog_clk;
33 36
34/* 37/*
35 * Reset the system. It is called by machine_restart(). 38 * Reset the system. It is called by machine_restart().
@@ -38,16 +41,13 @@ void mxc_restart(char mode, const char *cmd)
38{ 41{
39 unsigned int wcr_enable; 42 unsigned int wcr_enable;
40 43
41 if (cpu_is_mx1()) { 44 if (wdog_clk)
42 wcr_enable = (1 << 0); 45 clk_enable(wdog_clk);
43 } else {
44 struct clk *clk;
45 46
46 clk = clk_get_sys("imx2-wdt.0", NULL); 47 if (cpu_is_mx1())
47 if (!IS_ERR(clk)) 48 wcr_enable = (1 << 0);
48 clk_prepare_enable(clk); 49 else
49 wcr_enable = (1 << 2); 50 wcr_enable = (1 << 2);
50 }
51 51
52 /* Assert SRS signal */ 52 /* Assert SRS signal */
53 __raw_writew(wcr_enable, wdog_base); 53 __raw_writew(wcr_enable, wdog_base);
@@ -55,7 +55,7 @@ void mxc_restart(char mode, const char *cmd)
55 /* wait for reset to assert... */ 55 /* wait for reset to assert... */
56 mdelay(500); 56 mdelay(500);
57 57
58 printk(KERN_ERR "Watchdog reset failed to assert reset\n"); 58 pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
59 59
60 /* delay to allow the serial port to show the message */ 60 /* delay to allow the serial port to show the message */
61 mdelay(50); 61 mdelay(50);
@@ -64,7 +64,34 @@ void mxc_restart(char mode, const char *cmd)
64 soft_restart(0); 64 soft_restart(0);
65} 65}
66 66
67void mxc_arch_reset_init(void __iomem *base) 67void __init mxc_arch_reset_init(void __iomem *base)
68{ 68{
69 wdog_base = base; 69 wdog_base = base;
70
71 wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
72 if (IS_ERR(wdog_clk)) {
73 pr_warn("%s: failed to get wdog clock\n", __func__);
74 wdog_clk = NULL;
75 return;
76 }
77
78 clk_prepare(wdog_clk);
79}
80
81void __init mxc_arch_reset_init_dt(void)
82{
83 struct device_node *np;
84
85 np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
86 wdog_base = of_iomap(np, 0);
87 WARN_ON(!wdog_base);
88
89 wdog_clk = of_clk_get(np, 0);
90 if (IS_ERR(wdog_clk)) {
91 pr_warn("%s: failed to get wdog clock\n", __func__);
92 wdog_clk = NULL;
93 return;
94 }
95
96 clk_prepare(wdog_clk);
70} 97}
diff --git a/arch/arm/mach-imx/ulpi.c b/arch/arm/mach-imx/ulpi.c
deleted file mode 100644
index 0f051957d10c..000000000000
--- a/arch/arm/mach-imx/ulpi.c
+++ /dev/null
@@ -1,118 +0,0 @@
1/*
2 * Copyright 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright 2009 Daniel Mack <daniel@caiaq.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/io.h>
23#include <linux/delay.h>
24#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h>
26
27#include "ulpi.h"
28
29/* ULPIVIEW register bits */
30#define ULPIVW_WU (1 << 31) /* Wakeup */
31#define ULPIVW_RUN (1 << 30) /* read/write run */
32#define ULPIVW_WRITE (1 << 29) /* 0 = read 1 = write */
33#define ULPIVW_SS (1 << 27) /* SyncState */
34#define ULPIVW_PORT_MASK 0x07 /* Port field */
35#define ULPIVW_PORT_SHIFT 24
36#define ULPIVW_ADDR_MASK 0xff /* data address field */
37#define ULPIVW_ADDR_SHIFT 16
38#define ULPIVW_RDATA_MASK 0xff /* read data field */
39#define ULPIVW_RDATA_SHIFT 8
40#define ULPIVW_WDATA_MASK 0xff /* write data field */
41#define ULPIVW_WDATA_SHIFT 0
42
43static int ulpi_poll(void __iomem *view, u32 bit)
44{
45 int timeout = 10000;
46
47 while (timeout--) {
48 u32 data = __raw_readl(view);
49
50 if (!(data & bit))
51 return 0;
52
53 cpu_relax();
54 };
55
56 printk(KERN_WARNING "timeout polling for ULPI device\n");
57
58 return -ETIMEDOUT;
59}
60
61static int ulpi_read(struct usb_phy *otg, u32 reg)
62{
63 int ret;
64 void __iomem *view = otg->io_priv;
65
66 /* make sure interface is running */
67 if (!(__raw_readl(view) & ULPIVW_SS)) {
68 __raw_writel(ULPIVW_WU, view);
69
70 /* wait for wakeup */
71 ret = ulpi_poll(view, ULPIVW_WU);
72 if (ret)
73 return ret;
74 }
75
76 /* read the register */
77 __raw_writel((ULPIVW_RUN | (reg << ULPIVW_ADDR_SHIFT)), view);
78
79 /* wait for completion */
80 ret = ulpi_poll(view, ULPIVW_RUN);
81 if (ret)
82 return ret;
83
84 return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
85}
86
87static int ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
88{
89 int ret;
90 void __iomem *view = otg->io_priv;
91
92 /* make sure the interface is running */
93 if (!(__raw_readl(view) & ULPIVW_SS)) {
94 __raw_writel(ULPIVW_WU, view);
95 /* wait for wakeup */
96 ret = ulpi_poll(view, ULPIVW_WU);
97 if (ret)
98 return ret;
99 }
100
101 __raw_writel((ULPIVW_RUN | ULPIVW_WRITE |
102 (reg << ULPIVW_ADDR_SHIFT) |
103 ((val & ULPIVW_WDATA_MASK) << ULPIVW_WDATA_SHIFT)), view);
104
105 /* wait for completion */
106 return ulpi_poll(view, ULPIVW_RUN);
107}
108
109struct usb_phy_io_ops mxc_ulpi_access_ops = {
110 .read = ulpi_read,
111 .write = ulpi_write,
112};
113EXPORT_SYMBOL_GPL(mxc_ulpi_access_ops);
114
115struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
116{
117 return otg_ulpi_create(&mxc_ulpi_access_ops, flags);
118}
diff --git a/arch/arm/mach-imx/ulpi.h b/arch/arm/mach-imx/ulpi.h
index 42bdaca6d7d9..23f5c0349e80 100644
--- a/arch/arm/mach-imx/ulpi.h
+++ b/arch/arm/mach-imx/ulpi.h
@@ -1,8 +1,13 @@
1#ifndef __MACH_ULPI_H 1#ifndef __MACH_ULPI_H
2#define __MACH_ULPI_H 2#define __MACH_ULPI_H
3 3
4#ifdef CONFIG_USB_ULPI 4#include <linux/usb/ulpi.h>
5struct usb_phy *imx_otg_ulpi_create(unsigned int flags); 5
6#ifdef CONFIG_USB_ULPI_VIEWPORT
7static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
8{
9 return otg_ulpi_create(&ulpi_viewport_access_ops, flags);
10}
6#else 11#else
7static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags) 12static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
8{ 13{
@@ -10,7 +15,5 @@ static inline struct usb_phy *imx_otg_ulpi_create(unsigned int flags)
10} 15}
11#endif 16#endif
12 17
13extern struct usb_phy_io_ops mxc_ulpi_access_ops;
14
15#endif /* __MACH_ULPI_H */ 18#endif /* __MACH_ULPI_H */
16 19
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 827cde42414f..e96fd71abd76 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -22,9 +22,10 @@ static unsigned int __init kirkwood_variant(void)
22 22
23 kirkwood_pcie_id(&dev, &rev); 23 kirkwood_pcie_id(&dev, &rev);
24 24
25 if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) || 25 if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
26 (dev == MV88F6282_DEV_ID))
27 return MPP_F6281_MASK; 26 return MPP_F6281_MASK;
27 if (dev == MV88F6282_DEV_ID)
28 return MPP_F6282_MASK;
28 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) 29 if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
29 return MPP_F6192_MASK; 30 return MPP_F6192_MASK;
30 if (dev == MV88F6180_DEV_ID) 31 if (dev == MV88F6180_DEV_ID)
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index 8f3bf4e50908..bbd6a3f717e6 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -20,11 +20,12 @@
20 20
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/clk-provider.h>
23#include <linux/io.h> 24#include <linux/io.h>
24 25
25#include "clock.h" 26#include "clock.h"
26#include "clock36xx.h" 27#include "clock36xx.h"
27 28#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
28 29
29/** 30/**
30 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering 31 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
@@ -39,29 +40,28 @@
39 */ 40 */
40int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk) 41int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
41{ 42{
42 struct clk_hw_omap *parent; 43 struct clk_divider *parent;
43 struct clk_hw *parent_hw; 44 struct clk_hw *parent_hw;
44 u32 dummy_v, orig_v, clksel_shift; 45 u32 dummy_v, orig_v;
45 int ret; 46 int ret;
46 47
47 /* Clear PWRDN bit of HSDIVIDER */ 48 /* Clear PWRDN bit of HSDIVIDER */
48 ret = omap2_dflt_clk_enable(clk); 49 ret = omap2_dflt_clk_enable(clk);
49 50
50 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk)); 51 parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
51 parent = to_clk_hw_omap(parent_hw); 52 parent = to_clk_divider(parent_hw);
52 53
53 /* Restore the dividers */ 54 /* Restore the dividers */
54 if (!ret) { 55 if (!ret) {
55 clksel_shift = __ffs(parent->clksel_mask); 56 orig_v = __raw_readl(parent->reg);
56 orig_v = __raw_readl(parent->clksel_reg);
57 dummy_v = orig_v; 57 dummy_v = orig_v;
58 58
59 /* Write any other value different from the Read value */ 59 /* Write any other value different from the Read value */
60 dummy_v ^= (1 << clksel_shift); 60 dummy_v ^= (1 << parent->shift);
61 __raw_writel(dummy_v, parent->clksel_reg); 61 __raw_writel(dummy_v, parent->reg);
62 62
63 /* Write the original divider */ 63 /* Write the original divider */
64 __raw_writel(orig_v, parent->clksel_reg); 64 __raw_writel(orig_v, parent->reg);
65 } 65 }
66 66
67 return ret; 67 return ret;
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 1e2a6fb835c2..0c9a183131e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -2008,6 +2008,13 @@ static struct omap_hwmod am33xx_uart1_hwmod = {
2008 }, 2008 },
2009}; 2009};
2010 2010
2011/* uart2 */
2012static struct omap_hwmod_dma_info uart2_edma_reqs[] = {
2013 { .name = "tx", .dma_req = 28, },
2014 { .name = "rx", .dma_req = 29, },
2015 { .dma_req = -1 }
2016};
2017
2011static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = { 2018static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2012 { .irq = 73 + OMAP_INTC_START, }, 2019 { .irq = 73 + OMAP_INTC_START, },
2013 { .irq = -1 }, 2020 { .irq = -1 },
@@ -2019,7 +2026,7 @@ static struct omap_hwmod am33xx_uart2_hwmod = {
2019 .clkdm_name = "l4ls_clkdm", 2026 .clkdm_name = "l4ls_clkdm",
2020 .flags = HWMOD_SWSUP_SIDLE_ACT, 2027 .flags = HWMOD_SWSUP_SIDLE_ACT,
2021 .mpu_irqs = am33xx_uart2_irqs, 2028 .mpu_irqs = am33xx_uart2_irqs,
2022 .sdma_reqs = uart1_edma_reqs, 2029 .sdma_reqs = uart2_edma_reqs,
2023 .main_clk = "dpll_per_m2_div4_ck", 2030 .main_clk = "dpll_per_m2_div4_ck",
2024 .prcm = { 2031 .prcm = {
2025 .omap4 = { 2032 .omap4 = {
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index c01859398b54..5a2d8034c8de 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -546,8 +546,10 @@ static void __init prcm_setup_regs(void)
546 /* Clear any pending PRCM interrupts */ 546 /* Clear any pending PRCM interrupts */
547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); 547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
548 548
549 if (omap3_has_iva()) 549 /*
550 omap3_iva_idle(); 550 * We need to idle iva2_pwrdm even on am3703 with no iva2.
551 */
552 omap3_iva_idle();
551 553
552 omap3_d2d_idle(); 554 omap3_d2d_idle();
553} 555}
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 9936c180bf01..8f595c0cc8d9 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -101,8 +101,10 @@ static int __init sirfsoc_of_pwrc_init(void)
101 struct device_node *np; 101 struct device_node *np;
102 102
103 np = of_find_matching_node(NULL, pwrc_ids); 103 np = of_find_matching_node(NULL, pwrc_ids);
104 if (!np) 104 if (!np) {
105 panic("unable to find compatible pwrc node in dtb\n"); 105 pr_err("unable to find compatible sirf pwrc node in dtb\n");
106 return -ENOENT;
107 }
106 108
107 /* 109 /*
108 * pwrc behind rtciobrg is not located in memory space 110 * pwrc behind rtciobrg is not located in memory space
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 435019ca0a48..d5e0cbc934c0 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -28,8 +28,10 @@ static int __init sirfsoc_of_rstc_init(void)
28 struct device_node *np; 28 struct device_node *np;
29 29
30 np = of_find_matching_node(NULL, rstc_ids); 30 np = of_find_matching_node(NULL, rstc_ids);
31 if (!np) 31 if (!np) {
32 panic("unable to find compatible rstc node in dtb\n"); 32 pr_err("unable to find compatible sirf rstc node in dtb\n");
33 return -ENOENT;
34 }
33 35
34 sirfsoc_rstc_base = of_iomap(np, 0); 36 sirfsoc_rstc_base = of_iomap(np, 0);
35 if (!sirfsoc_rstc_base) 37 if (!sirfsoc_rstc_base)
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 53210ec4e8ec..bd7124c87fea 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -16,6 +16,7 @@
16#include <linux/suspend.h> 16#include <linux/suspend.h>
17#include <linux/errno.h> 17#include <linux/errno.h>
18#include <linux/delay.h> 18#include <linux/delay.h>
19#include <linux/of.h>
19#include <linux/serial_core.h> 20#include <linux/serial_core.h>
20#include <linux/io.h> 21#include <linux/io.h>
21 22
@@ -261,7 +262,8 @@ static int s3c_pm_enter(suspend_state_t state)
261 * require a full power-cycle) 262 * require a full power-cycle)
262 */ 263 */
263 264
264 if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && 265 if (!of_have_populated_dt() &&
266 !any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
265 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { 267 !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
266 printk(KERN_ERR "%s: No wake-up sources!\n", __func__); 268 printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
267 printk(KERN_ERR "%s: Aborting sleep\n", __func__); 269 printk(KERN_ERR "%s: Aborting sleep\n", __func__);
@@ -270,8 +272,11 @@ static int s3c_pm_enter(suspend_state_t state)
270 272
271 /* save all necessary core registers not covered by the drivers */ 273 /* save all necessary core registers not covered by the drivers */
272 274
273 samsung_pm_save_gpios(); 275 if (!of_have_populated_dt()) {
274 samsung_pm_saved_gpios(); 276 samsung_pm_save_gpios();
277 samsung_pm_saved_gpios();
278 }
279
275 s3c_pm_save_uarts(); 280 s3c_pm_save_uarts();
276 s3c_pm_save_core(); 281 s3c_pm_save_core();
277 282
@@ -310,8 +315,11 @@ static int s3c_pm_enter(suspend_state_t state)
310 315
311 s3c_pm_restore_core(); 316 s3c_pm_restore_core();
312 s3c_pm_restore_uarts(); 317 s3c_pm_restore_uarts();
313 samsung_pm_restore_gpios(); 318
314 s3c_pm_restored_gpios(); 319 if (!of_have_populated_dt()) {
320 samsung_pm_restore_gpios();
321 s3c_pm_restored_gpios();
322 }
315 323
316 s3c_pm_debug_init(); 324 s3c_pm_debug_init();
317 325
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 820116067c10..516e6e9a5594 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -117,7 +117,7 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
117 if (! ((asid += ASID_INC) & ASID_MASK) ) { 117 if (! ((asid += ASID_INC) & ASID_MASK) ) {
118 if (cpu_has_vtag_icache) 118 if (cpu_has_vtag_icache)
119 flush_icache_all(); 119 flush_icache_all();
120#ifdef CONFIG_VIRTUALIZATION 120#ifdef CONFIG_KVM
121 kvm_local_flush_tlb_all(); /* start new asid cycle */ 121 kvm_local_flush_tlb_all(); /* start new asid cycle */
122#else 122#else
123 local_flush_tlb_all(); /* start new asid cycle */ 123 local_flush_tlb_all(); /* start new asid cycle */
diff --git a/arch/mips/include/uapi/asm/kvm.h b/arch/mips/include/uapi/asm/kvm.h
index 3f424f5217da..f09ff5ae2059 100644
--- a/arch/mips/include/uapi/asm/kvm.h
+++ b/arch/mips/include/uapi/asm/kvm.h
@@ -58,56 +58,53 @@ struct kvm_fpu {
58 * bits[2..0] - Register 'sel' index. 58 * bits[2..0] - Register 'sel' index.
59 * bits[7..3] - Register 'rd' index. 59 * bits[7..3] - Register 'rd' index.
60 * bits[15..8] - Must be zero. 60 * bits[15..8] - Must be zero.
61 * bits[63..16] - 1 -> CP0 registers. 61 * bits[31..16] - 1 -> CP0 registers.
62 * bits[51..32] - Must be zero.
63 * bits[63..52] - As per linux/kvm.h
62 * 64 *
63 * Other sets registers may be added in the future. Each set would 65 * Other sets registers may be added in the future. Each set would
64 * have its own identifier in bits[63..16]. 66 * have its own identifier in bits[31..16].
65 *
66 * The addr field of struct kvm_one_reg must point to an aligned
67 * 64-bit wide location. For registers that are narrower than
68 * 64-bits, the value is stored in the low order bits of the location,
69 * and sign extended to 64-bits.
70 * 67 *
71 * The registers defined in struct kvm_regs are also accessible, the 68 * The registers defined in struct kvm_regs are also accessible, the
72 * id values for these are below. 69 * id values for these are below.
73 */ 70 */
74 71
75#define KVM_REG_MIPS_R0 0 72#define KVM_REG_MIPS_R0 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0)
76#define KVM_REG_MIPS_R1 1 73#define KVM_REG_MIPS_R1 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 1)
77#define KVM_REG_MIPS_R2 2 74#define KVM_REG_MIPS_R2 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 2)
78#define KVM_REG_MIPS_R3 3 75#define KVM_REG_MIPS_R3 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 3)
79#define KVM_REG_MIPS_R4 4 76#define KVM_REG_MIPS_R4 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 4)
80#define KVM_REG_MIPS_R5 5 77#define KVM_REG_MIPS_R5 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 5)
81#define KVM_REG_MIPS_R6 6 78#define KVM_REG_MIPS_R6 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 6)
82#define KVM_REG_MIPS_R7 7 79#define KVM_REG_MIPS_R7 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 7)
83#define KVM_REG_MIPS_R8 8 80#define KVM_REG_MIPS_R8 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 8)
84#define KVM_REG_MIPS_R9 9 81#define KVM_REG_MIPS_R9 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 9)
85#define KVM_REG_MIPS_R10 10 82#define KVM_REG_MIPS_R10 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 10)
86#define KVM_REG_MIPS_R11 11 83#define KVM_REG_MIPS_R11 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 11)
87#define KVM_REG_MIPS_R12 12 84#define KVM_REG_MIPS_R12 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 12)
88#define KVM_REG_MIPS_R13 13 85#define KVM_REG_MIPS_R13 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 13)
89#define KVM_REG_MIPS_R14 14 86#define KVM_REG_MIPS_R14 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 14)
90#define KVM_REG_MIPS_R15 15 87#define KVM_REG_MIPS_R15 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 15)
91#define KVM_REG_MIPS_R16 16 88#define KVM_REG_MIPS_R16 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 16)
92#define KVM_REG_MIPS_R17 17 89#define KVM_REG_MIPS_R17 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 17)
93#define KVM_REG_MIPS_R18 18 90#define KVM_REG_MIPS_R18 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 18)
94#define KVM_REG_MIPS_R19 19 91#define KVM_REG_MIPS_R19 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 19)
95#define KVM_REG_MIPS_R20 20 92#define KVM_REG_MIPS_R20 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 20)
96#define KVM_REG_MIPS_R21 21 93#define KVM_REG_MIPS_R21 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 21)
97#define KVM_REG_MIPS_R22 22 94#define KVM_REG_MIPS_R22 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 22)
98#define KVM_REG_MIPS_R23 23 95#define KVM_REG_MIPS_R23 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 23)
99#define KVM_REG_MIPS_R24 24 96#define KVM_REG_MIPS_R24 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 24)
100#define KVM_REG_MIPS_R25 25 97#define KVM_REG_MIPS_R25 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 25)
101#define KVM_REG_MIPS_R26 26 98#define KVM_REG_MIPS_R26 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 26)
102#define KVM_REG_MIPS_R27 27 99#define KVM_REG_MIPS_R27 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 27)
103#define KVM_REG_MIPS_R28 28 100#define KVM_REG_MIPS_R28 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 28)
104#define KVM_REG_MIPS_R29 29 101#define KVM_REG_MIPS_R29 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 29)
105#define KVM_REG_MIPS_R30 30 102#define KVM_REG_MIPS_R30 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 30)
106#define KVM_REG_MIPS_R31 31 103#define KVM_REG_MIPS_R31 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 31)
107 104
108#define KVM_REG_MIPS_HI 32 105#define KVM_REG_MIPS_HI (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 32)
109#define KVM_REG_MIPS_LO 33 106#define KVM_REG_MIPS_LO (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 33)
110#define KVM_REG_MIPS_PC 34 107#define KVM_REG_MIPS_PC (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 34)
111 108
112/* 109/*
113 * KVM MIPS specific structures and definitions 110 * KVM MIPS specific structures and definitions
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index cf5509f13dd5..dba90ec0dc38 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -25,12 +25,16 @@
25#define MCOUNT_OFFSET_INSNS 4 25#define MCOUNT_OFFSET_INSNS 4
26#endif 26#endif
27 27
28#ifdef CONFIG_DYNAMIC_FTRACE
29
28/* Arch override because MIPS doesn't need to run this from stop_machine() */ 30/* Arch override because MIPS doesn't need to run this from stop_machine() */
29void arch_ftrace_update_code(int command) 31void arch_ftrace_update_code(int command)
30{ 32{
31 ftrace_modify_all_code(command); 33 ftrace_modify_all_code(command);
32} 34}
33 35
36#endif
37
34/* 38/*
35 * Check if the address is in kernel space 39 * Check if the address is in kernel space
36 * 40 *
diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c
index 3b09b888afa9..0c655deeea4a 100644
--- a/arch/mips/kernel/idle.c
+++ b/arch/mips/kernel/idle.c
@@ -93,26 +93,27 @@ static void rm7k_wait_irqoff(void)
93} 93}
94 94
95/* 95/*
96 * The Au1xxx wait is available only if using 32khz counter or 96 * Au1 'wait' is only useful when the 32kHz counter is used as timer,
97 * external timer source, but specifically not CP0 Counter. 97 * since coreclock (and the cp0 counter) stops upon executing it. Only an
98 * alchemy/common/time.c may override cpu_wait! 98 * interrupt can wake it, so they must be enabled before entering idle modes.
99 */ 99 */
100static void au1k_wait(void) 100static void au1k_wait(void)
101{ 101{
102 unsigned long c0status = read_c0_status() | 1; /* irqs on */
103
102 __asm__( 104 __asm__(
103 " .set mips3 \n" 105 " .set mips3 \n"
104 " cache 0x14, 0(%0) \n" 106 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n" 107 " cache 0x14, 32(%0) \n"
106 " sync \n" 108 " sync \n"
107 " nop \n" 109 " mtc0 %1, $12 \n" /* wr c0status */
108 " wait \n" 110 " wait \n"
109 " nop \n" 111 " nop \n"
110 " nop \n" 112 " nop \n"
111 " nop \n" 113 " nop \n"
112 " nop \n" 114 " nop \n"
113 " .set mips0 \n" 115 " .set mips0 \n"
114 : : "r" (au1k_wait)); 116 : : "r" (au1k_wait), "r" (c0status));
115 local_irq_enable();
116} 117}
117 118
118static int __initdata nowait; 119static int __initdata nowait;
diff --git a/arch/mips/kvm/kvm_mips.c b/arch/mips/kvm/kvm_mips.c
index d934b017f479..dd203e59e6fd 100644
--- a/arch/mips/kvm/kvm_mips.c
+++ b/arch/mips/kvm/kvm_mips.c
@@ -485,29 +485,35 @@ kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
485 return -ENOIOCTLCMD; 485 return -ENOIOCTLCMD;
486} 486}
487 487
488#define KVM_REG_MIPS_CP0_INDEX (0x10000 + 8 * 0 + 0) 488#define MIPS_CP0_32(_R, _S) \
489#define KVM_REG_MIPS_CP0_ENTRYLO0 (0x10000 + 8 * 2 + 0) 489 (KVM_REG_MIPS | KVM_REG_SIZE_U32 | 0x10000 | (8 * (_R) + (_S)))
490#define KVM_REG_MIPS_CP0_ENTRYLO1 (0x10000 + 8 * 3 + 0) 490
491#define KVM_REG_MIPS_CP0_CONTEXT (0x10000 + 8 * 4 + 0) 491#define MIPS_CP0_64(_R, _S) \
492#define KVM_REG_MIPS_CP0_USERLOCAL (0x10000 + 8 * 4 + 2) 492 (KVM_REG_MIPS | KVM_REG_SIZE_U64 | 0x10000 | (8 * (_R) + (_S)))
493#define KVM_REG_MIPS_CP0_PAGEMASK (0x10000 + 8 * 5 + 0) 493
494#define KVM_REG_MIPS_CP0_PAGEGRAIN (0x10000 + 8 * 5 + 1) 494#define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0)
495#define KVM_REG_MIPS_CP0_WIRED (0x10000 + 8 * 6 + 0) 495#define KVM_REG_MIPS_CP0_ENTRYLO0 MIPS_CP0_64(2, 0)
496#define KVM_REG_MIPS_CP0_HWRENA (0x10000 + 8 * 7 + 0) 496#define KVM_REG_MIPS_CP0_ENTRYLO1 MIPS_CP0_64(3, 0)
497#define KVM_REG_MIPS_CP0_BADVADDR (0x10000 + 8 * 8 + 0) 497#define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0)
498#define KVM_REG_MIPS_CP0_COUNT (0x10000 + 8 * 9 + 0) 498#define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2)
499#define KVM_REG_MIPS_CP0_ENTRYHI (0x10000 + 8 * 10 + 0) 499#define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0)
500#define KVM_REG_MIPS_CP0_COMPARE (0x10000 + 8 * 11 + 0) 500#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1)
501#define KVM_REG_MIPS_CP0_STATUS (0x10000 + 8 * 12 + 0) 501#define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0)
502#define KVM_REG_MIPS_CP0_CAUSE (0x10000 + 8 * 13 + 0) 502#define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0)
503#define KVM_REG_MIPS_CP0_EBASE (0x10000 + 8 * 15 + 1) 503#define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0)
504#define KVM_REG_MIPS_CP0_CONFIG (0x10000 + 8 * 16 + 0) 504#define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0)
505#define KVM_REG_MIPS_CP0_CONFIG1 (0x10000 + 8 * 16 + 1) 505#define KVM_REG_MIPS_CP0_ENTRYHI MIPS_CP0_64(10, 0)
506#define KVM_REG_MIPS_CP0_CONFIG2 (0x10000 + 8 * 16 + 2) 506#define KVM_REG_MIPS_CP0_COMPARE MIPS_CP0_32(11, 0)
507#define KVM_REG_MIPS_CP0_CONFIG3 (0x10000 + 8 * 16 + 3) 507#define KVM_REG_MIPS_CP0_STATUS MIPS_CP0_32(12, 0)
508#define KVM_REG_MIPS_CP0_CONFIG7 (0x10000 + 8 * 16 + 7) 508#define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0)
509#define KVM_REG_MIPS_CP0_XCONTEXT (0x10000 + 8 * 20 + 0) 509#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1)
510#define KVM_REG_MIPS_CP0_ERROREPC (0x10000 + 8 * 30 + 0) 510#define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0)
511#define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1)
512#define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2)
513#define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3)
514#define KVM_REG_MIPS_CP0_CONFIG7 MIPS_CP0_32(16, 7)
515#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0)
516#define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0)
511 517
512static u64 kvm_mips_get_one_regs[] = { 518static u64 kvm_mips_get_one_regs[] = {
513 KVM_REG_MIPS_R0, 519 KVM_REG_MIPS_R0,
@@ -567,8 +573,6 @@ static u64 kvm_mips_get_one_regs[] = {
567static int kvm_mips_get_reg(struct kvm_vcpu *vcpu, 573static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
568 const struct kvm_one_reg *reg) 574 const struct kvm_one_reg *reg)
569{ 575{
570 u64 __user *uaddr = (u64 __user *)(long)reg->addr;
571
572 struct mips_coproc *cop0 = vcpu->arch.cop0; 576 struct mips_coproc *cop0 = vcpu->arch.cop0;
573 s64 v; 577 s64 v;
574 578
@@ -631,18 +635,39 @@ static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
631 default: 635 default:
632 return -EINVAL; 636 return -EINVAL;
633 } 637 }
634 return put_user(v, uaddr); 638 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
639 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
640 return put_user(v, uaddr64);
641 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
642 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
643 u32 v32 = (u32)v;
644 return put_user(v32, uaddr32);
645 } else {
646 return -EINVAL;
647 }
635} 648}
636 649
637static int kvm_mips_set_reg(struct kvm_vcpu *vcpu, 650static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
638 const struct kvm_one_reg *reg) 651 const struct kvm_one_reg *reg)
639{ 652{
640 u64 __user *uaddr = (u64 __user *)(long)reg->addr;
641 struct mips_coproc *cop0 = vcpu->arch.cop0; 653 struct mips_coproc *cop0 = vcpu->arch.cop0;
642 u64 v; 654 u64 v;
643 655
644 if (get_user(v, uaddr) != 0) 656 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
645 return -EFAULT; 657 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
658
659 if (get_user(v, uaddr64) != 0)
660 return -EFAULT;
661 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
662 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
663 s32 v32;
664
665 if (get_user(v32, uaddr32) != 0)
666 return -EFAULT;
667 v = (s64)v32;
668 } else {
669 return -EINVAL;
670 }
646 671
647 switch (reg->id) { 672 switch (reg->id) {
648 case KVM_REG_MIPS_R0: 673 case KVM_REG_MIPS_R0:
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 26807e5aff51..6f3887d884d2 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -176,6 +176,7 @@ extern const char *powerpc_base_platform;
176#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000) 176#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
177#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000) 177#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
178#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000) 178#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
179#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
179 180
180#ifndef __ASSEMBLY__ 181#ifndef __ASSEMBLY__
181 182
@@ -394,19 +395,20 @@ extern const char *powerpc_base_platform;
394 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \ 395 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
395 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ 396 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
396 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \ 397 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
397 CPU_FTR_HVMODE) 398 CPU_FTR_HVMODE | CPU_FTR_DABRX)
398#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 399#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
399 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 400 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
400 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 401 CPU_FTR_MMCRA | CPU_FTR_SMT | \
401 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \ 402 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
402 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB) 403 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
403#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 404#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
404 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 405 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
405 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 406 CPU_FTR_MMCRA | CPU_FTR_SMT | \
406 CPU_FTR_COHERENT_ICACHE | \ 407 CPU_FTR_COHERENT_ICACHE | \
407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ 408 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
408 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \ 409 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
409 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR) 410 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
411 CPU_FTR_DABRX)
410#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 412#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
411 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
412 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 414 CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -415,7 +417,7 @@ extern const char *powerpc_base_platform;
415 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \ 417 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
416 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 418 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
417 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \ 419 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
418 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR) 420 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
419#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 421#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
420 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\ 422 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
421 CPU_FTR_MMCRA | CPU_FTR_SMT | \ 423 CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -430,14 +432,15 @@ extern const char *powerpc_base_platform;
430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ 432 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
431 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ 433 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
432 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ 434 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
433 CPU_FTR_UNALIGNED_LD_STD) 435 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
434#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ 436#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
435 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \ 437 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
436 CPU_FTR_PURR | CPU_FTR_REAL_LE) 438 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
437#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) 439#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
438 440
439#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \ 441#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
440 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX) 442 CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
443 CPU_FTR_ICSWX | CPU_FTR_DABRX )
441 444
442#ifdef __powerpc64__ 445#ifdef __powerpc64__
443#ifdef CONFIG_PPC_BOOK3E 446#ifdef CONFIG_PPC_BOOK3E
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 8e5fae8beaf6..46793b58a761 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -513,7 +513,7 @@ label##_common: \
513 */ 513 */
514#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \ 514#define STD_EXCEPTION_COMMON_ASYNC(trap, label, hdlr) \
515 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \ 515 EXCEPTION_COMMON(trap, label, hdlr, ret_from_except_lite, \
516 FINISH_NAP;RUNLATCH_ON;DISABLE_INTS) 516 FINISH_NAP;DISABLE_INTS;RUNLATCH_ON)
517 517
518/* 518/*
519 * When the idle code in power4_idle puts the CPU into NAP mode, 519 * When the idle code in power4_idle puts the CPU into NAP mode,
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index b9dd382cb349..851bac7afa4b 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -54,8 +54,16 @@
54#define BOOKE_INTERRUPT_DEBUG 15 54#define BOOKE_INTERRUPT_DEBUG 15
55 55
56/* E500 */ 56/* E500 */
57#define BOOKE_INTERRUPT_SPE_UNAVAIL 32 57#define BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL 32
58#define BOOKE_INTERRUPT_SPE_FP_DATA 33 58#define BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST 33
59/*
60 * TODO: Unify 32-bit and 64-bit kernel exception handlers to use same defines
61 */
62#define BOOKE_INTERRUPT_SPE_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
63#define BOOKE_INTERRUPT_SPE_FP_DATA BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
64#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL
65#define BOOKE_INTERRUPT_ALTIVEC_ASSIST \
66 BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST
59#define BOOKE_INTERRUPT_SPE_FP_ROUND 34 67#define BOOKE_INTERRUPT_SPE_FP_ROUND 34
60#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35 68#define BOOKE_INTERRUPT_PERFORMANCE_MONITOR 35
61#define BOOKE_INTERRUPT_DOORBELL 36 69#define BOOKE_INTERRUPT_DOORBELL 36
@@ -67,10 +75,6 @@
67#define BOOKE_INTERRUPT_HV_SYSCALL 40 75#define BOOKE_INTERRUPT_HV_SYSCALL 40
68#define BOOKE_INTERRUPT_HV_PRIV 41 76#define BOOKE_INTERRUPT_HV_PRIV 41
69 77
70/* altivec */
71#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
72#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
73
74/* book3s */ 78/* book3s */
75 79
76#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100 80#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 1f0937d7d4b5..2a45d0f04385 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -452,8 +452,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
452 .mmu_features = MMU_FTRS_POWER8, 452 .mmu_features = MMU_FTRS_POWER8,
453 .icache_bsize = 128, 453 .icache_bsize = 128,
454 .dcache_bsize = 128, 454 .dcache_bsize = 128,
455 .oprofile_type = PPC_OPROFILE_POWER4, 455 .oprofile_type = PPC_OPROFILE_INVALID,
456 .oprofile_cpu_type = 0, 456 .oprofile_cpu_type = "ppc64/ibm-compat-v1",
457 .cpu_setup = __setup_cpu_power8, 457 .cpu_setup = __setup_cpu_power8,
458 .cpu_restore = __restore_cpu_power8, 458 .cpu_restore = __restore_cpu_power8,
459 .platform = "power8", 459 .platform = "power8",
@@ -506,8 +506,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
506 .dcache_bsize = 128, 506 .dcache_bsize = 128,
507 .num_pmcs = 6, 507 .num_pmcs = 6,
508 .pmc_type = PPC_PMC_IBM, 508 .pmc_type = PPC_PMC_IBM,
509 .oprofile_cpu_type = 0, 509 .oprofile_cpu_type = "ppc64/power8",
510 .oprofile_type = PPC_OPROFILE_POWER4, 510 .oprofile_type = PPC_OPROFILE_INVALID,
511 .cpu_setup = __setup_cpu_power8, 511 .cpu_setup = __setup_cpu_power8,
512 .cpu_restore = __restore_cpu_power8, 512 .cpu_restore = __restore_cpu_power8,
513 .platform = "power8", 513 .platform = "power8",
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 246b11c4fe7e..8741c854e03d 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -465,20 +465,6 @@ BEGIN_FTR_SECTION
465 std r0, THREAD_EBBHR(r3) 465 std r0, THREAD_EBBHR(r3)
466 mfspr r0, SPRN_EBBRR 466 mfspr r0, SPRN_EBBRR
467 std r0, THREAD_EBBRR(r3) 467 std r0, THREAD_EBBRR(r3)
468
469 /* PMU registers made user read/(write) by EBB */
470 mfspr r0, SPRN_SIAR
471 std r0, THREAD_SIAR(r3)
472 mfspr r0, SPRN_SDAR
473 std r0, THREAD_SDAR(r3)
474 mfspr r0, SPRN_SIER
475 std r0, THREAD_SIER(r3)
476 mfspr r0, SPRN_MMCR0
477 std r0, THREAD_MMCR0(r3)
478 mfspr r0, SPRN_MMCR2
479 std r0, THREAD_MMCR2(r3)
480 mfspr r0, SPRN_MMCRA
481 std r0, THREAD_MMCRA(r3)
482END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 468END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
483#endif 469#endif
484 470
@@ -581,20 +567,6 @@ BEGIN_FTR_SECTION
581 ld r0, THREAD_EBBRR(r4) 567 ld r0, THREAD_EBBRR(r4)
582 mtspr SPRN_EBBRR, r0 568 mtspr SPRN_EBBRR, r0
583 569
584 /* PMU registers made user read/(write) by EBB */
585 ld r0, THREAD_SIAR(r4)
586 mtspr SPRN_SIAR, r0
587 ld r0, THREAD_SDAR(r4)
588 mtspr SPRN_SDAR, r0
589 ld r0, THREAD_SIER(r4)
590 mtspr SPRN_SIER, r0
591 ld r0, THREAD_MMCR0(r4)
592 mtspr SPRN_MMCR0, r0
593 ld r0, THREAD_MMCR2(r4)
594 mtspr SPRN_MMCR2, r0
595 ld r0, THREAD_MMCRA(r4)
596 mtspr SPRN_MMCRA, r0
597
598 ld r0,THREAD_TAR(r4) 570 ld r0,THREAD_TAR(r4)
599 mtspr SPRN_TAR,r0 571 mtspr SPRN_TAR,r0
600END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 572END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index e6eba1bf61ad..40e4a17c8ba0 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -454,38 +454,14 @@ BEGIN_FTR_SECTION
454 xori r10,r10,(MSR_FE0|MSR_FE1) 454 xori r10,r10,(MSR_FE0|MSR_FE1)
455 mtmsrd r10 455 mtmsrd r10
456 sync 456 sync
457 fmr 0,0 457
458 fmr 1,1 458#define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
459 fmr 2,2 459#define FMR4(n) FMR2(n) ; FMR2(n+2)
460 fmr 3,3 460#define FMR8(n) FMR4(n) ; FMR4(n+4)
461 fmr 4,4 461#define FMR16(n) FMR8(n) ; FMR8(n+8)
462 fmr 5,5 462#define FMR32(n) FMR16(n) ; FMR16(n+16)
463 fmr 6,6 463 FMR32(0)
464 fmr 7,7 464
465 fmr 8,8
466 fmr 9,9
467 fmr 10,10
468 fmr 11,11
469 fmr 12,12
470 fmr 13,13
471 fmr 14,14
472 fmr 15,15
473 fmr 16,16
474 fmr 17,17
475 fmr 18,18
476 fmr 19,19
477 fmr 20,20
478 fmr 21,21
479 fmr 22,22
480 fmr 23,23
481 fmr 24,24
482 fmr 25,25
483 fmr 26,26
484 fmr 27,27
485 fmr 28,28
486 fmr 29,29
487 fmr 30,30
488 fmr 31,31
489FTR_SECTION_ELSE 465FTR_SECTION_ELSE
490/* 466/*
491 * To denormalise we need to move a copy of the register to itself. 467 * To denormalise we need to move a copy of the register to itself.
@@ -495,39 +471,25 @@ FTR_SECTION_ELSE
495 oris r10,r10,MSR_VSX@h 471 oris r10,r10,MSR_VSX@h
496 mtmsrd r10 472 mtmsrd r10
497 sync 473 sync
498 XVCPSGNDP(0,0,0) 474
499 XVCPSGNDP(1,1,1) 475#define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
500 XVCPSGNDP(2,2,2) 476#define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
501 XVCPSGNDP(3,3,3) 477#define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
502 XVCPSGNDP(4,4,4) 478#define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
503 XVCPSGNDP(5,5,5) 479#define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
504 XVCPSGNDP(6,6,6) 480 XVCPSGNDP32(0)
505 XVCPSGNDP(7,7,7) 481
506 XVCPSGNDP(8,8,8)
507 XVCPSGNDP(9,9,9)
508 XVCPSGNDP(10,10,10)
509 XVCPSGNDP(11,11,11)
510 XVCPSGNDP(12,12,12)
511 XVCPSGNDP(13,13,13)
512 XVCPSGNDP(14,14,14)
513 XVCPSGNDP(15,15,15)
514 XVCPSGNDP(16,16,16)
515 XVCPSGNDP(17,17,17)
516 XVCPSGNDP(18,18,18)
517 XVCPSGNDP(19,19,19)
518 XVCPSGNDP(20,20,20)
519 XVCPSGNDP(21,21,21)
520 XVCPSGNDP(22,22,22)
521 XVCPSGNDP(23,23,23)
522 XVCPSGNDP(24,24,24)
523 XVCPSGNDP(25,25,25)
524 XVCPSGNDP(26,26,26)
525 XVCPSGNDP(27,27,27)
526 XVCPSGNDP(28,28,28)
527 XVCPSGNDP(29,29,29)
528 XVCPSGNDP(30,30,30)
529 XVCPSGNDP(31,31,31)
530ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) 482ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
483
484BEGIN_FTR_SECTION
485 b denorm_done
486END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
487/*
488 * To denormalise we need to move a copy of the register to itself.
489 * For POWER8 we need to do that for all 64 VSX registers
490 */
491 XVCPSGNDP32(32)
492denorm_done:
531 mtspr SPRN_HSRR0,r11 493 mtspr SPRN_HSRR0,r11
532 mtcrf 0x80,r9 494 mtcrf 0x80,r9
533 ld r9,PACA_EXGEN+EX_R9(r13) 495 ld r9,PACA_EXGEN+EX_R9(r13)
@@ -721,7 +683,7 @@ machine_check_common:
721 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception) 683 STD_EXCEPTION_COMMON(0xb00, trap_0b, .unknown_exception)
722 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception) 684 STD_EXCEPTION_COMMON(0xd00, single_step, .single_step_exception)
723 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception) 685 STD_EXCEPTION_COMMON(0xe00, trap_0e, .unknown_exception)
724 STD_EXCEPTION_COMMON(0xe40, emulation_assist, .program_check_exception) 686 STD_EXCEPTION_COMMON(0xe40, emulation_assist, .emulation_assist_interrupt)
725 STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception) 687 STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
726#ifdef CONFIG_PPC_DOORBELL 688#ifdef CONFIG_PPC_DOORBELL
727 STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception) 689 STD_EXCEPTION_COMMON_ASYNC(0xe80, h_doorbell, .doorbell_exception)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5cbcf4d5a808..ea185e0b3cae 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -162,7 +162,7 @@ notrace unsigned int __check_irq_replay(void)
162 * in case we also had a rollover while hard disabled 162 * in case we also had a rollover while hard disabled
163 */ 163 */
164 local_paca->irq_happened &= ~PACA_IRQ_DEC; 164 local_paca->irq_happened &= ~PACA_IRQ_DEC;
165 if (decrementer_check_overflow()) 165 if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow())
166 return 0x900; 166 return 0x900;
167 167
168 /* Finally check if an external interrupt happened */ 168 /* Finally check if an external interrupt happened */
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 7f2273cc3c7d..eabeec991016 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -827,6 +827,7 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
827 } 827 }
828 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 828 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
829 struct resource *res = dev->resource + i; 829 struct resource *res = dev->resource + i;
830 struct pci_bus_region reg;
830 if (!res->flags) 831 if (!res->flags)
831 continue; 832 continue;
832 833
@@ -835,8 +836,9 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
835 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set 836 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
836 * since in that case, we don't want to re-assign anything 837 * since in that case, we don't want to re-assign anything
837 */ 838 */
839 pcibios_resource_to_bus(dev, &reg, res);
838 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) || 840 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
839 (res->start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) { 841 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
840 /* Only print message if not re-assigning */ 842 /* Only print message if not re-assigning */
841 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) 843 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
842 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] " 844 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] "
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index a902723fdc69..076d1242507a 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -399,7 +399,8 @@ static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
399static inline int __set_dabr(unsigned long dabr, unsigned long dabrx) 399static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
400{ 400{
401 mtspr(SPRN_DABR, dabr); 401 mtspr(SPRN_DABR, dabr);
402 mtspr(SPRN_DABRX, dabrx); 402 if (cpu_has_feature(CPU_FTR_DABRX))
403 mtspr(SPRN_DABRX, dabrx);
403 return 0; 404 return 0;
404} 405}
405#else 406#else
@@ -1368,7 +1369,7 @@ void show_stack(struct task_struct *tsk, unsigned long *stack)
1368 1369
1369#ifdef CONFIG_PPC64 1370#ifdef CONFIG_PPC64
1370/* Called with hard IRQs off */ 1371/* Called with hard IRQs off */
1371void __ppc64_runlatch_on(void) 1372void notrace __ppc64_runlatch_on(void)
1372{ 1373{
1373 struct thread_info *ti = current_thread_info(); 1374 struct thread_info *ti = current_thread_info();
1374 unsigned long ctrl; 1375 unsigned long ctrl;
@@ -1381,7 +1382,7 @@ void __ppc64_runlatch_on(void)
1381} 1382}
1382 1383
1383/* Called with hard IRQs off */ 1384/* Called with hard IRQs off */
1384void __ppc64_runlatch_off(void) 1385void notrace __ppc64_runlatch_off(void)
1385{ 1386{
1386 struct thread_info *ti = current_thread_info(); 1387 struct thread_info *ti = current_thread_info();
1387 unsigned long ctrl; 1388 unsigned long ctrl;
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f18c79c324ef..c0e5caf8ccc7 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -1165,6 +1165,16 @@ bail:
1165 exception_exit(prev_state); 1165 exception_exit(prev_state);
1166} 1166}
1167 1167
1168/*
1169 * This occurs when running in hypervisor mode on POWER6 or later
1170 * and an illegal instruction is encountered.
1171 */
1172void __kprobes emulation_assist_interrupt(struct pt_regs *regs)
1173{
1174 regs->msr |= REASON_ILLEGAL;
1175 program_check_exception(regs);
1176}
1177
1168void alignment_exception(struct pt_regs *regs) 1178void alignment_exception(struct pt_regs *regs)
1169{ 1179{
1170 enum ctx_state prev_state = exception_enter(); 1180 enum ctx_state prev_state = exception_enter();
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 5dd3ab469976..ed0385448148 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -441,6 +441,7 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
441 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu); 441 struct kvmppc_vcpu_44x *vcpu_44x = to_44x(vcpu);
442 struct kvmppc_44x_tlbe *tlbe; 442 struct kvmppc_44x_tlbe *tlbe;
443 unsigned int gtlb_index; 443 unsigned int gtlb_index;
444 int idx;
444 445
445 gtlb_index = kvmppc_get_gpr(vcpu, ra); 446 gtlb_index = kvmppc_get_gpr(vcpu, ra);
446 if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) { 447 if (gtlb_index >= KVM44x_GUEST_TLB_SIZE) {
@@ -473,6 +474,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
473 return EMULATE_FAIL; 474 return EMULATE_FAIL;
474 } 475 }
475 476
477 idx = srcu_read_lock(&vcpu->kvm->srcu);
478
476 if (tlbe_is_host_safe(vcpu, tlbe)) { 479 if (tlbe_is_host_safe(vcpu, tlbe)) {
477 gva_t eaddr; 480 gva_t eaddr;
478 gpa_t gpaddr; 481 gpa_t gpaddr;
@@ -489,6 +492,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
489 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index); 492 kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
490 } 493 }
491 494
495 srcu_read_unlock(&vcpu->kvm->srcu, idx);
496
492 trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1, 497 trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
493 tlbe->word2); 498 tlbe->word2);
494 499
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 1020119226db..5cd7ad0c1176 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -832,6 +832,18 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
832{ 832{
833 int r = RESUME_HOST; 833 int r = RESUME_HOST;
834 int s; 834 int s;
835 int idx;
836
837#ifdef CONFIG_PPC64
838 WARN_ON(local_paca->irq_happened != 0);
839#endif
840
841 /*
842 * We enter with interrupts disabled in hardware, but
843 * we need to call hard_irq_disable anyway to ensure that
844 * the software state is kept in sync.
845 */
846 hard_irq_disable();
835 847
836 /* update before a new last_exit_type is rewritten */ 848 /* update before a new last_exit_type is rewritten */
837 kvmppc_update_timing_stats(vcpu); 849 kvmppc_update_timing_stats(vcpu);
@@ -1053,6 +1065,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1053 break; 1065 break;
1054 } 1066 }
1055 1067
1068 idx = srcu_read_lock(&vcpu->kvm->srcu);
1069
1056 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1070 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1057 gfn = gpaddr >> PAGE_SHIFT; 1071 gfn = gpaddr >> PAGE_SHIFT;
1058 1072
@@ -1075,6 +1089,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1075 kvmppc_account_exit(vcpu, MMIO_EXITS); 1089 kvmppc_account_exit(vcpu, MMIO_EXITS);
1076 } 1090 }
1077 1091
1092 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1078 break; 1093 break;
1079 } 1094 }
1080 1095
@@ -1098,6 +1113,8 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1098 1113
1099 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS); 1114 kvmppc_account_exit(vcpu, ITLB_VIRT_MISS_EXITS);
1100 1115
1116 idx = srcu_read_lock(&vcpu->kvm->srcu);
1117
1101 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr); 1118 gpaddr = kvmppc_mmu_xlate(vcpu, gtlb_index, eaddr);
1102 gfn = gpaddr >> PAGE_SHIFT; 1119 gfn = gpaddr >> PAGE_SHIFT;
1103 1120
@@ -1114,6 +1131,7 @@ int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
1114 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK); 1131 kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_MACHINE_CHECK);
1115 } 1132 }
1116 1133
1134 srcu_read_unlock(&vcpu->kvm->srcu, idx);
1117 break; 1135 break;
1118 } 1136 }
1119 1137
diff --git a/arch/powerpc/kvm/e500_mmu.c b/arch/powerpc/kvm/e500_mmu.c
index c41a5a96b558..6d6f153b6c1d 100644
--- a/arch/powerpc/kvm/e500_mmu.c
+++ b/arch/powerpc/kvm/e500_mmu.c
@@ -396,6 +396,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
396 struct kvm_book3e_206_tlb_entry *gtlbe; 396 struct kvm_book3e_206_tlb_entry *gtlbe;
397 int tlbsel, esel; 397 int tlbsel, esel;
398 int recal = 0; 398 int recal = 0;
399 int idx;
399 400
400 tlbsel = get_tlb_tlbsel(vcpu); 401 tlbsel = get_tlb_tlbsel(vcpu);
401 esel = get_tlb_esel(vcpu, tlbsel); 402 esel = get_tlb_esel(vcpu, tlbsel);
@@ -430,6 +431,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
430 kvmppc_set_tlb1map_range(vcpu, gtlbe); 431 kvmppc_set_tlb1map_range(vcpu, gtlbe);
431 } 432 }
432 433
434 idx = srcu_read_lock(&vcpu->kvm->srcu);
435
433 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */ 436 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
434 if (tlbe_is_host_safe(vcpu, gtlbe)) { 437 if (tlbe_is_host_safe(vcpu, gtlbe)) {
435 u64 eaddr = get_tlb_eaddr(gtlbe); 438 u64 eaddr = get_tlb_eaddr(gtlbe);
@@ -444,6 +447,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
444 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel)); 447 kvmppc_mmu_map(vcpu, eaddr, raddr, index_of(tlbsel, esel));
445 } 448 }
446 449
450 srcu_read_unlock(&vcpu->kvm->srcu, idx);
451
447 kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS); 452 kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
448 return EMULATE_DONE; 453 return EMULATE_DONE;
449} 454}
diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
index 753cc99eff2b..19c8379575f7 100644
--- a/arch/powerpc/kvm/e500mc.c
+++ b/arch/powerpc/kvm/e500mc.c
@@ -177,8 +177,6 @@ int kvmppc_core_check_processor_compat(void)
177 r = 0; 177 r = 0;
178 else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0) 178 else if (strcmp(cur_cpu_spec->cpu_name, "e5500") == 0)
179 r = 0; 179 r = 0;
180 else if (strcmp(cur_cpu_spec->cpu_name, "e6500") == 0)
181 r = 0;
182 else 180 else
183 r = -ENOTSUPP; 181 r = -ENOTSUPP;
184 182
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 845c867444e6..29c6482890c8 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c
@@ -1758,7 +1758,7 @@ static void perf_event_interrupt(struct pt_regs *regs)
1758 } 1758 }
1759 } 1759 }
1760 } 1760 }
1761 if ((!found) && printk_ratelimit()) 1761 if (!found && !nmi && printk_ratelimit())
1762 printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 1762 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
1763 1763
1764 /* 1764 /*
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 19506f935737..b456b157d33d 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -83,7 +83,11 @@ static int pseries_eeh_init(void)
83 ibm_configure_pe = rtas_token("ibm,configure-pe"); 83 ibm_configure_pe = rtas_token("ibm,configure-pe");
84 ibm_configure_bridge = rtas_token("ibm,configure-bridge"); 84 ibm_configure_bridge = rtas_token("ibm,configure-bridge");
85 85
86 /* necessary sanity check */ 86 /*
87 * Necessary sanity check. We needn't check "get-config-addr-info"
88 * and its variant since the old firmware probably support address
89 * of domain/bus/slot/function for EEH RTAS operations.
90 */
87 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) { 91 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE) {
88 pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n", 92 pr_warning("%s: RTAS service <ibm,set-eeh-option> invalid\n",
89 __func__); 93 __func__);
@@ -102,12 +106,6 @@ static int pseries_eeh_init(void)
102 pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n", 106 pr_warning("%s: RTAS service <ibm,slot-error-detail> invalid\n",
103 __func__); 107 __func__);
104 return -EINVAL; 108 return -EINVAL;
105 } else if (ibm_get_config_addr_info2 == RTAS_UNKNOWN_SERVICE &&
106 ibm_get_config_addr_info == RTAS_UNKNOWN_SERVICE) {
107 pr_warning("%s: RTAS service <ibm,get-config-addr-info2> and "
108 "<ibm,get-config-addr-info> invalid\n",
109 __func__);
110 return -EINVAL;
111 } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE && 109 } else if (ibm_configure_pe == RTAS_UNKNOWN_SERVICE &&
112 ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) { 110 ibm_configure_bridge == RTAS_UNKNOWN_SERVICE) {
113 pr_warning("%s: RTAS service <ibm,configure-pe> and " 111 pr_warning("%s: RTAS service <ibm,configure-pe> and "
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index ac01463038f1..e8b6e5b8932c 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -623,7 +623,7 @@ static inline pgste_t pgste_get_lock(pte_t *ptep)
623 " csg %0,%1,%2\n" 623 " csg %0,%1,%2\n"
624 " jl 0b\n" 624 " jl 0b\n"
625 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE]) 625 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
626 : "Q" (ptep[PTRS_PER_PTE]) : "cc"); 626 : "Q" (ptep[PTRS_PER_PTE]) : "cc", "memory");
627#endif 627#endif
628 return __pgste(new); 628 return __pgste(new);
629} 629}
@@ -635,11 +635,19 @@ static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
635 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */ 635 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
636 " stg %1,%0\n" 636 " stg %1,%0\n"
637 : "=Q" (ptep[PTRS_PER_PTE]) 637 : "=Q" (ptep[PTRS_PER_PTE])
638 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc"); 638 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE])
639 : "cc", "memory");
639 preempt_enable(); 640 preempt_enable();
640#endif 641#endif
641} 642}
642 643
644static inline void pgste_set(pte_t *ptep, pgste_t pgste)
645{
646#ifdef CONFIG_PGSTE
647 *(pgste_t *)(ptep + PTRS_PER_PTE) = pgste;
648#endif
649}
650
643static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste) 651static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
644{ 652{
645#ifdef CONFIG_PGSTE 653#ifdef CONFIG_PGSTE
@@ -704,17 +712,19 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
704{ 712{
705#ifdef CONFIG_PGSTE 713#ifdef CONFIG_PGSTE
706 unsigned long address; 714 unsigned long address;
707 unsigned long okey, nkey; 715 unsigned long nkey;
708 716
709 if (pte_val(entry) & _PAGE_INVALID) 717 if (pte_val(entry) & _PAGE_INVALID)
710 return; 718 return;
719 VM_BUG_ON(!(pte_val(*ptep) & _PAGE_INVALID));
711 address = pte_val(entry) & PAGE_MASK; 720 address = pte_val(entry) & PAGE_MASK;
712 okey = nkey = page_get_storage_key(address); 721 /*
713 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT); 722 * Set page access key and fetch protection bit from pgste.
714 /* Set page access key and fetch protection bit from pgste */ 723 * The guest C/R information is still in the PGSTE, set real
715 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56; 724 * key C/R to 0.
716 if (okey != nkey) 725 */
717 page_set_storage_key(address, nkey, 0); 726 nkey = (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
727 page_set_storage_key(address, nkey, 0);
718#endif 728#endif
719} 729}
720 730
@@ -1099,8 +1109,10 @@ static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1099 if (!mm_exclusive(mm)) 1109 if (!mm_exclusive(mm))
1100 __ptep_ipte(address, ptep); 1110 __ptep_ipte(address, ptep);
1101 1111
1102 if (mm_has_pgste(mm)) 1112 if (mm_has_pgste(mm)) {
1103 pgste = pgste_update_all(&pte, pgste); 1113 pgste = pgste_update_all(&pte, pgste);
1114 pgste_set(ptep, pgste);
1115 }
1104 return pte; 1116 return pte;
1105} 1117}
1106 1118
diff --git a/arch/s390/kernel/dumpstack.c b/arch/s390/kernel/dumpstack.c
index 298297477257..87acc38f73c6 100644
--- a/arch/s390/kernel/dumpstack.c
+++ b/arch/s390/kernel/dumpstack.c
@@ -74,6 +74,8 @@ __show_trace(unsigned long sp, unsigned long low, unsigned long high)
74 74
75static void show_trace(struct task_struct *task, unsigned long *stack) 75static void show_trace(struct task_struct *task, unsigned long *stack)
76{ 76{
77 const unsigned long frame_size =
78 STACK_FRAME_OVERHEAD + sizeof(struct pt_regs);
77 register unsigned long __r15 asm ("15"); 79 register unsigned long __r15 asm ("15");
78 unsigned long sp; 80 unsigned long sp;
79 81
@@ -82,11 +84,13 @@ static void show_trace(struct task_struct *task, unsigned long *stack)
82 sp = task ? task->thread.ksp : __r15; 84 sp = task ? task->thread.ksp : __r15;
83 printk("Call Trace:\n"); 85 printk("Call Trace:\n");
84#ifdef CONFIG_CHECK_STACK 86#ifdef CONFIG_CHECK_STACK
85 sp = __show_trace(sp, S390_lowcore.panic_stack - 4096, 87 sp = __show_trace(sp,
86 S390_lowcore.panic_stack); 88 S390_lowcore.panic_stack + frame_size - 4096,
89 S390_lowcore.panic_stack + frame_size);
87#endif 90#endif
88 sp = __show_trace(sp, S390_lowcore.async_stack - ASYNC_SIZE, 91 sp = __show_trace(sp,
89 S390_lowcore.async_stack); 92 S390_lowcore.async_stack + frame_size - ASYNC_SIZE,
93 S390_lowcore.async_stack + frame_size);
90 if (task) 94 if (task)
91 __show_trace(sp, (unsigned long) task_stack_page(task), 95 __show_trace(sp, (unsigned long) task_stack_page(task),
92 (unsigned long) task_stack_page(task) + THREAD_SIZE); 96 (unsigned long) task_stack_page(task) + THREAD_SIZE);
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index f7fb58903f6a..408e866ae548 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -311,3 +311,67 @@ void measurement_alert_subclass_unregister(void)
311 spin_unlock(&ma_subclass_lock); 311 spin_unlock(&ma_subclass_lock);
312} 312}
313EXPORT_SYMBOL(measurement_alert_subclass_unregister); 313EXPORT_SYMBOL(measurement_alert_subclass_unregister);
314
315void synchronize_irq(unsigned int irq)
316{
317 /*
318 * Not needed, the handler is protected by a lock and IRQs that occur
319 * after the handler is deleted are just NOPs.
320 */
321}
322EXPORT_SYMBOL_GPL(synchronize_irq);
323
324#ifndef CONFIG_PCI
325
326/* Only PCI devices have dynamically-defined IRQ handlers */
327
328int request_irq(unsigned int irq, irq_handler_t handler,
329 unsigned long irqflags, const char *devname, void *dev_id)
330{
331 return -EINVAL;
332}
333EXPORT_SYMBOL_GPL(request_irq);
334
335void free_irq(unsigned int irq, void *dev_id)
336{
337 WARN_ON(1);
338}
339EXPORT_SYMBOL_GPL(free_irq);
340
341void enable_irq(unsigned int irq)
342{
343 WARN_ON(1);
344}
345EXPORT_SYMBOL_GPL(enable_irq);
346
347void disable_irq(unsigned int irq)
348{
349 WARN_ON(1);
350}
351EXPORT_SYMBOL_GPL(disable_irq);
352
353#endif /* !CONFIG_PCI */
354
355void disable_irq_nosync(unsigned int irq)
356{
357 disable_irq(irq);
358}
359EXPORT_SYMBOL_GPL(disable_irq_nosync);
360
361unsigned long probe_irq_on(void)
362{
363 return 0;
364}
365EXPORT_SYMBOL_GPL(probe_irq_on);
366
367int probe_irq_off(unsigned long val)
368{
369 return 0;
370}
371EXPORT_SYMBOL_GPL(probe_irq_off);
372
373unsigned int probe_irq_mask(unsigned long val)
374{
375 return val;
376}
377EXPORT_SYMBOL_GPL(probe_irq_mask);
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index b6506ee32a36..29bd7bec4176 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -225,7 +225,7 @@ _sclp_print:
225 ahi %r2,1 225 ahi %r2,1
226 ltr %r0,%r0 # end of string? 226 ltr %r0,%r0 # end of string?
227 jz .LfinalizemtoS4 227 jz .LfinalizemtoS4
228 chi %r0,0x15 # end of line (NL)? 228 chi %r0,0x0a # end of line (NL)?
229 jz .LfinalizemtoS4 229 jz .LfinalizemtoS4
230 stc %r0,0(%r6,%r7) # copy to mto 230 stc %r0,0(%r6,%r7) # copy to mto
231 la %r11,0(%r6,%r7) 231 la %r11,0(%r6,%r7)
diff --git a/arch/s390/pci/pci.c b/arch/s390/pci/pci.c
index e6f15b5d8b7d..f1e5be85d592 100644
--- a/arch/s390/pci/pci.c
+++ b/arch/s390/pci/pci.c
@@ -302,15 +302,6 @@ static int zpci_cfg_store(struct zpci_dev *zdev, int offset, u32 val, u8 len)
302 return rc; 302 return rc;
303} 303}
304 304
305void synchronize_irq(unsigned int irq)
306{
307 /*
308 * Not needed, the handler is protected by a lock and IRQs that occur
309 * after the handler is deleted are just NOPs.
310 */
311}
312EXPORT_SYMBOL_GPL(synchronize_irq);
313
314void enable_irq(unsigned int irq) 305void enable_irq(unsigned int irq)
315{ 306{
316 struct msi_desc *msi = irq_get_msi_desc(irq); 307 struct msi_desc *msi = irq_get_msi_desc(irq);
@@ -327,30 +318,6 @@ void disable_irq(unsigned int irq)
327} 318}
328EXPORT_SYMBOL_GPL(disable_irq); 319EXPORT_SYMBOL_GPL(disable_irq);
329 320
330void disable_irq_nosync(unsigned int irq)
331{
332 disable_irq(irq);
333}
334EXPORT_SYMBOL_GPL(disable_irq_nosync);
335
336unsigned long probe_irq_on(void)
337{
338 return 0;
339}
340EXPORT_SYMBOL_GPL(probe_irq_on);
341
342int probe_irq_off(unsigned long val)
343{
344 return 0;
345}
346EXPORT_SYMBOL_GPL(probe_irq_off);
347
348unsigned int probe_irq_mask(unsigned long val)
349{
350 return val;
351}
352EXPORT_SYMBOL_GPL(probe_irq_mask);
353
354void pcibios_fixup_bus(struct pci_bus *bus) 321void pcibios_fixup_bus(struct pci_bus *bus)
355{ 322{
356} 323}
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 9f20566b0773..79cc0d1a477d 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -54,6 +54,7 @@ EXPORT_SYMBOL(of_set_property_mutex);
54int of_set_property(struct device_node *dp, const char *name, void *val, int len) 54int of_set_property(struct device_node *dp, const char *name, void *val, int len)
55{ 55{
56 struct property **prevp; 56 struct property **prevp;
57 unsigned long flags;
57 void *new_val; 58 void *new_val;
58 int err; 59 int err;
59 60
@@ -64,7 +65,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
64 err = -ENODEV; 65 err = -ENODEV;
65 66
66 mutex_lock(&of_set_property_mutex); 67 mutex_lock(&of_set_property_mutex);
67 raw_spin_lock(&devtree_lock); 68 raw_spin_lock_irqsave(&devtree_lock, flags);
68 prevp = &dp->properties; 69 prevp = &dp->properties;
69 while (*prevp) { 70 while (*prevp) {
70 struct property *prop = *prevp; 71 struct property *prop = *prevp;
@@ -91,7 +92,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
91 } 92 }
92 prevp = &(*prevp)->next; 93 prevp = &(*prevp)->next;
93 } 94 }
94 raw_spin_unlock(&devtree_lock); 95 raw_spin_unlock_irqrestore(&devtree_lock, flags);
95 mutex_unlock(&of_set_property_mutex); 96 mutex_unlock(&of_set_property_mutex);
96 97
97 /* XXX Upate procfs if necessary... */ 98 /* XXX Upate procfs if necessary... */
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
index 35ee62fccf98..c205035a6b96 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -251,51 +251,6 @@ static void find_bits(unsigned long mask, u8 *pos, u8 *size)
251 *size = len; 251 *size = len;
252} 252}
253 253
254static efi_status_t setup_efi_vars(struct boot_params *params)
255{
256 struct setup_data *data;
257 struct efi_var_bootdata *efidata;
258 u64 store_size, remaining_size, var_size;
259 efi_status_t status;
260
261 if (sys_table->runtime->hdr.revision < EFI_2_00_SYSTEM_TABLE_REVISION)
262 return EFI_UNSUPPORTED;
263
264 data = (struct setup_data *)(unsigned long)params->hdr.setup_data;
265
266 while (data && data->next)
267 data = (struct setup_data *)(unsigned long)data->next;
268
269 status = efi_call_phys4((void *)sys_table->runtime->query_variable_info,
270 EFI_VARIABLE_NON_VOLATILE |
271 EFI_VARIABLE_BOOTSERVICE_ACCESS |
272 EFI_VARIABLE_RUNTIME_ACCESS, &store_size,
273 &remaining_size, &var_size);
274
275 if (status != EFI_SUCCESS)
276 return status;
277
278 status = efi_call_phys3(sys_table->boottime->allocate_pool,
279 EFI_LOADER_DATA, sizeof(*efidata), &efidata);
280
281 if (status != EFI_SUCCESS)
282 return status;
283
284 efidata->data.type = SETUP_EFI_VARS;
285 efidata->data.len = sizeof(struct efi_var_bootdata) -
286 sizeof(struct setup_data);
287 efidata->data.next = 0;
288 efidata->store_size = store_size;
289 efidata->remaining_size = remaining_size;
290 efidata->max_var_size = var_size;
291
292 if (data)
293 data->next = (unsigned long)efidata;
294 else
295 params->hdr.setup_data = (unsigned long)efidata;
296
297}
298
299static efi_status_t setup_efi_pci(struct boot_params *params) 254static efi_status_t setup_efi_pci(struct boot_params *params)
300{ 255{
301 efi_pci_io_protocol *pci; 256 efi_pci_io_protocol *pci;
@@ -1202,8 +1157,6 @@ struct boot_params *efi_main(void *handle, efi_system_table_t *_table,
1202 1157
1203 setup_graphics(boot_params); 1158 setup_graphics(boot_params);
1204 1159
1205 setup_efi_vars(boot_params);
1206
1207 setup_efi_pci(boot_params); 1160 setup_efi_pci(boot_params);
1208 1161
1209 status = efi_call_phys3(sys_table->boottime->allocate_pool, 1162 status = efi_call_phys3(sys_table->boottime->allocate_pool,
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index 2fb5d5884e23..60c89f30c727 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -102,13 +102,6 @@ extern void efi_call_phys_epilog(void);
102extern void efi_unmap_memmap(void); 102extern void efi_unmap_memmap(void);
103extern void efi_memory_uc(u64 addr, unsigned long size); 103extern void efi_memory_uc(u64 addr, unsigned long size);
104 104
105struct efi_var_bootdata {
106 struct setup_data data;
107 u64 store_size;
108 u64 remaining_size;
109 u64 max_var_size;
110};
111
112#ifdef CONFIG_EFI 105#ifdef CONFIG_EFI
113 106
114static inline bool efi_is_native(void) 107static inline bool efi_is_native(void)
diff --git a/arch/x86/include/uapi/asm/bootparam.h b/arch/x86/include/uapi/asm/bootparam.h
index 08744242b8d2..c15ddaf90710 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -6,7 +6,6 @@
6#define SETUP_E820_EXT 1 6#define SETUP_E820_EXT 1
7#define SETUP_DTB 2 7#define SETUP_DTB 2
8#define SETUP_PCI 3 8#define SETUP_PCI 3
9#define SETUP_EFI_VARS 4
10 9
11/* ram_size flags */ 10/* ram_size flags */
12#define RAMDISK_IMAGE_START_MASK 0x07FF 11#define RAMDISK_IMAGE_START_MASK 0x07FF
diff --git a/arch/x86/kernel/relocate_kernel_64.S b/arch/x86/kernel/relocate_kernel_64.S
index 7a6f3b3be3cf..f2bb9c96720a 100644
--- a/arch/x86/kernel/relocate_kernel_64.S
+++ b/arch/x86/kernel/relocate_kernel_64.S
@@ -160,7 +160,7 @@ identity_mapped:
160 xorq %rbp, %rbp 160 xorq %rbp, %rbp
161 xorq %r8, %r8 161 xorq %r8, %r8
162 xorq %r9, %r9 162 xorq %r9, %r9
163 xorq %r10, %r9 163 xorq %r10, %r10
164 xorq %r11, %r11 164 xorq %r11, %r11
165 xorq %r12, %r12 165 xorq %r12, %r12
166 xorq %r13, %r13 166 xorq %r13, %r13
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index eaac1743def7..1f34e9219775 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -277,6 +277,9 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
277 end_pfn = limit_pfn; 277 end_pfn = limit_pfn;
278 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 278 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
279 279
280 if (!after_bootmem)
281 adjust_range_page_size_mask(mr, nr_range);
282
280 /* try to merge same page size and continuous */ 283 /* try to merge same page size and continuous */
281 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) { 284 for (i = 0; nr_range > 1 && i < nr_range - 1; i++) {
282 unsigned long old_start; 285 unsigned long old_start;
@@ -291,9 +294,6 @@ static int __meminit split_mem_range(struct map_range *mr, int nr_range,
291 nr_range--; 294 nr_range--;
292 } 295 }
293 296
294 if (!after_bootmem)
295 adjust_range_page_size_mask(mr, nr_range);
296
297 for (i = 0; i < nr_range; i++) 297 for (i = 0; i < nr_range; i++)
298 printk(KERN_DEBUG " [mem %#010lx-%#010lx] page %s\n", 298 printk(KERN_DEBUG " [mem %#010lx-%#010lx] page %s\n",
299 mr[i].start, mr[i].end - 1, 299 mr[i].start, mr[i].end - 1,
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index 82089d8b1954..5ae2eb09419e 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -42,7 +42,6 @@
42#include <linux/io.h> 42#include <linux/io.h>
43#include <linux/reboot.h> 43#include <linux/reboot.h>
44#include <linux/bcd.h> 44#include <linux/bcd.h>
45#include <linux/ucs2_string.h>
46 45
47#include <asm/setup.h> 46#include <asm/setup.h>
48#include <asm/efi.h> 47#include <asm/efi.h>
@@ -54,12 +53,12 @@
54 53
55#define EFI_DEBUG 1 54#define EFI_DEBUG 1
56 55
57/* 56#define EFI_MIN_RESERVE 5120
58 * There's some additional metadata associated with each 57
59 * variable. Intel's reference implementation is 60 bytes - bump that 58#define EFI_DUMMY_GUID \
60 * to account for potential alignment constraints 59 EFI_GUID(0x4424ac57, 0xbe4b, 0x47dd, 0x9e, 0x97, 0xed, 0x50, 0xf0, 0x9f, 0x92, 0xa9)
61 */ 60
62#define VAR_METADATA_SIZE 64 61static efi_char16_t efi_dummy_name[6] = { 'D', 'U', 'M', 'M', 'Y', 0 };
63 62
64struct efi __read_mostly efi = { 63struct efi __read_mostly efi = {
65 .mps = EFI_INVALID_TABLE_ADDR, 64 .mps = EFI_INVALID_TABLE_ADDR,
@@ -79,13 +78,6 @@ struct efi_memory_map memmap;
79static struct efi efi_phys __initdata; 78static struct efi efi_phys __initdata;
80static efi_system_table_t efi_systab __initdata; 79static efi_system_table_t efi_systab __initdata;
81 80
82static u64 efi_var_store_size;
83static u64 efi_var_remaining_size;
84static u64 efi_var_max_var_size;
85static u64 boot_used_size;
86static u64 boot_var_size;
87static u64 active_size;
88
89unsigned long x86_efi_facility; 81unsigned long x86_efi_facility;
90 82
91/* 83/*
@@ -188,53 +180,8 @@ static efi_status_t virt_efi_get_next_variable(unsigned long *name_size,
188 efi_char16_t *name, 180 efi_char16_t *name,
189 efi_guid_t *vendor) 181 efi_guid_t *vendor)
190{ 182{
191 efi_status_t status; 183 return efi_call_virt3(get_next_variable,
192 static bool finished = false; 184 name_size, name, vendor);
193 static u64 var_size;
194
195 status = efi_call_virt3(get_next_variable,
196 name_size, name, vendor);
197
198 if (status == EFI_NOT_FOUND) {
199 finished = true;
200 if (var_size < boot_used_size) {
201 boot_var_size = boot_used_size - var_size;
202 active_size += boot_var_size;
203 } else {
204 printk(KERN_WARNING FW_BUG "efi: Inconsistent initial sizes\n");
205 }
206 }
207
208 if (boot_used_size && !finished) {
209 unsigned long size = 0;
210 u32 attr;
211 efi_status_t s;
212 void *tmp;
213
214 s = virt_efi_get_variable(name, vendor, &attr, &size, NULL);
215
216 if (s != EFI_BUFFER_TOO_SMALL || !size)
217 return status;
218
219 tmp = kmalloc(size, GFP_ATOMIC);
220
221 if (!tmp)
222 return status;
223
224 s = virt_efi_get_variable(name, vendor, &attr, &size, tmp);
225
226 if (s == EFI_SUCCESS && (attr & EFI_VARIABLE_NON_VOLATILE)) {
227 var_size += size;
228 var_size += ucs2_strsize(name, 1024);
229 active_size += size;
230 active_size += VAR_METADATA_SIZE;
231 active_size += ucs2_strsize(name, 1024);
232 }
233
234 kfree(tmp);
235 }
236
237 return status;
238} 185}
239 186
240static efi_status_t virt_efi_set_variable(efi_char16_t *name, 187static efi_status_t virt_efi_set_variable(efi_char16_t *name,
@@ -243,34 +190,9 @@ static efi_status_t virt_efi_set_variable(efi_char16_t *name,
243 unsigned long data_size, 190 unsigned long data_size,
244 void *data) 191 void *data)
245{ 192{
246 efi_status_t status; 193 return efi_call_virt5(set_variable,
247 u32 orig_attr = 0; 194 name, vendor, attr,
248 unsigned long orig_size = 0; 195 data_size, data);
249
250 status = virt_efi_get_variable(name, vendor, &orig_attr, &orig_size,
251 NULL);
252
253 if (status != EFI_BUFFER_TOO_SMALL)
254 orig_size = 0;
255
256 status = efi_call_virt5(set_variable,
257 name, vendor, attr,
258 data_size, data);
259
260 if (status == EFI_SUCCESS) {
261 if (orig_size) {
262 active_size -= orig_size;
263 active_size -= ucs2_strsize(name, 1024);
264 active_size -= VAR_METADATA_SIZE;
265 }
266 if (data_size) {
267 active_size += data_size;
268 active_size += ucs2_strsize(name, 1024);
269 active_size += VAR_METADATA_SIZE;
270 }
271 }
272
273 return status;
274} 196}
275 197
276static efi_status_t virt_efi_query_variable_info(u32 attr, 198static efi_status_t virt_efi_query_variable_info(u32 attr,
@@ -786,9 +708,6 @@ void __init efi_init(void)
786 char vendor[100] = "unknown"; 708 char vendor[100] = "unknown";
787 int i = 0; 709 int i = 0;
788 void *tmp; 710 void *tmp;
789 struct setup_data *data;
790 struct efi_var_bootdata *efi_var_data;
791 u64 pa_data;
792 711
793#ifdef CONFIG_X86_32 712#ifdef CONFIG_X86_32
794 if (boot_params.efi_info.efi_systab_hi || 713 if (boot_params.efi_info.efi_systab_hi ||
@@ -806,22 +725,6 @@ void __init efi_init(void)
806 if (efi_systab_init(efi_phys.systab)) 725 if (efi_systab_init(efi_phys.systab))
807 return; 726 return;
808 727
809 pa_data = boot_params.hdr.setup_data;
810 while (pa_data) {
811 data = early_ioremap(pa_data, sizeof(*efi_var_data));
812 if (data->type == SETUP_EFI_VARS) {
813 efi_var_data = (struct efi_var_bootdata *)data;
814
815 efi_var_store_size = efi_var_data->store_size;
816 efi_var_remaining_size = efi_var_data->remaining_size;
817 efi_var_max_var_size = efi_var_data->max_var_size;
818 }
819 pa_data = data->next;
820 early_iounmap(data, sizeof(*efi_var_data));
821 }
822
823 boot_used_size = efi_var_store_size - efi_var_remaining_size;
824
825 set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility); 728 set_bit(EFI_SYSTEM_TABLES, &x86_efi_facility);
826 729
827 /* 730 /*
@@ -1085,6 +988,13 @@ void __init efi_enter_virtual_mode(void)
1085 runtime_code_page_mkexec(); 988 runtime_code_page_mkexec();
1086 989
1087 kfree(new_memmap); 990 kfree(new_memmap);
991
992 /* clean DUMMY object */
993 efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
994 EFI_VARIABLE_NON_VOLATILE |
995 EFI_VARIABLE_BOOTSERVICE_ACCESS |
996 EFI_VARIABLE_RUNTIME_ACCESS,
997 0, NULL);
1088} 998}
1089 999
1090/* 1000/*
@@ -1136,33 +1046,65 @@ efi_status_t efi_query_variable_store(u32 attributes, unsigned long size)
1136 efi_status_t status; 1046 efi_status_t status;
1137 u64 storage_size, remaining_size, max_size; 1047 u64 storage_size, remaining_size, max_size;
1138 1048
1049 if (!(attributes & EFI_VARIABLE_NON_VOLATILE))
1050 return 0;
1051
1139 status = efi.query_variable_info(attributes, &storage_size, 1052 status = efi.query_variable_info(attributes, &storage_size,
1140 &remaining_size, &max_size); 1053 &remaining_size, &max_size);
1141 if (status != EFI_SUCCESS) 1054 if (status != EFI_SUCCESS)
1142 return status; 1055 return status;
1143 1056
1144 if (!max_size && remaining_size > size)
1145 printk_once(KERN_ERR FW_BUG "Broken EFI implementation"
1146 " is returning MaxVariableSize=0\n");
1147 /* 1057 /*
1148 * Some firmware implementations refuse to boot if there's insufficient 1058 * Some firmware implementations refuse to boot if there's insufficient
1149 * space in the variable store. We account for that by refusing the 1059 * space in the variable store. We account for that by refusing the
1150 * write if permitting it would reduce the available space to under 1060 * write if permitting it would reduce the available space to under
1151 * 50%. However, some firmware won't reclaim variable space until 1061 * 5KB. This figure was provided by Samsung, so should be safe.
1152 * after the used (not merely the actively used) space drops below
1153 * a threshold. We can approximate that case with the value calculated
1154 * above. If both the firmware and our calculations indicate that the
1155 * available space would drop below 50%, refuse the write.
1156 */ 1062 */
1063 if ((remaining_size - size < EFI_MIN_RESERVE) &&
1064 !efi_no_storage_paranoia) {
1065
1066 /*
1067 * Triggering garbage collection may require that the firmware
1068 * generate a real EFI_OUT_OF_RESOURCES error. We can force
1069 * that by attempting to use more space than is available.
1070 */
1071 unsigned long dummy_size = remaining_size + 1024;
1072 void *dummy = kmalloc(dummy_size, GFP_ATOMIC);
1073
1074 status = efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
1075 EFI_VARIABLE_NON_VOLATILE |
1076 EFI_VARIABLE_BOOTSERVICE_ACCESS |
1077 EFI_VARIABLE_RUNTIME_ACCESS,
1078 dummy_size, dummy);
1079
1080 if (status == EFI_SUCCESS) {
1081 /*
1082 * This should have failed, so if it didn't make sure
1083 * that we delete it...
1084 */
1085 efi.set_variable(efi_dummy_name, &EFI_DUMMY_GUID,
1086 EFI_VARIABLE_NON_VOLATILE |
1087 EFI_VARIABLE_BOOTSERVICE_ACCESS |
1088 EFI_VARIABLE_RUNTIME_ACCESS,
1089 0, dummy);
1090 }
1157 1091
1158 if (!storage_size || size > remaining_size || 1092 /*
1159 (max_size && size > max_size)) 1093 * The runtime code may now have triggered a garbage collection
1160 return EFI_OUT_OF_RESOURCES; 1094 * run, so check the variable info again
1095 */
1096 status = efi.query_variable_info(attributes, &storage_size,
1097 &remaining_size, &max_size);
1161 1098
1162 if (!efi_no_storage_paranoia && 1099 if (status != EFI_SUCCESS)
1163 ((active_size + size + VAR_METADATA_SIZE > storage_size / 2) && 1100 return status;
1164 (remaining_size - size < storage_size / 2))) 1101
1165 return EFI_OUT_OF_RESOURCES; 1102 /*
1103 * There still isn't enough room, so return an error
1104 */
1105 if (remaining_size - size < EFI_MIN_RESERVE)
1106 return EFI_OUT_OF_RESOURCES;
1107 }
1166 1108
1167 return EFI_SUCCESS; 1109 return EFI_SUCCESS;
1168} 1110}
diff --git a/arch/x86/tools/relocs.c b/arch/x86/tools/relocs.c
index 590be1090892..f7bab68a4b83 100644
--- a/arch/x86/tools/relocs.c
+++ b/arch/x86/tools/relocs.c
@@ -42,9 +42,6 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
42 "^(xen_irq_disable_direct_reloc$|" 42 "^(xen_irq_disable_direct_reloc$|"
43 "xen_save_fl_direct_reloc$|" 43 "xen_save_fl_direct_reloc$|"
44 "VDSO|" 44 "VDSO|"
45#if ELF_BITS == 64
46 "__vvar_page|"
47#endif
48 "__crc_)", 45 "__crc_)",
49 46
50/* 47/*
@@ -72,6 +69,7 @@ static const char * const sym_regex_kernel[S_NSYMTYPES] = {
72 "__per_cpu_load|" 69 "__per_cpu_load|"
73 "init_per_cpu__.*|" 70 "init_per_cpu__.*|"
74 "__end_rodata_hpage_align|" 71 "__end_rodata_hpage_align|"
72 "__vvar_page|"
75#endif 73#endif
76 "_end)$" 74 "_end)$"
77}; 75};
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index fb44426fe931..d99cae8147d1 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -17,6 +17,7 @@
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/smp.h> 18#include <linux/smp.h>
19#include <linux/irq_work.h> 19#include <linux/irq_work.h>
20#include <linux/tick.h>
20 21
21#include <asm/paravirt.h> 22#include <asm/paravirt.h>
22#include <asm/desc.h> 23#include <asm/desc.h>
@@ -447,6 +448,13 @@ static void __cpuinit xen_play_dead(void) /* used only with HOTPLUG_CPU */
447 play_dead_common(); 448 play_dead_common();
448 HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL); 449 HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL);
449 cpu_bringup(); 450 cpu_bringup();
451 /*
452 * commit 4b0c0f294 (tick: Cleanup NOHZ per cpu data on cpu down)
453 * clears certain data that the cpu_idle loop (which called us
454 * and that we return from) expects. The only way to get that
455 * data back is to call:
456 */
457 tick_nohz_idle_enter();
450} 458}
451 459
452#else /* !CONFIG_HOTPLUG_CPU */ 460#else /* !CONFIG_HOTPLUG_CPU */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-10 03:14:50 -0400