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authorArnd Bergmann <arnd@arndb.de>2013-06-19 19:51:18 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-19 19:51:18 -0400
commitc3b693d1d63444afe4fbf809d8a311b63741e503 (patch)
tree5c0c264203967f1524ac28645f0b5cea57b624bc /arch
parent596fd95ea606548adaa8310a7c05a6dcfec46f16 (diff)
parent7fca1f20c0f3e9d7a3b23ee1fc9e832f520f3f1a (diff)
Merge tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc
From Linus Walleij: Device Tree and Multiplatform support for U300: - Add devicetree support to timer, pinctrl (probe), I2C block, watchdog, DMA controller and clocks. - Piecewise add a device tree containing all peripherals. - Delete the ATAG boot path. - Delete redundant platform data and board files. - Convert to multiplatform. * tag 'u300-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: (40 commits) ARM: u300: switch to using syscon regmap for board ARM: u300: Update MMC configs for u300 defconfig spi: pl022: use DMA by default when probing from DT pinctrl: get rid of all platform data for coh901 ARM: u300: convert MMC/SD clock to device tree ARM: u300: move the gated system controller clocks to DT i2c: stu300: do not request a specific clock name clk: move the U300 fixed and fixed-factor to DT ARM: u300: remove register definition file ARM: u300: add syscon node ARM: u300 use module_spi_driver to register driver ARM: u300: delete remnant machine headers ARM: u300: convert to multiplatform ARM: u300: localize <mach/u300-regs.h> ARM: u300: delete <mach/irqs.h> ARM: u300: delete <mach/hardware.h> ARM: u300: push down syscon registers ARM: u300: remove deps from debug macro ARM: u300: move debugmacro to debug includes ARM: u300: delete all static board data ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig19
-rw-r--r--arch/arm/Kconfig.debug8
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/ste-u300.dts473
-rw-r--r--arch/arm/configs/u300_defconfig14
-rw-r--r--arch/arm/include/debug/u300.S (renamed from arch/arm/mach-u300/include/mach/debug-macro.S)9
-rw-r--r--arch/arm/mach-u300/Kconfig32
-rw-r--r--arch/arm/mach-u300/Makefile2
-rw-r--r--arch/arm/mach-u300/core.c759
-rw-r--r--arch/arm/mach-u300/dummyspichip.c20
-rw-r--r--arch/arm/mach-u300/i2c.c285
-rw-r--r--arch/arm/mach-u300/i2c.h23
-rw-r--r--arch/arm/mach-u300/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-u300/include/mach/irqs.h80
-rw-r--r--arch/arm/mach-u300/include/mach/syscon.h592
-rw-r--r--arch/arm/mach-u300/include/mach/timex.h17
-rw-r--r--arch/arm/mach-u300/include/mach/u300-regs.h165
-rw-r--r--arch/arm/mach-u300/include/mach/uncompress.h45
-rw-r--r--arch/arm/mach-u300/regulator.c67
-rw-r--r--arch/arm/mach-u300/spi.c102
-rw-r--r--arch/arm/mach-u300/spi.h26
-rw-r--r--arch/arm/mach-u300/timer.c113
-rw-r--r--arch/arm/mach-u300/timer.h1
-rw-r--r--arch/arm/mach-u300/u300-gpio.h70
24 files changed, 888 insertions, 2040 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2ca6d73472b6..23f6aeeaed92 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -815,23 +815,6 @@ config ARCH_SHARK
815 Support for the StrongARM based Digital DNARD machine, also known 815 Support for the StrongARM based Digital DNARD machine, also known
816 as "Shark" (<http://www.shark-linux.de/shark.html>). 816 as "Shark" (<http://www.shark-linux.de/shark.html>).
817 817
818config ARCH_U300
819 bool "ST-Ericsson U300 Series"
820 depends on MMU
821 select ARCH_REQUIRE_GPIOLIB
822 select ARM_AMBA
823 select ARM_PATCH_PHYS_VIRT
824 select ARM_VIC
825 select CLKDEV_LOOKUP
826 select CLKSRC_MMIO
827 select COMMON_CLK
828 select CPU_ARM926T
829 select GENERIC_CLOCKEVENTS
830 select HAVE_TCM
831 select SPARSE_IRQ
832 help
833 Support for ST-Ericsson U300 series mobile platforms.
834
835config ARCH_DAVINCI 818config ARCH_DAVINCI
836 bool "TI DaVinci" 819 bool "TI DaVinci"
837 select ARCH_HAS_HOLES_MEMORYMODEL 820 select ARCH_HAS_HOLES_MEMORYMODEL
@@ -2045,7 +2028,7 @@ config CRASH_DUMP
2045 2028
2046config AUTO_ZRELADDR 2029config AUTO_ZRELADDR
2047 bool "Auto calculation of the decompressed kernel image address" 2030 bool "Auto calculation of the decompressed kernel image address"
2048 depends on !ZBOOT_ROM && !ARCH_U300 2031 depends on !ZBOOT_ROM
2049 help 2032 help
2050 ZRELADDR is the physical address where the decompressed kernel 2033 ZRELADDR is the physical address where the decompressed kernel
2051 image will be placed. If AUTO_ZRELADDR is selected, the address 2034 image will be placed. If AUTO_ZRELADDR is selected, the address
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index d2b000a31b47..7ef6f145f964 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -482,6 +482,13 @@ choice
482 Say Y here if you want the debug print routines to direct 482 Say Y here if you want the debug print routines to direct
483 their output to the uart1 port on SiRFmarco devices. 483 their output to the uart1 port on SiRFmarco devices.
484 484
485 config DEBUG_U300_UART
486 bool "Kernel low-level debugging messages via U300 UART0"
487 depends on ARCH_U300
488 help
489 Say Y here if you want the debug print routines to direct
490 their output to the uart port on U300 devices.
491
485 config DEBUG_UX500_UART 492 config DEBUG_UX500_UART
486 depends on ARCH_U8500 493 depends on ARCH_U8500
487 bool "Use Ux500 UART for low-level debug" 494 bool "Use Ux500 UART for low-level debug"
@@ -685,6 +692,7 @@ config DEBUG_LL_INCLUDE
685 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART 692 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
686 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 693 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
687 default "debug/tegra.S" if DEBUG_TEGRA_UART 694 default "debug/tegra.S" if DEBUG_TEGRA_UART
695 default "debug/u300.S" if DEBUG_U300_UART
688 default "debug/ux500.S" if DEBUG_UX500_UART 696 default "debug/ux500.S" if DEBUG_UX500_UART
689 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ 697 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
690 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 698 DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3844ef27d7ba..f9eae2f0ae5d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -201,6 +201,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
201 tegra114-pluto.dtb 201 tegra114-pluto.dtb
202dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ 202dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
203 versatile-pb.dtb 203 versatile-pb.dtb
204dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
204dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \ 205dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2p-ca5s.dtb \
205 vexpress-v2p-ca9.dtb \ 206 vexpress-v2p-ca9.dtb \
206 vexpress-v2p-ca15-tc1.dtb \ 207 vexpress-v2p-ca15-tc1.dtb \
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
new file mode 100644
index 000000000000..8a1032c1ffc9
--- /dev/null
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -0,0 +1,473 @@
1/*
2 * Device Tree for the ST-Ericsson U300 Machine and SoC
3 */
4
5/dts-v1/;
6/include/ "skeleton.dtsi"
7
8/ {
9 model = "ST-Ericsson U300";
10 compatible = "stericsson,u300";
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 chosen {
15 bootargs = "root=/dev/ram0 console=ttyAMA0,115200n8 earlyprintk";
16 };
17
18 aliases {
19 serial0 = &uart0;
20 serial1 = &uart1;
21 };
22
23 memory {
24 reg = <0x48000000 0x03c00000>;
25 };
26
27 s365 {
28 compatible = "stericsson,s365";
29 vana15-supply = <&ab3100_ldo_d_reg>;
30 syscon = <&syscon>;
31 };
32
33 syscon: syscon@c0011000 {
34 compatible = "stericsson,u300-syscon", "syscon";
35 reg = <0xc0011000 0x1000>;
36 clk32: app_32_clk@32k {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-frequency = <32768>;
40 };
41 pll13: pll13@13M {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <13000000>;
45 };
46 /* Slow bridge clocks under PLL13 */
47 slow_clk: slow_clk@13M {
48 #clock-cells = <0>;
49 compatible = "stericsson,u300-syscon-clk";
50 clock-type = <0>; /* Slow */
51 clock-id = <0>;
52 clocks = <&pll13>;
53 };
54 uart0_clk: uart0_clk@13M {
55 #clock-cells = <0>;
56 compatible = "stericsson,u300-syscon-clk";
57 clock-type = <0>; /* Slow */
58 clock-id = <1>;
59 clocks = <&slow_clk>;
60 };
61 gpio_clk: gpio_clk@13M {
62 #clock-cells = <0>;
63 compatible = "stericsson,u300-syscon-clk";
64 clock-type = <0>; /* Slow */
65 clock-id = <4>;
66 clocks = <&slow_clk>;
67 };
68 rtc_clk: rtc_clk@13M {
69 #clock-cells = <0>;
70 compatible = "stericsson,u300-syscon-clk";
71 clock-type = <0>; /* Slow */
72 clock-id = <6>;
73 clocks = <&slow_clk>;
74 };
75 apptimer_clk: app_tmr_clk@13M {
76 #clock-cells = <0>;
77 compatible = "stericsson,u300-syscon-clk";
78 clock-type = <0>; /* Slow */
79 clock-id = <7>;
80 clocks = <&slow_clk>;
81 };
82 acc_tmr_clk@13M {
83 #clock-cells = <0>;
84 compatible = "stericsson,u300-syscon-clk";
85 clock-type = <0>; /* Slow */
86 clock-id = <8>;
87 clocks = <&slow_clk>;
88 };
89 pll208: pll208@208M {
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-frequency = <208000000>;
93 };
94 app208: app_208_clk@208M {
95 #clock-cells = <0>;
96 compatible = "fixed-factor-clock";
97 clock-div = <1>;
98 clock-mult = <1>;
99 clocks = <&pll208>;
100 };
101 cpu_clk@208M {
102 #clock-cells = <0>;
103 compatible = "stericsson,u300-syscon-clk";
104 clock-type = <2>; /* Rest */
105 clock-id = <3>;
106 clocks = <&app208>;
107 };
108 app104: app_104_clk@104M {
109 #clock-cells = <0>;
110 compatible = "fixed-factor-clock";
111 clock-div = <2>;
112 clock-mult = <1>;
113 clocks = <&pll208>;
114 };
115 semi_clk@104M {
116 #clock-cells = <0>;
117 compatible = "stericsson,u300-syscon-clk";
118 clock-type = <2>; /* Rest */
119 clock-id = <9>;
120 clocks = <&app104>;
121 };
122 app52: app_52_clk@52M {
123 #clock-cells = <0>;
124 compatible = "fixed-factor-clock";
125 clock-div = <4>;
126 clock-mult = <1>;
127 clocks = <&pll208>;
128 };
129 /* AHB subsystem clocks */
130 ahb_clk: ahb_subsys_clk@52M {
131 #clock-cells = <0>;
132 compatible = "stericsson,u300-syscon-clk";
133 clock-type = <2>; /* Rest */
134 clock-id = <10>;
135 clocks = <&app52>;
136 };
137 intcon_clk@52M {
138 #clock-cells = <0>;
139 compatible = "stericsson,u300-syscon-clk";
140 clock-type = <2>; /* Rest */
141 clock-id = <12>;
142 clocks = <&ahb_clk>;
143 };
144 emif_clk@52M {
145 #clock-cells = <0>;
146 compatible = "stericsson,u300-syscon-clk";
147 clock-type = <2>; /* Rest */
148 clock-id = <5>;
149 clocks = <&ahb_clk>;
150 };
151 dmac_clk: dmac_clk@52M {
152 #clock-cells = <0>;
153 compatible = "stericsson,u300-syscon-clk";
154 clock-type = <2>; /* Rest */
155 clock-id = <4>;
156 clocks = <&app52>;
157 };
158 fsmc_clk: fsmc_clk@52M {
159 #clock-cells = <0>;
160 compatible = "stericsson,u300-syscon-clk";
161 clock-type = <2>; /* Rest */
162 clock-id = <6>;
163 clocks = <&app52>;
164 };
165 xgam_clk: xgam_clk@52M {
166 #clock-cells = <0>;
167 compatible = "stericsson,u300-syscon-clk";
168 clock-type = <2>; /* Rest */
169 clock-id = <8>;
170 clocks = <&app52>;
171 };
172 app26: app_26_clk@26M {
173 #clock-cells = <0>;
174 compatible = "fixed-factor-clock";
175 clock-div = <2>;
176 clock-mult = <1>;
177 clocks = <&app52>;
178 };
179 /* Fast bridge clocks */
180 fast_clk: fast_clk@26M {
181 #clock-cells = <0>;
182 compatible = "stericsson,u300-syscon-clk";
183 clock-type = <1>; /* Fast */
184 clock-id = <0>;
185 clocks = <&app26>;
186 };
187 i2c0_clk: i2c0_clk@26M {
188 #clock-cells = <0>;
189 compatible = "stericsson,u300-syscon-clk";
190 clock-type = <1>; /* Fast */
191 clock-id = <1>;
192 clocks = <&fast_clk>;
193 };
194 i2c1_clk: i2c1_clk@26M {
195 #clock-cells = <0>;
196 compatible = "stericsson,u300-syscon-clk";
197 clock-type = <1>; /* Fast */
198 clock-id = <2>;
199 clocks = <&fast_clk>;
200 };
201 mmc_pclk: mmc_p_clk@26M {
202 #clock-cells = <0>;
203 compatible = "stericsson,u300-syscon-clk";
204 clock-type = <1>; /* Fast */
205 clock-id = <5>;
206 clocks = <&fast_clk>;
207 };
208 mmc_mclk: mmc_mclk {
209 #clock-cells = <0>;
210 compatible = "stericsson,u300-syscon-mclk";
211 clocks = <&mmc_pclk>;
212 };
213 spi_clk: spi_p_clk@26M {
214 #clock-cells = <0>;
215 compatible = "stericsson,u300-syscon-clk";
216 clock-type = <1>; /* Fast */
217 clock-id = <6>;
218 clocks = <&fast_clk>;
219 };
220 };
221
222 timer: timer@c0014000 {
223 compatible = "stericsson,u300-apptimer";
224 reg = <0xc0014000 0x1000>;
225 interrupt-parent = <&vica>;
226 interrupts = <24 25 26 27>;
227 clocks = <&apptimer_clk>;
228 };
229
230 gpio: gpio@c0016000 {
231 compatible = "stericsson,gpio-coh901";
232 reg = <0xc0016000 0x1000>;
233 interrupt-parent = <&vicb>;
234 interrupts = <0 1 2 18 21 22 23>;
235 clocks = <&gpio_clk>;
236 interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
237 "gpio4", "gpio5", "gpio6";
238 interrupt-controller;
239 #interrupt-cells = <2>;
240 gpio-controller;
241 #gpio-cells = <2>;
242 };
243
244 pinctrl: pinctrl@c0011000 {
245 compatible = "stericsson,pinctrl-u300";
246 reg = <0xc0011000 0x1000>;
247 };
248
249 watchdog: watchdog@c0012000 {
250 compatible = "stericsson,coh901327";
251 reg = <0xc0012000 0x1000>;
252 interrupt-parent = <&vicb>;
253 interrupts = <3>;
254 clocks = <&clk32>;
255 };
256
257 rtc: rtc@c0017000 {
258 compatible = "stericsson,coh901331";
259 reg = <0xc0017000 0x1000>;
260 interrupt-parent = <&vicb>;
261 interrupts = <10>;
262 clocks = <&rtc_clk>;
263 };
264
265 dmac: dma-controller@c00020000 {
266 compatible = "stericsson,coh901318";
267 reg = <0xc0020000 0x1000>;
268 interrupt-parent = <&vica>;
269 interrupts = <2>;
270 #dma-cells = <1>;
271 dma-channels = <40>;
272 clocks = <&dmac_clk>;
273 };
274
275 /* A NAND flash of 128 MiB */
276 fsmc: flash@40000000 {
277 compatible = "stericsson,fsmc-nand";
278 #address-cells = <1>;
279 #size-cells = <1>;
280 reg = <0x9f800000 0x1000>, /* FSMC Register*/
281 <0x80000000 0x4000>, /* NAND Base DATA */
282 <0x80020000 0x4000>, /* NAND Base ADDR */
283 <0x80010000 0x4000>; /* NAND Base CMD */
284 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
285 nand-skip-bbtscan;
286 clocks = <&fsmc_clk>;
287
288 partition@0 {
289 label = "boot records";
290 reg = <0x0 0x20000>;
291 };
292 partition@20000 {
293 label = "free";
294 reg = <0x20000 0x7e0000>;
295 };
296 partition@800000 {
297 label = "platform";
298 reg = <0x800000 0xf800000>;
299 };
300 };
301
302 i2c0: i2c@c0004000 {
303 compatible = "st,ddci2c";
304 reg = <0xc0004000 0x1000>;
305 interrupt-parent = <&vicb>;
306 interrupts = <8>;
307 clocks = <&i2c0_clk>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 ab3100: ab3100@0x48 {
311 compatible = "stericsson,ab3100";
312 reg = <0x48>;
313 interrupt-parent = <&vica>;
314 interrupts = <0>; /* EXT0 IRQ */
315 ab3100-regulators {
316 compatible = "stericsson,ab3100-regulators";
317 ab3100_ldo_a_reg: ab3100_ldo_a {
318 regulator-compatible = "ab3100_ldo_a";
319 startup-delay-us = <200>;
320 regulator-always-on;
321 regulator-boot-on;
322 };
323 ab3100_ldo_c_reg: ab3100_ldo_c {
324 regulator-compatible = "ab3100_ldo_c";
325 startup-delay-us = <200>;
326 };
327 ab3100_ldo_d_reg: ab3100_ldo_d {
328 regulator-compatible = "ab3100_ldo_d";
329 startup-delay-us = <200>;
330 };
331 ab3100_ldo_e_reg: ab3100_ldo_e {
332 regulator-compatible = "ab3100_ldo_e";
333 regulator-min-microvolt = <1800000>;
334 regulator-max-microvolt = <1800000>;
335 startup-delay-us = <200>;
336 regulator-always-on;
337 regulator-boot-on;
338 };
339 ab3100_ldo_f_reg: ab3100_ldo_f {
340 regulator-compatible = "ab3100_ldo_f";
341 regulator-min-microvolt = <2500000>;
342 regulator-max-microvolt = <2500000>;
343 startup-delay-us = <600>;
344 regulator-always-on;
345 regulator-boot-on;
346 };
347 ab3100_ldo_g_reg: ab3100_ldo_g {
348 regulator-compatible = "ab3100_ldo_g";
349 regulator-min-microvolt = <1500000>;
350 regulator-max-microvolt = <2850000>;
351 startup-delay-us = <400>;
352 };
353 ab3100_ldo_h_reg: ab3100_ldo_h {
354 regulator-compatible = "ab3100_ldo_h";
355 regulator-min-microvolt = <1200000>;
356 regulator-max-microvolt = <2750000>;
357 startup-delay-us = <200>;
358 };
359 ab3100_ldo_k_reg: ab3100_ldo_k {
360 regulator-compatible = "ab3100_ldo_k";
361 regulator-min-microvolt = <1800000>;
362 regulator-max-microvolt = <2750000>;
363 startup-delay-us = <200>;
364 };
365 ab3100_ext_reg: ab3100_ext {
366 regulator-compatible = "ab3100_ext";
367 };
368 ab3100_buck_reg: ab3100_buck {
369 regulator-compatible = "ab3100_buck";
370 regulator-min-microvolt = <1200000>;
371 regulator-max-microvolt = <1800000>;
372 startup-delay-us = <1000>;
373 regulator-always-on;
374 regulator-boot-on;
375 };
376 };
377 };
378 };
379
380 i2c1: i2c@c0005000 {
381 compatible = "st,ddci2c";
382 reg = <0xc0005000 0x1000>;
383 interrupt-parent = <&vicb>;
384 interrupts = <9>;
385 clocks = <&i2c1_clk>;
386 #address-cells = <1>;
387 #size-cells = <0>;
388 fwcam0: fwcam@0x10 {
389 reg = <0x10>;
390 };
391 fwcam1: fwcam@0x5d {
392 reg = <0x5d>;
393 };
394 };
395
396 amba {
397 compatible = "arm,amba-bus";
398 #address-cells = <1>;
399 #size-cells = <1>;
400 ranges;
401
402 vica: interrupt-controller@a0001000 {
403 compatible = "arm,versatile-vic";
404 interrupt-controller;
405 #interrupt-cells = <1>;
406 reg = <0xa0001000 0x20>;
407 };
408
409 vicb: interrupt-controller@a0002000 {
410 compatible = "arm,versatile-vic";
411 interrupt-controller;
412 #interrupt-cells = <1>;
413 reg = <0xa0002000 0x20>;
414 };
415
416 uart0: serial@c0013000 {
417 compatible = "arm,pl011", "arm,primecell";
418 reg = <0xc0013000 0x1000>;
419 interrupt-parent = <&vica>;
420 interrupts = <22>;
421 clocks = <&uart0_clk>, <&uart0_clk>;
422 clock-names = "apb_pclk", "uart0_clk";
423 dmas = <&dmac 17 &dmac 18>;
424 dma-names = "tx", "rx";
425 };
426
427 uart1: serial@c0007000 {
428 compatible = "arm,pl011", "arm,primecell";
429 reg = <0xc0007000 0x1000>;
430 interrupt-parent = <&vicb>;
431 interrupts = <20>;
432 dmas = <&dmac 38 &dmac 39>;
433 dma-names = "tx", "rx";
434 };
435
436 mmcsd: mmcsd@c0001000 {
437 compatible = "arm,pl18x", "arm,primecell";
438 reg = <0xc0001000 0x1000>;
439 interrupt-parent = <&vicb>;
440 interrupts = <6 7>;
441 clocks = <&mmc_pclk>, <&mmc_mclk>;
442 clock-names = "apb_pclk", "mclk";
443 max-frequency = <24000000>;
444 bus-width = <4>; // SD-card slot
445 mmc-cap-mmc-highspeed;
446 mmc-cap-sd-highspeed;
447 cd-gpios = <&gpio 12 0x4>;
448 cd-inverted;
449 vmmc-supply = <&ab3100_ldo_g_reg>;
450 dmas = <&dmac 14>;
451 dma-names = "rx";
452 };
453
454 spi: ssp@c0006000 {
455 compatible = "arm,pl022", "arm,primecell";
456 reg = <0xc0006000 0x1000>;
457 interrupt-parent = <&vica>;
458 interrupts = <23>;
459 clocks = <&spi_clk>, <&spi_clk>;
460 clock-names = "apb_pclk", "spi_clk";
461 dmas = <&dmac 27 &dmac 28>;
462 dma-names = "tx", "rx";
463 num-cs = <3>;
464 #address-cells = <1>;
465 #size-cells = <0>;
466 spi-dummy@1 {
467 compatible = "arm,pl022-dummy";
468 reg = <1>;
469 spi-max-frequency = <20000000>;
470 };
471 };
472 };
473};
diff --git a/arch/arm/configs/u300_defconfig b/arch/arm/configs/u300_defconfig
index 374000ec4e4e..fd81a1b99cce 100644
--- a/arch/arm/configs/u300_defconfig
+++ b/arch/arm/configs/u300_defconfig
@@ -1,7 +1,8 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_LOCALVERSION_AUTO is not set 1# CONFIG_LOCALVERSION_AUTO is not set
3# CONFIG_SWAP is not set 2# CONFIG_SWAP is not set
4CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
4CONFIG_NO_HZ=y
5CONFIG_HIGH_RES_TIMERS=y
5CONFIG_LOG_BUF_SHIFT=14 6CONFIG_LOG_BUF_SHIFT=14
6CONFIG_EXPERT=y 7CONFIG_EXPERT=y
7# CONFIG_AIO is not set 8# CONFIG_AIO is not set
@@ -11,12 +12,9 @@ CONFIG_MODULE_UNLOAD=y
11# CONFIG_LBDAF is not set 12# CONFIG_LBDAF is not set
12# CONFIG_BLK_DEV_BSG is not set 13# CONFIG_BLK_DEV_BSG is not set
13# CONFIG_IOSCHED_CFQ is not set 14# CONFIG_IOSCHED_CFQ is not set
15# CONFIG_ARCH_MULTI_V7 is not set
14CONFIG_ARCH_U300=y 16CONFIG_ARCH_U300=y
15CONFIG_MACH_U300=y
16CONFIG_MACH_U300_BS335=y
17CONFIG_MACH_U300_SPIDUMMY=y 17CONFIG_MACH_U300_SPIDUMMY=y
18CONFIG_NO_HZ=y
19CONFIG_HIGH_RES_TIMERS=y
20CONFIG_PREEMPT=y 18CONFIG_PREEMPT=y
21CONFIG_AEABI=y 19CONFIG_AEABI=y
22CONFIG_ZBOOT_ROM_TEXT=0x0 20CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -44,14 +42,15 @@ CONFIG_I2C=y
44# CONFIG_HWMON is not set 42# CONFIG_HWMON is not set
45CONFIG_WATCHDOG=y 43CONFIG_WATCHDOG=y
46CONFIG_REGULATOR=y 44CONFIG_REGULATOR=y
45CONFIG_REGULATOR_FIXED_VOLTAGE=y
47CONFIG_FB=y 46CONFIG_FB=y
48CONFIG_BACKLIGHT_LCD_SUPPORT=y 47CONFIG_BACKLIGHT_LCD_SUPPORT=y
49# CONFIG_LCD_CLASS_DEVICE is not set 48# CONFIG_LCD_CLASS_DEVICE is not set
50CONFIG_BACKLIGHT_CLASS_DEVICE=y 49CONFIG_BACKLIGHT_CLASS_DEVICE=y
51# CONFIG_HID_SUPPORT is not set
52# CONFIG_USB_SUPPORT is not set 50# CONFIG_USB_SUPPORT is not set
53CONFIG_MMC=y 51CONFIG_MMC=y
54CONFIG_MMC_CLKGATE=y 52CONFIG_MMC_UNSAFE_RESUME=y
53# CONFIG_MMC_BLOCK_BOUNCE is not set
55CONFIG_MMC_ARMMMCI=y 54CONFIG_MMC_ARMMMCI=y
56CONFIG_RTC_CLASS=y 55CONFIG_RTC_CLASS=y
57# CONFIG_RTC_HCTOSYS is not set 56# CONFIG_RTC_HCTOSYS is not set
@@ -70,4 +69,3 @@ CONFIG_DEBUG_FS=y
70CONFIG_TIMER_STATS=y 69CONFIG_TIMER_STATS=y
71# CONFIG_DEBUG_PREEMPT is not set 70# CONFIG_DEBUG_PREEMPT is not set
72CONFIG_DEBUG_INFO=y 71CONFIG_DEBUG_INFO=y
73# CONFIG_CRC32 is not set
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/include/debug/u300.S
index 8ae8e4ab34b0..6f04f08a203c 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/u300.S
@@ -1,14 +1,11 @@
1/* 1/*
2 * 2 * Copyright (C) 2006-2013 ST-Ericsson AB
3 * arch-arm/mach-u300/include/mach/debug-macro.S
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2 3 * License terms: GNU General Public License (GPL) version 2
8 * Debugging macro include header. 4 * Debugging macro include header.
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 5 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */ 6 */
11#include <mach/hardware.h> 7#define U300_SLOW_PER_PHYS_BASE 0xc0010000
8#define U300_SLOW_PER_VIRT_BASE 0xff000000
12 9
13 .macro addruart, rp, rv, tmp 10 .macro addruart, rp, rv, tmp
14 /* If we move the address using MMU, use this. */ 11 /* If we move the address using MMU, use this. */
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 1f597647d431..09f4dda01d5f 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,24 +1,46 @@
1if ARCH_U300
2
3menu "ST-Ericsson AB U300/U335 Platform" 1menu "ST-Ericsson AB U300/U335 Platform"
4 2
5comment "ST-Ericsson Mobile Platform Products" 3comment "ST-Ericsson Mobile Platform Products"
6 4
7config MACH_U300 5config ARCH_U300
8 bool "U300" 6 bool "ST-Ericsson U300 Series"
7 depends on MMU
8 select ARCH_REQUIRE_GPIOLIB
9 select ARM_AMBA
10 select ARM_PATCH_PHYS_VIRT
11 select ARM_VIC
12 select CLKDEV_LOOKUP
13 select CLKSRC_MMIO
14 select CLKSRC_OF
15 select COMMON_CLK
16 select CPU_ARM926T
17 select GENERIC_CLOCKEVENTS
18 select HAVE_TCM
9 select PINCTRL 19 select PINCTRL
10 select PINCTRL_COH901 20 select PINCTRL_COH901
11 select PINCTRL_U300 21 select PINCTRL_U300
22 select SPARSE_IRQ
23 select MFD_SYSCON
24 select USE_OF
25 help
26 Support for ST-Ericsson U300 series mobile platforms.
12 27
13comment "ST-Ericsson U300/U335 Feature Selections" 28comment "ST-Ericsson U300/U335 Feature Selections"
14 29
30config MACH_U300
31 depends on ARCH_U300
32 bool "U300"
33 default y
34
15config U300_DEBUG 35config U300_DEBUG
36 depends on ARCH_U300
16 bool "Debug support for U300" 37 bool "Debug support for U300"
17 depends on PM 38 depends on PM
18 help 39 help
19 Debug support for U300 in sysfs, procfs etc. 40 Debug support for U300 in sysfs, procfs etc.
20 41
21config MACH_U300_SPIDUMMY 42config MACH_U300_SPIDUMMY
43 depends on ARCH_U300
22 bool "SSP/SPI dummy chip" 44 bool "SSP/SPI dummy chip"
23 select SPI 45 select SPI
24 select SPI_MASTER 46 select SPI_MASTER
@@ -31,5 +53,3 @@ config MACH_U300_SPIDUMMY
31 SPI framework and ARM PL022 support. 53 SPI framework and ARM PL022 support.
32 54
33endmenu 55endmenu
34
35endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 5a86c58da396..0f362b64fb87 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,5 @@ obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
9 9
10obj-$(CONFIG_SPI_PL022) += spi.o
11obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o 10obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o
12obj-$(CONFIG_I2C_STU300) += i2c.o
13obj-$(CONFIG_REGULATOR_AB3100) += regulator.o 11obj-$(CONFIG_REGULATOR_AB3100) += regulator.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index a683d17b2ce4..4f7ac2a11452 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -9,46 +9,157 @@
9 * Author: Linus Walleij <linus.walleij@stericsson.com> 9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/mm.h>
18#include <linux/termios.h>
19#include <linux/dmaengine.h>
20#include <linux/amba/bus.h>
21#include <linux/amba/mmci.h>
22#include <linux/amba/serial.h>
23#include <linux/platform_device.h>
24#include <linux/gpio.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/mtd/nand.h>
28#include <linux/mtd/fsmc.h>
29#include <linux/pinctrl/machine.h> 12#include <linux/pinctrl/machine.h>
30#include <linux/pinctrl/pinconf-generic.h> 13#include <linux/pinctrl/pinconf-generic.h>
31#include <linux/dma-mapping.h>
32#include <linux/platform_data/clk-u300.h> 14#include <linux/platform_data/clk-u300.h>
33#include <linux/platform_data/pinctrl-coh901.h> 15#include <linux/irqchip.h>
34#include <linux/platform_data/dma-coh901318.h> 16#include <linux/of_address.h>
35#include <linux/irqchip/arm-vic.h> 17#include <linux/of_platform.h>
18#include <linux/clocksource.h>
19#include <linux/clk.h>
36 20
37#include <asm/types.h>
38#include <asm/setup.h>
39#include <asm/memory.h>
40#include <asm/mach/map.h> 21#include <asm/mach/map.h>
41#include <asm/mach-types.h>
42#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
43 23
44#include <mach/hardware.h> 24/*
45#include <mach/syscon.h> 25 * These are the large blocks of memory allocated for I/O.
46#include <mach/irqs.h> 26 * the defines are used for setting up the I/O memory mapping.
27 */
28
29/* NAND Flash CS0 */
30#define U300_NAND_CS0_PHYS_BASE 0x80000000
31/* NFIF */
32#define U300_NAND_IF_PHYS_BASE 0x9f800000
33/* ALE, CLE offset for FSMC NAND */
34#define PLAT_NAND_CLE (1 << 16)
35#define PLAT_NAND_ALE (1 << 17)
36/* AHB Peripherals */
37#define U300_AHB_PER_PHYS_BASE 0xa0000000
38#define U300_AHB_PER_VIRT_BASE 0xff010000
39/* FAST Peripherals */
40#define U300_FAST_PER_PHYS_BASE 0xc0000000
41#define U300_FAST_PER_VIRT_BASE 0xff020000
42/* SLOW Peripherals */
43#define U300_SLOW_PER_PHYS_BASE 0xc0010000
44#define U300_SLOW_PER_VIRT_BASE 0xff000000
45/* Boot ROM */
46#define U300_BOOTROM_PHYS_BASE 0xffff0000
47#define U300_BOOTROM_VIRT_BASE 0xffff0000
48/* SEMI config base */
49#define U300_SEMI_CONFIG_BASE 0x2FFE0000
50
51/*
52 * AHB peripherals
53 */
54
55/* AHB Peripherals Bridge Controller */
56#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
57/* Vectored Interrupt Controller 0, servicing 32 interrupts */
58#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
59#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
60/* Vectored Interrupt Controller 1, servicing 32 interrupts */
61#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
62#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
63/* Memory Stick Pro (MSPRO) controller */
64#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
65/* EMIF Configuration Area */
66#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
67
68/*
69 * FAST peripherals
70 */
71
72/* FAST bridge control */
73#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
74/* MMC/SD controller */
75#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
76/* PCM I2S0 controller */
77#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
78/* PCM I2S1 controller */
79#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
80/* I2C0 controller */
81#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
82/* I2C1 controller */
83#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
84/* SPI controller */
85#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
86/* Fast UART1 on U335 only */
87#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
88
89/*
90 * SLOW peripherals
91 */
92
93/* SLOW bridge control */
94#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
95/* SYSCON */
96#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
97#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
98/* Watchdog */
99#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
100/* UART0 */
101#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
102/* APP side special timer */
103#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
104#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
105/* Keypad */
106#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
107/* GPIO */
108#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
109/* RTC */
110#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
111/* Bus tracer */
112#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
113/* Event handler (hardware queue) */
114#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
115/* Genric Timer */
116#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
117/* PPM */
118#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
119
120/*
121 * REST peripherals
122 */
123
124/* ISP (image signal processor) */
125#define U300_ISP_BASE (0xA0008000)
126/* DMA Controller base */
127#define U300_DMAC_BASE (0xC0020000)
128/* MSL Base */
129#define U300_MSL_BASE (0xc0022000)
130/* APEX Base */
131#define U300_APEX_BASE (0xc0030000)
132/* Video Encoder Base */
133#define U300_VIDEOENC_BASE (0xc0080000)
134/* XGAM Base */
135#define U300_XGAM_BASE (0xd0000000)
136
137/*
138 * SYSCON addresses applicable to the core machine.
139 */
47 140
48#include "timer.h" 141/* Chip ID register 16bit (R/-) */
49#include "spi.h" 142#define U300_SYSCON_CIDR (0x400)
50#include "i2c.h" 143/* SMCR */
51#include "u300-gpio.h" 144#define U300_SYSCON_SMCR (0x4d0)
145#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
146#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
147#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
148#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
149/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
150#define U300_SYSCON_CSDR (0x4f0)
151#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
152/* PRINT_CONTROL Print Control 16bit (R/-) */
153#define U300_SYSCON_PCR (0x4f8)
154#define U300_SYSCON_PCR_SERV_IND (0x0001)
155/* BOOT_CONTROL 16bit (R/-) */
156#define U300_SYSCON_BCR (0x4fc)
157#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
158#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
159#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
160#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
161
162static void __iomem *syscon_base;
52 163
53/* 164/*
54 * Static I/O mappings that are needed for booting the U300 platforms. The 165 * Static I/O mappings that are needed for booting the U300 platforms. The
@@ -82,365 +193,6 @@ static void __init u300_map_io(void)
82 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); 193 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
83} 194}
84 195
85/*
86 * Declaration of devices found on the U300 board and
87 * their respective memory locations.
88 */
89
90static struct amba_pl011_data uart0_plat_data = {
91#ifdef CONFIG_COH901318
92 .dma_filter = coh901318_filter_id,
93 .dma_rx_param = (void *) U300_DMA_UART0_RX,
94 .dma_tx_param = (void *) U300_DMA_UART0_TX,
95#endif
96};
97
98/* Slow device at 0x3000 offset */
99static AMBA_APB_DEVICE(uart0, "uart0", 0, U300_UART0_BASE,
100 { IRQ_U300_UART0 }, &uart0_plat_data);
101
102/* The U335 have an additional UART1 on the APP CPU */
103static struct amba_pl011_data uart1_plat_data = {
104#ifdef CONFIG_COH901318
105 .dma_filter = coh901318_filter_id,
106 .dma_rx_param = (void *) U300_DMA_UART1_RX,
107 .dma_tx_param = (void *) U300_DMA_UART1_TX,
108#endif
109};
110
111/* Fast device at 0x7000 offset */
112static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
113 { IRQ_U300_UART1 }, &uart1_plat_data);
114
115/* AHB device at 0x4000 offset */
116static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
117
118/* Fast device at 0x6000 offset */
119static AMBA_APB_DEVICE(pl022, "pl022", 0, U300_SPI_BASE,
120 { IRQ_U300_SPI }, NULL);
121
122/* Fast device at 0x1000 offset */
123#define U300_MMCSD_IRQS { IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 }
124
125static struct mmci_platform_data mmcsd_platform_data = {
126 /*
127 * Do not set ocr_mask or voltage translation function,
128 * we have a regulator we can control instead.
129 */
130 .f_max = 24000000,
131 .gpio_wp = -1,
132 .gpio_cd = U300_GPIO_PIN_MMC_CD,
133 .cd_invert = true,
134 .capabilities = MMC_CAP_MMC_HIGHSPEED |
135 MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
136#ifdef CONFIG_COH901318
137 .dma_filter = coh901318_filter_id,
138 .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX,
139 /* Don't specify a TX channel, this RX channel is bidirectional */
140#endif
141};
142
143static AMBA_APB_DEVICE(mmcsd, "mmci", 0, U300_MMCSD_BASE,
144 U300_MMCSD_IRQS, &mmcsd_platform_data);
145
146/*
147 * The order of device declaration may be important, since some devices
148 * have dependencies on other devices being initialized first.
149 */
150static struct amba_device *amba_devs[] __initdata = {
151 &uart0_device,
152 &uart1_device,
153 &pl022_device,
154 &pl172_device,
155 &mmcsd_device,
156};
157
158/* Here follows a list of all hw resources that the platform devices
159 * allocate. Note, clock dependencies are not included
160 */
161
162static struct resource gpio_resources[] = {
163 {
164 .start = U300_GPIO_BASE,
165 .end = (U300_GPIO_BASE + SZ_4K - 1),
166 .flags = IORESOURCE_MEM,
167 },
168 {
169 .name = "gpio0",
170 .start = IRQ_U300_GPIO_PORT0,
171 .end = IRQ_U300_GPIO_PORT0,
172 .flags = IORESOURCE_IRQ,
173 },
174 {
175 .name = "gpio1",
176 .start = IRQ_U300_GPIO_PORT1,
177 .end = IRQ_U300_GPIO_PORT1,
178 .flags = IORESOURCE_IRQ,
179 },
180 {
181 .name = "gpio2",
182 .start = IRQ_U300_GPIO_PORT2,
183 .end = IRQ_U300_GPIO_PORT2,
184 .flags = IORESOURCE_IRQ,
185 },
186 {
187 .name = "gpio3",
188 .start = IRQ_U300_GPIO_PORT3,
189 .end = IRQ_U300_GPIO_PORT3,
190 .flags = IORESOURCE_IRQ,
191 },
192 {
193 .name = "gpio4",
194 .start = IRQ_U300_GPIO_PORT4,
195 .end = IRQ_U300_GPIO_PORT4,
196 .flags = IORESOURCE_IRQ,
197 },
198 {
199 .name = "gpio5",
200 .start = IRQ_U300_GPIO_PORT5,
201 .end = IRQ_U300_GPIO_PORT5,
202 .flags = IORESOURCE_IRQ,
203 },
204 {
205 .name = "gpio6",
206 .start = IRQ_U300_GPIO_PORT6,
207 .end = IRQ_U300_GPIO_PORT6,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211
212static struct resource keypad_resources[] = {
213 {
214 .start = U300_KEYPAD_BASE,
215 .end = U300_KEYPAD_BASE + SZ_4K - 1,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .name = "coh901461-press",
220 .start = IRQ_U300_KEYPAD_KEYBF,
221 .end = IRQ_U300_KEYPAD_KEYBF,
222 .flags = IORESOURCE_IRQ,
223 },
224 {
225 .name = "coh901461-release",
226 .start = IRQ_U300_KEYPAD_KEYBR,
227 .end = IRQ_U300_KEYPAD_KEYBR,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct resource rtc_resources[] = {
233 {
234 .start = U300_RTC_BASE,
235 .end = U300_RTC_BASE + SZ_4K - 1,
236 .flags = IORESOURCE_MEM,
237 },
238 {
239 .start = IRQ_U300_RTC,
240 .end = IRQ_U300_RTC,
241 .flags = IORESOURCE_IRQ,
242 },
243};
244
245/*
246 * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
247 * but these are not yet used by the driver.
248 */
249static struct resource fsmc_resources[] = {
250 {
251 .name = "nand_addr",
252 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE,
253 .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_ALE + SZ_16K - 1,
254 .flags = IORESOURCE_MEM,
255 },
256 {
257 .name = "nand_cmd",
258 .start = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE,
259 .end = U300_NAND_CS0_PHYS_BASE + PLAT_NAND_CLE + SZ_16K - 1,
260 .flags = IORESOURCE_MEM,
261 },
262 {
263 .name = "nand_data",
264 .start = U300_NAND_CS0_PHYS_BASE,
265 .end = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
266 .flags = IORESOURCE_MEM,
267 },
268 {
269 .name = "fsmc_regs",
270 .start = U300_NAND_IF_PHYS_BASE,
271 .end = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
272 .flags = IORESOURCE_MEM,
273 },
274};
275
276static struct resource i2c0_resources[] = {
277 {
278 .start = U300_I2C0_BASE,
279 .end = U300_I2C0_BASE + SZ_4K - 1,
280 .flags = IORESOURCE_MEM,
281 },
282 {
283 .start = IRQ_U300_I2C0,
284 .end = IRQ_U300_I2C0,
285 .flags = IORESOURCE_IRQ,
286 },
287};
288
289static struct resource i2c1_resources[] = {
290 {
291 .start = U300_I2C1_BASE,
292 .end = U300_I2C1_BASE + SZ_4K - 1,
293 .flags = IORESOURCE_MEM,
294 },
295 {
296 .start = IRQ_U300_I2C1,
297 .end = IRQ_U300_I2C1,
298 .flags = IORESOURCE_IRQ,
299 },
300
301};
302
303static struct resource wdog_resources[] = {
304 {
305 .start = U300_WDOG_BASE,
306 .end = U300_WDOG_BASE + SZ_4K - 1,
307 .flags = IORESOURCE_MEM,
308 },
309 {
310 .start = IRQ_U300_WDOG,
311 .end = IRQ_U300_WDOG,
312 .flags = IORESOURCE_IRQ,
313 }
314};
315
316static struct resource dma_resource[] = {
317 {
318 .start = U300_DMAC_BASE,
319 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
320 .flags = IORESOURCE_MEM,
321 },
322 {
323 .start = IRQ_U300_DMA,
324 .end = IRQ_U300_DMA,
325 .flags = IORESOURCE_IRQ,
326 }
327};
328
329
330static struct resource pinctrl_resources[] = {
331 {
332 .start = U300_SYSCON_BASE,
333 .end = U300_SYSCON_BASE + SZ_4K - 1,
334 .flags = IORESOURCE_MEM,
335 },
336};
337
338static struct platform_device wdog_device = {
339 .name = "coh901327_wdog",
340 .id = -1,
341 .num_resources = ARRAY_SIZE(wdog_resources),
342 .resource = wdog_resources,
343};
344
345static struct platform_device i2c0_device = {
346 .name = "stu300",
347 .id = 0,
348 .num_resources = ARRAY_SIZE(i2c0_resources),
349 .resource = i2c0_resources,
350};
351
352static struct platform_device i2c1_device = {
353 .name = "stu300",
354 .id = 1,
355 .num_resources = ARRAY_SIZE(i2c1_resources),
356 .resource = i2c1_resources,
357};
358
359static struct platform_device pinctrl_device = {
360 .name = "pinctrl-u300",
361 .id = -1,
362 .num_resources = ARRAY_SIZE(pinctrl_resources),
363 .resource = pinctrl_resources,
364};
365
366/*
367 * The different variants have a few different versions of the
368 * GPIO block, with different number of ports.
369 */
370static struct u300_gpio_platform u300_gpio_plat = {
371 .ports = 7,
372 .gpio_base = 0,
373};
374
375static struct platform_device gpio_device = {
376 .name = "u300-gpio",
377 .id = -1,
378 .num_resources = ARRAY_SIZE(gpio_resources),
379 .resource = gpio_resources,
380 .dev = {
381 .platform_data = &u300_gpio_plat,
382 },
383};
384
385static struct platform_device keypad_device = {
386 .name = "keypad",
387 .id = -1,
388 .num_resources = ARRAY_SIZE(keypad_resources),
389 .resource = keypad_resources,
390};
391
392static struct platform_device rtc_device = {
393 .name = "rtc-coh901331",
394 .id = -1,
395 .num_resources = ARRAY_SIZE(rtc_resources),
396 .resource = rtc_resources,
397};
398
399static struct mtd_partition u300_partitions[] = {
400 {
401 .name = "bootrecords",
402 .offset = 0,
403 .size = SZ_128K,
404 },
405 {
406 .name = "free",
407 .offset = SZ_128K,
408 .size = 8064 * SZ_1K,
409 },
410 {
411 .name = "platform",
412 .offset = 8192 * SZ_1K,
413 .size = 253952 * SZ_1K,
414 },
415};
416
417static struct fsmc_nand_platform_data nand_platform_data = {
418 .partitions = u300_partitions,
419 .nr_partitions = ARRAY_SIZE(u300_partitions),
420 .options = NAND_SKIP_BBTSCAN,
421 .width = FSMC_NAND_BW8,
422};
423
424static struct platform_device nand_device = {
425 .name = "fsmc-nand",
426 .id = -1,
427 .resource = fsmc_resources,
428 .num_resources = ARRAY_SIZE(fsmc_resources),
429 .dev = {
430 .platform_data = &nand_platform_data,
431 },
432};
433
434static struct platform_device dma_device = {
435 .name = "coh901318",
436 .id = -1,
437 .resource = dma_resource,
438 .num_resources = ARRAY_SIZE(dma_resource),
439 .dev = {
440 .coherent_dma_mask = ~0,
441 },
442};
443
444static unsigned long pin_pullup_conf[] = { 196static unsigned long pin_pullup_conf[] = {
445 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1), 197 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 1),
446}; 198};
@@ -467,61 +219,6 @@ static struct pinctrl_map __initdata u300_pinmux_map[] = {
467 pin_highz_conf), 219 pin_highz_conf),
468}; 220};
469 221
470/*
471 * Notice that AMBA devices are initialized before platform devices.
472 *
473 */
474static struct platform_device *platform_devs[] __initdata = {
475 &dma_device,
476 &i2c0_device,
477 &i2c1_device,
478 &keypad_device,
479 &rtc_device,
480 &pinctrl_device,
481 &gpio_device,
482 &nand_device,
483 &wdog_device,
484};
485
486/*
487 * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
488 * together so some interrupts are connected to the first one and some
489 * to the second one.
490 */
491static void __init u300_init_irq(void)
492{
493 u32 mask[2] = {0, 0};
494 struct clk *clk;
495 int i;
496
497 /* initialize clocking early, we want to clock the INTCON */
498 u300_clk_init(U300_SYSCON_VBASE);
499
500 /* Bootstrap EMIF and SEMI clocks */
501 clk = clk_get_sys("pl172", NULL);
502 BUG_ON(IS_ERR(clk));
503 clk_prepare_enable(clk);
504 clk = clk_get_sys("semi", NULL);
505 BUG_ON(IS_ERR(clk));
506 clk_prepare_enable(clk);
507
508 /* Clock the interrupt controller */
509 clk = clk_get_sys("intcon", NULL);
510 BUG_ON(IS_ERR(clk));
511 clk_prepare_enable(clk);
512
513 for (i = 0; i < U300_VIC_IRQS_END; i++)
514 set_bit(i, (unsigned long *) &mask[0]);
515 vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
516 mask[0], mask[0]);
517 vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
518 mask[1], mask[1]);
519}
520
521
522/*
523 * U300 platforms peripheral handling
524 */
525struct db_chip { 222struct db_chip {
526 u16 chipid; 223 u16 chipid;
527 const char *name; 224 const char *name;
@@ -578,7 +275,7 @@ static void __init u300_init_check_chip(void)
578 const char unknown[] = "UNKNOWN"; 275 const char unknown[] = "UNKNOWN";
579 276
580 /* Read out and print chip ID */ 277 /* Read out and print chip ID */
581 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR); 278 val = readw(syscon_base + U300_SYSCON_CIDR);
582 /* This is in funky bigendian order... */ 279 /* This is in funky bigendian order... */
583 val = (val & 0xFFU) << 8 | (val >> 8); 280 val = (val & 0xFFU) << 8 | (val >> 8);
584 chip = db_chips; 281 chip = db_chips;
@@ -600,74 +297,6 @@ static void __init u300_init_check_chip(void)
600 } 297 }
601} 298}
602 299
603/*
604 * Some devices and their resources require reserved physical memory from
605 * the end of the available RAM. This function traverses the list of devices
606 * and assigns actual addresses to these.
607 */
608static void __init u300_assign_physmem(void)
609{
610 unsigned long curr_start = __pa(high_memory);
611 int i, j;
612
613 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
614 for (j = 0; j < platform_devs[i]->num_resources; j++) {
615 struct resource *const res =
616 &platform_devs[i]->resource[j];
617
618 if (IORESOURCE_MEM == res->flags &&
619 0 == res->start) {
620 res->start = curr_start;
621 res->end += curr_start;
622 curr_start += resource_size(res);
623
624 printk(KERN_INFO "core.c: Mapping RAM " \
625 "%#x-%#x to device %s:%s\n",
626 res->start, res->end,
627 platform_devs[i]->name, res->name);
628 }
629 }
630 }
631}
632
633static void __init u300_init_machine(void)
634{
635 int i;
636 u16 val;
637
638 /* Check what platform we run and print some status information */
639 u300_init_check_chip();
640
641 /* Initialize SPI device with some board specifics */
642 u300_spi_init(&pl022_device);
643
644 /* Register the AMBA devices in the AMBA bus abstraction layer */
645 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
646 struct amba_device *d = amba_devs[i];
647 amba_device_register(d, &iomem_resource);
648 }
649
650 u300_assign_physmem();
651
652 /* Initialize pinmuxing */
653 pinctrl_register_mappings(u300_pinmux_map,
654 ARRAY_SIZE(u300_pinmux_map));
655
656 /* Register subdevices on the I2C buses */
657 u300_i2c_register_board_devices();
658
659 /* Register the platform devices */
660 platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
661
662 /* Register subdevices on the SPI bus */
663 u300_spi_register_board_devices();
664
665 /* Enable SEMI self refresh */
666 val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
667 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
668 writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
669}
670
671/* Forward declare this function from the watchdog */ 300/* Forward declare this function from the watchdog */
672void coh901327_watchdog_reset(void); 301void coh901327_watchdog_reset(void);
673 302
@@ -688,13 +317,99 @@ static void u300_restart(char mode, const char *cmd)
688 while (1); 317 while (1);
689} 318}
690 319
691MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board") 320/* These are mostly to get the right device names for the clock lookups */
692 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ 321static struct of_dev_auxdata u300_auxdata_lookup[] __initdata = {
693 .atag_offset = 0x100, 322 OF_DEV_AUXDATA("stericsson,pinctrl-u300", U300_SYSCON_BASE,
323 "pinctrl-u300", NULL),
324 OF_DEV_AUXDATA("stericsson,gpio-coh901", U300_GPIO_BASE,
325 "u300-gpio", NULL),
326 OF_DEV_AUXDATA("stericsson,coh901327", U300_WDOG_BASE,
327 "coh901327_wdog", NULL),
328 OF_DEV_AUXDATA("stericsson,coh901331", U300_RTC_BASE,
329 "rtc-coh901331", NULL),
330 OF_DEV_AUXDATA("stericsson,coh901318", U300_DMAC_BASE,
331 "coh901318", NULL),
332 OF_DEV_AUXDATA("stericsson,fsmc-nand", U300_NAND_IF_PHYS_BASE,
333 "fsmc-nand", NULL),
334 OF_DEV_AUXDATA("arm,primecell", U300_UART0_BASE,
335 "uart0", NULL),
336 OF_DEV_AUXDATA("arm,primecell", U300_UART1_BASE,
337 "uart1", NULL),
338 OF_DEV_AUXDATA("arm,primecell", U300_SPI_BASE,
339 "pl022", NULL),
340 OF_DEV_AUXDATA("st,ddci2c", U300_I2C0_BASE,
341 "stu300.0", NULL),
342 OF_DEV_AUXDATA("st,ddci2c", U300_I2C1_BASE,
343 "stu300.1", NULL),
344 OF_DEV_AUXDATA("arm,primecell", U300_MMCSD_BASE,
345 "mmci", NULL),
346 { /* sentinel */ },
347};
348
349static void __init u300_init_irq_dt(void)
350{
351 struct device_node *syscon;
352 struct clk *clk;
353
354 syscon = of_find_node_by_path("/syscon@c0011000");
355 if (!syscon) {
356 pr_crit("could not find syscon node\n");
357 return;
358 }
359 syscon_base = of_iomap(syscon, 0);
360 if (!syscon_base) {
361 pr_crit("could not remap syscon\n");
362 return;
363 }
364 /* initialize clocking early, we want to clock the INTCON */
365 u300_clk_init(syscon_base);
366
367 /* Bootstrap EMIF and SEMI clocks */
368 clk = clk_get_sys("pl172", NULL);
369 BUG_ON(IS_ERR(clk));
370 clk_prepare_enable(clk);
371 clk = clk_get_sys("semi", NULL);
372 BUG_ON(IS_ERR(clk));
373 clk_prepare_enable(clk);
374
375 /* Clock the interrupt controller */
376 clk = clk_get_sys("intcon", NULL);
377 BUG_ON(IS_ERR(clk));
378 clk_prepare_enable(clk);
379
380 irqchip_init();
381}
382
383static void __init u300_init_machine_dt(void)
384{
385 u16 val;
386
387 /* Check what platform we run and print some status information */
388 u300_init_check_chip();
389
390 /* Initialize pinmuxing */
391 pinctrl_register_mappings(u300_pinmux_map,
392 ARRAY_SIZE(u300_pinmux_map));
393
394 of_platform_populate(NULL, of_default_bus_match_table,
395 u300_auxdata_lookup, NULL);
396
397 /* Enable SEMI self refresh */
398 val = readw(syscon_base + U300_SYSCON_SMCR) |
399 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
400 writew(val, syscon_base + U300_SYSCON_SMCR);
401}
402
403static const char * u300_board_compat[] = {
404 "stericsson,u300",
405 NULL,
406};
407
408DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
694 .map_io = u300_map_io, 409 .map_io = u300_map_io,
695 .nr_irqs = 0, 410 .init_irq = u300_init_irq_dt,
696 .init_irq = u300_init_irq, 411 .init_time = clocksource_of_init,
697 .init_time = u300_timer_init, 412 .init_machine = u300_init_machine_dt,
698 .init_machine = u300_init_machine,
699 .restart = u300_restart, 413 .restart = u300_restart,
414 .dt_compat = u300_board_compat,
700MACHINE_END 415MACHINE_END
diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 2785cb67b5e8..ec0283cf9a32 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -263,28 +263,22 @@ static int pl022_dummy_remove(struct spi_device *spi)
263 return 0; 263 return 0;
264} 264}
265 265
266static const struct of_device_id pl022_dummy_dt_match[] = {
267 { .compatible = "arm,pl022-dummy" },
268 {},
269};
270
266static struct spi_driver pl022_dummy_driver = { 271static struct spi_driver pl022_dummy_driver = {
267 .driver = { 272 .driver = {
268 .name = "spi-dummy", 273 .name = "spi-dummy",
269 .owner = THIS_MODULE, 274 .owner = THIS_MODULE,
275 .of_match_table = pl022_dummy_dt_match,
270 }, 276 },
271 .probe = pl022_dummy_probe, 277 .probe = pl022_dummy_probe,
272 .remove = pl022_dummy_remove, 278 .remove = pl022_dummy_remove,
273}; 279};
274 280
275static int __init pl022_init_dummy(void) 281module_spi_driver(pl022_dummy_driver);
276{
277 return spi_register_driver(&pl022_dummy_driver);
278}
279
280static void __exit pl022_exit_dummy(void)
281{
282 spi_unregister_driver(&pl022_dummy_driver);
283}
284
285module_init(pl022_init_dummy);
286module_exit(pl022_exit_dummy);
287
288MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 282MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
289MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver"); 283MODULE_DESCRIPTION("PL022 SSP/SPI DUMMY Linux driver");
290MODULE_LICENSE("GPL"); 284MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
deleted file mode 100644
index 96800aa1316d..000000000000
--- a/arch/arm/mach-u300/i2c.c
+++ /dev/null
@@ -1,285 +0,0 @@
1/*
2 * arch/arm/mach-u300/i2c.c
3 *
4 * Copyright (C) 2009-2012 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * Register board i2c devices
8 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 */
10#include <linux/kernel.h>
11#include <linux/i2c.h>
12#include <linux/mfd/ab3100.h>
13#include <linux/regulator/machine.h>
14#include <linux/amba/bus.h>
15#include <mach/irqs.h>
16
17/*
18 * Initial settings of ab3100 registers.
19 * Common for below LDO regulator settings are that
20 * bit 7-5 controls voltage. Bit 4 turns regulator ON(1) or OFF(0).
21 * Bit 3-2 controls sleep enable and bit 1-0 controls sleep mode.
22 */
23
24/* LDO_A 0x16: 2.75V, ON, SLEEP_A, SLEEP OFF GND */
25#define LDO_A_SETTING 0x16
26/* LDO_C 0x10: 2.65V, ON, SLEEP_A or B, SLEEP full power */
27#define LDO_C_SETTING 0x10
28/* LDO_D 0x10: 2.65V, ON, sleep mode not used */
29#define LDO_D_SETTING 0x10
30/* LDO_E 0x10: 1.8V, ON, SLEEP_A or B, SLEEP full power */
31#define LDO_E_SETTING 0x10
32/* LDO_E SLEEP 0x00: 1.8V, not used, SLEEP_A or B, not used */
33#define LDO_E_SLEEP_SETTING 0x00
34/* LDO_F 0xD0: 2.5V, ON, SLEEP_A or B, SLEEP full power */
35#define LDO_F_SETTING 0xD0
36/* LDO_G 0x00: 2.85V, OFF, SLEEP_A or B, SLEEP full power */
37#define LDO_G_SETTING 0x00
38/* LDO_H 0x18: 2.75V, ON, SLEEP_B, SLEEP full power */
39#define LDO_H_SETTING 0x18
40/* LDO_K 0x00: 2.75V, OFF, SLEEP_A or B, SLEEP full power */
41#define LDO_K_SETTING 0x00
42/* LDO_EXT 0x00: Voltage not set, OFF, not used, not used */
43#define LDO_EXT_SETTING 0x00
44/* BUCK 0x7D: 1.2V, ON, SLEEP_A and B, SLEEP low power */
45#define BUCK_SETTING 0x7D
46/* BUCK SLEEP 0xAC: 1.05V, Not used, SLEEP_A and B, Not used */
47#define BUCK_SLEEP_SETTING 0xAC
48
49#ifdef CONFIG_AB3100_CORE
50static struct regulator_consumer_supply supply_ldo_c[] = {
51 {
52 .dev_name = "ab3100-codec",
53 .supply = "vaudio", /* Powers the codec */
54 },
55};
56
57/*
58 * This one needs to be a supply so we can turn it off
59 * in order to shut down the system.
60 */
61static struct regulator_consumer_supply supply_ldo_d[] = {
62 {
63 .supply = "vana15", /* Powers the SoC (CPU etc) */
64 },
65};
66
67static struct regulator_consumer_supply supply_ldo_g[] = {
68 {
69 .dev_name = "mmci",
70 .supply = "vmmc", /* Powers MMC/SD card */
71 },
72};
73
74static struct regulator_consumer_supply supply_ldo_h[] = {
75 {
76 .dev_name = "xgam_pdi",
77 .supply = "vdisp", /* Powers camera, display etc */
78 },
79};
80
81static struct regulator_consumer_supply supply_ldo_k[] = {
82 {
83 .dev_name = "irda",
84 .supply = "vir", /* Power IrDA */
85 },
86};
87
88/*
89 * This is a placeholder for whoever wish to use the
90 * external power.
91 */
92static struct regulator_consumer_supply supply_ldo_ext[] = {
93 {
94 .supply = "vext", /* External power */
95 },
96};
97
98/* Preset (hardware defined) voltages for these regulators */
99#define LDO_A_VOLTAGE 2750000
100#define LDO_C_VOLTAGE 2650000
101#define LDO_D_VOLTAGE 2650000
102
103static struct ab3100_platform_data ab3100_plf_data = {
104 .reg_constraints = {
105 /* LDO A routing and constraints */
106 {
107 .constraints = {
108 .name = "vrad",
109 .min_uV = LDO_A_VOLTAGE,
110 .max_uV = LDO_A_VOLTAGE,
111 .valid_modes_mask = REGULATOR_MODE_NORMAL,
112 .always_on = 1,
113 .boot_on = 1,
114 },
115 },
116 /* LDO C routing and constraints */
117 {
118 .constraints = {
119 .min_uV = LDO_C_VOLTAGE,
120 .max_uV = LDO_C_VOLTAGE,
121 .valid_modes_mask = REGULATOR_MODE_NORMAL,
122 },
123 .num_consumer_supplies = ARRAY_SIZE(supply_ldo_c),
124 .consumer_supplies = supply_ldo_c,
125 },
126 /* LDO D routing and constraints */
127 {
128 .constraints = {
129 .min_uV = LDO_D_VOLTAGE,
130 .max_uV = LDO_D_VOLTAGE,
131 .valid_modes_mask = REGULATOR_MODE_NORMAL,
132 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
133 /*
134 * Actually this is boot_on but we need
135 * to reference count it externally to
136 * be able to shut down the system.
137 */
138 },
139 .num_consumer_supplies = ARRAY_SIZE(supply_ldo_d),
140 .consumer_supplies = supply_ldo_d,
141 },
142 /* LDO E routing and constraints */
143 {
144 .constraints = {
145 .name = "vio",
146 .min_uV = 1800000,
147 .max_uV = 1800000,
148 .valid_modes_mask = REGULATOR_MODE_NORMAL,
149 .always_on = 1,
150 .boot_on = 1,
151 },
152 },
153 /* LDO F routing and constraints */
154 {
155 .constraints = {
156 .name = "vana25",
157 .min_uV = 2500000,
158 .max_uV = 2500000,
159 .valid_modes_mask = REGULATOR_MODE_NORMAL,
160 .always_on = 1,
161 .boot_on = 1,
162 },
163 },
164 /* LDO G routing and constraints */
165 {
166 .constraints = {
167 .min_uV = 1500000,
168 .max_uV = 2850000,
169 .valid_modes_mask = REGULATOR_MODE_NORMAL,
170 .valid_ops_mask =
171 REGULATOR_CHANGE_VOLTAGE |
172 REGULATOR_CHANGE_STATUS,
173 },
174 .num_consumer_supplies = ARRAY_SIZE(supply_ldo_g),
175 .consumer_supplies = supply_ldo_g,
176 },
177 /* LDO H routing and constraints */
178 {
179 .constraints = {
180 .min_uV = 1200000,
181 .max_uV = 2750000,
182 .valid_modes_mask = REGULATOR_MODE_NORMAL,
183 .valid_ops_mask =
184 REGULATOR_CHANGE_VOLTAGE |
185 REGULATOR_CHANGE_STATUS,
186 },
187 .num_consumer_supplies = ARRAY_SIZE(supply_ldo_h),
188 .consumer_supplies = supply_ldo_h,
189 },
190 /* LDO K routing and constraints */
191 {
192 .constraints = {
193 .min_uV = 1800000,
194 .max_uV = 2750000,
195 .valid_modes_mask = REGULATOR_MODE_NORMAL,
196 .valid_ops_mask =
197 REGULATOR_CHANGE_VOLTAGE |
198 REGULATOR_CHANGE_STATUS,
199 },
200 .num_consumer_supplies = ARRAY_SIZE(supply_ldo_k),
201 .consumer_supplies = supply_ldo_k,
202 },
203 /* External regulator interface. No fixed voltage specified.
204 * If we knew the voltage of the external regulator and it
205 * was connected on the board, we could add the (fixed)
206 * voltage for it here.
207 */
208 {
209 .constraints = {
210 .min_uV = 0,
211 .max_uV = 0,
212 .valid_modes_mask = REGULATOR_MODE_NORMAL,
213 .valid_ops_mask =
214 REGULATOR_CHANGE_STATUS,
215 },
216 .num_consumer_supplies = ARRAY_SIZE(supply_ldo_ext),
217 .consumer_supplies = supply_ldo_ext,
218 },
219 /* Buck converter routing and constraints */
220 {
221 .constraints = {
222 .name = "vcore",
223 .min_uV = 1200000,
224 .max_uV = 1800000,
225 .valid_modes_mask = REGULATOR_MODE_NORMAL,
226 .valid_ops_mask =
227 REGULATOR_CHANGE_VOLTAGE,
228 .always_on = 1,
229 .boot_on = 1,
230 },
231 },
232 },
233 .reg_initvals = {
234 LDO_A_SETTING,
235 LDO_C_SETTING,
236 LDO_E_SETTING,
237 LDO_E_SLEEP_SETTING,
238 LDO_F_SETTING,
239 LDO_G_SETTING,
240 LDO_H_SETTING,
241 LDO_K_SETTING,
242 LDO_EXT_SETTING,
243 BUCK_SETTING,
244 BUCK_SLEEP_SETTING,
245 LDO_D_SETTING,
246 },
247};
248#endif
249
250static struct i2c_board_info __initdata bus0_i2c_board_info[] = {
251#ifdef CONFIG_AB3100_CORE
252 {
253 .type = "ab3100",
254 .addr = 0x48,
255 .irq = IRQ_U300_IRQ0_EXT,
256 .platform_data = &ab3100_plf_data,
257 },
258#else
259 { },
260#endif
261};
262
263static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
264 {
265 .type = "fwcam",
266 .addr = 0x10,
267 },
268 {
269 .type = "fwcam",
270 .addr = 0x5d,
271 },
272};
273
274void __init u300_i2c_register_board_devices(void)
275{
276 i2c_register_board_info(0, bus0_i2c_board_info,
277 ARRAY_SIZE(bus0_i2c_board_info));
278 /*
279 * This makes the core shut down all unused regulators
280 * after all the initcalls have completed.
281 */
282 regulator_has_full_constraints();
283 i2c_register_board_info(1, bus1_i2c_board_info,
284 ARRAY_SIZE(bus1_i2c_board_info));
285}
diff --git a/arch/arm/mach-u300/i2c.h b/arch/arm/mach-u300/i2c.h
deleted file mode 100644
index 485c02e5c06d..000000000000
--- a/arch/arm/mach-u300/i2c.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * arch/arm/mach-u300/i2c.h
3 *
4 * Copyright (C) 2009 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * Register board i2c devices
8 * Author: Linus Walleij <linus.walleij@stericsson.com>
9 */
10
11#ifndef MACH_U300_I2C_H
12#define MACH_U300_I2C_H
13
14#ifdef CONFIG_I2C_STU300
15void __init u300_i2c_register_board_devices(void);
16#else
17/* Compile out this stuff if no I2C adapter is available */
18static inline void __init u300_i2c_register_board_devices(void)
19{
20}
21#endif
22
23#endif
diff --git a/arch/arm/mach-u300/include/mach/hardware.h b/arch/arm/mach-u300/include/mach/hardware.h
deleted file mode 100644
index b99d4ce0ac2b..000000000000
--- a/arch/arm/mach-u300/include/mach/hardware.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * arch/arm/mach-u300/include/mach/hardware.h
3 */
4#include <asm/sizes.h>
5#include <mach/u300-regs.h>
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
deleted file mode 100644
index 21d5e76a6cd3..000000000000
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/irqs.h
4 *
5 *
6 * Copyright (C) 2006-2012 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * IRQ channel definitions for the U300 platforms.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11
12#ifndef __MACH_IRQS_H
13#define __MACH_IRQS_H
14
15#define IRQ_U300_INTCON0_START 32
16#define IRQ_U300_INTCON1_START 64
17/* These are on INTCON0 - 30 lines */
18#define IRQ_U300_IRQ0_EXT 32
19#define IRQ_U300_IRQ1_EXT 33
20#define IRQ_U300_DMA 34
21#define IRQ_U300_VIDEO_ENC_0 35
22#define IRQ_U300_VIDEO_ENC_1 36
23#define IRQ_U300_AAIF_RX 37
24#define IRQ_U300_AAIF_TX 38
25#define IRQ_U300_AAIF_VGPIO 39
26#define IRQ_U300_AAIF_WAKEUP 40
27#define IRQ_U300_PCM_I2S0_FRAME 41
28#define IRQ_U300_PCM_I2S0_FIFO 42
29#define IRQ_U300_PCM_I2S1_FRAME 43
30#define IRQ_U300_PCM_I2S1_FIFO 44
31#define IRQ_U300_XGAM_GAMCON 45
32#define IRQ_U300_XGAM_CDI 46
33#define IRQ_U300_XGAM_CDICON 47
34#define IRQ_U300_XGAM_PDI 49
35#define IRQ_U300_XGAM_PDICON 50
36#define IRQ_U300_XGAM_GAMEACC 51
37#define IRQ_U300_XGAM_MCIDCT 52
38#define IRQ_U300_APEX 53
39#define IRQ_U300_UART0 54
40#define IRQ_U300_SPI 55
41#define IRQ_U300_TIMER_APP_OS 56
42#define IRQ_U300_TIMER_APP_DD 57
43#define IRQ_U300_TIMER_APP_GP1 58
44#define IRQ_U300_TIMER_APP_GP2 59
45#define IRQ_U300_TIMER_OS 60
46#define IRQ_U300_TIMER_MS 61
47#define IRQ_U300_KEYPAD_KEYBF 62
48#define IRQ_U300_KEYPAD_KEYBR 63
49/* These are on INTCON1 - 32 lines */
50#define IRQ_U300_GPIO_PORT0 64
51#define IRQ_U300_GPIO_PORT1 65
52#define IRQ_U300_GPIO_PORT2 66
53
54/* These are for DB3150, DB3200 and DB3350 */
55#define IRQ_U300_WDOG 67
56#define IRQ_U300_EVHIST 68
57#define IRQ_U300_MSPRO 69
58#define IRQ_U300_MMCSD_MCIINTR0 70
59#define IRQ_U300_MMCSD_MCIINTR1 71
60#define IRQ_U300_I2C0 72
61#define IRQ_U300_I2C1 73
62#define IRQ_U300_RTC 74
63#define IRQ_U300_NFIF 75
64#define IRQ_U300_NFIF2 76
65
66/* The DB3350-specific interrupt lines */
67#define IRQ_U300_ISP_F0 77
68#define IRQ_U300_ISP_F1 78
69#define IRQ_U300_ISP_F2 79
70#define IRQ_U300_ISP_F3 80
71#define IRQ_U300_ISP_F4 81
72#define IRQ_U300_GPIO_PORT3 82
73#define IRQ_U300_SYSCON_PLL_LOCK 83
74#define IRQ_U300_UART1 84
75#define IRQ_U300_GPIO_PORT4 85
76#define IRQ_U300_GPIO_PORT5 86
77#define IRQ_U300_GPIO_PORT6 87
78#define U300_VIC_IRQS_END 88
79
80#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
deleted file mode 100644
index 10bdd0be9774..000000000000
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ /dev/null
@@ -1,592 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/syscon.h
4 *
5 *
6 * Copyright (C) 2008-2012 ST-Ericsson AB
7 *
8 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
9 */
10
11#ifndef __MACH_SYSCON_H
12#define __MACH_SYSCON_H
13
14/*
15 * All register defines for SYSCON registers that concerns individual
16 * block clocks and reset lines are registered here. This is because
17 * we don't want any other file to try to fool around with this stuff.
18 */
19
20/* APP side SYSCON registers */
21/* TODO: this is incomplete. Add all from asic_syscon_map.h eventually. */
22/* CLK Control Register 16bit (R/W) */
23#define U300_SYSCON_CCR (0x0000)
24#define U300_SYSCON_CCR_I2S1_USE_VCXO (0x0040)
25#define U300_SYSCON_CCR_I2S0_USE_VCXO (0x0020)
26#define U300_SYSCON_CCR_TURN_VCXO_ON (0x0008)
27#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK (0x0007)
28#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER (0x04)
29#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW (0x03)
30#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE (0x02)
31#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH (0x01)
32#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST (0x00)
33/* CLK Status Register 16bit (R/W) */
34#define U300_SYSCON_CSR (0x0004)
35#define U300_SYSCON_CSR_PLL208_LOCK_IND (0x0002)
36#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
37/* Reset lines for SLOW devices 16bit (R/W) */
38#define U300_SYSCON_RSR (0x0014)
39#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
40#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
41#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
42#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
43#define U300_SYSCON_RSR_KEYPAD_RESET_EN (0x0020)
44#define U300_SYSCON_RSR_GPIO_RESET_EN (0x0010)
45#define U300_SYSCON_RSR_EH_RESET_EN (0x0008)
46#define U300_SYSCON_RSR_BTR_RESET_EN (0x0004)
47#define U300_SYSCON_RSR_UART_RESET_EN (0x0002)
48#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
49/* Reset lines for FAST devices 16bit (R/W) */
50#define U300_SYSCON_RFR (0x0018)
51#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
52#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
53#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
54#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
55#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE (0x0008)
56#define U300_SYSCON_RFR_I2C1_RESET_ENABLE (0x0004)
57#define U300_SYSCON_RFR_I2C0_RESET_ENABLE (0x0002)
58#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
59/* Reset lines for the rest of the peripherals 16bit (R/W) */
60#define U300_SYSCON_RRR (0x001c)
61#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
62#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
63#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
64#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
65#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
66#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN (0x0080)
67#define U300_SYSCON_RRR_NANDIF_RESET_EN (0x0040)
68#define U300_SYSCON_RRR_EMIF_RESET_EN (0x0020)
69#define U300_SYSCON_RRR_DMAC_RESET_EN (0x0010)
70#define U300_SYSCON_RRR_CPU_RESET_EN (0x0008)
71#define U300_SYSCON_RRR_APEX_RESET_EN (0x0004)
72#define U300_SYSCON_RRR_AHB_RESET_EN (0x0002)
73#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
74/* Clock enable for SLOW peripherals 16bit (R/W) */
75#define U300_SYSCON_CESR (0x0020)
76#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
77#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
78#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
79#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
80#define U300_SYSCON_CESR_GPIO_CLK_EN (0x0010)
81#define U300_SYSCON_CESR_EH_CLK_EN (0x0008)
82#define U300_SYSCON_CESR_BTR_CLK_EN (0x0004)
83#define U300_SYSCON_CESR_UART_CLK_EN (0x0002)
84#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
85/* Clock enable for FAST peripherals 16bit (R/W) */
86#define U300_SYSCON_CEFR (0x0024)
87#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
88#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
89#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
90#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
91#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
92#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
93#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
94#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
95#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
96#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
97/* Clock enable for the rest of the peripherals 16bit (R/W) */
98#define U300_SYSCON_CERR (0x0028)
99#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
100#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
101#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
102#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
103#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
104#define U300_SYSCON_CERR_XGAM_CLK_EN (0x0100)
105#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN (0x0080)
106#define U300_SYSCON_CERR_NANDIF_CLK_EN (0x0040)
107#define U300_SYSCON_CERR_EMIF_CLK_EN (0x0020)
108#define U300_SYSCON_CERR_DMAC_CLK_EN (0x0010)
109#define U300_SYSCON_CERR_CPU_CLK_EN (0x0008)
110#define U300_SYSCON_CERR_APEX_CLK_EN (0x0004)
111#define U300_SYSCON_CERR_AHB_CLK_EN (0x0002)
112#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
113/* Single block clock enable 16bit (-/W) */
114#define U300_SYSCON_SBCER (0x002c)
115#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
116#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
117#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
118#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
119#define U300_SYSCON_SBCER_GPIO_CLK_EN (0x0004)
120#define U300_SYSCON_SBCER_EH_CLK_EN (0x0003)
121#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
122#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
123#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
124#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
125#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
126#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
127#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
128#define U300_SYSCON_SBCER_MMC_CLK_EN (0x0015)
129#define U300_SYSCON_SBCER_I2S1_CLK_EN (0x0014)
130#define U300_SYSCON_SBCER_I2S0_CLK_EN (0x0013)
131#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
132#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
133#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
134#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
135#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
136#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
137#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
138#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
139#define U300_SYSCON_SBCER_XGAM_CLK_EN (0x0028)
140#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN (0x0027)
141#define U300_SYSCON_SBCER_NANDIF_CLK_EN (0x0026)
142#define U300_SYSCON_SBCER_EMIF_CLK_EN (0x0025)
143#define U300_SYSCON_SBCER_DMAC_CLK_EN (0x0024)
144#define U300_SYSCON_SBCER_CPU_CLK_EN (0x0023)
145#define U300_SYSCON_SBCER_APEX_CLK_EN (0x0022)
146#define U300_SYSCON_SBCER_AHB_CLK_EN (0x0021)
147#define U300_SYSCON_SBCER_AAIF_CLK_EN (0x0020)
148/* Single block clock disable 16bit (-/W) */
149#define U300_SYSCON_SBCDR (0x0030)
150/* Same values as above for SBCER */
151/* Clock force SLOW peripherals 16bit (R/W) */
152#define U300_SYSCON_CFSR (0x003c)
153#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
154#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
155#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
156#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
157#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN (0x0010)
158#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN (0x0008)
159#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN (0x0004)
160#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN (0x0002)
161#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN (0x0001)
162/* Clock force FAST peripherals 16bit (R/W) */
163#define U300_SYSCON_CFFR (0x40)
164/* Values not defined. Define if you want to use them. */
165/* Clock force the rest of the peripherals 16bit (R/W) */
166#define U300_SYSCON_CFRR (0x44)
167#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
168#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
169#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
170#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
171#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
172#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN (0x0100)
173#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN (0x0080)
174#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN (0x0040)
175#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN (0x0020)
176#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN (0x0010)
177#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN (0x0008)
178#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN (0x0004)
179#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN (0x0002)
180#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN (0x0001)
181/* PLL208 Frequency Control 16bit (R/W) */
182#define U300_SYSCON_PFCR (0x48)
183#define U300_SYSCON_PFCR_DPLL_MULT_NUM (0x000F)
184/* Power Management Control 16bit (R/W) */
185#define U300_SYSCON_PMCR (0x50)
186#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
187#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
188/*
189 * All other clocking registers moved to clock.c!
190 */
191/* Reset Out 16bit (R/W) */
192#define U300_SYSCON_RCR (0x6c)
193#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE (0x0001)
194/* EMIF Slew Rate Control 16bit (R/W) */
195#define U300_SYSCON_SRCLR (0x70)
196#define U300_SYSCON_SRCLR_MASK (0x03FF)
197#define U300_SYSCON_SRCLR_VALUE (0x03FF)
198#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B (0x0200)
199#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A (0x0100)
200#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B (0x0080)
201#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A (0x0040)
202#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B (0x0020)
203#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A (0x0010)
204#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B (0x0008)
205#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A (0x0004)
206#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B (0x0002)
207#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A (0x0001)
208/* EMIF Clock Control Register 16bit (R/W) */
209#define U300_SYSCON_ECCR (0x0078)
210#define U300_SYSCON_ECCR_MASK (0x000F)
211#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE (0x0008)
212#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE (0x0004)
213#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE (0x0002)
214#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE (0x0001)
215/* Step one for killing the applications system 16bit (-/W) */
216#define U300_SYSCON_KA1R (0x0080)
217#define U300_SYSCON_KA1R_MASK (0xFFFF)
218#define U300_SYSCON_KA1R_VALUE (0xFFFF)
219/* Step two for killing the application system 16bit (-/W) */
220#define U300_SYSCON_KA2R (0x0084)
221#define U300_SYSCON_KA2R_MASK (0xFFFF)
222#define U300_SYSCON_KA2R_VALUE (0xFFFF)
223/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
224#define U300_SYSCON_MMF0R (0x90)
225#define U300_SYSCON_MMF0R_MASK (0x00FF)
226#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK (0x00F0)
227#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK (0x000F)
228/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
229#define U300_SYSCON_MMF1R (0x94)
230#define U300_SYSCON_MMF1R_MASK (0x00FF)
231#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK (0x00F0)
232#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK (0x000F)
233/* AAIF control register 16 bit (R/W) */
234#define U300_SYSCON_AAIFCR (0x98)
235#define U300_SYSCON_AAIFCR_MASK (0x0003)
236#define U300_SYSCON_AAIFCR_AASW_CTRL_MASK (0x0003)
237#define U300_SYSCON_AAIFCR_AASW_CTRL_FUNCTIONAL (0x0000)
238#define U300_SYSCON_AAIFCR_AASW_CTRL_MONITORING (0x0001)
239#define U300_SYSCON_AAIFCR_AASW_CTRL_ACC_TO_EXT (0x0002)
240#define U300_SYSCON_AAIFCR_AASW_CTRL_APP_TO_EXT (0x0003)
241/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
242#define U300_SYSCON_MMCR (0x9C)
243#define U300_SYSCON_MMCR_MASK (0x0003)
244#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE (0x0002)
245#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE (0x0001)
246/* Pull up/down control (R/W) */
247#define U300_SYSCON_PUCR (0x104)
248#define U300_SYSCON_PUCR_EMIF_1_WAIT_N_PU_ENABLE (0x0200)
249#define U300_SYSCON_PUCR_EMIF_1_NFIF_READY_PU_ENABLE (0x0100)
250#define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE (0x0080)
251#define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE (0x0040)
252#define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK (0x003F)
253/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
254#define U300_SYSCON_S0CCR (0x120)
255#define U300_SYSCON_S0CCR_FIELD_MASK (0x43FF)
256#define U300_SYSCON_S0CCR_CLOCK_REQ (0x4000)
257#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR (0x2000)
258#define U300_SYSCON_S0CCR_CLOCK_INV (0x0200)
259#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
260#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
261#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
262#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
263#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
264#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
265#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
266#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
267#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
268#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
269#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
270#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
271/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
272#define U300_SYSCON_S1CCR (0x124)
273#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
274#define U300_SYSCON_S1CCR_CLOCK_REQ (0x4000)
275#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR (0x2000)
276#define U300_SYSCON_S1CCR_CLOCK_INV (0x0200)
277#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
278#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
279#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
280#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
281#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
282#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
283#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
284#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
285#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
286#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
287#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
288#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
289/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
290#define U300_SYSCON_S2CCR (0x128)
291#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
292#define U300_SYSCON_S2CCR_CLK_STEAL (0x8000)
293#define U300_SYSCON_S2CCR_CLOCK_REQ (0x4000)
294#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR (0x2000)
295#define U300_SYSCON_S2CCR_CLOCK_INV (0x0200)
296#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
297#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
298#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
299#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
300#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
301#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
302#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
303#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
304#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
305#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
306#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
307#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
308/* SYS_MISC_CONTROL, miscellaneous 16bit (R/W) */
309#define U300_SYSCON_MCR (0x12c)
310#define U300_SYSCON_MCR_FIELD_MASK (0x00FF)
311#define U300_SYSCON_MCR_PMGEN_CR_4_MASK (0x00C0)
312#define U300_SYSCON_MCR_PMGEN_CR_4_GPIO (0x0000)
313#define U300_SYSCON_MCR_PMGEN_CR_4_SPI (0x0040)
314#define U300_SYSCON_MCR_PMGEN_CR_4_AAIF (0x00C0)
315#define U300_SYSCON_MCR_PMGEN_CR_2_MASK (0x0030)
316#define U300_SYSCON_MCR_PMGEN_CR_2_GPIO (0x0000)
317#define U300_SYSCON_MCR_PMGEN_CR_2_EMIF_1_STATIC (0x0010)
318#define U300_SYSCON_MCR_PMGEN_CR_2_DSP (0x0020)
319#define U300_SYSCON_MCR_PMGEN_CR_2_AAIF (0x0030)
320#define U300_SYSCON_MCR_PMGEN_CR_0_MASK (0x000C)
321#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M1 (0x0000)
322#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M2 (0x0004)
323#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_1_SDRAM_M3 (0x0008)
324#define U300_SYSCON_MCR_PMGEN_CR_0_EMIF_0_SDRAM (0x000C)
325#define U300_SYSCON_MCR_PM1G_MODE_ENABLE (0x0002)
326#define U300_SYSCON_MCR_PMTG5_MODE_ENABLE (0x0001)
327/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
328#define U300_SYSCON_PICR (0x0130)
329#define U300_SYSCON_PICR_MASK (0x00FF)
330#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE (0x0080)
331#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE (0x0040)
332#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE (0x0020)
333#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE (0x0010)
334#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE (0x0008)
335#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE (0x0004)
336#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE (0x0002)
337#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE (0x0001)
338/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
339#define U300_SYSCON_PISR (0x0134)
340#define U300_SYSCON_PISR_MASK (0x000F)
341#define U300_SYSCON_PISR_PLL13_UNLOCK_IND (0x0008)
342#define U300_SYSCON_PISR_PLL13_LOCK_IND (0x0004)
343#define U300_SYSCON_PISR_PLL208_UNLOCK_IND (0x0002)
344#define U300_SYSCON_PISR_PLL208_LOCK_IND (0x0001)
345/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
346#define U300_SYSCON_PICLR (0x0138)
347#define U300_SYSCON_PICLR_MASK (0x000F)
348#define U300_SYSCON_PICLR_RWMASK (0x0000)
349#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC (0x0008)
350#define U300_SYSCON_PICLR_PLL13_LOCK_SC (0x0004)
351#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC (0x0002)
352#define U300_SYSCON_PICLR_PLL208_LOCK_SC (0x0001)
353/* CAMIF_CONTROL 16 bit (-/W) */
354#define U300_SYSCON_CICR (0x013C)
355#define U300_SYSCON_CICR_MASK (0x0FFF)
356#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_MASK (0x0F00)
357#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT1 (0x0C00)
358#define U300_SYSCON_CICR_APP_SUBLVDS_TESTMODE_PORT0 (0x0300)
359#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_MASK (0x00F0)
360#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT1 (0x00C0)
361#define U300_SYSCON_CICR_APP_SUBLVDS_RESCON_PORT0 (0x0030)
362#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_MASK (0x000F)
363#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT1 (0x000C)
364#define U300_SYSCON_CICR_APP_SUBLVDS_PWR_DWN_N_PORT0 (0x0003)
365/* Clock activity observability register 0 */
366#define U300_SYSCON_C0OAR (0x140)
367#define U300_SYSCON_C0OAR_MASK (0xFFFF)
368#define U300_SYSCON_C0OAR_VALUE (0xFFFF)
369#define U300_SYSCON_C0OAR_BT_H_CLK (0x8000)
370#define U300_SYSCON_C0OAR_ASPB_P_CLK (0x4000)
371#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK (0x2000)
372#define U300_SYSCON_C0OAR_APP_SEMI_CLK (0x1000)
373#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK (0x0800)
374#define U300_SYSCON_C0OAR_APP_I2S1_CLK (0x0400)
375#define U300_SYSCON_C0OAR_APP_I2S0_CLK (0x0200)
376#define U300_SYSCON_C0OAR_APP_CPU_CLK (0x0100)
377#define U300_SYSCON_C0OAR_APP_52_CLK (0x0080)
378#define U300_SYSCON_C0OAR_APP_208_CLK (0x0040)
379#define U300_SYSCON_C0OAR_APP_104_CLK (0x0020)
380#define U300_SYSCON_C0OAR_APEX_CLK (0x0010)
381#define U300_SYSCON_C0OAR_AHPB_M_H_CLK (0x0008)
382#define U300_SYSCON_C0OAR_AHB_CLK (0x0004)
383#define U300_SYSCON_C0OAR_AFPB_P_CLK (0x0002)
384#define U300_SYSCON_C0OAR_AAIF_CLK (0x0001)
385/* Clock activity observability register 1 */
386#define U300_SYSCON_C1OAR (0x144)
387#define U300_SYSCON_C1OAR_MASK (0x3FFE)
388#define U300_SYSCON_C1OAR_VALUE (0x3FFE)
389#define U300_SYSCON_C1OAR_NFIF_F_CLK (0x2000)
390#define U300_SYSCON_C1OAR_MSPRO_CLK (0x1000)
391#define U300_SYSCON_C1OAR_MMC_P_CLK (0x0800)
392#define U300_SYSCON_C1OAR_MMC_CLK (0x0400)
393#define U300_SYSCON_C1OAR_KP_P_CLK (0x0200)
394#define U300_SYSCON_C1OAR_I2C1_P_CLK (0x0100)
395#define U300_SYSCON_C1OAR_I2C0_P_CLK (0x0080)
396#define U300_SYSCON_C1OAR_GPIO_CLK (0x0040)
397#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK (0x0020)
398#define U300_SYSCON_C1OAR_EMIF_H_CLK (0x0010)
399#define U300_SYSCON_C1OAR_EVHIST_CLK (0x0008)
400#define U300_SYSCON_C1OAR_PPM_CLK (0x0004)
401#define U300_SYSCON_C1OAR_DMA_CLK (0x0002)
402/* Clock activity observability register 2 */
403#define U300_SYSCON_C2OAR (0x148)
404#define U300_SYSCON_C2OAR_MASK (0x0FFF)
405#define U300_SYSCON_C2OAR_VALUE (0x0FFF)
406#define U300_SYSCON_C2OAR_XGAM_CDI_CLK (0x0800)
407#define U300_SYSCON_C2OAR_XGAM_CLK (0x0400)
408#define U300_SYSCON_C2OAR_VC_H_CLK (0x0200)
409#define U300_SYSCON_C2OAR_VC_CLK (0x0100)
410#define U300_SYSCON_C2OAR_UA_P_CLK (0x0080)
411#define U300_SYSCON_C2OAR_TMR1_CLK (0x0040)
412#define U300_SYSCON_C2OAR_TMR0_CLK (0x0020)
413#define U300_SYSCON_C2OAR_SPI_P_CLK (0x0010)
414#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK (0x0008)
415#define U300_SYSCON_C2OAR_PCM_I2S1_CLK (0x0004)
416#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK (0x0002)
417#define U300_SYSCON_C2OAR_PCM_I2S0_CLK (0x0001)
418
419/* Chip ID register 16bit (R/-) */
420#define U300_SYSCON_CIDR (0x400)
421/* Video IRQ clear 16bit (R/W) */
422#define U300_SYSCON_VICR (0x404)
423#define U300_SYSCON_VICR_VIDEO1_IRQ_CLEAR_ENABLE (0x0002)
424#define U300_SYSCON_VICR_VIDEO0_IRQ_CLEAR_ENABLE (0x0001)
425/* SMCR */
426#define U300_SYSCON_SMCR (0x4d0)
427#define U300_SYSCON_SMCR_FIELD_MASK (0x000e)
428#define U300_SYSCON_SMCR_SEMI_SREFACK_IND (0x0008)
429#define U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE (0x0004)
430#define U300_SYSCON_SMCR_SEMI_EXT_BOOT_MODE_ENABLE (0x0002)
431/* CPU_SW_DBGEN Software Debug Enable 16bit (R/W) */
432#define U300_SYSCON_CSDR (0x4f0)
433#define U300_SYSCON_CSDR_SW_DEBUG_ENABLE (0x0001)
434/* PRINT_CONTROL Print Control 16bit (R/-) */
435#define U300_SYSCON_PCR (0x4f8)
436#define U300_SYSCON_PCR_SERV_IND (0x0001)
437/* BOOT_CONTROL 16bit (R/-) */
438#define U300_SYSCON_BCR (0x4fc)
439#define U300_SYSCON_BCR_ACC_CPU_SUBSYS_VINITHI_IND (0x0400)
440#define U300_SYSCON_BCR_APP_CPU_SUBSYS_VINITHI_IND (0x0200)
441#define U300_SYSCON_BCR_EXTRA_BOOT_OPTION_MASK (0x01FC)
442#define U300_SYSCON_BCR_APP_BOOT_SERV_MASK (0x0003)
443
444
445/* CPU clock defines */
446/**
447 * CPU high frequency in MHz
448 */
449#define SYSCON_CPU_CLOCK_HIGH 208
450/**
451 * CPU medium frequency in MHz
452 */
453#define SYSCON_CPU_CLOCK_MEDIUM 52
454/**
455 * CPU low frequency in MHz
456 */
457#define SYSCON_CPU_CLOCK_LOW 13
458
459/* EMIF clock defines */
460/**
461 * EMIF high frequency in MHz
462 */
463#define SYSCON_EMIF_CLOCK_HIGH 104
464/**
465 * EMIF medium frequency in MHz
466 */
467#define SYSCON_EMIF_CLOCK_MEDIUM 52
468/**
469 * EMIF low frequency in MHz
470 */
471#define SYSCON_EMIF_CLOCK_LOW 13
472
473/* AHB clock defines */
474/**
475 * AHB high frequency in MHz
476 */
477#define SYSCON_AHB_CLOCK_HIGH 52
478/**
479 * AHB medium frequency in MHz
480 */
481#define SYSCON_AHB_CLOCK_MEDIUM 26
482/**
483 * AHB low frequency in MHz
484 */
485#define SYSCON_AHB_CLOCK_LOW 7 /* i.e 13/2=6.5MHz */
486
487enum syscon_busmaster {
488 SYSCON_BM_DMAC,
489 SYSCON_BM_XGAM,
490 SYSCON_BM_VIDEO_ENC
491};
492
493/* Selectr a resistor or a set of resistors */
494enum syscon_pull_up_down {
495 SYSCON_PU_KEY_IN_EN,
496 SYSCON_PU_EMIF_1_8_BIT_EN,
497 SYSCON_PU_EMIF_1_16_BIT_EN,
498 SYSCON_PU_EMIF_1_NFIF_READY_EN,
499 SYSCON_PU_EMIF_1_NFIF_WAIT_N_EN,
500};
501
502/*
503 * Note that this array must match the order of the array "clk_reg"
504 * in syscon.c
505 */
506enum syscon_clk {
507 SYSCON_CLKCONTROL_SLOW_BRIDGE,
508 SYSCON_CLKCONTROL_UART,
509 SYSCON_CLKCONTROL_BTR,
510 SYSCON_CLKCONTROL_EH,
511 SYSCON_CLKCONTROL_GPIO,
512 SYSCON_CLKCONTROL_KEYPAD,
513 SYSCON_CLKCONTROL_APP_TIMER,
514 SYSCON_CLKCONTROL_ACC_TIMER,
515 SYSCON_CLKCONTROL_FAST_BRIDGE,
516 SYSCON_CLKCONTROL_I2C0,
517 SYSCON_CLKCONTROL_I2C1,
518 SYSCON_CLKCONTROL_I2S0,
519 SYSCON_CLKCONTROL_I2S1,
520 SYSCON_CLKCONTROL_MMC,
521 SYSCON_CLKCONTROL_SPI,
522 SYSCON_CLKCONTROL_I2S0_CORE,
523 SYSCON_CLKCONTROL_I2S1_CORE,
524 SYSCON_CLKCONTROL_UART1,
525 SYSCON_CLKCONTROL_AAIF,
526 SYSCON_CLKCONTROL_AHB,
527 SYSCON_CLKCONTROL_APEX,
528 SYSCON_CLKCONTROL_CPU,
529 SYSCON_CLKCONTROL_DMA,
530 SYSCON_CLKCONTROL_EMIF,
531 SYSCON_CLKCONTROL_NAND_IF,
532 SYSCON_CLKCONTROL_VIDEO_ENC,
533 SYSCON_CLKCONTROL_XGAM,
534 SYSCON_CLKCONTROL_SEMI,
535 SYSCON_CLKCONTROL_AHB_SUBSYS,
536 SYSCON_CLKCONTROL_MSPRO
537};
538
539enum syscon_sysclk_mode {
540 SYSCON_SYSCLK_DISABLED,
541 SYSCON_SYSCLK_M_CLK,
542 SYSCON_SYSCLK_ACC_FSM,
543 SYSCON_SYSCLK_PLL60_48,
544 SYSCON_SYSCLK_PLL60_60,
545 SYSCON_SYSCLK_ACC_PLL208,
546 SYSCON_SYSCLK_APP_PLL13,
547 SYSCON_SYSCLK_APP_FSM,
548 SYSCON_SYSCLK_RTC,
549 SYSCON_SYSCLK_APP_PLL208
550};
551
552enum syscon_sysclk_req {
553 SYSCON_SYSCLKREQ_DISABLED,
554 SYSCON_SYSCLKREQ_ACTIVE_LOW,
555 SYSCON_SYSCLKREQ_MONITOR
556};
557
558enum syscon_clk_mode {
559 SYSCON_CLKMODE_OFF,
560 SYSCON_CLKMODE_DEFAULT,
561 SYSCON_CLKMODE_LOW,
562 SYSCON_CLKMODE_MEDIUM,
563 SYSCON_CLKMODE_HIGH,
564 SYSCON_CLKMODE_PERMANENT,
565 SYSCON_CLKMODE_ON,
566};
567
568enum syscon_call_mode {
569 SYSCON_CLKCALL_NOWAIT,
570 SYSCON_CLKCALL_WAIT,
571};
572
573int syscon_dc_on(bool keep_power_on);
574int syscon_set_busmaster_active_state(enum syscon_busmaster busmaster,
575 bool active);
576bool syscon_get_busmaster_active_state(void);
577int syscon_set_sleep_mask(enum syscon_clk,
578 bool sleep_ctrl);
579int syscon_config_sysclk(u32 sysclk,
580 enum syscon_sysclk_mode sysclkmode,
581 bool inverse,
582 u32 divisor,
583 enum syscon_sysclk_req sysclkreq);
584bool syscon_can_turn_off_semi_clock(void);
585
586/* This function is restricted to core.c */
587int syscon_request_normal_power(bool req);
588
589/* This function is restricted to be used by platform_speed.c */
590int syscon_speed_request(enum syscon_call_mode wait_mode,
591 enum syscon_clk_mode req_clk_mode);
592#endif /* __MACH_SYSCON_H */
diff --git a/arch/arm/mach-u300/include/mach/timex.h b/arch/arm/mach-u300/include/mach/timex.h
deleted file mode 100644
index f233b72633f6..000000000000
--- a/arch/arm/mach-u300/include/mach/timex.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/timex.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Platform tick rate definition.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 */
11#ifndef __MACH_TIMEX_H
12#define __MACH_TIMEX_H
13
14/* This is for the APP OS GP1 (General Purpose 1) timer */
15#define CLOCK_TICK_RATE 1000000
16
17#endif
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
deleted file mode 100644
index 0320495efc4d..000000000000
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ /dev/null
@@ -1,165 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/include/mach/u300-regs.h
4 *
5 *
6 * Copyright (C) 2006-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Basic register address definitions in physical memory and
9 * some block definitions for core devices like the timer.
10 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 */
12
13#ifndef __MACH_U300_REGS_H
14#define __MACH_U300_REGS_H
15
16/*
17 * These are the large blocks of memory allocated for I/O.
18 * the defines are used for setting up the I/O memory mapping.
19 */
20
21/* NAND Flash CS0 */
22#define U300_NAND_CS0_PHYS_BASE 0x80000000
23
24/* NFIF */
25#define U300_NAND_IF_PHYS_BASE 0x9f800000
26
27/* ALE, CLE offset for FSMC NAND */
28#define PLAT_NAND_CLE (1 << 16)
29#define PLAT_NAND_ALE (1 << 17)
30
31/* AHB Peripherals */
32#define U300_AHB_PER_PHYS_BASE 0xa0000000
33#define U300_AHB_PER_VIRT_BASE 0xff010000
34
35/* FAST Peripherals */
36#define U300_FAST_PER_PHYS_BASE 0xc0000000
37#define U300_FAST_PER_VIRT_BASE 0xff020000
38
39/* SLOW Peripherals */
40#define U300_SLOW_PER_PHYS_BASE 0xc0010000
41#define U300_SLOW_PER_VIRT_BASE 0xff000000
42
43/* Boot ROM */
44#define U300_BOOTROM_PHYS_BASE 0xffff0000
45#define U300_BOOTROM_VIRT_BASE 0xffff0000
46
47/* SEMI config base */
48#define U300_SEMI_CONFIG_BASE 0x2FFE0000
49
50/*
51 * AHB peripherals
52 */
53
54/* AHB Peripherals Bridge Controller */
55#define U300_AHB_BRIDGE_BASE (U300_AHB_PER_PHYS_BASE+0x0000)
56
57/* Vectored Interrupt Controller 0, servicing 32 interrupts */
58#define U300_INTCON0_BASE (U300_AHB_PER_PHYS_BASE+0x1000)
59#define U300_INTCON0_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x1000)
60
61/* Vectored Interrupt Controller 1, servicing 32 interrupts */
62#define U300_INTCON1_BASE (U300_AHB_PER_PHYS_BASE+0x2000)
63#define U300_INTCON1_VBASE IOMEM(U300_AHB_PER_VIRT_BASE+0x2000)
64
65/* Memory Stick Pro (MSPRO) controller */
66#define U300_MSPRO_BASE (U300_AHB_PER_PHYS_BASE+0x3000)
67
68/* EMIF Configuration Area */
69#define U300_EMIF_CFG_BASE (U300_AHB_PER_PHYS_BASE+0x4000)
70
71
72/*
73 * FAST peripherals
74 */
75
76/* FAST bridge control */
77#define U300_FAST_BRIDGE_BASE (U300_FAST_PER_PHYS_BASE+0x0000)
78
79/* MMC/SD controller */
80#define U300_MMCSD_BASE (U300_FAST_PER_PHYS_BASE+0x1000)
81
82/* PCM I2S0 controller */
83#define U300_PCM_I2S0_BASE (U300_FAST_PER_PHYS_BASE+0x2000)
84
85/* PCM I2S1 controller */
86#define U300_PCM_I2S1_BASE (U300_FAST_PER_PHYS_BASE+0x3000)
87
88/* I2C0 controller */
89#define U300_I2C0_BASE (U300_FAST_PER_PHYS_BASE+0x4000)
90
91/* I2C1 controller */
92#define U300_I2C1_BASE (U300_FAST_PER_PHYS_BASE+0x5000)
93
94/* SPI controller */
95#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
96
97/* Fast UART1 on U335 only */
98#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
99
100/*
101 * SLOW peripherals
102 */
103
104/* SLOW bridge control */
105#define U300_SLOW_BRIDGE_BASE (U300_SLOW_PER_PHYS_BASE)
106
107/* SYSCON */
108#define U300_SYSCON_BASE (U300_SLOW_PER_PHYS_BASE+0x1000)
109#define U300_SYSCON_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x1000)
110
111/* Watchdog */
112#define U300_WDOG_BASE (U300_SLOW_PER_PHYS_BASE+0x2000)
113
114/* UART0 */
115#define U300_UART0_BASE (U300_SLOW_PER_PHYS_BASE+0x3000)
116
117/* APP side special timer */
118#define U300_TIMER_APP_BASE (U300_SLOW_PER_PHYS_BASE+0x4000)
119#define U300_TIMER_APP_VBASE IOMEM(U300_SLOW_PER_VIRT_BASE+0x4000)
120
121/* Keypad */
122#define U300_KEYPAD_BASE (U300_SLOW_PER_PHYS_BASE+0x5000)
123
124/* GPIO */
125#define U300_GPIO_BASE (U300_SLOW_PER_PHYS_BASE+0x6000)
126
127/* RTC */
128#define U300_RTC_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
129
130/* Bus tracer */
131#define U300_BUSTR_BASE (U300_SLOW_PER_PHYS_BASE+0x8000)
132
133/* Event handler (hardware queue) */
134#define U300_EVHIST_BASE (U300_SLOW_PER_PHYS_BASE+0x9000)
135
136/* Genric Timer */
137#define U300_TIMER_BASE (U300_SLOW_PER_PHYS_BASE+0xa000)
138
139/* PPM */
140#define U300_PPM_BASE (U300_SLOW_PER_PHYS_BASE+0xb000)
141
142
143/*
144 * REST peripherals
145 */
146
147/* ISP (image signal processor) */
148#define U300_ISP_BASE (0xA0008000)
149
150/* DMA Controller base */
151#define U300_DMAC_BASE (0xC0020000)
152
153/* MSL Base */
154#define U300_MSL_BASE (0xc0022000)
155
156/* APEX Base */
157#define U300_APEX_BASE (0xc0030000)
158
159/* Video Encoder Base */
160#define U300_VIDEOENC_BASE (0xc0080000)
161
162/* XGAM Base */
163#define U300_XGAM_BASE (0xd0000000)
164
165#endif
diff --git a/arch/arm/mach-u300/include/mach/uncompress.h b/arch/arm/mach-u300/include/mach/uncompress.h
deleted file mode 100644
index 783e7e60101b..000000000000
--- a/arch/arm/mach-u300/include/mach/uncompress.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * arch/arm/mach-u300/include/mach/uncompress.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#define AMBA_UART_DR (*(volatile unsigned char *)0xc0013000)
21#define AMBA_UART_LCRH (*(volatile unsigned char *)0xc001302C)
22#define AMBA_UART_CR (*(volatile unsigned char *)0xc0013030)
23#define AMBA_UART_FR (*(volatile unsigned char *)0xc0013018)
24
25/*
26 * This does not append a newline
27 */
28static inline void putc(int c)
29{
30 while (AMBA_UART_FR & (1 << 5))
31 barrier();
32
33 AMBA_UART_DR = c;
34}
35
36static inline void flush(void)
37{
38 while (AMBA_UART_FR & (1 << 3))
39 barrier();
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_setup()
diff --git a/arch/arm/mach-u300/regulator.c b/arch/arm/mach-u300/regulator.c
index 9c53f01c62eb..bf40cd478fe9 100644
--- a/arch/arm/mach-u300/regulator.c
+++ b/arch/arm/mach-u300/regulator.c
@@ -10,11 +10,18 @@
10#include <linux/device.h> 10#include <linux/device.h>
11#include <linux/signal.h> 11#include <linux/signal.h>
12#include <linux/err.h> 12#include <linux/err.h>
13#include <linux/of.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/machine.h>
13#include <linux/regulator/consumer.h> 17#include <linux/regulator/consumer.h>
14/* Those are just for writing in syscon */ 18#include <linux/mfd/syscon.h>
15#include <linux/io.h> 19#include <linux/regmap.h>
16#include <mach/hardware.h> 20
17#include <mach/syscon.h> 21/* Power Management Control 16bit (R/W) */
22#define U300_SYSCON_PMCR (0x50)
23#define U300_SYSCON_PMCR_DCON_ENABLE (0x0002)
24#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE (0x0001)
18 25
19/* 26/*
20 * Regulators that power the board and chip and which are 27 * Regulators that power the board and chip and which are
@@ -47,13 +54,28 @@ void u300_pm_poweroff(void)
47/* 54/*
48 * Hog the regulators needed to power up the board. 55 * Hog the regulators needed to power up the board.
49 */ 56 */
50static int __init u300_init_boardpower(void) 57static int __init __u300_init_boardpower(struct platform_device *pdev)
51{ 58{
59 struct device_node *np = pdev->dev.of_node;
60 struct device_node *syscon_np;
61 struct regmap *regmap;
52 int err; 62 int err;
53 u32 val;
54 63
55 pr_info("U300: setting up board power\n"); 64 pr_info("U300: setting up board power\n");
56 main_power_15 = regulator_get(NULL, "vana15"); 65
66 syscon_np = of_parse_phandle(np, "syscon", 0);
67 if (!syscon_np) {
68 pr_crit("U300: no syscon node\n");
69 return -ENODEV;
70 }
71 regmap = syscon_node_to_regmap(syscon_np);
72 if (!regmap) {
73 pr_crit("U300: could not locate syscon regmap\n");
74 return -ENODEV;
75 }
76
77 main_power_15 = regulator_get(&pdev->dev, "vana15");
78
57 if (IS_ERR(main_power_15)) { 79 if (IS_ERR(main_power_15)) {
58 pr_err("could not get vana15"); 80 pr_err("could not get vana15");
59 return PTR_ERR(main_power_15); 81 return PTR_ERR(main_power_15);
@@ -72,9 +94,8 @@ static int __init u300_init_boardpower(void)
72 * the rest of the U300 power management is implemented. 94 * the rest of the U300 power management is implemented.
73 */ 95 */
74 pr_info("U300: disable system controller pull-up\n"); 96 pr_info("U300: disable system controller pull-up\n");
75 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR); 97 regmap_update_bits(regmap, U300_SYSCON_PMCR,
76 val &= ~U300_SYSCON_PMCR_DCON_ENABLE; 98 U300_SYSCON_PMCR_DCON_ENABLE, 0);
77 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
78 99
79 /* Register globally exported PM poweroff hook */ 100 /* Register globally exported PM poweroff hook */
80 pm_power_off = u300_pm_poweroff; 101 pm_power_off = u300_pm_poweroff;
@@ -82,7 +103,31 @@ static int __init u300_init_boardpower(void)
82 return 0; 103 return 0;
83} 104}
84 105
106static int __init s365_board_probe(struct platform_device *pdev)
107{
108 return __u300_init_boardpower(pdev);
109}
110
111static const struct of_device_id s365_board_match[] = {
112 { .compatible = "stericsson,s365" },
113 {},
114};
115
116static struct platform_driver s365_board_driver = {
117 .driver = {
118 .name = "s365-board",
119 .owner = THIS_MODULE,
120 .of_match_table = s365_board_match,
121 },
122};
123
85/* 124/*
86 * So at module init time we hog the regulator! 125 * So at module init time we hog the regulator!
87 */ 126 */
88module_init(u300_init_boardpower); 127static int __init u300_init_boardpower(void)
128{
129 return platform_driver_probe(&s365_board_driver,
130 s365_board_probe);
131}
132
133device_initcall(u300_init_boardpower);
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
deleted file mode 100644
index 910698293d64..000000000000
--- a/arch/arm/mach-u300/spi.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * arch/arm/mach-u300/spi.c
3 *
4 * Copyright (C) 2009 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 */
9#include <linux/device.h>
10#include <linux/amba/bus.h>
11#include <linux/spi/spi.h>
12#include <linux/amba/pl022.h>
13#include <linux/platform_data/dma-coh901318.h>
14#include <linux/err.h>
15
16/*
17 * The following is for the actual devices on the SSP/SPI bus
18 */
19#ifdef CONFIG_MACH_U300_SPIDUMMY
20static void select_dummy_chip(u32 chipselect)
21{
22 pr_debug("CORE: %s called with CS=0x%x (%s)\n",
23 __func__,
24 chipselect,
25 chipselect ? "unselect chip" : "select chip");
26 /*
27 * Here you would write the chip select value to the GPIO pins if
28 * this was a real chip (but this is a loopback dummy).
29 */
30}
31
32struct pl022_config_chip dummy_chip_info = {
33 /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
34 .com_mode = DMA_TRANSFER,
35 .iface = SSP_INTERFACE_MOTOROLA_SPI,
36 /* We can only act as master but SSP_SLAVE is possible in theory */
37 .hierarchy = SSP_MASTER,
38 /* 0 = drive TX even as slave, 1 = do not drive TX as slave */
39 .slave_tx_disable = 0,
40 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
41 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
42 .ctrl_len = SSP_BITS_12,
43 .wait_state = SSP_MWIRE_WAIT_ZERO,
44 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
45 /*
46 * This is where you insert a call to a function to enable CS
47 * (usually GPIO) for a certain chip.
48 */
49 .cs_control = select_dummy_chip,
50};
51#endif
52
53static struct spi_board_info u300_spi_devices[] = {
54#ifdef CONFIG_MACH_U300_SPIDUMMY
55 {
56 /* A dummy chip used for loopback tests */
57 .modalias = "spi-dummy",
58 /* Really dummy, pass in additional chip config here */
59 .platform_data = NULL,
60 /* This defines how the controller shall handle the device */
61 .controller_data = &dummy_chip_info,
62 /* .irq - no external IRQ routed from this device */
63 .max_speed_hz = 1000000,
64 .bus_num = 0, /* Only one bus on this chip */
65 .chip_select = 0,
66 /* Means SPI_CS_HIGH, change if e.g low CS */
67 .mode = SPI_MODE_1 | SPI_LOOP,
68 },
69#endif
70};
71
72static struct pl022_ssp_controller ssp_platform_data = {
73 /* If you have several SPI buses this varies, we have only bus 0 */
74 .bus_id = 0,
75 /*
76 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
77 * chip selects for SPI. (Same on U330, U335 and U365.)
78 * TODO: make sure the GPIO driver can select these properly
79 * and do padmuxing accordingly too.
80 */
81 .num_chipselect = 3,
82#ifdef CONFIG_COH901318
83 .enable_dma = 1,
84 .dma_filter = coh901318_filter_id,
85 .dma_rx_param = (void *) U300_DMA_SPI_RX,
86 .dma_tx_param = (void *) U300_DMA_SPI_TX,
87#else
88 .enable_dma = 0,
89#endif
90};
91
92
93void __init u300_spi_init(struct amba_device *adev)
94{
95 adev->dev.platform_data = &ssp_platform_data;
96}
97
98void __init u300_spi_register_board_devices(void)
99{
100 /* Register any SPI devices */
101 spi_register_board_info(u300_spi_devices, ARRAY_SIZE(u300_spi_devices));
102}
diff --git a/arch/arm/mach-u300/spi.h b/arch/arm/mach-u300/spi.h
deleted file mode 100644
index bd3d867e240f..000000000000
--- a/arch/arm/mach-u300/spi.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * arch/arm/mach-u300/spi.h
3 *
4 * Copyright (C) 2009 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 */
9#ifndef SPI_H
10#define SPI_H
11#include <linux/amba/bus.h>
12
13#ifdef CONFIG_SPI_PL022
14void __init u300_spi_init(struct amba_device *adev);
15void __init u300_spi_register_board_devices(void);
16#else
17/* Compile out SPI support if PL022 is not selected */
18static inline void __init u300_spi_init(struct amba_device *adev)
19{
20}
21static inline void __init u300_spi_register_board_devices(void)
22{
23}
24#endif
25
26#endif
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index d9e73209c9b8..390ae5feb1d0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -18,17 +18,15 @@
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21 21#include <linux/delay.h>
22#include <mach/hardware.h> 22#include <linux/of_address.h>
23#include <mach/irqs.h> 23#include <linux/of_irq.h>
24 24
25/* Generic stuff */ 25/* Generic stuff */
26#include <asm/sched_clock.h> 26#include <asm/sched_clock.h>
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <asm/mach/time.h> 28#include <asm/mach/time.h>
29 29
30#include "timer.h"
31
32/* 30/*
33 * APP side special timer registers 31 * APP side special timer registers
34 * This timer contains four timers which can fire an interrupt each. 32 * This timer contains four timers which can fire an interrupt each.
@@ -189,6 +187,8 @@
189#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) 187#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
190#define US_PER_TICK ((1000000 + (HZ/2)) / HZ) 188#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
191 189
190static void __iomem *u300_timer_base;
191
192/* 192/*
193 * The u300_set_mode() function is always called first, if we 193 * The u300_set_mode() function is always called first, if we
194 * have oneshot timer active, the oneshot scheduling function 194 * have oneshot timer active, the oneshot scheduling function
@@ -201,28 +201,28 @@ static void u300_set_mode(enum clock_event_mode mode,
201 case CLOCK_EVT_MODE_PERIODIC: 201 case CLOCK_EVT_MODE_PERIODIC:
202 /* Disable interrupts on GPT1 */ 202 /* Disable interrupts on GPT1 */
203 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 203 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
204 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 204 u300_timer_base + U300_TIMER_APP_GPT1IE);
205 /* Disable GP1 while we're reprogramming it. */ 205 /* Disable GP1 while we're reprogramming it. */
206 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 206 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
207 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 207 u300_timer_base + U300_TIMER_APP_DGPT1);
208 /* 208 /*
209 * Set the periodic mode to a certain number of ticks per 209 * Set the periodic mode to a certain number of ticks per
210 * jiffy. 210 * jiffy.
211 */ 211 */
212 writel(TICKS_PER_JIFFY, 212 writel(TICKS_PER_JIFFY,
213 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); 213 u300_timer_base + U300_TIMER_APP_GPT1TC);
214 /* 214 /*
215 * Set continuous mode, so the timer keeps triggering 215 * Set continuous mode, so the timer keeps triggering
216 * interrupts. 216 * interrupts.
217 */ 217 */
218 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, 218 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
219 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); 219 u300_timer_base + U300_TIMER_APP_SGPT1M);
220 /* Enable timer interrupts */ 220 /* Enable timer interrupts */
221 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 221 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
222 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 222 u300_timer_base + U300_TIMER_APP_GPT1IE);
223 /* Then enable the OS timer again */ 223 /* Then enable the OS timer again */
224 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 224 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
225 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); 225 u300_timer_base + U300_TIMER_APP_EGPT1);
226 break; 226 break;
227 case CLOCK_EVT_MODE_ONESHOT: 227 case CLOCK_EVT_MODE_ONESHOT:
228 /* Just break; here? */ 228 /* Just break; here? */
@@ -233,33 +233,33 @@ static void u300_set_mode(enum clock_event_mode mode,
233 */ 233 */
234 /* Disable interrupts on GPT1 */ 234 /* Disable interrupts on GPT1 */
235 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 235 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
236 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 236 u300_timer_base + U300_TIMER_APP_GPT1IE);
237 /* Disable GP1 while we're reprogramming it. */ 237 /* Disable GP1 while we're reprogramming it. */
238 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 238 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
239 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 239 u300_timer_base + U300_TIMER_APP_DGPT1);
240 /* 240 /*
241 * Expire far in the future, u300_set_next_event() will be 241 * Expire far in the future, u300_set_next_event() will be
242 * called soon... 242 * called soon...
243 */ 243 */
244 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); 244 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
245 /* We run one shot per tick here! */ 245 /* We run one shot per tick here! */
246 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, 246 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
247 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); 247 u300_timer_base + U300_TIMER_APP_SGPT1M);
248 /* Enable interrupts for this timer */ 248 /* Enable interrupts for this timer */
249 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 249 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
250 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 250 u300_timer_base + U300_TIMER_APP_GPT1IE);
251 /* Enable timer */ 251 /* Enable timer */
252 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 252 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
253 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); 253 u300_timer_base + U300_TIMER_APP_EGPT1);
254 break; 254 break;
255 case CLOCK_EVT_MODE_UNUSED: 255 case CLOCK_EVT_MODE_UNUSED:
256 case CLOCK_EVT_MODE_SHUTDOWN: 256 case CLOCK_EVT_MODE_SHUTDOWN:
257 /* Disable interrupts on GP1 */ 257 /* Disable interrupts on GP1 */
258 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 258 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
259 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 259 u300_timer_base + U300_TIMER_APP_GPT1IE);
260 /* Disable GP1 */ 260 /* Disable GP1 */
261 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 261 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
262 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 262 u300_timer_base + U300_TIMER_APP_DGPT1);
263 break; 263 break;
264 case CLOCK_EVT_MODE_RESUME: 264 case CLOCK_EVT_MODE_RESUME:
265 /* Ignore this call */ 265 /* Ignore this call */
@@ -281,27 +281,27 @@ static int u300_set_next_event(unsigned long cycles,
281{ 281{
282 /* Disable interrupts on GPT1 */ 282 /* Disable interrupts on GPT1 */
283 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, 283 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
284 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 284 u300_timer_base + U300_TIMER_APP_GPT1IE);
285 /* Disable GP1 while we're reprogramming it. */ 285 /* Disable GP1 while we're reprogramming it. */
286 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, 286 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
287 U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1); 287 u300_timer_base + U300_TIMER_APP_DGPT1);
288 /* Reset the General Purpose timer 1. */ 288 /* Reset the General Purpose timer 1. */
289 writel(U300_TIMER_APP_RGPT1_TIMER_RESET, 289 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
290 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); 290 u300_timer_base + U300_TIMER_APP_RGPT1);
291 /* IRQ in n * cycles */ 291 /* IRQ in n * cycles */
292 writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC); 292 writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
293 /* 293 /*
294 * We run one shot per tick here! (This is necessary to reconfigure, 294 * We run one shot per tick here! (This is necessary to reconfigure,
295 * the timer will tilt if you don't!) 295 * the timer will tilt if you don't!)
296 */ 296 */
297 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, 297 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
298 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M); 298 u300_timer_base + U300_TIMER_APP_SGPT1M);
299 /* Enable timer interrupts */ 299 /* Enable timer interrupts */
300 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, 300 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
301 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE); 301 u300_timer_base + U300_TIMER_APP_GPT1IE);
302 /* Then enable the OS timer again */ 302 /* Then enable the OS timer again */
303 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, 303 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
304 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1); 304 u300_timer_base + U300_TIMER_APP_EGPT1);
305 return 0; 305 return 0;
306} 306}
307 307
@@ -320,8 +320,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
320{ 320{
321 struct clock_event_device *evt = &clockevent_u300_1mhz; 321 struct clock_event_device *evt = &clockevent_u300_1mhz;
322 /* ACK/Clear timer IRQ for the APP GPT1 Timer */ 322 /* ACK/Clear timer IRQ for the APP GPT1 Timer */
323
323 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, 324 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
324 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA); 325 u300_timer_base + U300_TIMER_APP_GPT1IA);
325 evt->event_handler(evt); 326 evt->event_handler(evt);
326 return IRQ_HANDLED; 327 return IRQ_HANDLED;
327} 328}
@@ -342,65 +343,88 @@ static struct irqaction u300_timer_irq = {
342 343
343static u32 notrace u300_read_sched_clock(void) 344static u32 notrace u300_read_sched_clock(void)
344{ 345{
345 return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC); 346 return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
347}
348
349static unsigned long u300_read_current_timer(void)
350{
351 return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
346} 352}
347 353
354static struct delay_timer u300_delay_timer;
348 355
349/* 356/*
350 * This sets up the system timers, clock source and clock event. 357 * This sets up the system timers, clock source and clock event.
351 */ 358 */
352void __init u300_timer_init(void) 359static void __init u300_timer_init_of(struct device_node *np)
353{ 360{
361 struct resource irq_res;
362 int irq;
354 struct clk *clk; 363 struct clk *clk;
355 unsigned long rate; 364 unsigned long rate;
356 365
366 u300_timer_base = of_iomap(np, 0);
367 if (!u300_timer_base)
368 panic("could not ioremap system timer\n");
369
370 /* Get the IRQ for the GP1 timer */
371 irq = of_irq_to_resource(np, 2, &irq_res);
372 if (irq <= 0)
373 panic("no IRQ for system timer\n");
374
375 pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
376
357 /* Clock the interrupt controller */ 377 /* Clock the interrupt controller */
358 clk = clk_get_sys("apptimer", NULL); 378 clk = of_clk_get(np, 0);
359 BUG_ON(IS_ERR(clk)); 379 BUG_ON(IS_ERR(clk));
360 clk_prepare_enable(clk); 380 clk_prepare_enable(clk);
361 rate = clk_get_rate(clk); 381 rate = clk_get_rate(clk);
362 382
363 setup_sched_clock(u300_read_sched_clock, 32, rate); 383 setup_sched_clock(u300_read_sched_clock, 32, rate);
364 384
385 u300_delay_timer.read_current_timer = &u300_read_current_timer;
386 u300_delay_timer.freq = rate;
387 register_current_timer_delay(&u300_delay_timer);
388
365 /* 389 /*
366 * Disable the "OS" and "DD" timers - these are designed for Symbian! 390 * Disable the "OS" and "DD" timers - these are designed for Symbian!
367 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c 391 * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
368 */ 392 */
369 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, 393 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
370 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC); 394 u300_timer_base + U300_TIMER_APP_CRC);
371 writel(U300_TIMER_APP_ROST_TIMER_RESET, 395 writel(U300_TIMER_APP_ROST_TIMER_RESET,
372 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST); 396 u300_timer_base + U300_TIMER_APP_ROST);
373 writel(U300_TIMER_APP_DOST_TIMER_DISABLE, 397 writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
374 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST); 398 u300_timer_base + U300_TIMER_APP_DOST);
375 writel(U300_TIMER_APP_RDDT_TIMER_RESET, 399 writel(U300_TIMER_APP_RDDT_TIMER_RESET,
376 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT); 400 u300_timer_base + U300_TIMER_APP_RDDT);
377 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, 401 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
378 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT); 402 u300_timer_base + U300_TIMER_APP_DDDT);
379 403
380 /* Reset the General Purpose timer 1. */ 404 /* Reset the General Purpose timer 1. */
381 writel(U300_TIMER_APP_RGPT1_TIMER_RESET, 405 writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
382 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1); 406 u300_timer_base + U300_TIMER_APP_RGPT1);
383 407
384 /* Set up the IRQ handler */ 408 /* Set up the IRQ handler */
385 setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq); 409 setup_irq(irq, &u300_timer_irq);
386 410
387 /* Reset the General Purpose timer 2 */ 411 /* Reset the General Purpose timer 2 */
388 writel(U300_TIMER_APP_RGPT2_TIMER_RESET, 412 writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
389 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2); 413 u300_timer_base + U300_TIMER_APP_RGPT2);
390 /* Set this timer to run around forever */ 414 /* Set this timer to run around forever */
391 writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC); 415 writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
392 /* Set continuous mode so it wraps around */ 416 /* Set continuous mode so it wraps around */
393 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, 417 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
394 U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M); 418 u300_timer_base + U300_TIMER_APP_SGPT2M);
395 /* Disable timer interrupts */ 419 /* Disable timer interrupts */
396 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, 420 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
397 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE); 421 u300_timer_base + U300_TIMER_APP_GPT2IE);
398 /* Then enable the GP2 timer to use as a free running us counter */ 422 /* Then enable the GP2 timer to use as a free running us counter */
399 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, 423 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
400 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2); 424 u300_timer_base + U300_TIMER_APP_EGPT2);
401 425
402 /* Use general purpose timer 2 as clock source */ 426 /* Use general purpose timer 2 as clock source */
403 if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC, 427 if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
404 "GPT2", rate, 300, 32, clocksource_mmio_readl_up)) 428 "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
405 pr_err("timer: failed to initialize U300 clock source\n"); 429 pr_err("timer: failed to initialize U300 clock source\n");
406 430
@@ -413,3 +437,6 @@ void __init u300_timer_init(void)
413 * used by hrtimers! 437 * used by hrtimers!
414 */ 438 */
415} 439}
440
441CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
442 u300_timer_init_of);
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
deleted file mode 100644
index d34287bc34f5..000000000000
--- a/arch/arm/mach-u300/timer.h
+++ /dev/null
@@ -1 +0,0 @@
1extern void u300_timer_init(void);
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
deleted file mode 100644
index 83f50772e169..000000000000
--- a/arch/arm/mach-u300/u300-gpio.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * Individual pin assignments for the B335/S335.
3 * Notice that the actual usage of these pins depends on the
4 * PAD MUX settings, that is why the same number can potentially
5 * appear several times. In the reference design each pin is only
6 * used for one purpose. These were determined by inspecting the
7 * S365 schematic.
8 */
9#define U300_GPIO_PIN_UART_RX 0
10#define U300_GPIO_PIN_UART_TX 1
11#define U300_GPIO_PIN_UART_CTS 2
12#define U300_GPIO_PIN_UART_RTS 3
13#define U300_GPIO_PIN_CAM_MAIN_STANDBY 4 /* Camera MAIN standby */
14#define U300_GPIO_PIN_GPIO05 5 /* Unrouted */
15#define U300_GPIO_PIN_MS_CD 6 /* Memory Stick Card insertion */
16#define U300_GPIO_PIN_GPIO07 7 /* Test point TP2430 */
17
18#define U300_GPIO_PIN_GPIO08 8 /* Test point TP2437 */
19#define U300_GPIO_PIN_GPIO09 9 /* Test point TP2431 */
20#define U300_GPIO_PIN_GPIO10 10 /* Test point TP2432 */
21#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
22#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
23#define U300_GPIO_PIN_CAM_SUB_STANDBY 13 /* Camera SUB standby */
24#define U300_GPIO_PIN_GPIO14 14 /* Test point TP2436 */
25#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
26
27#define U300_GPIO_PIN_GPIO16 16 /* Test point TP2438 */
28#define U300_GPIO_PIN_PHFSENSE 17 /* Headphone jack sensing */
29#define U300_GPIO_PIN_GPIO18 18 /* Test point TP2439 */
30#define U300_GPIO_PIN_GPIO19 19 /* Routed somewhere */
31#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
32#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
33#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
34#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
35
36#define U300_GPIO_PIN_GPIO24 24 /* Unrouted */
37#define U300_GPIO_PIN_GPIO25 25 /* Unrouted */
38#define U300_GPIO_PIN_GPIO26 26 /* Unrouted */
39#define U300_GPIO_PIN_GPIO27 27 /* Unrouted */
40#define U300_GPIO_PIN_GPIO28 28 /* Unrouted */
41#define U300_GPIO_PIN_GPIO29 29 /* Unrouted */
42#define U300_GPIO_PIN_GPIO30 30 /* Unrouted */
43#define U300_GPIO_PIN_GPIO31 31 /* Unrouted */
44
45#define U300_GPIO_PIN_GPIO32 32 /* Unrouted */
46#define U300_GPIO_PIN_GPIO33 33 /* Unrouted */
47#define U300_GPIO_PIN_GPIO34 34 /* Unrouted */
48#define U300_GPIO_PIN_GPIO35 35 /* Unrouted */
49#define U300_GPIO_PIN_GPIO36 36 /* Unrouted */
50#define U300_GPIO_PIN_GPIO37 37 /* Unrouted */
51#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
52#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
53
54#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
55#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
56#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
57#define U300_GPIO_PIN_GPIO43 43 /* Unrouted */
58#define U300_GPIO_PIN_GPIO44 44 /* Unrouted */
59#define U300_GPIO_PIN_GPIO45 45 /* Unrouted */
60#define U300_GPIO_PIN_GPIO46 46 /* Unrouted */
61#define U300_GPIO_PIN_GPIO47 47 /* Unrouted */
62
63#define U300_GPIO_PIN_GPIO48 48 /* Unrouted */
64#define U300_GPIO_PIN_GPIO49 49 /* Unrouted */
65#define U300_GPIO_PIN_GPIO50 50 /* Unrouted */
66#define U300_GPIO_PIN_GPIO51 51 /* Unrouted */
67#define U300_GPIO_PIN_GPIO52 52 /* Unrouted */
68#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
69#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
70#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-14 02:07:13 -0500