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authorArnd Bergmann <arnd@arndb.de>2012-11-12 16:53:22 -0500
committerArnd Bergmann <arnd@arndb.de>2012-11-12 16:53:22 -0500
commit65829ef5a0b9bdffa34b35479853d24e547cfde8 (patch)
tree53b2a46a0422eb8c9d03dd02cc18f8ab9067cf96 /arch
parent976669971ff7d2d668ee3d9e92d0d9db5aae847c (diff)
parent6ba54ab4a49bbad736b0254aa6bdf0cb83013815 (diff)
Merge tag 'omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/headers
From Tony Lindgren <tony@atomide.com>: These changes deal with the issues of relative includes introduced by the earlier clean-up and clean up few more things for enabling multiplatform support. The multiplatform kernel has been booted on omaps on top of this branch with the work-in-progress patches applied manually. We cannot yet enable the multiplatform support though. We still need the common clock framework patches, some solution for dma-omap.h, and serial-omap.h moved before we can enable it. * tag 'omap-for-v3.8/cleanup-headers-prepare-multiplatform-v3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: Remove omap_init_consistent_dma_size() ARM: OMAP: Remove NEED_MACH_GPIO_H ARM: OMAP: Remove unnecessary mach and plat includes ARM: OMAP2+: Fix relative includes for serial.h ARM: OMAP: Fix relative includes for fpga.h ARM: OMAP1: Remove relative includes ARM: OMAP: Remove cpu_is_omap usage from plat-omap/dma.c ARM: OMAP: Fix relative includes for debug-devices.h ARM: OMAP: Remove plat-omap/common.h ARM: OMAP: Move omap-pm-noop.c local to mach-omap2 ARM: OMAP: Fix relative includes for shared i2c.h file ARM: OMAP: Make plat-omap/i2c.c port checks local ARM: OMAP: Move omap2+ specific parts of sram.c to mach-omap2 ARM: OMAP: Move omap1 specific code to local sram.c ARM: OMAP: Introduce common omap_map_sram() and omap_sram_reset() ARM: OMAP: Split sram.h to local headers and minimal shared header ARM: OMAP1: usb: fix sparse warnings Conflicts: arch/arm/mach-omap2/cm33xx.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/mach-omap1/Makefile3
-rw-r--r--arch/arm/mach-omap1/board-fsample.c2
-rw-r--r--arch/arm/mach-omap1/board-innovator.c1
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c2
-rw-r--r--arch/arm/mach-omap1/clock.c3
-rw-r--r--arch/arm/mach-omap1/clock_data.c3
-rw-r--r--arch/arm/mach-omap1/common.h3
-rw-r--r--arch/arm/mach-omap1/devices.c3
-rw-r--r--arch/arm/mach-omap1/dma.c3
-rw-r--r--arch/arm/mach-omap1/fpga.c3
-rw-r--r--arch/arm/mach-omap1/fpga.h (renamed from arch/arm/plat-omap/fpga.h)22
-rw-r--r--arch/arm/mach-omap1/gpio15xx.c2
-rw-r--r--arch/arm/mach-omap1/gpio16xx.c2
-rw-r--r--arch/arm/mach-omap1/gpio7xx.c2
-rw-r--r--arch/arm/mach-omap1/i2c.c5
-rw-r--r--arch/arm/mach-omap1/include/mach/entry-macro.S2
-rw-r--r--arch/arm/mach-omap1/include/mach/gpio.h3
-rw-r--r--arch/arm/mach-omap1/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-omap1/include/mach/memory.h2
-rw-r--r--arch/arm/mach-omap1/include/mach/soc.h229
-rw-r--r--arch/arm/mach-omap1/io.c1
-rw-r--r--arch/arm/mach-omap1/iomap.h3
-rw-r--r--arch/arm/mach-omap1/pm.c4
-rw-r--r--arch/arm/mach-omap1/sleep.S2
-rw-r--r--arch/arm/mach-omap1/soc.h229
-rw-r--r--arch/arm/mach-omap1/sram-init.c76
-rw-r--r--arch/arm/mach-omap1/sram.h7
-rw-r--r--arch/arm/mach-omap1/timer32k.c1
-rw-r--r--arch/arm/mach-omap1/usb.c6
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c2
-rw-r--r--arch/arm/mach-omap2/board-h4.c2
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_dpllcore.c3
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c3
-rw-r--r--arch/arm/mach-omap2/clkt34xx_dpll3m2.c3
-rw-r--r--arch/arm/mach-omap2/cm33xx.c2
-rw-r--r--arch/arm/mach-omap2/common.h5
-rw-r--r--arch/arm/mach-omap2/dma.c3
-rw-r--r--arch/arm/mach-omap2/hsmmc.c1
-rw-r--r--arch/arm/mach-omap2/i2c.c16
-rw-r--r--arch/arm/mach-omap2/i2c.h2
-rw-r--r--arch/arm/mach-omap2/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-omap2/include/mach/gpio.h3
-rw-r--r--arch/arm/mach-omap2/include/mach/serial.h103
-rw-r--r--arch/arm/mach-omap2/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-omap2/io.c15
-rw-r--r--arch/arm/mach-omap2/omap-pm-noop.c (renamed from arch/arm/plat-omap/omap-pm-noop.c)4
-rw-r--r--arch/arm/mach-omap2/omap4-common.c3
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/pm24xx.c5
-rw-r--r--arch/arm/mach-omap2/pm34xx.c4
-rw-r--r--arch/arm/mach-omap2/prm33xx.c2
-rw-r--r--arch/arm/mach-omap2/prm_common.c1
-rw-r--r--arch/arm/mach-omap2/sdrc.c2
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c3
-rw-r--r--arch/arm/mach-omap2/serial.h113
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S3
-rw-r--r--arch/arm/mach-omap2/sram.c305
-rw-r--r--arch/arm/mach-omap2/sram.h (renamed from arch/arm/plat-omap/sram.h)26
-rw-r--r--arch/arm/mach-omap2/timer.c3
-rw-r--r--arch/arm/plat-omap/Makefile3
-rw-r--r--arch/arm/plat-omap/common.c27
-rw-r--r--arch/arm/plat-omap/common.h36
-rw-r--r--arch/arm/plat-omap/counter_32k.c2
-rw-r--r--arch/arm/plat-omap/debug-devices.c3
-rw-r--r--arch/arm/plat-omap/debug-leds.c23
-rw-r--r--arch/arm/plat-omap/dma.c108
-rw-r--r--arch/arm/plat-omap/dmtimer.c21
-rw-r--r--arch/arm/plat-omap/fb.c1
-rw-r--r--arch/arm/plat-omap/i2c.c30
-rw-r--r--arch/arm/plat-omap/include/plat-omap/dma-omap.h20
-rw-r--r--arch/arm/plat-omap/include/plat/counter-32k.h1
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h2
-rw-r--r--arch/arm/plat-omap/include/plat/debug-devices.h (renamed from arch/arm/mach-omap2/debug-devices.h)7
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h2
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h (renamed from arch/arm/plat-omap/i2c.h)0
-rw-r--r--arch/arm/plat-omap/include/plat/sram.h16
-rw-r--r--arch/arm/plat-omap/sram.c366
81 files changed, 956 insertions, 991 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 73067efd4845..6207cf734b2b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -937,7 +937,6 @@ config ARCH_OMAP
937 select CLKSRC_MMIO 937 select CLKSRC_MMIO
938 select GENERIC_CLOCKEVENTS 938 select GENERIC_CLOCKEVENTS
939 select HAVE_CLK 939 select HAVE_CLK
940 select NEED_MACH_GPIO_H
941 help 940 help
942 Support for TI's OMAP platform (OMAP1/2/3/4). 941 Support for TI's OMAP platform (OMAP1/2/3/4).
943 942
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index cd169c386161..f0e69cbc5baa 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,8 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := io.o id.o sram.o time.o irq.o mux.o flash.o serial.o devices.o dma.o 6obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
7 serial.o devices.o dma.o
7obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o 8obj-y += clock.o clock_data.o opp_data.o reset.o pm_bus.o timer.o
8 9
9ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 10ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 8b5800acf726..e067f221f0f9 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -30,13 +30,13 @@
30#include <mach/tc.h> 30#include <mach/tc.h>
31#include <mach/mux.h> 31#include <mach/mux.h>
32#include <mach/flash.h> 32#include <mach/flash.h>
33#include <../plat-omap/fpga.h>
34#include <linux/platform_data/keypad-omap.h> 33#include <linux/platform_data/keypad-omap.h>
35 34
36#include <mach/hardware.h> 35#include <mach/hardware.h>
37 36
38#include "iomap.h" 37#include "iomap.h"
39#include "common.h" 38#include "common.h"
39#include "fpga.h"
40 40
41/* fsample is pretty close to p2-sample */ 41/* fsample is pretty close to p2-sample */
42 42
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index c66334f22471..f8033fab0f82 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -33,7 +33,6 @@
33 33
34#include <mach/mux.h> 34#include <mach/mux.h>
35#include <mach/flash.h> 35#include <mach/flash.h>
36#include <../plat-omap/fpga.h>
37#include <mach/tc.h> 36#include <mach/tc.h>
38#include <linux/platform_data/keypad-omap.h> 37#include <linux/platform_data/keypad-omap.h>
39 38
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 030bd48727be..9a7e483ed6fd 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -30,13 +30,13 @@
30 30
31#include <mach/tc.h> 31#include <mach/tc.h>
32#include <mach/mux.h> 32#include <mach/mux.h>
33#include <../plat-omap/fpga.h>
34#include <mach/flash.h> 33#include <mach/flash.h>
35 34
36#include <mach/hardware.h> 35#include <mach/hardware.h>
37 36
38#include "iomap.h" 37#include "iomap.h"
39#include "common.h" 38#include "common.h"
39#include "fpga.h"
40 40
41static const unsigned int p2_keymap[] = { 41static const unsigned int p2_keymap[] = {
42 KEY(0, 0, KEY_UP), 42 KEY(0, 0, KEY_UP),
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 931f3f6d396b..4f5fd4a084c0 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -24,12 +24,11 @@
24 24
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27#include "../plat-omap/sram.h"
28
29#include "soc.h" 27#include "soc.h"
30#include "iomap.h" 28#include "iomap.h"
31#include "clock.h" 29#include "clock.h"
32#include "opp.h" 30#include "opp.h"
31#include "sram.h"
33 32
34__u32 arm_idlect1_mask; 33__u32 arm_idlect1_mask;
35struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; 34struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 28aea55a412e..cb7c6ae2e3fc 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -27,10 +27,9 @@
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/usb.h> /* for OTG_BASE */ 28#include <mach/usb.h> /* for OTG_BASE */
29 29
30#include "../plat-omap/sram.h"
31
32#include "iomap.h" 30#include "iomap.h"
33#include "clock.h" 31#include "clock.h"
32#include "sram.h"
34 33
35/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */ 34/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
36#define IDL_CLKOUT_ARM_SHIFT 12 35#define IDL_CLKOUT_ARM_SHIFT 12
diff --git a/arch/arm/mach-omap1/common.h b/arch/arm/mach-omap1/common.h
index d6ac18d04da7..dab2e102b9d7 100644
--- a/arch/arm/mach-omap1/common.h
+++ b/arch/arm/mach-omap1/common.h
@@ -26,11 +26,10 @@
26#ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H 26#ifndef __ARCH_ARM_MACH_OMAP1_COMMON_H
27#define __ARCH_ARM_MACH_OMAP1_COMMON_H 27#define __ARCH_ARM_MACH_OMAP1_COMMON_H
28 28
29#include "../plat-omap/common.h"
30#include <linux/mtd/mtd.h> 29#include <linux/mtd/mtd.h>
31#include <linux/i2c-omap.h> 30#include <linux/i2c-omap.h>
32 31
33#include "../plat-omap/i2c.h" 32#include <plat/i2c.h>
34 33
35#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 34#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
36void omap7xx_map_io(void); 35void omap7xx_map_io(void);
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 645668e2b1d5..7155ed8b97f8 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -26,12 +26,11 @@
26#include <mach/camera.h> 26#include <mach/camera.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28 28
29#include "../plat-omap/sram.h"
30
31#include "common.h" 29#include "common.h"
32#include "clock.h" 30#include "clock.h"
33#include "dma.h" 31#include "dma.h"
34#include "mmc.h" 32#include "mmc.h"
33#include "sram.h"
35 34
36#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE) 35#if defined(CONFIG_SND_SOC) || defined(CONFIG_SND_SOC_MODULE)
37 36
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index 71305c15fbd5..978aed85d328 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -321,6 +321,9 @@ static int __init omap1_system_dma_init(void)
321 d->dev_caps = ENABLE_1510_MODE; 321 d->dev_caps = ENABLE_1510_MODE;
322 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; 322 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
323 323
324 if (cpu_is_omap16xx())
325 d->dev_caps = ENABLE_16XX_MODE;
326
324 d->dev_caps |= SRC_PORT; 327 d->dev_caps |= SRC_PORT;
325 d->dev_caps |= DST_PORT; 328 d->dev_caps |= DST_PORT;
326 d->dev_caps |= SRC_INDEX; 329 d->dev_caps |= SRC_INDEX;
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index d940fac9a9ed..8bd71b2d0967 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -27,12 +27,11 @@
27#include <asm/irq.h> 27#include <asm/irq.h>
28#include <asm/mach/irq.h> 28#include <asm/mach/irq.h>
29 29
30#include <../plat-omap/fpga.h>
31
32#include <mach/hardware.h> 30#include <mach/hardware.h>
33 31
34#include "iomap.h" 32#include "iomap.h"
35#include "common.h" 33#include "common.h"
34#include "fpga.h"
36 35
37static void fpga_mask_irq(struct irq_data *d) 36static void fpga_mask_irq(struct irq_data *d)
38{ 37{
diff --git a/arch/arm/plat-omap/fpga.h b/arch/arm/mach-omap1/fpga.h
index 54faaa93e6f4..4b4307a80e48 100644
--- a/arch/arm/plat-omap/fpga.h
+++ b/arch/arm/mach-omap1/fpga.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/fpga.h
3 *
4 * Interrupt handler for OMAP-1510 FPGA 2 * Interrupt handler for OMAP-1510 FPGA
5 * 3 *
6 * Copyright (C) 2001 RidgeRun, Inc. 4 * Copyright (C) 2001 RidgeRun, Inc.
@@ -38,26 +36,6 @@
38#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */ 36#define H2P2_DBG_FPGA_LAN_STATUS IOMEM(H2P2_DBG_FPGA_BASE + 0x1A) /* LAN Status line */
39#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */ 37#define H2P2_DBG_FPGA_LAN_RESET IOMEM(H2P2_DBG_FPGA_BASE + 0x1C) /* LAN Reset line */
40 38
41/* NOTE: most boards don't have a static mapping for the FPGA ... */
42struct h2p2_dbg_fpga {
43 /* offset 0x00 */
44 u16 smc91x[8];
45 /* offset 0x10 */
46 u16 fpga_rev;
47 u16 board_rev;
48 u16 gpio_outputs;
49 u16 leds;
50 /* offset 0x18 */
51 u16 misc_inputs;
52 u16 lan_status;
53 u16 lan_reset;
54 u16 reserved0;
55 /* offset 0x20 */
56 u16 ps2_data;
57 u16 ps2_ctrl;
58 /* plus also 4 rs232 ports ... */
59};
60
61/* LEDs definition on debug board (16 LEDs, all physically green) */ 39/* LEDs definition on debug board (16 LEDs, all physically green) */
62#define H2P2_DBG_FPGA_LED_GREEN (1 << 15) 40#define H2P2_DBG_FPGA_LED_GREEN (1 << 15)
63#define H2P2_DBG_FPGA_LED_AMBER (1 << 14) 41#define H2P2_DBG_FPGA_LED_AMBER (1 << 14)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 98e6f39224a4..02b3eb2e201c 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -19,6 +19,8 @@
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/platform_data/gpio-omap.h> 20#include <linux/platform_data/gpio-omap.h>
21 21
22#include <mach/irqs.h>
23
22#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE 24#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
23#define OMAP1510_GPIO_BASE 0xFFFCE000 25#define OMAP1510_GPIO_BASE 0xFFFCE000
24 26
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 33f419236b17..b9952a258d82 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -19,6 +19,8 @@
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/platform_data/gpio-omap.h> 20#include <linux/platform_data/gpio-omap.h>
21 21
22#include <mach/irqs.h>
23
22#define OMAP1610_GPIO1_BASE 0xfffbe400 24#define OMAP1610_GPIO1_BASE 0xfffbe400
23#define OMAP1610_GPIO2_BASE 0xfffbec00 25#define OMAP1610_GPIO2_BASE 0xfffbec00
24#define OMAP1610_GPIO3_BASE 0xfffbb400 26#define OMAP1610_GPIO3_BASE 0xfffbb400
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 958ce9acee95..f5819b2b7cbe 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -19,6 +19,8 @@
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/platform_data/gpio-omap.h> 20#include <linux/platform_data/gpio-omap.h>
21 21
22#include <mach/irqs.h>
23
22#define OMAP7XX_GPIO1_BASE 0xfffbc000 24#define OMAP7XX_GPIO1_BASE 0xfffbc000
23#define OMAP7XX_GPIO2_BASE 0xfffbc800 25#define OMAP7XX_GPIO2_BASE 0xfffbc800
24#define OMAP7XX_GPIO3_BASE 0xfffbd000 26#define OMAP7XX_GPIO3_BASE 0xfffbd000
diff --git a/arch/arm/mach-omap1/i2c.c b/arch/arm/mach-omap1/i2c.c
index 32bcbb8d6c73..faca808cb3d9 100644
--- a/arch/arm/mach-omap1/i2c.c
+++ b/arch/arm/mach-omap1/i2c.c
@@ -23,7 +23,7 @@
23#include <mach/mux.h> 23#include <mach/mux.h>
24#include "soc.h" 24#include "soc.h"
25 25
26#include "../plat-omap/i2c.h" 26#include <plat/i2c.h>
27 27
28#define OMAP_I2C_SIZE 0x3f 28#define OMAP_I2C_SIZE 0x3f
29#define OMAP1_I2C_BASE 0xfffb3800 29#define OMAP1_I2C_BASE 0xfffb3800
@@ -54,6 +54,9 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *pdata,
54 struct platform_device *pdev; 54 struct platform_device *pdev;
55 struct resource *res; 55 struct resource *res;
56 56
57 if (bus_id > 1)
58 return -EINVAL;
59
57 omap1_i2c_mux_pins(bus_id); 60 omap1_i2c_mux_pins(bus_id);
58 61
59 pdev = &omap_i2c_devices[bus_id - 1]; 62 pdev = &omap_i2c_devices[bus_id - 1];
diff --git a/arch/arm/mach-omap1/include/mach/entry-macro.S b/arch/arm/mach-omap1/include/mach/entry-macro.S
index 88f08cab1717..78a8c6c24764 100644
--- a/arch/arm/mach-omap1/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap1/include/mach/entry-macro.S
@@ -13,8 +13,6 @@
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#include <mach/irqs.h> 14#include <mach/irqs.h>
15 15
16#include "../../iomap.h"
17
18 .macro get_irqnr_preamble, base, tmp 16 .macro get_irqnr_preamble, base, tmp
19 .endm 17 .endm
20 18
diff --git a/arch/arm/mach-omap1/include/mach/gpio.h b/arch/arm/mach-omap1/include/mach/gpio.h
deleted file mode 100644
index ebf86c0f4f46..000000000000
--- a/arch/arm/mach-omap1/include/mach/gpio.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * arch/arm/mach-omap1/include/mach/gpio.h
3 */
diff --git a/arch/arm/mach-omap1/include/mach/hardware.h b/arch/arm/mach-omap1/include/mach/hardware.h
index dc3237bd72d2..5875a5098d35 100644
--- a/arch/arm/mach-omap1/include/mach/hardware.h
+++ b/arch/arm/mach-omap1/include/mach/hardware.h
@@ -39,7 +39,7 @@
39#include <asm/sizes.h> 39#include <asm/sizes.h>
40#ifndef __ASSEMBLER__ 40#ifndef __ASSEMBLER__
41#include <asm/types.h> 41#include <asm/types.h>
42#include "../../mach-omap1/soc.h" 42#include <mach/soc.h>
43 43
44/* 44/*
45 * NOTE: Please use ioremap + __raw_read/write where possible instead of these 45 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
@@ -72,6 +72,9 @@ static inline u32 omap_cs3_phys(void)
72 72
73#endif /* ifndef __ASSEMBLER__ */ 73#endif /* ifndef __ASSEMBLER__ */
74 74
75#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
76#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
77
75#include <mach/serial.h> 78#include <mach/serial.h>
76 79
77/* 80/*
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index 351ae4f2c514..3c2530523111 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -19,7 +19,7 @@
19 * because of the strncmp(). 19 * because of the strncmp().
20 */ 20 */
21#if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__) 21#if defined(CONFIG_ARCH_OMAP15XX) && !defined(__ASSEMBLER__)
22#include "../../mach-omap1/soc.h" 22#include <mach/soc.h>
23 23
24/* 24/*
25 * OMAP-1510 Local Bus address offset 25 * OMAP-1510 Local Bus address offset
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h
new file mode 100644
index 000000000000..6cf9c1cc2bef
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/soc.h
@@ -0,0 +1,229 @@
1/*
2 * OMAP cpu type detection
3 *
4 * Copyright (C) 2004, 2008 Nokia Corporation
5 *
6 * Copyright (C) 2009-11 Texas Instruments.
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28#ifndef __ASM_ARCH_OMAP_CPU_H
29#define __ASM_ARCH_OMAP_CPU_H
30
31#ifndef __ASSEMBLY__
32
33#include <linux/bitops.h>
34
35/*
36 * Test if multicore OMAP support is needed
37 */
38#undef MULTI_OMAP1
39#undef OMAP_NAME
40
41#ifdef CONFIG_ARCH_OMAP730
42# ifdef OMAP_NAME
43# undef MULTI_OMAP1
44# define MULTI_OMAP1
45# else
46# define OMAP_NAME omap730
47# endif
48#endif
49#ifdef CONFIG_ARCH_OMAP850
50# ifdef OMAP_NAME
51# undef MULTI_OMAP1
52# define MULTI_OMAP1
53# else
54# define OMAP_NAME omap850
55# endif
56#endif
57#ifdef CONFIG_ARCH_OMAP15XX
58# ifdef OMAP_NAME
59# undef MULTI_OMAP1
60# define MULTI_OMAP1
61# else
62# define OMAP_NAME omap1510
63# endif
64#endif
65#ifdef CONFIG_ARCH_OMAP16XX
66# ifdef OMAP_NAME
67# undef MULTI_OMAP1
68# define MULTI_OMAP1
69# else
70# define OMAP_NAME omap16xx
71# endif
72#endif
73
74/*
75 * omap_rev bits:
76 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
77 * CPU revision (See _REV_ defined in cpu.h) [15:08]
78 * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
79 */
80unsigned int omap_rev(void);
81
82/*
83 * Get the CPU revision for OMAP devices
84 */
85#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
86
87/*
88 * Macros to group OMAP into cpu classes.
89 * These can be used in most places.
90 * cpu_is_omap7xx(): True for OMAP730, OMAP850
91 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
92 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
93 */
94#define GET_OMAP_CLASS (omap_rev() & 0xff)
95
96#define IS_OMAP_CLASS(class, id) \
97static inline int is_omap ##class (void) \
98{ \
99 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
100}
101
102#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
103
104#define IS_OMAP_SUBCLASS(subclass, id) \
105static inline int is_omap ##subclass (void) \
106{ \
107 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
108}
109
110IS_OMAP_CLASS(7xx, 0x07)
111IS_OMAP_CLASS(15xx, 0x15)
112IS_OMAP_CLASS(16xx, 0x16)
113
114#define cpu_is_omap7xx() 0
115#define cpu_is_omap15xx() 0
116#define cpu_is_omap16xx() 0
117
118#if defined(MULTI_OMAP1)
119# if defined(CONFIG_ARCH_OMAP730)
120# undef cpu_is_omap7xx
121# define cpu_is_omap7xx() is_omap7xx()
122# endif
123# if defined(CONFIG_ARCH_OMAP850)
124# undef cpu_is_omap7xx
125# define cpu_is_omap7xx() is_omap7xx()
126# endif
127# if defined(CONFIG_ARCH_OMAP15XX)
128# undef cpu_is_omap15xx
129# define cpu_is_omap15xx() is_omap15xx()
130# endif
131# if defined(CONFIG_ARCH_OMAP16XX)
132# undef cpu_is_omap16xx
133# define cpu_is_omap16xx() is_omap16xx()
134# endif
135#else
136# if defined(CONFIG_ARCH_OMAP730)
137# undef cpu_is_omap7xx
138# define cpu_is_omap7xx() 1
139# endif
140# if defined(CONFIG_ARCH_OMAP850)
141# undef cpu_is_omap7xx
142# define cpu_is_omap7xx() 1
143# endif
144# if defined(CONFIG_ARCH_OMAP15XX)
145# undef cpu_is_omap15xx
146# define cpu_is_omap15xx() 1
147# endif
148# if defined(CONFIG_ARCH_OMAP16XX)
149# undef cpu_is_omap16xx
150# define cpu_is_omap16xx() 1
151# endif
152#endif
153
154/*
155 * Macros to detect individual cpu types.
156 * These are only rarely needed.
157 * cpu_is_omap310(): True for OMAP310
158 * cpu_is_omap1510(): True for OMAP1510
159 * cpu_is_omap1610(): True for OMAP1610
160 * cpu_is_omap1611(): True for OMAP1611
161 * cpu_is_omap5912(): True for OMAP5912
162 * cpu_is_omap1621(): True for OMAP1621
163 * cpu_is_omap1710(): True for OMAP1710
164 */
165#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
166
167#define IS_OMAP_TYPE(type, id) \
168static inline int is_omap ##type (void) \
169{ \
170 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
171}
172
173IS_OMAP_TYPE(310, 0x0310)
174IS_OMAP_TYPE(1510, 0x1510)
175IS_OMAP_TYPE(1610, 0x1610)
176IS_OMAP_TYPE(1611, 0x1611)
177IS_OMAP_TYPE(5912, 0x1611)
178IS_OMAP_TYPE(1621, 0x1621)
179IS_OMAP_TYPE(1710, 0x1710)
180
181#define cpu_is_omap310() 0
182#define cpu_is_omap1510() 0
183#define cpu_is_omap1610() 0
184#define cpu_is_omap5912() 0
185#define cpu_is_omap1611() 0
186#define cpu_is_omap1621() 0
187#define cpu_is_omap1710() 0
188
189/* These are needed to compile common code */
190#ifdef CONFIG_ARCH_OMAP1
191#define cpu_is_omap242x() 0
192#define cpu_is_omap2430() 0
193#define cpu_is_omap243x() 0
194#define cpu_is_omap24xx() 0
195#define cpu_is_omap34xx() 0
196#define cpu_is_omap44xx() 0
197#define soc_is_omap54xx() 0
198#define soc_is_am33xx() 0
199#define cpu_class_is_omap1() 1
200#define cpu_class_is_omap2() 0
201#endif
202
203/*
204 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
205 * between 310 vs. 1510 and 1611B/5912 vs. 1710.
206 */
207
208#if defined(CONFIG_ARCH_OMAP15XX)
209# undef cpu_is_omap310
210# undef cpu_is_omap1510
211# define cpu_is_omap310() is_omap310()
212# define cpu_is_omap1510() is_omap1510()
213#endif
214
215#if defined(CONFIG_ARCH_OMAP16XX)
216# undef cpu_is_omap1610
217# undef cpu_is_omap1611
218# undef cpu_is_omap5912
219# undef cpu_is_omap1621
220# undef cpu_is_omap1710
221# define cpu_is_omap1610() is_omap1610()
222# define cpu_is_omap1611() is_omap1611()
223# define cpu_is_omap5912() is_omap5912()
224# define cpu_is_omap1621() is_omap1621()
225# define cpu_is_omap1710() is_omap1710()
226#endif
227
228#endif /* __ASSEMBLY__ */
229#endif
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 44389d7cd255..5a3b80617a11 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -134,7 +134,6 @@ void __init omap1_init_early(void)
134 */ 134 */
135 omap1_clk_init(); 135 omap1_clk_init();
136 omap1_mux_init(); 136 omap1_mux_init();
137 omap_init_consistent_dma_size();
138} 137}
139 138
140void __init omap1_init_late(void) 139void __init omap1_init_late(void)
diff --git a/arch/arm/mach-omap1/iomap.h b/arch/arm/mach-omap1/iomap.h
index 330c4716b028..f4e2d7a21365 100644
--- a/arch/arm/mach-omap1/iomap.h
+++ b/arch/arm/mach-omap1/iomap.h
@@ -22,9 +22,6 @@
22 * 675 Mass Ave, Cambridge, MA 02139, USA. 22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */ 23 */
24 24
25#define OMAP1_IO_OFFSET 0x01000000 /* Virtual IO = 0xfefb0000 */
26#define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET)
27
28/* 25/*
29 * ---------------------------------------------------------------------------- 26 * ----------------------------------------------------------------------------
30 * Omap1 specific IO mapping 27 * Omap1 specific IO mapping
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index b2c2328d7c18..66d663a6ef3a 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -44,6 +44,7 @@
44#include <linux/io.h> 44#include <linux/io.h>
45#include <linux/atomic.h> 45#include <linux/atomic.h>
46 46
47#include <asm/fncpy.h>
47#include <asm/system_misc.h> 48#include <asm/system_misc.h>
48#include <asm/irq.h> 49#include <asm/irq.h>
49#include <asm/mach/time.h> 50#include <asm/mach/time.h>
@@ -56,11 +57,10 @@
56 57
57#include <mach/irqs.h> 58#include <mach/irqs.h>
58 59
59#include "../plat-omap/sram.h"
60
61#include "iomap.h" 60#include "iomap.h"
62#include "clock.h" 61#include "clock.h"
63#include "pm.h" 62#include "pm.h"
63#include "sram.h"
64 64
65static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; 65static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
66static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; 66static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
diff --git a/arch/arm/mach-omap1/sleep.S b/arch/arm/mach-omap1/sleep.S
index 0e628743bd03..a908c51839a4 100644
--- a/arch/arm/mach-omap1/sleep.S
+++ b/arch/arm/mach-omap1/sleep.S
@@ -36,6 +36,8 @@
36 36
37#include <asm/assembler.h> 37#include <asm/assembler.h>
38 38
39#include <mach/hardware.h>
40
39#include "iomap.h" 41#include "iomap.h"
40#include "pm.h" 42#include "pm.h"
41 43
diff --git a/arch/arm/mach-omap1/soc.h b/arch/arm/mach-omap1/soc.h
index 6cf9c1cc2bef..69daf0187b1d 100644
--- a/arch/arm/mach-omap1/soc.h
+++ b/arch/arm/mach-omap1/soc.h
@@ -1,229 +1,4 @@
1/* 1/*
2 * OMAP cpu type detection 2 * We can move mach/soc.h here once the drivers are fixed
3 *
4 * Copyright (C) 2004, 2008 Nokia Corporation
5 *
6 * Copyright (C) 2009-11 Texas Instruments.
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */ 3 */
27 4#include <mach/soc.h>
28#ifndef __ASM_ARCH_OMAP_CPU_H
29#define __ASM_ARCH_OMAP_CPU_H
30
31#ifndef __ASSEMBLY__
32
33#include <linux/bitops.h>
34
35/*
36 * Test if multicore OMAP support is needed
37 */
38#undef MULTI_OMAP1
39#undef OMAP_NAME
40
41#ifdef CONFIG_ARCH_OMAP730
42# ifdef OMAP_NAME
43# undef MULTI_OMAP1
44# define MULTI_OMAP1
45# else
46# define OMAP_NAME omap730
47# endif
48#endif
49#ifdef CONFIG_ARCH_OMAP850
50# ifdef OMAP_NAME
51# undef MULTI_OMAP1
52# define MULTI_OMAP1
53# else
54# define OMAP_NAME omap850
55# endif
56#endif
57#ifdef CONFIG_ARCH_OMAP15XX
58# ifdef OMAP_NAME
59# undef MULTI_OMAP1
60# define MULTI_OMAP1
61# else
62# define OMAP_NAME omap1510
63# endif
64#endif
65#ifdef CONFIG_ARCH_OMAP16XX
66# ifdef OMAP_NAME
67# undef MULTI_OMAP1
68# define MULTI_OMAP1
69# else
70# define OMAP_NAME omap16xx
71# endif
72#endif
73
74/*
75 * omap_rev bits:
76 * CPU id bits (0730, 1510, 1710, 2422...) [31:16]
77 * CPU revision (See _REV_ defined in cpu.h) [15:08]
78 * CPU class bits (15xx, 16xx, 24xx, 34xx...) [07:00]
79 */
80unsigned int omap_rev(void);
81
82/*
83 * Get the CPU revision for OMAP devices
84 */
85#define GET_OMAP_REVISION() ((omap_rev() >> 8) & 0xff)
86
87/*
88 * Macros to group OMAP into cpu classes.
89 * These can be used in most places.
90 * cpu_is_omap7xx(): True for OMAP730, OMAP850
91 * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310
92 * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710
93 */
94#define GET_OMAP_CLASS (omap_rev() & 0xff)
95
96#define IS_OMAP_CLASS(class, id) \
97static inline int is_omap ##class (void) \
98{ \
99 return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
100}
101
102#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
103
104#define IS_OMAP_SUBCLASS(subclass, id) \
105static inline int is_omap ##subclass (void) \
106{ \
107 return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
108}
109
110IS_OMAP_CLASS(7xx, 0x07)
111IS_OMAP_CLASS(15xx, 0x15)
112IS_OMAP_CLASS(16xx, 0x16)
113
114#define cpu_is_omap7xx() 0
115#define cpu_is_omap15xx() 0
116#define cpu_is_omap16xx() 0
117
118#if defined(MULTI_OMAP1)
119# if defined(CONFIG_ARCH_OMAP730)
120# undef cpu_is_omap7xx
121# define cpu_is_omap7xx() is_omap7xx()
122# endif
123# if defined(CONFIG_ARCH_OMAP850)
124# undef cpu_is_omap7xx
125# define cpu_is_omap7xx() is_omap7xx()
126# endif
127# if defined(CONFIG_ARCH_OMAP15XX)
128# undef cpu_is_omap15xx
129# define cpu_is_omap15xx() is_omap15xx()
130# endif
131# if defined(CONFIG_ARCH_OMAP16XX)
132# undef cpu_is_omap16xx
133# define cpu_is_omap16xx() is_omap16xx()
134# endif
135#else
136# if defined(CONFIG_ARCH_OMAP730)
137# undef cpu_is_omap7xx
138# define cpu_is_omap7xx() 1
139# endif
140# if defined(CONFIG_ARCH_OMAP850)
141# undef cpu_is_omap7xx
142# define cpu_is_omap7xx() 1
143# endif
144# if defined(CONFIG_ARCH_OMAP15XX)
145# undef cpu_is_omap15xx
146# define cpu_is_omap15xx() 1
147# endif
148# if defined(CONFIG_ARCH_OMAP16XX)
149# undef cpu_is_omap16xx
150# define cpu_is_omap16xx() 1
151# endif
152#endif
153
154/*
155 * Macros to detect individual cpu types.
156 * These are only rarely needed.
157 * cpu_is_omap310(): True for OMAP310
158 * cpu_is_omap1510(): True for OMAP1510
159 * cpu_is_omap1610(): True for OMAP1610
160 * cpu_is_omap1611(): True for OMAP1611
161 * cpu_is_omap5912(): True for OMAP5912
162 * cpu_is_omap1621(): True for OMAP1621
163 * cpu_is_omap1710(): True for OMAP1710
164 */
165#define GET_OMAP_TYPE ((omap_rev() >> 16) & 0xffff)
166
167#define IS_OMAP_TYPE(type, id) \
168static inline int is_omap ##type (void) \
169{ \
170 return (GET_OMAP_TYPE == (id)) ? 1 : 0; \
171}
172
173IS_OMAP_TYPE(310, 0x0310)
174IS_OMAP_TYPE(1510, 0x1510)
175IS_OMAP_TYPE(1610, 0x1610)
176IS_OMAP_TYPE(1611, 0x1611)
177IS_OMAP_TYPE(5912, 0x1611)
178IS_OMAP_TYPE(1621, 0x1621)
179IS_OMAP_TYPE(1710, 0x1710)
180
181#define cpu_is_omap310() 0
182#define cpu_is_omap1510() 0
183#define cpu_is_omap1610() 0
184#define cpu_is_omap5912() 0
185#define cpu_is_omap1611() 0
186#define cpu_is_omap1621() 0
187#define cpu_is_omap1710() 0
188
189/* These are needed to compile common code */
190#ifdef CONFIG_ARCH_OMAP1
191#define cpu_is_omap242x() 0
192#define cpu_is_omap2430() 0
193#define cpu_is_omap243x() 0
194#define cpu_is_omap24xx() 0
195#define cpu_is_omap34xx() 0
196#define cpu_is_omap44xx() 0
197#define soc_is_omap54xx() 0
198#define soc_is_am33xx() 0
199#define cpu_class_is_omap1() 1
200#define cpu_class_is_omap2() 0
201#endif
202
203/*
204 * Whether we have MULTI_OMAP1 or not, we still need to distinguish
205 * between 310 vs. 1510 and 1611B/5912 vs. 1710.
206 */
207
208#if defined(CONFIG_ARCH_OMAP15XX)
209# undef cpu_is_omap310
210# undef cpu_is_omap1510
211# define cpu_is_omap310() is_omap310()
212# define cpu_is_omap1510() is_omap1510()
213#endif
214
215#if defined(CONFIG_ARCH_OMAP16XX)
216# undef cpu_is_omap1610
217# undef cpu_is_omap1611
218# undef cpu_is_omap5912
219# undef cpu_is_omap1621
220# undef cpu_is_omap1710
221# define cpu_is_omap1610() is_omap1610()
222# define cpu_is_omap1611() is_omap1611()
223# define cpu_is_omap5912() is_omap5912()
224# define cpu_is_omap1621() is_omap1621()
225# define cpu_is_omap1710() is_omap1710()
226#endif
227
228#endif /* __ASSEMBLY__ */
229#endif
diff --git a/arch/arm/mach-omap1/sram-init.c b/arch/arm/mach-omap1/sram-init.c
new file mode 100644
index 000000000000..6431b0f862ce
--- /dev/null
+++ b/arch/arm/mach-omap1/sram-init.c
@@ -0,0 +1,76 @@
1/*
2 * OMAP SRAM detection and management
3 *
4 * Copyright (C) 2005 Nokia Corporation
5 * Written by Tony Lindgren <tony@atomide.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/io.h>
16
17#include <asm/fncpy.h>
18#include <asm/tlb.h>
19#include <asm/cacheflush.h>
20
21#include <asm/mach/map.h>
22
23#include "soc.h"
24#include "sram.h"
25
26#define OMAP1_SRAM_PA 0x20000000
27#define SRAM_BOOTLOADER_SZ 0x80
28
29/*
30 * The amount of SRAM depends on the core type.
31 * Note that we cannot try to test for SRAM here because writes
32 * to secure SRAM will hang the system. Also the SRAM is not
33 * yet mapped at this point.
34 */
35static void __init omap_detect_and_map_sram(void)
36{
37 unsigned long omap_sram_skip = SRAM_BOOTLOADER_SZ;
38 unsigned long omap_sram_start = OMAP1_SRAM_PA;
39 unsigned long omap_sram_size;
40
41 if (cpu_is_omap7xx())
42 omap_sram_size = 0x32000; /* 200K */
43 else if (cpu_is_omap15xx())
44 omap_sram_size = 0x30000; /* 192K */
45 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
46 cpu_is_omap1621() || cpu_is_omap1710())
47 omap_sram_size = 0x4000; /* 16K */
48 else {
49 pr_err("Could not detect SRAM size\n");
50 omap_sram_size = 0x4000;
51 }
52
53 omap_map_sram(omap_sram_start, omap_sram_size,
54 omap_sram_skip, 1);
55}
56
57static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
58
59void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
60{
61 BUG_ON(!_omap_sram_reprogram_clock);
62 /* On 730, bit 13 must always be 1 */
63 if (cpu_is_omap7xx())
64 ckctl |= 0x2000;
65 _omap_sram_reprogram_clock(dpllctl, ckctl);
66}
67
68int __init omap_sram_init(void)
69{
70 omap_detect_and_map_sram();
71 _omap_sram_reprogram_clock =
72 omap_sram_push(omap1_sram_reprogram_clock,
73 omap1_sram_reprogram_clock_sz);
74
75 return 0;
76}
diff --git a/arch/arm/mach-omap1/sram.h b/arch/arm/mach-omap1/sram.h
new file mode 100644
index 000000000000..d5a6c8362301
--- /dev/null
+++ b/arch/arm/mach-omap1/sram.h
@@ -0,0 +1,7 @@
1#include <plat/sram.h>
2
3extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
4
5/* Do not use these */
6extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
7extern unsigned long omap1_sram_reprogram_clock_sz;
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 74529549130c..89368195bf08 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -50,6 +50,7 @@
50#include <asm/mach/irq.h> 50#include <asm/mach/irq.h>
51#include <asm/mach/time.h> 51#include <asm/mach/time.h>
52 52
53#include <plat/counter-32k.h>
53#include <plat/dmtimer.h> 54#include <plat/dmtimer.h>
54 55
55#include <mach/hardware.h> 56#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index 84267edd9421..104fed366b8f 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -301,7 +301,7 @@ static inline void otg_device_init(struct omap_usb_config *pdata)
301 301
302#endif 302#endif
303 303
304u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device) 304static u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
305{ 305{
306 u32 syscon1 = 0; 306 u32 syscon1 = 0;
307 307
@@ -409,7 +409,7 @@ u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
409 return syscon1 << 16; 409 return syscon1 << 16;
410} 410}
411 411
412u32 __init omap1_usb1_init(unsigned nwires) 412static u32 __init omap1_usb1_init(unsigned nwires)
413{ 413{
414 u32 syscon1 = 0; 414 u32 syscon1 = 0;
415 415
@@ -475,7 +475,7 @@ bad:
475 return syscon1 << 20; 475 return syscon1 << 20;
476} 476}
477 477
478u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) 478static u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
479{ 479{
480 u32 syscon1 = 0; 480 u32 syscon1 = 0;
481 481
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ae87a3ea53ae..c94d495b8d95 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -5,7 +5,7 @@
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
8 omap_device.o 8 omap_device.o sram.o
9 9
10omap-2-3-common = irq.o 10omap-2-3-common = irq.o
11hwmod-common = omap_hwmod.o \ 11hwmod-common = omap_hwmod.o \
@@ -75,6 +75,7 @@ obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
75obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 75obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
76obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o 76obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
77obj-$(CONFIG_PM_DEBUG) += pm-debug.o 77obj-$(CONFIG_PM_DEBUG) += pm-debug.o
78obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
78 79
79obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o 80obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
80obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o 81obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 3fc6d839fb3a..d1c01625fe5a 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -28,7 +28,6 @@
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30 30
31#include <mach/hardware.h>
32#include <asm/mach-types.h> 31#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
34#include <asm/mach/map.h> 33#include <asm/mach/map.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index cf9449bde186..a8cad2237a2a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -44,8 +44,6 @@
44#include <video/omap-panel-tfp410.h> 44#include <video/omap-panel-tfp410.h>
45#include <linux/platform_data/spi-omap2-mcspi.h> 45#include <linux/platform_data/spi-omap2-mcspi.h>
46 46
47#include <mach/hardware.h>
48
49#include "common.h" 47#include "common.h"
50#include "mux.h" 48#include "mux.h"
51#include "sdram-micron-mt46h32m32lf-6.h" 49#include "sdram-micron-mt46h32m32lf-6.h"
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index bd11b0aa9495..8668c72ee810 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -33,7 +33,7 @@
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34 34
35#include <plat-omap/dma-omap.h> 35#include <plat-omap/dma-omap.h>
36#include "debug-devices.h" 36#include <plat/debug-devices.h>
37 37
38#include <video/omapdss.h> 38#include <video/omapdss.h>
39#include <video/omap-panel-generic-dpi.h> 39#include <video/omap-panel-generic-dpi.h>
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 3432f913f743..0d2f14c2dcce 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -25,14 +25,13 @@
25#include <linux/clk.h> 25#include <linux/clk.h>
26#include <linux/io.h> 26#include <linux/io.h>
27 27
28#include "../plat-omap/sram.h"
29
30#include "clock.h" 28#include "clock.h"
31#include "clock2xxx.h" 29#include "clock2xxx.h"
32#include "opp2xxx.h" 30#include "opp2xxx.h"
33#include "cm2xxx_3xxx.h" 31#include "cm2xxx_3xxx.h"
34#include "cm-regbits-24xx.h" 32#include "cm-regbits-24xx.h"
35#include "sdrc.h" 33#include "sdrc.h"
34#include "sram.h"
36 35
37/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ 36/* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */
38 37
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index c66276b2bf0a..a38ebb209721 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -33,8 +33,6 @@
33#include <linux/cpufreq.h> 33#include <linux/cpufreq.h>
34#include <linux/slab.h> 34#include <linux/slab.h>
35 35
36#include "../plat-omap/sram.h"
37
38#include "soc.h" 36#include "soc.h"
39#include "clock.h" 37#include "clock.h"
40#include "clock2xxx.h" 38#include "clock2xxx.h"
@@ -42,6 +40,7 @@
42#include "cm2xxx_3xxx.h" 40#include "cm2xxx_3xxx.h"
43#include "cm-regbits-24xx.h" 41#include "cm-regbits-24xx.h"
44#include "sdrc.h" 42#include "sdrc.h"
43#include "sram.h"
45 44
46const struct prcm_config *curr_prcm_set; 45const struct prcm_config *curr_prcm_set;
47const struct prcm_config *rate_table; 46const struct prcm_config *rate_table;
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 5510d92abe6e..6cf298e262f6 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -21,12 +21,11 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/io.h> 22#include <linux/io.h>
23 23
24#include "../plat-omap/sram.h"
25
26#include "clock.h" 24#include "clock.h"
27#include "clock3xxx.h" 25#include "clock3xxx.h"
28#include "clock34xx.h" 26#include "clock34xx.h"
29#include "sdrc.h" 27#include "sdrc.h"
28#include "sram.h"
30 29
31#define CYCLES_PER_MHZ 1000000 30#define CYCLES_PER_MHZ 1000000
32 31
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index b2dfcd777194..058ce3c0873e 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -22,8 +22,6 @@
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/io.h> 23#include <linux/io.h>
24 24
25#include "../plat-omap/common.h"
26
27#include "clockdomain.h" 25#include "clockdomain.h"
28#include "cm.h" 26#include "cm.h"
29#include "cm33xx.h" 27#include "cm33xx.h"
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index c925c805969f..426fcfcfd821 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -34,8 +34,6 @@
34 34
35#include <asm/proc-fns.h> 35#include <asm/proc-fns.h>
36 36
37#include "../plat-omap/common.h"
38
39#include "i2c.h" 37#include "i2c.h"
40#include "serial.h" 38#include "serial.h"
41 39
@@ -345,5 +343,8 @@ struct omap2_hsmmc_info;
345extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); 343extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
346extern void omap_reserve(void); 344extern void omap_reserve(void);
347 345
346struct omap_hwmod;
347extern int omap_dss_reset(struct omap_hwmod *);
348
348#endif /* __ASSEMBLER__ */ 349#endif /* __ASSEMBLER__ */
349#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ 350#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index b1926cd70468..e5aba58da5d2 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -276,6 +276,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
276 return -ENOMEM; 276 return -ENOMEM;
277 } 277 }
278 278
279 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
280 d->dev_caps |= HS_CHANNELS_RESERVED;
281
279 /* Check the capabilities register for descriptor loading feature */ 282 /* Check the capabilities register for descriptor loading feature */
280 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) 283 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
281 dma_common_ch_end = CCDN; 284 dma_common_ch_end = CCDN;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index e3406dce59be..4a964338992a 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -14,7 +14,6 @@
14#include <linux/string.h> 14#include <linux/string.h>
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/gpio.h> 16#include <linux/gpio.h>
17#include <mach/hardware.h>
18#include <linux/platform_data/gpio-omap.h> 17#include <linux/platform_data/gpio-omap.h>
19 18
20#include "soc.h" 19#include "soc.h"
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index ad55b943108f..4e63097e3cd8 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -109,6 +109,19 @@ int omap_i2c_reset(struct omap_hwmod *oh)
109 return 0; 109 return 0;
110} 110}
111 111
112static int __init omap_i2c_nr_ports(void)
113{
114 int ports = 0;
115
116 if (cpu_is_omap24xx())
117 ports = 2;
118 else if (cpu_is_omap34xx())
119 ports = 3;
120 else if (cpu_is_omap44xx())
121 ports = 4;
122 return ports;
123}
124
112static const char name[] = "omap_i2c"; 125static const char name[] = "omap_i2c";
113 126
114int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata, 127int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
@@ -121,6 +134,9 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata,
121 struct omap_i2c_bus_platform_data *pdata; 134 struct omap_i2c_bus_platform_data *pdata;
122 struct omap_i2c_dev_attr *dev_attr; 135 struct omap_i2c_dev_attr *dev_attr;
123 136
137 if (bus_id > omap_i2c_nr_ports())
138 return -EINVAL;
139
124 omap2_i2c_mux_pins(bus_id); 140 omap2_i2c_mux_pins(bus_id);
125 141
126 l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id); 142 l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id);
diff --git a/arch/arm/mach-omap2/i2c.h b/arch/arm/mach-omap2/i2c.h
index 81dbb992a6bc..42b6f2e7d190 100644
--- a/arch/arm/mach-omap2/i2c.h
+++ b/arch/arm/mach-omap2/i2c.h
@@ -19,7 +19,7 @@
19 * 19 *
20 */ 20 */
21 21
22#include "../plat-omap/i2c.h" 22#include <plat/i2c.h>
23 23
24#ifndef __MACH_OMAP2_I2C_H 24#ifndef __MACH_OMAP2_I2C_H
25#define __MACH_OMAP2_I2C_H 25#define __MACH_OMAP2_I2C_H
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 4b5cbdfac028..cfaed13d0040 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <../mach-omap2/serial.h> 16#include <mach/serial.h>
17 17
18#define UART_OFFSET(addr) ((addr) & 0x00ffffff) 18#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
19 19
diff --git a/arch/arm/mach-omap2/include/mach/gpio.h b/arch/arm/mach-omap2/include/mach/gpio.h
deleted file mode 100644
index 5621cc59c9f4..000000000000
--- a/arch/arm/mach-omap2/include/mach/gpio.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * arch/arm/mach-omap2/include/mach/gpio.h
3 */
diff --git a/arch/arm/mach-omap2/include/mach/serial.h b/arch/arm/mach-omap2/include/mach/serial.h
new file mode 100644
index 000000000000..70eda00db7a4
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/serial.h
@@ -0,0 +1,103 @@
1/*
2 * Copyright (C) 2009 Texas Instruments
3 * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 */
10
11/*
12 * Memory entry used for the DEBUG_LL UART configuration, relative to
13 * start of RAM. See also uncompress.h and debug-macro.S.
14 *
15 * Note that using a memory location for storing the UART configuration
16 * has at least two limitations:
17 *
18 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
19 * uncompress code could then partially overwrite itself
20 * 2. We assume printascii is called at least once before paging_init,
21 * and addruart has a chance to read OMAP_UART_INFO
22 */
23#define OMAP_UART_INFO_OFS 0x3ffc
24
25/* OMAP2 serial ports */
26#define OMAP2_UART1_BASE 0x4806a000
27#define OMAP2_UART2_BASE 0x4806c000
28#define OMAP2_UART3_BASE 0x4806e000
29
30/* OMAP3 serial ports */
31#define OMAP3_UART1_BASE OMAP2_UART1_BASE
32#define OMAP3_UART2_BASE OMAP2_UART2_BASE
33#define OMAP3_UART3_BASE 0x49020000
34#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
35#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
36
37/* OMAP4 serial ports */
38#define OMAP4_UART1_BASE OMAP2_UART1_BASE
39#define OMAP4_UART2_BASE OMAP2_UART2_BASE
40#define OMAP4_UART3_BASE 0x48020000
41#define OMAP4_UART4_BASE 0x4806e000
42
43/* TI81XX serial ports */
44#define TI81XX_UART1_BASE 0x48020000
45#define TI81XX_UART2_BASE 0x48022000
46#define TI81XX_UART3_BASE 0x48024000
47
48/* AM3505/3517 UART4 */
49#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
50
51/* AM33XX serial port */
52#define AM33XX_UART1_BASE 0x44E09000
53
54/* OMAP5 serial ports */
55#define OMAP5_UART1_BASE OMAP2_UART1_BASE
56#define OMAP5_UART2_BASE OMAP2_UART2_BASE
57#define OMAP5_UART3_BASE OMAP4_UART3_BASE
58#define OMAP5_UART4_BASE OMAP4_UART4_BASE
59#define OMAP5_UART5_BASE 0x48066000
60#define OMAP5_UART6_BASE 0x48068000
61
62/* External port on Zoom2/3 */
63#define ZOOM_UART_BASE 0x10000000
64#define ZOOM_UART_VIRT 0xfa400000
65
66#define OMAP_PORT_SHIFT 2
67#define ZOOM_PORT_SHIFT 1
68
69#define OMAP24XX_BASE_BAUD (48000000/16)
70
71/*
72 * DEBUG_LL port encoding stored into the UART1 scratchpad register by
73 * decomp_setup in uncompress.h
74 */
75#define OMAP2UART1 21
76#define OMAP2UART2 22
77#define OMAP2UART3 23
78#define OMAP3UART1 OMAP2UART1
79#define OMAP3UART2 OMAP2UART2
80#define OMAP3UART3 33
81#define OMAP3UART4 34 /* Only on 36xx */
82#define OMAP4UART1 OMAP2UART1
83#define OMAP4UART2 OMAP2UART2
84#define OMAP4UART3 43
85#define OMAP4UART4 44
86#define TI81XXUART1 81
87#define TI81XXUART2 82
88#define TI81XXUART3 83
89#define AM33XXUART1 84
90#define OMAP5UART3 OMAP4UART3
91#define OMAP5UART4 OMAP4UART4
92#define ZOOM_UART 95 /* Only on zoom2/3 */
93
94#ifndef __ASSEMBLER__
95
96struct omap_board_data;
97struct omap_uart_port_info;
98
99extern void omap_serial_init(void);
100extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
101extern void omap_serial_init_port(struct omap_board_data *bdata,
102 struct omap_uart_port_info *platform_data);
103#endif
diff --git a/arch/arm/mach-omap2/include/mach/uncompress.h b/arch/arm/mach-omap2/include/mach/uncompress.h
index 28d1ec0e869a..8e3546d3e041 100644
--- a/arch/arm/mach-omap2/include/mach/uncompress.h
+++ b/arch/arm/mach-omap2/include/mach/uncompress.h
@@ -23,7 +23,7 @@
23#include <asm/memory.h> 23#include <asm/memory.h>
24#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25 25
26#include <../mach-omap2/serial.h> 26#include <mach/serial.h>
27 27
28#define MDR1_MODE_MASK 0x07 28#define MDR1_MODE_MASK 0x07
29 29
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4fadc7895579..807b8d919f81 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -27,8 +27,6 @@
27 27
28#include <plat-omap/dma-omap.h> 28#include <plat-omap/dma-omap.h>
29 29
30#include "../plat-omap/sram.h"
31
32#include "omap_hwmod.h" 30#include "omap_hwmod.h"
33#include "soc.h" 31#include "soc.h"
34#include "iomap.h" 32#include "iomap.h"
@@ -43,6 +41,7 @@
43#include "omap-pm.h" 41#include "omap-pm.h"
44#include "sdrc.h" 42#include "sdrc.h"
45#include "serial.h" 43#include "serial.h"
44#include "sram.h"
46 45
47/* 46/*
48 * The machine specific code may provide the extra mapping besides the 47 * The machine specific code may provide the extra mapping besides the
@@ -354,11 +353,6 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
354 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data); 353 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
355} 354}
356 355
357static void __init omap_common_init_early(void)
358{
359 omap_init_consistent_dma_size();
360}
361
362static void __init omap_hwmod_init_postsetup(void) 356static void __init omap_hwmod_init_postsetup(void)
363{ 357{
364 u8 postsetup_state; 358 u8 postsetup_state;
@@ -379,7 +373,6 @@ void __init omap2420_init_early(void)
379{ 373{
380 omap2_set_globals_242x(); 374 omap2_set_globals_242x();
381 omap2xxx_check_revision(); 375 omap2xxx_check_revision();
382 omap_common_init_early();
383 omap2xxx_voltagedomains_init(); 376 omap2xxx_voltagedomains_init();
384 omap242x_powerdomains_init(); 377 omap242x_powerdomains_init();
385 omap242x_clockdomains_init(); 378 omap242x_clockdomains_init();
@@ -401,7 +394,6 @@ void __init omap2430_init_early(void)
401{ 394{
402 omap2_set_globals_243x(); 395 omap2_set_globals_243x();
403 omap2xxx_check_revision(); 396 omap2xxx_check_revision();
404 omap_common_init_early();
405 omap2xxx_voltagedomains_init(); 397 omap2xxx_voltagedomains_init();
406 omap243x_powerdomains_init(); 398 omap243x_powerdomains_init();
407 omap243x_clockdomains_init(); 399 omap243x_clockdomains_init();
@@ -428,7 +420,6 @@ void __init omap3_init_early(void)
428 omap2_set_globals_3xxx(); 420 omap2_set_globals_3xxx();
429 omap3xxx_check_revision(); 421 omap3xxx_check_revision();
430 omap3xxx_check_features(); 422 omap3xxx_check_features();
431 omap_common_init_early();
432 omap3xxx_voltagedomains_init(); 423 omap3xxx_voltagedomains_init();
433 omap3xxx_powerdomains_init(); 424 omap3xxx_powerdomains_init();
434 omap3xxx_clockdomains_init(); 425 omap3xxx_clockdomains_init();
@@ -462,7 +453,6 @@ void __init ti81xx_init_early(void)
462 omap2_set_globals_ti81xx(); 453 omap2_set_globals_ti81xx();
463 omap3xxx_check_revision(); 454 omap3xxx_check_revision();
464 ti81xx_check_features(); 455 ti81xx_check_features();
465 omap_common_init_early();
466 omap3xxx_voltagedomains_init(); 456 omap3xxx_voltagedomains_init();
467 omap3xxx_powerdomains_init(); 457 omap3xxx_powerdomains_init();
468 omap3xxx_clockdomains_init(); 458 omap3xxx_clockdomains_init();
@@ -520,7 +510,6 @@ void __init am33xx_init_early(void)
520 omap2_set_globals_am33xx(); 510 omap2_set_globals_am33xx();
521 omap3xxx_check_revision(); 511 omap3xxx_check_revision();
522 ti81xx_check_features(); 512 ti81xx_check_features();
523 omap_common_init_early();
524 am33xx_voltagedomains_init(); 513 am33xx_voltagedomains_init();
525 am33xx_powerdomains_init(); 514 am33xx_powerdomains_init();
526 am33xx_clockdomains_init(); 515 am33xx_clockdomains_init();
@@ -536,7 +525,6 @@ void __init omap4430_init_early(void)
536 omap2_set_globals_443x(); 525 omap2_set_globals_443x();
537 omap4xxx_check_revision(); 526 omap4xxx_check_revision();
538 omap4xxx_check_features(); 527 omap4xxx_check_features();
539 omap_common_init_early();
540 omap44xx_voltagedomains_init(); 528 omap44xx_voltagedomains_init();
541 omap44xx_powerdomains_init(); 529 omap44xx_powerdomains_init();
542 omap44xx_clockdomains_init(); 530 omap44xx_clockdomains_init();
@@ -558,7 +546,6 @@ void __init omap5_init_early(void)
558{ 546{
559 omap2_set_globals_5xxx(); 547 omap2_set_globals_5xxx();
560 omap5xxx_check_revision(); 548 omap5xxx_check_revision();
561 omap_common_init_early();
562} 549}
563#endif 550#endif
564 551
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/mach-omap2/omap-pm-noop.c
index 198685b894b0..6a3be2bebddb 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/mach-omap2/omap-pm-noop.c
@@ -22,8 +22,8 @@
22#include <linux/device.h> 22#include <linux/device.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24 24
25#include "../mach-omap2/omap_device.h" 25#include "omap_device.h"
26#include "../mach-omap2/omap-pm.h" 26#include "omap-pm.h"
27 27
28static bool off_mode_enabled; 28static bool off_mode_enabled;
29static int dummy_context_loss_counter; 29static int dummy_context_loss_counter;
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index d25845c471da..3cfcd41bf8fa 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -25,8 +25,6 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/memblock.h> 26#include <asm/memblock.h>
27 27
28#include "../plat-omap/sram.h"
29
30#include "omap-wakeupgen.h" 28#include "omap-wakeupgen.h"
31#include "soc.h" 29#include "soc.h"
32#include "common.h" 30#include "common.h"
@@ -34,6 +32,7 @@
34#include "hsmmc.h" 32#include "hsmmc.h"
35#include "omap4-sar-layout.h" 33#include "omap4-sar-layout.h"
36#include "omap-secure.h" 34#include "omap-secure.h"
35#include "sram.h"
37 36
38#ifdef CONFIG_CACHE_L2X0 37#ifdef CONFIG_CACHE_L2X0
39static void __iomem *l2cache_base; 38static void __iomem *l2cache_base;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index 05c6a5906550..40d6c93d9853 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -12,8 +12,6 @@
12 12
13#include <plat-omap/dma-omap.h> 13#include <plat-omap/dma-omap.h>
14 14
15#include "../plat-omap/common.h"
16
17#include "omap_hwmod.h" 15#include "omap_hwmod.h"
18#include "hdq1w.h" 16#include "hdq1w.h"
19 17
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 5b9be734709c..7a6132848f5d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,8 +30,6 @@
30#include <plat/dmtimer.h> 30#include <plat/dmtimer.h>
31#include <plat/iommu.h> 31#include <plat/iommu.h>
32 32
33#include "../plat-omap/common.h"
34
35#include "omap_hwmod.h" 33#include "omap_hwmod.h"
36#include "omap_hwmod_common_data.h" 34#include "omap_hwmod_common_data.h"
37#include "cm1_44xx.h" 35#include "cm1_44xx.h"
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 83815ddc4786..13e1f4303989 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -31,6 +31,8 @@
31#include <linux/gpio.h> 31#include <linux/gpio.h>
32#include <linux/platform_data/gpio-omap.h> 32#include <linux/platform_data/gpio-omap.h>
33 33
34#include <asm/fncpy.h>
35
34#include <asm/mach/time.h> 36#include <asm/mach/time.h>
35#include <asm/mach/irq.h> 37#include <asm/mach/irq.h>
36#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -38,8 +40,6 @@
38 40
39#include <plat-omap/dma-omap.h> 41#include <plat-omap/dma-omap.h>
40 42
41#include "../plat-omap/sram.h"
42
43#include "soc.h" 43#include "soc.h"
44#include "common.h" 44#include "common.h"
45#include "clock.h" 45#include "clock.h"
@@ -48,6 +48,7 @@
48#include "cm2xxx.h" 48#include "cm2xxx.h"
49#include "cm-regbits-24xx.h" 49#include "cm-regbits-24xx.h"
50#include "sdrc.h" 50#include "sdrc.h"
51#include "sram.h"
51#include "pm.h" 52#include "pm.h"
52#include "control.h" 53#include "control.h"
53#include "powerdomain.h" 54#include "powerdomain.h"
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2f1ad87c1bb0..b16caea312ed 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -32,6 +32,7 @@
32 32
33#include <trace/events/power.h> 33#include <trace/events/power.h>
34 34
35#include <asm/fncpy.h>
35#include <asm/suspend.h> 36#include <asm/suspend.h>
36#include <asm/system_misc.h> 37#include <asm/system_misc.h>
37 38
@@ -40,8 +41,6 @@
40#include <plat/prcm.h> 41#include <plat/prcm.h>
41#include <plat-omap/dma-omap.h> 42#include <plat-omap/dma-omap.h>
42 43
43#include "../plat-omap/sram.h"
44
45#include "soc.h" 44#include "soc.h"
46#include "common.h" 45#include "common.h"
47#include "cm3xxx.h" 46#include "cm3xxx.h"
@@ -51,6 +50,7 @@
51#include "prm3xxx.h" 50#include "prm3xxx.h"
52#include "pm.h" 51#include "pm.h"
53#include "sdrc.h" 52#include "sdrc.h"
53#include "sram.h"
54#include "control.h" 54#include "control.h"
55 55
56/* pm34xx errata defined in pm.h */ 56/* pm34xx errata defined in pm.h */
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 53ec9cbaa3d3..1ac73883f891 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,8 +19,6 @@
19#include <linux/err.h> 19#include <linux/err.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include "../plat-omap/common.h"
23
24#include "common.h" 22#include "common.h"
25#include "powerdomain.h" 23#include "powerdomain.h"
26#include "prm33xx.h" 24#include "prm33xx.h"
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 6c595798c5c5..945b4ad6ab84 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -24,7 +24,6 @@
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26 26
27#include "../plat-omap/common.h"
28#include <plat/prcm.h> 27#include <plat/prcm.h>
29 28
30#include "prm2xxx_3xxx.h" 29#include "prm2xxx_3xxx.h"
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c
index 94d4082f87ed..c64ee1904be8 100644
--- a/arch/arm/mach-omap2/sdrc.c
+++ b/arch/arm/mach-omap2/sdrc.c
@@ -23,8 +23,6 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/io.h> 24#include <linux/io.h>
25 25
26#include "../plat-omap/sram.h"
27
28#include "common.h" 26#include "common.h"
29#include "clock.h" 27#include "clock.h"
30#include "sdrc.h" 28#include "sdrc.h"
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 26c1728e09ca..907291714643 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -24,14 +24,13 @@
24#include <linux/clk.h> 24#include <linux/clk.h>
25#include <linux/io.h> 25#include <linux/io.h>
26 26
27#include "../plat-omap/sram.h"
28
29#include "soc.h" 27#include "soc.h"
30#include "iomap.h" 28#include "iomap.h"
31#include "common.h" 29#include "common.h"
32#include "prm2xxx.h" 30#include "prm2xxx.h"
33#include "clock.h" 31#include "clock.h"
34#include "sdrc.h" 32#include "sdrc.h"
33#include "sram.h"
35 34
36/* Memory timing, DLL mode flags */ 35/* Memory timing, DLL mode flags */
37#define M_DDR 1 36#define M_DDR 1
diff --git a/arch/arm/mach-omap2/serial.h b/arch/arm/mach-omap2/serial.h
index 6a6806271fcf..c4014f013df0 100644
--- a/arch/arm/mach-omap2/serial.h
+++ b/arch/arm/mach-omap2/serial.h
@@ -1,112 +1 @@
1/* #include <mach/serial.h>
2 * arch/arm/plat-omap/include/mach/serial.h
3 *
4 * Copyright (C) 2009 Texas Instruments
5 * Added OMAP4 support- Santosh Shilimkar <santosh.shilimkar@ti.com>
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __ASM_ARCH_SERIAL_H
14#define __ASM_ARCH_SERIAL_H
15
16#include <linux/init.h>
17
18/*
19 * Memory entry used for the DEBUG_LL UART configuration, relative to
20 * start of RAM. See also uncompress.h and debug-macro.S.
21 *
22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations:
24 *
25 * 1. Kernel uncompress code cannot overlap OMAP_UART_INFO as the
26 * uncompress code could then partially overwrite itself
27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO
29 */
30#define OMAP_UART_INFO_OFS 0x3ffc
31
32/* OMAP2 serial ports */
33#define OMAP2_UART1_BASE 0x4806a000
34#define OMAP2_UART2_BASE 0x4806c000
35#define OMAP2_UART3_BASE 0x4806e000
36
37/* OMAP3 serial ports */
38#define OMAP3_UART1_BASE OMAP2_UART1_BASE
39#define OMAP3_UART2_BASE OMAP2_UART2_BASE
40#define OMAP3_UART3_BASE 0x49020000
41#define OMAP3_UART4_BASE 0x49042000 /* Only on 36xx */
42#define OMAP3_UART4_AM35XX_BASE 0x4809E000 /* Only on AM35xx */
43
44/* OMAP4 serial ports */
45#define OMAP4_UART1_BASE OMAP2_UART1_BASE
46#define OMAP4_UART2_BASE OMAP2_UART2_BASE
47#define OMAP4_UART3_BASE 0x48020000
48#define OMAP4_UART4_BASE 0x4806e000
49
50/* TI81XX serial ports */
51#define TI81XX_UART1_BASE 0x48020000
52#define TI81XX_UART2_BASE 0x48022000
53#define TI81XX_UART3_BASE 0x48024000
54
55/* AM3505/3517 UART4 */
56#define AM35XX_UART4_BASE 0x4809E000 /* Only on AM3505/3517 */
57
58/* AM33XX serial port */
59#define AM33XX_UART1_BASE 0x44E09000
60
61/* OMAP5 serial ports */
62#define OMAP5_UART1_BASE OMAP2_UART1_BASE
63#define OMAP5_UART2_BASE OMAP2_UART2_BASE
64#define OMAP5_UART3_BASE OMAP4_UART3_BASE
65#define OMAP5_UART4_BASE OMAP4_UART4_BASE
66#define OMAP5_UART5_BASE 0x48066000
67#define OMAP5_UART6_BASE 0x48068000
68
69/* External port on Zoom2/3 */
70#define ZOOM_UART_BASE 0x10000000
71#define ZOOM_UART_VIRT 0xfa400000
72
73#define OMAP_PORT_SHIFT 2
74#define ZOOM_PORT_SHIFT 1
75
76#define OMAP24XX_BASE_BAUD (48000000/16)
77
78/*
79 * DEBUG_LL port encoding stored into the UART1 scratchpad register by
80 * decomp_setup in uncompress.h
81 */
82#define OMAP2UART1 21
83#define OMAP2UART2 22
84#define OMAP2UART3 23
85#define OMAP3UART1 OMAP2UART1
86#define OMAP3UART2 OMAP2UART2
87#define OMAP3UART3 33
88#define OMAP3UART4 34 /* Only on 36xx */
89#define OMAP4UART1 OMAP2UART1
90#define OMAP4UART2 OMAP2UART2
91#define OMAP4UART3 43
92#define OMAP4UART4 44
93#define TI81XXUART1 81
94#define TI81XXUART2 82
95#define TI81XXUART3 83
96#define AM33XXUART1 84
97#define OMAP5UART3 OMAP4UART3
98#define OMAP5UART4 OMAP4UART4
99#define ZOOM_UART 95 /* Only on zoom2/3 */
100
101#ifndef __ASSEMBLER__
102
103struct omap_board_data;
104struct omap_uart_port_info;
105
106extern void omap_serial_init(void);
107extern void omap_serial_board_init(struct omap_uart_port_info *platform_data);
108extern void omap_serial_init_port(struct omap_board_data *bdata,
109 struct omap_uart_port_info *platform_data);
110#endif
111
112#endif
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 474dba7263e3..d1dedc8195ed 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -26,13 +26,12 @@
26 26
27#include <asm/assembler.h> 27#include <asm/assembler.h>
28 28
29#include "../plat-omap/sram.h"
30
31#include "omap34xx.h" 29#include "omap34xx.h"
32#include "iomap.h" 30#include "iomap.h"
33#include "cm3xxx.h" 31#include "cm3xxx.h"
34#include "prm3xxx.h" 32#include "prm3xxx.h"
35#include "sdrc.h" 33#include "sdrc.h"
34#include "sram.h"
36#include "control.h" 35#include "control.h"
37 36
38/* 37/*
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
new file mode 100644
index 000000000000..0ff0f068bea8
--- /dev/null
+++ b/arch/arm/mach-omap2/sram.c
@@ -0,0 +1,305 @@
1/*
2 *
3 * OMAP SRAM detection and management
4 *
5 * Copyright (C) 2005 Nokia Corporation
6 * Written by Tony Lindgren <tony@atomide.com>
7 *
8 * Copyright (C) 2009-2012 Texas Instruments
9 * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20
21#include <asm/fncpy.h>
22#include <asm/tlb.h>
23#include <asm/cacheflush.h>
24
25#include <asm/mach/map.h>
26
27#include "soc.h"
28#include "iomap.h"
29#include "prm2xxx_3xxx.h"
30#include "sdrc.h"
31#include "sram.h"
32
33#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
34#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
35#ifdef CONFIG_OMAP4_ERRATA_I688
36#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
37#else
38#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
39#endif
40#define OMAP5_SRAM_PA 0x40300000
41
42#define SRAM_BOOTLOADER_SZ 0x00
43
44#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
45#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
46#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
47
48#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
49#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
50#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
51#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
52#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
53
54#define GP_DEVICE 0x300
55
56#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
57
58static unsigned long omap_sram_start;
59static unsigned long omap_sram_skip;
60static unsigned long omap_sram_size;
61
62/*
63 * Depending on the target RAMFS firewall setup, the public usable amount of
64 * SRAM varies. The default accessible size for all device types is 2k. A GP
65 * device allows ARM11 but not other initiators for full size. This
66 * functionality seems ok until some nice security API happens.
67 */
68static int is_sram_locked(void)
69{
70 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
71 /* RAMFW: R/W access to all initiators for all qualifier sets */
72 if (cpu_is_omap242x()) {
73 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
74 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
75 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
76 }
77 if (cpu_is_omap34xx()) {
78 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
79 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
80 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
81 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
82 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
83 }
84 return 0;
85 } else
86 return 1; /* assume locked with no PPA or security driver */
87}
88
89/*
90 * The amount of SRAM depends on the core type.
91 * Note that we cannot try to test for SRAM here because writes
92 * to secure SRAM will hang the system. Also the SRAM is not
93 * yet mapped at this point.
94 */
95static void __init omap_detect_sram(void)
96{
97 omap_sram_skip = SRAM_BOOTLOADER_SZ;
98 if (is_sram_locked()) {
99 if (cpu_is_omap34xx()) {
100 omap_sram_start = OMAP3_SRAM_PUB_PA;
101 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
102 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
103 omap_sram_size = 0x7000; /* 28K */
104 omap_sram_skip += SZ_16K;
105 } else {
106 omap_sram_size = 0x8000; /* 32K */
107 }
108 } else if (cpu_is_omap44xx()) {
109 omap_sram_start = OMAP4_SRAM_PUB_PA;
110 omap_sram_size = 0xa000; /* 40K */
111 } else if (soc_is_omap54xx()) {
112 omap_sram_start = OMAP5_SRAM_PA;
113 omap_sram_size = SZ_128K; /* 128KB */
114 } else {
115 omap_sram_start = OMAP2_SRAM_PUB_PA;
116 omap_sram_size = 0x800; /* 2K */
117 }
118 } else {
119 if (soc_is_am33xx()) {
120 omap_sram_start = AM33XX_SRAM_PA;
121 omap_sram_size = 0x10000; /* 64K */
122 } else if (cpu_is_omap34xx()) {
123 omap_sram_start = OMAP3_SRAM_PA;
124 omap_sram_size = 0x10000; /* 64K */
125 } else if (cpu_is_omap44xx()) {
126 omap_sram_start = OMAP4_SRAM_PA;
127 omap_sram_size = 0xe000; /* 56K */
128 } else if (soc_is_omap54xx()) {
129 omap_sram_start = OMAP5_SRAM_PA;
130 omap_sram_size = SZ_128K; /* 128KB */
131 } else {
132 omap_sram_start = OMAP2_SRAM_PA;
133 if (cpu_is_omap242x())
134 omap_sram_size = 0xa0000; /* 640K */
135 else if (cpu_is_omap243x())
136 omap_sram_size = 0x10000; /* 64K */
137 }
138 }
139}
140
141/*
142 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
143 */
144static void __init omap2_map_sram(void)
145{
146 int cached = 1;
147
148#ifdef CONFIG_OMAP4_ERRATA_I688
149 if (cpu_is_omap44xx()) {
150 omap_sram_start += PAGE_SIZE;
151 omap_sram_size -= SZ_16K;
152 }
153#endif
154 if (cpu_is_omap34xx()) {
155 /*
156 * SRAM must be marked as non-cached on OMAP3 since the
157 * CORE DPLL M2 divider change code (in SRAM) runs with the
158 * SDRAM controller disabled, and if it is marked cached,
159 * the ARM may attempt to write cache lines back to SDRAM
160 * which will cause the system to hang.
161 */
162 cached = 0;
163 }
164
165 omap_map_sram(omap_sram_start, omap_sram_size,
166 omap_sram_skip, cached);
167}
168
169static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
170 u32 base_cs, u32 force_unlock);
171
172void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
173 u32 base_cs, u32 force_unlock)
174{
175 BUG_ON(!_omap2_sram_ddr_init);
176 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
177 base_cs, force_unlock);
178}
179
180static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
181 u32 mem_type);
182
183void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
184{
185 BUG_ON(!_omap2_sram_reprogram_sdrc);
186 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
187}
188
189static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
190
191u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
192{
193 BUG_ON(!_omap2_set_prcm);
194 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
195}
196
197#ifdef CONFIG_SOC_OMAP2420
198static int __init omap242x_sram_init(void)
199{
200 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
201 omap242x_sram_ddr_init_sz);
202
203 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
204 omap242x_sram_reprogram_sdrc_sz);
205
206 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
207 omap242x_sram_set_prcm_sz);
208
209 return 0;
210}
211#else
212static inline int omap242x_sram_init(void)
213{
214 return 0;
215}
216#endif
217
218#ifdef CONFIG_SOC_OMAP2430
219static int __init omap243x_sram_init(void)
220{
221 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
222 omap243x_sram_ddr_init_sz);
223
224 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
225 omap243x_sram_reprogram_sdrc_sz);
226
227 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
228 omap243x_sram_set_prcm_sz);
229
230 return 0;
231}
232#else
233static inline int omap243x_sram_init(void)
234{
235 return 0;
236}
237#endif
238
239#ifdef CONFIG_ARCH_OMAP3
240
241static u32 (*_omap3_sram_configure_core_dpll)(
242 u32 m2, u32 unlock_dll, u32 f, u32 inc,
243 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
244 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
245 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
246 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
247
248u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
249 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
250 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
251 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
252 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
253{
254 BUG_ON(!_omap3_sram_configure_core_dpll);
255 return _omap3_sram_configure_core_dpll(
256 m2, unlock_dll, f, inc,
257 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
258 sdrc_actim_ctrl_b_0, sdrc_mr_0,
259 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
260 sdrc_actim_ctrl_b_1, sdrc_mr_1);
261}
262
263void omap3_sram_restore_context(void)
264{
265 omap_sram_reset();
266
267 _omap3_sram_configure_core_dpll =
268 omap_sram_push(omap3_sram_configure_core_dpll,
269 omap3_sram_configure_core_dpll_sz);
270 omap_push_sram_idle();
271}
272
273static inline int omap34xx_sram_init(void)
274{
275 omap3_sram_restore_context();
276 return 0;
277}
278#else
279static inline int omap34xx_sram_init(void)
280{
281 return 0;
282}
283#endif /* CONFIG_ARCH_OMAP3 */
284
285static inline int am33xx_sram_init(void)
286{
287 return 0;
288}
289
290int __init omap_sram_init(void)
291{
292 omap_detect_sram();
293 omap2_map_sram();
294
295 if (cpu_is_omap242x())
296 omap242x_sram_init();
297 else if (cpu_is_omap2430())
298 omap243x_sram_init();
299 else if (soc_is_am33xx())
300 am33xx_sram_init();
301 else if (cpu_is_omap34xx())
302 omap34xx_sram_init();
303
304 return 0;
305}
diff --git a/arch/arm/plat-omap/sram.h b/arch/arm/mach-omap2/sram.h
index cefda2e09869..ca7277c2a9ee 100644
--- a/arch/arm/plat-omap/sram.h
+++ b/arch/arm/mach-omap2/sram.h
@@ -1,6 +1,4 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/sram.h
3 *
4 * Interface for functions that need to be run in internal SRAM 2 * Interface for functions that need to be run in internal SRAM
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
@@ -8,26 +6,8 @@
8 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
9 */ 7 */
10 8
11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H
13
14#ifndef __ASSEMBLY__ 9#ifndef __ASSEMBLY__
15#include <asm/fncpy.h> 10#include <plat/sram.h>
16
17int __init omap_sram_init(void);
18
19extern void *omap_sram_push_address(unsigned long size);
20
21/* Macro to push a function to the internal SRAM, using the fncpy API */
22#define omap_sram_push(funcp, size) ({ \
23 typeof(&(funcp)) _res = NULL; \
24 void *_sram_address = omap_sram_push_address(size); \
25 if (_sram_address) \
26 _res = fncpy(_sram_address, &(funcp), size); \
27 _res; \
28})
29
30extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
31 11
32extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 12extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
33 u32 base_cs, u32 force_unlock); 13 u32 base_cs, u32 force_unlock);
@@ -44,9 +24,6 @@ extern u32 omap3_configure_core_dpll(
44extern void omap3_sram_restore_context(void); 24extern void omap3_sram_restore_context(void);
45 25
46/* Do not use these */ 26/* Do not use these */
47extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
48extern unsigned long omap1_sram_reprogram_clock_sz;
49
50extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl); 27extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
51extern unsigned long omap24xx_sram_reprogram_clock_sz; 28extern unsigned long omap24xx_sram_reprogram_clock_sz;
52 29
@@ -104,4 +81,3 @@ static inline void omap_push_sram_idle(void) {}
104#define OMAP4_SRAM_PA 0x40300000 81#define OMAP4_SRAM_PA 0x40300000
105#endif 82#endif
106#define AM33XX_SRAM_PA 0x40300000 83#define AM33XX_SRAM_PA 0x40300000
107#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 565e5755c9bc..c5bc2cb4d8d3 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -45,6 +45,7 @@
45#include <asm/arch_timer.h> 45#include <asm/arch_timer.h>
46#include "omap_hwmod.h" 46#include "omap_hwmod.h"
47#include "omap_device.h" 47#include "omap_device.h"
48#include <plat/counter-32k.h>
48#include <plat/dmtimer.h> 49#include <plat/dmtimer.h>
49#include "omap-pm.h" 50#include "omap-pm.h"
50 51
@@ -559,6 +560,8 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
559 if (timer_dev_attr) 560 if (timer_dev_attr)
560 pdata->timer_capability = timer_dev_attr->timer_capability; 561 pdata->timer_capability = timer_dev_attr->timer_capability;
561 562
563 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
564
562 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 565 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
563 NULL, 0, 0); 566 NULL, 0, 0);
564 567
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 4bd0ace20e98..8d885848600a 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o dma.o fb.o counter_32k.o 6obj-y := sram.o dma.o fb.o counter_32k.o
7obj-m := 7obj-m :=
8obj-n := 8obj-n :=
9obj- := 9obj- :=
@@ -19,4 +19,3 @@ obj-y += $(i2c-omap-m) $(i2c-omap-y)
19# OMAP mailbox framework 19# OMAP mailbox framework
20obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o 20obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o
21 21
22obj-$(CONFIG_OMAP_PM_NOOP) += omap-pm-noop.o
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
deleted file mode 100644
index a1555e028123..000000000000
--- a/arch/arm/plat-omap/common.c
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * linux/arch/arm/plat-omap/common.c
3 *
4 * Code common to all OMAP machines.
5 * The file is created by Tony Lindgren <tony@atomide.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/dma-mapping.h>
18
19#include "common.h"
20#include <plat-omap/dma-omap.h>
21
22void __init omap_init_consistent_dma_size(void)
23{
24#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
25 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
26#endif
27}
diff --git a/arch/arm/plat-omap/common.h b/arch/arm/plat-omap/common.h
deleted file mode 100644
index 8ae0542a37d9..000000000000
--- a/arch/arm/plat-omap/common.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Header for shared OMAP code in plat-omap.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
26#define __ARCH_ARM_MACH_OMAP_COMMON_H
27
28extern int __init omap_init_clocksource_32k(void __iomem *vbase);
29
30extern void __init omap_check_revision(void);
31
32extern void omap_reserve(void);
33struct omap_hwmod;
34extern int omap_dss_reset(struct omap_hwmod *);
35
36#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 66bf3f9324fe..f3771cdb9838 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -22,8 +22,6 @@
22#include <asm/mach/time.h> 22#include <asm/mach/time.h>
23#include <asm/sched_clock.h> 23#include <asm/sched_clock.h>
24 24
25#include "common.h"
26
27/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ 25/* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */
28#define OMAP2_32KSYNCNT_REV_OFF 0x0 26#define OMAP2_32KSYNCNT_REV_OFF 0x0
29#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) 27#define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30)
diff --git a/arch/arm/plat-omap/debug-devices.c b/arch/arm/plat-omap/debug-devices.c
index 5a4678edd65a..a609e2161817 100644
--- a/arch/arm/plat-omap/debug-devices.c
+++ b/arch/arm/plat-omap/debug-devices.c
@@ -15,8 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/smc91x.h> 16#include <linux/smc91x.h>
17 17
18#include <mach/hardware.h> 18#include <plat/debug-devices.h>
19#include "../mach-omap2/debug-devices.h"
20 19
21/* Many OMAP development platforms reuse the same "debug board"; these 20/* Many OMAP development platforms reuse the same "debug board"; these
22 * platforms include H2, H3, H4, and Perseus2. 21 * platforms include H2, H3, H4, and Perseus2.
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index feca128bc8ed..c43ea21f33b4 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -17,16 +17,33 @@
17#include <linux/platform_data/gpio-omap.h> 17#include <linux/platform_data/gpio-omap.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19 19
20#include <mach/hardware.h>
21#include <asm/mach-types.h> 20#include <asm/mach-types.h>
22 21
23#include "fpga.h"
24
25/* Many OMAP development platforms reuse the same "debug board"; these 22/* Many OMAP development platforms reuse the same "debug board"; these
26 * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the 23 * platforms include H2, H3, H4, and Perseus2. There are 16 LEDs on the
27 * debug board (all green), accessed through FPGA registers. 24 * debug board (all green), accessed through FPGA registers.
28 */ 25 */
29 26
27/* NOTE: most boards don't have a static mapping for the FPGA ... */
28struct h2p2_dbg_fpga {
29 /* offset 0x00 */
30 u16 smc91x[8];
31 /* offset 0x10 */
32 u16 fpga_rev;
33 u16 board_rev;
34 u16 gpio_outputs;
35 u16 leds;
36 /* offset 0x18 */
37 u16 misc_inputs;
38 u16 lan_status;
39 u16 lan_reset;
40 u16 reserved0;
41 /* offset 0x20 */
42 u16 ps2_data;
43 u16 ps2_ctrl;
44 /* plus also 4 rs232 ports ... */
45};
46
30static struct h2p2_dbg_fpga __iomem *fpga; 47static struct h2p2_dbg_fpga __iomem *fpga;
31 48
32static u16 fpga_led_state; 49static u16 fpga_led_state;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 49803cc18787..c288b76f8e6c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -38,9 +38,6 @@
38 38
39#include <plat-omap/dma-omap.h> 39#include <plat-omap/dma-omap.h>
40 40
41#include "../mach-omap1/soc.h"
42#include "../mach-omap2/soc.h"
43
44/* 41/*
45 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA 42 * MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
46 * channels that an instance of the SDMA IP block can support. Used 43 * channels that an instance of the SDMA IP block can support. Used
@@ -182,7 +179,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
182 unsigned long reg; 179 unsigned long reg;
183 u32 l; 180 u32 l;
184 181
185 if (cpu_class_is_omap1()) { 182 if (dma_omap1()) {
186 switch (dst_port) { 183 switch (dst_port) {
187 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */ 184 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
188 reg = OMAP_TC_OCPT1_PRIOR; 185 reg = OMAP_TC_OCPT1_PRIOR;
@@ -234,7 +231,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
234 l |= data_type; 231 l |= data_type;
235 p->dma_write(l, CSDP, lch); 232 p->dma_write(l, CSDP, lch);
236 233
237 if (cpu_class_is_omap1()) { 234 if (dma_omap1()) {
238 u16 ccr; 235 u16 ccr;
239 236
240 ccr = p->dma_read(CCR, lch); 237 ccr = p->dma_read(CCR, lch);
@@ -250,7 +247,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
250 p->dma_write(ccr, CCR2, lch); 247 p->dma_write(ccr, CCR2, lch);
251 } 248 }
252 249
253 if (cpu_class_is_omap2() && dma_trigger) { 250 if (dma_omap2plus() && dma_trigger) {
254 u32 val; 251 u32 val;
255 252
256 val = p->dma_read(CCR, lch); 253 val = p->dma_read(CCR, lch);
@@ -290,7 +287,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
290{ 287{
291 BUG_ON(omap_dma_in_1510_mode()); 288 BUG_ON(omap_dma_in_1510_mode());
292 289
293 if (cpu_class_is_omap1()) { 290 if (dma_omap1()) {
294 u16 w; 291 u16 w;
295 292
296 w = p->dma_read(CCR2, lch); 293 w = p->dma_read(CCR2, lch);
@@ -320,7 +317,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
320 p->dma_write(w, LCH_CTRL, lch); 317 p->dma_write(w, LCH_CTRL, lch);
321 } 318 }
322 319
323 if (cpu_class_is_omap2()) { 320 if (dma_omap2plus()) {
324 u32 val; 321 u32 val;
325 322
326 val = p->dma_read(CCR, lch); 323 val = p->dma_read(CCR, lch);
@@ -348,7 +345,7 @@ EXPORT_SYMBOL(omap_set_dma_color_mode);
348 345
349void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 346void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
350{ 347{
351 if (cpu_class_is_omap2()) { 348 if (dma_omap2plus()) {
352 u32 csdp; 349 u32 csdp;
353 350
354 csdp = p->dma_read(CSDP, lch); 351 csdp = p->dma_read(CSDP, lch);
@@ -361,7 +358,7 @@ EXPORT_SYMBOL(omap_set_dma_write_mode);
361 358
362void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode) 359void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
363{ 360{
364 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { 361 if (dma_omap1() && !dma_omap15xx()) {
365 u32 l; 362 u32 l;
366 363
367 l = p->dma_read(LCH_CTRL, lch); 364 l = p->dma_read(LCH_CTRL, lch);
@@ -379,7 +376,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
379{ 376{
380 u32 l; 377 u32 l;
381 378
382 if (cpu_class_is_omap1()) { 379 if (dma_omap1()) {
383 u16 w; 380 u16 w;
384 381
385 w = p->dma_read(CSDP, lch); 382 w = p->dma_read(CSDP, lch);
@@ -421,7 +418,7 @@ EXPORT_SYMBOL(omap_set_dma_params);
421 418
422void omap_set_dma_src_index(int lch, int eidx, int fidx) 419void omap_set_dma_src_index(int lch, int eidx, int fidx)
423{ 420{
424 if (cpu_class_is_omap2()) 421 if (dma_omap2plus())
425 return; 422 return;
426 423
427 p->dma_write(eidx, CSEI, lch); 424 p->dma_write(eidx, CSEI, lch);
@@ -453,13 +450,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
453 case OMAP_DMA_DATA_BURST_DIS: 450 case OMAP_DMA_DATA_BURST_DIS:
454 break; 451 break;
455 case OMAP_DMA_DATA_BURST_4: 452 case OMAP_DMA_DATA_BURST_4:
456 if (cpu_class_is_omap2()) 453 if (dma_omap2plus())
457 burst = 0x1; 454 burst = 0x1;
458 else 455 else
459 burst = 0x2; 456 burst = 0x2;
460 break; 457 break;
461 case OMAP_DMA_DATA_BURST_8: 458 case OMAP_DMA_DATA_BURST_8:
462 if (cpu_class_is_omap2()) { 459 if (dma_omap2plus()) {
463 burst = 0x2; 460 burst = 0x2;
464 break; 461 break;
465 } 462 }
@@ -469,7 +466,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
469 * fall through 466 * fall through
470 */ 467 */
471 case OMAP_DMA_DATA_BURST_16: 468 case OMAP_DMA_DATA_BURST_16:
472 if (cpu_class_is_omap2()) { 469 if (dma_omap2plus()) {
473 burst = 0x3; 470 burst = 0x3;
474 break; 471 break;
475 } 472 }
@@ -493,7 +490,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
493{ 490{
494 u32 l; 491 u32 l;
495 492
496 if (cpu_class_is_omap1()) { 493 if (dma_omap1()) {
497 l = p->dma_read(CSDP, lch); 494 l = p->dma_read(CSDP, lch);
498 l &= ~(0x1f << 9); 495 l &= ~(0x1f << 9);
499 l |= dest_port << 9; 496 l |= dest_port << 9;
@@ -514,7 +511,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_params);
514 511
515void omap_set_dma_dest_index(int lch, int eidx, int fidx) 512void omap_set_dma_dest_index(int lch, int eidx, int fidx)
516{ 513{
517 if (cpu_class_is_omap2()) 514 if (dma_omap2plus())
518 return; 515 return;
519 516
520 p->dma_write(eidx, CDEI, lch); 517 p->dma_write(eidx, CDEI, lch);
@@ -546,19 +543,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
546 case OMAP_DMA_DATA_BURST_DIS: 543 case OMAP_DMA_DATA_BURST_DIS:
547 break; 544 break;
548 case OMAP_DMA_DATA_BURST_4: 545 case OMAP_DMA_DATA_BURST_4:
549 if (cpu_class_is_omap2()) 546 if (dma_omap2plus())
550 burst = 0x1; 547 burst = 0x1;
551 else 548 else
552 burst = 0x2; 549 burst = 0x2;
553 break; 550 break;
554 case OMAP_DMA_DATA_BURST_8: 551 case OMAP_DMA_DATA_BURST_8:
555 if (cpu_class_is_omap2()) 552 if (dma_omap2plus())
556 burst = 0x2; 553 burst = 0x2;
557 else 554 else
558 burst = 0x3; 555 burst = 0x3;
559 break; 556 break;
560 case OMAP_DMA_DATA_BURST_16: 557 case OMAP_DMA_DATA_BURST_16:
561 if (cpu_class_is_omap2()) { 558 if (dma_omap2plus()) {
562 burst = 0x3; 559 burst = 0x3;
563 break; 560 break;
564 } 561 }
@@ -579,7 +576,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
579static inline void omap_enable_channel_irq(int lch) 576static inline void omap_enable_channel_irq(int lch)
580{ 577{
581 /* Clear CSR */ 578 /* Clear CSR */
582 if (cpu_class_is_omap1()) 579 if (dma_omap1())
583 p->dma_read(CSR, lch); 580 p->dma_read(CSR, lch);
584 else 581 else
585 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 582 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -593,7 +590,7 @@ static inline void omap_disable_channel_irq(int lch)
593 /* disable channel interrupts */ 590 /* disable channel interrupts */
594 p->dma_write(0, CICR, lch); 591 p->dma_write(0, CICR, lch);
595 /* Clear CSR */ 592 /* Clear CSR */
596 if (cpu_class_is_omap1()) 593 if (dma_omap1())
597 p->dma_read(CSR, lch); 594 p->dma_read(CSR, lch);
598 else 595 else
599 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); 596 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
@@ -617,7 +614,7 @@ static inline void enable_lnk(int lch)
617 614
618 l = p->dma_read(CLNK_CTRL, lch); 615 l = p->dma_read(CLNK_CTRL, lch);
619 616
620 if (cpu_class_is_omap1()) 617 if (dma_omap1())
621 l &= ~(1 << 14); 618 l &= ~(1 << 14);
622 619
623 /* Set the ENABLE_LNK bits */ 620 /* Set the ENABLE_LNK bits */
@@ -625,7 +622,7 @@ static inline void enable_lnk(int lch)
625 l = dma_chan[lch].next_lch | (1 << 15); 622 l = dma_chan[lch].next_lch | (1 << 15);
626 623
627#ifndef CONFIG_ARCH_OMAP1 624#ifndef CONFIG_ARCH_OMAP1
628 if (cpu_class_is_omap2()) 625 if (dma_omap2plus())
629 if (dma_chan[lch].next_linked_ch != -1) 626 if (dma_chan[lch].next_linked_ch != -1)
630 l = dma_chan[lch].next_linked_ch | (1 << 15); 627 l = dma_chan[lch].next_linked_ch | (1 << 15);
631#endif 628#endif
@@ -642,12 +639,12 @@ static inline void disable_lnk(int lch)
642 /* Disable interrupts */ 639 /* Disable interrupts */
643 omap_disable_channel_irq(lch); 640 omap_disable_channel_irq(lch);
644 641
645 if (cpu_class_is_omap1()) { 642 if (dma_omap1()) {
646 /* Set the STOP_LNK bit */ 643 /* Set the STOP_LNK bit */
647 l |= 1 << 14; 644 l |= 1 << 14;
648 } 645 }
649 646
650 if (cpu_class_is_omap2()) { 647 if (dma_omap2plus()) {
651 /* Clear the ENABLE_LNK bit */ 648 /* Clear the ENABLE_LNK bit */
652 l &= ~(1 << 15); 649 l &= ~(1 << 15);
653 } 650 }
@@ -661,7 +658,7 @@ static inline void omap2_enable_irq_lch(int lch)
661 u32 val; 658 u32 val;
662 unsigned long flags; 659 unsigned long flags;
663 660
664 if (!cpu_class_is_omap2()) 661 if (dma_omap1())
665 return; 662 return;
666 663
667 spin_lock_irqsave(&dma_chan_lock, flags); 664 spin_lock_irqsave(&dma_chan_lock, flags);
@@ -679,7 +676,7 @@ static inline void omap2_disable_irq_lch(int lch)
679 u32 val; 676 u32 val;
680 unsigned long flags; 677 unsigned long flags;
681 678
682 if (!cpu_class_is_omap2()) 679 if (dma_omap1())
683 return; 680 return;
684 681
685 spin_lock_irqsave(&dma_chan_lock, flags); 682 spin_lock_irqsave(&dma_chan_lock, flags);
@@ -718,7 +715,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
718 if (p->clear_lch_regs) 715 if (p->clear_lch_regs)
719 p->clear_lch_regs(free_ch); 716 p->clear_lch_regs(free_ch);
720 717
721 if (cpu_class_is_omap2()) 718 if (dma_omap2plus())
722 omap_clear_dma(free_ch); 719 omap_clear_dma(free_ch);
723 720
724 spin_unlock_irqrestore(&dma_chan_lock, flags); 721 spin_unlock_irqrestore(&dma_chan_lock, flags);
@@ -729,7 +726,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
729 chan->flags = 0; 726 chan->flags = 0;
730 727
731#ifndef CONFIG_ARCH_OMAP1 728#ifndef CONFIG_ARCH_OMAP1
732 if (cpu_class_is_omap2()) { 729 if (dma_omap2plus()) {
733 chan->chain_id = -1; 730 chan->chain_id = -1;
734 chan->next_linked_ch = -1; 731 chan->next_linked_ch = -1;
735 } 732 }
@@ -737,13 +734,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
737 734
738 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 735 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
739 736
740 if (cpu_class_is_omap1()) 737 if (dma_omap1())
741 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ; 738 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
742 else if (cpu_class_is_omap2()) 739 else if (dma_omap2plus())
743 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ | 740 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
744 OMAP2_DMA_TRANS_ERR_IRQ; 741 OMAP2_DMA_TRANS_ERR_IRQ;
745 742
746 if (cpu_is_omap16xx()) { 743 if (dma_omap16xx()) {
747 /* If the sync device is set, configure it dynamically. */ 744 /* If the sync device is set, configure it dynamically. */
748 if (dev_id != 0) { 745 if (dev_id != 0) {
749 set_gdma_dev(free_ch + 1, dev_id); 746 set_gdma_dev(free_ch + 1, dev_id);
@@ -754,11 +751,11 @@ int omap_request_dma(int dev_id, const char *dev_name,
754 * id. 751 * id.
755 */ 752 */
756 p->dma_write(dev_id | (1 << 10), CCR, free_ch); 753 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
757 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { 754 } else if (dma_omap1()) {
758 p->dma_write(dev_id, CCR, free_ch); 755 p->dma_write(dev_id, CCR, free_ch);
759 } 756 }
760 757
761 if (cpu_class_is_omap2()) { 758 if (dma_omap2plus()) {
762 omap_enable_channel_irq(free_ch); 759 omap_enable_channel_irq(free_ch);
763 omap2_enable_irq_lch(free_ch); 760 omap2_enable_irq_lch(free_ch);
764 } 761 }
@@ -780,7 +777,7 @@ void omap_free_dma(int lch)
780 } 777 }
781 778
782 /* Disable interrupt for logical channel */ 779 /* Disable interrupt for logical channel */
783 if (cpu_class_is_omap2()) 780 if (dma_omap2plus())
784 omap2_disable_irq_lch(lch); 781 omap2_disable_irq_lch(lch);
785 782
786 /* Disable all DMA interrupts for the channel. */ 783 /* Disable all DMA interrupts for the channel. */
@@ -790,7 +787,7 @@ void omap_free_dma(int lch)
790 p->dma_write(0, CCR, lch); 787 p->dma_write(0, CCR, lch);
791 788
792 /* Clear registers */ 789 /* Clear registers */
793 if (cpu_class_is_omap2()) 790 if (dma_omap2plus())
794 omap_clear_dma(lch); 791 omap_clear_dma(lch);
795 792
796 spin_lock_irqsave(&dma_chan_lock, flags); 793 spin_lock_irqsave(&dma_chan_lock, flags);
@@ -816,7 +813,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
816{ 813{
817 u32 reg; 814 u32 reg;
818 815
819 if (!cpu_class_is_omap2()) { 816 if (dma_omap1()) {
820 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__); 817 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
821 return; 818 return;
822 } 819 }
@@ -855,7 +852,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
855 } 852 }
856 l = p->dma_read(CCR, lch); 853 l = p->dma_read(CCR, lch);
857 l &= ~((1 << 6) | (1 << 26)); 854 l &= ~((1 << 6) | (1 << 26));
858 if (cpu_class_is_omap2() && !cpu_is_omap242x()) 855 if (d->dev_caps & IS_RW_PRIORITY)
859 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 856 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
860 else 857 else
861 l |= ((read_prio & 0x1) << 6); 858 l |= ((read_prio & 0x1) << 6);
@@ -888,7 +885,7 @@ void omap_start_dma(int lch)
888 * The CPC/CDAC register needs to be initialized to zero 885 * The CPC/CDAC register needs to be initialized to zero
889 * before starting dma transfer. 886 * before starting dma transfer.
890 */ 887 */
891 if (cpu_is_omap15xx()) 888 if (dma_omap15xx())
892 p->dma_write(0, CPC, lch); 889 p->dma_write(0, CPC, lch);
893 else 890 else
894 p->dma_write(0, CDAC, lch); 891 p->dma_write(0, CDAC, lch);
@@ -1051,7 +1048,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
1051{ 1048{
1052 dma_addr_t offset = 0; 1049 dma_addr_t offset = 0;
1053 1050
1054 if (cpu_is_omap15xx()) 1051 if (dma_omap15xx())
1055 offset = p->dma_read(CPC, lch); 1052 offset = p->dma_read(CPC, lch);
1056 else 1053 else
1057 offset = p->dma_read(CSAC, lch); 1054 offset = p->dma_read(CSAC, lch);
@@ -1059,7 +1056,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
1059 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0) 1056 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1060 offset = p->dma_read(CSAC, lch); 1057 offset = p->dma_read(CSAC, lch);
1061 1058
1062 if (!cpu_is_omap15xx()) { 1059 if (!dma_omap15xx()) {
1063 /* 1060 /*
1064 * CDAC == 0 indicates that the DMA transfer on the channel has 1061 * CDAC == 0 indicates that the DMA transfer on the channel has
1065 * not been started (no data has been transferred so far). 1062 * not been started (no data has been transferred so far).
@@ -1071,7 +1068,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
1071 offset = p->dma_read(CSSA, lch); 1068 offset = p->dma_read(CSSA, lch);
1072 } 1069 }
1073 1070
1074 if (cpu_class_is_omap1()) 1071 if (dma_omap1())
1075 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000); 1072 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1076 1073
1077 return offset; 1074 return offset;
@@ -1090,7 +1087,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1090{ 1087{
1091 dma_addr_t offset = 0; 1088 dma_addr_t offset = 0;
1092 1089
1093 if (cpu_is_omap15xx()) 1090 if (dma_omap15xx())
1094 offset = p->dma_read(CPC, lch); 1091 offset = p->dma_read(CPC, lch);
1095 else 1092 else
1096 offset = p->dma_read(CDAC, lch); 1093 offset = p->dma_read(CDAC, lch);
@@ -1099,7 +1096,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1099 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is 1096 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1100 * read before the DMA controller finished disabling the channel. 1097 * read before the DMA controller finished disabling the channel.
1101 */ 1098 */
1102 if (!cpu_is_omap15xx() && offset == 0) { 1099 if (!dma_omap15xx() && offset == 0) {
1103 offset = p->dma_read(CDAC, lch); 1100 offset = p->dma_read(CDAC, lch);
1104 /* 1101 /*
1105 * CDAC == 0 indicates that the DMA transfer on the channel has 1102 * CDAC == 0 indicates that the DMA transfer on the channel has
@@ -1110,7 +1107,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
1110 offset = p->dma_read(CDSA, lch); 1107 offset = p->dma_read(CDSA, lch);
1111 } 1108 }
1112 1109
1113 if (cpu_class_is_omap1()) 1110 if (dma_omap1())
1114 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000); 1111 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1115 1112
1116 return offset; 1113 return offset;
@@ -1127,7 +1124,7 @@ int omap_dma_running(void)
1127{ 1124{
1128 int lch; 1125 int lch;
1129 1126
1130 if (cpu_class_is_omap1()) 1127 if (dma_omap1())
1131 if (omap_lcd_dma_running()) 1128 if (omap_lcd_dma_running())
1132 return 1; 1129 return 1;
1133 1130
@@ -2030,7 +2027,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2030 dma_chan = d->chan; 2027 dma_chan = d->chan;
2031 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; 2028 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2032 2029
2033 if (cpu_class_is_omap2()) { 2030 if (dma_omap2plus()) {
2034 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) * 2031 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2035 dma_lch_count, GFP_KERNEL); 2032 dma_lch_count, GFP_KERNEL);
2036 if (!dma_linked_lch) { 2033 if (!dma_linked_lch) {
@@ -2042,7 +2039,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2042 spin_lock_init(&dma_chan_lock); 2039 spin_lock_init(&dma_chan_lock);
2043 for (ch = 0; ch < dma_chan_count; ch++) { 2040 for (ch = 0; ch < dma_chan_count; ch++) {
2044 omap_clear_dma(ch); 2041 omap_clear_dma(ch);
2045 if (cpu_class_is_omap2()) 2042 if (dma_omap2plus())
2046 omap2_disable_irq_lch(ch); 2043 omap2_disable_irq_lch(ch);
2047 2044
2048 dma_chan[ch].dev_id = -1; 2045 dma_chan[ch].dev_id = -1;
@@ -2051,7 +2048,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2051 if (ch >= 6 && enable_1510_mode) 2048 if (ch >= 6 && enable_1510_mode)
2052 continue; 2049 continue;
2053 2050
2054 if (cpu_class_is_omap1()) { 2051 if (dma_omap1()) {
2055 /* 2052 /*
2056 * request_irq() doesn't like dev_id (ie. ch) being 2053 * request_irq() doesn't like dev_id (ie. ch) being
2057 * zero, so we have to kludge around this. 2054 * zero, so we have to kludge around this.
@@ -2076,11 +2073,11 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2076 } 2073 }
2077 } 2074 }
2078 2075
2079 if (cpu_class_is_omap2() && !cpu_is_omap242x()) 2076 if (d->dev_caps & IS_RW_PRIORITY)
2080 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 2077 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2081 DMA_DEFAULT_FIFO_DEPTH, 0); 2078 DMA_DEFAULT_FIFO_DEPTH, 0);
2082 2079
2083 if (cpu_class_is_omap2()) { 2080 if (dma_omap2plus()) {
2084 strcpy(irq_name, "0"); 2081 strcpy(irq_name, "0");
2085 dma_irq = platform_get_irq_byname(pdev, irq_name); 2082 dma_irq = platform_get_irq_byname(pdev, irq_name);
2086 if (dma_irq < 0) { 2083 if (dma_irq < 0) {
@@ -2095,9 +2092,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
2095 } 2092 }
2096 } 2093 }
2097 2094
2098 /* reserve dma channels 0 and 1 in high security devices */ 2095 /* reserve dma channels 0 and 1 in high security devices on 34xx */
2099 if (cpu_is_omap34xx() && 2096 if (d->dev_caps & HS_CHANNELS_RESERVED) {
2100 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2101 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n"); 2097 pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
2102 dma_chan[0].dev_id = 0; 2098 dma_chan[0].dev_id = 0;
2103 dma_chan[1].dev_id = 1; 2099 dma_chan[1].dev_id = 1;
@@ -2124,7 +2120,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2124{ 2120{
2125 int dma_irq; 2121 int dma_irq;
2126 2122
2127 if (cpu_class_is_omap2()) { 2123 if (dma_omap2plus()) {
2128 char irq_name[4]; 2124 char irq_name[4];
2129 strcpy(irq_name, "0"); 2125 strcpy(irq_name, "0");
2130 dma_irq = platform_get_irq_byname(pdev, irq_name); 2126 dma_irq = platform_get_irq_byname(pdev, irq_name);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 4a0b30a4ebda..82231a75abd6 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -43,10 +43,6 @@
43 43
44#include <plat/dmtimer.h> 44#include <plat/dmtimer.h>
45 45
46#include <mach/hardware.h>
47
48#include "../mach-omap2/omap-pm.h"
49
50static u32 omap_reserved_systimers; 46static u32 omap_reserved_systimers;
51static LIST_HEAD(omap_timer_list); 47static LIST_HEAD(omap_timer_list);
52static DEFINE_SPINLOCK(dm_timer_lock); 48static DEFINE_SPINLOCK(dm_timer_lock);
@@ -272,7 +268,7 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
272EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); 268EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
273 269
274#if defined(CONFIG_ARCH_OMAP1) 270#if defined(CONFIG_ARCH_OMAP1)
275 271#include <mach/hardware.h>
276/** 272/**
277 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR 273 * omap_dm_timer_modify_idlect_mask - Check if any running timers use ARMXOR
278 * @inputmask: current value of idlect mask 274 * @inputmask: current value of idlect mask
@@ -349,7 +345,8 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
349 omap_dm_timer_enable(timer); 345 omap_dm_timer_enable(timer);
350 346
351 if (!(timer->capability & OMAP_TIMER_ALWON)) { 347 if (!(timer->capability & OMAP_TIMER_ALWON)) {
352 if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != 348 if (timer->get_context_loss_count &&
349 timer->get_context_loss_count(&timer->pdev->dev) !=
353 timer->ctx_loss_count) 350 timer->ctx_loss_count)
354 omap_timer_restore_context(timer); 351 omap_timer_restore_context(timer);
355 } 352 }
@@ -378,9 +375,11 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
378 375
379 __omap_dm_timer_stop(timer, timer->posted, rate); 376 __omap_dm_timer_stop(timer, timer->posted, rate);
380 377
381 if (!(timer->capability & OMAP_TIMER_ALWON)) 378 if (!(timer->capability & OMAP_TIMER_ALWON)) {
382 timer->ctx_loss_count = 379 if (timer->get_context_loss_count)
383 omap_pm_get_dev_context_loss_count(&timer->pdev->dev); 380 timer->ctx_loss_count =
381 timer->get_context_loss_count(&timer->pdev->dev);
382 }
384 383
385 /* 384 /*
386 * Since the register values are computed and written within 385 * Since the register values are computed and written within
@@ -496,7 +495,8 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
496 omap_dm_timer_enable(timer); 495 omap_dm_timer_enable(timer);
497 496
498 if (!(timer->capability & OMAP_TIMER_ALWON)) { 497 if (!(timer->capability & OMAP_TIMER_ALWON)) {
499 if (omap_pm_get_dev_context_loss_count(&timer->pdev->dev) != 498 if (timer->get_context_loss_count &&
499 timer->get_context_loss_count(&timer->pdev->dev) !=
500 timer->ctx_loss_count) 500 timer->ctx_loss_count)
501 omap_timer_restore_context(timer); 501 omap_timer_restore_context(timer);
502 } 502 }
@@ -730,6 +730,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
730 timer->reserved = omap_dm_timer_reserved_systimer(timer->id); 730 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
731 timer->pdev = pdev; 731 timer->pdev = pdev;
732 timer->capability = pdata->timer_capability; 732 timer->capability = pdata->timer_capability;
733 timer->get_context_loss_count = pdata->get_context_loss_count;
733 734
734 /* Skip pm_runtime_enable for OMAP1 */ 735 /* Skip pm_runtime_enable for OMAP1 */
735 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { 736 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index f868caeedfd6..3a77b30f53d4 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -30,7 +30,6 @@
30#include <linux/io.h> 30#include <linux/io.h>
31#include <linux/omapfb.h> 31#include <linux/omapfb.h>
32 32
33#include <mach/hardware.h>
34#include <asm/mach/map.h> 33#include <asm/mach/map.h>
35 34
36#include <plat/cpu.h> 35#include <plat/cpu.h>
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c
index be6deb7c12ec..f9df624d108c 100644
--- a/arch/arm/plat-omap/i2c.c
+++ b/arch/arm/plat-omap/i2c.c
@@ -31,34 +31,13 @@
31#include <linux/err.h> 31#include <linux/err.h>
32#include <linux/clk.h> 32#include <linux/clk.h>
33 33
34#include <mach/irqs.h> 34#include <plat/i2c.h>
35
36#include "../mach-omap1/soc.h"
37#include "../mach-omap2/soc.h"
38
39#include "i2c.h"
40 35
41#define OMAP_I2C_MAX_CONTROLLERS 4 36#define OMAP_I2C_MAX_CONTROLLERS 4
42static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; 37static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS];
43 38
44#define OMAP_I2C_CMDLINE_SETUP (BIT(31)) 39#define OMAP_I2C_CMDLINE_SETUP (BIT(31))
45 40
46static int __init omap_i2c_nr_ports(void)
47{
48 int ports = 0;
49
50 if (cpu_class_is_omap1())
51 ports = 1;
52 else if (cpu_is_omap24xx())
53 ports = 2;
54 else if (cpu_is_omap34xx())
55 ports = 3;
56 else if (cpu_is_omap44xx())
57 ports = 4;
58
59 return ports;
60}
61
62/** 41/**
63 * omap_i2c_bus_setup - Process command line options for the I2C bus speed 42 * omap_i2c_bus_setup - Process command line options for the I2C bus speed
64 * @str: String of options 43 * @str: String of options
@@ -72,12 +51,11 @@ static int __init omap_i2c_nr_ports(void)
72 */ 51 */
73static int __init omap_i2c_bus_setup(char *str) 52static int __init omap_i2c_bus_setup(char *str)
74{ 53{
75 int ports;
76 int ints[3]; 54 int ints[3];
77 55
78 ports = omap_i2c_nr_ports();
79 get_options(str, 3, ints); 56 get_options(str, 3, ints);
80 if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports) 57 if (ints[0] < 2 || ints[1] < 1 ||
58 ints[1] > OMAP_I2C_MAX_CONTROLLERS)
81 return 0; 59 return 0;
82 i2c_pdata[ints[1] - 1].clkrate = ints[2]; 60 i2c_pdata[ints[1] - 1].clkrate = ints[2];
83 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP; 61 i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
@@ -122,7 +100,7 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
122{ 100{
123 int err; 101 int err;
124 102
125 BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports()); 103 BUG_ON(bus_id < 1 || bus_id > OMAP_I2C_MAX_CONTROLLERS);
126 104
127 if (info) { 105 if (info) {
128 err = i2c_register_board_info(bus_id, info, len); 106 err = i2c_register_board_info(bus_id, info, len);
diff --git a/arch/arm/plat-omap/include/plat-omap/dma-omap.h b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
index 222be7e934e5..6f506ba9e453 100644
--- a/arch/arm/plat-omap/include/plat-omap/dma-omap.h
+++ b/arch/arm/plat-omap/include/plat-omap/dma-omap.h
@@ -130,10 +130,12 @@
130#define SRC_PORT BIT(0x7) 130#define SRC_PORT BIT(0x7)
131#define DST_PORT BIT(0x8) 131#define DST_PORT BIT(0x8)
132#define SRC_INDEX BIT(0x9) 132#define SRC_INDEX BIT(0x9)
133#define DST_INDEX BIT(0xA) 133#define DST_INDEX BIT(0xa)
134#define IS_BURST_ONLY4 BIT(0xB) 134#define IS_BURST_ONLY4 BIT(0xb)
135#define CLEAR_CSR_ON_READ BIT(0xC) 135#define CLEAR_CSR_ON_READ BIT(0xc)
136#define IS_WORD_16 BIT(0xD) 136#define IS_WORD_16 BIT(0xd)
137#define ENABLE_16XX_MODE BIT(0xe)
138#define HS_CHANNELS_RESERVED BIT(0xf)
137 139
138/* Defines for DMA Capabilities */ 140/* Defines for DMA Capabilities */
139#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) 141#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)
@@ -270,7 +272,15 @@ struct omap_system_dma_plat_info {
270 u32 (*dma_read)(int reg, int lch); 272 u32 (*dma_read)(int reg, int lch);
271}; 273};
272 274
273extern void __init omap_init_consistent_dma_size(void); 275#ifdef CONFIG_ARCH_OMAP2PLUS
276#define dma_omap2plus() 1
277#else
278#define dma_omap2plus() 0
279#endif
280#define dma_omap1() (!dma_omap2plus())
281#define dma_omap15xx() ((dma_omap1() && (d->dev_caps & ENABLE_1510_MODE)))
282#define dma_omap16xx() ((dma_omap1() && (d->dev_caps & ENABLE_16XX_MODE)))
283
274extern void omap_set_dma_priority(int lch, int dst_port, int priority); 284extern void omap_set_dma_priority(int lch, int dst_port, int priority);
275extern int omap_request_dma(int dev_id, const char *dev_name, 285extern int omap_request_dma(int dev_id, const char *dev_name,
276 void (*callback)(int lch, u16 ch_status, void *data), 286 void (*callback)(int lch, u16 ch_status, void *data),
diff --git a/arch/arm/plat-omap/include/plat/counter-32k.h b/arch/arm/plat-omap/include/plat/counter-32k.h
new file mode 100644
index 000000000000..da000d482ff2
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/counter-32k.h
@@ -0,0 +1 @@
int omap_init_clocksource_32k(void __iomem *vbase);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index ba542ec8d513..b4516aba67ed 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -29,7 +29,7 @@
29#define __ASM_ARCH_OMAP_CPU_H 29#define __ASM_ARCH_OMAP_CPU_H
30 30
31#ifdef CONFIG_ARCH_OMAP1 31#ifdef CONFIG_ARCH_OMAP1
32#include "../../mach-omap1/soc.h" 32#include <mach/soc.h>
33#endif 33#endif
34 34
35#ifdef CONFIG_ARCH_OMAP2PLUS 35#ifdef CONFIG_ARCH_OMAP2PLUS
diff --git a/arch/arm/mach-omap2/debug-devices.h b/arch/arm/plat-omap/include/plat/debug-devices.h
index a4edbd2f7484..8fc4287222dd 100644
--- a/arch/arm/mach-omap2/debug-devices.h
+++ b/arch/arm/plat-omap/include/plat/debug-devices.h
@@ -1,9 +1,2 @@
1#ifndef _OMAP_DEBUG_DEVICES_H
2#define _OMAP_DEBUG_DEVICES_H
3
4#include <linux/types.h>
5
6/* for TI reference platforms sharing the same debug card */ 1/* for TI reference platforms sharing the same debug card */
7extern int debug_card_init(u32 addr, unsigned gpio); 2extern int debug_card_init(u32 addr, unsigned gpio);
8
9#endif
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 85868e98c11c..3f5b9cfd9c0b 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -94,6 +94,7 @@ struct dmtimer_platform_data {
94 /* set_timer_src - Only used for OMAP1 devices */ 94 /* set_timer_src - Only used for OMAP1 devices */
95 int (*set_timer_src)(struct platform_device *pdev, int source); 95 int (*set_timer_src)(struct platform_device *pdev, int source);
96 u32 timer_capability; 96 u32 timer_capability;
97 int (*get_context_loss_count)(struct device *);
97}; 98};
98 99
99int omap_dm_timer_reserve_systimer(int id); 100int omap_dm_timer_reserve_systimer(int id);
@@ -263,6 +264,7 @@ struct omap_dm_timer {
263 unsigned reserved:1; 264 unsigned reserved:1;
264 unsigned posted:1; 265 unsigned posted:1;
265 struct timer_regs context; 266 struct timer_regs context;
267 int (*get_context_loss_count)(struct device *);
266 int ctx_loss_count; 268 int ctx_loss_count;
267 int revision; 269 int revision;
268 u32 capability; 270 u32 capability;
diff --git a/arch/arm/plat-omap/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 7a9028cb5a75..7a9028cb5a75 100644
--- a/arch/arm/plat-omap/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
diff --git a/arch/arm/plat-omap/include/plat/sram.h b/arch/arm/plat-omap/include/plat/sram.h
new file mode 100644
index 000000000000..ba4525059a99
--- /dev/null
+++ b/arch/arm/plat-omap/include/plat/sram.h
@@ -0,0 +1,16 @@
1int omap_sram_init(void);
2
3void omap_map_sram(unsigned long start, unsigned long size,
4 unsigned long skip, int cached);
5void omap_sram_reset(void);
6
7extern void *omap_sram_push_address(unsigned long size);
8
9/* Macro to push a function to the internal SRAM, using the fncpy API */
10#define omap_sram_push(funcp, size) ({ \
11 typeof(&(funcp)) _res = NULL; \
12 void *_sram_address = omap_sram_push_address(size); \
13 if (_sram_address) \
14 _res = fncpy(_sram_address, &(funcp), size); \
15 _res; \
16})
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 70dcc225157f..743fc2836f7a 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -20,198 +20,20 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/io.h> 21#include <linux/io.h>
22 22
23#include <asm/fncpy.h>
23#include <asm/tlb.h> 24#include <asm/tlb.h>
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25 26
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
27 28
28#include "../mach-omap1/soc.h"
29#include "../mach-omap2/soc.h"
30
31#include "sram.h"
32
33/* XXX These "sideways" includes will disappear when sram.c becomes a driver */
34#include "../mach-omap2/iomap.h"
35#include "../mach-omap2/prm2xxx_3xxx.h"
36#include "../mach-omap2/sdrc.h"
37
38#define OMAP1_SRAM_PA 0x20000000
39#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
40#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
41#ifdef CONFIG_OMAP4_ERRATA_I688
42#define OMAP4_SRAM_PUB_PA OMAP4_SRAM_PA
43#else
44#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
45#endif
46#define OMAP5_SRAM_PA 0x40300000
47
48#if defined(CONFIG_ARCH_OMAP2PLUS)
49#define SRAM_BOOTLOADER_SZ 0x00
50#else
51#define SRAM_BOOTLOADER_SZ 0x80
52#endif
53
54#define OMAP24XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68005048)
55#define OMAP24XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68005050)
56#define OMAP24XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68005058)
57
58#define OMAP34XX_VA_REQINFOPERM0 OMAP2_L3_IO_ADDRESS(0x68012848)
59#define OMAP34XX_VA_READPERM0 OMAP2_L3_IO_ADDRESS(0x68012850)
60#define OMAP34XX_VA_WRITEPERM0 OMAP2_L3_IO_ADDRESS(0x68012858)
61#define OMAP34XX_VA_ADDR_MATCH2 OMAP2_L3_IO_ADDRESS(0x68012880)
62#define OMAP34XX_VA_SMS_RG_ATT0 OMAP2_L3_IO_ADDRESS(0x6C000048)
63
64#define GP_DEVICE 0x300
65
66#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 29#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
67 30
68static unsigned long omap_sram_start;
69static void __iomem *omap_sram_base; 31static void __iomem *omap_sram_base;
70static unsigned long omap_sram_skip; 32static unsigned long omap_sram_skip;
71static unsigned long omap_sram_size; 33static unsigned long omap_sram_size;
72static void __iomem *omap_sram_ceil; 34static void __iomem *omap_sram_ceil;
73 35
74/* 36/*
75 * Depending on the target RAMFS firewall setup, the public usable amount of
76 * SRAM varies. The default accessible size for all device types is 2k. A GP
77 * device allows ARM11 but not other initiators for full size. This
78 * functionality seems ok until some nice security API happens.
79 */
80static int is_sram_locked(void)
81{
82 if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
83 /* RAMFW: R/W access to all initiators for all qualifier sets */
84 if (cpu_is_omap242x()) {
85 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
86 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
87 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
88 }
89 if (cpu_is_omap34xx()) {
90 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
91 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
92 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
93 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
94 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
95 }
96 return 0;
97 } else
98 return 1; /* assume locked with no PPA or security driver */
99}
100
101/*
102 * The amount of SRAM depends on the core type.
103 * Note that we cannot try to test for SRAM here because writes
104 * to secure SRAM will hang the system. Also the SRAM is not
105 * yet mapped at this point.
106 */
107static void __init omap_detect_sram(void)
108{
109 omap_sram_skip = SRAM_BOOTLOADER_SZ;
110 if (cpu_class_is_omap2()) {
111 if (is_sram_locked()) {
112 if (cpu_is_omap34xx()) {
113 omap_sram_start = OMAP3_SRAM_PUB_PA;
114 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
115 (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
116 omap_sram_size = 0x7000; /* 28K */
117 omap_sram_skip += SZ_16K;
118 } else {
119 omap_sram_size = 0x8000; /* 32K */
120 }
121 } else if (cpu_is_omap44xx()) {
122 omap_sram_start = OMAP4_SRAM_PUB_PA;
123 omap_sram_size = 0xa000; /* 40K */
124 } else if (soc_is_omap54xx()) {
125 omap_sram_start = OMAP5_SRAM_PA;
126 omap_sram_size = SZ_128K; /* 128KB */
127 } else {
128 omap_sram_start = OMAP2_SRAM_PUB_PA;
129 omap_sram_size = 0x800; /* 2K */
130 }
131 } else {
132 if (soc_is_am33xx()) {
133 omap_sram_start = AM33XX_SRAM_PA;
134 omap_sram_size = 0x10000; /* 64K */
135 } else if (cpu_is_omap34xx()) {
136 omap_sram_start = OMAP3_SRAM_PA;
137 omap_sram_size = 0x10000; /* 64K */
138 } else if (cpu_is_omap44xx()) {
139 omap_sram_start = OMAP4_SRAM_PA;
140 omap_sram_size = 0xe000; /* 56K */
141 } else if (soc_is_omap54xx()) {
142 omap_sram_start = OMAP5_SRAM_PA;
143 omap_sram_size = SZ_128K; /* 128KB */
144 } else {
145 omap_sram_start = OMAP2_SRAM_PA;
146 if (cpu_is_omap242x())
147 omap_sram_size = 0xa0000; /* 640K */
148 else if (cpu_is_omap243x())
149 omap_sram_size = 0x10000; /* 64K */
150 }
151 }
152 } else {
153 omap_sram_start = OMAP1_SRAM_PA;
154
155 if (cpu_is_omap7xx())
156 omap_sram_size = 0x32000; /* 200K */
157 else if (cpu_is_omap15xx())
158 omap_sram_size = 0x30000; /* 192K */
159 else if (cpu_is_omap1610() || cpu_is_omap1611() ||
160 cpu_is_omap1621() || cpu_is_omap1710())
161 omap_sram_size = 0x4000; /* 16K */
162 else {
163 pr_err("Could not detect SRAM size\n");
164 omap_sram_size = 0x4000;
165 }
166 }
167}
168
169/*
170 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
171 */
172static void __init omap_map_sram(void)
173{
174 int cached = 1;
175
176 if (omap_sram_size == 0)
177 return;
178
179#ifdef CONFIG_OMAP4_ERRATA_I688
180 if (cpu_is_omap44xx()) {
181 omap_sram_start += PAGE_SIZE;
182 omap_sram_size -= SZ_16K;
183 }
184#endif
185 if (cpu_is_omap34xx()) {
186 /*
187 * SRAM must be marked as non-cached on OMAP3 since the
188 * CORE DPLL M2 divider change code (in SRAM) runs with the
189 * SDRAM controller disabled, and if it is marked cached,
190 * the ARM may attempt to write cache lines back to SDRAM
191 * which will cause the system to hang.
192 */
193 cached = 0;
194 }
195
196 omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
197 omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
198 cached);
199 if (!omap_sram_base) {
200 pr_err("SRAM: Could not map\n");
201 return;
202 }
203
204 omap_sram_ceil = omap_sram_base + omap_sram_size;
205
206 /*
207 * Looks like we need to preserve some bootloader code at the
208 * beginning of SRAM for jumping to flash for reboot to work...
209 */
210 memset_io(omap_sram_base + omap_sram_skip, 0,
211 omap_sram_size - omap_sram_skip);
212}
213
214/*
215 * Memory allocator for SRAM: calculates the new ceiling address 37 * Memory allocator for SRAM: calculates the new ceiling address
216 * for pushing a function using the fncpy API. 38 * for pushing a function using the fncpy API.
217 * 39 *
@@ -236,171 +58,39 @@ void *omap_sram_push_address(unsigned long size)
236 return (void *)omap_sram_ceil; 58 return (void *)omap_sram_ceil;
237} 59}
238 60
239#ifdef CONFIG_ARCH_OMAP1 61/*
240 62 * The SRAM context is lost during off-idle and stack
241static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl); 63 * needs to be reset.
242 64 */
243void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) 65void omap_sram_reset(void)
244{
245 BUG_ON(!_omap_sram_reprogram_clock);
246 /* On 730, bit 13 must always be 1 */
247 if (cpu_is_omap7xx())
248 ckctl |= 0x2000;
249 _omap_sram_reprogram_clock(dpllctl, ckctl);
250}
251
252static int __init omap1_sram_init(void)
253{
254 _omap_sram_reprogram_clock =
255 omap_sram_push(omap1_sram_reprogram_clock,
256 omap1_sram_reprogram_clock_sz);
257
258 return 0;
259}
260
261#else
262#define omap1_sram_init() do {} while (0)
263#endif
264
265#if defined(CONFIG_ARCH_OMAP2)
266
267static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
268 u32 base_cs, u32 force_unlock);
269
270void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
271 u32 base_cs, u32 force_unlock)
272{
273 BUG_ON(!_omap2_sram_ddr_init);
274 _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
275 base_cs, force_unlock);
276}
277
278static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
279 u32 mem_type);
280
281void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
282{
283 BUG_ON(!_omap2_sram_reprogram_sdrc);
284 _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
285}
286
287static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
288
289u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
290{
291 BUG_ON(!_omap2_set_prcm);
292 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
293}
294#endif
295
296#ifdef CONFIG_SOC_OMAP2420
297static int __init omap242x_sram_init(void)
298{
299 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
300 omap242x_sram_ddr_init_sz);
301
302 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
303 omap242x_sram_reprogram_sdrc_sz);
304
305 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
306 omap242x_sram_set_prcm_sz);
307
308 return 0;
309}
310#else
311static inline int omap242x_sram_init(void)
312{
313 return 0;
314}
315#endif
316
317#ifdef CONFIG_SOC_OMAP2430
318static int __init omap243x_sram_init(void)
319{
320 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
321 omap243x_sram_ddr_init_sz);
322
323 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
324 omap243x_sram_reprogram_sdrc_sz);
325
326 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
327 omap243x_sram_set_prcm_sz);
328
329 return 0;
330}
331#else
332static inline int omap243x_sram_init(void)
333{
334 return 0;
335}
336#endif
337
338#ifdef CONFIG_ARCH_OMAP3
339
340static u32 (*_omap3_sram_configure_core_dpll)(
341 u32 m2, u32 unlock_dll, u32 f, u32 inc,
342 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
343 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
344 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
345 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
346
347u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
348 u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
349 u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
350 u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
351 u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
352{
353 BUG_ON(!_omap3_sram_configure_core_dpll);
354 return _omap3_sram_configure_core_dpll(
355 m2, unlock_dll, f, inc,
356 sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
357 sdrc_actim_ctrl_b_0, sdrc_mr_0,
358 sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
359 sdrc_actim_ctrl_b_1, sdrc_mr_1);
360}
361
362void omap3_sram_restore_context(void)
363{ 66{
364 omap_sram_ceil = omap_sram_base + omap_sram_size; 67 omap_sram_ceil = omap_sram_base + omap_sram_size;
365
366 _omap3_sram_configure_core_dpll =
367 omap_sram_push(omap3_sram_configure_core_dpll,
368 omap3_sram_configure_core_dpll_sz);
369 omap_push_sram_idle();
370} 68}
371 69
372static inline int omap34xx_sram_init(void) 70/*
373{ 71 * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
374 omap3_sram_restore_context(); 72 */
375 return 0; 73void __init omap_map_sram(unsigned long start, unsigned long size,
376} 74 unsigned long skip, int cached)
377#else
378static inline int omap34xx_sram_init(void)
379{
380 return 0;
381}
382#endif /* CONFIG_ARCH_OMAP3 */
383
384static inline int am33xx_sram_init(void)
385{ 75{
386 return 0; 76 if (size == 0)
387} 77 return;
388 78
389int __init omap_sram_init(void) 79 start = ROUND_DOWN(start, PAGE_SIZE);
390{ 80 omap_sram_size = size;
391 omap_detect_sram(); 81 omap_sram_skip = skip;
392 omap_map_sram(); 82 omap_sram_base = __arm_ioremap_exec(start, size, cached);
83 if (!omap_sram_base) {
84 pr_err("SRAM: Could not map\n");
85 return;
86 }
393 87
394 if (!(cpu_class_is_omap2())) 88 omap_sram_reset();
395 omap1_sram_init();
396 else if (cpu_is_omap242x())
397 omap242x_sram_init();
398 else if (cpu_is_omap2430())
399 omap243x_sram_init();
400 else if (soc_is_am33xx())
401 am33xx_sram_init();
402 else if (cpu_is_omap34xx())
403 omap34xx_sram_init();
404 89
405 return 0; 90 /*
91 * Looks like we need to preserve some bootloader code at the
92 * beginning of SRAM for jumping to flash for reboot to work...
93 */
94 memset_io(omap_sram_base + omap_sram_skip, 0,
95 omap_sram_size - omap_sram_skip);
406} 96}
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