Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma

Pull slave-dmaengine updates from Vinod Koul:
 "This is fairly big pull by my standards as I had missed last merge
  window.  So we have the support for device tree for slave-dmaengine,
  large updates to dw_dmac driver from Andy for reusing on different
  architectures.  Along with this we have fixes on bunch of the drivers"

Fix up trivial conflicts, usually due to #include line movement next to
each other.

* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (111 commits)
  Revert "ARM: SPEAr13xx: Pass DW DMAC platform data from DT"
  ARM: dts: pl330: Add #dma-cells for generic dma binding support
  DMA: PL330: Register the DMA controller with the generic DMA helpers
  DMA: PL330: Add xlate function
  DMA: PL330: Add new pl330 filter for DT case.
  dma: tegra20-apb-dma: remove unnecessary assignment
  edma: do not waste memory for dma_mask
  dma: coh901318: set residue only if dma is in progress
  dma: coh901318: avoid unbalanced locking
  dmaengine.h: remove redundant else keyword
  dma: of-dma: protect list write operation by spin_lock
  dmaengine: ste_dma40: do not remove descriptors for cyclic transfers
  dma: of-dma.c: fix memory leakage
  dw_dmac: apply default dma_mask if needed
  dmaengine: ioat - fix spare sparse complain
  dmaengine: move drivers/of/dma.c -> drivers/dma/of-dma.c
  ioatdma: fix race between updating ioat->head and IOAT_COMPLETION_PENDING
  dw_dmac: add support for Lynxpoint DMA controllers
  dw_dmac: return proper residue value
  dw_dmac: fill individual length of descriptor
  ...

5 files changed, 14 insertions, 150 deletions

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f50b4e854355..b1ac73e21c80 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -312,24 +312,36 @@
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121A0000 0x1000>;
                         interrupts = <0 34 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                 };
 
                 pdma1: pdma@121B0000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x121B0000 0x1000>;
                         interrupts = <0 35 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <32>;
                 };
 
                 mdma0: mdma@10800000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x10800000 0x1000>;
                         interrupts = <0 33 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
                 };
 
                 mdma1: mdma@11C10000 {
                         compatible = "arm,pl330", "arm,primecell";
                         reg = <0x11C10000 0x1000>;
                         interrupts = <0 124 0>;
+                        #dma-cells = <1>;
+                        #dma-channels = <8>;
+                        #dma-requests = <1>;
                 };
         };
 
diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
deleted file mode 100644
index 4eea2107214b..000000000000
--- a/arch/arm/include/asm/hardware/pl080.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/* arch/arm/include/asm/hardware/pl080.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * ARM PrimeCell PL080 DMA controller
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* Note, there are some Samsung updates to this controller block which
- * make it not entierly compatible with the PL080 specification from
- * ARM. When in doubt, check the Samsung documentation first.
- *
- * The Samsung defines are PL080S, and add an extra control register,
- * the ability to move more than 2^11 counts of data and some extra
- * OneNAND features.
-*/
-
-#ifndef ASM_PL080_H
-#define ASM_PL080_H
-
-#define PL080_INT_STATUS                        (0x00)
-#define PL080_TC_STATUS                         (0x04)
-#define PL080_TC_CLEAR                          (0x08)
-#define PL080_ERR_STATUS                        (0x0C)
-#define PL080_ERR_CLEAR                         (0x10)
-#define PL080_RAW_TC_STATUS                     (0x14)
-#define PL080_RAW_ERR_STATUS                    (0x18)
-#define PL080_EN_CHAN                           (0x1c)
-#define PL080_SOFT_BREQ                         (0x20)
-#define PL080_SOFT_SREQ                         (0x24)
-#define PL080_SOFT_LBREQ                        (0x28)
-#define PL080_SOFT_LSREQ                        (0x2C)
-
-#define PL080_CONFIG                            (0x30)
-#define PL080_CONFIG_M2_BE                      (1 << 2)
-#define PL080_CONFIG_M1_BE                      (1 << 1)
-#define PL080_CONFIG_ENABLE                     (1 << 0)
-
-#define PL080_SYNC                              (0x34)
-
-/* Per channel configuration registers */
-
-#define PL080_Cx_STRIDE                         (0x20)
-#define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
-#define PL080_Cx_SRC_ADDR(x)                    ((0x100 + (x * 0x20)))
-#define PL080_Cx_DST_ADDR(x)                    ((0x104 + (x * 0x20)))
-#define PL080_Cx_LLI(x)                         ((0x108 + (x * 0x20)))
-#define PL080_Cx_CONTROL(x)                     ((0x10C + (x * 0x20)))
-#define PL080_Cx_CONFIG(x)                      ((0x110 + (x * 0x20)))
-#define PL080S_Cx_CONTROL2(x)                   ((0x110 + (x * 0x20)))
-#define PL080S_Cx_CONFIG(x)                     ((0x114 + (x * 0x20)))
-
-#define PL080_CH_SRC_ADDR                       (0x00)
-#define PL080_CH_DST_ADDR                       (0x04)
-#define PL080_CH_LLI                            (0x08)
-#define PL080_CH_CONTROL                        (0x0C)
-#define PL080_CH_CONFIG                         (0x10)
-#define PL080S_CH_CONTROL2                      (0x10)
-#define PL080S_CH_CONFIG                        (0x14)
-
-#define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
-#define PL080_LLI_ADDR_SHIFT                    (2)
-#define PL080_LLI_LM_AHB2                       (1 << 0)
-
-#define PL080_CONTROL_TC_IRQ_EN                 (1 << 31)
-#define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
-#define PL080_CONTROL_PROT_SHIFT                (28)
-#define PL080_CONTROL_PROT_CACHE                (1 << 30)
-#define PL080_CONTROL_PROT_BUFF                 (1 << 29)
-#define PL080_CONTROL_PROT_SYS                  (1 << 28)
-#define PL080_CONTROL_DST_INCR                  (1 << 27)
-#define PL080_CONTROL_SRC_INCR                  (1 << 26)
-#define PL080_CONTROL_DST_AHB2                  (1 << 25)
-#define PL080_CONTROL_SRC_AHB2                  (1 << 24)
-#define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
-#define PL080_CONTROL_DWIDTH_SHIFT              (21)
-#define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
-#define PL080_CONTROL_SWIDTH_SHIFT              (18)
-#define PL080_CONTROL_DB_SIZE_MASK              (0x7 << 15)
-#define PL080_CONTROL_DB_SIZE_SHIFT             (15)
-#define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
-#define PL080_CONTROL_SB_SIZE_SHIFT             (12)
-#define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
-#define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
-
-#define PL080_BSIZE_1                           (0x0)
-#define PL080_BSIZE_4                           (0x1)
-#define PL080_BSIZE_8                           (0x2)
-#define PL080_BSIZE_16                          (0x3)
-#define PL080_BSIZE_32                          (0x4)
-#define PL080_BSIZE_64                          (0x5)
-#define PL080_BSIZE_128                         (0x6)
-#define PL080_BSIZE_256                         (0x7)
-
-#define PL080_WIDTH_8BIT                        (0x0)
-#define PL080_WIDTH_16BIT                       (0x1)
-#define PL080_WIDTH_32BIT                       (0x2)
-
-#define PL080N_CONFIG_ITPROT                    (1 << 20)
-#define PL080N_CONFIG_SECPROT                   (1 << 19)
-#define PL080_CONFIG_HALT                       (1 << 18)
-#define PL080_CONFIG_ACTIVE                     (1 << 17)  /* RO */
-#define PL080_CONFIG_LOCK                       (1 << 16)
-#define PL080_CONFIG_TC_IRQ_MASK                (1 << 15)
-#define PL080_CONFIG_ERR_IRQ_MASK               (1 << 14)
-#define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
-#define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
-#define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
-#define PL080_CONFIG_DST_SEL_SHIFT              (6)
-#define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
-#define PL080_CONFIG_SRC_SEL_SHIFT              (1)
-#define PL080_CONFIG_ENABLE                     (1 << 0)
-
-#define PL080_FLOW_MEM2MEM                      (0x0)
-#define PL080_FLOW_MEM2PER                      (0x1)
-#define PL080_FLOW_PER2MEM                      (0x2)
-#define PL080_FLOW_SRC2DST                      (0x3)
-#define PL080_FLOW_SRC2DST_DST                  (0x4)
-#define PL080_FLOW_MEM2PER_PER                  (0x5)
-#define PL080_FLOW_PER2MEM_PER                  (0x6)
-#define PL080_FLOW_SRC2DST_SRC                  (0x7)
-
-/* DMA linked list chain structure */
-
-struct pl080_lli {
-        u32     src_addr;
-        u32     dst_addr;
-        u32     next_lli;
-        u32     control0;
-};
-
-struct pl080s_lli {
-        u32     src_addr;
-        u32     dst_addr;
-        u32     next_lli;
-        u32     control0;
-        u32     control1;
-};
-
-#endif /* ASM_PL080_H */
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index ec29b35f25c0..6af1aa1ef213 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -23,13 +23,12 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/amba/pl080.h>
 
 #include <mach/dma.h>
 #include <mach/map.h>
 #include <mach/irqs.h>
 
-#include <asm/hardware/pl080.h>
-
 #include "regs-sys.h"
 
 /* dma channel state information */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index b2ba516ca2d4..f9d754f90c59 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -16,7 +16,6 @@
 #include <linux/amba/pl022.h>
 #include <linux/amba/pl08x.h>
 #include <linux/io.h>
-#include <asm/hardware/pl080.h>
 #include <plat/pl080.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index b8bd33ca88bd..8904d8a52d84 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -20,7 +20,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
-#include <asm/hardware/pl080.h>
+#include <linux/amba/pl080.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>