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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-03-20 19:56:04 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-03-20 19:56:04 -0400
commit4286f84ef6d7f44de1e70b904706bdc3e1f7af01 (patch)
tree1fd5fc121f508525d62b0bdf7cc22f16c18b110d /arch
parent2d87e06e7477fa1467e730087b68c2f518c0fff6 (diff)
parente96dde2b5edbc0d385ccced05fb5db68c070b0d4 (diff)
Merge remote-tracking branch 'kumar/next' into next
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/Makefile2
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi16
-rw-r--r--arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p1010si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p1020si-post.dtsi6
-rw-r--r--arch/powerpc/boot/dts/fsl/p1021si-post.dtsi7
-rw-r--r--arch/powerpc/boot/dts/fsl/p1022si-post.dtsi12
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2020si-post.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p3060si-post.dtsi6
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi3
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi10
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi6
-rw-r--r--arch/powerpc/boot/dts/ge_imp3a.dts255
-rw-r--r--arch/powerpc/boot/dts/mpc836x_mds.dts4
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dts6
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds.dtsi93
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts8
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts306
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dtsi306
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds_32b.dts86
-rw-r--r--arch/powerpc/boot/dts/mpc8548cds_36b.dts86
-rw-r--r--arch/powerpc/boot/dts/mpc8572ds.dtsi50
-rw-r--r--arch/powerpc/boot/dts/p1010rdb.dtsi4
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc.dtsi247
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_32b.dts90
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_36b.dts90
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts64
-rw-r--r--arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts142
-rw-r--r--arch/powerpc/boot/dts/p1021rdb.dts96
-rw-r--r--arch/powerpc/boot/dts/p1021rdb.dtsi236
-rw-r--r--arch/powerpc/boot/dts/p1021rdb_36b.dts96
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts274
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dtsi234
-rw-r--r--arch/powerpc/boot/dts/p1022ds_32b.dts103
-rw-r--r--arch/powerpc/boot/dts/p1022ds_36b.dts103
-rw-r--r--arch/powerpc/boot/dts/p1025rdb.dtsi286
-rw-r--r--arch/powerpc/boot/dts/p1025rdb_32b.dts135
-rw-r--r--arch/powerpc/boot/dts/p1025rdb_36b.dts88
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc.dtsi241
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc_32b.dts96
-rw-r--r--arch/powerpc/boot/dts/p2020rdb-pc_36b.dts96
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts4
-rw-r--r--arch/powerpc/configs/85xx/ge_imp3a_defconfig257
-rw-r--r--arch/powerpc/configs/86xx/gef_ppc9a_defconfig1
-rw-r--r--arch/powerpc/configs/86xx/gef_sbc310_defconfig1
-rw-r--r--arch/powerpc/configs/86xx/gef_sbc610_defconfig2
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig1
-rw-r--r--arch/powerpc/include/asm/cputable.h12
-rw-r--r--arch/powerpc/include/asm/fsl_guts.h6
-rw-r--r--arch/powerpc/include/asm/mpic_msgr.h132
-rw-r--r--arch/powerpc/include/asm/reg_booke.h1
-rw-r--r--arch/powerpc/kernel/cputable.c18
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c19
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig27
-rw-r--r--arch/powerpc/platforms/85xx/Makefile1
-rw-r--r--arch/powerpc/platforms/85xx/ge_imp3a.c246
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_cds.c81
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_mds.c35
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_rdb.c215
-rw-r--r--arch/powerpc/platforms/85xx/p1022_ds.c203
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig3
-rw-r--r--arch/powerpc/platforms/86xx/Makefile7
-rw-r--r--arch/powerpc/platforms/86xx/gef_gpio.c171
-rw-r--r--arch/powerpc/platforms/86xx/gef_ppc9a.c2
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc310.c2
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c2
-rw-r--r--arch/powerpc/platforms/Kconfig8
-rw-r--r--arch/powerpc/sysdev/Kconfig4
-rw-r--r--arch/powerpc/sysdev/Makefile4
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_cache_sram.c1
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_l2ctlr.c4
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c1
-rw-r--r--arch/powerpc/sysdev/fsl_rio.c4
-rw-r--r--arch/powerpc/sysdev/fsl_rmu.c42
-rw-r--r--arch/powerpc/sysdev/ge/Makefile1
-rw-r--r--arch/powerpc/sysdev/ge/ge_pic.c (renamed from arch/powerpc/platforms/86xx/gef_pic.c)2
-rw-r--r--arch/powerpc/sysdev/ge/ge_pic.h (renamed from arch/powerpc/platforms/86xx/gef_pic.h)0
-rw-r--r--arch/powerpc/sysdev/mpic_msgr.c282
87 files changed, 4927 insertions, 897 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 8844a17ce8ed..f6622e022364 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -247,7 +247,7 @@ image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
247image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads 247image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
248image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads 248image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
249image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \ 249image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
250 cuImage.mpc8548cds \ 250 cuImage.mpc8548cds_32b \
251 cuImage.mpc8555cds 251 cuImage.mpc8555cds
252image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds 252image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds
253image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \ 253image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
diff --git a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
index b37da56018b6..c8b2daa40ac8 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi
@@ -202,7 +202,7 @@
202/include/ "pq3-etsec1-timer-0.dtsi" 202/include/ "pq3-etsec1-timer-0.dtsi"
203 203
204 usb@22000 { 204 usb@22000 {
205 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; 205 compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
206 reg = <0x22000 0x1000>; 206 reg = <0x22000 0x1000>;
207 #address-cells = <1>; 207 #address-cells = <1>;
208 #size-cells = <0>; 208 #size-cells = <0>;
@@ -210,7 +210,7 @@
210 }; 210 };
211 211
212 usb@23000 { 212 usb@23000 {
213 compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph"; 213 compatible = "fsl-usb2-mph-v1.2", "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
214 reg = <0x23000 0x1000>; 214 reg = <0x23000 0x1000>;
215 #address-cells = <1>; 215 #address-cells = <1>;
216 #size-cells = <0>; 216 #size-cells = <0>;
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
index 9d8023a69d7d..579d76cb8e32 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-post.dtsi
@@ -89,6 +89,21 @@
89 }; 89 };
90}; 90};
91 91
92&rio {
93 compatible = "fsl,srio";
94 interrupts = <48 2 0 0>;
95 #address-cells = <2>;
96 #size-cells = <2>;
97 fsl,srio-rmu-handle = <&rmu>;
98 ranges;
99
100 port1 {
101 #address-cells = <2>;
102 #size-cells = <2>;
103 cell-index = <1>;
104 };
105};
106
92&soc { 107&soc {
93 #address-cells = <1>; 108 #address-cells = <1>;
94 #size-cells = <1>; 109 #size-cells = <1>;
@@ -134,6 +149,7 @@
134 149
135/include/ "pq3-sec2.1-0.dtsi" 150/include/ "pq3-sec2.1-0.dtsi"
136/include/ "pq3-mpic.dtsi" 151/include/ "pq3-mpic.dtsi"
152/include/ "pq3-rmu-0.dtsi"
137 153
138 global-utilities@e0000 { 154 global-utilities@e0000 {
139 compatible = "fsl,mpc8548-guts"; 155 compatible = "fsl,mpc8548-guts";
diff --git a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
index 289f1218d755..720422d83529 100644
--- a/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/mpc8548si-pre.dtsi
@@ -43,7 +43,9 @@
43 serial0 = &serial0; 43 serial0 = &serial0;
44 serial1 = &serial1; 44 serial1 = &serial1;
45 ethernet0 = &enet0; 45 ethernet0 = &enet0;
46 ethernet1 = &enet2; 46 ethernet1 = &enet1;
47 ethernet2 = &enet2;
48 ethernet3 = &enet3;
47 pci0 = &pci0; 49 pci0 = &pci0;
48 pci1 = &pci1; 50 pci1 = &pci1;
49 pci2 = &pci2; 51 pci2 = &pci2;
diff --git a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
index a97d1263372c..0bde9ee8afaf 100644
--- a/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1010si-post.dtsi
@@ -156,6 +156,9 @@
156 156
157/include/ "pq3-dma-0.dtsi" 157/include/ "pq3-dma-0.dtsi"
158/include/ "pq3-usb2-dr-0.dtsi" 158/include/ "pq3-usb2-dr-0.dtsi"
159 usb@22000 {
160 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
161 };
159/include/ "pq3-esdhc-0.dtsi" 162/include/ "pq3-esdhc-0.dtsi"
160 sdhc@2e000 { 163 sdhc@2e000 {
161 compatible = "fsl,p1010-esdhc", "fsl,esdhc"; 164 compatible = "fsl,p1010-esdhc", "fsl,esdhc";
diff --git a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
index 5de5fc351314..68cc5e7f6477 100644
--- a/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1020si-post.dtsi
@@ -142,7 +142,13 @@
142 142
143/include/ "pq3-dma-0.dtsi" 143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi" 144/include/ "pq3-usb2-dr-0.dtsi"
145 usb@22000 {
146 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
147 };
145/include/ "pq3-usb2-dr-1.dtsi" 148/include/ "pq3-usb2-dr-1.dtsi"
149 usb@23000 {
150 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
151 };
146 152
147/include/ "pq3-esdhc-0.dtsi" 153/include/ "pq3-esdhc-0.dtsi"
148 sdhc@2e000 { 154 sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
index 38ba54d1e32e..4252ef85fb7a 100644
--- a/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1021si-post.dtsi
@@ -142,8 +142,15 @@
142 142
143/include/ "pq3-dma-0.dtsi" 143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi" 144/include/ "pq3-usb2-dr-0.dtsi"
145 usb@22000 {
146 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
147 };
145 148
146/include/ "pq3-esdhc-0.dtsi" 149/include/ "pq3-esdhc-0.dtsi"
150 sdhc@2e000 {
151 sdhci,auto-cmd12;
152 };
153
147/include/ "pq3-sec3.3-0.dtsi" 154/include/ "pq3-sec3.3-0.dtsi"
148 155
149/include/ "pq3-mpic.dtsi" 156/include/ "pq3-mpic.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
index ff9ed1d87929..06216b8c0af5 100644
--- a/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1022si-post.dtsi
@@ -35,7 +35,11 @@
35&lbc { 35&lbc {
36 #address-cells = <2>; 36 #address-cells = <2>;
37 #size-cells = <1>; 37 #size-cells = <1>;
38 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; 38 /*
39 * The localbus on the P1022 is not a simple-bus because of the eLBC
40 * pin muxing when the DIU is enabled.
41 */
42 compatible = "fsl,p1022-elbc", "fsl,elbc";
39 interrupts = <19 2 0 0>; 43 interrupts = <19 2 0 0>;
40}; 44};
41 45
@@ -199,7 +203,13 @@
199 203
200/include/ "pq3-dma-0.dtsi" 204/include/ "pq3-dma-0.dtsi"
201/include/ "pq3-usb2-dr-0.dtsi" 205/include/ "pq3-usb2-dr-0.dtsi"
206 usb@22000 {
207 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
208 };
202/include/ "pq3-usb2-dr-1.dtsi" 209/include/ "pq3-usb2-dr-1.dtsi"
210 usb@23000 {
211 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
212 };
203 213
204/include/ "pq3-esdhc-0.dtsi" 214/include/ "pq3-esdhc-0.dtsi"
205 sdhc@2e000 { 215 sdhc@2e000 {
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index b06bb4cc1fe8..941fa159cefb 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -142,6 +142,9 @@
142 142
143/include/ "pq3-dma-0.dtsi" 143/include/ "pq3-dma-0.dtsi"
144/include/ "pq3-usb2-dr-0.dtsi" 144/include/ "pq3-usb2-dr-0.dtsi"
145 usb@22000 {
146 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
147 };
145 148
146 crypto: crypto@300000 { 149 crypto: crypto@300000 {
147 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 150 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
diff --git a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
index 332e9e75e6c2..884e01bcb243 100644
--- a/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2020si-post.dtsi
@@ -171,6 +171,9 @@
171 171
172/include/ "pq3-dma-0.dtsi" 172/include/ "pq3-dma-0.dtsi"
173/include/ "pq3-usb2-dr-0.dtsi" 173/include/ "pq3-usb2-dr-0.dtsi"
174 usb@22000 {
175 compatible = "fsl-usb2-dr-v1.6", "fsl-usb2-dr";
176 };
174/include/ "pq3-etsec1-0.dtsi" 177/include/ "pq3-etsec1-0.dtsi"
175/include/ "pq3-etsec1-timer-0.dtsi" 178/include/ "pq3-etsec1-timer-0.dtsi"
176 179
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 234a399ddeb2..531eab82c6c9 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -309,12 +309,14 @@
309/include/ "qoriq-gpio-0.dtsi" 309/include/ "qoriq-gpio-0.dtsi"
310/include/ "qoriq-usb2-mph-0.dtsi" 310/include/ "qoriq-usb2-mph-0.dtsi"
311 usb0: usb@210000 { 311 usb0: usb@210000 {
312 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
312 phy_type = "utmi"; 313 phy_type = "utmi";
313 port0; 314 port0;
314 }; 315 };
315 316
316/include/ "qoriq-usb2-dr-0.dtsi" 317/include/ "qoriq-usb2-dr-0.dtsi"
317 usb1: usb@211000 { 318 usb1: usb@211000 {
319 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
318 dr_mode = "host"; 320 dr_mode = "host";
319 phy_type = "utmi"; 321 phy_type = "utmi";
320 }; 322 };
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index d41d08de7f7e..af4ebc8009e3 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -336,12 +336,14 @@
336/include/ "qoriq-gpio-0.dtsi" 336/include/ "qoriq-gpio-0.dtsi"
337/include/ "qoriq-usb2-mph-0.dtsi" 337/include/ "qoriq-usb2-mph-0.dtsi"
338 usb0: usb@210000 { 338 usb0: usb@210000 {
339 compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
339 phy_type = "utmi"; 340 phy_type = "utmi";
340 port0; 341 port0;
341 }; 342 };
342 343
343/include/ "qoriq-usb2-dr-0.dtsi" 344/include/ "qoriq-usb2-dr-0.dtsi"
344 usb1: usb@211000 { 345 usb1: usb@211000 {
346 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
345 dr_mode = "host"; 347 dr_mode = "host";
346 phy_type = "utmi"; 348 phy_type = "utmi";
347 }; 349 };
diff --git a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
index a63edd195ae5..b3e56929eee2 100644
--- a/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3060si-post.dtsi
@@ -291,6 +291,12 @@
291/include/ "qoriq-duart-1.dtsi" 291/include/ "qoriq-duart-1.dtsi"
292/include/ "qoriq-gpio-0.dtsi" 292/include/ "qoriq-gpio-0.dtsi"
293/include/ "qoriq-usb2-mph-0.dtsi" 293/include/ "qoriq-usb2-mph-0.dtsi"
294 usb@210000 {
295 compatible = "fsl-usb2-mph-v2.2", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
296 };
294/include/ "qoriq-usb2-dr-0.dtsi" 297/include/ "qoriq-usb2-dr-0.dtsi"
298 usb@211000 {
299 compatible = "fsl-usb2-dr-v2.2", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
300 };
295/include/ "qoriq-sec4.1-0.dtsi" 301/include/ "qoriq-sec4.1-0.dtsi"
296}; 302};
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 914074b91a85..64b6abea8464 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -339,12 +339,14 @@
339/include/ "qoriq-gpio-0.dtsi" 339/include/ "qoriq-gpio-0.dtsi"
340/include/ "qoriq-usb2-mph-0.dtsi" 340/include/ "qoriq-usb2-mph-0.dtsi"
341 usb0: usb@210000 { 341 usb0: usb@210000 {
342 compatible = "fsl-usb2-mph-v1.6", "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
342 phy_type = "utmi"; 343 phy_type = "utmi";
343 port0; 344 port0;
344 }; 345 };
345 346
346/include/ "qoriq-usb2-dr-0.dtsi" 347/include/ "qoriq-usb2-dr-0.dtsi"
347 usb1: usb@211000 { 348 usb1: usb@211000 {
349 compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
348 dr_mode = "host"; 350 dr_mode = "host";
349 phy_type = "utmi"; 351 phy_type = "utmi";
350 }; 352 };
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
index a1979ae334a7..3b0650a98478 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x24000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@24000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x24000 0x1000>; 42 reg = <0x24000 0x1000>;
43 ranges = <0x0 0x24000 0x1000>; 43 ranges = <0x0 0x24000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>; 46 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
index 4c4fdde1ec2a..96693b41f0f1 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x25000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@25000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x25000 0x1000>; 42 reg = <0x25000 0x1000>;
43 ranges = <0x0 0x25000 0x1000>; 43 ranges = <0x0 0x25000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>; 46 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
index 4b8ab438668a..6b3fab19da1f 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-2.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x26000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@26000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x26000 0x1000>; 42 reg = <0x26000 0x1000>;
43 ranges = <0x0 0x26000 0x1000>; 43 ranges = <0x0 0x26000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>; 46 interrupts = <31 2 0 0 32 2 0 0 33 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
index 40c9137729ae..0da592d93ddd 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-etsec1-3.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ] 2 * PQ3 eTSEC device tree stub [ @ offsets 0x27000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2011-2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@ ethernet@27000 {
41 compatible = "gianfar"; 41 compatible = "gianfar";
42 reg = <0x27000 0x1000>; 42 reg = <0x27000 0x1000>;
43 ranges = <0x0 0x27000 0x1000>; 43 ranges = <0x0 0x27000 0x1000>;
44 fsl,magic-packet;
44 local-mac-address = [ 00 00 00 00 00 00 ]; 45 local-mac-address = [ 00 00 00 00 00 00 ];
45 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>; 46 interrupts = <37 2 0 0 38 2 0 0 39 2 0 0>;
46}; 47};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index bf957a7fca2a..d4c9d5daab21 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -33,32 +33,32 @@
33 */ 33 */
34 34
35crypto@30000 { 35crypto@30000 {
36 compatible = "fsl,sec4.4", "fsl,sec4.0"; 36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 #address-cells = <1>; 37 #address-cells = <1>;
38 #size-cells = <1>; 38 #size-cells = <1>;
39 reg = <0x30000 0x10000>; 39 reg = <0x30000 0x10000>;
40 interrupts = <58 2 0 0>; 40 interrupts = <58 2 0 0>;
41 41
42 sec_jr0: jr@1000 { 42 sec_jr0: jr@1000 {
43 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 43 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
44 reg = <0x1000 0x1000>; 44 reg = <0x1000 0x1000>;
45 interrupts = <45 2 0 0>; 45 interrupts = <45 2 0 0>;
46 }; 46 };
47 47
48 sec_jr1: jr@2000 { 48 sec_jr1: jr@2000 {
49 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 49 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
50 reg = <0x2000 0x1000>; 50 reg = <0x2000 0x1000>;
51 interrupts = <45 2 0 0>; 51 interrupts = <45 2 0 0>;
52 }; 52 };
53 53
54 sec_jr2: jr@3000 { 54 sec_jr2: jr@3000 {
55 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 55 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
56 reg = <0x3000 0x1000>; 56 reg = <0x3000 0x1000>;
57 interrupts = <45 2 0 0>; 57 interrupts = <45 2 0 0>;
58 }; 58 };
59 59
60 sec_jr3: jr@4000 { 60 sec_jr3: jr@4000 {
61 compatible = "fsl,sec4.4-job-ring", "fsl,sec4.0-job-ring"; 61 compatible = "fsl,sec-v4.4-job-ring", "fsl,sec-v4.0-job-ring";
62 reg = <0x4000 0x1000>; 62 reg = <0x4000 0x1000>;
63 interrupts = <45 2 0 0>; 63 interrupts = <45 2 0 0>;
64 }; 64 };
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
index b9bada6a87dc..08f42271f86a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-mpic.dtsi
@@ -53,7 +53,7 @@ timer@41100 {
53 53
54msi0: msi@41600 { 54msi0: msi@41600 {
55 compatible = "fsl,mpic-msi"; 55 compatible = "fsl,mpic-msi";
56 reg = <0x41600 0x200>; 56 reg = <0x41600 0x200 0x44140 4>;
57 msi-available-ranges = <0 0x100>; 57 msi-available-ranges = <0 0x100>;
58 interrupts = < 58 interrupts = <
59 0xe0 0 0 0 59 0xe0 0 0 0
@@ -68,7 +68,7 @@ msi0: msi@41600 {
68 68
69msi1: msi@41800 { 69msi1: msi@41800 {
70 compatible = "fsl,mpic-msi"; 70 compatible = "fsl,mpic-msi";
71 reg = <0x41800 0x200>; 71 reg = <0x41800 0x200 0x45140 4>;
72 msi-available-ranges = <0 0x100>; 72 msi-available-ranges = <0 0x100>;
73 interrupts = < 73 interrupts = <
74 0xe8 0 0 0 74 0xe8 0 0 0
@@ -83,7 +83,7 @@ msi1: msi@41800 {
83 83
84msi2: msi@41a00 { 84msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi"; 85 compatible = "fsl,mpic-msi";
86 reg = <0x41a00 0x200>; 86 reg = <0x41a00 0x200 0x46140 4>;
87 msi-available-ranges = <0 0x100>; 87 msi-available-ranges = <0 0x100>;
88 interrupts = < 88 interrupts = <
89 0xf0 0 0 0 89 0xf0 0 0 0
diff --git a/arch/powerpc/boot/dts/ge_imp3a.dts b/arch/powerpc/boot/dts/ge_imp3a.dts
new file mode 100644
index 000000000000..fefae416a097
--- /dev/null
+++ b/arch/powerpc/boot/dts/ge_imp3a.dts
@@ -0,0 +1,255 @@
1/*
2 * GE IMP3A Device Tree Source
3 *
4 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: P2020 DS Device Tree Source
12 * Copyright 2009 Freescale Semiconductor Inc.
13 */
14
15/include/ "fsl/p2020si-pre.dtsi"
16
17/ {
18 model = "GE_IMP3A";
19 compatible = "ge,imp3a";
20
21 memory {
22 device_type = "memory";
23 };
24
25 lbc: localbus@fef05000 {
26 reg = <0 0xfef05000 0 0x1000>;
27
28 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
29 0x1 0x0 0x0 0xe0000000 0x08000000
30 0x2 0x0 0x0 0xe8000000 0x08000000
31 0x3 0x0 0x0 0xfc100000 0x00020000
32 0x4 0x0 0x0 0xfc000000 0x00008000
33 0x5 0x0 0x0 0xfc008000 0x00008000
34 0x6 0x0 0x0 0xfee00000 0x00040000
35 0x7 0x0 0x0 0xfee80000 0x00040000>;
36
37 /* nor@0,0 is a mirror of part of the memory in nor@1,0
38 nor@0,0 {
39 #address-cells = <1>;
40 #size-cells = <1>;
41 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
42 reg = <0x0 0x0 0x1000000>;
43 bank-width = <2>;
44 device-width = <1>;
45
46 partition@0 {
47 label = "firmware";
48 reg = <0x0 0x1000000>;
49 read-only;
50 };
51 };
52 */
53
54 nor@1,0 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "ge,imp3a-paged-flash", "cfi-flash";
58 reg = <0x1 0x0 0x8000000>;
59 bank-width = <2>;
60 device-width = <1>;
61
62 partition@0 {
63 label = "user";
64 reg = <0x0 0x7800000>;
65 };
66
67 partition@7800000 {
68 label = "firmware";
69 reg = <0x7800000 0x800000>;
70 read-only;
71 };
72 };
73
74 nvram@3,0 {
75 device_type = "nvram";
76 compatible = "simtek,stk14ca8";
77 reg = <0x3 0x0 0x20000>;
78 };
79
80 fpga@4,0 {
81 compatible = "ge,imp3a-fpga-regs";
82 reg = <0x4 0x0 0x20>;
83 };
84
85 gef_pic: pic@4,20 {
86 #interrupt-cells = <1>;
87 interrupt-controller;
88 device_type = "interrupt-controller";
89 compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
90 reg = <0x4 0x20 0x20>;
91 interrupts = <6 7 0 0>;
92 };
93
94 gef_gpio: gpio@4,400 {
95 #gpio-cells = <2>;
96 compatible = "ge,imp3a-gpio";
97 reg = <0x4 0x400 0x24>;
98 gpio-controller;
99 };
100
101 wdt@4,800 {
102 compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
103 "gef,fpga-wdt";
104 reg = <0x4 0x800 0x8>;
105 interrupts = <10 4>;
106 interrupt-parent = <&gef_pic>;
107 };
108
109 /* Second watchdog available, driver currently supports one.
110 wdt@4,808 {
111 compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
112 "gef,fpga-wdt";
113 reg = <0x4 0x808 0x8>;
114 interrupts = <9 4>;
115 interrupt-parent = <&gef_pic>;
116 };
117 */
118
119 nand@6,0 {
120 compatible = "fsl,elbc-fcm-nand";
121 reg = <0x6 0x0 0x40000>;
122 };
123
124 nand@7,0 {
125 compatible = "fsl,elbc-fcm-nand";
126 reg = <0x7 0x0 0x40000>;
127 };
128 };
129
130 soc: soc@fef00000 {
131 ranges = <0x0 0 0xfef00000 0x100000>;
132
133 i2c@3000 {
134 hwmon@48 {
135 compatible = "national,lm92";
136 reg = <0x48>;
137 };
138
139 hwmon@4c {
140 compatible = "adi,adt7461";
141 reg = <0x4c>;
142 };
143
144 rtc@51 {
145 compatible = "epson,rx8581";
146 reg = <0x51>;
147 };
148
149 eti@6b {
150 compatible = "dallas,ds1682";
151 reg = <0x6b>;
152 };
153 };
154
155 usb@22000 {
156 phy_type = "ulpi";
157 dr_mode = "host";
158 };
159
160 mdio@24520 {
161 phy0: ethernet-phy@0 {
162 interrupt-parent = <&gef_pic>;
163 interrupts = <0xc 0x4>;
164 reg = <0x1>;
165 };
166 phy1: ethernet-phy@1 {
167 interrupt-parent = <&gef_pic>;
168 interrupts = <0xb 0x4>;
169 reg = <0x2>;
170 };
171 tbi0: tbi-phy@11 {
172 reg = <0x11>;
173 device_type = "tbi-phy";
174 };
175 };
176
177 mdio@25520 {
178 tbi1: tbi-phy@11 {
179 reg = <0x11>;
180 device_type = "tbi-phy";
181 };
182 };
183
184 mdio@26520 {
185 status = "disabled";
186 };
187
188 enet0: ethernet@24000 {
189 tbi-handle = <&tbi0>;
190 phy-handle = <&phy0>;
191 phy-connection-type = "gmii";
192 };
193
194 enet1: ethernet@25000 {
195 tbi-handle = <&tbi1>;
196 phy-handle = <&phy1>;
197 phy-connection-type = "gmii";
198 };
199
200 enet2: ethernet@26000 {
201 status = "disabled";
202 };
203 };
204
205 pci0: pcie@fef08000 {
206 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
207 0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
208 reg = <0 0xfef08000 0 0x1000>;
209
210 pcie@0 {
211 ranges = <0x2000000 0x0 0xc0000000
212 0x2000000 0x0 0xc0000000
213 0x0 0x20000000
214
215 0x1000000 0x0 0x0
216 0x1000000 0x0 0x0
217 0x0 0x10000>;
218 };
219 };
220
221 pci1: pcie@fef09000 {
222 reg = <0 0xfef09000 0 0x1000>;
223 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
224 0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
225
226 pcie@0 {
227 ranges = <0x2000000 0x0 0xa0000000
228 0x2000000 0x0 0xa0000000
229 0x0 0x20000000
230
231 0x1000000 0x0 0x0
232 0x1000000 0x0 0x0
233 0x0 0x10000>;
234 };
235
236 };
237
238 pci2: pcie@fef0a000 {
239 reg = <0 0xfef0a000 0 0x1000>;
240 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
241 0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
242
243 pcie@0 {
244 ranges = <0x2000000 0x0 0x80000000
245 0x2000000 0x0 0x80000000
246 0x0 0x20000000
247
248 0x1000000 0x0 0x0
249 0x1000000 0x0 0x0
250 0x0 0x10000>;
251 };
252 };
253};
254
255/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index c0e450a551bf..81dd513d6308 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -405,6 +405,10 @@
405 reg = <0x1>; 405 reg = <0x1>;
406 device_type = "ethernet-phy"; 406 device_type = "ethernet-phy";
407 }; 407 };
408 tbi-phy@2 {
409 device_type = "tbi-phy";
410 reg = <0x2>;
411 };
408 }; 412 };
409 413
410 qeic: interrupt-controller@80 { 414 qeic: interrupt-controller@80 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dts b/arch/powerpc/boot/dts/mpc8536ds.dts
index c15881574fdc..19736222a0b9 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8536 DS Device Tree Source 2 * MPC8536 DS Device Tree Source
3 * 3 *
4 * Copyright 2008 Freescale Semiconductor, Inc. 4 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -34,6 +34,10 @@
34 34
35 lbc: localbus@ffe05000 { 35 lbc: localbus@ffe05000 {
36 reg = <0 0xffe05000 0 0x1000>; 36 reg = <0 0xffe05000 0 0x1000>;
37
38 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
39 0x2 0x0 0x0 0xffa00000 0x00040000
40 0x3 0x0 0x0 0xffdf0000 0x00008000>;
37 }; 41 };
38 42
39 board_soc: soc: soc@ffe00000 { 43 board_soc: soc: soc@ffe00000 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds.dtsi b/arch/powerpc/boot/dts/mpc8536ds.dtsi
index 1462e4cf49d7..cc46dbd9746d 100644
--- a/arch/powerpc/boot/dts/mpc8536ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8536ds.dtsi
@@ -32,6 +32,99 @@
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */ 33 */
34 34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x8000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 reg = <0x0 0x03000000>;
46 label = "ramdisk-nor";
47 };
48
49 partition@3000000 {
50 reg = <0x03000000 0x00e00000>;
51 label = "diagnostic-nor";
52 read-only;
53 };
54
55 partition@3e00000 {
56 reg = <0x03e00000 0x00200000>;
57 label = "dink-nor";
58 read-only;
59 };
60
61 partition@4000000 {
62 reg = <0x04000000 0x00400000>;
63 label = "kernel-nor";
64 };
65
66 partition@4400000 {
67 reg = <0x04400000 0x03b00000>;
68 label = "fs-nor";
69 };
70
71 partition@7f00000 {
72 reg = <0x07f00000 0x00080000>;
73 label = "dtb-nor";
74 };
75
76 partition@7f80000 {
77 reg = <0x07f80000 0x00080000>;
78 label = "u-boot-nor";
79 read-only;
80 };
81 };
82
83 nand@2,0 {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "fsl,mpc8536-fcm-nand",
87 "fsl,elbc-fcm-nand";
88 reg = <0x2 0x0 0x40000>;
89
90 partition@0 {
91 reg = <0x0 0x02000000>;
92 label = "u-boot-nand";
93 read-only;
94 };
95
96 partition@2000000 {
97 reg = <0x02000000 0x10000000>;
98 label = "fs-nand";
99 };
100
101 partition@12000000 {
102 reg = <0x12000000 0x08000000>;
103 label = "ramdisk-nand";
104 };
105
106 partition@1a000000 {
107 reg = <0x1a000000 0x04000000>;
108 label = "kernel-nand";
109 };
110
111 partition@1e000000 {
112 reg = <0x1e000000 0x01000000>;
113 label = "dtb-nand";
114 };
115
116 partition@1f000000 {
117 reg = <0x1f000000 0x21000000>;
118 label = "empty-nand";
119 };
120 };
121
122 board-control@3,0 {
123 compatible = "fsl,mpc8536ds-fpga-pixis";
124 reg = <0x3 0x0 0x8000>;
125 };
126};
127
35&board_soc { 128&board_soc {
36 i2c@3100 { 129 i2c@3100 {
37 rtc@68 { 130 rtc@68 {
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index 8f4b929b1d1d..f8a3b3413176 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC8536DS Device Tree Source (36-bit address map) 2 * MPC8536DS Device Tree Source (36-bit address map)
3 * 3 *
4 * Copyright 2008-2009 Freescale Semiconductor, Inc. 4 * Copyright 2008-2009, 2011 Freescale Semiconductor, Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -33,7 +33,11 @@
33 }; 33 };
34 34
35 lbc: localbus@ffe05000 { 35 lbc: localbus@ffe05000 {
36 reg = <0 0xffe05000 0 0x1000>; 36 reg = <0xf 0xffe05000 0 0x1000>;
37
38 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
39 0x2 0x0 0xf 0xffa00000 0x00040000
40 0x3 0x0 0xf 0xffdf0000 0x00008000>;
37 }; 41 };
38 42
39 board_soc: soc: soc@fffe00000 { 43 board_soc: soc: soc@fffe00000 {
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
deleted file mode 100644
index 07b8dae0f46e..000000000000
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ /dev/null
@@ -1,306 +0,0 @@
1/*
2 * MPC8548 CDS Device Tree Source
3 *
4 * Copyright 2006, 2008 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8548si-pre.dtsi"
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17
18 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
21 ethernet2 = &enet2;
22 ethernet3 = &enet3;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
33 };
34
35 lbc: localbus@e0005000 {
36 reg = <0 0xe0005000 0 0x1000>;
37 };
38
39 soc: soc8548@e0000000 {
40 ranges = <0 0x0 0xe0000000 0x100000>;
41
42 i2c@3000 {
43 eeprom@50 {
44 compatible = "atmel,24c64";
45 reg = <0x50>;
46 };
47
48 eeprom@56 {
49 compatible = "atmel,24c64";
50 reg = <0x56>;
51 };
52
53 eeprom@57 {
54 compatible = "atmel,24c64";
55 reg = <0x57>;
56 };
57 };
58
59 i2c@3100 {
60 eeprom@50 {
61 compatible = "atmel,24c64";
62 reg = <0x50>;
63 };
64 };
65
66 enet0: ethernet@24000 {
67 tbi-handle = <&tbi0>;
68 phy-handle = <&phy0>;
69 };
70
71 mdio@24520 {
72 phy0: ethernet-phy@0 {
73 interrupts = <5 1 0 0>;
74 reg = <0x0>;
75 device_type = "ethernet-phy";
76 };
77 phy1: ethernet-phy@1 {
78 interrupts = <5 1 0 0>;
79 reg = <0x1>;
80 device_type = "ethernet-phy";
81 };
82 phy2: ethernet-phy@2 {
83 interrupts = <5 1 0 0>;
84 reg = <0x2>;
85 device_type = "ethernet-phy";
86 };
87 phy3: ethernet-phy@3 {
88 interrupts = <5 1 0 0>;
89 reg = <0x3>;
90 device_type = "ethernet-phy";
91 };
92 tbi0: tbi-phy@11 {
93 reg = <0x11>;
94 device_type = "tbi-phy";
95 };
96 };
97
98 enet1: ethernet@25000 {
99 tbi-handle = <&tbi1>;
100 phy-handle = <&phy1>;
101 };
102
103 mdio@25520 {
104 tbi1: tbi-phy@11 {
105 reg = <0x11>;
106 device_type = "tbi-phy";
107 };
108 };
109
110 enet2: ethernet@26000 {
111 tbi-handle = <&tbi2>;
112 phy-handle = <&phy2>;
113 };
114
115 mdio@26520 {
116 tbi2: tbi-phy@11 {
117 reg = <0x11>;
118 device_type = "tbi-phy";
119 };
120 };
121
122 enet3: ethernet@27000 {
123 tbi-handle = <&tbi3>;
124 phy-handle = <&phy3>;
125 };
126
127 mdio@27520 {
128 tbi3: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
131 };
132 };
133 };
134
135 pci0: pci@e0008000 {
136 reg = <0 0xe0008000 0 0x1000>;
137 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
138 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
139 clock-frequency = <66666666>;
140 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
141 interrupt-map = <
142 /* IDSEL 0x4 (PCIX Slot 2) */
143 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
144 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
145 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
146 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
147
148 /* IDSEL 0x5 (PCIX Slot 3) */
149 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
150 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
151 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
152 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
153
154 /* IDSEL 0x6 (PCIX Slot 4) */
155 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
156 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
157 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
158 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
159
160 /* IDSEL 0x8 (PCIX Slot 5) */
161 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
162 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
163 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
164 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
165
166 /* IDSEL 0xC (Tsi310 bridge) */
167 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
168 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
169 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
170 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
171
172 /* IDSEL 0x14 (Slot 2) */
173 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
174 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
175 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
176 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
177
178 /* IDSEL 0x15 (Slot 3) */
179 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
180 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
181 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
182 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
183
184 /* IDSEL 0x16 (Slot 4) */
185 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
186 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
187 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
188 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
189
190 /* IDSEL 0x18 (Slot 5) */
191 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
192 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
193 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
194 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
195
196 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
197 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
198 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
199 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
200 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
201
202 pci_bridge@1c {
203 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
204 interrupt-map = <
205
206 /* IDSEL 0x00 (PrPMC Site) */
207 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
208 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
209 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
210 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
211
212 /* IDSEL 0x04 (VIA chip) */
213 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
214 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
215 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
216 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
217
218 /* IDSEL 0x05 (8139) */
219 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
220
221 /* IDSEL 0x06 (Slot 6) */
222 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
223 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
224 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
225 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
226
227 /* IDESL 0x07 (Slot 7) */
228 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
229 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
230 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
231 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
232
233 reg = <0xe000 0x0 0x0 0x0 0x0>;
234 #interrupt-cells = <1>;
235 #size-cells = <2>;
236 #address-cells = <3>;
237 ranges = <0x2000000 0x0 0x80000000
238 0x2000000 0x0 0x80000000
239 0x0 0x20000000
240 0x1000000 0x0 0x0
241 0x1000000 0x0 0x0
242 0x0 0x80000>;
243 clock-frequency = <33333333>;
244
245 isa@4 {
246 device_type = "isa";
247 #interrupt-cells = <2>;
248 #size-cells = <1>;
249 #address-cells = <2>;
250 reg = <0x2000 0x0 0x0 0x0 0x0>;
251 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
252 interrupt-parent = <&i8259>;
253
254 i8259: interrupt-controller@20 {
255 interrupt-controller;
256 device_type = "interrupt-controller";
257 reg = <0x1 0x20 0x2
258 0x1 0xa0 0x2
259 0x1 0x4d0 0x2>;
260 #address-cells = <0>;
261 #interrupt-cells = <2>;
262 compatible = "chrp,iic";
263 interrupts = <0 1 0 0>;
264 interrupt-parent = <&mpic>;
265 };
266
267 rtc@70 {
268 compatible = "pnpPNP,b00";
269 reg = <0x1 0x70 0x2>;
270 };
271 };
272 };
273 };
274
275 pci1: pci@e0009000 {
276 reg = <0 0xe0009000 0 0x1000>;
277 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
278 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
279 clock-frequency = <66666666>;
280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
281 interrupt-map = <
282
283 /* IDSEL 0x15 */
284 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
285 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
286 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
287 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
288 };
289
290 pci2: pcie@e000a000 {
291 reg = <0 0xe000a000 0 0x1000>;
292 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
293 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
294 pcie@0 {
295 ranges = <0x2000000 0x0 0xa0000000
296 0x2000000 0x0 0xa0000000
297 0x0 0x20000000
298
299 0x1000000 0x0 0x0
300 0x1000000 0x0 0x0
301 0x0 0x100000>;
302 };
303 };
304};
305
306/include/ "fsl/mpc8548si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dtsi b/arch/powerpc/boot/dts/mpc8548cds.dtsi
new file mode 100644
index 000000000000..c61f525e4740
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds.dtsi
@@ -0,0 +1,306 @@
1/*
2 * MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x01000000>;
41 bank-width = <2>;
42 device-width = <2>;
43
44 partition@0 {
45 reg = <0x0 0x0b00000>;
46 label = "ramdisk-nor";
47 };
48
49 partition@300000 {
50 reg = <0x0b00000 0x0400000>;
51 label = "kernel-nor";
52 };
53
54 partition@700000 {
55 reg = <0x0f00000 0x060000>;
56 label = "dtb-nor";
57 };
58
59 partition@760000 {
60 reg = <0x0f60000 0x020000>;
61 label = "env-nor";
62 read-only;
63 };
64
65 partition@780000 {
66 reg = <0x0f80000 0x080000>;
67 label = "u-boot-nor";
68 read-only;
69 };
70 };
71
72 board-control@1,0 {
73 compatible = "fsl,mpc8548cds-fpga";
74 reg = <0x1 0x0 0x1000>;
75 };
76};
77
78&board_soc {
79 i2c@3000 {
80 eeprom@50 {
81 compatible = "atmel,24c64";
82 reg = <0x50>;
83 };
84
85 eeprom@56 {
86 compatible = "atmel,24c64";
87 reg = <0x56>;
88 };
89
90 eeprom@57 {
91 compatible = "atmel,24c64";
92 reg = <0x57>;
93 };
94 };
95
96 i2c@3100 {
97 eeprom@50 {
98 compatible = "atmel,24c64";
99 reg = <0x50>;
100 };
101 };
102
103 enet0: ethernet@24000 {
104 tbi-handle = <&tbi0>;
105 phy-handle = <&phy0>;
106 };
107
108 mdio@24520 {
109 phy0: ethernet-phy@0 {
110 interrupts = <5 1 0 0>;
111 reg = <0x0>;
112 device_type = "ethernet-phy";
113 };
114 phy1: ethernet-phy@1 {
115 interrupts = <5 1 0 0>;
116 reg = <0x1>;
117 device_type = "ethernet-phy";
118 };
119 phy2: ethernet-phy@2 {
120 interrupts = <5 1 0 0>;
121 reg = <0x2>;
122 device_type = "ethernet-phy";
123 };
124 phy3: ethernet-phy@3 {
125 interrupts = <5 1 0 0>;
126 reg = <0x3>;
127 device_type = "ethernet-phy";
128 };
129 tbi0: tbi-phy@11 {
130 reg = <0x11>;
131 device_type = "tbi-phy";
132 };
133 };
134
135 enet1: ethernet@25000 {
136 tbi-handle = <&tbi1>;
137 phy-handle = <&phy1>;
138 };
139
140 mdio@25520 {
141 tbi1: tbi-phy@11 {
142 reg = <0x11>;
143 device_type = "tbi-phy";
144 };
145 };
146
147 enet2: ethernet@26000 {
148 tbi-handle = <&tbi2>;
149 phy-handle = <&phy2>;
150 };
151
152 mdio@26520 {
153 tbi2: tbi-phy@11 {
154 reg = <0x11>;
155 device_type = "tbi-phy";
156 };
157 };
158
159 enet3: ethernet@27000 {
160 tbi-handle = <&tbi3>;
161 phy-handle = <&phy3>;
162 };
163
164 mdio@27520 {
165 tbi3: tbi-phy@11 {
166 reg = <0x11>;
167 device_type = "tbi-phy";
168 };
169 };
170};
171
172&board_pci0 {
173 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
174 interrupt-map = <
175 /* IDSEL 0x4 (PCIX Slot 2) */
176 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
177 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
178 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
179 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
180
181 /* IDSEL 0x5 (PCIX Slot 3) */
182 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
183 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
184 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
185 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
186
187 /* IDSEL 0x6 (PCIX Slot 4) */
188 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
189 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
190 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
191 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
192
193 /* IDSEL 0x8 (PCIX Slot 5) */
194 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
195 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
196 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
197 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
198
199 /* IDSEL 0xC (Tsi310 bridge) */
200 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
201 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
202 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
203 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
204
205 /* IDSEL 0x14 (Slot 2) */
206 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
207 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
208 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
209 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
210
211 /* IDSEL 0x15 (Slot 3) */
212 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
213 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
214 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
215 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
216
217 /* IDSEL 0x16 (Slot 4) */
218 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
219 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
220 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
221 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
222
223 /* IDSEL 0x18 (Slot 5) */
224 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
225 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
226 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
227 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
228
229 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
230 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
231 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
232 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
233 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
234
235 pci_bridge@1c {
236 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
237 interrupt-map = <
238
239 /* IDSEL 0x00 (PrPMC Site) */
240 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
241 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
242 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
243 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
244
245 /* IDSEL 0x04 (VIA chip) */
246 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
247 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
248 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
249 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
250
251 /* IDSEL 0x05 (8139) */
252 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
253
254 /* IDSEL 0x06 (Slot 6) */
255 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
256 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
257 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
258 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
259
260 /* IDESL 0x07 (Slot 7) */
261 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
262 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
263 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
264 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
265
266 reg = <0xe000 0x0 0x0 0x0 0x0>;
267 #interrupt-cells = <1>;
268 #size-cells = <2>;
269 #address-cells = <3>;
270 ranges = <0x2000000 0x0 0x80000000
271 0x2000000 0x0 0x80000000
272 0x0 0x20000000
273 0x1000000 0x0 0x0
274 0x1000000 0x0 0x0
275 0x0 0x80000>;
276 clock-frequency = <33333333>;
277
278 isa@4 {
279 device_type = "isa";
280 #interrupt-cells = <2>;
281 #size-cells = <1>;
282 #address-cells = <2>;
283 reg = <0x2000 0x0 0x0 0x0 0x0>;
284 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
285 interrupt-parent = <&i8259>;
286
287 i8259: interrupt-controller@20 {
288 interrupt-controller;
289 device_type = "interrupt-controller";
290 reg = <0x1 0x20 0x2
291 0x1 0xa0 0x2
292 0x1 0x4d0 0x2>;
293 #address-cells = <0>;
294 #interrupt-cells = <2>;
295 compatible = "chrp,iic";
296 interrupts = <0 1 0 0>;
297 interrupt-parent = <&mpic>;
298 };
299
300 rtc@70 {
301 compatible = "pnpPNP,b00";
302 reg = <0x1 0x70 0x2>;
303 };
304 };
305 };
306};
diff --git a/arch/powerpc/boot/dts/mpc8548cds_32b.dts b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
new file mode 100644
index 000000000000..6fd63163fc6b
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_32b.dts
@@ -0,0 +1,86 @@
1/*
2 * MPC8548 CDS Device Tree Source (32-bit address map)
3 *
4 * Copyright 2006, 2008, 2011-2012 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8548si-pre.dtsi"
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17
18 memory {
19 device_type = "memory";
20 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
21 };
22
23 board_lbc: lbc: localbus@e0005000 {
24 reg = <0 0xe0005000 0 0x1000>;
25
26 ranges = <0x0 0x0 0x0 0xff000000 0x01000000
27 0x1 0x0 0x0 0xf8004000 0x00001000>;
28
29 };
30
31 board_soc: soc: soc8548@e0000000 {
32 ranges = <0 0x0 0xe0000000 0x100000>;
33 };
34
35 board_pci0: pci0: pci@e0008000 {
36 reg = <0 0xe0008000 0 0x1000>;
37 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
38 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
39 clock-frequency = <66666666>;
40 };
41
42 pci1: pci@e0009000 {
43 reg = <0 0xe0009000 0 0x1000>;
44 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
45 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
46 clock-frequency = <66666666>;
47 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
48 interrupt-map = <
49
50 /* IDSEL 0x15 */
51 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
52 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
53 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
54 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
55 };
56
57 pci2: pcie@e000a000 {
58 reg = <0 0xe000a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 rio: rapidio@e00c0000 {
73 reg = <0x0 0xe00c0000 0x0 0x20000>;
74 port1 {
75 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;
76 };
77 };
78};
79
80/*
81 * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
82 * for interrupt-map & interrupt-map-mask.
83 */
84
85/include/ "fsl/mpc8548si-post.dtsi"
86/include/ "mpc8548cds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8548cds_36b.dts b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
new file mode 100644
index 000000000000..10e551b11bd6
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8548cds_36b.dts
@@ -0,0 +1,86 @@
1/*
2 * MPC8548 CDS Device Tree Source (36-bit address map)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/include/ "fsl/mpc8548si-pre.dtsi"
13
14/ {
15 model = "MPC8548CDS";
16 compatible = "MPC8548CDS", "MPC85xxCDS";
17
18 memory {
19 device_type = "memory";
20 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
21 };
22
23 board_lbc: lbc: localbus@fe0005000 {
24 reg = <0xf 0xe0005000 0 0x1000>;
25
26 ranges = <0x0 0x0 0xf 0xff000000 0x01000000
27 0x1 0x0 0xf 0xf8004000 0x00001000>;
28
29 };
30
31 board_soc: soc: soc8548@fe0000000 {
32 ranges = <0 0xf 0xe0000000 0x100000>;
33 };
34
35 board_pci0: pci0: pci@fe0008000 {
36 reg = <0xf 0xe0008000 0 0x1000>;
37 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000
38 0x1000000 0x0 0x00000000 0xf 0xe2000000 0x0 0x800000>;
39 clock-frequency = <66666666>;
40 };
41
42 pci1: pci@fe0009000 {
43 reg = <0xf 0xe0009000 0 0x1000>;
44 ranges = <0x2000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
45 0x1000000 0x0 0x00000000 0xf 0xe2800000 0x0 0x800000>;
46 clock-frequency = <66666666>;
47 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
48 interrupt-map = <
49
50 /* IDSEL 0x15 */
51 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
52 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
53 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
54 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
55 };
56
57 pci2: pcie@fe000a000 {
58 reg = <0xf 0xe000a000 0 0x1000>;
59 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x100000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 rio: rapidio@fe00c0000 {
73 reg = <0xf 0xe00c0000 0x0 0x20000>;
74 port1 {
75 ranges = <0x0 0x0 0xc 0x40000000 0x0 0x20000000>;
76 };
77 };
78};
79
80/*
81 * mpc8548cds.dtsi must be last to ensure board_pci0 overrides pci0 settings
82 * for interrupt-map & interrupt-map-mask.
83 */
84
85/include/ "fsl/mpc8548si-post.dtsi"
86/include/ "mpc8548cds.dtsi"
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dtsi b/arch/powerpc/boot/dts/mpc8572ds.dtsi
index c3d4fac0532a..14178944e220 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dtsi
+++ b/arch/powerpc/boot/dts/mpc8572ds.dtsi
@@ -41,37 +41,47 @@
41 bank-width = <2>; 41 bank-width = <2>;
42 device-width = <1>; 42 device-width = <1>;
43 43
44 ramdisk@0 { 44 partition@0 {
45 reg = <0x0 0x03000000>; 45 reg = <0x0 0x03000000>;
46 read-only; 46 label = "ramdisk-nor";
47 }; 47 };
48 48
49 diagnostic@3000000 { 49 partition@3000000 {
50 reg = <0x03000000 0x00e00000>; 50 reg = <0x03000000 0x00e00000>;
51 label = "diagnostic-nor";
51 read-only; 52 read-only;
52 }; 53 };
53 54
54 dink@3e00000 { 55 partition@3e00000 {
55 reg = <0x03e00000 0x00200000>; 56 reg = <0x03e00000 0x00200000>;
57 label = "dink-nor";
56 read-only; 58 read-only;
57 }; 59 };
58 60
59 kernel@4000000 { 61 partition@4000000 {
60 reg = <0x04000000 0x00400000>; 62 reg = <0x04000000 0x00400000>;
61 read-only; 63 label = "kernel-nor";
62 }; 64 };
63 65
64 jffs2@4400000 { 66 partition@4400000 {
65 reg = <0x04400000 0x03b00000>; 67 reg = <0x04400000 0x03b00000>;
68 label = "fs-nor";
69 };
70
71 partition@7f00000 {
72 reg = <0x07f00000 0x00060000>;
73 label = "dtb-nor";
66 }; 74 };
67 75
68 dtb@7f00000 { 76 partition@7f60000 {
69 reg = <0x07f00000 0x00080000>; 77 reg = <0x07f60000 0x00020000>;
78 label = "env-nor";
70 read-only; 79 read-only;
71 }; 80 };
72 81
73 u-boot@7f80000 { 82 partition@7f80000 {
74 reg = <0x07f80000 0x00080000>; 83 reg = <0x07f80000 0x00080000>;
84 label = "u-boot-nor";
75 read-only; 85 read-only;
76 }; 86 };
77 }; 87 };
@@ -83,31 +93,35 @@
83 "fsl,elbc-fcm-nand"; 93 "fsl,elbc-fcm-nand";
84 reg = <0x2 0x0 0x40000>; 94 reg = <0x2 0x0 0x40000>;
85 95
86 u-boot@0 { 96 partition@0 {
87 reg = <0x0 0x02000000>; 97 reg = <0x0 0x02000000>;
98 label = "u-boot-nand";
88 read-only; 99 read-only;
89 }; 100 };
90 101
91 jffs2@2000000 { 102 partition@2000000 {
92 reg = <0x02000000 0x10000000>; 103 reg = <0x02000000 0x10000000>;
104 label = "fs-nand";
93 }; 105 };
94 106
95 ramdisk@12000000 { 107 partition@12000000 {
96 reg = <0x12000000 0x08000000>; 108 reg = <0x12000000 0x08000000>;
97 read-only; 109 label = "ramdisk-nand";
98 }; 110 };
99 111
100 kernel@1a000000 { 112 partition@1a000000 {
101 reg = <0x1a000000 0x04000000>; 113 reg = <0x1a000000 0x04000000>;
114 label = "kernel-nand";
102 }; 115 };
103 116
104 dtb@1e000000 { 117 partition@1e000000 {
105 reg = <0x1e000000 0x01000000>; 118 reg = <0x1e000000 0x01000000>;
106 read-only; 119 label = "dtb-nand";
107 }; 120 };
108 121
109 empty@1f000000 { 122 partition@1f000000 {
110 reg = <0x1f000000 0x21000000>; 123 reg = <0x1f000000 0x21000000>;
124 label = "empty-nand";
111 }; 125 };
112 }; 126 };
113 127
diff --git a/arch/powerpc/boot/dts/p1010rdb.dtsi b/arch/powerpc/boot/dts/p1010rdb.dtsi
index d4c4a7730285..49776143a1b8 100644
--- a/arch/powerpc/boot/dts/p1010rdb.dtsi
+++ b/arch/powerpc/boot/dts/p1010rdb.dtsi
@@ -138,7 +138,7 @@
138 #size-cells = <1>; 138 #size-cells = <1>;
139 compatible = "spansion,s25sl12801"; 139 compatible = "spansion,s25sl12801";
140 reg = <0>; 140 reg = <0>;
141 spi-max-frequency = <50000000>; 141 spi-max-frequency = <40000000>;
142 142
143 partition@0 { 143 partition@0 {
144 /* 1MB for u-boot Bootloader Image */ 144 /* 1MB for u-boot Bootloader Image */
@@ -196,7 +196,7 @@
196 }; 196 };
197 197
198 tbi-phy@3 { 198 tbi-phy@3 {
199 device-type = "tbi-phy"; 199 device_type = "tbi-phy";
200 reg = <0x3>; 200 reg = <0x3>;
201 }; 201 };
202 }; 202 };
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
new file mode 100644
index 000000000000..c952cd37cf6d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -0,0 +1,247 @@
1/*
2 * P1020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p1020-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 7MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00700000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1100000 {
120 /* 15MB for JFFS2 based Root file System */
121 reg = <0x01100000 0x00f00000>;
122 label = "NAND Writable User area";
123 };
124 };
125
126 L2switch@2,0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "vitesse-7385";
130 reg = <0x2 0x0 0x20000>;
131 };
132
133 cpld@3,0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "cpld";
137 reg = <0x3 0x0 0x20000>;
138 read-only;
139 };
140};
141
142&soc {
143 i2c@3000 {
144 rtc@68 {
145 compatible = "pericom,pt7c4338";
146 reg = <0x68>;
147 };
148 };
149
150 spi@7000 {
151 flash@0 {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "spansion,s25sl12801";
155 reg = <0>;
156 spi-max-frequency = <40000000>; /* input clock */
157
158 partition@u-boot {
159 /* 512KB for u-boot Bootloader Image */
160 reg = <0x0 0x00080000>;
161 label = "u-boot";
162 read-only;
163 };
164
165 partition@dtb {
166 /* 512KB for DTB Image*/
167 reg = <0x00080000 0x00080000>;
168 label = "dtb";
169 };
170
171 partition@kernel {
172 /* 4MB for Linux Kernel Image */
173 reg = <0x00100000 0x00400000>;
174 label = "kernel";
175 };
176
177 partition@fs {
178 /* 4MB for Compressed RFS Image */
179 reg = <0x00500000 0x00400000>;
180 label = "file system";
181 };
182
183 partition@jffs-fs {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "file system jffs2";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 /* USB2 is shared with localbus, so it must be disabled
196 by default. We can't put 'status = "disabled";' here
197 since U-Boot doesn't clear the status property when
198 it enables USB2. OTOH, U-Boot does create a new node
199 when there isn't any. So, just comment it out.
200 usb@23000 {
201 phy_type = "ulpi";
202 };
203 */
204
205 mdio@24000 {
206 phy0: ethernet-phy@0 {
207 interrupt-parent = <&mpic>;
208 interrupts = <3 1>;
209 reg = <0x0>;
210 };
211
212 phy1: ethernet-phy@1 {
213 interrupt-parent = <&mpic>;
214 interrupts = <2 1>;
215 reg = <0x1>;
216 };
217
218 tbi0: tbi-phy@11 {
219 device_type = "tbi-phy";
220 reg = <0x11>;
221 };
222 };
223
224 mdio@25000 {
225 tbi1: tbi-phy@11 {
226 reg = <0x11>;
227 device_type = "tbi-phy";
228 };
229 };
230
231 enet0: ethernet@b0000 {
232 fixed-link = <1 1 1000 0 0>;
233 phy-connection-type = "rgmii-id";
234
235 };
236
237 enet1: ethernet@b1000 {
238 phy-handle = <&phy0>;
239 tbi-handle = <&tbi1>;
240 phy-connection-type = "sgmii";
241 };
242
243 enet2: ethernet@b2000 {
244 phy-handle = <&phy1>;
245 phy-connection-type = "rgmii-id";
246 };
247};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
new file mode 100644
index 000000000000..4de69b726dc5
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_32b.dts
@@ -0,0 +1,90 @@
1/*
2 * P1020 RDB-PC Device Tree Source (32-bit address map)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1020RDB-PC";
38 compatible = "fsl,P1020RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000
51 0x3 0x0 0x0 0xffa00000 0x00020000>;
52 };
53
54 soc: soc@ffe00000 {
55 ranges = <0x0 0x0 0xffe00000 0x100000>;
56 };
57
58 pci0: pcie@ffe09000 {
59 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
60 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
61 reg = <0 0xffe09000 0 0x1000>;
62 pcie@0 {
63 ranges = <0x2000000 0x0 0xa0000000
64 0x2000000 0x0 0xa0000000
65 0x0 0x20000000
66
67 0x1000000 0x0 0x0
68 0x1000000 0x0 0x0
69 0x0 0x100000>;
70 };
71 };
72
73 pci1: pcie@ffe0a000 {
74 reg = <0 0xffe0a000 0 0x1000>;
75 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
76 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
77 pcie@0 {
78 ranges = <0x2000000 0x0 0x80000000
79 0x2000000 0x0 0x80000000
80 0x0 0x20000000
81
82 0x1000000 0x0 0x0
83 0x1000000 0x0 0x0
84 0x0 0x100000>;
85 };
86 };
87};
88
89/include/ "p1020rdb-pc.dtsi"
90/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
new file mode 100644
index 000000000000..5237da7441bc
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_36b.dts
@@ -0,0 +1,90 @@
1/*
2 * P1020 RDB-PC Device Tree Source (36-bit address map)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1020si-pre.dtsi"
36/ {
37 model = "fsl,P1020RDB-PC";
38 compatible = "fsl,P1020RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00040000
51 0x3 0x0 0xf 0xffa00000 0x00020000>;
52 };
53
54 soc: soc@fffe00000 {
55 ranges = <0x0 0xf 0xffe00000 0x100000>;
56 };
57
58 pci0: pcie@fffe09000 {
59 reg = <0xf 0xffe09000 0 0x1000>;
60 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
61 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
62 pcie@0 {
63 ranges = <0x2000000 0x0 0xc0000000
64 0x2000000 0x0 0xc0000000
65 0x0 0x20000000
66
67 0x1000000 0x0 0x0
68 0x1000000 0x0 0x0
69 0x0 0x100000>;
70 };
71 };
72
73 pci1: pcie@fffe0a000 {
74 reg = <0xf 0xffe0a000 0 0x1000>;
75 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
76 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
77 pcie@0 {
78 ranges = <0x2000000 0x0 0x80000000
79 0x2000000 0x0 0x80000000
80 0x0 0x20000000
81
82 0x1000000 0x0 0x0
83 0x1000000 0x0 0x0
84 0x0 0x100000>;
85 };
86 };
87};
88
89/include/ "p1020rdb-pc.dtsi"
90/include/ "fsl/p1020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
new file mode 100644
index 000000000000..f411515937ec
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core0.dts
@@ -0,0 +1,64 @@
1/*
2 * P1020 RDB-PC Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
7 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
8 *
9 * Please note to add "-b 0" for core0's dts compiling.
10 *
11 * Copyright 2012 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19/include/ "p1020rdb-pc_32b.dts"
20
21/ {
22 model = "fsl,P1020RDB-PC";
23 compatible = "fsl,P1020RDB-PC";
24
25 aliases {
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 serial0 = &serial0;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 PowerPC,P1020@1 {
35 status = "disabled";
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 };
42
43 localbus@ffe05000 {
44 status = "disabled";
45 };
46
47 soc@ffe00000 {
48 serial1: serial@4600 {
49 status = "disabled";
50 };
51
52 enet0: ethernet@b0000 {
53 status = "disabled";
54 };
55
56 mpic: pic@40000 {
57 protected-sources = <
58 42 29 30 34 /* serial1, enet0-queue-group0 */
59 17 18 24 45 /* enet0-queue-group1, crypto */
60 >;
61 pic-no-reset;
62 };
63 };
64};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
new file mode 100644
index 000000000000..a91335ad82c2
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pc_camp_core1.dts
@@ -0,0 +1,142 @@
1/*
2 * P1020 RDB-PC Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, eth0, crypto.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2012 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/include/ "p1020rdb-pc_32b.dts"
19
20/ {
21 model = "fsl,P1020RDB-PC";
22 compatible = "fsl,P1020RDB-PC";
23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 };
28
29 cpus {
30 PowerPC,P1020@0 {
31 status = "disabled";
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 };
38
39 localbus@ffe05000 {
40 status = "disabled";
41 };
42
43 soc@ffe00000 {
44 ecm-law@0 {
45 status = "disabled";
46 };
47
48 ecm@1000 {
49 status = "disabled";
50 };
51
52 memory-controller@2000 {
53 status = "disabled";
54 };
55
56 i2c@3000 {
57 status = "disabled";
58 };
59
60 i2c@3100 {
61 status = "disabled";
62 };
63
64 serial0: serial@4500 {
65 status = "disabled";
66 };
67
68 spi@7000 {
69 status = "disabled";
70 };
71
72 gpio: gpio-controller@f000 {
73 status = "disabled";
74 };
75
76 dma@21300 {
77 status = "disabled";
78 };
79
80 mdio@24000 {
81 status = "disabled";
82 };
83
84 mdio@25000 {
85 status = "disabled";
86 };
87
88 enet1: ethernet@b1000 {
89 status = "disabled";
90 };
91
92 enet2: ethernet@b2000 {
93 status = "disabled";
94 };
95
96 usb@22000 {
97 status = "disabled";
98 };
99
100 sdhci@2e000 {
101 status = "disabled";
102 };
103
104 mpic: pic@40000 {
105 protected-sources = <
106 16 /* ecm, mem, L2, pci0, pci1 */
107 43 42 59 /* i2c, serial0, spi */
108 47 63 62 /* gpio, tdm */
109 20 21 22 23 /* dma */
110 03 02 /* mdio */
111 35 36 40 /* enet1-queue-group0 */
112 51 52 67 /* enet1-queue-group1 */
113 31 32 33 /* enet2-queue-group0 */
114 25 26 27 /* enet2-queue-group1 */
115 28 72 58 /* usb, sdhci, crypto */
116 0xb0 0xb1 0xb2 /* message */
117 0xb3 0xb4 0xb5
118 0xb6 0xb7
119 0xe0 0xe1 0xe2 /* msi */
120 0xe3 0xe4 0xe5
121 0xe6 0xe7 /* sdhci, crypto , pci */
122 >;
123 pic-no-reset;
124 };
125
126 msi@41600 {
127 status = "disabled";
128 };
129
130 global-utilities@e0000 { //global utilities block
131 status = "disabled";
132 };
133 };
134
135 pci0: pcie@ffe09000 {
136 status = "disabled";
137 };
138
139 pci1: pcie@ffe0a000 {
140 status = "disabled";
141 };
142};
diff --git a/arch/powerpc/boot/dts/p1021rdb.dts b/arch/powerpc/boot/dts/p1021rdb.dts
new file mode 100644
index 000000000000..90b6b4caa273
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb.dts
@@ -0,0 +1,96 @@
1/*
2 * P1021 RDB Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1021RDB";
38 compatible = "fsl,P1021RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000
50 0x2 0x0 0x0 0xffb00000 0x00020000>;
51 };
52
53 soc: soc@ffe00000 {
54 ranges = <0x0 0x0 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@ffe09000 {
58 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
60 reg = <0 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@ffe0a000 {
73 reg = <0 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0x80000000
78 0x2000000 0x0 0x80000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86
87 qe: qe@ffe80000 {
88 ranges = <0x0 0x0 0xffe80000 0x40000>;
89 reg = <0 0xffe80000 0 0x480>;
90 brg-frequency = <0>;
91 bus-frequency = <0>;
92 };
93};
94
95/include/ "p1021rdb.dtsi"
96/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1021rdb.dtsi b/arch/powerpc/boot/dts/p1021rdb.dtsi
new file mode 100644
index 000000000000..b973461ab751
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb.dtsi
@@ -0,0 +1,236 @@
1/*
2 * P1021 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 };
77 };
78
79 nand@1,0 {
80 #address-cells = <1>;
81 #size-cells = <1>;
82 compatible = "fsl,p1021-fcm-nand",
83 "fsl,elbc-fcm-nand";
84 reg = <0x1 0x0 0x40000>;
85
86 partition@0 {
87 /* This location must not be altered */
88 /* 1MB for u-boot Bootloader Image */
89 reg = <0x0 0x00100000>;
90 label = "NAND U-Boot Image";
91 read-only;
92 };
93
94 partition@100000 {
95 /* 1MB for DTB Image */
96 reg = <0x00100000 0x00100000>;
97 label = "NAND DTB Image";
98 };
99
100 partition@200000 {
101 /* 4MB for Linux Kernel Image */
102 reg = <0x00200000 0x00400000>;
103 label = "NAND Linux Kernel Image";
104 };
105
106 partition@600000 {
107 /* 4MB for Compressed Root file System Image */
108 reg = <0x00600000 0x00400000>;
109 label = "NAND Compressed RFS Image";
110 };
111
112 partition@a00000 {
113 /* 7MB for JFFS2 based Root file System */
114 reg = <0x00a00000 0x00700000>;
115 label = "NAND JFFS2 Root File System";
116 };
117
118 partition@1100000 {
119 /* 15MB for User Writable Area */
120 reg = <0x01100000 0x00f00000>;
121 label = "NAND Writable User area";
122 };
123 };
124
125 L2switch@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "vitesse-7385";
129 reg = <0x2 0x0 0x20000>;
130 };
131};
132
133&soc {
134 i2c@3000 {
135 rtc@68 {
136 compatible = "pericom,pt7c4338";
137 reg = <0x68>;
138 };
139 };
140
141 spi@7000 {
142 flash@0 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "spansion,s25sl12801";
146 reg = <0>;
147 spi-max-frequency = <40000000>; /* input clock */
148
149 partition@u-boot {
150 /* 512KB for u-boot Bootloader Image */
151 reg = <0x0 0x00080000>;
152 label = "SPI Flash U-Boot Image";
153 read-only;
154 };
155
156 partition@dtb {
157 /* 512KB for DTB Image */
158 reg = <0x00080000 0x00080000>;
159 label = "SPI Flash DTB Image";
160 };
161
162 partition@kernel {
163 /* 4MB for Linux Kernel Image */
164 reg = <0x00100000 0x00400000>;
165 label = "SPI Flash Linux Kernel Image";
166 };
167
168 partition@fs {
169 /* 4MB for Compressed RFS Image */
170 reg = <0x00500000 0x00400000>;
171 label = "SPI Flash Compressed RFSImage";
172 };
173
174 partition@jffs-fs {
175 /* 7MB for JFFS2 based RFS */
176 reg = <0x00900000 0x00700000>;
177 label = "SPI Flash JFFS2 RFS";
178 };
179 };
180 };
181
182 usb@22000 {
183 phy_type = "ulpi";
184 };
185
186 mdio@24000 {
187 phy0: ethernet-phy@0 {
188 interrupt-parent = <&mpic>;
189 interrupts = <3 1 0 0>;
190 reg = <0x0>;
191 };
192
193 phy1: ethernet-phy@1 {
194 interrupt-parent = <&mpic>;
195 interrupts = <2 1 0 0>;
196 reg = <0x1>;
197 };
198
199 tbi0: tbi-phy@11 {
200 reg = <0x11>;
201 device_type = "tbi-phy";
202 };
203 };
204
205 mdio@25000 {
206 tbi1: tbi-phy@11 {
207 reg = <0x11>;
208 device_type = "tbi-phy";
209 };
210 };
211
212 mdio@26000 {
213 tbi2: tbi-phy@11 {
214 reg = <0x11>;
215 device_type = "tbi-phy";
216 };
217 };
218
219 enet0: ethernet@b0000 {
220 fixed-link = <1 1 1000 0 0>;
221 phy-connection-type = "rgmii-id";
222
223 };
224
225 enet1: ethernet@b1000 {
226 phy-handle = <&phy0>;
227 tbi-handle = <&tbi1>;
228 phy-connection-type = "sgmii";
229 };
230
231 enet2: ethernet@b2000 {
232 phy-handle = <&phy1>;
233 tbi-handle = <&tbi2>;
234 phy-connection-type = "rgmii-id";
235 };
236};
diff --git a/arch/powerpc/boot/dts/p1021rdb_36b.dts b/arch/powerpc/boot/dts/p1021rdb_36b.dts
new file mode 100644
index 000000000000..ea6d8b5fa10b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1021rdb_36b.dts
@@ -0,0 +1,96 @@
1/*
2 * P1021 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1021RDB";
38 compatible = "fsl,P1021RDB-PC";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000
50 0x2 0x0 0xf 0xffb00000 0x00020000>;
51 };
52
53 soc: soc@fffe00000 {
54 ranges = <0x0 0xf 0xffe00000 0x100000>;
55 };
56
57 pci0: pcie@fffe09000 {
58 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 reg = <0xf 0xffe09000 0 0x1000>;
61 pcie@0 {
62 ranges = <0x2000000 0x0 0xa0000000
63 0x2000000 0x0 0xa0000000
64 0x0 0x20000000
65
66 0x1000000 0x0 0x0
67 0x1000000 0x0 0x0
68 0x0 0x100000>;
69 };
70 };
71
72 pci1: pcie@fffe0a000 {
73 reg = <0xf 0xffe0a000 0 0x1000>;
74 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
75 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
76 pcie@0 {
77 ranges = <0x2000000 0x0 0xc0000000
78 0x2000000 0x0 0xc0000000
79 0x0 0x20000000
80
81 0x1000000 0x0 0x0
82 0x1000000 0x0 0x0
83 0x0 0x100000>;
84 };
85 };
86
87 qe: qe@fffe80000 {
88 ranges = <0x0 0xf 0xffe80000 0x40000>;
89 reg = <0xf 0xffe80000 0 0x480>;
90 brg-frequency = <0>;
91 bus-frequency = <0>;
92 };
93};
94
95/include/ "p1021rdb.dtsi"
96/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
deleted file mode 100644
index ef95717db4bc..000000000000
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ /dev/null
@@ -1,274 +0,0 @@
1/*
2 * P1022 DS 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "fsl/p1022si-pre.dtsi"
12/ {
13 model = "fsl,P1022DS";
14 compatible = "fsl,P1022DS";
15
16 memory {
17 device_type = "memory";
18 };
19
20 lbc: localbus@fffe05000 {
21 reg = <0xf 0xffe05000 0 0x1000>;
22 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
23 0x1 0x0 0xf 0xe0000000 0x08000000
24 0x2 0x0 0xf 0xff800000 0x00040000
25 0x3 0x0 0xf 0xffdf0000 0x00008000>;
26
27 /*
28 * This node is used to access the pixis via "indirect" mode,
29 * which is done by writing the pixis register index to chip
30 * select 0 and the value to/from chip select 1. Indirect
31 * mode is the only way to access the pixis when DIU video
32 * is enabled. Note that this assumes that the first column
33 * of the 'ranges' property above is the chip select number.
34 */
35 board-control@0,0 {
36 compatible = "fsl,p1022ds-indirect-pixis";
37 reg = <0x0 0x0 1 /* CS0 */
38 0x1 0x0 1>; /* CS1 */
39 };
40
41 nor@0,0 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 compatible = "cfi-flash";
45 reg = <0x0 0x0 0x8000000>;
46 bank-width = <2>;
47 device-width = <1>;
48
49 partition@0 {
50 reg = <0x0 0x03000000>;
51 label = "ramdisk-nor";
52 read-only;
53 };
54
55 partition@3000000 {
56 reg = <0x03000000 0x00e00000>;
57 label = "diagnostic-nor";
58 read-only;
59 };
60
61 partition@3e00000 {
62 reg = <0x03e00000 0x00200000>;
63 label = "dink-nor";
64 read-only;
65 };
66
67 partition@4000000 {
68 reg = <0x04000000 0x00400000>;
69 label = "kernel-nor";
70 read-only;
71 };
72
73 partition@4400000 {
74 reg = <0x04400000 0x03b00000>;
75 label = "jffs2-nor";
76 };
77
78 partition@7f00000 {
79 reg = <0x07f00000 0x00080000>;
80 label = "dtb-nor";
81 read-only;
82 };
83
84 partition@7f80000 {
85 reg = <0x07f80000 0x00080000>;
86 label = "u-boot-nor";
87 read-only;
88 };
89 };
90
91 nand@2,0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "fsl,elbc-fcm-nand";
95 reg = <0x2 0x0 0x40000>;
96
97 partition@0 {
98 reg = <0x0 0x02000000>;
99 label = "u-boot-nand";
100 read-only;
101 };
102
103 partition@2000000 {
104 reg = <0x02000000 0x10000000>;
105 label = "jffs2-nand";
106 };
107
108 partition@12000000 {
109 reg = <0x12000000 0x10000000>;
110 label = "ramdisk-nand";
111 read-only;
112 };
113
114 partition@22000000 {
115 reg = <0x22000000 0x04000000>;
116 label = "kernel-nand";
117 };
118
119 partition@26000000 {
120 reg = <0x26000000 0x01000000>;
121 label = "dtb-nand";
122 read-only;
123 };
124
125 partition@27000000 {
126 reg = <0x27000000 0x19000000>;
127 label = "reserved-nand";
128 };
129 };
130
131 board-control@3,0 {
132 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
133 reg = <3 0 0x30>;
134 interrupt-parent = <&mpic>;
135 /*
136 * IRQ8 is generated if the "EVENT" switch is pressed
137 * and PX_CTL[EVESEL] is set to 00.
138 */
139 interrupts = <8 8 0 0>;
140 };
141 };
142
143 soc: soc@fffe00000 {
144 ranges = <0x0 0xf 0xffe00000 0x100000>;
145
146 i2c@3100 {
147 wm8776:codec@1a {
148 compatible = "wlf,wm8776";
149 reg = <0x1a>;
150 /*
151 * clock-frequency will be set by U-Boot if
152 * the clock is enabled.
153 */
154 };
155 };
156
157 spi@7000 {
158 flash@0 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "spansion,s25sl12801";
162 reg = <0>;
163 spi-max-frequency = <40000000>; /* input clock */
164
165 partition@0 {
166 label = "u-boot-spi";
167 reg = <0x00000000 0x00100000>;
168 read-only;
169 };
170 partition@100000 {
171 label = "kernel-spi";
172 reg = <0x00100000 0x00500000>;
173 read-only;
174 };
175 partition@600000 {
176 label = "dtb-spi";
177 reg = <0x00600000 0x00100000>;
178 read-only;
179 };
180 partition@700000 {
181 label = "file system-spi";
182 reg = <0x00700000 0x00900000>;
183 };
184 };
185 };
186
187 ssi@15000 {
188 fsl,mode = "i2s-slave";
189 codec-handle = <&wm8776>;
190 fsl,ssi-asynchronous;
191 };
192
193 usb@22000 {
194 phy_type = "ulpi";
195 };
196
197 usb@23000 {
198 status = "disabled";
199 };
200
201 mdio@24000 {
202 phy0: ethernet-phy@0 {
203 interrupts = <3 1 0 0>;
204 reg = <0x1>;
205 };
206 phy1: ethernet-phy@1 {
207 interrupts = <9 1 0 0>;
208 reg = <0x2>;
209 };
210 tbi-phy@2 {
211 device_type = "tbi-phy";
212 reg = <0x2>;
213 };
214 };
215
216 ethernet@b0000 {
217 phy-handle = <&phy0>;
218 phy-connection-type = "rgmii-id";
219 };
220
221 ethernet@b1000 {
222 phy-handle = <&phy1>;
223 phy-connection-type = "rgmii-id";
224 };
225 };
226
227 pci0: pcie@fffe09000 {
228 reg = <0xf 0xffe09000 0 0x1000>;
229 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
230 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
231 pcie@0 {
232 ranges = <0x2000000 0x0 0xe0000000
233 0x2000000 0x0 0xe0000000
234 0x0 0x20000000
235
236 0x1000000 0x0 0x0
237 0x1000000 0x0 0x0
238 0x0 0x100000>;
239 };
240 };
241
242 pci1: pcie@fffe0a000 {
243 reg = <0xf 0xffe0a000 0 0x1000>;
244 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
245 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
246 pcie@0 {
247 reg = <0x0 0x0 0x0 0x0 0x0>;
248 ranges = <0x2000000 0x0 0xe0000000
249 0x2000000 0x0 0xe0000000
250 0x0 0x20000000
251
252 0x1000000 0x0 0x0
253 0x1000000 0x0 0x0
254 0x0 0x100000>;
255 };
256 };
257
258 pci2: pcie@fffe0b000 {
259 reg = <0xf 0xffe0b000 0 0x1000>;
260 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
261 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
262 pcie@0 {
263 ranges = <0x2000000 0x0 0xe0000000
264 0x2000000 0x0 0xe0000000
265 0x0 0x20000000
266
267 0x1000000 0x0 0x0
268 0x1000000 0x0 0x0
269 0x0 0x100000>;
270 };
271 };
272};
273
274/include/ "fsl/p1022si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds.dtsi b/arch/powerpc/boot/dts/p1022ds.dtsi
new file mode 100644
index 000000000000..7cdb505036bb
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds.dtsi
@@ -0,0 +1,234 @@
1/*
2 * P1022 DS Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&board_lbc {
36 /*
37 * This node is used to access the pixis via "indirect" mode,
38 * which is done by writing the pixis register index to chip
39 * select 0 and the value to/from chip select 1. Indirect
40 * mode is the only way to access the pixis when DIU video
41 * is enabled. Note that this assumes that the first column
42 * of the 'ranges' property above is the chip select number.
43 */
44 board-control@0,0 {
45 compatible = "fsl,p1022ds-indirect-pixis";
46 reg = <0x0 0x0 1 /* CS0 */
47 0x1 0x0 1>; /* CS1 */
48 interrupt-parent = <&mpic>;
49 interrupts = <8 0 0 0>;
50 };
51
52 nor@0,0 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "cfi-flash";
56 reg = <0x0 0x0 0x8000000>;
57 bank-width = <2>;
58 device-width = <1>;
59
60 partition@0 {
61 reg = <0x0 0x03000000>;
62 label = "ramdisk-nor";
63 read-only;
64 };
65
66 partition@3000000 {
67 reg = <0x03000000 0x00e00000>;
68 label = "diagnostic-nor";
69 read-only;
70 };
71
72 partition@3e00000 {
73 reg = <0x03e00000 0x00200000>;
74 label = "dink-nor";
75 read-only;
76 };
77
78 partition@4000000 {
79 reg = <0x04000000 0x00400000>;
80 label = "kernel-nor";
81 read-only;
82 };
83
84 partition@4400000 {
85 reg = <0x04400000 0x03b00000>;
86 label = "jffs2-nor";
87 };
88
89 partition@7f00000 {
90 reg = <0x07f00000 0x00080000>;
91 label = "dtb-nor";
92 read-only;
93 };
94
95 partition@7f80000 {
96 reg = <0x07f80000 0x00080000>;
97 label = "u-boot-nor";
98 read-only;
99 };
100 };
101
102 nand@2,0 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "fsl,elbc-fcm-nand";
106 reg = <0x2 0x0 0x40000>;
107
108 partition@0 {
109 reg = <0x0 0x02000000>;
110 label = "u-boot-nand";
111 read-only;
112 };
113
114 partition@2000000 {
115 reg = <0x02000000 0x10000000>;
116 label = "jffs2-nand";
117 };
118
119 partition@12000000 {
120 reg = <0x12000000 0x10000000>;
121 label = "ramdisk-nand";
122 read-only;
123 };
124
125 partition@22000000 {
126 reg = <0x22000000 0x04000000>;
127 label = "kernel-nand";
128 };
129
130 partition@26000000 {
131 reg = <0x26000000 0x01000000>;
132 label = "dtb-nand";
133 read-only;
134 };
135
136 partition@27000000 {
137 reg = <0x27000000 0x19000000>;
138 label = "reserved-nand";
139 };
140 };
141
142 board-control@3,0 {
143 compatible = "fsl,p1022ds-fpga", "fsl,fpga-ngpixis";
144 reg = <3 0 0x30>;
145 interrupt-parent = <&mpic>;
146 /*
147 * IRQ8 is generated if the "EVENT" switch is pressed
148 * and PX_CTL[EVESEL] is set to 00.
149 */
150 interrupts = <8 0 0 0>;
151 };
152};
153
154&board_soc {
155 i2c@3100 {
156 wm8776:codec@1a {
157 compatible = "wlf,wm8776";
158 reg = <0x1a>;
159 /*
160 * clock-frequency will be set by U-Boot if
161 * the clock is enabled.
162 */
163 };
164 };
165
166 spi@7000 {
167 flash@0 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "spansion,s25sl12801";
171 reg = <0>;
172 spi-max-frequency = <40000000>; /* input clock */
173
174 partition@0 {
175 label = "u-boot-spi";
176 reg = <0x00000000 0x00100000>;
177 read-only;
178 };
179 partition@100000 {
180 label = "kernel-spi";
181 reg = <0x00100000 0x00500000>;
182 read-only;
183 };
184 partition@600000 {
185 label = "dtb-spi";
186 reg = <0x00600000 0x00100000>;
187 read-only;
188 };
189 partition@700000 {
190 label = "file system-spi";
191 reg = <0x00700000 0x00900000>;
192 };
193 };
194 };
195
196 ssi@15000 {
197 fsl,mode = "i2s-slave";
198 codec-handle = <&wm8776>;
199 fsl,ssi-asynchronous;
200 };
201
202 usb@22000 {
203 phy_type = "ulpi";
204 };
205
206 usb@23000 {
207 status = "disabled";
208 };
209
210 mdio@24000 {
211 phy0: ethernet-phy@0 {
212 interrupts = <3 1 0 0>;
213 reg = <0x1>;
214 };
215 phy1: ethernet-phy@1 {
216 interrupts = <9 1 0 0>;
217 reg = <0x2>;
218 };
219 tbi-phy@2 {
220 device_type = "tbi-phy";
221 reg = <0x2>;
222 };
223 };
224
225 ethernet@b0000 {
226 phy-handle = <&phy0>;
227 phy-connection-type = "rgmii-id";
228 };
229
230 ethernet@b1000 {
231 phy-handle = <&phy1>;
232 phy-connection-type = "rgmii-id";
233 };
234};
diff --git a/arch/powerpc/boot/dts/p1022ds_32b.dts b/arch/powerpc/boot/dts/p1022ds_32b.dts
new file mode 100644
index 000000000000..d96cae00a9e3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_32b.dts
@@ -0,0 +1,103 @@
1/*
2 * P1022 DS 32-bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1022si-pre.dtsi"
36/ {
37 model = "fsl,P1022DS";
38 compatible = "fsl,P1022DS";
39
40 memory {
41 device_type = "memory";
42 };
43
44 board_lbc: lbc: localbus@ffe05000 {
45 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
46 0x1 0x0 0x0 0xe0000000 0x08000000
47 0x2 0x0 0x0 0xff800000 0x00040000
48 0x3 0x0 0x0 0xffdf0000 0x00008000>;
49 reg = <0x0 0xffe05000 0 0x1000>;
50 };
51
52 board_soc: soc: soc@ffe00000 {
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@ffe09000 {
57 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0x0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@ffe0a000 {
72 ranges = <0x2000000 0x0 0xe0000000 0 0xc0000000 0x0 0x20000000
73 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
74 reg = <0 0xffe0a000 0 0x1000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 pci2: pcie@ffe0b000 {
87 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
88 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
89 reg = <0 0xffe0b000 0 0x1000>;
90 pcie@0 {
91 ranges = <0x2000000 0x0 0xe0000000
92 0x2000000 0x0 0xe0000000
93 0x0 0x20000000
94
95 0x1000000 0x0 0x0
96 0x1000000 0x0 0x0
97 0x0 0x100000>;
98 };
99 };
100};
101
102/include/ "fsl/p1022si-post.dtsi"
103/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1022ds_36b.dts b/arch/powerpc/boot/dts/p1022ds_36b.dts
new file mode 100644
index 000000000000..f7aacce40bf6
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1022ds_36b.dts
@@ -0,0 +1,103 @@
1/*
2 * P1022 DS 36-bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1022si-pre.dtsi"
36/ {
37 model = "fsl,P1022DS";
38 compatible = "fsl,P1022DS";
39
40 memory {
41 device_type = "memory";
42 };
43
44 board_lbc: lbc: localbus@fffe05000 {
45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
46 0x1 0x0 0xf 0xe0000000 0x08000000
47 0x2 0x0 0xf 0xff800000 0x00040000
48 0x3 0x0 0xf 0xffdf0000 0x00008000>;
49 reg = <0xf 0xffe05000 0 0x1000>;
50 };
51
52 board_soc: soc: soc@fffe00000 {
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@fffe09000 {
57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@fffe0a000 {
72 ranges = <0x2000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000
73 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
74 reg = <0xf 0xffe0a000 0 0x1000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 pci2: pcie@fffe0b000 {
87 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
88 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
89 reg = <0xf 0xffe0b000 0 0x1000>;
90 pcie@0 {
91 ranges = <0x2000000 0x0 0xe0000000
92 0x2000000 0x0 0xe0000000
93 0x0 0x20000000
94
95 0x1000000 0x0 0x0
96 0x1000000 0x0 0x0
97 0x0 0x100000>;
98 };
99 };
100};
101
102/include/ "fsl/p1022si-post.dtsi"
103/include/ "p1022ds.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb.dtsi b/arch/powerpc/boot/dts/p1025rdb.dtsi
new file mode 100644
index 000000000000..cf3676fc714b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb.dtsi
@@ -0,0 +1,286 @@
1/*
2 * P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p1025-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 7MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00700000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1100000 {
120 /* 15MB for JFFS2 based Root file System */
121 reg = <0x01100000 0x00f00000>;
122 label = "NAND Writable User area";
123 };
124 };
125
126};
127
128&soc {
129 i2c@3000 {
130 rtc@68 {
131 compatible = "dallas,ds1339";
132 reg = <0x68>;
133 };
134 };
135
136 spi@7000 {
137 flash@0 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "spansion,s25sl12801";
141 reg = <0>;
142 spi-max-frequency = <40000000>; /* input clock */
143
144 partition@u-boot {
145 /* 512KB for u-boot Bootloader Image */
146 reg = <0x0 0x00080000>;
147 label = "u-boot";
148 read-only;
149 };
150
151 partition@dtb {
152 /* 512KB for DTB Image */
153 reg = <0x00080000 0x00080000>;
154 label = "dtb";
155 };
156
157 partition@kernel {
158 /* 4MB for Linux Kernel Image */
159 reg = <0x00100000 0x00400000>;
160 label = "kernel";
161 };
162
163 partition@fs {
164 /* 4MB for Compressed RFS Image */
165 reg = <0x00500000 0x00400000>;
166 label = "file system";
167 };
168
169 partition@jffs-fs {
170 /* 7MB for JFFS2 based RFS */
171 reg = <0x00900000 0x00700000>;
172 label = "file system jffs2";
173 };
174 };
175 };
176
177 usb@22000 {
178 phy_type = "ulpi";
179 };
180
181 /* USB2 is shared with localbus, so it must be disabled
182 by default. We can't put 'status = "disabled";' here
183 since U-Boot doesn't clear the status property when
184 it enables USB2. OTOH, U-Boot does create a new node
185 when there isn't any. So, just comment it out.
186 usb@23000 {
187 phy_type = "ulpi";
188 };
189 */
190
191 mdio@24000 {
192 phy0: ethernet-phy@0 {
193 interrupt-parent = <&mpic>;
194 interrupts = <3 1>;
195 reg = <0x0>;
196 };
197
198 phy1: ethernet-phy@1 {
199 interrupt-parent = <&mpic>;
200 interrupts = <2 1>;
201 reg = <0x1>;
202 };
203
204 tbi0: tbi-phy@11 {
205 reg = <0x11>;
206 device_type = "tbi-phy";
207 };
208 };
209
210 mdio@25000 {
211 tbi1: tbi-phy@11 {
212 reg = <0x11>;
213 device_type = "tbi-phy";
214 };
215 };
216
217 mdio@26000 {
218 tbi2: tbi-phy@11 {
219 reg = <0x11>;
220 device_type = "tbi-phy";
221 };
222 };
223
224 enet0: ethernet@b0000 {
225 fixed-link = <1 1 1000 0 0>;
226 phy-connection-type = "rgmii-id";
227
228 };
229
230 enet1: ethernet@b1000 {
231 phy-handle = <&phy0>;
232 tbi-handle = <&tbi1>;
233 phy-connection-type = "sgmii";
234 };
235
236 enet2: ethernet@b2000 {
237 phy-handle = <&phy1>;
238 phy-connection-type = "rgmii-id";
239 };
240
241 par_io@e0100 {
242 #address-cells = <1>;
243 #size-cells = <1>;
244 reg = <0xe0100 0x60>;
245 ranges = <0x0 0xe0100 0x60>;
246 device_type = "par_io";
247 num-ports = <3>;
248 pio1: ucc_pin@01 {
249 pio-map = <
250 /* port pin dir open_drain assignment has_irq */
251 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
252 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
253 0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
254 0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
255 0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
256 0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
257 0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
258 0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
259 0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
260 0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
261 0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
262 0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
263 0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
264 0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
265 0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
266 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
267 0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
268 0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
269 };
270
271 pio2: ucc_pin@02 {
272 pio-map = <
273 /* port pin dir open_drain assignment has_irq */
274 0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
275 0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
276 0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
277 0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
278 0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
279 0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
280 0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
281 0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
282 0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
283 0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
284 };
285 };
286};
diff --git a/arch/powerpc/boot/dts/p1025rdb_32b.dts b/arch/powerpc/boot/dts/p1025rdb_32b.dts
new file mode 100644
index 000000000000..ac5729c14eda
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb_32b.dts
@@ -0,0 +1,135 @@
1/*
2 * P1025 RDB Device Tree Source (32-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1025RDB";
38 compatible = "fsl,P1025RDB";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@ffe05000 {
45 reg = <0 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes */
48 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
49 0x1 0x0 0x0 0xff800000 0x00040000>;
50 };
51
52 soc: soc@ffe00000 {
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@ffe09000 {
57 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0 0xffe09000 0 0x1000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@ffe0a000 {
72 reg = <0 0xffe0a000 0 0x1000>;
73 ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
74 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85
86 qe: qe@ffe80000 {
87 ranges = <0x0 0x0 0xffe80000 0x40000>;
88 reg = <0 0xffe80000 0 0x480>;
89 brg-frequency = <0>;
90 bus-frequency = <0>;
91 status = "disabled"; /* no firmware loaded */
92
93 enet3: ucc@2000 {
94 device_type = "network";
95 compatible = "ucc_geth";
96 rx-clock-name = "clk12";
97 tx-clock-name = "clk9";
98 pio-handle = <&pio1>;
99 phy-handle = <&qe_phy0>;
100 phy-connection-type = "mii";
101 };
102
103 mdio@2120 {
104 qe_phy0: ethernet-phy@0 {
105 interrupt-parent = <&mpic>;
106 interrupts = <4 1 0 0>;
107 reg = <0x6>;
108 device_type = "ethernet-phy";
109 };
110 qe_phy1: ethernet-phy@03 {
111 interrupt-parent = <&mpic>;
112 interrupts = <5 1 0 0>;
113 reg = <0x3>;
114 device_type = "ethernet-phy";
115 };
116 tbi-phy@11 {
117 reg = <0x11>;
118 device_type = "tbi-phy";
119 };
120 };
121
122 enet4: ucc@2400 {
123 device_type = "network";
124 compatible = "ucc_geth";
125 rx-clock-name = "none";
126 tx-clock-name = "clk13";
127 pio-handle = <&pio2>;
128 phy-handle = <&qe_phy1>;
129 phy-connection-type = "rmii";
130 };
131 };
132};
133
134/include/ "p1025rdb.dtsi"
135/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts b/arch/powerpc/boot/dts/p1025rdb_36b.dts
new file mode 100644
index 000000000000..4ce4bfa0eda4
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -0,0 +1,88 @@
1/*
2 * P1025 RDB Device Tree Source (36-bit address map)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p1021si-pre.dtsi"
36/ {
37 model = "fsl,P1025RDB";
38 compatible = "fsl,P1025RDB";
39
40 memory {
41 device_type = "memory";
42 };
43
44 lbc: localbus@fffe05000 {
45 reg = <0xf 0xffe05000 0 0x1000>;
46
47 /* NOR, NAND Flashes */
48 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
49 0x1 0x0 0xf 0xff800000 0x00040000>;
50 };
51
52 soc: soc@fffe00000 {
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
54 };
55
56 pci0: pcie@fffe09000 {
57 reg = <0xf 0xffe09000 0 0x1000>;
58 ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000
59 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
60 pcie@0 {
61 ranges = <0x2000000 0x0 0xe0000000
62 0x2000000 0x0 0xe0000000
63 0x0 0x20000000
64
65 0x1000000 0x0 0x0
66 0x1000000 0x0 0x0
67 0x0 0x100000>;
68 };
69 };
70
71 pci1: pcie@fffe0a000 {
72 reg = <0xf 0xffe0a000 0 0x1000>;
73 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
74 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
75 pcie@0 {
76 ranges = <0x2000000 0x0 0xe0000000
77 0x2000000 0x0 0xe0000000
78 0x0 0x20000000
79
80 0x1000000 0x0 0x0
81 0x1000000 0x0 0x0
82 0x0 0x100000>;
83 };
84 };
85};
86
87/include/ "p1025rdb.dtsi"
88/include/ "fsl/p1021si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc.dtsi b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
new file mode 100644
index 000000000000..c21d1c7d16cd
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc.dtsi
@@ -0,0 +1,241 @@
1/*
2 * P2020 RDB-PC Device Tree Source stub (no addresses or top-level ranges)
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&lbc {
36 nor@0,0 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "cfi-flash";
40 reg = <0x0 0x0 0x1000000>;
41 bank-width = <2>;
42 device-width = <1>;
43
44 partition@0 {
45 /* This location must not be altered */
46 /* 256KB for Vitesse 7385 Switch firmware */
47 reg = <0x0 0x00040000>;
48 label = "NOR Vitesse-7385 Firmware";
49 read-only;
50 };
51
52 partition@40000 {
53 /* 256KB for DTB Image */
54 reg = <0x00040000 0x00040000>;
55 label = "NOR DTB Image";
56 };
57
58 partition@80000 {
59 /* 3.5 MB for Linux Kernel Image */
60 reg = <0x00080000 0x00380000>;
61 label = "NOR Linux Kernel Image";
62 };
63
64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>;
67 label = "NOR JFFS2 Root File System";
68 };
69
70 partition@f00000 {
71 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */
73 /* 512KB for u-boot Environment Variables */
74 reg = <0x00f00000 0x00100000>;
75 label = "NOR U-Boot Image";
76 read-only;
77 };
78 };
79
80 nand@1,0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "fsl,p2020-fcm-nand",
84 "fsl,elbc-fcm-nand";
85 reg = <0x1 0x0 0x40000>;
86
87 partition@0 {
88 /* This location must not be altered */
89 /* 1MB for u-boot Bootloader Image */
90 reg = <0x0 0x00100000>;
91 label = "NAND U-Boot Image";
92 read-only;
93 };
94
95 partition@100000 {
96 /* 1MB for DTB Image */
97 reg = <0x00100000 0x00100000>;
98 label = "NAND DTB Image";
99 };
100
101 partition@200000 {
102 /* 4MB for Linux Kernel Image */
103 reg = <0x00200000 0x00400000>;
104 label = "NAND Linux Kernel Image";
105 };
106
107 partition@600000 {
108 /* 4MB for Compressed Root file System Image */
109 reg = <0x00600000 0x00400000>;
110 label = "NAND Compressed RFS Image";
111 };
112
113 partition@a00000 {
114 /* 7MB for JFFS2 based Root file System */
115 reg = <0x00a00000 0x00700000>;
116 label = "NAND JFFS2 Root File System";
117 };
118
119 partition@1100000 {
120 /* 15MB for JFFS2 based Root file System */
121 reg = <0x01100000 0x00f00000>;
122 label = "NAND Writable User area";
123 };
124 };
125
126 L2switch@2,0 {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "vitesse-7385";
130 reg = <0x2 0x0 0x20000>;
131 };
132
133 cpld@3,0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "cpld";
137 reg = <0x3 0x0 0x20000>;
138 read-only;
139 };
140};
141
142&soc {
143 i2c@3000 {
144 rtc@68 {
145 compatible = "pericom,pt7c4338";
146 reg = <0x68>;
147 };
148 };
149
150 spi@7000 {
151 flash@0 {
152 #address-cells = <1>;
153 #size-cells = <1>;
154 compatible = "spansion,m25p80";
155 reg = <0>;
156 spi-max-frequency = <40000000>;
157
158 partition@0 {
159 /* 512KB for u-boot Bootloader Image */
160 reg = <0x0 0x00080000>;
161 label = "SPI U-Boot Image";
162 read-only;
163 };
164
165 partition@80000 {
166 /* 512KB for DTB Image */
167 reg = <0x00080000 0x00080000>;
168 label = "SPI DTB Image";
169 };
170
171 partition@100000 {
172 /* 4MB for Linux Kernel Image */
173 reg = <0x00100000 0x00400000>;
174 label = "SPI Linux Kernel Image";
175 };
176
177 partition@500000 {
178 /* 4MB for Compressed RFS Image */
179 reg = <0x00500000 0x00400000>;
180 label = "SPI Compressed RFS Image";
181 };
182
183 partition@900000 {
184 /* 7MB for JFFS2 based RFS */
185 reg = <0x00900000 0x00700000>;
186 label = "SPI JFFS2 RFS";
187 };
188 };
189 };
190
191 usb@22000 {
192 phy_type = "ulpi";
193 };
194
195 mdio@24520 {
196 phy0: ethernet-phy@0 {
197 interrupts = <3 1 0 0>;
198 reg = <0x0>;
199 };
200 phy1: ethernet-phy@1 {
201 interrupts = <2 1 0 0>;
202 reg = <0x1>;
203 };
204 };
205
206 mdio@25520 {
207 tbi0: tbi-phy@11 {
208 reg = <0x11>;
209 device_type = "tbi-phy";
210 };
211 };
212
213 mdio@26520 {
214 status = "disabled";
215 };
216
217 ptp_clock@24e00 {
218 fsl,tclk-period = <5>;
219 fsl,tmr-prsc = <200>;
220 fsl,tmr-add = <0xCCCCCCCD>;
221 fsl,tmr-fiper1 = <0x3B9AC9FB>;
222 fsl,tmr-fiper2 = <0x0001869B>;
223 fsl,max-adj = <249999999>;
224 };
225
226 enet0: ethernet@24000 {
227 fixed-link = <1 1 1000 0 0>;
228 phy-connection-type = "rgmii-id";
229 };
230
231 enet1: ethernet@25000 {
232 tbi-handle = <&tbi0>;
233 phy-handle = <&phy0>;
234 phy-connection-type = "sgmii";
235 };
236
237 enet2: ethernet@26000 {
238 phy-handle = <&phy1>;
239 phy-connection-type = "rgmii-id";
240 };
241};
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
new file mode 100644
index 000000000000..852e5b27485d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_32b.dts
@@ -0,0 +1,96 @@
1/*
2 * P2020 RDB-PC 32Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p2020si-pre.dtsi"
36
37/ {
38 model = "fsl,P2020RDB";
39 compatible = "fsl,P2020RDB-PC";
40
41 memory {
42 device_type = "memory";
43 };
44
45 lbc: localbus@ffe05000 {
46 reg = <0 0xffe05000 0 0x1000>;
47
48 /* NOR and NAND Flashes */
49 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
50 0x1 0x0 0x0 0xff800000 0x00040000
51 0x2 0x0 0x0 0xffb00000 0x00020000
52 0x3 0x0 0x0 0xffa00000 0x00020000>;
53 };
54
55 soc: soc@ffe00000 {
56 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 };
58
59 pci0: pcie@ffe08000 {
60 reg = <0 0xffe08000 0 0x1000>;
61 status = "disabled";
62 };
63
64 pci1: pcie@ffe09000 {
65 reg = <0 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
68 pcie@0 {
69 ranges = <0x2000000 0x0 0xe0000000
70 0x2000000 0x0 0xe0000000
71 0x0 0x20000000
72
73 0x1000000 0x0 0x0
74 0x1000000 0x0 0x0
75 0x0 0x100000>;
76 };
77 };
78
79 pci2: pcie@ffe0a000 {
80 reg = <0 0xffe0a000 0 0x1000>;
81 ranges = <0x2000000 0x0 0xe0000000 0 0x80000000 0x0 0x20000000
82 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
83 pcie@0 {
84 ranges = <0x2000000 0x0 0xe0000000
85 0x2000000 0x0 0xe0000000
86 0x0 0x20000000
87
88 0x1000000 0x0 0x0
89 0x1000000 0x0 0x0
90 0x0 0x100000>;
91 };
92 };
93};
94
95/include/ "p2020rdb-pc.dtsi"
96/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
new file mode 100644
index 000000000000..b5a56ca51cf7
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020rdb-pc_36b.dts
@@ -0,0 +1,96 @@
1/*
2 * P2020 RDB-PC 36Bit Physical Address Map Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/p2020si-pre.dtsi"
36
37/ {
38 model = "fsl,P2020RDB";
39 compatible = "fsl,P2020RDB-PC";
40
41 memory {
42 device_type = "memory";
43 };
44
45 lbc: localbus@fffe05000 {
46 reg = <0xf 0xffe05000 0 0x1000>;
47
48 /* NOR and NAND Flashes */
49 ranges = <0x0 0x0 0xf 0xef000000 0x01000000
50 0x1 0x0 0xf 0xff800000 0x00040000
51 0x2 0x0 0xf 0xffb00000 0x00020000
52 0x3 0x0 0xf 0xffa00000 0x00020000>;
53 };
54
55 soc: soc@fffe00000 {
56 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 };
58
59 pci0: pcie@fffe08000 {
60 reg = <0xf 0xffe08000 0 0x1000>;
61 status = "disabled";
62 };
63
64 pci1: pcie@fffe09000 {
65 reg = <0xf 0xffe09000 0 0x1000>;
66 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
67 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
68 pcie@0 {
69 ranges = <0x2000000 0x0 0xe0000000
70 0x2000000 0x0 0xe0000000
71 0x0 0x20000000
72
73 0x1000000 0x0 0x0
74 0x1000000 0x0 0x0
75 0x0 0x100000>;
76 };
77 };
78
79 pci2: pcie@fffe0a000 {
80 reg = <0xf 0xffe0a000 0 0x1000>;
81 ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
82 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
83 pcie@0 {
84 ranges = <0x2000000 0x0 0xe0000000
85 0x2000000 0x0 0xe0000000
86 0x0 0x20000000
87
88 0x1000000 0x0 0x0
89 0x1000000 0x0 0x0
90 0x0 0x100000>;
91 };
92 };
93};
94
95/include/ "p2020rdb-pc.dtsi"
96/include/ "fsl/p2020si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index eb8a6aa2bda5..153bc76bb48e 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -34,7 +34,7 @@
34 34
35 /* NOR and NAND Flashes */ 35 /* NOR and NAND Flashes */
36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 36 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
37 0x1 0x0 0x0 0xffa00000 0x00040000 37 0x1 0x0 0x0 0xff800000 0x00040000
38 0x2 0x0 0x0 0xffb00000 0x00020000>; 38 0x2 0x0 0x0 0xffb00000 0x00020000>;
39 39
40 nor@0,0 { 40 nor@0,0 {
@@ -157,7 +157,7 @@
157 #size-cells = <1>; 157 #size-cells = <1>;
158 compatible = "spansion,s25sl12801"; 158 compatible = "spansion,s25sl12801";
159 reg = <0>; 159 reg = <0>;
160 spi-max-frequency = <50000000>; 160 spi-max-frequency = <40000000>;
161 161
162 partition@0 { 162 partition@0 {
163 /* 512KB for u-boot Bootloader Image */ 163 /* 512KB for u-boot Bootloader Image */
diff --git a/arch/powerpc/configs/85xx/ge_imp3a_defconfig b/arch/powerpc/configs/85xx/ge_imp3a_defconfig
new file mode 100644
index 000000000000..f8c51a4ab995
--- /dev/null
+++ b/arch/powerpc/configs/85xx/ge_imp3a_defconfig
@@ -0,0 +1,257 @@
1CONFIG_PPC_85xx=y
2CONFIG_SMP=y
3CONFIG_NR_CPUS=2
4CONFIG_EXPERIMENTAL=y
5CONFIG_SYSVIPC=y
6CONFIG_POSIX_MQUEUE=y
7CONFIG_BSD_PROCESS_ACCT=y
8CONFIG_BSD_PROCESS_ACCT_V3=y
9CONFIG_SPARSE_IRQ=y
10CONFIG_IKCONFIG=y
11CONFIG_IKCONFIG_PROC=y
12# CONFIG_UTS_NS is not set
13# CONFIG_IPC_NS is not set
14# CONFIG_USER_NS is not set
15# CONFIG_PID_NS is not set
16# CONFIG_NET_NS is not set
17CONFIG_SYSFS_DEPRECATED=y
18CONFIG_SYSFS_DEPRECATED_V2=y
19CONFIG_RELAY=y
20CONFIG_BLK_DEV_INITRD=y
21CONFIG_PERF_EVENTS=y
22CONFIG_SLAB=y
23CONFIG_MODULES=y
24CONFIG_MODULE_UNLOAD=y
25# CONFIG_BLK_DEV_BSG is not set
26CONFIG_GE_IMP3A=y
27CONFIG_QUICC_ENGINE=y
28CONFIG_QE_GPIO=y
29CONFIG_CPM2=y
30CONFIG_HIGHMEM=y
31CONFIG_HIGH_RES_TIMERS=y
32CONFIG_HZ_1000=y
33CONFIG_PREEMPT=y
34# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
35CONFIG_BINFMT_MISC=m
36CONFIG_MATH_EMULATION=y
37CONFIG_IRQ_ALL_CPUS=y
38CONFIG_FORCE_MAX_ZONEORDER=17
39CONFIG_PCI=y
40CONFIG_PCIEPORTBUS=y
41CONFIG_PCI_MSI=y
42CONFIG_PCCARD=y
43# CONFIG_PCMCIA_LOAD_CIS is not set
44CONFIG_YENTA=y
45CONFIG_NET=y
46CONFIG_PACKET=y
47CONFIG_UNIX=y
48CONFIG_XFRM_USER=m
49CONFIG_NET_KEY=y
50CONFIG_INET=y
51CONFIG_IP_MULTICAST=y
52CONFIG_IP_ADVANCED_ROUTER=y
53CONFIG_IP_MULTIPLE_TABLES=y
54CONFIG_IP_ROUTE_MULTIPATH=y
55CONFIG_IP_ROUTE_VERBOSE=y
56CONFIG_IP_PNP=y
57CONFIG_IP_PNP_DHCP=y
58CONFIG_IP_PNP_BOOTP=y
59CONFIG_IP_PNP_RARP=y
60CONFIG_NET_IPIP=m
61CONFIG_IP_MROUTE=y
62CONFIG_IP_PIMSM_V1=y
63CONFIG_IP_PIMSM_V2=y
64CONFIG_SYN_COOKIES=y
65CONFIG_INET_AH=m
66CONFIG_INET_ESP=m
67CONFIG_INET_IPCOMP=m
68# CONFIG_INET_XFRM_MODE_BEET is not set
69CONFIG_INET6_AH=m
70CONFIG_INET6_IPCOMP=m
71CONFIG_IPV6_TUNNEL=m
72CONFIG_NET_PKTGEN=m
73CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
74CONFIG_MTD=y
75CONFIG_MTD_OF_PARTS=y
76CONFIG_MTD_CHAR=y
77CONFIG_MTD_BLOCK=y
78CONFIG_MTD_CFI=y
79CONFIG_MTD_JEDECPROBE=y
80CONFIG_MTD_CFI_INTELEXT=y
81CONFIG_MTD_CFI_AMDSTD=y
82CONFIG_MTD_PHYSMAP_OF=y
83CONFIG_MTD_NAND=y
84CONFIG_MTD_NAND_FSL_ELBC=y
85CONFIG_PROC_DEVICETREE=y
86CONFIG_BLK_DEV_LOOP=m
87CONFIG_BLK_DEV_CRYPTOLOOP=m
88CONFIG_BLK_DEV_NBD=m
89CONFIG_BLK_DEV_RAM=y
90CONFIG_BLK_DEV_RAM_SIZE=131072
91CONFIG_MISC_DEVICES=y
92CONFIG_DS1682=y
93CONFIG_BLK_DEV_SD=y
94CONFIG_CHR_DEV_ST=y
95CONFIG_BLK_DEV_SR=y
96CONFIG_ATA=y
97CONFIG_SATA_AHCI=y
98CONFIG_SATA_SIL24=y
99# CONFIG_ATA_SFF is not set
100CONFIG_NETDEVICES=y
101CONFIG_BONDING=m
102CONFIG_DUMMY=m
103CONFIG_NETCONSOLE=y
104CONFIG_NETPOLL_TRAP=y
105CONFIG_TUN=m
106# CONFIG_NET_VENDOR_3COM is not set
107CONFIG_FS_ENET=y
108CONFIG_UCC_GETH=y
109CONFIG_GIANFAR=y
110CONFIG_PPP=m
111CONFIG_PPP_BSDCOMP=m
112CONFIG_PPP_DEFLATE=m
113CONFIG_PPP_FILTER=y
114CONFIG_PPP_MULTILINK=y
115CONFIG_PPPOE=m
116CONFIG_PPP_ASYNC=m
117CONFIG_PPP_SYNC_TTY=m
118CONFIG_SLIP=m
119CONFIG_SLIP_COMPRESSED=y
120CONFIG_SLIP_SMART=y
121CONFIG_SLIP_MODE_SLIP6=y
122# CONFIG_INPUT_KEYBOARD is not set
123# CONFIG_INPUT_MOUSE is not set
124# CONFIG_SERIO is not set
125# CONFIG_LEGACY_PTYS is not set
126CONFIG_SERIAL_8250=y
127CONFIG_SERIAL_8250_CONSOLE=y
128CONFIG_SERIAL_8250_NR_UARTS=2
129CONFIG_SERIAL_8250_RUNTIME_UARTS=2
130CONFIG_SERIAL_8250_EXTENDED=y
131CONFIG_SERIAL_8250_MANY_PORTS=y
132CONFIG_SERIAL_8250_DETECT_IRQ=y
133CONFIG_SERIAL_8250_RSA=y
134CONFIG_SERIAL_QE=m
135CONFIG_NVRAM=y
136CONFIG_I2C=y
137CONFIG_I2C_CHARDEV=y
138CONFIG_I2C_CPM=m
139CONFIG_I2C_MPC=y
140CONFIG_GPIO_SYSFS=y
141CONFIG_GPIO_GE_FPGA=y
142CONFIG_SENSORS_LM90=y
143CONFIG_SENSORS_LM92=y
144CONFIG_WATCHDOG=y
145CONFIG_GEF_WDT=y
146CONFIG_VIDEO_OUTPUT_CONTROL=m
147CONFIG_HID_DRAGONRISE=y
148CONFIG_HID_GYRATION=y
149CONFIG_HID_TWINHAN=y
150CONFIG_HID_ORTEK=y
151CONFIG_HID_PANTHERLORD=y
152CONFIG_HID_PETALYNX=y
153CONFIG_HID_SAMSUNG=y
154CONFIG_HID_SONY=y
155CONFIG_HID_SUNPLUS=y
156CONFIG_HID_GREENASIA=y
157CONFIG_HID_SMARTJOYPLUS=y
158CONFIG_HID_TOPSEED=y
159CONFIG_HID_THRUSTMASTER=y
160CONFIG_HID_ZEROPLUS=y
161CONFIG_USB=y
162CONFIG_USB_DEVICEFS=y
163CONFIG_USB_EHCI_HCD=y
164# CONFIG_USB_EHCI_TT_NEWSCHED is not set
165CONFIG_USB_EHCI_FSL=y
166CONFIG_USB_OHCI_HCD=y
167CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
168CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
169CONFIG_USB_STORAGE=y
170CONFIG_EDAC=y
171CONFIG_EDAC_MM_EDAC=y
172CONFIG_EDAC_MPC85XX=y
173CONFIG_RTC_CLASS=y
174# CONFIG_RTC_INTF_PROC is not set
175CONFIG_RTC_DRV_RX8581=y
176CONFIG_DMADEVICES=y
177CONFIG_FSL_DMA=y
178# CONFIG_NET_DMA is not set
179CONFIG_EXT2_FS=y
180CONFIG_EXT2_FS_XATTR=y
181CONFIG_EXT2_FS_POSIX_ACL=y
182CONFIG_EXT3_FS=y
183# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
184CONFIG_EXT3_FS_POSIX_ACL=y
185CONFIG_EXT4_FS=y
186CONFIG_FUSE_FS=y
187CONFIG_ISO9660_FS=y
188CONFIG_JOLIET=y
189CONFIG_ZISOFS=y
190CONFIG_UDF_FS=y
191CONFIG_MSDOS_FS=y
192CONFIG_VFAT_FS=y
193CONFIG_FAT_DEFAULT_CODEPAGE=850
194CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
195CONFIG_NTFS_FS=y
196CONFIG_PROC_KCORE=y
197CONFIG_TMPFS=y
198CONFIG_JFFS2_FS=y
199CONFIG_NFS_FS=y
200CONFIG_NFS_V3=y
201CONFIG_NFS_V4=y
202CONFIG_ROOT_NFS=y
203CONFIG_NFSD=y
204CONFIG_NFSD_V4=y
205CONFIG_CIFS=m
206CONFIG_CIFS_XATTR=y
207CONFIG_CIFS_POSIX=y
208CONFIG_NLS_CODEPAGE_437=y
209CONFIG_NLS_CODEPAGE_737=m
210CONFIG_NLS_CODEPAGE_775=m
211CONFIG_NLS_CODEPAGE_850=y
212CONFIG_NLS_CODEPAGE_852=m
213CONFIG_NLS_CODEPAGE_855=m
214CONFIG_NLS_CODEPAGE_857=m
215CONFIG_NLS_CODEPAGE_860=m
216CONFIG_NLS_CODEPAGE_861=m
217CONFIG_NLS_CODEPAGE_862=m
218CONFIG_NLS_CODEPAGE_863=m
219CONFIG_NLS_CODEPAGE_864=m
220CONFIG_NLS_CODEPAGE_865=m
221CONFIG_NLS_CODEPAGE_866=m
222CONFIG_NLS_CODEPAGE_869=m
223CONFIG_NLS_CODEPAGE_936=m
224CONFIG_NLS_CODEPAGE_950=m
225CONFIG_NLS_CODEPAGE_932=m
226CONFIG_NLS_CODEPAGE_949=m
227CONFIG_NLS_CODEPAGE_874=m
228CONFIG_NLS_ISO8859_8=m
229CONFIG_NLS_CODEPAGE_1250=m
230CONFIG_NLS_CODEPAGE_1251=m
231CONFIG_NLS_ASCII=y
232CONFIG_NLS_ISO8859_1=y
233CONFIG_NLS_ISO8859_2=m
234CONFIG_NLS_ISO8859_3=m
235CONFIG_NLS_ISO8859_4=m
236CONFIG_NLS_ISO8859_5=m
237CONFIG_NLS_ISO8859_6=m
238CONFIG_NLS_ISO8859_7=m
239CONFIG_NLS_ISO8859_9=m
240CONFIG_NLS_ISO8859_13=m
241CONFIG_NLS_ISO8859_14=m
242CONFIG_NLS_ISO8859_15=y
243CONFIG_NLS_KOI8_R=m
244CONFIG_NLS_KOI8_U=m
245CONFIG_NLS_UTF8=y
246CONFIG_CRC_CCITT=y
247CONFIG_CRC_T10DIF=y
248CONFIG_LIBCRC32C=y
249CONFIG_MAGIC_SYSRQ=y
250CONFIG_SYSCTL_SYSCALL_CHECK=y
251CONFIG_CRYPTO_CBC=y
252CONFIG_CRYPTO_MD5=y
253CONFIG_CRYPTO_SHA256=m
254CONFIG_CRYPTO_SHA512=m
255CONFIG_CRYPTO_DES=y
256# CONFIG_CRYPTO_ANSI_CPRNG is not set
257CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
index d41857a5152d..da731c2fe984 100644
--- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
+++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
@@ -131,6 +131,7 @@ CONFIG_I2C=y
131CONFIG_I2C_CHARDEV=y 131CONFIG_I2C_CHARDEV=y
132CONFIG_I2C_MPC=y 132CONFIG_I2C_MPC=y
133CONFIG_GPIO_SYSFS=y 133CONFIG_GPIO_SYSFS=y
134CONFIG_GPIO_GE_FPGA=y
134CONFIG_SENSORS_LM90=y 135CONFIG_SENSORS_LM90=y
135CONFIG_SENSORS_LM92=y 136CONFIG_SENSORS_LM92=y
136CONFIG_WATCHDOG=y 137CONFIG_WATCHDOG=y
diff --git a/arch/powerpc/configs/86xx/gef_sbc310_defconfig b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
index 38303ec11bcd..2149360a1e62 100644
--- a/arch/powerpc/configs/86xx/gef_sbc310_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc310_defconfig
@@ -132,6 +132,7 @@ CONFIG_I2C=y
132CONFIG_I2C_CHARDEV=y 132CONFIG_I2C_CHARDEV=y
133CONFIG_I2C_MPC=y 133CONFIG_I2C_MPC=y
134CONFIG_GPIO_SYSFS=y 134CONFIG_GPIO_SYSFS=y
135CONFIG_GPIO_GE_FPGA=y
135CONFIG_SENSORS_LM90=y 136CONFIG_SENSORS_LM90=y
136CONFIG_SENSORS_LM92=y 137CONFIG_SENSORS_LM92=y
137CONFIG_WATCHDOG=y 138CONFIG_WATCHDOG=y
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index 98533973d20f..af2e8e1edba6 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -183,6 +183,8 @@ CONFIG_NVRAM=y
183CONFIG_I2C=y 183CONFIG_I2C=y
184CONFIG_I2C_CHARDEV=y 184CONFIG_I2C_CHARDEV=y
185CONFIG_I2C_MPC=y 185CONFIG_I2C_MPC=y
186CONFIG_GPIO_SYSFS=y
187CONFIG_GPIO_GE_FPGA=y
186CONFIG_SENSORS_LM90=y 188CONFIG_SENSORS_LM90=y
187CONFIG_SENSORS_LM92=y 189CONFIG_SENSORS_LM92=y
188CONFIG_WATCHDOG=y 190CONFIG_WATCHDOG=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index f37a2ab48881..5fb0c8a94811 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,4 +1,5 @@
1CONFIG_PPC_85xx=y 1CONFIG_PPC_85xx=y
2CONFIG_PHYS_64BIT=y
2CONFIG_EXPERIMENTAL=y 3CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y 4CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y 5CONFIG_POSIX_MQUEUE=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index abdcd317cda7..fb51bc90edd2 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -1,4 +1,5 @@
1CONFIG_PPC_85xx=y 1CONFIG_PPC_85xx=y
2CONFIG_PHYS_64BIT=y
2CONFIG_SMP=y 3CONFIG_SMP=y
3CONFIG_NR_CPUS=8 4CONFIG_NR_CPUS=8
4CONFIG_EXPERIMENTAL=y 5CONFIG_EXPERIMENTAL=y
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index ad55a1ccb9fb..b9219e99bd2a 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -390,6 +390,10 @@ extern const char *powerpc_base_platform;
390 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 390 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
391 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 391 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
392 CPU_FTR_DEBUG_LVL_EXC) 392 CPU_FTR_DEBUG_LVL_EXC)
393#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
394 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
395 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
396 CPU_FTR_DEBUG_LVL_EXC)
393#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 397#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
394 398
395/* 64-bit CPUs */ 399/* 64-bit CPUs */
@@ -442,7 +446,7 @@ extern const char *powerpc_base_platform;
442 446
443#ifdef __powerpc64__ 447#ifdef __powerpc64__
444#ifdef CONFIG_PPC_BOOK3E 448#ifdef CONFIG_PPC_BOOK3E
445#define CPU_FTRS_POSSIBLE (CPU_FTRS_E5500 | CPU_FTRS_A2) 449#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500 | CPU_FTRS_A2)
446#else 450#else
447#define CPU_FTRS_POSSIBLE \ 451#define CPU_FTRS_POSSIBLE \
448 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ 452 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
@@ -483,7 +487,7 @@ enum {
483#endif 487#endif
484#ifdef CONFIG_E500 488#ifdef CONFIG_E500
485 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC | 489 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
486 CPU_FTRS_E5500 | 490 CPU_FTRS_E5500 | CPU_FTRS_E6500 |
487#endif 491#endif
488 0, 492 0,
489}; 493};
@@ -491,7 +495,7 @@ enum {
491 495
492#ifdef __powerpc64__ 496#ifdef __powerpc64__
493#ifdef CONFIG_PPC_BOOK3E 497#ifdef CONFIG_PPC_BOOK3E
494#define CPU_FTRS_ALWAYS (CPU_FTRS_E5500 & CPU_FTRS_A2) 498#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
495#else 499#else
496#define CPU_FTRS_ALWAYS \ 500#define CPU_FTRS_ALWAYS \
497 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ 501 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
@@ -528,7 +532,7 @@ enum {
528#endif 532#endif
529#ifdef CONFIG_E500 533#ifdef CONFIG_E500
530 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC & 534 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
531 CPU_FTRS_E5500 & 535 CPU_FTRS_E5500 & CPU_FTRS_E6500 &
532#endif 536#endif
533 CPU_FTRS_POSSIBLE, 537 CPU_FTRS_POSSIBLE,
534}; 538};
diff --git a/arch/powerpc/include/asm/fsl_guts.h b/arch/powerpc/include/asm/fsl_guts.h
index bebd12463ec9..ce04530d2000 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -4,7 +4,7 @@
4 * Authors: Jeff Brown 4 * Authors: Jeff Brown
5 * Timur Tabi <timur@freescale.com> 5 * Timur Tabi <timur@freescale.com>
6 * 6 *
7 * Copyright 2004,2007 Freescale Semiconductor, Inc 7 * Copyright 2004,2007,2012 Freescale Semiconductor, Inc
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -114,6 +114,10 @@ struct ccsr_guts_86xx {
114 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */ 114 __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
115} __attribute__ ((packed)); 115} __attribute__ ((packed));
116 116
117
118/* Alternate function signal multiplex control */
119#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
120
117#ifdef CONFIG_PPC_86xx 121#ifdef CONFIG_PPC_86xx
118 122
119#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ 123#define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
new file mode 100644
index 000000000000..3ec37dc9003e
--- /dev/null
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; version 2 of the
7 * License.
8 *
9 */
10
11#ifndef _ASM_MPIC_MSGR_H
12#define _ASM_MPIC_MSGR_H
13
14#include <linux/types.h>
15#include <linux/spinlock.h>
16
17struct mpic_msgr {
18 u32 __iomem *base;
19 u32 __iomem *mer;
20 int irq;
21 unsigned char in_use;
22 raw_spinlock_t lock;
23 int num;
24};
25
26/* Get a message register
27 *
28 * @reg_num: the MPIC message register to get
29 *
30 * A pointer to the message register is returned. If
31 * the message register asked for is already in use, then
32 * EBUSY is returned. If the number given is not associated
33 * with an actual message register, then ENODEV is returned.
34 * Successfully getting the register marks it as in use.
35 */
36extern struct mpic_msgr *mpic_msgr_get(unsigned int reg_num);
37
38/* Relinquish a message register
39 *
40 * @msgr: the message register to return
41 *
42 * Disables the given message register and marks it as free.
43 * After this call has completed successully the message
44 * register is available to be acquired by a call to
45 * mpic_msgr_get.
46 */
47extern void mpic_msgr_put(struct mpic_msgr *msgr);
48
49/* Enable a message register
50 *
51 * @msgr: the message register to enable
52 *
53 * The given message register is enabled for sending
54 * messages.
55 */
56extern void mpic_msgr_enable(struct mpic_msgr *msgr);
57
58/* Disable a message register
59 *
60 * @msgr: the message register to disable
61 *
62 * The given message register is disabled for sending
63 * messages.
64 */
65extern void mpic_msgr_disable(struct mpic_msgr *msgr);
66
67/* Write a message to a message register
68 *
69 * @msgr: the message register to write to
70 * @message: the message to write
71 *
72 * The given 32-bit message is written to the given message
73 * register. Writing to an enabled message registers fires
74 * an interrupt.
75 */
76static inline void mpic_msgr_write(struct mpic_msgr *msgr, u32 message)
77{
78 out_be32(msgr->base, message);
79}
80
81/* Read a message from a message register
82 *
83 * @msgr: the message register to read from
84 *
85 * Returns the 32-bit value currently in the given message register.
86 * Upon reading the register any interrupts for that register are
87 * cleared.
88 */
89static inline u32 mpic_msgr_read(struct mpic_msgr *msgr)
90{
91 return in_be32(msgr->base);
92}
93
94/* Clear a message register
95 *
96 * @msgr: the message register to clear
97 *
98 * Clears any interrupts associated with the given message register.
99 */
100static inline void mpic_msgr_clear(struct mpic_msgr *msgr)
101{
102 (void) mpic_msgr_read(msgr);
103}
104
105/* Set the destination CPU for the message register
106 *
107 * @msgr: the message register whose destination is to be set
108 * @cpu_num: the Linux CPU number to bind the message register to
109 *
110 * Note that the CPU number given is the CPU number used by the kernel
111 * and *not* the actual hardware CPU number.
112 */
113static inline void mpic_msgr_set_destination(struct mpic_msgr *msgr,
114 u32 cpu_num)
115{
116 out_be32(msgr->base, 1 << get_hard_smp_processor_id(cpu_num));
117}
118
119/* Get the IRQ number for the message register
120 * @msgr: the message register whose IRQ is to be returned
121 *
122 * Returns the IRQ number associated with the given message register.
123 * NO_IRQ is returned if this message register is not capable of
124 * receiving interrupts. What message register can and cannot receive
125 * interrupts is specified in the device tree for the system.
126 */
127static inline int mpic_msgr_get_irq(struct mpic_msgr *msgr)
128{
129 return msgr->irq;
130}
131
132#endif
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 500fe1dc43e6..8a97aa7289d3 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -62,6 +62,7 @@
62#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ 62#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
63#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ 63#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
64#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ 64#define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
65#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
65#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ 66#define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
66#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */ 67#define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
67#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */ 68#define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 87353baf21fb..138ae183c440 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -2019,6 +2019,24 @@ static struct cpu_spec __initdata cpu_specs[] = {
2019 .machine_check = machine_check_e500mc, 2019 .machine_check = machine_check_e500mc,
2020 .platform = "ppce5500", 2020 .platform = "ppce5500",
2021 }, 2021 },
2022 { /* e6500 */
2023 .pvr_mask = 0xffff0000,
2024 .pvr_value = 0x80400000,
2025 .cpu_name = "e6500",
2026 .cpu_features = CPU_FTRS_E6500,
2027 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
2028 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
2029 MMU_FTR_USE_TLBILX,
2030 .icache_bsize = 64,
2031 .dcache_bsize = 64,
2032 .num_pmcs = 4,
2033 .oprofile_cpu_type = "ppc/e6500",
2034 .oprofile_type = PPC_OPROFILE_FSL_EMB,
2035 .cpu_setup = __setup_cpu_e5500,
2036 .cpu_restore = __restore_cpu_e5500,
2037 .machine_check = machine_check_e500mc,
2038 .platform = "ppce6500",
2039 },
2022#ifdef CONFIG_PPC32 2040#ifdef CONFIG_PPC32
2023 { /* default match */ 2041 { /* default match */
2024 .pvr_mask = 0x00000000, 2042 .pvr_mask = 0x00000000,
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 66a6fd38e9cd..07ba45b0f07c 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -149,12 +149,19 @@ static void settlbcam(int index, unsigned long virt, phys_addr_t phys,
149unsigned long calc_cam_sz(unsigned long ram, unsigned long virt, 149unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
150 phys_addr_t phys) 150 phys_addr_t phys)
151{ 151{
152 unsigned int camsize = __ilog2(ram) & ~1U; 152 unsigned int camsize = __ilog2(ram);
153 unsigned int align = __ffs(virt | phys) & ~1U; 153 unsigned int align = __ffs(virt | phys);
154 unsigned long max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; 154 unsigned long max_cam;
155 155
156 /* Convert (4^max) kB to (2^max) bytes */ 156 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
157 max_cam = max_cam * 2 + 10; 157 /* Convert (4^max) kB to (2^max) bytes */
158 max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
159 camsize &= ~1U;
160 align &= ~1U;
161 } else {
162 /* Convert (2^max) kB to (2^max) bytes */
163 max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
164 }
158 165
159 if (camsize > align) 166 if (camsize > align)
160 camsize = align; 167 camsize = align;
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index d7946be298b6..f000d81c4e31 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -6,6 +6,7 @@ menuconfig FSL_SOC_BOOKE
6 select MPIC 6 select MPIC
7 select PPC_PCI_CHOICE 7 select PPC_PCI_CHOICE
8 select FSL_PCI if PCI 8 select FSL_PCI if PCI
9 select SERIAL_8250_EXTENDED if SERIAL_8250
9 select SERIAL_8250_SHARE_IRQ if SERIAL_8250 10 select SERIAL_8250_SHARE_IRQ if SERIAL_8250
10 default y 11 default y
11 12
@@ -13,6 +14,15 @@ if FSL_SOC_BOOKE
13 14
14if PPC32 15if PPC32
15 16
17config FSL_85XX_CACHE_SRAM
18 bool
19 select PPC_LIB_RHEAP
20 help
21 When selected, this option enables cache-sram support
22 for memory allocation on P1/P2 QorIQ platforms.
23 cache-sram-size and cache-sram-offset kernel boot
24 parameters should be passed when this option is enabled.
25
16config MPC8540_ADS 26config MPC8540_ADS
17 bool "Freescale MPC8540 ADS" 27 bool "Freescale MPC8540 ADS"
18 select DEFAULT_UIMAGE 28 select DEFAULT_UIMAGE
@@ -30,6 +40,7 @@ config MPC85xx_CDS
30 bool "Freescale MPC85xx CDS" 40 bool "Freescale MPC85xx CDS"
31 select DEFAULT_UIMAGE 41 select DEFAULT_UIMAGE
32 select PPC_I8259 42 select PPC_I8259
43 select HAS_RAPIDIO
33 help 44 help
34 This option enables support for the MPC85xx CDS board 45 This option enables support for the MPC85xx CDS board
35 46
@@ -80,7 +91,6 @@ config P1010_RDB
80config P1022_DS 91config P1022_DS
81 bool "Freescale P1022 DS" 92 bool "Freescale P1022 DS"
82 select DEFAULT_UIMAGE 93 select DEFAULT_UIMAGE
83 select PHYS_64BIT # The DTS has 36-bit addresses
84 select SWIOTLB 94 select SWIOTLB
85 help 95 help
86 This option enables support for the Freescale P1022DS reference board. 96 This option enables support for the Freescale P1022DS reference board.
@@ -171,6 +181,21 @@ config SBC8560
171 help 181 help
172 This option enables support for the Wind River SBC8560 board 182 This option enables support for the Wind River SBC8560 board
173 183
184config GE_IMP3A
185 bool "GE Intelligent Platforms IMP3A"
186 select DEFAULT_UIMAGE
187 select SWIOTLB
188 select MMIO_NVRAM
189 select GENERIC_GPIO
190 select ARCH_REQUIRE_GPIOLIB
191 select GE_FPGA
192 help
193 This option enables support for the GE Intelligent Platforms IMP3A
194 board.
195
196 This board is a 3U CompactPCI Single Board Computer with a Freescale
197 P2020 processor.
198
174config P2041_RDB 199config P2041_RDB
175 bool "Freescale P2041 RDB" 200 bool "Freescale P2041 RDB"
176 select DEFAULT_UIMAGE 201 select DEFAULT_UIMAGE
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 9cb2d4320dcc..2125d4ca068a 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -27,3 +27,4 @@ obj-$(CONFIG_SBC8548) += sbc8548.o
27obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o 27obj-$(CONFIG_SOCRATES) += socrates.o socrates_fpga_pic.o
28obj-$(CONFIG_KSI8560) += ksi8560.o 28obj-$(CONFIG_KSI8560) += ksi8560.o
29obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o 29obj-$(CONFIG_XES_MPC85xx) += xes_mpc85xx.o
30obj-$(CONFIG_GE_IMP3A) += ge_imp3a.o
diff --git a/arch/powerpc/platforms/85xx/ge_imp3a.c b/arch/powerpc/platforms/85xx/ge_imp3a.c
new file mode 100644
index 000000000000..d50056f424f6
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/ge_imp3a.c
@@ -0,0 +1,246 @@
1/*
2 * GE IMP3A Board Setup
3 *
4 * Author Martyn Welch <martyn.welch@ge.com>
5 *
6 * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
14 * Copyright 2007 Freescale Semiconductor Inc.
15 */
16
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/delay.h>
22#include <linux/seq_file.h>
23#include <linux/interrupt.h>
24#include <linux/of_platform.h>
25#include <linux/memblock.h>
26
27#include <asm/system.h>
28#include <asm/time.h>
29#include <asm/machdep.h>
30#include <asm/pci-bridge.h>
31#include <mm/mmu_decl.h>
32#include <asm/prom.h>
33#include <asm/udbg.h>
34#include <asm/mpic.h>
35#include <asm/swiotlb.h>
36#include <asm/nvram.h>
37
38#include <sysdev/fsl_soc.h>
39#include <sysdev/fsl_pci.h>
40#include "smp.h"
41
42#include "mpc85xx.h"
43#include <sysdev/ge/ge_pic.h>
44
45void __iomem *imp3a_regs;
46
47void __init ge_imp3a_pic_init(void)
48{
49 struct mpic *mpic;
50 struct device_node *np;
51 struct device_node *cascade_node = NULL;
52 unsigned long root = of_get_flat_dt_root();
53
54 if (of_flat_dt_is_compatible(root, "fsl,MPC8572DS-CAMP")) {
55 mpic = mpic_alloc(NULL, 0,
56 MPIC_NO_RESET |
57 MPIC_BIG_ENDIAN |
58 MPIC_SINGLE_DEST_CPU,
59 0, 256, " OpenPIC ");
60 } else {
61 mpic = mpic_alloc(NULL, 0,
62 MPIC_BIG_ENDIAN |
63 MPIC_SINGLE_DEST_CPU,
64 0, 256, " OpenPIC ");
65 }
66
67 BUG_ON(mpic == NULL);
68 mpic_init(mpic);
69 /*
70 * There is a simple interrupt handler in the main FPGA, this needs
71 * to be cascaded into the MPIC
72 */
73 for_each_node_by_type(np, "interrupt-controller")
74 if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
75 cascade_node = np;
76 break;
77 }
78
79 if (cascade_node == NULL) {
80 printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
81 return;
82 }
83
84 gef_pic_init(cascade_node);
85 of_node_put(cascade_node);
86}
87
88#ifdef CONFIG_PCI
89static int primary_phb_addr;
90#endif /* CONFIG_PCI */
91
92/*
93 * Setup the architecture
94 */
95static void __init ge_imp3a_setup_arch(void)
96{
97 struct device_node *regs;
98#ifdef CONFIG_PCI
99 struct device_node *np;
100 struct pci_controller *hose;
101#endif
102 dma_addr_t max = 0xffffffff;
103
104 if (ppc_md.progress)
105 ppc_md.progress("ge_imp3a_setup_arch()", 0);
106
107#ifdef CONFIG_PCI
108 for_each_node_by_type(np, "pci") {
109 if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
110 of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
111 of_device_is_compatible(np, "fsl,p2020-pcie")) {
112 struct resource rsrc;
113 of_address_to_resource(np, 0, &rsrc);
114 if ((rsrc.start & 0xfffff) == primary_phb_addr)
115 fsl_add_bridge(np, 1);
116 else
117 fsl_add_bridge(np, 0);
118
119 hose = pci_find_hose_for_OF_device(np);
120 max = min(max, hose->dma_window_base_cur +
121 hose->dma_window_size);
122 }
123 }
124#endif
125
126 mpc85xx_smp_init();
127
128#ifdef CONFIG_SWIOTLB
129 if (memblock_end_of_DRAM() > max) {
130 ppc_swiotlb_enable = 1;
131 set_pci_dma_ops(&swiotlb_dma_ops);
132 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
133 }
134#endif
135
136 /* Remap basic board registers */
137 regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
138 if (regs) {
139 imp3a_regs = of_iomap(regs, 0);
140 if (imp3a_regs == NULL)
141 printk(KERN_WARNING "Unable to map board registers\n");
142 of_node_put(regs);
143 }
144
145#if defined(CONFIG_MMIO_NVRAM)
146 mmio_nvram_init();
147#endif
148
149 printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
150}
151
152/* Return the PCB revision */
153static unsigned int ge_imp3a_get_pcb_rev(void)
154{
155 unsigned int reg;
156
157 reg = ioread16(imp3a_regs);
158 return (reg >> 8) & 0xff;
159}
160
161/* Return the board (software) revision */
162static unsigned int ge_imp3a_get_board_rev(void)
163{
164 unsigned int reg;
165
166 reg = ioread16(imp3a_regs + 0x2);
167 return reg & 0xff;
168}
169
170/* Return the FPGA revision */
171static unsigned int ge_imp3a_get_fpga_rev(void)
172{
173 unsigned int reg;
174
175 reg = ioread16(imp3a_regs + 0x2);
176 return (reg >> 8) & 0xff;
177}
178
179/* Return compactPCI Geographical Address */
180static unsigned int ge_imp3a_get_cpci_geo_addr(void)
181{
182 unsigned int reg;
183
184 reg = ioread16(imp3a_regs + 0x6);
185 return (reg & 0x0f00) >> 8;
186}
187
188/* Return compactPCI System Controller Status */
189static unsigned int ge_imp3a_get_cpci_is_syscon(void)
190{
191 unsigned int reg;
192
193 reg = ioread16(imp3a_regs + 0x6);
194 return reg & (1 << 12);
195}
196
197static void ge_imp3a_show_cpuinfo(struct seq_file *m)
198{
199 seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
200
201 seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
202 ('A' + ge_imp3a_get_board_rev() - 1));
203
204 seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
205
206 seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
207
208 seq_printf(m, "cPCI syscon\t: %s\n",
209 ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
210}
211
212/*
213 * Called very early, device-tree isn't unflattened
214 */
215static int __init ge_imp3a_probe(void)
216{
217 unsigned long root = of_get_flat_dt_root();
218
219 if (of_flat_dt_is_compatible(root, "ge,IMP3A")) {
220#ifdef CONFIG_PCI
221 primary_phb_addr = 0x9000;
222#endif
223 return 1;
224 }
225
226 return 0;
227}
228
229machine_device_initcall(ge_imp3a, mpc85xx_common_publish_devices);
230
231machine_arch_initcall(ge_imp3a, swiotlb_setup_bus_notifier);
232
233define_machine(ge_imp3a) {
234 .name = "GE_IMP3A",
235 .probe = ge_imp3a_probe,
236 .setup_arch = ge_imp3a_setup_arch,
237 .init_IRQ = ge_imp3a_pic_init,
238 .show_cpuinfo = ge_imp3a_show_cpuinfo,
239#ifdef CONFIG_PCI
240 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
241#endif
242 .get_irq = mpic_get_irq,
243 .restart = fsl_rstcr_restart,
244 .calibrate_decr = generic_calibrate_decr,
245 .progress = udbg_progress,
246};
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 02d97e31c18c..ab5f0bf19454 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information) 4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 * 5 *
6 * Copyright 2005 Freescale Semiconductor Inc. 6 * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify it 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 9 * under the terms of the GNU General Public License as published by the
@@ -48,17 +48,24 @@
48 48
49#include "mpc85xx.h" 49#include "mpc85xx.h"
50 50
51/* CADMUS info */ 51/*
52/* xxx - galak, move into device tree */ 52 * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
53#define CADMUS_BASE (0xf8004000) 53 * various logic and performs system control functions.
54#define CADMUS_SIZE (256) 54 * Here is the FPGA/CPLD register map.
55#define CM_VER (0) 55 */
56#define CM_CSR (1) 56struct cadmus_reg {
57#define CM_RST (2) 57 u8 cm_ver; /* Board version */
58 58 u8 cm_csr; /* General control/status */
59 u8 cm_rst; /* Reset control */
60 u8 cm_hsclk; /* High speed clock */
61 u8 cm_hsxclk; /* High speed clock extended */
62 u8 cm_led; /* LED data */
63 u8 cm_pci; /* PCI control/status */
64 u8 cm_dma; /* DMA control */
65 u8 res[248]; /* Total 256 bytes */
66};
59 67
60static int cds_pci_slot = 2; 68static struct cadmus_reg *cadmus;
61static volatile u8 *cadmus;
62 69
63#ifdef CONFIG_PCI 70#ifdef CONFIG_PCI
64 71
@@ -158,6 +165,33 @@ DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
158DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge); 165DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
159DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge); 166DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
160 167
168#define PCI_DEVICE_ID_IDT_TSI310 0x01a7
169
170/*
171 * Fix Tsi310 PCI-X bridge resource.
172 * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
173 * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
174 */
175void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
176{
177 struct pci_dev *dev = bus->self;
178 struct resource *res = bus->resource[0];
179
180 if (dev != NULL &&
181 dev->vendor == PCI_VENDOR_ID_IBM &&
182 dev->device == PCI_DEVICE_ID_IDT_TSI310) {
183 if (res) {
184 res->start = 0;
185 res->end = 0x1fff;
186 res->flags = IORESOURCE_IO;
187 pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
188 pr_info("mpc85xx_cds: %pR\n", res);
189 }
190 }
191
192 fsl_pcibios_fixup_bus(bus);
193}
194
161#ifdef CONFIG_PPC_I8259 195#ifdef CONFIG_PPC_I8259
162static void mpc85xx_8259_cascade_handler(unsigned int irq, 196static void mpc85xx_8259_cascade_handler(unsigned int irq,
163 struct irq_desc *desc) 197 struct irq_desc *desc)
@@ -248,20 +282,30 @@ machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
248 */ 282 */
249static void __init mpc85xx_cds_setup_arch(void) 283static void __init mpc85xx_cds_setup_arch(void)
250{ 284{
251#ifdef CONFIG_PCI
252 struct device_node *np; 285 struct device_node *np;
253#endif 286 int cds_pci_slot;
254 287
255 if (ppc_md.progress) 288 if (ppc_md.progress)
256 ppc_md.progress("mpc85xx_cds_setup_arch()", 0); 289 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
257 290
258 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE); 291 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
259 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1; 292 if (!np) {
293 pr_err("Could not find FPGA node.\n");
294 return;
295 }
296
297 cadmus = of_iomap(np, 0);
298 of_node_put(np);
299 if (!cadmus) {
300 pr_err("Fail to map FPGA area.\n");
301 return;
302 }
260 303
261 if (ppc_md.progress) { 304 if (ppc_md.progress) {
262 char buf[40]; 305 char buf[40];
306 cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
263 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n", 307 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
264 cadmus[CM_VER], cds_pci_slot); 308 in_8(&cadmus->cm_ver), cds_pci_slot);
265 ppc_md.progress(buf, 0); 309 ppc_md.progress(buf, 0);
266 } 310 }
267 311
@@ -291,7 +335,8 @@ static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
291 svid = mfspr(SPRN_SVR); 335 svid = mfspr(SPRN_SVR);
292 336
293 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n"); 337 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
294 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n", cadmus[CM_VER]); 338 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
339 in_8(&cadmus->cm_ver));
295 seq_printf(m, "PVR\t\t: 0x%x\n", pvid); 340 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
296 seq_printf(m, "SVR\t\t: 0x%x\n", svid); 341 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
297 342
@@ -322,7 +367,7 @@ define_machine(mpc85xx_cds) {
322 .get_irq = mpic_get_irq, 367 .get_irq = mpic_get_irq,
323#ifdef CONFIG_PCI 368#ifdef CONFIG_PCI
324 .restart = mpc85xx_cds_restart, 369 .restart = mpc85xx_cds_restart,
325 .pcibios_fixup_bus = fsl_pcibios_fixup_bus, 370 .pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
326#else 371#else
327 .restart = fsl_rstcr_restart, 372 .restart = fsl_rstcr_restart,
328#endif 373#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 57aceb5d273e..f33662b46b8d 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -1,5 +1,6 @@
1/* 1/*
2 * Copyright (C) Freescale Semicondutor, Inc. 2006-2010. All rights reserved. 2 * Copyright (C) 2006-2010, 2012 Freescale Semicondutor, Inc.
3 * All rights reserved.
3 * 4 *
4 * Author: Andy Fleming <afleming@freescale.com> 5 * Author: Andy Fleming <afleming@freescale.com>
5 * 6 *
@@ -51,6 +52,7 @@
51#include <asm/qe_ic.h> 52#include <asm/qe_ic.h>
52#include <asm/mpic.h> 53#include <asm/mpic.h>
53#include <asm/swiotlb.h> 54#include <asm/swiotlb.h>
55#include <asm/fsl_guts.h>
54#include "smp.h" 56#include "smp.h"
55 57
56#include "mpc85xx.h" 58#include "mpc85xx.h"
@@ -268,34 +270,27 @@ static void __init mpc85xx_mds_qe_init(void)
268 mpc85xx_mds_reset_ucc_phys(); 270 mpc85xx_mds_reset_ucc_phys();
269 271
270 if (machine_is(p1021_mds)) { 272 if (machine_is(p1021_mds)) {
271#define MPC85xx_PMUXCR_OFFSET 0x60
272#define MPC85xx_PMUXCR_QE0 0x00008000
273#define MPC85xx_PMUXCR_QE3 0x00001000
274#define MPC85xx_PMUXCR_QE9 0x00000040
275#define MPC85xx_PMUXCR_QE12 0x00000008
276 static __be32 __iomem *pmuxcr;
277 273
278 np = of_find_node_by_name(NULL, "global-utilities"); 274 struct ccsr_guts_85xx __iomem *guts;
279 275
276 np = of_find_node_by_name(NULL, "global-utilities");
280 if (np) { 277 if (np) {
281 pmuxcr = of_iomap(np, 0) + MPC85xx_PMUXCR_OFFSET; 278 guts = of_iomap(np, 0);
282 279 if (!guts)
283 if (!pmuxcr) 280 pr_err("mpc85xx-rdb: could not map global utilities register\n");
284 printk(KERN_EMERG "Error: Alternate function" 281 else{
285 " signal multiplex control register not"
286 " mapped!\n");
287 else
288 /* P1021 has pins muxed for QE and other functions. To 282 /* P1021 has pins muxed for QE and other functions. To
289 * enable QE UEC mode, we need to set bit QE0 for UCC1 283 * enable QE UEC mode, we need to set bit QE0 for UCC1
290 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9 284 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
291 * and QE12 for QE MII management signals in PMUXCR 285 * and QE12 for QE MII management signals in PMUXCR
292 * register. 286 * register.
293 */ 287 */
294 setbits32(pmuxcr, MPC85xx_PMUXCR_QE0 | 288 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
295 MPC85xx_PMUXCR_QE3 | 289 MPC85xx_PMUXCR_QE(3) |
296 MPC85xx_PMUXCR_QE9 | 290 MPC85xx_PMUXCR_QE(9) |
297 MPC85xx_PMUXCR_QE12); 291 MPC85xx_PMUXCR_QE(12));
298 292 iounmap(guts);
293 }
299 of_node_put(np); 294 of_node_put(np);
300 } 295 }
301 296
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 407c7391e360..db214cd4c822 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC85xx RDB Board Setup 2 * MPC85xx RDB Board Setup
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009,2012 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -26,6 +26,9 @@
26#include <asm/prom.h> 26#include <asm/prom.h>
27#include <asm/udbg.h> 27#include <asm/udbg.h>
28#include <asm/mpic.h> 28#include <asm/mpic.h>
29#include <asm/qe.h>
30#include <asm/qe_ic.h>
31#include <asm/fsl_guts.h>
29 32
30#include <sysdev/fsl_soc.h> 33#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h> 34#include <sysdev/fsl_pci.h>
@@ -47,6 +50,10 @@ void __init mpc85xx_rdb_pic_init(void)
47 struct mpic *mpic; 50 struct mpic *mpic;
48 unsigned long root = of_get_flat_dt_root(); 51 unsigned long root = of_get_flat_dt_root();
49 52
53#ifdef CONFIG_QUICC_ENGINE
54 struct device_node *np;
55#endif
56
50 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) { 57 if (of_flat_dt_is_compatible(root, "fsl,MPC85XXRDB-CAMP")) {
51 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET | 58 mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
52 MPIC_BIG_ENDIAN | 59 MPIC_BIG_ENDIAN |
@@ -61,6 +68,18 @@ void __init mpc85xx_rdb_pic_init(void)
61 68
62 BUG_ON(mpic == NULL); 69 BUG_ON(mpic == NULL);
63 mpic_init(mpic); 70 mpic_init(mpic);
71
72#ifdef CONFIG_QUICC_ENGINE
73 np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
74 if (np) {
75 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
76 qe_ic_cascade_high_mpic);
77 of_node_put(np);
78
79 } else
80 pr_err("%s: Could not find qe-ic node\n", __func__);
81#endif
82
64} 83}
65 84
66/* 85/*
@@ -68,7 +87,7 @@ void __init mpc85xx_rdb_pic_init(void)
68 */ 87 */
69static void __init mpc85xx_rdb_setup_arch(void) 88static void __init mpc85xx_rdb_setup_arch(void)
70{ 89{
71#ifdef CONFIG_PCI 90#if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
72 struct device_node *np; 91 struct device_node *np;
73#endif 92#endif
74 93
@@ -84,11 +103,73 @@ static void __init mpc85xx_rdb_setup_arch(void)
84#endif 103#endif
85 104
86 mpc85xx_smp_init(); 105 mpc85xx_smp_init();
106
107#ifdef CONFIG_QUICC_ENGINE
108 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
109 if (!np) {
110 pr_err("%s: Could not find Quicc Engine node\n", __func__);
111 goto qe_fail;
112 }
113
114 qe_reset();
115 of_node_put(np);
116
117 np = of_find_node_by_name(NULL, "par_io");
118 if (np) {
119 struct device_node *ucc;
120
121 par_io_init(np);
122 of_node_put(np);
123
124 for_each_node_by_name(ucc, "ucc")
125 par_io_of_config(ucc);
126
127 }
128#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
129 if (machine_is(p1025_rdb)) {
130
131 struct ccsr_guts_85xx __iomem *guts;
132
133 np = of_find_node_by_name(NULL, "global-utilities");
134 if (np) {
135 guts = of_iomap(np, 0);
136 if (!guts) {
137
138 pr_err("mpc85xx-rdb: could not map global utilities register\n");
139
140 } else {
141 /* P1025 has pins muxed for QE and other functions. To
142 * enable QE UEC mode, we need to set bit QE0 for UCC1
143 * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
144 * and QE12 for QE MII management singals in PMUXCR
145 * register.
146 */
147 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
148 MPC85xx_PMUXCR_QE(3) |
149 MPC85xx_PMUXCR_QE(9) |
150 MPC85xx_PMUXCR_QE(12));
151 iounmap(guts);
152 }
153 of_node_put(np);
154 }
155
156 }
157#endif
158
159qe_fail:
160#endif /* CONFIG_QUICC_ENGINE */
161
87 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n"); 162 printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
88} 163}
89 164
90machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices); 165machine_device_initcall(p2020_rdb, mpc85xx_common_publish_devices);
166machine_device_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
167machine_device_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
91machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices); 168machine_device_initcall(p1020_rdb, mpc85xx_common_publish_devices);
169machine_device_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
170machine_device_initcall(p1020_utm_pc, mpc85xx_common_publish_devices);
171machine_device_initcall(p1021_rdb_pc, mpc85xx_common_publish_devices);
172machine_device_initcall(p1025_rdb, mpc85xx_common_publish_devices);
92 173
93/* 174/*
94 * Called very early, device-tree isn't unflattened 175 * Called very early, device-tree isn't unflattened
@@ -111,6 +192,52 @@ static int __init p1020_rdb_probe(void)
111 return 0; 192 return 0;
112} 193}
113 194
195static int __init p1020_rdb_pc_probe(void)
196{
197 unsigned long root = of_get_flat_dt_root();
198
199 return of_flat_dt_is_compatible(root, "fsl,P1020RDB-PC");
200}
201
202static int __init p1021_rdb_pc_probe(void)
203{
204 unsigned long root = of_get_flat_dt_root();
205
206 if (of_flat_dt_is_compatible(root, "fsl,P1021RDB-PC"))
207 return 1;
208 return 0;
209}
210
211static int __init p2020_rdb_pc_probe(void)
212{
213 unsigned long root = of_get_flat_dt_root();
214
215 if (of_flat_dt_is_compatible(root, "fsl,P2020RDB-PC"))
216 return 1;
217 return 0;
218}
219
220static int __init p1025_rdb_probe(void)
221{
222 unsigned long root = of_get_flat_dt_root();
223
224 return of_flat_dt_is_compatible(root, "fsl,P1025RDB");
225}
226
227static int __init p1020_mbg_pc_probe(void)
228{
229 unsigned long root = of_get_flat_dt_root();
230
231 return of_flat_dt_is_compatible(root, "fsl,P1020MBG-PC");
232}
233
234static int __init p1020_utm_pc_probe(void)
235{
236 unsigned long root = of_get_flat_dt_root();
237
238 return of_flat_dt_is_compatible(root, "fsl,P1020UTM-PC");
239}
240
114define_machine(p2020_rdb) { 241define_machine(p2020_rdb) {
115 .name = "P2020 RDB", 242 .name = "P2020 RDB",
116 .probe = p2020_rdb_probe, 243 .probe = p2020_rdb_probe,
@@ -138,3 +265,87 @@ define_machine(p1020_rdb) {
138 .calibrate_decr = generic_calibrate_decr, 265 .calibrate_decr = generic_calibrate_decr,
139 .progress = udbg_progress, 266 .progress = udbg_progress,
140}; 267};
268
269define_machine(p1021_rdb_pc) {
270 .name = "P1021 RDB-PC",
271 .probe = p1021_rdb_pc_probe,
272 .setup_arch = mpc85xx_rdb_setup_arch,
273 .init_IRQ = mpc85xx_rdb_pic_init,
274#ifdef CONFIG_PCI
275 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
276#endif
277 .get_irq = mpic_get_irq,
278 .restart = fsl_rstcr_restart,
279 .calibrate_decr = generic_calibrate_decr,
280 .progress = udbg_progress,
281};
282
283define_machine(p2020_rdb_pc) {
284 .name = "P2020RDB-PC",
285 .probe = p2020_rdb_pc_probe,
286 .setup_arch = mpc85xx_rdb_setup_arch,
287 .init_IRQ = mpc85xx_rdb_pic_init,
288#ifdef CONFIG_PCI
289 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
290#endif
291 .get_irq = mpic_get_irq,
292 .restart = fsl_rstcr_restart,
293 .calibrate_decr = generic_calibrate_decr,
294 .progress = udbg_progress,
295};
296
297define_machine(p1025_rdb) {
298 .name = "P1025 RDB",
299 .probe = p1025_rdb_probe,
300 .setup_arch = mpc85xx_rdb_setup_arch,
301 .init_IRQ = mpc85xx_rdb_pic_init,
302#ifdef CONFIG_PCI
303 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
304#endif
305 .get_irq = mpic_get_irq,
306 .restart = fsl_rstcr_restart,
307 .calibrate_decr = generic_calibrate_decr,
308 .progress = udbg_progress,
309};
310
311define_machine(p1020_mbg_pc) {
312 .name = "P1020 MBG-PC",
313 .probe = p1020_mbg_pc_probe,
314 .setup_arch = mpc85xx_rdb_setup_arch,
315 .init_IRQ = mpc85xx_rdb_pic_init,
316#ifdef CONFIG_PCI
317 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
318#endif
319 .get_irq = mpic_get_irq,
320 .restart = fsl_rstcr_restart,
321 .calibrate_decr = generic_calibrate_decr,
322 .progress = udbg_progress,
323};
324
325define_machine(p1020_utm_pc) {
326 .name = "P1020 UTM-PC",
327 .probe = p1020_utm_pc_probe,
328 .setup_arch = mpc85xx_rdb_setup_arch,
329 .init_IRQ = mpc85xx_rdb_pic_init,
330#ifdef CONFIG_PCI
331 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
332#endif
333 .get_irq = mpic_get_irq,
334 .restart = fsl_rstcr_restart,
335 .calibrate_decr = generic_calibrate_decr,
336 .progress = udbg_progress,
337};
338
339define_machine(p1020_rdb_pc) {
340 .name = "P1020RDB-PC",
341 .probe = p1020_rdb_pc_probe,
342 .setup_arch = mpc85xx_rdb_setup_arch,
343 .init_IRQ = mpc85xx_rdb_pic_init,
344#ifdef CONFIG_PCI
345 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
346#endif
347 .get_irq = mpic_get_irq,
348 .restart = fsl_rstcr_restart,
349 .calibrate_decr = generic_calibrate_decr,
350 .progress = udbg_progress,
351};
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index 63ba79053960..0fe88e39945e 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -33,6 +33,10 @@
33 33
34#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 34#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
35 35
36#define PMUXCR_ELBCDIU_MASK 0xc0000000
37#define PMUXCR_ELBCDIU_NOR16 0x80000000
38#define PMUXCR_ELBCDIU_DIU 0x40000000
39
36/* 40/*
37 * Board-specific initialization of the DIU. This code should probably be 41 * Board-specific initialization of the DIU. This code should probably be
38 * executed when the DIU is opened, rather than in arch code, but the DIU 42 * executed when the DIU is opened, rather than in arch code, but the DIU
@@ -50,11 +54,22 @@
50#define CLKDVDR_PXCLK_MASK 0x00FF0000 54#define CLKDVDR_PXCLK_MASK 0x00FF0000
51 55
52/* Some ngPIXIS register definitions */ 56/* Some ngPIXIS register definitions */
57#define PX_CTL 3
58#define PX_BRDCFG0 8
59#define PX_BRDCFG1 9
60
61#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
62#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
63#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
64#define PX_BRDCFG0_ELBC_DIU 0x02
65
53#define PX_BRDCFG1_DVIEN 0x80 66#define PX_BRDCFG1_DVIEN 0x80
54#define PX_BRDCFG1_DFPEN 0x40 67#define PX_BRDCFG1_DFPEN 0x40
55#define PX_BRDCFG1_BACKLIGHT 0x20 68#define PX_BRDCFG1_BACKLIGHT 0x20
56#define PX_BRDCFG1_DDCEN 0x10 69#define PX_BRDCFG1_DDCEN 0x10
57 70
71#define PX_CTL_ALTACC 0x80
72
58/* 73/*
59 * DIU Area Descriptor 74 * DIU Area Descriptor
60 * 75 *
@@ -133,44 +148,117 @@ static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
133 */ 148 */
134static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port) 149static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
135{ 150{
136 struct device_node *np; 151 struct device_node *guts_node;
137 void __iomem *pixis; 152 struct device_node *indirect_node = NULL;
138 u8 __iomem *brdcfg1; 153 struct ccsr_guts_85xx __iomem *guts;
139 154 u8 __iomem *lbc_lcs0_ba = NULL;
140 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga"); 155 u8 __iomem *lbc_lcs1_ba = NULL;
141 if (!np) 156 u8 b;
142 /* older device trees used "fsl,p1022ds-pixis" */ 157
143 np = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis"); 158 /* Map the global utilities registers. */
144 if (!np) { 159 guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
145 pr_err("p1022ds: missing ngPIXIS node\n"); 160 if (!guts_node) {
161 pr_err("p1022ds: missing global utilties device node\n");
146 return; 162 return;
147 } 163 }
148 164
149 pixis = of_iomap(np, 0); 165 guts = of_iomap(guts_node, 0);
150 if (!pixis) { 166 if (!guts) {
151 pr_err("p1022ds: could not map ngPIXIS registers\n"); 167 pr_err("p1022ds: could not map global utilties device\n");
152 return; 168 goto exit;
153 } 169 }
154 brdcfg1 = pixis + 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */ 170
171 indirect_node = of_find_compatible_node(NULL, NULL,
172 "fsl,p1022ds-indirect-pixis");
173 if (!indirect_node) {
174 pr_err("p1022ds: missing pixis indirect mode node\n");
175 goto exit;
176 }
177
178 lbc_lcs0_ba = of_iomap(indirect_node, 0);
179 if (!lbc_lcs0_ba) {
180 pr_err("p1022ds: could not map localbus chip select 0\n");
181 goto exit;
182 }
183
184 lbc_lcs1_ba = of_iomap(indirect_node, 1);
185 if (!lbc_lcs1_ba) {
186 pr_err("p1022ds: could not map localbus chip select 1\n");
187 goto exit;
188 }
189
190 /* Make sure we're in indirect mode first. */
191 if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
192 PMUXCR_ELBCDIU_DIU) {
193 struct device_node *pixis_node;
194 void __iomem *pixis;
195
196 pixis_node =
197 of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
198 if (!pixis_node) {
199 pr_err("p1022ds: missing pixis node\n");
200 goto exit;
201 }
202
203 pixis = of_iomap(pixis_node, 0);
204 of_node_put(pixis_node);
205 if (!pixis) {
206 pr_err("p1022ds: could not map pixis registers\n");
207 goto exit;
208 }
209
210 /* Enable indirect PIXIS mode. */
211 setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
212 iounmap(pixis);
213
214 /* Switch the board mux to the DIU */
215 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
216 b = in_8(lbc_lcs1_ba);
217 b |= PX_BRDCFG0_ELBC_DIU;
218 out_8(lbc_lcs1_ba, b);
219
220 /* Set the chip mux to DIU mode. */
221 clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
222 PMUXCR_ELBCDIU_DIU);
223 in_be32(&guts->pmuxcr);
224 }
225
155 226
156 switch (port) { 227 switch (port) {
157 case FSL_DIU_PORT_DVI: 228 case FSL_DIU_PORT_DVI:
158 printk(KERN_INFO "%s:%u\n", __func__, __LINE__);
159 /* Enable the DVI port, disable the DFP and the backlight */ 229 /* Enable the DVI port, disable the DFP and the backlight */
160 clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT, 230 out_8(lbc_lcs0_ba, PX_BRDCFG1);
161 PX_BRDCFG1_DVIEN); 231 b = in_8(lbc_lcs1_ba);
232 b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
233 b |= PX_BRDCFG1_DVIEN;
234 out_8(lbc_lcs1_ba, b);
162 break; 235 break;
163 case FSL_DIU_PORT_LVDS: 236 case FSL_DIU_PORT_LVDS:
164 printk(KERN_INFO "%s:%u\n", __func__, __LINE__); 237 /*
238 * LVDS also needs backlight enabled, otherwise the display
239 * will be blank.
240 */
165 /* Enable the DFP port, disable the DVI and the backlight */ 241 /* Enable the DFP port, disable the DVI and the backlight */
166 clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT, 242 out_8(lbc_lcs0_ba, PX_BRDCFG1);
167 PX_BRDCFG1_DFPEN); 243 b = in_8(lbc_lcs1_ba);
244 b &= ~PX_BRDCFG1_DVIEN;
245 b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
246 out_8(lbc_lcs1_ba, b);
168 break; 247 break;
169 default: 248 default:
170 pr_err("p1022ds: unsupported monitor port %i\n", port); 249 pr_err("p1022ds: unsupported monitor port %i\n", port);
171 } 250 }
172 251
173 iounmap(pixis); 252exit:
253 if (lbc_lcs1_ba)
254 iounmap(lbc_lcs1_ba);
255 if (lbc_lcs0_ba)
256 iounmap(lbc_lcs0_ba);
257 if (guts)
258 iounmap(guts);
259
260 of_node_put(indirect_node);
261 of_node_put(guts_node);
174} 262}
175 263
176/** 264/**
@@ -249,6 +337,49 @@ void __init p1022_ds_pic_init(void)
249 mpic_init(mpic); 337 mpic_init(mpic);
250} 338}
251 339
340#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
341
342/*
343 * Disables a node in the device tree.
344 *
345 * This function is called before kmalloc() is available, so the 'new' object
346 * should be allocated in the global area. The easiest way is to do that is
347 * to allocate one static local variable for each call to this function.
348 */
349static void __init disable_one_node(struct device_node *np, struct property *new)
350{
351 struct property *old;
352
353 old = of_find_property(np, new->name, NULL);
354 if (old)
355 prom_update_property(np, new, old);
356 else
357 prom_add_property(np, new);
358}
359
360/* TRUE if there is a "video=fslfb" command-line parameter. */
361static bool fslfb;
362
363/*
364 * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
365 * true if we find it.
366 *
367 * We need to use early_param() instead of __setup() because the normal
368 * __setup() gets called to late. However, early_param() gets called very
369 * early, before the device tree is unflattened, so all we can do now is set a
370 * global variable. Later on, p1022_ds_setup_arch() will use that variable
371 * to determine if we need to update the device tree.
372 */
373static int __init early_video_setup(char *options)
374{
375 fslfb = (strncmp(options, "fslfb:", 6) == 0);
376
377 return 0;
378}
379early_param("video", early_video_setup);
380
381#endif
382
252/* 383/*
253 * Setup the architecture 384 * Setup the architecture
254 */ 385 */
@@ -286,6 +417,34 @@ static void __init p1022_ds_setup_arch(void)
286 diu_ops.set_monitor_port = p1022ds_set_monitor_port; 417 diu_ops.set_monitor_port = p1022ds_set_monitor_port;
287 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock; 418 diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
288 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port; 419 diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
420
421 /*
422 * Disable the NOR flash node if there is video=fslfb... command-line
423 * parameter. When the DIU is active, NOR flash is unavailable, so we
424 * have to disable the node before the MTD driver loads.
425 */
426 if (fslfb) {
427 struct device_node *np =
428 of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
429
430 if (np) {
431 np = of_find_compatible_node(np, NULL, "cfi-flash");
432 if (np) {
433 static struct property nor_status = {
434 .name = "status",
435 .value = "disabled",
436 .length = sizeof("disabled"),
437 };
438
439 pr_info("p1022ds: disabling %s node",
440 np->full_name);
441 disable_one_node(np, &nor_status);
442 of_node_put(np);
443 }
444 }
445
446 }
447
289#endif 448#endif
290 449
291 mpc85xx_smp_init(); 450 mpc85xx_smp_init();
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 8d6599d54ea6..7a6279e38213 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -39,6 +39,7 @@ config GEF_PPC9A
39 select MMIO_NVRAM 39 select MMIO_NVRAM
40 select GENERIC_GPIO 40 select GENERIC_GPIO
41 select ARCH_REQUIRE_GPIOLIB 41 select ARCH_REQUIRE_GPIOLIB
42 select GE_FPGA
42 help 43 help
43 This option enables support for the GE PPC9A. 44 This option enables support for the GE PPC9A.
44 45
@@ -48,6 +49,7 @@ config GEF_SBC310
48 select MMIO_NVRAM 49 select MMIO_NVRAM
49 select GENERIC_GPIO 50 select GENERIC_GPIO
50 select ARCH_REQUIRE_GPIOLIB 51 select ARCH_REQUIRE_GPIOLIB
52 select GE_FPGA
51 help 53 help
52 This option enables support for the GE SBC310. 54 This option enables support for the GE SBC310.
53 55
@@ -57,6 +59,7 @@ config GEF_SBC610
57 select MMIO_NVRAM 59 select MMIO_NVRAM
58 select GENERIC_GPIO 60 select GENERIC_GPIO
59 select ARCH_REQUIRE_GPIOLIB 61 select ARCH_REQUIRE_GPIOLIB
62 select GE_FPGA
60 select HAS_RAPIDIO 63 select HAS_RAPIDIO
61 help 64 help
62 This option enables support for the GE SBC610. 65 This option enables support for the GE SBC610.
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 4b0d7b1aa005..ede815d6489d 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
7obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o 7obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
8obj-$(CONFIG_SBC8641D) += sbc8641d.o 8obj-$(CONFIG_SBC8641D) += sbc8641d.o
9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o 9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
10gef-gpio-$(CONFIG_GPIOLIB) += gef_gpio.o 10obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
11obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o gef_pic.o $(gef-gpio-y) 11obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
12obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o gef_pic.o $(gef-gpio-y) 12obj-$(CONFIG_GEF_PPC9A) += gef_ppc9a.o
13obj-$(CONFIG_GEF_PPC9A) += gef_ppc9a.o gef_pic.o $(gef-gpio-y)
diff --git a/arch/powerpc/platforms/86xx/gef_gpio.c b/arch/powerpc/platforms/86xx/gef_gpio.c
deleted file mode 100644
index 2a703365e664..000000000000
--- a/arch/powerpc/platforms/86xx/gef_gpio.c
+++ /dev/null
@@ -1,171 +0,0 @@
1/*
2 * Driver for GE FPGA based GPIO
3 *
4 * Author: Martyn Welch <martyn.welch@ge.com>
5 *
6 * 2008 (c) GE Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
13/* TODO
14 *
15 * Configuration of output modes (totem-pole/open-drain)
16 * Interrupt configuration - interrupts are always generated the FPGA relies on
17 * the I/O interrupt controllers mask to stop them propergating
18 */
19
20#include <linux/kernel.h>
21#include <linux/compiler.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/of_platform.h>
27#include <linux/of_gpio.h>
28#include <linux/gpio.h>
29#include <linux/slab.h>
30#include <linux/module.h>
31
32#define GEF_GPIO_DIRECT 0x00
33#define GEF_GPIO_IN 0x04
34#define GEF_GPIO_OUT 0x08
35#define GEF_GPIO_TRIG 0x0C
36#define GEF_GPIO_POLAR_A 0x10
37#define GEF_GPIO_POLAR_B 0x14
38#define GEF_GPIO_INT_STAT 0x18
39#define GEF_GPIO_OVERRUN 0x1C
40#define GEF_GPIO_MODE 0x20
41
42static void _gef_gpio_set(void __iomem *reg, unsigned int offset, int value)
43{
44 unsigned int data;
45
46 data = ioread32be(reg);
47 /* value: 0=low; 1=high */
48 if (value & 0x1)
49 data = data | (0x1 << offset);
50 else
51 data = data & ~(0x1 << offset);
52
53 iowrite32be(data, reg);
54}
55
56
57static int gef_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
58{
59 unsigned int data;
60 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
61
62 data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
63 data = data | (0x1 << offset);
64 iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
65
66 return 0;
67}
68
69static int gef_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int value)
70{
71 unsigned int data;
72 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
73
74 /* Set direction before switching to input */
75 _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
76
77 data = ioread32be(mmchip->regs + GEF_GPIO_DIRECT);
78 data = data & ~(0x1 << offset);
79 iowrite32be(data, mmchip->regs + GEF_GPIO_DIRECT);
80
81 return 0;
82}
83
84static int gef_gpio_get(struct gpio_chip *chip, unsigned offset)
85{
86 unsigned int data;
87 int state = 0;
88 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
89
90 data = ioread32be(mmchip->regs + GEF_GPIO_IN);
91 state = (int)((data >> offset) & 0x1);
92
93 return state;
94}
95
96static void gef_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
97{
98 struct of_mm_gpio_chip *mmchip = to_of_mm_gpio_chip(chip);
99
100 _gef_gpio_set(mmchip->regs + GEF_GPIO_OUT, offset, value);
101}
102
103static int __init gef_gpio_init(void)
104{
105 struct device_node *np;
106 int retval;
107 struct of_mm_gpio_chip *gef_gpio_chip;
108
109 for_each_compatible_node(np, NULL, "gef,sbc610-gpio") {
110
111 pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
112
113 /* Allocate chip structure */
114 gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
115 if (!gef_gpio_chip) {
116 pr_err("%s: Unable to allocate structure\n",
117 np->full_name);
118 continue;
119 }
120
121 /* Setup pointers to chip functions */
122 gef_gpio_chip->gc.of_gpio_n_cells = 2;
123 gef_gpio_chip->gc.ngpio = 19;
124 gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
125 gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
126 gef_gpio_chip->gc.get = gef_gpio_get;
127 gef_gpio_chip->gc.set = gef_gpio_set;
128
129 /* This function adds a memory mapped GPIO chip */
130 retval = of_mm_gpiochip_add(np, gef_gpio_chip);
131 if (retval) {
132 kfree(gef_gpio_chip);
133 pr_err("%s: Unable to add GPIO\n", np->full_name);
134 }
135 }
136
137 for_each_compatible_node(np, NULL, "gef,sbc310-gpio") {
138
139 pr_debug("%s: Initialising GEF GPIO\n", np->full_name);
140
141 /* Allocate chip structure */
142 gef_gpio_chip = kzalloc(sizeof(*gef_gpio_chip), GFP_KERNEL);
143 if (!gef_gpio_chip) {
144 pr_err("%s: Unable to allocate structure\n",
145 np->full_name);
146 continue;
147 }
148
149 /* Setup pointers to chip functions */
150 gef_gpio_chip->gc.of_gpio_n_cells = 2;
151 gef_gpio_chip->gc.ngpio = 6;
152 gef_gpio_chip->gc.direction_input = gef_gpio_dir_in;
153 gef_gpio_chip->gc.direction_output = gef_gpio_dir_out;
154 gef_gpio_chip->gc.get = gef_gpio_get;
155 gef_gpio_chip->gc.set = gef_gpio_set;
156
157 /* This function adds a memory mapped GPIO chip */
158 retval = of_mm_gpiochip_add(np, gef_gpio_chip);
159 if (retval) {
160 kfree(gef_gpio_chip);
161 pr_err("%s: Unable to add GPIO\n", np->full_name);
162 }
163 }
164
165 return 0;
166};
167arch_initcall(gef_gpio_init);
168
169MODULE_DESCRIPTION("GE I/O FPGA GPIO driver");
170MODULE_AUTHOR("Martyn Welch <martyn.welch@ge.com");
171MODULE_LICENSE("GPL");
diff --git a/arch/powerpc/platforms/86xx/gef_ppc9a.c b/arch/powerpc/platforms/86xx/gef_ppc9a.c
index 60ce07e39100..ed58b6cfd60c 100644
--- a/arch/powerpc/platforms/86xx/gef_ppc9a.c
+++ b/arch/powerpc/platforms/86xx/gef_ppc9a.c
@@ -37,9 +37,9 @@
37 37
38#include <sysdev/fsl_pci.h> 38#include <sysdev/fsl_pci.h>
39#include <sysdev/fsl_soc.h> 39#include <sysdev/fsl_soc.h>
40#include <sysdev/ge/ge_pic.h>
40 41
41#include "mpc86xx.h" 42#include "mpc86xx.h"
42#include "gef_pic.h"
43 43
44#undef DEBUG 44#undef DEBUG
45 45
diff --git a/arch/powerpc/platforms/86xx/gef_sbc310.c b/arch/powerpc/platforms/86xx/gef_sbc310.c
index 3ecee25bf3ed..710db69bd523 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc310.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc310.c
@@ -37,9 +37,9 @@
37 37
38#include <sysdev/fsl_pci.h> 38#include <sysdev/fsl_pci.h>
39#include <sysdev/fsl_soc.h> 39#include <sysdev/fsl_soc.h>
40#include <sysdev/ge/ge_pic.h>
40 41
41#include "mpc86xx.h" 42#include "mpc86xx.h"
42#include "gef_pic.h"
43 43
44#undef DEBUG 44#undef DEBUG
45 45
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index 5090d608d9ee..4a13d2f4ac20 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -37,9 +37,9 @@
37 37
38#include <sysdev/fsl_pci.h> 38#include <sysdev/fsl_pci.h>
39#include <sysdev/fsl_soc.h> 39#include <sysdev/fsl_soc.h>
40#include <sysdev/ge/ge_pic.h>
40 41
41#include "mpc86xx.h" 42#include "mpc86xx.h"
42#include "gef_pic.h"
43 43
44#undef DEBUG 44#undef DEBUG
45 45
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 236ab67bc3a4..a35ca44ade66 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -86,6 +86,14 @@ config MPIC_WEIRD
86 bool 86 bool
87 default n 87 default n
88 88
89config MPIC_MSGR
90 bool "MPIC message register support"
91 depends on MPIC
92 default n
93 help
94 Enables support for the MPIC message registers. These
95 registers are used for inter-processor communication.
96
89config PPC_I8259 97config PPC_I8259
90 bool 98 bool
91 default n 99 default n
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index 7b4df37ac381..a84fecf63c4d 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -29,3 +29,7 @@ config SCOM_DEBUGFS
29 bool "Expose SCOM controllers via debugfs" 29 bool "Expose SCOM controllers via debugfs"
30 depends on PPC_SCOM 30 depends on PPC_SCOM
31 default n 31 default n
32
33config GE_FPGA
34 bool
35 default n
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5e37b4717864..1bd7ecb24620 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -4,6 +4,8 @@ ccflags-$(CONFIG_PPC64) := -mno-minimal-toc
4 4
5mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o 5mpic-msi-obj-$(CONFIG_PCI_MSI) += mpic_msi.o mpic_u3msi.o mpic_pasemi_msi.o
6obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) 6obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y)
7mpic-msgr-obj-$(CONFIG_MPIC_MSGR) += mpic_msgr.o
8obj-$(CONFIG_MPIC) += mpic.o $(mpic-msi-obj-y) $(mpic-msgr-obj-y)
7obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o 9obj-$(CONFIG_PPC_EPAPR_HV_PIC) += ehv_pic.o
8fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o 10fsl-msi-obj-$(CONFIG_PCI_MSI) += fsl_msi.o
9obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o 11obj-$(CONFIG_PPC_MSI_BITMAP) += msi_bitmap.o
@@ -65,3 +67,5 @@ obj-$(CONFIG_PPC_SCOM) += scom.o
65subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror 67subdir-ccflags-$(CONFIG_PPC_WERROR) := -Werror
66 68
67obj-$(CONFIG_PPC_XICS) += xics/ 69obj-$(CONFIG_PPC_XICS) += xics/
70
71obj-$(CONFIG_GE_FPGA) += ge/
diff --git a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
index 116415899176..37a69097e022 100644
--- a/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
+++ b/arch/powerpc/sysdev/fsl_85xx_cache_sram.c
@@ -24,6 +24,7 @@
24 */ 24 */
25 25
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/export.h>
27#include <linux/slab.h> 28#include <linux/slab.h>
28#include <linux/err.h> 29#include <linux/err.h>
29#include <linux/of_platform.h> 30#include <linux/of_platform.h>
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 5f88797dce73..cedabd0f4bfe 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -21,6 +21,7 @@
21 */ 21 */
22 22
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/module.h>
24#include <linux/of_platform.h> 25#include <linux/of_platform.h>
25#include <asm/io.h> 26#include <asm/io.h>
26 27
@@ -200,6 +201,9 @@ static struct of_device_id mpc85xx_l2ctlr_of_match[] = {
200 { 201 {
201 .compatible = "fsl,p1022-l2-cache-controller", 202 .compatible = "fsl,p1022-l2-cache-controller",
202 }, 203 },
204 {
205 .compatible = "fsl,mpc8548-l2-cache-controller",
206 },
203 {}, 207 {},
204}; 208};
205 209
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index ecb5c1946d22..0bab15626ee2 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -410,6 +410,7 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
410 410
411 msi->msi_regs = ioremap(res.start, resource_size(&res)); 411 msi->msi_regs = ioremap(res.start, resource_size(&res));
412 if (!msi->msi_regs) { 412 if (!msi->msi_regs) {
413 err = -ENOMEM;
413 dev_err(&dev->dev, "could not map node %s\n", 414 dev_err(&dev->dev, "could not map node %s\n",
414 dev->dev.of_node->full_name); 415 dev->dev.of_node->full_name);
415 goto error_out; 416 goto error_out;
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index a4c4f4a932d8..5b6f556094dd 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -66,8 +66,8 @@
66 " li %0,%3\n" \ 66 " li %0,%3\n" \
67 " b 2b\n" \ 67 " b 2b\n" \
68 ".section __ex_table,\"a\"\n" \ 68 ".section __ex_table,\"a\"\n" \
69 " .align 2\n" \ 69 PPC_LONG_ALIGN "\n" \
70 " .long 1b,3b\n" \ 70 PPC_LONG "1b,3b\n" \
71 ".text" \ 71 ".text" \
72 : "=r" (err), "=r" (x) \ 72 : "=r" (err), "=r" (x) \
73 : "b" (addr), "i" (-EFAULT), "0" (err)) 73 : "b" (addr), "i" (-EFAULT), "0" (err))
diff --git a/arch/powerpc/sysdev/fsl_rmu.c b/arch/powerpc/sysdev/fsl_rmu.c
index 15485789e9db..14bd5221f28a 100644
--- a/arch/powerpc/sysdev/fsl_rmu.c
+++ b/arch/powerpc/sysdev/fsl_rmu.c
@@ -100,14 +100,8 @@
100#define DOORBELL_DSR_TE 0x00000080 100#define DOORBELL_DSR_TE 0x00000080
101#define DOORBELL_DSR_QFI 0x00000010 101#define DOORBELL_DSR_QFI 0x00000010
102#define DOORBELL_DSR_DIQI 0x00000001 102#define DOORBELL_DSR_DIQI 0x00000001
103#define DOORBELL_TID_OFFSET 0x02
104#define DOORBELL_SID_OFFSET 0x04
105#define DOORBELL_INFO_OFFSET 0x06
106 103
107#define DOORBELL_MESSAGE_SIZE 0x08 104#define DOORBELL_MESSAGE_SIZE 0x08
108#define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET))
109#define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET))
110#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET))
111 105
112struct rio_msg_regs { 106struct rio_msg_regs {
113 u32 omr; 107 u32 omr;
@@ -193,6 +187,13 @@ struct fsl_rmu {
193 int rxirq; 187 int rxirq;
194}; 188};
195 189
190struct rio_dbell_msg {
191 u16 pad1;
192 u16 tid;
193 u16 sid;
194 u16 info;
195};
196
196/** 197/**
197 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler 198 * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
198 * @irq: Linux interrupt number 199 * @irq: Linux interrupt number
@@ -311,8 +312,8 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
311 312
312 /* XXX Need to check/dispatch until queue empty */ 313 /* XXX Need to check/dispatch until queue empty */
313 if (dsr & DOORBELL_DSR_DIQI) { 314 if (dsr & DOORBELL_DSR_DIQI) {
314 u32 dmsg = 315 struct rio_dbell_msg *dmsg =
315 (u32) fsl_dbell->dbell_ring.virt + 316 fsl_dbell->dbell_ring.virt +
316 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff); 317 (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
317 struct rio_dbell *dbell; 318 struct rio_dbell *dbell;
318 int found = 0; 319 int found = 0;
@@ -320,25 +321,25 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
320 pr_debug 321 pr_debug
321 ("RIO: processing doorbell," 322 ("RIO: processing doorbell,"
322 " sid %2.2x tid %2.2x info %4.4x\n", 323 " sid %2.2x tid %2.2x info %4.4x\n",
323 DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); 324 dmsg->sid, dmsg->tid, dmsg->info);
324 325
325 for (i = 0; i < MAX_PORT_NUM; i++) { 326 for (i = 0; i < MAX_PORT_NUM; i++) {
326 if (fsl_dbell->mport[i]) { 327 if (fsl_dbell->mport[i]) {
327 list_for_each_entry(dbell, 328 list_for_each_entry(dbell,
328 &fsl_dbell->mport[i]->dbells, node) { 329 &fsl_dbell->mport[i]->dbells, node) {
329 if ((dbell->res->start 330 if ((dbell->res->start
330 <= DBELL_INF(dmsg)) 331 <= dmsg->info)
331 && (dbell->res->end 332 && (dbell->res->end
332 >= DBELL_INF(dmsg))) { 333 >= dmsg->info)) {
333 found = 1; 334 found = 1;
334 break; 335 break;
335 } 336 }
336 } 337 }
337 if (found && dbell->dinb) { 338 if (found && dbell->dinb) {
338 dbell->dinb(fsl_dbell->mport[i], 339 dbell->dinb(fsl_dbell->mport[i],
339 dbell->dev_id, DBELL_SID(dmsg), 340 dbell->dev_id, dmsg->sid,
340 DBELL_TID(dmsg), 341 dmsg->tid,
341 DBELL_INF(dmsg)); 342 dmsg->info);
342 break; 343 break;
343 } 344 }
344 } 345 }
@@ -348,8 +349,8 @@ fsl_rio_dbell_handler(int irq, void *dev_instance)
348 pr_debug 349 pr_debug
349 ("RIO: spurious doorbell," 350 ("RIO: spurious doorbell,"
350 " sid %2.2x tid %2.2x info %4.4x\n", 351 " sid %2.2x tid %2.2x info %4.4x\n",
351 DBELL_SID(dmsg), DBELL_TID(dmsg), 352 dmsg->sid, dmsg->tid,
352 DBELL_INF(dmsg)); 353 dmsg->info);
353 } 354 }
354 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI); 355 setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
355 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI); 356 out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
@@ -657,7 +658,7 @@ fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
657 int ret = 0; 658 int ret = 0;
658 659
659 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ 660 pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
660 "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); 661 "%p len %8.8zx\n", rdev->destid, mbox, buffer, len);
661 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { 662 if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
662 ret = -EINVAL; 663 ret = -EINVAL;
663 goto out; 664 goto out;
@@ -972,7 +973,8 @@ out:
972void *fsl_get_inb_message(struct rio_mport *mport, int mbox) 973void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
973{ 974{
974 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); 975 struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
975 u32 phys_buf, virt_buf; 976 u32 phys_buf;
977 void *virt_buf;
976 void *buf = NULL; 978 void *buf = NULL;
977 int buf_idx; 979 int buf_idx;
978 980
@@ -982,7 +984,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
982 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) 984 if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
983 goto out2; 985 goto out2;
984 986
985 virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf 987 virt_buf = rmu->msg_rx_ring.virt + (phys_buf
986 - rmu->msg_rx_ring.phys); 988 - rmu->msg_rx_ring.phys);
987 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; 989 buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
988 buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; 990 buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
@@ -994,7 +996,7 @@ void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
994 } 996 }
995 997
996 /* Copy max message size, caller is expected to allocate that big */ 998 /* Copy max message size, caller is expected to allocate that big */
997 memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); 999 memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE);
998 1000
999 /* Clear the available buffer */ 1001 /* Clear the available buffer */
1000 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; 1002 rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
diff --git a/arch/powerpc/sysdev/ge/Makefile b/arch/powerpc/sysdev/ge/Makefile
new file mode 100644
index 000000000000..8731ffcb79b9
--- /dev/null
+++ b/arch/powerpc/sysdev/ge/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_GE_FPGA) += ge_pic.o
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/sysdev/ge/ge_pic.c
index 94594e58594c..002a56295e01 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/sysdev/ge/ge_pic.c
@@ -22,7 +22,7 @@
22#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24 24
25#include "gef_pic.h" 25#include "ge_pic.h"
26 26
27#define DEBUG 27#define DEBUG
28#undef DEBUG 28#undef DEBUG
diff --git a/arch/powerpc/platforms/86xx/gef_pic.h b/arch/powerpc/sysdev/ge/ge_pic.h
index 6149916da3f4..6149916da3f4 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.h
+++ b/arch/powerpc/sysdev/ge/ge_pic.h
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
new file mode 100644
index 000000000000..6e7fa386e76a
--- /dev/null
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -0,0 +1,282 @@
1/*
2 * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
3 *
4 * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
5 * Mingkai Hu from Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 */
13
14#include <linux/list.h>
15#include <linux/of_platform.h>
16#include <linux/errno.h>
17#include <asm/prom.h>
18#include <asm/hw_irq.h>
19#include <asm/ppc-pci.h>
20#include <asm/mpic_msgr.h>
21
22#define MPIC_MSGR_REGISTERS_PER_BLOCK 4
23#define MPIC_MSGR_STRIDE 0x10
24#define MPIC_MSGR_MER_OFFSET 0x100
25#define MSGR_INUSE 0
26#define MSGR_FREE 1
27
28static struct mpic_msgr **mpic_msgrs;
29static unsigned int mpic_msgr_count;
30
31static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
32{
33 out_be32(msgr->mer, value);
34}
35
36static inline u32 _mpic_msgr_mer_read(struct mpic_msgr *msgr)
37{
38 return in_be32(msgr->mer);
39}
40
41static inline void _mpic_msgr_disable(struct mpic_msgr *msgr)
42{
43 u32 mer = _mpic_msgr_mer_read(msgr);
44
45 _mpic_msgr_mer_write(msgr, mer & ~(1 << msgr->num));
46}
47
48struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
49{
50 unsigned long flags;
51 struct mpic_msgr *msgr;
52
53 /* Assume busy until proven otherwise. */
54 msgr = ERR_PTR(-EBUSY);
55
56 if (reg_num >= mpic_msgr_count)
57 return ERR_PTR(-ENODEV);
58
59 raw_spin_lock_irqsave(&msgr->lock, flags);
60 if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
61 msgr = mpic_msgrs[reg_num];
62 msgr->in_use = MSGR_INUSE;
63 }
64 raw_spin_unlock_irqrestore(&msgr->lock, flags);
65
66 return msgr;
67}
68EXPORT_SYMBOL_GPL(mpic_msgr_get);
69
70void mpic_msgr_put(struct mpic_msgr *msgr)
71{
72 unsigned long flags;
73
74 raw_spin_lock_irqsave(&msgr->lock, flags);
75 msgr->in_use = MSGR_FREE;
76 _mpic_msgr_disable(msgr);
77 raw_spin_unlock_irqrestore(&msgr->lock, flags);
78}
79EXPORT_SYMBOL_GPL(mpic_msgr_put);
80
81void mpic_msgr_enable(struct mpic_msgr *msgr)
82{
83 unsigned long flags;
84 u32 mer;
85
86 raw_spin_lock_irqsave(&msgr->lock, flags);
87 mer = _mpic_msgr_mer_read(msgr);
88 _mpic_msgr_mer_write(msgr, mer | (1 << msgr->num));
89 raw_spin_unlock_irqrestore(&msgr->lock, flags);
90}
91EXPORT_SYMBOL_GPL(mpic_msgr_enable);
92
93void mpic_msgr_disable(struct mpic_msgr *msgr)
94{
95 unsigned long flags;
96
97 raw_spin_lock_irqsave(&msgr->lock, flags);
98 _mpic_msgr_disable(msgr);
99 raw_spin_unlock_irqrestore(&msgr->lock, flags);
100}
101EXPORT_SYMBOL_GPL(mpic_msgr_disable);
102
103/* The following three functions are used to compute the order and number of
104 * the message register blocks. They are clearly very inefficent. However,
105 * they are called *only* a few times during device initialization.
106 */
107static unsigned int mpic_msgr_number_of_blocks(void)
108{
109 unsigned int count;
110 struct device_node *aliases;
111
112 count = 0;
113 aliases = of_find_node_by_name(NULL, "aliases");
114
115 if (aliases) {
116 char buf[32];
117
118 for (;;) {
119 snprintf(buf, sizeof(buf), "mpic-msgr-block%d", count);
120 if (!of_find_property(aliases, buf, NULL))
121 break;
122
123 count += 1;
124 }
125 }
126
127 return count;
128}
129
130static unsigned int mpic_msgr_number_of_registers(void)
131{
132 return mpic_msgr_number_of_blocks() * MPIC_MSGR_REGISTERS_PER_BLOCK;
133}
134
135static int mpic_msgr_block_number(struct device_node *node)
136{
137 struct device_node *aliases;
138 unsigned int index, number_of_blocks;
139 char buf[64];
140
141 number_of_blocks = mpic_msgr_number_of_blocks();
142 aliases = of_find_node_by_name(NULL, "aliases");
143 if (!aliases)
144 return -1;
145
146 for (index = 0; index < number_of_blocks; ++index) {
147 struct property *prop;
148
149 snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index);
150 prop = of_find_property(aliases, buf, NULL);
151 if (node == of_find_node_by_path(prop->value))
152 break;
153 }
154
155 return index == number_of_blocks ? -1 : index;
156}
157
158/* The probe function for a single message register block.
159 */
160static __devinit int mpic_msgr_probe(struct platform_device *dev)
161{
162 void __iomem *msgr_block_addr;
163 int block_number;
164 struct resource rsrc;
165 unsigned int i;
166 unsigned int irq_index;
167 struct device_node *np = dev->dev.of_node;
168 unsigned int receive_mask;
169 const unsigned int *prop;
170
171 if (!np) {
172 dev_err(&dev->dev, "Device OF-Node is NULL");
173 return -EFAULT;
174 }
175
176 /* Allocate the message register array upon the first device
177 * registered.
178 */
179 if (!mpic_msgrs) {
180 mpic_msgr_count = mpic_msgr_number_of_registers();
181 dev_info(&dev->dev, "Found %d message registers\n",
182 mpic_msgr_count);
183
184 mpic_msgrs = kzalloc(sizeof(struct mpic_msgr) * mpic_msgr_count,
185 GFP_KERNEL);
186 if (!mpic_msgrs) {
187 dev_err(&dev->dev,
188 "No memory for message register blocks\n");
189 return -ENOMEM;
190 }
191 }
192 dev_info(&dev->dev, "Of-device full name %s\n", np->full_name);
193
194 /* IO map the message register block. */
195 of_address_to_resource(np, 0, &rsrc);
196 msgr_block_addr = ioremap(rsrc.start, rsrc.end - rsrc.start);
197 if (!msgr_block_addr) {
198 dev_err(&dev->dev, "Failed to iomap MPIC message registers");
199 return -EFAULT;
200 }
201
202 /* Ensure the block has a defined order. */
203 block_number = mpic_msgr_block_number(np);
204 if (block_number < 0) {
205 dev_err(&dev->dev,
206 "Failed to find message register block alias\n");
207 return -ENODEV;
208 }
209 dev_info(&dev->dev, "Setting up message register block %d\n",
210 block_number);
211
212 /* Grab the receive mask which specifies what registers can receive
213 * interrupts.
214 */
215 prop = of_get_property(np, "mpic-msgr-receive-mask", NULL);
216 receive_mask = (prop) ? *prop : 0xF;
217
218 /* Build up the appropriate message register data structures. */
219 for (i = 0, irq_index = 0; i < MPIC_MSGR_REGISTERS_PER_BLOCK; ++i) {
220 struct mpic_msgr *msgr;
221 unsigned int reg_number;
222
223 msgr = kzalloc(sizeof(struct mpic_msgr), GFP_KERNEL);
224 if (!msgr) {
225 dev_err(&dev->dev, "No memory for message register\n");
226 return -ENOMEM;
227 }
228
229 reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
230 msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
231 msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
232 msgr->in_use = MSGR_FREE;
233 msgr->num = i;
234 raw_spin_lock_init(&msgr->lock);
235
236 if (receive_mask & (1 << i)) {
237 struct resource irq;
238
239 if (of_irq_to_resource(np, irq_index, &irq) == NO_IRQ) {
240 dev_err(&dev->dev,
241 "Missing interrupt specifier");
242 kfree(msgr);
243 return -EFAULT;
244 }
245 msgr->irq = irq.start;
246 irq_index += 1;
247 } else {
248 msgr->irq = NO_IRQ;
249 }
250
251 mpic_msgrs[reg_number] = msgr;
252 mpic_msgr_disable(msgr);
253 dev_info(&dev->dev, "Register %d initialized: irq %d\n",
254 reg_number, msgr->irq);
255
256 }
257
258 return 0;
259}
260
261static const struct of_device_id mpic_msgr_ids[] = {
262 {
263 .compatible = "fsl,mpic-v3.1-msgr",
264 .data = NULL,
265 },
266 {}
267};
268
269static struct platform_driver mpic_msgr_driver = {
270 .driver = {
271 .name = "mpic-msgr",
272 .owner = THIS_MODULE,
273 .of_match_table = mpic_msgr_ids,
274 },
275 .probe = mpic_msgr_probe,
276};
277
278static __init int mpic_msgr_init(void)
279{
280 return platform_driver_register(&mpic_msgr_driver);
281}
282subsys_initcall(mpic_msgr_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 03:57:39 -0500