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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-06-28 07:01:34 -0400
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2013-06-28 07:01:34 -0400
commit405a1086bdd091d2d55db0ac905cd6332b35cec1 (patch)
tree5e7e2d38278da0bb52e9d8b987c7d0af22a8c9ed /arch
parent52388492ea7046888156ed2756fbba390b18c01e (diff)
parente11158c0c9ab59d46bb70953f6275643a7a01fa1 (diff)
Merge branch 'pm-cpufreq'
* pm-cpufreq: (41 commits) cpufreq: tegra: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: s3c64xx: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: omap: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: imx6q: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: exynos: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: dbx500: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: davinci: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: arm-big-little: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: powernow-k8: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: pcc: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: e_powersaver: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: ACPI: call CPUFREQ_POSTCHANGE notfier in error cases cpufreq: s3c2416: fix forgotten driver_data conversions cpufreq: make __cpufreq_notify_transition() static cpufreq: Fix minor formatting issues cpufreq: Fix governor start/stop race condition cpufreq: Simplify userspace governor cpufreq: X86_AMD_FREQ_SENSITIVITY: select CPU_FREQ_TABLE cpufreq: tegra: create CONFIG_ARM_TEGRA_CPUFREQ cpufreq: S3C2416/S3C64XX: select CPU_FREQ_TABLE ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/Kconfig1
-rw-r--r--arch/arm/mach-davinci/da850.c8
-rw-r--r--arch/arm/mach-pxa/Kconfig3
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq-utils.c2
-rw-r--r--arch/arm/mach-s3c24xx/cpufreq.c4
-rw-r--r--arch/arm/mach-s3c24xx/pll-s3c2410.c54
-rw-r--r--arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c54
-rw-r--r--arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c110
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c6
-rw-r--r--arch/arm/mach-tegra/Kconfig3
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu-freq-core.h2
-rw-r--r--arch/cris/Kconfig2
-rw-r--r--arch/mips/loongson/lemote-2f/clock.c3
-rw-r--r--arch/powerpc/platforms/Kconfig31
-rw-r--r--arch/powerpc/platforms/pasemi/Makefile1
-rw-r--r--arch/powerpc/platforms/pasemi/cpufreq.c330
-rw-r--r--arch/powerpc/platforms/powermac/Makefile2
-rw-r--r--arch/powerpc/platforms/powermac/cpufreq_32.c721
-rw-r--r--arch/powerpc/platforms/powermac/cpufreq_64.c746
19 files changed, 128 insertions, 1955 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index a075b3e0c5c7..e026b19b23ea 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -40,6 +40,7 @@ config ARCH_DAVINCI_DA850
40 bool "DA850/OMAP-L138/AM18x based system" 40 bool "DA850/OMAP-L138/AM18x based system"
41 select ARCH_DAVINCI_DA8XX 41 select ARCH_DAVINCI_DA8XX
42 select ARCH_HAS_CPUFREQ 42 select ARCH_HAS_CPUFREQ
43 select CPU_FREQ_TABLE
43 select CP_INTC 44 select CP_INTC
44 45
45config ARCH_DAVINCI_DA8XX 46config ARCH_DAVINCI_DA8XX
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4d6933848abf..a0d4f6038b60 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1004,7 +1004,7 @@ static const struct da850_opp da850_opp_96 = {
1004 1004
1005#define OPP(freq) \ 1005#define OPP(freq) \
1006 { \ 1006 { \
1007 .index = (unsigned int) &da850_opp_##freq, \ 1007 .driver_data = (unsigned int) &da850_opp_##freq, \
1008 .frequency = freq * 1000, \ 1008 .frequency = freq * 1000, \
1009 } 1009 }
1010 1010
@@ -1016,7 +1016,7 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
1016 OPP(200), 1016 OPP(200),
1017 OPP(96), 1017 OPP(96),
1018 { 1018 {
1019 .index = 0, 1019 .driver_data = 0,
1020 .frequency = CPUFREQ_TABLE_END, 1020 .frequency = CPUFREQ_TABLE_END,
1021 }, 1021 },
1022}; 1022};
@@ -1044,7 +1044,7 @@ static int da850_set_voltage(unsigned int index)
1044 if (!cvdd) 1044 if (!cvdd)
1045 return -ENODEV; 1045 return -ENODEV;
1046 1046
1047 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; 1047 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1048 1048
1049 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); 1049 return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
1050} 1050}
@@ -1125,7 +1125,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
1125 struct pll_data *pll = clk->pll_data; 1125 struct pll_data *pll = clk->pll_data;
1126 int ret; 1126 int ret;
1127 1127
1128 opp = (struct da850_opp *) cpufreq_info.freq_table[index].index; 1128 opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data;
1129 prediv = opp->prediv; 1129 prediv = opp->prediv;
1130 mult = opp->mult; 1130 mult = opp->mult;
1131 postdiv = opp->postdiv; 1131 postdiv = opp->postdiv;
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 96100dbf5a2e..a8427115ee07 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -615,12 +615,14 @@ endmenu
615config PXA25x 615config PXA25x
616 bool 616 bool
617 select CPU_XSCALE 617 select CPU_XSCALE
618 select CPU_FREQ_TABLE if CPU_FREQ
618 help 619 help
619 Select code specific to PXA21x/25x/26x variants 620 Select code specific to PXA21x/25x/26x variants
620 621
621config PXA27x 622config PXA27x
622 bool 623 bool
623 select CPU_XSCALE 624 select CPU_XSCALE
625 select CPU_FREQ_TABLE if CPU_FREQ
624 help 626 help
625 Select code specific to PXA27x variants 627 Select code specific to PXA27x variants
626 628
@@ -633,6 +635,7 @@ config CPU_PXA26x
633config PXA3xx 635config PXA3xx
634 bool 636 bool
635 select CPU_XSC3 637 select CPU_XSC3
638 select CPU_FREQ_TABLE if CPU_FREQ
636 help 639 help
637 Select code specific to PXA3xx variants 640 Select code specific to PXA3xx variants
638 641
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index ddd8280e3875..2a0aa5684e72 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -60,5 +60,5 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
60 */ 60 */
61void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg) 61void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
62{ 62{
63 __raw_writel(cfg->pll.index, S3C2410_MPLLCON); 63 __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
64} 64}
diff --git a/arch/arm/mach-s3c24xx/cpufreq.c b/arch/arm/mach-s3c24xx/cpufreq.c
index 3c0e78ede0da..3513e7477160 100644
--- a/arch/arm/mach-s3c24xx/cpufreq.c
+++ b/arch/arm/mach-s3c24xx/cpufreq.c
@@ -70,7 +70,7 @@ static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
70 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); 70 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
71 cfg->freq.armclk = armclk = clk_get_rate(clk_arm); 71 cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
72 72
73 cfg->pll.index = __raw_readl(S3C2410_MPLLCON); 73 cfg->pll.driver_data = __raw_readl(S3C2410_MPLLCON);
74 cfg->pll.frequency = fclk; 74 cfg->pll.frequency = fclk;
75 75
76 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10); 76 cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
@@ -431,7 +431,7 @@ static unsigned int suspend_freq;
431static int s3c_cpufreq_suspend(struct cpufreq_policy *policy) 431static int s3c_cpufreq_suspend(struct cpufreq_policy *policy)
432{ 432{
433 suspend_pll.frequency = clk_get_rate(_clk_mpll); 433 suspend_pll.frequency = clk_get_rate(_clk_mpll);
434 suspend_pll.index = __raw_readl(S3C2410_MPLLCON); 434 suspend_pll.driver_data = __raw_readl(S3C2410_MPLLCON);
435 suspend_freq = s3c_cpufreq_get(0) * 1000; 435 suspend_freq = s3c_cpufreq_get(0) * 1000;
436 436
437 return 0; 437 return 0;
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2410.c b/arch/arm/mach-s3c24xx/pll-s3c2410.c
index dcf3420a3271..5e37d368594b 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2410.c
@@ -33,36 +33,36 @@
33#include <plat/cpu-freq-core.h> 33#include <plat/cpu-freq-core.h>
34 34
35static struct cpufreq_frequency_table pll_vals_12MHz[] = { 35static struct cpufreq_frequency_table pll_vals_12MHz[] = {
36 { .frequency = 34000000, .index = PLLVAL(82, 2, 3), }, 36 { .frequency = 34000000, .driver_data = PLLVAL(82, 2, 3), },
37 { .frequency = 45000000, .index = PLLVAL(82, 1, 3), }, 37 { .frequency = 45000000, .driver_data = PLLVAL(82, 1, 3), },
38 { .frequency = 51000000, .index = PLLVAL(161, 3, 3), }, 38 { .frequency = 51000000, .driver_data = PLLVAL(161, 3, 3), },
39 { .frequency = 48000000, .index = PLLVAL(120, 2, 3), }, 39 { .frequency = 48000000, .driver_data = PLLVAL(120, 2, 3), },
40 { .frequency = 56000000, .index = PLLVAL(142, 2, 3), }, 40 { .frequency = 56000000, .driver_data = PLLVAL(142, 2, 3), },
41 { .frequency = 68000000, .index = PLLVAL(82, 2, 2), }, 41 { .frequency = 68000000, .driver_data = PLLVAL(82, 2, 2), },
42 { .frequency = 79000000, .index = PLLVAL(71, 1, 2), }, 42 { .frequency = 79000000, .driver_data = PLLVAL(71, 1, 2), },
43 { .frequency = 85000000, .index = PLLVAL(105, 2, 2), }, 43 { .frequency = 85000000, .driver_data = PLLVAL(105, 2, 2), },
44 { .frequency = 90000000, .index = PLLVAL(112, 2, 2), }, 44 { .frequency = 90000000, .driver_data = PLLVAL(112, 2, 2), },
45 { .frequency = 101000000, .index = PLLVAL(127, 2, 2), }, 45 { .frequency = 101000000, .driver_data = PLLVAL(127, 2, 2), },
46 { .frequency = 113000000, .index = PLLVAL(105, 1, 2), }, 46 { .frequency = 113000000, .driver_data = PLLVAL(105, 1, 2), },
47 { .frequency = 118000000, .index = PLLVAL(150, 2, 2), }, 47 { .frequency = 118000000, .driver_data = PLLVAL(150, 2, 2), },
48 { .frequency = 124000000, .index = PLLVAL(116, 1, 2), }, 48 { .frequency = 124000000, .driver_data = PLLVAL(116, 1, 2), },
49 { .frequency = 135000000, .index = PLLVAL(82, 2, 1), }, 49 { .frequency = 135000000, .driver_data = PLLVAL(82, 2, 1), },
50 { .frequency = 147000000, .index = PLLVAL(90, 2, 1), }, 50 { .frequency = 147000000, .driver_data = PLLVAL(90, 2, 1), },
51 { .frequency = 152000000, .index = PLLVAL(68, 1, 1), }, 51 { .frequency = 152000000, .driver_data = PLLVAL(68, 1, 1), },
52 { .frequency = 158000000, .index = PLLVAL(71, 1, 1), }, 52 { .frequency = 158000000, .driver_data = PLLVAL(71, 1, 1), },
53 { .frequency = 170000000, .index = PLLVAL(77, 1, 1), }, 53 { .frequency = 170000000, .driver_data = PLLVAL(77, 1, 1), },
54 { .frequency = 180000000, .index = PLLVAL(82, 1, 1), }, 54 { .frequency = 180000000, .driver_data = PLLVAL(82, 1, 1), },
55 { .frequency = 186000000, .index = PLLVAL(85, 1, 1), }, 55 { .frequency = 186000000, .driver_data = PLLVAL(85, 1, 1), },
56 { .frequency = 192000000, .index = PLLVAL(88, 1, 1), }, 56 { .frequency = 192000000, .driver_data = PLLVAL(88, 1, 1), },
57 { .frequency = 203000000, .index = PLLVAL(161, 3, 1), }, 57 { .frequency = 203000000, .driver_data = PLLVAL(161, 3, 1), },
58 58
59 /* 2410A extras */ 59 /* 2410A extras */
60 60
61 { .frequency = 210000000, .index = PLLVAL(132, 2, 1), }, 61 { .frequency = 210000000, .driver_data = PLLVAL(132, 2, 1), },
62 { .frequency = 226000000, .index = PLLVAL(105, 1, 1), }, 62 { .frequency = 226000000, .driver_data = PLLVAL(105, 1, 1), },
63 { .frequency = 266000000, .index = PLLVAL(125, 1, 1), }, 63 { .frequency = 266000000, .driver_data = PLLVAL(125, 1, 1), },
64 { .frequency = 268000000, .index = PLLVAL(126, 1, 1), }, 64 { .frequency = 268000000, .driver_data = PLLVAL(126, 1, 1), },
65 { .frequency = 270000000, .index = PLLVAL(127, 1, 1), }, 65 { .frequency = 270000000, .driver_data = PLLVAL(127, 1, 1), },
66}; 66};
67 67
68static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif) 68static int s3c2410_plls_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
index 673781758319..a19460e6e7b0 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c
@@ -21,33 +21,33 @@
21#include <plat/cpu-freq-core.h> 21#include <plat/cpu-freq-core.h>
22 22
23static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = { 23static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
24 { .frequency = 75000000, .index = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */ 24 { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
25 { .frequency = 80000000, .index = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */ 25 { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
26 { .frequency = 90000000, .index = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */ 26 { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
27 { .frequency = 100000000, .index = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */ 27 { .frequency = 100000000, .driver_data = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
28 { .frequency = 110000000, .index = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */ 28 { .frequency = 110000000, .driver_data = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
29 { .frequency = 120000000, .index = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */ 29 { .frequency = 120000000, .driver_data = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
30 { .frequency = 150000000, .index = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */ 30 { .frequency = 150000000, .driver_data = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
31 { .frequency = 160000000, .index = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */ 31 { .frequency = 160000000, .driver_data = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
32 { .frequency = 170000000, .index = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */ 32 { .frequency = 170000000, .driver_data = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
33 { .frequency = 180000000, .index = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */ 33 { .frequency = 180000000, .driver_data = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
34 { .frequency = 190000000, .index = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */ 34 { .frequency = 190000000, .driver_data = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
35 { .frequency = 200000000, .index = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */ 35 { .frequency = 200000000, .driver_data = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
36 { .frequency = 210000000, .index = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */ 36 { .frequency = 210000000, .driver_data = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
37 { .frequency = 220000000, .index = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */ 37 { .frequency = 220000000, .driver_data = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
38 { .frequency = 230000000, .index = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */ 38 { .frequency = 230000000, .driver_data = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
39 { .frequency = 240000000, .index = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */ 39 { .frequency = 240000000, .driver_data = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
40 { .frequency = 300000000, .index = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */ 40 { .frequency = 300000000, .driver_data = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
41 { .frequency = 310000000, .index = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */ 41 { .frequency = 310000000, .driver_data = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
42 { .frequency = 320000000, .index = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */ 42 { .frequency = 320000000, .driver_data = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
43 { .frequency = 330000000, .index = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */ 43 { .frequency = 330000000, .driver_data = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
44 { .frequency = 340000000, .index = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */ 44 { .frequency = 340000000, .driver_data = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
45 { .frequency = 350000000, .index = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */ 45 { .frequency = 350000000, .driver_data = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
46 { .frequency = 360000000, .index = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */ 46 { .frequency = 360000000, .driver_data = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
47 { .frequency = 370000000, .index = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */ 47 { .frequency = 370000000, .driver_data = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
48 { .frequency = 380000000, .index = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */ 48 { .frequency = 380000000, .driver_data = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
49 { .frequency = 390000000, .index = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */ 49 { .frequency = 390000000, .driver_data = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
50 { .frequency = 400000000, .index = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */ 50 { .frequency = 400000000, .driver_data = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
51}; 51};
52 52
53static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif) 53static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
diff --git a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
index debfa106289b..1191b2905625 100644
--- a/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
+++ b/arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c
@@ -21,61 +21,61 @@
21#include <plat/cpu-freq-core.h> 21#include <plat/cpu-freq-core.h>
22 22
23static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = { 23static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
24 { .frequency = 78019200, .index = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */ 24 { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), }, /* FVco 624.153600 */
25 { .frequency = 84067200, .index = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */ 25 { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), }, /* FVco 672.537600 */
26 { .frequency = 90115200, .index = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */ 26 { .frequency = 90115200, .driver_data = PLLVAL(141, 5, 3), }, /* FVco 720.921600 */
27 { .frequency = 96163200, .index = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */ 27 { .frequency = 96163200, .driver_data = PLLVAL(151, 5, 3), }, /* FVco 769.305600 */
28 { .frequency = 102135600, .index = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */ 28 { .frequency = 102135600, .driver_data = PLLVAL(185, 6, 3), }, /* FVco 817.084800 */
29 { .frequency = 108259200, .index = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */ 29 { .frequency = 108259200, .driver_data = PLLVAL(171, 5, 3), }, /* FVco 866.073600 */
30 { .frequency = 114307200, .index = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */ 30 { .frequency = 114307200, .driver_data = PLLVAL(127, 3, 3), }, /* FVco 914.457600 */
31 { .frequency = 120234240, .index = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */ 31 { .frequency = 120234240, .driver_data = PLLVAL(134, 3, 3), }, /* FVco 961.873920 */
32 { .frequency = 126161280, .index = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */ 32 { .frequency = 126161280, .driver_data = PLLVAL(141, 3, 3), }, /* FVco 1009.290240 */
33 { .frequency = 132088320, .index = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */ 33 { .frequency = 132088320, .driver_data = PLLVAL(148, 3, 3), }, /* FVco 1056.706560 */
34 { .frequency = 138015360, .index = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */ 34 { .frequency = 138015360, .driver_data = PLLVAL(155, 3, 3), }, /* FVco 1104.122880 */
35 { .frequency = 144789120, .index = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */ 35 { .frequency = 144789120, .driver_data = PLLVAL(163, 3, 3), }, /* FVco 1158.312960 */
36 { .frequency = 150100363, .index = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */ 36 { .frequency = 150100363, .driver_data = PLLVAL(187, 9, 2), }, /* FVco 600.401454 */
37 { .frequency = 156038400, .index = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */ 37 { .frequency = 156038400, .driver_data = PLLVAL(121, 5, 2), }, /* FVco 624.153600 */
38 { .frequency = 162086400, .index = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */ 38 { .frequency = 162086400, .driver_data = PLLVAL(126, 5, 2), }, /* FVco 648.345600 */
39 { .frequency = 168134400, .index = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */ 39 { .frequency = 168134400, .driver_data = PLLVAL(131, 5, 2), }, /* FVco 672.537600 */
40 { .frequency = 174048000, .index = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */ 40 { .frequency = 174048000, .driver_data = PLLVAL(177, 7, 2), }, /* FVco 696.192000 */
41 { .frequency = 180230400, .index = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */ 41 { .frequency = 180230400, .driver_data = PLLVAL(141, 5, 2), }, /* FVco 720.921600 */
42 { .frequency = 186278400, .index = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */ 42 { .frequency = 186278400, .driver_data = PLLVAL(124, 4, 2), }, /* FVco 745.113600 */
43 { .frequency = 192326400, .index = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */ 43 { .frequency = 192326400, .driver_data = PLLVAL(151, 5, 2), }, /* FVco 769.305600 */
44 { .frequency = 198132480, .index = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */ 44 { .frequency = 198132480, .driver_data = PLLVAL(109, 3, 2), }, /* FVco 792.529920 */
45 { .frequency = 204271200, .index = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */ 45 { .frequency = 204271200, .driver_data = PLLVAL(185, 6, 2), }, /* FVco 817.084800 */
46 { .frequency = 210268800, .index = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */ 46 { .frequency = 210268800, .driver_data = PLLVAL(141, 4, 2), }, /* FVco 841.075200 */
47 { .frequency = 216518400, .index = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */ 47 { .frequency = 216518400, .driver_data = PLLVAL(171, 5, 2), }, /* FVco 866.073600 */
48 { .frequency = 222264000, .index = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */ 48 { .frequency = 222264000, .driver_data = PLLVAL(97, 2, 2), }, /* FVco 889.056000 */
49 { .frequency = 228614400, .index = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */ 49 { .frequency = 228614400, .driver_data = PLLVAL(127, 3, 2), }, /* FVco 914.457600 */
50 { .frequency = 234259200, .index = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */ 50 { .frequency = 234259200, .driver_data = PLLVAL(158, 4, 2), }, /* FVco 937.036800 */
51 { .frequency = 240468480, .index = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */ 51 { .frequency = 240468480, .driver_data = PLLVAL(134, 3, 2), }, /* FVco 961.873920 */
52 { .frequency = 246960000, .index = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */ 52 { .frequency = 246960000, .driver_data = PLLVAL(167, 4, 2), }, /* FVco 987.840000 */
53 { .frequency = 252322560, .index = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */ 53 { .frequency = 252322560, .driver_data = PLLVAL(141, 3, 2), }, /* FVco 1009.290240 */
54 { .frequency = 258249600, .index = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */ 54 { .frequency = 258249600, .driver_data = PLLVAL(114, 2, 2), }, /* FVco 1032.998400 */
55 { .frequency = 264176640, .index = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */ 55 { .frequency = 264176640, .driver_data = PLLVAL(148, 3, 2), }, /* FVco 1056.706560 */
56 { .frequency = 270950400, .index = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */ 56 { .frequency = 270950400, .driver_data = PLLVAL(120, 2, 2), }, /* FVco 1083.801600 */
57 { .frequency = 276030720, .index = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */ 57 { .frequency = 276030720, .driver_data = PLLVAL(155, 3, 2), }, /* FVco 1104.122880 */
58 { .frequency = 282240000, .index = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */ 58 { .frequency = 282240000, .driver_data = PLLVAL(92, 1, 2), }, /* FVco 1128.960000 */
59 { .frequency = 289578240, .index = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */ 59 { .frequency = 289578240, .driver_data = PLLVAL(163, 3, 2), }, /* FVco 1158.312960 */
60 { .frequency = 294235200, .index = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */ 60 { .frequency = 294235200, .driver_data = PLLVAL(131, 2, 2), }, /* FVco 1176.940800 */
61 { .frequency = 300200727, .index = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */ 61 { .frequency = 300200727, .driver_data = PLLVAL(187, 9, 1), }, /* FVco 600.401454 */
62 { .frequency = 306358690, .index = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */ 62 { .frequency = 306358690, .driver_data = PLLVAL(191, 9, 1), }, /* FVco 612.717380 */
63 { .frequency = 312076800, .index = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */ 63 { .frequency = 312076800, .driver_data = PLLVAL(121, 5, 1), }, /* FVco 624.153600 */
64 { .frequency = 318366720, .index = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */ 64 { .frequency = 318366720, .driver_data = PLLVAL(86, 3, 1), }, /* FVco 636.733440 */
65 { .frequency = 324172800, .index = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */ 65 { .frequency = 324172800, .driver_data = PLLVAL(126, 5, 1), }, /* FVco 648.345600 */
66 { .frequency = 330220800, .index = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */ 66 { .frequency = 330220800, .driver_data = PLLVAL(109, 4, 1), }, /* FVco 660.441600 */
67 { .frequency = 336268800, .index = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */ 67 { .frequency = 336268800, .driver_data = PLLVAL(131, 5, 1), }, /* FVco 672.537600 */
68 { .frequency = 342074880, .index = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */ 68 { .frequency = 342074880, .driver_data = PLLVAL(93, 3, 1), }, /* FVco 684.149760 */
69 { .frequency = 348096000, .index = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */ 69 { .frequency = 348096000, .driver_data = PLLVAL(177, 7, 1), }, /* FVco 696.192000 */
70 { .frequency = 355622400, .index = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */ 70 { .frequency = 355622400, .driver_data = PLLVAL(118, 4, 1), }, /* FVco 711.244800 */
71 { .frequency = 360460800, .index = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */ 71 { .frequency = 360460800, .driver_data = PLLVAL(141, 5, 1), }, /* FVco 720.921600 */
72 { .frequency = 366206400, .index = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */ 72 { .frequency = 366206400, .driver_data = PLLVAL(165, 6, 1), }, /* FVco 732.412800 */
73 { .frequency = 372556800, .index = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */ 73 { .frequency = 372556800, .driver_data = PLLVAL(124, 4, 1), }, /* FVco 745.113600 */
74 { .frequency = 378201600, .index = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */ 74 { .frequency = 378201600, .driver_data = PLLVAL(126, 4, 1), }, /* FVco 756.403200 */
75 { .frequency = 384652800, .index = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */ 75 { .frequency = 384652800, .driver_data = PLLVAL(151, 5, 1), }, /* FVco 769.305600 */
76 { .frequency = 391608000, .index = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */ 76 { .frequency = 391608000, .driver_data = PLLVAL(177, 6, 1), }, /* FVco 783.216000 */
77 { .frequency = 396264960, .index = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */ 77 { .frequency = 396264960, .driver_data = PLLVAL(109, 3, 1), }, /* FVco 792.529920 */
78 { .frequency = 402192000, .index = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */ 78 { .frequency = 402192000, .driver_data = PLLVAL(87, 2, 1), }, /* FVco 804.384000 */
79}; 79};
80 80
81static int s3c2440_plls169344_add(struct device *dev, 81static int s3c2440_plls169344_add(struct device *dev,
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7e105932c09d..5390c6bbbc02 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -142,15 +142,15 @@ static void pllc2_table_rebuild(struct clk *clk)
142 /* Initialise PLLC2 frequency table */ 142 /* Initialise PLLC2 frequency table */
143 for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) { 143 for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
144 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2; 144 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
145 pllc2_freq_table[i].index = i; 145 pllc2_freq_table[i].driver_data = i;
146 } 146 }
147 147
148 /* This is a special entry - switching PLL off makes it a repeater */ 148 /* This is a special entry - switching PLL off makes it a repeater */
149 pllc2_freq_table[i].frequency = clk->parent->rate; 149 pllc2_freq_table[i].frequency = clk->parent->rate;
150 pllc2_freq_table[i].index = i; 150 pllc2_freq_table[i].driver_data = i;
151 151
152 pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END; 152 pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
153 pllc2_freq_table[i].index = i; 153 pllc2_freq_table[i].driver_data = i;
154} 154}
155 155
156static unsigned long pllc2_recalc(struct clk *clk) 156static unsigned long pllc2_recalc(struct clk *clk)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 84d72fc36dfe..5c0db065baa4 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -28,7 +28,6 @@ config ARCH_TEGRA_2x_SOC
28 select ARM_ERRATA_754327 if SMP 28 select ARM_ERRATA_754327 if SMP
29 select ARM_ERRATA_764369 if SMP 29 select ARM_ERRATA_764369 if SMP
30 select ARM_GIC 30 select ARM_GIC
31 select CPU_FREQ_TABLE if CPU_FREQ
32 select CPU_V7 31 select CPU_V7
33 select PINCTRL 32 select PINCTRL
34 select PINCTRL_TEGRA20 33 select PINCTRL_TEGRA20
@@ -46,7 +45,6 @@ config ARCH_TEGRA_3x_SOC
46 select ARM_ERRATA_754322 45 select ARM_ERRATA_754322
47 select ARM_ERRATA_764369 if SMP 46 select ARM_ERRATA_764369 if SMP
48 select ARM_GIC 47 select ARM_GIC
49 select CPU_FREQ_TABLE if CPU_FREQ
50 select CPU_V7 48 select CPU_V7
51 select PINCTRL 49 select PINCTRL
52 select PINCTRL_TEGRA30 50 select PINCTRL_TEGRA30
@@ -63,7 +61,6 @@ config ARCH_TEGRA_114_SOC
63 select ARM_ARCH_TIMER 61 select ARM_ARCH_TIMER
64 select ARM_GIC 62 select ARM_GIC
65 select ARM_L1_CACHE_SHIFT_6 63 select ARM_L1_CACHE_SHIFT_6
66 select CPU_FREQ_TABLE if CPU_FREQ
67 select CPU_V7 64 select CPU_V7
68 select PINCTRL 65 select PINCTRL
69 select PINCTRL_TEGRA114 66 select PINCTRL_TEGRA114
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 95509d8eb140..a8a760ddfae1 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -285,7 +285,7 @@ static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
285 s3c_freq_dbg("%s: { %d = %u kHz }\n", 285 s3c_freq_dbg("%s: { %d = %u kHz }\n",
286 __func__, index, freq); 286 __func__, index, freq);
287 287
288 table[index].index = index; 288 table[index].driver_data = index;
289 table[index].frequency = freq; 289 table[index].frequency = freq;
290 } 290 }
291 291
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 8769a9045a54..5f7530cc9a27 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -134,11 +134,13 @@ config SVINTO_SIM
134 134
135config ETRAXFS 135config ETRAXFS
136 bool "ETRAX-FS-V32" 136 bool "ETRAX-FS-V32"
137 select CPU_FREQ_TABLE if CPU_FREQ
137 help 138 help
138 Support CRIS V32. 139 Support CRIS V32.
139 140
140config CRIS_MACH_ARTPEC3 141config CRIS_MACH_ARTPEC3
141 bool "ARTPEC-3" 142 bool "ARTPEC-3"
143 select CPU_FREQ_TABLE if CPU_FREQ
142 help 144 help
143 Support Axis ARTPEC-3. 145 Support Axis ARTPEC-3.
144 146
diff --git a/arch/mips/loongson/lemote-2f/clock.c b/arch/mips/loongson/lemote-2f/clock.c
index bc739d4bab2e..4dc2f5fa3f67 100644
--- a/arch/mips/loongson/lemote-2f/clock.c
+++ b/arch/mips/loongson/lemote-2f/clock.c
@@ -121,7 +121,8 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
121 clk->rate = rate; 121 clk->rate = rate;
122 122
123 regval = LOONGSON_CHIPCFG0; 123 regval = LOONGSON_CHIPCFG0;
124 regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1); 124 regval = (regval & ~0x7) |
125 (loongson2_clockmod_table[i].driver_data - 1);
125 LOONGSON_CHIPCFG0 = regval; 126 LOONGSON_CHIPCFG0 = regval;
126 127
127 return ret; 128 return ret;
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index b62aab3e22ec..e17cdfc5ba40 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -193,37 +193,6 @@ config PPC_IO_WORKAROUNDS
193 193
194source "drivers/cpufreq/Kconfig" 194source "drivers/cpufreq/Kconfig"
195 195
196menu "CPU Frequency drivers"
197 depends on CPU_FREQ
198
199config CPU_FREQ_PMAC
200 bool "Support for Apple PowerBooks"
201 depends on ADB_PMU && PPC32
202 select CPU_FREQ_TABLE
203 help
204 This adds support for frequency switching on Apple PowerBooks,
205 this currently includes some models of iBook & Titanium
206 PowerBook.
207
208config CPU_FREQ_PMAC64
209 bool "Support for some Apple G5s"
210 depends on PPC_PMAC && PPC64
211 select CPU_FREQ_TABLE
212 help
213 This adds support for frequency switching on Apple iMac G5,
214 and some of the more recent desktop G5 machines as well.
215
216config PPC_PASEMI_CPUFREQ
217 bool "Support for PA Semi PWRficient"
218 depends on PPC_PASEMI
219 default y
220 select CPU_FREQ_TABLE
221 help
222 This adds the support for frequency switching on PA Semi
223 PWRficient processors.
224
225endmenu
226
227menu "CPUIdle driver" 196menu "CPUIdle driver"
228 197
229source "drivers/cpuidle/Kconfig" 198source "drivers/cpuidle/Kconfig"
diff --git a/arch/powerpc/platforms/pasemi/Makefile b/arch/powerpc/platforms/pasemi/Makefile
index ce6d789e0741..8e8d4cae5ebe 100644
--- a/arch/powerpc/platforms/pasemi/Makefile
+++ b/arch/powerpc/platforms/pasemi/Makefile
@@ -1,3 +1,2 @@
1obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o dma_lib.o misc.o 1obj-y += setup.o pci.o time.o idle.o powersave.o iommu.o dma_lib.o misc.o
2obj-$(CONFIG_PPC_PASEMI_MDIO) += gpio_mdio.o 2obj-$(CONFIG_PPC_PASEMI_MDIO) += gpio_mdio.o
3obj-$(CONFIG_PPC_PASEMI_CPUFREQ) += cpufreq.o
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
deleted file mode 100644
index be1e7958909e..000000000000
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ /dev/null
@@ -1,330 +0,0 @@
1/*
2 * Copyright (C) 2007 PA Semi, Inc
3 *
4 * Authors: Egor Martovetsky <egor@pasemi.com>
5 * Olof Johansson <olof@lixom.net>
6 *
7 * Maintained by: Olof Johansson <olof@lixom.net>
8 *
9 * Based on arch/powerpc/platforms/cell/cbe_cpufreq.c:
10 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28#include <linux/cpufreq.h>
29#include <linux/timer.h>
30#include <linux/module.h>
31
32#include <asm/hw_irq.h>
33#include <asm/io.h>
34#include <asm/prom.h>
35#include <asm/time.h>
36#include <asm/smp.h>
37
38#define SDCASR_REG 0x0100
39#define SDCASR_REG_STRIDE 0x1000
40#define SDCPWR_CFGA0_REG 0x0100
41#define SDCPWR_PWST0_REG 0x0000
42#define SDCPWR_GIZTIME_REG 0x0440
43
44/* SDCPWR_GIZTIME_REG fields */
45#define SDCPWR_GIZTIME_GR 0x80000000
46#define SDCPWR_GIZTIME_LONGLOCK 0x000000ff
47
48/* Offset of ASR registers from SDC base */
49#define SDCASR_OFFSET 0x120000
50
51static void __iomem *sdcpwr_mapbase;
52static void __iomem *sdcasr_mapbase;
53
54static DEFINE_MUTEX(pas_switch_mutex);
55
56/* Current astate, is used when waking up from power savings on
57 * one core, in case the other core has switched states during
58 * the idle time.
59 */
60static int current_astate;
61
62/* We support 5(A0-A4) power states excluding turbo(A5-A6) modes */
63static struct cpufreq_frequency_table pas_freqs[] = {
64 {0, 0},
65 {1, 0},
66 {2, 0},
67 {3, 0},
68 {4, 0},
69 {0, CPUFREQ_TABLE_END},
70};
71
72static struct freq_attr *pas_cpu_freqs_attr[] = {
73 &cpufreq_freq_attr_scaling_available_freqs,
74 NULL,
75};
76
77/*
78 * hardware specific functions
79 */
80
81static int get_astate_freq(int astate)
82{
83 u32 ret;
84 ret = in_le32(sdcpwr_mapbase + SDCPWR_CFGA0_REG + (astate * 0x10));
85
86 return ret & 0x3f;
87}
88
89static int get_cur_astate(int cpu)
90{
91 u32 ret;
92
93 ret = in_le32(sdcpwr_mapbase + SDCPWR_PWST0_REG);
94 ret = (ret >> (cpu * 4)) & 0x7;
95
96 return ret;
97}
98
99static int get_gizmo_latency(void)
100{
101 u32 giztime, ret;
102
103 giztime = in_le32(sdcpwr_mapbase + SDCPWR_GIZTIME_REG);
104
105 /* just provide the upper bound */
106 if (giztime & SDCPWR_GIZTIME_GR)
107 ret = (giztime & SDCPWR_GIZTIME_LONGLOCK) * 128000;
108 else
109 ret = (giztime & SDCPWR_GIZTIME_LONGLOCK) * 1000;
110
111 return ret;
112}
113
114static void set_astate(int cpu, unsigned int astate)
115{
116 unsigned long flags;
117
118 /* Return if called before init has run */
119 if (unlikely(!sdcasr_mapbase))
120 return;
121
122 local_irq_save(flags);
123
124 out_le32(sdcasr_mapbase + SDCASR_REG + SDCASR_REG_STRIDE*cpu, astate);
125
126 local_irq_restore(flags);
127}
128
129int check_astate(void)
130{
131 return get_cur_astate(hard_smp_processor_id());
132}
133
134void restore_astate(int cpu)
135{
136 set_astate(cpu, current_astate);
137}
138
139/*
140 * cpufreq functions
141 */
142
143static int pas_cpufreq_cpu_init(struct cpufreq_policy *policy)
144{
145 const u32 *max_freqp;
146 u32 max_freq;
147 int i, cur_astate;
148 struct resource res;
149 struct device_node *cpu, *dn;
150 int err = -ENODEV;
151
152 cpu = of_get_cpu_node(policy->cpu, NULL);
153
154 if (!cpu)
155 goto out;
156
157 dn = of_find_compatible_node(NULL, NULL, "1682m-sdc");
158 if (!dn)
159 dn = of_find_compatible_node(NULL, NULL,
160 "pasemi,pwrficient-sdc");
161 if (!dn)
162 goto out;
163 err = of_address_to_resource(dn, 0, &res);
164 of_node_put(dn);
165 if (err)
166 goto out;
167 sdcasr_mapbase = ioremap(res.start + SDCASR_OFFSET, 0x2000);
168 if (!sdcasr_mapbase) {
169 err = -EINVAL;
170 goto out;
171 }
172
173 dn = of_find_compatible_node(NULL, NULL, "1682m-gizmo");
174 if (!dn)
175 dn = of_find_compatible_node(NULL, NULL,
176 "pasemi,pwrficient-gizmo");
177 if (!dn) {
178 err = -ENODEV;
179 goto out_unmap_sdcasr;
180 }
181 err = of_address_to_resource(dn, 0, &res);
182 of_node_put(dn);
183 if (err)
184 goto out_unmap_sdcasr;
185 sdcpwr_mapbase = ioremap(res.start, 0x1000);
186 if (!sdcpwr_mapbase) {
187 err = -EINVAL;
188 goto out_unmap_sdcasr;
189 }
190
191 pr_debug("init cpufreq on CPU %d\n", policy->cpu);
192
193 max_freqp = of_get_property(cpu, "clock-frequency", NULL);
194 if (!max_freqp) {
195 err = -EINVAL;
196 goto out_unmap_sdcpwr;
197 }
198
199 /* we need the freq in kHz */
200 max_freq = *max_freqp / 1000;
201
202 pr_debug("max clock-frequency is at %u kHz\n", max_freq);
203 pr_debug("initializing frequency table\n");
204
205 /* initialize frequency table */
206 for (i=0; pas_freqs[i].frequency!=CPUFREQ_TABLE_END; i++) {
207 pas_freqs[i].frequency = get_astate_freq(pas_freqs[i].index) * 100000;
208 pr_debug("%d: %d\n", i, pas_freqs[i].frequency);
209 }
210
211 policy->cpuinfo.transition_latency = get_gizmo_latency();
212
213 cur_astate = get_cur_astate(policy->cpu);
214 pr_debug("current astate is at %d\n",cur_astate);
215
216 policy->cur = pas_freqs[cur_astate].frequency;
217 cpumask_copy(policy->cpus, cpu_online_mask);
218
219 ppc_proc_freq = policy->cur * 1000ul;
220
221 cpufreq_frequency_table_get_attr(pas_freqs, policy->cpu);
222
223 /* this ensures that policy->cpuinfo_min and policy->cpuinfo_max
224 * are set correctly
225 */
226 return cpufreq_frequency_table_cpuinfo(policy, pas_freqs);
227
228out_unmap_sdcpwr:
229 iounmap(sdcpwr_mapbase);
230
231out_unmap_sdcasr:
232 iounmap(sdcasr_mapbase);
233out:
234 return err;
235}
236
237static int pas_cpufreq_cpu_exit(struct cpufreq_policy *policy)
238{
239 /*
240 * We don't support CPU hotplug. Don't unmap after the system
241 * has already made it to a running state.
242 */
243 if (system_state != SYSTEM_BOOTING)
244 return 0;
245
246 if (sdcasr_mapbase)
247 iounmap(sdcasr_mapbase);
248 if (sdcpwr_mapbase)
249 iounmap(sdcpwr_mapbase);
250
251 cpufreq_frequency_table_put_attr(policy->cpu);
252 return 0;
253}
254
255static int pas_cpufreq_verify(struct cpufreq_policy *policy)
256{
257 return cpufreq_frequency_table_verify(policy, pas_freqs);
258}
259
260static int pas_cpufreq_target(struct cpufreq_policy *policy,
261 unsigned int target_freq,
262 unsigned int relation)
263{
264 struct cpufreq_freqs freqs;
265 int pas_astate_new;
266 int i;
267
268 cpufreq_frequency_table_target(policy,
269 pas_freqs,
270 target_freq,
271 relation,
272 &pas_astate_new);
273
274 freqs.old = policy->cur;
275 freqs.new = pas_freqs[pas_astate_new].frequency;
276
277 mutex_lock(&pas_switch_mutex);
278 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
279
280 pr_debug("setting frequency for cpu %d to %d kHz, 1/%d of max frequency\n",
281 policy->cpu,
282 pas_freqs[pas_astate_new].frequency,
283 pas_freqs[pas_astate_new].index);
284
285 current_astate = pas_astate_new;
286
287 for_each_online_cpu(i)
288 set_astate(i, pas_astate_new);
289
290 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
291 mutex_unlock(&pas_switch_mutex);
292
293 ppc_proc_freq = freqs.new * 1000ul;
294 return 0;
295}
296
297static struct cpufreq_driver pas_cpufreq_driver = {
298 .name = "pas-cpufreq",
299 .owner = THIS_MODULE,
300 .flags = CPUFREQ_CONST_LOOPS,
301 .init = pas_cpufreq_cpu_init,
302 .exit = pas_cpufreq_cpu_exit,
303 .verify = pas_cpufreq_verify,
304 .target = pas_cpufreq_target,
305 .attr = pas_cpu_freqs_attr,
306};
307
308/*
309 * module init and destoy
310 */
311
312static int __init pas_cpufreq_init(void)
313{
314 if (!of_machine_is_compatible("PA6T-1682M") &&
315 !of_machine_is_compatible("pasemi,pwrficient"))
316 return -ENODEV;
317
318 return cpufreq_register_driver(&pas_cpufreq_driver);
319}
320
321static void __exit pas_cpufreq_exit(void)
322{
323 cpufreq_unregister_driver(&pas_cpufreq_driver);
324}
325
326module_init(pas_cpufreq_init);
327module_exit(pas_cpufreq_exit);
328
329MODULE_LICENSE("GPL");
330MODULE_AUTHOR("Egor Martovetsky <egor@pasemi.com>, Olof Johansson <olof@lixom.net>");
diff --git a/arch/powerpc/platforms/powermac/Makefile b/arch/powerpc/platforms/powermac/Makefile
index ea47df66fee5..52c6ce1cc985 100644
--- a/arch/powerpc/platforms/powermac/Makefile
+++ b/arch/powerpc/platforms/powermac/Makefile
@@ -9,8 +9,6 @@ obj-y += pic.o setup.o time.o feature.o pci.o \
9 sleep.o low_i2c.o cache.o pfunc_core.o \ 9 sleep.o low_i2c.o cache.o pfunc_core.o \
10 pfunc_base.o udbg_scc.o udbg_adb.o 10 pfunc_base.o udbg_scc.o udbg_adb.o
11obj-$(CONFIG_PMAC_BACKLIGHT) += backlight.o 11obj-$(CONFIG_PMAC_BACKLIGHT) += backlight.o
12obj-$(CONFIG_CPU_FREQ_PMAC) += cpufreq_32.o
13obj-$(CONFIG_CPU_FREQ_PMAC64) += cpufreq_64.o
14# CONFIG_NVRAM is an arch. independent tristate symbol, for pmac32 we really 12# CONFIG_NVRAM is an arch. independent tristate symbol, for pmac32 we really
15# need this to be a bool. Cheat here and pretend CONFIG_NVRAM=m is really 13# need this to be a bool. Cheat here and pretend CONFIG_NVRAM=m is really
16# CONFIG_NVRAM=y 14# CONFIG_NVRAM=y
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
deleted file mode 100644
index 3104fad82480..000000000000
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ /dev/null
@@ -1,721 +0,0 @@
1/*
2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 * Copyright (C) 2004 John Steele Scott <toojays@toojays.net>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * TODO: Need a big cleanup here. Basically, we need to have different
10 * cpufreq_driver structures for the different type of HW instead of the
11 * current mess. We also need to better deal with the detection of the
12 * type of machine.
13 *
14 */
15
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/sched.h>
22#include <linux/adb.h>
23#include <linux/pmu.h>
24#include <linux/cpufreq.h>
25#include <linux/init.h>
26#include <linux/device.h>
27#include <linux/hardirq.h>
28#include <asm/prom.h>
29#include <asm/machdep.h>
30#include <asm/irq.h>
31#include <asm/pmac_feature.h>
32#include <asm/mmu_context.h>
33#include <asm/sections.h>
34#include <asm/cputable.h>
35#include <asm/time.h>
36#include <asm/mpic.h>
37#include <asm/keylargo.h>
38#include <asm/switch_to.h>
39
40/* WARNING !!! This will cause calibrate_delay() to be called,
41 * but this is an __init function ! So you MUST go edit
42 * init/main.c to make it non-init before enabling DEBUG_FREQ
43 */
44#undef DEBUG_FREQ
45
46extern void low_choose_7447a_dfs(int dfs);
47extern void low_choose_750fx_pll(int pll);
48extern void low_sleep_handler(void);
49
50/*
51 * Currently, PowerMac cpufreq supports only high & low frequencies
52 * that are set by the firmware
53 */
54static unsigned int low_freq;
55static unsigned int hi_freq;
56static unsigned int cur_freq;
57static unsigned int sleep_freq;
58static unsigned long transition_latency;
59
60/*
61 * Different models uses different mechanisms to switch the frequency
62 */
63static int (*set_speed_proc)(int low_speed);
64static unsigned int (*get_speed_proc)(void);
65
66/*
67 * Some definitions used by the various speedprocs
68 */
69static u32 voltage_gpio;
70static u32 frequency_gpio;
71static u32 slew_done_gpio;
72static int no_schedule;
73static int has_cpu_l2lve;
74static int is_pmu_based;
75
76/* There are only two frequency states for each processor. Values
77 * are in kHz for the time being.
78 */
79#define CPUFREQ_HIGH 0
80#define CPUFREQ_LOW 1
81
82static struct cpufreq_frequency_table pmac_cpu_freqs[] = {
83 {CPUFREQ_HIGH, 0},
84 {CPUFREQ_LOW, 0},
85 {0, CPUFREQ_TABLE_END},
86};
87
88static struct freq_attr* pmac_cpu_freqs_attr[] = {
89 &cpufreq_freq_attr_scaling_available_freqs,
90 NULL,
91};
92
93static inline void local_delay(unsigned long ms)
94{
95 if (no_schedule)
96 mdelay(ms);
97 else
98 msleep(ms);
99}
100
101#ifdef DEBUG_FREQ
102static inline void debug_calc_bogomips(void)
103{
104 /* This will cause a recalc of bogomips and display the
105 * result. We backup/restore the value to avoid affecting the
106 * core cpufreq framework's own calculation.
107 */
108 unsigned long save_lpj = loops_per_jiffy;
109 calibrate_delay();
110 loops_per_jiffy = save_lpj;
111}
112#endif /* DEBUG_FREQ */
113
114/* Switch CPU speed under 750FX CPU control
115 */
116static int cpu_750fx_cpu_speed(int low_speed)
117{
118 u32 hid2;
119
120 if (low_speed == 0) {
121 /* ramping up, set voltage first */
122 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
123 /* Make sure we sleep for at least 1ms */
124 local_delay(10);
125
126 /* tweak L2 for high voltage */
127 if (has_cpu_l2lve) {
128 hid2 = mfspr(SPRN_HID2);
129 hid2 &= ~0x2000;
130 mtspr(SPRN_HID2, hid2);
131 }
132 }
133#ifdef CONFIG_6xx
134 low_choose_750fx_pll(low_speed);
135#endif
136 if (low_speed == 1) {
137 /* tweak L2 for low voltage */
138 if (has_cpu_l2lve) {
139 hid2 = mfspr(SPRN_HID2);
140 hid2 |= 0x2000;
141 mtspr(SPRN_HID2, hid2);
142 }
143
144 /* ramping down, set voltage last */
145 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
146 local_delay(10);
147 }
148
149 return 0;
150}
151
152static unsigned int cpu_750fx_get_cpu_speed(void)
153{
154 if (mfspr(SPRN_HID1) & HID1_PS)
155 return low_freq;
156 else
157 return hi_freq;
158}
159
160/* Switch CPU speed using DFS */
161static int dfs_set_cpu_speed(int low_speed)
162{
163 if (low_speed == 0) {
164 /* ramping up, set voltage first */
165 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
166 /* Make sure we sleep for at least 1ms */
167 local_delay(1);
168 }
169
170 /* set frequency */
171#ifdef CONFIG_6xx
172 low_choose_7447a_dfs(low_speed);
173#endif
174 udelay(100);
175
176 if (low_speed == 1) {
177 /* ramping down, set voltage last */
178 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
179 local_delay(1);
180 }
181
182 return 0;
183}
184
185static unsigned int dfs_get_cpu_speed(void)
186{
187 if (mfspr(SPRN_HID1) & HID1_DFS)
188 return low_freq;
189 else
190 return hi_freq;
191}
192
193
194/* Switch CPU speed using slewing GPIOs
195 */
196static int gpios_set_cpu_speed(int low_speed)
197{
198 int gpio, timeout = 0;
199
200 /* If ramping up, set voltage first */
201 if (low_speed == 0) {
202 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x05);
203 /* Delay is way too big but it's ok, we schedule */
204 local_delay(10);
205 }
206
207 /* Set frequency */
208 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
209 if (low_speed == ((gpio & 0x01) == 0))
210 goto skip;
211
212 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, frequency_gpio,
213 low_speed ? 0x04 : 0x05);
214 udelay(200);
215 do {
216 if (++timeout > 100)
217 break;
218 local_delay(1);
219 gpio = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, slew_done_gpio, 0);
220 } while((gpio & 0x02) == 0);
221 skip:
222 /* If ramping down, set voltage last */
223 if (low_speed == 1) {
224 pmac_call_feature(PMAC_FTR_WRITE_GPIO, NULL, voltage_gpio, 0x04);
225 /* Delay is way too big but it's ok, we schedule */
226 local_delay(10);
227 }
228
229#ifdef DEBUG_FREQ
230 debug_calc_bogomips();
231#endif
232
233 return 0;
234}
235
236/* Switch CPU speed under PMU control
237 */
238static int pmu_set_cpu_speed(int low_speed)
239{
240 struct adb_request req;
241 unsigned long save_l2cr;
242 unsigned long save_l3cr;
243 unsigned int pic_prio;
244 unsigned long flags;
245
246 preempt_disable();
247
248#ifdef DEBUG_FREQ
249 printk(KERN_DEBUG "HID1, before: %x\n", mfspr(SPRN_HID1));
250#endif
251 pmu_suspend();
252
253 /* Disable all interrupt sources on openpic */
254 pic_prio = mpic_cpu_get_priority();
255 mpic_cpu_set_priority(0xf);
256
257 /* Make sure the decrementer won't interrupt us */
258 asm volatile("mtdec %0" : : "r" (0x7fffffff));
259 /* Make sure any pending DEC interrupt occurring while we did
260 * the above didn't re-enable the DEC */
261 mb();
262 asm volatile("mtdec %0" : : "r" (0x7fffffff));
263
264 /* We can now disable MSR_EE */
265 local_irq_save(flags);
266
267 /* Giveup the FPU & vec */
268 enable_kernel_fp();
269
270#ifdef CONFIG_ALTIVEC
271 if (cpu_has_feature(CPU_FTR_ALTIVEC))
272 enable_kernel_altivec();
273#endif /* CONFIG_ALTIVEC */
274
275 /* Save & disable L2 and L3 caches */
276 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */
277 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */
278
279 /* Send the new speed command. My assumption is that this command
280 * will cause PLL_CFG[0..3] to be changed next time CPU goes to sleep
281 */
282 pmu_request(&req, NULL, 6, PMU_CPU_SPEED, 'W', 'O', 'O', 'F', low_speed);
283 while (!req.complete)
284 pmu_poll();
285
286 /* Prepare the northbridge for the speed transition */
287 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,1);
288
289 /* Call low level code to backup CPU state and recover from
290 * hardware reset
291 */
292 low_sleep_handler();
293
294 /* Restore the northbridge */
295 pmac_call_feature(PMAC_FTR_SLEEP_STATE,NULL,1,0);
296
297 /* Restore L2 cache */
298 if (save_l2cr != 0xffffffff && (save_l2cr & L2CR_L2E) != 0)
299 _set_L2CR(save_l2cr);
300 /* Restore L3 cache */
301 if (save_l3cr != 0xffffffff && (save_l3cr & L3CR_L3E) != 0)
302 _set_L3CR(save_l3cr);
303
304 /* Restore userland MMU context */
305 switch_mmu_context(NULL, current->active_mm);
306
307#ifdef DEBUG_FREQ
308 printk(KERN_DEBUG "HID1, after: %x\n", mfspr(SPRN_HID1));
309#endif
310
311 /* Restore low level PMU operations */
312 pmu_unlock();
313
314 /*
315 * Restore decrementer; we'll take a decrementer interrupt
316 * as soon as interrupts are re-enabled and the generic
317 * clockevents code will reprogram it with the right value.
318 */
319 set_dec(1);
320
321 /* Restore interrupts */
322 mpic_cpu_set_priority(pic_prio);
323
324 /* Let interrupts flow again ... */
325 local_irq_restore(flags);
326
327#ifdef DEBUG_FREQ
328 debug_calc_bogomips();
329#endif
330
331 pmu_resume();
332
333 preempt_enable();
334
335 return 0;
336}
337
338static int do_set_cpu_speed(struct cpufreq_policy *policy, int speed_mode,
339 int notify)
340{
341 struct cpufreq_freqs freqs;
342 unsigned long l3cr;
343 static unsigned long prev_l3cr;
344
345 freqs.old = cur_freq;
346 freqs.new = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
347
348 if (freqs.old == freqs.new)
349 return 0;
350
351 if (notify)
352 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
353 if (speed_mode == CPUFREQ_LOW &&
354 cpu_has_feature(CPU_FTR_L3CR)) {
355 l3cr = _get_L3CR();
356 if (l3cr & L3CR_L3E) {
357 prev_l3cr = l3cr;
358 _set_L3CR(0);
359 }
360 }
361 set_speed_proc(speed_mode == CPUFREQ_LOW);
362 if (speed_mode == CPUFREQ_HIGH &&
363 cpu_has_feature(CPU_FTR_L3CR)) {
364 l3cr = _get_L3CR();
365 if ((prev_l3cr & L3CR_L3E) && l3cr != prev_l3cr)
366 _set_L3CR(prev_l3cr);
367 }
368 if (notify)
369 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
370 cur_freq = (speed_mode == CPUFREQ_HIGH) ? hi_freq : low_freq;
371
372 return 0;
373}
374
375static unsigned int pmac_cpufreq_get_speed(unsigned int cpu)
376{
377 return cur_freq;
378}
379
380static int pmac_cpufreq_verify(struct cpufreq_policy *policy)
381{
382 return cpufreq_frequency_table_verify(policy, pmac_cpu_freqs);
383}
384
385static int pmac_cpufreq_target( struct cpufreq_policy *policy,
386 unsigned int target_freq,
387 unsigned int relation)
388{
389 unsigned int newstate = 0;
390 int rc;
391
392 if (cpufreq_frequency_table_target(policy, pmac_cpu_freqs,
393 target_freq, relation, &newstate))
394 return -EINVAL;
395
396 rc = do_set_cpu_speed(policy, newstate, 1);
397
398 ppc_proc_freq = cur_freq * 1000ul;
399 return rc;
400}
401
402static int pmac_cpufreq_cpu_init(struct cpufreq_policy *policy)
403{
404 if (policy->cpu != 0)
405 return -ENODEV;
406
407 policy->cpuinfo.transition_latency = transition_latency;
408 policy->cur = cur_freq;
409
410 cpufreq_frequency_table_get_attr(pmac_cpu_freqs, policy->cpu);
411 return cpufreq_frequency_table_cpuinfo(policy, pmac_cpu_freqs);
412}
413
414static u32 read_gpio(struct device_node *np)
415{
416 const u32 *reg = of_get_property(np, "reg", NULL);
417 u32 offset;
418
419 if (reg == NULL)
420 return 0;
421 /* That works for all keylargos but shall be fixed properly
422 * some day... The problem is that it seems we can't rely
423 * on the "reg" property of the GPIO nodes, they are either
424 * relative to the base of KeyLargo or to the base of the
425 * GPIO space, and the device-tree doesn't help.
426 */
427 offset = *reg;
428 if (offset < KEYLARGO_GPIO_LEVELS0)
429 offset += KEYLARGO_GPIO_LEVELS0;
430 return offset;
431}
432
433static int pmac_cpufreq_suspend(struct cpufreq_policy *policy)
434{
435 /* Ok, this could be made a bit smarter, but let's be robust for now. We
436 * always force a speed change to high speed before sleep, to make sure
437 * we have appropriate voltage and/or bus speed for the wakeup process,
438 * and to make sure our loops_per_jiffies are "good enough", that is will
439 * not cause too short delays if we sleep in low speed and wake in high
440 * speed..
441 */
442 no_schedule = 1;
443 sleep_freq = cur_freq;
444 if (cur_freq == low_freq && !is_pmu_based)
445 do_set_cpu_speed(policy, CPUFREQ_HIGH, 0);
446 return 0;
447}
448
449static int pmac_cpufreq_resume(struct cpufreq_policy *policy)
450{
451 /* If we resume, first check if we have a get() function */
452 if (get_speed_proc)
453 cur_freq = get_speed_proc();
454 else
455 cur_freq = 0;
456
457 /* We don't, hrm... we don't really know our speed here, best
458 * is that we force a switch to whatever it was, which is
459 * probably high speed due to our suspend() routine
460 */
461 do_set_cpu_speed(policy, sleep_freq == low_freq ?
462 CPUFREQ_LOW : CPUFREQ_HIGH, 0);
463
464 ppc_proc_freq = cur_freq * 1000ul;
465
466 no_schedule = 0;
467 return 0;
468}
469
470static struct cpufreq_driver pmac_cpufreq_driver = {
471 .verify = pmac_cpufreq_verify,
472 .target = pmac_cpufreq_target,
473 .get = pmac_cpufreq_get_speed,
474 .init = pmac_cpufreq_cpu_init,
475 .suspend = pmac_cpufreq_suspend,
476 .resume = pmac_cpufreq_resume,
477 .flags = CPUFREQ_PM_NO_WARN,
478 .attr = pmac_cpu_freqs_attr,
479 .name = "powermac",
480 .owner = THIS_MODULE,
481};
482
483
484static int pmac_cpufreq_init_MacRISC3(struct device_node *cpunode)
485{
486 struct device_node *volt_gpio_np = of_find_node_by_name(NULL,
487 "voltage-gpio");
488 struct device_node *freq_gpio_np = of_find_node_by_name(NULL,
489 "frequency-gpio");
490 struct device_node *slew_done_gpio_np = of_find_node_by_name(NULL,
491 "slewing-done");
492 const u32 *value;
493
494 /*
495 * Check to see if it's GPIO driven or PMU only
496 *
497 * The way we extract the GPIO address is slightly hackish, but it
498 * works well enough for now. We need to abstract the whole GPIO
499 * stuff sooner or later anyway
500 */
501
502 if (volt_gpio_np)
503 voltage_gpio = read_gpio(volt_gpio_np);
504 if (freq_gpio_np)
505 frequency_gpio = read_gpio(freq_gpio_np);
506 if (slew_done_gpio_np)
507 slew_done_gpio = read_gpio(slew_done_gpio_np);
508
509 /* If we use the frequency GPIOs, calculate the min/max speeds based
510 * on the bus frequencies
511 */
512 if (frequency_gpio && slew_done_gpio) {
513 int lenp, rc;
514 const u32 *freqs, *ratio;
515
516 freqs = of_get_property(cpunode, "bus-frequencies", &lenp);
517 lenp /= sizeof(u32);
518 if (freqs == NULL || lenp != 2) {
519 printk(KERN_ERR "cpufreq: bus-frequencies incorrect or missing\n");
520 return 1;
521 }
522 ratio = of_get_property(cpunode, "processor-to-bus-ratio*2",
523 NULL);
524 if (ratio == NULL) {
525 printk(KERN_ERR "cpufreq: processor-to-bus-ratio*2 missing\n");
526 return 1;
527 }
528
529 /* Get the min/max bus frequencies */
530 low_freq = min(freqs[0], freqs[1]);
531 hi_freq = max(freqs[0], freqs[1]);
532
533 /* Grrrr.. It _seems_ that the device-tree is lying on the low bus
534 * frequency, it claims it to be around 84Mhz on some models while
535 * it appears to be approx. 101Mhz on all. Let's hack around here...
536 * fortunately, we don't need to be too precise
537 */
538 if (low_freq < 98000000)
539 low_freq = 101000000;
540
541 /* Convert those to CPU core clocks */
542 low_freq = (low_freq * (*ratio)) / 2000;
543 hi_freq = (hi_freq * (*ratio)) / 2000;
544
545 /* Now we get the frequencies, we read the GPIO to see what is out current
546 * speed
547 */
548 rc = pmac_call_feature(PMAC_FTR_READ_GPIO, NULL, frequency_gpio, 0);
549 cur_freq = (rc & 0x01) ? hi_freq : low_freq;
550
551 set_speed_proc = gpios_set_cpu_speed;
552 return 1;
553 }
554
555 /* If we use the PMU, look for the min & max frequencies in the
556 * device-tree
557 */
558 value = of_get_property(cpunode, "min-clock-frequency", NULL);
559 if (!value)
560 return 1;
561 low_freq = (*value) / 1000;
562 /* The PowerBook G4 12" (PowerBook6,1) has an error in the device-tree
563 * here */
564 if (low_freq < 100000)
565 low_freq *= 10;
566
567 value = of_get_property(cpunode, "max-clock-frequency", NULL);
568 if (!value)
569 return 1;
570 hi_freq = (*value) / 1000;
571 set_speed_proc = pmu_set_cpu_speed;
572 is_pmu_based = 1;
573
574 return 0;
575}
576
577static int pmac_cpufreq_init_7447A(struct device_node *cpunode)
578{
579 struct device_node *volt_gpio_np;
580
581 if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL)
582 return 1;
583
584 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
585 if (volt_gpio_np)
586 voltage_gpio = read_gpio(volt_gpio_np);
587 if (!voltage_gpio){
588 printk(KERN_ERR "cpufreq: missing cpu-vcore-select gpio\n");
589 return 1;
590 }
591
592 /* OF only reports the high frequency */
593 hi_freq = cur_freq;
594 low_freq = cur_freq/2;
595
596 /* Read actual frequency from CPU */
597 cur_freq = dfs_get_cpu_speed();
598 set_speed_proc = dfs_set_cpu_speed;
599 get_speed_proc = dfs_get_cpu_speed;
600
601 return 0;
602}
603
604static int pmac_cpufreq_init_750FX(struct device_node *cpunode)
605{
606 struct device_node *volt_gpio_np;
607 u32 pvr;
608 const u32 *value;
609
610 if (of_get_property(cpunode, "dynamic-power-step", NULL) == NULL)
611 return 1;
612
613 hi_freq = cur_freq;
614 value = of_get_property(cpunode, "reduced-clock-frequency", NULL);
615 if (!value)
616 return 1;
617 low_freq = (*value) / 1000;
618
619 volt_gpio_np = of_find_node_by_name(NULL, "cpu-vcore-select");
620 if (volt_gpio_np)
621 voltage_gpio = read_gpio(volt_gpio_np);
622
623 pvr = mfspr(SPRN_PVR);
624 has_cpu_l2lve = !((pvr & 0xf00) == 0x100);
625
626 set_speed_proc = cpu_750fx_cpu_speed;
627 get_speed_proc = cpu_750fx_get_cpu_speed;
628 cur_freq = cpu_750fx_get_cpu_speed();
629
630 return 0;
631}
632
633/* Currently, we support the following machines:
634 *
635 * - Titanium PowerBook 1Ghz (PMU based, 667Mhz & 1Ghz)
636 * - Titanium PowerBook 800 (PMU based, 667Mhz & 800Mhz)
637 * - Titanium PowerBook 400 (PMU based, 300Mhz & 400Mhz)
638 * - Titanium PowerBook 500 (PMU based, 300Mhz & 500Mhz)
639 * - iBook2 500/600 (PMU based, 400Mhz & 500/600Mhz)
640 * - iBook2 700 (CPU based, 400Mhz & 700Mhz, support low voltage)
641 * - Recent MacRISC3 laptops
642 * - All new machines with 7447A CPUs
643 */
644static int __init pmac_cpufreq_setup(void)
645{
646 struct device_node *cpunode;
647 const u32 *value;
648
649 if (strstr(cmd_line, "nocpufreq"))
650 return 0;
651
652 /* Assume only one CPU */
653 cpunode = of_find_node_by_type(NULL, "cpu");
654 if (!cpunode)
655 goto out;
656
657 /* Get current cpu clock freq */
658 value = of_get_property(cpunode, "clock-frequency", NULL);
659 if (!value)
660 goto out;
661 cur_freq = (*value) / 1000;
662 transition_latency = CPUFREQ_ETERNAL;
663
664 /* Check for 7447A based MacRISC3 */
665 if (of_machine_is_compatible("MacRISC3") &&
666 of_get_property(cpunode, "dynamic-power-step", NULL) &&
667 PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
668 pmac_cpufreq_init_7447A(cpunode);
669 transition_latency = 8000000;
670 /* Check for other MacRISC3 machines */
671 } else if (of_machine_is_compatible("PowerBook3,4") ||
672 of_machine_is_compatible("PowerBook3,5") ||
673 of_machine_is_compatible("MacRISC3")) {
674 pmac_cpufreq_init_MacRISC3(cpunode);
675 /* Else check for iBook2 500/600 */
676 } else if (of_machine_is_compatible("PowerBook4,1")) {
677 hi_freq = cur_freq;
678 low_freq = 400000;
679 set_speed_proc = pmu_set_cpu_speed;
680 is_pmu_based = 1;
681 }
682 /* Else check for TiPb 550 */
683 else if (of_machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
684 hi_freq = cur_freq;
685 low_freq = 500000;
686 set_speed_proc = pmu_set_cpu_speed;
687 is_pmu_based = 1;
688 }
689 /* Else check for TiPb 400 & 500 */
690 else if (of_machine_is_compatible("PowerBook3,2")) {
691 /* We only know about the 400 MHz and the 500Mhz model
692 * they both have 300 MHz as low frequency
693 */
694 if (cur_freq < 350000 || cur_freq > 550000)
695 goto out;
696 hi_freq = cur_freq;
697 low_freq = 300000;
698 set_speed_proc = pmu_set_cpu_speed;
699 is_pmu_based = 1;
700 }
701 /* Else check for 750FX */
702 else if (PVR_VER(mfspr(SPRN_PVR)) == 0x7000)
703 pmac_cpufreq_init_750FX(cpunode);
704out:
705 of_node_put(cpunode);
706 if (set_speed_proc == NULL)
707 return -ENODEV;
708
709 pmac_cpu_freqs[CPUFREQ_LOW].frequency = low_freq;
710 pmac_cpu_freqs[CPUFREQ_HIGH].frequency = hi_freq;
711 ppc_proc_freq = cur_freq * 1000ul;
712
713 printk(KERN_INFO "Registering PowerMac CPU frequency driver\n");
714 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Boot: %d Mhz\n",
715 low_freq/1000, hi_freq/1000, cur_freq/1000);
716
717 return cpufreq_register_driver(&pmac_cpufreq_driver);
718}
719
720module_init(pmac_cpufreq_setup);
721
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c
deleted file mode 100644
index 7ba423431cfe..000000000000
--- a/arch/powerpc/platforms/powermac/cpufreq_64.c
+++ /dev/null
@@ -1,746 +0,0 @@
1/*
2 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
3 * and Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
10 * that is iMac G5 and latest single CPU desktop.
11 */
12
13#undef DEBUG
14
15#include <linux/module.h>
16#include <linux/types.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
20#include <linux/sched.h>
21#include <linux/cpufreq.h>
22#include <linux/init.h>
23#include <linux/completion.h>
24#include <linux/mutex.h>
25#include <asm/prom.h>
26#include <asm/machdep.h>
27#include <asm/irq.h>
28#include <asm/sections.h>
29#include <asm/cputable.h>
30#include <asm/time.h>
31#include <asm/smu.h>
32#include <asm/pmac_pfunc.h>
33
34#define DBG(fmt...) pr_debug(fmt)
35
36/* see 970FX user manual */
37
38#define SCOM_PCR 0x0aa001 /* PCR scom addr */
39
40#define PCR_HILO_SELECT 0x80000000U /* 1 = PCR, 0 = PCRH */
41#define PCR_SPEED_FULL 0x00000000U /* 1:1 speed value */
42#define PCR_SPEED_HALF 0x00020000U /* 1:2 speed value */
43#define PCR_SPEED_QUARTER 0x00040000U /* 1:4 speed value */
44#define PCR_SPEED_MASK 0x000e0000U /* speed mask */
45#define PCR_SPEED_SHIFT 17
46#define PCR_FREQ_REQ_VALID 0x00010000U /* freq request valid */
47#define PCR_VOLT_REQ_VALID 0x00008000U /* volt request valid */
48#define PCR_TARGET_TIME_MASK 0x00006000U /* target time */
49#define PCR_STATLAT_MASK 0x00001f00U /* STATLAT value */
50#define PCR_SNOOPLAT_MASK 0x000000f0U /* SNOOPLAT value */
51#define PCR_SNOOPACC_MASK 0x0000000fU /* SNOOPACC value */
52
53#define SCOM_PSR 0x408001 /* PSR scom addr */
54/* warning: PSR is a 64 bits register */
55#define PSR_CMD_RECEIVED 0x2000000000000000U /* command received */
56#define PSR_CMD_COMPLETED 0x1000000000000000U /* command completed */
57#define PSR_CUR_SPEED_MASK 0x0300000000000000U /* current speed */
58#define PSR_CUR_SPEED_SHIFT (56)
59
60/*
61 * The G5 only supports two frequencies (Quarter speed is not supported)
62 */
63#define CPUFREQ_HIGH 0
64#define CPUFREQ_LOW 1
65
66static struct cpufreq_frequency_table g5_cpu_freqs[] = {
67 {CPUFREQ_HIGH, 0},
68 {CPUFREQ_LOW, 0},
69 {0, CPUFREQ_TABLE_END},
70};
71
72static struct freq_attr* g5_cpu_freqs_attr[] = {
73 &cpufreq_freq_attr_scaling_available_freqs,
74 NULL,
75};
76
77/* Power mode data is an array of the 32 bits PCR values to use for
78 * the various frequencies, retrieved from the device-tree
79 */
80static int g5_pmode_cur;
81
82static void (*g5_switch_volt)(int speed_mode);
83static int (*g5_switch_freq)(int speed_mode);
84static int (*g5_query_freq)(void);
85
86static DEFINE_MUTEX(g5_switch_mutex);
87
88static unsigned long transition_latency;
89
90#ifdef CONFIG_PMAC_SMU
91
92static const u32 *g5_pmode_data;
93static int g5_pmode_max;
94
95static struct smu_sdbp_fvt *g5_fvt_table; /* table of op. points */
96static int g5_fvt_count; /* number of op. points */
97static int g5_fvt_cur; /* current op. point */
98
99/*
100 * SMU based voltage switching for Neo2 platforms
101 */
102
103static void g5_smu_switch_volt(int speed_mode)
104{
105 struct smu_simple_cmd cmd;
106
107 DECLARE_COMPLETION_ONSTACK(comp);
108 smu_queue_simple(&cmd, SMU_CMD_POWER_COMMAND, 8, smu_done_complete,
109 &comp, 'V', 'S', 'L', 'E', 'W',
110 0xff, g5_fvt_cur+1, speed_mode);
111 wait_for_completion(&comp);
112}
113
114/*
115 * Platform function based voltage/vdnap switching for Neo2
116 */
117
118static struct pmf_function *pfunc_set_vdnap0;
119static struct pmf_function *pfunc_vdnap0_complete;
120
121static void g5_vdnap_switch_volt(int speed_mode)
122{
123 struct pmf_args args;
124 u32 slew, done = 0;
125 unsigned long timeout;
126
127 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0;
128 args.count = 1;
129 args.u[0].p = &slew;
130
131 pmf_call_one(pfunc_set_vdnap0, &args);
132
133 /* It's an irq GPIO so we should be able to just block here,
134 * I'll do that later after I've properly tested the IRQ code for
135 * platform functions
136 */
137 timeout = jiffies + HZ/10;
138 while(!time_after(jiffies, timeout)) {
139 args.count = 1;
140 args.u[0].p = &done;
141 pmf_call_one(pfunc_vdnap0_complete, &args);
142 if (done)
143 break;
144 msleep(1);
145 }
146 if (done == 0)
147 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
148}
149
150
151/*
152 * SCOM based frequency switching for 970FX rev3
153 */
154static int g5_scom_switch_freq(int speed_mode)
155{
156 unsigned long flags;
157 int to;
158
159 /* If frequency is going up, first ramp up the voltage */
160 if (speed_mode < g5_pmode_cur)
161 g5_switch_volt(speed_mode);
162
163 local_irq_save(flags);
164
165 /* Clear PCR high */
166 scom970_write(SCOM_PCR, 0);
167 /* Clear PCR low */
168 scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
169 /* Set PCR low */
170 scom970_write(SCOM_PCR, PCR_HILO_SELECT |
171 g5_pmode_data[speed_mode]);
172
173 /* Wait for completion */
174 for (to = 0; to < 10; to++) {
175 unsigned long psr = scom970_read(SCOM_PSR);
176
177 if ((psr & PSR_CMD_RECEIVED) == 0 &&
178 (((psr >> PSR_CUR_SPEED_SHIFT) ^
179 (g5_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
180 == 0)
181 break;
182 if (psr & PSR_CMD_COMPLETED)
183 break;
184 udelay(100);
185 }
186
187 local_irq_restore(flags);
188
189 /* If frequency is going down, last ramp the voltage */
190 if (speed_mode > g5_pmode_cur)
191 g5_switch_volt(speed_mode);
192
193 g5_pmode_cur = speed_mode;
194 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
195
196 return 0;
197}
198
199static int g5_scom_query_freq(void)
200{
201 unsigned long psr = scom970_read(SCOM_PSR);
202 int i;
203
204 for (i = 0; i <= g5_pmode_max; i++)
205 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
206 (g5_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
207 break;
208 return i;
209}
210
211/*
212 * Fake voltage switching for platforms with missing support
213 */
214
215static void g5_dummy_switch_volt(int speed_mode)
216{
217}
218
219#endif /* CONFIG_PMAC_SMU */
220
221/*
222 * Platform function based voltage switching for PowerMac7,2 & 7,3
223 */
224
225static struct pmf_function *pfunc_cpu0_volt_high;
226static struct pmf_function *pfunc_cpu0_volt_low;
227static struct pmf_function *pfunc_cpu1_volt_high;
228static struct pmf_function *pfunc_cpu1_volt_low;
229
230static void g5_pfunc_switch_volt(int speed_mode)
231{
232 if (speed_mode == CPUFREQ_HIGH) {
233 if (pfunc_cpu0_volt_high)
234 pmf_call_one(pfunc_cpu0_volt_high, NULL);
235 if (pfunc_cpu1_volt_high)
236 pmf_call_one(pfunc_cpu1_volt_high, NULL);
237 } else {
238 if (pfunc_cpu0_volt_low)
239 pmf_call_one(pfunc_cpu0_volt_low, NULL);
240 if (pfunc_cpu1_volt_low)
241 pmf_call_one(pfunc_cpu1_volt_low, NULL);
242 }
243 msleep(10); /* should be faster , to fix */
244}
245
246/*
247 * Platform function based frequency switching for PowerMac7,2 & 7,3
248 */
249
250static struct pmf_function *pfunc_cpu_setfreq_high;
251static struct pmf_function *pfunc_cpu_setfreq_low;
252static struct pmf_function *pfunc_cpu_getfreq;
253static struct pmf_function *pfunc_slewing_done;
254
255static int g5_pfunc_switch_freq(int speed_mode)
256{
257 struct pmf_args args;
258 u32 done = 0;
259 unsigned long timeout;
260 int rc;
261
262 DBG("g5_pfunc_switch_freq(%d)\n", speed_mode);
263
264 /* If frequency is going up, first ramp up the voltage */
265 if (speed_mode < g5_pmode_cur)
266 g5_switch_volt(speed_mode);
267
268 /* Do it */
269 if (speed_mode == CPUFREQ_HIGH)
270 rc = pmf_call_one(pfunc_cpu_setfreq_high, NULL);
271 else
272 rc = pmf_call_one(pfunc_cpu_setfreq_low, NULL);
273
274 if (rc)
275 printk(KERN_WARNING "cpufreq: pfunc switch error %d\n", rc);
276
277 /* It's an irq GPIO so we should be able to just block here,
278 * I'll do that later after I've properly tested the IRQ code for
279 * platform functions
280 */
281 timeout = jiffies + HZ/10;
282 while(!time_after(jiffies, timeout)) {
283 args.count = 1;
284 args.u[0].p = &done;
285 pmf_call_one(pfunc_slewing_done, &args);
286 if (done)
287 break;
288 msleep(1);
289 }
290 if (done == 0)
291 printk(KERN_WARNING "cpufreq: Timeout in clock slewing !\n");
292
293 /* If frequency is going down, last ramp the voltage */
294 if (speed_mode > g5_pmode_cur)
295 g5_switch_volt(speed_mode);
296
297 g5_pmode_cur = speed_mode;
298 ppc_proc_freq = g5_cpu_freqs[speed_mode].frequency * 1000ul;
299
300 return 0;
301}
302
303static int g5_pfunc_query_freq(void)
304{
305 struct pmf_args args;
306 u32 val = 0;
307
308 args.count = 1;
309 args.u[0].p = &val;
310 pmf_call_one(pfunc_cpu_getfreq, &args);
311 return val ? CPUFREQ_HIGH : CPUFREQ_LOW;
312}
313
314
315/*
316 * Common interface to the cpufreq core
317 */
318
319static int g5_cpufreq_verify(struct cpufreq_policy *policy)
320{
321 return cpufreq_frequency_table_verify(policy, g5_cpu_freqs);
322}
323
324static int g5_cpufreq_target(struct cpufreq_policy *policy,
325 unsigned int target_freq, unsigned int relation)
326{
327 unsigned int newstate = 0;
328 struct cpufreq_freqs freqs;
329 int rc;
330
331 if (cpufreq_frequency_table_target(policy, g5_cpu_freqs,
332 target_freq, relation, &newstate))
333 return -EINVAL;
334
335 if (g5_pmode_cur == newstate)
336 return 0;
337
338 mutex_lock(&g5_switch_mutex);
339
340 freqs.old = g5_cpu_freqs[g5_pmode_cur].frequency;
341 freqs.new = g5_cpu_freqs[newstate].frequency;
342
343 cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
344 rc = g5_switch_freq(newstate);
345 cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
346
347 mutex_unlock(&g5_switch_mutex);
348
349 return rc;
350}
351
352static unsigned int g5_cpufreq_get_speed(unsigned int cpu)
353{
354 return g5_cpu_freqs[g5_pmode_cur].frequency;
355}
356
357static int g5_cpufreq_cpu_init(struct cpufreq_policy *policy)
358{
359 policy->cpuinfo.transition_latency = transition_latency;
360 policy->cur = g5_cpu_freqs[g5_query_freq()].frequency;
361 /* secondary CPUs are tied to the primary one by the
362 * cpufreq core if in the secondary policy we tell it that
363 * it actually must be one policy together with all others. */
364 cpumask_copy(policy->cpus, cpu_online_mask);
365 cpufreq_frequency_table_get_attr(g5_cpu_freqs, policy->cpu);
366
367 return cpufreq_frequency_table_cpuinfo(policy,
368 g5_cpu_freqs);
369}
370
371
372static struct cpufreq_driver g5_cpufreq_driver = {
373 .name = "powermac",
374 .owner = THIS_MODULE,
375 .flags = CPUFREQ_CONST_LOOPS,
376 .init = g5_cpufreq_cpu_init,
377 .verify = g5_cpufreq_verify,
378 .target = g5_cpufreq_target,
379 .get = g5_cpufreq_get_speed,
380 .attr = g5_cpu_freqs_attr,
381};
382
383
384#ifdef CONFIG_PMAC_SMU
385
386static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
387{
388 struct device_node *cpunode;
389 unsigned int psize, ssize;
390 unsigned long max_freq;
391 char *freq_method, *volt_method;
392 const u32 *valp;
393 u32 pvr_hi;
394 int use_volts_vdnap = 0;
395 int use_volts_smu = 0;
396 int rc = -ENODEV;
397
398 /* Check supported platforms */
399 if (of_machine_is_compatible("PowerMac8,1") ||
400 of_machine_is_compatible("PowerMac8,2") ||
401 of_machine_is_compatible("PowerMac9,1"))
402 use_volts_smu = 1;
403 else if (of_machine_is_compatible("PowerMac11,2"))
404 use_volts_vdnap = 1;
405 else
406 return -ENODEV;
407
408 /* Get first CPU node */
409 for (cpunode = NULL;
410 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
411 const u32 *reg = of_get_property(cpunode, "reg", NULL);
412 if (reg == NULL || (*reg) != 0)
413 continue;
414 if (!strcmp(cpunode->type, "cpu"))
415 break;
416 }
417 if (cpunode == NULL) {
418 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
419 return -ENODEV;
420 }
421
422 /* Check 970FX for now */
423 valp = of_get_property(cpunode, "cpu-version", NULL);
424 if (!valp) {
425 DBG("No cpu-version property !\n");
426 goto bail_noprops;
427 }
428 pvr_hi = (*valp) >> 16;
429 if (pvr_hi != 0x3c && pvr_hi != 0x44) {
430 printk(KERN_ERR "cpufreq: Unsupported CPU version\n");
431 goto bail_noprops;
432 }
433
434 /* Look for the powertune data in the device-tree */
435 g5_pmode_data = of_get_property(cpunode, "power-mode-data",&psize);
436 if (!g5_pmode_data) {
437 DBG("No power-mode-data !\n");
438 goto bail_noprops;
439 }
440 g5_pmode_max = psize / sizeof(u32) - 1;
441
442 if (use_volts_smu) {
443 const struct smu_sdbp_header *shdr;
444
445 /* Look for the FVT table */
446 shdr = smu_get_sdb_partition(SMU_SDB_FVT_ID, NULL);
447 if (!shdr)
448 goto bail_noprops;
449 g5_fvt_table = (struct smu_sdbp_fvt *)&shdr[1];
450 ssize = (shdr->len * sizeof(u32)) -
451 sizeof(struct smu_sdbp_header);
452 g5_fvt_count = ssize / sizeof(struct smu_sdbp_fvt);
453 g5_fvt_cur = 0;
454
455 /* Sanity checking */
456 if (g5_fvt_count < 1 || g5_pmode_max < 1)
457 goto bail_noprops;
458
459 g5_switch_volt = g5_smu_switch_volt;
460 volt_method = "SMU";
461 } else if (use_volts_vdnap) {
462 struct device_node *root;
463
464 root = of_find_node_by_path("/");
465 if (root == NULL) {
466 printk(KERN_ERR "cpufreq: Can't find root of "
467 "device tree\n");
468 goto bail_noprops;
469 }
470 pfunc_set_vdnap0 = pmf_find_function(root, "set-vdnap0");
471 pfunc_vdnap0_complete =
472 pmf_find_function(root, "slewing-done");
473 if (pfunc_set_vdnap0 == NULL ||
474 pfunc_vdnap0_complete == NULL) {
475 printk(KERN_ERR "cpufreq: Can't find required "
476 "platform function\n");
477 goto bail_noprops;
478 }
479
480 g5_switch_volt = g5_vdnap_switch_volt;
481 volt_method = "GPIO";
482 } else {
483 g5_switch_volt = g5_dummy_switch_volt;
484 volt_method = "none";
485 }
486
487 /*
488 * From what I see, clock-frequency is always the maximal frequency.
489 * The current driver can not slew sysclk yet, so we really only deal
490 * with powertune steps for now. We also only implement full freq and
491 * half freq in this version. So far, I haven't yet seen a machine
492 * supporting anything else.
493 */
494 valp = of_get_property(cpunode, "clock-frequency", NULL);
495 if (!valp)
496 return -ENODEV;
497 max_freq = (*valp)/1000;
498 g5_cpu_freqs[0].frequency = max_freq;
499 g5_cpu_freqs[1].frequency = max_freq/2;
500
501 /* Set callbacks */
502 transition_latency = 12000;
503 g5_switch_freq = g5_scom_switch_freq;
504 g5_query_freq = g5_scom_query_freq;
505 freq_method = "SCOM";
506
507 /* Force apply current frequency to make sure everything is in
508 * sync (voltage is right for example). Firmware may leave us with
509 * a strange setting ...
510 */
511 g5_switch_volt(CPUFREQ_HIGH);
512 msleep(10);
513 g5_pmode_cur = -1;
514 g5_switch_freq(g5_query_freq());
515
516 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
517 printk(KERN_INFO "Frequency method: %s, Voltage method: %s\n",
518 freq_method, volt_method);
519 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
520 g5_cpu_freqs[1].frequency/1000,
521 g5_cpu_freqs[0].frequency/1000,
522 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
523
524 rc = cpufreq_register_driver(&g5_cpufreq_driver);
525
526 /* We keep the CPU node on hold... hopefully, Apple G5 don't have
527 * hotplug CPU with a dynamic device-tree ...
528 */
529 return rc;
530
531 bail_noprops:
532 of_node_put(cpunode);
533
534 return rc;
535}
536
537#endif /* CONFIG_PMAC_SMU */
538
539
540static int __init g5_pm72_cpufreq_init(struct device_node *cpus)
541{
542 struct device_node *cpuid = NULL, *hwclock = NULL, *cpunode = NULL;
543 const u8 *eeprom = NULL;
544 const u32 *valp;
545 u64 max_freq, min_freq, ih, il;
546 int has_volt = 1, rc = 0;
547
548 DBG("cpufreq: Initializing for PowerMac7,2, PowerMac7,3 and"
549 " RackMac3,1...\n");
550
551 /* Get first CPU node */
552 for (cpunode = NULL;
553 (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
554 if (!strcmp(cpunode->type, "cpu"))
555 break;
556 }
557 if (cpunode == NULL) {
558 printk(KERN_ERR "cpufreq: Can't find any CPU node\n");
559 return -ENODEV;
560 }
561
562 /* Lookup the cpuid eeprom node */
563 cpuid = of_find_node_by_path("/u3@0,f8000000/i2c@f8001000/cpuid@a0");
564 if (cpuid != NULL)
565 eeprom = of_get_property(cpuid, "cpuid", NULL);
566 if (eeprom == NULL) {
567 printk(KERN_ERR "cpufreq: Can't find cpuid EEPROM !\n");
568 rc = -ENODEV;
569 goto bail;
570 }
571
572 /* Lookup the i2c hwclock */
573 for (hwclock = NULL;
574 (hwclock = of_find_node_by_name(hwclock, "i2c-hwclock")) != NULL;){
575 const char *loc = of_get_property(hwclock,
576 "hwctrl-location", NULL);
577 if (loc == NULL)
578 continue;
579 if (strcmp(loc, "CPU CLOCK"))
580 continue;
581 if (!of_get_property(hwclock, "platform-get-frequency", NULL))
582 continue;
583 break;
584 }
585 if (hwclock == NULL) {
586 printk(KERN_ERR "cpufreq: Can't find i2c clock chip !\n");
587 rc = -ENODEV;
588 goto bail;
589 }
590
591 DBG("cpufreq: i2c clock chip found: %s\n", hwclock->full_name);
592
593 /* Now get all the platform functions */
594 pfunc_cpu_getfreq =
595 pmf_find_function(hwclock, "get-frequency");
596 pfunc_cpu_setfreq_high =
597 pmf_find_function(hwclock, "set-frequency-high");
598 pfunc_cpu_setfreq_low =
599 pmf_find_function(hwclock, "set-frequency-low");
600 pfunc_slewing_done =
601 pmf_find_function(hwclock, "slewing-done");
602 pfunc_cpu0_volt_high =
603 pmf_find_function(hwclock, "set-voltage-high-0");
604 pfunc_cpu0_volt_low =
605 pmf_find_function(hwclock, "set-voltage-low-0");
606 pfunc_cpu1_volt_high =
607 pmf_find_function(hwclock, "set-voltage-high-1");
608 pfunc_cpu1_volt_low =
609 pmf_find_function(hwclock, "set-voltage-low-1");
610
611 /* Check we have minimum requirements */
612 if (pfunc_cpu_getfreq == NULL || pfunc_cpu_setfreq_high == NULL ||
613 pfunc_cpu_setfreq_low == NULL || pfunc_slewing_done == NULL) {
614 printk(KERN_ERR "cpufreq: Can't find platform functions !\n");
615 rc = -ENODEV;
616 goto bail;
617 }
618
619 /* Check that we have complete sets */
620 if (pfunc_cpu0_volt_high == NULL || pfunc_cpu0_volt_low == NULL) {
621 pmf_put_function(pfunc_cpu0_volt_high);
622 pmf_put_function(pfunc_cpu0_volt_low);
623 pfunc_cpu0_volt_high = pfunc_cpu0_volt_low = NULL;
624 has_volt = 0;
625 }
626 if (!has_volt ||
627 pfunc_cpu1_volt_high == NULL || pfunc_cpu1_volt_low == NULL) {
628 pmf_put_function(pfunc_cpu1_volt_high);
629 pmf_put_function(pfunc_cpu1_volt_low);
630 pfunc_cpu1_volt_high = pfunc_cpu1_volt_low = NULL;
631 }
632
633 /* Note: The device tree also contains a "platform-set-values"
634 * function for which I haven't quite figured out the usage. It
635 * might have to be called on init and/or wakeup, I'm not too sure
636 * but things seem to work fine without it so far ...
637 */
638
639 /* Get max frequency from device-tree */
640 valp = of_get_property(cpunode, "clock-frequency", NULL);
641 if (!valp) {
642 printk(KERN_ERR "cpufreq: Can't find CPU frequency !\n");
643 rc = -ENODEV;
644 goto bail;
645 }
646
647 max_freq = (*valp)/1000;
648
649 /* Now calculate reduced frequency by using the cpuid input freq
650 * ratio. This requires 64 bits math unless we are willing to lose
651 * some precision
652 */
653 ih = *((u32 *)(eeprom + 0x10));
654 il = *((u32 *)(eeprom + 0x20));
655
656 /* Check for machines with no useful settings */
657 if (il == ih) {
658 printk(KERN_WARNING "cpufreq: No low frequency mode available"
659 " on this model !\n");
660 rc = -ENODEV;
661 goto bail;
662 }
663
664 min_freq = 0;
665 if (ih != 0 && il != 0)
666 min_freq = (max_freq * il) / ih;
667
668 /* Sanity check */
669 if (min_freq >= max_freq || min_freq < 1000) {
670 printk(KERN_ERR "cpufreq: Can't calculate low frequency !\n");
671 rc = -ENXIO;
672 goto bail;
673 }
674 g5_cpu_freqs[0].frequency = max_freq;
675 g5_cpu_freqs[1].frequency = min_freq;
676
677 /* Set callbacks */
678 transition_latency = CPUFREQ_ETERNAL;
679 g5_switch_volt = g5_pfunc_switch_volt;
680 g5_switch_freq = g5_pfunc_switch_freq;
681 g5_query_freq = g5_pfunc_query_freq;
682
683 /* Force apply current frequency to make sure everything is in
684 * sync (voltage is right for example). Firmware may leave us with
685 * a strange setting ...
686 */
687 g5_switch_volt(CPUFREQ_HIGH);
688 msleep(10);
689 g5_pmode_cur = -1;
690 g5_switch_freq(g5_query_freq());
691
692 printk(KERN_INFO "Registering G5 CPU frequency driver\n");
693 printk(KERN_INFO "Frequency method: i2c/pfunc, "
694 "Voltage method: %s\n", has_volt ? "i2c/pfunc" : "none");
695 printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
696 g5_cpu_freqs[1].frequency/1000,
697 g5_cpu_freqs[0].frequency/1000,
698 g5_cpu_freqs[g5_pmode_cur].frequency/1000);
699
700 rc = cpufreq_register_driver(&g5_cpufreq_driver);
701 bail:
702 if (rc != 0) {
703 pmf_put_function(pfunc_cpu_getfreq);
704 pmf_put_function(pfunc_cpu_setfreq_high);
705 pmf_put_function(pfunc_cpu_setfreq_low);
706 pmf_put_function(pfunc_slewing_done);
707 pmf_put_function(pfunc_cpu0_volt_high);
708 pmf_put_function(pfunc_cpu0_volt_low);
709 pmf_put_function(pfunc_cpu1_volt_high);
710 pmf_put_function(pfunc_cpu1_volt_low);
711 }
712 of_node_put(hwclock);
713 of_node_put(cpuid);
714 of_node_put(cpunode);
715
716 return rc;
717}
718
719static int __init g5_cpufreq_init(void)
720{
721 struct device_node *cpus;
722 int rc = 0;
723
724 cpus = of_find_node_by_path("/cpus");
725 if (cpus == NULL) {
726 DBG("No /cpus node !\n");
727 return -ENODEV;
728 }
729
730 if (of_machine_is_compatible("PowerMac7,2") ||
731 of_machine_is_compatible("PowerMac7,3") ||
732 of_machine_is_compatible("RackMac3,1"))
733 rc = g5_pm72_cpufreq_init(cpus);
734#ifdef CONFIG_PMAC_SMU
735 else
736 rc = g5_neo2_cpufreq_init(cpus);
737#endif /* CONFIG_PMAC_SMU */
738
739 of_node_put(cpus);
740 return rc;
741}
742
743module_init(g5_cpufreq_init);
744
745
746MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-08 13:07:06 -0400