MIPS: Alchemy: remove au_read/write/sync

replace au_read/write/sync with __raw_read/write and wmb.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7465/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 44 insertions, 91 deletions

diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 19d5642c16d9..745695db5ba0 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -341,7 +341,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                         (dtp->dev_flags & DEV_FLAGS_SYNC))
                                 i |= DDMA_CFG_SYNC;
                 cp->ddma_cfg = i;
-                au_sync();
+                wmb(); /* drain writebuffer */
 
                 /*
                  * Return a non-zero value that can be used to find the channel
@@ -631,7 +631,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
          */
         dma_cache_wback_inv((unsigned long)buf, nbytes);
         dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
-        au_sync();
+        wmb(); /* drain writebuffer */
         dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
         ctp->chan_ptr->ddma_dbell = 0;
 
@@ -693,7 +693,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
          */
         dma_cache_inv((unsigned long)buf, nbytes);
         dp->dscr_cmd0 |= DSCR_CMD0_V;   /* Let it rip */
-        au_sync();
+        wmb(); /* drain writebuffer */
         dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
         ctp->chan_ptr->ddma_dbell = 0;
 
@@ -760,7 +760,7 @@ void au1xxx_dbdma_stop(u32 chanid)
 
         cp = ctp->chan_ptr;
         cp->ddma_cfg &= ~DDMA_CFG_EN;   /* Disable channel */
-        au_sync();
+        wmb(); /* drain writebuffer */
         while (!(cp->ddma_stat & DDMA_STAT_H)) {
                 udelay(1);
                 halt_timeout++;
@@ -771,7 +771,7 @@ void au1xxx_dbdma_stop(u32 chanid)
         }
         /* clear current desc valid and doorbell */
         cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
-        au_sync();
+        wmb(); /* drain writebuffer */
 }
 EXPORT_SYMBOL(au1xxx_dbdma_stop);
 
@@ -789,9 +789,9 @@ void au1xxx_dbdma_start(u32 chanid)
         cp = ctp->chan_ptr;
         cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
         cp->ddma_cfg |= DDMA_CFG_EN;    /* Enable channel */
-        au_sync();
+        wmb(); /* drain writebuffer */
         cp->ddma_dbell = 0;
-        au_sync();
+        wmb(); /* drain writebuffer */
 }
 EXPORT_SYMBOL(au1xxx_dbdma_start);
 
@@ -832,7 +832,7 @@ u32 au1xxx_get_dma_residue(u32 chanid)
 
         /* This is only valid if the channel is stopped. */
         rv = cp->ddma_bytecnt;
-        au_sync();
+        wmb(); /* drain writebuffer */
 
         return rv;
 }
@@ -868,7 +868,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
         au1x_dma_chan_t *cp;
 
         intstat = dbdma_gptr->ddma_intstat;
-        au_sync();
+        wmb(); /* drain writebuffer */
         chan_index = __ffs(intstat);
 
         ctp = chan_tab_ptr[chan_index];
@@ -877,7 +877,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
 
         /* Reset interrupt. */
         cp->ddma_irq = 0;
-        au_sync();
+        wmb(); /* drain writebuffer */
 
         if (ctp->chan_callback)
                 ctp->chan_callback(irq, ctp->chan_callparam);
@@ -1061,7 +1061,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
         dbdma_gptr->ddma_config = 0;
         dbdma_gptr->ddma_throttle = 0;
         dbdma_gptr->ddma_inten = 0xffff;
-        au_sync();
+        wmb(); /* drain writebuffer */
 
         ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
         if (ret)
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 9b624e2c0fcf..4fb6207b883b 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -141,17 +141,17 @@ void dump_au1000_dma_channel(unsigned int dmanr)
 
         printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
         printk(KERN_INFO "  mode = 0x%08x\n",
-               au_readl(chan->io + DMA_MODE_SET));
+               __raw_readl(chan->io + DMA_MODE_SET));
         printk(KERN_INFO "  addr = 0x%08x\n",
-               au_readl(chan->io + DMA_PERIPHERAL_ADDR));
+               __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
         printk(KERN_INFO "  start0 = 0x%08x\n",
-               au_readl(chan->io + DMA_BUFFER0_START));
+               __raw_readl(chan->io + DMA_BUFFER0_START));
         printk(KERN_INFO "  start1 = 0x%08x\n",
-               au_readl(chan->io + DMA_BUFFER1_START));
+               __raw_readl(chan->io + DMA_BUFFER1_START));
         printk(KERN_INFO "  count0 = 0x%08x\n",
-               au_readl(chan->io + DMA_BUFFER0_COUNT));
+               __raw_readl(chan->io + DMA_BUFFER0_COUNT));
         printk(KERN_INFO "  count1 = 0x%08x\n",
-               au_readl(chan->io + DMA_BUFFER1_COUNT));
+               __raw_readl(chan->io + DMA_BUFFER1_COUNT));
 }
 
 /*
@@ -204,7 +204,8 @@ int request_au1000_dma(int dev_id, const char *dev_str,
         }
 
         /* fill it in */
-        chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN;
+        chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
+                        i * DMA_CHANNEL_LEN);
         chan->dev_id = dev_id;
         chan->dev_str = dev_str;
         chan->fifo_addr = dev->fifo_addr;
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index d664b11e0baf..754207071b58 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -645,54 +645,6 @@
 
 #include <asm/cpu.h>
 
-/* cpu pipeline flush */
-void static inline au_sync(void)
-{
-        __asm__ volatile ("sync");
-}
-
-void static inline au_sync_udelay(int us)
-{
-        __asm__ volatile ("sync");
-        udelay(us);
-}
-
-void static inline au_sync_delay(int ms)
-{
-        __asm__ volatile ("sync");
-        mdelay(ms);
-}
-
-void static inline au_writeb(u8 val, unsigned long reg)
-{
-        *(volatile u8 *)reg = val;
-}
-
-void static inline au_writew(u16 val, unsigned long reg)
-{
-        *(volatile u16 *)reg = val;
-}
-
-void static inline au_writel(u32 val, unsigned long reg)
-{
-        *(volatile u32 *)reg = val;
-}
-
-static inline u8 au_readb(unsigned long reg)
-{
-        return *(volatile u8 *)reg;
-}
-
-static inline u16 au_readw(unsigned long reg)
-{
-        return *(volatile u16 *)reg;
-}
-
-static inline u32 au_readl(unsigned long reg)
-{
-        return *(volatile u32 *)reg;
-}
-
 /* helpers to access the SYS_* registers */
 static inline unsigned long alchemy_rdsys(int regofs)
 {
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index 7cedca5a305c..0a0cd4270c6f 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -106,7 +106,7 @@ enum {
 struct dma_chan {
         int dev_id;             /* this channel is allocated if >= 0, */
                                 /* free otherwise */
-        unsigned int io;
+        void __iomem *io;
         const char *dev_str;
         int irq;
         void *irq_dev;
@@ -157,7 +157,7 @@ static inline void enable_dma_buffer0(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
+        __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
 }
 
 static inline void enable_dma_buffer1(unsigned int dmanr)
@@ -166,7 +166,7 @@ static inline void enable_dma_buffer1(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
+        __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
 }
 static inline void enable_dma_buffers(unsigned int dmanr)
 {
@@ -174,7 +174,7 @@ static inline void enable_dma_buffers(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
+        __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
 }
 
 static inline void start_dma(unsigned int dmanr)
@@ -183,7 +183,7 @@ static inline void start_dma(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_GO, chan->io + DMA_MODE_SET);
+        __raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
 }
 
 #define DMA_HALT_POLL 0x5000
@@ -195,11 +195,11 @@ static inline void halt_dma(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
+        __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
 
         /* Poll the halt bit */
         for (i = 0; i < DMA_HALT_POLL; i++)
-                if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
+                if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
                         break;
         if (i == DMA_HALT_POLL)
                 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
@@ -215,7 +215,7 @@ static inline void disable_dma(unsigned int dmanr)
         halt_dma(dmanr);
 
         /* Now we can disable the buffers */
-        au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
+        __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
 }
 
 static inline int dma_halted(unsigned int dmanr)
@@ -224,7 +224,7 @@ static inline int dma_halted(unsigned int dmanr)
 
         if (!chan)
                 return 1;
-        return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
+        return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
 }
 
 /* Initialize a DMA channel. */
@@ -239,14 +239,14 @@ static inline void init_dma(unsigned int dmanr)
         disable_dma(dmanr);
 
         /* Set device FIFO address */
-        au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
+        __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
 
         mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
         if (chan->irq)
                 mode |= DMA_IE;
 
-        au_writel(~mode, chan->io + DMA_MODE_CLEAR);
-        au_writel(mode,  chan->io + DMA_MODE_SET);
+        __raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
+        __raw_writel(mode,       chan->io + DMA_MODE_SET);
 }
 
 /*
@@ -283,7 +283,7 @@ static inline int get_dma_active_buffer(unsigned int dmanr)
 
         if (!chan)
                 return -1;
-        return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
+        return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
 }
 
 /*
@@ -304,7 +304,7 @@ static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
         if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
                 return;
 
-        au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
+        __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
 }
 
 /*
@@ -316,7 +316,7 @@ static inline void clear_dma_done0(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
+        __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
 }
 
 static inline void clear_dma_done1(unsigned int dmanr)
@@ -325,7 +325,7 @@ static inline void clear_dma_done1(unsigned int dmanr)
 
         if (!chan)
                 return;
-        au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
+        __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
 }
 
 /*
@@ -344,7 +344,7 @@ static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
 
         if (!chan)
                 return;
-        au_writel(a, chan->io + DMA_BUFFER0_START);
+        __raw_writel(a, chan->io + DMA_BUFFER0_START);
 }
 
 /*
@@ -356,7 +356,7 @@ static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
 
         if (!chan)
                 return;
-        au_writel(a, chan->io + DMA_BUFFER1_START);
+        __raw_writel(a, chan->io + DMA_BUFFER1_START);
 }
 
 
@@ -370,7 +370,7 @@ static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
         if (!chan)
                 return;
         count &= DMA_COUNT_MASK;
-        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
+        __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
 }
 
 /*
@@ -383,7 +383,7 @@ static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
         if (!chan)
                 return;
         count &= DMA_COUNT_MASK;
-        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
+        __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
 }
 
 /*
@@ -396,8 +396,8 @@ static inline void set_dma_count(unsigned int dmanr, unsigned int count)
         if (!chan)
                 return;
         count &= DMA_COUNT_MASK;
-        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
-        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
+        __raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
+        __raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
 }
 
 /*
@@ -410,7 +410,7 @@ static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
 
         if (!chan)
                 return 0;
-        return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
+        return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
 }
 
 
@@ -437,10 +437,10 @@ static inline int get_dma_residue(unsigned int dmanr)
         if (!chan)
                 return 0;
 
-        curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
+        curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
             DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
 
-        count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
+        count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
 
         if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
                 count <<= 1;