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authorViresh Kumar <viresh.kumar@st.com>2011-03-03 05:17:26 -0500
committerVinod Koul <vinod.koul@intel.com>2011-03-06 14:42:28 -0500
commit1c5b0538c719f52cface39f699fb5d39a50149d6 (patch)
treee06d61c874c41d50ee1f64393597385263f25dcf /arch
parente51dc53b8c7fa2d9ac4ef8f317f5dfe07a79e65a (diff)
avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize
Now that the dw_dmac DMA driver supports configurable Flow Controller, source and destination burst or msize, we need to specify which ones to use. Msize or burst size was previously hardcoded to 1, Flow controller was DMA for both M2P & P2M transfers. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index 2747cde8c9a7..b4aaebd8780c 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -2050,6 +2050,9 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2050 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2050 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2051 rx_dws->src_master = 0; 2051 rx_dws->src_master = 0;
2052 rx_dws->dst_master = 1; 2052 rx_dws->dst_master = 1;
2053 rx_dws->src_msize = DW_DMA_MSIZE_1;
2054 rx_dws->dst_msize = DW_DMA_MSIZE_1;
2055 rx_dws->fc = DW_DMA_FC_D_P2M;
2053 } 2056 }
2054 2057
2055 /* Check if DMA slave interface for playback should be configured. */ 2058 /* Check if DMA slave interface for playback should be configured. */
@@ -2060,6 +2063,9 @@ at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2060 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2063 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2061 rx_dws->src_master = 0; 2064 rx_dws->src_master = 0;
2062 rx_dws->dst_master = 1; 2065 rx_dws->dst_master = 1;
2066 tx_dws->src_msize = DW_DMA_MSIZE_1;
2067 tx_dws->dst_msize = DW_DMA_MSIZE_1;
2068 tx_dws->fc = DW_DMA_FC_D_M2P;
2063 } 2069 }
2064 2070
2065 if (platform_device_add_data(pdev, data, 2071 if (platform_device_add_data(pdev, data,
@@ -2134,6 +2140,9 @@ at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2134 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL); 2140 dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2135 dws->src_master = 0; 2141 dws->src_master = 0;
2136 dws->dst_master = 1; 2142 dws->dst_master = 1;
2143 dws->src_msize = DW_DMA_MSIZE_1;
2144 dws->dst_msize = DW_DMA_MSIZE_1;
2145 dws->fc = DW_DMA_FC_D_M2P;
2137 2146
2138 if (platform_device_add_data(pdev, data, 2147 if (platform_device_add_data(pdev, data,
2139 sizeof(struct atmel_abdac_pdata))) 2148 sizeof(struct atmel_abdac_pdata)))