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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-01 16:05:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-01 16:05:40 -0500
commit13dda80e48439b446d0bc9bab34b91484bc8f533 (patch)
treee8037122d65fe2a5dd8f633a7648b2597640a2ce /arch
parent379e3a820da171cb1d97e8dccd736a69cebfb7c0 (diff)
parent5f19daa16ffca55db5b0253eba2bd0f71ee7f7f4 (diff)
Merge branch 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci
* 'davinci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci: (40 commits) DaVinci DM365: Adding support for SPI EEPROM DaVinci DM365: Adding DM365 SPI support DaVinci DM355: Modifications to DM355 SPI support DaVinci: SPI: Adding header file for SPI support. davinci: dm646x: CDCE clocks: davinci_clk converted to clk_lookup davinci: clkdev cleanup: remove clk_lookup wrapper, use clkdev_add_table() DaVinci: DM365: Voice codec support for the DM365 SoC davinci: clock: let clk->set_rate function sleep Add SDA and SCL pin numbers to i2c platform data davinci: da8xx/omap-l1xx: Add EDMA platform data for da850/omap-l138 davinci: build list of unused EDMA events dynamically davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY case davinci: Keep count of channel controllers on a platform davinci: Correct return value of edma_alloc_channel api davinci: add CDCE949 support on DM6467 EVM davinci: add support for CDCE949 clock synthesizer davinci: da850/omap-l138 EVM: register for suspend support davinci: da850/omap-l138: add support for SoC suspend davinci: add power management support DaVinci: DM365: Changing default queue for DM365. ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/Kconfig4
-rw-r--r--arch/arm/mach-davinci/Makefile3
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c4
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c34
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c23
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c143
-rw-r--r--arch/arm/mach-davinci/cdce949.c293
-rw-r--r--arch/arm/mach-davinci/clock.c93
-rw-r--r--arch/arm/mach-davinci/clock.h45
-rw-r--r--arch/arm/mach-davinci/common.c2
-rw-r--r--arch/arm/mach-davinci/cpuidle.c38
-rw-r--r--arch/arm/mach-davinci/da830.c10
-rw-r--r--arch/arm/mach-davinci/da850.c90
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c146
-rw-r--r--arch/arm/mach-davinci/dm355.c49
-rw-r--r--arch/arm/mach-davinci/dm365.c111
-rw-r--r--arch/arm/mach-davinci/dm644x.c12
-rw-r--r--arch/arm/mach-davinci/dm646x.c14
-rw-r--r--arch/arm/mach-davinci/dma.c67
-rw-r--r--arch/arm/mach-davinci/include/mach/cdce949.h19
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/cpuidle.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h18
-rw-r--r--arch/arm/mach-davinci/include/mach/dm365.h9
-rw-r--r--arch/arm/mach-davinci/include/mach/dm644x.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/edma.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/emac.h36
-rw-r--r--arch/arm/mach-davinci/include/mach/i2c.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h5
-rw-r--r--arch/arm/mach-davinci/include/mach/mux.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/pm.h54
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h15
-rw-r--r--arch/arm/mach-davinci/include/mach/spi.h44
-rw-r--r--arch/arm/mach-davinci/include/mach/timex.h7
-rw-r--r--arch/arm/mach-davinci/pm.c158
-rw-r--r--arch/arm/mach-davinci/psc.c11
-rw-r--r--arch/arm/mach-davinci/sleep.S224
40 files changed, 1492 insertions, 309 deletions
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 033bfede6b67..0ebe185610bf 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -91,10 +91,14 @@ config MACH_DAVINCI_DM6467_EVM
91 bool "TI DM6467 EVM" 91 bool "TI DM6467 EVM"
92 default ARCH_DAVINCI_DM646x 92 default ARCH_DAVINCI_DM646x
93 depends on ARCH_DAVINCI_DM646x 93 depends on ARCH_DAVINCI_DM646x
94 select MACH_DAVINCI_DM6467TEVM
94 help 95 help
95 Configure this option to specify the whether the board used 96 Configure this option to specify the whether the board used
96 for development is a DM6467 EVM 97 for development is a DM6467 EVM
97 98
99config MACH_DAVINCI_DM6467TEVM
100 bool
101
98config MACH_DAVINCI_DM365_EVM 102config MACH_DAVINCI_DM365_EVM
99 bool "TI DM365 EVM" 103 bool "TI DM365 EVM"
100 default ARCH_DAVINCI_DM365 104 default ARCH_DAVINCI_DM365
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index eeb9230d8844..6aac880eb794 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
26obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o 26obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
27obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o 27obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o
28obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o 28obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o
29obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o 29obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM) += board-dm646x-evm.o cdce949.o
30obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o 30obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o
31obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o 31obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o
32obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o 32obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
@@ -34,3 +34,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o
34# Power Management 34# Power Management
35obj-$(CONFIG_CPU_FREQ) += cpufreq.o 35obj-$(CONFIG_CPU_FREQ) += cpufreq.o
36obj-$(CONFIG_CPU_IDLE) += cpuidle.o 36obj-$(CONFIG_CPU_IDLE) += cpuidle.o
37obj-$(CONFIG_SUSPEND) += pm.o sleep.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 31dc9901e556..dc19870b23cd 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -112,7 +112,7 @@ static __init void da830_evm_usb_init(void)
112 * Set up USB clock/mode in the CFGCHIP2 register. 112 * Set up USB clock/mode in the CFGCHIP2 register.
113 * FYI: CFGCHIP2 is 0x0000ef00 initially. 113 * FYI: CFGCHIP2 is 0x0000ef00 initially.
114 */ 114 */
115 cfgchip2 = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG)); 115 cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
116 116
117 /* USB2.0 PHY reference clock is 24 MHz */ 117 /* USB2.0 PHY reference clock is 24 MHz */
118 cfgchip2 &= ~CFGCHIP2_REFFREQ; 118 cfgchip2 &= ~CFGCHIP2_REFFREQ;
@@ -139,7 +139,7 @@ static __init void da830_evm_usb_init(void)
139 cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN; 139 cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
140#endif 140#endif
141 141
142 __raw_writel(cfgchip2, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG)); 142 __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
143 143
144 /* USB_REFCLKIN is not used. */ 144 /* USB_REFCLKIN is not used. */
145 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); 145 ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 07de8db14581..411284d0b0fa 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -46,8 +46,20 @@
46 46
47static struct mtd_partition da850_evm_norflash_partition[] = { 47static struct mtd_partition da850_evm_norflash_partition[] = {
48 { 48 {
49 .name = "NOR filesystem", 49 .name = "bootloaders + env",
50 .offset = 0, 50 .offset = 0,
51 .size = SZ_512K,
52 .mask_flags = MTD_WRITEABLE,
53 },
54 {
55 .name = "kernel",
56 .offset = MTDPART_OFS_APPEND,
57 .size = SZ_2M,
58 .mask_flags = 0,
59 },
60 {
61 .name = "filesystem",
62 .offset = MTDPART_OFS_APPEND,
51 .size = MTDPART_SIZ_FULL, 63 .size = MTDPART_SIZ_FULL,
52 .mask_flags = 0, 64 .mask_flags = 0,
53 }, 65 },
@@ -77,6 +89,18 @@ static struct platform_device da850_evm_norflash_device = {
77 .resource = da850_evm_norflash_resource, 89 .resource = da850_evm_norflash_resource,
78}; 90};
79 91
92static struct davinci_pm_config da850_pm_pdata = {
93 .sleepcount = 128,
94};
95
96static struct platform_device da850_pm_device = {
97 .name = "pm-davinci",
98 .dev = {
99 .platform_data = &da850_pm_pdata,
100 },
101 .id = -1,
102};
103
80/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash 104/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
81 * (128K blocks). It may be used instead of the (default) SPI flash 105 * (128K blocks). It may be used instead of the (default) SPI flash
82 * to boot, using TI's tools to install the secondary boot loader 106 * to boot, using TI's tools to install the secondary boot loader
@@ -119,6 +143,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = {
119 .parts = da850_evm_nandflash_partition, 143 .parts = da850_evm_nandflash_partition,
120 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), 144 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition),
121 .ecc_mode = NAND_ECC_HW, 145 .ecc_mode = NAND_ECC_HW,
146 .ecc_bits = 4,
122 .options = NAND_USE_FLASH_BBT, 147 .options = NAND_USE_FLASH_BBT,
123}; 148};
124 149
@@ -537,7 +562,7 @@ static int __init da850_evm_config_emac(void)
537 if (!machine_is_davinci_da850_evm()) 562 if (!machine_is_davinci_da850_evm())
538 return 0; 563 return 0;
539 564
540 cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG); 565 cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
541 566
542 val = __raw_readl(cfg_chip3_base); 567 val = __raw_readl(cfg_chip3_base);
543 568
@@ -696,6 +721,11 @@ static __init void da850_evm_init(void)
696 if (ret) 721 if (ret)
697 pr_warning("da850_evm_init: cpuidle registration failed: %d\n", 722 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
698 ret); 723 ret);
724
725 ret = da850_register_pm(&da850_pm_device);
726 if (ret)
727 pr_warning("da850_evm_init: suspend registration failed: %d\n",
728 ret);
699} 729}
700 730
701#ifdef CONFIG_SERIAL_8250_CONSOLE 731#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 077ecf4fecda..aa48e3f69715 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -111,6 +111,8 @@ static struct platform_device davinci_nand_device = {
111static struct davinci_i2c_platform_data i2c_pdata = { 111static struct davinci_i2c_platform_data i2c_pdata = {
112 .bus_freq = 400 /* kHz */, 112 .bus_freq = 400 /* kHz */,
113 .bus_delay = 0 /* usec */, 113 .bus_delay = 0 /* usec */,
114 .sda_pin = 15,
115 .scl_pin = 14,
114}; 116};
115 117
116static struct snd_platform_data dm355_evm_snd_data; 118static struct snd_platform_data dm355_evm_snd_data;
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 38e9033d2e86..d15beceb632e 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -24,6 +24,8 @@
24#include <linux/mtd/partitions.h> 24#include <linux/mtd/partitions.h>
25#include <linux/mtd/nand.h> 25#include <linux/mtd/nand.h>
26#include <linux/input.h> 26#include <linux/input.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/eeprom.h>
27 29
28#include <asm/mach-types.h> 30#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
@@ -571,6 +573,24 @@ static void __init dm365_evm_map_io(void)
571 dm365_init(); 573 dm365_init();
572} 574}
573 575
576static struct spi_eeprom at25640 = {
577 .byte_len = SZ_64K / 8,
578 .name = "at25640",
579 .page_size = 32,
580 .flags = EE_ADDR2,
581};
582
583static struct spi_board_info dm365_evm_spi_info[] __initconst = {
584 {
585 .modalias = "at25",
586 .platform_data = &at25640,
587 .max_speed_hz = 10 * 1000 * 1000,
588 .bus_num = 0,
589 .chip_select = 0,
590 .mode = SPI_MODE_0,
591 },
592};
593
574static __init void dm365_evm_init(void) 594static __init void dm365_evm_init(void)
575{ 595{
576 evm_init_i2c(); 596 evm_init_i2c();
@@ -587,6 +607,9 @@ static __init void dm365_evm_init(void)
587 dm365_init_asp(&dm365_evm_snd_data); 607 dm365_init_asp(&dm365_evm_snd_data);
588 dm365_init_rtc(); 608 dm365_init_rtc();
589 dm365_init_ks(&dm365evm_ks_data); 609 dm365_init_ks(&dm365evm_ks_data);
610
611 dm365_init_spi0(BIT(0), dm365_evm_spi_info,
612 ARRAY_SIZE(dm365_evm_spi_info));
590} 613}
591 614
592static __init void dm365_evm_irq_init(void) 615static __init void dm365_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index e9612cf727b7..976e11b7fa4a 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -629,6 +629,8 @@ static struct i2c_board_info __initdata i2c_info[] = {
629static struct davinci_i2c_platform_data i2c_pdata = { 629static struct davinci_i2c_platform_data i2c_pdata = {
630 .bus_freq = 20 /* kHz */, 630 .bus_freq = 20 /* kHz */,
631 .bus_delay = 100 /* usec */, 631 .bus_delay = 100 /* usec */,
632 .sda_pin = 44,
633 .scl_pin = 43,
632}; 634};
633 635
634static void __init evm_init_i2c(void) 636static void __init evm_init_i2c(void)
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 8d0b0e01c59b..5ba3cb2daaa0 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -30,6 +30,7 @@
30#include <linux/mtd/mtd.h> 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h> 31#include <linux/mtd/nand.h>
32#include <linux/mtd/partitions.h> 32#include <linux/mtd/partitions.h>
33#include <linux/clk.h>
33 34
34#include <asm/mach-types.h> 35#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
@@ -39,54 +40,13 @@
39#include <mach/serial.h> 40#include <mach/serial.h>
40#include <mach/i2c.h> 41#include <mach/i2c.h>
41#include <mach/nand.h> 42#include <mach/nand.h>
43#include <mach/clock.h>
44#include <mach/cdce949.h>
42 45
43#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \ 46#include "clock.h"
44 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
45#define HAS_ATA 1
46#else
47#define HAS_ATA 0
48#endif
49
50#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
51#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
52 47
53#define NAND_BLOCK_SIZE SZ_128K 48#define NAND_BLOCK_SIZE SZ_128K
54 49
55/* CPLD Register 0 bits to control ATA */
56#define DM646X_EVM_ATA_RST BIT(0)
57#define DM646X_EVM_ATA_PWD BIT(1)
58
59#define DM646X_EVM_PHY_MASK (0x2)
60#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
61
62#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
63#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
64#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
65#define VCH2CLK_SYSCLK8 (BIT(9))
66#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
67#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
68#define VCH3CLK_SYSCLK8 (BIT(13))
69#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
70
71#define VIDCH2CLK (BIT(10))
72#define VIDCH3CLK (BIT(11))
73#define VIDCH1CLK (BIT(4))
74#define TVP7002_INPUT (BIT(4))
75#define TVP5147_INPUT (~BIT(4))
76#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
77#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
78#define TVP5147_CH0 "tvp514x-0"
79#define TVP5147_CH1 "tvp514x-1"
80
81static void __iomem *vpif_vidclkctl_reg;
82static void __iomem *vpif_vsclkdis_reg;
83/* spin lock for updating above registers */
84static spinlock_t vpif_reg_lock;
85
86static struct davinci_uart_config uart_config __initdata = {
87 .enabled_uarts = (1 << 0),
88};
89
90/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot 50/* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
91 * and U-Boot environment this avoids dependency on any particular combination 51 * and U-Boot environment this avoids dependency on any particular combination
92 * of UBL, U-Boot or flashing tools etc. 52 * of UBL, U-Boot or flashing tools etc.
@@ -120,6 +80,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
120 .options = 0, 80 .options = 0,
121}; 81};
122 82
83#define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x20008000
84#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
85
123static struct resource davinci_nand_resources[] = { 86static struct resource davinci_nand_resources[] = {
124 { 87 {
125 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE, 88 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
@@ -144,6 +107,17 @@ static struct platform_device davinci_nand_device = {
144 }, 107 },
145}; 108};
146 109
110#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
111 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
112#define HAS_ATA 1
113#else
114#define HAS_ATA 0
115#endif
116
117/* CPLD Register 0 bits to control ATA */
118#define DM646X_EVM_ATA_RST BIT(0)
119#define DM646X_EVM_ATA_PWD BIT(1)
120
147/* CPLD Register 0 Client: used for I/O Control */ 121/* CPLD Register 0 Client: used for I/O Control */
148static int cpld_reg0_probe(struct i2c_client *client, 122static int cpld_reg0_probe(struct i2c_client *client,
149 const struct i2c_device_id *id) 123 const struct i2c_device_id *id)
@@ -417,6 +391,9 @@ static struct i2c_board_info __initdata i2c_info[] = {
417 { 391 {
418 I2C_BOARD_INFO("cpld_video", 0x3b), 392 I2C_BOARD_INFO("cpld_video", 0x3b),
419 }, 393 },
394 {
395 I2C_BOARD_INFO("cdce949", 0x6c),
396 },
420}; 397};
421 398
422static struct davinci_i2c_platform_data i2c_pdata = { 399static struct davinci_i2c_platform_data i2c_pdata = {
@@ -424,6 +401,30 @@ static struct davinci_i2c_platform_data i2c_pdata = {
424 .bus_delay = 0 /* usec */, 401 .bus_delay = 0 /* usec */,
425}; 402};
426 403
404#define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
405#define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
406#define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
407#define VCH2CLK_SYSCLK8 (BIT(9))
408#define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
409#define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
410#define VCH3CLK_SYSCLK8 (BIT(13))
411#define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
412
413#define VIDCH2CLK (BIT(10))
414#define VIDCH3CLK (BIT(11))
415#define VIDCH1CLK (BIT(4))
416#define TVP7002_INPUT (BIT(4))
417#define TVP5147_INPUT (~BIT(4))
418#define VPIF_INPUT_ONE_CHANNEL (BIT(5))
419#define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
420#define TVP5147_CH0 "tvp514x-0"
421#define TVP5147_CH1 "tvp514x-1"
422
423static void __iomem *vpif_vidclkctl_reg;
424static void __iomem *vpif_vsclkdis_reg;
425/* spin lock for updating above registers */
426static spinlock_t vpif_reg_lock;
427
427static int set_vpif_clock(int mux_mode, int hd) 428static int set_vpif_clock(int mux_mode, int hd)
428{ 429{
429 unsigned long flags; 430 unsigned long flags;
@@ -685,11 +686,44 @@ static void __init evm_init_i2c(void)
685 evm_init_video(); 686 evm_init_video();
686} 687}
687 688
689#define CDCE949_XIN_RATE 27000000
690
691/* CDCE949 support - "lpsc" field is overridden to work as clock number */
692static struct clk cdce_clk_in = {
693 .name = "cdce_xin",
694 .rate = CDCE949_XIN_RATE,
695};
696
697static struct clk_lookup cdce_clks[] = {
698 CLK(NULL, "xin", &cdce_clk_in),
699 CLK(NULL, NULL, NULL),
700};
701
702static void __init cdce_clk_init(void)
703{
704 struct clk_lookup *c;
705 struct clk *clk;
706
707 for (c = cdce_clks; c->clk; c++) {
708 clk = c->clk;
709 clkdev_add(c);
710 clk_register(clk);
711 }
712}
713
688static void __init davinci_map_io(void) 714static void __init davinci_map_io(void)
689{ 715{
690 dm646x_init(); 716 dm646x_init();
717 cdce_clk_init();
691} 718}
692 719
720static struct davinci_uart_config uart_config __initdata = {
721 .enabled_uarts = (1 << 0),
722};
723
724#define DM646X_EVM_PHY_MASK (0x2)
725#define DM646X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
726
693static __init void evm_init(void) 727static __init void evm_init(void)
694{ 728{
695 struct davinci_soc_info *soc_info = &davinci_soc_info; 729 struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -713,6 +747,17 @@ static __init void davinci_dm646x_evm_irq_init(void)
713 davinci_irq_init(); 747 davinci_irq_init();
714} 748}
715 749
750#define DM646X_EVM_REF_FREQ 27000000
751#define DM6467T_EVM_REF_FREQ 33000000
752
753void __init dm646x_board_setup_refclk(struct clk *clk)
754{
755 if (machine_is_davinci_dm6467tevm())
756 clk->rate = DM6467T_EVM_REF_FREQ;
757 else
758 clk->rate = DM646X_EVM_REF_FREQ;
759}
760
716MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") 761MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
717 .phys_io = IO_PHYS, 762 .phys_io = IO_PHYS,
718 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc, 763 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
@@ -723,3 +768,13 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
723 .init_machine = evm_init, 768 .init_machine = evm_init,
724MACHINE_END 769MACHINE_END
725 770
771MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
772 .phys_io = IO_PHYS,
773 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
774 .boot_params = (0x80000100),
775 .map_io = davinci_map_io,
776 .init_irq = davinci_dm646x_evm_irq_init,
777 .timer = &davinci_timer,
778 .init_machine = evm_init,
779MACHINE_END
780
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
new file mode 100644
index 000000000000..aec375690543
--- /dev/null
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -0,0 +1,293 @@
1/*
2 * TI CDCE949 clock synthesizer driver
3 *
4 * Note: This implementation assumes an input of 27MHz to the CDCE.
5 * This is by no means constrained by CDCE hardware although the datasheet
6 * does use this as an example for all illustrations and more importantly:
7 * that is the crystal input on boards it is currently used on.
8 *
9 * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20
21#include <mach/clock.h>
22
23#include "clock.h"
24
25static struct i2c_client *cdce_i2c_client;
26static DEFINE_MUTEX(cdce_mutex);
27
28/* CDCE register descriptor */
29struct cdce_reg {
30 u8 addr;
31 u8 val;
32};
33
34/* Per-Output (Y1, Y2 etc.) frequency descriptor */
35struct cdce_freq {
36 /* Frequency in KHz */
37 unsigned long frequency;
38 /*
39 * List of registers to program to obtain a particular frequency.
40 * 0x0 in register address and value is the end of list marker.
41 */
42 struct cdce_reg *reglist;
43};
44
45#define CDCE_FREQ_TABLE_ENTRY(line, out) \
46{ \
47 .reglist = cdce_y ##line## _ ##out, \
48 .frequency = out, \
49}
50
51/* List of CDCE outputs */
52struct cdce_output {
53 /* List of frequencies on this output */
54 struct cdce_freq *freq_table;
55 /* Number of possible frequencies */
56 int size;
57};
58
59/*
60 * Finding out the values to program into CDCE949 registers for a particular
61 * frequency output is not a simple calculation. Have a look at the datasheet
62 * for the details. There is desktop software available to help users with
63 * the calculations. Here, we just depend on the output of that software
64 * (or hand calculations) instead trying to runtime calculate the register
65 * values and inflicting misery on ourselves.
66 */
67static struct cdce_reg cdce_y1_148500[] = {
68 { 0x13, 0x00 },
69 /* program PLL1_0 multiplier */
70 { 0x18, 0xaf },
71 { 0x19, 0x50 },
72 { 0x1a, 0x02 },
73 { 0x1b, 0xc9 },
74 /* program PLL1_11 multiplier */
75 { 0x1c, 0x00 },
76 { 0x1d, 0x40 },
77 { 0x1e, 0x02 },
78 { 0x1f, 0xc9 },
79 /* output state selection */
80 { 0x15, 0x00 },
81 { 0x14, 0xef },
82 /* switch MUX to PLL1 output */
83 { 0x14, 0x6f },
84 { 0x16, 0x06 },
85 /* set P2DIV divider, P3DIV and input crystal */
86 { 0x17, 0x06 },
87 { 0x01, 0x00 },
88 { 0x05, 0x48 },
89 { 0x02, 0x80 },
90 /* enable and disable PLL */
91 { 0x02, 0xbc },
92 { 0x03, 0x01 },
93 { },
94};
95
96static struct cdce_reg cdce_y1_74250[] = {
97 { 0x13, 0x00 },
98 { 0x18, 0xaf },
99 { 0x19, 0x50 },
100 { 0x1a, 0x02 },
101 { 0x1b, 0xc9 },
102 { 0x1c, 0x00 },
103 { 0x1d, 0x40 },
104 { 0x1e, 0x02 },
105 { 0x1f, 0xc9 },
106 /* output state selection */
107 { 0x15, 0x00 },
108 { 0x14, 0xef },
109 /* switch MUX to PLL1 output */
110 { 0x14, 0x6f },
111 { 0x16, 0x06 },
112 /* set P2DIV divider, P3DIV and input crystal */
113 { 0x17, 0x06 },
114 { 0x01, 0x00 },
115 { 0x05, 0x48 },
116 { 0x02, 0x80 },
117 /* enable and disable PLL */
118 { 0x02, 0xbc },
119 { 0x03, 0x02 },
120 { },
121};
122
123static struct cdce_reg cdce_y1_27000[] = {
124 { 0x13, 0x00 },
125 { 0x18, 0x00 },
126 { 0x19, 0x40 },
127 { 0x1a, 0x02 },
128 { 0x1b, 0x08 },
129 { 0x1c, 0x00 },
130 { 0x1d, 0x40 },
131 { 0x1e, 0x02 },
132 { 0x1f, 0x08 },
133 { 0x15, 0x02 },
134 { 0x14, 0xed },
135 { 0x16, 0x01 },
136 { 0x17, 0x01 },
137 { 0x01, 0x00 },
138 { 0x05, 0x50 },
139 { 0x02, 0xb4 },
140 { 0x03, 0x01 },
141 { },
142};
143
144static struct cdce_freq cdce_y1_freqs[] = {
145 CDCE_FREQ_TABLE_ENTRY(1, 148500),
146 CDCE_FREQ_TABLE_ENTRY(1, 74250),
147 CDCE_FREQ_TABLE_ENTRY(1, 27000),
148};
149
150static struct cdce_reg cdce_y5_13500[] = {
151 { 0x27, 0x08 },
152 { 0x28, 0x00 },
153 { 0x29, 0x40 },
154 { 0x2a, 0x02 },
155 { 0x2b, 0x08 },
156 { 0x24, 0x6f },
157 { },
158};
159
160static struct cdce_reg cdce_y5_16875[] = {
161 { 0x27, 0x08 },
162 { 0x28, 0x9f },
163 { 0x29, 0xb0 },
164 { 0x2a, 0x02 },
165 { 0x2b, 0x89 },
166 { 0x24, 0x6f },
167 { },
168};
169
170static struct cdce_reg cdce_y5_27000[] = {
171 { 0x27, 0x04 },
172 { 0x28, 0x00 },
173 { 0x29, 0x40 },
174 { 0x2a, 0x02 },
175 { 0x2b, 0x08 },
176 { 0x24, 0x6f },
177 { },
178};
179static struct cdce_reg cdce_y5_54000[] = {
180 { 0x27, 0x04 },
181 { 0x28, 0xff },
182 { 0x29, 0x80 },
183 { 0x2a, 0x02 },
184 { 0x2b, 0x07 },
185 { 0x24, 0x6f },
186 { },
187};
188
189static struct cdce_reg cdce_y5_81000[] = {
190 { 0x27, 0x02 },
191 { 0x28, 0xbf },
192 { 0x29, 0xa0 },
193 { 0x2a, 0x03 },
194 { 0x2b, 0x0a },
195 { 0x24, 0x6f },
196 { },
197};
198
199static struct cdce_freq cdce_y5_freqs[] = {
200 CDCE_FREQ_TABLE_ENTRY(5, 13500),
201 CDCE_FREQ_TABLE_ENTRY(5, 16875),
202 CDCE_FREQ_TABLE_ENTRY(5, 27000),
203 CDCE_FREQ_TABLE_ENTRY(5, 54000),
204 CDCE_FREQ_TABLE_ENTRY(5, 81000),
205};
206
207
208static struct cdce_output output_list[] = {
209 [1] = { cdce_y1_freqs, ARRAY_SIZE(cdce_y1_freqs) },
210 [5] = { cdce_y5_freqs, ARRAY_SIZE(cdce_y5_freqs) },
211};
212
213int cdce_set_rate(struct clk *clk, unsigned long rate)
214{
215 int i, ret = 0;
216 struct cdce_freq *freq_table = output_list[clk->lpsc].freq_table;
217 struct cdce_reg *regs = NULL;
218
219 if (!cdce_i2c_client)
220 return -ENODEV;
221
222 if (!freq_table)
223 return -EINVAL;
224
225 for (i = 0; i < output_list[clk->lpsc].size; i++) {
226 if (freq_table[i].frequency == rate / 1000) {
227 regs = freq_table[i].reglist;
228 break;
229 }
230 }
231
232 if (!regs)
233 return -EINVAL;
234
235 mutex_lock(&cdce_mutex);
236 for (i = 0; regs[i].addr; i++) {
237 ret = i2c_smbus_write_byte_data(cdce_i2c_client,
238 regs[i].addr | 0x80, regs[i].val);
239 if (ret)
240 break;
241 }
242 mutex_unlock(&cdce_mutex);
243
244 if (!ret)
245 clk->rate = rate;
246
247 return ret;
248}
249
250static int cdce_probe(struct i2c_client *client,
251 const struct i2c_device_id *id)
252{
253 cdce_i2c_client = client;
254 return 0;
255}
256
257static int __devexit cdce_remove(struct i2c_client *client)
258{
259 cdce_i2c_client = NULL;
260 return 0;
261}
262
263static const struct i2c_device_id cdce_id[] = {
264 {"cdce949", 0},
265 {},
266};
267MODULE_DEVICE_TABLE(i2c, cdce_id);
268
269static struct i2c_driver cdce_driver = {
270 .driver = {
271 .owner = THIS_MODULE,
272 .name = "cdce949",
273 },
274 .probe = cdce_probe,
275 .remove = __devexit_p(cdce_remove),
276 .id_table = cdce_id,
277};
278
279static int __init cdce_init(void)
280{
281 return i2c_add_driver(&cdce_driver);
282}
283subsys_initcall(cdce_init);
284
285static void __exit cdce_exit(void)
286{
287 i2c_del_driver(&cdce_driver);
288}
289module_exit(cdce_exit);
290
291MODULE_AUTHOR("Texas Instruments");
292MODULE_DESCRIPTION("CDCE949 clock synthesizer driver");
293MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index baece65cb9c0..bf6218ee94e1 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -49,7 +49,8 @@ static void __clk_disable(struct clk *clk)
49{ 49{
50 if (WARN_ON(clk->usecount == 0)) 50 if (WARN_ON(clk->usecount == 0))
51 return; 51 return;
52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL)) 52 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
53 (clk->flags & CLK_PSC))
53 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0); 54 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
54 if (clk->parent) 55 if (clk->parent)
55 __clk_disable(clk->parent); 56 __clk_disable(clk->parent);
@@ -124,9 +125,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
124 if (clk == NULL || IS_ERR(clk)) 125 if (clk == NULL || IS_ERR(clk))
125 return ret; 126 return ret;
126 127
127 spin_lock_irqsave(&clockfw_lock, flags);
128 if (clk->set_rate) 128 if (clk->set_rate)
129 ret = clk->set_rate(clk, rate); 129 ret = clk->set_rate(clk, rate);
130
131 spin_lock_irqsave(&clockfw_lock, flags);
130 if (ret == 0) { 132 if (ret == 0) {
131 if (clk->recalc) 133 if (clk->recalc)
132 clk->rate = clk->recalc(clk); 134 clk->rate = clk->recalc(clk);
@@ -363,6 +365,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
363{ 365{
364 u32 ctrl; 366 u32 ctrl;
365 unsigned int locktime; 367 unsigned int locktime;
368 unsigned long flags;
366 369
367 if (pll->base == NULL) 370 if (pll->base == NULL)
368 return -EINVAL; 371 return -EINVAL;
@@ -376,25 +379,23 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
376 locktime = ((2000 * prediv) / 100); 379 locktime = ((2000 * prediv) / 100);
377 prediv = (prediv - 1) | PLLDIV_EN; 380 prediv = (prediv - 1) | PLLDIV_EN;
378 } else { 381 } else {
379 locktime = 20; 382 locktime = PLL_LOCK_TIME;
380 } 383 }
381 if (postdiv) 384 if (postdiv)
382 postdiv = (postdiv - 1) | PLLDIV_EN; 385 postdiv = (postdiv - 1) | PLLDIV_EN;
383 if (mult) 386 if (mult)
384 mult = mult - 1; 387 mult = mult - 1;
385 388
389 /* Protect against simultaneous calls to PLL setting seqeunce */
390 spin_lock_irqsave(&clockfw_lock, flags);
391
386 ctrl = __raw_readl(pll->base + PLLCTL); 392 ctrl = __raw_readl(pll->base + PLLCTL);
387 393
388 /* Switch the PLL to bypass mode */ 394 /* Switch the PLL to bypass mode */
389 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); 395 ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
390 __raw_writel(ctrl, pll->base + PLLCTL); 396 __raw_writel(ctrl, pll->base + PLLCTL);
391 397
392 /* 398 udelay(PLL_BYPASS_TIME);
393 * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
394 * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
395 * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
396 */
397 udelay(1);
398 399
399 /* Reset and enable PLL */ 400 /* Reset and enable PLL */
400 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS); 401 ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
@@ -408,11 +409,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
408 if (pll->flags & PLL_HAS_POSTDIV) 409 if (pll->flags & PLL_HAS_POSTDIV)
409 __raw_writel(postdiv, pll->base + POSTDIV); 410 __raw_writel(postdiv, pll->base + POSTDIV);
410 411
411 /* 412 udelay(PLL_RESET_TIME);
412 * Wait for PLL to reset properly, OMAP-L138 datasheet says
413 * 'min' time = 125ns
414 */
415 udelay(1);
416 413
417 /* Bring PLL out of reset */ 414 /* Bring PLL out of reset */
418 ctrl |= PLLCTL_PLLRST; 415 ctrl |= PLLCTL_PLLRST;
@@ -424,17 +421,20 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
424 ctrl |= PLLCTL_PLLEN; 421 ctrl |= PLLCTL_PLLEN;
425 __raw_writel(ctrl, pll->base + PLLCTL); 422 __raw_writel(ctrl, pll->base + PLLCTL);
426 423
424 spin_unlock_irqrestore(&clockfw_lock, flags);
425
427 return 0; 426 return 0;
428} 427}
429EXPORT_SYMBOL(davinci_set_pllrate); 428EXPORT_SYMBOL(davinci_set_pllrate);
430 429
431int __init davinci_clk_init(struct davinci_clk *clocks) 430int __init davinci_clk_init(struct clk_lookup *clocks)
432 { 431 {
433 struct davinci_clk *c; 432 struct clk_lookup *c;
434 struct clk *clk; 433 struct clk *clk;
434 size_t num_clocks = 0;
435 435
436 for (c = clocks; c->lk.clk; c++) { 436 for (c = clocks; c->clk; c++) {
437 clk = c->lk.clk; 437 clk = c->clk;
438 438
439 if (!clk->recalc) { 439 if (!clk->recalc) {
440 440
@@ -457,35 +457,23 @@ int __init davinci_clk_init(struct davinci_clk *clocks)
457 if (clk->lpsc) 457 if (clk->lpsc)
458 clk->flags |= CLK_PSC; 458 clk->flags |= CLK_PSC;
459 459
460 clkdev_add(&c->lk);
461 clk_register(clk); 460 clk_register(clk);
461 num_clocks++;
462 462
463 /* Turn on clocks that Linux doesn't otherwise manage */ 463 /* Turn on clocks that Linux doesn't otherwise manage */
464 if (clk->flags & ALWAYS_ENABLED) 464 if (clk->flags & ALWAYS_ENABLED)
465 clk_enable(clk); 465 clk_enable(clk);
466 } 466 }
467 467
468 return 0; 468 clkdev_add_table(clocks, num_clocks);
469}
470
471#ifdef CONFIG_PROC_FS
472#include <linux/proc_fs.h>
473#include <linux/seq_file.h>
474 469
475static void *davinci_ck_start(struct seq_file *m, loff_t *pos) 470 return 0;
476{
477 return *pos < 1 ? (void *)1 : NULL;
478} 471}
479 472
480static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos) 473#ifdef CONFIG_DEBUG_FS
481{
482 ++*pos;
483 return NULL;
484}
485 474
486static void davinci_ck_stop(struct seq_file *m, void *v) 475#include <linux/debugfs.h>
487{ 476#include <linux/seq_file.h>
488}
489 477
490#define CLKNAME_MAX 10 /* longest clock name */ 478#define CLKNAME_MAX 10 /* longest clock name */
491#define NEST_DELTA 2 479#define NEST_DELTA 2
@@ -525,41 +513,38 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
525 513
526static int davinci_ck_show(struct seq_file *m, void *v) 514static int davinci_ck_show(struct seq_file *m, void *v)
527{ 515{
528 /* Show clock tree; we know the main oscillator is first. 516 struct clk *clk;
529 * We trust nonzero usecounts equate to PSC enables... 517
518 /*
519 * Show clock tree; We trust nonzero usecounts equate to PSC enables...
530 */ 520 */
531 mutex_lock(&clocks_mutex); 521 mutex_lock(&clocks_mutex);
532 if (!list_empty(&clocks)) 522 list_for_each_entry(clk, &clocks, node)
533 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node)); 523 if (!clk->parent)
524 dump_clock(m, 0, clk);
534 mutex_unlock(&clocks_mutex); 525 mutex_unlock(&clocks_mutex);
535 526
536 return 0; 527 return 0;
537} 528}
538 529
539static const struct seq_operations davinci_ck_op = {
540 .start = davinci_ck_start,
541 .next = davinci_ck_next,
542 .stop = davinci_ck_stop,
543 .show = davinci_ck_show
544};
545
546static int davinci_ck_open(struct inode *inode, struct file *file) 530static int davinci_ck_open(struct inode *inode, struct file *file)
547{ 531{
548 return seq_open(file, &davinci_ck_op); 532 return single_open(file, davinci_ck_show, NULL);
549} 533}
550 534
551static const struct file_operations proc_davinci_ck_operations = { 535static const struct file_operations davinci_ck_operations = {
552 .open = davinci_ck_open, 536 .open = davinci_ck_open,
553 .read = seq_read, 537 .read = seq_read,
554 .llseek = seq_lseek, 538 .llseek = seq_lseek,
555 .release = seq_release, 539 .release = single_release,
556}; 540};
557 541
558static int __init davinci_ck_proc_init(void) 542static int __init davinci_clk_debugfs_init(void)
559{ 543{
560 proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations); 544 debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
545 &davinci_ck_operations);
561 return 0; 546 return 0;
562 547
563} 548}
564__initcall(davinci_ck_proc_init); 549device_initcall(davinci_clk_debugfs_init);
565#endif /* CONFIG_DEBUG_PROC_FS */ 550#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index c92d77a3008d..aa0a61150325 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -12,9 +12,6 @@
12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H 12#ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13#define __ARCH_ARM_DAVINCI_CLOCK_H 13#define __ARCH_ARM_DAVINCI_CLOCK_H
14 14
15#include <linux/list.h>
16#include <asm/clkdev.h>
17
18#define DAVINCI_PLL1_BASE 0x01c40800 15#define DAVINCI_PLL1_BASE 0x01c40800
19#define DAVINCI_PLL2_BASE 0x01c40c00 16#define DAVINCI_PLL2_BASE 0x01c40c00
20#define MAX_PLL 2 17#define MAX_PLL 2
@@ -53,6 +50,26 @@
53#define PLLDIV_EN BIT(15) 50#define PLLDIV_EN BIT(15)
54#define PLLDIV_RATIO_MASK 0x1f 51#define PLLDIV_RATIO_MASK 0x1f
55 52
53/*
54 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
55 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
56 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
57 * is ~25MHz. Units are micro seconds.
58 */
59#define PLL_BYPASS_TIME 1
60/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
61#define PLL_RESET_TIME 1
62/*
63 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
64 * Units are micro seconds.
65 */
66#define PLL_LOCK_TIME 20
67
68#ifndef __ASSEMBLER__
69
70#include <linux/list.h>
71#include <asm/clkdev.h>
72
56struct pll_data { 73struct pll_data {
57 u32 phys_base; 74 u32 phys_base;
58 void __iomem *base; 75 void __iomem *base;
@@ -89,23 +106,19 @@ struct clk {
89#define CLK_PLL BIT(4) /* PLL-derived clock */ 106#define CLK_PLL BIT(4) /* PLL-derived clock */
90#define PRE_PLL BIT(5) /* source is before PLL mult/div */ 107#define PRE_PLL BIT(5) /* source is before PLL mult/div */
91 108
92struct davinci_clk { 109#define CLK(dev, con, ck) \
93 struct clk_lookup lk; 110 { \
94}; 111 .dev_id = dev, \
95 112 .con_id = con, \
96#define CLK(dev, con, ck) \ 113 .clk = ck, \
97 { \ 114 } \
98 .lk = { \
99 .dev_id = dev, \
100 .con_id = con, \
101 .clk = ck, \
102 }, \
103 }
104 115
105int davinci_clk_init(struct davinci_clk *clocks); 116int davinci_clk_init(struct clk_lookup *clocks);
106int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv, 117int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
107 unsigned int mult, unsigned int postdiv); 118 unsigned int mult, unsigned int postdiv);
108 119
109extern struct platform_device davinci_wdt_device; 120extern struct platform_device davinci_wdt_device;
110 121
111#endif 122#endif
123
124#endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index c2de94cde56a..94f27cbcd55a 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -11,13 +11,13 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/etherdevice.h> 13#include <linux/etherdevice.h>
14#include <linux/davinci_emac.h>
14 15
15#include <asm/tlb.h> 16#include <asm/tlb.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
17 18
18#include <mach/common.h> 19#include <mach/common.h>
19#include <mach/cputype.h> 20#include <mach/cputype.h>
20#include <mach/emac.h>
21 21
22#include "clock.h" 22#include "clock.h"
23 23
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 97a90f36fc92..bd59f31b8a95 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -19,6 +19,7 @@
19#include <asm/proc-fns.h> 19#include <asm/proc-fns.h>
20 20
21#include <mach/cpuidle.h> 21#include <mach/cpuidle.h>
22#include <mach/memory.h>
22 23
23#define DAVINCI_CPUIDLE_MAX_STATES 2 24#define DAVINCI_CPUIDLE_MAX_STATES 2
24 25
@@ -39,10 +40,6 @@ static struct cpuidle_driver davinci_idle_driver = {
39static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device); 40static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
40static void __iomem *ddr2_reg_base; 41static void __iomem *ddr2_reg_base;
41 42
42#define DDR2_SDRCR_OFFSET 0xc
43#define DDR2_SRPD_BIT BIT(23)
44#define DDR2_LPMODEN_BIT BIT(31)
45
46static void davinci_save_ddr_power(int enter, bool pdown) 43static void davinci_save_ddr_power(int enter, bool pdown)
47{ 44{
48 u32 val; 45 u32 val;
@@ -109,8 +106,6 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
109 int ret; 106 int ret;
110 struct cpuidle_device *device; 107 struct cpuidle_device *device;
111 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data; 108 struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
112 struct resource *ddr2_regs;
113 resource_size_t len;
114 109
115 device = &per_cpu(davinci_cpuidle_device, smp_processor_id()); 110 device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
116 111
@@ -119,28 +114,12 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
119 return -ENOENT; 114 return -ENOENT;
120 } 115 }
121 116
122 ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 117 ddr2_reg_base = pdata->ddr2_ctlr_base;
123 if (!ddr2_regs) {
124 dev_err(&pdev->dev, "cannot get DDR2 controller register base");
125 return -ENODEV;
126 }
127
128 len = resource_size(ddr2_regs);
129
130 ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
131 if (!ddr2_regs)
132 return -EBUSY;
133
134 ddr2_reg_base = ioremap(ddr2_regs->start, len);
135 if (!ddr2_reg_base) {
136 ret = -ENOMEM;
137 goto ioremap_fail;
138 }
139 118
140 ret = cpuidle_register_driver(&davinci_idle_driver); 119 ret = cpuidle_register_driver(&davinci_idle_driver);
141 if (ret) { 120 if (ret) {
142 dev_err(&pdev->dev, "failed to register driver\n"); 121 dev_err(&pdev->dev, "failed to register driver\n");
143 goto driver_register_fail; 122 return ret;
144 } 123 }
145 124
146 /* Wait for interrupt state */ 125 /* Wait for interrupt state */
@@ -167,18 +146,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
167 ret = cpuidle_register_device(device); 146 ret = cpuidle_register_device(device);
168 if (ret) { 147 if (ret) {
169 dev_err(&pdev->dev, "failed to register device\n"); 148 dev_err(&pdev->dev, "failed to register device\n");
170 goto device_register_fail; 149 cpuidle_unregister_driver(&davinci_idle_driver);
150 return ret;
171 } 151 }
172 152
173 return 0; 153 return 0;
174
175device_register_fail:
176 cpuidle_unregister_driver(&davinci_idle_driver);
177driver_register_fail:
178 iounmap(ddr2_reg_base);
179ioremap_fail:
180 release_mem_region(ddr2_regs->start, len);
181 return ret;
182} 154}
183 155
184static struct platform_driver davinci_cpuidle_driver = { 156static struct platform_driver davinci_cpuidle_driver = {
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index b22b5cf04250..122e61a9f505 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -371,7 +371,7 @@ static struct clk rmii_clk = {
371 .parent = &pll0_sysclk7, 371 .parent = &pll0_sysclk7,
372}; 372};
373 373
374static struct davinci_clk da830_clks[] = { 374static struct clk_lookup da830_clks[] = {
375 CLK(NULL, "ref", &ref_clk), 375 CLK(NULL, "ref", &ref_clk),
376 CLK(NULL, "pll0", &pll0_clk), 376 CLK(NULL, "pll0", &pll0_clk),
377 CLK(NULL, "pll0_aux", &pll0_aux_clk), 377 CLK(NULL, "pll0_aux", &pll0_aux_clk),
@@ -1208,13 +1208,13 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
1208 1208
1209void __init da830_init(void) 1209void __init da830_init(void)
1210{ 1210{
1211 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K); 1211 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1212 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module")) 1212 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1213 return; 1213 return;
1214 1214
1215 davinci_soc_info_da830.jtag_id_base = 1215 davinci_soc_info_da830.jtag_id_base =
1216 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG); 1216 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1217 davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG_VIRT(0x120); 1217 davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1218 1218
1219 davinci_common_init(&davinci_soc_info_da830); 1219 davinci_common_init(&davinci_soc_info_da830);
1220} 1220}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 717806c6cef9..d0fd7566712a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -26,6 +26,7 @@
26#include <mach/time.h> 26#include <mach/time.h>
27#include <mach/da8xx.h> 27#include <mach/da8xx.h>
28#include <mach/cpufreq.h> 28#include <mach/cpufreq.h>
29#include <mach/pm.h>
29 30
30#include "clock.h" 31#include "clock.h"
31#include "mux.h" 32#include "mux.h"
@@ -40,6 +41,7 @@
40#define DA850_REF_FREQ 24000000 41#define DA850_REF_FREQ 24000000
41 42
42#define CFGCHIP3_ASYNC3_CLKSRC BIT(4) 43#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
44#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
43#define CFGCHIP0_PLL_MASTER_LOCK BIT(4) 45#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
44 46
45static int da850_set_armrate(struct clk *clk, unsigned long rate); 47static int da850_set_armrate(struct clk *clk, unsigned long rate);
@@ -333,7 +335,7 @@ static struct clk aemif_clk = {
333 .flags = ALWAYS_ENABLED, 335 .flags = ALWAYS_ENABLED,
334}; 336};
335 337
336static struct davinci_clk da850_clks[] = { 338static struct clk_lookup da850_clks[] = {
337 CLK(NULL, "ref", &ref_clk), 339 CLK(NULL, "ref", &ref_clk),
338 CLK(NULL, "pll0", &pll0_clk), 340 CLK(NULL, "pll0", &pll0_clk),
339 CLK(NULL, "pll0_aux", &pll0_aux_clk), 341 CLK(NULL, "pll0_aux", &pll0_aux_clk),
@@ -535,6 +537,7 @@ static const struct mux_config da850_pins[] = {
535 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false) 537 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
536 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false) 538 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
537 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false) 539 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
540 MUX_CFG(DA850, RTC_ALARM, 0, 28, 15, 2, false)
538#endif 541#endif
539}; 542};
540 543
@@ -770,6 +773,12 @@ static struct map_desc da850_io_desc[] = {
770 .length = DA8XX_CP_INTC_SIZE, 773 .length = DA8XX_CP_INTC_SIZE,
771 .type = MT_DEVICE 774 .type = MT_DEVICE
772 }, 775 },
776 {
777 .virtual = SRAM_VIRT,
778 .pfn = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
779 .length = SZ_8K,
780 .type = MT_DEVICE
781 },
773}; 782};
774 783
775static void __iomem *da850_psc_bases[] = { 784static void __iomem *da850_psc_bases[] = {
@@ -825,12 +834,12 @@ static struct davinci_timer_info da850_timer_info = {
825static void da850_set_async3_src(int pllnum) 834static void da850_set_async3_src(int pllnum)
826{ 835{
827 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2; 836 struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
828 struct davinci_clk *c; 837 struct clk_lookup *c;
829 unsigned int v; 838 unsigned int v;
830 int ret; 839 int ret;
831 840
832 for (c = da850_clks; c->lk.clk; c++) { 841 for (c = da850_clks; c->clk; c++) {
833 clk = c->lk.clk; 842 clk = c->clk;
834 if (clk->flags & DA850_CLK_ASYNC3) { 843 if (clk->flags & DA850_CLK_ASYNC3) {
835 ret = clk_set_parent(clk, newparent); 844 ret = clk_set_parent(clk, newparent);
836 WARN(ret, "DA850: unable to re-parent clock %s", 845 WARN(ret, "DA850: unable to re-parent clock %s",
@@ -838,12 +847,12 @@ static void da850_set_async3_src(int pllnum)
838 } 847 }
839 } 848 }
840 849
841 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); 850 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
842 if (pllnum) 851 if (pllnum)
843 v |= CFGCHIP3_ASYNC3_CLKSRC; 852 v |= CFGCHIP3_ASYNC3_CLKSRC;
844 else 853 else
845 v &= ~CFGCHIP3_ASYNC3_CLKSRC; 854 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
846 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG)); 855 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
847} 856}
848 857
849#ifdef CONFIG_CPU_FREQ 858#ifdef CONFIG_CPU_FREQ
@@ -987,7 +996,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
987 unsigned int prediv, mult, postdiv; 996 unsigned int prediv, mult, postdiv;
988 struct da850_opp *opp; 997 struct da850_opp *opp;
989 struct pll_data *pll = clk->pll_data; 998 struct pll_data *pll = clk->pll_data;
990 unsigned int v;
991 int ret; 999 int ret;
992 1000
993 opp = (struct da850_opp *) da850_freq_table[index].index; 1001 opp = (struct da850_opp *) da850_freq_table[index].index;
@@ -995,11 +1003,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
995 mult = opp->mult; 1003 mult = opp->mult;
996 postdiv = opp->postdiv; 1004 postdiv = opp->postdiv;
997 1005
998 /* Unlock writing to PLL registers */
999 v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
1000 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1001 __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
1002
1003 ret = davinci_set_pllrate(pll, prediv, mult, postdiv); 1006 ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
1004 if (WARN_ON(ret)) 1007 if (WARN_ON(ret))
1005 return ret; 1008 return ret;
@@ -1028,6 +1031,43 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
1028} 1031}
1029#endif 1032#endif
1030 1033
1034int da850_register_pm(struct platform_device *pdev)
1035{
1036 int ret;
1037 struct davinci_pm_config *pdata = pdev->dev.platform_data;
1038
1039 ret = davinci_cfg_reg(DA850_RTC_ALARM);
1040 if (ret)
1041 return ret;
1042
1043 pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
1044 pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
1045 pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
1046
1047 pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
1048 if (!pdata->cpupll_reg_base)
1049 return -ENOMEM;
1050
1051 pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
1052 if (!pdata->ddrpll_reg_base) {
1053 ret = -ENOMEM;
1054 goto no_ddrpll_mem;
1055 }
1056
1057 pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
1058 if (!pdata->ddrpsc_reg_base) {
1059 ret = -ENOMEM;
1060 goto no_ddrpsc_mem;
1061 }
1062
1063 return platform_device_register(pdev);
1064
1065no_ddrpsc_mem:
1066 iounmap(pdata->ddrpll_reg_base);
1067no_ddrpll_mem:
1068 iounmap(pdata->cpupll_reg_base);
1069 return ret;
1070}
1031 1071
1032static struct davinci_soc_info davinci_soc_info_da850 = { 1072static struct davinci_soc_info davinci_soc_info_da850 = {
1033 .io_desc = da850_io_desc, 1073 .io_desc = da850_io_desc,
@@ -1049,17 +1089,25 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
1049 .gpio_irq = IRQ_DA8XX_GPIO0, 1089 .gpio_irq = IRQ_DA8XX_GPIO0,
1050 .serial_dev = &da8xx_serial_device, 1090 .serial_dev = &da8xx_serial_device,
1051 .emac_pdata = &da8xx_emac_pdata, 1091 .emac_pdata = &da8xx_emac_pdata,
1092 .sram_dma = DA8XX_ARM_RAM_BASE,
1093 .sram_len = SZ_8K,
1052}; 1094};
1053 1095
1054void __init da850_init(void) 1096void __init da850_init(void)
1055{ 1097{
1056 da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K); 1098 unsigned int v;
1057 if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module")) 1099
1100 da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
1101 if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
1102 return;
1103
1104 da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
1105 if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
1058 return; 1106 return;
1059 1107
1060 davinci_soc_info_da850.jtag_id_base = 1108 davinci_soc_info_da850.jtag_id_base =
1061 DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG); 1109 DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
1062 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120); 1110 davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
1063 1111
1064 davinci_common_init(&davinci_soc_info_da850); 1112 davinci_common_init(&davinci_soc_info_da850);
1065 1113
@@ -1071,4 +1119,14 @@ void __init da850_init(void)
1071 * be any noticible change even in non-DVFS use cases. 1119 * be any noticible change even in non-DVFS use cases.
1072 */ 1120 */
1073 da850_set_async3_src(1); 1121 da850_set_async3_src(1);
1122
1123 /* Unlock writing to PLL0 registers */
1124 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1125 v &= ~CFGCHIP0_PLL_MASTER_LOCK;
1126 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
1127
1128 /* Unlock writing to PLL1 registers */
1129 v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1130 v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
1131 __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
1074} 1132}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index a5105f03fd86..0a96791d3b0f 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,8 +24,10 @@
24#include "clock.h" 24#include "clock.h"
25 25
26#define DA8XX_TPCC_BASE 0x01c00000 26#define DA8XX_TPCC_BASE 0x01c00000
27#define DA850_TPCC1_BASE 0x01e30000
27#define DA8XX_TPTC0_BASE 0x01c08000 28#define DA8XX_TPTC0_BASE 0x01c08000
28#define DA8XX_TPTC1_BASE 0x01c08400 29#define DA8XX_TPTC1_BASE 0x01c08400
30#define DA850_TPTC2_BASE 0x01e38000
29#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */ 31#define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
30#define DA8XX_I2C0_BASE 0x01c22000 32#define DA8XX_I2C0_BASE 0x01c22000
31#define DA8XX_RTC_BASE 0x01C23000 33#define DA8XX_RTC_BASE 0x01C23000
@@ -42,7 +44,8 @@
42#define DA8XX_MDIO_REG_OFFSET 0x4000 44#define DA8XX_MDIO_REG_OFFSET 0x4000
43#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K 45#define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
44 46
45void __iomem *da8xx_syscfg_base; 47void __iomem *da8xx_syscfg0_base;
48void __iomem *da8xx_syscfg1_base;
46 49
47static struct plat_serial8250_port da8xx_serial_pdata[] = { 50static struct plat_serial8250_port da8xx_serial_pdata[] = {
48 { 51 {
@@ -82,11 +85,6 @@ struct platform_device da8xx_serial_device = {
82 }, 85 },
83}; 86};
84 87
85static const s8 da8xx_dma_chan_no_event[] = {
86 20, 21,
87 -1
88};
89
90static const s8 da8xx_queue_tc_mapping[][2] = { 88static const s8 da8xx_queue_tc_mapping[][2] = {
91 /* {event queue no, TC no} */ 89 /* {event queue no, TC no} */
92 {0, 0}, 90 {0, 0},
@@ -101,20 +99,52 @@ static const s8 da8xx_queue_priority_mapping[][2] = {
101 {-1, -1} 99 {-1, -1}
102}; 100};
103 101
104static struct edma_soc_info da8xx_edma_info[] = { 102static const s8 da850_queue_tc_mapping[][2] = {
103 /* {event queue no, TC no} */
104 {0, 0},
105 {-1, -1}
106};
107
108static const s8 da850_queue_priority_mapping[][2] = {
109 /* {event queue no, Priority} */
110 {0, 3},
111 {-1, -1}
112};
113
114static struct edma_soc_info da830_edma_info[] = {
105 { 115 {
106 .n_channel = 32, 116 .n_channel = 32,
107 .n_region = 4, 117 .n_region = 4,
108 .n_slot = 128, 118 .n_slot = 128,
109 .n_tc = 2, 119 .n_tc = 2,
110 .n_cc = 1, 120 .n_cc = 1,
111 .noevent = da8xx_dma_chan_no_event,
112 .queue_tc_mapping = da8xx_queue_tc_mapping, 121 .queue_tc_mapping = da8xx_queue_tc_mapping,
113 .queue_priority_mapping = da8xx_queue_priority_mapping, 122 .queue_priority_mapping = da8xx_queue_priority_mapping,
114 }, 123 },
115}; 124};
116 125
117static struct resource da8xx_edma_resources[] = { 126static struct edma_soc_info da850_edma_info[] = {
127 {
128 .n_channel = 32,
129 .n_region = 4,
130 .n_slot = 128,
131 .n_tc = 2,
132 .n_cc = 1,
133 .queue_tc_mapping = da8xx_queue_tc_mapping,
134 .queue_priority_mapping = da8xx_queue_priority_mapping,
135 },
136 {
137 .n_channel = 32,
138 .n_region = 4,
139 .n_slot = 128,
140 .n_tc = 1,
141 .n_cc = 1,
142 .queue_tc_mapping = da850_queue_tc_mapping,
143 .queue_priority_mapping = da850_queue_priority_mapping,
144 },
145};
146
147static struct resource da830_edma_resources[] = {
118 { 148 {
119 .name = "edma_cc0", 149 .name = "edma_cc0",
120 .start = DA8XX_TPCC_BASE, 150 .start = DA8XX_TPCC_BASE,
@@ -145,19 +175,91 @@ static struct resource da8xx_edma_resources[] = {
145 }, 175 },
146}; 176};
147 177
148static struct platform_device da8xx_edma_device = { 178static struct resource da850_edma_resources[] = {
179 {
180 .name = "edma_cc0",
181 .start = DA8XX_TPCC_BASE,
182 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
183 .flags = IORESOURCE_MEM,
184 },
185 {
186 .name = "edma_tc0",
187 .start = DA8XX_TPTC0_BASE,
188 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .name = "edma_tc1",
193 .start = DA8XX_TPTC1_BASE,
194 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .name = "edma_cc1",
199 .start = DA850_TPCC1_BASE,
200 .end = DA850_TPCC1_BASE + SZ_32K - 1,
201 .flags = IORESOURCE_MEM,
202 },
203 {
204 .name = "edma_tc2",
205 .start = DA850_TPTC2_BASE,
206 .end = DA850_TPTC2_BASE + SZ_1K - 1,
207 .flags = IORESOURCE_MEM,
208 },
209 {
210 .name = "edma0",
211 .start = IRQ_DA8XX_CCINT0,
212 .flags = IORESOURCE_IRQ,
213 },
214 {
215 .name = "edma0_err",
216 .start = IRQ_DA8XX_CCERRINT,
217 .flags = IORESOURCE_IRQ,
218 },
219 {
220 .name = "edma1",
221 .start = IRQ_DA850_CCINT1,
222 .flags = IORESOURCE_IRQ,
223 },
224 {
225 .name = "edma1_err",
226 .start = IRQ_DA850_CCERRINT1,
227 .flags = IORESOURCE_IRQ,
228 },
229};
230
231static struct platform_device da830_edma_device = {
149 .name = "edma", 232 .name = "edma",
150 .id = -1, 233 .id = -1,
151 .dev = { 234 .dev = {
152 .platform_data = da8xx_edma_info, 235 .platform_data = da830_edma_info,
153 }, 236 },
154 .num_resources = ARRAY_SIZE(da8xx_edma_resources), 237 .num_resources = ARRAY_SIZE(da830_edma_resources),
155 .resource = da8xx_edma_resources, 238 .resource = da830_edma_resources,
239};
240
241static struct platform_device da850_edma_device = {
242 .name = "edma",
243 .id = -1,
244 .dev = {
245 .platform_data = da850_edma_info,
246 },
247 .num_resources = ARRAY_SIZE(da850_edma_resources),
248 .resource = da850_edma_resources,
156}; 249};
157 250
158int __init da8xx_register_edma(void) 251int __init da8xx_register_edma(void)
159{ 252{
160 return platform_device_register(&da8xx_edma_device); 253 struct platform_device *pdev;
254
255 if (cpu_is_davinci_da830())
256 pdev = &da830_edma_device;
257 else if (cpu_is_davinci_da850())
258 pdev = &da850_edma_device;
259 else
260 return -ENODEV;
261
262 return platform_device_register(pdev);
161} 263}
162 264
163static struct resource da8xx_i2c_resources0[] = { 265static struct resource da8xx_i2c_resources0[] = {
@@ -495,6 +597,19 @@ int da8xx_register_rtc(void)
495 return ret; 597 return ret;
496} 598}
497 599
600static void __iomem *da8xx_ddr2_ctlr_base;
601void __iomem * __init da8xx_get_mem_ctlr(void)
602{
603 if (da8xx_ddr2_ctlr_base)
604 return da8xx_ddr2_ctlr_base;
605
606 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
607 if (!da8xx_ddr2_ctlr_base)
608 pr_warning("%s: Unable to map DDR2 controller", __func__);
609
610 return da8xx_ddr2_ctlr_base;
611}
612
498static struct resource da8xx_cpuidle_resources[] = { 613static struct resource da8xx_cpuidle_resources[] = {
499 { 614 {
500 .start = DA8XX_DDR2_CTL_BASE, 615 .start = DA8XX_DDR2_CTL_BASE,
@@ -520,6 +635,7 @@ static struct platform_device da8xx_cpuidle_device = {
520 635
521int __init da8xx_register_cpuidle(void) 636int __init da8xx_register_cpuidle(void)
522{ 637{
638 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
639
523 return platform_device_register(&da8xx_cpuidle_device); 640 return platform_device_register(&da8xx_cpuidle_device);
524} 641}
525
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index d84e85414d20..3dc0a88712eb 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -29,6 +29,7 @@
29#include <mach/serial.h> 29#include <mach/serial.h>
30#include <mach/common.h> 30#include <mach/common.h>
31#include <mach/asp.h> 31#include <mach/asp.h>
32#include <mach/spi.h>
32 33
33#include "clock.h" 34#include "clock.h"
34#include "mux.h" 35#include "mux.h"
@@ -334,7 +335,7 @@ static struct clk usb_clk = {
334 .lpsc = DAVINCI_LPSC_USB, 335 .lpsc = DAVINCI_LPSC_USB,
335}; 336};
336 337
337static struct davinci_clk dm355_clks[] = { 338static struct clk_lookup dm355_clks[] = {
338 CLK(NULL, "ref", &ref_clk), 339 CLK(NULL, "ref", &ref_clk),
339 CLK(NULL, "pll1", &pll1_clk), 340 CLK(NULL, "pll1", &pll1_clk),
340 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 341 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -362,9 +363,9 @@ static struct davinci_clk dm355_clks[] = {
362 CLK("davinci-asp.1", NULL, &asp1_clk), 363 CLK("davinci-asp.1", NULL, &asp1_clk),
363 CLK("davinci_mmc.0", NULL, &mmcsd0_clk), 364 CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
364 CLK("davinci_mmc.1", NULL, &mmcsd1_clk), 365 CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
365 CLK(NULL, "spi0", &spi0_clk), 366 CLK("spi_davinci.0", NULL, &spi0_clk),
366 CLK(NULL, "spi1", &spi1_clk), 367 CLK("spi_davinci.1", NULL, &spi1_clk),
367 CLK(NULL, "spi2", &spi2_clk), 368 CLK("spi_davinci.2", NULL, &spi2_clk),
368 CLK(NULL, "gpio", &gpio_clk), 369 CLK(NULL, "gpio", &gpio_clk),
369 CLK(NULL, "aemif", &aemif_clk), 370 CLK(NULL, "aemif", &aemif_clk),
370 CLK(NULL, "pwm0", &pwm0_clk), 371 CLK(NULL, "pwm0", &pwm0_clk),
@@ -391,24 +392,40 @@ static struct resource dm355_spi0_resources[] = {
391 .flags = IORESOURCE_MEM, 392 .flags = IORESOURCE_MEM,
392 }, 393 },
393 { 394 {
394 .start = IRQ_DM355_SPINT0_1, 395 .start = IRQ_DM355_SPINT0_0,
395 .flags = IORESOURCE_IRQ, 396 .flags = IORESOURCE_IRQ,
396 }, 397 },
397 /* Not yet used, so not included: 398 {
398 * IORESOURCE_IRQ: 399 .start = 17,
399 * - IRQ_DM355_SPINT0_0 400 .flags = IORESOURCE_DMA,
400 * IORESOURCE_DMA: 401 },
401 * - DAVINCI_DMA_SPI_SPIX 402 {
402 * - DAVINCI_DMA_SPI_SPIR 403 .start = 16,
403 */ 404 .flags = IORESOURCE_DMA,
405 },
406 {
407 .start = EVENTQ_1,
408 .flags = IORESOURCE_DMA,
409 },
404}; 410};
405 411
412static struct davinci_spi_platform_data dm355_spi0_pdata = {
413 .version = SPI_VERSION_1,
414 .num_chipselect = 2,
415 .clk_internal = 1,
416 .cs_hold = 1,
417 .intr_level = 0,
418 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
419 .c2tdelay = 0,
420 .t2cdelay = 0,
421};
406static struct platform_device dm355_spi0_device = { 422static struct platform_device dm355_spi0_device = {
407 .name = "spi_davinci", 423 .name = "spi_davinci",
408 .id = 0, 424 .id = 0,
409 .dev = { 425 .dev = {
410 .dma_mask = &dm355_spi0_dma_mask, 426 .dma_mask = &dm355_spi0_dma_mask,
411 .coherent_dma_mask = DMA_BIT_MASK(32), 427 .coherent_dma_mask = DMA_BIT_MASK(32),
428 .platform_data = &dm355_spi0_pdata,
412 }, 429 },
413 .num_resources = ARRAY_SIZE(dm355_spi0_resources), 430 .num_resources = ARRAY_SIZE(dm355_spi0_resources),
414 .resource = dm355_spi0_resources, 431 .resource = dm355_spi0_resources,
@@ -563,13 +580,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
563 580
564/*----------------------------------------------------------------------*/ 581/*----------------------------------------------------------------------*/
565 582
566static const s8 dma_chan_dm355_no_event[] = {
567 12, 13, 24, 56, 57,
568 58, 59, 60, 61, 62,
569 63,
570 -1
571};
572
573static const s8 583static const s8
574queue_tc_mapping[][2] = { 584queue_tc_mapping[][2] = {
575 /* {event queue no, TC no} */ 585 /* {event queue no, TC no} */
@@ -593,7 +603,6 @@ static struct edma_soc_info dm355_edma_info[] = {
593 .n_slot = 128, 603 .n_slot = 128,
594 .n_tc = 2, 604 .n_tc = 2,
595 .n_cc = 1, 605 .n_cc = 1,
596 .noevent = dma_chan_dm355_no_event,
597 .queue_tc_mapping = queue_tc_mapping, 606 .queue_tc_mapping = queue_tc_mapping,
598 .queue_priority_mapping = queue_priority_mapping, 607 .queue_priority_mapping = queue_priority_mapping,
599 }, 608 },
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ce9da43a628b..27772e18e45b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -18,6 +18,7 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/spi/spi.h>
21 22
22#include <asm/mach/map.h> 23#include <asm/mach/map.h>
23 24
@@ -32,6 +33,8 @@
32#include <mach/common.h> 33#include <mach/common.h>
33#include <mach/asp.h> 34#include <mach/asp.h>
34#include <mach/keyscan.h> 35#include <mach/keyscan.h>
36#include <mach/spi.h>
37
35 38
36#include "clock.h" 39#include "clock.h"
37#include "mux.h" 40#include "mux.h"
@@ -403,7 +406,7 @@ static struct clk mjcp_clk = {
403 .lpsc = DM365_LPSC_MJCP, 406 .lpsc = DM365_LPSC_MJCP,
404}; 407};
405 408
406static struct davinci_clk dm365_clks[] = { 409static struct clk_lookup dm365_clks[] = {
407 CLK(NULL, "ref", &ref_clk), 410 CLK(NULL, "ref", &ref_clk),
408 CLK(NULL, "pll1", &pll1_clk), 411 CLK(NULL, "pll1", &pll1_clk),
409 CLK(NULL, "pll1_aux", &pll1_aux_clk), 412 CLK(NULL, "pll1_aux", &pll1_aux_clk),
@@ -455,7 +458,7 @@ static struct davinci_clk dm365_clks[] = {
455 CLK(NULL, "timer3", &timer3_clk), 458 CLK(NULL, "timer3", &timer3_clk),
456 CLK(NULL, "usb", &usb_clk), 459 CLK(NULL, "usb", &usb_clk),
457 CLK("davinci_emac.1", NULL, &emac_clk), 460 CLK("davinci_emac.1", NULL, &emac_clk),
458 CLK("voice_codec", NULL, &voicecodec_clk), 461 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
459 CLK("davinci-asp.0", NULL, &asp0_clk), 462 CLK("davinci-asp.0", NULL, &asp0_clk),
460 CLK(NULL, "rto", &rto_clk), 463 CLK(NULL, "rto", &rto_clk),
461 CLK(NULL, "mjcp", &mjcp_clk), 464 CLK(NULL, "mjcp", &mjcp_clk),
@@ -606,9 +609,78 @@ INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
606 609
607EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false) 610EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
608EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false) 611EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
612EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
613EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
609#endif 614#endif
610}; 615};
611 616
617static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
618
619static struct davinci_spi_platform_data dm365_spi0_pdata = {
620 .version = SPI_VERSION_1,
621 .num_chipselect = 2,
622 .clk_internal = 1,
623 .cs_hold = 1,
624 .intr_level = 0,
625 .poll_mode = 1, /* 0 -> interrupt mode 1-> polling mode */
626 .c2tdelay = 0,
627 .t2cdelay = 0,
628};
629
630static struct resource dm365_spi0_resources[] = {
631 {
632 .start = 0x01c66000,
633 .end = 0x01c667ff,
634 .flags = IORESOURCE_MEM,
635 },
636 {
637 .start = IRQ_DM365_SPIINT0_0,
638 .flags = IORESOURCE_IRQ,
639 },
640 {
641 .start = 17,
642 .flags = IORESOURCE_DMA,
643 },
644 {
645 .start = 16,
646 .flags = IORESOURCE_DMA,
647 },
648 {
649 .start = EVENTQ_3,
650 .flags = IORESOURCE_DMA,
651 },
652};
653
654static struct platform_device dm365_spi0_device = {
655 .name = "spi_davinci",
656 .id = 0,
657 .dev = {
658 .dma_mask = &dm365_spi0_dma_mask,
659 .coherent_dma_mask = DMA_BIT_MASK(32),
660 .platform_data = &dm365_spi0_pdata,
661 },
662 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
663 .resource = dm365_spi0_resources,
664};
665
666void __init dm365_init_spi0(unsigned chipselect_mask,
667 struct spi_board_info *info, unsigned len)
668{
669 davinci_cfg_reg(DM365_SPI0_SCLK);
670 davinci_cfg_reg(DM365_SPI0_SDI);
671 davinci_cfg_reg(DM365_SPI0_SDO);
672
673 /* not all slaves will be wired up */
674 if (chipselect_mask & BIT(0))
675 davinci_cfg_reg(DM365_SPI0_SDENA0);
676 if (chipselect_mask & BIT(1))
677 davinci_cfg_reg(DM365_SPI0_SDENA1);
678
679 spi_register_board_info(info, len);
680
681 platform_device_register(&dm365_spi0_device);
682}
683
612static struct emac_platform_data dm365_emac_pdata = { 684static struct emac_platform_data dm365_emac_pdata = {
613 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET, 685 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
614 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET, 686 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
@@ -754,7 +826,7 @@ static struct edma_soc_info dm365_edma_info[] = {
754 .n_cc = 1, 826 .n_cc = 1,
755 .queue_tc_mapping = dm365_queue_tc_mapping, 827 .queue_tc_mapping = dm365_queue_tc_mapping,
756 .queue_priority_mapping = dm365_queue_priority_mapping, 828 .queue_priority_mapping = dm365_queue_priority_mapping,
757 .default_queue = EVENTQ_2, 829 .default_queue = EVENTQ_3,
758 }, 830 },
759}; 831};
760 832
@@ -835,6 +907,31 @@ static struct platform_device dm365_asp_device = {
835 .resource = dm365_asp_resources, 907 .resource = dm365_asp_resources,
836}; 908};
837 909
910static struct resource dm365_vc_resources[] = {
911 {
912 .start = DAVINCI_DM365_VC_BASE,
913 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
914 .flags = IORESOURCE_MEM,
915 },
916 {
917 .start = DAVINCI_DMA_VC_TX,
918 .end = DAVINCI_DMA_VC_TX,
919 .flags = IORESOURCE_DMA,
920 },
921 {
922 .start = DAVINCI_DMA_VC_RX,
923 .end = DAVINCI_DMA_VC_RX,
924 .flags = IORESOURCE_DMA,
925 },
926};
927
928static struct platform_device dm365_vc_device = {
929 .name = "davinci_voicecodec",
930 .id = -1,
931 .num_resources = ARRAY_SIZE(dm365_vc_resources),
932 .resource = dm365_vc_resources,
933};
934
838static struct resource dm365_rtc_resources[] = { 935static struct resource dm365_rtc_resources[] = {
839 { 936 {
840 .start = DM365_RTC_BASE, 937 .start = DM365_RTC_BASE,
@@ -991,6 +1088,14 @@ void __init dm365_init_asp(struct snd_platform_data *pdata)
991 platform_device_register(&dm365_asp_device); 1088 platform_device_register(&dm365_asp_device);
992} 1089}
993 1090
1091void __init dm365_init_vc(struct snd_platform_data *pdata)
1092{
1093 davinci_cfg_reg(DM365_EVT2_VC_TX);
1094 davinci_cfg_reg(DM365_EVT3_VC_RX);
1095 dm365_vc_device.dev.platform_data = pdata;
1096 platform_device_register(&dm365_vc_device);
1097}
1098
994void __init dm365_init_ks(struct davinci_ks_platform_data *pdata) 1099void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
995{ 1100{
996 dm365_ks_device.dev.platform_data = pdata; 1101 dm365_ks_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 92aeb5600680..2f2ae8bc77bb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
277 .usecount = 1, /* REVISIT: why cant' this be disabled? */ 277 .usecount = 1, /* REVISIT: why cant' this be disabled? */
278}; 278};
279 279
280struct davinci_clk dm644x_clks[] = { 280struct clk_lookup dm644x_clks[] = {
281 CLK(NULL, "ref", &ref_clk), 281 CLK(NULL, "ref", &ref_clk),
282 CLK(NULL, "pll1", &pll1_clk), 282 CLK(NULL, "pll1", &pll1_clk),
283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1), 283 CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -479,15 +479,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
479 479
480/*----------------------------------------------------------------------*/ 480/*----------------------------------------------------------------------*/
481 481
482static const s8 dma_chan_dm644x_no_event[] = {
483 0, 1, 12, 13, 14,
484 15, 25, 30, 31, 45,
485 46, 47, 55, 56, 57,
486 58, 59, 60, 61, 62,
487 63,
488 -1
489};
490
491static const s8 482static const s8
492queue_tc_mapping[][2] = { 483queue_tc_mapping[][2] = {
493 /* {event queue no, TC no} */ 484 /* {event queue no, TC no} */
@@ -511,7 +502,6 @@ static struct edma_soc_info dm644x_edma_info[] = {
511 .n_slot = 128, 502 .n_slot = 128,
512 .n_tc = 2, 503 .n_tc = 2,
513 .n_cc = 1, 504 .n_cc = 1,
514 .noevent = dma_chan_dm644x_no_event,
515 .queue_tc_mapping = queue_tc_mapping, 505 .queue_tc_mapping = queue_tc_mapping,
516 .queue_priority_mapping = queue_priority_mapping, 506 .queue_priority_mapping = queue_priority_mapping,
517 }, 507 },
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 829a44bcf799..893baf4ad37d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -42,7 +42,6 @@
42/* 42/*
43 * Device specific clocks 43 * Device specific clocks
44 */ 44 */
45#define DM646X_REF_FREQ 27000000
46#define DM646X_AUX_FREQ 24000000 45#define DM646X_AUX_FREQ 24000000
47 46
48static struct pll_data pll1_data = { 47static struct pll_data pll1_data = {
@@ -57,7 +56,6 @@ static struct pll_data pll2_data = {
57 56
58static struct clk ref_clk = { 57static struct clk ref_clk = {
59 .name = "ref_clk", 58 .name = "ref_clk",
60 .rate = DM646X_REF_FREQ,
61}; 59};
62 60
63static struct clk aux_clkin = { 61static struct clk aux_clkin = {
@@ -313,7 +311,7 @@ static struct clk vpif1_clk = {
313 .flags = ALWAYS_ENABLED, 311 .flags = ALWAYS_ENABLED,
314}; 312};
315 313
316struct davinci_clk dm646x_clks[] = { 314struct clk_lookup dm646x_clks[] = {
317 CLK(NULL, "ref", &ref_clk), 315 CLK(NULL, "ref", &ref_clk),
318 CLK(NULL, "aux", &aux_clkin), 316 CLK(NULL, "aux", &aux_clkin),
319 CLK(NULL, "pll1", &pll1_clk), 317 CLK(NULL, "pll1", &pll1_clk),
@@ -513,14 +511,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
513 511
514/*----------------------------------------------------------------------*/ 512/*----------------------------------------------------------------------*/
515 513
516static const s8 dma_chan_dm646x_no_event[] = {
517 0, 1, 2, 3, 13,
518 14, 15, 24, 25, 26,
519 27, 30, 31, 54, 55,
520 56,
521 -1
522};
523
524/* Four Transfer Controllers on DM646x */ 514/* Four Transfer Controllers on DM646x */
525static const s8 515static const s8
526dm646x_queue_tc_mapping[][2] = { 516dm646x_queue_tc_mapping[][2] = {
@@ -549,7 +539,6 @@ static struct edma_soc_info dm646x_edma_info[] = {
549 .n_slot = 512, 539 .n_slot = 512,
550 .n_tc = 4, 540 .n_tc = 4,
551 .n_cc = 1, 541 .n_cc = 1,
552 .noevent = dma_chan_dm646x_no_event,
553 .queue_tc_mapping = dm646x_queue_tc_mapping, 542 .queue_tc_mapping = dm646x_queue_tc_mapping,
554 .queue_priority_mapping = dm646x_queue_priority_mapping, 543 .queue_priority_mapping = dm646x_queue_priority_mapping,
555 }, 544 },
@@ -925,6 +914,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
925 914
926void __init dm646x_init(void) 915void __init dm646x_init(void)
927{ 916{
917 dm646x_board_setup_refclk(&ref_clk);
928 davinci_common_init(&davinci_soc_info_dm646x); 918 davinci_common_init(&davinci_soc_info_dm646x);
929} 919}
930 920
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 648fbb760ae1..15dd886df04c 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -226,11 +226,11 @@ struct edma {
226 */ 226 */
227 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); 227 DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
228 228
229 /* The edma_noevent bit for each channel is clear unless 229 /* The edma_unused bit for each channel is clear unless
230 * it doesn't trigger DMA events on this platform. It uses a 230 * it is not being used on this platform. It uses a bit
231 * bit of SOC-specific initialization code. 231 * of SOC-specific initialization code.
232 */ 232 */
233 DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH); 233 DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
234 234
235 unsigned irq_res_start; 235 unsigned irq_res_start;
236 unsigned irq_res_end; 236 unsigned irq_res_end;
@@ -243,6 +243,7 @@ struct edma {
243}; 243};
244 244
245static struct edma *edma_info[EDMA_MAX_CC]; 245static struct edma *edma_info[EDMA_MAX_CC];
246static int arch_num_cc;
246 247
247/* dummy param set used to (re)initialize parameter RAM slots */ 248/* dummy param set used to (re)initialize parameter RAM slots */
248static const struct edmacc_param dummy_paramset = { 249static const struct edmacc_param dummy_paramset = {
@@ -555,8 +556,27 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
555 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); 556 return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
556} 557}
557 558
559static int prepare_unused_channel_list(struct device *dev, void *data)
560{
561 struct platform_device *pdev = to_platform_device(dev);
562 int i, ctlr;
563
564 for (i = 0; i < pdev->num_resources; i++) {
565 if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
566 (int)pdev->resource[i].start >= 0) {
567 ctlr = EDMA_CTLR(pdev->resource[i].start);
568 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
569 edma_info[ctlr]->edma_unused);
570 }
571 }
572
573 return 0;
574}
575
558/*-----------------------------------------------------------------------*/ 576/*-----------------------------------------------------------------------*/
559 577
578static bool unused_chan_list_done;
579
560/* Resource alloc/free: dma channels, parameter RAM slots */ 580/* Resource alloc/free: dma channels, parameter RAM slots */
561 581
562/** 582/**
@@ -594,7 +614,22 @@ int edma_alloc_channel(int channel,
594 void *data, 614 void *data,
595 enum dma_event_q eventq_no) 615 enum dma_event_q eventq_no)
596{ 616{
597 unsigned i, done, ctlr = 0; 617 unsigned i, done = 0, ctlr = 0;
618 int ret = 0;
619
620 if (!unused_chan_list_done) {
621 /*
622 * Scan all the platform devices to find out the EDMA channels
623 * used and clear them in the unused list, making the rest
624 * available for ARM usage.
625 */
626 ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
627 prepare_unused_channel_list);
628 if (ret < 0)
629 return ret;
630
631 unused_chan_list_done = true;
632 }
598 633
599 if (channel >= 0) { 634 if (channel >= 0) {
600 ctlr = EDMA_CTLR(channel); 635 ctlr = EDMA_CTLR(channel);
@@ -602,15 +637,15 @@ int edma_alloc_channel(int channel,
602 } 637 }
603 638
604 if (channel < 0) { 639 if (channel < 0) {
605 for (i = 0; i < EDMA_MAX_CC; i++) { 640 for (i = 0; i < arch_num_cc; i++) {
606 channel = 0; 641 channel = 0;
607 for (;;) { 642 for (;;) {
608 channel = find_next_bit(edma_info[i]-> 643 channel = find_next_bit(edma_info[i]->
609 edma_noevent, 644 edma_unused,
610 edma_info[i]->num_channels, 645 edma_info[i]->num_channels,
611 channel); 646 channel);
612 if (channel == edma_info[i]->num_channels) 647 if (channel == edma_info[i]->num_channels)
613 return -ENOMEM; 648 break;
614 if (!test_and_set_bit(channel, 649 if (!test_and_set_bit(channel,
615 edma_info[i]->edma_inuse)) { 650 edma_info[i]->edma_inuse)) {
616 done = 1; 651 done = 1;
@@ -622,6 +657,8 @@ int edma_alloc_channel(int channel,
622 if (done) 657 if (done)
623 break; 658 break;
624 } 659 }
660 if (!done)
661 return -ENOMEM;
625 } else if (channel >= edma_info[ctlr]->num_channels) { 662 } else if (channel >= edma_info[ctlr]->num_channels) {
626 return -EINVAL; 663 return -EINVAL;
627 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) { 664 } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
@@ -642,7 +679,7 @@ int edma_alloc_channel(int channel,
642 679
643 map_dmach_queue(ctlr, channel, eventq_no); 680 map_dmach_queue(ctlr, channel, eventq_no);
644 681
645 return channel; 682 return EDMA_CTLR_CHAN(ctlr, channel);
646} 683}
647EXPORT_SYMBOL(edma_alloc_channel); 684EXPORT_SYMBOL(edma_alloc_channel);
648 685
@@ -1219,7 +1256,7 @@ int edma_start(unsigned channel)
1219 unsigned int mask = (1 << (channel & 0x1f)); 1256 unsigned int mask = (1 << (channel & 0x1f));
1220 1257
1221 /* EDMA channels without event association */ 1258 /* EDMA channels without event association */
1222 if (test_bit(channel, edma_info[ctlr]->edma_noevent)) { 1259 if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
1223 pr_debug("EDMA: ESR%d %08x\n", j, 1260 pr_debug("EDMA: ESR%d %08x\n", j,
1224 edma_shadow0_read_array(ctlr, SH_ESR, j)); 1261 edma_shadow0_read_array(ctlr, SH_ESR, j));
1225 edma_shadow0_write_array(ctlr, SH_ESR, j, mask); 1262 edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1344,7 +1381,6 @@ static int __init edma_probe(struct platform_device *pdev)
1344 const s8 (*queue_tc_mapping)[2]; 1381 const s8 (*queue_tc_mapping)[2];
1345 int i, j, found = 0; 1382 int i, j, found = 0;
1346 int status = -1; 1383 int status = -1;
1347 const s8 *noevent;
1348 int irq[EDMA_MAX_CC] = {0, 0}; 1384 int irq[EDMA_MAX_CC] = {0, 0};
1349 int err_irq[EDMA_MAX_CC] = {0, 0}; 1385 int err_irq[EDMA_MAX_CC] = {0, 0};
1350 struct resource *r[EDMA_MAX_CC] = {NULL}; 1386 struct resource *r[EDMA_MAX_CC] = {NULL};
@@ -1407,11 +1443,9 @@ static int __init edma_probe(struct platform_device *pdev)
1407 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), 1443 memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1408 &dummy_paramset, PARM_SIZE); 1444 &dummy_paramset, PARM_SIZE);
1409 1445
1410 noevent = info[j].noevent; 1446 /* Mark all channels as unused */
1411 if (noevent) { 1447 memset(edma_info[j]->edma_unused, 0xff,
1412 while (*noevent != -1) 1448 sizeof(edma_info[j]->edma_unused));
1413 set_bit(*noevent++, edma_info[j]->edma_noevent);
1414 }
1415 1449
1416 sprintf(irq_name, "edma%d", j); 1450 sprintf(irq_name, "edma%d", j);
1417 irq[j] = platform_get_irq_byname(pdev, irq_name); 1451 irq[j] = platform_get_irq_byname(pdev, irq_name);
@@ -1467,6 +1501,7 @@ static int __init edma_probe(struct platform_device *pdev)
1467 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); 1501 edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1468 edma_write_array(j, EDMA_QRAE, i, 0x0); 1502 edma_write_array(j, EDMA_QRAE, i, 0x0);
1469 } 1503 }
1504 arch_num_cc++;
1470 } 1505 }
1471 1506
1472 if (tc_errs_handled) { 1507 if (tc_errs_handled) {
diff --git a/arch/arm/mach-davinci/include/mach/cdce949.h b/arch/arm/mach-davinci/include/mach/cdce949.h
new file mode 100644
index 000000000000..c73331fae341
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cdce949.h
@@ -0,0 +1,19 @@
1/*
2 * TI CDCE949 off-chip clock synthesizer support
3 *
4 * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10#ifndef _MACH_DAVINCI_CDCE949_H
11#define _MACH_DAVINCI_CDCE949_H
12
13#include <linux/clk.h>
14
15#include <mach/clock.h>
16
17int cdce_set_rate(struct clk *clk, unsigned long rate);
18
19#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 6ca2c9a0a482..50a955f05ef9 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -43,7 +43,7 @@ struct davinci_soc_info {
43 void __iomem *jtag_id_base; 43 void __iomem *jtag_id_base;
44 struct davinci_id *ids; 44 struct davinci_id *ids;
45 unsigned long ids_num; 45 unsigned long ids_num;
46 struct davinci_clk *cpu_clks; 46 struct clk_lookup *cpu_clks;
47 void __iomem **psc_bases; 47 void __iomem **psc_bases;
48 unsigned long psc_bases_num; 48 unsigned long psc_bases_num;
49 void __iomem *pinmux_base; 49 void __iomem *pinmux_base;
diff --git a/arch/arm/mach-davinci/include/mach/cpuidle.h b/arch/arm/mach-davinci/include/mach/cpuidle.h
index cbfc6a9c81b4..74f088b0edfb 100644
--- a/arch/arm/mach-davinci/include/mach/cpuidle.h
+++ b/arch/arm/mach-davinci/include/mach/cpuidle.h
@@ -12,6 +12,7 @@
12 12
13struct davinci_cpuidle_config { 13struct davinci_cpuidle_config {
14 u32 ddr2_pdown; 14 u32 ddr2_pdown;
15 void __iomem *ddr2_ctlr_base;
15}; 16};
16 17
17#endif 18#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 90704910d343..cc9be7fee627 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -13,15 +13,17 @@
13 13
14#include <video/da8xx-fb.h> 14#include <video/da8xx-fb.h>
15 15
16#include <linux/davinci_emac.h>
16#include <mach/serial.h> 17#include <mach/serial.h>
17#include <mach/edma.h> 18#include <mach/edma.h>
18#include <mach/i2c.h> 19#include <mach/i2c.h>
19#include <mach/emac.h>
20#include <mach/asp.h> 20#include <mach/asp.h>
21#include <mach/mmc.h> 21#include <mach/mmc.h>
22#include <mach/usb.h> 22#include <mach/usb.h>
23#include <mach/pm.h>
23 24
24extern void __iomem *da8xx_syscfg_base; 25extern void __iomem *da8xx_syscfg0_base;
26extern void __iomem *da8xx_syscfg1_base;
25 27
26/* 28/*
27 * The cp_intc interrupt controller for the da8xx isn't in the same 29 * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -34,13 +36,17 @@ extern void __iomem *da8xx_syscfg_base;
34#define DA8XX_CP_INTC_SIZE SZ_8K 36#define DA8XX_CP_INTC_SIZE SZ_8K
35#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K) 37#define DA8XX_CP_INTC_VIRT (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
36 38
37#define DA8XX_SYSCFG_BASE (IO_PHYS + 0x14000) 39#define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
38#define DA8XX_SYSCFG_VIRT(x) (da8xx_syscfg_base + (x)) 40#define DA8XX_SYSCFG0_VIRT(x) (da8xx_syscfg0_base + (x))
39#define DA8XX_JTAG_ID_REG 0x18 41#define DA8XX_JTAG_ID_REG 0x18
40#define DA8XX_CFGCHIP0_REG 0x17c 42#define DA8XX_CFGCHIP0_REG 0x17c
41#define DA8XX_CFGCHIP2_REG 0x184 43#define DA8XX_CFGCHIP2_REG 0x184
42#define DA8XX_CFGCHIP3_REG 0x188 44#define DA8XX_CFGCHIP3_REG 0x188
43 45
46#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
47#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
48#define DA8XX_DEEPSLEEP_REG 0x8
49
44#define DA8XX_PSC0_BASE 0x01c10000 50#define DA8XX_PSC0_BASE 0x01c10000
45#define DA8XX_PLL0_BASE 0x01c11000 51#define DA8XX_PLL0_BASE 0x01c11000
46#define DA8XX_TIMER64P0_BASE 0x01c20000 52#define DA8XX_TIMER64P0_BASE 0x01c20000
@@ -48,11 +54,13 @@ extern void __iomem *da8xx_syscfg_base;
48#define DA8XX_GPIO_BASE 0x01e26000 54#define DA8XX_GPIO_BASE 0x01e26000
49#define DA8XX_PSC1_BASE 0x01e27000 55#define DA8XX_PSC1_BASE 0x01e27000
50#define DA8XX_LCD_CNTRL_BASE 0x01e13000 56#define DA8XX_LCD_CNTRL_BASE 0x01e13000
57#define DA8XX_PLL1_BASE 0x01e1a000
51#define DA8XX_MMCSD0_BASE 0x01c40000 58#define DA8XX_MMCSD0_BASE 0x01c40000
52#define DA8XX_AEMIF_CS2_BASE 0x60000000 59#define DA8XX_AEMIF_CS2_BASE 0x60000000
53#define DA8XX_AEMIF_CS3_BASE 0x62000000 60#define DA8XX_AEMIF_CS3_BASE 0x62000000
54#define DA8XX_AEMIF_CTL_BASE 0x68000000 61#define DA8XX_AEMIF_CTL_BASE 0x68000000
55#define DA8XX_DDR2_CTL_BASE 0xb0000000 62#define DA8XX_DDR2_CTL_BASE 0xb0000000
63#define DA8XX_ARM_RAM_BASE 0xffff0000
56 64
57#define PINMUX0 0x00 65#define PINMUX0 0x00
58#define PINMUX1 0x04 66#define PINMUX1 0x04
@@ -90,6 +98,8 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
90int da8xx_register_rtc(void); 98int da8xx_register_rtc(void);
91int da850_register_cpufreq(void); 99int da850_register_cpufreq(void);
92int da8xx_register_cpuidle(void); 100int da8xx_register_cpuidle(void);
101void __iomem * __init da8xx_get_mem_ctlr(void);
102int da850_register_pm(struct platform_device *pdev);
93 103
94extern struct platform_device da8xx_serial_device; 104extern struct platform_device da8xx_serial_device;
95extern struct emac_platform_data da8xx_emac_pdata; 105extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 9fc5a64a5364..3a37b5a6983c 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -14,8 +14,8 @@
14#define __ASM_ARCH_DM665_H 14#define __ASM_ARCH_DM665_H
15 15
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/davinci_emac.h>
17#include <mach/hardware.h> 18#include <mach/hardware.h>
18#include <mach/emac.h>
19#include <mach/asp.h> 19#include <mach/asp.h>
20#include <mach/keyscan.h> 20#include <mach/keyscan.h>
21#include <media/davinci/vpfe_capture.h> 21#include <media/davinci/vpfe_capture.h>
@@ -32,10 +32,17 @@
32 32
33#define DM365_RTC_BASE (0x01C69000) 33#define DM365_RTC_BASE (0x01C69000)
34 34
35#define DAVINCI_DM365_VC_BASE (0x01D0C000)
36#define DAVINCI_DMA_VC_TX 2
37#define DAVINCI_DMA_VC_RX 3
38
35void __init dm365_init(void); 39void __init dm365_init(void);
36void __init dm365_init_asp(struct snd_platform_data *pdata); 40void __init dm365_init_asp(struct snd_platform_data *pdata);
41void __init dm365_init_vc(struct snd_platform_data *pdata);
37void __init dm365_init_ks(struct davinci_ks_platform_data *pdata); 42void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
38void __init dm365_init_rtc(void); 43void __init dm365_init_rtc(void);
44void dm365_init_spi0(unsigned chipselect_mask,
45 struct spi_board_info *info, unsigned len);
39 46
40void dm365_set_vpfe_config(struct vpfe_config *cfg); 47void dm365_set_vpfe_config(struct vpfe_config *cfg);
41#endif /* __ASM_ARCH_DM365_H */ 48#endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 44e8f0fae9ea..1a8b09ccc3c8 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -22,8 +22,8 @@
22#ifndef __ASM_ARCH_DM644X_H 22#ifndef __ASM_ARCH_DM644X_H
23#define __ASM_ARCH_DM644X_H 23#define __ASM_ARCH_DM644X_H
24 24
25#include <linux/davinci_emac.h>
25#include <mach/hardware.h> 26#include <mach/hardware.h>
26#include <mach/emac.h>
27#include <mach/asp.h> 27#include <mach/asp.h>
28#include <media/davinci/vpfe_capture.h> 28#include <media/davinci/vpfe_capture.h>
29 29
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 8cec746ae9d2..846da98b619a 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -12,10 +12,11 @@
12#define __ASM_ARCH_DM646X_H 12#define __ASM_ARCH_DM646X_H
13 13
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/emac.h>
16#include <mach/asp.h> 15#include <mach/asp.h>
17#include <linux/i2c.h> 16#include <linux/i2c.h>
18#include <linux/videodev2.h> 17#include <linux/videodev2.h>
18#include <linux/clk.h>
19#include <linux/davinci_emac.h>
19 20
20#define DM646X_EMAC_BASE (0x01C80000) 21#define DM646X_EMAC_BASE (0x01C80000)
21#define DM646X_EMAC_CNTRL_OFFSET (0x0000) 22#define DM646X_EMAC_CNTRL_OFFSET (0x0000)
@@ -30,6 +31,7 @@ void __init dm646x_init(void);
30void __init dm646x_init_ide(void); 31void __init dm646x_init_ide(void);
31void __init dm646x_init_mcasp0(struct snd_platform_data *pdata); 32void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
32void __init dm646x_init_mcasp1(struct snd_platform_data *pdata); 33void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
34void __init dm646x_board_setup_refclk(struct clk *clk);
33 35
34void dm646x_video_init(void); 36void dm646x_video_init(void);
35 37
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index eb8bfd7925e7..ced3092af5ba 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -280,8 +280,6 @@ struct edma_soc_info {
280 unsigned n_cc; 280 unsigned n_cc;
281 enum dma_event_q default_queue; 281 enum dma_event_q default_queue;
282 282
283 /* list of channels with no even trigger; terminated by "-1" */
284 const s8 *noevent;
285 const s8 (*queue_tc_mapping)[2]; 283 const s8 (*queue_tc_mapping)[2];
286 const s8 (*queue_priority_mapping)[2]; 284 const s8 (*queue_priority_mapping)[2];
287}; 285};
diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h
deleted file mode 100644
index beff4fb7c845..000000000000
--- a/arch/arm/mach-davinci/include/mach/emac.h
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * TI DaVinci EMAC platform support
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef _MACH_DAVINCI_EMAC_H
12#define _MACH_DAVINCI_EMAC_H
13
14#include <linux/if_ether.h>
15#include <linux/memory.h>
16
17struct emac_platform_data {
18 char mac_addr[ETH_ALEN];
19 u32 ctrl_reg_offset;
20 u32 ctrl_mod_reg_offset;
21 u32 ctrl_ram_offset;
22 u32 mdio_reg_offset;
23 u32 ctrl_ram_size;
24 u32 phy_mask;
25 u32 mdio_max_freq;
26 u8 rmii_en;
27 u8 version;
28};
29
30enum {
31 EMAC_VERSION_1, /* DM644x */
32 EMAC_VERSION_2, /* DM646x */
33};
34
35void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context);
36#endif
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
index c248e9b7e825..39fdceac8414 100644
--- a/arch/arm/mach-davinci/include/mach/i2c.h
+++ b/arch/arm/mach-davinci/include/mach/i2c.h
@@ -16,6 +16,8 @@
16struct davinci_i2c_platform_data { 16struct davinci_i2c_platform_data {
17 unsigned int bus_freq; /* standard bus frequency (kHz) */ 17 unsigned int bus_freq; /* standard bus frequency (kHz) */
18 unsigned int bus_delay; /* post-transaction delay (usec) */ 18 unsigned int bus_delay; /* post-transaction delay (usec) */
19 unsigned int sda_pin; /* GPIO pin ID to use for SDA */
20 unsigned int scl_pin; /* GPIO pin ID to use for SCL */
19}; 21};
20 22
21/* for board setup code */ 23/* for board setup code */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 80309aed534a..a91edfb8beea 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -31,6 +31,11 @@
31#define PHYS_OFFSET DAVINCI_DDR_BASE 31#define PHYS_OFFSET DAVINCI_DDR_BASE
32#endif 32#endif
33 33
34#define DDR2_SDRCR_OFFSET 0xc
35#define DDR2_SRPD_BIT BIT(23)
36#define DDR2_MCLKSTOPEN_BIT BIT(30)
37#define DDR2_LPMODEN_BIT BIT(31)
38
34/* 39/*
35 * Increase size of DMA-consistent memory region 40 * Increase size of DMA-consistent memory region
36 */ 41 */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index b60c693985ff..2a68c1d8a24b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -327,6 +327,8 @@ enum davinci_dm365_index {
327 /* EDMA event muxing */ 327 /* EDMA event muxing */
328 DM365_EVT2_ASP_TX, 328 DM365_EVT2_ASP_TX,
329 DM365_EVT3_ASP_RX, 329 DM365_EVT3_ASP_RX,
330 DM365_EVT2_VC_TX,
331 DM365_EVT3_VC_RX,
330 DM365_EVT26_MMC0_RX, 332 DM365_EVT26_MMC0_RX,
331}; 333};
332 334
@@ -899,6 +901,7 @@ enum davinci_da850_index {
899 DA850_GPIO2_15, 901 DA850_GPIO2_15,
900 DA850_GPIO4_0, 902 DA850_GPIO4_0,
901 DA850_GPIO4_1, 903 DA850_GPIO4_1,
904 DA850_RTC_ALARM,
902}; 905};
903 906
904#ifdef CONFIG_DAVINCI_MUX 907#ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
new file mode 100644
index 000000000000..37b19bf35a85
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pm.h
@@ -0,0 +1,54 @@
1/*
2 * TI DaVinci platform support for power management.
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MACH_DAVINCI_PM_H
16#define _MACH_DAVINCI_PM_H
17
18/*
19 * Caution: Assembly code in sleep.S makes assumtion on the order
20 * of the members of this structure.
21 */
22struct davinci_pm_config {
23 void __iomem *ddr2_ctlr_base;
24 void __iomem *ddrpsc_reg_base;
25 int ddrpsc_num;
26 void __iomem *ddrpll_reg_base;
27 void __iomem *deepsleep_reg;
28 void __iomem *cpupll_reg_base;
29 /*
30 * Note on SLEEPCOUNT:
31 * The SLEEPCOUNT feature is mainly intended for cases in which
32 * the internal oscillator is used. The internal oscillator is
33 * fully disabled in deep sleep mode. When you exist deep sleep
34 * mode, the oscillator will be turned on and will generate very
35 * small oscillations which will not be detected by the deep sleep
36 * counter. Eventually those oscillations will grow to an amplitude
37 * large enough to start incrementing the deep sleep counter.
38 * In this case recommendation from hardware engineers is that the
39 * SLEEPCOUNT be set to 4096. This means that 4096 valid clock cycles
40 * must be detected before the clock is passed to the rest of the
41 * system.
42 * In the case that the internal oscillator is not used and the
43 * clock is generated externally, the SLEEPCOUNT value can be very
44 * small since the clock input is assumed to be stable before SoC
45 * is taken out of deepsleep mode. A value of 128 would be more than
46 * adequate.
47 */
48 int sleepcount;
49};
50
51extern unsigned int davinci_cpu_suspend_sz;
52extern void davinci_cpu_suspend(struct davinci_pm_config *);
53
54#endif
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 171173c1dbad..651f6d8158fa 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,8 +180,23 @@
180#define DA8XX_LPSC1_CR_P3_SS 26 180#define DA8XX_LPSC1_CR_P3_SS 26
181#define DA8XX_LPSC1_L3_CBA_RAM 31 181#define DA8XX_LPSC1_L3_CBA_RAM 31
182 182
183/* PSC register offsets */
184#define EPCPR 0x070
185#define PTCMD 0x120
186#define PTSTAT 0x128
187#define PDSTAT 0x200
188#define PDCTL1 0x304
189#define MDSTAT 0x800
190#define MDCTL 0xA00
191
192#define MDSTAT_STATE_MASK 0x1f
193
194#ifndef __ASSEMBLER__
195
183extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id); 196extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
184extern void davinci_psc_config(unsigned int domain, unsigned int ctlr, 197extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
185 unsigned int id, char enable); 198 unsigned int id, char enable);
186 199
200#endif
201
187#endif /* __ASM_ARCH_PSC_H */ 202#endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
new file mode 100644
index 000000000000..910efbf099c0
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __ARCH_ARM_DAVINCI_SPI_H
20#define __ARCH_ARM_DAVINCI_SPI_H
21
22enum {
23 SPI_VERSION_1, /* For DM355/DM365/DM6467 */
24 SPI_VERSION_2, /* For DA8xx */
25};
26
27struct davinci_spi_platform_data {
28 u8 version;
29 u8 num_chipselect;
30 u8 wdelay;
31 u8 odd_parity;
32 u8 parity_enable;
33 u8 wait_enable;
34 u8 timer_disable;
35 u8 clk_internal;
36 u8 cs_hold;
37 u8 intr_level;
38 u8 poll_mode;
39 u8 use_dma;
40 u8 c2tdelay;
41 u8 t2cdelay;
42};
43
44#endif /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
index 52827567841d..9b885298f106 100644
--- a/arch/arm/mach-davinci/include/mach/timex.h
+++ b/arch/arm/mach-davinci/include/mach/timex.h
@@ -11,7 +11,12 @@
11#ifndef __ASM_ARCH_TIMEX_H 11#ifndef __ASM_ARCH_TIMEX_H
12#define __ASM_ARCH_TIMEX_H 12#define __ASM_ARCH_TIMEX_H
13 13
14/* The source frequency for the timers is the 27MHz clock */ 14/*
15 * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz,
16 * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/
17 * linux/jiffies.h) are not used directly in code. Currently none of the
18 * code relevant to DaVinci platform depends on these values directly.
19 */
15#define CLOCK_TICK_RATE 27000000 20#define CLOCK_TICK_RATE 27000000
16 21
17#endif /* __ASM_ARCH_TIMEX_H__ */ 22#endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
new file mode 100644
index 000000000000..fab953b43dea
--- /dev/null
+++ b/arch/arm/mach-davinci/pm.c
@@ -0,0 +1,158 @@
1/*
2 * DaVinci Power Management Routines
3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/spinlock.h>
17
18#include <asm/cacheflush.h>
19#include <asm/delay.h>
20
21#include <mach/da8xx.h>
22#include <mach/sram.h>
23#include <mach/pm.h>
24
25#include "clock.h"
26
27#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF
28
29static void (*davinci_sram_suspend) (struct davinci_pm_config *);
30static struct davinci_pm_config *pdata;
31
32static void davinci_sram_push(void *dest, void *src, unsigned int size)
33{
34 memcpy(dest, src, size);
35 flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
36}
37
38static void davinci_pm_suspend(void)
39{
40 unsigned val;
41
42 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
43
44 /* Switch CPU PLL to bypass mode */
45 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
46 val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
47 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
48
49 udelay(PLL_BYPASS_TIME);
50
51 /* Powerdown CPU PLL */
52 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
53 val |= PLLCTL_PLLPWRDN;
54 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
55 }
56
57 /* Configure sleep count in deep sleep register */
58 val = __raw_readl(pdata->deepsleep_reg);
59 val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
60 val |= pdata->sleepcount;
61 __raw_writel(val, pdata->deepsleep_reg);
62
63 /* System goes to sleep in this call */
64 davinci_sram_suspend(pdata);
65
66 if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
67
68 /* put CPU PLL in reset */
69 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
70 val &= ~PLLCTL_PLLRST;
71 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
72
73 /* put CPU PLL in power down */
74 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
75 val &= ~PLLCTL_PLLPWRDN;
76 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
77
78 /* wait for CPU PLL reset */
79 udelay(PLL_RESET_TIME);
80
81 /* bring CPU PLL out of reset */
82 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
83 val |= PLLCTL_PLLRST;
84 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
85
86 /* Wait for CPU PLL to lock */
87 udelay(PLL_LOCK_TIME);
88
89 /* Remove CPU PLL from bypass mode */
90 val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
91 val &= ~PLLCTL_PLLENSRC;
92 val |= PLLCTL_PLLEN;
93 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
94 }
95}
96
97static int davinci_pm_enter(suspend_state_t state)
98{
99 int ret = 0;
100
101 switch (state) {
102 case PM_SUSPEND_STANDBY:
103 case PM_SUSPEND_MEM:
104 davinci_pm_suspend();
105 break;
106 default:
107 ret = -EINVAL;
108 }
109
110 return ret;
111}
112
113static struct platform_suspend_ops davinci_pm_ops = {
114 .enter = davinci_pm_enter,
115 .valid = suspend_valid_only_mem,
116};
117
118static int __init davinci_pm_probe(struct platform_device *pdev)
119{
120 pdata = pdev->dev.platform_data;
121 if (!pdata) {
122 dev_err(&pdev->dev, "cannot get platform data\n");
123 return -ENOENT;
124 }
125
126 davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
127 if (!davinci_sram_suspend) {
128 dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
129 return -ENOMEM;
130 }
131
132 davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
133 davinci_cpu_suspend_sz);
134
135 suspend_set_ops(&davinci_pm_ops);
136
137 return 0;
138}
139
140static int __exit davinci_pm_remove(struct platform_device *pdev)
141{
142 sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
143 return 0;
144}
145
146static struct platform_driver davinci_pm_driver = {
147 .driver = {
148 .name = "pm-davinci",
149 .owner = THIS_MODULE,
150 },
151 .remove = __exit_p(davinci_pm_remove),
152};
153
154static int __init davinci_pm_init(void)
155{
156 return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
157}
158late_initcall(davinci_pm_init);
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 04a3cb72c5ab..adf6b5c7f1e5 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -25,17 +25,6 @@
25#include <mach/cputype.h> 25#include <mach/cputype.h>
26#include <mach/psc.h> 26#include <mach/psc.h>
27 27
28/* PSC register offsets */
29#define EPCPR 0x070
30#define PTCMD 0x120
31#define PTSTAT 0x128
32#define PDSTAT 0x200
33#define PDCTL1 0x304
34#define MDSTAT 0x800
35#define MDCTL 0xA00
36
37#define MDSTAT_STATE_MASK 0x1f
38
39/* Return nonzero iff the domain's clock is active */ 28/* Return nonzero iff the domain's clock is active */
40int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id) 29int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
41{ 30{
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
new file mode 100644
index 000000000000..fb5e72b532b0
--- /dev/null
+++ b/arch/arm/mach-davinci/sleep.S
@@ -0,0 +1,224 @@
1/*
2 * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
16 * MA 02111-1307 USA
17 */
18
19/* replicated define because linux/bitops.h cannot be included in assembly */
20#define BIT(nr) (1 << (nr))
21
22#include <linux/linkage.h>
23#include <asm/assembler.h>
24#include <mach/psc.h>
25#include <mach/memory.h>
26
27#include "clock.h"
28
29/* Arbitrary, hardware currently does not update PHYRDY correctly */
30#define PHYRDY_CYCLES 0x1000
31
32/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
33#define PLL_BYPASS_CYCLES (PLL_BYPASS_TIME * 25)
34#define PLL_RESET_CYCLES (PLL_RESET_TIME * 25)
35#define PLL_LOCK_CYCLES (PLL_LOCK_TIME * 25)
36
37#define DEEPSLEEP_SLEEPENABLE_BIT BIT(31)
38
39 .text
40/*
41 * Move DaVinci into deep sleep state
42 *
43 * Note: This code is copied to internal SRAM by PM code. When the DaVinci
44 * wakes up it continues execution at the point it went to sleep.
45 * Register Usage:
46 * r0: contains virtual base for DDR2 controller
47 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
48 * r2: contains PSC number for DDR2
49 * r3: contains virtual base DDR2 PLL controller
50 * r4: contains virtual address of the DEEPSLEEP register
51 */
52ENTRY(davinci_cpu_suspend)
53 stmfd sp!, {r0-r12, lr} @ save registers on stack
54
55 ldr ip, CACHE_FLUSH
56 blx ip
57
58 ldmia r0, {r0-r4}
59
60 /*
61 * Switch DDR to self-refresh mode.
62 */
63
64 /* calculate SDRCR address */
65 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
66 bic ip, ip, #DDR2_SRPD_BIT
67 orr ip, ip, #DDR2_LPMODEN_BIT
68 str ip, [r0, #DDR2_SDRCR_OFFSET]
69
70 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
71 orr ip, ip, #DDR2_MCLKSTOPEN_BIT
72 str ip, [r0, #DDR2_SDRCR_OFFSET]
73
74 mov ip, #PHYRDY_CYCLES
751: subs ip, ip, #0x1
76 bne 1b
77
78 /* Disable DDR2 LPSC */
79 mov r7, r0
80 mov r0, #0x2
81 bl davinci_ddr_psc_config
82 mov r0, r7
83
84 /* Disable clock to DDR PHY */
85 ldr ip, [r3, #PLLDIV1]
86 bic ip, ip, #PLLDIV_EN
87 str ip, [r3, #PLLDIV1]
88
89 /* Put the DDR PLL in bypass and power down */
90 ldr ip, [r3, #PLLCTL]
91 bic ip, ip, #PLLCTL_PLLENSRC
92 bic ip, ip, #PLLCTL_PLLEN
93 str ip, [r3, #PLLCTL]
94
95 /* Wait for PLL to switch to bypass */
96 mov ip, #PLL_BYPASS_CYCLES
972: subs ip, ip, #0x1
98 bne 2b
99
100 /* Power down the PLL */
101 ldr ip, [r3, #PLLCTL]
102 orr ip, ip, #PLLCTL_PLLPWRDN
103 str ip, [r3, #PLLCTL]
104
105 /* Go to deep sleep */
106 ldr ip, [r4]
107 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
108 /* System goes to sleep beyond after this instruction */
109 str ip, [r4]
110
111 /* Wake up from sleep */
112
113 /* Clear sleep enable */
114 ldr ip, [r4]
115 bic ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
116 str ip, [r4]
117
118 /* initialize the DDR PLL controller */
119
120 /* Put PLL in reset */
121 ldr ip, [r3, #PLLCTL]
122 bic ip, ip, #PLLCTL_PLLRST
123 str ip, [r3, #PLLCTL]
124
125 /* Clear PLL power down */
126 ldr ip, [r3, #PLLCTL]
127 bic ip, ip, #PLLCTL_PLLPWRDN
128 str ip, [r3, #PLLCTL]
129
130 mov ip, #PLL_RESET_CYCLES
1313: subs ip, ip, #0x1
132 bne 3b
133
134 /* Bring PLL out of reset */
135 ldr ip, [r3, #PLLCTL]
136 orr ip, ip, #PLLCTL_PLLRST
137 str ip, [r3, #PLLCTL]
138
139 /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
140 mov ip, #PLL_LOCK_CYCLES
1414: subs ip, ip, #0x1
142 bne 4b
143
144 /* Remove PLL from bypass mode */
145 ldr ip, [r3, #PLLCTL]
146 bic ip, ip, #PLLCTL_PLLENSRC
147 orr ip, ip, #PLLCTL_PLLEN
148 str ip, [r3, #PLLCTL]
149
150 /* Start 2x clock to DDR2 */
151
152 ldr ip, [r3, #PLLDIV1]
153 orr ip, ip, #PLLDIV_EN
154 str ip, [r3, #PLLDIV1]
155
156 /* Enable VCLK */
157
158 /* Enable DDR2 LPSC */
159 mov r7, r0
160 mov r0, #0x3
161 bl davinci_ddr_psc_config
162 mov r0, r7
163
164 /* clear MCLKSTOPEN */
165
166 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
167 bic ip, ip, #DDR2_MCLKSTOPEN_BIT
168 str ip, [r0, #DDR2_SDRCR_OFFSET]
169
170 ldr ip, [r0, #DDR2_SDRCR_OFFSET]
171 bic ip, ip, #DDR2_LPMODEN_BIT
172 str ip, [r0, #DDR2_SDRCR_OFFSET]
173
174 /* Restore registers and return */
175 ldmfd sp!, {r0-r12, pc}
176
177ENDPROC(davinci_cpu_suspend)
178
179/*
180 * Disables or Enables DDR2 LPSC
181 * Register Usage:
182 * r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
183 * r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
184 * r2: contains PSC number for DDR2
185 */
186ENTRY(davinci_ddr_psc_config)
187 /* Set next state in mdctl for DDR2 */
188 mov r6, #MDCTL
189 add r6, r6, r2, lsl #2
190 ldr ip, [r1, r6]
191 bic ip, ip, #MDSTAT_STATE_MASK
192 orr ip, ip, r0
193 str ip, [r1, r6]
194
195 /* Enable the Power Domain Transition Command */
196 ldr ip, [r1, #PTCMD]
197 orr ip, ip, #0x1
198 str ip, [r1, #PTCMD]
199
200 /* Check for Transition Complete (PTSTAT) */
201ptstat_done:
202 ldr ip, [r1, #PTSTAT]
203 and ip, ip, #0x1
204 cmp ip, #0x0
205 bne ptstat_done
206
207 /* Check for DDR2 clock disable completion; */
208 mov r6, #MDSTAT
209 add r6, r6, r2, lsl #2
210ddr2clk_stop_done:
211 ldr ip, [r1, r6]
212 and ip, ip, #MDSTAT_STATE_MASK
213 cmp ip, r0
214 bne ddr2clk_stop_done
215
216 mov pc, lr
217ENDPROC(davinci_ddr_psc_config)
218
219CACHE_FLUSH:
220 .word arm926_flush_kern_cache_all
221
222ENTRY(davinci_cpu_suspend_sz)
223 .word . - davinci_cpu_suspend
224ENDPROC(davinci_cpu_suspend_sz)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 15:09:13 -0500