diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-05-25 15:06:33 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-05-25 15:06:33 -0400 |
| commit | ec96e2fe954c23a54bfdf2673437a39e193a1822 (patch) | |
| tree | e4041c68ef20a3337c56aefc8db785156307edd1 /arch | |
| parent | 8e9815a0f8882aaa68645b001bb7538db8886802 (diff) | |
| parent | f949c0edd84101bfd30b3e7389c1a12b067e561d (diff) | |
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (103 commits)
ARM: 6141/1: Add audio support part in arch/arm/mach-w90x900
ARM: 5939/1: ARM: Add option CMDLINE_FORCE to force usage of the in-kernel cmdline
ARM: 6140/1: silence a bogus sparse warning in unwind.c
ARM: mach-at91: duplicated include
ARM: arch/arm/nwfpe/fpsr.h: Checkpatch cleanup
ARM: arch/arm/mach-shark/pci.c: Checkpatch cleanup
ARM: arch/arm/nwfpe/ChangeLog: Checkpatch cleanup
ARM: arch/arm/mach-sa1100/leds.c: Checkpatch cleanup
ARM: arch/arm/mach-h720x/common.h: Checkpatch cleanup
ARM: arch/arm/mach-footbridge/ebsa285-pci.c: Checkpatch cleanup
ARM: arch/arm/mach-clps711x/Makefile.boot: Checkpatch cleanup
ARM: arch/arm/boot/bootp/bootp.lds: Checkpatch cleanup
ARM: SPEAR6xx: remove duplicated #include
ARM: s3c6400_defconfig: Add NAND driver
ARM: s3c6400_defconfig: enable sound as modules
ARM: s3c6400_defconfig: enable power management
ARM: s5pv210_defconfig: Update s5pv210_defconfig to v2.6.34
ARM: s5pc110_defconfig: Update s5pc110_defconfig to v2.6.34
ARM: s5p6442_defconfig: Update s5p6442_defconfig to v2.6.34
ARM: s5p6440_defconfig: Update s5p6440_defconfig to v2.6.34
...
Diffstat (limited to 'arch')
167 files changed, 5804 insertions, 3817 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d70cece2ea2..1f254bd6c937 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -671,6 +671,7 @@ config ARCH_S5P6440 | |||
| 671 | select CPU_V6 | 671 | select CPU_V6 |
| 672 | select GENERIC_GPIO | 672 | select GENERIC_GPIO |
| 673 | select HAVE_CLK | 673 | select HAVE_CLK |
| 674 | select ARCH_USES_GETTIMEOFFSET | ||
| 674 | help | 675 | help |
| 675 | Samsung S5P6440 CPU based systems | 676 | Samsung S5P6440 CPU based systems |
| 676 | 677 | ||
| @@ -679,17 +680,19 @@ config ARCH_S5P6442 | |||
| 679 | select CPU_V6 | 680 | select CPU_V6 |
| 680 | select GENERIC_GPIO | 681 | select GENERIC_GPIO |
| 681 | select HAVE_CLK | 682 | select HAVE_CLK |
| 683 | select ARCH_USES_GETTIMEOFFSET | ||
| 682 | help | 684 | help |
| 683 | Samsung S5P6442 CPU based systems | 685 | Samsung S5P6442 CPU based systems |
| 684 | 686 | ||
| 685 | config ARCH_S5PC1XX | 687 | config ARCH_S5PC100 |
| 686 | bool "Samsung S5PC1XX" | 688 | bool "Samsung S5PC100" |
| 687 | select GENERIC_GPIO | 689 | select GENERIC_GPIO |
| 688 | select HAVE_CLK | 690 | select HAVE_CLK |
| 689 | select CPU_V7 | 691 | select CPU_V7 |
| 690 | select ARM_L1_CACHE_SHIFT_6 | 692 | select ARM_L1_CACHE_SHIFT_6 |
| 693 | select ARCH_USES_GETTIMEOFFSET | ||
| 691 | help | 694 | help |
| 692 | Samsung S5PC1XX series based systems | 695 | Samsung S5PC100 series based systems |
| 693 | 696 | ||
| 694 | config ARCH_S5PV210 | 697 | config ARCH_S5PV210 |
| 695 | bool "Samsung S5PV210/S5PC110" | 698 | bool "Samsung S5PV210/S5PC110" |
| @@ -697,6 +700,7 @@ config ARCH_S5PV210 | |||
| 697 | select GENERIC_GPIO | 700 | select GENERIC_GPIO |
| 698 | select HAVE_CLK | 701 | select HAVE_CLK |
| 699 | select ARM_L1_CACHE_SHIFT_6 | 702 | select ARM_L1_CACHE_SHIFT_6 |
| 703 | select ARCH_USES_GETTIMEOFFSET | ||
| 700 | help | 704 | help |
| 701 | Samsung S5PV210/S5PC110 series based systems | 705 | Samsung S5PV210/S5PC110 series based systems |
| 702 | 706 | ||
| @@ -876,7 +880,7 @@ source "arch/arm/mach-sa1100/Kconfig" | |||
| 876 | source "arch/arm/plat-samsung/Kconfig" | 880 | source "arch/arm/plat-samsung/Kconfig" |
| 877 | source "arch/arm/plat-s3c24xx/Kconfig" | 881 | source "arch/arm/plat-s3c24xx/Kconfig" |
| 878 | source "arch/arm/plat-s5p/Kconfig" | 882 | source "arch/arm/plat-s5p/Kconfig" |
| 879 | source "arch/arm/plat-s5pc1xx/Kconfig" | 883 | |
| 880 | source "arch/arm/plat-spear/Kconfig" | 884 | source "arch/arm/plat-spear/Kconfig" |
| 881 | 885 | ||
| 882 | if ARCH_S3C2410 | 886 | if ARCH_S3C2410 |
| @@ -896,9 +900,7 @@ source "arch/arm/mach-s5p6440/Kconfig" | |||
| 896 | 900 | ||
| 897 | source "arch/arm/mach-s5p6442/Kconfig" | 901 | source "arch/arm/mach-s5p6442/Kconfig" |
| 898 | 902 | ||
| 899 | if ARCH_S5PC1XX | ||
| 900 | source "arch/arm/mach-s5pc100/Kconfig" | 903 | source "arch/arm/mach-s5pc100/Kconfig" |
| 901 | endif | ||
| 902 | 904 | ||
| 903 | source "arch/arm/mach-s5pv210/Kconfig" | 905 | source "arch/arm/mach-s5pv210/Kconfig" |
| 904 | 906 | ||
| @@ -1419,6 +1421,17 @@ config CMDLINE | |||
| 1419 | time by entering them here. As a minimum, you should specify the | 1421 | time by entering them here. As a minimum, you should specify the |
| 1420 | memory size and the root device (e.g., mem=64M root=/dev/nfs). | 1422 | memory size and the root device (e.g., mem=64M root=/dev/nfs). |
| 1421 | 1423 | ||
| 1424 | config CMDLINE_FORCE | ||
| 1425 | bool "Always use the default kernel command string" | ||
| 1426 | depends on CMDLINE != "" | ||
| 1427 | help | ||
| 1428 | Always use the default kernel command string, even if the boot | ||
| 1429 | loader passes other arguments to the kernel. | ||
| 1430 | This is useful if you cannot or don't want to change the | ||
| 1431 | command-line options your boot loader passes to the kernel. | ||
| 1432 | |||
| 1433 | If unsure, say N. | ||
| 1434 | |||
| 1422 | config XIP_KERNEL | 1435 | config XIP_KERNEL |
| 1423 | bool "Kernel Execute-In-Place from ROM" | 1436 | bool "Kernel Execute-In-Place from ROM" |
| 1424 | depends on !ZBOOT_ROM | 1437 | depends on !ZBOOT_ROM |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b857fbe4314..64ba313724d2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -168,7 +168,7 @@ machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0 | |||
| 168 | machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx | 168 | machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx |
| 169 | machine-$(CONFIG_ARCH_S5P6440) := s5p6440 | 169 | machine-$(CONFIG_ARCH_S5P6440) := s5p6440 |
| 170 | machine-$(CONFIG_ARCH_S5P6442) := s5p6442 | 170 | machine-$(CONFIG_ARCH_S5P6442) := s5p6442 |
| 171 | machine-$(CONFIG_ARCH_S5PC1XX) := s5pc100 | 171 | machine-$(CONFIG_ARCH_S5PC100) := s5pc100 |
| 172 | machine-$(CONFIG_ARCH_S5PV210) := s5pv210 | 172 | machine-$(CONFIG_ARCH_S5PV210) := s5pv210 |
| 173 | machine-$(CONFIG_ARCH_SA1100) := sa1100 | 173 | machine-$(CONFIG_ARCH_SA1100) := sa1100 |
| 174 | machine-$(CONFIG_ARCH_SHARK) := shark | 174 | machine-$(CONFIG_ARCH_SHARK) := shark |
| @@ -198,7 +198,6 @@ plat-$(CONFIG_PLAT_NOMADIK) := nomadik | |||
| 198 | plat-$(CONFIG_PLAT_ORION) := orion | 198 | plat-$(CONFIG_PLAT_ORION) := orion |
| 199 | plat-$(CONFIG_PLAT_PXA) := pxa | 199 | plat-$(CONFIG_PLAT_PXA) := pxa |
| 200 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung | 200 | plat-$(CONFIG_PLAT_S3C24XX) := s3c24xx samsung |
| 201 | plat-$(CONFIG_PLAT_S5PC1XX) := s5pc1xx samsung | ||
| 202 | plat-$(CONFIG_PLAT_S5P) := s5p samsung | 201 | plat-$(CONFIG_PLAT_S5P) := s5p samsung |
| 203 | plat-$(CONFIG_PLAT_SPEAR) := spear | 202 | plat-$(CONFIG_PLAT_SPEAR) := spear |
| 204 | plat-$(CONFIG_PLAT_VERSATILE) := versatile | 203 | plat-$(CONFIG_PLAT_VERSATILE) := versatile |
diff --git a/arch/arm/boot/bootp/bootp.lds b/arch/arm/boot/bootp/bootp.lds index 8e3d81ce695e..fc54394f4340 100644 --- a/arch/arm/boot/bootp/bootp.lds +++ b/arch/arm/boot/bootp/bootp.lds | |||
| @@ -19,7 +19,7 @@ SECTIONS | |||
| 19 | initrd_size = initrd_end - initrd_start; | 19 | initrd_size = initrd_end - initrd_start; |
| 20 | _etext = .; | 20 | _etext = .; |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | .stab 0 : { *(.stab) } | 23 | .stab 0 : { *(.stab) } |
| 24 | .stabstr 0 : { *(.stabstr) } | 24 | .stabstr 0 : { *(.stabstr) } |
| 25 | .stab.excl 0 : { *(.stab.excl) } | 25 | .stab.excl 0 : { *(.stab.excl) } |
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig index c88e9527a8ec..a708fd6d6ffe 100644 --- a/arch/arm/configs/mx51_defconfig +++ b/arch/arm/configs/mx51_defconfig | |||
| @@ -809,7 +809,22 @@ CONFIG_SSB_POSSIBLE=y | |||
| 809 | CONFIG_DUMMY_CONSOLE=y | 809 | CONFIG_DUMMY_CONSOLE=y |
| 810 | # CONFIG_SOUND is not set | 810 | # CONFIG_SOUND is not set |
| 811 | # CONFIG_HID_SUPPORT is not set | 811 | # CONFIG_HID_SUPPORT is not set |
| 812 | # CONFIG_USB_SUPPORT is not set | 812 | CONFIG_USB_SUPPORT=y |
| 813 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 814 | # CONFIG_USB_ARCH_HAS_OHCI is not set | ||
| 815 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 816 | CONFIG_USB=y | ||
| 817 | |||
| 818 | # | ||
| 819 | # USB Host Controller Drivers | ||
| 820 | # | ||
| 821 | # CONFIG_USB_C67X00_HCD is not set | ||
| 822 | CONFIG_USB_EHCI_HCD=y | ||
| 823 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | ||
| 824 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | ||
| 825 | CONFIG_USB_EHCI_MXC=y | ||
| 826 | |||
| 827 | |||
| 813 | CONFIG_MMC=y | 828 | CONFIG_MMC=y |
| 814 | # CONFIG_MMC_DEBUG is not set | 829 | # CONFIG_MMC_DEBUG is not set |
| 815 | # CONFIG_MMC_UNSAFE_RESUME is not set | 830 | # CONFIG_MMC_UNSAFE_RESUME is not set |
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig index 8e94c3caeb8c..9236475e7131 100644 --- a/arch/arm/configs/s3c2410_defconfig +++ b/arch/arm/configs/s3c2410_defconfig | |||
| @@ -1,14 +1,13 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.30-rc2 | 3 | # Linux kernel version: 2.6.34 |
| 4 | # Sat May 22 03:17:31 2010 | ||
| 4 | # | 5 | # |
| 5 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 6 | CONFIG_HAVE_PWM=y | 7 | CONFIG_HAVE_PWM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 8 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 9 | CONFIG_GENERIC_GPIO=y |
| 9 | # CONFIG_GENERIC_TIME is not set | 10 | CONFIG_HAVE_PROC_CPU=y |
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | CONFIG_NO_IOPORT=y | 11 | CONFIG_NO_IOPORT=y |
| 13 | CONFIG_GENERIC_HARDIRQS=y | 12 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 13 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -18,13 +17,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y | |||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | 17 | CONFIG_HARDIRQS_SW_RESEND=y |
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | 18 | CONFIG_GENERIC_IRQ_PROBE=y |
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | 20 | CONFIG_ARCH_HAS_CPUFREQ=y |
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | 21 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 22 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 23 | CONFIG_NEED_DMA_MAP_STATE=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 24 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | 25 | CONFIG_VECTORS_BASE=0xffff0000 |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 26 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 27 | CONFIG_CONSTRUCTORS=y | ||
| 28 | 28 | ||
| 29 | # | 29 | # |
| 30 | # General setup | 30 | # General setup |
| @@ -34,6 +34,12 @@ CONFIG_BROKEN_ON_SMP=y | |||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 35 | CONFIG_LOCALVERSION="" | 35 | CONFIG_LOCALVERSION="" |
| 36 | CONFIG_LOCALVERSION_AUTO=y | 36 | CONFIG_LOCALVERSION_AUTO=y |
| 37 | CONFIG_HAVE_KERNEL_GZIP=y | ||
| 38 | CONFIG_HAVE_KERNEL_LZO=y | ||
| 39 | CONFIG_KERNEL_GZIP=y | ||
| 40 | # CONFIG_KERNEL_BZIP2 is not set | ||
| 41 | # CONFIG_KERNEL_LZMA is not set | ||
| 42 | # CONFIG_KERNEL_LZO is not set | ||
| 37 | CONFIG_SWAP=y | 43 | CONFIG_SWAP=y |
| 38 | CONFIG_SYSVIPC=y | 44 | CONFIG_SYSVIPC=y |
| 39 | CONFIG_SYSVIPC_SYSCTL=y | 45 | CONFIG_SYSVIPC_SYSCTL=y |
| @@ -45,15 +51,16 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 45 | # | 51 | # |
| 46 | # RCU Subsystem | 52 | # RCU Subsystem |
| 47 | # | 53 | # |
| 48 | CONFIG_CLASSIC_RCU=y | 54 | CONFIG_TREE_RCU=y |
| 49 | # CONFIG_TREE_RCU is not set | 55 | # CONFIG_TREE_PREEMPT_RCU is not set |
| 50 | # CONFIG_PREEMPT_RCU is not set | 56 | # CONFIG_TINY_RCU is not set |
| 57 | # CONFIG_RCU_TRACE is not set | ||
| 58 | CONFIG_RCU_FANOUT=32 | ||
| 59 | # CONFIG_RCU_FANOUT_EXACT is not set | ||
| 51 | # CONFIG_TREE_RCU_TRACE is not set | 60 | # CONFIG_TREE_RCU_TRACE is not set |
| 52 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 53 | CONFIG_IKCONFIG=m | 61 | CONFIG_IKCONFIG=m |
| 54 | CONFIG_IKCONFIG_PROC=y | 62 | CONFIG_IKCONFIG_PROC=y |
| 55 | CONFIG_LOG_BUF_SHIFT=16 | 63 | CONFIG_LOG_BUF_SHIFT=16 |
| 56 | # CONFIG_GROUP_SCHED is not set | ||
| 57 | # CONFIG_CGROUPS is not set | 64 | # CONFIG_CGROUPS is not set |
| 58 | CONFIG_SYSFS_DEPRECATED=y | 65 | CONFIG_SYSFS_DEPRECATED=y |
| 59 | CONFIG_SYSFS_DEPRECATED_V2=y | 66 | CONFIG_SYSFS_DEPRECATED_V2=y |
| @@ -69,6 +76,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 69 | CONFIG_RD_GZIP=y | 76 | CONFIG_RD_GZIP=y |
| 70 | CONFIG_RD_BZIP2=y | 77 | CONFIG_RD_BZIP2=y |
| 71 | CONFIG_RD_LZMA=y | 78 | CONFIG_RD_LZMA=y |
| 79 | CONFIG_RD_LZO=y | ||
| 72 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 80 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 73 | CONFIG_SYSCTL=y | 81 | CONFIG_SYSCTL=y |
| 74 | CONFIG_ANON_INODES=y | 82 | CONFIG_ANON_INODES=y |
| @@ -78,7 +86,6 @@ CONFIG_SYSCTL_SYSCALL=y | |||
| 78 | CONFIG_KALLSYMS=y | 86 | CONFIG_KALLSYMS=y |
| 79 | # CONFIG_KALLSYMS_ALL is not set | 87 | # CONFIG_KALLSYMS_ALL is not set |
| 80 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 88 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 81 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 82 | CONFIG_HOTPLUG=y | 89 | CONFIG_HOTPLUG=y |
| 83 | CONFIG_PRINTK=y | 90 | CONFIG_PRINTK=y |
| 84 | CONFIG_BUG=y | 91 | CONFIG_BUG=y |
| @@ -91,19 +98,30 @@ CONFIG_TIMERFD=y | |||
| 91 | CONFIG_EVENTFD=y | 98 | CONFIG_EVENTFD=y |
| 92 | CONFIG_SHMEM=y | 99 | CONFIG_SHMEM=y |
| 93 | CONFIG_AIO=y | 100 | CONFIG_AIO=y |
| 101 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 102 | CONFIG_PERF_USE_VMALLOC=y | ||
| 103 | |||
| 104 | # | ||
| 105 | # Kernel Performance Events And Counters | ||
| 106 | # | ||
| 107 | # CONFIG_PERF_EVENTS is not set | ||
| 108 | # CONFIG_PERF_COUNTERS is not set | ||
| 94 | CONFIG_VM_EVENT_COUNTERS=y | 109 | CONFIG_VM_EVENT_COUNTERS=y |
| 95 | CONFIG_COMPAT_BRK=y | 110 | CONFIG_COMPAT_BRK=y |
| 96 | CONFIG_SLAB=y | 111 | CONFIG_SLAB=y |
| 97 | # CONFIG_SLUB is not set | 112 | # CONFIG_SLUB is not set |
| 98 | # CONFIG_SLOB is not set | 113 | # CONFIG_SLOB is not set |
| 99 | # CONFIG_PROFILING is not set | 114 | # CONFIG_PROFILING is not set |
| 100 | # CONFIG_MARKERS is not set | ||
| 101 | CONFIG_HAVE_OPROFILE=y | 115 | CONFIG_HAVE_OPROFILE=y |
| 102 | # CONFIG_KPROBES is not set | 116 | # CONFIG_KPROBES is not set |
| 103 | CONFIG_HAVE_KPROBES=y | 117 | CONFIG_HAVE_KPROBES=y |
| 104 | CONFIG_HAVE_KRETPROBES=y | 118 | CONFIG_HAVE_KRETPROBES=y |
| 105 | CONFIG_HAVE_CLK=y | 119 | CONFIG_HAVE_CLK=y |
| 106 | # CONFIG_SLOW_WORK is not set | 120 | |
| 121 | # | ||
| 122 | # GCOV-based kernel profiling | ||
| 123 | # | ||
| 124 | CONFIG_SLOW_WORK=y | ||
| 107 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 125 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 108 | CONFIG_SLABINFO=y | 126 | CONFIG_SLABINFO=y |
| 109 | CONFIG_RT_MUTEXES=y | 127 | CONFIG_RT_MUTEXES=y |
| @@ -115,7 +133,7 @@ CONFIG_MODULE_UNLOAD=y | |||
| 115 | # CONFIG_MODVERSIONS is not set | 133 | # CONFIG_MODVERSIONS is not set |
| 116 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 134 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 117 | CONFIG_BLOCK=y | 135 | CONFIG_BLOCK=y |
| 118 | # CONFIG_LBD is not set | 136 | CONFIG_LBDAF=y |
| 119 | # CONFIG_BLK_DEV_BSG is not set | 137 | # CONFIG_BLK_DEV_BSG is not set |
| 120 | # CONFIG_BLK_DEV_INTEGRITY is not set | 138 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 121 | 139 | ||
| @@ -123,32 +141,62 @@ CONFIG_BLOCK=y | |||
| 123 | # IO Schedulers | 141 | # IO Schedulers |
| 124 | # | 142 | # |
| 125 | CONFIG_IOSCHED_NOOP=y | 143 | CONFIG_IOSCHED_NOOP=y |
| 126 | CONFIG_IOSCHED_AS=y | ||
| 127 | CONFIG_IOSCHED_DEADLINE=y | 144 | CONFIG_IOSCHED_DEADLINE=y |
| 128 | CONFIG_IOSCHED_CFQ=y | 145 | CONFIG_IOSCHED_CFQ=y |
| 129 | CONFIG_DEFAULT_AS=y | ||
| 130 | # CONFIG_DEFAULT_DEADLINE is not set | 146 | # CONFIG_DEFAULT_DEADLINE is not set |
| 131 | # CONFIG_DEFAULT_CFQ is not set | 147 | CONFIG_DEFAULT_CFQ=y |
| 132 | # CONFIG_DEFAULT_NOOP is not set | 148 | # CONFIG_DEFAULT_NOOP is not set |
| 133 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 149 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 150 | # CONFIG_INLINE_SPIN_TRYLOCK is not set | ||
| 151 | # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set | ||
| 152 | # CONFIG_INLINE_SPIN_LOCK is not set | ||
| 153 | # CONFIG_INLINE_SPIN_LOCK_BH is not set | ||
| 154 | # CONFIG_INLINE_SPIN_LOCK_IRQ is not set | ||
| 155 | # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set | ||
| 156 | CONFIG_INLINE_SPIN_UNLOCK=y | ||
| 157 | # CONFIG_INLINE_SPIN_UNLOCK_BH is not set | ||
| 158 | CONFIG_INLINE_SPIN_UNLOCK_IRQ=y | ||
| 159 | # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set | ||
| 160 | # CONFIG_INLINE_READ_TRYLOCK is not set | ||
| 161 | # CONFIG_INLINE_READ_LOCK is not set | ||
| 162 | # CONFIG_INLINE_READ_LOCK_BH is not set | ||
| 163 | # CONFIG_INLINE_READ_LOCK_IRQ is not set | ||
| 164 | # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set | ||
| 165 | CONFIG_INLINE_READ_UNLOCK=y | ||
| 166 | # CONFIG_INLINE_READ_UNLOCK_BH is not set | ||
| 167 | CONFIG_INLINE_READ_UNLOCK_IRQ=y | ||
| 168 | # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set | ||
| 169 | # CONFIG_INLINE_WRITE_TRYLOCK is not set | ||
| 170 | # CONFIG_INLINE_WRITE_LOCK is not set | ||
| 171 | # CONFIG_INLINE_WRITE_LOCK_BH is not set | ||
| 172 | # CONFIG_INLINE_WRITE_LOCK_IRQ is not set | ||
| 173 | # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set | ||
| 174 | CONFIG_INLINE_WRITE_UNLOCK=y | ||
| 175 | # CONFIG_INLINE_WRITE_UNLOCK_BH is not set | ||
| 176 | CONFIG_INLINE_WRITE_UNLOCK_IRQ=y | ||
| 177 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | ||
| 178 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | ||
| 134 | CONFIG_FREEZER=y | 179 | CONFIG_FREEZER=y |
| 135 | 180 | ||
| 136 | # | 181 | # |
| 137 | # System Type | 182 | # System Type |
| 138 | # | 183 | # |
| 184 | CONFIG_MMU=y | ||
| 139 | # CONFIG_ARCH_AAEC2000 is not set | 185 | # CONFIG_ARCH_AAEC2000 is not set |
| 140 | # CONFIG_ARCH_INTEGRATOR is not set | 186 | # CONFIG_ARCH_INTEGRATOR is not set |
| 141 | # CONFIG_ARCH_REALVIEW is not set | 187 | # CONFIG_ARCH_REALVIEW is not set |
| 142 | # CONFIG_ARCH_VERSATILE is not set | 188 | # CONFIG_ARCH_VERSATILE is not set |
| 143 | # CONFIG_ARCH_AT91 is not set | 189 | # CONFIG_ARCH_AT91 is not set |
| 190 | # CONFIG_ARCH_BCMRING is not set | ||
| 144 | # CONFIG_ARCH_CLPS711X is not set | 191 | # CONFIG_ARCH_CLPS711X is not set |
| 192 | # CONFIG_ARCH_GEMINI is not set | ||
| 145 | # CONFIG_ARCH_EBSA110 is not set | 193 | # CONFIG_ARCH_EBSA110 is not set |
| 146 | # CONFIG_ARCH_EP93XX is not set | 194 | # CONFIG_ARCH_EP93XX is not set |
| 147 | # CONFIG_ARCH_GEMINI is not set | ||
| 148 | # CONFIG_ARCH_FOOTBRIDGE is not set | 195 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 196 | # CONFIG_ARCH_MXC is not set | ||
| 197 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 149 | # CONFIG_ARCH_NETX is not set | 198 | # CONFIG_ARCH_NETX is not set |
| 150 | # CONFIG_ARCH_H720X is not set | 199 | # CONFIG_ARCH_H720X is not set |
| 151 | # CONFIG_ARCH_IMX is not set | ||
| 152 | # CONFIG_ARCH_IOP13XX is not set | 200 | # CONFIG_ARCH_IOP13XX is not set |
| 153 | # CONFIG_ARCH_IOP32X is not set | 201 | # CONFIG_ARCH_IOP32X is not set |
| 154 | # CONFIG_ARCH_IOP33X is not set | 202 | # CONFIG_ARCH_IOP33X is not set |
| @@ -156,42 +204,36 @@ CONFIG_FREEZER=y | |||
| 156 | # CONFIG_ARCH_IXP2000 is not set | 204 | # CONFIG_ARCH_IXP2000 is not set |
| 157 | # CONFIG_ARCH_IXP4XX is not set | 205 | # CONFIG_ARCH_IXP4XX is not set |
| 158 | # CONFIG_ARCH_L7200 is not set | 206 | # CONFIG_ARCH_L7200 is not set |
| 207 | # CONFIG_ARCH_DOVE is not set | ||
| 159 | # CONFIG_ARCH_KIRKWOOD is not set | 208 | # CONFIG_ARCH_KIRKWOOD is not set |
| 160 | # CONFIG_ARCH_KS8695 is not set | ||
| 161 | # CONFIG_ARCH_NS9XXX is not set | ||
| 162 | # CONFIG_ARCH_LOKI is not set | 209 | # CONFIG_ARCH_LOKI is not set |
| 163 | # CONFIG_ARCH_MV78XX0 is not set | 210 | # CONFIG_ARCH_MV78XX0 is not set |
| 164 | # CONFIG_ARCH_MXC is not set | ||
| 165 | # CONFIG_ARCH_ORION5X is not set | 211 | # CONFIG_ARCH_ORION5X is not set |
| 212 | # CONFIG_ARCH_MMP is not set | ||
| 213 | # CONFIG_ARCH_KS8695 is not set | ||
| 214 | # CONFIG_ARCH_NS9XXX is not set | ||
| 215 | # CONFIG_ARCH_W90X900 is not set | ||
| 216 | # CONFIG_ARCH_NUC93X is not set | ||
| 166 | # CONFIG_ARCH_PNX4008 is not set | 217 | # CONFIG_ARCH_PNX4008 is not set |
| 167 | # CONFIG_ARCH_PXA is not set | 218 | # CONFIG_ARCH_PXA is not set |
| 168 | # CONFIG_ARCH_MMP is not set | 219 | # CONFIG_ARCH_MSM is not set |
| 220 | # CONFIG_ARCH_SHMOBILE is not set | ||
| 169 | # CONFIG_ARCH_RPC is not set | 221 | # CONFIG_ARCH_RPC is not set |
| 170 | # CONFIG_ARCH_SA1100 is not set | 222 | # CONFIG_ARCH_SA1100 is not set |
| 171 | CONFIG_ARCH_S3C2410=y | 223 | CONFIG_ARCH_S3C2410=y |
| 172 | # CONFIG_ARCH_S3C64XX is not set | 224 | # CONFIG_ARCH_S3C64XX is not set |
| 225 | # CONFIG_ARCH_S5P6440 is not set | ||
| 226 | # CONFIG_ARCH_S5P6442 is not set | ||
| 227 | # CONFIG_ARCH_S5PC1XX is not set | ||
| 228 | # CONFIG_ARCH_S5PV210 is not set | ||
| 173 | # CONFIG_ARCH_SHARK is not set | 229 | # CONFIG_ARCH_SHARK is not set |
| 174 | # CONFIG_ARCH_LH7A40X is not set | 230 | # CONFIG_ARCH_LH7A40X is not set |
| 231 | # CONFIG_ARCH_U300 is not set | ||
| 232 | # CONFIG_ARCH_U8500 is not set | ||
| 233 | # CONFIG_ARCH_NOMADIK is not set | ||
| 175 | # CONFIG_ARCH_DAVINCI is not set | 234 | # CONFIG_ARCH_DAVINCI is not set |
| 176 | # CONFIG_ARCH_OMAP is not set | 235 | # CONFIG_ARCH_OMAP is not set |
| 177 | # CONFIG_ARCH_MSM is not set | 236 | CONFIG_PLAT_SAMSUNG=y |
| 178 | # CONFIG_ARCH_W90X900 is not set | ||
| 179 | CONFIG_PLAT_S3C24XX=y | ||
| 180 | CONFIG_S3C2410_CLOCK=y | ||
| 181 | CONFIG_S3C24XX_DCLK=y | ||
| 182 | CONFIG_CPU_S3C244X=y | ||
| 183 | CONFIG_S3C24XX_PWM=y | ||
| 184 | CONFIG_S3C24XX_GPIO_EXTRA=128 | ||
| 185 | CONFIG_S3C24XX_GPIO_EXTRA64=y | ||
| 186 | CONFIG_S3C24XX_GPIO_EXTRA128=y | ||
| 187 | CONFIG_PM_SIMTEC=y | ||
| 188 | CONFIG_S3C2410_DMA=y | ||
| 189 | # CONFIG_S3C2410_DMA_DEBUG is not set | ||
| 190 | CONFIG_S3C_ADC=y | ||
| 191 | CONFIG_MACH_SMDK=y | ||
| 192 | CONFIG_PLAT_S3C=y | ||
| 193 | CONFIG_CPU_LLSERIAL_S3C2410=y | ||
| 194 | CONFIG_CPU_LLSERIAL_S3C2440=y | ||
| 195 | 237 | ||
| 196 | # | 238 | # |
| 197 | # Boot options | 239 | # Boot options |
| @@ -199,15 +241,35 @@ CONFIG_CPU_LLSERIAL_S3C2440=y | |||
| 199 | # CONFIG_S3C_BOOT_WATCHDOG is not set | 241 | # CONFIG_S3C_BOOT_WATCHDOG is not set |
| 200 | CONFIG_S3C_BOOT_ERROR_RESET=y | 242 | CONFIG_S3C_BOOT_ERROR_RESET=y |
| 201 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | 243 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y |
| 244 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
| 245 | CONFIG_SAMSUNG_CLKSRC=y | ||
| 246 | CONFIG_SAMSUNG_GPIO_EXTRA=0 | ||
| 247 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 248 | CONFIG_S3C_ADC=y | ||
| 249 | CONFIG_S3C_DEV_HSMMC=y | ||
| 250 | CONFIG_S3C_DEV_USB_HOST=y | ||
| 251 | CONFIG_S3C_DEV_NAND=y | ||
| 252 | CONFIG_S3C_DMA=y | ||
| 202 | 253 | ||
| 203 | # | 254 | # |
| 204 | # Power management | 255 | # Power management |
| 205 | # | 256 | # |
| 206 | # CONFIG_SAMSUNG_PM_DEBUG is not set | 257 | # CONFIG_SAMSUNG_PM_DEBUG is not set |
| 207 | # CONFIG_SAMSUNG_PM_CHECK is not set | 258 | # CONFIG_SAMSUNG_PM_CHECK is not set |
| 208 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | 259 | CONFIG_PLAT_S3C24XX=y |
| 209 | CONFIG_S3C_GPIO_SPACE=0 | 260 | CONFIG_CPU_LLSERIAL_S3C2410=y |
| 210 | CONFIG_S3C_DEV_HSMMC=y | 261 | CONFIG_CPU_LLSERIAL_S3C2440=y |
| 262 | CONFIG_S3C2410_CLOCK=y | ||
| 263 | CONFIG_S3C24XX_DCLK=y | ||
| 264 | CONFIG_S3C24XX_PWM=y | ||
| 265 | CONFIG_S3C24XX_GPIO_EXTRA=128 | ||
| 266 | CONFIG_S3C24XX_GPIO_EXTRA64=y | ||
| 267 | CONFIG_S3C24XX_GPIO_EXTRA128=y | ||
| 268 | CONFIG_PM_SIMTEC=y | ||
| 269 | CONFIG_S3C2410_DMA=y | ||
| 270 | # CONFIG_S3C2410_DMA_DEBUG is not set | ||
| 271 | CONFIG_MACH_SMDK=y | ||
| 272 | CONFIG_S3C24XX_SIMTEC_AUDIO=y | ||
| 211 | 273 | ||
| 212 | # | 274 | # |
| 213 | # S3C2400 Machines | 275 | # S3C2400 Machines |
| @@ -224,6 +286,7 @@ CONFIG_MACH_BAST_IDE=y | |||
| 224 | # | 286 | # |
| 225 | CONFIG_ARCH_SMDK2410=y | 287 | CONFIG_ARCH_SMDK2410=y |
| 226 | CONFIG_ARCH_H1940=y | 288 | CONFIG_ARCH_H1940=y |
| 289 | # CONFIG_H1940BT is not set | ||
| 227 | CONFIG_PM_H1940=y | 290 | CONFIG_PM_H1940=y |
| 228 | CONFIG_MACH_N30=y | 291 | CONFIG_MACH_N30=y |
| 229 | CONFIG_ARCH_BAST=y | 292 | CONFIG_ARCH_BAST=y |
| @@ -247,25 +310,26 @@ CONFIG_MACH_S3C2413=y | |||
| 247 | CONFIG_MACH_SMDK2412=y | 310 | CONFIG_MACH_SMDK2412=y |
| 248 | CONFIG_MACH_VSTMS=y | 311 | CONFIG_MACH_VSTMS=y |
| 249 | CONFIG_CPU_S3C2440=y | 312 | CONFIG_CPU_S3C2440=y |
| 313 | CONFIG_CPU_S3C2442=y | ||
| 314 | CONFIG_CPU_S3C244X=y | ||
| 315 | CONFIG_S3C2440_XTAL_12000000=y | ||
| 316 | CONFIG_S3C2440_XTAL_16934400=y | ||
| 250 | CONFIG_S3C2440_DMA=y | 317 | CONFIG_S3C2440_DMA=y |
| 251 | 318 | ||
| 252 | # | 319 | # |
| 253 | # S3C2440 Machines | 320 | # S3C2440 and S3C2442 Machines |
| 254 | # | 321 | # |
| 255 | CONFIG_MACH_ANUBIS=y | 322 | CONFIG_MACH_ANUBIS=y |
| 323 | # CONFIG_MACH_NEO1973_GTA02 is not set | ||
| 256 | CONFIG_MACH_OSIRIS=y | 324 | CONFIG_MACH_OSIRIS=y |
| 325 | # CONFIG_MACH_OSIRIS_DVS is not set | ||
| 257 | CONFIG_MACH_RX3715=y | 326 | CONFIG_MACH_RX3715=y |
| 258 | CONFIG_ARCH_S3C2440=y | 327 | CONFIG_ARCH_S3C2440=y |
| 259 | CONFIG_MACH_NEXCODER_2440=y | 328 | CONFIG_MACH_NEXCODER_2440=y |
| 260 | CONFIG_SMDK2440_CPU2440=y | 329 | CONFIG_SMDK2440_CPU2440=y |
| 330 | CONFIG_SMDK2440_CPU2442=y | ||
| 261 | CONFIG_MACH_AT2440EVB=y | 331 | CONFIG_MACH_AT2440EVB=y |
| 262 | CONFIG_CPU_S3C2442=y | ||
| 263 | CONFIG_MACH_MINI2440=y | 332 | CONFIG_MACH_MINI2440=y |
| 264 | |||
| 265 | # | ||
| 266 | # S3C2442 Machines | ||
| 267 | # | ||
| 268 | CONFIG_SMDK2440_CPU2442=y | ||
| 269 | CONFIG_CPU_S3C2443=y | 333 | CONFIG_CPU_S3C2443=y |
| 270 | CONFIG_S3C2443_DMA=y | 334 | CONFIG_S3C2443_DMA=y |
| 271 | 335 | ||
| @@ -283,7 +347,7 @@ CONFIG_CPU_32v4T=y | |||
| 283 | CONFIG_CPU_32v5=y | 347 | CONFIG_CPU_32v5=y |
| 284 | CONFIG_CPU_ABRT_EV4T=y | 348 | CONFIG_CPU_ABRT_EV4T=y |
| 285 | CONFIG_CPU_ABRT_EV5TJ=y | 349 | CONFIG_CPU_ABRT_EV5TJ=y |
| 286 | CONFIG_CPU_PABRT_NOIFAR=y | 350 | CONFIG_CPU_PABRT_LEGACY=y |
| 287 | CONFIG_CPU_CACHE_V4WT=y | 351 | CONFIG_CPU_CACHE_V4WT=y |
| 288 | CONFIG_CPU_CACHE_VIVT=y | 352 | CONFIG_CPU_CACHE_VIVT=y |
| 289 | CONFIG_CPU_COPY_V4WB=y | 353 | CONFIG_CPU_COPY_V4WB=y |
| @@ -299,7 +363,7 @@ CONFIG_CPU_CP15_MMU=y | |||
| 299 | # CONFIG_CPU_DCACHE_DISABLE is not set | 363 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 300 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | 364 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set |
| 301 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | 365 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set |
| 302 | # CONFIG_OUTER_CACHE is not set | 366 | CONFIG_ARM_L1_CACHE_SHIFT=5 |
| 303 | 367 | ||
| 304 | # | 368 | # |
| 305 | # Bus support | 369 | # Bus support |
| @@ -316,10 +380,11 @@ CONFIG_VMSPLIT_3G=y | |||
| 316 | # CONFIG_VMSPLIT_2G is not set | 380 | # CONFIG_VMSPLIT_2G is not set |
| 317 | # CONFIG_VMSPLIT_1G is not set | 381 | # CONFIG_VMSPLIT_1G is not set |
| 318 | CONFIG_PAGE_OFFSET=0xC0000000 | 382 | CONFIG_PAGE_OFFSET=0xC0000000 |
| 383 | CONFIG_PREEMPT_NONE=y | ||
| 384 | # CONFIG_PREEMPT_VOLUNTARY is not set | ||
| 319 | # CONFIG_PREEMPT is not set | 385 | # CONFIG_PREEMPT is not set |
| 320 | CONFIG_HZ=200 | 386 | CONFIG_HZ=200 |
| 321 | # CONFIG_AEABI is not set | 387 | # CONFIG_AEABI is not set |
| 322 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 323 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | 388 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set |
| 324 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | 389 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set |
| 325 | # CONFIG_HIGHMEM is not set | 390 | # CONFIG_HIGHMEM is not set |
| @@ -330,14 +395,14 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 330 | CONFIG_FLATMEM=y | 395 | CONFIG_FLATMEM=y |
| 331 | CONFIG_FLAT_NODE_MEM_MAP=y | 396 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 332 | CONFIG_PAGEFLAGS_EXTENDED=y | 397 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 333 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 398 | CONFIG_SPLIT_PTLOCK_CPUS=999999 |
| 334 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 399 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 335 | CONFIG_ZONE_DMA_FLAG=0 | 400 | CONFIG_ZONE_DMA_FLAG=0 |
| 336 | CONFIG_VIRT_TO_BUS=y | 401 | CONFIG_VIRT_TO_BUS=y |
| 337 | CONFIG_UNEVICTABLE_LRU=y | 402 | # CONFIG_KSM is not set |
| 338 | CONFIG_HAVE_MLOCK=y | 403 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 |
| 339 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 340 | CONFIG_ALIGNMENT_TRAP=y | 404 | CONFIG_ALIGNMENT_TRAP=y |
| 405 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 341 | 406 | ||
| 342 | # | 407 | # |
| 343 | # Boot options | 408 | # Boot options |
| @@ -351,6 +416,7 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" | |||
| 351 | # | 416 | # |
| 352 | # CPU Power Management | 417 | # CPU Power Management |
| 353 | # | 418 | # |
| 419 | # CONFIG_CPU_FREQ is not set | ||
| 354 | # CONFIG_CPU_IDLE is not set | 420 | # CONFIG_CPU_IDLE is not set |
| 355 | 421 | ||
| 356 | # | 422 | # |
| @@ -384,6 +450,8 @@ CONFIG_PM_SLEEP=y | |||
| 384 | CONFIG_SUSPEND=y | 450 | CONFIG_SUSPEND=y |
| 385 | CONFIG_SUSPEND_FREEZER=y | 451 | CONFIG_SUSPEND_FREEZER=y |
| 386 | CONFIG_APM_EMULATION=m | 452 | CONFIG_APM_EMULATION=m |
| 453 | # CONFIG_PM_RUNTIME is not set | ||
| 454 | CONFIG_PM_OPS=y | ||
| 387 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 455 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 388 | CONFIG_NET=y | 456 | CONFIG_NET=y |
| 389 | 457 | ||
| @@ -391,7 +459,6 @@ CONFIG_NET=y | |||
| 391 | # Networking options | 459 | # Networking options |
| 392 | # | 460 | # |
| 393 | CONFIG_PACKET=y | 461 | CONFIG_PACKET=y |
| 394 | # CONFIG_PACKET_MMAP is not set | ||
| 395 | CONFIG_UNIX=y | 462 | CONFIG_UNIX=y |
| 396 | CONFIG_XFRM=y | 463 | CONFIG_XFRM=y |
| 397 | CONFIG_XFRM_USER=m | 464 | CONFIG_XFRM_USER=m |
| @@ -463,6 +530,7 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m | |||
| 463 | CONFIG_INET6_XFRM_MODE_BEET=m | 530 | CONFIG_INET6_XFRM_MODE_BEET=m |
| 464 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m | 531 | CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m |
| 465 | CONFIG_IPV6_SIT=m | 532 | CONFIG_IPV6_SIT=m |
| 533 | # CONFIG_IPV6_SIT_6RD is not set | ||
| 466 | CONFIG_IPV6_NDISC_NODETYPE=y | 534 | CONFIG_IPV6_NDISC_NODETYPE=y |
| 467 | CONFIG_IPV6_TUNNEL=m | 535 | CONFIG_IPV6_TUNNEL=m |
| 468 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | 536 | # CONFIG_IPV6_MULTIPLE_TABLES is not set |
| @@ -500,6 +568,7 @@ CONFIG_NF_CT_NETLINK=m | |||
| 500 | CONFIG_NETFILTER_XTABLES=m | 568 | CONFIG_NETFILTER_XTABLES=m |
| 501 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m | 569 | CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m |
| 502 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m | 570 | CONFIG_NETFILTER_XT_TARGET_CONNMARK=m |
| 571 | # CONFIG_NETFILTER_XT_TARGET_CT is not set | ||
| 503 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set | 572 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set |
| 504 | CONFIG_NETFILTER_XT_TARGET_HL=m | 573 | CONFIG_NETFILTER_XT_TARGET_HL=m |
| 505 | CONFIG_NETFILTER_XT_TARGET_LED=m | 574 | CONFIG_NETFILTER_XT_TARGET_LED=m |
| @@ -544,6 +613,7 @@ CONFIG_NETFILTER_XT_MATCH_STRING=m | |||
| 544 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m | 613 | CONFIG_NETFILTER_XT_MATCH_TCPMSS=m |
| 545 | CONFIG_NETFILTER_XT_MATCH_TIME=m | 614 | CONFIG_NETFILTER_XT_MATCH_TIME=m |
| 546 | CONFIG_NETFILTER_XT_MATCH_U32=m | 615 | CONFIG_NETFILTER_XT_MATCH_U32=m |
| 616 | # CONFIG_NETFILTER_XT_MATCH_OSF is not set | ||
| 547 | CONFIG_IP_VS=m | 617 | CONFIG_IP_VS=m |
| 548 | # CONFIG_IP_VS_IPV6 is not set | 618 | # CONFIG_IP_VS_IPV6 is not set |
| 549 | # CONFIG_IP_VS_DEBUG is not set | 619 | # CONFIG_IP_VS_DEBUG is not set |
| @@ -556,6 +626,7 @@ CONFIG_IP_VS_TAB_BITS=12 | |||
| 556 | # CONFIG_IP_VS_PROTO_UDP is not set | 626 | # CONFIG_IP_VS_PROTO_UDP is not set |
| 557 | # CONFIG_IP_VS_PROTO_ESP is not set | 627 | # CONFIG_IP_VS_PROTO_ESP is not set |
| 558 | # CONFIG_IP_VS_PROTO_AH is not set | 628 | # CONFIG_IP_VS_PROTO_AH is not set |
| 629 | # CONFIG_IP_VS_PROTO_SCTP is not set | ||
| 559 | 630 | ||
| 560 | # | 631 | # |
| 561 | # IPVS scheduler | 632 | # IPVS scheduler |
| @@ -639,6 +710,7 @@ CONFIG_IP6_NF_MANGLE=m | |||
| 639 | CONFIG_IP6_NF_RAW=m | 710 | CONFIG_IP6_NF_RAW=m |
| 640 | # CONFIG_IP_DCCP is not set | 711 | # CONFIG_IP_DCCP is not set |
| 641 | # CONFIG_IP_SCTP is not set | 712 | # CONFIG_IP_SCTP is not set |
| 713 | # CONFIG_RDS is not set | ||
| 642 | # CONFIG_TIPC is not set | 714 | # CONFIG_TIPC is not set |
| 643 | # CONFIG_ATM is not set | 715 | # CONFIG_ATM is not set |
| 644 | # CONFIG_BRIDGE is not set | 716 | # CONFIG_BRIDGE is not set |
| @@ -653,6 +725,7 @@ CONFIG_IP6_NF_RAW=m | |||
| 653 | # CONFIG_ECONET is not set | 725 | # CONFIG_ECONET is not set |
| 654 | # CONFIG_WAN_ROUTER is not set | 726 | # CONFIG_WAN_ROUTER is not set |
| 655 | # CONFIG_PHONET is not set | 727 | # CONFIG_PHONET is not set |
| 728 | # CONFIG_IEEE802154 is not set | ||
| 656 | # CONFIG_NET_SCHED is not set | 729 | # CONFIG_NET_SCHED is not set |
| 657 | CONFIG_NET_CLS_ROUTE=y | 730 | CONFIG_NET_CLS_ROUTE=y |
| 658 | # CONFIG_DCB is not set | 731 | # CONFIG_DCB is not set |
| @@ -687,19 +760,21 @@ CONFIG_BT_HCIBCM203X=m | |||
| 687 | CONFIG_BT_HCIBPA10X=m | 760 | CONFIG_BT_HCIBPA10X=m |
| 688 | CONFIG_BT_HCIBFUSB=m | 761 | CONFIG_BT_HCIBFUSB=m |
| 689 | CONFIG_BT_HCIVHCI=m | 762 | CONFIG_BT_HCIVHCI=m |
| 763 | # CONFIG_BT_MRVL is not set | ||
| 690 | # CONFIG_AF_RXRPC is not set | 764 | # CONFIG_AF_RXRPC is not set |
| 691 | CONFIG_WIRELESS=y | 765 | CONFIG_WIRELESS=y |
| 766 | CONFIG_WEXT_CORE=y | ||
| 767 | CONFIG_WEXT_PROC=y | ||
| 692 | CONFIG_CFG80211=m | 768 | CONFIG_CFG80211=m |
| 769 | # CONFIG_NL80211_TESTMODE is not set | ||
| 770 | # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set | ||
| 693 | # CONFIG_CFG80211_REG_DEBUG is not set | 771 | # CONFIG_CFG80211_REG_DEBUG is not set |
| 694 | # CONFIG_WIRELESS_OLD_REGULATORY is not set | 772 | CONFIG_CFG80211_DEFAULT_PS=y |
| 695 | CONFIG_WIRELESS_EXT=y | 773 | # CONFIG_CFG80211_INTERNAL_REGDB is not set |
| 774 | CONFIG_CFG80211_WEXT=y | ||
| 696 | CONFIG_WIRELESS_EXT_SYSFS=y | 775 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 697 | # CONFIG_LIB80211 is not set | 776 | # CONFIG_LIB80211 is not set |
| 698 | CONFIG_MAC80211=m | 777 | CONFIG_MAC80211=m |
| 699 | |||
| 700 | # | ||
| 701 | # Rate control algorithm selection | ||
| 702 | # | ||
| 703 | CONFIG_MAC80211_RC_MINSTREL=y | 778 | CONFIG_MAC80211_RC_MINSTREL=y |
| 704 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | 779 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set |
| 705 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y | 780 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y |
| @@ -719,6 +794,7 @@ CONFIG_MAC80211_LEDS=y | |||
| 719 | # Generic Driver Options | 794 | # Generic Driver Options |
| 720 | # | 795 | # |
| 721 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 796 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 797 | # CONFIG_DEVTMPFS is not set | ||
| 722 | CONFIG_STANDALONE=y | 798 | CONFIG_STANDALONE=y |
| 723 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 799 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 724 | CONFIG_FW_LOADER=y | 800 | CONFIG_FW_LOADER=y |
| @@ -730,9 +806,9 @@ CONFIG_EXTRA_FIRMWARE="" | |||
| 730 | # CONFIG_CONNECTOR is not set | 806 | # CONFIG_CONNECTOR is not set |
| 731 | CONFIG_MTD=y | 807 | CONFIG_MTD=y |
| 732 | # CONFIG_MTD_DEBUG is not set | 808 | # CONFIG_MTD_DEBUG is not set |
| 809 | # CONFIG_MTD_TESTS is not set | ||
| 733 | # CONFIG_MTD_CONCAT is not set | 810 | # CONFIG_MTD_CONCAT is not set |
| 734 | CONFIG_MTD_PARTITIONS=y | 811 | CONFIG_MTD_PARTITIONS=y |
| 735 | # CONFIG_MTD_TESTS is not set | ||
| 736 | CONFIG_MTD_REDBOOT_PARTS=y | 812 | CONFIG_MTD_REDBOOT_PARTS=y |
| 737 | CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 | 813 | CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 |
| 738 | CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y | 814 | CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y |
| @@ -793,6 +869,7 @@ CONFIG_MTD_ROM=y | |||
| 793 | # | 869 | # |
| 794 | # CONFIG_MTD_DATAFLASH is not set | 870 | # CONFIG_MTD_DATAFLASH is not set |
| 795 | # CONFIG_MTD_M25P80 is not set | 871 | # CONFIG_MTD_M25P80 is not set |
| 872 | # CONFIG_MTD_SST25L is not set | ||
| 796 | # CONFIG_MTD_SLRAM is not set | 873 | # CONFIG_MTD_SLRAM is not set |
| 797 | # CONFIG_MTD_PHRAM is not set | 874 | # CONFIG_MTD_PHRAM is not set |
| 798 | # CONFIG_MTD_MTDRAM is not set | 875 | # CONFIG_MTD_MTDRAM is not set |
| @@ -843,6 +920,10 @@ CONFIG_BLK_DEV=y | |||
| 843 | # CONFIG_BLK_DEV_COW_COMMON is not set | 920 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 844 | CONFIG_BLK_DEV_LOOP=y | 921 | CONFIG_BLK_DEV_LOOP=y |
| 845 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | 922 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set |
| 923 | |||
| 924 | # | ||
| 925 | # DRBD disabled because PROC_FS, INET or CONNECTOR not selected | ||
| 926 | # | ||
| 846 | CONFIG_BLK_DEV_NBD=m | 927 | CONFIG_BLK_DEV_NBD=m |
| 847 | CONFIG_BLK_DEV_UB=m | 928 | CONFIG_BLK_DEV_UB=m |
| 848 | CONFIG_BLK_DEV_RAM=y | 929 | CONFIG_BLK_DEV_RAM=y |
| @@ -851,19 +932,26 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 | |||
| 851 | # CONFIG_BLK_DEV_XIP is not set | 932 | # CONFIG_BLK_DEV_XIP is not set |
| 852 | # CONFIG_CDROM_PKTCDVD is not set | 933 | # CONFIG_CDROM_PKTCDVD is not set |
| 853 | CONFIG_ATA_OVER_ETH=m | 934 | CONFIG_ATA_OVER_ETH=m |
| 935 | # CONFIG_MG_DISK is not set | ||
| 854 | CONFIG_MISC_DEVICES=y | 936 | CONFIG_MISC_DEVICES=y |
| 937 | # CONFIG_AD525X_DPOT is not set | ||
| 855 | # CONFIG_ICS932S401 is not set | 938 | # CONFIG_ICS932S401 is not set |
| 856 | # CONFIG_ENCLOSURE_SERVICES is not set | 939 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 857 | # CONFIG_ISL29003 is not set | 940 | # CONFIG_ISL29003 is not set |
| 941 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 942 | # CONFIG_DS1682 is not set | ||
| 943 | # CONFIG_TI_DAC7512 is not set | ||
| 858 | # CONFIG_C2PORT is not set | 944 | # CONFIG_C2PORT is not set |
| 859 | 945 | ||
| 860 | # | 946 | # |
| 861 | # EEPROM support | 947 | # EEPROM support |
| 862 | # | 948 | # |
| 863 | CONFIG_EEPROM_AT24=m | 949 | CONFIG_EEPROM_AT24=y |
| 864 | CONFIG_EEPROM_AT25=m | 950 | CONFIG_EEPROM_AT25=m |
| 865 | CONFIG_EEPROM_LEGACY=m | 951 | CONFIG_EEPROM_LEGACY=m |
| 952 | # CONFIG_EEPROM_MAX6875 is not set | ||
| 866 | CONFIG_EEPROM_93CX6=m | 953 | CONFIG_EEPROM_93CX6=m |
| 954 | # CONFIG_IWMC3200TOP is not set | ||
| 867 | CONFIG_HAVE_IDE=y | 955 | CONFIG_HAVE_IDE=y |
| 868 | CONFIG_IDE=y | 956 | CONFIG_IDE=y |
| 869 | 957 | ||
| @@ -890,6 +978,7 @@ CONFIG_BLK_DEV_PLATFORM=y | |||
| 890 | # | 978 | # |
| 891 | # SCSI device support | 979 | # SCSI device support |
| 892 | # | 980 | # |
| 981 | CONFIG_SCSI_MOD=y | ||
| 893 | # CONFIG_RAID_ATTRS is not set | 982 | # CONFIG_RAID_ATTRS is not set |
| 894 | CONFIG_SCSI=y | 983 | CONFIG_SCSI=y |
| 895 | CONFIG_SCSI_DMA=y | 984 | CONFIG_SCSI_DMA=y |
| @@ -907,10 +996,6 @@ CONFIG_BLK_DEV_SR=m | |||
| 907 | CONFIG_BLK_DEV_SR_VENDOR=y | 996 | CONFIG_BLK_DEV_SR_VENDOR=y |
| 908 | CONFIG_CHR_DEV_SG=y | 997 | CONFIG_CHR_DEV_SG=y |
| 909 | CONFIG_CHR_DEV_SCH=m | 998 | CONFIG_CHR_DEV_SCH=m |
| 910 | |||
| 911 | # | ||
| 912 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 913 | # | ||
| 914 | CONFIG_SCSI_MULTI_LUN=y | 999 | CONFIG_SCSI_MULTI_LUN=y |
| 915 | CONFIG_SCSI_CONSTANTS=y | 1000 | CONFIG_SCSI_CONSTANTS=y |
| 916 | # CONFIG_SCSI_LOGGING is not set | 1001 | # CONFIG_SCSI_LOGGING is not set |
| @@ -951,7 +1036,6 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 951 | CONFIG_HAVE_PATA_PLATFORM=y | 1036 | CONFIG_HAVE_PATA_PLATFORM=y |
| 952 | # CONFIG_MD is not set | 1037 | # CONFIG_MD is not set |
| 953 | CONFIG_NETDEVICES=y | 1038 | CONFIG_NETDEVICES=y |
| 954 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 955 | # CONFIG_DUMMY is not set | 1039 | # CONFIG_DUMMY is not set |
| 956 | # CONFIG_BONDING is not set | 1040 | # CONFIG_BONDING is not set |
| 957 | # CONFIG_MACVLAN is not set | 1041 | # CONFIG_MACVLAN is not set |
| @@ -989,16 +1073,30 @@ CONFIG_DM9000_DEBUGLEVEL=4 | |||
| 989 | # CONFIG_NET_PCI is not set | 1073 | # CONFIG_NET_PCI is not set |
| 990 | # CONFIG_B44 is not set | 1074 | # CONFIG_B44 is not set |
| 991 | # CONFIG_CS89x0 is not set | 1075 | # CONFIG_CS89x0 is not set |
| 1076 | # CONFIG_KS8842 is not set | ||
| 1077 | # CONFIG_KS8851 is not set | ||
| 1078 | # CONFIG_KS8851_MLL is not set | ||
| 992 | # CONFIG_NET_POCKET is not set | 1079 | # CONFIG_NET_POCKET is not set |
| 993 | CONFIG_NETDEV_1000=y | 1080 | CONFIG_NETDEV_1000=y |
| 994 | CONFIG_NETDEV_10000=y | 1081 | CONFIG_NETDEV_10000=y |
| 995 | # CONFIG_TR is not set | 1082 | # CONFIG_TR is not set |
| 996 | 1083 | CONFIG_WLAN=y | |
| 997 | # | 1084 | # CONFIG_LIBERTAS_THINFIRM is not set |
| 998 | # Wireless LAN | 1085 | # CONFIG_AT76C50X_USB is not set |
| 999 | # | 1086 | # CONFIG_USB_ZD1201 is not set |
| 1000 | # CONFIG_WLAN_PRE80211 is not set | 1087 | # CONFIG_USB_NET_RNDIS_WLAN is not set |
| 1001 | # CONFIG_WLAN_80211 is not set | 1088 | # CONFIG_RTL8187 is not set |
| 1089 | # CONFIG_MAC80211_HWSIM is not set | ||
| 1090 | # CONFIG_ATH_COMMON is not set | ||
| 1091 | # CONFIG_B43 is not set | ||
| 1092 | # CONFIG_B43LEGACY is not set | ||
| 1093 | # CONFIG_HOSTAP is not set | ||
| 1094 | # CONFIG_IWM is not set | ||
| 1095 | # CONFIG_LIBERTAS is not set | ||
| 1096 | # CONFIG_P54_COMMON is not set | ||
| 1097 | # CONFIG_RT2X00 is not set | ||
| 1098 | # CONFIG_WL12XX is not set | ||
| 1099 | # CONFIG_ZD1211RW is not set | ||
| 1002 | 1100 | ||
| 1003 | # | 1101 | # |
| 1004 | # Enable WiMAX (Networking options) to see the WiMAX drivers | 1102 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| @@ -1012,6 +1110,7 @@ CONFIG_NETDEV_10000=y | |||
| 1012 | # CONFIG_USB_PEGASUS is not set | 1110 | # CONFIG_USB_PEGASUS is not set |
| 1013 | # CONFIG_USB_RTL8150 is not set | 1111 | # CONFIG_USB_RTL8150 is not set |
| 1014 | # CONFIG_USB_USBNET is not set | 1112 | # CONFIG_USB_USBNET is not set |
| 1113 | # CONFIG_USB_IPHETH is not set | ||
| 1015 | # CONFIG_WAN is not set | 1114 | # CONFIG_WAN is not set |
| 1016 | # CONFIG_PLIP is not set | 1115 | # CONFIG_PLIP is not set |
| 1017 | # CONFIG_PPP is not set | 1116 | # CONFIG_PPP is not set |
| @@ -1020,6 +1119,7 @@ CONFIG_NETDEV_10000=y | |||
| 1020 | # CONFIG_NETPOLL is not set | 1119 | # CONFIG_NETPOLL is not set |
| 1021 | # CONFIG_NET_POLL_CONTROLLER is not set | 1120 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 1022 | # CONFIG_ISDN is not set | 1121 | # CONFIG_ISDN is not set |
| 1122 | # CONFIG_PHONE is not set | ||
| 1023 | 1123 | ||
| 1024 | # | 1124 | # |
| 1025 | # Input device support | 1125 | # Input device support |
| @@ -1027,6 +1127,7 @@ CONFIG_NETDEV_10000=y | |||
| 1027 | CONFIG_INPUT=y | 1127 | CONFIG_INPUT=y |
| 1028 | CONFIG_INPUT_FF_MEMLESS=m | 1128 | CONFIG_INPUT_FF_MEMLESS=m |
| 1029 | # CONFIG_INPUT_POLLDEV is not set | 1129 | # CONFIG_INPUT_POLLDEV is not set |
| 1130 | # CONFIG_INPUT_SPARSEKMAP is not set | ||
| 1030 | 1131 | ||
| 1031 | # | 1132 | # |
| 1032 | # Userland interfaces | 1133 | # Userland interfaces |
| @@ -1043,13 +1144,19 @@ CONFIG_INPUT_EVDEV=y | |||
| 1043 | # Input Device Drivers | 1144 | # Input Device Drivers |
| 1044 | # | 1145 | # |
| 1045 | CONFIG_INPUT_KEYBOARD=y | 1146 | CONFIG_INPUT_KEYBOARD=y |
| 1147 | # CONFIG_KEYBOARD_ADP5588 is not set | ||
| 1046 | CONFIG_KEYBOARD_ATKBD=y | 1148 | CONFIG_KEYBOARD_ATKBD=y |
| 1047 | # CONFIG_KEYBOARD_SUNKBD is not set | 1149 | # CONFIG_QT2160 is not set |
| 1048 | # CONFIG_KEYBOARD_LKKBD is not set | 1150 | # CONFIG_KEYBOARD_LKKBD is not set |
| 1049 | # CONFIG_KEYBOARD_XTKBD is not set | 1151 | # CONFIG_KEYBOARD_GPIO is not set |
| 1152 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 1153 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 1154 | # CONFIG_KEYBOARD_MAX7359 is not set | ||
| 1050 | # CONFIG_KEYBOARD_NEWTON is not set | 1155 | # CONFIG_KEYBOARD_NEWTON is not set |
| 1156 | # CONFIG_KEYBOARD_OPENCORES is not set | ||
| 1051 | # CONFIG_KEYBOARD_STOWAWAY is not set | 1157 | # CONFIG_KEYBOARD_STOWAWAY is not set |
| 1052 | # CONFIG_KEYBOARD_GPIO is not set | 1158 | # CONFIG_KEYBOARD_SUNKBD is not set |
| 1159 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 1053 | CONFIG_INPUT_MOUSE=y | 1160 | CONFIG_INPUT_MOUSE=y |
| 1054 | CONFIG_MOUSE_PS2=y | 1161 | CONFIG_MOUSE_PS2=y |
| 1055 | CONFIG_MOUSE_PS2_ALPS=y | 1162 | CONFIG_MOUSE_PS2_ALPS=y |
| @@ -1057,6 +1164,7 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y | |||
| 1057 | CONFIG_MOUSE_PS2_SYNAPTICS=y | 1164 | CONFIG_MOUSE_PS2_SYNAPTICS=y |
| 1058 | CONFIG_MOUSE_PS2_TRACKPOINT=y | 1165 | CONFIG_MOUSE_PS2_TRACKPOINT=y |
| 1059 | # CONFIG_MOUSE_PS2_ELANTECH is not set | 1166 | # CONFIG_MOUSE_PS2_ELANTECH is not set |
| 1167 | # CONFIG_MOUSE_PS2_SENTELIC is not set | ||
| 1060 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | 1168 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set |
| 1061 | # CONFIG_MOUSE_SERIAL is not set | 1169 | # CONFIG_MOUSE_SERIAL is not set |
| 1062 | CONFIG_MOUSE_APPLETOUCH=m | 1170 | CONFIG_MOUSE_APPLETOUCH=m |
| @@ -1066,6 +1174,7 @@ CONFIG_MOUSE_BCM5974=m | |||
| 1066 | # CONFIG_MOUSE_PC110PAD is not set | 1174 | # CONFIG_MOUSE_PC110PAD is not set |
| 1067 | # CONFIG_MOUSE_VSXXXAA is not set | 1175 | # CONFIG_MOUSE_VSXXXAA is not set |
| 1068 | # CONFIG_MOUSE_GPIO is not set | 1176 | # CONFIG_MOUSE_GPIO is not set |
| 1177 | # CONFIG_MOUSE_SYNAPTICS_I2C is not set | ||
| 1069 | CONFIG_INPUT_JOYSTICK=y | 1178 | CONFIG_INPUT_JOYSTICK=y |
| 1070 | CONFIG_JOYSTICK_ANALOG=m | 1179 | CONFIG_JOYSTICK_ANALOG=m |
| 1071 | CONFIG_JOYSTICK_A3D=m | 1180 | CONFIG_JOYSTICK_A3D=m |
| @@ -1102,10 +1211,14 @@ CONFIG_INPUT_TOUCHSCREEN=y | |||
| 1102 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set | 1211 | # CONFIG_TOUCHSCREEN_AD7879_I2C is not set |
| 1103 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set | 1212 | # CONFIG_TOUCHSCREEN_AD7879_SPI is not set |
| 1104 | # CONFIG_TOUCHSCREEN_AD7879 is not set | 1213 | # CONFIG_TOUCHSCREEN_AD7879 is not set |
| 1214 | # CONFIG_TOUCHSCREEN_DYNAPRO is not set | ||
| 1215 | # CONFIG_TOUCHSCREEN_EETI is not set | ||
| 1105 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 1216 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 1217 | # CONFIG_TOUCHSCREEN_S3C2410 is not set | ||
| 1106 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 1218 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 1107 | # CONFIG_TOUCHSCREEN_ELO is not set | 1219 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 1108 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | 1220 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set |
| 1221 | # CONFIG_TOUCHSCREEN_MCS5000 is not set | ||
| 1109 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 1222 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 1110 | # CONFIG_TOUCHSCREEN_INEXIO is not set | 1223 | # CONFIG_TOUCHSCREEN_INEXIO is not set |
| 1111 | # CONFIG_TOUCHSCREEN_MK712 is not set | 1224 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| @@ -1126,8 +1239,14 @@ CONFIG_TOUCHSCREEN_USB_IRTOUCH=y | |||
| 1126 | CONFIG_TOUCHSCREEN_USB_IDEALTEK=y | 1239 | CONFIG_TOUCHSCREEN_USB_IDEALTEK=y |
| 1127 | CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y | 1240 | CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y |
| 1128 | CONFIG_TOUCHSCREEN_USB_GOTOP=y | 1241 | CONFIG_TOUCHSCREEN_USB_GOTOP=y |
| 1242 | CONFIG_TOUCHSCREEN_USB_JASTEC=y | ||
| 1243 | CONFIG_TOUCHSCREEN_USB_E2I=y | ||
| 1244 | CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y | ||
| 1245 | CONFIG_TOUCHSCREEN_USB_ETT_TC5UH=y | ||
| 1246 | CONFIG_TOUCHSCREEN_USB_NEXIO=y | ||
| 1129 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | 1247 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set |
| 1130 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | 1248 | # CONFIG_TOUCHSCREEN_TSC2007 is not set |
| 1249 | # CONFIG_TOUCHSCREEN_W90X900 is not set | ||
| 1131 | CONFIG_INPUT_MISC=y | 1250 | CONFIG_INPUT_MISC=y |
| 1132 | CONFIG_INPUT_ATI_REMOTE=m | 1251 | CONFIG_INPUT_ATI_REMOTE=m |
| 1133 | CONFIG_INPUT_ATI_REMOTE2=m | 1252 | CONFIG_INPUT_ATI_REMOTE2=m |
| @@ -1146,6 +1265,7 @@ CONFIG_SERIO_SERPORT=y | |||
| 1146 | # CONFIG_SERIO_PARKBD is not set | 1265 | # CONFIG_SERIO_PARKBD is not set |
| 1147 | CONFIG_SERIO_LIBPS2=y | 1266 | CONFIG_SERIO_LIBPS2=y |
| 1148 | # CONFIG_SERIO_RAW is not set | 1267 | # CONFIG_SERIO_RAW is not set |
| 1268 | # CONFIG_SERIO_ALTERA_PS2 is not set | ||
| 1149 | CONFIG_GAMEPORT=m | 1269 | CONFIG_GAMEPORT=m |
| 1150 | # CONFIG_GAMEPORT_NS558 is not set | 1270 | # CONFIG_GAMEPORT_NS558 is not set |
| 1151 | # CONFIG_GAMEPORT_L4 is not set | 1271 | # CONFIG_GAMEPORT_L4 is not set |
| @@ -1169,8 +1289,6 @@ CONFIG_SERIAL_NONSTANDARD=y | |||
| 1169 | # CONFIG_N_HDLC is not set | 1289 | # CONFIG_N_HDLC is not set |
| 1170 | # CONFIG_RISCOM8 is not set | 1290 | # CONFIG_RISCOM8 is not set |
| 1171 | # CONFIG_SPECIALIX is not set | 1291 | # CONFIG_SPECIALIX is not set |
| 1172 | # CONFIG_SX is not set | ||
| 1173 | # CONFIG_RIO is not set | ||
| 1174 | # CONFIG_STALDRV is not set | 1292 | # CONFIG_STALDRV is not set |
| 1175 | 1293 | ||
| 1176 | # | 1294 | # |
| @@ -1195,6 +1313,7 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y | |||
| 1195 | # Non-8250 serial port support | 1313 | # Non-8250 serial port support |
| 1196 | # | 1314 | # |
| 1197 | CONFIG_SERIAL_SAMSUNG=y | 1315 | CONFIG_SERIAL_SAMSUNG=y |
| 1316 | CONFIG_SERIAL_SAMSUNG_UARTS_4=y | ||
| 1198 | CONFIG_SERIAL_SAMSUNG_UARTS=4 | 1317 | CONFIG_SERIAL_SAMSUNG_UARTS=4 |
| 1199 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set | 1318 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set |
| 1200 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | 1319 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y |
| @@ -1204,6 +1323,7 @@ CONFIG_SERIAL_S3C2440=y | |||
| 1204 | # CONFIG_SERIAL_MAX3100 is not set | 1323 | # CONFIG_SERIAL_MAX3100 is not set |
| 1205 | CONFIG_SERIAL_CORE=y | 1324 | CONFIG_SERIAL_CORE=y |
| 1206 | CONFIG_SERIAL_CORE_CONSOLE=y | 1325 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 1326 | # CONFIG_SERIAL_TIMBERDALE is not set | ||
| 1207 | CONFIG_UNIX98_PTYS=y | 1327 | CONFIG_UNIX98_PTYS=y |
| 1208 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 1328 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
| 1209 | CONFIG_LEGACY_PTYS=y | 1329 | CONFIG_LEGACY_PTYS=y |
| @@ -1221,6 +1341,7 @@ CONFIG_HW_RANDOM=y | |||
| 1221 | CONFIG_DEVPORT=y | 1341 | CONFIG_DEVPORT=y |
| 1222 | CONFIG_I2C=y | 1342 | CONFIG_I2C=y |
| 1223 | CONFIG_I2C_BOARDINFO=y | 1343 | CONFIG_I2C_BOARDINFO=y |
| 1344 | CONFIG_I2C_COMPAT=y | ||
| 1224 | CONFIG_I2C_CHARDEV=m | 1345 | CONFIG_I2C_CHARDEV=m |
| 1225 | CONFIG_I2C_HELPER_AUTO=y | 1346 | CONFIG_I2C_HELPER_AUTO=y |
| 1226 | CONFIG_I2C_ALGOBIT=y | 1347 | CONFIG_I2C_ALGOBIT=y |
| @@ -1232,10 +1353,12 @@ CONFIG_I2C_ALGOBIT=y | |||
| 1232 | # | 1353 | # |
| 1233 | # I2C system bus drivers (mostly embedded / system-on-chip) | 1354 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 1234 | # | 1355 | # |
| 1356 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 1235 | # CONFIG_I2C_GPIO is not set | 1357 | # CONFIG_I2C_GPIO is not set |
| 1236 | # CONFIG_I2C_OCORES is not set | 1358 | # CONFIG_I2C_OCORES is not set |
| 1237 | CONFIG_I2C_S3C2410=y | 1359 | CONFIG_I2C_S3C2410=y |
| 1238 | CONFIG_I2C_SIMTEC=y | 1360 | CONFIG_I2C_SIMTEC=y |
| 1361 | # CONFIG_I2C_XILINX is not set | ||
| 1239 | 1362 | ||
| 1240 | # | 1363 | # |
| 1241 | # External I2C/SMBus adapter drivers | 1364 | # External I2C/SMBus adapter drivers |
| @@ -1252,20 +1375,9 @@ CONFIG_I2C_SIMTEC=y | |||
| 1252 | # CONFIG_I2C_PCA_ISA is not set | 1375 | # CONFIG_I2C_PCA_ISA is not set |
| 1253 | # CONFIG_I2C_PCA_PLATFORM is not set | 1376 | # CONFIG_I2C_PCA_PLATFORM is not set |
| 1254 | # CONFIG_I2C_STUB is not set | 1377 | # CONFIG_I2C_STUB is not set |
| 1255 | |||
| 1256 | # | ||
| 1257 | # Miscellaneous I2C Chip support | ||
| 1258 | # | ||
| 1259 | # CONFIG_DS1682 is not set | ||
| 1260 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 1261 | # CONFIG_PCF8575 is not set | ||
| 1262 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 1263 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 1264 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 1265 | # CONFIG_I2C_DEBUG_CORE is not set | 1378 | # CONFIG_I2C_DEBUG_CORE is not set |
| 1266 | # CONFIG_I2C_DEBUG_ALGO is not set | 1379 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 1267 | # CONFIG_I2C_DEBUG_BUS is not set | 1380 | # CONFIG_I2C_DEBUG_BUS is not set |
| 1268 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 1269 | CONFIG_SPI=y | 1381 | CONFIG_SPI=y |
| 1270 | # CONFIG_SPI_DEBUG is not set | 1382 | # CONFIG_SPI_DEBUG is not set |
| 1271 | CONFIG_SPI_MASTER=y | 1383 | CONFIG_SPI_MASTER=y |
| @@ -1278,13 +1390,21 @@ CONFIG_SPI_BITBANG=m | |||
| 1278 | CONFIG_SPI_GPIO=m | 1390 | CONFIG_SPI_GPIO=m |
| 1279 | # CONFIG_SPI_LM70_LLP is not set | 1391 | # CONFIG_SPI_LM70_LLP is not set |
| 1280 | CONFIG_SPI_S3C24XX=m | 1392 | CONFIG_SPI_S3C24XX=m |
| 1393 | # CONFIG_SPI_S3C24XX_FIQ is not set | ||
| 1281 | CONFIG_SPI_S3C24XX_GPIO=m | 1394 | CONFIG_SPI_S3C24XX_GPIO=m |
| 1395 | # CONFIG_SPI_XILINX is not set | ||
| 1396 | # CONFIG_SPI_DESIGNWARE is not set | ||
| 1282 | 1397 | ||
| 1283 | # | 1398 | # |
| 1284 | # SPI Protocol Masters | 1399 | # SPI Protocol Masters |
| 1285 | # | 1400 | # |
| 1286 | CONFIG_SPI_SPIDEV=m | 1401 | CONFIG_SPI_SPIDEV=m |
| 1287 | CONFIG_SPI_TLE62X0=m | 1402 | CONFIG_SPI_TLE62X0=m |
| 1403 | |||
| 1404 | # | ||
| 1405 | # PPS support | ||
| 1406 | # | ||
| 1407 | # CONFIG_PPS is not set | ||
| 1288 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 1408 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 1289 | CONFIG_GPIOLIB=y | 1409 | CONFIG_GPIOLIB=y |
| 1290 | # CONFIG_DEBUG_GPIO is not set | 1410 | # CONFIG_DEBUG_GPIO is not set |
| @@ -1293,13 +1413,16 @@ CONFIG_GPIOLIB=y | |||
| 1293 | # | 1413 | # |
| 1294 | # Memory mapped GPIO expanders: | 1414 | # Memory mapped GPIO expanders: |
| 1295 | # | 1415 | # |
| 1416 | # CONFIG_GPIO_IT8761E is not set | ||
| 1296 | 1417 | ||
| 1297 | # | 1418 | # |
| 1298 | # I2C GPIO expanders: | 1419 | # I2C GPIO expanders: |
| 1299 | # | 1420 | # |
| 1421 | # CONFIG_GPIO_MAX7300 is not set | ||
| 1300 | # CONFIG_GPIO_MAX732X is not set | 1422 | # CONFIG_GPIO_MAX732X is not set |
| 1301 | # CONFIG_GPIO_PCA953X is not set | 1423 | # CONFIG_GPIO_PCA953X is not set |
| 1302 | # CONFIG_GPIO_PCF857X is not set | 1424 | # CONFIG_GPIO_PCF857X is not set |
| 1425 | # CONFIG_GPIO_ADP5588 is not set | ||
| 1303 | 1426 | ||
| 1304 | # | 1427 | # |
| 1305 | # PCI GPIO expanders: | 1428 | # PCI GPIO expanders: |
| @@ -1310,10 +1433,20 @@ CONFIG_GPIOLIB=y | |||
| 1310 | # | 1433 | # |
| 1311 | # CONFIG_GPIO_MAX7301 is not set | 1434 | # CONFIG_GPIO_MAX7301 is not set |
| 1312 | # CONFIG_GPIO_MCP23S08 is not set | 1435 | # CONFIG_GPIO_MCP23S08 is not set |
| 1436 | # CONFIG_GPIO_MC33880 is not set | ||
| 1437 | |||
| 1438 | # | ||
| 1439 | # AC97 GPIO expanders: | ||
| 1440 | # | ||
| 1313 | # CONFIG_W1 is not set | 1441 | # CONFIG_W1 is not set |
| 1314 | # CONFIG_POWER_SUPPLY is not set | 1442 | # CONFIG_POWER_SUPPLY is not set |
| 1315 | CONFIG_HWMON=y | 1443 | CONFIG_HWMON=y |
| 1316 | CONFIG_HWMON_VID=m | 1444 | CONFIG_HWMON_VID=m |
| 1445 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 1446 | |||
| 1447 | # | ||
| 1448 | # Native drivers | ||
| 1449 | # | ||
| 1317 | # CONFIG_SENSORS_AD7414 is not set | 1450 | # CONFIG_SENSORS_AD7414 is not set |
| 1318 | # CONFIG_SENSORS_AD7418 is not set | 1451 | # CONFIG_SENSORS_AD7418 is not set |
| 1319 | # CONFIG_SENSORS_ADCXX is not set | 1452 | # CONFIG_SENSORS_ADCXX is not set |
| @@ -1323,10 +1456,11 @@ CONFIG_HWMON_VID=m | |||
| 1323 | # CONFIG_SENSORS_ADM1029 is not set | 1456 | # CONFIG_SENSORS_ADM1029 is not set |
| 1324 | # CONFIG_SENSORS_ADM1031 is not set | 1457 | # CONFIG_SENSORS_ADM1031 is not set |
| 1325 | # CONFIG_SENSORS_ADM9240 is not set | 1458 | # CONFIG_SENSORS_ADM9240 is not set |
| 1459 | # CONFIG_SENSORS_ADT7411 is not set | ||
| 1326 | # CONFIG_SENSORS_ADT7462 is not set | 1460 | # CONFIG_SENSORS_ADT7462 is not set |
| 1327 | # CONFIG_SENSORS_ADT7470 is not set | 1461 | # CONFIG_SENSORS_ADT7470 is not set |
| 1328 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 1329 | # CONFIG_SENSORS_ADT7475 is not set | 1462 | # CONFIG_SENSORS_ADT7475 is not set |
| 1463 | # CONFIG_SENSORS_ASC7621 is not set | ||
| 1330 | # CONFIG_SENSORS_ATXP1 is not set | 1464 | # CONFIG_SENSORS_ATXP1 is not set |
| 1331 | # CONFIG_SENSORS_DS1621 is not set | 1465 | # CONFIG_SENSORS_DS1621 is not set |
| 1332 | # CONFIG_SENSORS_F71805F is not set | 1466 | # CONFIG_SENSORS_F71805F is not set |
| @@ -1338,6 +1472,7 @@ CONFIG_HWMON_VID=m | |||
| 1338 | # CONFIG_SENSORS_IT87 is not set | 1472 | # CONFIG_SENSORS_IT87 is not set |
| 1339 | # CONFIG_SENSORS_LM63 is not set | 1473 | # CONFIG_SENSORS_LM63 is not set |
| 1340 | # CONFIG_SENSORS_LM70 is not set | 1474 | # CONFIG_SENSORS_LM70 is not set |
| 1475 | # CONFIG_SENSORS_LM73 is not set | ||
| 1341 | CONFIG_SENSORS_LM75=m | 1476 | CONFIG_SENSORS_LM75=m |
| 1342 | # CONFIG_SENSORS_LM77 is not set | 1477 | # CONFIG_SENSORS_LM77 is not set |
| 1343 | CONFIG_SENSORS_LM78=m | 1478 | CONFIG_SENSORS_LM78=m |
| @@ -1358,12 +1493,16 @@ CONFIG_SENSORS_LM85=m | |||
| 1358 | # CONFIG_SENSORS_PC87427 is not set | 1493 | # CONFIG_SENSORS_PC87427 is not set |
| 1359 | # CONFIG_SENSORS_PCF8591 is not set | 1494 | # CONFIG_SENSORS_PCF8591 is not set |
| 1360 | # CONFIG_SENSORS_SHT15 is not set | 1495 | # CONFIG_SENSORS_SHT15 is not set |
| 1496 | # CONFIG_SENSORS_S3C is not set | ||
| 1361 | # CONFIG_SENSORS_DME1737 is not set | 1497 | # CONFIG_SENSORS_DME1737 is not set |
| 1362 | # CONFIG_SENSORS_SMSC47M1 is not set | 1498 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 1363 | # CONFIG_SENSORS_SMSC47M192 is not set | 1499 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 1364 | # CONFIG_SENSORS_SMSC47B397 is not set | 1500 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 1365 | # CONFIG_SENSORS_ADS7828 is not set | 1501 | # CONFIG_SENSORS_ADS7828 is not set |
| 1502 | # CONFIG_SENSORS_AMC6821 is not set | ||
| 1366 | # CONFIG_SENSORS_THMC50 is not set | 1503 | # CONFIG_SENSORS_THMC50 is not set |
| 1504 | # CONFIG_SENSORS_TMP401 is not set | ||
| 1505 | # CONFIG_SENSORS_TMP421 is not set | ||
| 1367 | # CONFIG_SENSORS_VT1211 is not set | 1506 | # CONFIG_SENSORS_VT1211 is not set |
| 1368 | # CONFIG_SENSORS_W83781D is not set | 1507 | # CONFIG_SENSORS_W83781D is not set |
| 1369 | # CONFIG_SENSORS_W83791D is not set | 1508 | # CONFIG_SENSORS_W83791D is not set |
| @@ -1374,9 +1513,8 @@ CONFIG_SENSORS_LM85=m | |||
| 1374 | # CONFIG_SENSORS_W83627HF is not set | 1513 | # CONFIG_SENSORS_W83627HF is not set |
| 1375 | # CONFIG_SENSORS_W83627EHF is not set | 1514 | # CONFIG_SENSORS_W83627EHF is not set |
| 1376 | # CONFIG_SENSORS_LIS3_SPI is not set | 1515 | # CONFIG_SENSORS_LIS3_SPI is not set |
| 1377 | # CONFIG_HWMON_DEBUG_CHIP is not set | 1516 | # CONFIG_SENSORS_LIS3_I2C is not set |
| 1378 | # CONFIG_THERMAL is not set | 1517 | # CONFIG_THERMAL is not set |
| 1379 | # CONFIG_THERMAL_HWMON is not set | ||
| 1380 | CONFIG_WATCHDOG=y | 1518 | CONFIG_WATCHDOG=y |
| 1381 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 1519 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 1382 | 1520 | ||
| @@ -1385,6 +1523,7 @@ CONFIG_WATCHDOG=y | |||
| 1385 | # | 1523 | # |
| 1386 | # CONFIG_SOFT_WATCHDOG is not set | 1524 | # CONFIG_SOFT_WATCHDOG is not set |
| 1387 | CONFIG_S3C2410_WATCHDOG=y | 1525 | CONFIG_S3C2410_WATCHDOG=y |
| 1526 | # CONFIG_MAX63XX_WATCHDOG is not set | ||
| 1388 | 1527 | ||
| 1389 | # | 1528 | # |
| 1390 | # ISA-based Watchdog Cards | 1529 | # ISA-based Watchdog Cards |
| @@ -1408,11 +1547,13 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1408 | # Multifunction device drivers | 1547 | # Multifunction device drivers |
| 1409 | # | 1548 | # |
| 1410 | # CONFIG_MFD_CORE is not set | 1549 | # CONFIG_MFD_CORE is not set |
| 1550 | # CONFIG_MFD_88PM860X is not set | ||
| 1411 | CONFIG_MFD_SM501=y | 1551 | CONFIG_MFD_SM501=y |
| 1412 | # CONFIG_MFD_SM501_GPIO is not set | 1552 | # CONFIG_MFD_SM501_GPIO is not set |
| 1413 | # CONFIG_MFD_ASIC3 is not set | 1553 | # CONFIG_MFD_ASIC3 is not set |
| 1414 | # CONFIG_HTC_EGPIO is not set | 1554 | # CONFIG_HTC_EGPIO is not set |
| 1415 | # CONFIG_HTC_PASIC3 is not set | 1555 | # CONFIG_HTC_PASIC3 is not set |
| 1556 | # CONFIG_HTC_I2CPLD is not set | ||
| 1416 | # CONFIG_UCB1400_CORE is not set | 1557 | # CONFIG_UCB1400_CORE is not set |
| 1417 | # CONFIG_TPS65010 is not set | 1558 | # CONFIG_TPS65010 is not set |
| 1418 | # CONFIG_TWL4030_CORE is not set | 1559 | # CONFIG_TWL4030_CORE is not set |
| @@ -1421,200 +1562,19 @@ CONFIG_MFD_SM501=y | |||
| 1421 | # CONFIG_MFD_TC6387XB is not set | 1562 | # CONFIG_MFD_TC6387XB is not set |
| 1422 | # CONFIG_MFD_TC6393XB is not set | 1563 | # CONFIG_MFD_TC6393XB is not set |
| 1423 | # CONFIG_PMIC_DA903X is not set | 1564 | # CONFIG_PMIC_DA903X is not set |
| 1565 | # CONFIG_PMIC_ADP5520 is not set | ||
| 1566 | # CONFIG_MFD_MAX8925 is not set | ||
| 1424 | # CONFIG_MFD_WM8400 is not set | 1567 | # CONFIG_MFD_WM8400 is not set |
| 1568 | # CONFIG_MFD_WM831X is not set | ||
| 1425 | # CONFIG_MFD_WM8350_I2C is not set | 1569 | # CONFIG_MFD_WM8350_I2C is not set |
| 1570 | # CONFIG_MFD_WM8994 is not set | ||
| 1426 | # CONFIG_MFD_PCF50633 is not set | 1571 | # CONFIG_MFD_PCF50633 is not set |
| 1427 | 1572 | # CONFIG_MFD_MC13783 is not set | |
| 1428 | # | 1573 | # CONFIG_AB3100_CORE is not set |
| 1429 | # Multimedia devices | 1574 | # CONFIG_EZX_PCAP is not set |
| 1430 | # | 1575 | # CONFIG_AB4500_CORE is not set |
| 1431 | 1576 | # CONFIG_REGULATOR is not set | |
| 1432 | # | 1577 | # CONFIG_MEDIA_SUPPORT is not set |
| 1433 | # Multimedia core support | ||
| 1434 | # | ||
| 1435 | CONFIG_VIDEO_DEV=m | ||
| 1436 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1437 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1438 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1439 | CONFIG_DVB_CORE=m | ||
| 1440 | CONFIG_VIDEO_MEDIA=m | ||
| 1441 | |||
| 1442 | # | ||
| 1443 | # Multimedia drivers | ||
| 1444 | # | ||
| 1445 | CONFIG_MEDIA_ATTACH=y | ||
| 1446 | CONFIG_MEDIA_TUNER=m | ||
| 1447 | # CONFIG_MEDIA_TUNER_CUSTOMISE is not set | ||
| 1448 | CONFIG_MEDIA_TUNER_SIMPLE=m | ||
| 1449 | CONFIG_MEDIA_TUNER_TDA8290=m | ||
| 1450 | CONFIG_MEDIA_TUNER_TDA827X=m | ||
| 1451 | CONFIG_MEDIA_TUNER_TDA18271=m | ||
| 1452 | CONFIG_MEDIA_TUNER_TDA9887=m | ||
| 1453 | CONFIG_MEDIA_TUNER_TEA5761=m | ||
| 1454 | CONFIG_MEDIA_TUNER_TEA5767=m | ||
| 1455 | CONFIG_MEDIA_TUNER_MT20XX=m | ||
| 1456 | CONFIG_MEDIA_TUNER_MT2060=m | ||
| 1457 | CONFIG_MEDIA_TUNER_MT2266=m | ||
| 1458 | CONFIG_MEDIA_TUNER_QT1010=m | ||
| 1459 | CONFIG_MEDIA_TUNER_XC2028=m | ||
| 1460 | CONFIG_MEDIA_TUNER_XC5000=m | ||
| 1461 | CONFIG_MEDIA_TUNER_MXL5005S=m | ||
| 1462 | CONFIG_MEDIA_TUNER_MXL5007T=m | ||
| 1463 | CONFIG_MEDIA_TUNER_MC44S803=m | ||
| 1464 | CONFIG_VIDEO_V4L2=m | ||
| 1465 | CONFIG_VIDEO_V4L1=m | ||
| 1466 | CONFIG_VIDEOBUF_GEN=m | ||
| 1467 | CONFIG_VIDEOBUF_VMALLOC=m | ||
| 1468 | CONFIG_VIDEO_TVEEPROM=m | ||
| 1469 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1470 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1471 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1472 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1473 | CONFIG_VIDEO_VIVI=m | ||
| 1474 | CONFIG_VIDEO_PMS=m | ||
| 1475 | CONFIG_VIDEO_BWQCAM=m | ||
| 1476 | CONFIG_VIDEO_CQCAM=m | ||
| 1477 | CONFIG_VIDEO_W9966=m | ||
| 1478 | CONFIG_VIDEO_CPIA=m | ||
| 1479 | CONFIG_VIDEO_CPIA_PP=m | ||
| 1480 | CONFIG_VIDEO_CPIA_USB=m | ||
| 1481 | CONFIG_VIDEO_CPIA2=m | ||
| 1482 | CONFIG_VIDEO_SAA5246A=m | ||
| 1483 | CONFIG_VIDEO_SAA5249=m | ||
| 1484 | CONFIG_VIDEO_AU0828=m | ||
| 1485 | # CONFIG_SOC_CAMERA is not set | ||
| 1486 | CONFIG_V4L_USB_DRIVERS=y | ||
| 1487 | # CONFIG_USB_VIDEO_CLASS is not set | ||
| 1488 | CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y | ||
| 1489 | CONFIG_USB_GSPCA=m | ||
| 1490 | # CONFIG_USB_M5602 is not set | ||
| 1491 | # CONFIG_USB_STV06XX is not set | ||
| 1492 | # CONFIG_USB_GSPCA_CONEX is not set | ||
| 1493 | # CONFIG_USB_GSPCA_ETOMS is not set | ||
| 1494 | # CONFIG_USB_GSPCA_FINEPIX is not set | ||
| 1495 | # CONFIG_USB_GSPCA_MARS is not set | ||
| 1496 | # CONFIG_USB_GSPCA_MR97310A is not set | ||
| 1497 | # CONFIG_USB_GSPCA_OV519 is not set | ||
| 1498 | # CONFIG_USB_GSPCA_OV534 is not set | ||
| 1499 | # CONFIG_USB_GSPCA_PAC207 is not set | ||
| 1500 | # CONFIG_USB_GSPCA_PAC7311 is not set | ||
| 1501 | # CONFIG_USB_GSPCA_SONIXB is not set | ||
| 1502 | # CONFIG_USB_GSPCA_SONIXJ is not set | ||
| 1503 | # CONFIG_USB_GSPCA_SPCA500 is not set | ||
| 1504 | # CONFIG_USB_GSPCA_SPCA501 is not set | ||
| 1505 | # CONFIG_USB_GSPCA_SPCA505 is not set | ||
| 1506 | # CONFIG_USB_GSPCA_SPCA506 is not set | ||
| 1507 | # CONFIG_USB_GSPCA_SPCA508 is not set | ||
| 1508 | # CONFIG_USB_GSPCA_SPCA561 is not set | ||
| 1509 | # CONFIG_USB_GSPCA_SQ905 is not set | ||
| 1510 | # CONFIG_USB_GSPCA_SQ905C is not set | ||
| 1511 | # CONFIG_USB_GSPCA_STK014 is not set | ||
| 1512 | # CONFIG_USB_GSPCA_SUNPLUS is not set | ||
| 1513 | # CONFIG_USB_GSPCA_T613 is not set | ||
| 1514 | # CONFIG_USB_GSPCA_TV8532 is not set | ||
| 1515 | # CONFIG_USB_GSPCA_VC032X is not set | ||
| 1516 | # CONFIG_USB_GSPCA_ZC3XX is not set | ||
| 1517 | # CONFIG_VIDEO_PVRUSB2 is not set | ||
| 1518 | # CONFIG_VIDEO_HDPVR is not set | ||
| 1519 | # CONFIG_VIDEO_EM28XX is not set | ||
| 1520 | # CONFIG_VIDEO_CX231XX is not set | ||
| 1521 | # CONFIG_VIDEO_USBVISION is not set | ||
| 1522 | # CONFIG_USB_VICAM is not set | ||
| 1523 | # CONFIG_USB_IBMCAM is not set | ||
| 1524 | # CONFIG_USB_KONICAWC is not set | ||
| 1525 | # CONFIG_USB_QUICKCAM_MESSENGER is not set | ||
| 1526 | # CONFIG_USB_ET61X251 is not set | ||
| 1527 | # CONFIG_VIDEO_OVCAMCHIP is not set | ||
| 1528 | # CONFIG_USB_OV511 is not set | ||
| 1529 | # CONFIG_USB_SE401 is not set | ||
| 1530 | # CONFIG_USB_SN9C102 is not set | ||
| 1531 | # CONFIG_USB_STV680 is not set | ||
| 1532 | # CONFIG_USB_ZC0301 is not set | ||
| 1533 | # CONFIG_USB_PWC is not set | ||
| 1534 | CONFIG_USB_PWC_INPUT_EVDEV=y | ||
| 1535 | # CONFIG_USB_ZR364XX is not set | ||
| 1536 | # CONFIG_USB_STKWEBCAM is not set | ||
| 1537 | # CONFIG_USB_S2255 is not set | ||
| 1538 | CONFIG_RADIO_ADAPTERS=y | ||
| 1539 | CONFIG_RADIO_CADET=m | ||
| 1540 | CONFIG_RADIO_RTRACK=m | ||
| 1541 | CONFIG_RADIO_RTRACK2=m | ||
| 1542 | CONFIG_RADIO_AZTECH=m | ||
| 1543 | CONFIG_RADIO_GEMTEK=m | ||
| 1544 | CONFIG_RADIO_SF16FMI=m | ||
| 1545 | CONFIG_RADIO_SF16FMR2=m | ||
| 1546 | CONFIG_RADIO_TERRATEC=m | ||
| 1547 | CONFIG_RADIO_TRUST=m | ||
| 1548 | CONFIG_RADIO_TYPHOON=m | ||
| 1549 | CONFIG_RADIO_TYPHOON_PROC_FS=y | ||
| 1550 | CONFIG_RADIO_ZOLTRIX=m | ||
| 1551 | CONFIG_USB_DSBR=m | ||
| 1552 | CONFIG_USB_SI470X=m | ||
| 1553 | CONFIG_USB_MR800=m | ||
| 1554 | CONFIG_RADIO_TEA5764=m | ||
| 1555 | CONFIG_DVB_DYNAMIC_MINORS=y | ||
| 1556 | CONFIG_DVB_CAPTURE_DRIVERS=y | ||
| 1557 | # CONFIG_TTPCI_EEPROM is not set | ||
| 1558 | |||
| 1559 | # | ||
| 1560 | # Supported USB Adapters | ||
| 1561 | # | ||
| 1562 | CONFIG_DVB_USB=m | ||
| 1563 | # CONFIG_DVB_USB_DEBUG is not set | ||
| 1564 | # CONFIG_DVB_USB_A800 is not set | ||
| 1565 | CONFIG_DVB_USB_DIBUSB_MB=m | ||
| 1566 | # CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set | ||
| 1567 | CONFIG_DVB_USB_DIBUSB_MC=m | ||
| 1568 | CONFIG_DVB_USB_DIB0700=m | ||
| 1569 | CONFIG_DVB_USB_UMT_010=m | ||
| 1570 | CONFIG_DVB_USB_CXUSB=m | ||
| 1571 | CONFIG_DVB_USB_M920X=m | ||
| 1572 | # CONFIG_DVB_USB_GL861 is not set | ||
| 1573 | # CONFIG_DVB_USB_AU6610 is not set | ||
| 1574 | # CONFIG_DVB_USB_DIGITV is not set | ||
| 1575 | # CONFIG_DVB_USB_VP7045 is not set | ||
| 1576 | # CONFIG_DVB_USB_VP702X is not set | ||
| 1577 | # CONFIG_DVB_USB_GP8PSK is not set | ||
| 1578 | # CONFIG_DVB_USB_NOVA_T_USB2 is not set | ||
| 1579 | # CONFIG_DVB_USB_TTUSB2 is not set | ||
| 1580 | # CONFIG_DVB_USB_DTT200U is not set | ||
| 1581 | # CONFIG_DVB_USB_OPERA1 is not set | ||
| 1582 | CONFIG_DVB_USB_AF9005=m | ||
| 1583 | # CONFIG_DVB_USB_AF9005_REMOTE is not set | ||
| 1584 | # CONFIG_DVB_USB_DW2102 is not set | ||
| 1585 | # CONFIG_DVB_USB_CINERGY_T2 is not set | ||
| 1586 | # CONFIG_DVB_USB_ANYSEE is not set | ||
| 1587 | # CONFIG_DVB_USB_DTV5100 is not set | ||
| 1588 | # CONFIG_DVB_USB_AF9015 is not set | ||
| 1589 | # CONFIG_DVB_USB_CE6230 is not set | ||
| 1590 | # CONFIG_DVB_SIANO_SMS1XXX is not set | ||
| 1591 | |||
| 1592 | # | ||
| 1593 | # Supported FlexCopII (B2C2) Adapters | ||
| 1594 | # | ||
| 1595 | # CONFIG_DVB_B2C2_FLEXCOP is not set | ||
| 1596 | |||
| 1597 | # | ||
| 1598 | # Supported DVB Frontends | ||
| 1599 | # | ||
| 1600 | # CONFIG_DVB_FE_CUSTOMISE is not set | ||
| 1601 | CONFIG_DVB_CX22702=m | ||
| 1602 | CONFIG_DVB_TDA1004X=m | ||
| 1603 | CONFIG_DVB_MT352=m | ||
| 1604 | CONFIG_DVB_ZL10353=m | ||
| 1605 | CONFIG_DVB_DIB3000MB=m | ||
| 1606 | CONFIG_DVB_DIB3000MC=m | ||
| 1607 | CONFIG_DVB_DIB7000M=m | ||
| 1608 | CONFIG_DVB_DIB7000P=m | ||
| 1609 | CONFIG_DVB_LGDT330X=m | ||
| 1610 | CONFIG_DVB_LGDT3305=m | ||
| 1611 | CONFIG_DVB_AU8522=m | ||
| 1612 | CONFIG_DVB_S5H1411=m | ||
| 1613 | CONFIG_DVB_PLL=m | ||
| 1614 | CONFIG_DVB_TUNER_DIB0070=m | ||
| 1615 | CONFIG_DVB_LGS8GL5=m | ||
| 1616 | CONFIG_DAB=y | ||
| 1617 | CONFIG_USB_DABUSB=m | ||
| 1618 | 1578 | ||
| 1619 | # | 1579 | # |
| 1620 | # Graphics support | 1580 | # Graphics support |
| @@ -1653,6 +1613,8 @@ CONFIG_FB_SM501=y | |||
| 1653 | # CONFIG_FB_BROADSHEET is not set | 1613 | # CONFIG_FB_BROADSHEET is not set |
| 1654 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 1614 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 1655 | CONFIG_LCD_CLASS_DEVICE=m | 1615 | CONFIG_LCD_CLASS_DEVICE=m |
| 1616 | # CONFIG_LCD_L4F00242T03 is not set | ||
| 1617 | # CONFIG_LCD_LMS283GF05 is not set | ||
| 1656 | # CONFIG_LCD_LTV350QV is not set | 1618 | # CONFIG_LCD_LTV350QV is not set |
| 1657 | # CONFIG_LCD_ILI9320 is not set | 1619 | # CONFIG_LCD_ILI9320 is not set |
| 1658 | # CONFIG_LCD_TDO24M is not set | 1620 | # CONFIG_LCD_TDO24M is not set |
| @@ -1682,6 +1644,7 @@ CONFIG_FONT_8x16=y | |||
| 1682 | # CONFIG_LOGO is not set | 1644 | # CONFIG_LOGO is not set |
| 1683 | CONFIG_SOUND=y | 1645 | CONFIG_SOUND=y |
| 1684 | CONFIG_SOUND_OSS_CORE=y | 1646 | CONFIG_SOUND_OSS_CORE=y |
| 1647 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y | ||
| 1685 | CONFIG_SND=y | 1648 | CONFIG_SND=y |
| 1686 | CONFIG_SND_TIMER=y | 1649 | CONFIG_SND_TIMER=y |
| 1687 | CONFIG_SND_PCM=y | 1650 | CONFIG_SND_PCM=y |
| @@ -1701,36 +1664,43 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 1701 | CONFIG_SND_VERBOSE_PRINTK=y | 1664 | CONFIG_SND_VERBOSE_PRINTK=y |
| 1702 | # CONFIG_SND_DEBUG is not set | 1665 | # CONFIG_SND_DEBUG is not set |
| 1703 | CONFIG_SND_VMASTER=y | 1666 | CONFIG_SND_VMASTER=y |
| 1667 | CONFIG_SND_RAWMIDI_SEQ=m | ||
| 1668 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
| 1669 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
| 1670 | # CONFIG_SND_SBAWE_SEQ is not set | ||
| 1671 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 1704 | CONFIG_SND_AC97_CODEC=m | 1672 | CONFIG_SND_AC97_CODEC=m |
| 1705 | # CONFIG_SND_DRIVERS is not set | 1673 | # CONFIG_SND_DRIVERS is not set |
| 1706 | # CONFIG_SND_ARM is not set | 1674 | # CONFIG_SND_ARM is not set |
| 1707 | # CONFIG_SND_SPI is not set | 1675 | # CONFIG_SND_SPI is not set |
| 1708 | CONFIG_SND_USB=y | 1676 | CONFIG_SND_USB=y |
| 1709 | CONFIG_SND_USB_AUDIO=m | 1677 | CONFIG_SND_USB_AUDIO=m |
| 1678 | # CONFIG_SND_USB_UA101 is not set | ||
| 1710 | CONFIG_SND_USB_CAIAQ=m | 1679 | CONFIG_SND_USB_CAIAQ=m |
| 1711 | # CONFIG_SND_USB_CAIAQ_INPUT is not set | 1680 | # CONFIG_SND_USB_CAIAQ_INPUT is not set |
| 1712 | CONFIG_SND_SOC=y | 1681 | CONFIG_SND_SOC=y |
| 1713 | CONFIG_SND_SOC_AC97_BUS=y | 1682 | CONFIG_SND_SOC_AC97_BUS=y |
| 1714 | CONFIG_SND_S3C24XX_SOC=y | 1683 | CONFIG_SND_S3C24XX_SOC=y |
| 1715 | CONFIG_SND_S3C24XX_SOC_I2S=m | 1684 | CONFIG_SND_S3C24XX_SOC_I2S=y |
| 1716 | CONFIG_SND_S3C_I2SV2_SOC=m | 1685 | CONFIG_SND_S3C_I2SV2_SOC=m |
| 1717 | CONFIG_SND_S3C2412_SOC_I2S=m | 1686 | CONFIG_SND_S3C2412_SOC_I2S=m |
| 1718 | CONFIG_SND_S3C2443_SOC_AC97=m | 1687 | CONFIG_SND_S3C_SOC_AC97=m |
| 1719 | CONFIG_SND_S3C24XX_SOC_JIVE_WM8750=m | 1688 | CONFIG_SND_S3C24XX_SOC_JIVE_WM8750=m |
| 1720 | CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710=m | 1689 | CONFIG_SND_S3C24XX_SOC_SMDK2443_WM9710=m |
| 1721 | CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650=m | 1690 | CONFIG_SND_S3C24XX_SOC_LN2440SBC_ALC650=m |
| 1722 | CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=m | 1691 | CONFIG_SND_S3C24XX_SOC_S3C24XX_UDA134X=y |
| 1692 | # CONFIG_SND_S3C24XX_SOC_SIMTEC_TLV320AIC23 is not set | ||
| 1693 | # CONFIG_SND_S3C24XX_SOC_SIMTEC_HERMES is not set | ||
| 1723 | CONFIG_SND_SOC_I2C_AND_SPI=y | 1694 | CONFIG_SND_SOC_I2C_AND_SPI=y |
| 1724 | # CONFIG_SND_SOC_ALL_CODECS is not set | 1695 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 1725 | CONFIG_SND_SOC_AC97_CODEC=m | 1696 | CONFIG_SND_SOC_AC97_CODEC=m |
| 1726 | CONFIG_SND_SOC_L3=m | 1697 | CONFIG_SND_SOC_L3=y |
| 1727 | CONFIG_SND_SOC_UDA134X=m | 1698 | CONFIG_SND_SOC_UDA134X=y |
| 1728 | CONFIG_SND_SOC_WM8750=m | 1699 | CONFIG_SND_SOC_WM8750=m |
| 1729 | # CONFIG_SOUND_PRIME is not set | 1700 | # CONFIG_SOUND_PRIME is not set |
| 1730 | CONFIG_AC97_BUS=y | 1701 | CONFIG_AC97_BUS=y |
| 1731 | CONFIG_HID_SUPPORT=y | 1702 | CONFIG_HID_SUPPORT=y |
| 1732 | CONFIG_HID=y | 1703 | CONFIG_HID=y |
| 1733 | # CONFIG_HID_DEBUG is not set | ||
| 1734 | # CONFIG_HIDRAW is not set | 1704 | # CONFIG_HIDRAW is not set |
| 1735 | 1705 | ||
| 1736 | # | 1706 | # |
| @@ -1743,6 +1713,8 @@ CONFIG_HID=y | |||
| 1743 | # Special HID drivers | 1713 | # Special HID drivers |
| 1744 | # | 1714 | # |
| 1745 | CONFIG_HID_APPLE=m | 1715 | CONFIG_HID_APPLE=m |
| 1716 | # CONFIG_HID_MAGICMOUSE is not set | ||
| 1717 | # CONFIG_HID_WACOM is not set | ||
| 1746 | CONFIG_USB_SUPPORT=y | 1718 | CONFIG_USB_SUPPORT=y |
| 1747 | CONFIG_USB_ARCH_HAS_HCD=y | 1719 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1748 | CONFIG_USB_ARCH_HAS_OHCI=y | 1720 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -1757,8 +1729,6 @@ CONFIG_USB=y | |||
| 1757 | CONFIG_USB_DEVICEFS=y | 1729 | CONFIG_USB_DEVICEFS=y |
| 1758 | CONFIG_USB_DEVICE_CLASS=y | 1730 | CONFIG_USB_DEVICE_CLASS=y |
| 1759 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1731 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1760 | # CONFIG_USB_SUSPEND is not set | ||
| 1761 | # CONFIG_USB_OTG is not set | ||
| 1762 | CONFIG_USB_MON=y | 1732 | CONFIG_USB_MON=y |
| 1763 | # CONFIG_USB_WUSB is not set | 1733 | # CONFIG_USB_WUSB is not set |
| 1764 | # CONFIG_USB_WUSB_CBAF is not set | 1734 | # CONFIG_USB_WUSB_CBAF is not set |
| @@ -1770,6 +1740,7 @@ CONFIG_USB_MON=y | |||
| 1770 | # CONFIG_USB_OXU210HP_HCD is not set | 1740 | # CONFIG_USB_OXU210HP_HCD is not set |
| 1771 | # CONFIG_USB_ISP116X_HCD is not set | 1741 | # CONFIG_USB_ISP116X_HCD is not set |
| 1772 | # CONFIG_USB_ISP1760_HCD is not set | 1742 | # CONFIG_USB_ISP1760_HCD is not set |
| 1743 | # CONFIG_USB_ISP1362_HCD is not set | ||
| 1773 | CONFIG_USB_OHCI_HCD=y | 1744 | CONFIG_USB_OHCI_HCD=y |
| 1774 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | 1745 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 1775 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | 1746 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set |
| @@ -1854,6 +1825,7 @@ CONFIG_USB_SERIAL_FTDI_SIO=y | |||
| 1854 | CONFIG_USB_SERIAL_NAVMAN=m | 1825 | CONFIG_USB_SERIAL_NAVMAN=m |
| 1855 | CONFIG_USB_SERIAL_PL2303=y | 1826 | CONFIG_USB_SERIAL_PL2303=y |
| 1856 | # CONFIG_USB_SERIAL_OTI6858 is not set | 1827 | # CONFIG_USB_SERIAL_OTI6858 is not set |
| 1828 | # CONFIG_USB_SERIAL_QCAUX is not set | ||
| 1857 | # CONFIG_USB_SERIAL_QUALCOMM is not set | 1829 | # CONFIG_USB_SERIAL_QUALCOMM is not set |
| 1858 | # CONFIG_USB_SERIAL_SPCP8X5 is not set | 1830 | # CONFIG_USB_SERIAL_SPCP8X5 is not set |
| 1859 | # CONFIG_USB_SERIAL_HP4X is not set | 1831 | # CONFIG_USB_SERIAL_HP4X is not set |
| @@ -1867,6 +1839,7 @@ CONFIG_USB_SERIAL_PL2303=y | |||
| 1867 | CONFIG_USB_SERIAL_OPTION=m | 1839 | CONFIG_USB_SERIAL_OPTION=m |
| 1868 | # CONFIG_USB_SERIAL_OMNINET is not set | 1840 | # CONFIG_USB_SERIAL_OMNINET is not set |
| 1869 | # CONFIG_USB_SERIAL_OPTICON is not set | 1841 | # CONFIG_USB_SERIAL_OPTICON is not set |
| 1842 | # CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set | ||
| 1870 | # CONFIG_USB_SERIAL_DEBUG is not set | 1843 | # CONFIG_USB_SERIAL_DEBUG is not set |
| 1871 | 1844 | ||
| 1872 | # | 1845 | # |
| @@ -1879,7 +1852,6 @@ CONFIG_USB_SEVSEG=m | |||
| 1879 | CONFIG_USB_RIO500=m | 1852 | CONFIG_USB_RIO500=m |
| 1880 | CONFIG_USB_LEGOTOWER=m | 1853 | CONFIG_USB_LEGOTOWER=m |
| 1881 | CONFIG_USB_LCD=m | 1854 | CONFIG_USB_LCD=m |
| 1882 | CONFIG_USB_BERRY_CHARGE=m | ||
| 1883 | CONFIG_USB_LED=m | 1855 | CONFIG_USB_LED=m |
| 1884 | CONFIG_USB_CYPRESS_CY7C63=m | 1856 | CONFIG_USB_CYPRESS_CY7C63=m |
| 1885 | CONFIG_USB_CYTHERM=m | 1857 | CONFIG_USB_CYTHERM=m |
| @@ -1891,13 +1863,13 @@ CONFIG_USB_TRANCEVIBRATOR=m | |||
| 1891 | CONFIG_USB_IOWARRIOR=m | 1863 | CONFIG_USB_IOWARRIOR=m |
| 1892 | CONFIG_USB_TEST=m | 1864 | CONFIG_USB_TEST=m |
| 1893 | # CONFIG_USB_ISIGHTFW is not set | 1865 | # CONFIG_USB_ISIGHTFW is not set |
| 1894 | # CONFIG_USB_VST is not set | ||
| 1895 | # CONFIG_USB_GADGET is not set | 1866 | # CONFIG_USB_GADGET is not set |
| 1896 | 1867 | ||
| 1897 | # | 1868 | # |
| 1898 | # OTG and related infrastructure | 1869 | # OTG and related infrastructure |
| 1899 | # | 1870 | # |
| 1900 | # CONFIG_USB_GPIO_VBUS is not set | 1871 | # CONFIG_USB_GPIO_VBUS is not set |
| 1872 | # CONFIG_USB_ULPI is not set | ||
| 1901 | # CONFIG_NOP_USB_XCEIV is not set | 1873 | # CONFIG_NOP_USB_XCEIV is not set |
| 1902 | CONFIG_MMC=y | 1874 | CONFIG_MMC=y |
| 1903 | # CONFIG_MMC_DEBUG is not set | 1875 | # CONFIG_MMC_DEBUG is not set |
| @@ -1915,10 +1887,15 @@ CONFIG_MMC_TEST=m | |||
| 1915 | # MMC/SD/SDIO Host Controller Drivers | 1887 | # MMC/SD/SDIO Host Controller Drivers |
| 1916 | # | 1888 | # |
| 1917 | CONFIG_MMC_SDHCI=m | 1889 | CONFIG_MMC_SDHCI=m |
| 1890 | # CONFIG_MMC_SDHCI_PLTFM is not set | ||
| 1891 | # CONFIG_MMC_SDHCI_S3C is not set | ||
| 1918 | CONFIG_MMC_SPI=m | 1892 | CONFIG_MMC_SPI=m |
| 1919 | CONFIG_MMC_S3C=y | 1893 | CONFIG_MMC_S3C=y |
| 1894 | # CONFIG_MMC_S3C_HW_SDIO_IRQ is not set | ||
| 1895 | CONFIG_MMC_S3C_PIO=y | ||
| 1896 | # CONFIG_MMC_S3C_DMA is not set | ||
| 1897 | # CONFIG_MMC_S3C_PIODMA is not set | ||
| 1920 | # CONFIG_MEMSTICK is not set | 1898 | # CONFIG_MEMSTICK is not set |
| 1921 | # CONFIG_ACCESSIBILITY is not set | ||
| 1922 | CONFIG_NEW_LEDS=y | 1899 | CONFIG_NEW_LEDS=y |
| 1923 | CONFIG_LEDS_CLASS=m | 1900 | CONFIG_LEDS_CLASS=m |
| 1924 | 1901 | ||
| @@ -1930,26 +1907,28 @@ CONFIG_LEDS_H1940=m | |||
| 1930 | CONFIG_LEDS_PCA9532=m | 1907 | CONFIG_LEDS_PCA9532=m |
| 1931 | CONFIG_LEDS_GPIO=m | 1908 | CONFIG_LEDS_GPIO=m |
| 1932 | CONFIG_LEDS_GPIO_PLATFORM=y | 1909 | CONFIG_LEDS_GPIO_PLATFORM=y |
| 1933 | CONFIG_LEDS_LP5521=m | 1910 | # CONFIG_LEDS_LP3944 is not set |
| 1934 | CONFIG_LEDS_PCA955X=m | 1911 | CONFIG_LEDS_PCA955X=m |
| 1935 | CONFIG_LEDS_DAC124S085=m | 1912 | CONFIG_LEDS_DAC124S085=m |
| 1936 | CONFIG_LEDS_PWM=m | 1913 | CONFIG_LEDS_PWM=m |
| 1937 | CONFIG_LEDS_BD2802=m | 1914 | CONFIG_LEDS_BD2802=m |
| 1915 | # CONFIG_LEDS_LT3593 is not set | ||
| 1916 | CONFIG_LEDS_TRIGGERS=y | ||
| 1938 | 1917 | ||
| 1939 | # | 1918 | # |
| 1940 | # LED Triggers | 1919 | # LED Triggers |
| 1941 | # | 1920 | # |
| 1942 | CONFIG_LEDS_TRIGGERS=y | ||
| 1943 | CONFIG_LEDS_TRIGGER_TIMER=m | 1921 | CONFIG_LEDS_TRIGGER_TIMER=m |
| 1944 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set | 1922 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set |
| 1945 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m | 1923 | CONFIG_LEDS_TRIGGER_HEARTBEAT=m |
| 1946 | CONFIG_LEDS_TRIGGER_BACKLIGHT=m | 1924 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y |
| 1947 | CONFIG_LEDS_TRIGGER_GPIO=m | 1925 | CONFIG_LEDS_TRIGGER_GPIO=m |
| 1948 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=m | 1926 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=m |
| 1949 | 1927 | ||
| 1950 | # | 1928 | # |
| 1951 | # iptables trigger is under Netfilter config (LED target) | 1929 | # iptables trigger is under Netfilter config (LED target) |
| 1952 | # | 1930 | # |
| 1931 | # CONFIG_ACCESSIBILITY is not set | ||
| 1953 | CONFIG_RTC_LIB=y | 1932 | CONFIG_RTC_LIB=y |
| 1954 | CONFIG_RTC_CLASS=y | 1933 | CONFIG_RTC_CLASS=y |
| 1955 | CONFIG_RTC_HCTOSYS=y | 1934 | CONFIG_RTC_HCTOSYS=y |
| @@ -1978,9 +1957,11 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1978 | # CONFIG_RTC_DRV_PCF8563 is not set | 1957 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1979 | # CONFIG_RTC_DRV_PCF8583 is not set | 1958 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1980 | # CONFIG_RTC_DRV_M41T80 is not set | 1959 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1960 | # CONFIG_RTC_DRV_BQ32K is not set | ||
| 1981 | # CONFIG_RTC_DRV_S35390A is not set | 1961 | # CONFIG_RTC_DRV_S35390A is not set |
| 1982 | # CONFIG_RTC_DRV_FM3130 is not set | 1962 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1983 | # CONFIG_RTC_DRV_RX8581 is not set | 1963 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1964 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1984 | 1965 | ||
| 1985 | # | 1966 | # |
| 1986 | # SPI RTC drivers | 1967 | # SPI RTC drivers |
| @@ -1992,6 +1973,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1992 | # CONFIG_RTC_DRV_R9701 is not set | 1973 | # CONFIG_RTC_DRV_R9701 is not set |
| 1993 | # CONFIG_RTC_DRV_RS5C348 is not set | 1974 | # CONFIG_RTC_DRV_RS5C348 is not set |
| 1994 | # CONFIG_RTC_DRV_DS3234 is not set | 1975 | # CONFIG_RTC_DRV_DS3234 is not set |
| 1976 | # CONFIG_RTC_DRV_PCF2123 is not set | ||
| 1995 | 1977 | ||
| 1996 | # | 1978 | # |
| 1997 | # Platform RTC drivers | 1979 | # Platform RTC drivers |
| @@ -2005,7 +1987,9 @@ CONFIG_RTC_INTF_DEV=y | |||
| 2005 | # CONFIG_RTC_DRV_M48T86 is not set | 1987 | # CONFIG_RTC_DRV_M48T86 is not set |
| 2006 | # CONFIG_RTC_DRV_M48T35 is not set | 1988 | # CONFIG_RTC_DRV_M48T35 is not set |
| 2007 | # CONFIG_RTC_DRV_M48T59 is not set | 1989 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1990 | # CONFIG_RTC_DRV_MSM6242 is not set | ||
| 2008 | # CONFIG_RTC_DRV_BQ4802 is not set | 1991 | # CONFIG_RTC_DRV_BQ4802 is not set |
| 1992 | # CONFIG_RTC_DRV_RP5C01 is not set | ||
| 2009 | # CONFIG_RTC_DRV_V3020 is not set | 1993 | # CONFIG_RTC_DRV_V3020 is not set |
| 2010 | 1994 | ||
| 2011 | # | 1995 | # |
| @@ -2014,8 +1998,11 @@ CONFIG_RTC_INTF_DEV=y | |||
| 2014 | CONFIG_RTC_DRV_S3C=y | 1998 | CONFIG_RTC_DRV_S3C=y |
| 2015 | # CONFIG_DMADEVICES is not set | 1999 | # CONFIG_DMADEVICES is not set |
| 2016 | # CONFIG_AUXDISPLAY is not set | 2000 | # CONFIG_AUXDISPLAY is not set |
| 2017 | # CONFIG_REGULATOR is not set | ||
| 2018 | # CONFIG_UIO is not set | 2001 | # CONFIG_UIO is not set |
| 2002 | |||
| 2003 | # | ||
| 2004 | # TI VLYNQ | ||
| 2005 | # | ||
| 2019 | # CONFIG_STAGING is not set | 2006 | # CONFIG_STAGING is not set |
| 2020 | 2007 | ||
| 2021 | # | 2008 | # |
| @@ -2032,20 +2019,23 @@ CONFIG_EXT3_FS_XATTR=y | |||
| 2032 | CONFIG_EXT3_FS_POSIX_ACL=y | 2019 | CONFIG_EXT3_FS_POSIX_ACL=y |
| 2033 | # CONFIG_EXT3_FS_SECURITY is not set | 2020 | # CONFIG_EXT3_FS_SECURITY is not set |
| 2034 | CONFIG_EXT4_FS=m | 2021 | CONFIG_EXT4_FS=m |
| 2035 | # CONFIG_EXT4DEV_COMPAT is not set | ||
| 2036 | CONFIG_EXT4_FS_XATTR=y | 2022 | CONFIG_EXT4_FS_XATTR=y |
| 2037 | CONFIG_EXT4_FS_POSIX_ACL=y | 2023 | CONFIG_EXT4_FS_POSIX_ACL=y |
| 2038 | # CONFIG_EXT4_FS_SECURITY is not set | 2024 | # CONFIG_EXT4_FS_SECURITY is not set |
| 2025 | # CONFIG_EXT4_DEBUG is not set | ||
| 2039 | CONFIG_JBD=y | 2026 | CONFIG_JBD=y |
| 2040 | CONFIG_JBD2=m | 2027 | CONFIG_JBD2=m |
| 2041 | CONFIG_FS_MBCACHE=y | 2028 | CONFIG_FS_MBCACHE=y |
| 2042 | # CONFIG_REISERFS_FS is not set | 2029 | # CONFIG_REISERFS_FS is not set |
| 2043 | # CONFIG_JFS_FS is not set | 2030 | # CONFIG_JFS_FS is not set |
| 2044 | CONFIG_FS_POSIX_ACL=y | 2031 | CONFIG_FS_POSIX_ACL=y |
| 2045 | CONFIG_FILE_LOCKING=y | ||
| 2046 | # CONFIG_XFS_FS is not set | 2032 | # CONFIG_XFS_FS is not set |
| 2033 | # CONFIG_GFS2_FS is not set | ||
| 2047 | # CONFIG_OCFS2_FS is not set | 2034 | # CONFIG_OCFS2_FS is not set |
| 2048 | # CONFIG_BTRFS_FS is not set | 2035 | # CONFIG_BTRFS_FS is not set |
| 2036 | # CONFIG_NILFS2_FS is not set | ||
| 2037 | CONFIG_FILE_LOCKING=y | ||
| 2038 | CONFIG_FSNOTIFY=y | ||
| 2049 | CONFIG_DNOTIFY=y | 2039 | CONFIG_DNOTIFY=y |
| 2050 | CONFIG_INOTIFY=y | 2040 | CONFIG_INOTIFY=y |
| 2051 | CONFIG_INOTIFY_USER=y | 2041 | CONFIG_INOTIFY_USER=y |
| @@ -2053,6 +2043,7 @@ CONFIG_INOTIFY_USER=y | |||
| 2053 | CONFIG_AUTOFS_FS=m | 2043 | CONFIG_AUTOFS_FS=m |
| 2054 | CONFIG_AUTOFS4_FS=m | 2044 | CONFIG_AUTOFS4_FS=m |
| 2055 | CONFIG_FUSE_FS=m | 2045 | CONFIG_FUSE_FS=m |
| 2046 | # CONFIG_CUSE is not set | ||
| 2056 | CONFIG_GENERIC_ACL=y | 2047 | CONFIG_GENERIC_ACL=y |
| 2057 | 2048 | ||
| 2058 | # | 2049 | # |
| @@ -2111,6 +2102,7 @@ CONFIG_JFFS2_ZLIB=y | |||
| 2111 | # CONFIG_JFFS2_LZO is not set | 2102 | # CONFIG_JFFS2_LZO is not set |
| 2112 | CONFIG_JFFS2_RTIME=y | 2103 | CONFIG_JFFS2_RTIME=y |
| 2113 | # CONFIG_JFFS2_RUBIN is not set | 2104 | # CONFIG_JFFS2_RUBIN is not set |
| 2105 | # CONFIG_LOGFS is not set | ||
| 2114 | CONFIG_CRAMFS=y | 2106 | CONFIG_CRAMFS=y |
| 2115 | CONFIG_SQUASHFS=m | 2107 | CONFIG_SQUASHFS=m |
| 2116 | # CONFIG_SQUASHFS_EMBEDDED is not set | 2108 | # CONFIG_SQUASHFS_EMBEDDED is not set |
| @@ -2127,7 +2119,6 @@ CONFIG_ROMFS_BACKED_BY_BLOCK=y | |||
| 2127 | CONFIG_ROMFS_ON_BLOCK=y | 2119 | CONFIG_ROMFS_ON_BLOCK=y |
| 2128 | # CONFIG_SYSV_FS is not set | 2120 | # CONFIG_SYSV_FS is not set |
| 2129 | # CONFIG_UFS_FS is not set | 2121 | # CONFIG_UFS_FS is not set |
| 2130 | # CONFIG_NILFS2_FS is not set | ||
| 2131 | CONFIG_NETWORK_FILESYSTEMS=y | 2122 | CONFIG_NETWORK_FILESYSTEMS=y |
| 2132 | CONFIG_NFS_FS=y | 2123 | CONFIG_NFS_FS=y |
| 2133 | CONFIG_NFS_V3=y | 2124 | CONFIG_NFS_V3=y |
| @@ -2149,6 +2140,7 @@ CONFIG_SUNRPC_GSS=m | |||
| 2149 | CONFIG_RPCSEC_GSS_KRB5=m | 2140 | CONFIG_RPCSEC_GSS_KRB5=m |
| 2150 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 2141 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 2151 | # CONFIG_SMB_FS is not set | 2142 | # CONFIG_SMB_FS is not set |
| 2143 | # CONFIG_CEPH_FS is not set | ||
| 2152 | CONFIG_CIFS=m | 2144 | CONFIG_CIFS=m |
| 2153 | # CONFIG_CIFS_STATS is not set | 2145 | # CONFIG_CIFS_STATS is not set |
| 2154 | # CONFIG_CIFS_WEAK_PW_HASH is not set | 2146 | # CONFIG_CIFS_WEAK_PW_HASH is not set |
| @@ -2230,6 +2222,7 @@ CONFIG_ENABLE_WARN_DEPRECATED=y | |||
| 2230 | CONFIG_ENABLE_MUST_CHECK=y | 2222 | CONFIG_ENABLE_MUST_CHECK=y |
| 2231 | CONFIG_FRAME_WARN=1024 | 2223 | CONFIG_FRAME_WARN=1024 |
| 2232 | CONFIG_MAGIC_SYSRQ=y | 2224 | CONFIG_MAGIC_SYSRQ=y |
| 2225 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 2233 | # CONFIG_UNUSED_SYMBOLS is not set | 2226 | # CONFIG_UNUSED_SYMBOLS is not set |
| 2234 | # CONFIG_DEBUG_FS is not set | 2227 | # CONFIG_DEBUG_FS is not set |
| 2235 | # CONFIG_HEADERS_CHECK is not set | 2228 | # CONFIG_HEADERS_CHECK is not set |
| @@ -2246,6 +2239,7 @@ CONFIG_SCHED_DEBUG=y | |||
| 2246 | # CONFIG_TIMER_STATS is not set | 2239 | # CONFIG_TIMER_STATS is not set |
| 2247 | # CONFIG_DEBUG_OBJECTS is not set | 2240 | # CONFIG_DEBUG_OBJECTS is not set |
| 2248 | # CONFIG_DEBUG_SLAB is not set | 2241 | # CONFIG_DEBUG_SLAB is not set |
| 2242 | # CONFIG_DEBUG_KMEMLEAK is not set | ||
| 2249 | # CONFIG_DEBUG_RT_MUTEXES is not set | 2243 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 2250 | # CONFIG_RT_MUTEX_TESTER is not set | 2244 | # CONFIG_RT_MUTEX_TESTER is not set |
| 2251 | # CONFIG_DEBUG_SPINLOCK is not set | 2245 | # CONFIG_DEBUG_SPINLOCK is not set |
| @@ -2264,28 +2258,28 @@ CONFIG_DEBUG_MEMORY_INIT=y | |||
| 2264 | # CONFIG_DEBUG_LIST is not set | 2258 | # CONFIG_DEBUG_LIST is not set |
| 2265 | # CONFIG_DEBUG_SG is not set | 2259 | # CONFIG_DEBUG_SG is not set |
| 2266 | # CONFIG_DEBUG_NOTIFIERS is not set | 2260 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 2261 | # CONFIG_DEBUG_CREDENTIALS is not set | ||
| 2267 | CONFIG_FRAME_POINTER=y | 2262 | CONFIG_FRAME_POINTER=y |
| 2268 | # CONFIG_BOOT_PRINTK_DELAY is not set | 2263 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 2269 | # CONFIG_RCU_TORTURE_TEST is not set | 2264 | # CONFIG_RCU_TORTURE_TEST is not set |
| 2270 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 2265 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| 2271 | # CONFIG_BACKTRACE_SELF_TEST is not set | 2266 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 2272 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 2267 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 2268 | # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set | ||
| 2273 | # CONFIG_FAULT_INJECTION is not set | 2269 | # CONFIG_FAULT_INJECTION is not set |
| 2274 | # CONFIG_LATENCYTOP is not set | 2270 | # CONFIG_LATENCYTOP is not set |
| 2275 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 2271 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 2276 | # CONFIG_PAGE_POISONING is not set | 2272 | # CONFIG_PAGE_POISONING is not set |
| 2277 | CONFIG_HAVE_FUNCTION_TRACER=y | 2273 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 2278 | CONFIG_TRACING_SUPPORT=y | 2274 | CONFIG_TRACING_SUPPORT=y |
| 2279 | 2275 | CONFIG_FTRACE=y | |
| 2280 | # | ||
| 2281 | # Tracers | ||
| 2282 | # | ||
| 2283 | # CONFIG_FUNCTION_TRACER is not set | 2276 | # CONFIG_FUNCTION_TRACER is not set |
| 2284 | # CONFIG_SCHED_TRACER is not set | 2277 | # CONFIG_SCHED_TRACER is not set |
| 2285 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 2278 | # CONFIG_ENABLE_DEFAULT_TRACERS is not set |
| 2286 | # CONFIG_EVENT_TRACER is not set | ||
| 2287 | # CONFIG_BOOT_TRACER is not set | 2279 | # CONFIG_BOOT_TRACER is not set |
| 2288 | # CONFIG_TRACE_BRANCH_PROFILING is not set | 2280 | CONFIG_BRANCH_PROFILE_NONE=y |
| 2281 | # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set | ||
| 2282 | # CONFIG_PROFILE_ALL_BRANCHES is not set | ||
| 2289 | # CONFIG_STACK_TRACER is not set | 2283 | # CONFIG_STACK_TRACER is not set |
| 2290 | # CONFIG_KMEMTRACE is not set | 2284 | # CONFIG_KMEMTRACE is not set |
| 2291 | # CONFIG_WORKQUEUE_TRACER is not set | 2285 | # CONFIG_WORKQUEUE_TRACER is not set |
| @@ -2297,7 +2291,9 @@ CONFIG_DEBUG_USER=y | |||
| 2297 | CONFIG_DEBUG_ERRORS=y | 2291 | CONFIG_DEBUG_ERRORS=y |
| 2298 | # CONFIG_DEBUG_STACK_USAGE is not set | 2292 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 2299 | CONFIG_DEBUG_LL=y | 2293 | CONFIG_DEBUG_LL=y |
| 2294 | # CONFIG_EARLY_PRINTK is not set | ||
| 2300 | # CONFIG_DEBUG_ICEDCC is not set | 2295 | # CONFIG_DEBUG_ICEDCC is not set |
| 2296 | # CONFIG_OC_ETM is not set | ||
| 2301 | CONFIG_DEBUG_S3C_UART=0 | 2297 | CONFIG_DEBUG_S3C_UART=0 |
| 2302 | 2298 | ||
| 2303 | # | 2299 | # |
| @@ -2306,13 +2302,16 @@ CONFIG_DEBUG_S3C_UART=0 | |||
| 2306 | # CONFIG_KEYS is not set | 2302 | # CONFIG_KEYS is not set |
| 2307 | # CONFIG_SECURITY is not set | 2303 | # CONFIG_SECURITY is not set |
| 2308 | # CONFIG_SECURITYFS is not set | 2304 | # CONFIG_SECURITYFS is not set |
| 2309 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 2305 | # CONFIG_DEFAULT_SECURITY_SELINUX is not set |
| 2306 | # CONFIG_DEFAULT_SECURITY_SMACK is not set | ||
| 2307 | # CONFIG_DEFAULT_SECURITY_TOMOYO is not set | ||
| 2308 | CONFIG_DEFAULT_SECURITY_DAC=y | ||
| 2309 | CONFIG_DEFAULT_SECURITY="" | ||
| 2310 | CONFIG_CRYPTO=y | 2310 | CONFIG_CRYPTO=y |
| 2311 | 2311 | ||
| 2312 | # | 2312 | # |
| 2313 | # Crypto core or helper | 2313 | # Crypto core or helper |
| 2314 | # | 2314 | # |
| 2315 | # CONFIG_CRYPTO_FIPS is not set | ||
| 2316 | CONFIG_CRYPTO_ALGAPI=m | 2315 | CONFIG_CRYPTO_ALGAPI=m |
| 2317 | CONFIG_CRYPTO_ALGAPI2=m | 2316 | CONFIG_CRYPTO_ALGAPI2=m |
| 2318 | CONFIG_CRYPTO_AEAD=m | 2317 | CONFIG_CRYPTO_AEAD=m |
| @@ -2355,11 +2354,13 @@ CONFIG_CRYPTO_ECB=m | |||
| 2355 | # | 2354 | # |
| 2356 | CONFIG_CRYPTO_HMAC=m | 2355 | CONFIG_CRYPTO_HMAC=m |
| 2357 | # CONFIG_CRYPTO_XCBC is not set | 2356 | # CONFIG_CRYPTO_XCBC is not set |
| 2357 | # CONFIG_CRYPTO_VMAC is not set | ||
| 2358 | 2358 | ||
| 2359 | # | 2359 | # |
| 2360 | # Digest | 2360 | # Digest |
| 2361 | # | 2361 | # |
| 2362 | CONFIG_CRYPTO_CRC32C=m | 2362 | CONFIG_CRYPTO_CRC32C=m |
| 2363 | # CONFIG_CRYPTO_GHASH is not set | ||
| 2363 | # CONFIG_CRYPTO_MD4 is not set | 2364 | # CONFIG_CRYPTO_MD4 is not set |
| 2364 | CONFIG_CRYPTO_MD5=m | 2365 | CONFIG_CRYPTO_MD5=m |
| 2365 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 2366 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| @@ -2420,9 +2421,11 @@ CONFIG_CRC7=m | |||
| 2420 | CONFIG_LIBCRC32C=m | 2421 | CONFIG_LIBCRC32C=m |
| 2421 | CONFIG_ZLIB_INFLATE=y | 2422 | CONFIG_ZLIB_INFLATE=y |
| 2422 | CONFIG_ZLIB_DEFLATE=y | 2423 | CONFIG_ZLIB_DEFLATE=y |
| 2424 | CONFIG_LZO_DECOMPRESS=y | ||
| 2423 | CONFIG_DECOMPRESS_GZIP=y | 2425 | CONFIG_DECOMPRESS_GZIP=y |
| 2424 | CONFIG_DECOMPRESS_BZIP2=y | 2426 | CONFIG_DECOMPRESS_BZIP2=y |
| 2425 | CONFIG_DECOMPRESS_LZMA=y | 2427 | CONFIG_DECOMPRESS_LZMA=y |
| 2428 | CONFIG_DECOMPRESS_LZO=y | ||
| 2426 | CONFIG_TEXTSEARCH=y | 2429 | CONFIG_TEXTSEARCH=y |
| 2427 | CONFIG_TEXTSEARCH_KMP=m | 2430 | CONFIG_TEXTSEARCH_KMP=m |
| 2428 | CONFIG_TEXTSEARCH_BM=m | 2431 | CONFIG_TEXTSEARCH_BM=m |
| @@ -2430,3 +2433,4 @@ CONFIG_TEXTSEARCH_FSM=m | |||
| 2430 | CONFIG_HAS_IOMEM=y | 2433 | CONFIG_HAS_IOMEM=y |
| 2431 | CONFIG_HAS_DMA=y | 2434 | CONFIG_HAS_DMA=y |
| 2432 | CONFIG_NLATTR=y | 2435 | CONFIG_NLATTR=y |
| 2436 | CONFIG_GENERIC_ATOMIC64=y | ||
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig index 5e7d4c1b8fc1..a3a9993e5cd0 100644 --- a/arch/arm/configs/s3c6400_defconfig +++ b/arch/arm/configs/s3c6400_defconfig | |||
| @@ -1,11 +1,12 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.33-rc4 | 3 | # Linux kernel version: 2.6.34 |
| 4 | # Tue Jan 19 13:12:40 2010 | 4 | # Sat May 22 03:17:32 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_HAVE_PROC_CPU=y | ||
| 9 | CONFIG_NO_IOPORT=y | 10 | CONFIG_NO_IOPORT=y |
| 10 | CONFIG_GENERIC_HARDIRQS=y | 11 | CONFIG_GENERIC_HARDIRQS=y |
| 11 | CONFIG_STACKTRACE_SUPPORT=y | 12 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -18,6 +19,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 18 | CONFIG_ARCH_HAS_CPUFREQ=y | 19 | CONFIG_ARCH_HAS_CPUFREQ=y |
| 19 | CONFIG_GENERIC_HWEIGHT=y | 20 | CONFIG_GENERIC_HWEIGHT=y |
| 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 22 | CONFIG_NEED_DMA_MAP_STATE=y | ||
| 21 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 23 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 22 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
| 23 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 25 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| @@ -53,7 +55,6 @@ CONFIG_RCU_FANOUT=32 | |||
| 53 | # CONFIG_TREE_RCU_TRACE is not set | 55 | # CONFIG_TREE_RCU_TRACE is not set |
| 54 | # CONFIG_IKCONFIG is not set | 56 | # CONFIG_IKCONFIG is not set |
| 55 | CONFIG_LOG_BUF_SHIFT=17 | 57 | CONFIG_LOG_BUF_SHIFT=17 |
| 56 | # CONFIG_GROUP_SCHED is not set | ||
| 57 | # CONFIG_CGROUPS is not set | 58 | # CONFIG_CGROUPS is not set |
| 58 | CONFIG_SYSFS_DEPRECATED=y | 59 | CONFIG_SYSFS_DEPRECATED=y |
| 59 | CONFIG_SYSFS_DEPRECATED_V2=y | 60 | CONFIG_SYSFS_DEPRECATED_V2=y |
| @@ -89,10 +90,14 @@ CONFIG_TIMERFD=y | |||
| 89 | CONFIG_EVENTFD=y | 90 | CONFIG_EVENTFD=y |
| 90 | CONFIG_SHMEM=y | 91 | CONFIG_SHMEM=y |
| 91 | CONFIG_AIO=y | 92 | CONFIG_AIO=y |
| 93 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 94 | CONFIG_PERF_USE_VMALLOC=y | ||
| 92 | 95 | ||
| 93 | # | 96 | # |
| 94 | # Kernel Performance Events And Counters | 97 | # Kernel Performance Events And Counters |
| 95 | # | 98 | # |
| 99 | # CONFIG_PERF_EVENTS is not set | ||
| 100 | # CONFIG_PERF_COUNTERS is not set | ||
| 96 | CONFIG_VM_EVENT_COUNTERS=y | 101 | CONFIG_VM_EVENT_COUNTERS=y |
| 97 | CONFIG_SLUB_DEBUG=y | 102 | CONFIG_SLUB_DEBUG=y |
| 98 | CONFIG_COMPAT_BRK=y | 103 | CONFIG_COMPAT_BRK=y |
| @@ -164,7 +169,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" | |||
| 164 | # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set | 169 | # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set |
| 165 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set | 170 | # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set |
| 166 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set | 171 | # CONFIG_MUTEX_SPIN_ON_OWNER is not set |
| 167 | # CONFIG_FREEZER is not set | 172 | CONFIG_FREEZER=y |
| 168 | 173 | ||
| 169 | # | 174 | # |
| 170 | # System Type | 175 | # System Type |
| @@ -175,6 +180,7 @@ CONFIG_MMU=y | |||
| 175 | # CONFIG_ARCH_REALVIEW is not set | 180 | # CONFIG_ARCH_REALVIEW is not set |
| 176 | # CONFIG_ARCH_VERSATILE is not set | 181 | # CONFIG_ARCH_VERSATILE is not set |
| 177 | # CONFIG_ARCH_AT91 is not set | 182 | # CONFIG_ARCH_AT91 is not set |
| 183 | # CONFIG_ARCH_BCMRING is not set | ||
| 178 | # CONFIG_ARCH_CLPS711X is not set | 184 | # CONFIG_ARCH_CLPS711X is not set |
| 179 | # CONFIG_ARCH_GEMINI is not set | 185 | # CONFIG_ARCH_GEMINI is not set |
| 180 | # CONFIG_ARCH_EBSA110 is not set | 186 | # CONFIG_ARCH_EBSA110 is not set |
| @@ -184,7 +190,6 @@ CONFIG_MMU=y | |||
| 184 | # CONFIG_ARCH_STMP3XXX is not set | 190 | # CONFIG_ARCH_STMP3XXX is not set |
| 185 | # CONFIG_ARCH_NETX is not set | 191 | # CONFIG_ARCH_NETX is not set |
| 186 | # CONFIG_ARCH_H720X is not set | 192 | # CONFIG_ARCH_H720X is not set |
| 187 | # CONFIG_ARCH_NOMADIK is not set | ||
| 188 | # CONFIG_ARCH_IOP13XX is not set | 193 | # CONFIG_ARCH_IOP13XX is not set |
| 189 | # CONFIG_ARCH_IOP32X is not set | 194 | # CONFIG_ARCH_IOP32X is not set |
| 190 | # CONFIG_ARCH_IOP33X is not set | 195 | # CONFIG_ARCH_IOP33X is not set |
| @@ -201,30 +206,44 @@ CONFIG_MMU=y | |||
| 201 | # CONFIG_ARCH_KS8695 is not set | 206 | # CONFIG_ARCH_KS8695 is not set |
| 202 | # CONFIG_ARCH_NS9XXX is not set | 207 | # CONFIG_ARCH_NS9XXX is not set |
| 203 | # CONFIG_ARCH_W90X900 is not set | 208 | # CONFIG_ARCH_W90X900 is not set |
| 209 | # CONFIG_ARCH_NUC93X is not set | ||
| 204 | # CONFIG_ARCH_PNX4008 is not set | 210 | # CONFIG_ARCH_PNX4008 is not set |
| 205 | # CONFIG_ARCH_PXA is not set | 211 | # CONFIG_ARCH_PXA is not set |
| 206 | # CONFIG_ARCH_MSM is not set | 212 | # CONFIG_ARCH_MSM is not set |
| 213 | # CONFIG_ARCH_SHMOBILE is not set | ||
| 207 | # CONFIG_ARCH_RPC is not set | 214 | # CONFIG_ARCH_RPC is not set |
| 208 | # CONFIG_ARCH_SA1100 is not set | 215 | # CONFIG_ARCH_SA1100 is not set |
| 209 | # CONFIG_ARCH_S3C2410 is not set | 216 | # CONFIG_ARCH_S3C2410 is not set |
| 210 | CONFIG_ARCH_S3C64XX=y | 217 | CONFIG_ARCH_S3C64XX=y |
| 211 | # CONFIG_ARCH_S5P6440 is not set | 218 | # CONFIG_ARCH_S5P6440 is not set |
| 219 | # CONFIG_ARCH_S5P6442 is not set | ||
| 212 | # CONFIG_ARCH_S5PC1XX is not set | 220 | # CONFIG_ARCH_S5PC1XX is not set |
| 221 | # CONFIG_ARCH_S5PV210 is not set | ||
| 213 | # CONFIG_ARCH_SHARK is not set | 222 | # CONFIG_ARCH_SHARK is not set |
| 214 | # CONFIG_ARCH_LH7A40X is not set | 223 | # CONFIG_ARCH_LH7A40X is not set |
| 215 | # CONFIG_ARCH_U300 is not set | 224 | # CONFIG_ARCH_U300 is not set |
| 225 | # CONFIG_ARCH_U8500 is not set | ||
| 226 | # CONFIG_ARCH_NOMADIK is not set | ||
| 216 | # CONFIG_ARCH_DAVINCI is not set | 227 | # CONFIG_ARCH_DAVINCI is not set |
| 217 | # CONFIG_ARCH_OMAP is not set | 228 | # CONFIG_ARCH_OMAP is not set |
| 218 | # CONFIG_ARCH_BCMRING is not set | ||
| 219 | # CONFIG_ARCH_U8500 is not set | ||
| 220 | CONFIG_PLAT_SAMSUNG=y | 229 | CONFIG_PLAT_SAMSUNG=y |
| 230 | |||
| 231 | # | ||
| 232 | # Boot options | ||
| 233 | # | ||
| 234 | CONFIG_S3C_BOOT_ERROR_RESET=y | ||
| 235 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
| 236 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
| 221 | CONFIG_SAMSUNG_CLKSRC=y | 237 | CONFIG_SAMSUNG_CLKSRC=y |
| 222 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y | 238 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y |
| 223 | CONFIG_SAMSUNG_IRQ_UART=y | 239 | CONFIG_SAMSUNG_IRQ_UART=y |
| 240 | CONFIG_SAMSUNG_GPIOLIB_4BIT=y | ||
| 224 | CONFIG_S3C_GPIO_CFG_S3C24XX=y | 241 | CONFIG_S3C_GPIO_CFG_S3C24XX=y |
| 225 | CONFIG_S3C_GPIO_CFG_S3C64XX=y | 242 | CONFIG_S3C_GPIO_CFG_S3C64XX=y |
| 226 | CONFIG_S3C_GPIO_PULL_UPDOWN=y | 243 | CONFIG_S3C_GPIO_PULL_UPDOWN=y |
| 227 | CONFIG_SAMSUNG_GPIO_EXTRA=0 | 244 | CONFIG_SAMSUNG_GPIO_EXTRA=0 |
| 245 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 246 | CONFIG_S3C_GPIO_TRACK=y | ||
| 228 | # CONFIG_S3C_ADC is not set | 247 | # CONFIG_S3C_ADC is not set |
| 229 | CONFIG_S3C_DEV_HSMMC=y | 248 | CONFIG_S3C_DEV_HSMMC=y |
| 230 | CONFIG_S3C_DEV_HSMMC1=y | 249 | CONFIG_S3C_DEV_HSMMC1=y |
| @@ -233,36 +252,29 @@ CONFIG_S3C_DEV_FB=y | |||
| 233 | CONFIG_S3C_DEV_USB_HOST=y | 252 | CONFIG_S3C_DEV_USB_HOST=y |
| 234 | CONFIG_S3C_DEV_USB_HSOTG=y | 253 | CONFIG_S3C_DEV_USB_HSOTG=y |
| 235 | CONFIG_S3C_DEV_NAND=y | 254 | CONFIG_S3C_DEV_NAND=y |
| 255 | CONFIG_S3C_DMA=y | ||
| 256 | |||
| 257 | # | ||
| 258 | # Power management | ||
| 259 | # | ||
| 260 | # CONFIG_SAMSUNG_PM_DEBUG is not set | ||
| 261 | # CONFIG_S3C_PM_DEBUG_LED_SMDK is not set | ||
| 262 | # CONFIG_SAMSUNG_PM_CHECK is not set | ||
| 236 | CONFIG_PLAT_S3C64XX=y | 263 | CONFIG_PLAT_S3C64XX=y |
| 237 | CONFIG_CPU_S3C6400_INIT=y | 264 | CONFIG_CPU_S3C6410=y |
| 238 | CONFIG_CPU_S3C6400_CLOCK=y | 265 | CONFIG_S3C64XX_DMA=y |
| 239 | # CONFIG_S3C64XX_DMA is not set | 266 | CONFIG_S3C64XX_SETUP_SDHCI=y |
| 240 | CONFIG_S3C64XX_SETUP_I2C0=y | 267 | CONFIG_S3C64XX_SETUP_I2C0=y |
| 241 | CONFIG_S3C64XX_SETUP_I2C1=y | 268 | CONFIG_S3C64XX_SETUP_I2C1=y |
| 242 | CONFIG_S3C64XX_SETUP_FB_24BPP=y | 269 | CONFIG_S3C64XX_SETUP_FB_24BPP=y |
| 243 | CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y | 270 | CONFIG_S3C64XX_SETUP_SDHCI_GPIO=y |
| 244 | CONFIG_PLAT_S3C=y | ||
| 245 | |||
| 246 | # | ||
| 247 | # Boot options | ||
| 248 | # | ||
| 249 | CONFIG_S3C_BOOT_ERROR_RESET=y | ||
| 250 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
| 251 | |||
| 252 | # | ||
| 253 | # Power management | ||
| 254 | # | ||
| 255 | CONFIG_S3C_LOWLEVEL_UART_PORT=0 | ||
| 256 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 257 | CONFIG_S3C_GPIO_TRACK=y | ||
| 258 | # CONFIG_MACH_SMDK6400 is not set | 271 | # CONFIG_MACH_SMDK6400 is not set |
| 259 | CONFIG_CPU_S3C6410=y | ||
| 260 | CONFIG_S3C6410_SETUP_SDHCI=y | ||
| 261 | # CONFIG_MACH_ANW6410 is not set | 272 | # CONFIG_MACH_ANW6410 is not set |
| 262 | CONFIG_MACH_SMDK6410=y | 273 | CONFIG_MACH_SMDK6410=y |
| 263 | CONFIG_SMDK6410_SD_CH0=y | 274 | CONFIG_SMDK6410_SD_CH0=y |
| 264 | # CONFIG_SMDK6410_SD_CH1 is not set | 275 | # CONFIG_SMDK6410_SD_CH1 is not set |
| 265 | # CONFIG_SMDK6410_WM1190_EV1 is not set | 276 | # CONFIG_SMDK6410_WM1190_EV1 is not set |
| 277 | # CONFIG_SMDK6410_WM1192_EV1 is not set | ||
| 266 | # CONFIG_MACH_NCP is not set | 278 | # CONFIG_MACH_NCP is not set |
| 267 | # CONFIG_MACH_HMT is not set | 279 | # CONFIG_MACH_HMT is not set |
| 268 | 280 | ||
| @@ -290,6 +302,7 @@ CONFIG_ARM_THUMB=y | |||
| 290 | # CONFIG_CPU_DCACHE_DISABLE is not set | 302 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 291 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 303 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 292 | CONFIG_ARM_L1_CACHE_SHIFT=5 | 304 | CONFIG_ARM_L1_CACHE_SHIFT=5 |
| 305 | CONFIG_CPU_HAS_PMU=y | ||
| 293 | # CONFIG_ARM_ERRATA_411920 is not set | 306 | # CONFIG_ARM_ERRATA_411920 is not set |
| 294 | CONFIG_ARM_VIC=y | 307 | CONFIG_ARM_VIC=y |
| 295 | CONFIG_ARM_VIC_NR=2 | 308 | CONFIG_ARM_VIC_NR=2 |
| @@ -371,7 +384,14 @@ CONFIG_HAVE_AOUT=y | |||
| 371 | # | 384 | # |
| 372 | # Power management options | 385 | # Power management options |
| 373 | # | 386 | # |
| 374 | # CONFIG_PM is not set | 387 | CONFIG_PM=y |
| 388 | # CONFIG_PM_DEBUG is not set | ||
| 389 | CONFIG_PM_SLEEP=y | ||
| 390 | CONFIG_SUSPEND=y | ||
| 391 | CONFIG_SUSPEND_FREEZER=y | ||
| 392 | # CONFIG_APM_EMULATION is not set | ||
| 393 | # CONFIG_PM_RUNTIME is not set | ||
| 394 | CONFIG_PM_OPS=y | ||
| 375 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 395 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 376 | # CONFIG_NET is not set | 396 | # CONFIG_NET is not set |
| 377 | 397 | ||
| @@ -392,7 +412,88 @@ CONFIG_EXTRA_FIRMWARE="" | |||
| 392 | # CONFIG_DEBUG_DRIVER is not set | 412 | # CONFIG_DEBUG_DRIVER is not set |
| 393 | # CONFIG_DEBUG_DEVRES is not set | 413 | # CONFIG_DEBUG_DEVRES is not set |
| 394 | # CONFIG_SYS_HYPERVISOR is not set | 414 | # CONFIG_SYS_HYPERVISOR is not set |
| 395 | # CONFIG_MTD is not set | 415 | CONFIG_MTD=y |
| 416 | # CONFIG_MTD_DEBUG is not set | ||
| 417 | # CONFIG_MTD_TESTS is not set | ||
| 418 | # CONFIG_MTD_CONCAT is not set | ||
| 419 | # CONFIG_MTD_PARTITIONS is not set | ||
| 420 | |||
| 421 | # | ||
| 422 | # User Modules And Translation Layers | ||
| 423 | # | ||
| 424 | # CONFIG_MTD_CHAR is not set | ||
| 425 | # CONFIG_MTD_BLKDEVS is not set | ||
| 426 | # CONFIG_MTD_BLOCK is not set | ||
| 427 | # CONFIG_MTD_BLOCK_RO is not set | ||
| 428 | # CONFIG_FTL is not set | ||
| 429 | # CONFIG_NFTL is not set | ||
| 430 | # CONFIG_INFTL is not set | ||
| 431 | # CONFIG_RFD_FTL is not set | ||
| 432 | # CONFIG_SSFDC is not set | ||
| 433 | # CONFIG_MTD_OOPS is not set | ||
| 434 | |||
| 435 | # | ||
| 436 | # RAM/ROM/Flash chip drivers | ||
| 437 | # | ||
| 438 | # CONFIG_MTD_CFI is not set | ||
| 439 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 440 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 441 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 442 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 443 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 444 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 445 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 446 | CONFIG_MTD_CFI_I1=y | ||
| 447 | CONFIG_MTD_CFI_I2=y | ||
| 448 | # CONFIG_MTD_CFI_I4 is not set | ||
| 449 | # CONFIG_MTD_CFI_I8 is not set | ||
| 450 | # CONFIG_MTD_RAM is not set | ||
| 451 | # CONFIG_MTD_ROM is not set | ||
| 452 | # CONFIG_MTD_ABSENT is not set | ||
| 453 | |||
| 454 | # | ||
| 455 | # Mapping drivers for chip access | ||
| 456 | # | ||
| 457 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 458 | # CONFIG_MTD_PLATRAM is not set | ||
| 459 | |||
| 460 | # | ||
| 461 | # Self-contained MTD device drivers | ||
| 462 | # | ||
| 463 | # CONFIG_MTD_SLRAM is not set | ||
| 464 | # CONFIG_MTD_PHRAM is not set | ||
| 465 | # CONFIG_MTD_MTDRAM is not set | ||
| 466 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 467 | |||
| 468 | # | ||
| 469 | # Disk-On-Chip Device Drivers | ||
| 470 | # | ||
| 471 | # CONFIG_MTD_DOC2000 is not set | ||
| 472 | # CONFIG_MTD_DOC2001 is not set | ||
| 473 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 474 | CONFIG_MTD_NAND=y | ||
| 475 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 476 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 477 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 478 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 479 | CONFIG_MTD_NAND_IDS=y | ||
| 480 | CONFIG_MTD_NAND_S3C2410=y | ||
| 481 | # CONFIG_MTD_NAND_S3C2410_DEBUG is not set | ||
| 482 | # CONFIG_MTD_NAND_S3C2410_HWECC is not set | ||
| 483 | # CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set | ||
| 484 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 485 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 486 | # CONFIG_MTD_ONENAND is not set | ||
| 487 | |||
| 488 | # | ||
| 489 | # LPDDR flash memory drivers | ||
| 490 | # | ||
| 491 | # CONFIG_MTD_LPDDR is not set | ||
| 492 | |||
| 493 | # | ||
| 494 | # UBI - Unsorted block images | ||
| 495 | # | ||
| 496 | # CONFIG_MTD_UBI is not set | ||
| 396 | # CONFIG_PARPORT is not set | 497 | # CONFIG_PARPORT is not set |
| 397 | CONFIG_BLK_DEV=y | 498 | CONFIG_BLK_DEV=y |
| 398 | # CONFIG_BLK_DEV_COW_COMMON is not set | 499 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| @@ -413,6 +514,7 @@ CONFIG_MISC_DEVICES=y | |||
| 413 | # CONFIG_ICS932S401 is not set | 514 | # CONFIG_ICS932S401 is not set |
| 414 | # CONFIG_ENCLOSURE_SERVICES is not set | 515 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 415 | # CONFIG_ISL29003 is not set | 516 | # CONFIG_ISL29003 is not set |
| 517 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 416 | # CONFIG_DS1682 is not set | 518 | # CONFIG_DS1682 is not set |
| 417 | # CONFIG_C2PORT is not set | 519 | # CONFIG_C2PORT is not set |
| 418 | 520 | ||
| @@ -430,6 +532,7 @@ CONFIG_HAVE_IDE=y | |||
| 430 | # | 532 | # |
| 431 | # SCSI device support | 533 | # SCSI device support |
| 432 | # | 534 | # |
| 535 | CONFIG_SCSI_MOD=y | ||
| 433 | # CONFIG_RAID_ATTRS is not set | 536 | # CONFIG_RAID_ATTRS is not set |
| 434 | # CONFIG_SCSI is not set | 537 | # CONFIG_SCSI is not set |
| 435 | # CONFIG_SCSI_DMA is not set | 538 | # CONFIG_SCSI_DMA is not set |
| @@ -527,12 +630,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | |||
| 527 | # Non-8250 serial port support | 630 | # Non-8250 serial port support |
| 528 | # | 631 | # |
| 529 | CONFIG_SERIAL_SAMSUNG=y | 632 | CONFIG_SERIAL_SAMSUNG=y |
| 633 | CONFIG_SERIAL_SAMSUNG_UARTS_4=y | ||
| 530 | CONFIG_SERIAL_SAMSUNG_UARTS=4 | 634 | CONFIG_SERIAL_SAMSUNG_UARTS=4 |
| 531 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set | 635 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set |
| 532 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | 636 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y |
| 533 | CONFIG_SERIAL_S3C6400=y | 637 | CONFIG_SERIAL_S3C6400=y |
| 534 | CONFIG_SERIAL_CORE=y | 638 | CONFIG_SERIAL_CORE=y |
| 535 | CONFIG_SERIAL_CORE_CONSOLE=y | 639 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 640 | # CONFIG_SERIAL_TIMBERDALE is not set | ||
| 536 | CONFIG_UNIX98_PTYS=y | 641 | CONFIG_UNIX98_PTYS=y |
| 537 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 642 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
| 538 | CONFIG_LEGACY_PTYS=y | 643 | CONFIG_LEGACY_PTYS=y |
| @@ -561,6 +666,7 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 561 | # CONFIG_I2C_OCORES is not set | 666 | # CONFIG_I2C_OCORES is not set |
| 562 | CONFIG_I2C_S3C2410=y | 667 | CONFIG_I2C_S3C2410=y |
| 563 | # CONFIG_I2C_SIMTEC is not set | 668 | # CONFIG_I2C_SIMTEC is not set |
| 669 | # CONFIG_I2C_XILINX is not set | ||
| 564 | 670 | ||
| 565 | # | 671 | # |
| 566 | # External I2C/SMBus adapter drivers | 672 | # External I2C/SMBus adapter drivers |
| @@ -573,15 +679,9 @@ CONFIG_I2C_S3C2410=y | |||
| 573 | # | 679 | # |
| 574 | # CONFIG_I2C_PCA_PLATFORM is not set | 680 | # CONFIG_I2C_PCA_PLATFORM is not set |
| 575 | # CONFIG_I2C_STUB is not set | 681 | # CONFIG_I2C_STUB is not set |
| 576 | |||
| 577 | # | ||
| 578 | # Miscellaneous I2C Chip support | ||
| 579 | # | ||
| 580 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 581 | # CONFIG_I2C_DEBUG_CORE is not set | 682 | # CONFIG_I2C_DEBUG_CORE is not set |
| 582 | # CONFIG_I2C_DEBUG_ALGO is not set | 683 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 583 | # CONFIG_I2C_DEBUG_BUS is not set | 684 | # CONFIG_I2C_DEBUG_BUS is not set |
| 584 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 585 | # CONFIG_SPI is not set | 685 | # CONFIG_SPI is not set |
| 586 | 686 | ||
| 587 | # | 687 | # |
| @@ -596,10 +696,12 @@ CONFIG_GPIOLIB=y | |||
| 596 | # | 696 | # |
| 597 | # Memory mapped GPIO expanders: | 697 | # Memory mapped GPIO expanders: |
| 598 | # | 698 | # |
| 699 | # CONFIG_GPIO_IT8761E is not set | ||
| 599 | 700 | ||
| 600 | # | 701 | # |
| 601 | # I2C GPIO expanders: | 702 | # I2C GPIO expanders: |
| 602 | # | 703 | # |
| 704 | # CONFIG_GPIO_MAX7300 is not set | ||
| 603 | # CONFIG_GPIO_MAX732X is not set | 705 | # CONFIG_GPIO_MAX732X is not set |
| 604 | # CONFIG_GPIO_PCA953X is not set | 706 | # CONFIG_GPIO_PCA953X is not set |
| 605 | # CONFIG_GPIO_PCF857X is not set | 707 | # CONFIG_GPIO_PCF857X is not set |
| @@ -633,10 +735,11 @@ CONFIG_HWMON=y | |||
| 633 | # CONFIG_SENSORS_ADM1029 is not set | 735 | # CONFIG_SENSORS_ADM1029 is not set |
| 634 | # CONFIG_SENSORS_ADM1031 is not set | 736 | # CONFIG_SENSORS_ADM1031 is not set |
| 635 | # CONFIG_SENSORS_ADM9240 is not set | 737 | # CONFIG_SENSORS_ADM9240 is not set |
| 738 | # CONFIG_SENSORS_ADT7411 is not set | ||
| 636 | # CONFIG_SENSORS_ADT7462 is not set | 739 | # CONFIG_SENSORS_ADT7462 is not set |
| 637 | # CONFIG_SENSORS_ADT7470 is not set | 740 | # CONFIG_SENSORS_ADT7470 is not set |
| 638 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 639 | # CONFIG_SENSORS_ADT7475 is not set | 741 | # CONFIG_SENSORS_ADT7475 is not set |
| 742 | # CONFIG_SENSORS_ASC7621 is not set | ||
| 640 | # CONFIG_SENSORS_ATXP1 is not set | 743 | # CONFIG_SENSORS_ATXP1 is not set |
| 641 | # CONFIG_SENSORS_DS1621 is not set | 744 | # CONFIG_SENSORS_DS1621 is not set |
| 642 | # CONFIG_SENSORS_F71805F is not set | 745 | # CONFIG_SENSORS_F71805F is not set |
| @@ -699,10 +802,13 @@ CONFIG_SSB_POSSIBLE=y | |||
| 699 | # Multifunction device drivers | 802 | # Multifunction device drivers |
| 700 | # | 803 | # |
| 701 | # CONFIG_MFD_CORE is not set | 804 | # CONFIG_MFD_CORE is not set |
| 805 | # CONFIG_MFD_88PM860X is not set | ||
| 702 | # CONFIG_MFD_SM501 is not set | 806 | # CONFIG_MFD_SM501 is not set |
| 703 | # CONFIG_MFD_ASIC3 is not set | 807 | # CONFIG_MFD_ASIC3 is not set |
| 704 | # CONFIG_HTC_EGPIO is not set | 808 | # CONFIG_HTC_EGPIO is not set |
| 705 | # CONFIG_HTC_PASIC3 is not set | 809 | # CONFIG_HTC_PASIC3 is not set |
| 810 | # CONFIG_HTC_I2CPLD is not set | ||
| 811 | # CONFIG_UCB1400_CORE is not set | ||
| 706 | # CONFIG_TPS65010 is not set | 812 | # CONFIG_TPS65010 is not set |
| 707 | # CONFIG_TWL4030_CORE is not set | 813 | # CONFIG_TWL4030_CORE is not set |
| 708 | # CONFIG_MFD_TMIO is not set | 814 | # CONFIG_MFD_TMIO is not set |
| @@ -711,12 +817,13 @@ CONFIG_SSB_POSSIBLE=y | |||
| 711 | # CONFIG_MFD_TC6393XB is not set | 817 | # CONFIG_MFD_TC6393XB is not set |
| 712 | # CONFIG_PMIC_DA903X is not set | 818 | # CONFIG_PMIC_DA903X is not set |
| 713 | # CONFIG_PMIC_ADP5520 is not set | 819 | # CONFIG_PMIC_ADP5520 is not set |
| 820 | # CONFIG_MFD_MAX8925 is not set | ||
| 714 | # CONFIG_MFD_WM8400 is not set | 821 | # CONFIG_MFD_WM8400 is not set |
| 715 | # CONFIG_MFD_WM831X is not set | 822 | # CONFIG_MFD_WM831X is not set |
| 716 | # CONFIG_MFD_WM8350_I2C is not set | 823 | # CONFIG_MFD_WM8350_I2C is not set |
| 824 | # CONFIG_MFD_WM8994 is not set | ||
| 717 | # CONFIG_MFD_PCF50633 is not set | 825 | # CONFIG_MFD_PCF50633 is not set |
| 718 | # CONFIG_AB3100_CORE is not set | 826 | # CONFIG_AB3100_CORE is not set |
| 719 | # CONFIG_MFD_88PM8607 is not set | ||
| 720 | # CONFIG_REGULATOR is not set | 827 | # CONFIG_REGULATOR is not set |
| 721 | # CONFIG_MEDIA_SUPPORT is not set | 828 | # CONFIG_MEDIA_SUPPORT is not set |
| 722 | 829 | ||
| @@ -738,7 +845,44 @@ CONFIG_SSB_POSSIBLE=y | |||
| 738 | # | 845 | # |
| 739 | # CONFIG_VGA_CONSOLE is not set | 846 | # CONFIG_VGA_CONSOLE is not set |
| 740 | CONFIG_DUMMY_CONSOLE=y | 847 | CONFIG_DUMMY_CONSOLE=y |
| 741 | # CONFIG_SOUND is not set | 848 | CONFIG_SOUND=y |
| 849 | CONFIG_SOUND_OSS_CORE=y | ||
| 850 | CONFIG_SOUND_OSS_CORE_PRECLAIM=y | ||
| 851 | CONFIG_SND=m | ||
| 852 | CONFIG_SND_TIMER=m | ||
| 853 | CONFIG_SND_PCM=m | ||
| 854 | CONFIG_SND_JACK=y | ||
| 855 | # CONFIG_SND_SEQUENCER is not set | ||
| 856 | CONFIG_SND_OSSEMUL=y | ||
| 857 | CONFIG_SND_MIXER_OSS=m | ||
| 858 | CONFIG_SND_PCM_OSS=m | ||
| 859 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 860 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 861 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 862 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 863 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 864 | # CONFIG_SND_DEBUG is not set | ||
| 865 | # CONFIG_SND_RAWMIDI_SEQ is not set | ||
| 866 | # CONFIG_SND_OPL3_LIB_SEQ is not set | ||
| 867 | # CONFIG_SND_OPL4_LIB_SEQ is not set | ||
| 868 | # CONFIG_SND_SBAWE_SEQ is not set | ||
| 869 | # CONFIG_SND_EMU10K1_SEQ is not set | ||
| 870 | CONFIG_SND_DRIVERS=y | ||
| 871 | # CONFIG_SND_DUMMY is not set | ||
| 872 | # CONFIG_SND_MTPAV is not set | ||
| 873 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 874 | # CONFIG_SND_MPU401 is not set | ||
| 875 | CONFIG_SND_ARM=y | ||
| 876 | CONFIG_SND_SOC=m | ||
| 877 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 878 | CONFIG_SND_S3C24XX_SOC=m | ||
| 879 | CONFIG_SND_S3C_SOC_AC97=m | ||
| 880 | CONFIG_SND_SOC_SMDK_WM9713=m | ||
| 881 | CONFIG_SND_SOC_I2C_AND_SPI=m | ||
| 882 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 883 | CONFIG_SND_SOC_WM9713=m | ||
| 884 | # CONFIG_SOUND_PRIME is not set | ||
| 885 | CONFIG_AC97_BUS=m | ||
| 742 | CONFIG_HID_SUPPORT=y | 886 | CONFIG_HID_SUPPORT=y |
| 743 | CONFIG_HID=y | 887 | CONFIG_HID=y |
| 744 | # CONFIG_HIDRAW is not set | 888 | # CONFIG_HIDRAW is not set |
| @@ -784,8 +928,6 @@ CONFIG_MMC_SDHCI=y | |||
| 784 | # CONFIG_MMC_SDHCI_PLTFM is not set | 928 | # CONFIG_MMC_SDHCI_PLTFM is not set |
| 785 | CONFIG_MMC_SDHCI_S3C=y | 929 | CONFIG_MMC_SDHCI_S3C=y |
| 786 | # CONFIG_MMC_SDHCI_S3C_DMA is not set | 930 | # CONFIG_MMC_SDHCI_S3C_DMA is not set |
| 787 | # CONFIG_MMC_AT91 is not set | ||
| 788 | # CONFIG_MMC_ATMELMCI is not set | ||
| 789 | # CONFIG_MEMSTICK is not set | 931 | # CONFIG_MEMSTICK is not set |
| 790 | # CONFIG_NEW_LEDS is not set | 932 | # CONFIG_NEW_LEDS is not set |
| 791 | # CONFIG_ACCESSIBILITY is not set | 933 | # CONFIG_ACCESSIBILITY is not set |
| @@ -869,6 +1011,8 @@ CONFIG_MISC_FILESYSTEMS=y | |||
| 869 | # CONFIG_BEFS_FS is not set | 1011 | # CONFIG_BEFS_FS is not set |
| 870 | # CONFIG_BFS_FS is not set | 1012 | # CONFIG_BFS_FS is not set |
| 871 | # CONFIG_EFS_FS is not set | 1013 | # CONFIG_EFS_FS is not set |
| 1014 | # CONFIG_JFFS2_FS is not set | ||
| 1015 | # CONFIG_LOGFS is not set | ||
| 872 | CONFIG_CRAMFS=y | 1016 | CONFIG_CRAMFS=y |
| 873 | # CONFIG_SQUASHFS is not set | 1017 | # CONFIG_SQUASHFS is not set |
| 874 | # CONFIG_VXFS_FS is not set | 1018 | # CONFIG_VXFS_FS is not set |
diff --git a/arch/arm/configs/s5p6440_defconfig b/arch/arm/configs/s5p6440_defconfig index 279a15e53114..619bfab3ab39 100644 --- a/arch/arm/configs/s5p6440_defconfig +++ b/arch/arm/configs/s5p6440_defconfig | |||
| @@ -1,11 +1,12 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.33-rc2 | 3 | # Linux kernel version: 2.6.34 |
| 4 | # Sat Jan 9 16:33:55 2010 | 4 | # Sat May 22 03:18:18 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_HAVE_PROC_CPU=y | ||
| 9 | CONFIG_NO_IOPORT=y | 10 | CONFIG_NO_IOPORT=y |
| 10 | CONFIG_GENERIC_HARDIRQS=y | 11 | CONFIG_GENERIC_HARDIRQS=y |
| 11 | CONFIG_STACKTRACE_SUPPORT=y | 12 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y | |||
| 17 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 18 | CONFIG_GENERIC_HWEIGHT=y | 19 | CONFIG_GENERIC_HWEIGHT=y |
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 21 | CONFIG_NEED_DMA_MAP_STATE=y | ||
| 20 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 21 | CONFIG_VECTORS_BASE=0xffff0000 | 23 | CONFIG_VECTORS_BASE=0xffff0000 |
| 22 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 24 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| @@ -30,6 +32,12 @@ CONFIG_BROKEN_ON_SMP=y | |||
| 30 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 32 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 31 | CONFIG_LOCALVERSION="" | 33 | CONFIG_LOCALVERSION="" |
| 32 | CONFIG_LOCALVERSION_AUTO=y | 34 | CONFIG_LOCALVERSION_AUTO=y |
| 35 | CONFIG_HAVE_KERNEL_GZIP=y | ||
| 36 | CONFIG_HAVE_KERNEL_LZO=y | ||
| 37 | CONFIG_KERNEL_GZIP=y | ||
| 38 | # CONFIG_KERNEL_BZIP2 is not set | ||
| 39 | # CONFIG_KERNEL_LZMA is not set | ||
| 40 | # CONFIG_KERNEL_LZO is not set | ||
| 33 | CONFIG_SWAP=y | 41 | CONFIG_SWAP=y |
| 34 | # CONFIG_SYSVIPC is not set | 42 | # CONFIG_SYSVIPC is not set |
| 35 | # CONFIG_BSD_PROCESS_ACCT is not set | 43 | # CONFIG_BSD_PROCESS_ACCT is not set |
| @@ -46,7 +54,6 @@ CONFIG_RCU_FANOUT=32 | |||
| 46 | # CONFIG_TREE_RCU_TRACE is not set | 54 | # CONFIG_TREE_RCU_TRACE is not set |
| 47 | # CONFIG_IKCONFIG is not set | 55 | # CONFIG_IKCONFIG is not set |
| 48 | CONFIG_LOG_BUF_SHIFT=17 | 56 | CONFIG_LOG_BUF_SHIFT=17 |
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | 57 | # CONFIG_CGROUPS is not set |
| 51 | CONFIG_SYSFS_DEPRECATED=y | 58 | CONFIG_SYSFS_DEPRECATED=y |
| 52 | CONFIG_SYSFS_DEPRECATED_V2=y | 59 | CONFIG_SYSFS_DEPRECATED_V2=y |
| @@ -60,6 +67,7 @@ CONFIG_INITRAMFS_SOURCE="" | |||
| 60 | CONFIG_RD_GZIP=y | 67 | CONFIG_RD_GZIP=y |
| 61 | CONFIG_RD_BZIP2=y | 68 | CONFIG_RD_BZIP2=y |
| 62 | CONFIG_RD_LZMA=y | 69 | CONFIG_RD_LZMA=y |
| 70 | CONFIG_RD_LZO=y | ||
| 63 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 71 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 64 | CONFIG_SYSCTL=y | 72 | CONFIG_SYSCTL=y |
| 65 | CONFIG_ANON_INODES=y | 73 | CONFIG_ANON_INODES=y |
| @@ -81,10 +89,14 @@ CONFIG_TIMERFD=y | |||
| 81 | CONFIG_EVENTFD=y | 89 | CONFIG_EVENTFD=y |
| 82 | CONFIG_SHMEM=y | 90 | CONFIG_SHMEM=y |
| 83 | CONFIG_AIO=y | 91 | CONFIG_AIO=y |
| 92 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 93 | CONFIG_PERF_USE_VMALLOC=y | ||
| 84 | 94 | ||
| 85 | # | 95 | # |
| 86 | # Kernel Performance Events And Counters | 96 | # Kernel Performance Events And Counters |
| 87 | # | 97 | # |
| 98 | # CONFIG_PERF_EVENTS is not set | ||
| 99 | # CONFIG_PERF_COUNTERS is not set | ||
| 88 | CONFIG_VM_EVENT_COUNTERS=y | 100 | CONFIG_VM_EVENT_COUNTERS=y |
| 89 | CONFIG_SLUB_DEBUG=y | 101 | CONFIG_SLUB_DEBUG=y |
| 90 | CONFIG_COMPAT_BRK=y | 102 | CONFIG_COMPAT_BRK=y |
| @@ -167,6 +179,7 @@ CONFIG_MMU=y | |||
| 167 | # CONFIG_ARCH_REALVIEW is not set | 179 | # CONFIG_ARCH_REALVIEW is not set |
| 168 | # CONFIG_ARCH_VERSATILE is not set | 180 | # CONFIG_ARCH_VERSATILE is not set |
| 169 | # CONFIG_ARCH_AT91 is not set | 181 | # CONFIG_ARCH_AT91 is not set |
| 182 | # CONFIG_ARCH_BCMRING is not set | ||
| 170 | # CONFIG_ARCH_CLPS711X is not set | 183 | # CONFIG_ARCH_CLPS711X is not set |
| 171 | # CONFIG_ARCH_GEMINI is not set | 184 | # CONFIG_ARCH_GEMINI is not set |
| 172 | # CONFIG_ARCH_EBSA110 is not set | 185 | # CONFIG_ARCH_EBSA110 is not set |
| @@ -176,7 +189,6 @@ CONFIG_MMU=y | |||
| 176 | # CONFIG_ARCH_STMP3XXX is not set | 189 | # CONFIG_ARCH_STMP3XXX is not set |
| 177 | # CONFIG_ARCH_NETX is not set | 190 | # CONFIG_ARCH_NETX is not set |
| 178 | # CONFIG_ARCH_H720X is not set | 191 | # CONFIG_ARCH_H720X is not set |
| 179 | # CONFIG_ARCH_NOMADIK is not set | ||
| 180 | # CONFIG_ARCH_IOP13XX is not set | 192 | # CONFIG_ARCH_IOP13XX is not set |
| 181 | # CONFIG_ARCH_IOP32X is not set | 193 | # CONFIG_ARCH_IOP32X is not set |
| 182 | # CONFIG_ARCH_IOP33X is not set | 194 | # CONFIG_ARCH_IOP33X is not set |
| @@ -193,44 +205,50 @@ CONFIG_MMU=y | |||
| 193 | # CONFIG_ARCH_KS8695 is not set | 205 | # CONFIG_ARCH_KS8695 is not set |
| 194 | # CONFIG_ARCH_NS9XXX is not set | 206 | # CONFIG_ARCH_NS9XXX is not set |
| 195 | # CONFIG_ARCH_W90X900 is not set | 207 | # CONFIG_ARCH_W90X900 is not set |
| 208 | # CONFIG_ARCH_NUC93X is not set | ||
| 196 | # CONFIG_ARCH_PNX4008 is not set | 209 | # CONFIG_ARCH_PNX4008 is not set |
| 197 | # CONFIG_ARCH_PXA is not set | 210 | # CONFIG_ARCH_PXA is not set |
| 198 | # CONFIG_ARCH_MSM is not set | 211 | # CONFIG_ARCH_MSM is not set |
| 212 | # CONFIG_ARCH_SHMOBILE is not set | ||
| 199 | # CONFIG_ARCH_RPC is not set | 213 | # CONFIG_ARCH_RPC is not set |
| 200 | # CONFIG_ARCH_SA1100 is not set | 214 | # CONFIG_ARCH_SA1100 is not set |
| 201 | # CONFIG_ARCH_S3C2410 is not set | 215 | # CONFIG_ARCH_S3C2410 is not set |
| 202 | # CONFIG_ARCH_S3C64XX is not set | 216 | # CONFIG_ARCH_S3C64XX is not set |
| 203 | CONFIG_ARCH_S5P6440=y | 217 | CONFIG_ARCH_S5P6440=y |
| 218 | # CONFIG_ARCH_S5P6442 is not set | ||
| 204 | # CONFIG_ARCH_S5PC1XX is not set | 219 | # CONFIG_ARCH_S5PC1XX is not set |
| 220 | # CONFIG_ARCH_S5PV210 is not set | ||
| 205 | # CONFIG_ARCH_SHARK is not set | 221 | # CONFIG_ARCH_SHARK is not set |
| 206 | # CONFIG_ARCH_LH7A40X is not set | 222 | # CONFIG_ARCH_LH7A40X is not set |
| 207 | # CONFIG_ARCH_U300 is not set | 223 | # CONFIG_ARCH_U300 is not set |
| 224 | # CONFIG_ARCH_U8500 is not set | ||
| 225 | # CONFIG_ARCH_NOMADIK is not set | ||
| 208 | # CONFIG_ARCH_DAVINCI is not set | 226 | # CONFIG_ARCH_DAVINCI is not set |
| 209 | # CONFIG_ARCH_OMAP is not set | 227 | # CONFIG_ARCH_OMAP is not set |
| 210 | # CONFIG_ARCH_BCMRING is not set | ||
| 211 | # CONFIG_ARCH_U8500 is not set | ||
| 212 | CONFIG_PLAT_SAMSUNG=y | 228 | CONFIG_PLAT_SAMSUNG=y |
| 213 | CONFIG_SAMSUNG_CLKSRC=y | ||
| 214 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y | ||
| 215 | CONFIG_SAMSUNG_IRQ_UART=y | ||
| 216 | CONFIG_SAMSUNG_GPIO_EXTRA=0 | ||
| 217 | CONFIG_PLAT_S3C=y | ||
| 218 | 229 | ||
| 219 | # | 230 | # |
| 220 | # Boot options | 231 | # Boot options |
| 221 | # | 232 | # |
| 222 | CONFIG_S3C_BOOT_ERROR_RESET=y | 233 | CONFIG_S3C_BOOT_ERROR_RESET=y |
| 223 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | 234 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y |
| 235 | CONFIG_S3C_LOWLEVEL_UART_PORT=1 | ||
| 236 | CONFIG_SAMSUNG_CLKSRC=y | ||
| 237 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y | ||
| 238 | CONFIG_SAMSUNG_IRQ_UART=y | ||
| 239 | CONFIG_SAMSUNG_GPIOLIB_4BIT=y | ||
| 240 | CONFIG_S3C_GPIO_CFG_S3C24XX=y | ||
| 241 | CONFIG_S3C_GPIO_CFG_S3C64XX=y | ||
| 242 | CONFIG_S3C_GPIO_PULL_UPDOWN=y | ||
| 243 | CONFIG_SAMSUNG_GPIO_EXTRA=0 | ||
| 244 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 245 | CONFIG_S3C_GPIO_TRACK=y | ||
| 246 | # CONFIG_S3C_ADC is not set | ||
| 224 | 247 | ||
| 225 | # | 248 | # |
| 226 | # Power management | 249 | # Power management |
| 227 | # | 250 | # |
| 228 | CONFIG_S3C_LOWLEVEL_UART_PORT=1 | ||
| 229 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 230 | CONFIG_S3C_GPIO_TRACK=y | ||
| 231 | CONFIG_PLAT_S5P=y | 251 | CONFIG_PLAT_S5P=y |
| 232 | CONFIG_CPU_S5P6440_INIT=y | ||
| 233 | CONFIG_CPU_S5P6440_CLOCK=y | ||
| 234 | CONFIG_CPU_S5P6440=y | 252 | CONFIG_CPU_S5P6440=y |
| 235 | CONFIG_MACH_SMDK6440=y | 253 | CONFIG_MACH_SMDK6440=y |
| 236 | 254 | ||
| @@ -258,6 +276,7 @@ CONFIG_ARM_THUMB=y | |||
| 258 | # CONFIG_CPU_DCACHE_DISABLE is not set | 276 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 259 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 277 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 260 | CONFIG_ARM_L1_CACHE_SHIFT=5 | 278 | CONFIG_ARM_L1_CACHE_SHIFT=5 |
| 279 | CONFIG_CPU_HAS_PMU=y | ||
| 261 | # CONFIG_ARM_ERRATA_411920 is not set | 280 | # CONFIG_ARM_ERRATA_411920 is not set |
| 262 | CONFIG_ARM_VIC=y | 281 | CONFIG_ARM_VIC=y |
| 263 | CONFIG_ARM_VIC_NR=2 | 282 | CONFIG_ARM_VIC_NR=2 |
| @@ -382,6 +401,7 @@ CONFIG_HAVE_IDE=y | |||
| 382 | # | 401 | # |
| 383 | # SCSI device support | 402 | # SCSI device support |
| 384 | # | 403 | # |
| 404 | CONFIG_SCSI_MOD=y | ||
| 385 | # CONFIG_RAID_ATTRS is not set | 405 | # CONFIG_RAID_ATTRS is not set |
| 386 | CONFIG_SCSI=y | 406 | CONFIG_SCSI=y |
| 387 | CONFIG_SCSI_DMA=y | 407 | CONFIG_SCSI_DMA=y |
| @@ -518,12 +538,14 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=3 | |||
| 518 | # Non-8250 serial port support | 538 | # Non-8250 serial port support |
| 519 | # | 539 | # |
| 520 | CONFIG_SERIAL_SAMSUNG=y | 540 | CONFIG_SERIAL_SAMSUNG=y |
| 541 | CONFIG_SERIAL_SAMSUNG_UARTS_4=y | ||
| 521 | CONFIG_SERIAL_SAMSUNG_UARTS=4 | 542 | CONFIG_SERIAL_SAMSUNG_UARTS=4 |
| 522 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set | 543 | # CONFIG_SERIAL_SAMSUNG_DEBUG is not set |
| 523 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | 544 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y |
| 524 | CONFIG_SERIAL_S5P6440=y | 545 | CONFIG_SERIAL_S3C6400=y |
| 525 | CONFIG_SERIAL_CORE=y | 546 | CONFIG_SERIAL_CORE=y |
| 526 | CONFIG_SERIAL_CORE_CONSOLE=y | 547 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 548 | # CONFIG_SERIAL_TIMBERDALE is not set | ||
| 527 | CONFIG_UNIX98_PTYS=y | 549 | CONFIG_UNIX98_PTYS=y |
| 528 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 550 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
| 529 | CONFIG_LEGACY_PTYS=y | 551 | CONFIG_LEGACY_PTYS=y |
| @@ -549,6 +571,7 @@ CONFIG_GPIOLIB=y | |||
| 549 | # | 571 | # |
| 550 | # Memory mapped GPIO expanders: | 572 | # Memory mapped GPIO expanders: |
| 551 | # | 573 | # |
| 574 | # CONFIG_GPIO_IT8761E is not set | ||
| 552 | 575 | ||
| 553 | # | 576 | # |
| 554 | # I2C GPIO expanders: | 577 | # I2C GPIO expanders: |
| @@ -704,6 +727,7 @@ CONFIG_MISC_FILESYSTEMS=y | |||
| 704 | # CONFIG_BEFS_FS is not set | 727 | # CONFIG_BEFS_FS is not set |
| 705 | # CONFIG_BFS_FS is not set | 728 | # CONFIG_BFS_FS is not set |
| 706 | # CONFIG_EFS_FS is not set | 729 | # CONFIG_EFS_FS is not set |
| 730 | # CONFIG_LOGFS is not set | ||
| 707 | CONFIG_CRAMFS=y | 731 | CONFIG_CRAMFS=y |
| 708 | # CONFIG_SQUASHFS is not set | 732 | # CONFIG_SQUASHFS is not set |
| 709 | # CONFIG_VXFS_FS is not set | 733 | # CONFIG_VXFS_FS is not set |
| @@ -962,8 +986,10 @@ CONFIG_CRC32=y | |||
| 962 | # CONFIG_CRC7 is not set | 986 | # CONFIG_CRC7 is not set |
| 963 | # CONFIG_LIBCRC32C is not set | 987 | # CONFIG_LIBCRC32C is not set |
| 964 | CONFIG_ZLIB_INFLATE=y | 988 | CONFIG_ZLIB_INFLATE=y |
| 989 | CONFIG_LZO_DECOMPRESS=y | ||
| 965 | CONFIG_DECOMPRESS_GZIP=y | 990 | CONFIG_DECOMPRESS_GZIP=y |
| 966 | CONFIG_DECOMPRESS_BZIP2=y | 991 | CONFIG_DECOMPRESS_BZIP2=y |
| 967 | CONFIG_DECOMPRESS_LZMA=y | 992 | CONFIG_DECOMPRESS_LZMA=y |
| 993 | CONFIG_DECOMPRESS_LZO=y | ||
| 968 | CONFIG_HAS_IOMEM=y | 994 | CONFIG_HAS_IOMEM=y |
| 969 | CONFIG_HAS_DMA=y | 995 | CONFIG_HAS_DMA=y |
diff --git a/arch/arm/configs/s5p6442_defconfig b/arch/arm/configs/s5p6442_defconfig index 74e20bfc0487..d7ea27509cf4 100644 --- a/arch/arm/configs/s5p6442_defconfig +++ b/arch/arm/configs/s5p6442_defconfig | |||
| @@ -1,11 +1,12 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.33-rc4 | 3 | # Linux kernel version: 2.6.34 |
| 4 | # Mon Jan 25 08:50:28 2010 | 4 | # Sat May 22 03:18:19 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_HAVE_PROC_CPU=y | ||
| 9 | CONFIG_NO_IOPORT=y | 10 | CONFIG_NO_IOPORT=y |
| 10 | CONFIG_GENERIC_HARDIRQS=y | 11 | CONFIG_GENERIC_HARDIRQS=y |
| 11 | CONFIG_STACKTRACE_SUPPORT=y | 12 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y | |||
| 17 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 18 | CONFIG_GENERIC_HWEIGHT=y | 19 | CONFIG_GENERIC_HWEIGHT=y |
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 21 | CONFIG_NEED_DMA_MAP_STATE=y | ||
| 20 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 21 | CONFIG_VECTORS_BASE=0xffff0000 | 23 | CONFIG_VECTORS_BASE=0xffff0000 |
| 22 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 24 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| @@ -52,7 +54,6 @@ CONFIG_RCU_FANOUT=32 | |||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | 54 | # CONFIG_TREE_RCU_TRACE is not set |
| 53 | # CONFIG_IKCONFIG is not set | 55 | # CONFIG_IKCONFIG is not set |
| 54 | CONFIG_LOG_BUF_SHIFT=17 | 56 | CONFIG_LOG_BUF_SHIFT=17 |
| 55 | # CONFIG_GROUP_SCHED is not set | ||
| 56 | # CONFIG_CGROUPS is not set | 57 | # CONFIG_CGROUPS is not set |
| 57 | CONFIG_SYSFS_DEPRECATED=y | 58 | CONFIG_SYSFS_DEPRECATED=y |
| 58 | CONFIG_SYSFS_DEPRECATED_V2=y | 59 | CONFIG_SYSFS_DEPRECATED_V2=y |
| @@ -88,10 +89,14 @@ CONFIG_TIMERFD=y | |||
| 88 | CONFIG_EVENTFD=y | 89 | CONFIG_EVENTFD=y |
| 89 | CONFIG_SHMEM=y | 90 | CONFIG_SHMEM=y |
| 90 | CONFIG_AIO=y | 91 | CONFIG_AIO=y |
| 92 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 93 | CONFIG_PERF_USE_VMALLOC=y | ||
| 91 | 94 | ||
| 92 | # | 95 | # |
| 93 | # Kernel Performance Events And Counters | 96 | # Kernel Performance Events And Counters |
| 94 | # | 97 | # |
| 98 | # CONFIG_PERF_EVENTS is not set | ||
| 99 | # CONFIG_PERF_COUNTERS is not set | ||
| 95 | CONFIG_VM_EVENT_COUNTERS=y | 100 | CONFIG_VM_EVENT_COUNTERS=y |
| 96 | CONFIG_SLUB_DEBUG=y | 101 | CONFIG_SLUB_DEBUG=y |
| 97 | CONFIG_COMPAT_BRK=y | 102 | CONFIG_COMPAT_BRK=y |
| @@ -174,6 +179,7 @@ CONFIG_MMU=y | |||
| 174 | # CONFIG_ARCH_REALVIEW is not set | 179 | # CONFIG_ARCH_REALVIEW is not set |
| 175 | # CONFIG_ARCH_VERSATILE is not set | 180 | # CONFIG_ARCH_VERSATILE is not set |
| 176 | # CONFIG_ARCH_AT91 is not set | 181 | # CONFIG_ARCH_AT91 is not set |
| 182 | # CONFIG_ARCH_BCMRING is not set | ||
| 177 | # CONFIG_ARCH_CLPS711X is not set | 183 | # CONFIG_ARCH_CLPS711X is not set |
| 178 | # CONFIG_ARCH_GEMINI is not set | 184 | # CONFIG_ARCH_GEMINI is not set |
| 179 | # CONFIG_ARCH_EBSA110 is not set | 185 | # CONFIG_ARCH_EBSA110 is not set |
| @@ -183,7 +189,6 @@ CONFIG_MMU=y | |||
| 183 | # CONFIG_ARCH_STMP3XXX is not set | 189 | # CONFIG_ARCH_STMP3XXX is not set |
| 184 | # CONFIG_ARCH_NETX is not set | 190 | # CONFIG_ARCH_NETX is not set |
| 185 | # CONFIG_ARCH_H720X is not set | 191 | # CONFIG_ARCH_H720X is not set |
| 186 | # CONFIG_ARCH_NOMADIK is not set | ||
| 187 | # CONFIG_ARCH_IOP13XX is not set | 192 | # CONFIG_ARCH_IOP13XX is not set |
| 188 | # CONFIG_ARCH_IOP32X is not set | 193 | # CONFIG_ARCH_IOP32X is not set |
| 189 | # CONFIG_ARCH_IOP33X is not set | 194 | # CONFIG_ARCH_IOP33X is not set |
| @@ -200,9 +205,11 @@ CONFIG_MMU=y | |||
| 200 | # CONFIG_ARCH_KS8695 is not set | 205 | # CONFIG_ARCH_KS8695 is not set |
| 201 | # CONFIG_ARCH_NS9XXX is not set | 206 | # CONFIG_ARCH_NS9XXX is not set |
| 202 | # CONFIG_ARCH_W90X900 is not set | 207 | # CONFIG_ARCH_W90X900 is not set |
| 208 | # CONFIG_ARCH_NUC93X is not set | ||
| 203 | # CONFIG_ARCH_PNX4008 is not set | 209 | # CONFIG_ARCH_PNX4008 is not set |
| 204 | # CONFIG_ARCH_PXA is not set | 210 | # CONFIG_ARCH_PXA is not set |
| 205 | # CONFIG_ARCH_MSM is not set | 211 | # CONFIG_ARCH_MSM is not set |
| 212 | # CONFIG_ARCH_SHMOBILE is not set | ||
| 206 | # CONFIG_ARCH_RPC is not set | 213 | # CONFIG_ARCH_RPC is not set |
| 207 | # CONFIG_ARCH_SA1100 is not set | 214 | # CONFIG_ARCH_SA1100 is not set |
| 208 | # CONFIG_ARCH_S3C2410 is not set | 215 | # CONFIG_ARCH_S3C2410 is not set |
| @@ -210,14 +217,22 @@ CONFIG_MMU=y | |||
| 210 | # CONFIG_ARCH_S5P6440 is not set | 217 | # CONFIG_ARCH_S5P6440 is not set |
| 211 | CONFIG_ARCH_S5P6442=y | 218 | CONFIG_ARCH_S5P6442=y |
| 212 | # CONFIG_ARCH_S5PC1XX is not set | 219 | # CONFIG_ARCH_S5PC1XX is not set |
| 220 | # CONFIG_ARCH_S5PV210 is not set | ||
| 213 | # CONFIG_ARCH_SHARK is not set | 221 | # CONFIG_ARCH_SHARK is not set |
| 214 | # CONFIG_ARCH_LH7A40X is not set | 222 | # CONFIG_ARCH_LH7A40X is not set |
| 215 | # CONFIG_ARCH_U300 is not set | 223 | # CONFIG_ARCH_U300 is not set |
| 224 | # CONFIG_ARCH_U8500 is not set | ||
| 225 | # CONFIG_ARCH_NOMADIK is not set | ||
| 216 | # CONFIG_ARCH_DAVINCI is not set | 226 | # CONFIG_ARCH_DAVINCI is not set |
| 217 | # CONFIG_ARCH_OMAP is not set | 227 | # CONFIG_ARCH_OMAP is not set |
| 218 | # CONFIG_ARCH_BCMRING is not set | ||
| 219 | # CONFIG_ARCH_U8500 is not set | ||
| 220 | CONFIG_PLAT_SAMSUNG=y | 228 | CONFIG_PLAT_SAMSUNG=y |
| 229 | |||
| 230 | # | ||
| 231 | # Boot options | ||
| 232 | # | ||
| 233 | # CONFIG_S3C_BOOT_ERROR_RESET is not set | ||
| 234 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
| 235 | CONFIG_S3C_LOWLEVEL_UART_PORT=1 | ||
| 221 | CONFIG_SAMSUNG_CLKSRC=y | 236 | CONFIG_SAMSUNG_CLKSRC=y |
| 222 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y | 237 | CONFIG_SAMSUNG_IRQ_VIC_TIMER=y |
| 223 | CONFIG_SAMSUNG_IRQ_UART=y | 238 | CONFIG_SAMSUNG_IRQ_UART=y |
| @@ -226,21 +241,13 @@ CONFIG_S3C_GPIO_CFG_S3C24XX=y | |||
| 226 | CONFIG_S3C_GPIO_CFG_S3C64XX=y | 241 | CONFIG_S3C_GPIO_CFG_S3C64XX=y |
| 227 | CONFIG_S3C_GPIO_PULL_UPDOWN=y | 242 | CONFIG_S3C_GPIO_PULL_UPDOWN=y |
| 228 | CONFIG_SAMSUNG_GPIO_EXTRA=0 | 243 | CONFIG_SAMSUNG_GPIO_EXTRA=0 |
| 244 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 245 | CONFIG_S3C_GPIO_TRACK=y | ||
| 229 | # CONFIG_S3C_ADC is not set | 246 | # CONFIG_S3C_ADC is not set |
| 230 | 247 | ||
| 231 | # | 248 | # |
| 232 | # Power management | 249 | # Power management |
| 233 | # | 250 | # |
| 234 | CONFIG_PLAT_S3C=y | ||
| 235 | |||
| 236 | # | ||
| 237 | # Boot options | ||
| 238 | # | ||
| 239 | # CONFIG_S3C_BOOT_ERROR_RESET is not set | ||
| 240 | CONFIG_S3C_BOOT_UART_FORCE_FIFO=y | ||
| 241 | CONFIG_S3C_LOWLEVEL_UART_PORT=1 | ||
| 242 | CONFIG_S3C_GPIO_SPACE=0 | ||
| 243 | CONFIG_S3C_GPIO_TRACK=y | ||
| 244 | CONFIG_PLAT_S5P=y | 251 | CONFIG_PLAT_S5P=y |
| 245 | CONFIG_CPU_S5P6442=y | 252 | CONFIG_CPU_S5P6442=y |
| 246 | CONFIG_MACH_SMDK6442=y | 253 | CONFIG_MACH_SMDK6442=y |
| @@ -269,6 +276,7 @@ CONFIG_ARM_THUMB=y | |||
| 269 | # CONFIG_CPU_DCACHE_DISABLE is not set | 276 | # CONFIG_CPU_DCACHE_DISABLE is not set |
| 270 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 277 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 271 | CONFIG_ARM_L1_CACHE_SHIFT=5 | 278 | CONFIG_ARM_L1_CACHE_SHIFT=5 |
| 279 | CONFIG_CPU_HAS_PMU=y | ||
| 272 | # CONFIG_ARM_ERRATA_411920 is not set | 280 | # CONFIG_ARM_ERRATA_411920 is not set |
| 273 | CONFIG_ARM_VIC=y | 281 | CONFIG_ARM_VIC=y |
| 274 | CONFIG_ARM_VIC_NR=2 | 282 | CONFIG_ARM_VIC_NR=2 |
| @@ -394,6 +402,7 @@ CONFIG_HAVE_IDE=y | |||
| 394 | # | 402 | # |
| 395 | # SCSI device support | 403 | # SCSI device support |
| 396 | # | 404 | # |
| 405 | CONFIG_SCSI_MOD=y | ||
| 397 | # CONFIG_RAID_ATTRS is not set | 406 | # CONFIG_RAID_ATTRS is not set |
| 398 | CONFIG_SCSI=y | 407 | CONFIG_SCSI=y |
| 399 | CONFIG_SCSI_DMA=y | 408 | CONFIG_SCSI_DMA=y |
| @@ -515,6 +524,7 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y | |||
| 515 | CONFIG_SERIAL_S5PV210=y | 524 | CONFIG_SERIAL_S5PV210=y |
| 516 | CONFIG_SERIAL_CORE=y | 525 | CONFIG_SERIAL_CORE=y |
| 517 | CONFIG_SERIAL_CORE_CONSOLE=y | 526 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 527 | # CONFIG_SERIAL_TIMBERDALE is not set | ||
| 518 | CONFIG_UNIX98_PTYS=y | 528 | CONFIG_UNIX98_PTYS=y |
| 519 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 529 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
| 520 | CONFIG_LEGACY_PTYS=y | 530 | CONFIG_LEGACY_PTYS=y |
| @@ -540,6 +550,7 @@ CONFIG_GPIOLIB=y | |||
| 540 | # | 550 | # |
| 541 | # Memory mapped GPIO expanders: | 551 | # Memory mapped GPIO expanders: |
| 542 | # | 552 | # |
| 553 | # CONFIG_GPIO_IT8761E is not set | ||
| 543 | 554 | ||
| 544 | # | 555 | # |
| 545 | # I2C GPIO expanders: | 556 | # I2C GPIO expanders: |
| @@ -685,6 +696,7 @@ CONFIG_MISC_FILESYSTEMS=y | |||
| 685 | # CONFIG_BEFS_FS is not set | 696 | # CONFIG_BEFS_FS is not set |
| 686 | # CONFIG_BFS_FS is not set | 697 | # CONFIG_BFS_FS is not set |
| 687 | # CONFIG_EFS_FS is not set | 698 | # CONFIG_EFS_FS is not set |
| 699 | # CONFIG_LOGFS is not set | ||
| 688 | CONFIG_CRAMFS=y | 700 | CONFIG_CRAMFS=y |
| 689 | # CONFIG_SQUASHFS is not set | 701 | # CONFIG_SQUASHFS is not set |
| 690 | # CONFIG_VXFS_FS is not set | 702 | # CONFIG_VXFS_FS is not set |
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig index dc108afc060c..2053be6c9af1 100644 --- a/arch/arm/configs/s5pc100_defconfig +++ b/arch/arm/configs/s5pc100_defconfig | |||
| @@ -171,7 +171,7 @@ CONFIG_DEFAULT_IOSCHED="cfq" | |||
| 171 | # CONFIG_ARCH_SA1100 is not set | 171 | # CONFIG_ARCH_SA1100 is not set |
| 172 | # CONFIG_ARCH_S3C2410 is not set | 172 | # CONFIG_ARCH_S3C2410 is not set |
| 173 | # CONFIG_ARCH_S3C64XX is not set | 173 | # CONFIG_ARCH_S3C64XX is not set |
| 174 | CONFIG_ARCH_S5PC1XX=y | 174 | CONFIG_ARCH_S5PC100=y |
| 175 | # CONFIG_ARCH_SHARK is not set | 175 | # CONFIG_ARCH_SHARK is not set |
| 176 | # CONFIG_ARCH_LH7A40X is not set | 176 | # CONFIG_ARCH_LH7A40X is not set |
| 177 | # CONFIG_ARCH_U300 is not set | 177 | # CONFIG_ARCH_U300 is not set |
diff --git a/arch/arm/configs/s5pc110_defconfig b/arch/arm/configs/s5pc110_defconfig index 6ea636131ac8..796cb78498c3 100644 --- a/arch/arm/configs/s5pc110_defconfig +++ b/arch/arm/configs/s5pc110_defconfig | |||
| @@ -1,11 +1,12 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.33-rc4 | 3 | # Linux kernel version: 2.6.34 |
| 4 | # Wed Feb 24 15:36:54 2010 | 4 | # Sat May 22 03:18:21 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_HAVE_PROC_CPU=y | ||
| 9 | CONFIG_NO_IOPORT=y | 10 | CONFIG_NO_IOPORT=y |
| 10 | CONFIG_GENERIC_HARDIRQS=y | 11 | CONFIG_GENERIC_HARDIRQS=y |
| 11 | CONFIG_STACKTRACE_SUPPORT=y | 12 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y | |||
| 17 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 18 | CONFIG_GENERIC_HWEIGHT=y | 19 | CONFIG_GENERIC_HWEIGHT=y |
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 21 | CONFIG_NEED_DMA_MAP_STATE=y | ||
| 20 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 21 | CONFIG_ARM_L1_CACHE_SHIFT_6=y | 23 | CONFIG_ARM_L1_CACHE_SHIFT_6=y |
| 22 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
| @@ -54,7 +56,6 @@ CONFIG_RCU_FANOUT=32 | |||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | 56 | # CONFIG_TREE_RCU_TRACE is not set |
| 55 | # CONFIG_IKCONFIG is not set | 57 | # CONFIG_IKCONFIG is not set |
| 56 | CONFIG_LOG_BUF_SHIFT=17 | 58 | CONFIG_LOG_BUF_SHIFT=17 |
| 57 | # CONFIG_GROUP_SCHED is not set | ||
| 58 | # CONFIG_CGROUPS is not set | 59 | # CONFIG_CGROUPS is not set |
| 59 | CONFIG_SYSFS_DEPRECATED=y | 60 | CONFIG_SYSFS_DEPRECATED=y |
| 60 | CONFIG_SYSFS_DEPRECATED_V2=y | 61 | CONFIG_SYSFS_DEPRECATED_V2=y |
| @@ -90,10 +91,14 @@ CONFIG_TIMERFD=y | |||
| 90 | CONFIG_EVENTFD=y | 91 | CONFIG_EVENTFD=y |
| 91 | CONFIG_SHMEM=y | 92 | CONFIG_SHMEM=y |
| 92 | CONFIG_AIO=y | 93 | CONFIG_AIO=y |
| 94 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 95 | CONFIG_PERF_USE_VMALLOC=y | ||
| 93 | 96 | ||
| 94 | # | 97 | # |
| 95 | # Kernel Performance Events And Counters | 98 | # Kernel Performance Events And Counters |
| 96 | # | 99 | # |
| 100 | # CONFIG_PERF_EVENTS is not set | ||
| 101 | # CONFIG_PERF_COUNTERS is not set | ||
| 97 | CONFIG_VM_EVENT_COUNTERS=y | 102 | CONFIG_VM_EVENT_COUNTERS=y |
| 98 | CONFIG_SLUB_DEBUG=y | 103 | CONFIG_SLUB_DEBUG=y |
| 99 | CONFIG_COMPAT_BRK=y | 104 | CONFIG_COMPAT_BRK=y |
| @@ -176,6 +181,7 @@ CONFIG_MMU=y | |||
| 176 | # CONFIG_ARCH_REALVIEW is not set | 181 | # CONFIG_ARCH_REALVIEW is not set |
| 177 | # CONFIG_ARCH_VERSATILE is not set | 182 | # CONFIG_ARCH_VERSATILE is not set |
| 178 | # CONFIG_ARCH_AT91 is not set | 183 | # CONFIG_ARCH_AT91 is not set |
| 184 | # CONFIG_ARCH_BCMRING is not set | ||
| 179 | # CONFIG_ARCH_CLPS711X is not set | 185 | # CONFIG_ARCH_CLPS711X is not set |
| 180 | # CONFIG_ARCH_GEMINI is not set | 186 | # CONFIG_ARCH_GEMINI is not set |
| 181 | # CONFIG_ARCH_EBSA110 is not set | 187 | # CONFIG_ARCH_EBSA110 is not set |
| @@ -185,7 +191,6 @@ CONFIG_MMU=y | |||
| 185 | # CONFIG_ARCH_STMP3XXX is not set | 191 | # CONFIG_ARCH_STMP3XXX is not set |
| 186 | # CONFIG_ARCH_NETX is not set | 192 | # CONFIG_ARCH_NETX is not set |
| 187 | # CONFIG_ARCH_H720X is not set | 193 | # CONFIG_ARCH_H720X is not set |
| 188 | # CONFIG_ARCH_NOMADIK is not set | ||
| 189 | # CONFIG_ARCH_IOP13XX is not set | 194 | # CONFIG_ARCH_IOP13XX is not set |
| 190 | # CONFIG_ARCH_IOP32X is not set | 195 | # CONFIG_ARCH_IOP32X is not set |
| 191 | # CONFIG_ARCH_IOP33X is not set | 196 | # CONFIG_ARCH_IOP33X is not set |
| @@ -202,9 +207,11 @@ CONFIG_MMU=y | |||
| 202 | # CONFIG_ARCH_KS8695 is not set | 207 | # CONFIG_ARCH_KS8695 is not set |
| 203 | # CONFIG_ARCH_NS9XXX is not set | 208 | # CONFIG_ARCH_NS9XXX is not set |
| 204 | # CONFIG_ARCH_W90X900 is not set | 209 | # CONFIG_ARCH_W90X900 is not set |
| 210 | # CONFIG_ARCH_NUC93X is not set | ||
| 205 | # CONFIG_ARCH_PNX4008 is not set | 211 | # CONFIG_ARCH_PNX4008 is not set |
| 206 | # CONFIG_ARCH_PXA is not set | 212 | # CONFIG_ARCH_PXA is not set |
| 207 | # CONFIG_ARCH_MSM is not set | 213 | # CONFIG_ARCH_MSM is not set |
| 214 | # CONFIG_ARCH_SHMOBILE is not set | ||
| 208 | # CONFIG_ARCH_RPC is not set | 215 | # CONFIG_ARCH_RPC is not set |
| 209 | # CONFIG_ARCH_SA1100 is not set | 216 | # CONFIG_ARCH_SA1100 is not set |
| 210 | # CONFIG_ARCH_S3C2410 is not set | 217 | # CONFIG_ARCH_S3C2410 is not set |
| @@ -216,10 +223,10 @@ CONFIG_ARCH_S5PV210=y | |||
| 216 | # CONFIG_ARCH_SHARK is not set | 223 | # CONFIG_ARCH_SHARK is not set |
| 217 | # CONFIG_ARCH_LH7A40X is not set | 224 | # CONFIG_ARCH_LH7A40X is not set |
| 218 | # CONFIG_ARCH_U300 is not set | 225 | # CONFIG_ARCH_U300 is not set |
| 226 | # CONFIG_ARCH_U8500 is not set | ||
| 227 | # CONFIG_ARCH_NOMADIK is not set | ||
| 219 | # CONFIG_ARCH_DAVINCI is not set | 228 | # CONFIG_ARCH_DAVINCI is not set |
| 220 | # CONFIG_ARCH_OMAP is not set | 229 | # CONFIG_ARCH_OMAP is not set |
| 221 | # CONFIG_ARCH_BCMRING is not set | ||
| 222 | # CONFIG_ARCH_U8500 is not set | ||
| 223 | CONFIG_PLAT_SAMSUNG=y | 230 | CONFIG_PLAT_SAMSUNG=y |
| 224 | 231 | ||
| 225 | # | 232 | # |
| @@ -274,6 +281,7 @@ CONFIG_ARM_THUMB=y | |||
| 274 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 281 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 275 | CONFIG_HAS_TLS_REG=y | 282 | CONFIG_HAS_TLS_REG=y |
| 276 | CONFIG_ARM_L1_CACHE_SHIFT=6 | 283 | CONFIG_ARM_L1_CACHE_SHIFT=6 |
| 284 | CONFIG_CPU_HAS_PMU=y | ||
| 277 | # CONFIG_ARM_ERRATA_430973 is not set | 285 | # CONFIG_ARM_ERRATA_430973 is not set |
| 278 | # CONFIG_ARM_ERRATA_458693 is not set | 286 | # CONFIG_ARM_ERRATA_458693 is not set |
| 279 | # CONFIG_ARM_ERRATA_460075 is not set | 287 | # CONFIG_ARM_ERRATA_460075 is not set |
| @@ -404,6 +412,7 @@ CONFIG_HAVE_IDE=y | |||
| 404 | # | 412 | # |
| 405 | # SCSI device support | 413 | # SCSI device support |
| 406 | # | 414 | # |
| 415 | CONFIG_SCSI_MOD=y | ||
| 407 | # CONFIG_RAID_ATTRS is not set | 416 | # CONFIG_RAID_ATTRS is not set |
| 408 | CONFIG_SCSI=y | 417 | CONFIG_SCSI=y |
| 409 | CONFIG_SCSI_DMA=y | 418 | CONFIG_SCSI_DMA=y |
| @@ -526,6 +535,7 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y | |||
| 526 | CONFIG_SERIAL_S5PV210=y | 535 | CONFIG_SERIAL_S5PV210=y |
| 527 | CONFIG_SERIAL_CORE=y | 536 | CONFIG_SERIAL_CORE=y |
| 528 | CONFIG_SERIAL_CORE_CONSOLE=y | 537 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 538 | # CONFIG_SERIAL_TIMBERDALE is not set | ||
| 529 | CONFIG_UNIX98_PTYS=y | 539 | CONFIG_UNIX98_PTYS=y |
| 530 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 540 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
| 531 | CONFIG_LEGACY_PTYS=y | 541 | CONFIG_LEGACY_PTYS=y |
| @@ -551,6 +561,7 @@ CONFIG_GPIOLIB=y | |||
| 551 | # | 561 | # |
| 552 | # Memory mapped GPIO expanders: | 562 | # Memory mapped GPIO expanders: |
| 553 | # | 563 | # |
| 564 | # CONFIG_GPIO_IT8761E is not set | ||
| 554 | 565 | ||
| 555 | # | 566 | # |
| 556 | # I2C GPIO expanders: | 567 | # I2C GPIO expanders: |
| @@ -696,6 +707,7 @@ CONFIG_MISC_FILESYSTEMS=y | |||
| 696 | # CONFIG_BEFS_FS is not set | 707 | # CONFIG_BEFS_FS is not set |
| 697 | # CONFIG_BFS_FS is not set | 708 | # CONFIG_BFS_FS is not set |
| 698 | # CONFIG_EFS_FS is not set | 709 | # CONFIG_EFS_FS is not set |
| 710 | # CONFIG_LOGFS is not set | ||
| 699 | CONFIG_CRAMFS=y | 711 | CONFIG_CRAMFS=y |
| 700 | # CONFIG_SQUASHFS is not set | 712 | # CONFIG_SQUASHFS is not set |
| 701 | # CONFIG_VXFS_FS is not set | 713 | # CONFIG_VXFS_FS is not set |
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig index 3f7d47491b54..6831dab97d96 100644 --- a/arch/arm/configs/s5pv210_defconfig +++ b/arch/arm/configs/s5pv210_defconfig | |||
| @@ -1,11 +1,12 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.33-rc4 | 3 | # Linux kernel version: 2.6.34 |
| 4 | # Wed Feb 24 15:36:16 2010 | 4 | # Sat May 22 03:18:22 2010 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_HAVE_PROC_CPU=y | ||
| 9 | CONFIG_NO_IOPORT=y | 10 | CONFIG_NO_IOPORT=y |
| 10 | CONFIG_GENERIC_HARDIRQS=y | 11 | CONFIG_GENERIC_HARDIRQS=y |
| 11 | CONFIG_STACKTRACE_SUPPORT=y | 12 | CONFIG_STACKTRACE_SUPPORT=y |
| @@ -17,6 +18,7 @@ CONFIG_GENERIC_IRQ_PROBE=y | |||
| 17 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 18 | CONFIG_GENERIC_HWEIGHT=y | 19 | CONFIG_GENERIC_HWEIGHT=y |
| 19 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 21 | CONFIG_NEED_DMA_MAP_STATE=y | ||
| 20 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 21 | CONFIG_ARM_L1_CACHE_SHIFT_6=y | 23 | CONFIG_ARM_L1_CACHE_SHIFT_6=y |
| 22 | CONFIG_VECTORS_BASE=0xffff0000 | 24 | CONFIG_VECTORS_BASE=0xffff0000 |
| @@ -54,7 +56,6 @@ CONFIG_RCU_FANOUT=32 | |||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | 56 | # CONFIG_TREE_RCU_TRACE is not set |
| 55 | # CONFIG_IKCONFIG is not set | 57 | # CONFIG_IKCONFIG is not set |
| 56 | CONFIG_LOG_BUF_SHIFT=17 | 58 | CONFIG_LOG_BUF_SHIFT=17 |
| 57 | # CONFIG_GROUP_SCHED is not set | ||
| 58 | # CONFIG_CGROUPS is not set | 59 | # CONFIG_CGROUPS is not set |
| 59 | CONFIG_SYSFS_DEPRECATED=y | 60 | CONFIG_SYSFS_DEPRECATED=y |
| 60 | CONFIG_SYSFS_DEPRECATED_V2=y | 61 | CONFIG_SYSFS_DEPRECATED_V2=y |
| @@ -90,10 +91,14 @@ CONFIG_TIMERFD=y | |||
| 90 | CONFIG_EVENTFD=y | 91 | CONFIG_EVENTFD=y |
| 91 | CONFIG_SHMEM=y | 92 | CONFIG_SHMEM=y |
| 92 | CONFIG_AIO=y | 93 | CONFIG_AIO=y |
| 94 | CONFIG_HAVE_PERF_EVENTS=y | ||
| 95 | CONFIG_PERF_USE_VMALLOC=y | ||
| 93 | 96 | ||
| 94 | # | 97 | # |
| 95 | # Kernel Performance Events And Counters | 98 | # Kernel Performance Events And Counters |
| 96 | # | 99 | # |
| 100 | # CONFIG_PERF_EVENTS is not set | ||
| 101 | # CONFIG_PERF_COUNTERS is not set | ||
| 97 | CONFIG_VM_EVENT_COUNTERS=y | 102 | CONFIG_VM_EVENT_COUNTERS=y |
| 98 | CONFIG_SLUB_DEBUG=y | 103 | CONFIG_SLUB_DEBUG=y |
| 99 | CONFIG_COMPAT_BRK=y | 104 | CONFIG_COMPAT_BRK=y |
| @@ -176,6 +181,7 @@ CONFIG_MMU=y | |||
| 176 | # CONFIG_ARCH_REALVIEW is not set | 181 | # CONFIG_ARCH_REALVIEW is not set |
| 177 | # CONFIG_ARCH_VERSATILE is not set | 182 | # CONFIG_ARCH_VERSATILE is not set |
| 178 | # CONFIG_ARCH_AT91 is not set | 183 | # CONFIG_ARCH_AT91 is not set |
| 184 | # CONFIG_ARCH_BCMRING is not set | ||
| 179 | # CONFIG_ARCH_CLPS711X is not set | 185 | # CONFIG_ARCH_CLPS711X is not set |
| 180 | # CONFIG_ARCH_GEMINI is not set | 186 | # CONFIG_ARCH_GEMINI is not set |
| 181 | # CONFIG_ARCH_EBSA110 is not set | 187 | # CONFIG_ARCH_EBSA110 is not set |
| @@ -185,7 +191,6 @@ CONFIG_MMU=y | |||
| 185 | # CONFIG_ARCH_STMP3XXX is not set | 191 | # CONFIG_ARCH_STMP3XXX is not set |
| 186 | # CONFIG_ARCH_NETX is not set | 192 | # CONFIG_ARCH_NETX is not set |
| 187 | # CONFIG_ARCH_H720X is not set | 193 | # CONFIG_ARCH_H720X is not set |
| 188 | # CONFIG_ARCH_NOMADIK is not set | ||
| 189 | # CONFIG_ARCH_IOP13XX is not set | 194 | # CONFIG_ARCH_IOP13XX is not set |
| 190 | # CONFIG_ARCH_IOP32X is not set | 195 | # CONFIG_ARCH_IOP32X is not set |
| 191 | # CONFIG_ARCH_IOP33X is not set | 196 | # CONFIG_ARCH_IOP33X is not set |
| @@ -202,9 +207,11 @@ CONFIG_MMU=y | |||
| 202 | # CONFIG_ARCH_KS8695 is not set | 207 | # CONFIG_ARCH_KS8695 is not set |
| 203 | # CONFIG_ARCH_NS9XXX is not set | 208 | # CONFIG_ARCH_NS9XXX is not set |
| 204 | # CONFIG_ARCH_W90X900 is not set | 209 | # CONFIG_ARCH_W90X900 is not set |
| 210 | # CONFIG_ARCH_NUC93X is not set | ||
| 205 | # CONFIG_ARCH_PNX4008 is not set | 211 | # CONFIG_ARCH_PNX4008 is not set |
| 206 | # CONFIG_ARCH_PXA is not set | 212 | # CONFIG_ARCH_PXA is not set |
| 207 | # CONFIG_ARCH_MSM is not set | 213 | # CONFIG_ARCH_MSM is not set |
| 214 | # CONFIG_ARCH_SHMOBILE is not set | ||
| 208 | # CONFIG_ARCH_RPC is not set | 215 | # CONFIG_ARCH_RPC is not set |
| 209 | # CONFIG_ARCH_SA1100 is not set | 216 | # CONFIG_ARCH_SA1100 is not set |
| 210 | # CONFIG_ARCH_S3C2410 is not set | 217 | # CONFIG_ARCH_S3C2410 is not set |
| @@ -216,10 +223,10 @@ CONFIG_ARCH_S5PV210=y | |||
| 216 | # CONFIG_ARCH_SHARK is not set | 223 | # CONFIG_ARCH_SHARK is not set |
| 217 | # CONFIG_ARCH_LH7A40X is not set | 224 | # CONFIG_ARCH_LH7A40X is not set |
| 218 | # CONFIG_ARCH_U300 is not set | 225 | # CONFIG_ARCH_U300 is not set |
| 226 | # CONFIG_ARCH_U8500 is not set | ||
| 227 | # CONFIG_ARCH_NOMADIK is not set | ||
| 219 | # CONFIG_ARCH_DAVINCI is not set | 228 | # CONFIG_ARCH_DAVINCI is not set |
| 220 | # CONFIG_ARCH_OMAP is not set | 229 | # CONFIG_ARCH_OMAP is not set |
| 221 | # CONFIG_ARCH_BCMRING is not set | ||
| 222 | # CONFIG_ARCH_U8500 is not set | ||
| 223 | CONFIG_PLAT_SAMSUNG=y | 230 | CONFIG_PLAT_SAMSUNG=y |
| 224 | 231 | ||
| 225 | # | 232 | # |
| @@ -274,6 +281,7 @@ CONFIG_ARM_THUMB=y | |||
| 274 | # CONFIG_CPU_BPREDICT_DISABLE is not set | 281 | # CONFIG_CPU_BPREDICT_DISABLE is not set |
| 275 | CONFIG_HAS_TLS_REG=y | 282 | CONFIG_HAS_TLS_REG=y |
| 276 | CONFIG_ARM_L1_CACHE_SHIFT=6 | 283 | CONFIG_ARM_L1_CACHE_SHIFT=6 |
| 284 | CONFIG_CPU_HAS_PMU=y | ||
| 277 | # CONFIG_ARM_ERRATA_430973 is not set | 285 | # CONFIG_ARM_ERRATA_430973 is not set |
| 278 | # CONFIG_ARM_ERRATA_458693 is not set | 286 | # CONFIG_ARM_ERRATA_458693 is not set |
| 279 | # CONFIG_ARM_ERRATA_460075 is not set | 287 | # CONFIG_ARM_ERRATA_460075 is not set |
| @@ -404,6 +412,7 @@ CONFIG_HAVE_IDE=y | |||
| 404 | # | 412 | # |
| 405 | # SCSI device support | 413 | # SCSI device support |
| 406 | # | 414 | # |
| 415 | CONFIG_SCSI_MOD=y | ||
| 407 | # CONFIG_RAID_ATTRS is not set | 416 | # CONFIG_RAID_ATTRS is not set |
| 408 | CONFIG_SCSI=y | 417 | CONFIG_SCSI=y |
| 409 | CONFIG_SCSI_DMA=y | 418 | CONFIG_SCSI_DMA=y |
| @@ -526,6 +535,7 @@ CONFIG_SERIAL_SAMSUNG_CONSOLE=y | |||
| 526 | CONFIG_SERIAL_S5PV210=y | 535 | CONFIG_SERIAL_S5PV210=y |
| 527 | CONFIG_SERIAL_CORE=y | 536 | CONFIG_SERIAL_CORE=y |
| 528 | CONFIG_SERIAL_CORE_CONSOLE=y | 537 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 538 | # CONFIG_SERIAL_TIMBERDALE is not set | ||
| 529 | CONFIG_UNIX98_PTYS=y | 539 | CONFIG_UNIX98_PTYS=y |
| 530 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 540 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
| 531 | CONFIG_LEGACY_PTYS=y | 541 | CONFIG_LEGACY_PTYS=y |
| @@ -551,6 +561,7 @@ CONFIG_GPIOLIB=y | |||
| 551 | # | 561 | # |
| 552 | # Memory mapped GPIO expanders: | 562 | # Memory mapped GPIO expanders: |
| 553 | # | 563 | # |
| 564 | # CONFIG_GPIO_IT8761E is not set | ||
| 554 | 565 | ||
| 555 | # | 566 | # |
| 556 | # I2C GPIO expanders: | 567 | # I2C GPIO expanders: |
| @@ -696,6 +707,7 @@ CONFIG_MISC_FILESYSTEMS=y | |||
| 696 | # CONFIG_BEFS_FS is not set | 707 | # CONFIG_BEFS_FS is not set |
| 697 | # CONFIG_BFS_FS is not set | 708 | # CONFIG_BFS_FS is not set |
| 698 | # CONFIG_EFS_FS is not set | 709 | # CONFIG_EFS_FS is not set |
| 710 | # CONFIG_LOGFS is not set | ||
| 699 | CONFIG_CRAMFS=y | 711 | CONFIG_CRAMFS=y |
| 700 | # CONFIG_SQUASHFS is not set | 712 | # CONFIG_SQUASHFS is not set |
| 701 | # CONFIG_VXFS_FS is not set | 713 | # CONFIG_VXFS_FS is not set |
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h index 182310b99195..6d7485aff955 100644 --- a/arch/arm/include/asm/hardirq.h +++ b/arch/arm/include/asm/hardirq.h | |||
| @@ -12,7 +12,9 @@ typedef struct { | |||
| 12 | 12 | ||
| 13 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ | 13 | #include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ |
| 14 | 14 | ||
| 15 | #if NR_IRQS > 256 | 15 | #if NR_IRQS > 512 |
| 16 | #define HARDIRQ_BITS 10 | ||
| 17 | #elif NR_IRQS > 256 | ||
| 16 | #define HARDIRQ_BITS 9 | 18 | #define HARDIRQ_BITS 9 |
| 17 | #else | 19 | #else |
| 18 | #define HARDIRQ_BITS 8 | 20 | #define HARDIRQ_BITS 8 |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index c91c77b54dea..122d999bdc7c 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
| @@ -593,6 +593,7 @@ static int __init parse_tag_revision(const struct tag *tag) | |||
| 593 | 593 | ||
| 594 | __tagtable(ATAG_REVISION, parse_tag_revision); | 594 | __tagtable(ATAG_REVISION, parse_tag_revision); |
| 595 | 595 | ||
| 596 | #ifndef CONFIG_CMDLINE_FORCE | ||
| 596 | static int __init parse_tag_cmdline(const struct tag *tag) | 597 | static int __init parse_tag_cmdline(const struct tag *tag) |
| 597 | { | 598 | { |
| 598 | strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); | 599 | strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE); |
| @@ -600,6 +601,7 @@ static int __init parse_tag_cmdline(const struct tag *tag) | |||
| 600 | } | 601 | } |
| 601 | 602 | ||
| 602 | __tagtable(ATAG_CMDLINE, parse_tag_cmdline); | 603 | __tagtable(ATAG_CMDLINE, parse_tag_cmdline); |
| 604 | #endif /* CONFIG_CMDLINE_FORCE */ | ||
| 603 | 605 | ||
| 604 | /* | 606 | /* |
| 605 | * Scan the tag table for this tag, and call its parse function. | 607 | * Scan the tag table for this tag, and call its parse function. |
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c index 50292cd9c120..dd81a918c106 100644 --- a/arch/arm/kernel/unwind.c +++ b/arch/arm/kernel/unwind.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html | 26 | * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html |
| 27 | */ | 27 | */ |
| 28 | 28 | ||
| 29 | #ifndef __CHECKER__ | ||
| 29 | #if !defined (__ARM_EABI__) | 30 | #if !defined (__ARM_EABI__) |
| 30 | #warning Your compiler does not have EABI support. | 31 | #warning Your compiler does not have EABI support. |
| 31 | #warning ARM unwind is known to compile only with EABI compilers. | 32 | #warning ARM unwind is known to compile only with EABI compilers. |
| @@ -34,6 +35,7 @@ | |||
| 34 | #warning Your compiler is too buggy; it is known to not compile ARM unwind support. | 35 | #warning Your compiler is too buggy; it is known to not compile ARM unwind support. |
| 35 | #warning Change compiler or disable ARM_UNWIND option. | 36 | #warning Change compiler or disable ARM_UNWIND option. |
| 36 | #endif | 37 | #endif |
| 38 | #endif /* __CHECKER__ */ | ||
| 37 | 39 | ||
| 38 | #include <linux/kernel.h> | 40 | #include <linux/kernel.h> |
| 39 | #include <linux/init.h> | 41 | #include <linux/init.h> |
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c index 98f9f4bc9396..ee800595594d 100644 --- a/arch/arm/mach-at91/board-sam9m10g45ek.c +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <linux/leds.h> | 25 | #include <linux/leds.h> |
| 26 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
| 27 | 27 | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <video/atmel_lcdc.h> | 28 | #include <video/atmel_lcdc.h> |
| 30 | 29 | ||
| 31 | #include <asm/setup.h> | 30 | #include <asm/setup.h> |
diff --git a/arch/arm/mach-clps711x/Makefile.boot b/arch/arm/mach-clps711x/Makefile.boot index d3d29339e149..a51fcef64fe0 100644 --- a/arch/arm/mach-clps711x/Makefile.boot +++ b/arch/arm/mach-clps711x/Makefile.boot | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | # The standard locations for stuff on CLPS711x type processors | 1 | # The standard locations for stuff on CLPS711x type processors |
| 2 | zreladdr-y := 0xc0028000 | 2 | zreladdr-y := 0xc0028000 |
| 3 | params_phys-y := 0xc0000100 | 3 | params_phys-y := 0xc0000100 |
| 4 | # Should probably have some agreement on these... | 4 | # Should probably have some agreement on these... |
| 5 | initrd_phys-$(CONFIG_ARCH_P720T) := 0xc0400000 | 5 | initrd_phys-$(CONFIG_ARCH_P720T) := 0xc0400000 |
| 6 | initrd_phys-$(CONFIG_ARCH_CDB89712) := 0x00700000 | 6 | initrd_phys-$(CONFIG_ARCH_CDB89712) := 0x00700000 |
| 7 | |||
diff --git a/arch/arm/mach-footbridge/ebsa285-pci.c b/arch/arm/mach-footbridge/ebsa285-pci.c index 720c0bac1702..e5ab5bddbc8c 100644 --- a/arch/arm/mach-footbridge/ebsa285-pci.c +++ b/arch/arm/mach-footbridge/ebsa285-pci.c | |||
| @@ -20,9 +20,9 @@ static int __init ebsa285_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | |||
| 20 | if (dev->vendor == PCI_VENDOR_ID_CONTAQ && | 20 | if (dev->vendor == PCI_VENDOR_ID_CONTAQ && |
| 21 | dev->device == PCI_DEVICE_ID_CONTAQ_82C693) | 21 | dev->device == PCI_DEVICE_ID_CONTAQ_82C693) |
| 22 | switch (PCI_FUNC(dev->devfn)) { | 22 | switch (PCI_FUNC(dev->devfn)) { |
| 23 | case 1: return 14; | 23 | case 1: return 14; |
| 24 | case 2: return 15; | 24 | case 2: return 15; |
| 25 | case 3: return 12; | 25 | case 3: return 12; |
| 26 | } | 26 | } |
| 27 | 27 | ||
| 28 | return irqmap_ebsa285[(slot + pin) & 3]; | 28 | return irqmap_ebsa285[(slot + pin) & 3]; |
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h index d8798dbc44f8..7dd5fa604efc 100644 --- a/arch/arm/mach-h720x/common.h +++ b/arch/arm/mach-h720x/common.h | |||
| @@ -14,13 +14,13 @@ | |||
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | extern unsigned long h720x_gettimeoffset(void); | 16 | extern unsigned long h720x_gettimeoffset(void); |
| 17 | extern void __init h720x_init_irq (void); | 17 | extern void __init h720x_init_irq(void); |
| 18 | extern void __init h720x_map_io(void); | 18 | extern void __init h720x_map_io(void); |
| 19 | 19 | ||
| 20 | #ifdef CONFIG_ARCH_H7202 | 20 | #ifdef CONFIG_ARCH_H7202 |
| 21 | extern struct sys_timer h7202_timer; | 21 | extern struct sys_timer h7202_timer; |
| 22 | extern void __init init_hw_h7202(void); | 22 | extern void __init init_hw_h7202(void); |
| 23 | extern void __init h7202_init_irq (void); | 23 | extern void __init h7202_init_irq(void); |
| 24 | extern void __init h7202_init_time(void); | 24 | extern void __init h7202_init_time(void); |
| 25 | #endif | 25 | #endif |
| 26 | 26 | ||
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c index cccb9f3c9d01..db9381b85bf0 100644 --- a/arch/arm/mach-msm/board-msm7x27.c +++ b/arch/arm/mach-msm/board-msm7x27.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <linux/input.h> | 20 | #include <linux/input.h> |
| 21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/bootmem.h> | ||
| 24 | #include <linux/power_supply.h> | 23 | #include <linux/power_supply.h> |
| 25 | 24 | ||
| 26 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index bac1f3c38a3b..e32981928c77 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/bootmem.h> | ||
| 24 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 25 | #include <linux/smsc911x.h> | 24 | #include <linux/smsc911x.h> |
| 26 | 25 | ||
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c index ec4606643d2c..e3cc80792d6c 100644 --- a/arch/arm/mach-msm/board-qsd8x50.c +++ b/arch/arm/mach-msm/board-qsd8x50.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
| 20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/bootmem.h> | ||
| 23 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 24 | 23 | ||
| 25 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index b91e412f7b3e..a0aeb8a4adc1 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c | |||
| @@ -109,12 +109,7 @@ DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5); | |||
| 109 | DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); | 109 | DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6); |
| 110 | #endif | 110 | #endif |
| 111 | 111 | ||
| 112 | /* | 112 | /* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */ |
| 113 | * Watchdog: | ||
| 114 | * - i.MX1 | ||
| 115 | * - i.MX21 | ||
| 116 | * - i.MX27 | ||
| 117 | */ | ||
| 118 | static struct resource mxc_wdt_resources[] = { | 113 | static struct resource mxc_wdt_resources[] = { |
| 119 | { | 114 | { |
| 120 | .start = MX2x_WDOG_BASE_ADDR, | 115 | .start = MX2x_WDOG_BASE_ADDR, |
| @@ -124,7 +119,7 @@ static struct resource mxc_wdt_resources[] = { | |||
| 124 | }; | 119 | }; |
| 125 | 120 | ||
| 126 | struct platform_device mxc_wdt = { | 121 | struct platform_device mxc_wdt = { |
| 127 | .name = "mxc_wdt", | 122 | .name = "imx2-wdt", |
| 128 | .id = 0, | 123 | .id = 0, |
| 129 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | 124 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), |
| 130 | .resource = mxc_wdt_resources, | 125 | .resource = mxc_wdt_resources, |
| @@ -483,8 +478,8 @@ int __init mxc_register_gpios(void) | |||
| 483 | #ifdef CONFIG_MACH_MX21 | 478 | #ifdef CONFIG_MACH_MX21 |
| 484 | static struct resource mx21_usbhc_resources[] = { | 479 | static struct resource mx21_usbhc_resources[] = { |
| 485 | { | 480 | { |
| 486 | .start = MX21_BASE_ADDR, | 481 | .start = MX21_USBOTG_BASE_ADDR, |
| 487 | .end = MX21_BASE_ADDR + 0x1FFF, | 482 | .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1, |
| 488 | .flags = IORESOURCE_MEM, | 483 | .flags = IORESOURCE_MEM, |
| 489 | }, | 484 | }, |
| 490 | { | 485 | { |
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c index 778fff230918..a87422ed4ff5 100644 --- a/arch/arm/mach-mx2/mach-pca100.c +++ b/arch/arm/mach-mx2/mach-pca100.c | |||
| @@ -145,6 +145,7 @@ static struct mxc_nand_platform_data pca100_nand_board_info = { | |||
| 145 | static struct platform_device *platform_devices[] __initdata = { | 145 | static struct platform_device *platform_devices[] __initdata = { |
| 146 | &mxc_w1_master_device, | 146 | &mxc_w1_master_device, |
| 147 | &mxc_fec_device, | 147 | &mxc_fec_device, |
| 148 | &mxc_wdt, | ||
| 148 | }; | 149 | }; |
| 149 | 150 | ||
| 150 | static struct imxi2c_platform_data pca100_i2c_1_data = { | 151 | static struct imxi2c_platform_data pca100_i2c_1_data = { |
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-mx2/mach-pcm038.c index 035fbe046ec0..36c89431679a 100644 --- a/arch/arm/mach-mx2/mach-pcm038.c +++ b/arch/arm/mach-mx2/mach-pcm038.c | |||
| @@ -182,6 +182,7 @@ static struct platform_device *platform_devices[] __initdata = { | |||
| 182 | &mxc_w1_master_device, | 182 | &mxc_w1_master_device, |
| 183 | &mxc_fec_device, | 183 | &mxc_fec_device, |
| 184 | &pcm038_sram_mtd_device, | 184 | &pcm038_sram_mtd_device, |
| 185 | &mxc_wdt, | ||
| 185 | }; | 186 | }; |
| 186 | 187 | ||
| 187 | /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and | 188 | /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and |
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 3f4b8a0b5fac..3a405fa400eb 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c | |||
| @@ -500,3 +500,18 @@ struct platform_device mx25_fb_device = { | |||
| 500 | .coherent_dma_mask = 0xFFFFFFFF, | 500 | .coherent_dma_mask = 0xFFFFFFFF, |
| 501 | }, | 501 | }, |
| 502 | }; | 502 | }; |
| 503 | |||
| 504 | static struct resource mxc_wdt_resources[] = { | ||
| 505 | { | ||
| 506 | .start = MX25_WDOG_BASE_ADDR, | ||
| 507 | .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1, | ||
| 508 | .flags = IORESOURCE_MEM, | ||
| 509 | }, | ||
| 510 | }; | ||
| 511 | |||
| 512 | struct platform_device mxc_wdt = { | ||
| 513 | .name = "imx2-wdt", | ||
| 514 | .id = 0, | ||
| 515 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | ||
| 516 | .resource = mxc_wdt_resources, | ||
| 517 | }; | ||
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h index 39560e13bc0d..cee12c0a0be6 100644 --- a/arch/arm/mach-mx25/devices.h +++ b/arch/arm/mach-mx25/devices.h | |||
| @@ -21,3 +21,4 @@ extern struct platform_device mx25_fec_device; | |||
| 21 | extern struct platform_device mxc_nand_device; | 21 | extern struct platform_device mxc_nand_device; |
| 22 | extern struct platform_device mx25_rtc_device; | 22 | extern struct platform_device mx25_rtc_device; |
| 23 | extern struct platform_device mx25_fb_device; | 23 | extern struct platform_device mx25_fb_device; |
| 24 | extern struct platform_device mxc_wdt; | ||
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index 170f68e46dd5..344753fdf25e 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig | |||
| @@ -82,6 +82,7 @@ config MACH_MX31MOBOARD | |||
| 82 | config MACH_MX31LILLY | 82 | config MACH_MX31LILLY |
| 83 | bool "Support MX31 LILLY-1131 platforms (INCO startec)" | 83 | bool "Support MX31 LILLY-1131 platforms (INCO startec)" |
| 84 | select ARCH_MX31 | 84 | select ARCH_MX31 |
| 85 | select MXC_ULPI if USB_ULPI | ||
| 85 | help | 86 | help |
| 86 | Include support for mx31 based LILLY1131 modules. This includes | 87 | Include support for mx31 based LILLY1131 modules. This includes |
| 87 | specific configurations for the board and its peripherals. | 88 | specific configurations for the board and its peripherals. |
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index f8911154a9fa..db7acd6e9101 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
| @@ -582,12 +582,50 @@ static struct resource imx_wdt_resources[] = { | |||
| 582 | }; | 582 | }; |
| 583 | 583 | ||
| 584 | struct platform_device imx_wdt_device0 = { | 584 | struct platform_device imx_wdt_device0 = { |
| 585 | .name = "imx-wdt", | 585 | .name = "imx2-wdt", |
| 586 | .id = 0, | 586 | .id = 0, |
| 587 | .num_resources = ARRAY_SIZE(imx_wdt_resources), | 587 | .num_resources = ARRAY_SIZE(imx_wdt_resources), |
| 588 | .resource = imx_wdt_resources, | 588 | .resource = imx_wdt_resources, |
| 589 | }; | 589 | }; |
| 590 | 590 | ||
| 591 | static struct resource imx_rtc_resources[] = { | ||
| 592 | { | ||
| 593 | .start = MX31_RTC_BASE_ADDR, | ||
| 594 | .end = MX31_RTC_BASE_ADDR + 0x3fff, | ||
| 595 | .flags = IORESOURCE_MEM, | ||
| 596 | }, | ||
| 597 | { | ||
| 598 | .start = MX31_INT_RTC, | ||
| 599 | .flags = IORESOURCE_IRQ, | ||
| 600 | }, | ||
| 601 | }; | ||
| 602 | |||
| 603 | struct platform_device imx_rtc_device0 = { | ||
| 604 | .name = "mxc_rtc", | ||
| 605 | .id = -1, | ||
| 606 | .num_resources = ARRAY_SIZE(imx_rtc_resources), | ||
| 607 | .resource = imx_rtc_resources, | ||
| 608 | }; | ||
| 609 | |||
| 610 | static struct resource imx_kpp_resources[] = { | ||
| 611 | { | ||
| 612 | .start = MX3x_KPP_BASE_ADDR, | ||
| 613 | .end = MX3x_KPP_BASE_ADDR + 0xf, | ||
| 614 | .flags = IORESOURCE_MEM | ||
| 615 | }, { | ||
| 616 | .start = MX3x_INT_KPP, | ||
| 617 | .end = MX3x_INT_KPP, | ||
| 618 | .flags = IORESOURCE_IRQ, | ||
| 619 | }, | ||
| 620 | }; | ||
| 621 | |||
| 622 | struct platform_device imx_kpp_device = { | ||
| 623 | .name = "imx-keypad", | ||
| 624 | .id = -1, | ||
| 625 | .num_resources = ARRAY_SIZE(imx_kpp_resources), | ||
| 626 | .resource = imx_kpp_resources, | ||
| 627 | }; | ||
| 628 | |||
| 591 | static int __init mx3_devices_init(void) | 629 | static int __init mx3_devices_init(void) |
| 592 | { | 630 | { |
| 593 | if (cpu_is_mx31()) { | 631 | if (cpu_is_mx31()) { |
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 4f77eb501274..2c3c8646a29e 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h | |||
| @@ -27,3 +27,5 @@ extern struct platform_device imx_ssi_device0; | |||
| 27 | extern struct platform_device imx_ssi_device1; | 27 | extern struct platform_device imx_ssi_device1; |
| 28 | extern struct platform_device imx_ssi_device1; | 28 | extern struct platform_device imx_ssi_device1; |
| 29 | extern struct platform_device imx_wdt_device0; | 29 | extern struct platform_device imx_wdt_device0; |
| 30 | extern struct platform_device imx_rtc_device0; | ||
| 31 | extern struct platform_device imx_kpp_device; | ||
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index f54af1e29ca4..58e57291b79d 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/delay.h> | ||
| 19 | #include <linux/types.h> | 20 | #include <linux/types.h> |
| 20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| 21 | #include <linux/clk.h> | 22 | #include <linux/clk.h> |
| @@ -26,6 +27,8 @@ | |||
| 26 | #include <linux/mfd/mc13783.h> | 27 | #include <linux/mfd/mc13783.h> |
| 27 | #include <linux/spi/spi.h> | 28 | #include <linux/spi/spi.h> |
| 28 | #include <linux/regulator/machine.h> | 29 | #include <linux/regulator/machine.h> |
| 30 | #include <linux/fsl_devices.h> | ||
| 31 | #include <linux/input/matrix_keypad.h> | ||
| 29 | 32 | ||
| 30 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 31 | #include <asm/mach-types.h> | 34 | #include <asm/mach-types.h> |
| @@ -65,6 +68,50 @@ static int mx31_3ds_pins[] = { | |||
| 65 | MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ | 68 | MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */ |
| 66 | /* MC13783 IRQ */ | 69 | /* MC13783 IRQ */ |
| 67 | IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), | 70 | IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), |
| 71 | /* USB OTG reset */ | ||
| 72 | IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO), | ||
| 73 | /* USB OTG */ | ||
| 74 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, | ||
| 75 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, | ||
| 76 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, | ||
| 77 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, | ||
| 78 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, | ||
| 79 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, | ||
| 80 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, | ||
| 81 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, | ||
| 82 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, | ||
| 83 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, | ||
| 84 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, | ||
| 85 | MX31_PIN_USBOTG_STP__USBOTG_STP, | ||
| 86 | /*Keyboard*/ | ||
| 87 | MX31_PIN_KEY_ROW0_KEY_ROW0, | ||
| 88 | MX31_PIN_KEY_ROW1_KEY_ROW1, | ||
| 89 | MX31_PIN_KEY_ROW2_KEY_ROW2, | ||
| 90 | MX31_PIN_KEY_COL0_KEY_COL0, | ||
| 91 | MX31_PIN_KEY_COL1_KEY_COL1, | ||
| 92 | MX31_PIN_KEY_COL2_KEY_COL2, | ||
| 93 | MX31_PIN_KEY_COL3_KEY_COL3, | ||
| 94 | }; | ||
| 95 | |||
| 96 | /* | ||
| 97 | * Matrix keyboard | ||
| 98 | */ | ||
| 99 | |||
| 100 | static const uint32_t mx31_3ds_keymap[] = { | ||
| 101 | KEY(0, 0, KEY_UP), | ||
| 102 | KEY(0, 1, KEY_DOWN), | ||
| 103 | KEY(1, 0, KEY_RIGHT), | ||
| 104 | KEY(1, 1, KEY_LEFT), | ||
| 105 | KEY(1, 2, KEY_ENTER), | ||
| 106 | KEY(2, 0, KEY_F6), | ||
| 107 | KEY(2, 1, KEY_F8), | ||
| 108 | KEY(2, 2, KEY_F9), | ||
| 109 | KEY(2, 3, KEY_F10), | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct matrix_keymap_data mx31_3ds_keymap_data = { | ||
| 113 | .keymap = mx31_3ds_keymap, | ||
| 114 | .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), | ||
| 68 | }; | 115 | }; |
| 69 | 116 | ||
| 70 | /* Regulators */ | 117 | /* Regulators */ |
| @@ -126,6 +173,41 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = { | |||
| 126 | #endif | 173 | #endif |
| 127 | }; | 174 | }; |
| 128 | 175 | ||
| 176 | /* | ||
| 177 | * USB OTG | ||
| 178 | */ | ||
| 179 | |||
| 180 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 181 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 182 | |||
| 183 | #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) | ||
| 184 | |||
| 185 | static void mx31_3ds_usbotg_init(void) | ||
| 186 | { | ||
| 187 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); | ||
| 188 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); | ||
| 189 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); | ||
| 190 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); | ||
| 191 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); | ||
| 192 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); | ||
| 193 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); | ||
| 194 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); | ||
| 195 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); | ||
| 196 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); | ||
| 197 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); | ||
| 198 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); | ||
| 199 | |||
| 200 | gpio_request(USBOTG_RST_B, "otgusb-reset"); | ||
| 201 | gpio_direction_output(USBOTG_RST_B, 0); | ||
| 202 | mdelay(1); | ||
| 203 | gpio_set_value(USBOTG_RST_B, 1); | ||
| 204 | } | ||
| 205 | |||
| 206 | static struct fsl_usb2_platform_data usbotg_pdata = { | ||
| 207 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 208 | .phy_mode = FSL_USB2_PHY_ULPI, | ||
| 209 | }; | ||
| 210 | |||
| 129 | static struct imxuart_platform_data uart_pdata = { | 211 | static struct imxuart_platform_data uart_pdata = { |
| 130 | .flags = IMXUART_HAVE_RTSCTS, | 212 | .flags = IMXUART_HAVE_RTSCTS, |
| 131 | }; | 213 | }; |
| @@ -315,6 +397,11 @@ static void __init mxc_board_init(void) | |||
| 315 | spi_register_board_info(mx31_3ds_spi_devs, | 397 | spi_register_board_info(mx31_3ds_spi_devs, |
| 316 | ARRAY_SIZE(mx31_3ds_spi_devs)); | 398 | ARRAY_SIZE(mx31_3ds_spi_devs)); |
| 317 | 399 | ||
| 400 | mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); | ||
| 401 | |||
| 402 | mx31_3ds_usbotg_init(); | ||
| 403 | mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); | ||
| 404 | |||
| 318 | if (!mx31_3ds_init_expio()) | 405 | if (!mx31_3ds_init_expio()) |
| 319 | platform_device_register(&smsc911x_device); | 406 | platform_device_register(&smsc911x_device); |
| 320 | } | 407 | } |
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c index 80847b04c063..d3d5877c750e 100644 --- a/arch/arm/mach-mx3/mach-mx31lilly.c +++ b/arch/arm/mach-mx3/mach-mx31lilly.c | |||
| @@ -27,12 +27,15 @@ | |||
| 27 | #include <linux/types.h> | 27 | #include <linux/types.h> |
| 28 | #include <linux/init.h> | 28 | #include <linux/init.h> |
| 29 | #include <linux/clk.h> | 29 | #include <linux/clk.h> |
| 30 | #include <linux/gpio.h> | ||
| 30 | #include <linux/platform_device.h> | 31 | #include <linux/platform_device.h> |
| 31 | #include <linux/interrupt.h> | 32 | #include <linux/interrupt.h> |
| 32 | #include <linux/smsc911x.h> | 33 | #include <linux/smsc911x.h> |
| 33 | #include <linux/mtd/physmap.h> | 34 | #include <linux/mtd/physmap.h> |
| 34 | #include <linux/spi/spi.h> | 35 | #include <linux/spi/spi.h> |
| 35 | #include <linux/mfd/mc13783.h> | 36 | #include <linux/mfd/mc13783.h> |
| 37 | #include <linux/usb/otg.h> | ||
| 38 | #include <linux/usb/ulpi.h> | ||
| 36 | 39 | ||
| 37 | #include <asm/mach-types.h> | 40 | #include <asm/mach-types.h> |
| 38 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
| @@ -44,6 +47,8 @@ | |||
| 44 | #include <mach/iomux-mx3.h> | 47 | #include <mach/iomux-mx3.h> |
| 45 | #include <mach/board-mx31lilly.h> | 48 | #include <mach/board-mx31lilly.h> |
| 46 | #include <mach/spi.h> | 49 | #include <mach/spi.h> |
| 50 | #include <mach/mxc_ehci.h> | ||
| 51 | #include <mach/ulpi.h> | ||
| 47 | 52 | ||
| 48 | #include "devices.h" | 53 | #include "devices.h" |
| 49 | 54 | ||
| @@ -108,6 +113,137 @@ static struct platform_device physmap_flash_device = { | |||
| 108 | .num_resources = 1, | 113 | .num_resources = 1, |
| 109 | }; | 114 | }; |
| 110 | 115 | ||
| 116 | /* USB */ | ||
| 117 | |||
| 118 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | ||
| 119 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | ||
| 120 | |||
| 121 | static int usbotg_init(struct platform_device *pdev) | ||
| 122 | { | ||
| 123 | unsigned int pins[] = { | ||
| 124 | MX31_PIN_USBOTG_DATA0__USBOTG_DATA0, | ||
| 125 | MX31_PIN_USBOTG_DATA1__USBOTG_DATA1, | ||
| 126 | MX31_PIN_USBOTG_DATA2__USBOTG_DATA2, | ||
| 127 | MX31_PIN_USBOTG_DATA3__USBOTG_DATA3, | ||
| 128 | MX31_PIN_USBOTG_DATA4__USBOTG_DATA4, | ||
| 129 | MX31_PIN_USBOTG_DATA5__USBOTG_DATA5, | ||
| 130 | MX31_PIN_USBOTG_DATA6__USBOTG_DATA6, | ||
| 131 | MX31_PIN_USBOTG_DATA7__USBOTG_DATA7, | ||
| 132 | MX31_PIN_USBOTG_CLK__USBOTG_CLK, | ||
| 133 | MX31_PIN_USBOTG_DIR__USBOTG_DIR, | ||
| 134 | MX31_PIN_USBOTG_NXT__USBOTG_NXT, | ||
| 135 | MX31_PIN_USBOTG_STP__USBOTG_STP, | ||
| 136 | }; | ||
| 137 | |||
| 138 | mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB OTG"); | ||
| 139 | |||
| 140 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); | ||
| 141 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); | ||
| 142 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); | ||
| 143 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); | ||
| 144 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); | ||
| 145 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); | ||
| 146 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); | ||
| 147 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); | ||
| 148 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); | ||
| 149 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); | ||
| 150 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); | ||
| 151 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); | ||
| 152 | |||
| 153 | mxc_iomux_set_gpr(MUX_PGP_USB_4WIRE, true); | ||
| 154 | mxc_iomux_set_gpr(MUX_PGP_USB_COMMON, true); | ||
| 155 | |||
| 156 | /* chip select */ | ||
| 157 | mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE2, IOMUX_CONFIG_GPIO), | ||
| 158 | "USBOTG_CS"); | ||
| 159 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), "USBH1 CS"); | ||
| 160 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE2), 0); | ||
| 161 | |||
| 162 | return 0; | ||
| 163 | } | ||
| 164 | |||
| 165 | static int usbh1_init(struct platform_device *pdev) | ||
| 166 | { | ||
| 167 | int pins[] = { | ||
| 168 | MX31_PIN_CSPI1_MOSI__USBH1_RXDM, | ||
| 169 | MX31_PIN_CSPI1_MISO__USBH1_RXDP, | ||
| 170 | MX31_PIN_CSPI1_SS0__USBH1_TXDM, | ||
| 171 | MX31_PIN_CSPI1_SS1__USBH1_TXDP, | ||
| 172 | MX31_PIN_CSPI1_SS2__USBH1_RCV, | ||
| 173 | MX31_PIN_CSPI1_SCLK__USBH1_OEB, | ||
| 174 | MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, | ||
| 175 | }; | ||
| 176 | |||
| 177 | mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1"); | ||
| 178 | |||
| 179 | mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG); | ||
| 180 | mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG); | ||
| 181 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG); | ||
| 182 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG); | ||
| 183 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG); | ||
| 184 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG); | ||
| 185 | mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG); | ||
| 186 | |||
| 187 | mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true); | ||
| 188 | |||
| 189 | return 0; | ||
| 190 | } | ||
| 191 | |||
| 192 | static int usbh2_init(struct platform_device *pdev) | ||
| 193 | { | ||
| 194 | int pins[] = { | ||
| 195 | MX31_PIN_USBH2_DATA0__USBH2_DATA0, | ||
| 196 | MX31_PIN_USBH2_DATA1__USBH2_DATA1, | ||
| 197 | MX31_PIN_USBH2_CLK__USBH2_CLK, | ||
| 198 | MX31_PIN_USBH2_DIR__USBH2_DIR, | ||
| 199 | MX31_PIN_USBH2_NXT__USBH2_NXT, | ||
| 200 | MX31_PIN_USBH2_STP__USBH2_STP, | ||
| 201 | }; | ||
| 202 | |||
| 203 | mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); | ||
| 204 | |||
| 205 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | ||
| 206 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | ||
| 207 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | ||
| 208 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | ||
| 209 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | ||
| 210 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | ||
| 211 | mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); | ||
| 212 | mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); | ||
| 213 | mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); | ||
| 214 | mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); | ||
| 215 | mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); | ||
| 216 | mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); | ||
| 217 | |||
| 218 | mxc_iomux_set_gpr(MUX_PGP_UH2, true); | ||
| 219 | |||
| 220 | /* chip select */ | ||
| 221 | mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), | ||
| 222 | "USBH2_CS"); | ||
| 223 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); | ||
| 224 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); | ||
| 225 | |||
| 226 | return 0; | ||
| 227 | } | ||
| 228 | |||
| 229 | static struct mxc_usbh_platform_data usbotg_pdata = { | ||
| 230 | .init = usbotg_init, | ||
| 231 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | ||
| 232 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 233 | }; | ||
| 234 | |||
| 235 | static struct mxc_usbh_platform_data usbh1_pdata = { | ||
| 236 | .init = usbh1_init, | ||
| 237 | .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, | ||
| 238 | .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, | ||
| 239 | }; | ||
| 240 | |||
| 241 | static struct mxc_usbh_platform_data usbh2_pdata = { | ||
| 242 | .init = usbh2_init, | ||
| 243 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | ||
| 244 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 245 | }; | ||
| 246 | |||
| 111 | static struct platform_device *devices[] __initdata = { | 247 | static struct platform_device *devices[] __initdata = { |
| 112 | &smsc91x_device, | 248 | &smsc91x_device, |
| 113 | &physmap_flash_device, | 249 | &physmap_flash_device, |
| @@ -183,6 +319,15 @@ static void __init mx31lilly_board_init(void) | |||
| 183 | spi_register_board_info(&mc13783_dev, 1); | 319 | spi_register_board_info(&mc13783_dev, 1); |
| 184 | 320 | ||
| 185 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 321 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 322 | |||
| 323 | /* USB */ | ||
| 324 | usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 325 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | ||
| 326 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 327 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | ||
| 328 | |||
| 329 | mxc_register_device(&mxc_usbh1, &usbh1_pdata); | ||
| 330 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | ||
| 186 | } | 331 | } |
| 187 | 332 | ||
| 188 | static void __init mx31lilly_timer_init(void) | 333 | static void __init mx31lilly_timer_init(void) |
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index fccb9207b78d..33a8d35498a7 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c | |||
| @@ -18,7 +18,6 @@ | |||
| 18 | 18 | ||
| 19 | #include <linux/delay.h> | 19 | #include <linux/delay.h> |
| 20 | #include <linux/dma-mapping.h> | 20 | #include <linux/dma-mapping.h> |
| 21 | #include <linux/fsl_devices.h> | ||
| 22 | #include <linux/gfp.h> | 21 | #include <linux/gfp.h> |
| 23 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 24 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| @@ -306,84 +305,56 @@ static struct imxmmc_platform_data sdhc1_pdata = { | |||
| 306 | * this pin is dedicated for all mx31moboard systems, so we do it here | 305 | * this pin is dedicated for all mx31moboard systems, so we do it here |
| 307 | */ | 306 | */ |
| 308 | #define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) | 307 | #define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0) |
| 309 | |||
| 310 | static void usb_xcvr_reset(void) | ||
| 311 | { | ||
| 312 | gpio_request(USB_RESET_B, "usb-reset"); | ||
| 313 | gpio_direction_output(USB_RESET_B, 0); | ||
| 314 | mdelay(1); | ||
| 315 | gpio_set_value(USB_RESET_B, 1); | ||
| 316 | } | ||
| 317 | |||
| 318 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ | 308 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ |
| 319 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | 309 | PAD_CTL_ODE_CMOS) |
| 320 | 310 | ||
| 321 | #define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) | 311 | #define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC) |
| 322 | |||
| 323 | static void moboard_usbotg_init(void) | ||
| 324 | { | ||
| 325 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG); | ||
| 326 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG); | ||
| 327 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG); | ||
| 328 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG); | ||
| 329 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG); | ||
| 330 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG); | ||
| 331 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG); | ||
| 332 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG); | ||
| 333 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG); | ||
| 334 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG); | ||
| 335 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG); | ||
| 336 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG); | ||
| 337 | |||
| 338 | gpio_request(OTG_EN_B, "usb-udc-en"); | ||
| 339 | gpio_direction_output(OTG_EN_B, 0); | ||
| 340 | } | ||
| 341 | |||
| 342 | static struct fsl_usb2_platform_data usb_pdata = { | ||
| 343 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 344 | .phy_mode = FSL_USB2_PHY_ULPI, | ||
| 345 | }; | ||
| 346 | |||
| 347 | #if defined(CONFIG_USB_ULPI) | ||
| 348 | |||
| 349 | #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) | 312 | #define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6) |
| 350 | 313 | ||
| 351 | static int moboard_usbh2_hw_init(struct platform_device *pdev) | 314 | static void usb_xcvr_reset(void) |
| 352 | { | 315 | { |
| 353 | int ret; | 316 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); |
| 317 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 318 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 319 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 320 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 321 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 322 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 323 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 324 | mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 325 | mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 326 | mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 327 | mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 354 | 328 | ||
| 355 | mxc_iomux_set_gpr(MUX_PGP_UH2, true); | 329 | mxc_iomux_set_gpr(MUX_PGP_UH2, true); |
| 330 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 331 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 332 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 333 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU); | ||
| 334 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 335 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 336 | mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 337 | mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 338 | mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 339 | mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 340 | mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 341 | mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD); | ||
| 356 | 342 | ||
| 357 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | 343 | gpio_request(OTG_EN_B, "usb-udc-en"); |
| 358 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | 344 | gpio_direction_output(OTG_EN_B, 0); |
| 359 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | 345 | gpio_request(USBH2_EN_B, "usbh2-en"); |
| 360 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | ||
| 361 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | ||
| 362 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | ||
| 363 | mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); | ||
| 364 | mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); | ||
| 365 | mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); | ||
| 366 | mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); | ||
| 367 | mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); | ||
| 368 | mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); | ||
| 369 | |||
| 370 | ret = gpio_request(USBH2_EN_B, "usbh2-en"); | ||
| 371 | if (ret) | ||
| 372 | return ret; | ||
| 373 | gpio_direction_output(USBH2_EN_B, 0); | 346 | gpio_direction_output(USBH2_EN_B, 0); |
| 374 | 347 | ||
| 375 | return 0; | 348 | gpio_request(USB_RESET_B, "usb-reset"); |
| 349 | gpio_direction_output(USB_RESET_B, 0); | ||
| 350 | mdelay(1); | ||
| 351 | gpio_set_value(USB_RESET_B, 1); | ||
| 352 | mdelay(1); | ||
| 376 | } | 353 | } |
| 377 | 354 | ||
| 378 | static int moboard_usbh2_hw_exit(struct platform_device *pdev) | 355 | #if defined(CONFIG_USB_ULPI) |
| 379 | { | ||
| 380 | gpio_free(USBH2_EN_B); | ||
| 381 | return 0; | ||
| 382 | } | ||
| 383 | 356 | ||
| 384 | static struct mxc_usbh_platform_data usbh2_pdata = { | 357 | static struct mxc_usbh_platform_data usbh2_pdata = { |
| 385 | .init = moboard_usbh2_hw_init, | ||
| 386 | .exit = moboard_usbh2_hw_exit, | ||
| 387 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | 358 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, |
| 388 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | 359 | .flags = MXC_EHCI_POWER_PINS_ENABLED, |
| 389 | }; | 360 | }; |
| @@ -508,8 +479,6 @@ static void __init mxc_board_init(void) | |||
| 508 | 479 | ||
| 509 | usb_xcvr_reset(); | 480 | usb_xcvr_reset(); |
| 510 | 481 | ||
| 511 | moboard_usbotg_init(); | ||
| 512 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | ||
| 513 | moboard_usbh2_init(); | 482 | moboard_usbh2_init(); |
| 514 | 483 | ||
| 515 | switch (mx31moboard_baseboard) { | 484 | switch (mx31moboard_baseboard) { |
| @@ -522,7 +491,8 @@ static void __init mxc_board_init(void) | |||
| 522 | mx31moboard_marxbot_init(); | 491 | mx31moboard_marxbot_init(); |
| 523 | break; | 492 | break; |
| 524 | case MX31SMARTBOT: | 493 | case MX31SMARTBOT: |
| 525 | mx31moboard_smartbot_init(); | 494 | case MX31EYEBOT: |
| 495 | mx31moboard_smartbot_init(mx31moboard_baseboard); | ||
| 526 | break; | 496 | break; |
| 527 | default: | 497 | default: |
| 528 | printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", | 498 | printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", |
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c index 78ecd751549b..cce410662383 100644 --- a/arch/arm/mach-mx3/mach-pcm037.c +++ b/arch/arm/mach-mx3/mach-pcm037.c | |||
| @@ -449,6 +449,7 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size) | |||
| 449 | static struct platform_device *devices[] __initdata = { | 449 | static struct platform_device *devices[] __initdata = { |
| 450 | &pcm037_flash, | 450 | &pcm037_flash, |
| 451 | &pcm037_sram_device, | 451 | &pcm037_sram_device, |
| 452 | &imx_wdt_device0, | ||
| 452 | &pcm037_mt9t031, | 453 | &pcm037_mt9t031, |
| 453 | &pcm037_mt9v022, | 454 | &pcm037_mt9v022, |
| 454 | }; | 455 | }; |
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c index 1bf1ec2eef5e..78d9185a9d4b 100644 --- a/arch/arm/mach-mx3/mach-pcm043.c +++ b/arch/arm/mach-mx3/mach-pcm043.c | |||
| @@ -150,6 +150,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = { | |||
| 150 | static struct platform_device *devices[] __initdata = { | 150 | static struct platform_device *devices[] __initdata = { |
| 151 | &pcm043_flash, | 151 | &pcm043_flash, |
| 152 | &mxc_fec_device, | 152 | &mxc_fec_device, |
| 153 | &imx_wdt_device0, | ||
| 153 | }; | 154 | }; |
| 154 | 155 | ||
| 155 | static struct pad_desc pcm043_pads[] = { | 156 | static struct pad_desc pcm043_pads[] = { |
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c index 093c595ca581..5f05bfbec380 100644 --- a/arch/arm/mach-mx3/mx31lite-db.c +++ b/arch/arm/mach-mx3/mx31lite-db.c | |||
| @@ -206,5 +206,6 @@ void __init mx31lite_db_init(void) | |||
| 206 | mxc_register_device(&mxc_spi_device0, &spi0_pdata); | 206 | mxc_register_device(&mxc_spi_device0, &spi0_pdata); |
| 207 | platform_device_register(&litekit_led_device); | 207 | platform_device_register(&litekit_led_device); |
| 208 | mxc_register_device(&imx_wdt_device0, NULL); | 208 | mxc_register_device(&imx_wdt_device0, NULL); |
| 209 | mxc_register_device(&imx_rtc_device0, NULL); | ||
| 209 | } | 210 | } |
| 210 | 211 | ||
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c index 11b906ce7eae..582299cb2c08 100644 --- a/arch/arm/mach-mx3/mx31moboard-devboard.c +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/slab.h> | 23 | #include <linux/slab.h> |
| 24 | #include <linux/types.h> | 24 | #include <linux/types.h> |
| 25 | #include <linux/fsl_devices.h> | ||
| 25 | 26 | ||
| 26 | #include <linux/usb/otg.h> | 27 | #include <linux/usb/otg.h> |
| 27 | 28 | ||
| @@ -213,6 +214,12 @@ static int __init devboard_usbh1_init(void) | |||
| 213 | return mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 214 | return mxc_register_device(&mxc_usbh1, &usbh1_pdata); |
| 214 | } | 215 | } |
| 215 | 216 | ||
| 217 | |||
| 218 | static struct fsl_usb2_platform_data usb_pdata = { | ||
| 219 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 220 | .phy_mode = FSL_USB2_PHY_ULPI, | ||
| 221 | }; | ||
| 222 | |||
| 216 | /* | 223 | /* |
| 217 | * system init for baseboard usage. Will be called by mx31moboard init. | 224 | * system init for baseboard usage. Will be called by mx31moboard init. |
| 218 | */ | 225 | */ |
| @@ -229,5 +236,7 @@ void __init mx31moboard_devboard_init(void) | |||
| 229 | 236 | ||
| 230 | devboard_init_sel_gpios(); | 237 | devboard_init_sel_gpios(); |
| 231 | 238 | ||
| 239 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | ||
| 240 | |||
| 232 | devboard_usbh1_init(); | 241 | devboard_usbh1_init(); |
| 233 | } | 242 | } |
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c index ffb105e14d88..4930f8c27e66 100644 --- a/arch/arm/mach-mx3/mx31moboard-marxbot.c +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/slab.h> | 25 | #include <linux/slab.h> |
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/types.h> | 27 | #include <linux/types.h> |
| 28 | #include <linux/fsl_devices.h> | ||
| 28 | 29 | ||
| 29 | #include <linux/usb/otg.h> | 30 | #include <linux/usb/otg.h> |
| 30 | 31 | ||
| @@ -329,6 +330,11 @@ static int __init marxbot_usbh1_init(void) | |||
| 329 | return mxc_register_device(&mxc_usbh1, &usbh1_pdata); | 330 | return mxc_register_device(&mxc_usbh1, &usbh1_pdata); |
| 330 | } | 331 | } |
| 331 | 332 | ||
| 333 | static struct fsl_usb2_platform_data usb_pdata = { | ||
| 334 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 335 | .phy_mode = FSL_USB2_PHY_ULPI, | ||
| 336 | }; | ||
| 337 | |||
| 332 | /* | 338 | /* |
| 333 | * system init for baseboard usage. Will be called by mx31moboard init. | 339 | * system init for baseboard usage. Will be called by mx31moboard init. |
| 334 | */ | 340 | */ |
| @@ -356,5 +362,7 @@ void __init mx31moboard_marxbot_init(void) | |||
| 356 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); | 362 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); |
| 357 | gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); | 363 | gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); |
| 358 | 364 | ||
| 365 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | ||
| 366 | |||
| 359 | marxbot_usbh1_init(); | 367 | marxbot_usbh1_init(); |
| 360 | } | 368 | } |
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c index 52a69fc8b14f..293eea6d9d97 100644 --- a/arch/arm/mach-mx3/mx31moboard-smartbot.c +++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c | |||
| @@ -23,11 +23,18 @@ | |||
| 23 | #include <linux/i2c.h> | 23 | #include <linux/i2c.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/types.h> | 25 | #include <linux/types.h> |
| 26 | #include <linux/fsl_devices.h> | ||
| 27 | |||
| 28 | #include <linux/usb/otg.h> | ||
| 29 | #include <linux/usb/ulpi.h> | ||
| 26 | 30 | ||
| 27 | #include <mach/common.h> | 31 | #include <mach/common.h> |
| 28 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 29 | #include <mach/imx-uart.h> | 33 | #include <mach/imx-uart.h> |
| 30 | #include <mach/iomux-mx3.h> | 34 | #include <mach/iomux-mx3.h> |
| 35 | #include <mach/board-mx31moboard.h> | ||
| 36 | #include <mach/mxc_ehci.h> | ||
| 37 | #include <mach/ulpi.h> | ||
| 31 | 38 | ||
| 32 | #include <media/soc_camera.h> | 39 | #include <media/soc_camera.h> |
| 33 | 40 | ||
| @@ -116,10 +123,33 @@ static int __init smartbot_cam_init(void) | |||
| 116 | return 0; | 123 | return 0; |
| 117 | } | 124 | } |
| 118 | 125 | ||
| 126 | static struct fsl_usb2_platform_data usb_pdata = { | ||
| 127 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 128 | .phy_mode = FSL_USB2_PHY_ULPI, | ||
| 129 | }; | ||
| 130 | |||
| 131 | #if defined(CONFIG_USB_ULPI) | ||
| 132 | |||
| 133 | static struct mxc_usbh_platform_data otg_host_pdata = { | ||
| 134 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | ||
| 135 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static int __init smartbot_otg_host_init(void) | ||
| 139 | { | ||
| 140 | otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | ||
| 141 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | ||
| 142 | |||
| 143 | return mxc_register_device(&mxc_otg_host, &otg_host_pdata); | ||
| 144 | } | ||
| 145 | #else | ||
| 146 | static inline int smartbot_otg_host_init(void) { return 0; } | ||
| 147 | #endif | ||
| 148 | |||
| 119 | #define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) | 149 | #define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1) |
| 120 | #define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) | 150 | #define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1) |
| 121 | #define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) | 151 | #define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1) |
| 122 | #define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) | 152 | #define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1) |
| 123 | 153 | ||
| 124 | static void smartbot_resets_init(void) | 154 | static void smartbot_resets_init(void) |
| 125 | { | 155 | { |
| @@ -138,15 +168,15 @@ static void smartbot_resets_init(void) | |||
| 138 | gpio_export(TRSLAT_RST_B, false); | 168 | gpio_export(TRSLAT_RST_B, false); |
| 139 | } | 169 | } |
| 140 | 170 | ||
| 141 | if (!gpio_request(SEL3, "sel3")) { | 171 | if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) { |
| 142 | gpio_direction_input(SEL3); | 172 | gpio_direction_output(TRSLAT_SRC_CHOICE, 0); |
| 143 | gpio_export(SEL3, true); | 173 | gpio_export(TRSLAT_SRC_CHOICE, false); |
| 144 | } | 174 | } |
| 145 | } | 175 | } |
| 146 | /* | 176 | /* |
| 147 | * system init for baseboard usage. Will be called by mx31moboard init. | 177 | * system init for baseboard usage. Will be called by mx31moboard init. |
| 148 | */ | 178 | */ |
| 149 | void __init mx31moboard_smartbot_init(void) | 179 | void __init mx31moboard_smartbot_init(int board) |
| 150 | { | 180 | { |
| 151 | printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); | 181 | printk(KERN_INFO "Initializing mx31smartbot peripherals\n"); |
| 152 | 182 | ||
| @@ -155,6 +185,19 @@ void __init mx31moboard_smartbot_init(void) | |||
| 155 | 185 | ||
| 156 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | 186 | mxc_register_device(&mxc_uart_device1, &uart_pdata); |
| 157 | 187 | ||
| 188 | |||
| 189 | switch (board) { | ||
| 190 | case MX31SMARTBOT: | ||
| 191 | mxc_register_device(&mxc_otg_udc_device, &usb_pdata); | ||
| 192 | break; | ||
| 193 | case MX31EYEBOT: | ||
| 194 | smartbot_otg_host_init(); | ||
| 195 | break; | ||
| 196 | default: | ||
| 197 | printk(KERN_WARNING "Unknown board %d, USB OTG not initialized", | ||
| 198 | board); | ||
| 199 | } | ||
| 200 | |||
| 158 | smartbot_resets_init(); | 201 | smartbot_resets_init(); |
| 159 | 202 | ||
| 160 | smartbot_cam_init(); | 203 | smartbot_cam_init(); |
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c index ee67a71db80d..ed885f9d7b73 100644 --- a/arch/arm/mach-mx5/board-mx51_babbage.c +++ b/arch/arm/mach-mx5/board-mx51_babbage.c | |||
| @@ -12,11 +12,16 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/gpio.h> | ||
| 16 | #include <linux/delay.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/fsl_devices.h> | ||
| 15 | 19 | ||
| 16 | #include <mach/common.h> | 20 | #include <mach/common.h> |
| 17 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 18 | #include <mach/imx-uart.h> | 22 | #include <mach/imx-uart.h> |
| 19 | #include <mach/iomux-mx51.h> | 23 | #include <mach/iomux-mx51.h> |
| 24 | #include <mach/mxc_ehci.h> | ||
| 20 | 25 | ||
| 21 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
| 22 | #include <asm/setup.h> | 27 | #include <asm/setup.h> |
| @@ -26,6 +31,18 @@ | |||
| 26 | 31 | ||
| 27 | #include "devices.h" | 32 | #include "devices.h" |
| 28 | 33 | ||
| 34 | #define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ | ||
| 35 | #define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ | ||
| 36 | #define BABBAGE_PHY_RESET (1*32 +5) /* GPIO_2_5 */ | ||
| 37 | |||
| 38 | /* USB_CTRL_1 */ | ||
| 39 | #define MX51_USB_CTRL_1_OFFSET 0x10 | ||
| 40 | #define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) | ||
| 41 | |||
| 42 | #define MX51_USB_PLLDIV_12_MHZ 0x00 | ||
| 43 | #define MX51_USB_PLL_DIV_19_2_MHZ 0x01 | ||
| 44 | #define MX51_USB_PLL_DIV_24_MHZ 0x02 | ||
| 45 | |||
| 29 | static struct platform_device *devices[] __initdata = { | 46 | static struct platform_device *devices[] __initdata = { |
| 30 | &mxc_fec_device, | 47 | &mxc_fec_device, |
| 31 | }; | 48 | }; |
| @@ -46,6 +63,22 @@ static struct pad_desc mx51babbage_pads[] = { | |||
| 46 | MX51_PAD_EIM_D26__UART3_TXD, | 63 | MX51_PAD_EIM_D26__UART3_TXD, |
| 47 | MX51_PAD_EIM_D27__UART3_RTS, | 64 | MX51_PAD_EIM_D27__UART3_RTS, |
| 48 | MX51_PAD_EIM_D24__UART3_CTS, | 65 | MX51_PAD_EIM_D24__UART3_CTS, |
| 66 | |||
| 67 | /* USB HOST1 */ | ||
| 68 | MX51_PAD_USBH1_CLK__USBH1_CLK, | ||
| 69 | MX51_PAD_USBH1_DIR__USBH1_DIR, | ||
| 70 | MX51_PAD_USBH1_NXT__USBH1_NXT, | ||
| 71 | MX51_PAD_USBH1_DATA0__USBH1_DATA0, | ||
| 72 | MX51_PAD_USBH1_DATA1__USBH1_DATA1, | ||
| 73 | MX51_PAD_USBH1_DATA2__USBH1_DATA2, | ||
| 74 | MX51_PAD_USBH1_DATA3__USBH1_DATA3, | ||
| 75 | MX51_PAD_USBH1_DATA4__USBH1_DATA4, | ||
| 76 | MX51_PAD_USBH1_DATA5__USBH1_DATA5, | ||
| 77 | MX51_PAD_USBH1_DATA6__USBH1_DATA6, | ||
| 78 | MX51_PAD_USBH1_DATA7__USBH1_DATA7, | ||
| 79 | |||
| 80 | /* USB HUB reset line*/ | ||
| 81 | MX51_PAD_GPIO_1_7__GPIO1_7, | ||
| 49 | }; | 82 | }; |
| 50 | 83 | ||
| 51 | /* Serial ports */ | 84 | /* Serial ports */ |
| @@ -66,15 +99,149 @@ static inline void mxc_init_imx_uart(void) | |||
| 66 | } | 99 | } |
| 67 | #endif /* SERIAL_IMX */ | 100 | #endif /* SERIAL_IMX */ |
| 68 | 101 | ||
| 102 | static int gpio_usbh1_active(void) | ||
| 103 | { | ||
| 104 | struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; | ||
| 105 | struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; | ||
| 106 | int ret; | ||
| 107 | |||
| 108 | /* Set USBH1_STP to GPIO and toggle it */ | ||
| 109 | mxc_iomux_v3_setup_pad(&usbh1stp_gpio); | ||
| 110 | ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); | ||
| 111 | |||
| 112 | if (ret) { | ||
| 113 | pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret); | ||
| 114 | return ret; | ||
| 115 | } | ||
| 116 | gpio_direction_output(BABBAGE_USBH1_STP, 0); | ||
| 117 | gpio_set_value(BABBAGE_USBH1_STP, 1); | ||
| 118 | msleep(100); | ||
| 119 | gpio_free(BABBAGE_USBH1_STP); | ||
| 120 | |||
| 121 | /* De-assert USB PHY RESETB */ | ||
| 122 | mxc_iomux_v3_setup_pad(&phyreset_gpio); | ||
| 123 | ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); | ||
| 124 | |||
| 125 | if (ret) { | ||
| 126 | pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret); | ||
| 127 | return ret; | ||
| 128 | } | ||
| 129 | gpio_direction_output(BABBAGE_PHY_RESET, 1); | ||
| 130 | return 0; | ||
| 131 | } | ||
| 132 | |||
| 133 | static inline void babbage_usbhub_reset(void) | ||
| 134 | { | ||
| 135 | int ret; | ||
| 136 | |||
| 137 | /* Bring USB hub out of reset */ | ||
| 138 | ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7"); | ||
| 139 | if (ret) { | ||
| 140 | printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret); | ||
| 141 | return; | ||
| 142 | } | ||
| 143 | gpio_direction_output(BABBAGE_USB_HUB_RESET, 0); | ||
| 144 | |||
| 145 | /* USB HUB RESET - De-assert USB HUB RESET_N */ | ||
| 146 | msleep(1); | ||
| 147 | gpio_set_value(BABBAGE_USB_HUB_RESET, 0); | ||
| 148 | msleep(1); | ||
| 149 | gpio_set_value(BABBAGE_USB_HUB_RESET, 1); | ||
| 150 | } | ||
| 151 | |||
| 152 | /* This function is board specific as the bit mask for the plldiv will also | ||
| 153 | be different for other Freescale SoCs, thus a common bitmask is not | ||
| 154 | possible and cannot get place in /plat-mxc/ehci.c.*/ | ||
| 155 | static int initialize_otg_port(struct platform_device *pdev) | ||
| 156 | { | ||
| 157 | u32 v; | ||
| 158 | void __iomem *usb_base; | ||
| 159 | u32 usbother_base; | ||
| 160 | |||
| 161 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | ||
| 162 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | ||
| 163 | |||
| 164 | /* Set the PHY clock to 19.2MHz */ | ||
| 165 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | ||
| 166 | v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; | ||
| 167 | v |= MX51_USB_PLL_DIV_19_2_MHZ; | ||
| 168 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); | ||
| 169 | iounmap(usb_base); | ||
| 170 | return 0; | ||
| 171 | } | ||
| 172 | |||
| 173 | static int initialize_usbh1_port(struct platform_device *pdev) | ||
| 174 | { | ||
| 175 | u32 v; | ||
| 176 | void __iomem *usb_base; | ||
| 177 | u32 usbother_base; | ||
| 178 | |||
| 179 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | ||
| 180 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | ||
| 181 | |||
| 182 | /* The clock for the USBH1 ULPI port will come externally from the PHY. */ | ||
| 183 | v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); | ||
| 184 | __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); | ||
| 185 | iounmap(usb_base); | ||
| 186 | return 0; | ||
| 187 | } | ||
| 188 | |||
| 189 | static struct mxc_usbh_platform_data dr_utmi_config = { | ||
| 190 | .init = initialize_otg_port, | ||
| 191 | .portsc = MXC_EHCI_UTMI_16BIT, | ||
| 192 | .flags = MXC_EHCI_INTERNAL_PHY, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static struct fsl_usb2_platform_data usb_pdata = { | ||
| 196 | .operating_mode = FSL_USB2_DR_DEVICE, | ||
| 197 | .phy_mode = FSL_USB2_PHY_UTMI_WIDE, | ||
| 198 | }; | ||
| 199 | |||
| 200 | static struct mxc_usbh_platform_data usbh1_config = { | ||
| 201 | .init = initialize_usbh1_port, | ||
| 202 | .portsc = MXC_EHCI_MODE_ULPI, | ||
| 203 | .flags = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD), | ||
| 204 | }; | ||
| 205 | |||
| 206 | static int otg_mode_host; | ||
| 207 | |||
| 208 | static int __init babbage_otg_mode(char *options) | ||
| 209 | { | ||
| 210 | if (!strcmp(options, "host")) | ||
| 211 | otg_mode_host = 1; | ||
| 212 | else if (!strcmp(options, "device")) | ||
| 213 | otg_mode_host = 0; | ||
| 214 | else | ||
| 215 | pr_info("otg_mode neither \"host\" nor \"device\". " | ||
| 216 | "Defaulting to device\n"); | ||
| 217 | return 0; | ||
| 218 | } | ||
| 219 | __setup("otg_mode=", babbage_otg_mode); | ||
| 220 | |||
| 69 | /* | 221 | /* |
| 70 | * Board specific initialization. | 222 | * Board specific initialization. |
| 71 | */ | 223 | */ |
| 72 | static void __init mxc_board_init(void) | 224 | static void __init mxc_board_init(void) |
| 73 | { | 225 | { |
| 226 | struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; | ||
| 227 | |||
| 74 | mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, | 228 | mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, |
| 75 | ARRAY_SIZE(mx51babbage_pads)); | 229 | ARRAY_SIZE(mx51babbage_pads)); |
| 76 | mxc_init_imx_uart(); | 230 | mxc_init_imx_uart(); |
| 77 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 231 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 232 | |||
| 233 | if (otg_mode_host) | ||
| 234 | mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); | ||
| 235 | else { | ||
| 236 | initialize_otg_port(NULL); | ||
| 237 | mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata); | ||
| 238 | } | ||
| 239 | |||
| 240 | gpio_usbh1_active(); | ||
| 241 | mxc_register_device(&mxc_usbh1_device, &usbh1_config); | ||
| 242 | /* setback USBH1_STP to be function */ | ||
| 243 | mxc_iomux_v3_setup_pad(&usbh1stp); | ||
| 244 | babbage_usbhub_reset(); | ||
| 78 | } | 245 | } |
| 79 | 246 | ||
| 80 | static void __init mx51_babbage_timer_init(void) | 247 | static void __init mx51_babbage_timer_init(void) |
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c index 1ee6ce4087b8..d9f612d3370e 100644 --- a/arch/arm/mach-mx5/clock-mx51.c +++ b/arch/arm/mach-mx5/clock-mx51.c | |||
| @@ -37,6 +37,7 @@ static struct clk lp_apm_clk; | |||
| 37 | static struct clk periph_apm_clk; | 37 | static struct clk periph_apm_clk; |
| 38 | static struct clk ahb_clk; | 38 | static struct clk ahb_clk; |
| 39 | static struct clk ipg_clk; | 39 | static struct clk ipg_clk; |
| 40 | static struct clk usboh3_clk; | ||
| 40 | 41 | ||
| 41 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ | 42 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ |
| 42 | 43 | ||
| @@ -570,6 +571,35 @@ static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) | |||
| 570 | return 0; | 571 | return 0; |
| 571 | } | 572 | } |
| 572 | 573 | ||
| 574 | static unsigned long clk_usboh3_get_rate(struct clk *clk) | ||
| 575 | { | ||
| 576 | u32 reg, prediv, podf; | ||
| 577 | unsigned long parent_rate; | ||
| 578 | |||
| 579 | parent_rate = clk_get_rate(clk->parent); | ||
| 580 | |||
| 581 | reg = __raw_readl(MXC_CCM_CSCDR1); | ||
| 582 | prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> | ||
| 583 | MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; | ||
| 584 | podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> | ||
| 585 | MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; | ||
| 586 | |||
| 587 | return parent_rate / (prediv * podf); | ||
| 588 | } | ||
| 589 | |||
| 590 | static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) | ||
| 591 | { | ||
| 592 | u32 reg, mux; | ||
| 593 | |||
| 594 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, | ||
| 595 | &lp_apm_clk); | ||
| 596 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; | ||
| 597 | reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; | ||
| 598 | __raw_writel(reg, MXC_CCM_CSCMR1); | ||
| 599 | |||
| 600 | return 0; | ||
| 601 | } | ||
| 602 | |||
| 573 | static unsigned long get_high_reference_clock_rate(struct clk *clk) | 603 | static unsigned long get_high_reference_clock_rate(struct clk *clk) |
| 574 | { | 604 | { |
| 575 | return external_high_reference; | 605 | return external_high_reference; |
| @@ -691,6 +721,12 @@ static struct clk uart_root_clk = { | |||
| 691 | .set_parent = _clk_uart_set_parent, | 721 | .set_parent = _clk_uart_set_parent, |
| 692 | }; | 722 | }; |
| 693 | 723 | ||
| 724 | static struct clk usboh3_clk = { | ||
| 725 | .parent = &pll2_sw_clk, | ||
| 726 | .get_rate = clk_usboh3_get_rate, | ||
| 727 | .set_parent = _clk_usboh3_set_parent, | ||
| 728 | }; | ||
| 729 | |||
| 694 | static struct clk ahb_max_clk = { | 730 | static struct clk ahb_max_clk = { |
| 695 | .parent = &ahb_clk, | 731 | .parent = &ahb_clk, |
| 696 | .enable_reg = MXC_CCM_CCGR0, | 732 | .enable_reg = MXC_CCM_CCGR0, |
| @@ -779,6 +815,12 @@ static struct clk_lookup lookups[] = { | |||
| 779 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | 815 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 780 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | 816 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) |
| 781 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | 817 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
| 818 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) | ||
| 819 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) | ||
| 820 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) | ||
| 821 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) | ||
| 822 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) | ||
| 823 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) | ||
| 782 | }; | 824 | }; |
| 783 | 825 | ||
| 784 | static void clk_tree_init(void) | 826 | static void clk_tree_init(void) |
| @@ -819,6 +861,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |||
| 819 | clk_enable(&cpu_clk); | 861 | clk_enable(&cpu_clk); |
| 820 | clk_enable(&main_bus_clk); | 862 | clk_enable(&main_bus_clk); |
| 821 | 863 | ||
| 864 | /* set the usboh3_clk parent to pll2_sw_clk */ | ||
| 865 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); | ||
| 866 | |||
| 822 | /* System timer */ | 867 | /* System timer */ |
| 823 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), | 868 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), |
| 824 | MX51_MXC_INT_GPT); | 869 | MX51_MXC_INT_GPT); |
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index d6fd3961ade9..7130449aacdc 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> | 2 | * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> |
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 3 | * | 4 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 5 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 6 | * License. You may obtain a copy of the GNU General Public License |
| @@ -10,8 +11,11 @@ | |||
| 10 | */ | 11 | */ |
| 11 | 12 | ||
| 12 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/dma-mapping.h> | ||
| 15 | #include <linux/gpio.h> | ||
| 13 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 14 | #include <mach/imx-uart.h> | 17 | #include <mach/imx-uart.h> |
| 18 | #include <mach/irqs.h> | ||
| 15 | 19 | ||
| 16 | static struct resource uart0[] = { | 20 | static struct resource uart0[] = { |
| 17 | { | 21 | { |
| @@ -89,8 +93,109 @@ struct platform_device mxc_fec_device = { | |||
| 89 | .resource = mxc_fec_resources, | 93 | .resource = mxc_fec_resources, |
| 90 | }; | 94 | }; |
| 91 | 95 | ||
| 92 | /* Dummy definition to allow compiling in AVIC and TZIC simultaneously */ | 96 | static u64 usb_dma_mask = DMA_BIT_MASK(32); |
| 97 | |||
| 98 | static struct resource usbotg_resources[] = { | ||
| 99 | { | ||
| 100 | .start = MX51_OTG_BASE_ADDR, | ||
| 101 | .end = MX51_OTG_BASE_ADDR + 0x1ff, | ||
| 102 | .flags = IORESOURCE_MEM, | ||
| 103 | }, | ||
| 104 | { | ||
| 105 | .start = MX51_MXC_INT_USB_OTG, | ||
| 106 | .flags = IORESOURCE_IRQ, | ||
| 107 | }, | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* OTG gadget device */ | ||
| 111 | struct platform_device mxc_usbdr_udc_device = { | ||
| 112 | .name = "fsl-usb2-udc", | ||
| 113 | .id = -1, | ||
| 114 | .num_resources = ARRAY_SIZE(usbotg_resources), | ||
| 115 | .resource = usbotg_resources, | ||
| 116 | .dev = { | ||
| 117 | .dma_mask = &usb_dma_mask, | ||
| 118 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 119 | }, | ||
| 120 | }; | ||
| 121 | |||
| 122 | struct platform_device mxc_usbdr_host_device = { | ||
| 123 | .name = "mxc-ehci", | ||
| 124 | .id = 0, | ||
| 125 | .num_resources = ARRAY_SIZE(usbotg_resources), | ||
| 126 | .resource = usbotg_resources, | ||
| 127 | .dev = { | ||
| 128 | .dma_mask = &usb_dma_mask, | ||
| 129 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 130 | }, | ||
| 131 | }; | ||
| 132 | |||
| 133 | static struct resource usbh1_resources[] = { | ||
| 134 | { | ||
| 135 | .start = MX51_OTG_BASE_ADDR + 0x200, | ||
| 136 | .end = MX51_OTG_BASE_ADDR + 0x200 + 0x1ff, | ||
| 137 | .flags = IORESOURCE_MEM, | ||
| 138 | }, | ||
| 139 | { | ||
| 140 | .start = MX51_MXC_INT_USB_H1, | ||
| 141 | .flags = IORESOURCE_IRQ, | ||
| 142 | }, | ||
| 143 | }; | ||
| 144 | |||
| 145 | struct platform_device mxc_usbh1_device = { | ||
| 146 | .name = "mxc-ehci", | ||
| 147 | .id = 1, | ||
| 148 | .num_resources = ARRAY_SIZE(usbh1_resources), | ||
| 149 | .resource = usbh1_resources, | ||
| 150 | .dev = { | ||
| 151 | .dma_mask = &usb_dma_mask, | ||
| 152 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 153 | }, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct resource mxc_wdt_resources[] = { | ||
| 157 | { | ||
| 158 | .start = MX51_WDOG_BASE_ADDR, | ||
| 159 | .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, | ||
| 160 | .flags = IORESOURCE_MEM, | ||
| 161 | }, | ||
| 162 | }; | ||
| 163 | |||
| 164 | struct platform_device mxc_wdt = { | ||
| 165 | .name = "imx2-wdt", | ||
| 166 | .id = 0, | ||
| 167 | .num_resources = ARRAY_SIZE(mxc_wdt_resources), | ||
| 168 | .resource = mxc_wdt_resources, | ||
| 169 | }; | ||
| 170 | |||
| 171 | static struct mxc_gpio_port mxc_gpio_ports[] = { | ||
| 172 | { | ||
| 173 | .chip.label = "gpio-0", | ||
| 174 | .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR), | ||
| 175 | .irq = MX51_MXC_INT_GPIO1_LOW, | ||
| 176 | .virtual_irq_start = MXC_GPIO_IRQ_START | ||
| 177 | }, | ||
| 178 | { | ||
| 179 | .chip.label = "gpio-1", | ||
| 180 | .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR), | ||
| 181 | .irq = MX51_MXC_INT_GPIO2_LOW, | ||
| 182 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1 | ||
| 183 | }, | ||
| 184 | { | ||
| 185 | .chip.label = "gpio-2", | ||
| 186 | .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR), | ||
| 187 | .irq = MX51_MXC_INT_GPIO3_LOW, | ||
| 188 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2 | ||
| 189 | }, | ||
| 190 | { | ||
| 191 | .chip.label = "gpio-3", | ||
| 192 | .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR), | ||
| 193 | .irq = MX51_MXC_INT_GPIO4_LOW, | ||
| 194 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 | ||
| 195 | }, | ||
| 196 | }; | ||
| 197 | |||
| 93 | int __init mxc_register_gpios(void) | 198 | int __init mxc_register_gpios(void) |
| 94 | { | 199 | { |
| 95 | return 0; | 200 | return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); |
| 96 | } | 201 | } |
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index f339ab8c19be..c879ae71cd5b 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h | |||
| @@ -2,3 +2,7 @@ extern struct platform_device mxc_uart_device0; | |||
| 2 | extern struct platform_device mxc_uart_device1; | 2 | extern struct platform_device mxc_uart_device1; |
| 3 | extern struct platform_device mxc_uart_device2; | 3 | extern struct platform_device mxc_uart_device2; |
| 4 | extern struct platform_device mxc_fec_device; | 4 | extern struct platform_device mxc_fec_device; |
| 5 | extern struct platform_device mxc_usbdr_host_device; | ||
| 6 | extern struct platform_device mxc_usbh1_device; | ||
| 7 | extern struct platform_device mxc_usbdr_udc_device; | ||
| 8 | extern struct platform_device mxc_wdt; | ||
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c index 60f5bee09f2e..2c471fc451d7 100644 --- a/arch/arm/mach-nomadik/clock.c +++ b/arch/arm/mach-nomadik/clock.c | |||
| @@ -56,6 +56,7 @@ static struct clk_lookup lookups[] = { | |||
| 56 | CLK(&clk_default, "gpio.1"), | 56 | CLK(&clk_default, "gpio.1"), |
| 57 | CLK(&clk_default, "gpio.2"), | 57 | CLK(&clk_default, "gpio.2"), |
| 58 | CLK(&clk_default, "gpio.3"), | 58 | CLK(&clk_default, "gpio.3"), |
| 59 | CLK(&clk_default, "rng"), | ||
| 59 | }; | 60 | }; |
| 60 | 61 | ||
| 61 | static int __init clk_init(void) | 62 | static int __init clk_init(void) |
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 091c98a639d9..cd3983ad4160 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h | |||
| @@ -114,6 +114,7 @@ | |||
| 114 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST | 114 | #define S3C_PA_USBHOST S3C2410_PA_USBHOST |
| 115 | #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC | 115 | #define S3C_PA_HSMMC0 S3C2443_PA_HSMMC |
| 116 | #define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0 | 116 | #define S3C_PA_HSMMC1 S3C2416_PA_HSMMC0 |
| 117 | #define S3C_PA_WDT S3C2410_PA_WATCHDOG | ||
| 117 | #define S3C_PA_NAND S3C24XX_PA_NAND | 118 | #define S3C_PA_NAND S3C24XX_PA_NAND |
| 118 | 119 | ||
| 119 | #endif /* __ASM_ARCH_MAP_H */ | 120 | #endif /* __ASM_ARCH_MAP_H */ |
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 69e9fbfea917..f5a59727949f 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig | |||
| @@ -7,6 +7,7 @@ | |||
| 7 | config PLAT_S3C64XX | 7 | config PLAT_S3C64XX |
| 8 | bool | 8 | bool |
| 9 | depends on ARCH_S3C64XX | 9 | depends on ARCH_S3C64XX |
| 10 | select SAMSUNG_WAKEMASK | ||
| 10 | default y | 11 | default y |
| 11 | help | 12 | help |
| 12 | Base platform code for any Samsung S3C64XX device | 13 | Base platform code for any Samsung S3C64XX device |
| @@ -35,6 +36,11 @@ config S3C64XX_SETUP_SDHCI | |||
| 35 | Internal configuration for default SDHCI setup for S3C6400 and | 36 | Internal configuration for default SDHCI setup for S3C6400 and |
| 36 | S3C6410 SoCs. | 37 | S3C6410 SoCs. |
| 37 | 38 | ||
| 39 | config S3C64XX_DEV_ONENAND1 | ||
| 40 | bool | ||
| 41 | help | ||
| 42 | Compile in platform device definition for OneNAND1 controller | ||
| 43 | |||
| 38 | # platform specific device setup | 44 | # platform specific device setup |
| 39 | 45 | ||
| 40 | config S3C64XX_SETUP_I2C0 | 46 | config S3C64XX_SETUP_I2C0 |
| @@ -90,8 +96,11 @@ config MACH_SMDK6410 | |||
| 90 | select S3C_DEV_HSMMC1 | 96 | select S3C_DEV_HSMMC1 |
| 91 | select S3C_DEV_I2C1 | 97 | select S3C_DEV_I2C1 |
| 92 | select S3C_DEV_FB | 98 | select S3C_DEV_FB |
| 99 | select SAMSUNG_DEV_TS | ||
| 93 | select S3C_DEV_USB_HOST | 100 | select S3C_DEV_USB_HOST |
| 94 | select S3C_DEV_USB_HSOTG | 101 | select S3C_DEV_USB_HSOTG |
| 102 | select S3C_DEV_WDT | ||
| 103 | select HAVE_S3C2410_WATCHDOG | ||
| 95 | select S3C64XX_SETUP_SDHCI | 104 | select S3C64XX_SETUP_SDHCI |
| 96 | select S3C64XX_SETUP_I2C1 | 105 | select S3C64XX_SETUP_I2C1 |
| 97 | select S3C64XX_SETUP_FB_24BPP | 106 | select S3C64XX_SETUP_FB_24BPP |
| @@ -179,3 +188,34 @@ config MACH_HMT | |||
| 179 | select HAVE_PWM | 188 | select HAVE_PWM |
| 180 | help | 189 | help |
| 181 | Machine support for the Airgoo HMT | 190 | Machine support for the Airgoo HMT |
| 191 | |||
| 192 | config MACH_SMARTQ | ||
| 193 | bool | ||
| 194 | select CPU_S3C6410 | ||
| 195 | select S3C_DEV_HSMMC | ||
| 196 | select S3C_DEV_HSMMC1 | ||
| 197 | select S3C_DEV_HSMMC2 | ||
| 198 | select S3C_DEV_FB | ||
| 199 | select S3C_DEV_HWMON | ||
| 200 | select S3C_DEV_RTC | ||
| 201 | select S3C_DEV_USB_HSOTG | ||
| 202 | select S3C_DEV_USB_HOST | ||
| 203 | select S3C64XX_SETUP_SDHCI | ||
| 204 | select S3C64XX_SETUP_FB_24BPP | ||
| 205 | select SAMSUNG_DEV_ADC | ||
| 206 | select SAMSUNG_DEV_TS | ||
| 207 | select HAVE_PWM | ||
| 208 | help | ||
| 209 | Shared machine support for SmartQ 5/7 | ||
| 210 | |||
| 211 | config MACH_SMARTQ5 | ||
| 212 | bool "SmartQ 5" | ||
| 213 | select MACH_SMARTQ | ||
| 214 | help | ||
| 215 | Machine support for the SmartQ 5 | ||
| 216 | |||
| 217 | config MACH_SMARTQ7 | ||
| 218 | bool "SmartQ 7" | ||
| 219 | select MACH_SMARTQ | ||
| 220 | help | ||
| 221 | Machine support for the SmartQ 7 | ||
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index a10f1fc6b023..9d1006938f5c 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
| @@ -52,6 +52,9 @@ obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o | |||
| 52 | obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o | 52 | obj-$(CONFIG_MACH_SMDK6410) += mach-smdk6410.o |
| 53 | obj-$(CONFIG_MACH_NCP) += mach-ncp.o | 53 | obj-$(CONFIG_MACH_NCP) += mach-ncp.o |
| 54 | obj-$(CONFIG_MACH_HMT) += mach-hmt.o | 54 | obj-$(CONFIG_MACH_HMT) += mach-hmt.o |
| 55 | obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o | ||
| 56 | obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o | ||
| 57 | obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o | ||
| 55 | 58 | ||
| 56 | # device support | 59 | # device support |
| 57 | 60 | ||
| @@ -59,3 +62,4 @@ obj-y += dev-uart.o | |||
| 59 | obj-y += dev-audio.o | 62 | obj-y += dev-audio.o |
| 60 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | 63 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o |
| 61 | obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o | 64 | obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o |
| 65 | obj-$(CONFIG_S3C64XX_DEV_ONENAND1) += dev-onenand1.o | ||
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c new file mode 100644 index 000000000000..92ffd5bac104 --- /dev/null +++ b/arch/arm/mach-s3c64xx/dev-onenand1.c | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s3c64xx/dev-onenand1.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008-2010 Samsung Electronics | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * | ||
| 7 | * S3C64XX series device definition for OneNAND devices | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/mtd/mtd.h> | ||
| 17 | #include <linux/mtd/onenand.h> | ||
| 18 | |||
| 19 | #include <mach/irqs.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | static struct resource s3c64xx_onenand1_resources[] = { | ||
| 23 | [0] = { | ||
| 24 | .start = S3C64XX_PA_ONENAND1, | ||
| 25 | .end = S3C64XX_PA_ONENAND1 + 0x400 - 1, | ||
| 26 | .flags = IORESOURCE_MEM, | ||
| 27 | }, | ||
| 28 | [1] = { | ||
| 29 | .start = S3C64XX_PA_ONENAND1_BUF, | ||
| 30 | .end = S3C64XX_PA_ONENAND1_BUF + S3C64XX_SZ_ONENAND1_BUF - 1, | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }, | ||
| 33 | [2] = { | ||
| 34 | .start = IRQ_ONENAND1, | ||
| 35 | .end = IRQ_ONENAND1, | ||
| 36 | .flags = IORESOURCE_IRQ, | ||
| 37 | }, | ||
| 38 | }; | ||
| 39 | |||
| 40 | struct platform_device s3c64xx_device_onenand1 = { | ||
| 41 | .name = "samsung-onenand", | ||
| 42 | .id = 1, | ||
| 43 | .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources), | ||
| 44 | .resource = s3c64xx_onenand1_resources, | ||
| 45 | }; | ||
| 46 | |||
| 47 | void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata) | ||
| 48 | { | ||
| 49 | struct onenand_platform_data *pd; | ||
| 50 | |||
| 51 | pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); | ||
| 52 | if (!pd) | ||
| 53 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
| 54 | s3c64xx_device_onenand1.dev.platform_data = pd; | ||
| 55 | } | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h index e9ab4ac0b9a8..8e2df26cf14a 100644 --- a/arch/arm/mach-s3c64xx/include/mach/irqs.h +++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h | |||
| @@ -212,5 +212,9 @@ | |||
| 212 | 212 | ||
| 213 | #define NR_IRQS (IRQ_BOARD_END + 1) | 213 | #define NR_IRQS (IRQ_BOARD_END + 1) |
| 214 | 214 | ||
| 215 | /* Compatibility */ | ||
| 216 | |||
| 217 | #define IRQ_ONENAND IRQ_ONENAND0 | ||
| 218 | |||
| 215 | #endif /* __ASM_MACH_S3C64XX_IRQS_H */ | 219 | #endif /* __ASM_MACH_S3C64XX_IRQS_H */ |
| 216 | 220 | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h index 9fdd50c8c767..e1eab3c94aea 100644 --- a/arch/arm/mach-s3c64xx/include/mach/map.h +++ b/arch/arm/mach-s3c64xx/include/mach/map.h | |||
| @@ -52,6 +52,16 @@ | |||
| 52 | 52 | ||
| 53 | #define S3C64XX_PA_SROM (0x70000000) | 53 | #define S3C64XX_PA_SROM (0x70000000) |
| 54 | 54 | ||
| 55 | #define S3C64XX_PA_ONENAND0 (0x70100000) | ||
| 56 | #define S3C64XX_PA_ONENAND0_BUF (0x20000000) | ||
| 57 | #define S3C64XX_SZ_ONENAND0_BUF (SZ_64M) | ||
| 58 | |||
| 59 | /* NAND and OneNAND1 controllers occupy the same register region | ||
| 60 | (depending on SoC POP version) */ | ||
| 61 | #define S3C64XX_PA_ONENAND1 (0x70200000) | ||
| 62 | #define S3C64XX_PA_ONENAND1_BUF (0x28000000) | ||
| 63 | #define S3C64XX_SZ_ONENAND1_BUF (SZ_64M) | ||
| 64 | |||
| 55 | #define S3C64XX_PA_NAND (0x70200000) | 65 | #define S3C64XX_PA_NAND (0x70200000) |
| 56 | #define S3C64XX_PA_FB (0x77100000) | 66 | #define S3C64XX_PA_FB (0x77100000) |
| 57 | #define S3C64XX_PA_USB_HSOTG (0x7C000000) | 67 | #define S3C64XX_PA_USB_HSOTG (0x7C000000) |
| @@ -99,11 +109,15 @@ | |||
| 99 | #define S3C_PA_IIC S3C64XX_PA_IIC0 | 109 | #define S3C_PA_IIC S3C64XX_PA_IIC0 |
| 100 | #define S3C_PA_IIC1 S3C64XX_PA_IIC1 | 110 | #define S3C_PA_IIC1 S3C64XX_PA_IIC1 |
| 101 | #define S3C_PA_NAND S3C64XX_PA_NAND | 111 | #define S3C_PA_NAND S3C64XX_PA_NAND |
| 112 | #define S3C_PA_ONENAND S3C64XX_PA_ONENAND0 | ||
| 113 | #define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF | ||
| 114 | #define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF | ||
| 102 | #define S3C_PA_FB S3C64XX_PA_FB | 115 | #define S3C_PA_FB S3C64XX_PA_FB |
| 103 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST | 116 | #define S3C_PA_USBHOST S3C64XX_PA_USBHOST |
| 104 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG | 117 | #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG |
| 105 | #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY | 118 | #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY |
| 106 | #define S3C_PA_RTC S3C64XX_PA_RTC | 119 | #define S3C_PA_RTC S3C64XX_PA_RTC |
| 120 | #define S3C_PA_WDT S3C64XX_PA_WATCHDOG | ||
| 107 | 121 | ||
| 108 | #define SAMSUNG_PA_ADC S3C64XX_PA_ADC | 122 | #define SAMSUNG_PA_ADC S3C64XX_PA_ADC |
| 109 | 123 | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c new file mode 100644 index 000000000000..028d080dcd35 --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq.c | |||
| @@ -0,0 +1,363 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s3c64xx/mach-smartq.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Maurus Cuelenaere | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/delay.h> | ||
| 13 | #include <linux/fb.h> | ||
| 14 | #include <linux/gpio.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/pwm_backlight.h> | ||
| 18 | #include <linux/serial_core.h> | ||
| 19 | #include <linux/usb/gpio_vbus.h> | ||
| 20 | |||
| 21 | #include <asm/mach-types.h> | ||
| 22 | #include <asm/mach/map.h> | ||
| 23 | |||
| 24 | #include <mach/map.h> | ||
| 25 | #include <mach/regs-gpio.h> | ||
| 26 | #include <mach/regs-modem.h> | ||
| 27 | |||
| 28 | #include <plat/clock.h> | ||
| 29 | #include <plat/cpu.h> | ||
| 30 | #include <plat/devs.h> | ||
| 31 | #include <plat/iic.h> | ||
| 32 | #include <plat/gpio-cfg.h> | ||
| 33 | #include <plat/hwmon.h> | ||
| 34 | #include <plat/regs-serial.h> | ||
| 35 | #include <plat/udc-hs.h> | ||
| 36 | #include <plat/usb-control.h> | ||
| 37 | #include <plat/sdhci.h> | ||
| 38 | #include <plat/ts.h> | ||
| 39 | |||
| 40 | #include <video/platform_lcd.h> | ||
| 41 | |||
| 42 | #define UCON S3C2410_UCON_DEFAULT | ||
| 43 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE) | ||
| 44 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | ||
| 45 | |||
| 46 | static struct s3c2410_uartcfg smartq_uartcfgs[] __initdata = { | ||
| 47 | [0] = { | ||
| 48 | .hwport = 0, | ||
| 49 | .flags = 0, | ||
| 50 | .ucon = UCON, | ||
| 51 | .ulcon = ULCON, | ||
| 52 | .ufcon = UFCON, | ||
| 53 | }, | ||
| 54 | [1] = { | ||
| 55 | .hwport = 1, | ||
| 56 | .flags = 0, | ||
| 57 | .ucon = UCON, | ||
| 58 | .ulcon = ULCON, | ||
| 59 | .ufcon = UFCON, | ||
| 60 | }, | ||
| 61 | [2] = { | ||
| 62 | .hwport = 2, | ||
| 63 | .flags = 0, | ||
| 64 | .ucon = UCON, | ||
| 65 | .ulcon = ULCON, | ||
| 66 | .ufcon = UFCON, | ||
| 67 | }, | ||
| 68 | }; | ||
| 69 | |||
| 70 | static void smartq_usb_host_powercontrol(int port, int to) | ||
| 71 | { | ||
| 72 | pr_debug("%s(%d, %d)\n", __func__, port, to); | ||
| 73 | |||
| 74 | if (port == 0) { | ||
| 75 | gpio_set_value(S3C64XX_GPL(0), to); | ||
| 76 | gpio_set_value(S3C64XX_GPL(1), to); | ||
| 77 | } | ||
| 78 | } | ||
| 79 | |||
| 80 | static irqreturn_t smartq_usb_host_ocirq(int irq, void *pw) | ||
| 81 | { | ||
| 82 | struct s3c2410_hcd_info *info = pw; | ||
| 83 | |||
| 84 | if (gpio_get_value(S3C64XX_GPL(10)) == 0) { | ||
| 85 | pr_debug("%s: over-current irq (oc detected)\n", __func__); | ||
| 86 | s3c2410_usb_report_oc(info, 3); | ||
| 87 | } else { | ||
| 88 | pr_debug("%s: over-current irq (oc cleared)\n", __func__); | ||
| 89 | s3c2410_usb_report_oc(info, 0); | ||
| 90 | } | ||
| 91 | |||
| 92 | return IRQ_HANDLED; | ||
| 93 | } | ||
| 94 | |||
| 95 | static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on) | ||
| 96 | { | ||
| 97 | int ret; | ||
| 98 | |||
| 99 | /* This isn't present on a SmartQ 5 board */ | ||
| 100 | if (machine_is_smartq5()) | ||
| 101 | return; | ||
| 102 | |||
| 103 | if (on) { | ||
| 104 | ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)), | ||
| 105 | smartq_usb_host_ocirq, IRQF_DISABLED | | ||
| 106 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | ||
| 107 | "USB host overcurrent", info); | ||
| 108 | if (ret != 0) | ||
| 109 | pr_err("failed to request usb oc irq: %d\n", ret); | ||
| 110 | } else { | ||
| 111 | free_irq(gpio_to_irq(S3C64XX_GPL(10)), info); | ||
| 112 | } | ||
| 113 | } | ||
| 114 | |||
| 115 | static struct s3c2410_hcd_info smartq_usb_host_info = { | ||
| 116 | .port[0] = { | ||
| 117 | .flags = S3C_HCDFLG_USED | ||
| 118 | }, | ||
| 119 | .port[1] = { | ||
| 120 | .flags = 0 | ||
| 121 | }, | ||
| 122 | |||
| 123 | .power_control = smartq_usb_host_powercontrol, | ||
| 124 | .enable_oc = smartq_usb_host_enableoc, | ||
| 125 | }; | ||
| 126 | |||
| 127 | static struct gpio_vbus_mach_info smartq_usb_otg_vbus_pdata = { | ||
| 128 | .gpio_vbus = S3C64XX_GPL(9), | ||
| 129 | .gpio_pullup = -1, | ||
| 130 | .gpio_vbus_inverted = true, | ||
| 131 | }; | ||
| 132 | |||
| 133 | static struct platform_device smartq_usb_otg_vbus_dev = { | ||
| 134 | .name = "gpio-vbus", | ||
| 135 | .dev.platform_data = &smartq_usb_otg_vbus_pdata, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static int __init smartq_bl_init(struct device *dev) | ||
| 139 | { | ||
| 140 | s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2)); | ||
| 141 | |||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | static struct platform_pwm_backlight_data smartq_backlight_data = { | ||
| 146 | .pwm_id = 1, | ||
| 147 | .max_brightness = 1000, | ||
| 148 | .dft_brightness = 600, | ||
| 149 | .pwm_period_ns = 1000000000 / (1000 * 20), | ||
| 150 | .init = smartq_bl_init, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static struct platform_device smartq_backlight_device = { | ||
| 154 | .name = "pwm-backlight", | ||
| 155 | .dev = { | ||
| 156 | .parent = &s3c_device_timer[1].dev, | ||
| 157 | .platform_data = &smartq_backlight_data, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct s3c2410_ts_mach_info smartq_touchscreen_pdata __initdata = { | ||
| 162 | .delay = 65535, | ||
| 163 | .presc = 99, | ||
| 164 | .oversampling_shift = 4, | ||
| 165 | }; | ||
| 166 | |||
| 167 | static struct s3c_sdhci_platdata smartq_internal_hsmmc_pdata = { | ||
| 168 | .max_width = 4, | ||
| 169 | /*.broken_card_detection = true,*/ | ||
| 170 | }; | ||
| 171 | |||
| 172 | static struct s3c_hwmon_pdata smartq_hwmon_pdata __initdata = { | ||
| 173 | /* Battery voltage (?-4.2V) */ | ||
| 174 | .in[0] = &(struct s3c_hwmon_chcfg) { | ||
| 175 | .name = "smartq:battery-voltage", | ||
| 176 | .mult = 3300, | ||
| 177 | .div = 2048, | ||
| 178 | }, | ||
| 179 | /* Reference voltage (1.2V) */ | ||
| 180 | .in[1] = &(struct s3c_hwmon_chcfg) { | ||
| 181 | .name = "smartq:reference-voltage", | ||
| 182 | .mult = 3300, | ||
| 183 | .div = 4096, | ||
| 184 | }, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static void smartq_lcd_power_set(struct plat_lcd_data *pd, unsigned int power) | ||
| 188 | { | ||
| 189 | gpio_direction_output(S3C64XX_GPM(3), power); | ||
| 190 | } | ||
| 191 | |||
| 192 | static struct plat_lcd_data smartq_lcd_power_data = { | ||
| 193 | .set_power = smartq_lcd_power_set, | ||
| 194 | }; | ||
| 195 | |||
| 196 | static struct platform_device smartq_lcd_power_device = { | ||
| 197 | .name = "platform-lcd", | ||
| 198 | .dev.parent = &s3c_device_fb.dev, | ||
| 199 | .dev.platform_data = &smartq_lcd_power_data, | ||
| 200 | }; | ||
| 201 | |||
| 202 | |||
| 203 | static struct platform_device *smartq_devices[] __initdata = { | ||
| 204 | &s3c_device_hsmmc1, /* Init iNAND first, ... */ | ||
| 205 | &s3c_device_hsmmc0, /* ... then the external SD card */ | ||
| 206 | &s3c_device_hsmmc2, | ||
| 207 | &s3c_device_adc, | ||
| 208 | &s3c_device_fb, | ||
| 209 | &s3c_device_hwmon, | ||
| 210 | &s3c_device_i2c0, | ||
| 211 | &s3c_device_ohci, | ||
| 212 | &s3c_device_rtc, | ||
| 213 | &s3c_device_timer[1], | ||
| 214 | &s3c_device_ts, | ||
| 215 | &s3c_device_usb_hsotg, | ||
| 216 | &smartq_backlight_device, | ||
| 217 | &smartq_lcd_power_device, | ||
| 218 | &smartq_usb_otg_vbus_dev, | ||
| 219 | }; | ||
| 220 | |||
| 221 | static void __init smartq_lcd_mode_set(void) | ||
| 222 | { | ||
| 223 | u32 tmp; | ||
| 224 | |||
| 225 | /* set the LCD type */ | ||
| 226 | tmp = __raw_readl(S3C64XX_SPCON); | ||
| 227 | tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK; | ||
| 228 | tmp |= S3C64XX_SPCON_LCD_SEL_RGB; | ||
| 229 | __raw_writel(tmp, S3C64XX_SPCON); | ||
| 230 | |||
| 231 | /* remove the LCD bypass */ | ||
| 232 | tmp = __raw_readl(S3C64XX_MODEM_MIFPCON); | ||
| 233 | tmp &= ~MIFPCON_LCD_BYPASS; | ||
| 234 | __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); | ||
| 235 | } | ||
| 236 | |||
| 237 | static void smartq_power_off(void) | ||
| 238 | { | ||
| 239 | gpio_direction_output(S3C64XX_GPK(15), 1); | ||
| 240 | } | ||
| 241 | |||
| 242 | static int __init smartq_power_off_init(void) | ||
| 243 | { | ||
| 244 | int ret; | ||
| 245 | |||
| 246 | ret = gpio_request(S3C64XX_GPK(15), "Power control"); | ||
| 247 | if (ret < 0) { | ||
| 248 | pr_err("%s: failed to get GPK15\n", __func__); | ||
| 249 | return ret; | ||
| 250 | } | ||
| 251 | |||
| 252 | /* leave power on */ | ||
| 253 | gpio_direction_output(S3C64XX_GPK(15), 0); | ||
| 254 | |||
| 255 | |||
| 256 | pm_power_off = smartq_power_off; | ||
| 257 | |||
| 258 | return ret; | ||
| 259 | } | ||
| 260 | |||
| 261 | static int __init smartq_usb_host_init(void) | ||
| 262 | { | ||
| 263 | int ret; | ||
| 264 | |||
| 265 | ret = gpio_request(S3C64XX_GPL(0), "USB power control"); | ||
| 266 | if (ret < 0) { | ||
| 267 | pr_err("%s: failed to get GPL0\n", __func__); | ||
| 268 | return ret; | ||
| 269 | } | ||
| 270 | |||
| 271 | ret = gpio_request(S3C64XX_GPL(1), "USB host power control"); | ||
| 272 | if (ret < 0) { | ||
| 273 | pr_err("%s: failed to get GPL1\n", __func__); | ||
| 274 | goto err; | ||
| 275 | } | ||
| 276 | |||
| 277 | if (!machine_is_smartq5()) { | ||
| 278 | /* This isn't present on a SmartQ 5 board */ | ||
| 279 | ret = gpio_request(S3C64XX_GPL(10), "USB host overcurrent"); | ||
| 280 | if (ret < 0) { | ||
| 281 | pr_err("%s: failed to get GPL10\n", __func__); | ||
| 282 | goto err2; | ||
| 283 | } | ||
| 284 | } | ||
| 285 | |||
| 286 | /* turn power off */ | ||
| 287 | gpio_direction_output(S3C64XX_GPL(0), 0); | ||
| 288 | gpio_direction_output(S3C64XX_GPL(1), 0); | ||
| 289 | if (!machine_is_smartq5()) | ||
| 290 | gpio_direction_input(S3C64XX_GPL(10)); | ||
| 291 | |||
| 292 | s3c_device_ohci.dev.platform_data = &smartq_usb_host_info; | ||
| 293 | |||
| 294 | return 0; | ||
| 295 | |||
| 296 | err2: | ||
| 297 | gpio_free(S3C64XX_GPL(1)); | ||
| 298 | err: | ||
| 299 | gpio_free(S3C64XX_GPL(0)); | ||
| 300 | return ret; | ||
| 301 | } | ||
| 302 | |||
| 303 | static int __init smartq_usb_otg_init(void) | ||
| 304 | { | ||
| 305 | clk_xusbxti.rate = 12000000; | ||
| 306 | |||
| 307 | return 0; | ||
| 308 | } | ||
| 309 | |||
| 310 | static int __init smartq_wifi_init(void) | ||
| 311 | { | ||
| 312 | int ret; | ||
| 313 | |||
| 314 | ret = gpio_request(S3C64XX_GPK(1), "wifi control"); | ||
| 315 | if (ret < 0) { | ||
| 316 | pr_err("%s: failed to get GPK1\n", __func__); | ||
| 317 | return ret; | ||
| 318 | } | ||
| 319 | |||
| 320 | ret = gpio_request(S3C64XX_GPK(2), "wifi reset"); | ||
| 321 | if (ret < 0) { | ||
| 322 | pr_err("%s: failed to get GPK2\n", __func__); | ||
| 323 | gpio_free(S3C64XX_GPK(1)); | ||
| 324 | return ret; | ||
| 325 | } | ||
| 326 | |||
| 327 | /* turn power on */ | ||
| 328 | gpio_direction_output(S3C64XX_GPK(1), 1); | ||
| 329 | |||
| 330 | /* reset device */ | ||
| 331 | gpio_direction_output(S3C64XX_GPK(2), 0); | ||
| 332 | mdelay(100); | ||
| 333 | gpio_set_value(S3C64XX_GPK(2), 1); | ||
| 334 | gpio_direction_input(S3C64XX_GPK(2)); | ||
| 335 | |||
| 336 | return 0; | ||
| 337 | } | ||
| 338 | |||
| 339 | static struct map_desc smartq_iodesc[] __initdata = {}; | ||
| 340 | void __init smartq_map_io(void) | ||
| 341 | { | ||
| 342 | s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc)); | ||
| 343 | s3c24xx_init_clocks(12000000); | ||
| 344 | s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs)); | ||
| 345 | |||
| 346 | smartq_lcd_mode_set(); | ||
| 347 | } | ||
| 348 | |||
| 349 | void __init smartq_machine_init(void) | ||
| 350 | { | ||
| 351 | s3c_i2c0_set_platdata(NULL); | ||
| 352 | s3c_hwmon_set_platdata(&smartq_hwmon_pdata); | ||
| 353 | s3c_sdhci1_set_platdata(&smartq_internal_hsmmc_pdata); | ||
| 354 | s3c_sdhci2_set_platdata(&smartq_internal_hsmmc_pdata); | ||
| 355 | s3c24xx_ts_set_platdata(&smartq_touchscreen_pdata); | ||
| 356 | |||
| 357 | WARN_ON(smartq_power_off_init()); | ||
| 358 | WARN_ON(smartq_usb_host_init()); | ||
| 359 | WARN_ON(smartq_usb_otg_init()); | ||
| 360 | WARN_ON(smartq_wifi_init()); | ||
| 361 | |||
| 362 | platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices)); | ||
| 363 | } | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.h b/arch/arm/mach-s3c64xx/mach-smartq.h new file mode 100644 index 000000000000..8e8b693db3af --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq.h | |||
| @@ -0,0 +1,20 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s3c64xx/mach-smartq.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Maurus Cuelenaere | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __MACH_SMARTQ_H | ||
| 13 | #define __MACH_SMARTQ_H __FILE__ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | |||
| 17 | extern void __init smartq_map_io(void); | ||
| 18 | extern void __init smartq_machine_init(void); | ||
| 19 | |||
| 20 | #endif /* __MACH_SMARTQ_H */ | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c new file mode 100644 index 000000000000..1d0326ead90f --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c | |||
| @@ -0,0 +1,185 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s3c64xx/mach-smartq5.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Maurus Cuelenaere | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/fb.h> | ||
| 13 | #include <linux/gpio.h> | ||
| 14 | #include <linux/gpio_keys.h> | ||
| 15 | #include <linux/i2c-gpio.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/input.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | |||
| 21 | #include <asm/mach-types.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | |||
| 24 | #include <mach/map.h> | ||
| 25 | #include <mach/regs-fb.h> | ||
| 26 | #include <mach/regs-gpio.h> | ||
| 27 | #include <mach/s3c6410.h> | ||
| 28 | |||
| 29 | #include <plat/cpu.h> | ||
| 30 | #include <plat/devs.h> | ||
| 31 | #include <plat/fb.h> | ||
| 32 | #include <plat/gpio-cfg.h> | ||
| 33 | |||
| 34 | #include "mach-smartq.h" | ||
| 35 | |||
| 36 | static void __init smartq5_lcd_setup_gpio(void) | ||
| 37 | { | ||
| 38 | gpio_request(S3C64XX_GPM(0), "LCD SCEN pin"); | ||
| 39 | gpio_request(S3C64XX_GPM(1), "LCD SCL pin"); | ||
| 40 | gpio_request(S3C64XX_GPM(2), "LCD SDA pin"); | ||
| 41 | gpio_request(S3C64XX_GPM(3), "LCD power"); | ||
| 42 | |||
| 43 | /* turn power off */ | ||
| 44 | gpio_direction_output(S3C64XX_GPM(0), 1); | ||
| 45 | gpio_direction_input(S3C64XX_GPM(1)); | ||
| 46 | gpio_direction_input(S3C64XX_GPM(2)); | ||
| 47 | gpio_direction_output(S3C64XX_GPM(3), 0); | ||
| 48 | } | ||
| 49 | |||
| 50 | static struct i2c_gpio_platform_data smartq5_lcd_control = { | ||
| 51 | .sda_pin = S3C64XX_GPM(2), | ||
| 52 | .scl_pin = S3C64XX_GPM(1), | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct platform_device smartq5_lcd_control_device = { | ||
| 56 | .name = "i2c-gpio", | ||
| 57 | .id = 1, | ||
| 58 | .dev.platform_data = &smartq5_lcd_control, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct gpio_led smartq5_leds[] __initdata = { | ||
| 62 | { | ||
| 63 | .name = "smartq5:green", | ||
| 64 | .active_low = 1, | ||
| 65 | .gpio = S3C64XX_GPN(8), | ||
| 66 | }, | ||
| 67 | { | ||
| 68 | .name = "smartq5:red", | ||
| 69 | .active_low = 1, | ||
| 70 | .gpio = S3C64XX_GPN(9), | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct gpio_led_platform_data smartq5_led_data = { | ||
| 75 | .num_leds = ARRAY_SIZE(smartq5_leds), | ||
| 76 | .leds = smartq5_leds, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct platform_device smartq5_leds_device = { | ||
| 80 | .name = "leds-gpio", | ||
| 81 | .id = -1, | ||
| 82 | .dev.platform_data = &smartq5_led_data, | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* Labels according to the SmartQ manual */ | ||
| 86 | static struct gpio_keys_button smartq5_buttons[] = { | ||
| 87 | { | ||
| 88 | .gpio = S3C64XX_GPL(14), | ||
| 89 | .code = KEY_POWER, | ||
| 90 | .desc = "Power", | ||
| 91 | .active_low = 1, | ||
| 92 | .debounce_interval = 5, | ||
| 93 | .type = EV_KEY, | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .gpio = S3C64XX_GPN(2), | ||
| 97 | .code = KEY_KPMINUS, | ||
| 98 | .desc = "Minus", | ||
| 99 | .active_low = 1, | ||
| 100 | .debounce_interval = 5, | ||
| 101 | .type = EV_KEY, | ||
| 102 | }, | ||
| 103 | { | ||
| 104 | .gpio = S3C64XX_GPN(12), | ||
| 105 | .code = KEY_KPPLUS, | ||
| 106 | .desc = "Plus", | ||
| 107 | .active_low = 1, | ||
| 108 | .debounce_interval = 5, | ||
| 109 | .type = EV_KEY, | ||
| 110 | }, | ||
| 111 | { | ||
| 112 | .gpio = S3C64XX_GPN(15), | ||
| 113 | .code = KEY_ENTER, | ||
| 114 | .desc = "Move", | ||
| 115 | .active_low = 1, | ||
| 116 | .debounce_interval = 5, | ||
| 117 | .type = EV_KEY, | ||
| 118 | }, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct gpio_keys_platform_data smartq5_buttons_data = { | ||
| 122 | .buttons = smartq5_buttons, | ||
| 123 | .nbuttons = ARRAY_SIZE(smartq5_buttons), | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct platform_device smartq5_buttons_device = { | ||
| 127 | .name = "gpio-keys", | ||
| 128 | .id = 0, | ||
| 129 | .num_resources = 0, | ||
| 130 | .dev = { | ||
| 131 | .platform_data = &smartq5_buttons_data, | ||
| 132 | } | ||
| 133 | }; | ||
| 134 | |||
| 135 | static struct s3c_fb_pd_win smartq5_fb_win0 = { | ||
| 136 | .win_mode = { | ||
| 137 | .pixclock = 1000000000000ULL / | ||
| 138 | ((40+1+216+800)*(10+1+35+480)*80), | ||
| 139 | .left_margin = 40, | ||
| 140 | .right_margin = 216, | ||
| 141 | .upper_margin = 10, | ||
| 142 | .lower_margin = 35, | ||
| 143 | .hsync_len = 1, | ||
| 144 | .vsync_len = 1, | ||
| 145 | .xres = 800, | ||
| 146 | .yres = 480, | ||
| 147 | }, | ||
| 148 | .max_bpp = 32, | ||
| 149 | .default_bpp = 16, | ||
| 150 | }; | ||
| 151 | |||
| 152 | static struct s3c_fb_platdata smartq5_lcd_pdata __initdata = { | ||
| 153 | .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, | ||
| 154 | .win[0] = &smartq5_fb_win0, | ||
| 155 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
| 156 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | | ||
| 157 | VIDCON1_INV_VDEN, | ||
| 158 | }; | ||
| 159 | |||
| 160 | static struct platform_device *smartq5_devices[] __initdata = { | ||
| 161 | &smartq5_leds_device, | ||
| 162 | &smartq5_buttons_device, | ||
| 163 | &smartq5_lcd_control_device, | ||
| 164 | }; | ||
| 165 | |||
| 166 | static void __init smartq5_machine_init(void) | ||
| 167 | { | ||
| 168 | s3c_fb_set_platdata(&smartq5_lcd_pdata); | ||
| 169 | |||
| 170 | smartq_machine_init(); | ||
| 171 | smartq5_lcd_setup_gpio(); | ||
| 172 | |||
| 173 | platform_add_devices(smartq5_devices, ARRAY_SIZE(smartq5_devices)); | ||
| 174 | } | ||
| 175 | |||
| 176 | MACHINE_START(SMARTQ5, "SmartQ 5") | ||
| 177 | /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ | ||
| 178 | .phys_io = S3C_PA_UART & 0xfff00000, | ||
| 179 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | ||
| 180 | .boot_params = S3C64XX_PA_SDRAM + 0x100, | ||
| 181 | .init_irq = s3c6410_init_irq, | ||
| 182 | .map_io = smartq_map_io, | ||
| 183 | .init_machine = smartq5_machine_init, | ||
| 184 | .timer = &s3c24xx_timer, | ||
| 185 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c new file mode 100644 index 000000000000..e0bc78ecb156 --- /dev/null +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c | |||
| @@ -0,0 +1,201 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s3c64xx/mach-smartq7.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2010 Maurus Cuelenaere | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/fb.h> | ||
| 13 | #include <linux/gpio.h> | ||
| 14 | #include <linux/gpio_keys.h> | ||
| 15 | #include <linux/i2c-gpio.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/input.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | |||
| 21 | #include <asm/mach-types.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | |||
| 24 | #include <mach/map.h> | ||
| 25 | #include <mach/regs-fb.h> | ||
| 26 | #include <mach/regs-gpio.h> | ||
| 27 | #include <mach/s3c6410.h> | ||
| 28 | |||
| 29 | #include <plat/cpu.h> | ||
| 30 | #include <plat/devs.h> | ||
| 31 | #include <plat/fb.h> | ||
| 32 | #include <plat/gpio-cfg.h> | ||
| 33 | |||
| 34 | #include "mach-smartq.h" | ||
| 35 | |||
| 36 | static void __init smartq7_lcd_setup_gpio(void) | ||
| 37 | { | ||
| 38 | gpio_request(S3C64XX_GPM(0), "LCD CSB pin"); | ||
| 39 | gpio_request(S3C64XX_GPM(3), "LCD power"); | ||
| 40 | gpio_request(S3C64XX_GPM(4), "LCD power status"); | ||
| 41 | |||
| 42 | /* turn power off */ | ||
| 43 | gpio_direction_output(S3C64XX_GPM(0), 1); | ||
| 44 | gpio_direction_output(S3C64XX_GPM(3), 0); | ||
| 45 | gpio_direction_input(S3C64XX_GPM(4)); | ||
| 46 | } | ||
| 47 | |||
| 48 | static struct i2c_gpio_platform_data smartq7_lcd_control = { | ||
| 49 | .sda_pin = S3C64XX_GPM(2), | ||
| 50 | .scl_pin = S3C64XX_GPM(1), | ||
| 51 | .sda_is_open_drain = 1, | ||
| 52 | .scl_is_open_drain = 1, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct platform_device smartq7_lcd_control_device = { | ||
| 56 | .name = "i2c-gpio", | ||
| 57 | .id = 1, | ||
| 58 | .dev.platform_data = &smartq7_lcd_control, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct gpio_led smartq7_leds[] __initdata = { | ||
| 62 | { | ||
| 63 | .name = "smartq7:red", | ||
| 64 | .active_low = 1, | ||
| 65 | .gpio = S3C64XX_GPN(8), | ||
| 66 | }, | ||
| 67 | { | ||
| 68 | .name = "smartq7:green", | ||
| 69 | .active_low = 1, | ||
| 70 | .gpio = S3C64XX_GPN(9), | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct gpio_led_platform_data smartq7_led_data = { | ||
| 75 | .num_leds = ARRAY_SIZE(smartq7_leds), | ||
| 76 | .leds = smartq7_leds, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct platform_device smartq7_leds_device = { | ||
| 80 | .name = "leds-gpio", | ||
| 81 | .id = -1, | ||
| 82 | .dev.platform_data = &smartq7_led_data, | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* Labels according to the SmartQ manual */ | ||
| 86 | static struct gpio_keys_button smartq7_buttons[] = { | ||
| 87 | { | ||
| 88 | .gpio = S3C64XX_GPL(14), | ||
| 89 | .code = KEY_POWER, | ||
| 90 | .desc = "Power", | ||
| 91 | .active_low = 1, | ||
| 92 | .debounce_interval = 5, | ||
| 93 | .type = EV_KEY, | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .gpio = S3C64XX_GPN(2), | ||
| 97 | .code = KEY_FN, | ||
| 98 | .desc = "Function", | ||
| 99 | .active_low = 1, | ||
| 100 | .debounce_interval = 5, | ||
| 101 | .type = EV_KEY, | ||
| 102 | }, | ||
| 103 | { | ||
| 104 | .gpio = S3C64XX_GPN(3), | ||
| 105 | .code = KEY_KPMINUS, | ||
| 106 | .desc = "Minus", | ||
| 107 | .active_low = 1, | ||
| 108 | .debounce_interval = 5, | ||
| 109 | .type = EV_KEY, | ||
| 110 | }, | ||
| 111 | { | ||
| 112 | .gpio = S3C64XX_GPN(4), | ||
| 113 | .code = KEY_KPPLUS, | ||
| 114 | .desc = "Plus", | ||
| 115 | .active_low = 1, | ||
| 116 | .debounce_interval = 5, | ||
| 117 | .type = EV_KEY, | ||
| 118 | }, | ||
| 119 | { | ||
| 120 | .gpio = S3C64XX_GPN(12), | ||
| 121 | .code = KEY_ENTER, | ||
| 122 | .desc = "Enter", | ||
| 123 | .active_low = 1, | ||
| 124 | .debounce_interval = 5, | ||
| 125 | .type = EV_KEY, | ||
| 126 | }, | ||
| 127 | { | ||
| 128 | .gpio = S3C64XX_GPN(15), | ||
| 129 | .code = KEY_ESC, | ||
| 130 | .desc = "Cancel", | ||
| 131 | .active_low = 1, | ||
| 132 | .debounce_interval = 5, | ||
| 133 | .type = EV_KEY, | ||
| 134 | }, | ||
| 135 | }; | ||
| 136 | |||
| 137 | static struct gpio_keys_platform_data smartq7_buttons_data = { | ||
| 138 | .buttons = smartq7_buttons, | ||
| 139 | .nbuttons = ARRAY_SIZE(smartq7_buttons), | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct platform_device smartq7_buttons_device = { | ||
| 143 | .name = "gpio-keys", | ||
| 144 | .id = 0, | ||
| 145 | .num_resources = 0, | ||
| 146 | .dev = { | ||
| 147 | .platform_data = &smartq7_buttons_data, | ||
| 148 | } | ||
| 149 | }; | ||
| 150 | |||
| 151 | static struct s3c_fb_pd_win smartq7_fb_win0 = { | ||
| 152 | .win_mode = { | ||
| 153 | .pixclock = 1000000000000ULL / | ||
| 154 | ((3+10+5+800)*(1+3+20+480)*80), | ||
| 155 | .left_margin = 3, | ||
| 156 | .right_margin = 5, | ||
| 157 | .upper_margin = 1, | ||
| 158 | .lower_margin = 20, | ||
| 159 | .hsync_len = 10, | ||
| 160 | .vsync_len = 3, | ||
| 161 | .xres = 800, | ||
| 162 | .yres = 480, | ||
| 163 | }, | ||
| 164 | .max_bpp = 32, | ||
| 165 | .default_bpp = 16, | ||
| 166 | }; | ||
| 167 | |||
| 168 | static struct s3c_fb_platdata smartq7_lcd_pdata __initdata = { | ||
| 169 | .setup_gpio = s3c64xx_fb_gpio_setup_24bpp, | ||
| 170 | .win[0] = &smartq7_fb_win0, | ||
| 171 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
| 172 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | | ||
| 173 | VIDCON1_INV_VCLK, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct platform_device *smartq7_devices[] __initdata = { | ||
| 177 | &smartq7_leds_device, | ||
| 178 | &smartq7_buttons_device, | ||
| 179 | &smartq7_lcd_control_device, | ||
| 180 | }; | ||
| 181 | |||
| 182 | static void __init smartq7_machine_init(void) | ||
| 183 | { | ||
| 184 | s3c_fb_set_platdata(&smartq7_lcd_pdata); | ||
| 185 | |||
| 186 | smartq_machine_init(); | ||
| 187 | smartq7_lcd_setup_gpio(); | ||
| 188 | |||
| 189 | platform_add_devices(smartq7_devices, ARRAY_SIZE(smartq7_devices)); | ||
| 190 | } | ||
| 191 | |||
| 192 | MACHINE_START(SMARTQ7, "SmartQ 7") | ||
| 193 | /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ | ||
| 194 | .phys_io = S3C_PA_UART & 0xfff00000, | ||
| 195 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | ||
| 196 | .boot_params = S3C64XX_PA_SDRAM + 0x100, | ||
| 197 | .init_irq = s3c6410_init_irq, | ||
| 198 | .map_io = smartq_map_io, | ||
| 199 | .init_machine = smartq7_machine_init, | ||
| 200 | .timer = &s3c24xx_timer, | ||
| 201 | MACHINE_END | ||
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c index 9d51455feb31..d9a03555f88b 100644 --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c | |||
| @@ -64,6 +64,8 @@ | |||
| 64 | #include <plat/clock.h> | 64 | #include <plat/clock.h> |
| 65 | #include <plat/devs.h> | 65 | #include <plat/devs.h> |
| 66 | #include <plat/cpu.h> | 66 | #include <plat/cpu.h> |
| 67 | #include <plat/adc.h> | ||
| 68 | #include <plat/ts.h> | ||
| 67 | 69 | ||
| 68 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK | 70 | #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK |
| 69 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB | 71 | #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB |
| @@ -262,6 +264,9 @@ static struct platform_device *smdk6410_devices[] __initdata = { | |||
| 262 | &smdk6410_lcd_powerdev, | 264 | &smdk6410_lcd_powerdev, |
| 263 | 265 | ||
| 264 | &smdk6410_smsc911x, | 266 | &smdk6410_smsc911x, |
| 267 | &s3c_device_adc, | ||
| 268 | &s3c_device_ts, | ||
| 269 | &s3c_device_wdt, | ||
| 265 | }; | 270 | }; |
| 266 | 271 | ||
| 267 | #ifdef CONFIG_REGULATOR | 272 | #ifdef CONFIG_REGULATOR |
| @@ -596,6 +601,12 @@ static struct i2c_board_info i2c_devs1[] __initdata = { | |||
| 596 | { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ | 601 | { I2C_BOARD_INFO("24c128", 0x57), }, /* Samsung S524AD0XD1 */ |
| 597 | }; | 602 | }; |
| 598 | 603 | ||
| 604 | static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | ||
| 605 | .delay = 10000, | ||
| 606 | .presc = 49, | ||
| 607 | .oversampling_shift = 2, | ||
| 608 | }; | ||
| 609 | |||
| 599 | static void __init smdk6410_map_io(void) | 610 | static void __init smdk6410_map_io(void) |
| 600 | { | 611 | { |
| 601 | u32 tmp; | 612 | u32 tmp; |
| @@ -625,6 +636,8 @@ static void __init smdk6410_machine_init(void) | |||
| 625 | s3c_i2c1_set_platdata(NULL); | 636 | s3c_i2c1_set_platdata(NULL); |
| 626 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); | 637 | s3c_fb_set_platdata(&smdk6410_lcd_pdata); |
| 627 | 638 | ||
| 639 | s3c24xx_ts_set_platdata(&s3c_ts_platform); | ||
| 640 | |||
| 628 | /* configure nCS1 width to 16 bits */ | 641 | /* configure nCS1 width to 16 bits */ |
| 629 | 642 | ||
| 630 | cs1 = __raw_readl(S3C64XX_SROM_BW) & | 643 | cs1 = __raw_readl(S3C64XX_SROM_BW) & |
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c index b8ac4597fad7..79412f735a8d 100644 --- a/arch/arm/mach-s3c64xx/pm.c +++ b/arch/arm/mach-s3c64xx/pm.c | |||
| @@ -18,8 +18,11 @@ | |||
| 18 | #include <linux/io.h> | 18 | #include <linux/io.h> |
| 19 | 19 | ||
| 20 | #include <mach/map.h> | 20 | #include <mach/map.h> |
| 21 | #include <mach/irqs.h> | ||
| 21 | 22 | ||
| 22 | #include <plat/pm.h> | 23 | #include <plat/pm.h> |
| 24 | #include <plat/wakeup-mask.h> | ||
| 25 | |||
| 23 | #include <mach/regs-sys.h> | 26 | #include <mach/regs-sys.h> |
| 24 | #include <mach/regs-gpio.h> | 27 | #include <mach/regs-gpio.h> |
| 25 | #include <mach/regs-clock.h> | 28 | #include <mach/regs-clock.h> |
| @@ -153,8 +156,25 @@ static void s3c64xx_cpu_suspend(void) | |||
| 153 | panic("sleep resumed to originator?"); | 156 | panic("sleep resumed to originator?"); |
| 154 | } | 157 | } |
| 155 | 158 | ||
| 159 | /* mapping of interrupts to parts of the wakeup mask */ | ||
| 160 | static struct samsung_wakeup_mask wake_irqs[] = { | ||
| 161 | { .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, }, | ||
| 162 | { .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, }, | ||
| 163 | { .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, }, | ||
| 164 | { .irq = IRQ_HSMMC0, .bit = S3C64XX_PWRCFG_MMC0_DISABLE, }, | ||
| 165 | { .irq = IRQ_HSMMC1, .bit = S3C64XX_PWRCFG_MMC1_DISABLE, }, | ||
| 166 | { .irq = IRQ_HSMMC2, .bit = S3C64XX_PWRCFG_MMC2_DISABLE, }, | ||
| 167 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_BATF_DISABLE}, | ||
| 168 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, | ||
| 169 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_HSI_DISABLE }, | ||
| 170 | { .irq = NO_WAKEUP_IRQ, .bit = S3C64XX_PWRCFG_MSM_DISABLE }, | ||
| 171 | }; | ||
| 172 | |||
| 156 | static void s3c64xx_pm_prepare(void) | 173 | static void s3c64xx_pm_prepare(void) |
| 157 | { | 174 | { |
| 175 | samsung_sync_wakemask(S3C64XX_PWR_CFG, | ||
| 176 | wake_irqs, ARRAY_SIZE(wake_irqs)); | ||
| 177 | |||
| 158 | /* store address of resume. */ | 178 | /* store address of resume. */ |
| 159 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); | 179 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); |
| 160 | 180 | ||
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c index 707e34e3afd1..5e93fe3f3f40 100644 --- a/arch/arm/mach-s3c64xx/s3c6400.c +++ b/arch/arm/mach-s3c64xx/s3c6400.c | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include <plat/clock.h> | 37 | #include <plat/clock.h> |
| 38 | #include <plat/sdhci.h> | 38 | #include <plat/sdhci.h> |
| 39 | #include <plat/iic-core.h> | 39 | #include <plat/iic-core.h> |
| 40 | #include <plat/onenand-core.h> | ||
| 40 | #include <mach/s3c6400.h> | 41 | #include <mach/s3c6400.h> |
| 41 | 42 | ||
| 42 | void __init s3c6400_map_io(void) | 43 | void __init s3c6400_map_io(void) |
| @@ -51,6 +52,9 @@ void __init s3c6400_map_io(void) | |||
| 51 | s3c_i2c0_setname("s3c2440-i2c"); | 52 | s3c_i2c0_setname("s3c2440-i2c"); |
| 52 | 53 | ||
| 53 | s3c_device_nand.name = "s3c6400-nand"; | 54 | s3c_device_nand.name = "s3c6400-nand"; |
| 55 | |||
| 56 | s3c_onenand_setname("s3c6400-onenand"); | ||
| 57 | s3c64xx_onenand1_setname("s3c6400-onenand"); | ||
| 54 | } | 58 | } |
| 55 | 59 | ||
| 56 | void __init s3c6400_init_clocks(int xtal) | 60 | void __init s3c6400_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c index 3ab695c691ee..014401c39f36 100644 --- a/arch/arm/mach-s3c64xx/s3c6410.c +++ b/arch/arm/mach-s3c64xx/s3c6410.c | |||
| @@ -39,6 +39,7 @@ | |||
| 39 | #include <plat/sdhci.h> | 39 | #include <plat/sdhci.h> |
| 40 | #include <plat/iic-core.h> | 40 | #include <plat/iic-core.h> |
| 41 | #include <plat/adc.h> | 41 | #include <plat/adc.h> |
| 42 | #include <plat/onenand-core.h> | ||
| 42 | #include <mach/s3c6400.h> | 43 | #include <mach/s3c6400.h> |
| 43 | #include <mach/s3c6410.h> | 44 | #include <mach/s3c6410.h> |
| 44 | 45 | ||
| @@ -55,6 +56,8 @@ void __init s3c6410_map_io(void) | |||
| 55 | 56 | ||
| 56 | s3c_device_adc.name = "s3c64xx-adc"; | 57 | s3c_device_adc.name = "s3c64xx-adc"; |
| 57 | s3c_device_nand.name = "s3c6400-nand"; | 58 | s3c_device_nand.name = "s3c6400-nand"; |
| 59 | s3c_onenand_setname("s3c6410-onenand"); | ||
| 60 | s3c64xx_onenand1_setname("s3c6410-onenand"); | ||
| 58 | } | 61 | } |
| 59 | 62 | ||
| 60 | void __init s3c6410_init_clocks(int xtal) | 63 | void __init s3c6410_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig index 77aeffd17330..f066fae07c57 100644 --- a/arch/arm/mach-s5p6440/Kconfig +++ b/arch/arm/mach-s5p6440/Kconfig | |||
| @@ -16,6 +16,10 @@ config CPU_S5P6440 | |||
| 16 | config MACH_SMDK6440 | 16 | config MACH_SMDK6440 |
| 17 | bool "SMDK6440" | 17 | bool "SMDK6440" |
| 18 | select CPU_S5P6440 | 18 | select CPU_S5P6440 |
| 19 | select SAMSUNG_DEV_TS | ||
| 20 | select SAMSUNG_DEV_ADC | ||
| 21 | select S3C_DEV_WDT | ||
| 22 | select HAVE_S3C2410_WATCHDOG | ||
| 19 | help | 23 | help |
| 20 | Machine support for the Samsung SMDK6440 | 24 | Machine support for the Samsung SMDK6440 |
| 21 | 25 | ||
diff --git a/arch/arm/mach-s5p6440/Makefile b/arch/arm/mach-s5p6440/Makefile index 44facf43d59f..be3c53aab23f 100644 --- a/arch/arm/mach-s5p6440/Makefile +++ b/arch/arm/mach-s5p6440/Makefile | |||
| @@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o | |||
| 21 | 21 | ||
| 22 | # device support | 22 | # device support |
| 23 | obj-y += dev-audio.o | 23 | obj-y += dev-audio.o |
| 24 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | ||
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c index ca3b3206e6f8..b2fe6a58155a 100644 --- a/arch/arm/mach-s5p6440/cpu.c +++ b/arch/arm/mach-s5p6440/cpu.c | |||
| @@ -61,6 +61,7 @@ static void s5p6440_idle(void) | |||
| 61 | void __init s5p6440_map_io(void) | 61 | void __init s5p6440_map_io(void) |
| 62 | { | 62 | { |
| 63 | /* initialize any device information early */ | 63 | /* initialize any device information early */ |
| 64 | s3c_device_adc.name = "s3c64xx-adc"; | ||
| 64 | } | 65 | } |
| 65 | 66 | ||
| 66 | void __init s5p6440_init_clocks(int xtal) | 67 | void __init s5p6440_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s5p6440/dev-spi.c b/arch/arm/mach-s5p6440/dev-spi.c new file mode 100644 index 000000000000..0a30280019c0 --- /dev/null +++ b/arch/arm/mach-s5p6440/dev-spi.c | |||
| @@ -0,0 +1,176 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/dev-spi.c | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/dma-mapping.h> | ||
| 13 | |||
| 14 | #include <mach/dma.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <mach/gpio.h> | ||
| 18 | #include <mach/spi-clocks.h> | ||
| 19 | |||
| 20 | #include <plat/s3c64xx-spi.h> | ||
| 21 | #include <plat/gpio-cfg.h> | ||
| 22 | |||
| 23 | static char *spi_src_clks[] = { | ||
| 24 | [S5P6440_SPI_SRCCLK_PCLK] = "pclk", | ||
| 25 | [S5P6440_SPI_SRCCLK_SCLK] = "spi_epll", | ||
| 26 | }; | ||
| 27 | |||
| 28 | /* SPI Controller platform_devices */ | ||
| 29 | |||
| 30 | /* Since we emulate multi-cs capability, we do not touch the CS. | ||
| 31 | * The emulated CS is toggled by board specific mechanism, as it can | ||
| 32 | * be either some immediate GPIO or some signal out of some other | ||
| 33 | * chip in between ... or some yet another way. | ||
| 34 | * We simply do not assume anything about CS. | ||
| 35 | */ | ||
| 36 | static int s5p6440_spi_cfg_gpio(struct platform_device *pdev) | ||
| 37 | { | ||
| 38 | switch (pdev->id) { | ||
| 39 | case 0: | ||
| 40 | s3c_gpio_cfgpin(S5P6440_GPC(0), S3C_GPIO_SFN(2)); | ||
| 41 | s3c_gpio_cfgpin(S5P6440_GPC(1), S3C_GPIO_SFN(2)); | ||
| 42 | s3c_gpio_cfgpin(S5P6440_GPC(2), S3C_GPIO_SFN(2)); | ||
| 43 | s3c_gpio_setpull(S5P6440_GPC(0), S3C_GPIO_PULL_UP); | ||
| 44 | s3c_gpio_setpull(S5P6440_GPC(1), S3C_GPIO_PULL_UP); | ||
| 45 | s3c_gpio_setpull(S5P6440_GPC(2), S3C_GPIO_PULL_UP); | ||
| 46 | break; | ||
| 47 | |||
| 48 | case 1: | ||
| 49 | s3c_gpio_cfgpin(S5P6440_GPC(4), S3C_GPIO_SFN(2)); | ||
| 50 | s3c_gpio_cfgpin(S5P6440_GPC(5), S3C_GPIO_SFN(2)); | ||
| 51 | s3c_gpio_cfgpin(S5P6440_GPC(6), S3C_GPIO_SFN(2)); | ||
| 52 | s3c_gpio_setpull(S5P6440_GPC(4), S3C_GPIO_PULL_UP); | ||
| 53 | s3c_gpio_setpull(S5P6440_GPC(5), S3C_GPIO_PULL_UP); | ||
| 54 | s3c_gpio_setpull(S5P6440_GPC(6), S3C_GPIO_PULL_UP); | ||
| 55 | break; | ||
| 56 | |||
| 57 | default: | ||
| 58 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | ||
| 59 | return -EINVAL; | ||
| 60 | } | ||
| 61 | |||
| 62 | return 0; | ||
| 63 | } | ||
| 64 | |||
| 65 | static struct resource s5p6440_spi0_resource[] = { | ||
| 66 | [0] = { | ||
| 67 | .start = S5P6440_PA_SPI0, | ||
| 68 | .end = S5P6440_PA_SPI0 + 0x100 - 1, | ||
| 69 | .flags = IORESOURCE_MEM, | ||
| 70 | }, | ||
| 71 | [1] = { | ||
| 72 | .start = DMACH_SPI0_TX, | ||
| 73 | .end = DMACH_SPI0_TX, | ||
| 74 | .flags = IORESOURCE_DMA, | ||
| 75 | }, | ||
| 76 | [2] = { | ||
| 77 | .start = DMACH_SPI0_RX, | ||
| 78 | .end = DMACH_SPI0_RX, | ||
| 79 | .flags = IORESOURCE_DMA, | ||
| 80 | }, | ||
| 81 | [3] = { | ||
| 82 | .start = IRQ_SPI0, | ||
| 83 | .end = IRQ_SPI0, | ||
| 84 | .flags = IORESOURCE_IRQ, | ||
| 85 | }, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct s3c64xx_spi_info s5p6440_spi0_pdata = { | ||
| 89 | .cfg_gpio = s5p6440_spi_cfg_gpio, | ||
| 90 | .fifo_lvl_mask = 0x1ff, | ||
| 91 | .rx_lvl_offset = 15, | ||
| 92 | }; | ||
| 93 | |||
| 94 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
| 95 | |||
| 96 | struct platform_device s5p6440_device_spi0 = { | ||
| 97 | .name = "s3c64xx-spi", | ||
| 98 | .id = 0, | ||
| 99 | .num_resources = ARRAY_SIZE(s5p6440_spi0_resource), | ||
| 100 | .resource = s5p6440_spi0_resource, | ||
| 101 | .dev = { | ||
| 102 | .dma_mask = &spi_dmamask, | ||
| 103 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 104 | .platform_data = &s5p6440_spi0_pdata, | ||
| 105 | }, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static struct resource s5p6440_spi1_resource[] = { | ||
| 109 | [0] = { | ||
| 110 | .start = S5P6440_PA_SPI1, | ||
| 111 | .end = S5P6440_PA_SPI1 + 0x100 - 1, | ||
| 112 | .flags = IORESOURCE_MEM, | ||
| 113 | }, | ||
| 114 | [1] = { | ||
| 115 | .start = DMACH_SPI1_TX, | ||
| 116 | .end = DMACH_SPI1_TX, | ||
| 117 | .flags = IORESOURCE_DMA, | ||
| 118 | }, | ||
| 119 | [2] = { | ||
| 120 | .start = DMACH_SPI1_RX, | ||
| 121 | .end = DMACH_SPI1_RX, | ||
| 122 | .flags = IORESOURCE_DMA, | ||
| 123 | }, | ||
| 124 | [3] = { | ||
| 125 | .start = IRQ_SPI1, | ||
| 126 | .end = IRQ_SPI1, | ||
| 127 | .flags = IORESOURCE_IRQ, | ||
| 128 | }, | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct s3c64xx_spi_info s5p6440_spi1_pdata = { | ||
| 132 | .cfg_gpio = s5p6440_spi_cfg_gpio, | ||
| 133 | .fifo_lvl_mask = 0x7f, | ||
| 134 | .rx_lvl_offset = 15, | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct platform_device s5p6440_device_spi1 = { | ||
| 138 | .name = "s3c64xx-spi", | ||
| 139 | .id = 1, | ||
| 140 | .num_resources = ARRAY_SIZE(s5p6440_spi1_resource), | ||
| 141 | .resource = s5p6440_spi1_resource, | ||
| 142 | .dev = { | ||
| 143 | .dma_mask = &spi_dmamask, | ||
| 144 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 145 | .platform_data = &s5p6440_spi1_pdata, | ||
| 146 | }, | ||
| 147 | }; | ||
| 148 | |||
| 149 | void __init s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | ||
| 150 | { | ||
| 151 | struct s3c64xx_spi_info *pd; | ||
| 152 | |||
| 153 | /* Reject invalid configuration */ | ||
| 154 | if (!num_cs || src_clk_nr < 0 | ||
| 155 | || src_clk_nr > S5P6440_SPI_SRCCLK_SCLK) { | ||
| 156 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | ||
| 157 | return; | ||
| 158 | } | ||
| 159 | |||
| 160 | switch (cntrlr) { | ||
| 161 | case 0: | ||
| 162 | pd = &s5p6440_spi0_pdata; | ||
| 163 | break; | ||
| 164 | case 1: | ||
| 165 | pd = &s5p6440_spi1_pdata; | ||
| 166 | break; | ||
| 167 | default: | ||
| 168 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | ||
| 169 | __func__, cntrlr); | ||
| 170 | return; | ||
| 171 | } | ||
| 172 | |||
| 173 | pd->num_cs = num_cs; | ||
| 174 | pd->src_clk_nr = src_clk_nr; | ||
| 175 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | ||
| 176 | } | ||
diff --git a/arch/arm/mach-s5p6440/gpio.c b/arch/arm/mach-s5p6440/gpio.c index 262dc75d5bea..92efc05b1ba2 100644 --- a/arch/arm/mach-s5p6440/gpio.c +++ b/arch/arm/mach-s5p6440/gpio.c | |||
| @@ -46,6 +46,7 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, | |||
| 46 | void __iomem *base = ourchip->base; | 46 | void __iomem *base = ourchip->base; |
| 47 | void __iomem *regcon = base; | 47 | void __iomem *regcon = base; |
| 48 | unsigned long con; | 48 | unsigned long con; |
| 49 | unsigned long flags; | ||
| 49 | 50 | ||
| 50 | switch (offset) { | 51 | switch (offset) { |
| 51 | case 6: | 52 | case 6: |
| @@ -63,10 +64,14 @@ static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, | |||
| 63 | break; | 64 | break; |
| 64 | } | 65 | } |
| 65 | 66 | ||
| 67 | s3c_gpio_lock(ourchip, flags); | ||
| 68 | |||
| 66 | con = __raw_readl(regcon); | 69 | con = __raw_readl(regcon); |
| 67 | con &= ~(0xf << con_4bit_shift(offset)); | 70 | con &= ~(0xf << con_4bit_shift(offset)); |
| 68 | __raw_writel(con, regcon); | 71 | __raw_writel(con, regcon); |
| 69 | 72 | ||
| 73 | s3c_gpio_unlock(ourchip, flags); | ||
| 74 | |||
| 70 | return 0; | 75 | return 0; |
| 71 | } | 76 | } |
| 72 | 77 | ||
| @@ -78,6 +83,7 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, | |||
| 78 | void __iomem *regcon = base; | 83 | void __iomem *regcon = base; |
| 79 | unsigned long con; | 84 | unsigned long con; |
| 80 | unsigned long dat; | 85 | unsigned long dat; |
| 86 | unsigned long flags; | ||
| 81 | unsigned con_offset = offset; | 87 | unsigned con_offset = offset; |
| 82 | 88 | ||
| 83 | switch (con_offset) { | 89 | switch (con_offset) { |
| @@ -96,6 +102,8 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, | |||
| 96 | break; | 102 | break; |
| 97 | } | 103 | } |
| 98 | 104 | ||
| 105 | s3c_gpio_lock(ourchip, flags); | ||
| 106 | |||
| 99 | con = __raw_readl(regcon); | 107 | con = __raw_readl(regcon); |
| 100 | con &= ~(0xf << con_4bit_shift(con_offset)); | 108 | con &= ~(0xf << con_4bit_shift(con_offset)); |
| 101 | con |= 0x1 << con_4bit_shift(con_offset); | 109 | con |= 0x1 << con_4bit_shift(con_offset); |
| @@ -109,6 +117,8 @@ static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, | |||
| 109 | __raw_writel(con, regcon); | 117 | __raw_writel(con, regcon); |
| 110 | __raw_writel(dat, base + GPIODAT_OFF); | 118 | __raw_writel(dat, base + GPIODAT_OFF); |
| 111 | 119 | ||
| 120 | s3c_gpio_unlock(ourchip, flags); | ||
| 121 | |||
| 112 | return 0; | 122 | return 0; |
| 113 | } | 123 | } |
| 114 | 124 | ||
| @@ -117,6 +127,7 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, | |||
| 117 | { | 127 | { |
| 118 | void __iomem *reg = chip->base; | 128 | void __iomem *reg = chip->base; |
| 119 | unsigned int shift; | 129 | unsigned int shift; |
| 130 | unsigned long flags; | ||
| 120 | u32 con; | 131 | u32 con; |
| 121 | 132 | ||
| 122 | switch (off) { | 133 | switch (off) { |
| @@ -142,11 +153,15 @@ int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, | |||
| 142 | cfg <<= shift; | 153 | cfg <<= shift; |
| 143 | } | 154 | } |
| 144 | 155 | ||
| 156 | s3c_gpio_lock(chip, flags); | ||
| 157 | |||
| 145 | con = __raw_readl(reg); | 158 | con = __raw_readl(reg); |
| 146 | con &= ~(0xf << shift); | 159 | con &= ~(0xf << shift); |
| 147 | con |= cfg; | 160 | con |= cfg; |
| 148 | __raw_writel(con, reg); | 161 | __raw_writel(con, reg); |
| 149 | 162 | ||
| 163 | s3c_gpio_unlock(chip, flags); | ||
| 164 | |||
| 150 | return 0; | 165 | return 0; |
| 151 | } | 166 | } |
| 152 | 167 | ||
diff --git a/arch/arm/mach-s5p6440/include/mach/map.h b/arch/arm/mach-s5p6440/include/mach/map.h index 72aedadd412c..44011b91fbd1 100644 --- a/arch/arm/mach-s5p6440/include/mach/map.h +++ b/arch/arm/mach-s5p6440/include/mach/map.h | |||
| @@ -54,6 +54,9 @@ | |||
| 54 | 54 | ||
| 55 | #define S5P6440_PA_IIC0 (0xEC104000) | 55 | #define S5P6440_PA_IIC0 (0xEC104000) |
| 56 | 56 | ||
| 57 | #define S5P6440_PA_SPI0 0xEC400000 | ||
| 58 | #define S5P6440_PA_SPI1 0xEC500000 | ||
| 59 | |||
| 57 | #define S5P6440_PA_HSOTG (0xED100000) | 60 | #define S5P6440_PA_HSOTG (0xED100000) |
| 58 | 61 | ||
| 59 | #define S5P6440_PA_HSMMC0 (0xED800000) | 62 | #define S5P6440_PA_HSMMC0 (0xED800000) |
| @@ -69,8 +72,13 @@ | |||
| 69 | /* PCM */ | 72 | /* PCM */ |
| 70 | #define S5P6440_PA_PCM 0xF2100000 | 73 | #define S5P6440_PA_PCM 0xF2100000 |
| 71 | 74 | ||
| 75 | #define S5P6440_PA_ADC (0xF3000000) | ||
| 76 | |||
| 72 | /* compatibiltiy defines. */ | 77 | /* compatibiltiy defines. */ |
| 73 | #define S3C_PA_UART S5P6440_PA_UART | 78 | #define S3C_PA_UART S5P6440_PA_UART |
| 74 | #define S3C_PA_IIC S5P6440_PA_IIC0 | 79 | #define S3C_PA_IIC S5P6440_PA_IIC0 |
| 80 | #define S3C_PA_WDT S5P6440_PA_WDT | ||
| 81 | |||
| 82 | #define SAMSUNG_PA_ADC S5P6440_PA_ADC | ||
| 75 | 83 | ||
| 76 | #endif /* __ASM_ARCH_MAP_H */ | 84 | #endif /* __ASM_ARCH_MAP_H */ |
diff --git a/arch/arm/mach-s5p6440/include/mach/spi-clocks.h b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h new file mode 100644 index 000000000000..5fbca50d1cfb --- /dev/null +++ b/arch/arm/mach-s5p6440/include/mach/spi-clocks.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6440/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S5P6440_PLAT_SPI_CLKS_H | ||
| 12 | #define __S5P6440_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S5P6440_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S5P6440_SPI_SRCCLK_SCLK 1 | ||
| 16 | |||
| 17 | #endif /* __S5P6440_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c index d7fede971ca6..8291fecc701a 100644 --- a/arch/arm/mach-s5p6440/mach-smdk6440.c +++ b/arch/arm/mach-s5p6440/mach-smdk6440.c | |||
| @@ -38,6 +38,8 @@ | |||
| 38 | #include <plat/devs.h> | 38 | #include <plat/devs.h> |
| 39 | #include <plat/cpu.h> | 39 | #include <plat/cpu.h> |
| 40 | #include <plat/pll.h> | 40 | #include <plat/pll.h> |
| 41 | #include <plat/adc.h> | ||
| 42 | #include <plat/ts.h> | ||
| 41 | 43 | ||
| 42 | #define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 44 | #define S5P6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 43 | S3C2410_UCON_RXILEVEL | \ | 45 | S3C2410_UCON_RXILEVEL | \ |
| @@ -85,6 +87,15 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { | |||
| 85 | 87 | ||
| 86 | static struct platform_device *smdk6440_devices[] __initdata = { | 88 | static struct platform_device *smdk6440_devices[] __initdata = { |
| 87 | &s5p6440_device_iis, | 89 | &s5p6440_device_iis, |
| 90 | &s3c_device_adc, | ||
| 91 | &s3c_device_ts, | ||
| 92 | &s3c_device_wdt, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | ||
| 96 | .delay = 10000, | ||
| 97 | .presc = 49, | ||
| 98 | .oversampling_shift = 2, | ||
| 88 | }; | 99 | }; |
| 89 | 100 | ||
| 90 | static void __init smdk6440_map_io(void) | 101 | static void __init smdk6440_map_io(void) |
| @@ -96,6 +107,8 @@ static void __init smdk6440_map_io(void) | |||
| 96 | 107 | ||
| 97 | static void __init smdk6440_machine_init(void) | 108 | static void __init smdk6440_machine_init(void) |
| 98 | { | 109 | { |
| 110 | s3c24xx_ts_set_platdata(&s3c_ts_platform); | ||
| 111 | |||
| 99 | platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); | 112 | platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); |
| 100 | } | 113 | } |
| 101 | 114 | ||
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile index e30a7f76aee6..90a3d8373416 100644 --- a/arch/arm/mach-s5p6442/Makefile +++ b/arch/arm/mach-s5p6442/Makefile | |||
| @@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o | |||
| 21 | 21 | ||
| 22 | # device support | 22 | # device support |
| 23 | obj-y += dev-audio.o | 23 | obj-y += dev-audio.o |
| 24 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | ||
diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c new file mode 100644 index 000000000000..30199525daca --- /dev/null +++ b/arch/arm/mach-s5p6442/dev-spi.c | |||
| @@ -0,0 +1,123 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6442/dev-spi.c | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/dma-mapping.h> | ||
| 13 | |||
| 14 | #include <mach/dma.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <mach/gpio.h> | ||
| 18 | #include <mach/spi-clocks.h> | ||
| 19 | |||
| 20 | #include <plat/s3c64xx-spi.h> | ||
| 21 | #include <plat/gpio-cfg.h> | ||
| 22 | |||
| 23 | static char *spi_src_clks[] = { | ||
| 24 | [S5P6442_SPI_SRCCLK_PCLK] = "pclk", | ||
| 25 | [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll", | ||
| 26 | }; | ||
| 27 | |||
| 28 | /* SPI Controller platform_devices */ | ||
| 29 | |||
| 30 | /* Since we emulate multi-cs capability, we do not touch the CS. | ||
| 31 | * The emulated CS is toggled by board specific mechanism, as it can | ||
| 32 | * be either some immediate GPIO or some signal out of some other | ||
| 33 | * chip in between ... or some yet another way. | ||
| 34 | * We simply do not assume anything about CS. | ||
| 35 | */ | ||
| 36 | static int s5p6442_spi_cfg_gpio(struct platform_device *pdev) | ||
| 37 | { | ||
| 38 | switch (pdev->id) { | ||
| 39 | case 0: | ||
| 40 | s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2)); | ||
| 41 | s3c_gpio_cfgpin(S5P6442_GPB(2), S3C_GPIO_SFN(2)); | ||
| 42 | s3c_gpio_cfgpin(S5P6442_GPB(3), S3C_GPIO_SFN(2)); | ||
| 43 | s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP); | ||
| 44 | s3c_gpio_setpull(S5P6442_GPB(2), S3C_GPIO_PULL_UP); | ||
| 45 | s3c_gpio_setpull(S5P6442_GPB(3), S3C_GPIO_PULL_UP); | ||
| 46 | break; | ||
| 47 | |||
| 48 | default: | ||
| 49 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | ||
| 50 | return -EINVAL; | ||
| 51 | } | ||
| 52 | |||
| 53 | return 0; | ||
| 54 | } | ||
| 55 | |||
| 56 | static struct resource s5p6442_spi0_resource[] = { | ||
| 57 | [0] = { | ||
| 58 | .start = S5P6442_PA_SPI, | ||
| 59 | .end = S5P6442_PA_SPI + 0x100 - 1, | ||
| 60 | .flags = IORESOURCE_MEM, | ||
| 61 | }, | ||
| 62 | [1] = { | ||
| 63 | .start = DMACH_SPI0_TX, | ||
| 64 | .end = DMACH_SPI0_TX, | ||
| 65 | .flags = IORESOURCE_DMA, | ||
| 66 | }, | ||
| 67 | [2] = { | ||
| 68 | .start = DMACH_SPI0_RX, | ||
| 69 | .end = DMACH_SPI0_RX, | ||
| 70 | .flags = IORESOURCE_DMA, | ||
| 71 | }, | ||
| 72 | [3] = { | ||
| 73 | .start = IRQ_SPI0, | ||
| 74 | .end = IRQ_SPI0, | ||
| 75 | .flags = IORESOURCE_IRQ, | ||
| 76 | }, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct s3c64xx_spi_info s5p6442_spi0_pdata = { | ||
| 80 | .cfg_gpio = s5p6442_spi_cfg_gpio, | ||
| 81 | .fifo_lvl_mask = 0x1ff, | ||
| 82 | .rx_lvl_offset = 15, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
| 86 | |||
| 87 | struct platform_device s5p6442_device_spi = { | ||
| 88 | .name = "s3c64xx-spi", | ||
| 89 | .id = 0, | ||
| 90 | .num_resources = ARRAY_SIZE(s5p6442_spi0_resource), | ||
| 91 | .resource = s5p6442_spi0_resource, | ||
| 92 | .dev = { | ||
| 93 | .dma_mask = &spi_dmamask, | ||
| 94 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 95 | .platform_data = &s5p6442_spi0_pdata, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | ||
| 100 | { | ||
| 101 | struct s3c64xx_spi_info *pd; | ||
| 102 | |||
| 103 | /* Reject invalid configuration */ | ||
| 104 | if (!num_cs || src_clk_nr < 0 | ||
| 105 | || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) { | ||
| 106 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | ||
| 107 | return; | ||
| 108 | } | ||
| 109 | |||
| 110 | switch (cntrlr) { | ||
| 111 | case 0: | ||
| 112 | pd = &s5p6442_spi0_pdata; | ||
| 113 | break; | ||
| 114 | default: | ||
| 115 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | ||
| 116 | __func__, cntrlr); | ||
| 117 | return; | ||
| 118 | } | ||
| 119 | |||
| 120 | pd->num_cs = num_cs; | ||
| 121 | pd->src_clk_nr = src_clk_nr; | ||
| 122 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | ||
| 123 | } | ||
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h index 7568dc0d6be0..32ca424ef7f9 100644 --- a/arch/arm/mach-s5p6442/include/mach/map.h +++ b/arch/arm/mach-s5p6442/include/mach/map.h | |||
| @@ -54,6 +54,8 @@ | |||
| 54 | #define S5P6442_PA_SDRAM (0x20000000) | 54 | #define S5P6442_PA_SDRAM (0x20000000) |
| 55 | #define S5P_PA_SDRAM S5P6442_PA_SDRAM | 55 | #define S5P_PA_SDRAM S5P6442_PA_SDRAM |
| 56 | 56 | ||
| 57 | #define S5P6442_PA_SPI 0xEC300000 | ||
| 58 | |||
| 57 | /* I2S */ | 59 | /* I2S */ |
| 58 | #define S5P6442_PA_I2S0 0xC0B00000 | 60 | #define S5P6442_PA_I2S0 0xC0B00000 |
| 59 | #define S5P6442_PA_I2S1 0xF2200000 | 61 | #define S5P6442_PA_I2S1 0xF2200000 |
diff --git a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h new file mode 100644 index 000000000000..7fd88205a97c --- /dev/null +++ b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S5P6442_PLAT_SPI_CLKS_H | ||
| 12 | #define __S5P6442_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S5P6442_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S5P6442_SPI_SRCCLK_SCLK 1 | ||
| 16 | |||
| 17 | #endif /* __S5P6442_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig index 8593337784e1..b2a11dfa3399 100644 --- a/arch/arm/mach-s5pc100/Kconfig +++ b/arch/arm/mach-s5pc100/Kconfig | |||
| @@ -5,10 +5,13 @@ | |||
| 5 | 5 | ||
| 6 | # Configuration options for the S5PC100 CPU | 6 | # Configuration options for the S5PC100 CPU |
| 7 | 7 | ||
| 8 | if ARCH_S5PC100 | ||
| 9 | |||
| 8 | config CPU_S5PC100 | 10 | config CPU_S5PC100 |
| 9 | bool | 11 | bool |
| 10 | select CPU_S5PC100_INIT | 12 | select PLAT_S5P |
| 11 | select CPU_S5PC100_CLOCK | 13 | select S5P_EXT_INT |
| 14 | select S3C_PL330_DMA | ||
| 12 | help | 15 | help |
| 13 | Enable S5PC100 CPU support | 16 | Enable S5PC100 CPU support |
| 14 | 17 | ||
| @@ -17,17 +20,22 @@ config S5PC100_SETUP_FB_24BPP | |||
| 17 | help | 20 | help |
| 18 | Common setup code for S5PC1XX with an 24bpp RGB display helper. | 21 | Common setup code for S5PC1XX with an 24bpp RGB display helper. |
| 19 | 22 | ||
| 20 | config S5PC100_SETUP_SDHCI | ||
| 21 | bool | ||
| 22 | select S5PC1XX_SETUP_SDHCI_GPIO | ||
| 23 | help | ||
| 24 | Internal helper functions for S5PC100 based SDHCI systems | ||
| 25 | |||
| 26 | config S5PC100_SETUP_I2C1 | 23 | config S5PC100_SETUP_I2C1 |
| 27 | bool | 24 | bool |
| 28 | help | 25 | help |
| 29 | Common setup code for i2c bus 1. | 26 | Common setup code for i2c bus 1. |
| 30 | 27 | ||
| 28 | config S5PC100_SETUP_SDHCI | ||
| 29 | bool | ||
| 30 | select S5PC100_SETUP_SDHCI_GPIO | ||
| 31 | help | ||
| 32 | Internal helper functions for S5PC100 based SDHCI systems | ||
| 33 | |||
| 34 | config S5PC100_SETUP_SDHCI_GPIO | ||
| 35 | bool | ||
| 36 | help | ||
| 37 | Common setup code for SDHCI gpio. | ||
| 38 | |||
| 31 | config MACH_SMDKC100 | 39 | config MACH_SMDKC100 |
| 32 | bool "SMDKC100" | 40 | bool "SMDKC100" |
| 33 | select CPU_S5PC100 | 41 | select CPU_S5PC100 |
| @@ -41,3 +49,5 @@ config MACH_SMDKC100 | |||
| 41 | select S5PC100_SETUP_SDHCI | 49 | select S5PC100_SETUP_SDHCI |
| 42 | help | 50 | help |
| 43 | Machine support for the Samsung SMDKC100 | 51 | Machine support for the Samsung SMDKC100 |
| 52 | |||
| 53 | endif | ||
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile index 373bc546eae8..543f3de5131e 100644 --- a/arch/arm/mach-s5pc100/Makefile +++ b/arch/arm/mach-s5pc100/Makefile | |||
| @@ -11,14 +11,24 @@ obj- := | |||
| 11 | 11 | ||
| 12 | # Core support for S5PC100 system | 12 | # Core support for S5PC100 system |
| 13 | 13 | ||
| 14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o | 14 | obj-$(CONFIG_CPU_S5PC100) += cpu.o init.o clock.o gpiolib.o irq-gpio.o |
| 15 | obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o | 15 | obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o |
| 16 | obj-$(CONFIG_CPU_S5PC100) += dma.o | ||
| 16 | 17 | ||
| 17 | # Helper and device support | 18 | # Helper and device support |
| 18 | 19 | ||
| 19 | obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o | 20 | obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o |
| 20 | obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o | 21 | obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o |
| 21 | obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o | 22 | obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o |
| 23 | obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | ||
| 24 | |||
| 25 | # device support | ||
| 26 | obj-y += dev-audio.o | ||
| 27 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | ||
| 22 | 28 | ||
| 23 | # machine support | 29 | # machine support |
| 30 | |||
| 24 | obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o | 31 | obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o |
| 32 | |||
| 33 | # device support | ||
| 34 | obj-y += dev-audio.o | ||
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c index d79e7574a852..7b5bdbc9a5df 100644 --- a/arch/arm/mach-s5pc100/cpu.c +++ b/arch/arm/mach-s5pc100/cpu.c | |||
| @@ -22,47 +22,55 @@ | |||
| 22 | #include <linux/serial_core.h> | 22 | #include <linux/serial_core.h> |
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | 24 | ||
| 25 | #include <asm/proc-fns.h> | ||
| 26 | |||
| 27 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
| 28 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/irq.h> | 27 | #include <asm/mach/irq.h> |
| 30 | 28 | ||
| 29 | #include <asm/proc-fns.h> | ||
| 30 | |||
| 31 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 32 | #include <mach/map.h> | 32 | #include <mach/map.h> |
| 33 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| 34 | 34 | ||
| 35 | #include <plat/cpu-freq.h> | ||
| 36 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
| 37 | #include <plat/regs-power.h> | 36 | #include <mach/regs-clock.h> |
| 38 | 37 | ||
| 39 | #include <plat/cpu.h> | 38 | #include <plat/cpu.h> |
| 40 | #include <plat/devs.h> | 39 | #include <plat/devs.h> |
| 41 | #include <plat/clock.h> | 40 | #include <plat/clock.h> |
| 42 | #include <plat/sdhci.h> | ||
| 43 | #include <plat/iic-core.h> | 41 | #include <plat/iic-core.h> |
| 42 | #include <plat/sdhci.h> | ||
| 43 | #include <plat/onenand-core.h> | ||
| 44 | |||
| 44 | #include <plat/s5pc100.h> | 45 | #include <plat/s5pc100.h> |
| 45 | 46 | ||
| 46 | /* Initial IO mappings */ | 47 | /* Initial IO mappings */ |
| 47 | 48 | ||
| 48 | static struct map_desc s5pc100_iodesc[] __initdata = { | 49 | static struct map_desc s5pc100_iodesc[] __initdata = { |
| 50 | { | ||
| 51 | .virtual = (unsigned long)S5P_VA_SYSTIMER, | ||
| 52 | .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER), | ||
| 53 | .length = SZ_16K, | ||
| 54 | .type = MT_DEVICE, | ||
| 55 | }, { | ||
| 56 | .virtual = (unsigned long)VA_VIC2, | ||
| 57 | .pfn = __phys_to_pfn(S5P_PA_VIC2), | ||
| 58 | .length = SZ_16K, | ||
| 59 | .type = MT_DEVICE, | ||
| 60 | }, { | ||
| 61 | .virtual = (unsigned long)S5PC100_VA_OTHERS, | ||
| 62 | .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), | ||
| 63 | .length = SZ_4K, | ||
| 64 | .type = MT_DEVICE, | ||
| 65 | } | ||
| 49 | }; | 66 | }; |
| 50 | 67 | ||
| 51 | static void s5pc100_idle(void) | 68 | static void s5pc100_idle(void) |
| 52 | { | 69 | { |
| 53 | unsigned long tmp; | 70 | if (!need_resched()) |
| 54 | 71 | cpu_do_idle(); | |
| 55 | tmp = __raw_readl(S5PC100_PWR_CFG); | ||
| 56 | tmp &= ~S5PC100_PWRCFG_CFG_DEEP_IDLE; | ||
| 57 | tmp &= ~S5PC100_PWRCFG_CFG_WFI_MASK; | ||
| 58 | tmp |= S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE; | ||
| 59 | __raw_writel(tmp, S5PC100_PWR_CFG); | ||
| 60 | |||
| 61 | tmp = __raw_readl(S5PC100_OTHERS); | ||
| 62 | tmp |= S5PC100_PMU_INT_DISABLE; | ||
| 63 | __raw_writel(tmp, S5PC100_OTHERS); | ||
| 64 | 72 | ||
| 65 | cpu_do_idle(); | 73 | local_irq_enable(); |
| 66 | } | 74 | } |
| 67 | 75 | ||
| 68 | /* s5pc100_map_io | 76 | /* s5pc100_map_io |
| @@ -82,26 +90,29 @@ void __init s5pc100_map_io(void) | |||
| 82 | /* the i2c devices are directly compatible with s3c2440 */ | 90 | /* the i2c devices are directly compatible with s3c2440 */ |
| 83 | s3c_i2c0_setname("s3c2440-i2c"); | 91 | s3c_i2c0_setname("s3c2440-i2c"); |
| 84 | s3c_i2c1_setname("s3c2440-i2c"); | 92 | s3c_i2c1_setname("s3c2440-i2c"); |
| 93 | |||
| 94 | s3c_onenand_setname("s5pc100-onenand"); | ||
| 85 | } | 95 | } |
| 86 | 96 | ||
| 87 | void __init s5pc100_init_clocks(int xtal) | 97 | void __init s5pc100_init_clocks(int xtal) |
| 88 | { | 98 | { |
| 89 | printk(KERN_DEBUG "%s: initialising clocks\n", __func__); | 99 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); |
| 100 | |||
| 90 | s3c24xx_register_baseclocks(xtal); | 101 | s3c24xx_register_baseclocks(xtal); |
| 91 | s5pc1xx_register_clocks(); | 102 | s5p_register_clocks(xtal); |
| 92 | s5pc100_register_clocks(); | 103 | s5pc100_register_clocks(); |
| 93 | s5pc100_setup_clocks(); | 104 | s5pc100_setup_clocks(); |
| 94 | } | 105 | } |
| 95 | 106 | ||
| 96 | void __init s5pc100_init_irq(void) | 107 | void __init s5pc100_init_irq(void) |
| 97 | { | 108 | { |
| 98 | u32 vic_valid[] = {~0, ~0, ~0}; | 109 | u32 vic[] = {~0, ~0, ~0}; |
| 99 | 110 | ||
| 100 | /* VIC0, VIC1, and VIC2 are fully populated. */ | 111 | /* VIC0, VIC1, and VIC2 are fully populated. */ |
| 101 | s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid)); | 112 | s5p_init_irq(vic, ARRAY_SIZE(vic)); |
| 102 | } | 113 | } |
| 103 | 114 | ||
| 104 | struct sysdev_class s5pc100_sysclass = { | 115 | static struct sysdev_class s5pc100_sysclass = { |
| 105 | .name = "s5pc100-core", | 116 | .name = "s5pc100-core", |
| 106 | }; | 117 | }; |
| 107 | 118 | ||
| @@ -118,9 +129,10 @@ core_initcall(s5pc100_core_init); | |||
| 118 | 129 | ||
| 119 | int __init s5pc100_init(void) | 130 | int __init s5pc100_init(void) |
| 120 | { | 131 | { |
| 121 | printk(KERN_DEBUG "S5PC100: Initialising architecture\n"); | 132 | printk(KERN_INFO "S5PC100: Initializing architecture\n"); |
| 122 | 133 | ||
| 123 | s5pc1xx_idle = s5pc100_idle; | 134 | /* set idle function */ |
| 135 | pm_idle = s5pc100_idle; | ||
| 124 | 136 | ||
| 125 | return sysdev_register(&s5pc100_sysdev); | 137 | return sysdev_register(&s5pc100_sysdev); |
| 126 | } | 138 | } |
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c new file mode 100644 index 000000000000..18cfe9ae1936 --- /dev/null +++ b/arch/arm/mach-s5pc100/dev-audio.c | |||
| @@ -0,0 +1,287 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pc100/dev-audio.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/dma-mapping.h> | ||
| 13 | |||
| 14 | #include <plat/gpio-cfg.h> | ||
| 15 | #include <plat/audio.h> | ||
| 16 | |||
| 17 | #include <mach/gpio.h> | ||
| 18 | #include <mach/map.h> | ||
| 19 | #include <mach/dma.h> | ||
| 20 | #include <mach/irqs.h> | ||
| 21 | |||
| 22 | static int s5pc100_cfg_i2s(struct platform_device *pdev) | ||
| 23 | { | ||
| 24 | /* configure GPIO for i2s port */ | ||
| 25 | switch (pdev->id) { | ||
| 26 | case 1: | ||
| 27 | s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(2)); | ||
| 28 | s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(2)); | ||
| 29 | s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(2)); | ||
| 30 | s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(2)); | ||
| 31 | s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(2)); | ||
| 32 | break; | ||
| 33 | |||
| 34 | case 2: | ||
| 35 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(4)); | ||
| 36 | s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(4)); | ||
| 37 | s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(4)); | ||
| 38 | s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(4)); | ||
| 39 | s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(4)); | ||
| 40 | break; | ||
| 41 | |||
| 42 | case -1: /* Dedicated pins */ | ||
| 43 | break; | ||
| 44 | |||
| 45 | default: | ||
| 46 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
| 47 | return -EINVAL; | ||
| 48 | } | ||
| 49 | |||
| 50 | return 0; | ||
| 51 | } | ||
| 52 | |||
| 53 | static struct s3c_audio_pdata s3c_i2s_pdata = { | ||
| 54 | .cfg_gpio = s5pc100_cfg_i2s, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static struct resource s5pc100_iis0_resource[] = { | ||
| 58 | [0] = { | ||
| 59 | .start = S5PC100_PA_I2S0, | ||
| 60 | .end = S5PC100_PA_I2S0 + 0x100 - 1, | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }, | ||
| 63 | [1] = { | ||
| 64 | .start = DMACH_I2S0_TX, | ||
| 65 | .end = DMACH_I2S0_TX, | ||
| 66 | .flags = IORESOURCE_DMA, | ||
| 67 | }, | ||
| 68 | [2] = { | ||
| 69 | .start = DMACH_I2S0_RX, | ||
| 70 | .end = DMACH_I2S0_RX, | ||
| 71 | .flags = IORESOURCE_DMA, | ||
| 72 | }, | ||
| 73 | }; | ||
| 74 | |||
| 75 | struct platform_device s5pc100_device_iis0 = { | ||
| 76 | .name = "s3c64xx-iis-v4", | ||
| 77 | .id = -1, | ||
| 78 | .num_resources = ARRAY_SIZE(s5pc100_iis0_resource), | ||
| 79 | .resource = s5pc100_iis0_resource, | ||
| 80 | .dev = { | ||
| 81 | .platform_data = &s3c_i2s_pdata, | ||
| 82 | }, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct resource s5pc100_iis1_resource[] = { | ||
| 86 | [0] = { | ||
| 87 | .start = S5PC100_PA_I2S1, | ||
| 88 | .end = S5PC100_PA_I2S1 + 0x100 - 1, | ||
| 89 | .flags = IORESOURCE_MEM, | ||
| 90 | }, | ||
| 91 | [1] = { | ||
| 92 | .start = DMACH_I2S1_TX, | ||
| 93 | .end = DMACH_I2S1_TX, | ||
| 94 | .flags = IORESOURCE_DMA, | ||
| 95 | }, | ||
| 96 | [2] = { | ||
| 97 | .start = DMACH_I2S1_RX, | ||
| 98 | .end = DMACH_I2S1_RX, | ||
| 99 | .flags = IORESOURCE_DMA, | ||
| 100 | }, | ||
| 101 | }; | ||
| 102 | |||
| 103 | struct platform_device s5pc100_device_iis1 = { | ||
| 104 | .name = "s3c64xx-iis", | ||
| 105 | .id = 1, | ||
| 106 | .num_resources = ARRAY_SIZE(s5pc100_iis1_resource), | ||
| 107 | .resource = s5pc100_iis1_resource, | ||
| 108 | .dev = { | ||
| 109 | .platform_data = &s3c_i2s_pdata, | ||
| 110 | }, | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct resource s5pc100_iis2_resource[] = { | ||
| 114 | [0] = { | ||
| 115 | .start = S5PC100_PA_I2S2, | ||
| 116 | .end = S5PC100_PA_I2S2 + 0x100 - 1, | ||
| 117 | .flags = IORESOURCE_MEM, | ||
| 118 | }, | ||
| 119 | [1] = { | ||
| 120 | .start = DMACH_I2S2_TX, | ||
| 121 | .end = DMACH_I2S2_TX, | ||
| 122 | .flags = IORESOURCE_DMA, | ||
| 123 | }, | ||
| 124 | [2] = { | ||
| 125 | .start = DMACH_I2S2_RX, | ||
| 126 | .end = DMACH_I2S2_RX, | ||
| 127 | .flags = IORESOURCE_DMA, | ||
| 128 | }, | ||
| 129 | }; | ||
| 130 | |||
| 131 | struct platform_device s5pc100_device_iis2 = { | ||
| 132 | .name = "s3c64xx-iis", | ||
| 133 | .id = 2, | ||
| 134 | .num_resources = ARRAY_SIZE(s5pc100_iis2_resource), | ||
| 135 | .resource = s5pc100_iis2_resource, | ||
| 136 | .dev = { | ||
| 137 | .platform_data = &s3c_i2s_pdata, | ||
| 138 | }, | ||
| 139 | }; | ||
| 140 | |||
| 141 | /* PCM Controller platform_devices */ | ||
| 142 | |||
| 143 | static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev) | ||
| 144 | { | ||
| 145 | switch (pdev->id) { | ||
| 146 | case 0: | ||
| 147 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(5)); | ||
| 148 | s3c_gpio_cfgpin(S5PC100_GPG3(1), S3C_GPIO_SFN(5)); | ||
| 149 | s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(5)); | ||
| 150 | s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(5)); | ||
| 151 | s3c_gpio_cfgpin(S5PC100_GPG3(4), S3C_GPIO_SFN(5)); | ||
| 152 | break; | ||
| 153 | |||
| 154 | case 1: | ||
| 155 | s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(3)); | ||
| 156 | s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(3)); | ||
| 157 | s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(3)); | ||
| 158 | s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(3)); | ||
| 159 | s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(3)); | ||
| 160 | break; | ||
| 161 | |||
| 162 | default: | ||
| 163 | printk(KERN_DEBUG "Invalid PCM Controller number!"); | ||
| 164 | return -EINVAL; | ||
| 165 | } | ||
| 166 | |||
| 167 | return 0; | ||
| 168 | } | ||
| 169 | |||
| 170 | static struct s3c_audio_pdata s3c_pcm_pdata = { | ||
| 171 | .cfg_gpio = s5pc100_pcm_cfg_gpio, | ||
| 172 | }; | ||
| 173 | |||
| 174 | static struct resource s5pc100_pcm0_resource[] = { | ||
| 175 | [0] = { | ||
| 176 | .start = S5PC100_PA_PCM0, | ||
| 177 | .end = S5PC100_PA_PCM0 + 0x100 - 1, | ||
| 178 | .flags = IORESOURCE_MEM, | ||
| 179 | }, | ||
| 180 | [1] = { | ||
| 181 | .start = DMACH_PCM0_TX, | ||
| 182 | .end = DMACH_PCM0_TX, | ||
| 183 | .flags = IORESOURCE_DMA, | ||
| 184 | }, | ||
| 185 | [2] = { | ||
| 186 | .start = DMACH_PCM0_RX, | ||
| 187 | .end = DMACH_PCM0_RX, | ||
| 188 | .flags = IORESOURCE_DMA, | ||
| 189 | }, | ||
| 190 | }; | ||
| 191 | |||
| 192 | struct platform_device s5pc100_device_pcm0 = { | ||
| 193 | .name = "samsung-pcm", | ||
| 194 | .id = 0, | ||
| 195 | .num_resources = ARRAY_SIZE(s5pc100_pcm0_resource), | ||
| 196 | .resource = s5pc100_pcm0_resource, | ||
| 197 | .dev = { | ||
| 198 | .platform_data = &s3c_pcm_pdata, | ||
| 199 | }, | ||
| 200 | }; | ||
| 201 | |||
| 202 | static struct resource s5pc100_pcm1_resource[] = { | ||
| 203 | [0] = { | ||
| 204 | .start = S5PC100_PA_PCM1, | ||
| 205 | .end = S5PC100_PA_PCM1 + 0x100 - 1, | ||
| 206 | .flags = IORESOURCE_MEM, | ||
| 207 | }, | ||
| 208 | [1] = { | ||
| 209 | .start = DMACH_PCM1_TX, | ||
| 210 | .end = DMACH_PCM1_TX, | ||
| 211 | .flags = IORESOURCE_DMA, | ||
| 212 | }, | ||
| 213 | [2] = { | ||
| 214 | .start = DMACH_PCM1_RX, | ||
| 215 | .end = DMACH_PCM1_RX, | ||
| 216 | .flags = IORESOURCE_DMA, | ||
| 217 | }, | ||
| 218 | }; | ||
| 219 | |||
| 220 | struct platform_device s5pc100_device_pcm1 = { | ||
| 221 | .name = "samsung-pcm", | ||
| 222 | .id = 1, | ||
| 223 | .num_resources = ARRAY_SIZE(s5pc100_pcm1_resource), | ||
| 224 | .resource = s5pc100_pcm1_resource, | ||
| 225 | .dev = { | ||
| 226 | .platform_data = &s3c_pcm_pdata, | ||
| 227 | }, | ||
| 228 | }; | ||
| 229 | |||
| 230 | /* AC97 Controller platform devices */ | ||
| 231 | |||
| 232 | static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) | ||
| 233 | { | ||
| 234 | s3c_gpio_cfgpin(S5PC100_GPC(0), S3C_GPIO_SFN(4)); | ||
| 235 | s3c_gpio_cfgpin(S5PC100_GPC(1), S3C_GPIO_SFN(4)); | ||
| 236 | s3c_gpio_cfgpin(S5PC100_GPC(2), S3C_GPIO_SFN(4)); | ||
| 237 | s3c_gpio_cfgpin(S5PC100_GPC(3), S3C_GPIO_SFN(4)); | ||
| 238 | s3c_gpio_cfgpin(S5PC100_GPC(4), S3C_GPIO_SFN(4)); | ||
| 239 | |||
| 240 | return 0; | ||
| 241 | } | ||
| 242 | |||
| 243 | static struct resource s5pc100_ac97_resource[] = { | ||
| 244 | [0] = { | ||
| 245 | .start = S5PC100_PA_AC97, | ||
| 246 | .end = S5PC100_PA_AC97 + 0x100 - 1, | ||
| 247 | .flags = IORESOURCE_MEM, | ||
| 248 | }, | ||
| 249 | [1] = { | ||
| 250 | .start = DMACH_AC97_PCMOUT, | ||
| 251 | .end = DMACH_AC97_PCMOUT, | ||
| 252 | .flags = IORESOURCE_DMA, | ||
| 253 | }, | ||
| 254 | [2] = { | ||
| 255 | .start = DMACH_AC97_PCMIN, | ||
| 256 | .end = DMACH_AC97_PCMIN, | ||
| 257 | .flags = IORESOURCE_DMA, | ||
| 258 | }, | ||
| 259 | [3] = { | ||
| 260 | .start = DMACH_AC97_MICIN, | ||
| 261 | .end = DMACH_AC97_MICIN, | ||
| 262 | .flags = IORESOURCE_DMA, | ||
| 263 | }, | ||
| 264 | [4] = { | ||
| 265 | .start = IRQ_AC97, | ||
| 266 | .end = IRQ_AC97, | ||
| 267 | .flags = IORESOURCE_IRQ, | ||
| 268 | }, | ||
| 269 | }; | ||
| 270 | |||
| 271 | static struct s3c_audio_pdata s3c_ac97_pdata = { | ||
| 272 | .cfg_gpio = s5pc100_ac97_cfg_gpio, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32); | ||
| 276 | |||
| 277 | struct platform_device s5pc100_device_ac97 = { | ||
| 278 | .name = "s3c-ac97", | ||
| 279 | .id = -1, | ||
| 280 | .num_resources = ARRAY_SIZE(s5pc100_ac97_resource), | ||
| 281 | .resource = s5pc100_ac97_resource, | ||
| 282 | .dev = { | ||
| 283 | .platform_data = &s3c_ac97_pdata, | ||
| 284 | .dma_mask = &s5pc100_ac97_dmamask, | ||
| 285 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 286 | }, | ||
| 287 | }; | ||
diff --git a/arch/arm/mach-s5pc100/dev-spi.c b/arch/arm/mach-s5pc100/dev-spi.c new file mode 100644 index 000000000000..14618c346057 --- /dev/null +++ b/arch/arm/mach-s5pc100/dev-spi.c | |||
| @@ -0,0 +1,233 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pc100/dev-spi.c | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/dma-mapping.h> | ||
| 13 | |||
| 14 | #include <mach/dma.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | #include <mach/gpio.h> | ||
| 17 | #include <mach/spi-clocks.h> | ||
| 18 | |||
| 19 | #include <plat/s3c64xx-spi.h> | ||
| 20 | #include <plat/gpio-cfg.h> | ||
| 21 | #include <plat/irqs.h> | ||
| 22 | |||
| 23 | static char *spi_src_clks[] = { | ||
| 24 | [S5PC100_SPI_SRCCLK_PCLK] = "pclk", | ||
| 25 | [S5PC100_SPI_SRCCLK_48M] = "spi_48m", | ||
| 26 | [S5PC100_SPI_SRCCLK_SPIBUS] = "spi_bus", | ||
| 27 | }; | ||
| 28 | |||
| 29 | /* SPI Controller platform_devices */ | ||
| 30 | |||
| 31 | /* Since we emulate multi-cs capability, we do not touch the CS. | ||
| 32 | * The emulated CS is toggled by board specific mechanism, as it can | ||
| 33 | * be either some immediate GPIO or some signal out of some other | ||
| 34 | * chip in between ... or some yet another way. | ||
| 35 | * We simply do not assume anything about CS. | ||
| 36 | */ | ||
| 37 | static int s5pc100_spi_cfg_gpio(struct platform_device *pdev) | ||
| 38 | { | ||
| 39 | switch (pdev->id) { | ||
| 40 | case 0: | ||
| 41 | s3c_gpio_cfgpin(S5PC100_GPB(0), S3C_GPIO_SFN(2)); | ||
| 42 | s3c_gpio_cfgpin(S5PC100_GPB(1), S3C_GPIO_SFN(2)); | ||
| 43 | s3c_gpio_cfgpin(S5PC100_GPB(2), S3C_GPIO_SFN(2)); | ||
| 44 | s3c_gpio_setpull(S5PC100_GPB(0), S3C_GPIO_PULL_UP); | ||
| 45 | s3c_gpio_setpull(S5PC100_GPB(1), S3C_GPIO_PULL_UP); | ||
| 46 | s3c_gpio_setpull(S5PC100_GPB(2), S3C_GPIO_PULL_UP); | ||
| 47 | break; | ||
| 48 | |||
| 49 | case 1: | ||
| 50 | s3c_gpio_cfgpin(S5PC100_GPB(4), S3C_GPIO_SFN(2)); | ||
| 51 | s3c_gpio_cfgpin(S5PC100_GPB(5), S3C_GPIO_SFN(2)); | ||
| 52 | s3c_gpio_cfgpin(S5PC100_GPB(6), S3C_GPIO_SFN(2)); | ||
| 53 | s3c_gpio_setpull(S5PC100_GPB(4), S3C_GPIO_PULL_UP); | ||
| 54 | s3c_gpio_setpull(S5PC100_GPB(5), S3C_GPIO_PULL_UP); | ||
| 55 | s3c_gpio_setpull(S5PC100_GPB(6), S3C_GPIO_PULL_UP); | ||
| 56 | break; | ||
| 57 | |||
| 58 | case 2: | ||
| 59 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); | ||
| 60 | s3c_gpio_cfgpin(S5PC100_GPG3(2), S3C_GPIO_SFN(3)); | ||
| 61 | s3c_gpio_cfgpin(S5PC100_GPG3(3), S3C_GPIO_SFN(3)); | ||
| 62 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); | ||
| 63 | s3c_gpio_setpull(S5PC100_GPG3(2), S3C_GPIO_PULL_UP); | ||
| 64 | s3c_gpio_setpull(S5PC100_GPG3(3), S3C_GPIO_PULL_UP); | ||
| 65 | break; | ||
| 66 | |||
| 67 | default: | ||
| 68 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | ||
| 69 | return -EINVAL; | ||
| 70 | } | ||
| 71 | |||
| 72 | return 0; | ||
| 73 | } | ||
| 74 | |||
| 75 | static struct resource s5pc100_spi0_resource[] = { | ||
| 76 | [0] = { | ||
| 77 | .start = S5PC100_PA_SPI0, | ||
| 78 | .end = S5PC100_PA_SPI0 + 0x100 - 1, | ||
| 79 | .flags = IORESOURCE_MEM, | ||
| 80 | }, | ||
| 81 | [1] = { | ||
| 82 | .start = DMACH_SPI0_TX, | ||
| 83 | .end = DMACH_SPI0_TX, | ||
| 84 | .flags = IORESOURCE_DMA, | ||
| 85 | }, | ||
| 86 | [2] = { | ||
| 87 | .start = DMACH_SPI0_RX, | ||
| 88 | .end = DMACH_SPI0_RX, | ||
| 89 | .flags = IORESOURCE_DMA, | ||
| 90 | }, | ||
| 91 | [3] = { | ||
| 92 | .start = IRQ_SPI0, | ||
| 93 | .end = IRQ_SPI0, | ||
| 94 | .flags = IORESOURCE_IRQ, | ||
| 95 | }, | ||
| 96 | }; | ||
| 97 | |||
| 98 | static struct s3c64xx_spi_info s5pc100_spi0_pdata = { | ||
| 99 | .cfg_gpio = s5pc100_spi_cfg_gpio, | ||
| 100 | .fifo_lvl_mask = 0x7f, | ||
| 101 | .rx_lvl_offset = 13, | ||
| 102 | .high_speed = 1, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
| 106 | |||
| 107 | struct platform_device s5pc100_device_spi0 = { | ||
| 108 | .name = "s3c64xx-spi", | ||
| 109 | .id = 0, | ||
| 110 | .num_resources = ARRAY_SIZE(s5pc100_spi0_resource), | ||
| 111 | .resource = s5pc100_spi0_resource, | ||
| 112 | .dev = { | ||
| 113 | .dma_mask = &spi_dmamask, | ||
| 114 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 115 | .platform_data = &s5pc100_spi0_pdata, | ||
| 116 | }, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct resource s5pc100_spi1_resource[] = { | ||
| 120 | [0] = { | ||
| 121 | .start = S5PC100_PA_SPI1, | ||
| 122 | .end = S5PC100_PA_SPI1 + 0x100 - 1, | ||
| 123 | .flags = IORESOURCE_MEM, | ||
| 124 | }, | ||
| 125 | [1] = { | ||
| 126 | .start = DMACH_SPI1_TX, | ||
| 127 | .end = DMACH_SPI1_TX, | ||
| 128 | .flags = IORESOURCE_DMA, | ||
| 129 | }, | ||
| 130 | [2] = { | ||
| 131 | .start = DMACH_SPI1_RX, | ||
| 132 | .end = DMACH_SPI1_RX, | ||
| 133 | .flags = IORESOURCE_DMA, | ||
| 134 | }, | ||
| 135 | [3] = { | ||
| 136 | .start = IRQ_SPI1, | ||
| 137 | .end = IRQ_SPI1, | ||
| 138 | .flags = IORESOURCE_IRQ, | ||
| 139 | }, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static struct s3c64xx_spi_info s5pc100_spi1_pdata = { | ||
| 143 | .cfg_gpio = s5pc100_spi_cfg_gpio, | ||
| 144 | .fifo_lvl_mask = 0x7f, | ||
| 145 | .rx_lvl_offset = 13, | ||
| 146 | .high_speed = 1, | ||
| 147 | }; | ||
| 148 | |||
| 149 | struct platform_device s5pc100_device_spi1 = { | ||
| 150 | .name = "s3c64xx-spi", | ||
| 151 | .id = 1, | ||
| 152 | .num_resources = ARRAY_SIZE(s5pc100_spi1_resource), | ||
| 153 | .resource = s5pc100_spi1_resource, | ||
| 154 | .dev = { | ||
| 155 | .dma_mask = &spi_dmamask, | ||
| 156 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 157 | .platform_data = &s5pc100_spi1_pdata, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static struct resource s5pc100_spi2_resource[] = { | ||
| 162 | [0] = { | ||
| 163 | .start = S5PC100_PA_SPI2, | ||
| 164 | .end = S5PC100_PA_SPI2 + 0x100 - 1, | ||
| 165 | .flags = IORESOURCE_MEM, | ||
| 166 | }, | ||
| 167 | [1] = { | ||
| 168 | .start = DMACH_SPI2_TX, | ||
| 169 | .end = DMACH_SPI2_TX, | ||
| 170 | .flags = IORESOURCE_DMA, | ||
| 171 | }, | ||
| 172 | [2] = { | ||
| 173 | .start = DMACH_SPI2_RX, | ||
| 174 | .end = DMACH_SPI2_RX, | ||
| 175 | .flags = IORESOURCE_DMA, | ||
| 176 | }, | ||
| 177 | [3] = { | ||
| 178 | .start = IRQ_SPI2, | ||
| 179 | .end = IRQ_SPI2, | ||
| 180 | .flags = IORESOURCE_IRQ, | ||
| 181 | }, | ||
| 182 | }; | ||
| 183 | |||
| 184 | static struct s3c64xx_spi_info s5pc100_spi2_pdata = { | ||
| 185 | .cfg_gpio = s5pc100_spi_cfg_gpio, | ||
| 186 | .fifo_lvl_mask = 0x7f, | ||
| 187 | .rx_lvl_offset = 13, | ||
| 188 | .high_speed = 1, | ||
| 189 | }; | ||
| 190 | |||
| 191 | struct platform_device s5pc100_device_spi2 = { | ||
| 192 | .name = "s3c64xx-spi", | ||
| 193 | .id = 2, | ||
| 194 | .num_resources = ARRAY_SIZE(s5pc100_spi2_resource), | ||
| 195 | .resource = s5pc100_spi2_resource, | ||
| 196 | .dev = { | ||
| 197 | .dma_mask = &spi_dmamask, | ||
| 198 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 199 | .platform_data = &s5pc100_spi2_pdata, | ||
| 200 | }, | ||
| 201 | }; | ||
| 202 | |||
| 203 | void __init s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | ||
| 204 | { | ||
| 205 | struct s3c64xx_spi_info *pd; | ||
| 206 | |||
| 207 | /* Reject invalid configuration */ | ||
| 208 | if (!num_cs || src_clk_nr < 0 | ||
| 209 | || src_clk_nr > S5PC100_SPI_SRCCLK_SPIBUS) { | ||
| 210 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | ||
| 211 | return; | ||
| 212 | } | ||
| 213 | |||
| 214 | switch (cntrlr) { | ||
| 215 | case 0: | ||
| 216 | pd = &s5pc100_spi0_pdata; | ||
| 217 | break; | ||
| 218 | case 1: | ||
| 219 | pd = &s5pc100_spi1_pdata; | ||
| 220 | break; | ||
| 221 | case 2: | ||
| 222 | pd = &s5pc100_spi2_pdata; | ||
| 223 | break; | ||
| 224 | default: | ||
| 225 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | ||
| 226 | __func__, cntrlr); | ||
| 227 | return; | ||
| 228 | } | ||
| 229 | |||
| 230 | pd->num_cs = num_cs; | ||
| 231 | pd->src_clk_nr = src_clk_nr; | ||
| 232 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | ||
| 233 | } | ||
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c new file mode 100644 index 000000000000..0f5517571e2c --- /dev/null +++ b/arch/arm/mach-s5pc100/dma.c | |||
| @@ -0,0 +1,167 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/dma-mapping.h> | ||
| 22 | |||
| 23 | #include <plat/devs.h> | ||
| 24 | |||
| 25 | #include <mach/map.h> | ||
| 26 | #include <mach/irqs.h> | ||
| 27 | |||
| 28 | #include <plat/s3c-pl330-pdata.h> | ||
| 29 | |||
| 30 | static u64 dma_dmamask = DMA_BIT_MASK(32); | ||
| 31 | |||
| 32 | static struct resource s5pc100_pdma0_resource[] = { | ||
| 33 | [0] = { | ||
| 34 | .start = S5PC100_PA_PDMA0, | ||
| 35 | .end = S5PC100_PA_PDMA0 + SZ_4K, | ||
| 36 | .flags = IORESOURCE_MEM, | ||
| 37 | }, | ||
| 38 | [1] = { | ||
| 39 | .start = IRQ_PDMA0, | ||
| 40 | .end = IRQ_PDMA0, | ||
| 41 | .flags = IORESOURCE_IRQ, | ||
| 42 | }, | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct s3c_pl330_platdata s5pc100_pdma0_pdata = { | ||
| 46 | .peri = { | ||
| 47 | [0] = DMACH_UART0_RX, | ||
| 48 | [1] = DMACH_UART0_TX, | ||
| 49 | [2] = DMACH_UART1_RX, | ||
| 50 | [3] = DMACH_UART1_TX, | ||
| 51 | [4] = DMACH_UART2_RX, | ||
| 52 | [5] = DMACH_UART2_TX, | ||
| 53 | [6] = DMACH_UART3_RX, | ||
| 54 | [7] = DMACH_UART3_TX, | ||
| 55 | [8] = DMACH_IRDA, | ||
| 56 | [9] = DMACH_I2S0_RX, | ||
| 57 | [10] = DMACH_I2S0_TX, | ||
| 58 | [11] = DMACH_I2S0S_TX, | ||
| 59 | [12] = DMACH_I2S1_RX, | ||
| 60 | [13] = DMACH_I2S1_TX, | ||
| 61 | [14] = DMACH_I2S2_RX, | ||
| 62 | [15] = DMACH_I2S2_TX, | ||
| 63 | [16] = DMACH_SPI0_RX, | ||
| 64 | [17] = DMACH_SPI0_TX, | ||
| 65 | [18] = DMACH_SPI1_RX, | ||
| 66 | [19] = DMACH_SPI1_TX, | ||
| 67 | [20] = DMACH_SPI2_RX, | ||
| 68 | [21] = DMACH_SPI2_TX, | ||
| 69 | [22] = DMACH_AC97_MICIN, | ||
| 70 | [23] = DMACH_AC97_PCMIN, | ||
| 71 | [24] = DMACH_AC97_PCMOUT, | ||
| 72 | [25] = DMACH_EXTERNAL, | ||
| 73 | [26] = DMACH_PWM, | ||
| 74 | [27] = DMACH_SPDIF, | ||
| 75 | [28] = DMACH_HSI_RX, | ||
| 76 | [29] = DMACH_HSI_TX, | ||
| 77 | [30] = DMACH_MAX, | ||
| 78 | [31] = DMACH_MAX, | ||
| 79 | }, | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct platform_device s5pc100_device_pdma0 = { | ||
| 83 | .name = "s3c-pl330", | ||
| 84 | .id = 1, | ||
| 85 | .num_resources = ARRAY_SIZE(s5pc100_pdma0_resource), | ||
| 86 | .resource = s5pc100_pdma0_resource, | ||
| 87 | .dev = { | ||
| 88 | .dma_mask = &dma_dmamask, | ||
| 89 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 90 | .platform_data = &s5pc100_pdma0_pdata, | ||
| 91 | }, | ||
| 92 | }; | ||
| 93 | |||
| 94 | static struct resource s5pc100_pdma1_resource[] = { | ||
| 95 | [0] = { | ||
| 96 | .start = S5PC100_PA_PDMA1, | ||
| 97 | .end = S5PC100_PA_PDMA1 + SZ_4K, | ||
| 98 | .flags = IORESOURCE_MEM, | ||
| 99 | }, | ||
| 100 | [1] = { | ||
| 101 | .start = IRQ_PDMA1, | ||
| 102 | .end = IRQ_PDMA1, | ||
| 103 | .flags = IORESOURCE_IRQ, | ||
| 104 | }, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct s3c_pl330_platdata s5pc100_pdma1_pdata = { | ||
| 108 | .peri = { | ||
| 109 | [0] = DMACH_UART0_RX, | ||
| 110 | [1] = DMACH_UART0_TX, | ||
| 111 | [2] = DMACH_UART1_RX, | ||
| 112 | [3] = DMACH_UART1_TX, | ||
| 113 | [4] = DMACH_UART2_RX, | ||
| 114 | [5] = DMACH_UART2_TX, | ||
| 115 | [6] = DMACH_UART3_RX, | ||
| 116 | [7] = DMACH_UART3_TX, | ||
| 117 | [8] = DMACH_IRDA, | ||
| 118 | [9] = DMACH_I2S0_RX, | ||
| 119 | [10] = DMACH_I2S0_TX, | ||
| 120 | [11] = DMACH_I2S0S_TX, | ||
| 121 | [12] = DMACH_I2S1_RX, | ||
| 122 | [13] = DMACH_I2S1_TX, | ||
| 123 | [14] = DMACH_I2S2_RX, | ||
| 124 | [15] = DMACH_I2S2_TX, | ||
| 125 | [16] = DMACH_SPI0_RX, | ||
| 126 | [17] = DMACH_SPI0_TX, | ||
| 127 | [18] = DMACH_SPI1_RX, | ||
| 128 | [19] = DMACH_SPI1_TX, | ||
| 129 | [20] = DMACH_SPI2_RX, | ||
| 130 | [21] = DMACH_SPI2_TX, | ||
| 131 | [22] = DMACH_PCM0_RX, | ||
| 132 | [23] = DMACH_PCM0_TX, | ||
| 133 | [24] = DMACH_PCM1_RX, | ||
| 134 | [25] = DMACH_PCM1_TX, | ||
| 135 | [26] = DMACH_MSM_REQ0, | ||
| 136 | [27] = DMACH_MSM_REQ1, | ||
| 137 | [28] = DMACH_MSM_REQ2, | ||
| 138 | [29] = DMACH_MSM_REQ3, | ||
| 139 | [30] = DMACH_MAX, | ||
| 140 | [31] = DMACH_MAX, | ||
| 141 | }, | ||
| 142 | }; | ||
| 143 | |||
| 144 | static struct platform_device s5pc100_device_pdma1 = { | ||
| 145 | .name = "s3c-pl330", | ||
| 146 | .id = 2, | ||
| 147 | .num_resources = ARRAY_SIZE(s5pc100_pdma1_resource), | ||
| 148 | .resource = s5pc100_pdma1_resource, | ||
| 149 | .dev = { | ||
| 150 | .dma_mask = &dma_dmamask, | ||
| 151 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 152 | .platform_data = &s5pc100_pdma1_pdata, | ||
| 153 | }, | ||
| 154 | }; | ||
| 155 | |||
| 156 | static struct platform_device *s5pc100_dmacs[] __initdata = { | ||
| 157 | &s5pc100_device_pdma0, | ||
| 158 | &s5pc100_device_pdma1, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static int __init s5pc100_dma_init(void) | ||
| 162 | { | ||
| 163 | platform_add_devices(s5pc100_dmacs, ARRAY_SIZE(s5pc100_dmacs)); | ||
| 164 | |||
| 165 | return 0; | ||
| 166 | } | ||
| 167 | arch_initcall(s5pc100_dma_init); | ||
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c index c8e8336a3a12..0fab7f2cd8bf 100644 --- a/arch/arm/mach-s5pc100/gpiolib.c +++ b/arch/arm/mach-s5pc100/gpiolib.c | |||
| @@ -1,10 +1,10 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-s5pc1xx/gpiolib.c | 2 | * arch/arm/plat-s5pc100/gpiolib.c |
| 3 | * | 3 | * |
| 4 | * Copyright 2009 Samsung Electronics Co | 4 | * Copyright 2009 Samsung Electronics Co |
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | 5 | * Kyungmin Park <kyungmin.park@samsung.com> |
| 6 | * | 6 | * |
| 7 | * S5PC1XX - GPIOlib support | 7 | * S5PC100 - GPIOlib support |
| 8 | * | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License version 2 as | 10 | * it under the terms of the GNU General Public License version 2 as |
| @@ -61,13 +61,12 @@ | |||
| 61 | * L3 8 4Bit None | 61 | * L3 8 4Bit None |
| 62 | */ | 62 | */ |
| 63 | 63 | ||
| 64 | #if 0 | 64 | static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) |
| 65 | static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) | ||
| 66 | { | 65 | { |
| 67 | return S3C_IRQ_GPIO(chip->base + offset); | 66 | return S3C_IRQ_GPIO(chip->base + offset); |
| 68 | } | 67 | } |
| 69 | 68 | ||
| 70 | static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) | 69 | static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) |
| 71 | { | 70 | { |
| 72 | int base; | 71 | int base; |
| 73 | 72 | ||
| @@ -85,7 +84,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) | |||
| 85 | return IRQ_EINT(24 + offset); | 84 | return IRQ_EINT(24 + offset); |
| 86 | return -EINVAL; | 85 | return -EINVAL; |
| 87 | } | 86 | } |
| 88 | #endif | 87 | |
| 89 | static struct s3c_gpio_cfg gpio_cfg = { | 88 | static struct s3c_gpio_cfg gpio_cfg = { |
| 90 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | 89 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, |
| 91 | .set_pull = s3c_gpio_setpull_updown, | 90 | .set_pull = s3c_gpio_setpull_updown, |
| @@ -382,31 +381,30 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { | |||
| 382 | }; | 381 | }; |
| 383 | 382 | ||
| 384 | /* FIXME move from irq-gpio.c */ | 383 | /* FIXME move from irq-gpio.c */ |
| 385 | extern struct irq_chip s5pc1xx_gpioint; | 384 | extern struct irq_chip s5pc100_gpioint; |
| 386 | extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); | 385 | extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); |
| 387 | 386 | ||
| 388 | static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) | 387 | static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip) |
| 389 | { | 388 | { |
| 390 | #if 0 | ||
| 391 | /* Interrupt */ | 389 | /* Interrupt */ |
| 392 | if (chip->config == &gpio_cfg) { | 390 | if (chip->config == &gpio_cfg) { |
| 393 | int i, irq; | 391 | int i, irq; |
| 394 | 392 | ||
| 395 | chip->chip.to_irq = s5pc1xx_gpiolib_to_irq; | 393 | chip->chip.to_irq = s5pc100_gpiolib_to_irq; |
| 396 | 394 | ||
| 397 | for (i = 0; i < chip->chip.ngpio; i++) { | 395 | for (i = 0; i < chip->chip.ngpio; i++) { |
| 398 | irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; | 396 | irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i; |
| 399 | set_irq_chip(irq, &s5pc1xx_gpioint); | 397 | set_irq_chip(irq, &s5pc100_gpioint); |
| 400 | set_irq_data(irq, &chip->chip); | 398 | set_irq_data(irq, &chip->chip); |
| 401 | set_irq_handler(irq, handle_level_irq); | 399 | set_irq_handler(irq, handle_level_irq); |
| 402 | set_irq_flags(irq, IRQF_VALID); | 400 | set_irq_flags(irq, IRQF_VALID); |
| 403 | } | 401 | } |
| 404 | } else if (chip->config == &gpio_cfg_eint) | 402 | } else if (chip->config == &gpio_cfg_eint) { |
| 405 | chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; | 403 | chip->chip.to_irq = s5pc100_gpiolib_to_eint; |
| 406 | #endif | 404 | } |
| 407 | } | 405 | } |
| 408 | 406 | ||
| 409 | static __init int s5pc1xx_gpiolib_init(void) | 407 | static __init int s5pc100_gpiolib_init(void) |
| 410 | { | 408 | { |
| 411 | struct s3c_gpio_chip *chip; | 409 | struct s3c_gpio_chip *chip; |
| 412 | int nr_chips; | 410 | int nr_chips; |
| @@ -419,10 +417,10 @@ static __init int s5pc1xx_gpiolib_init(void) | |||
| 419 | 417 | ||
| 420 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, | 418 | samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, |
| 421 | ARRAY_SIZE(s5pc100_gpio_chips)); | 419 | ARRAY_SIZE(s5pc100_gpio_chips)); |
| 422 | #if 0 | 420 | |
| 423 | /* Interrupt */ | 421 | /* Interrupt */ |
| 424 | set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); | 422 | set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler); |
| 425 | #endif | 423 | |
| 426 | return 0; | 424 | return 0; |
| 427 | } | 425 | } |
| 428 | core_initcall(s5pc1xx_gpiolib_init); | 426 | core_initcall(s5pc100_gpiolib_init); |
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S index e181f5789482..70e02e91ee3c 100644 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S | |||
| @@ -22,12 +22,14 @@ | |||
| 22 | * aligned and add in the offset when we load the value here. | 22 | * aligned and add in the offset when we load the value here. |
| 23 | */ | 23 | */ |
| 24 | 24 | ||
| 25 | .macro addruart, rx, tmp | 25 | .macro addruart, rx, rtmp |
| 26 | mrc p15, 0, \rx, c1, c0 | 26 | mrc p15, 0, \rx, c1, c0 |
| 27 | tst \rx, #1 | 27 | tst \rx, #1 |
| 28 | ldreq \rx, = S3C_PA_UART | 28 | ldreq \rx, = S3C_PA_UART |
| 29 | ldrne \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) | 29 | ldrne \rx, = S3C_VA_UART |
| 30 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
| 30 | add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) | 31 | add \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART) |
| 32 | #endif | ||
| 31 | .endm | 33 | .endm |
| 32 | 34 | ||
| 33 | /* include the reset of the code which will do the work, we're only | 35 | /* include the reset of the code which will do the work, we're only |
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h new file mode 100644 index 000000000000..81209eb1409b --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/dma.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __MACH_DMA_H | ||
| 21 | #define __MACH_DMA_H | ||
| 22 | |||
| 23 | /* This platform uses the common S3C DMA API driver for PL330 */ | ||
| 24 | #include <plat/s3c-dma-pl330.h> | ||
| 25 | |||
| 26 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S index 67131939e626..ba76af052c81 100644 --- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S +++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | .endm | 20 | .endm |
| 21 | 21 | ||
| 22 | .macro get_irqnr_preamble, base, tmp | 22 | .macro get_irqnr_preamble, base, tmp |
| 23 | ldr \base, =S3C_VA_VIC0 | 23 | ldr \base, =VA_VIC0 |
| 24 | .endm | 24 | .endm |
| 25 | 25 | ||
| 26 | .macro arch_ret_to_user, tmp1, tmp2 | 26 | .macro arch_ret_to_user, tmp1, tmp2 |
| @@ -29,18 +29,18 @@ | |||
| 29 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 29 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
| 30 | 30 | ||
| 31 | @ check the vic0 | 31 | @ check the vic0 |
| 32 | mov \irqnr, # S3C_IRQ_OFFSET + 31 | 32 | mov \irqnr, # S5P_IRQ_OFFSET + 31 |
| 33 | ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] | 33 | ldr \irqstat, [ \base, # VIC_IRQ_STATUS ] |
| 34 | teq \irqstat, #0 | 34 | teq \irqstat, #0 |
| 35 | 35 | ||
| 36 | @ otherwise try vic1 | 36 | @ otherwise try vic1 |
| 37 | addeq \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0) | 37 | addeq \tmp, \base, #(VA_VIC1 - VA_VIC0) |
| 38 | addeq \irqnr, \irqnr, #32 | 38 | addeq \irqnr, \irqnr, #32 |
| 39 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | 39 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] |
| 40 | teqeq \irqstat, #0 | 40 | teqeq \irqstat, #0 |
| 41 | 41 | ||
| 42 | @ otherwise try vic2 | 42 | @ otherwise try vic2 |
| 43 | addeq \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0) | 43 | addeq \tmp, \base, #(VA_VIC2 - VA_VIC0) |
| 44 | addeq \irqnr, \irqnr, #32 | 44 | addeq \irqnr, \irqnr, #32 |
| 45 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] | 45 | ldreq \irqstat, [ \tmp, # VIC_IRQ_STATUS ] |
| 46 | teqeq \irqstat, #0 | 46 | teqeq \irqstat, #0 |
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h index 29a8a12d9b4f..71ae1f52df1d 100644 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/gpio.h | |||
| @@ -146,6 +146,13 @@ enum s5p_gpio_number { | |||
| 146 | /* define the number of gpios we need to the one after the MP04() range */ | 146 | /* define the number of gpios we need to the one after the MP04() range */ |
| 147 | #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) | 147 | #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) |
| 148 | 148 | ||
| 149 | #define EINT_MODE S3C_GPIO_SFN(0x2) | ||
| 150 | |||
| 151 | #define EINT_GPIO_0(x) S5PC100_GPH0(x) | ||
| 152 | #define EINT_GPIO_1(x) S5PC100_GPH1(x) | ||
| 153 | #define EINT_GPIO_2(x) S5PC100_GPH2(x) | ||
| 154 | #define EINT_GPIO_3(x) S5PC100_GPH3(x) | ||
| 155 | |||
| 149 | #include <asm-generic/gpio.h> | 156 | #include <asm-generic/gpio.h> |
| 150 | 157 | ||
| 151 | #endif /* __ASM_ARCH_GPIO_H */ | 158 | #endif /* __ASM_ARCH_GPIO_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h index b53fa48a52c6..15066df3ced9 100644 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ b/arch/arm/mach-s5pc100/include/mach/irqs.h | |||
| @@ -11,9 +11,107 @@ | |||
| 11 | 11 | ||
| 12 | #include <plat/irqs.h> | 12 | #include <plat/irqs.h> |
| 13 | 13 | ||
| 14 | /* LCD */ | 14 | /* VIC0: system, DMA, timer */ |
| 15 | #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) | ||
| 16 | #define IRQ_BATF S5P_IRQ_VIC0(17) | ||
| 17 | #define IRQ_MDMA S5P_IRQ_VIC0(18) | ||
| 18 | #define IRQ_PDMA0 S5P_IRQ_VIC0(19) | ||
| 19 | #define IRQ_PDMA1 S5P_IRQ_VIC0(20) | ||
| 20 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) | ||
| 21 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) | ||
| 22 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) | ||
| 23 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) | ||
| 24 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) | ||
| 25 | #define IRQ_SYSTIMER S5P_IRQ_VIC0(26) | ||
| 26 | #define IRQ_WDT S5P_IRQ_VIC0(27) | ||
| 27 | #define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) | ||
| 28 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(29) | ||
| 29 | #define IRQ_GPIOINT S5P_IRQ_VIC0(30) | ||
| 30 | |||
| 31 | /* VIC1: ARM, power, memory, connectivity */ | ||
| 32 | #define IRQ_CORTEX0 S5P_IRQ_VIC1(0) | ||
| 33 | #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) | ||
| 34 | #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) | ||
| 35 | #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) | ||
| 36 | #define IRQ_CORTEX4 S5P_IRQ_VIC1(4) | ||
| 37 | #define IRQ_IEMAPC S5P_IRQ_VIC1(5) | ||
| 38 | #define IRQ_IEMIEC S5P_IRQ_VIC1(6) | ||
| 39 | #define IRQ_ONENAND S5P_IRQ_VIC1(7) | ||
| 40 | #define IRQ_NFC S5P_IRQ_VIC1(8) | ||
| 41 | #define IRQ_CFC S5P_IRQ_VIC1(9) | ||
| 42 | #define IRQ_UART0 S5P_IRQ_VIC1(10) | ||
| 43 | #define IRQ_UART1 S5P_IRQ_VIC1(11) | ||
| 44 | #define IRQ_UART2 S5P_IRQ_VIC1(12) | ||
| 45 | #define IRQ_UART3 S5P_IRQ_VIC1(13) | ||
| 46 | #define IRQ_IIC S5P_IRQ_VIC1(14) | ||
| 47 | #define IRQ_SPI0 S5P_IRQ_VIC1(15) | ||
| 48 | #define IRQ_SPI1 S5P_IRQ_VIC1(16) | ||
| 49 | #define IRQ_SPI2 S5P_IRQ_VIC1(17) | ||
| 50 | #define IRQ_IRDA S5P_IRQ_VIC1(18) | ||
| 51 | #define IRQ_CAN0 S5P_IRQ_VIC1(19) | ||
| 52 | #define IRQ_CAN1 S5P_IRQ_VIC1(20) | ||
| 53 | #define IRQ_HSIRX S5P_IRQ_VIC1(21) | ||
| 54 | #define IRQ_HSITX S5P_IRQ_VIC1(22) | ||
| 55 | #define IRQ_UHOST S5P_IRQ_VIC1(23) | ||
| 56 | #define IRQ_OTG S5P_IRQ_VIC1(24) | ||
| 57 | #define IRQ_MSM S5P_IRQ_VIC1(25) | ||
| 58 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(26) | ||
| 59 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(27) | ||
| 60 | #define IRQ_HSMMC2 S5P_IRQ_VIC1(28) | ||
| 61 | #define IRQ_MIPICSI S5P_IRQ_VIC1(29) | ||
| 62 | #define IRQ_MIPIDSI S5P_IRQ_VIC1(30) | ||
| 63 | |||
| 64 | /* VIC2: multimedia, audio, security */ | ||
| 65 | #define IRQ_LCD0 S5P_IRQ_VIC2(0) | ||
| 66 | #define IRQ_LCD1 S5P_IRQ_VIC2(1) | ||
| 67 | #define IRQ_LCD2 S5P_IRQ_VIC2(2) | ||
| 68 | #define IRQ_LCD3 S5P_IRQ_VIC2(3) | ||
| 69 | #define IRQ_ROTATOR S5P_IRQ_VIC2(4) | ||
| 70 | #define IRQ_FIMC0 S5P_IRQ_VIC2(5) | ||
| 71 | #define IRQ_FIMC1 S5P_IRQ_VIC2(6) | ||
| 72 | #define IRQ_FIMC2 S5P_IRQ_VIC2(7) | ||
| 73 | #define IRQ_JPEG S5P_IRQ_VIC2(8) | ||
| 74 | #define IRQ_2D S5P_IRQ_VIC2(9) | ||
| 75 | #define IRQ_3D S5P_IRQ_VIC2(10) | ||
| 76 | #define IRQ_MIXER S5P_IRQ_VIC2(11) | ||
| 77 | #define IRQ_HDMI S5P_IRQ_VIC2(12) | ||
| 78 | #define IRQ_IIC1 S5P_IRQ_VIC2(13) | ||
| 79 | #define IRQ_MFC S5P_IRQ_VIC2(14) | ||
| 80 | #define IRQ_TVENC S5P_IRQ_VIC2(15) | ||
| 81 | #define IRQ_I2S0 S5P_IRQ_VIC2(16) | ||
| 82 | #define IRQ_I2S1 S5P_IRQ_VIC2(17) | ||
| 83 | #define IRQ_I2S2 S5P_IRQ_VIC2(18) | ||
| 84 | #define IRQ_AC97 S5P_IRQ_VIC2(19) | ||
| 85 | #define IRQ_PCM0 S5P_IRQ_VIC2(20) | ||
| 86 | #define IRQ_PCM1 S5P_IRQ_VIC2(21) | ||
| 87 | #define IRQ_SPDIF S5P_IRQ_VIC2(22) | ||
| 88 | #define IRQ_ADC S5P_IRQ_VIC2(23) | ||
| 89 | #define IRQ_PENDN S5P_IRQ_VIC2(24) | ||
| 90 | #define IRQ_TC IRQ_PENDN | ||
| 91 | #define IRQ_KEYPAD S5P_IRQ_VIC2(25) | ||
| 92 | #define IRQ_CG S5P_IRQ_VIC2(26) | ||
| 93 | #define IRQ_SEC S5P_IRQ_VIC2(27) | ||
| 94 | #define IRQ_SECRX S5P_IRQ_VIC2(28) | ||
| 95 | #define IRQ_SECTX S5P_IRQ_VIC2(29) | ||
| 96 | #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) | ||
| 97 | #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) | ||
| 98 | #define IRQ_VIC_END S5P_IRQ_VIC2(31) | ||
| 99 | |||
| 100 | #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) | ||
| 101 | #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) | ||
| 102 | |||
| 103 | #define IRQ_EINT(x) ((x) < 16 ? S5P_IRQ_VIC0(x) : \ | ||
| 104 | (S5P_EINT_BASE2 + (x) - 16)) | ||
| 105 | |||
| 106 | #define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) | ||
| 107 | #define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) | ||
| 108 | |||
| 109 | /* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */ | ||
| 110 | #define NR_IRQS (S3C_IRQ_GPIO(320) + 1) | ||
| 111 | |||
| 112 | /* Compatibility */ | ||
| 15 | #define IRQ_LCD_FIFO IRQ_LCD0 | 113 | #define IRQ_LCD_FIFO IRQ_LCD0 |
| 16 | #define IRQ_LCD_VSYNC IRQ_LCD1 | 114 | #define IRQ_LCD_VSYNC IRQ_LCD1 |
| 17 | #define IRQ_LCD_SYSTEM IRQ_LCD2 | 115 | #define IRQ_LCD_SYSTEM IRQ_LCD2 |
| 18 | 116 | ||
| 19 | #endif /* __ASM_ARCH_IRQ_H */ | 117 | #endif /* __ASM_ARCH_IRQS_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h index 4681ebe8bef6..cadae4305688 100644 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ b/arch/arm/mach-s5pc100/include/mach/map.h | |||
| @@ -3,9 +3,7 @@ | |||
| 3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * | 5 | * |
| 6 | * Based on mach-s3c6400/include/mach/map.h | 6 | * S5PC100 - Memory map definitions |
| 7 | * | ||
| 8 | * S5PC1XX - Memory map definitions | ||
| 9 | * | 7 | * |
| 10 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| @@ -16,6 +14,7 @@ | |||
| 16 | #define __ASM_ARCH_MAP_H __FILE__ | 14 | #define __ASM_ARCH_MAP_H __FILE__ |
| 17 | 15 | ||
| 18 | #include <plat/map-base.h> | 16 | #include <plat/map-base.h> |
| 17 | #include <plat/map-s5p.h> | ||
| 19 | 18 | ||
| 20 | /* | 19 | /* |
| 21 | * map-base.h has already defined virtual memory address | 20 | * map-base.h has already defined virtual memory address |
| @@ -31,25 +30,21 @@ | |||
| 31 | * | 30 | * |
| 32 | */ | 31 | */ |
| 33 | 32 | ||
| 33 | #define S5PC100_PA_ONENAND_BUF (0xB0000000) | ||
| 34 | #define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M) | ||
| 35 | |||
| 34 | /* Chip ID */ | 36 | /* Chip ID */ |
| 37 | |||
| 35 | #define S5PC100_PA_CHIPID (0xE0000000) | 38 | #define S5PC100_PA_CHIPID (0xE0000000) |
| 36 | #define S5PC1XX_PA_CHIPID S5PC100_PA_CHIPID | 39 | #define S5P_PA_CHIPID S5PC100_PA_CHIPID |
| 37 | #define S5PC1XX_VA_CHIPID S3C_VA_SYS | 40 | |
| 38 | 41 | #define S5PC100_PA_SYSCON (0xE0100000) | |
| 39 | /* System */ | 42 | #define S5P_PA_SYSCON S5PC100_PA_SYSCON |
| 40 | #define S5PC100_PA_CLK (0xE0100000) | 43 | |
| 41 | #define S5PC100_PA_CLK_OTHER (0xE0200000) | 44 | #define S5PC100_PA_OTHERS (0xE0200000) |
| 42 | #define S5PC100_PA_PWR (0xE0108000) | 45 | #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) |
| 43 | #define S5PC1XX_PA_CLK S5PC100_PA_CLK | 46 | |
| 44 | #define S5PC1XX_PA_PWR S5PC100_PA_PWR | 47 | #define S5P_PA_GPIO (0xE0300000) |
| 45 | #define S5PC1XX_PA_CLK_OTHER S5PC100_PA_CLK_OTHER | ||
| 46 | #define S5PC1XX_VA_CLK (S3C_VA_SYS + 0x10000) | ||
| 47 | #define S5PC1XX_VA_PWR (S3C_VA_SYS + 0x20000) | ||
| 48 | #define S5PC1XX_VA_CLK_OTHER (S3C_VA_SYS + 0x30000) | ||
| 49 | |||
| 50 | /* GPIO */ | ||
| 51 | #define S5PC100_PA_GPIO (0xE0300000) | ||
| 52 | #define S5PC1XX_PA_GPIO S5PC100_PA_GPIO | ||
| 53 | #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) | 48 | #define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) |
| 54 | 49 | ||
| 55 | /* Interrupt */ | 50 | /* Interrupt */ |
| @@ -59,6 +54,12 @@ | |||
| 59 | #define S5PC100_VA_VIC_OFFSET 0x10000 | 54 | #define S5PC100_VA_VIC_OFFSET 0x10000 |
| 60 | #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) | 55 | #define S5PC1XX_PA_VIC(x) (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET)) |
| 61 | #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) | 56 | #define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET)) |
| 57 | #define S5P_PA_VIC0 S5PC1XX_PA_VIC(0) | ||
| 58 | #define S5P_PA_VIC1 S5PC1XX_PA_VIC(1) | ||
| 59 | #define S5P_PA_VIC2 S5PC1XX_PA_VIC(2) | ||
| 60 | |||
| 61 | |||
| 62 | #define S5PC100_PA_ONENAND (0xE7100000) | ||
| 62 | 63 | ||
| 63 | /* DMA */ | 64 | /* DMA */ |
| 64 | #define S5PC100_PA_MDMA (0xE8100000) | 65 | #define S5PC100_PA_MDMA (0xE8100000) |
| @@ -67,84 +68,71 @@ | |||
| 67 | 68 | ||
| 68 | /* Timer */ | 69 | /* Timer */ |
| 69 | #define S5PC100_PA_TIMER (0xEA000000) | 70 | #define S5PC100_PA_TIMER (0xEA000000) |
| 70 | #define S5PC1XX_PA_TIMER S5PC100_PA_TIMER | 71 | #define S5P_PA_TIMER S5PC100_PA_TIMER |
| 71 | #define S5PC1XX_VA_TIMER S3C_VA_TIMER | ||
| 72 | 72 | ||
| 73 | /* RTC */ | 73 | #define S5PC100_PA_SYSTIMER (0xEA100000) |
| 74 | #define S5PC100_PA_RTC (0xEA300000) | ||
| 75 | 74 | ||
| 76 | /* UART */ | ||
| 77 | #define S5PC100_PA_UART (0xEC000000) | 75 | #define S5PC100_PA_UART (0xEC000000) |
| 78 | #define S5PC1XX_PA_UART S5PC100_PA_UART | ||
| 79 | #define S5PC1XX_VA_UART S3C_VA_UART | ||
| 80 | 76 | ||
| 81 | /* I2C */ | 77 | #define S5P_PA_UART0 (S5PC100_PA_UART + 0x0) |
| 82 | #define S5PC100_PA_I2C (0xEC100000) | 78 | #define S5P_PA_UART1 (S5PC100_PA_UART + 0x400) |
| 83 | #define S5PC100_PA_I2C1 (0xEC200000) | 79 | #define S5P_PA_UART2 (S5PC100_PA_UART + 0x800) |
| 80 | #define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00) | ||
| 81 | #define S5P_SZ_UART SZ_256 | ||
| 82 | |||
| 83 | #define S5PC100_PA_IIC0 (0xEC100000) | ||
| 84 | #define S5PC100_PA_IIC1 (0xEC200000) | ||
| 85 | |||
| 86 | /* SPI */ | ||
| 87 | #define S5PC100_PA_SPI0 0xEC300000 | ||
| 88 | #define S5PC100_PA_SPI1 0xEC400000 | ||
| 89 | #define S5PC100_PA_SPI2 0xEC500000 | ||
| 84 | 90 | ||
| 85 | /* USB HS OTG */ | 91 | /* USB HS OTG */ |
| 86 | #define S5PC100_PA_USB_HSOTG (0xED200000) | 92 | #define S5PC100_PA_USB_HSOTG (0xED200000) |
| 87 | #define S5PC100_PA_USB_HSPHY (0xED300000) | 93 | #define S5PC100_PA_USB_HSPHY (0xED300000) |
| 88 | 94 | ||
| 89 | /* SD/MMC */ | ||
| 90 | #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) | ||
| 91 | #define S5PC100_PA_HSMMC0 S5PC100_PA_HSMMC(0) | ||
| 92 | #define S5PC100_PA_HSMMC1 S5PC100_PA_HSMMC(1) | ||
| 93 | #define S5PC100_PA_HSMMC2 S5PC100_PA_HSMMC(2) | ||
| 94 | |||
| 95 | /* LCD */ | ||
| 96 | #define S5PC100_PA_FB (0xEE000000) | 95 | #define S5PC100_PA_FB (0xEE000000) |
| 97 | 96 | ||
| 98 | /* Multimedia */ | ||
| 99 | #define S5PC100_PA_G2D (0xEE800000) | ||
| 100 | #define S5PC100_PA_JPEG (0xEE500000) | ||
| 101 | #define S5PC100_PA_ROTATOR (0xEE100000) | ||
| 102 | #define S5PC100_PA_G3D (0xEF000000) | ||
| 103 | |||
| 104 | /* I2S */ | ||
| 105 | #define S5PC100_PA_I2S0 (0xF2000000) | 97 | #define S5PC100_PA_I2S0 (0xF2000000) |
| 106 | #define S5PC100_PA_I2S1 (0xF2100000) | 98 | #define S5PC100_PA_I2S1 (0xF2100000) |
| 107 | #define S5PC100_PA_I2S2 (0xF2200000) | 99 | #define S5PC100_PA_I2S2 (0xF2200000) |
| 108 | 100 | ||
| 101 | #define S5PC100_PA_AC97 0xF2300000 | ||
| 102 | |||
| 103 | /* PCM */ | ||
| 104 | #define S5PC100_PA_PCM0 0xF2400000 | ||
| 105 | #define S5PC100_PA_PCM1 0xF2500000 | ||
| 106 | |||
| 109 | /* KEYPAD */ | 107 | /* KEYPAD */ |
| 110 | #define S5PC100_PA_KEYPAD (0xF3100000) | 108 | #define S5PC100_PA_KEYPAD (0xF3100000) |
| 111 | 109 | ||
| 112 | /* ADC & TouchScreen */ | 110 | #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) |
| 113 | #define S5PC100_PA_TSADC (0xF3000000) | ||
| 114 | 111 | ||
| 115 | /* ETC */ | ||
| 116 | #define S5PC100_PA_SDRAM (0x20000000) | 112 | #define S5PC100_PA_SDRAM (0x20000000) |
| 117 | #define S5PC1XX_PA_SDRAM S5PC100_PA_SDRAM | 113 | #define S5P_PA_SDRAM S5PC100_PA_SDRAM |
| 118 | 114 | ||
| 119 | /* compatibility defines. */ | 115 | /* compatibiltiy defines. */ |
| 120 | #define S3C_PA_RTC S5PC100_PA_RTC | ||
| 121 | #define S3C_PA_UART S5PC100_PA_UART | 116 | #define S3C_PA_UART S5PC100_PA_UART |
| 122 | #define S3C_PA_UART0 (S5PC100_PA_UART + 0x0) | 117 | #define S3C_PA_IIC S5PC100_PA_IIC0 |
| 123 | #define S3C_PA_UART1 (S5PC100_PA_UART + 0x400) | 118 | #define S3C_PA_IIC1 S5PC100_PA_IIC1 |
| 124 | #define S3C_PA_UART2 (S5PC100_PA_UART + 0x800) | ||
| 125 | #define S3C_PA_UART3 (S5PC100_PA_UART + 0xC00) | ||
| 126 | #define S3C_VA_UART0 (S3C_VA_UART + 0x0) | ||
| 127 | #define S3C_VA_UART1 (S3C_VA_UART + 0x400) | ||
| 128 | #define S3C_VA_UART2 (S3C_VA_UART + 0x800) | ||
| 129 | #define S3C_VA_UART3 (S3C_VA_UART + 0xC00) | ||
| 130 | #define S3C_UART_OFFSET 0x400 | ||
| 131 | #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) | ||
| 132 | #define S3C_PA_FB S5PC100_PA_FB | 119 | #define S3C_PA_FB S5PC100_PA_FB |
| 133 | #define S3C_PA_G2D S5PC100_PA_G2D | 120 | #define S3C_PA_G2D S5PC100_PA_G2D |
| 134 | #define S3C_PA_G3D S5PC100_PA_G3D | 121 | #define S3C_PA_G3D S5PC100_PA_G3D |
| 135 | #define S3C_PA_JPEG S5PC100_PA_JPEG | 122 | #define S3C_PA_JPEG S5PC100_PA_JPEG |
| 136 | #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR | 123 | #define S3C_PA_ROTATOR S5PC100_PA_ROTATOR |
| 137 | #define S3C_VA_VIC0 (S3C_VA_IRQ + 0x0) | 124 | #define S5P_VA_VIC0 S5PC1XX_VA_VIC(0) |
| 138 | #define S3C_VA_VIC1 (S3C_VA_IRQ + 0x10000) | 125 | #define S5P_VA_VIC1 S5PC1XX_VA_VIC(1) |
| 139 | #define S3C_VA_VIC2 (S3C_VA_IRQ + 0x20000) | 126 | #define S5P_VA_VIC2 S5PC1XX_VA_VIC(2) |
| 140 | #define S3C_PA_IIC S5PC100_PA_I2C | ||
| 141 | #define S3C_PA_IIC1 S5PC100_PA_I2C1 | ||
| 142 | #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG | 127 | #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG |
| 143 | #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY | 128 | #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY |
| 144 | #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC0 | 129 | #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) |
| 145 | #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC1 | 130 | #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) |
| 146 | #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC2 | 131 | #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) |
| 147 | #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD | 132 | #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD |
| 148 | #define S3C_PA_TSADC S5PC100_PA_TSADC | 133 | #define S3C_PA_TSADC S5PC100_PA_TSADC |
| 134 | #define S3C_PA_ONENAND S5PC100_PA_ONENAND | ||
| 135 | #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF | ||
| 136 | #define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF | ||
| 149 | 137 | ||
| 150 | #endif /* __ASM_ARCH_C100_MAP_H */ | 138 | #endif /* __ASM_ARCH_C100_MAP_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h index f2283bdc941e..5d27d286d504 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h | |||
| @@ -17,6 +17,8 @@ | |||
| 17 | 17 | ||
| 18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | 18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) |
| 19 | 19 | ||
| 20 | #define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x)) | ||
| 21 | |||
| 20 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | 22 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) |
| 21 | #define S5P_MPLL_LOCK S5P_CLKREG(0x04) | 23 | #define S5P_MPLL_LOCK S5P_CLKREG(0x04) |
| 22 | #define S5P_EPLL_LOCK S5P_CLKREG(0x08) | 24 | #define S5P_EPLL_LOCK S5P_CLKREG(0x08) |
| @@ -68,4 +70,8 @@ | |||
| 68 | #define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) | 70 | #define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) |
| 69 | #define S5P_CLKDIV1_PCLKD1_SHIFT (16) | 71 | #define S5P_CLKDIV1_PCLKD1_SHIFT (16) |
| 70 | 72 | ||
| 73 | #define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) | ||
| 74 | |||
| 75 | #define S5PC100_SWRESET_RESETVAL 0xc100 | ||
| 76 | |||
| 71 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | 77 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h index 68666913354c..763edebdd577 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h | |||
| @@ -1,4 +1,4 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/regs-gpio.h | 1 | /* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h |
| 2 | * | 2 | * |
| 3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
| @@ -12,7 +12,7 @@ | |||
| 12 | #include <mach/map.h> | 12 | #include <mach/map.h> |
| 13 | 13 | ||
| 14 | /* S5PC100 */ | 14 | /* S5PC100 */ |
| 15 | #define S5PC100_GPIO_BASE S5PC1XX_VA_GPIO | 15 | #define S5PC100_GPIO_BASE S5P_VA_GPIO |
| 16 | #define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) | 16 | #define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000) |
| 17 | #define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) | 17 | #define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020) |
| 18 | #define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) | 18 | #define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040) |
| @@ -47,24 +47,32 @@ | |||
| 47 | #define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) | 47 | #define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360) |
| 48 | #define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) | 48 | #define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380) |
| 49 | #define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) | 49 | #define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0) |
| 50 | #define S5PC100_EINT_BASE (S5PC100_GPIO_BASE + 0x0E00) | ||
| 51 | 50 | ||
| 52 | #define S5PC100_UHOST (S5PC100_GPIO_BASE + 0x0B68) | 51 | #define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00) |
| 53 | #define S5PC100_PDNEN (S5PC100_GPIO_BASE + 0x0F80) | 52 | #define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4)) |
| 54 | 53 | ||
| 55 | /* PDNEN */ | 54 | #define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) |
| 56 | #define S5PC100_PDNEN_CFG_PDNEN (1 << 1) | 55 | #define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4)) |
| 57 | #define S5PC100_PDNEN_CFG_AUTO (0 << 1) | ||
| 58 | #define S5PC100_PDNEN_POWERDOWN (1 << 0) | ||
| 59 | #define S5PC100_PDNEN_NORMAL (0 << 0) | ||
| 60 | 56 | ||
| 61 | /* Common part */ | 57 | #define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00) |
| 62 | /* External interrupt base is same at both s5pc100 and s5pc110 */ | 58 | #define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4)) |
| 63 | #define S5PC1XX_EINT_BASE (S5PC100_EINT_BASE) | ||
| 64 | 59 | ||
| 65 | #define S5PC100_GPx_INPUT(__gpio) (0x0 << ((__gpio) * 4)) | 60 | #define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40) |
| 66 | #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) | 61 | #define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4)) |
| 67 | #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) | 62 | |
| 63 | #define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) : \ | ||
| 64 | (((irq) - S5P_EINT_BASE2))) | ||
| 65 | |||
| 66 | #define EINT_REG_NR(x) (eint_offset(x) >> 3) | ||
| 67 | |||
| 68 | #define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7)) | ||
| 69 | |||
| 70 | /* values for S5P_EXTINT0 */ | ||
| 71 | #define S5P_EXTINT_LOWLEV (0x00) | ||
| 72 | #define S5P_EXTINT_HILEV (0x01) | ||
| 73 | #define S5P_EXTINT_FALLEDGE (0x02) | ||
| 74 | #define S5P_EXTINT_RISEEDGE (0x03) | ||
| 75 | #define S5P_EXTINT_BOTHEDGE (0x04) | ||
| 68 | 76 | ||
| 69 | #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ | 77 | #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ |
| 70 | 78 | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h index 751ac15438c8..4d9036d0f288 100644 --- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h +++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * | 5 | * |
| 6 | * S5PC1XX - IRQ register definitions | 6 | * S5PC100 - IRQ register definitions |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| @@ -16,9 +16,4 @@ | |||
| 16 | #include <mach/map.h> | 16 | #include <mach/map.h> |
| 17 | #include <asm/hardware/vic.h> | 17 | #include <asm/hardware/vic.h> |
| 18 | 18 | ||
| 19 | /* interrupt controller */ | ||
| 20 | #define S5PC1XX_VIC0REG(x) ((x) + S5PC1XX_VA_VIC(0)) | ||
| 21 | #define S5PC1XX_VIC1REG(x) ((x) + S5PC1XX_VA_VIC(1)) | ||
| 22 | #define S5PC1XX_VIC2REG(x) ((x) + S5PC1XX_VA_VIC(2)) | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_REGS_IRQ_H */ | 19 | #endif /* __ASM_ARCH_REGS_IRQ_H */ |
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h new file mode 100644 index 000000000000..65e426370bb2 --- /dev/null +++ b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h | |||
| @@ -0,0 +1,18 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S5PC100_PLAT_SPI_CLKS_H | ||
| 12 | #define __S5PC100_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S5PC100_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S5PC100_SPI_SRCCLK_48M 1 | ||
| 16 | #define S5PC100_SPI_SRCCLK_SPIBUS 2 | ||
| 17 | |||
| 18 | #endif /* __S5PC100_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h index f0d31a2a598c..681f626a9ae1 100644 --- a/arch/arm/mach-s5pc100/include/mach/system.h +++ b/arch/arm/mach-s5pc100/include/mach/system.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * | 5 | * |
| 6 | * S5PC1XX - system implementation | 6 | * S5PC100 - system implementation |
| 7 | * | 7 | * |
| 8 | * Based on mach-s3c6400/include/mach/system.h | 8 | * Based on mach-s3c6400/include/mach/system.h |
| 9 | */ | 9 | */ |
| @@ -13,14 +13,11 @@ | |||
| 13 | 13 | ||
| 14 | #include <linux/io.h> | 14 | #include <linux/io.h> |
| 15 | #include <mach/map.h> | 15 | #include <mach/map.h> |
| 16 | #include <plat/regs-clock.h> | 16 | #include <mach/regs-clock.h> |
| 17 | |||
| 18 | void (*s5pc1xx_idle)(void); | ||
| 19 | 17 | ||
| 20 | static void arch_idle(void) | 18 | static void arch_idle(void) |
| 21 | { | 19 | { |
| 22 | if (s5pc1xx_idle) | 20 | /* nothing here yet */ |
| 23 | s5pc1xx_idle(); | ||
| 24 | } | 21 | } |
| 25 | 22 | ||
| 26 | static void arch_reset(char mode, const char *cmd) | 23 | static void arch_reset(char mode, const char *cmd) |
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h index f338c9eec717..20f68730ed18 100644 --- a/arch/arm/mach-s5pc100/include/mach/tick.h +++ b/arch/arm/mach-s5pc100/include/mach/tick.h | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | */ | 20 | */ |
| 21 | static inline u32 s3c24xx_ostimer_pending(void) | 21 | static inline u32 s3c24xx_ostimer_pending(void) |
| 22 | { | 22 | { |
| 23 | u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS); | 23 | u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS); |
| 24 | return pend & 1 << (IRQ_TIMER4_VIC - S5PC1XX_IRQ_VIC0(0)); | 24 | return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0))); |
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | #define TICK_MAX (0xffffffff) | 27 | #define TICK_MAX (0xffffffff) |
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/mach-s5pc100/init.c index c58710884ceb..19d7b523c137 100644 --- a/arch/arm/plat-s5pc1xx/s5pc100-init.c +++ b/arch/arm/mach-s5pc100/init.c | |||
| @@ -1,9 +1,8 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c | 1 | /* linux/arch/arm/plat-s5pc100/s5pc100-init.c |
| 2 | * | 2 | * |
| 3 | * Copyright 2009 Samsung Electronics Co. | 3 | * Copyright 2009 Samsung Electronics Co. |
| 4 | * Byungho Min <bhmin@samsung.com> | 4 | * Byungho Min <bhmin@samsung.com> |
| 5 | * | 5 | * |
| 6 | * S5PC100 - CPU initialisation (common with other S5PC1XX chips) | ||
| 7 | * | 6 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
| @@ -19,9 +18,7 @@ | |||
| 19 | #include <plat/s5pc100.h> | 18 | #include <plat/s5pc100.h> |
| 20 | 19 | ||
| 21 | /* uart registration process */ | 20 | /* uart registration process */ |
| 22 | |||
| 23 | void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) | 21 | void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
| 24 | { | 22 | { |
| 25 | /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv */ | 23 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); |
| 26 | s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no); | ||
| 27 | } | 24 | } |
diff --git a/arch/arm/plat-s5pc1xx/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c index fecca7a679b0..2bf86c18bc73 100644 --- a/arch/arm/plat-s5pc1xx/irq-gpio.c +++ b/arch/arm/mach-s5pc100/irq-gpio.c | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-s5pc1xx/irq-gpio.c | 2 | * arch/arm/mach-s5pc100/irq-gpio.c |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2009 Samsung Electronics | 4 | * Copyright (C) 2009 Samsung Electronics |
| 5 | * | 5 | * |
| 6 | * S5PC1XX - Interrupt handling for IRQ_GPIO${group}(x) | 6 | * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x) |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify | 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as | 9 | * it under the terms of the GNU General Public License version 2 as |
| @@ -19,7 +19,7 @@ | |||
| 19 | #include <mach/map.h> | 19 | #include <mach/map.h> |
| 20 | #include <plat/gpio-cfg.h> | 20 | #include <plat/gpio-cfg.h> |
| 21 | 21 | ||
| 22 | #define S5PC1XX_GPIOREG(x) (S5PC1XX_VA_GPIO + (x)) | 22 | #define S5P_GPIOREG(x) (S5P_VA_GPIO + (x)) |
| 23 | 23 | ||
| 24 | #define CON_OFFSET 0x700 | 24 | #define CON_OFFSET 0x700 |
| 25 | #define MASK_OFFSET 0x900 | 25 | #define MASK_OFFSET 0x900 |
| @@ -49,7 +49,7 @@ static int group_to_pend_offset(int group) | |||
| 49 | return group << 2; | 49 | return group << 2; |
| 50 | } | 50 | } |
| 51 | 51 | ||
| 52 | static int s5pc1xx_get_start(unsigned int group) | 52 | static int s5pc100_get_start(unsigned int group) |
| 53 | { | 53 | { |
| 54 | switch (group) { | 54 | switch (group) { |
| 55 | case 0: return S5PC100_GPIO_A0_START; | 55 | case 0: return S5PC100_GPIO_A0_START; |
| @@ -80,7 +80,7 @@ static int s5pc1xx_get_start(unsigned int group) | |||
| 80 | return -EINVAL; | 80 | return -EINVAL; |
| 81 | } | 81 | } |
| 82 | 82 | ||
| 83 | static int s5pc1xx_get_group(unsigned int irq) | 83 | static int s5pc100_get_group(unsigned int irq) |
| 84 | { | 84 | { |
| 85 | irq -= S3C_IRQ_GPIO(0); | 85 | irq -= S3C_IRQ_GPIO(0); |
| 86 | 86 | ||
| @@ -134,67 +134,67 @@ static int s5pc1xx_get_group(unsigned int irq) | |||
| 134 | return -EINVAL; | 134 | return -EINVAL; |
| 135 | } | 135 | } |
| 136 | 136 | ||
| 137 | static int s5pc1xx_get_offset(unsigned int irq) | 137 | static int s5pc100_get_offset(unsigned int irq) |
| 138 | { | 138 | { |
| 139 | struct gpio_chip *chip = get_irq_data(irq); | 139 | struct gpio_chip *chip = get_irq_data(irq); |
| 140 | return irq - S3C_IRQ_GPIO(chip->base); | 140 | return irq - S3C_IRQ_GPIO(chip->base); |
| 141 | } | 141 | } |
| 142 | 142 | ||
| 143 | static void s5pc1xx_gpioint_ack(unsigned int irq) | 143 | static void s5pc100_gpioint_ack(unsigned int irq) |
| 144 | { | 144 | { |
| 145 | int group, offset, pend_offset; | 145 | int group, offset, pend_offset; |
| 146 | unsigned int value; | 146 | unsigned int value; |
| 147 | 147 | ||
| 148 | group = s5pc1xx_get_group(irq); | 148 | group = s5pc100_get_group(irq); |
| 149 | offset = s5pc1xx_get_offset(irq); | 149 | offset = s5pc100_get_offset(irq); |
| 150 | pend_offset = group_to_pend_offset(group); | 150 | pend_offset = group_to_pend_offset(group); |
| 151 | 151 | ||
| 152 | value = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | 152 | value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); |
| 153 | value |= 1 << offset; | 153 | value |= 1 << offset; |
| 154 | __raw_writel(value, S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | 154 | __raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset); |
| 155 | } | 155 | } |
| 156 | 156 | ||
| 157 | static void s5pc1xx_gpioint_mask(unsigned int irq) | 157 | static void s5pc100_gpioint_mask(unsigned int irq) |
| 158 | { | 158 | { |
| 159 | int group, offset, mask_offset; | 159 | int group, offset, mask_offset; |
| 160 | unsigned int value; | 160 | unsigned int value; |
| 161 | 161 | ||
| 162 | group = s5pc1xx_get_group(irq); | 162 | group = s5pc100_get_group(irq); |
| 163 | offset = s5pc1xx_get_offset(irq); | 163 | offset = s5pc100_get_offset(irq); |
| 164 | mask_offset = group_to_mask_offset(group); | 164 | mask_offset = group_to_mask_offset(group); |
| 165 | 165 | ||
| 166 | value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 166 | value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
| 167 | value |= 1 << offset; | 167 | value |= 1 << offset; |
| 168 | __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 168 | __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
| 169 | } | 169 | } |
| 170 | 170 | ||
| 171 | static void s5pc1xx_gpioint_unmask(unsigned int irq) | 171 | static void s5pc100_gpioint_unmask(unsigned int irq) |
| 172 | { | 172 | { |
| 173 | int group, offset, mask_offset; | 173 | int group, offset, mask_offset; |
| 174 | unsigned int value; | 174 | unsigned int value; |
| 175 | 175 | ||
| 176 | group = s5pc1xx_get_group(irq); | 176 | group = s5pc100_get_group(irq); |
| 177 | offset = s5pc1xx_get_offset(irq); | 177 | offset = s5pc100_get_offset(irq); |
| 178 | mask_offset = group_to_mask_offset(group); | 178 | mask_offset = group_to_mask_offset(group); |
| 179 | 179 | ||
| 180 | value = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 180 | value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
| 181 | value &= ~(1 << offset); | 181 | value &= ~(1 << offset); |
| 182 | __raw_writel(value, S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 182 | __raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
| 183 | } | 183 | } |
| 184 | 184 | ||
| 185 | static void s5pc1xx_gpioint_mask_ack(unsigned int irq) | 185 | static void s5pc100_gpioint_mask_ack(unsigned int irq) |
| 186 | { | 186 | { |
| 187 | s5pc1xx_gpioint_mask(irq); | 187 | s5pc100_gpioint_mask(irq); |
| 188 | s5pc1xx_gpioint_ack(irq); | 188 | s5pc100_gpioint_ack(irq); |
| 189 | } | 189 | } |
| 190 | 190 | ||
| 191 | static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) | 191 | static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type) |
| 192 | { | 192 | { |
| 193 | int group, offset, con_offset; | 193 | int group, offset, con_offset; |
| 194 | unsigned int value; | 194 | unsigned int value; |
| 195 | 195 | ||
| 196 | group = s5pc1xx_get_group(irq); | 196 | group = s5pc100_get_group(irq); |
| 197 | offset = s5pc1xx_get_offset(irq); | 197 | offset = s5pc100_get_offset(irq); |
| 198 | con_offset = group_to_con_offset(group); | 198 | con_offset = group_to_con_offset(group); |
| 199 | 199 | ||
| 200 | switch (type) { | 200 | switch (type) { |
| @@ -221,24 +221,24 @@ static int s5pc1xx_gpioint_set_type(unsigned int irq, unsigned int type) | |||
| 221 | } | 221 | } |
| 222 | 222 | ||
| 223 | 223 | ||
| 224 | value = __raw_readl(S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); | 224 | value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset); |
| 225 | value &= ~(0xf << (offset * 0x4)); | 225 | value &= ~(0xf << (offset * 0x4)); |
| 226 | value |= (type << (offset * 0x4)); | 226 | value |= (type << (offset * 0x4)); |
| 227 | __raw_writel(value, S5PC1XX_GPIOREG(CON_OFFSET) + con_offset); | 227 | __raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset); |
| 228 | 228 | ||
| 229 | return 0; | 229 | return 0; |
| 230 | } | 230 | } |
| 231 | 231 | ||
| 232 | struct irq_chip s5pc1xx_gpioint = { | 232 | struct irq_chip s5pc100_gpioint = { |
| 233 | .name = "GPIO", | 233 | .name = "GPIO", |
| 234 | .ack = s5pc1xx_gpioint_ack, | 234 | .ack = s5pc100_gpioint_ack, |
| 235 | .mask = s5pc1xx_gpioint_mask, | 235 | .mask = s5pc100_gpioint_mask, |
| 236 | .mask_ack = s5pc1xx_gpioint_mask_ack, | 236 | .mask_ack = s5pc100_gpioint_mask_ack, |
| 237 | .unmask = s5pc1xx_gpioint_unmask, | 237 | .unmask = s5pc100_gpioint_unmask, |
| 238 | .set_type = s5pc1xx_gpioint_set_type, | 238 | .set_type = s5pc100_gpioint_set_type, |
| 239 | }; | 239 | }; |
| 240 | 240 | ||
| 241 | void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) | 241 | void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) |
| 242 | { | 242 | { |
| 243 | int group, offset, pend_offset, mask_offset; | 243 | int group, offset, pend_offset, mask_offset; |
| 244 | int real_irq, group_end; | 244 | int real_irq, group_end; |
| @@ -248,17 +248,17 @@ void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc) | |||
| 248 | 248 | ||
| 249 | for (group = 0; group < group_end; group++) { | 249 | for (group = 0; group < group_end; group++) { |
| 250 | pend_offset = group_to_pend_offset(group); | 250 | pend_offset = group_to_pend_offset(group); |
| 251 | pend = __raw_readl(S5PC1XX_GPIOREG(PEND_OFFSET) + pend_offset); | 251 | pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset); |
| 252 | if (!pend) | 252 | if (!pend) |
| 253 | continue; | 253 | continue; |
| 254 | 254 | ||
| 255 | mask_offset = group_to_mask_offset(group); | 255 | mask_offset = group_to_mask_offset(group); |
| 256 | mask = __raw_readl(S5PC1XX_GPIOREG(MASK_OFFSET) + mask_offset); | 256 | mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset); |
| 257 | pend &= ~mask; | 257 | pend &= ~mask; |
| 258 | 258 | ||
| 259 | for (offset = 0; offset < 8; offset++) { | 259 | for (offset = 0; offset < 8; offset++) { |
| 260 | if (pend & (1 << offset)) { | 260 | if (pend & (1 << offset)) { |
| 261 | real_irq = s5pc1xx_get_start(group) + offset; | 261 | real_irq = s5pc100_get_start(group) + offset; |
| 262 | generic_handle_irq(S3C_IRQ_GPIO(real_irq)); | 262 | generic_handle_irq(S3C_IRQ_GPIO(real_irq)); |
| 263 | } | 263 | } |
| 264 | } | 264 | } |
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c index bfe67db34f04..af22f8202a07 100644 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ b/arch/arm/mach-s5pc100/mach-smdkc100.c | |||
| @@ -43,38 +43,48 @@ | |||
| 43 | #include <plat/fb.h> | 43 | #include <plat/fb.h> |
| 44 | #include <plat/iic.h> | 44 | #include <plat/iic.h> |
| 45 | 45 | ||
| 46 | #define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK) | 46 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
| 47 | #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB) | 47 | #define S5PC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 48 | #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) | 48 | S3C2410_UCON_RXILEVEL | \ |
| 49 | S3C2410_UCON_TXIRQMODE | \ | ||
| 50 | S3C2410_UCON_RXIRQMODE | \ | ||
| 51 | S3C2410_UCON_RXFIFO_TOI | \ | ||
| 52 | S3C2443_UCON_RXERR_IRQEN) | ||
| 53 | |||
| 54 | #define S5PC100_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
| 55 | |||
| 56 | #define S5PC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
| 57 | S3C2440_UFCON_RXTRIG8 | \ | ||
| 58 | S3C2440_UFCON_TXTRIG16) | ||
| 49 | 59 | ||
| 50 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | 60 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { |
| 51 | [0] = { | 61 | [0] = { |
| 52 | .hwport = 0, | 62 | .hwport = 0, |
| 53 | .flags = 0, | 63 | .flags = 0, |
| 54 | .ucon = 0x3c5, | 64 | .ucon = S5PC100_UCON_DEFAULT, |
| 55 | .ulcon = 0x03, | 65 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 56 | .ufcon = 0x51, | 66 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 57 | }, | 67 | }, |
| 58 | [1] = { | 68 | [1] = { |
| 59 | .hwport = 1, | 69 | .hwport = 1, |
| 60 | .flags = 0, | 70 | .flags = 0, |
| 61 | .ucon = 0x3c5, | 71 | .ucon = S5PC100_UCON_DEFAULT, |
| 62 | .ulcon = 0x03, | 72 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 63 | .ufcon = 0x51, | 73 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 64 | }, | 74 | }, |
| 65 | [2] = { | 75 | [2] = { |
| 66 | .hwport = 2, | 76 | .hwport = 2, |
| 67 | .flags = 0, | 77 | .flags = 0, |
| 68 | .ucon = 0x3c5, | 78 | .ucon = S5PC100_UCON_DEFAULT, |
| 69 | .ulcon = 0x03, | 79 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 70 | .ufcon = 0x51, | 80 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 71 | }, | 81 | }, |
| 72 | [3] = { | 82 | [3] = { |
| 73 | .hwport = 3, | 83 | .hwport = 3, |
| 74 | .flags = 0, | 84 | .flags = 0, |
| 75 | .ucon = 0x3c5, | 85 | .ucon = S5PC100_UCON_DEFAULT, |
| 76 | .ulcon = 0x03, | 86 | .ulcon = S5PC100_ULCON_DEFAULT, |
| 77 | .ufcon = 0x51, | 87 | .ufcon = S5PC100_UFCON_DEFAULT, |
| 78 | }, | 88 | }, |
| 79 | }; | 89 | }; |
| 80 | 90 | ||
| @@ -118,8 +128,7 @@ static struct platform_device smdkc100_lcd_powerdev = { | |||
| 118 | static struct s3c_fb_pd_win smdkc100_fb_win0 = { | 128 | static struct s3c_fb_pd_win smdkc100_fb_win0 = { |
| 119 | /* this is to ensure we use win0 */ | 129 | /* this is to ensure we use win0 */ |
| 120 | .win_mode = { | 130 | .win_mode = { |
| 121 | .refresh = 70, | 131 | .pixclock = 1000000000000ULL / ((8+13+3+800)*(7+5+1+480)*80), |
| 122 | .pixclock = (8+13+3+800)*(7+5+1+480), | ||
| 123 | .left_margin = 8, | 132 | .left_margin = 8, |
| 124 | .right_margin = 13, | 133 | .right_margin = 13, |
| 125 | .upper_margin = 7, | 134 | .upper_margin = 7, |
| @@ -140,8 +149,6 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { | |||
| 140 | .setup_gpio = s5pc100_fb_gpio_setup_24bpp, | 149 | .setup_gpio = s5pc100_fb_gpio_setup_24bpp, |
| 141 | }; | 150 | }; |
| 142 | 151 | ||
| 143 | static struct map_desc smdkc100_iodesc[] = {}; | ||
| 144 | |||
| 145 | static struct platform_device *smdkc100_devices[] __initdata = { | 152 | static struct platform_device *smdkc100_devices[] __initdata = { |
| 146 | &s3c_device_i2c0, | 153 | &s3c_device_i2c0, |
| 147 | &s3c_device_i2c1, | 154 | &s3c_device_i2c1, |
| @@ -150,11 +157,13 @@ static struct platform_device *smdkc100_devices[] __initdata = { | |||
| 150 | &s3c_device_hsmmc1, | 157 | &s3c_device_hsmmc1, |
| 151 | &s3c_device_hsmmc2, | 158 | &s3c_device_hsmmc2, |
| 152 | &smdkc100_lcd_powerdev, | 159 | &smdkc100_lcd_powerdev, |
| 160 | &s5pc100_device_iis0, | ||
| 161 | &s5pc100_device_ac97, | ||
| 153 | }; | 162 | }; |
| 154 | 163 | ||
| 155 | static void __init smdkc100_map_io(void) | 164 | static void __init smdkc100_map_io(void) |
| 156 | { | 165 | { |
| 157 | s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc)); | 166 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
| 158 | s3c24xx_init_clocks(12000000); | 167 | s3c24xx_init_clocks(12000000); |
| 159 | s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); | 168 | s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); |
| 160 | } | 169 | } |
| @@ -178,10 +187,9 @@ static void __init smdkc100_machine_init(void) | |||
| 178 | 187 | ||
| 179 | MACHINE_START(SMDKC100, "SMDKC100") | 188 | MACHINE_START(SMDKC100, "SMDKC100") |
| 180 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ | 189 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ |
| 181 | .phys_io = S5PC100_PA_UART & 0xfff00000, | 190 | .phys_io = S3C_PA_UART & 0xfff00000, |
| 182 | .io_pg_offst = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc, | 191 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, |
| 183 | .boot_params = S5PC100_PA_SDRAM + 0x100, | 192 | .boot_params = S5P_PA_SDRAM + 0x100, |
| 184 | |||
| 185 | .init_irq = s5pc100_init_irq, | 193 | .init_irq = s5pc100_init_irq, |
| 186 | .map_io = smdkc100_map_io, | 194 | .map_io = smdkc100_map_io, |
| 187 | .init_machine = smdkc100_machine_init, | 195 | .init_machine = smdkc100_machine_init, |
diff --git a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c index 185c8941e644..7769c760c9ef 100644 --- a/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c | |||
| @@ -1,8 +1,8 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c | 1 | /* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c |
| 2 | * | 2 | * |
| 3 | * Copyright 2009 Samsung Eletronics | 3 | * Copyright 2009 Samsung Eletronics |
| 4 | * | 4 | * |
| 5 | * S5PC1XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) | 5 | * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig index 7601c28e240b..0761eac9aaea 100644 --- a/arch/arm/mach-s5pv210/Kconfig +++ b/arch/arm/mach-s5pv210/Kconfig | |||
| @@ -13,18 +13,68 @@ config CPU_S5PV210 | |||
| 13 | bool | 13 | bool |
| 14 | select PLAT_S5P | 14 | select PLAT_S5P |
| 15 | select S3C_PL330_DMA | 15 | select S3C_PL330_DMA |
| 16 | select S5P_EXT_INT | ||
| 16 | help | 17 | help |
| 17 | Enable S5PV210 CPU support | 18 | Enable S5PV210 CPU support |
| 18 | 19 | ||
| 19 | choice | 20 | config S5PV210_SETUP_I2C1 |
| 20 | prompt "Select machine type" | 21 | bool |
| 21 | depends on ARCH_S5PV210 | 22 | help |
| 22 | default MACH_SMDKV210 | 23 | Common setup code for i2c bus 1. |
| 24 | |||
| 25 | config S5PV210_SETUP_I2C2 | ||
| 26 | bool | ||
| 27 | help | ||
| 28 | Common setup code for i2c bus 2. | ||
| 29 | |||
| 30 | config S5PV210_SETUP_FB_24BPP | ||
| 31 | bool | ||
| 32 | help | ||
| 33 | Common setup code for S5PV210 with an 24bpp RGB display helper. | ||
| 34 | |||
| 35 | config S5PV210_SETUP_SDHCI | ||
| 36 | bool | ||
| 37 | select S5PV210_SETUP_SDHCI_GPIO | ||
| 38 | help | ||
| 39 | Internal helper functions for S5PV210 based SDHCI systems | ||
| 40 | |||
| 41 | config S5PV210_SETUP_SDHCI_GPIO | ||
| 42 | bool | ||
| 43 | help | ||
| 44 | Common setup code for SDHCI gpio. | ||
| 45 | |||
| 46 | # machine support | ||
| 47 | |||
| 48 | config MACH_AQUILA | ||
| 49 | bool "Samsung Aquila" | ||
| 50 | select CPU_S5PV210 | ||
| 51 | select ARCH_SPARSEMEM_ENABLE | ||
| 52 | select S5PV210_SETUP_FB_24BPP | ||
| 53 | select S3C_DEV_FB | ||
| 54 | help | ||
| 55 | Machine support for the Samsung Aquila target based on S5PC110 SoC | ||
| 56 | |||
| 57 | config MACH_GONI | ||
| 58 | bool "GONI" | ||
| 59 | select CPU_S5PV210 | ||
| 60 | select ARCH_SPARSEMEM_ENABLE | ||
| 61 | help | ||
| 62 | Machine support for Samsung GONI board | ||
| 63 | S5PC110(MCP) is one of package option of S5PV210 | ||
| 64 | |||
| 65 | config S5PC110_DEV_ONENAND | ||
| 66 | bool | ||
| 67 | help | ||
| 68 | Compile in platform device definition for OneNAND1 controller | ||
| 23 | 69 | ||
| 24 | config MACH_SMDKV210 | 70 | config MACH_SMDKV210 |
| 25 | bool "SMDKV210" | 71 | bool "SMDKV210" |
| 26 | select CPU_S5PV210 | 72 | select CPU_S5PV210 |
| 27 | select ARCH_SPARSEMEM_ENABLE | 73 | select ARCH_SPARSEMEM_ENABLE |
| 74 | select SAMSUNG_DEV_ADC | ||
| 75 | select SAMSUNG_DEV_TS | ||
| 76 | select S3C_DEV_WDT | ||
| 77 | select HAVE_S3C2410_WATCHDOG | ||
| 28 | help | 78 | help |
| 29 | Machine support for Samsung SMDKV210 | 79 | Machine support for Samsung SMDKV210 |
| 30 | 80 | ||
| @@ -32,10 +82,10 @@ config MACH_SMDKC110 | |||
| 32 | bool "SMDKC110" | 82 | bool "SMDKC110" |
| 33 | select CPU_S5PV210 | 83 | select CPU_S5PV210 |
| 34 | select ARCH_SPARSEMEM_ENABLE | 84 | select ARCH_SPARSEMEM_ENABLE |
| 85 | select S3C_DEV_WDT | ||
| 86 | select HAVE_S3C2410_WATCHDOG | ||
| 35 | help | 87 | help |
| 36 | Machine support for Samsung SMDKC110 | 88 | Machine support for Samsung SMDKC110 |
| 37 | S5PC110(MCP) is one of package option of S5PV210 | 89 | S5PC110(MCP) is one of package option of S5PV210 |
| 38 | 90 | ||
| 39 | endchoice | ||
| 40 | |||
| 41 | endif | 91 | endif |
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile index 99827813d293..30be9a6a4620 100644 --- a/arch/arm/mach-s5pv210/Makefile +++ b/arch/arm/mach-s5pv210/Makefile | |||
| @@ -17,9 +17,19 @@ obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o | |||
| 17 | 17 | ||
| 18 | # machine support | 18 | # machine support |
| 19 | 19 | ||
| 20 | obj-$(CONFIG_MACH_AQUILA) += mach-aquila.o | ||
| 20 | obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o | 21 | obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o |
| 21 | obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o | 22 | obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o |
| 23 | obj-$(CONFIG_MACH_GONI) += mach-goni.o | ||
| 22 | 24 | ||
| 23 | # device support | 25 | # device support |
| 24 | 26 | ||
| 25 | obj-y += dev-audio.o | 27 | obj-y += dev-audio.o |
| 28 | obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o | ||
| 29 | obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o | ||
| 30 | |||
| 31 | obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o | ||
| 32 | obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o | ||
| 33 | obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o | ||
| 34 | obj-$(CONFIG_S5PV210_SETUP_SDHCI) += setup-sdhci.o | ||
| 35 | obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | ||
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c index 2b776eb5d150..411a4a9cbfc7 100644 --- a/arch/arm/mach-s5pv210/cpu.c +++ b/arch/arm/mach-s5pv210/cpu.c | |||
| @@ -32,6 +32,8 @@ | |||
| 32 | #include <plat/devs.h> | 32 | #include <plat/devs.h> |
| 33 | #include <plat/clock.h> | 33 | #include <plat/clock.h> |
| 34 | #include <plat/s5pv210.h> | 34 | #include <plat/s5pv210.h> |
| 35 | #include <plat/iic-core.h> | ||
| 36 | #include <plat/sdhci.h> | ||
| 35 | 37 | ||
| 36 | /* Initial IO mappings */ | 38 | /* Initial IO mappings */ |
| 37 | 39 | ||
| @@ -74,7 +76,21 @@ static void s5pv210_idle(void) | |||
| 74 | 76 | ||
| 75 | void __init s5pv210_map_io(void) | 77 | void __init s5pv210_map_io(void) |
| 76 | { | 78 | { |
| 79 | #ifdef CONFIG_S3C_DEV_ADC | ||
| 80 | s3c_device_adc.name = "s3c64xx-adc"; | ||
| 81 | #endif | ||
| 82 | |||
| 77 | iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); | 83 | iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); |
| 84 | |||
| 85 | /* initialise device information early */ | ||
| 86 | s5pv210_default_sdhci0(); | ||
| 87 | s5pv210_default_sdhci1(); | ||
| 88 | s5pv210_default_sdhci2(); | ||
| 89 | |||
| 90 | /* the i2c devices are directly compatible with s3c2440 */ | ||
| 91 | s3c_i2c0_setname("s3c2440-i2c"); | ||
| 92 | s3c_i2c1_setname("s3c2440-i2c"); | ||
| 93 | s3c_i2c2_setname("s3c2440-i2c"); | ||
| 78 | } | 94 | } |
| 79 | 95 | ||
| 80 | void __init s5pv210_init_clocks(int xtal) | 96 | void __init s5pv210_init_clocks(int xtal) |
diff --git a/arch/arm/mach-s5pv210/dev-onenand.c b/arch/arm/mach-s5pv210/dev-onenand.c new file mode 100644 index 000000000000..34997b752f93 --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-onenand.c | |||
| @@ -0,0 +1,50 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-s5pv210/dev-onenand.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008-2010 Samsung Electronics | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * | ||
| 7 | * S5PC110 series device definition for OneNAND devices | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/mtd/mtd.h> | ||
| 17 | #include <linux/mtd/onenand.h> | ||
| 18 | |||
| 19 | #include <mach/irqs.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | static struct resource s5pc110_onenand_resources[] = { | ||
| 23 | [0] = { | ||
| 24 | .start = S5PC110_PA_ONENAND, | ||
| 25 | .end = S5PC110_PA_ONENAND + SZ_128K - 1, | ||
| 26 | .flags = IORESOURCE_MEM, | ||
| 27 | }, | ||
| 28 | [1] = { | ||
| 29 | .start = S5PC110_PA_ONENAND_DMA, | ||
| 30 | .end = S5PC110_PA_ONENAND_DMA + SZ_2K - 1, | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }, | ||
| 33 | }; | ||
| 34 | |||
| 35 | struct platform_device s5pc110_device_onenand = { | ||
| 36 | .name = "s5pc110-onenand", | ||
| 37 | .id = -1, | ||
| 38 | .num_resources = ARRAY_SIZE(s5pc110_onenand_resources), | ||
| 39 | .resource = s5pc110_onenand_resources, | ||
| 40 | }; | ||
| 41 | |||
| 42 | void s5pc110_onenand_set_platdata(struct onenand_platform_data *pdata) | ||
| 43 | { | ||
| 44 | struct onenand_platform_data *pd; | ||
| 45 | |||
| 46 | pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); | ||
| 47 | if (!pd) | ||
| 48 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
| 49 | s5pc110_device_onenand.dev.platform_data = pd; | ||
| 50 | } | ||
diff --git a/arch/arm/mach-s5pv210/dev-spi.c b/arch/arm/mach-s5pv210/dev-spi.c new file mode 100644 index 000000000000..337a62b57a0b --- /dev/null +++ b/arch/arm/mach-s5pv210/dev-spi.c | |||
| @@ -0,0 +1,178 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/dev-spi.c | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/platform_device.h> | ||
| 12 | #include <linux/dma-mapping.h> | ||
| 13 | |||
| 14 | #include <mach/dma.h> | ||
| 15 | #include <mach/map.h> | ||
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <mach/gpio.h> | ||
| 18 | #include <mach/spi-clocks.h> | ||
| 19 | |||
| 20 | #include <plat/s3c64xx-spi.h> | ||
| 21 | #include <plat/gpio-cfg.h> | ||
| 22 | |||
| 23 | static char *spi_src_clks[] = { | ||
| 24 | [S5PV210_SPI_SRCCLK_PCLK] = "pclk", | ||
| 25 | [S5PV210_SPI_SRCCLK_SCLK] = "sclk_spi", | ||
| 26 | }; | ||
| 27 | |||
| 28 | /* SPI Controller platform_devices */ | ||
| 29 | |||
| 30 | /* Since we emulate multi-cs capability, we do not touch the CS. | ||
| 31 | * The emulated CS is toggled by board specific mechanism, as it can | ||
| 32 | * be either some immediate GPIO or some signal out of some other | ||
| 33 | * chip in between ... or some yet another way. | ||
| 34 | * We simply do not assume anything about CS. | ||
| 35 | */ | ||
| 36 | static int s5pv210_spi_cfg_gpio(struct platform_device *pdev) | ||
| 37 | { | ||
| 38 | switch (pdev->id) { | ||
| 39 | case 0: | ||
| 40 | s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2)); | ||
| 41 | s3c_gpio_cfgpin(S5PV210_GPB(1), S3C_GPIO_SFN(2)); | ||
| 42 | s3c_gpio_cfgpin(S5PV210_GPB(2), S3C_GPIO_SFN(2)); | ||
| 43 | s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP); | ||
| 44 | s3c_gpio_setpull(S5PV210_GPB(1), S3C_GPIO_PULL_UP); | ||
| 45 | s3c_gpio_setpull(S5PV210_GPB(2), S3C_GPIO_PULL_UP); | ||
| 46 | break; | ||
| 47 | |||
| 48 | case 1: | ||
| 49 | s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2)); | ||
| 50 | s3c_gpio_cfgpin(S5PV210_GPB(5), S3C_GPIO_SFN(2)); | ||
| 51 | s3c_gpio_cfgpin(S5PV210_GPB(6), S3C_GPIO_SFN(2)); | ||
| 52 | s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP); | ||
| 53 | s3c_gpio_setpull(S5PV210_GPB(5), S3C_GPIO_PULL_UP); | ||
| 54 | s3c_gpio_setpull(S5PV210_GPB(6), S3C_GPIO_PULL_UP); | ||
| 55 | break; | ||
| 56 | |||
| 57 | default: | ||
| 58 | dev_err(&pdev->dev, "Invalid SPI Controller number!"); | ||
| 59 | return -EINVAL; | ||
| 60 | } | ||
| 61 | |||
| 62 | return 0; | ||
| 63 | } | ||
| 64 | |||
| 65 | static struct resource s5pv210_spi0_resource[] = { | ||
| 66 | [0] = { | ||
| 67 | .start = S5PV210_PA_SPI0, | ||
| 68 | .end = S5PV210_PA_SPI0 + 0x100 - 1, | ||
| 69 | .flags = IORESOURCE_MEM, | ||
| 70 | }, | ||
| 71 | [1] = { | ||
| 72 | .start = DMACH_SPI0_TX, | ||
| 73 | .end = DMACH_SPI0_TX, | ||
| 74 | .flags = IORESOURCE_DMA, | ||
| 75 | }, | ||
| 76 | [2] = { | ||
| 77 | .start = DMACH_SPI0_RX, | ||
| 78 | .end = DMACH_SPI0_RX, | ||
| 79 | .flags = IORESOURCE_DMA, | ||
| 80 | }, | ||
| 81 | [3] = { | ||
| 82 | .start = IRQ_SPI0, | ||
| 83 | .end = IRQ_SPI0, | ||
| 84 | .flags = IORESOURCE_IRQ, | ||
| 85 | }, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct s3c64xx_spi_info s5pv210_spi0_pdata = { | ||
| 89 | .cfg_gpio = s5pv210_spi_cfg_gpio, | ||
| 90 | .fifo_lvl_mask = 0x1ff, | ||
| 91 | .rx_lvl_offset = 15, | ||
| 92 | .high_speed = 1, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
| 96 | |||
| 97 | struct platform_device s5pv210_device_spi0 = { | ||
| 98 | .name = "s3c64xx-spi", | ||
| 99 | .id = 0, | ||
| 100 | .num_resources = ARRAY_SIZE(s5pv210_spi0_resource), | ||
| 101 | .resource = s5pv210_spi0_resource, | ||
| 102 | .dev = { | ||
| 103 | .dma_mask = &spi_dmamask, | ||
| 104 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 105 | .platform_data = &s5pv210_spi0_pdata, | ||
| 106 | }, | ||
| 107 | }; | ||
| 108 | |||
| 109 | static struct resource s5pv210_spi1_resource[] = { | ||
| 110 | [0] = { | ||
| 111 | .start = S5PV210_PA_SPI1, | ||
| 112 | .end = S5PV210_PA_SPI1 + 0x100 - 1, | ||
| 113 | .flags = IORESOURCE_MEM, | ||
| 114 | }, | ||
| 115 | [1] = { | ||
| 116 | .start = DMACH_SPI1_TX, | ||
| 117 | .end = DMACH_SPI1_TX, | ||
| 118 | .flags = IORESOURCE_DMA, | ||
| 119 | }, | ||
| 120 | [2] = { | ||
| 121 | .start = DMACH_SPI1_RX, | ||
| 122 | .end = DMACH_SPI1_RX, | ||
| 123 | .flags = IORESOURCE_DMA, | ||
| 124 | }, | ||
| 125 | [3] = { | ||
| 126 | .start = IRQ_SPI1, | ||
| 127 | .end = IRQ_SPI1, | ||
| 128 | .flags = IORESOURCE_IRQ, | ||
| 129 | }, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct s3c64xx_spi_info s5pv210_spi1_pdata = { | ||
| 133 | .cfg_gpio = s5pv210_spi_cfg_gpio, | ||
| 134 | .fifo_lvl_mask = 0x7f, | ||
| 135 | .rx_lvl_offset = 15, | ||
| 136 | .high_speed = 1, | ||
| 137 | }; | ||
| 138 | |||
| 139 | struct platform_device s5pv210_device_spi1 = { | ||
| 140 | .name = "s3c64xx-spi", | ||
| 141 | .id = 1, | ||
| 142 | .num_resources = ARRAY_SIZE(s5pv210_spi1_resource), | ||
| 143 | .resource = s5pv210_spi1_resource, | ||
| 144 | .dev = { | ||
| 145 | .dma_mask = &spi_dmamask, | ||
| 146 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 147 | .platform_data = &s5pv210_spi1_pdata, | ||
| 148 | }, | ||
| 149 | }; | ||
| 150 | |||
| 151 | void __init s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs) | ||
| 152 | { | ||
| 153 | struct s3c64xx_spi_info *pd; | ||
| 154 | |||
| 155 | /* Reject invalid configuration */ | ||
| 156 | if (!num_cs || src_clk_nr < 0 | ||
| 157 | || src_clk_nr > S5PV210_SPI_SRCCLK_SCLK) { | ||
| 158 | printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__); | ||
| 159 | return; | ||
| 160 | } | ||
| 161 | |||
| 162 | switch (cntrlr) { | ||
| 163 | case 0: | ||
| 164 | pd = &s5pv210_spi0_pdata; | ||
| 165 | break; | ||
| 166 | case 1: | ||
| 167 | pd = &s5pv210_spi1_pdata; | ||
| 168 | break; | ||
| 169 | default: | ||
| 170 | printk(KERN_ERR "%s: Invalid SPI controller(%d)\n", | ||
| 171 | __func__, cntrlr); | ||
| 172 | return; | ||
| 173 | } | ||
| 174 | |||
| 175 | pd->num_cs = num_cs; | ||
| 176 | pd->src_clk_nr = src_clk_nr; | ||
| 177 | pd->src_clk_name = spi_src_clks[src_clk_nr]; | ||
| 178 | } | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h index 62c5175ef291..92fc6c7fc064 100644 --- a/arch/arm/mach-s5pv210/include/mach/irqs.h +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h | |||
| @@ -17,22 +17,6 @@ | |||
| 17 | 17 | ||
| 18 | /* VIC0: System, DMA, Timer */ | 18 | /* VIC0: System, DMA, Timer */ |
| 19 | 19 | ||
| 20 | #define IRQ_EINT0 S5P_IRQ_VIC0(0) | ||
| 21 | #define IRQ_EINT1 S5P_IRQ_VIC0(1) | ||
| 22 | #define IRQ_EINT2 S5P_IRQ_VIC0(2) | ||
| 23 | #define IRQ_EINT3 S5P_IRQ_VIC0(3) | ||
| 24 | #define IRQ_EINT4 S5P_IRQ_VIC0(4) | ||
| 25 | #define IRQ_EINT5 S5P_IRQ_VIC0(5) | ||
| 26 | #define IRQ_EINT6 S5P_IRQ_VIC0(6) | ||
| 27 | #define IRQ_EINT7 S5P_IRQ_VIC0(7) | ||
| 28 | #define IRQ_EINT8 S5P_IRQ_VIC0(8) | ||
| 29 | #define IRQ_EINT9 S5P_IRQ_VIC0(9) | ||
| 30 | #define IRQ_EINT10 S5P_IRQ_VIC0(10) | ||
| 31 | #define IRQ_EINT11 S5P_IRQ_VIC0(11) | ||
| 32 | #define IRQ_EINT12 S5P_IRQ_VIC0(12) | ||
| 33 | #define IRQ_EINT13 S5P_IRQ_VIC0(13) | ||
| 34 | #define IRQ_EINT14 S5P_IRQ_VIC0(14) | ||
| 35 | #define IRQ_EINT15 S5P_IRQ_VIC0(15) | ||
| 36 | #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) | 20 | #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) |
| 37 | #define IRQ_BATF S5P_IRQ_VIC0(17) | 21 | #define IRQ_BATF S5P_IRQ_VIC0(17) |
| 38 | #define IRQ_MDMA S5P_IRQ_VIC0(18) | 22 | #define IRQ_MDMA S5P_IRQ_VIC0(18) |
| @@ -134,13 +118,25 @@ | |||
| 134 | #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) | 118 | #define IRQ_MDNIE3 S5P_IRQ_VIC3(8) |
| 135 | #define IRQ_VIC_END S5P_IRQ_VIC3(31) | 119 | #define IRQ_VIC_END S5P_IRQ_VIC3(31) |
| 136 | 120 | ||
| 137 | #define S5P_IRQ_EINT_BASE (IRQ_VIC_END + 1) | 121 | #define S5P_EINT_16_31_BASE (IRQ_VIC_END + 1) |
| 138 | 122 | ||
| 139 | #define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) | 123 | #define EINT_MODE S3C_GPIO_SFN(0xf) |
| 140 | #define IRQ_EINT(x) S5P_EINT(x) | 124 | |
| 125 | #define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_IRQ_VIC0(0)) \ | ||
| 126 | : ((x) + S5P_EINT_16_31_BASE)) | ||
| 141 | 127 | ||
| 142 | /* Set the default NR_IRQS */ | 128 | /* Set the default NR_IRQS */ |
| 143 | 129 | ||
| 144 | #define NR_IRQS (IRQ_EINT(31) + 1) | 130 | #define NR_IRQS (IRQ_EINT(31) + 1) |
| 131 | |||
| 132 | #define EINT_GPIO_0(x) S5PV210_GPH0(x) | ||
| 133 | #define EINT_GPIO_1(x) S5PV210_GPH1(x) | ||
| 134 | #define EINT_GPIO_2(x) S5PV210_GPH2(x) | ||
| 135 | #define EINT_GPIO_3(x) S5PV210_GPH3(x) | ||
| 136 | |||
| 137 | /* Compatibility */ | ||
| 138 | #define IRQ_LCD_FIFO IRQ_LCD0 | ||
| 139 | #define IRQ_LCD_VSYNC IRQ_LCD1 | ||
| 140 | #define IRQ_LCD_SYSTEM IRQ_LCD2 | ||
| 145 | 141 | ||
| 146 | #endif /* ASM_ARCH_IRQS_H */ | 142 | #endif /* ASM_ARCH_IRQS_H */ |
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h index 5adcb9f26e44..34eb168ec950 100644 --- a/arch/arm/mach-s5pv210/include/mach/map.h +++ b/arch/arm/mach-s5pv210/include/mach/map.h | |||
| @@ -16,6 +16,9 @@ | |||
| 16 | #include <plat/map-base.h> | 16 | #include <plat/map-base.h> |
| 17 | #include <plat/map-s5p.h> | 17 | #include <plat/map-s5p.h> |
| 18 | 18 | ||
| 19 | #define S5PC110_PA_ONENAND (0xB0000000) | ||
| 20 | #define S5PC110_PA_ONENAND_DMA (0xB0600000) | ||
| 21 | |||
| 19 | #define S5PV210_PA_CHIPID (0xE0000000) | 22 | #define S5PV210_PA_CHIPID (0xE0000000) |
| 20 | #define S5P_PA_CHIPID S5PV210_PA_CHIPID | 23 | #define S5P_PA_CHIPID S5PV210_PA_CHIPID |
| 21 | 24 | ||
| @@ -25,13 +28,21 @@ | |||
| 25 | #define S5PV210_PA_GPIO (0xE0200000) | 28 | #define S5PV210_PA_GPIO (0xE0200000) |
| 26 | #define S5P_PA_GPIO S5PV210_PA_GPIO | 29 | #define S5P_PA_GPIO S5PV210_PA_GPIO |
| 27 | 30 | ||
| 31 | /* SPI */ | ||
| 32 | #define S5PV210_PA_SPI0 0xE1300000 | ||
| 33 | #define S5PV210_PA_SPI1 0xE1400000 | ||
| 34 | |||
| 28 | #define S5PV210_PA_IIC0 (0xE1800000) | 35 | #define S5PV210_PA_IIC0 (0xE1800000) |
| 36 | #define S5PV210_PA_IIC1 (0xFAB00000) | ||
| 37 | #define S5PV210_PA_IIC2 (0xE1A00000) | ||
| 29 | 38 | ||
| 30 | #define S5PV210_PA_TIMER (0xE2500000) | 39 | #define S5PV210_PA_TIMER (0xE2500000) |
| 31 | #define S5P_PA_TIMER S5PV210_PA_TIMER | 40 | #define S5P_PA_TIMER S5PV210_PA_TIMER |
| 32 | 41 | ||
| 33 | #define S5PV210_PA_SYSTIMER (0xE2600000) | 42 | #define S5PV210_PA_SYSTIMER (0xE2600000) |
| 34 | 43 | ||
| 44 | #define S5PV210_PA_WATCHDOG (0xE2700000) | ||
| 45 | |||
| 35 | #define S5PV210_PA_UART (0xE2900000) | 46 | #define S5PV210_PA_UART (0xE2900000) |
| 36 | 47 | ||
| 37 | #define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) | 48 | #define S5P_PA_UART0 (S5PV210_PA_UART + 0x0) |
| @@ -47,6 +58,10 @@ | |||
| 47 | #define S5PV210_PA_PDMA0 0xE0900000 | 58 | #define S5PV210_PA_PDMA0 0xE0900000 |
| 48 | #define S5PV210_PA_PDMA1 0xE0A00000 | 59 | #define S5PV210_PA_PDMA1 0xE0A00000 |
| 49 | 60 | ||
| 61 | #define S5PV210_PA_FB (0xF8000000) | ||
| 62 | |||
| 63 | #define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000)) | ||
| 64 | |||
| 50 | #define S5PV210_PA_VIC0 (0xF2000000) | 65 | #define S5PV210_PA_VIC0 (0xF2000000) |
| 51 | #define S5P_PA_VIC0 S5PV210_PA_VIC0 | 66 | #define S5P_PA_VIC0 S5PV210_PA_VIC0 |
| 52 | 67 | ||
| @@ -75,8 +90,19 @@ | |||
| 75 | /* AC97 */ | 90 | /* AC97 */ |
| 76 | #define S5PV210_PA_AC97 0xE2200000 | 91 | #define S5PV210_PA_AC97 0xE2200000 |
| 77 | 92 | ||
| 93 | #define S5PV210_PA_ADC (0xE1700000) | ||
| 94 | |||
| 78 | /* compatibiltiy defines. */ | 95 | /* compatibiltiy defines. */ |
| 79 | #define S3C_PA_UART S5PV210_PA_UART | 96 | #define S3C_PA_UART S5PV210_PA_UART |
| 97 | #define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0) | ||
| 98 | #define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1) | ||
| 99 | #define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2) | ||
| 80 | #define S3C_PA_IIC S5PV210_PA_IIC0 | 100 | #define S3C_PA_IIC S5PV210_PA_IIC0 |
| 101 | #define S3C_PA_IIC1 S5PV210_PA_IIC1 | ||
| 102 | #define S3C_PA_IIC2 S5PV210_PA_IIC2 | ||
| 103 | #define S3C_PA_FB S5PV210_PA_FB | ||
| 104 | #define S3C_PA_WDT S5PV210_PA_WATCHDOG | ||
| 105 | |||
| 106 | #define SAMSUNG_PA_ADC S5PV210_PA_ADC | ||
| 81 | 107 | ||
| 82 | #endif /* __ASM_ARCH_MAP_H */ | 108 | #endif /* __ASM_ARCH_MAP_H */ |
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h index e56e0e4673ed..2a25ab40c863 100644 --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h | |||
| @@ -126,6 +126,7 @@ | |||
| 126 | 126 | ||
| 127 | #define S5P_RST_STAT S5P_CLKREG(0xA000) | 127 | #define S5P_RST_STAT S5P_CLKREG(0xA000) |
| 128 | #define S5P_OSC_CON S5P_CLKREG(0x8000) | 128 | #define S5P_OSC_CON S5P_CLKREG(0x8000) |
| 129 | #define S5P_MDNIE_SEL S5P_CLKREG(0x7008) | ||
| 129 | #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) | 130 | #define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) |
| 130 | #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) | 131 | #define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) |
| 131 | #define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) | 132 | #define S5P_MIPI_CONTROL S5P_CLKREG(0xE814) |
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h new file mode 100644 index 000000000000..60d992989bdc --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-fb.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2010 Ben Dooks <ben-linux@fluff.org> | ||
| 3 | * | ||
| 4 | * Dummy framebuffer to allow build for the moment. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MACH_REGS_FB_H | ||
| 12 | #define __ASM_ARCH_MACH_REGS_FB_H __FILE__ | ||
| 13 | |||
| 14 | #include <plat/regs-fb-v4.h> | ||
| 15 | |||
| 16 | static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg) | ||
| 17 | { | ||
| 18 | return 0x2400 + (window * 256 *4 ) + reg; | ||
| 19 | } | ||
| 20 | |||
| 21 | #endif /* __ASM_ARCH_MACH_REGS_FB_H */ | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h new file mode 100644 index 000000000000..6d068091c36c --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/include/mach/regs-gpio.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * S5PV210 - GPIO (including EINT) register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARCH_REGS_GPIO_H | ||
| 14 | #define __ASM_ARCH_REGS_GPIO_H __FILE__ | ||
| 15 | |||
| 16 | #include <mach/map.h> | ||
| 17 | |||
| 18 | #define S5PV210_EINT30CON (S5P_VA_GPIO + 0xE00) | ||
| 19 | #define S5P_EINT_CON(x) (S5PV210_EINT30CON + ((x) * 0x4)) | ||
| 20 | |||
| 21 | #define S5PV210_EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) | ||
| 22 | #define S5P_EINT_FLTCON(x) (S5PV210_EINT30FLTCON0 + ((x) * 0x4)) | ||
| 23 | |||
| 24 | #define S5PV210_EINT30MASK (S5P_VA_GPIO + 0xF00) | ||
| 25 | #define S5P_EINT_MASK(x) (S5PV210_EINT30MASK + ((x) * 0x4)) | ||
| 26 | |||
| 27 | #define S5PV210_EINT30PEND (S5P_VA_GPIO + 0xF40) | ||
| 28 | #define S5P_EINT_PEND(x) (S5PV210_EINT30PEND + ((x) * 0x4)) | ||
| 29 | |||
| 30 | #define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) \ | ||
| 31 | : ((irq) - S5P_EINT_16_31_BASE)) | ||
| 32 | |||
| 33 | #define EINT_REG_NR(x) (eint_offset(x) >> 3) | ||
| 34 | |||
| 35 | #define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7)) | ||
| 36 | |||
| 37 | /* values for S5P_EXTINT0 */ | ||
| 38 | #define S5P_EXTINT_LOWLEV (0x00) | ||
| 39 | #define S5P_EXTINT_HILEV (0x01) | ||
| 40 | #define S5P_EXTINT_FALLEDGE (0x02) | ||
| 41 | #define S5P_EXTINT_RISEEDGE (0x03) | ||
| 42 | #define S5P_EXTINT_BOTHEDGE (0x04) | ||
| 43 | |||
| 44 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h new file mode 100644 index 000000000000..02acded5f73d --- /dev/null +++ b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h | |||
| @@ -0,0 +1,17 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h | ||
| 2 | * | ||
| 3 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
| 4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __S5PV210_PLAT_SPI_CLKS_H | ||
| 12 | #define __S5PV210_PLAT_SPI_CLKS_H __FILE__ | ||
| 13 | |||
| 14 | #define S5PV210_SPI_SRCCLK_PCLK 0 | ||
| 15 | #define S5PV210_SPI_SRCCLK_SCLK 1 | ||
| 16 | |||
| 17 | #endif /* __S5PV210_PLAT_SPI_CLKS_H */ | ||
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c new file mode 100644 index 000000000000..10bc76ec4025 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-aquila.c | |||
| @@ -0,0 +1,149 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/mach-aquila.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/serial_core.h> | ||
| 15 | #include <linux/fb.h> | ||
| 16 | |||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <asm/mach/map.h> | ||
| 19 | #include <asm/setup.h> | ||
| 20 | #include <asm/mach-types.h> | ||
| 21 | |||
| 22 | #include <mach/map.h> | ||
| 23 | #include <mach/regs-clock.h> | ||
| 24 | #include <mach/regs-fb.h> | ||
| 25 | |||
| 26 | #include <plat/regs-serial.h> | ||
| 27 | #include <plat/s5pv210.h> | ||
| 28 | #include <plat/devs.h> | ||
| 29 | #include <plat/cpu.h> | ||
| 30 | #include <plat/fb.h> | ||
| 31 | |||
| 32 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | ||
| 33 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
| 34 | S3C2410_UCON_RXILEVEL | \ | ||
| 35 | S3C2410_UCON_TXIRQMODE | \ | ||
| 36 | S3C2410_UCON_RXIRQMODE | \ | ||
| 37 | S3C2410_UCON_RXFIFO_TOI | \ | ||
| 38 | S3C2443_UCON_RXERR_IRQEN) | ||
| 39 | |||
| 40 | #define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
| 41 | |||
| 42 | #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
| 43 | S5PV210_UFCON_TXTRIG4 | \ | ||
| 44 | S5PV210_UFCON_RXTRIG4) | ||
| 45 | |||
| 46 | static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { | ||
| 47 | [0] = { | ||
| 48 | .hwport = 0, | ||
| 49 | .flags = 0, | ||
| 50 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 51 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 52 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 53 | }, | ||
| 54 | [1] = { | ||
| 55 | .hwport = 1, | ||
| 56 | .flags = 0, | ||
| 57 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 58 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 59 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 60 | }, | ||
| 61 | [2] = { | ||
| 62 | .hwport = 2, | ||
| 63 | .flags = 0, | ||
| 64 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 65 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 66 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 67 | }, | ||
| 68 | [3] = { | ||
| 69 | .hwport = 3, | ||
| 70 | .flags = 0, | ||
| 71 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 72 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 73 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 74 | }, | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* Frame Buffer */ | ||
| 78 | static struct s3c_fb_pd_win aquila_fb_win0 = { | ||
| 79 | .win_mode = { | ||
| 80 | .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), | ||
| 81 | .left_margin = 16, | ||
| 82 | .right_margin = 16, | ||
| 83 | .upper_margin = 3, | ||
| 84 | .lower_margin = 28, | ||
| 85 | .hsync_len = 2, | ||
| 86 | .vsync_len = 2, | ||
| 87 | .xres = 480, | ||
| 88 | .yres = 800, | ||
| 89 | }, | ||
| 90 | .max_bpp = 32, | ||
| 91 | .default_bpp = 16, | ||
| 92 | }; | ||
| 93 | |||
| 94 | static struct s3c_fb_pd_win aquila_fb_win1 = { | ||
| 95 | .win_mode = { | ||
| 96 | .pixclock = 1000000000000ULL / ((16+16+2+480)*(28+3+2+800)*60), | ||
| 97 | .left_margin = 16, | ||
| 98 | .right_margin = 16, | ||
| 99 | .upper_margin = 3, | ||
| 100 | .lower_margin = 28, | ||
| 101 | .hsync_len = 2, | ||
| 102 | .vsync_len = 2, | ||
| 103 | .xres = 480, | ||
| 104 | .yres = 800, | ||
| 105 | }, | ||
| 106 | .max_bpp = 32, | ||
| 107 | .default_bpp = 16, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static struct s3c_fb_platdata aquila_lcd_pdata __initdata = { | ||
| 111 | .win[0] = &aquila_fb_win0, | ||
| 112 | .win[1] = &aquila_fb_win1, | ||
| 113 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
| 114 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC | | ||
| 115 | VIDCON1_INV_VCLK | VIDCON1_INV_VDEN, | ||
| 116 | .setup_gpio = s5pv210_fb_gpio_setup_24bpp, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static struct platform_device *aquila_devices[] __initdata = { | ||
| 120 | &s3c_device_fb, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static void __init aquila_map_io(void) | ||
| 124 | { | ||
| 125 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | ||
| 126 | s3c24xx_init_clocks(24000000); | ||
| 127 | s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs)); | ||
| 128 | } | ||
| 129 | |||
| 130 | static void __init aquila_machine_init(void) | ||
| 131 | { | ||
| 132 | /* FB */ | ||
| 133 | s3c_fb_set_platdata(&aquila_lcd_pdata); | ||
| 134 | |||
| 135 | platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices)); | ||
| 136 | } | ||
| 137 | |||
| 138 | MACHINE_START(AQUILA, "Aquila") | ||
| 139 | /* Maintainers: | ||
| 140 | Marek Szyprowski <m.szyprowski@samsung.com> | ||
| 141 | Kyungmin Park <kyungmin.park@samsung.com> */ | ||
| 142 | .phys_io = S3C_PA_UART & 0xfff00000, | ||
| 143 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | ||
| 144 | .boot_params = S5P_PA_SDRAM + 0x100, | ||
| 145 | .init_irq = s5pv210_init_irq, | ||
| 146 | .map_io = aquila_map_io, | ||
| 147 | .init_machine = aquila_machine_init, | ||
| 148 | .timer = &s3c24xx_timer, | ||
| 149 | MACHINE_END | ||
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c new file mode 100644 index 000000000000..4863b13824e4 --- /dev/null +++ b/arch/arm/mach-s5pv210/mach-goni.c | |||
| @@ -0,0 +1,98 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/mach-goni.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/types.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/serial_core.h> | ||
| 15 | |||
| 16 | #include <asm/mach/arch.h> | ||
| 17 | #include <asm/mach/map.h> | ||
| 18 | #include <asm/setup.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | |||
| 21 | #include <mach/map.h> | ||
| 22 | #include <mach/regs-clock.h> | ||
| 23 | |||
| 24 | #include <plat/regs-serial.h> | ||
| 25 | #include <plat/s5pv210.h> | ||
| 26 | #include <plat/devs.h> | ||
| 27 | #include <plat/cpu.h> | ||
| 28 | |||
| 29 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | ||
| 30 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
| 31 | S3C2410_UCON_RXILEVEL | \ | ||
| 32 | S3C2410_UCON_TXIRQMODE | \ | ||
| 33 | S3C2410_UCON_RXIRQMODE | \ | ||
| 34 | S3C2410_UCON_RXFIFO_TOI | \ | ||
| 35 | S3C2443_UCON_RXERR_IRQEN) | ||
| 36 | |||
| 37 | #define S5PV210_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
| 38 | |||
| 39 | #define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
| 40 | S5PV210_UFCON_TXTRIG4 | \ | ||
| 41 | S5PV210_UFCON_RXTRIG4) | ||
| 42 | |||
| 43 | static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = { | ||
| 44 | [0] = { | ||
| 45 | .hwport = 0, | ||
| 46 | .flags = 0, | ||
| 47 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 48 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 49 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 50 | }, | ||
| 51 | [1] = { | ||
| 52 | .hwport = 1, | ||
| 53 | .flags = 0, | ||
| 54 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 55 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 56 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 57 | }, | ||
| 58 | [2] = { | ||
| 59 | .hwport = 2, | ||
| 60 | .flags = 0, | ||
| 61 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 62 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 63 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 64 | }, | ||
| 65 | [3] = { | ||
| 66 | .hwport = 3, | ||
| 67 | .flags = 0, | ||
| 68 | .ucon = S5PV210_UCON_DEFAULT, | ||
| 69 | .ulcon = S5PV210_ULCON_DEFAULT, | ||
| 70 | .ufcon = S5PV210_UFCON_DEFAULT, | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct platform_device *goni_devices[] __initdata = { | ||
| 75 | }; | ||
| 76 | |||
| 77 | static void __init goni_map_io(void) | ||
| 78 | { | ||
| 79 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); | ||
| 80 | s3c24xx_init_clocks(24000000); | ||
| 81 | s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs)); | ||
| 82 | } | ||
| 83 | |||
| 84 | static void __init goni_machine_init(void) | ||
| 85 | { | ||
| 86 | platform_add_devices(goni_devices, ARRAY_SIZE(goni_devices)); | ||
| 87 | } | ||
| 88 | |||
| 89 | MACHINE_START(GONI, "GONI") | ||
| 90 | /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */ | ||
| 91 | .phys_io = S3C_PA_UART & 0xfff00000, | ||
| 92 | .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, | ||
| 93 | .boot_params = S5P_PA_SDRAM + 0x100, | ||
| 94 | .init_irq = s5pv210_init_irq, | ||
| 95 | .map_io = goni_map_io, | ||
| 96 | .init_machine = goni_machine_init, | ||
| 97 | .timer = &s3c24xx_timer, | ||
| 98 | MACHINE_END | ||
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c index 6f9fd3274e2e..4c8903c6d104 100644 --- a/arch/arm/mach-s5pv210/mach-smdkc110.c +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c | |||
| @@ -74,6 +74,7 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { | |||
| 74 | static struct platform_device *smdkc110_devices[] __initdata = { | 74 | static struct platform_device *smdkc110_devices[] __initdata = { |
| 75 | &s5pv210_device_iis0, | 75 | &s5pv210_device_iis0, |
| 76 | &s5pv210_device_ac97, | 76 | &s5pv210_device_ac97, |
| 77 | &s3c_device_wdt, | ||
| 77 | }; | 78 | }; |
| 78 | 79 | ||
| 79 | static void __init smdkc110_map_io(void) | 80 | static void __init smdkc110_map_io(void) |
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 3c29e18528a5..0d4627948040 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | #include <plat/s5pv210.h> | 25 | #include <plat/s5pv210.h> |
| 26 | #include <plat/devs.h> | 26 | #include <plat/devs.h> |
| 27 | #include <plat/cpu.h> | 27 | #include <plat/cpu.h> |
| 28 | #include <plat/adc.h> | ||
| 29 | #include <plat/ts.h> | ||
| 28 | 30 | ||
| 29 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | 31 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
| 30 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | 32 | #define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| @@ -74,6 +76,15 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { | |||
| 74 | static struct platform_device *smdkv210_devices[] __initdata = { | 76 | static struct platform_device *smdkv210_devices[] __initdata = { |
| 75 | &s5pv210_device_iis0, | 77 | &s5pv210_device_iis0, |
| 76 | &s5pv210_device_ac97, | 78 | &s5pv210_device_ac97, |
| 79 | &s3c_device_adc, | ||
| 80 | &s3c_device_ts, | ||
| 81 | &s3c_device_wdt, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = { | ||
| 85 | .delay = 10000, | ||
| 86 | .presc = 49, | ||
| 87 | .oversampling_shift = 2, | ||
| 77 | }; | 88 | }; |
| 78 | 89 | ||
| 79 | static void __init smdkv210_map_io(void) | 90 | static void __init smdkv210_map_io(void) |
| @@ -85,6 +96,7 @@ static void __init smdkv210_map_io(void) | |||
| 85 | 96 | ||
| 86 | static void __init smdkv210_machine_init(void) | 97 | static void __init smdkv210_machine_init(void) |
| 87 | { | 98 | { |
| 99 | s3c24xx_ts_set_platdata(&s3c_ts_platform); | ||
| 88 | platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); | 100 | platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); |
| 89 | } | 101 | } |
| 90 | 102 | ||
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c new file mode 100644 index 000000000000..a50cbac8720d --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * Base s5pv210 setup information for 24bpp LCD framebuffer | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/fb.h> | ||
| 16 | |||
| 17 | #include <mach/regs-fb.h> | ||
| 18 | #include <mach/gpio.h> | ||
| 19 | #include <mach/map.h> | ||
| 20 | #include <plat/fb.h> | ||
| 21 | #include <mach/regs-clock.h> | ||
| 22 | #include <plat/gpio-cfg.h> | ||
| 23 | |||
| 24 | void s5pv210_fb_gpio_setup_24bpp(void) | ||
| 25 | { | ||
| 26 | unsigned int gpio = 0; | ||
| 27 | |||
| 28 | for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) { | ||
| 29 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 30 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 31 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
| 32 | } | ||
| 33 | |||
| 34 | for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) { | ||
| 35 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 36 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 37 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
| 38 | } | ||
| 39 | |||
| 40 | for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) { | ||
| 41 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 42 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 43 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
| 44 | } | ||
| 45 | |||
| 46 | for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) { | ||
| 47 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 48 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 49 | s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4); | ||
| 50 | } | ||
| 51 | |||
| 52 | /* Set DISPLAY_CONTROL register for Display path selection. | ||
| 53 | * | ||
| 54 | * ouput | RGB | I80 | ITU | ||
| 55 | * ----------------------------------- | ||
| 56 | * 00 | MIE | FIMD | FIMD | ||
| 57 | * 01 | MDNIE | MDNIE | FIMD | ||
| 58 | * 10 | FIMD | FIMD | FIMD | ||
| 59 | * 11 | FIMD | FIMD | FIMD | ||
| 60 | */ | ||
| 61 | writel(0x2, S5P_MDNIE_SEL); | ||
| 62 | } | ||
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index 9ec6845840e5..c718253c70b8 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/setup-i2c0.c | 1 | /* linux/arch/arm/mach-s5pv210/setup-i2c0.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2009 Samsung Electronics Co., Ltd. | 3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com/ | 4 | * http://www.samsung.com/ |
| 5 | * | 5 | * |
| 6 | * I2C0 GPIO configuration. | 6 | * I2C0 GPIO configuration. |
| @@ -17,9 +17,14 @@ | |||
| 17 | 17 | ||
| 18 | struct platform_device; /* don't need the contents */ | 18 | struct platform_device; /* don't need the contents */ |
| 19 | 19 | ||
| 20 | #include <mach/gpio.h> | ||
| 20 | #include <plat/iic.h> | 21 | #include <plat/iic.h> |
| 22 | #include <plat/gpio-cfg.h> | ||
| 21 | 23 | ||
| 22 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | 24 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) |
| 23 | { | 25 | { |
| 24 | /* Will be populated later */ | 26 | s3c_gpio_cfgpin(S5PV210_GPD1(0), S3C_GPIO_SFN(2)); |
| 27 | s3c_gpio_setpull(S5PV210_GPD1(0), S3C_GPIO_PULL_UP); | ||
| 28 | s3c_gpio_cfgpin(S5PV210_GPD1(1), S3C_GPIO_SFN(2)); | ||
| 29 | s3c_gpio_setpull(S5PV210_GPD1(1), S3C_GPIO_PULL_UP); | ||
| 25 | } | 30 | } |
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c new file mode 100644 index 000000000000..45e0e6ed2ed0 --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c1.c | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/setup-i2c1.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * I2C1 GPIO configuration. | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/setup-i2c1.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | |||
| 18 | struct platform_device; /* don't need the contents */ | ||
| 19 | |||
| 20 | #include <mach/gpio.h> | ||
| 21 | #include <plat/iic.h> | ||
| 22 | #include <plat/gpio-cfg.h> | ||
| 23 | |||
| 24 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) | ||
| 25 | { | ||
| 26 | s3c_gpio_cfgpin(S5PV210_GPD1(2), S3C_GPIO_SFN(2)); | ||
| 27 | s3c_gpio_setpull(S5PV210_GPD1(2), S3C_GPIO_PULL_UP); | ||
| 28 | s3c_gpio_cfgpin(S5PV210_GPD1(3), S3C_GPIO_SFN(2)); | ||
| 29 | s3c_gpio_setpull(S5PV210_GPD1(3), S3C_GPIO_PULL_UP); | ||
| 30 | } | ||
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c new file mode 100644 index 000000000000..b11b4bff69ac --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-i2c2.c | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/setup-i2c2.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * I2C2 GPIO configuration. | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | |||
| 18 | struct platform_device; /* don't need the contents */ | ||
| 19 | |||
| 20 | #include <mach/gpio.h> | ||
| 21 | #include <plat/iic.h> | ||
| 22 | #include <plat/gpio-cfg.h> | ||
| 23 | |||
| 24 | void s3c_i2c2_cfg_gpio(struct platform_device *dev) | ||
| 25 | { | ||
| 26 | s3c_gpio_cfgpin(S5PV210_GPD1(4), S3C_GPIO_SFN(2)); | ||
| 27 | s3c_gpio_setpull(S5PV210_GPD1(4), S3C_GPIO_PULL_UP); | ||
| 28 | s3c_gpio_cfgpin(S5PV210_GPD1(5), S3C_GPIO_SFN(2)); | ||
| 29 | s3c_gpio_setpull(S5PV210_GPD1(5), S3C_GPIO_PULL_UP); | ||
| 30 | } | ||
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c new file mode 100644 index 000000000000..fe7d86dad14c --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c | |||
| @@ -0,0 +1,104 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/setup-sdhci-gpio.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5PV210 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/mmc/host.h> | ||
| 19 | #include <linux/mmc/card.h> | ||
| 20 | |||
| 21 | #include <mach/gpio.h> | ||
| 22 | #include <plat/gpio-cfg.h> | ||
| 23 | #include <plat/regs-sdhci.h> | ||
| 24 | |||
| 25 | void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | ||
| 26 | { | ||
| 27 | unsigned int gpio; | ||
| 28 | |||
| 29 | /* Set all the necessary GPG0/GPG1 pins to special-function 2 */ | ||
| 30 | for (gpio = S5PV210_GPG0(0); gpio < S5PV210_GPG0(2); gpio++) { | ||
| 31 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 32 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 33 | } | ||
| 34 | switch (width) { | ||
| 35 | case 8: | ||
| 36 | /* GPG1[3:6] special-funtion 3 */ | ||
| 37 | for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { | ||
| 38 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); | ||
| 39 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 40 | } | ||
| 41 | case 4: | ||
| 42 | /* GPG0[3:6] special-funtion 2 */ | ||
| 43 | for (gpio = S5PV210_GPG0(3); gpio <= S5PV210_GPG0(6); gpio++) { | ||
| 44 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 45 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 46 | } | ||
| 47 | default: | ||
| 48 | break; | ||
| 49 | } | ||
| 50 | |||
| 51 | s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP); | ||
| 52 | s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2)); | ||
| 53 | } | ||
| 54 | |||
| 55 | void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | ||
| 56 | { | ||
| 57 | unsigned int gpio; | ||
| 58 | |||
| 59 | /* Set all the necessary GPG1[0:1] pins to special-function 2 */ | ||
| 60 | for (gpio = S5PV210_GPG1(0); gpio < S5PV210_GPG1(2); gpio++) { | ||
| 61 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 62 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 63 | } | ||
| 64 | |||
| 65 | /* Data pin GPG1[3:6] to special-function 2 */ | ||
| 66 | for (gpio = S5PV210_GPG1(3); gpio <= S5PV210_GPG1(6); gpio++) { | ||
| 67 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 68 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 69 | } | ||
| 70 | |||
| 71 | s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP); | ||
| 72 | s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2)); | ||
| 73 | } | ||
| 74 | |||
| 75 | void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | ||
| 76 | { | ||
| 77 | unsigned int gpio; | ||
| 78 | |||
| 79 | /* Set all the necessary GPG2[0:1] pins to special-function 2 */ | ||
| 80 | for (gpio = S5PV210_GPG2(0); gpio < S5PV210_GPG2(2); gpio++) { | ||
| 81 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 82 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 83 | } | ||
| 84 | |||
| 85 | switch (width) { | ||
| 86 | case 8: | ||
| 87 | /* Data pin GPG3[3:6] to special-function 3 */ | ||
| 88 | for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) { | ||
| 89 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3)); | ||
| 90 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 91 | } | ||
| 92 | case 4: | ||
| 93 | /* Data pin GPG2[3:6] to special-function 2 */ | ||
| 94 | for (gpio = S5PV210_GPG2(3); gpio <= S5PV210_GPG2(6); gpio++) { | ||
| 95 | s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2)); | ||
| 96 | s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); | ||
| 97 | } | ||
| 98 | default: | ||
| 99 | break; | ||
| 100 | } | ||
| 101 | |||
| 102 | s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP); | ||
| 103 | s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2)); | ||
| 104 | } | ||
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c new file mode 100644 index 000000000000..51815ec60c2a --- /dev/null +++ b/arch/arm/mach-s5pv210/setup-sdhci.c | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* linux/arch/arm/mach-s5pv210/setup-sdhci.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S5PV210 - Helper functions for settign up SDHCI device(s) (HSMMC) | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/types.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | |||
| 19 | #include <linux/mmc/card.h> | ||
| 20 | #include <linux/mmc/host.h> | ||
| 21 | |||
| 22 | #include <plat/regs-sdhci.h> | ||
| 23 | #include <plat/sdhci.h> | ||
| 24 | |||
| 25 | /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */ | ||
| 26 | |||
| 27 | char *s5pv210_hsmmc_clksrcs[4] = { | ||
| 28 | [0] = "hsmmc", /* HCLK */ | ||
| 29 | [1] = "hsmmc", /* HCLK */ | ||
| 30 | [2] = "sclk_mmc", /* mmc_bus */ | ||
| 31 | /*[4] = reserved */ | ||
| 32 | }; | ||
| 33 | |||
| 34 | void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, | ||
| 35 | void __iomem *r, | ||
| 36 | struct mmc_ios *ios, | ||
| 37 | struct mmc_card *card) | ||
| 38 | { | ||
| 39 | u32 ctrl2, ctrl3; | ||
| 40 | |||
| 41 | /* don't need to alter anything acording to card-type */ | ||
| 42 | |||
| 43 | writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA, r + S3C64XX_SDHCI_CONTROL4); | ||
| 44 | |||
| 45 | ctrl2 = readl(r + S3C_SDHCI_CONTROL2); | ||
| 46 | ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK; | ||
| 47 | ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR | | ||
| 48 | S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK | | ||
| 49 | S3C_SDHCI_CTRL2_ENFBCLKRX | | ||
| 50 | S3C_SDHCI_CTRL2_DFCNT_NONE | | ||
| 51 | S3C_SDHCI_CTRL2_ENCLKOUTHOLD); | ||
| 52 | |||
| 53 | if (ios->clock < 25 * 1000000) | ||
| 54 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 | | ||
| 55 | S3C_SDHCI_CTRL3_FCSEL2 | | ||
| 56 | S3C_SDHCI_CTRL3_FCSEL1 | | ||
| 57 | S3C_SDHCI_CTRL3_FCSEL0); | ||
| 58 | else | ||
| 59 | ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0); | ||
| 60 | |||
| 61 | writel(ctrl2, r + S3C_SDHCI_CONTROL2); | ||
| 62 | writel(ctrl3, r + S3C_SDHCI_CONTROL3); | ||
| 63 | } | ||
diff --git a/arch/arm/mach-sa1100/leds.c b/arch/arm/mach-sa1100/leds.c index 4cf7c565aaed..bbfe197fb4d6 100644 --- a/arch/arm/mach-sa1100/leds.c +++ b/arch/arm/mach-sa1100/leds.c | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * linux/arch/arm/mach-sa1100/leds.c | 2 | * linux/arch/arm/mach-sa1100/leds.c |
| 3 | * | 3 | * |
| 4 | * SA1100 LEDs dispatcher | 4 | * SA1100 LEDs dispatcher |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2001 Nicolas Pitre | 6 | * Copyright (C) 2001 Nicolas Pitre |
| 7 | */ | 7 | */ |
| 8 | #include <linux/compiler.h> | 8 | #include <linux/compiler.h> |
| @@ -18,10 +18,10 @@ sa1100_leds_init(void) | |||
| 18 | { | 18 | { |
| 19 | if (machine_is_assabet()) | 19 | if (machine_is_assabet()) |
| 20 | leds_event = assabet_leds_event; | 20 | leds_event = assabet_leds_event; |
| 21 | if (machine_is_consus()) | 21 | if (machine_is_consus()) |
| 22 | leds_event = consus_leds_event; | 22 | leds_event = consus_leds_event; |
| 23 | if (machine_is_badge4()) | 23 | if (machine_is_badge4()) |
| 24 | leds_event = badge4_leds_event; | 24 | leds_event = badge4_leds_event; |
| 25 | if (machine_is_brutus()) | 25 | if (machine_is_brutus()) |
| 26 | leds_event = brutus_leds_event; | 26 | leds_event = brutus_leds_event; |
| 27 | if (machine_is_cerf()) | 27 | if (machine_is_cerf()) |
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c index 37a7112d4117..89d175ce74d2 100644 --- a/arch/arm/mach-shark/pci.c +++ b/arch/arm/mach-shark/pci.c | |||
| @@ -16,16 +16,19 @@ | |||
| 16 | static int __init shark_map_irq(struct pci_dev *dev, u8 slot, u8 pin) | 16 | static int __init shark_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 17 | { | 17 | { |
| 18 | if (dev->bus->number == 0) | 18 | if (dev->bus->number == 0) |
| 19 | if (dev->devfn == 0) return 255; | 19 | if (dev->devfn == 0) |
| 20 | else return 11; | 20 | return 255; |
| 21 | else return 255; | 21 | else |
| 22 | return 11; | ||
| 23 | else | ||
| 24 | return 255; | ||
| 22 | } | 25 | } |
| 23 | 26 | ||
| 24 | extern void __init via82c505_preinit(void); | 27 | extern void __init via82c505_preinit(void); |
| 25 | 28 | ||
| 26 | static struct hw_pci shark_pci __initdata = { | 29 | static struct hw_pci shark_pci __initdata = { |
| 27 | .setup = via82c505_setup, | 30 | .setup = via82c505_setup, |
| 28 | .swizzle = pci_std_swizzle, | 31 | .swizzle = pci_std_swizzle, |
| 29 | .map_irq = shark_map_irq, | 32 | .map_irq = shark_map_irq, |
| 30 | .nr_controllers = 1, | 33 | .nr_controllers = 1, |
| 31 | .scan = via82c505_scan_bus, | 34 | .scan = via82c505_scan_bus, |
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c index b67e571d4bf7..baf6bcc3169c 100644 --- a/arch/arm/mach-spear6xx/spear6xx.c +++ b/arch/arm/mach-spear6xx/spear6xx.c | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | 13 | ||
| 14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
| 15 | #include <linux/amba/pl061.h> | 15 | #include <linux/amba/pl061.h> |
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/ptrace.h> | 16 | #include <linux/ptrace.h> |
| 18 | #include <linux/io.h> | 17 | #include <linux/io.h> |
| 19 | #include <asm/hardware/vic.h> | 18 | #include <asm/hardware/vic.h> |
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c index e2958eb567f9..b2eda4dc1c34 100644 --- a/arch/arm/mach-w90x900/dev.c +++ b/arch/arm/mach-w90x900/dev.c | |||
| @@ -423,6 +423,33 @@ void nuc900_fb_set_platdata(struct nuc900fb_mach_info *pd) | |||
| 423 | } | 423 | } |
| 424 | #endif | 424 | #endif |
| 425 | 425 | ||
| 426 | /* AUDIO controller*/ | ||
| 427 | static u64 nuc900_device_audio_dmamask = -1; | ||
| 428 | static struct resource nuc900_ac97_resource[] = { | ||
| 429 | [0] = { | ||
| 430 | .start = W90X900_PA_ACTL, | ||
| 431 | .end = W90X900_PA_ACTL + W90X900_SZ_ACTL - 1, | ||
| 432 | .flags = IORESOURCE_MEM, | ||
| 433 | }, | ||
| 434 | [1] = { | ||
| 435 | .start = IRQ_ACTL, | ||
| 436 | .end = IRQ_ACTL, | ||
| 437 | .flags = IORESOURCE_IRQ, | ||
| 438 | } | ||
| 439 | |||
| 440 | }; | ||
| 441 | |||
| 442 | struct platform_device nuc900_device_audio = { | ||
| 443 | .name = "nuc900-audio", | ||
| 444 | .id = -1, | ||
| 445 | .num_resources = ARRAY_SIZE(nuc900_ac97_resource), | ||
| 446 | .resource = nuc900_ac97_resource, | ||
| 447 | .dev = { | ||
| 448 | .dma_mask = &nuc900_device_audio_dmamask, | ||
| 449 | .coherent_dma_mask = -1, | ||
| 450 | } | ||
| 451 | }; | ||
| 452 | |||
| 426 | /*Here should be your evb resourse,such as LCD*/ | 453 | /*Here should be your evb resourse,such as LCD*/ |
| 427 | 454 | ||
| 428 | static struct platform_device *nuc900_public_dev[] __initdata = { | 455 | static struct platform_device *nuc900_public_dev[] __initdata = { |
| @@ -434,6 +461,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = { | |||
| 434 | &nuc900_device_emc, | 461 | &nuc900_device_emc, |
| 435 | &nuc900_device_spi, | 462 | &nuc900_device_spi, |
| 436 | &nuc900_device_wdt, | 463 | &nuc900_device_wdt, |
| 464 | &nuc900_device_audio, | ||
| 437 | }; | 465 | }; |
| 438 | 466 | ||
| 439 | /* Provide adding specific CPU platform devices API */ | 467 | /* Provide adding specific CPU platform devices API */ |
diff --git a/arch/arm/mach-w90x900/include/mach/mfp.h b/arch/arm/mach-w90x900/include/mach/mfp.h new file mode 100644 index 000000000000..94c0e71617c6 --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/mfp.h | |||
| @@ -0,0 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-w90x900/include/mach/mfp.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2010 Nuvoton technology corporation. | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * Based on arch/arm/mach-s3c2410/include/mach/map.h | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation;version 2 of the License. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_MFP_H | ||
| 17 | #define __ASM_ARCH_MFP_H | ||
| 18 | |||
| 19 | extern void mfp_set_groupf(struct device *dev); | ||
| 20 | extern void mfp_set_groupc(struct device *dev); | ||
| 21 | extern void mfp_set_groupi(struct device *dev); | ||
| 22 | extern void mfp_set_groupg(struct device *dev); | ||
| 23 | |||
| 24 | #endif /* __ASM_ARCH_MFP_H */ | ||
diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c index a47dc9a708ee..fb7fb627b1a5 100644 --- a/arch/arm/mach-w90x900/mfp.c +++ b/arch/arm/mach-w90x900/mfp.c | |||
| @@ -36,9 +36,12 @@ | |||
| 36 | 36 | ||
| 37 | #define GPIOG0TO1 (0x03 << 14) | 37 | #define GPIOG0TO1 (0x03 << 14) |
| 38 | #define GPIOG2TO3 (0x03 << 16) | 38 | #define GPIOG2TO3 (0x03 << 16) |
| 39 | #define GPIOG22TO23 (0x03 << 22) | ||
| 40 | |||
| 39 | #define ENSPI (0x0a << 14) | 41 | #define ENSPI (0x0a << 14) |
| 40 | #define ENI2C0 (0x01 << 14) | 42 | #define ENI2C0 (0x01 << 14) |
| 41 | #define ENI2C1 (0x01 << 16) | 43 | #define ENI2C1 (0x01 << 16) |
| 44 | #define ENAC97 (0x02 << 22) | ||
| 42 | 45 | ||
| 43 | static DEFINE_MUTEX(mfp_mutex); | 46 | static DEFINE_MUTEX(mfp_mutex); |
| 44 | 47 | ||
| @@ -146,6 +149,9 @@ void mfp_set_groupg(struct device *dev) | |||
| 146 | } else if (strcmp(dev_id, "nuc900-i2c1") == 0) { | 149 | } else if (strcmp(dev_id, "nuc900-i2c1") == 0) { |
| 147 | mfpen &= ~(GPIOG2TO3); | 150 | mfpen &= ~(GPIOG2TO3); |
| 148 | mfpen |= ENI2C1;/*enable i2c1*/ | 151 | mfpen |= ENI2C1;/*enable i2c1*/ |
| 152 | } else if (strcmp(dev_id, "nuc900-audio") == 0) { | ||
| 153 | mfpen &= ~(GPIOG22TO23); | ||
| 154 | mfpen |= ENAC97;/*enable AC97*/ | ||
| 149 | } else { | 155 | } else { |
| 150 | mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/ | 156 | mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/ |
| 151 | } | 157 | } |
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 06a90dcfc60a..37c8157e116e 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S | |||
| @@ -91,7 +91,11 @@ ENTRY(v7_flush_kern_cache_all) | |||
| 91 | THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) | 91 | THUMB( stmfd sp!, {r4-r7, r9-r11, lr} ) |
| 92 | bl v7_flush_dcache_all | 92 | bl v7_flush_dcache_all |
| 93 | mov r0, #0 | 93 | mov r0, #0 |
| 94 | #ifdef CONFIG_SMP | ||
| 95 | mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable | ||
| 96 | #else | ||
| 94 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate | 97 | mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate |
| 98 | #endif | ||
| 95 | ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) | 99 | ARM( ldmfd sp!, {r4-r5, r7, r9-r11, lr} ) |
| 96 | THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) | 100 | THUMB( ldmfd sp!, {r4-r7, r9-r11, lr} ) |
| 97 | mov pc, lr | 101 | mov pc, lr |
diff --git a/arch/arm/nwfpe/ChangeLog b/arch/arm/nwfpe/ChangeLog index eeb5a7c5ff09..fa8028b1e1cf 100644 --- a/arch/arm/nwfpe/ChangeLog +++ b/arch/arm/nwfpe/ChangeLog | |||
| @@ -72,7 +72,7 @@ | |||
| 72 | 1998-11-23 Scott Bambrough <scottb@netwinder.org> | 72 | 1998-11-23 Scott Bambrough <scottb@netwinder.org> |
| 73 | 73 | ||
| 74 | * README.FPE - fix typo in description of lfm/sfm instructions | 74 | * README.FPE - fix typo in description of lfm/sfm instructions |
| 75 | * NOTES - Added file to describe known bugs/problems | 75 | * NOTES - Added file to describe known bugs/problems |
| 76 | * fpmodule.c - Changed version number to 0.94 | 76 | * fpmodule.c - Changed version number to 0.94 |
| 77 | 77 | ||
| 78 | 1998-11-20 Scott Bambrough <scottb@netwinder.org> | 78 | 1998-11-20 Scott Bambrough <scottb@netwinder.org> |
diff --git a/arch/arm/nwfpe/fpsr.h b/arch/arm/nwfpe/fpsr.h index 859b300d89fd..bd425dc13b61 100644 --- a/arch/arm/nwfpe/fpsr.h +++ b/arch/arm/nwfpe/fpsr.h | |||
| @@ -30,7 +30,7 @@ one byte. | |||
| 30 | EXCEPTION TRAP ENABLE BYTE | 30 | EXCEPTION TRAP ENABLE BYTE |
| 31 | SYSTEM CONTROL BYTE | 31 | SYSTEM CONTROL BYTE |
| 32 | CUMULATIVE EXCEPTION FLAGS BYTE | 32 | CUMULATIVE EXCEPTION FLAGS BYTE |
| 33 | 33 | ||
| 34 | The FPCR is a 32 bit register consisting of bit flags. | 34 | The FPCR is a 32 bit register consisting of bit flags. |
| 35 | */ | 35 | */ |
| 36 | 36 | ||
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c index cb0b63874482..2a8646173c2f 100644 --- a/arch/arm/plat-mxc/ehci.c +++ b/arch/arm/plat-mxc/ehci.c | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> | 2 | * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de> |
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 3 | * | 4 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 5 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the | 6 | * under the terms of the GNU General Public License as published by the |
| @@ -50,7 +51,26 @@ | |||
| 50 | #define MX35_H1_TLL_BIT (1 << 5) | 51 | #define MX35_H1_TLL_BIT (1 << 5) |
| 51 | #define MX35_H1_USBTE_BIT (1 << 4) | 52 | #define MX35_H1_USBTE_BIT (1 << 4) |
| 52 | 53 | ||
| 53 | int mxc_set_usbcontrol(int port, unsigned int flags) | 54 | #define MXC_OTG_OFFSET 0 |
| 55 | #define MXC_H1_OFFSET 0x200 | ||
| 56 | |||
| 57 | /* USB_CTRL */ | ||
| 58 | #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ | ||
| 59 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ | ||
| 60 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ | ||
| 61 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ | ||
| 62 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ | ||
| 63 | |||
| 64 | /* USB_PHY_CTRL_FUNC */ | ||
| 65 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ | ||
| 66 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ | ||
| 67 | |||
| 68 | #define MXC_USBCMD_OFFSET 0x140 | ||
| 69 | |||
| 70 | /* USBCMD */ | ||
| 71 | #define MXC_UCMD_ITC_NO_THRESHOLD_MASK (~(0xff << 16)) /* Interrupt Threshold Control */ | ||
| 72 | |||
| 73 | int mxc_initialize_usb_hw(int port, unsigned int flags) | ||
| 54 | { | 74 | { |
| 55 | unsigned int v; | 75 | unsigned int v; |
| 56 | #ifdef CONFIG_ARCH_MX3 | 76 | #ifdef CONFIG_ARCH_MX3 |
| @@ -186,9 +206,85 @@ int mxc_set_usbcontrol(int port, unsigned int flags) | |||
| 186 | return 0; | 206 | return 0; |
| 187 | } | 207 | } |
| 188 | #endif /* CONFIG_MACH_MX27 */ | 208 | #endif /* CONFIG_MACH_MX27 */ |
| 209 | #ifdef CONFIG_ARCH_MX51 | ||
| 210 | if (cpu_is_mx51()) { | ||
| 211 | void __iomem *usb_base; | ||
| 212 | u32 usbotg_base; | ||
| 213 | u32 usbother_base; | ||
| 214 | int ret = 0; | ||
| 215 | |||
| 216 | usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); | ||
| 217 | |||
| 218 | switch (port) { | ||
| 219 | case 0: /* OTG port */ | ||
| 220 | usbotg_base = usb_base + MXC_OTG_OFFSET; | ||
| 221 | break; | ||
| 222 | case 1: /* Host 1 port */ | ||
| 223 | usbotg_base = usb_base + MXC_H1_OFFSET; | ||
| 224 | break; | ||
| 225 | default: | ||
| 226 | printk(KERN_ERR"%s no such port %d\n", __func__, port); | ||
| 227 | ret = -ENOENT; | ||
| 228 | goto error; | ||
| 229 | } | ||
| 230 | usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; | ||
| 231 | |||
| 232 | switch (port) { | ||
| 233 | case 0: /*OTG port */ | ||
| 234 | if (flags & MXC_EHCI_INTERNAL_PHY) { | ||
| 235 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 236 | |||
| 237 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 238 | v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ | ||
| 239 | else | ||
| 240 | v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ | ||
| 241 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 242 | |||
| 243 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | ||
| 244 | if (flags & MXC_EHCI_WAKEUP_ENABLED) | ||
| 245 | v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ | ||
| 246 | else | ||
| 247 | v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ | ||
| 248 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | ||
| 249 | } | ||
| 250 | break; | ||
| 251 | case 1: /* Host 1 */ | ||
| 252 | /*Host ULPI */ | ||
| 253 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | ||
| 254 | if (flags & MXC_EHCI_WAKEUP_ENABLED) | ||
| 255 | v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ | ||
| 256 | else | ||
| 257 | v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ | ||
| 258 | |||
| 259 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 260 | v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | ||
| 261 | else | ||
| 262 | v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ | ||
| 263 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | ||
| 264 | |||
| 265 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 266 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | ||
| 267 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ | ||
| 268 | else | ||
| 269 | v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ | ||
| 270 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | ||
| 271 | |||
| 272 | v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); | ||
| 273 | if (flags & MXC_EHCI_ITC_NO_THRESHOLD) | ||
| 274 | /* Interrupt Threshold Control:Immediate (no threshold) */ | ||
| 275 | v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; | ||
| 276 | __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); | ||
| 277 | break; | ||
| 278 | } | ||
| 279 | |||
| 280 | error: | ||
| 281 | iounmap(usb_base); | ||
| 282 | return ret; | ||
| 283 | } | ||
| 284 | #endif | ||
| 189 | printk(KERN_WARNING | 285 | printk(KERN_WARNING |
| 190 | "%s() unable to setup USBCONTROL for this CPU\n", __func__); | 286 | "%s() unable to setup USBCONTROL for this CPU\n", __func__); |
| 191 | return -EINVAL; | 287 | return -EINVAL; |
| 192 | } | 288 | } |
| 193 | EXPORT_SYMBOL(mxc_set_usbcontrol); | 289 | EXPORT_SYMBOL(mxc_initialize_usb_hw); |
| 194 | 290 | ||
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index 70b23893f094..71437c61cfd7 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * | 4 | * |
| 5 | * Based on code from Freescale, | 5 | * Based on code from Freescale, |
| 6 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. | 6 | * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 7 | * | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or | 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License | 9 | * modify it under the terms of the GNU General Public License |
| @@ -38,7 +38,6 @@ static int gpio_table_size; | |||
| 38 | #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) | 38 | #define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10) |
| 39 | #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) | 39 | #define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14) |
| 40 | #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) | 40 | #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) |
| 41 | #define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18) | ||
| 42 | 41 | ||
| 43 | #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) | 42 | #define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0) |
| 44 | #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) | 43 | #define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1) |
| @@ -289,7 +288,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt) | |||
| 289 | /* its a serious configuration bug when it fails */ | 288 | /* its a serious configuration bug when it fails */ |
| 290 | BUG_ON( gpiochip_add(&port[i].chip) < 0 ); | 289 | BUG_ON( gpiochip_add(&port[i].chip) < 0 ); |
| 291 | 290 | ||
| 292 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) { | 291 | if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) { |
| 293 | /* setup one handler for each entry */ | 292 | /* setup one handler for each entry */ |
| 294 | set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); | 293 | set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler); |
| 295 | set_irq_data(port[i].irq, &port[i]); | 294 | set_irq_data(port[i].irq, &port[i]); |
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h index fc5fec9b55f0..36ff3cedee1a 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h | |||
| @@ -26,6 +26,7 @@ enum mx31moboard_boards { | |||
| 26 | MX31DEVBOARD = 1, | 26 | MX31DEVBOARD = 1, |
| 27 | MX31MARXBOT = 2, | 27 | MX31MARXBOT = 2, |
| 28 | MX31SMARTBOT = 3, | 28 | MX31SMARTBOT = 3, |
| 29 | MX31EYEBOT = 4, | ||
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | /* | 32 | /* |
| @@ -35,7 +36,7 @@ enum mx31moboard_boards { | |||
| 35 | 36 | ||
| 36 | extern void mx31moboard_devboard_init(void); | 37 | extern void mx31moboard_devboard_init(void); |
| 37 | extern void mx31moboard_marxbot_init(void); | 38 | extern void mx31moboard_marxbot_init(void); |
| 38 | extern void mx31moboard_smartbot_init(void); | 39 | extern void mx31moboard_smartbot_init(int board); |
| 39 | 40 | ||
| 40 | #endif | 41 | #endif |
| 41 | 42 | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index e51465d7b224..cbaed295a2bf 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h | |||
| @@ -719,6 +719,23 @@ enum iomux_pins { | |||
| 719 | #define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) | 719 | #define MX31_PIN_SRXD5__SRXD5 IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_FUNC) |
| 720 | #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) | 720 | #define MX31_PIN_SCK5__SCK5 IOMUX_MODE(MX31_PIN_SCK5, IOMUX_CONFIG_FUNC) |
| 721 | #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) | 721 | #define MX31_PIN_SFS5__SFS5 IOMUX_MODE(MX31_PIN_SFS5, IOMUX_CONFIG_FUNC) |
| 722 | #define MX31_PIN_KEY_ROW0_KEY_ROW0 IOMUX_MODE(MX31_PIN_KEY_ROW0, IOMUX_CONFIG_FUNC) | ||
| 723 | #define MX31_PIN_KEY_ROW1_KEY_ROW1 IOMUX_MODE(MX31_PIN_KEY_ROW1, IOMUX_CONFIG_FUNC) | ||
| 724 | #define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC) | ||
| 725 | #define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC) | ||
| 726 | #define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC) | ||
| 727 | #define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC) | ||
| 728 | #define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC) | ||
| 729 | #define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC) | ||
| 730 | #define MX31_PIN_KEY_COL0_KEY_COL0 IOMUX_MODE(MX31_PIN_KEY_COL0, IOMUX_CONFIG_FUNC) | ||
| 731 | #define MX31_PIN_KEY_COL1_KEY_COL1 IOMUX_MODE(MX31_PIN_KEY_COL1, IOMUX_CONFIG_FUNC) | ||
| 732 | #define MX31_PIN_KEY_COL2_KEY_COL2 IOMUX_MODE(MX31_PIN_KEY_COL2, IOMUX_CONFIG_FUNC) | ||
| 733 | #define MX31_PIN_KEY_COL3_KEY_COL3 IOMUX_MODE(MX31_PIN_KEY_COL3, IOMUX_CONFIG_FUNC) | ||
| 734 | #define MX31_PIN_KEY_COL4_KEY_COL4 IOMUX_MODE(MX31_PIN_KEY_COL4, IOMUX_CONFIG_FUNC) | ||
| 735 | #define MX31_PIN_KEY_COL5_KEY_COL5 IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_FUNC) | ||
| 736 | #define MX31_PIN_KEY_COL6_KEY_COL6 IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_FUNC) | ||
| 737 | #define MX31_PIN_KEY_COL7_KEY_COL7 IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_FUNC) | ||
| 738 | |||
| 722 | 739 | ||
| 723 | /* | 740 | /* |
| 724 | * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, | 741 | * XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed with cspi2_ss0, |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h index b4f975e6a665..ab0f95d953d0 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h | |||
| @@ -1,5 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | 2 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> |
| 3 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | ||
| 3 | * | 4 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 5 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 6 | * License. You may obtain a copy of the GNU General Public License |
| @@ -37,6 +38,11 @@ typedef enum iomux_config { | |||
| 37 | PAD_CTL_SRE_FAST) | 38 | PAD_CTL_SRE_FAST) |
| 38 | #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ | 39 | #define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ |
| 39 | PAD_CTL_SRE_FAST) | 40 | PAD_CTL_SRE_FAST) |
| 41 | #define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ | ||
| 42 | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ | ||
| 43 | PAD_CTL_PKE | PAD_CTL_HYS) | ||
| 44 | #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ | ||
| 45 | PAD_CTL_SRE_FAST) | ||
| 40 | 46 | ||
| 41 | /* | 47 | /* |
| 42 | * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> | 48 | * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> |
| @@ -57,6 +63,7 @@ typedef enum iomux_config { | |||
| 57 | #define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) | 63 | #define MX51_PAD_GPIO_2_3__EIM_D19 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) |
| 58 | #define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) | 64 | #define MX51_PAD_GPIO_2_4__EIM_D20 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) |
| 59 | #define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) | 65 | #define MX51_PAD_GPIO_2_5__EIM_D21 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, NO_PAD_CTRL) |
| 66 | #define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_GPIO_PAD_CTRL) | ||
| 60 | #define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) | 67 | #define MX51_PAD_GPIO_2_6__EIM_D22 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) |
| 61 | #define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) | 68 | #define MX51_PAD_GPIO_2_7__EIM_D23 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) |
| 62 | 69 | ||
| @@ -208,18 +215,19 @@ typedef enum iomux_config { | |||
| 208 | #define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) | 215 | #define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) |
| 209 | #define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) | 216 | #define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) |
| 210 | #define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) | 217 | #define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) |
| 211 | #define MX51_PAD_GPIO_1_25__USBH1_CLK IOMUX_PAD(0x678, 0x278, 2, 0x0, 0, NO_PAD_CTRL) | 218 | #define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 212 | #define MX51_PAD_GPIO_1_26__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 2, 0x0, 0, NO_PAD_CTRL) | 219 | #define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 213 | #define MX51_PAD_GPIO_1_27__USBH1_STP IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, NO_PAD_CTRL) | 220 | #define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 214 | #define MX51_PAD_GPIO_1_28__USBH1_NXT IOMUX_PAD(0x684, 0x284, 2, 0x0, 0, NO_PAD_CTRL) | 221 | #define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 215 | #define MX51_PAD_GPIO_1_11__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 2, 0x0, 0, NO_PAD_CTRL) | 222 | #define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 216 | #define MX51_PAD_GPIO_1_12__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 2, 0x0, 0, NO_PAD_CTRL) | 223 | #define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 217 | #define MX51_PAD_GPIO_1_13__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 2, 0x0, 0, NO_PAD_CTRL) | 224 | #define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 218 | #define MX51_PAD_GPIO_1_14__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 2, 0x0, 0, NO_PAD_CTRL) | 225 | #define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 219 | #define MX51_PAD_GPIO_1_15__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 2, 0x0, 0, NO_PAD_CTRL) | 226 | #define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 220 | #define MX51_PAD_GPIO_1_16__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 2, 0x0, 0, NO_PAD_CTRL) | 227 | #define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 221 | #define MX51_PAD_GPIO_1_17__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 2, 0x0, 0, NO_PAD_CTRL) | 228 | #define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 222 | #define MX51_PAD_GPIO_1_18__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 2, 0x0, 0, NO_PAD_CTRL) | 229 | #define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) |
| 230 | #define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL) | ||
| 223 | #define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) | 231 | #define MX51_PAD_GPIO_3_0__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) |
| 224 | #define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) | 232 | #define MX51_PAD_GPIO_3_1__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL) |
| 225 | #define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) | 233 | #define MX51_PAD_GPIO_3_2__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL) |
| @@ -299,7 +307,7 @@ typedef enum iomux_config { | |||
| 299 | #define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) | 307 | #define MX51_PAD_GPIO_1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) |
| 300 | #define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) | 308 | #define MX51_PAD_GPIO_1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) |
| 301 | #define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) | 309 | #define MX51_PAD_GPIO_1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) |
| 302 | #define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) | 310 | #define MX51_PAD_GPIO_1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL) |
| 303 | #define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ | 311 | #define MX51_PAD_GPIO_1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \ |
| 304 | (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) | 312 | (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)) |
| 305 | #define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) | 313 | #define MX51_PAD_GPIO_1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) |
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 4b9b8368c0c0..7fc5f9946199 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h | |||
| @@ -25,6 +25,18 @@ | |||
| 25 | #define MXC_EHCI_INTERNAL_PHY (1 << 7) | 25 | #define MXC_EHCI_INTERNAL_PHY (1 << 7) |
| 26 | #define MXC_EHCI_IPPUE_DOWN (1 << 8) | 26 | #define MXC_EHCI_IPPUE_DOWN (1 << 8) |
| 27 | #define MXC_EHCI_IPPUE_UP (1 << 9) | 27 | #define MXC_EHCI_IPPUE_UP (1 << 9) |
| 28 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 10) | ||
| 29 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) | ||
| 30 | |||
| 31 | #define MXC_USBCTRL_OFFSET 0 | ||
| 32 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | ||
| 33 | #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc | ||
| 34 | |||
| 35 | #define MX5_USBOTHER_REGS_OFFSET 0x800 | ||
| 36 | |||
| 37 | /* USB_PHY_CTRL_FUNC2*/ | ||
| 38 | #define MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3 | ||
| 39 | #define MX5_USB_UTMI_PHYCTRL1_PLLDIV_SHIFT 0 | ||
| 28 | 40 | ||
| 29 | struct mxc_usbh_platform_data { | 41 | struct mxc_usbh_platform_data { |
| 30 | int (*init)(struct platform_device *pdev); | 42 | int (*init)(struct platform_device *pdev); |
| @@ -35,7 +47,7 @@ struct mxc_usbh_platform_data { | |||
| 35 | struct otg_transceiver *otg; | 47 | struct otg_transceiver *otg; |
| 36 | }; | 48 | }; |
| 37 | 49 | ||
| 38 | int mxc_set_usbcontrol(int port, unsigned int flags); | 50 | int mxc_initialize_usb_hw(int port, unsigned int flags); |
| 39 | 51 | ||
| 40 | #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ | 52 | #endif /* __INCLUDE_ASM_ARCH_MXC_EHCI_H */ |
| 41 | 53 | ||
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index c1ce51abdba6..f9a1b059a76c 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c | |||
| @@ -54,14 +54,14 @@ | |||
| 54 | #define MX2_TSTAT_COMP (1 << 0) | 54 | #define MX2_TSTAT_COMP (1 << 0) |
| 55 | 55 | ||
| 56 | /* MX31, MX35, MX25, MXC91231, MX5 */ | 56 | /* MX31, MX35, MX25, MXC91231, MX5 */ |
| 57 | #define MX3_TCTL_WAITEN (1 << 3) /* Wait enable mode */ | 57 | #define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */ |
| 58 | #define MX3_TCTL_CLK_IPG (1 << 6) | 58 | #define V2_TCTL_CLK_IPG (1 << 6) |
| 59 | #define MX3_TCTL_FRR (1 << 9) | 59 | #define V2_TCTL_FRR (1 << 9) |
| 60 | #define MX3_IR 0x0c | 60 | #define V2_IR 0x0c |
| 61 | #define MX3_TSTAT 0x08 | 61 | #define V2_TSTAT 0x08 |
| 62 | #define MX3_TSTAT_OF1 (1 << 0) | 62 | #define V2_TSTAT_OF1 (1 << 0) |
| 63 | #define MX3_TCN 0x24 | 63 | #define V2_TCN 0x24 |
| 64 | #define MX3_TCMP 0x10 | 64 | #define V2_TCMP 0x10 |
| 65 | 65 | ||
| 66 | #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) | 66 | #define timer_is_v1() (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27()) |
| 67 | #define timer_is_v2() (!timer_is_v1()) | 67 | #define timer_is_v2() (!timer_is_v1()) |
| @@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void) | |||
| 76 | unsigned int tmp; | 76 | unsigned int tmp; |
| 77 | 77 | ||
| 78 | if (timer_is_v2()) | 78 | if (timer_is_v2()) |
| 79 | __raw_writel(0, timer_base + MX3_IR); | 79 | __raw_writel(0, timer_base + V2_IR); |
| 80 | else { | 80 | else { |
| 81 | tmp = __raw_readl(timer_base + MXC_TCTL); | 81 | tmp = __raw_readl(timer_base + MXC_TCTL); |
| 82 | __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); | 82 | __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); |
| @@ -86,7 +86,7 @@ static inline void gpt_irq_disable(void) | |||
| 86 | static inline void gpt_irq_enable(void) | 86 | static inline void gpt_irq_enable(void) |
| 87 | { | 87 | { |
| 88 | if (timer_is_v2()) | 88 | if (timer_is_v2()) |
| 89 | __raw_writel(1<<0, timer_base + MX3_IR); | 89 | __raw_writel(1<<0, timer_base + V2_IR); |
| 90 | else { | 90 | else { |
| 91 | __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, | 91 | __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, |
| 92 | timer_base + MXC_TCTL); | 92 | timer_base + MXC_TCTL); |
| @@ -102,7 +102,7 @@ static void gpt_irq_acknowledge(void) | |||
| 102 | __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, | 102 | __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, |
| 103 | timer_base + MX1_2_TSTAT); | 103 | timer_base + MX1_2_TSTAT); |
| 104 | } else if (timer_is_v2()) | 104 | } else if (timer_is_v2()) |
| 105 | __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT); | 105 | __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); |
| 106 | } | 106 | } |
| 107 | 107 | ||
| 108 | static cycle_t mx1_2_get_cycles(struct clocksource *cs) | 108 | static cycle_t mx1_2_get_cycles(struct clocksource *cs) |
| @@ -110,9 +110,9 @@ static cycle_t mx1_2_get_cycles(struct clocksource *cs) | |||
| 110 | return __raw_readl(timer_base + MX1_2_TCN); | 110 | return __raw_readl(timer_base + MX1_2_TCN); |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | static cycle_t mx3_get_cycles(struct clocksource *cs) | 113 | static cycle_t v2_get_cycles(struct clocksource *cs) |
| 114 | { | 114 | { |
| 115 | return __raw_readl(timer_base + MX3_TCN); | 115 | return __raw_readl(timer_base + V2_TCN); |
| 116 | } | 116 | } |
| 117 | 117 | ||
| 118 | static struct clocksource clocksource_mxc = { | 118 | static struct clocksource clocksource_mxc = { |
| @@ -129,7 +129,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk) | |||
| 129 | unsigned int c = clk_get_rate(timer_clk); | 129 | unsigned int c = clk_get_rate(timer_clk); |
| 130 | 130 | ||
| 131 | if (timer_is_v2()) | 131 | if (timer_is_v2()) |
| 132 | clocksource_mxc.read = mx3_get_cycles; | 132 | clocksource_mxc.read = v2_get_cycles; |
| 133 | 133 | ||
| 134 | clocksource_mxc.mult = clocksource_hz2mult(c, | 134 | clocksource_mxc.mult = clocksource_hz2mult(c, |
| 135 | clocksource_mxc.shift); | 135 | clocksource_mxc.shift); |
| @@ -153,16 +153,16 @@ static int mx1_2_set_next_event(unsigned long evt, | |||
| 153 | -ETIME : 0; | 153 | -ETIME : 0; |
| 154 | } | 154 | } |
| 155 | 155 | ||
| 156 | static int mx3_set_next_event(unsigned long evt, | 156 | static int v2_set_next_event(unsigned long evt, |
| 157 | struct clock_event_device *unused) | 157 | struct clock_event_device *unused) |
| 158 | { | 158 | { |
| 159 | unsigned long tcmp; | 159 | unsigned long tcmp; |
| 160 | 160 | ||
| 161 | tcmp = __raw_readl(timer_base + MX3_TCN) + evt; | 161 | tcmp = __raw_readl(timer_base + V2_TCN) + evt; |
| 162 | 162 | ||
| 163 | __raw_writel(tcmp, timer_base + MX3_TCMP); | 163 | __raw_writel(tcmp, timer_base + V2_TCMP); |
| 164 | 164 | ||
| 165 | return (int)(tcmp - __raw_readl(timer_base + MX3_TCN)) < 0 ? | 165 | return (int)(tcmp - __raw_readl(timer_base + V2_TCN)) < 0 ? |
| 166 | -ETIME : 0; | 166 | -ETIME : 0; |
| 167 | } | 167 | } |
| 168 | 168 | ||
| @@ -192,8 +192,8 @@ static void mxc_set_mode(enum clock_event_mode mode, | |||
| 192 | if (mode != clockevent_mode) { | 192 | if (mode != clockevent_mode) { |
| 193 | /* Set event time into far-far future */ | 193 | /* Set event time into far-far future */ |
| 194 | if (timer_is_v2()) | 194 | if (timer_is_v2()) |
| 195 | __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3, | 195 | __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, |
| 196 | timer_base + MX3_TCMP); | 196 | timer_base + V2_TCMP); |
| 197 | else | 197 | else |
| 198 | __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, | 198 | __raw_writel(__raw_readl(timer_base + MX1_2_TCN) - 3, |
| 199 | timer_base + MX1_2_TCMP); | 199 | timer_base + MX1_2_TCMP); |
| @@ -245,7 +245,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id) | |||
| 245 | uint32_t tstat; | 245 | uint32_t tstat; |
| 246 | 246 | ||
| 247 | if (timer_is_v2()) | 247 | if (timer_is_v2()) |
| 248 | tstat = __raw_readl(timer_base + MX3_TSTAT); | 248 | tstat = __raw_readl(timer_base + V2_TSTAT); |
| 249 | else | 249 | else |
| 250 | tstat = __raw_readl(timer_base + MX1_2_TSTAT); | 250 | tstat = __raw_readl(timer_base + MX1_2_TSTAT); |
| 251 | 251 | ||
| @@ -276,7 +276,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk) | |||
| 276 | unsigned int c = clk_get_rate(timer_clk); | 276 | unsigned int c = clk_get_rate(timer_clk); |
| 277 | 277 | ||
| 278 | if (timer_is_v2()) | 278 | if (timer_is_v2()) |
| 279 | clockevent_mxc.set_next_event = mx3_set_next_event; | 279 | clockevent_mxc.set_next_event = v2_set_next_event; |
| 280 | 280 | ||
| 281 | clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, | 281 | clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, |
| 282 | clockevent_mxc.shift); | 282 | clockevent_mxc.shift); |
| @@ -308,7 +308,7 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq) | |||
| 308 | __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ | 308 | __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */ |
| 309 | 309 | ||
| 310 | if (timer_is_v2()) | 310 | if (timer_is_v2()) |
| 311 | tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN; | 311 | tctl_val = V2_TCTL_CLK_IPG | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN; |
| 312 | else | 312 | else |
| 313 | tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; | 313 | tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN; |
| 314 | 314 | ||
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index afa6709db0b3..9b86d2a60d43 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * | 3 | * |
| 4 | * The code contained herein is licensed under the GNU General Public | 4 | * The code contained herein is licensed under the GNU General Public |
| 5 | * License. You may obtain a copy of the GNU General Public License | 5 | * License. You may obtain a copy of the GNU General Public License |
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <asm/mach/irq.h> | 19 | #include <asm/mach/irq.h> |
| 20 | 20 | ||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 22 | #include <mach/common.h> | ||
| 22 | 23 | ||
| 23 | /* | 24 | /* |
| 24 | ***************************************** | 25 | ***************************************** |
| @@ -144,6 +145,7 @@ void __init tzic_init_irq(void __iomem *irqbase) | |||
| 144 | set_irq_handler(i, handle_level_irq); | 145 | set_irq_handler(i, handle_level_irq); |
| 145 | set_irq_flags(i, IRQF_VALID); | 146 | set_irq_flags(i, IRQF_VALID); |
| 146 | } | 147 | } |
| 148 | mxc_register_gpios(); | ||
| 147 | 149 | ||
| 148 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); | 150 | pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); |
| 149 | } | 151 | } |
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index 58583732b29a..452e18438b41 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c | |||
| @@ -234,32 +234,6 @@ void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd) | |||
| 234 | } | 234 | } |
| 235 | } | 235 | } |
| 236 | 236 | ||
| 237 | |||
| 238 | /* Watchdog */ | ||
| 239 | |||
| 240 | static struct resource s3c_wdt_resource[] = { | ||
| 241 | [0] = { | ||
| 242 | .start = S3C24XX_PA_WATCHDOG, | ||
| 243 | .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1, | ||
| 244 | .flags = IORESOURCE_MEM, | ||
| 245 | }, | ||
| 246 | [1] = { | ||
| 247 | .start = IRQ_WDT, | ||
| 248 | .end = IRQ_WDT, | ||
| 249 | .flags = IORESOURCE_IRQ, | ||
| 250 | } | ||
| 251 | |||
| 252 | }; | ||
| 253 | |||
| 254 | struct platform_device s3c_device_wdt = { | ||
| 255 | .name = "s3c2410-wdt", | ||
| 256 | .id = -1, | ||
| 257 | .num_resources = ARRAY_SIZE(s3c_wdt_resource), | ||
| 258 | .resource = s3c_wdt_resource, | ||
| 259 | }; | ||
| 260 | |||
| 261 | EXPORT_SYMBOL(s3c_device_wdt); | ||
| 262 | |||
| 263 | /* IIS */ | 237 | /* IIS */ |
| 264 | 238 | ||
| 265 | static struct resource s3c_iis_resource[] = { | 239 | static struct resource s3c_iis_resource[] = { |
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 92bd75607b43..5cb2dd1da632 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | 7 | ||
| 8 | config PLAT_S5P | 8 | config PLAT_S5P |
| 9 | bool | 9 | bool |
| 10 | depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210) | 10 | depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210) |
| 11 | default y | 11 | default y |
| 12 | select ARM_VIC | 12 | select ARM_VIC |
| 13 | select NO_IOPORT | 13 | select NO_IOPORT |
| @@ -24,3 +24,8 @@ config PLAT_S5P | |||
| 24 | select SAMSUNG_IRQ_UART | 24 | select SAMSUNG_IRQ_UART |
| 25 | help | 25 | help |
| 26 | Base platform code for Samsung's S5P series SoC. | 26 | Base platform code for Samsung's S5P series SoC. |
| 27 | |||
| 28 | config S5P_EXT_INT | ||
| 29 | bool | ||
| 30 | help | ||
| 31 | Use the external interrupts (other than GPIO interrupts.) | ||
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile index 0ec09a9c36bd..39c242bb9d58 100644 --- a/arch/arm/plat-s5p/Makefile +++ b/arch/arm/plat-s5p/Makefile | |||
| @@ -16,3 +16,5 @@ obj-y += dev-uart.o | |||
| 16 | obj-y += cpu.o | 16 | obj-y += cpu.o |
| 17 | obj-y += clock.o | 17 | obj-y += clock.o |
| 18 | obj-y += irq.o | 18 | obj-y += irq.o |
| 19 | obj-$(CONFIG_S5P_EXT_INT) += irq-eint.o | ||
| 20 | |||
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c index f92e5de3a755..75cb8c37ca2c 100644 --- a/arch/arm/plat-s5p/cpu.c +++ b/arch/arm/plat-s5p/cpu.c | |||
| @@ -19,12 +19,14 @@ | |||
| 19 | #include <plat/cpu.h> | 19 | #include <plat/cpu.h> |
| 20 | #include <plat/s5p6440.h> | 20 | #include <plat/s5p6440.h> |
| 21 | #include <plat/s5p6442.h> | 21 | #include <plat/s5p6442.h> |
| 22 | #include <plat/s5pc100.h> | ||
| 22 | #include <plat/s5pv210.h> | 23 | #include <plat/s5pv210.h> |
| 23 | 24 | ||
| 24 | /* table of supported CPUs */ | 25 | /* table of supported CPUs */ |
| 25 | 26 | ||
| 26 | static const char name_s5p6440[] = "S5P6440"; | 27 | static const char name_s5p6440[] = "S5P6440"; |
| 27 | static const char name_s5p6442[] = "S5P6442"; | 28 | static const char name_s5p6442[] = "S5P6442"; |
| 29 | static const char name_s5pc100[] = "S5PC100"; | ||
| 28 | static const char name_s5pv210[] = "S5PV210/S5PC110"; | 30 | static const char name_s5pv210[] = "S5PV210/S5PC110"; |
| 29 | 31 | ||
| 30 | static struct cpu_table cpu_ids[] __initdata = { | 32 | static struct cpu_table cpu_ids[] __initdata = { |
| @@ -45,6 +47,14 @@ static struct cpu_table cpu_ids[] __initdata = { | |||
| 45 | .init = s5p6442_init, | 47 | .init = s5p6442_init, |
| 46 | .name = name_s5p6442, | 48 | .name = name_s5p6442, |
| 47 | }, { | 49 | }, { |
| 50 | .idcode = 0x43100000, | ||
| 51 | .idmask = 0xfffff000, | ||
| 52 | .map_io = s5pc100_map_io, | ||
| 53 | .init_clocks = s5pc100_init_clocks, | ||
| 54 | .init_uarts = s5pc100_init_uarts, | ||
| 55 | .init = s5pc100_init, | ||
| 56 | .name = name_s5pc100, | ||
| 57 | }, { | ||
| 48 | .idcode = 0x43110000, | 58 | .idcode = 0x43110000, |
| 49 | .idmask = 0xfffff000, | 59 | .idmask = 0xfffff000, |
| 50 | .map_io = s5pv210_map_io, | 60 | .map_io = s5pv210_map_io, |
diff --git a/arch/arm/plat-s5p/include/plat/s5pc100.h b/arch/arm/plat-s5p/include/plat/s5pc100.h new file mode 100644 index 000000000000..5f6099dd7cad --- /dev/null +++ b/arch/arm/plat-s5p/include/plat/s5pc100.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* arch/arm/plat-s5p/include/plat/s5pc100.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * Header file for s5pc100 cpu support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | /* Common init code for S5PC100 related SoCs */ | ||
| 14 | |||
| 15 | extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
| 16 | extern void s5pc100_register_clocks(void); | ||
| 17 | extern void s5pc100_setup_clocks(void); | ||
| 18 | |||
| 19 | #ifdef CONFIG_CPU_S5PC100 | ||
| 20 | |||
| 21 | extern int s5pc100_init(void); | ||
| 22 | extern void s5pc100_init_irq(void); | ||
| 23 | extern void s5pc100_map_io(void); | ||
| 24 | extern void s5pc100_init_clocks(int xtal); | ||
| 25 | |||
| 26 | #define s5pc100_init_uarts s5pc100_common_init_uarts | ||
| 27 | |||
| 28 | #else | ||
| 29 | #define s5pc100_init_clocks NULL | ||
| 30 | #define s5pc100_init_uarts NULL | ||
| 31 | #define s5pc100_map_io NULL | ||
| 32 | #define s5pc100_init NULL | ||
| 33 | #endif | ||
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c new file mode 100644 index 000000000000..eaa70aa0127b --- /dev/null +++ b/arch/arm/plat-s5p/irq-eint.c | |||
| @@ -0,0 +1,213 @@ | |||
| 1 | /* linux/arch/arm/plat-s5p/irq-eint.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com | ||
| 5 | * | ||
| 6 | * S5P - IRQ EINT support | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/interrupt.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/sysdev.h> | ||
| 18 | #include <linux/gpio.h> | ||
| 19 | |||
| 20 | #include <asm/hardware/vic.h> | ||
| 21 | |||
| 22 | #include <plat/regs-irqtype.h> | ||
| 23 | |||
| 24 | #include <mach/map.h> | ||
| 25 | #include <plat/cpu.h> | ||
| 26 | #include <plat/pm.h> | ||
| 27 | |||
| 28 | #include <plat/gpio-cfg.h> | ||
| 29 | #include <mach/regs-gpio.h> | ||
| 30 | |||
| 31 | static inline void s5p_irq_eint_mask(unsigned int irq) | ||
| 32 | { | ||
| 33 | u32 mask; | ||
| 34 | |||
| 35 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| 36 | mask |= eint_irq_to_bit(irq); | ||
| 37 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| 38 | } | ||
| 39 | |||
| 40 | static void s5p_irq_eint_unmask(unsigned int irq) | ||
| 41 | { | ||
| 42 | u32 mask; | ||
| 43 | |||
| 44 | mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| 45 | mask &= ~(eint_irq_to_bit(irq)); | ||
| 46 | __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); | ||
| 47 | } | ||
| 48 | |||
| 49 | static inline void s5p_irq_eint_ack(unsigned int irq) | ||
| 50 | { | ||
| 51 | __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); | ||
| 52 | } | ||
| 53 | |||
| 54 | static void s5p_irq_eint_maskack(unsigned int irq) | ||
| 55 | { | ||
| 56 | /* compiler should in-line these */ | ||
| 57 | s5p_irq_eint_mask(irq); | ||
| 58 | s5p_irq_eint_ack(irq); | ||
| 59 | } | ||
| 60 | |||
| 61 | static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) | ||
| 62 | { | ||
| 63 | int offs = eint_offset(irq); | ||
| 64 | int shift; | ||
| 65 | u32 ctrl, mask; | ||
| 66 | u32 newvalue = 0; | ||
| 67 | |||
| 68 | switch (type) { | ||
| 69 | case IRQ_TYPE_EDGE_RISING: | ||
| 70 | newvalue = S5P_EXTINT_RISEEDGE; | ||
| 71 | break; | ||
| 72 | |||
| 73 | case IRQ_TYPE_EDGE_FALLING: | ||
| 74 | newvalue = S5P_EXTINT_RISEEDGE; | ||
| 75 | break; | ||
| 76 | |||
| 77 | case IRQ_TYPE_EDGE_BOTH: | ||
| 78 | newvalue = S5P_EXTINT_BOTHEDGE; | ||
| 79 | break; | ||
| 80 | |||
| 81 | case IRQ_TYPE_LEVEL_LOW: | ||
| 82 | newvalue = S5P_EXTINT_LOWLEV; | ||
| 83 | break; | ||
| 84 | |||
| 85 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 86 | newvalue = S5P_EXTINT_HILEV; | ||
| 87 | break; | ||
| 88 | |||
| 89 | default: | ||
| 90 | printk(KERN_ERR "No such irq type %d", type); | ||
| 91 | return -EINVAL; | ||
| 92 | } | ||
| 93 | |||
| 94 | shift = (offs & 0x7) * 4; | ||
| 95 | mask = 0x7 << shift; | ||
| 96 | |||
| 97 | ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); | ||
| 98 | ctrl &= ~mask; | ||
| 99 | ctrl |= newvalue << shift; | ||
| 100 | __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); | ||
| 101 | |||
| 102 | if ((0 <= offs) && (offs < 8)) | ||
| 103 | s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); | ||
| 104 | |||
| 105 | else if ((8 <= offs) && (offs < 16)) | ||
| 106 | s3c_gpio_cfgpin(EINT_GPIO_1(offs & 0x7), EINT_MODE); | ||
| 107 | |||
| 108 | else if ((16 <= offs) && (offs < 24)) | ||
| 109 | s3c_gpio_cfgpin(EINT_GPIO_2(offs & 0x7), EINT_MODE); | ||
| 110 | |||
| 111 | else if ((24 <= offs) && (offs < 32)) | ||
| 112 | s3c_gpio_cfgpin(EINT_GPIO_3(offs & 0x7), EINT_MODE); | ||
| 113 | |||
| 114 | else | ||
| 115 | printk(KERN_ERR "No such irq number %d", offs); | ||
| 116 | |||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | static struct irq_chip s5p_irq_eint = { | ||
| 121 | .name = "s5p-eint", | ||
| 122 | .mask = s5p_irq_eint_mask, | ||
| 123 | .unmask = s5p_irq_eint_unmask, | ||
| 124 | .mask_ack = s5p_irq_eint_maskack, | ||
| 125 | .ack = s5p_irq_eint_ack, | ||
| 126 | .set_type = s5p_irq_eint_set_type, | ||
| 127 | #ifdef CONFIG_PM | ||
| 128 | .set_wake = s3c_irqext_wake, | ||
| 129 | #endif | ||
| 130 | }; | ||
| 131 | |||
| 132 | /* s5p_irq_demux_eint | ||
| 133 | * | ||
| 134 | * This function demuxes the IRQ from the group0 external interrupts, | ||
| 135 | * from EINTs 16 to 31. It is designed to be inlined into the specific | ||
| 136 | * handler s5p_irq_demux_eintX_Y. | ||
| 137 | * | ||
| 138 | * Each EINT pend/mask registers handle eight of them. | ||
| 139 | */ | ||
| 140 | static inline void s5p_irq_demux_eint(unsigned int start) | ||
| 141 | { | ||
| 142 | u32 status; | ||
| 143 | u32 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(start))); | ||
| 144 | unsigned int irq; | ||
| 145 | |||
| 146 | status = __raw_readl(S5P_EINT_PEND(EINT_REG_NR(start))); | ||
| 147 | status &= ~mask; | ||
| 148 | status &= 0xff; | ||
| 149 | |||
| 150 | while (status) { | ||
| 151 | irq = fls(status); | ||
| 152 | generic_handle_irq(irq - 1 + start); | ||
| 153 | status &= ~(1 << irq); | ||
| 154 | } | ||
| 155 | } | ||
| 156 | |||
| 157 | static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | ||
| 158 | { | ||
| 159 | s5p_irq_demux_eint(IRQ_EINT(16)); | ||
| 160 | s5p_irq_demux_eint(IRQ_EINT(24)); | ||
| 161 | } | ||
| 162 | |||
| 163 | static inline void s5p_irq_vic_eint_mask(unsigned int irq) | ||
| 164 | { | ||
| 165 | s5p_irq_eint_mask(irq); | ||
| 166 | } | ||
| 167 | |||
| 168 | static void s5p_irq_vic_eint_unmask(unsigned int irq) | ||
| 169 | { | ||
| 170 | s5p_irq_eint_unmask(irq); | ||
| 171 | } | ||
| 172 | |||
| 173 | static inline void s5p_irq_vic_eint_ack(unsigned int irq) | ||
| 174 | { | ||
| 175 | __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); | ||
| 176 | } | ||
| 177 | |||
| 178 | static void s5p_irq_vic_eint_maskack(unsigned int irq) | ||
| 179 | { | ||
| 180 | s5p_irq_vic_eint_mask(irq); | ||
| 181 | s5p_irq_vic_eint_ack(irq); | ||
| 182 | } | ||
| 183 | |||
| 184 | static struct irq_chip s5p_irq_vic_eint = { | ||
| 185 | .name = "s5p_vic_eint", | ||
| 186 | .mask = s5p_irq_vic_eint_mask, | ||
| 187 | .unmask = s5p_irq_vic_eint_unmask, | ||
| 188 | .mask_ack = s5p_irq_vic_eint_maskack, | ||
| 189 | .ack = s5p_irq_vic_eint_ack, | ||
| 190 | .set_type = s5p_irq_eint_set_type, | ||
| 191 | #ifdef CONFIG_PM | ||
| 192 | .set_wake = s3c_irqext_wake, | ||
| 193 | #endif | ||
| 194 | }; | ||
| 195 | |||
| 196 | int __init s5p_init_irq_eint(void) | ||
| 197 | { | ||
| 198 | int irq; | ||
| 199 | |||
| 200 | for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) | ||
| 201 | set_irq_chip(irq, &s5p_irq_vic_eint); | ||
| 202 | |||
| 203 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | ||
| 204 | set_irq_chip(irq, &s5p_irq_eint); | ||
| 205 | set_irq_handler(irq, handle_level_irq); | ||
| 206 | set_irq_flags(irq, IRQF_VALID); | ||
| 207 | } | ||
| 208 | |||
| 209 | set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); | ||
| 210 | return 0; | ||
| 211 | } | ||
| 212 | |||
| 213 | arch_initcall(s5p_init_irq_eint); | ||
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig deleted file mode 100644 index c7bd2bbda239..000000000000 --- a/arch/arm/plat-s5pc1xx/Kconfig +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | # Copyright 2009 Samsung Electronics Co. | ||
| 2 | # Byungho Min <bhmin@samsung.com> | ||
| 3 | # | ||
| 4 | # Licensed under GPLv2 | ||
| 5 | |||
| 6 | config PLAT_S5PC1XX | ||
| 7 | bool | ||
| 8 | depends on ARCH_S5PC1XX | ||
| 9 | default y | ||
| 10 | select PLAT_S3C | ||
| 11 | select ARM_VIC | ||
| 12 | select NO_IOPORT | ||
| 13 | select ARCH_REQUIRE_GPIOLIB | ||
| 14 | select SAMSUNG_CLKSRC | ||
| 15 | select SAMSUNG_IRQ_UART | ||
| 16 | select SAMSUNG_IRQ_VIC_TIMER | ||
| 17 | select S3C_GPIO_TRACK | ||
| 18 | select S3C_GPIO_PULL_UPDOWN | ||
| 19 | select S5P_GPIO_DRVSTR | ||
| 20 | select S3C_GPIO_CFG_S3C24XX | ||
| 21 | select S3C_GPIO_CFG_S3C64XX | ||
| 22 | select SAMSUNG_GPIOLIB_4BIT | ||
| 23 | help | ||
| 24 | Base platform code for any Samsung S5PC1XX device | ||
| 25 | |||
| 26 | if PLAT_S5PC1XX | ||
| 27 | |||
| 28 | # Configuration options shared by all S3C64XX implementations | ||
| 29 | |||
| 30 | config CPU_S5PC100_INIT | ||
| 31 | bool | ||
| 32 | help | ||
| 33 | Common initialisation code for the S5PC1XX | ||
| 34 | |||
| 35 | config CPU_S5PC100_CLOCK | ||
| 36 | bool | ||
| 37 | help | ||
| 38 | Common clock support code for the S5PC1XX | ||
| 39 | |||
| 40 | # platform specific device setup | ||
| 41 | |||
| 42 | config S5PC1XX_SETUP_SDHCI_GPIO | ||
| 43 | bool | ||
| 44 | help | ||
| 45 | Common setup code for SDHCI gpio. | ||
| 46 | |||
| 47 | endif | ||
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile deleted file mode 100644 index 9ce6409a9e02..000000000000 --- a/arch/arm/plat-s5pc1xx/Makefile +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | # arch/arm/plat-s5pc1xx/Makefile | ||
| 2 | # | ||
| 3 | # Copyright 2009 Samsung Electronics Co. | ||
| 4 | # | ||
| 5 | # Licensed under GPLv2 | ||
| 6 | |||
| 7 | obj-y := | ||
| 8 | obj-m := | ||
| 9 | obj-n := dummy.o | ||
| 10 | obj- := | ||
| 11 | |||
| 12 | # Core files | ||
| 13 | |||
| 14 | obj-y += dev-uart.o | ||
| 15 | obj-y += cpu.o | ||
| 16 | obj-y += irq.o | ||
| 17 | obj-y += clock.o | ||
| 18 | |||
| 19 | # CPU support | ||
| 20 | |||
| 21 | obj-$(CONFIG_CPU_S5PC100_INIT) += s5pc100-init.o | ||
| 22 | obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o | ||
| 23 | |||
| 24 | # Device setup | ||
| 25 | |||
| 26 | obj-$(CONFIG_S5PC1XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | ||
diff --git a/arch/arm/plat-s5pc1xx/clock.c b/arch/arm/plat-s5pc1xx/clock.c deleted file mode 100644 index 387f23190c3c..000000000000 --- a/arch/arm/plat-s5pc1xx/clock.c +++ /dev/null | |||
| @@ -1,709 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/clock.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * | ||
| 5 | * S5PC1XX Base clock support | ||
| 6 | * | ||
| 7 | * Based on plat-s3c64xx/clock.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/ioport.h> | ||
| 18 | #include <linux/clk.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <mach/map.h> | ||
| 23 | |||
| 24 | #include <plat/regs-clock.h> | ||
| 25 | #include <plat/devs.h> | ||
| 26 | #include <plat/clock.h> | ||
| 27 | |||
| 28 | struct clk clk_27m = { | ||
| 29 | .name = "clk_27m", | ||
| 30 | .id = -1, | ||
| 31 | .rate = 27000000, | ||
| 32 | }; | ||
| 33 | |||
| 34 | static int clk_48m_ctrl(struct clk *clk, int enable) | ||
| 35 | { | ||
| 36 | unsigned long flags; | ||
| 37 | u32 val; | ||
| 38 | |||
| 39 | /* can't rely on clock lock, this register has other usages */ | ||
| 40 | local_irq_save(flags); | ||
| 41 | |||
| 42 | val = __raw_readl(S5PC100_CLKSRC1); | ||
| 43 | if (enable) | ||
| 44 | val |= S5PC100_CLKSRC1_CLK48M_MASK; | ||
| 45 | else | ||
| 46 | val &= ~S5PC100_CLKSRC1_CLK48M_MASK; | ||
| 47 | |||
| 48 | __raw_writel(val, S5PC100_CLKSRC1); | ||
| 49 | local_irq_restore(flags); | ||
| 50 | |||
| 51 | return 0; | ||
| 52 | } | ||
| 53 | |||
| 54 | struct clk clk_48m = { | ||
| 55 | .name = "clk_48m", | ||
| 56 | .id = -1, | ||
| 57 | .rate = 48000000, | ||
| 58 | .enable = clk_48m_ctrl, | ||
| 59 | }; | ||
| 60 | |||
| 61 | struct clk clk_54m = { | ||
| 62 | .name = "clk_54m", | ||
| 63 | .id = -1, | ||
| 64 | .rate = 54000000, | ||
| 65 | }; | ||
| 66 | |||
| 67 | struct clk clk_hd0 = { | ||
| 68 | .name = "hclkd0", | ||
| 69 | .id = -1, | ||
| 70 | .rate = 0, | ||
| 71 | .parent = NULL, | ||
| 72 | .ctrlbit = 0, | ||
| 73 | .ops = &clk_ops_def_setrate, | ||
| 74 | }; | ||
| 75 | |||
| 76 | struct clk clk_pd0 = { | ||
| 77 | .name = "pclkd0", | ||
| 78 | .id = -1, | ||
| 79 | .rate = 0, | ||
| 80 | .parent = NULL, | ||
| 81 | .ctrlbit = 0, | ||
| 82 | .ops = &clk_ops_def_setrate, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable) | ||
| 86 | { | ||
| 87 | unsigned int ctrlbit = clk->ctrlbit; | ||
| 88 | u32 con; | ||
| 89 | |||
| 90 | con = __raw_readl(reg); | ||
| 91 | if (enable) | ||
| 92 | con |= ctrlbit; | ||
| 93 | else | ||
| 94 | con &= ~ctrlbit; | ||
| 95 | __raw_writel(con, reg); | ||
| 96 | |||
| 97 | return 0; | ||
| 98 | } | ||
| 99 | |||
| 100 | static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable) | ||
| 101 | { | ||
| 102 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable); | ||
| 103 | } | ||
| 104 | |||
| 105 | static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable) | ||
| 106 | { | ||
| 107 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable); | ||
| 108 | } | ||
| 109 | |||
| 110 | static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable) | ||
| 111 | { | ||
| 112 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable); | ||
| 113 | } | ||
| 114 | |||
| 115 | static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable) | ||
| 116 | { | ||
| 117 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable); | ||
| 118 | } | ||
| 119 | |||
| 120 | static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable) | ||
| 121 | { | ||
| 122 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable); | ||
| 123 | } | ||
| 124 | |||
| 125 | static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable) | ||
| 126 | { | ||
| 127 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable); | ||
| 128 | } | ||
| 129 | |||
| 130 | static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable) | ||
| 131 | { | ||
| 132 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable); | ||
| 133 | } | ||
| 134 | |||
| 135 | static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable) | ||
| 136 | { | ||
| 137 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable); | ||
| 138 | } | ||
| 139 | |||
| 140 | static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable) | ||
| 141 | { | ||
| 142 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable); | ||
| 143 | } | ||
| 144 | |||
| 145 | static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable) | ||
| 146 | { | ||
| 147 | return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable); | ||
| 148 | } | ||
| 149 | |||
| 150 | int s5pc100_sclk0_ctrl(struct clk *clk, int enable) | ||
| 151 | { | ||
| 152 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable); | ||
| 153 | } | ||
| 154 | |||
| 155 | int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | ||
| 156 | { | ||
| 157 | return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable); | ||
| 158 | } | ||
| 159 | |||
| 160 | static struct clk s5pc100_init_clocks_disable[] = { | ||
| 161 | { | ||
| 162 | .name = "dsi", | ||
| 163 | .id = -1, | ||
| 164 | .parent = &clk_p, | ||
| 165 | .enable = s5pc100_clk_d11_ctrl, | ||
| 166 | .ctrlbit = S5PC100_CLKGATE_D11_DSI, | ||
| 167 | }, { | ||
| 168 | .name = "csi", | ||
| 169 | .id = -1, | ||
| 170 | .parent = &clk_h, | ||
| 171 | .enable = s5pc100_clk_d11_ctrl, | ||
| 172 | .ctrlbit = S5PC100_CLKGATE_D11_CSI, | ||
| 173 | }, { | ||
| 174 | .name = "ccan", | ||
| 175 | .id = 0, | ||
| 176 | .parent = &clk_p, | ||
| 177 | .enable = s5pc100_clk_d14_ctrl, | ||
| 178 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN0, | ||
| 179 | }, { | ||
| 180 | .name = "ccan", | ||
| 181 | .id = 1, | ||
| 182 | .parent = &clk_p, | ||
| 183 | .enable = s5pc100_clk_d14_ctrl, | ||
| 184 | .ctrlbit = S5PC100_CLKGATE_D14_CCAN1, | ||
| 185 | }, { | ||
| 186 | .name = "keypad", | ||
| 187 | .id = -1, | ||
| 188 | .parent = &clk_p, | ||
| 189 | .enable = s5pc100_clk_d15_ctrl, | ||
| 190 | .ctrlbit = S5PC100_CLKGATE_D15_KEYIF, | ||
| 191 | }, { | ||
| 192 | .name = "hclkd2", | ||
| 193 | .id = -1, | ||
| 194 | .parent = NULL, | ||
| 195 | .enable = s5pc100_clk_d20_ctrl, | ||
| 196 | .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2, | ||
| 197 | }, { | ||
| 198 | .name = "iis-d2", | ||
| 199 | .id = -1, | ||
| 200 | .parent = NULL, | ||
| 201 | .enable = s5pc100_clk_d20_ctrl, | ||
| 202 | .ctrlbit = S5PC100_CLKGATE_D20_I2SD2, | ||
| 203 | }, | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct clk s5pc100_init_clocks[] = { | ||
| 207 | /* System1 (D0_0) devices */ | ||
| 208 | { | ||
| 209 | .name = "intc", | ||
| 210 | .id = -1, | ||
| 211 | .parent = &clk_hd0, | ||
| 212 | .enable = s5pc100_clk_d00_ctrl, | ||
| 213 | .ctrlbit = S5PC100_CLKGATE_D00_INTC, | ||
| 214 | }, { | ||
| 215 | .name = "tzic", | ||
| 216 | .id = -1, | ||
| 217 | .parent = &clk_hd0, | ||
| 218 | .enable = s5pc100_clk_d00_ctrl, | ||
| 219 | .ctrlbit = S5PC100_CLKGATE_D00_TZIC, | ||
| 220 | }, { | ||
| 221 | .name = "cf-ata", | ||
| 222 | .id = -1, | ||
| 223 | .parent = &clk_hd0, | ||
| 224 | .enable = s5pc100_clk_d00_ctrl, | ||
| 225 | .ctrlbit = S5PC100_CLKGATE_D00_CFCON, | ||
| 226 | }, { | ||
| 227 | .name = "mdma", | ||
| 228 | .id = -1, | ||
| 229 | .parent = &clk_hd0, | ||
| 230 | .enable = s5pc100_clk_d00_ctrl, | ||
| 231 | .ctrlbit = S5PC100_CLKGATE_D00_MDMA, | ||
| 232 | }, { | ||
| 233 | .name = "g2d", | ||
| 234 | .id = -1, | ||
| 235 | .parent = &clk_hd0, | ||
| 236 | .enable = s5pc100_clk_d00_ctrl, | ||
| 237 | .ctrlbit = S5PC100_CLKGATE_D00_G2D, | ||
| 238 | }, { | ||
| 239 | .name = "secss", | ||
| 240 | .id = -1, | ||
| 241 | .parent = &clk_hd0, | ||
| 242 | .enable = s5pc100_clk_d00_ctrl, | ||
| 243 | .ctrlbit = S5PC100_CLKGATE_D00_SECSS, | ||
| 244 | }, { | ||
| 245 | .name = "cssys", | ||
| 246 | .id = -1, | ||
| 247 | .parent = &clk_hd0, | ||
| 248 | .enable = s5pc100_clk_d00_ctrl, | ||
| 249 | .ctrlbit = S5PC100_CLKGATE_D00_CSSYS, | ||
| 250 | }, | ||
| 251 | |||
| 252 | /* Memory (D0_1) devices */ | ||
| 253 | { | ||
| 254 | .name = "dmc", | ||
| 255 | .id = -1, | ||
| 256 | .parent = &clk_hd0, | ||
| 257 | .enable = s5pc100_clk_d01_ctrl, | ||
| 258 | .ctrlbit = S5PC100_CLKGATE_D01_DMC, | ||
| 259 | }, { | ||
| 260 | .name = "sromc", | ||
| 261 | .id = -1, | ||
| 262 | .parent = &clk_hd0, | ||
| 263 | .enable = s5pc100_clk_d01_ctrl, | ||
| 264 | .ctrlbit = S5PC100_CLKGATE_D01_SROMC, | ||
| 265 | }, { | ||
| 266 | .name = "onenand", | ||
| 267 | .id = -1, | ||
| 268 | .parent = &clk_hd0, | ||
| 269 | .enable = s5pc100_clk_d01_ctrl, | ||
| 270 | .ctrlbit = S5PC100_CLKGATE_D01_ONENAND, | ||
| 271 | }, { | ||
| 272 | .name = "nand", | ||
| 273 | .id = -1, | ||
| 274 | .parent = &clk_hd0, | ||
| 275 | .enable = s5pc100_clk_d01_ctrl, | ||
| 276 | .ctrlbit = S5PC100_CLKGATE_D01_NFCON, | ||
| 277 | }, { | ||
| 278 | .name = "intmem", | ||
| 279 | .id = -1, | ||
| 280 | .parent = &clk_hd0, | ||
| 281 | .enable = s5pc100_clk_d01_ctrl, | ||
| 282 | .ctrlbit = S5PC100_CLKGATE_D01_INTMEM, | ||
| 283 | }, { | ||
| 284 | .name = "ebi", | ||
| 285 | .id = -1, | ||
| 286 | .parent = &clk_hd0, | ||
| 287 | .enable = s5pc100_clk_d01_ctrl, | ||
| 288 | .ctrlbit = S5PC100_CLKGATE_D01_EBI, | ||
| 289 | }, | ||
| 290 | |||
| 291 | /* System2 (D0_2) devices */ | ||
| 292 | { | ||
| 293 | .name = "seckey", | ||
| 294 | .id = -1, | ||
| 295 | .parent = &clk_pd0, | ||
| 296 | .enable = s5pc100_clk_d02_ctrl, | ||
| 297 | .ctrlbit = S5PC100_CLKGATE_D02_SECKEY, | ||
| 298 | }, { | ||
| 299 | .name = "sdm", | ||
| 300 | .id = -1, | ||
| 301 | .parent = &clk_hd0, | ||
| 302 | .enable = s5pc100_clk_d02_ctrl, | ||
| 303 | .ctrlbit = S5PC100_CLKGATE_D02_SDM, | ||
| 304 | }, | ||
| 305 | |||
| 306 | /* File (D1_0) devices */ | ||
| 307 | { | ||
| 308 | .name = "pdma", | ||
| 309 | .id = 0, | ||
| 310 | .parent = &clk_h, | ||
| 311 | .enable = s5pc100_clk_d10_ctrl, | ||
| 312 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA0, | ||
| 313 | }, { | ||
| 314 | .name = "pdma", | ||
| 315 | .id = 1, | ||
| 316 | .parent = &clk_h, | ||
| 317 | .enable = s5pc100_clk_d10_ctrl, | ||
| 318 | .ctrlbit = S5PC100_CLKGATE_D10_PDMA1, | ||
| 319 | }, { | ||
| 320 | .name = "usb-host", | ||
| 321 | .id = -1, | ||
| 322 | .parent = &clk_h, | ||
| 323 | .enable = s5pc100_clk_d10_ctrl, | ||
| 324 | .ctrlbit = S5PC100_CLKGATE_D10_USBHOST, | ||
| 325 | }, { | ||
| 326 | .name = "otg", | ||
| 327 | .id = -1, | ||
| 328 | .parent = &clk_h, | ||
| 329 | .enable = s5pc100_clk_d10_ctrl, | ||
| 330 | .ctrlbit = S5PC100_CLKGATE_D10_USBOTG, | ||
| 331 | }, { | ||
| 332 | .name = "modem", | ||
| 333 | .id = -1, | ||
| 334 | .parent = &clk_h, | ||
| 335 | .enable = s5pc100_clk_d10_ctrl, | ||
| 336 | .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF, | ||
| 337 | }, { | ||
| 338 | .name = "hsmmc", | ||
| 339 | .id = 0, | ||
| 340 | .parent = &clk_48m, | ||
| 341 | .enable = s5pc100_clk_d10_ctrl, | ||
| 342 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0, | ||
| 343 | }, { | ||
| 344 | .name = "hsmmc", | ||
| 345 | .id = 1, | ||
| 346 | .parent = &clk_48m, | ||
| 347 | .enable = s5pc100_clk_d10_ctrl, | ||
| 348 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1, | ||
| 349 | }, { | ||
| 350 | .name = "hsmmc", | ||
| 351 | .id = 2, | ||
| 352 | .parent = &clk_48m, | ||
| 353 | .enable = s5pc100_clk_d10_ctrl, | ||
| 354 | .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2, | ||
| 355 | }, | ||
| 356 | |||
| 357 | /* Multimedia1 (D1_1) devices */ | ||
| 358 | { | ||
| 359 | .name = "lcd", | ||
| 360 | .id = -1, | ||
| 361 | .parent = &clk_p, | ||
| 362 | .enable = s5pc100_clk_d11_ctrl, | ||
| 363 | .ctrlbit = S5PC100_CLKGATE_D11_LCD, | ||
| 364 | }, { | ||
| 365 | .name = "rotator", | ||
| 366 | .id = -1, | ||
| 367 | .parent = &clk_p, | ||
| 368 | .enable = s5pc100_clk_d11_ctrl, | ||
| 369 | .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR, | ||
| 370 | }, { | ||
| 371 | .name = "fimc", | ||
| 372 | .id = -1, | ||
| 373 | .parent = &clk_p, | ||
| 374 | .enable = s5pc100_clk_d11_ctrl, | ||
| 375 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC0, | ||
| 376 | }, { | ||
| 377 | .name = "fimc", | ||
| 378 | .id = -1, | ||
| 379 | .parent = &clk_p, | ||
| 380 | .enable = s5pc100_clk_d11_ctrl, | ||
| 381 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC1, | ||
| 382 | }, { | ||
| 383 | .name = "fimc", | ||
| 384 | .id = -1, | ||
| 385 | .parent = &clk_p, | ||
| 386 | .enable = s5pc100_clk_d11_ctrl, | ||
| 387 | .ctrlbit = S5PC100_CLKGATE_D11_FIMC2, | ||
| 388 | }, { | ||
| 389 | .name = "jpeg", | ||
| 390 | .id = -1, | ||
| 391 | .parent = &clk_p, | ||
| 392 | .enable = s5pc100_clk_d11_ctrl, | ||
| 393 | .ctrlbit = S5PC100_CLKGATE_D11_JPEG, | ||
| 394 | }, { | ||
| 395 | .name = "g3d", | ||
| 396 | .id = -1, | ||
| 397 | .parent = &clk_p, | ||
| 398 | .enable = s5pc100_clk_d11_ctrl, | ||
| 399 | .ctrlbit = S5PC100_CLKGATE_D11_G3D, | ||
| 400 | }, | ||
| 401 | |||
| 402 | /* Multimedia2 (D1_2) devices */ | ||
| 403 | { | ||
| 404 | .name = "tv", | ||
| 405 | .id = -1, | ||
| 406 | .parent = &clk_p, | ||
| 407 | .enable = s5pc100_clk_d12_ctrl, | ||
| 408 | .ctrlbit = S5PC100_CLKGATE_D12_TV, | ||
| 409 | }, { | ||
| 410 | .name = "vp", | ||
| 411 | .id = -1, | ||
| 412 | .parent = &clk_p, | ||
| 413 | .enable = s5pc100_clk_d12_ctrl, | ||
| 414 | .ctrlbit = S5PC100_CLKGATE_D12_VP, | ||
| 415 | }, { | ||
| 416 | .name = "mixer", | ||
| 417 | .id = -1, | ||
| 418 | .parent = &clk_p, | ||
| 419 | .enable = s5pc100_clk_d12_ctrl, | ||
| 420 | .ctrlbit = S5PC100_CLKGATE_D12_MIXER, | ||
| 421 | }, { | ||
| 422 | .name = "hdmi", | ||
| 423 | .id = -1, | ||
| 424 | .parent = &clk_p, | ||
| 425 | .enable = s5pc100_clk_d12_ctrl, | ||
| 426 | .ctrlbit = S5PC100_CLKGATE_D12_HDMI, | ||
| 427 | }, { | ||
| 428 | .name = "mfc", | ||
| 429 | .id = -1, | ||
| 430 | .parent = &clk_p, | ||
| 431 | .enable = s5pc100_clk_d12_ctrl, | ||
| 432 | .ctrlbit = S5PC100_CLKGATE_D12_MFC, | ||
| 433 | }, | ||
| 434 | |||
| 435 | /* System (D1_3) devices */ | ||
| 436 | { | ||
| 437 | .name = "chipid", | ||
| 438 | .id = -1, | ||
| 439 | .parent = &clk_p, | ||
| 440 | .enable = s5pc100_clk_d13_ctrl, | ||
| 441 | .ctrlbit = S5PC100_CLKGATE_D13_CHIPID, | ||
| 442 | }, { | ||
| 443 | .name = "gpio", | ||
| 444 | .id = -1, | ||
| 445 | .parent = &clk_p, | ||
| 446 | .enable = s5pc100_clk_d13_ctrl, | ||
| 447 | .ctrlbit = S5PC100_CLKGATE_D13_GPIO, | ||
| 448 | }, { | ||
| 449 | .name = "apc", | ||
| 450 | .id = -1, | ||
| 451 | .parent = &clk_p, | ||
| 452 | .enable = s5pc100_clk_d13_ctrl, | ||
| 453 | .ctrlbit = S5PC100_CLKGATE_D13_APC, | ||
| 454 | }, { | ||
| 455 | .name = "iec", | ||
| 456 | .id = -1, | ||
| 457 | .parent = &clk_p, | ||
| 458 | .enable = s5pc100_clk_d13_ctrl, | ||
| 459 | .ctrlbit = S5PC100_CLKGATE_D13_IEC, | ||
| 460 | }, { | ||
| 461 | .name = "timers", | ||
| 462 | .id = -1, | ||
| 463 | .parent = &clk_p, | ||
| 464 | .enable = s5pc100_clk_d13_ctrl, | ||
| 465 | .ctrlbit = S5PC100_CLKGATE_D13_PWM, | ||
| 466 | }, { | ||
| 467 | .name = "systimer", | ||
| 468 | .id = -1, | ||
| 469 | .parent = &clk_p, | ||
| 470 | .enable = s5pc100_clk_d13_ctrl, | ||
| 471 | .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER, | ||
| 472 | }, { | ||
| 473 | .name = "watchdog", | ||
| 474 | .id = -1, | ||
| 475 | .parent = &clk_p, | ||
| 476 | .enable = s5pc100_clk_d13_ctrl, | ||
| 477 | .ctrlbit = S5PC100_CLKGATE_D13_WDT, | ||
| 478 | }, { | ||
| 479 | .name = "rtc", | ||
| 480 | .id = -1, | ||
| 481 | .parent = &clk_p, | ||
| 482 | .enable = s5pc100_clk_d13_ctrl, | ||
| 483 | .ctrlbit = S5PC100_CLKGATE_D13_RTC, | ||
| 484 | }, | ||
| 485 | |||
| 486 | /* Connectivity (D1_4) devices */ | ||
| 487 | { | ||
| 488 | .name = "uart", | ||
| 489 | .id = 0, | ||
| 490 | .parent = &clk_p, | ||
| 491 | .enable = s5pc100_clk_d14_ctrl, | ||
| 492 | .ctrlbit = S5PC100_CLKGATE_D14_UART0, | ||
| 493 | }, { | ||
| 494 | .name = "uart", | ||
| 495 | .id = 1, | ||
| 496 | .parent = &clk_p, | ||
| 497 | .enable = s5pc100_clk_d14_ctrl, | ||
| 498 | .ctrlbit = S5PC100_CLKGATE_D14_UART1, | ||
| 499 | }, { | ||
| 500 | .name = "uart", | ||
| 501 | .id = 2, | ||
| 502 | .parent = &clk_p, | ||
| 503 | .enable = s5pc100_clk_d14_ctrl, | ||
| 504 | .ctrlbit = S5PC100_CLKGATE_D14_UART2, | ||
| 505 | }, { | ||
| 506 | .name = "uart", | ||
| 507 | .id = 3, | ||
| 508 | .parent = &clk_p, | ||
| 509 | .enable = s5pc100_clk_d14_ctrl, | ||
| 510 | .ctrlbit = S5PC100_CLKGATE_D14_UART3, | ||
| 511 | }, { | ||
| 512 | .name = "i2c", | ||
| 513 | .id = -1, | ||
| 514 | .parent = &clk_p, | ||
| 515 | .enable = s5pc100_clk_d14_ctrl, | ||
| 516 | .ctrlbit = S5PC100_CLKGATE_D14_IIC, | ||
| 517 | }, { | ||
| 518 | .name = "hdmi-i2c", | ||
| 519 | .id = -1, | ||
| 520 | .parent = &clk_p, | ||
| 521 | .enable = s5pc100_clk_d14_ctrl, | ||
| 522 | .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC, | ||
| 523 | }, { | ||
| 524 | .name = "spi", | ||
| 525 | .id = 0, | ||
| 526 | .parent = &clk_p, | ||
| 527 | .enable = s5pc100_clk_d14_ctrl, | ||
| 528 | .ctrlbit = S5PC100_CLKGATE_D14_SPI0, | ||
| 529 | }, { | ||
| 530 | .name = "spi", | ||
| 531 | .id = 1, | ||
| 532 | .parent = &clk_p, | ||
| 533 | .enable = s5pc100_clk_d14_ctrl, | ||
| 534 | .ctrlbit = S5PC100_CLKGATE_D14_SPI1, | ||
| 535 | }, { | ||
| 536 | .name = "spi", | ||
| 537 | .id = 2, | ||
| 538 | .parent = &clk_p, | ||
| 539 | .enable = s5pc100_clk_d14_ctrl, | ||
| 540 | .ctrlbit = S5PC100_CLKGATE_D14_SPI2, | ||
| 541 | }, { | ||
| 542 | .name = "irda", | ||
| 543 | .id = -1, | ||
| 544 | .parent = &clk_p, | ||
| 545 | .enable = s5pc100_clk_d14_ctrl, | ||
| 546 | .ctrlbit = S5PC100_CLKGATE_D14_IRDA, | ||
| 547 | }, { | ||
| 548 | .name = "hsitx", | ||
| 549 | .id = -1, | ||
| 550 | .parent = &clk_p, | ||
| 551 | .enable = s5pc100_clk_d14_ctrl, | ||
| 552 | .ctrlbit = S5PC100_CLKGATE_D14_HSITX, | ||
| 553 | }, { | ||
| 554 | .name = "hsirx", | ||
| 555 | .id = -1, | ||
| 556 | .parent = &clk_p, | ||
| 557 | .enable = s5pc100_clk_d14_ctrl, | ||
| 558 | .ctrlbit = S5PC100_CLKGATE_D14_HSIRX, | ||
| 559 | }, | ||
| 560 | |||
| 561 | /* Audio (D1_5) devices */ | ||
| 562 | { | ||
| 563 | .name = "iis", | ||
| 564 | .id = 0, | ||
| 565 | .parent = &clk_p, | ||
| 566 | .enable = s5pc100_clk_d15_ctrl, | ||
| 567 | .ctrlbit = S5PC100_CLKGATE_D15_IIS0, | ||
| 568 | }, { | ||
| 569 | .name = "iis", | ||
| 570 | .id = 1, | ||
| 571 | .parent = &clk_p, | ||
| 572 | .enable = s5pc100_clk_d15_ctrl, | ||
| 573 | .ctrlbit = S5PC100_CLKGATE_D15_IIS1, | ||
| 574 | }, { | ||
| 575 | .name = "iis", | ||
| 576 | .id = 2, | ||
| 577 | .parent = &clk_p, | ||
| 578 | .enable = s5pc100_clk_d15_ctrl, | ||
| 579 | .ctrlbit = S5PC100_CLKGATE_D15_IIS2, | ||
| 580 | }, { | ||
| 581 | .name = "ac97", | ||
| 582 | .id = -1, | ||
| 583 | .parent = &clk_p, | ||
| 584 | .enable = s5pc100_clk_d15_ctrl, | ||
| 585 | .ctrlbit = S5PC100_CLKGATE_D15_AC97, | ||
| 586 | }, { | ||
| 587 | .name = "pcm", | ||
| 588 | .id = 0, | ||
| 589 | .parent = &clk_p, | ||
| 590 | .enable = s5pc100_clk_d15_ctrl, | ||
| 591 | .ctrlbit = S5PC100_CLKGATE_D15_PCM0, | ||
| 592 | }, { | ||
| 593 | .name = "pcm", | ||
| 594 | .id = 1, | ||
| 595 | .parent = &clk_p, | ||
| 596 | .enable = s5pc100_clk_d15_ctrl, | ||
| 597 | .ctrlbit = S5PC100_CLKGATE_D15_PCM1, | ||
| 598 | }, { | ||
| 599 | .name = "spdif", | ||
| 600 | .id = -1, | ||
| 601 | .parent = &clk_p, | ||
| 602 | .enable = s5pc100_clk_d15_ctrl, | ||
| 603 | .ctrlbit = S5PC100_CLKGATE_D15_SPDIF, | ||
| 604 | }, { | ||
| 605 | .name = "adc", | ||
| 606 | .id = -1, | ||
| 607 | .parent = &clk_p, | ||
| 608 | .enable = s5pc100_clk_d15_ctrl, | ||
| 609 | .ctrlbit = S5PC100_CLKGATE_D15_TSADC, | ||
| 610 | }, { | ||
| 611 | .name = "cg", | ||
| 612 | .id = -1, | ||
| 613 | .parent = &clk_p, | ||
| 614 | .enable = s5pc100_clk_d15_ctrl, | ||
| 615 | .ctrlbit = S5PC100_CLKGATE_D15_CG, | ||
| 616 | }, | ||
| 617 | |||
| 618 | /* Audio (D2_0) devices: all disabled */ | ||
| 619 | |||
| 620 | /* Special Clocks 0 */ | ||
| 621 | { | ||
| 622 | .name = "sclk_hpm", | ||
| 623 | .id = -1, | ||
| 624 | .parent = NULL, | ||
| 625 | .enable = s5pc100_sclk0_ctrl, | ||
| 626 | .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM, | ||
| 627 | }, { | ||
| 628 | .name = "sclk_onenand", | ||
| 629 | .id = -1, | ||
| 630 | .parent = NULL, | ||
| 631 | .enable = s5pc100_sclk0_ctrl, | ||
| 632 | .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND, | ||
| 633 | }, { | ||
| 634 | .name = "spi_48", | ||
| 635 | .id = 0, | ||
| 636 | .parent = &clk_48m, | ||
| 637 | .enable = s5pc100_sclk0_ctrl, | ||
| 638 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48, | ||
| 639 | }, { | ||
| 640 | .name = "spi_48", | ||
| 641 | .id = 1, | ||
| 642 | .parent = &clk_48m, | ||
| 643 | .enable = s5pc100_sclk0_ctrl, | ||
| 644 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48, | ||
| 645 | }, { | ||
| 646 | .name = "spi_48", | ||
| 647 | .id = 2, | ||
| 648 | .parent = &clk_48m, | ||
| 649 | .enable = s5pc100_sclk0_ctrl, | ||
| 650 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48, | ||
| 651 | }, { | ||
| 652 | .name = "mmc_48", | ||
| 653 | .id = 0, | ||
| 654 | .parent = &clk_48m, | ||
| 655 | .enable = s5pc100_sclk0_ctrl, | ||
| 656 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48, | ||
| 657 | }, { | ||
| 658 | .name = "mmc_48", | ||
| 659 | .id = 1, | ||
| 660 | .parent = &clk_48m, | ||
| 661 | .enable = s5pc100_sclk0_ctrl, | ||
| 662 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48, | ||
| 663 | }, { | ||
| 664 | .name = "mmc_48", | ||
| 665 | .id = 2, | ||
| 666 | .parent = &clk_48m, | ||
| 667 | .enable = s5pc100_sclk0_ctrl, | ||
| 668 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48, | ||
| 669 | }, | ||
| 670 | /* Special Clocks 1 */ | ||
| 671 | }; | ||
| 672 | |||
| 673 | static struct clk *clks[] __initdata = { | ||
| 674 | &clk_ext, | ||
| 675 | &clk_epll, | ||
| 676 | &clk_pd0, | ||
| 677 | &clk_hd0, | ||
| 678 | &clk_27m, | ||
| 679 | &clk_48m, | ||
| 680 | &clk_54m, | ||
| 681 | }; | ||
| 682 | |||
| 683 | void __init s5pc1xx_register_clocks(void) | ||
| 684 | { | ||
| 685 | struct clk *clkp; | ||
| 686 | int ret; | ||
| 687 | int ptr; | ||
| 688 | int size; | ||
| 689 | |||
| 690 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
| 691 | |||
| 692 | s3c_register_clocks(s5pc100_init_clocks, | ||
| 693 | ARRAY_SIZE(s5pc100_init_clocks)); | ||
| 694 | |||
| 695 | clkp = s5pc100_init_clocks_disable; | ||
| 696 | size = ARRAY_SIZE(s5pc100_init_clocks_disable); | ||
| 697 | |||
| 698 | for (ptr = 0; ptr < size; ptr++, clkp++) { | ||
| 699 | ret = s3c24xx_register_clock(clkp); | ||
| 700 | if (ret < 0) { | ||
| 701 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 702 | clkp->name, ret); | ||
| 703 | } | ||
| 704 | |||
| 705 | (clkp->enable)(clkp, 0); | ||
| 706 | } | ||
| 707 | |||
| 708 | s3c_pwmclk_init(); | ||
| 709 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c deleted file mode 100644 index 02baeaa2a121..000000000000 --- a/arch/arm/plat-s5pc1xx/cpu.c +++ /dev/null | |||
| @@ -1,122 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/cpu.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX CPU Support | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/cpu.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/ioport.h> | ||
| 19 | #include <linux/serial_core.h> | ||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | |||
| 23 | #include <mach/hardware.h> | ||
| 24 | #include <mach/map.h> | ||
| 25 | |||
| 26 | #include <asm/mach/map.h> | ||
| 27 | |||
| 28 | #include <plat/regs-serial.h> | ||
| 29 | |||
| 30 | #include <plat/cpu.h> | ||
| 31 | #include <plat/devs.h> | ||
| 32 | #include <plat/clock.h> | ||
| 33 | |||
| 34 | #include <plat/s5pc100.h> | ||
| 35 | |||
| 36 | /* table of supported CPUs */ | ||
| 37 | |||
| 38 | static const char name_s5pc100[] = "S5PC100"; | ||
| 39 | |||
| 40 | static struct cpu_table cpu_ids[] __initdata = { | ||
| 41 | { | ||
| 42 | .idcode = 0x43100000, | ||
| 43 | .idmask = 0xfffff000, | ||
| 44 | .map_io = s5pc100_map_io, | ||
| 45 | .init_clocks = s5pc100_init_clocks, | ||
| 46 | .init_uarts = s5pc100_init_uarts, | ||
| 47 | .init = s5pc100_init, | ||
| 48 | .name = name_s5pc100, | ||
| 49 | }, | ||
| 50 | }; | ||
| 51 | /* minimal IO mapping */ | ||
| 52 | |||
| 53 | /* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */ | ||
| 54 | #define UART_OFFS (S3C_PA_UART & 0xffff) | ||
| 55 | |||
| 56 | static struct map_desc s5pc1xx_iodesc[] __initdata = { | ||
| 57 | { | ||
| 58 | .virtual = (unsigned long)S5PC1XX_VA_CLK_OTHER, | ||
| 59 | .pfn = __phys_to_pfn(S5PC1XX_PA_CLK_OTHER), | ||
| 60 | .length = SZ_4K, | ||
| 61 | .type = MT_DEVICE, | ||
| 62 | }, { | ||
| 63 | .virtual = (unsigned long)S5PC1XX_VA_GPIO, | ||
| 64 | .pfn = __phys_to_pfn(S5PC100_PA_GPIO), | ||
| 65 | .length = SZ_4K, | ||
| 66 | .type = MT_DEVICE, | ||
| 67 | }, { | ||
| 68 | .virtual = (unsigned long)S5PC1XX_VA_CHIPID, | ||
| 69 | .pfn = __phys_to_pfn(S5PC1XX_PA_CHIPID), | ||
| 70 | .length = SZ_16, | ||
| 71 | .type = MT_DEVICE, | ||
| 72 | }, { | ||
| 73 | .virtual = (unsigned long)S5PC1XX_VA_CLK, | ||
| 74 | .pfn = __phys_to_pfn(S5PC1XX_PA_CLK), | ||
| 75 | .length = SZ_4K, | ||
| 76 | .type = MT_DEVICE, | ||
| 77 | }, { | ||
| 78 | .virtual = (unsigned long)S5PC1XX_VA_PWR, | ||
| 79 | .pfn = __phys_to_pfn(S5PC1XX_PA_PWR), | ||
| 80 | .length = SZ_4K, | ||
| 81 | .type = MT_DEVICE, | ||
| 82 | }, { | ||
| 83 | .virtual = (unsigned long)(S5PC1XX_VA_UART), | ||
| 84 | .pfn = __phys_to_pfn(S5PC1XX_PA_UART), | ||
| 85 | .length = SZ_4K, | ||
| 86 | .type = MT_DEVICE, | ||
| 87 | }, { | ||
| 88 | .virtual = (unsigned long)S5PC1XX_VA_VIC(0), | ||
| 89 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(0)), | ||
| 90 | .length = SZ_4K, | ||
| 91 | .type = MT_DEVICE, | ||
| 92 | }, { | ||
| 93 | .virtual = (unsigned long)S5PC1XX_VA_VIC(1), | ||
| 94 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(1)), | ||
| 95 | .length = SZ_4K, | ||
| 96 | .type = MT_DEVICE, | ||
| 97 | }, { | ||
| 98 | .virtual = (unsigned long)S5PC1XX_VA_VIC(2), | ||
| 99 | .pfn = __phys_to_pfn(S5PC1XX_PA_VIC(2)), | ||
| 100 | .length = SZ_4K, | ||
| 101 | .type = MT_DEVICE, | ||
| 102 | }, { | ||
| 103 | .virtual = (unsigned long)S5PC1XX_VA_TIMER, | ||
| 104 | .pfn = __phys_to_pfn(S5PC1XX_PA_TIMER), | ||
| 105 | .length = SZ_256, | ||
| 106 | .type = MT_DEVICE, | ||
| 107 | }, | ||
| 108 | }; | ||
| 109 | |||
| 110 | /* read cpu identification code */ | ||
| 111 | |||
| 112 | void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size) | ||
| 113 | { | ||
| 114 | unsigned long idcode; | ||
| 115 | |||
| 116 | /* initialise the io descriptors we need for initialisation */ | ||
| 117 | iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc)); | ||
| 118 | iotable_init(mach_desc, size); | ||
| 119 | |||
| 120 | idcode = __raw_readl(S5PC1XX_VA_CHIPID); | ||
| 121 | s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
| 122 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c deleted file mode 100644 index 586c95c60bfe..000000000000 --- a/arch/arm/plat-s5pc1xx/dev-uart.c +++ /dev/null | |||
| @@ -1,145 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/dev-uart.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * Based on plat-s3c64xx/dev-uart.c | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/list.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | |||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <asm/mach/irq.h> | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/map.h> | ||
| 24 | |||
| 25 | #include <plat/devs.h> | ||
| 26 | |||
| 27 | /* Serial port registrations */ | ||
| 28 | |||
| 29 | /* 64xx uarts are closer together */ | ||
| 30 | |||
| 31 | static struct resource s5pc1xx_uart0_resource[] = { | ||
| 32 | [0] = { | ||
| 33 | .start = S3C_PA_UART0, | ||
| 34 | .end = S3C_PA_UART0 + 0x100, | ||
| 35 | .flags = IORESOURCE_MEM, | ||
| 36 | }, | ||
| 37 | [1] = { | ||
| 38 | .start = IRQ_S3CUART_RX0, | ||
| 39 | .end = IRQ_S3CUART_RX0, | ||
| 40 | .flags = IORESOURCE_IRQ, | ||
| 41 | }, | ||
| 42 | [2] = { | ||
| 43 | .start = IRQ_S3CUART_TX0, | ||
| 44 | .end = IRQ_S3CUART_TX0, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | |||
| 47 | }, | ||
| 48 | [3] = { | ||
| 49 | .start = IRQ_S3CUART_ERR0, | ||
| 50 | .end = IRQ_S3CUART_ERR0, | ||
| 51 | .flags = IORESOURCE_IRQ, | ||
| 52 | } | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct resource s5pc1xx_uart1_resource[] = { | ||
| 56 | [0] = { | ||
| 57 | .start = S3C_PA_UART1, | ||
| 58 | .end = S3C_PA_UART1 + 0x100, | ||
| 59 | .flags = IORESOURCE_MEM, | ||
| 60 | }, | ||
| 61 | [1] = { | ||
| 62 | .start = IRQ_S3CUART_RX1, | ||
| 63 | .end = IRQ_S3CUART_RX1, | ||
| 64 | .flags = IORESOURCE_IRQ, | ||
| 65 | }, | ||
| 66 | [2] = { | ||
| 67 | .start = IRQ_S3CUART_TX1, | ||
| 68 | .end = IRQ_S3CUART_TX1, | ||
| 69 | .flags = IORESOURCE_IRQ, | ||
| 70 | |||
| 71 | }, | ||
| 72 | [3] = { | ||
| 73 | .start = IRQ_S3CUART_ERR1, | ||
| 74 | .end = IRQ_S3CUART_ERR1, | ||
| 75 | .flags = IORESOURCE_IRQ, | ||
| 76 | }, | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct resource s5pc1xx_uart2_resource[] = { | ||
| 80 | [0] = { | ||
| 81 | .start = S3C_PA_UART2, | ||
| 82 | .end = S3C_PA_UART2 + 0x100, | ||
| 83 | .flags = IORESOURCE_MEM, | ||
| 84 | }, | ||
| 85 | [1] = { | ||
| 86 | .start = IRQ_S3CUART_RX2, | ||
| 87 | .end = IRQ_S3CUART_RX2, | ||
| 88 | .flags = IORESOURCE_IRQ, | ||
| 89 | }, | ||
| 90 | [2] = { | ||
| 91 | .start = IRQ_S3CUART_TX2, | ||
| 92 | .end = IRQ_S3CUART_TX2, | ||
| 93 | .flags = IORESOURCE_IRQ, | ||
| 94 | |||
| 95 | }, | ||
| 96 | [3] = { | ||
| 97 | .start = IRQ_S3CUART_ERR2, | ||
| 98 | .end = IRQ_S3CUART_ERR2, | ||
| 99 | .flags = IORESOURCE_IRQ, | ||
| 100 | }, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct resource s5pc1xx_uart3_resource[] = { | ||
| 104 | [0] = { | ||
| 105 | .start = S3C_PA_UART3, | ||
| 106 | .end = S3C_PA_UART3 + 0x100, | ||
| 107 | .flags = IORESOURCE_MEM, | ||
| 108 | }, | ||
| 109 | [1] = { | ||
| 110 | .start = IRQ_S3CUART_RX3, | ||
| 111 | .end = IRQ_S3CUART_RX3, | ||
| 112 | .flags = IORESOURCE_IRQ, | ||
| 113 | }, | ||
| 114 | [2] = { | ||
| 115 | .start = IRQ_S3CUART_TX3, | ||
| 116 | .end = IRQ_S3CUART_TX3, | ||
| 117 | .flags = IORESOURCE_IRQ, | ||
| 118 | |||
| 119 | }, | ||
| 120 | [3] = { | ||
| 121 | .start = IRQ_S3CUART_ERR3, | ||
| 122 | .end = IRQ_S3CUART_ERR3, | ||
| 123 | .flags = IORESOURCE_IRQ, | ||
| 124 | }, | ||
| 125 | }; | ||
| 126 | |||
| 127 | |||
| 128 | struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = { | ||
| 129 | [0] = { | ||
| 130 | .resources = s5pc1xx_uart0_resource, | ||
| 131 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart0_resource), | ||
| 132 | }, | ||
| 133 | [1] = { | ||
| 134 | .resources = s5pc1xx_uart1_resource, | ||
| 135 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart1_resource), | ||
| 136 | }, | ||
| 137 | [2] = { | ||
| 138 | .resources = s5pc1xx_uart2_resource, | ||
| 139 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart2_resource), | ||
| 140 | }, | ||
| 141 | [3] = { | ||
| 142 | .resources = s5pc1xx_uart3_resource, | ||
| 143 | .nr_resources = ARRAY_SIZE(s5pc1xx_uart3_resource), | ||
| 144 | }, | ||
| 145 | }; | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h b/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h deleted file mode 100644 index 33ad267e8477..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/gpio-ext.h +++ /dev/null | |||
| @@ -1,44 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/gpio-eint.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * | ||
| 5 | * External Interrupt (GPH0 ~ GPH3) control register definitions | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #define S5PC1XX_WKUP_INT_CON0_7 (S5PC1XX_EINT_BASE + 0x0) | ||
| 13 | #define S5PC1XX_WKUP_INT_CON8_15 (S5PC1XX_EINT_BASE + 0x4) | ||
| 14 | #define S5PC1XX_WKUP_INT_CON16_23 (S5PC1XX_EINT_BASE + 0x8) | ||
| 15 | #define S5PC1XX_WKUP_INT_CON24_31 (S5PC1XX_EINT_BASE + 0xC) | ||
| 16 | #define S5PC1XX_WKUP_INT_CON(x) (S5PC1XX_WKUP_INT_CON0_7 + (x * 0x4)) | ||
| 17 | |||
| 18 | #define S5PC1XX_WKUP_INT_FLTCON0_3 (S5PC1XX_EINT_BASE + 0x80) | ||
| 19 | #define S5PC1XX_WKUP_INT_FLTCON4_7 (S5PC1XX_EINT_BASE + 0x84) | ||
| 20 | #define S5PC1XX_WKUP_INT_FLTCON8_11 (S5PC1XX_EINT_BASE + 0x88) | ||
| 21 | #define S5PC1XX_WKUP_INT_FLTCON12_15 (S5PC1XX_EINT_BASE + 0x8C) | ||
| 22 | #define S5PC1XX_WKUP_INT_FLTCON16_19 (S5PC1XX_EINT_BASE + 0x90) | ||
| 23 | #define S5PC1XX_WKUP_INT_FLTCON20_23 (S5PC1XX_EINT_BASE + 0x94) | ||
| 24 | #define S5PC1XX_WKUP_INT_FLTCON24_27 (S5PC1XX_EINT_BASE + 0x98) | ||
| 25 | #define S5PC1XX_WKUP_INT_FLTCON28_31 (S5PC1XX_EINT_BASE + 0x9C) | ||
| 26 | #define S5PC1XX_WKUP_INT_FLTCON(x) (S5PC1XX_WKUP_INT_FLTCON0_3 + (x * 0x4)) | ||
| 27 | |||
| 28 | #define S5PC1XX_WKUP_INT_MASK0_7 (S5PC1XX_EINT_BASE + 0x100) | ||
| 29 | #define S5PC1XX_WKUP_INT_MASK8_15 (S5PC1XX_EINT_BASE + 0x104) | ||
| 30 | #define S5PC1XX_WKUP_INT_MASK16_23 (S5PC1XX_EINT_BASE + 0x108) | ||
| 31 | #define S5PC1XX_WKUP_INT_MASK24_31 (S5PC1XX_EINT_BASE + 0x10C) | ||
| 32 | #define S5PC1XX_WKUP_INT_MASK(x) (S5PC1XX_WKUP_INT_MASK0_7 + (x * 0x4)) | ||
| 33 | |||
| 34 | #define S5PC1XX_WKUP_INT_PEND0_7 (S5PC1XX_EINT_BASE + 0x140) | ||
| 35 | #define S5PC1XX_WKUP_INT_PEND8_15 (S5PC1XX_EINT_BASE + 0x144) | ||
| 36 | #define S5PC1XX_WKUP_INT_PEND16_23 (S5PC1XX_EINT_BASE + 0x148) | ||
| 37 | #define S5PC1XX_WKUP_INT_PEND24_31 (S5PC1XX_EINT_BASE + 0x14C) | ||
| 38 | #define S5PC1XX_WKUP_INT_PEND(x) (S5PC1XX_WKUP_INT_PEND0_7 + (x * 0x4)) | ||
| 39 | |||
| 40 | #define S5PC1XX_WKUP_INT_LOWLEV (0x00) | ||
| 41 | #define S5PC1XX_WKUP_INT_HILEV (0x01) | ||
| 42 | #define S5PC1XX_WKUP_INT_FALLEDGE (0x02) | ||
| 43 | #define S5PC1XX_WKUP_INT_RISEEDGE (0x03) | ||
| 44 | #define S5PC1XX_WKUP_INT_BOTHEDGE (0x04) | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h deleted file mode 100644 index 409c804315e8..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/irqs.h +++ /dev/null | |||
| @@ -1,198 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX - Common IRQ support | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/include/plat/irqs.h | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_PLAT_S5PC1XX_IRQS_H | ||
| 12 | #define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__ | ||
| 13 | |||
| 14 | /* we keep the first set of CPU IRQs out of the range of | ||
| 15 | * the ISA space, so that the PC104 has them to itself | ||
| 16 | * and we don't end up having to do horrible things to the | ||
| 17 | * standard ISA drivers.... | ||
| 18 | * | ||
| 19 | * note, since we're using the VICs, our start must be a | ||
| 20 | * mulitple of 32 to allow the common code to work | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define S3C_IRQ_OFFSET (32) | ||
| 24 | |||
| 25 | #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) | ||
| 26 | |||
| 27 | #define S3C_VIC0_BASE S3C_IRQ(0) | ||
| 28 | #define S3C_VIC1_BASE S3C_IRQ(32) | ||
| 29 | #define S3C_VIC2_BASE S3C_IRQ(64) | ||
| 30 | |||
| 31 | /* UART interrupts, each UART has 4 intterupts per channel so | ||
| 32 | * use the space between the ISA and S3C main interrupts. Note, these | ||
| 33 | * are not in the same order as the S3C24XX series! */ | ||
| 34 | |||
| 35 | #define IRQ_S3CUART_BASE0 (16) | ||
| 36 | #define IRQ_S3CUART_BASE1 (20) | ||
| 37 | #define IRQ_S3CUART_BASE2 (24) | ||
| 38 | #define IRQ_S3CUART_BASE3 (28) | ||
| 39 | |||
| 40 | #define UART_IRQ_RXD (0) | ||
| 41 | #define UART_IRQ_ERR (1) | ||
| 42 | #define UART_IRQ_TXD (2) | ||
| 43 | #define UART_IRQ_MODEM (3) | ||
| 44 | |||
| 45 | #define IRQ_S3CUART_RX0 (IRQ_S3CUART_BASE0 + UART_IRQ_RXD) | ||
| 46 | #define IRQ_S3CUART_TX0 (IRQ_S3CUART_BASE0 + UART_IRQ_TXD) | ||
| 47 | #define IRQ_S3CUART_ERR0 (IRQ_S3CUART_BASE0 + UART_IRQ_ERR) | ||
| 48 | |||
| 49 | #define IRQ_S3CUART_RX1 (IRQ_S3CUART_BASE1 + UART_IRQ_RXD) | ||
| 50 | #define IRQ_S3CUART_TX1 (IRQ_S3CUART_BASE1 + UART_IRQ_TXD) | ||
| 51 | #define IRQ_S3CUART_ERR1 (IRQ_S3CUART_BASE1 + UART_IRQ_ERR) | ||
| 52 | |||
| 53 | #define IRQ_S3CUART_RX2 (IRQ_S3CUART_BASE2 + UART_IRQ_RXD) | ||
| 54 | #define IRQ_S3CUART_TX2 (IRQ_S3CUART_BASE2 + UART_IRQ_TXD) | ||
| 55 | #define IRQ_S3CUART_ERR2 (IRQ_S3CUART_BASE2 + UART_IRQ_ERR) | ||
| 56 | |||
| 57 | #define IRQ_S3CUART_RX3 (IRQ_S3CUART_BASE3 + UART_IRQ_RXD) | ||
| 58 | #define IRQ_S3CUART_TX3 (IRQ_S3CUART_BASE3 + UART_IRQ_TXD) | ||
| 59 | #define IRQ_S3CUART_ERR3 (IRQ_S3CUART_BASE3 + UART_IRQ_ERR) | ||
| 60 | |||
| 61 | /* VIC based IRQs */ | ||
| 62 | |||
| 63 | #define S5PC1XX_IRQ_VIC0(x) (S3C_VIC0_BASE + (x)) | ||
| 64 | #define S5PC1XX_IRQ_VIC1(x) (S3C_VIC1_BASE + (x)) | ||
| 65 | #define S5PC1XX_IRQ_VIC2(x) (S3C_VIC2_BASE + (x)) | ||
| 66 | |||
| 67 | /* | ||
| 68 | * VIC0: system, DMA, timer | ||
| 69 | */ | ||
| 70 | #define IRQ_EINT0 S5PC1XX_IRQ_VIC0(0) | ||
| 71 | #define IRQ_EINT1 S5PC1XX_IRQ_VIC0(1) | ||
| 72 | #define IRQ_EINT2 S5PC1XX_IRQ_VIC0(2) | ||
| 73 | #define IRQ_EINT3 S5PC1XX_IRQ_VIC0(3) | ||
| 74 | #define IRQ_EINT4 S5PC1XX_IRQ_VIC0(4) | ||
| 75 | #define IRQ_EINT5 S5PC1XX_IRQ_VIC0(5) | ||
| 76 | #define IRQ_EINT6 S5PC1XX_IRQ_VIC0(6) | ||
| 77 | #define IRQ_EINT7 S5PC1XX_IRQ_VIC0(7) | ||
| 78 | #define IRQ_EINT8 S5PC1XX_IRQ_VIC0(8) | ||
| 79 | #define IRQ_EINT9 S5PC1XX_IRQ_VIC0(9) | ||
| 80 | #define IRQ_EINT10 S5PC1XX_IRQ_VIC0(10) | ||
| 81 | #define IRQ_EINT11 S5PC1XX_IRQ_VIC0(11) | ||
| 82 | #define IRQ_EINT12 S5PC1XX_IRQ_VIC0(12) | ||
| 83 | #define IRQ_EINT13 S5PC1XX_IRQ_VIC0(13) | ||
| 84 | #define IRQ_EINT14 S5PC1XX_IRQ_VIC0(14) | ||
| 85 | #define IRQ_EINT15 S5PC1XX_IRQ_VIC0(15) | ||
| 86 | #define IRQ_EINT16_31 S5PC1XX_IRQ_VIC0(16) | ||
| 87 | #define IRQ_BATF S5PC1XX_IRQ_VIC0(17) | ||
| 88 | #define IRQ_MDMA S5PC1XX_IRQ_VIC0(18) | ||
| 89 | #define IRQ_PDMA0 S5PC1XX_IRQ_VIC0(19) | ||
| 90 | #define IRQ_PDMA1 S5PC1XX_IRQ_VIC0(20) | ||
| 91 | #define IRQ_TIMER0_VIC S5PC1XX_IRQ_VIC0(21) | ||
| 92 | #define IRQ_TIMER1_VIC S5PC1XX_IRQ_VIC0(22) | ||
| 93 | #define IRQ_TIMER2_VIC S5PC1XX_IRQ_VIC0(23) | ||
| 94 | #define IRQ_TIMER3_VIC S5PC1XX_IRQ_VIC0(24) | ||
| 95 | #define IRQ_TIMER4_VIC S5PC1XX_IRQ_VIC0(25) | ||
| 96 | #define IRQ_SYSTIMER S5PC1XX_IRQ_VIC0(26) | ||
| 97 | #define IRQ_WDT S5PC1XX_IRQ_VIC0(27) | ||
| 98 | #define IRQ_RTC_ALARM S5PC1XX_IRQ_VIC0(28) | ||
| 99 | #define IRQ_RTC_TIC S5PC1XX_IRQ_VIC0(29) | ||
| 100 | #define IRQ_GPIOINT S5PC1XX_IRQ_VIC0(30) | ||
| 101 | |||
| 102 | /* | ||
| 103 | * VIC1: ARM, power, memory, connectivity | ||
| 104 | */ | ||
| 105 | #define IRQ_CORTEX0 S5PC1XX_IRQ_VIC1(0) | ||
| 106 | #define IRQ_CORTEX1 S5PC1XX_IRQ_VIC1(1) | ||
| 107 | #define IRQ_CORTEX2 S5PC1XX_IRQ_VIC1(2) | ||
| 108 | #define IRQ_CORTEX3 S5PC1XX_IRQ_VIC1(3) | ||
| 109 | #define IRQ_CORTEX4 S5PC1XX_IRQ_VIC1(4) | ||
| 110 | #define IRQ_IEMAPC S5PC1XX_IRQ_VIC1(5) | ||
| 111 | #define IRQ_IEMIEC S5PC1XX_IRQ_VIC1(6) | ||
| 112 | #define IRQ_ONENAND S5PC1XX_IRQ_VIC1(7) | ||
| 113 | #define IRQ_NFC S5PC1XX_IRQ_VIC1(8) | ||
| 114 | #define IRQ_CFC S5PC1XX_IRQ_VIC1(9) | ||
| 115 | #define IRQ_UART0 S5PC1XX_IRQ_VIC1(10) | ||
| 116 | #define IRQ_UART1 S5PC1XX_IRQ_VIC1(11) | ||
| 117 | #define IRQ_UART2 S5PC1XX_IRQ_VIC1(12) | ||
| 118 | #define IRQ_UART3 S5PC1XX_IRQ_VIC1(13) | ||
| 119 | #define IRQ_IIC S5PC1XX_IRQ_VIC1(14) | ||
| 120 | #define IRQ_SPI0 S5PC1XX_IRQ_VIC1(15) | ||
| 121 | #define IRQ_SPI1 S5PC1XX_IRQ_VIC1(16) | ||
| 122 | #define IRQ_SPI2 S5PC1XX_IRQ_VIC1(17) | ||
| 123 | #define IRQ_IRDA S5PC1XX_IRQ_VIC1(18) | ||
| 124 | #define IRQ_CAN0 S5PC1XX_IRQ_VIC1(19) | ||
| 125 | #define IRQ_CAN1 S5PC1XX_IRQ_VIC1(20) | ||
| 126 | #define IRQ_HSIRX S5PC1XX_IRQ_VIC1(21) | ||
| 127 | #define IRQ_HSITX S5PC1XX_IRQ_VIC1(22) | ||
| 128 | #define IRQ_UHOST S5PC1XX_IRQ_VIC1(23) | ||
| 129 | #define IRQ_OTG S5PC1XX_IRQ_VIC1(24) | ||
| 130 | #define IRQ_MSM S5PC1XX_IRQ_VIC1(25) | ||
| 131 | #define IRQ_HSMMC0 S5PC1XX_IRQ_VIC1(26) | ||
| 132 | #define IRQ_HSMMC1 S5PC1XX_IRQ_VIC1(27) | ||
| 133 | #define IRQ_HSMMC2 S5PC1XX_IRQ_VIC1(28) | ||
| 134 | #define IRQ_MIPICSI S5PC1XX_IRQ_VIC1(29) | ||
| 135 | #define IRQ_MIPIDSI S5PC1XX_IRQ_VIC1(30) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * VIC2: multimedia, audio, security | ||
| 139 | */ | ||
| 140 | #define IRQ_LCD0 S5PC1XX_IRQ_VIC2(0) | ||
| 141 | #define IRQ_LCD1 S5PC1XX_IRQ_VIC2(1) | ||
| 142 | #define IRQ_LCD2 S5PC1XX_IRQ_VIC2(2) | ||
| 143 | #define IRQ_LCD3 S5PC1XX_IRQ_VIC2(3) | ||
| 144 | #define IRQ_ROTATOR S5PC1XX_IRQ_VIC2(4) | ||
| 145 | #define IRQ_FIMC0 S5PC1XX_IRQ_VIC2(5) | ||
| 146 | #define IRQ_FIMC1 S5PC1XX_IRQ_VIC2(6) | ||
| 147 | #define IRQ_FIMC2 S5PC1XX_IRQ_VIC2(7) | ||
| 148 | #define IRQ_JPEG S5PC1XX_IRQ_VIC2(8) | ||
| 149 | #define IRQ_2D S5PC1XX_IRQ_VIC2(9) | ||
| 150 | #define IRQ_3D S5PC1XX_IRQ_VIC2(10) | ||
| 151 | #define IRQ_MIXER S5PC1XX_IRQ_VIC2(11) | ||
| 152 | #define IRQ_HDMI S5PC1XX_IRQ_VIC2(12) | ||
| 153 | #define IRQ_IIC1 S5PC1XX_IRQ_VIC2(13) | ||
| 154 | #define IRQ_MFC S5PC1XX_IRQ_VIC2(14) | ||
| 155 | #define IRQ_TVENC S5PC1XX_IRQ_VIC2(15) | ||
| 156 | #define IRQ_I2S0 S5PC1XX_IRQ_VIC2(16) | ||
| 157 | #define IRQ_I2S1 S5PC1XX_IRQ_VIC2(17) | ||
| 158 | #define IRQ_I2S2 S5PC1XX_IRQ_VIC2(18) | ||
| 159 | #define IRQ_AC97 S5PC1XX_IRQ_VIC2(19) | ||
| 160 | #define IRQ_PCM0 S5PC1XX_IRQ_VIC2(20) | ||
| 161 | #define IRQ_PCM1 S5PC1XX_IRQ_VIC2(21) | ||
| 162 | #define IRQ_SPDIF S5PC1XX_IRQ_VIC2(22) | ||
| 163 | #define IRQ_ADC S5PC1XX_IRQ_VIC2(23) | ||
| 164 | #define IRQ_PENDN S5PC1XX_IRQ_VIC2(24) | ||
| 165 | #define IRQ_TC IRQ_PENDN | ||
| 166 | #define IRQ_KEYPAD S5PC1XX_IRQ_VIC2(25) | ||
| 167 | #define IRQ_CG S5PC1XX_IRQ_VIC2(26) | ||
| 168 | #define IRQ_SEC S5PC1XX_IRQ_VIC2(27) | ||
| 169 | #define IRQ_SECRX S5PC1XX_IRQ_VIC2(28) | ||
| 170 | #define IRQ_SECTX S5PC1XX_IRQ_VIC2(29) | ||
| 171 | #define IRQ_SDMIRQ S5PC1XX_IRQ_VIC2(30) | ||
| 172 | #define IRQ_SDMFIQ S5PC1XX_IRQ_VIC2(31) | ||
| 173 | |||
| 174 | #define IRQ_TIMER(x) (IRQ_SDMFIQ + 1 + (x)) | ||
| 175 | #define IRQ_TIMER0 IRQ_TIMER(0) | ||
| 176 | #define IRQ_TIMER1 IRQ_TIMER(1) | ||
| 177 | #define IRQ_TIMER2 IRQ_TIMER(2) | ||
| 178 | #define IRQ_TIMER3 IRQ_TIMER(3) | ||
| 179 | #define IRQ_TIMER4 IRQ_TIMER(4) | ||
| 180 | |||
| 181 | /* External interrupt */ | ||
| 182 | #define S3C_IRQ_EINT_BASE (IRQ_SDMFIQ + 6) | ||
| 183 | |||
| 184 | #define S3C_EINT(x) (S3C_IRQ_EINT_BASE + (x - 16)) | ||
| 185 | #define IRQ_EINT(x) (x < 16 ? IRQ_EINT0 + x : S3C_EINT(x)) | ||
| 186 | #define IRQ_EINT_BIT(x) (x < IRQ_EINT16_31 ? x - IRQ_EINT0 : x - S3C_EINT(0)) | ||
| 187 | |||
| 188 | /* GPIO interrupt */ | ||
| 189 | #define S3C_IRQ_GPIO_BASE (IRQ_EINT(31) + 1) | ||
| 190 | #define S3C_IRQ_GPIO(x) (S3C_IRQ_GPIO_BASE + (x)) | ||
| 191 | |||
| 192 | /* | ||
| 193 | * Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs | ||
| 194 | */ | ||
| 195 | #define NR_IRQS (S3C_IRQ_GPIO(320) + 1) | ||
| 196 | |||
| 197 | #endif /* __ASM_PLAT_S5PC1XX_IRQS_H */ | ||
| 198 | |||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h deleted file mode 100644 index 21afef1573e7..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/pll.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* arch/arm/plat-s5pc1xx/include/plat/pll.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX PLL code | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/include/plat/pll.h | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #define S5P_PLL_MDIV_MASK ((1 << (25-16+1)) - 1) | ||
| 16 | #define S5P_PLL_PDIV_MASK ((1 << (13-8+1)) - 1) | ||
| 17 | #define S5P_PLL_SDIV_MASK ((1 << (2-0+1)) - 1) | ||
| 18 | #define S5P_PLL_MDIV_SHIFT (16) | ||
| 19 | #define S5P_PLL_PDIV_SHIFT (8) | ||
| 20 | #define S5P_PLL_SDIV_SHIFT (0) | ||
| 21 | |||
| 22 | #include <asm/div64.h> | ||
| 23 | |||
| 24 | static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk, | ||
| 25 | u32 pllcon) | ||
| 26 | { | ||
| 27 | u32 mdiv, pdiv, sdiv; | ||
| 28 | u64 fvco = baseclk; | ||
| 29 | |||
| 30 | mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK; | ||
| 31 | pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK; | ||
| 32 | sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK; | ||
| 33 | |||
| 34 | fvco *= mdiv; | ||
| 35 | do_div(fvco, (pdiv << sdiv)); | ||
| 36 | |||
| 37 | return (unsigned long)fvco; | ||
| 38 | } | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h deleted file mode 100644 index 24dec4e52538..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h +++ /dev/null | |||
| @@ -1,252 +0,0 @@ | |||
| 1 | /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX clock register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __PLAT_REGS_CLOCK_H | ||
| 14 | #define __PLAT_REGS_CLOCK_H __FILE__ | ||
| 15 | |||
| 16 | #define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x)) | ||
| 17 | #define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x)) | ||
| 18 | |||
| 19 | /* s5pc100 register for clock */ | ||
| 20 | #define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00) | ||
| 21 | #define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04) | ||
| 22 | #define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08) | ||
| 23 | #define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C) | ||
| 24 | |||
| 25 | #define S5PC100_APLL_CON S5PC100_CLKREG(0x100) | ||
| 26 | #define S5PC100_MPLL_CON S5PC100_CLKREG(0x104) | ||
| 27 | #define S5PC100_EPLL_CON S5PC100_CLKREG(0x108) | ||
| 28 | #define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C) | ||
| 29 | |||
| 30 | #define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200) | ||
| 31 | #define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204) | ||
| 32 | #define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208) | ||
| 33 | #define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C) | ||
| 34 | |||
| 35 | #define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300) | ||
| 36 | #define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304) | ||
| 37 | #define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308) | ||
| 38 | #define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C) | ||
| 39 | #define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310) | ||
| 40 | |||
| 41 | #define S5PC100_CLK_OUT S5PC100_CLKREG(0x400) | ||
| 42 | |||
| 43 | #define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500) | ||
| 44 | #define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504) | ||
| 45 | #define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508) | ||
| 46 | |||
| 47 | #define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520) | ||
| 48 | #define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524) | ||
| 49 | #define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528) | ||
| 50 | #define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C) | ||
| 51 | #define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530) | ||
| 52 | #define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534) | ||
| 53 | |||
| 54 | #define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540) | ||
| 55 | |||
| 56 | #define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560) | ||
| 57 | #define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564) | ||
| 58 | |||
| 59 | /* EPLL_CON */ | ||
| 60 | #define S5PC100_EPLL_EN (1<<31) | ||
| 61 | #define S5PC100_EPLL_MASK 0xffffffff | ||
| 62 | #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s))) | ||
| 63 | |||
| 64 | /* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */ | ||
| 65 | #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24) | ||
| 66 | #define S5PC100_CLKSRC1_CLK48M_SHIFT (24) | ||
| 67 | |||
| 68 | /* CLKDIV0 */ | ||
| 69 | #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0) | ||
| 70 | #define S5PC100_CLKDIV0_APLL_SHIFT (0) | ||
| 71 | #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4) | ||
| 72 | #define S5PC100_CLKDIV0_ARM_SHIFT (4) | ||
| 73 | #define S5PC100_CLKDIV0_D0_MASK (0x7<<8) | ||
| 74 | #define S5PC100_CLKDIV0_D0_SHIFT (8) | ||
| 75 | #define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12) | ||
| 76 | #define S5PC100_CLKDIV0_PCLKD0_SHIFT (12) | ||
| 77 | #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16) | ||
| 78 | #define S5PC100_CLKDIV0_SECSS_SHIFT (16) | ||
| 79 | |||
| 80 | /* CLKDIV1 (OneNAND clock only used in one place, removed) */ | ||
| 81 | #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0) | ||
| 82 | #define S5PC100_CLKDIV1_APLL2_SHIFT (0) | ||
| 83 | #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4) | ||
| 84 | #define S5PC100_CLKDIV1_MPLL_SHIFT (4) | ||
| 85 | #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8) | ||
| 86 | #define S5PC100_CLKDIV1_MPLL2_SHIFT (8) | ||
| 87 | #define S5PC100_CLKDIV1_D1_MASK (0x7<<12) | ||
| 88 | #define S5PC100_CLKDIV1_D1_SHIFT (12) | ||
| 89 | #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16) | ||
| 90 | #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16) | ||
| 91 | #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24) | ||
| 92 | #define S5PC100_CLKDIV1_CAM_SHIFT (24) | ||
| 93 | |||
| 94 | /* CLKDIV2 => removed in clksrc update */ | ||
| 95 | /* CLKDIV3 => removed in clksrc update, or not needed */ | ||
| 96 | /* CLKDIV4 => removed in clksrc update, or not needed */ | ||
| 97 | |||
| 98 | /* HCLKD0/PCLKD0 Clock Gate 0 Registers */ | ||
| 99 | #define S5PC100_CLKGATE_D00_INTC (1<<0) | ||
| 100 | #define S5PC100_CLKGATE_D00_TZIC (1<<1) | ||
| 101 | #define S5PC100_CLKGATE_D00_CFCON (1<<2) | ||
| 102 | #define S5PC100_CLKGATE_D00_MDMA (1<<3) | ||
| 103 | #define S5PC100_CLKGATE_D00_G2D (1<<4) | ||
| 104 | #define S5PC100_CLKGATE_D00_SECSS (1<<5) | ||
| 105 | #define S5PC100_CLKGATE_D00_CSSYS (1<<6) | ||
| 106 | |||
| 107 | /* HCLKD0/PCLKD0 Clock Gate 1 Registers */ | ||
| 108 | #define S5PC100_CLKGATE_D01_DMC (1<<0) | ||
| 109 | #define S5PC100_CLKGATE_D01_SROMC (1<<1) | ||
| 110 | #define S5PC100_CLKGATE_D01_ONENAND (1<<2) | ||
| 111 | #define S5PC100_CLKGATE_D01_NFCON (1<<3) | ||
| 112 | #define S5PC100_CLKGATE_D01_INTMEM (1<<4) | ||
| 113 | #define S5PC100_CLKGATE_D01_EBI (1<<5) | ||
| 114 | |||
| 115 | /* PCLKD0 Clock Gate 2 Registers */ | ||
| 116 | #define S5PC100_CLKGATE_D02_SECKEY (1<<1) | ||
| 117 | #define S5PC100_CLKGATE_D02_SDM (1<<2) | ||
| 118 | |||
| 119 | /* HCLKD1/PCLKD1 Clock Gate 0 Registers */ | ||
| 120 | #define S5PC100_CLKGATE_D10_PDMA0 (1<<0) | ||
| 121 | #define S5PC100_CLKGATE_D10_PDMA1 (1<<1) | ||
| 122 | #define S5PC100_CLKGATE_D10_USBHOST (1<<2) | ||
| 123 | #define S5PC100_CLKGATE_D10_USBOTG (1<<3) | ||
| 124 | #define S5PC100_CLKGATE_D10_MODEMIF (1<<4) | ||
| 125 | #define S5PC100_CLKGATE_D10_HSMMC0 (1<<5) | ||
| 126 | #define S5PC100_CLKGATE_D10_HSMMC1 (1<<6) | ||
| 127 | #define S5PC100_CLKGATE_D10_HSMMC2 (1<<7) | ||
| 128 | |||
| 129 | /* HCLKD1/PCLKD1 Clock Gate 1 Registers */ | ||
| 130 | #define S5PC100_CLKGATE_D11_LCD (1<<0) | ||
| 131 | #define S5PC100_CLKGATE_D11_ROTATOR (1<<1) | ||
| 132 | #define S5PC100_CLKGATE_D11_FIMC0 (1<<2) | ||
| 133 | #define S5PC100_CLKGATE_D11_FIMC1 (1<<3) | ||
| 134 | #define S5PC100_CLKGATE_D11_FIMC2 (1<<4) | ||
| 135 | #define S5PC100_CLKGATE_D11_JPEG (1<<5) | ||
| 136 | #define S5PC100_CLKGATE_D11_DSI (1<<6) | ||
| 137 | #define S5PC100_CLKGATE_D11_CSI (1<<7) | ||
| 138 | #define S5PC100_CLKGATE_D11_G3D (1<<8) | ||
| 139 | |||
| 140 | /* HCLKD1/PCLKD1 Clock Gate 2 Registers */ | ||
| 141 | #define S5PC100_CLKGATE_D12_TV (1<<0) | ||
| 142 | #define S5PC100_CLKGATE_D12_VP (1<<1) | ||
| 143 | #define S5PC100_CLKGATE_D12_MIXER (1<<2) | ||
| 144 | #define S5PC100_CLKGATE_D12_HDMI (1<<3) | ||
| 145 | #define S5PC100_CLKGATE_D12_MFC (1<<4) | ||
| 146 | |||
| 147 | /* HCLKD1/PCLKD1 Clock Gate 3 Registers */ | ||
| 148 | #define S5PC100_CLKGATE_D13_CHIPID (1<<0) | ||
| 149 | #define S5PC100_CLKGATE_D13_GPIO (1<<1) | ||
| 150 | #define S5PC100_CLKGATE_D13_APC (1<<2) | ||
| 151 | #define S5PC100_CLKGATE_D13_IEC (1<<3) | ||
| 152 | #define S5PC100_CLKGATE_D13_PWM (1<<6) | ||
| 153 | #define S5PC100_CLKGATE_D13_SYSTIMER (1<<7) | ||
| 154 | #define S5PC100_CLKGATE_D13_WDT (1<<8) | ||
| 155 | #define S5PC100_CLKGATE_D13_RTC (1<<9) | ||
| 156 | |||
| 157 | /* HCLKD1/PCLKD1 Clock Gate 4 Registers */ | ||
| 158 | #define S5PC100_CLKGATE_D14_UART0 (1<<0) | ||
| 159 | #define S5PC100_CLKGATE_D14_UART1 (1<<1) | ||
| 160 | #define S5PC100_CLKGATE_D14_UART2 (1<<2) | ||
| 161 | #define S5PC100_CLKGATE_D14_UART3 (1<<3) | ||
| 162 | #define S5PC100_CLKGATE_D14_IIC (1<<4) | ||
| 163 | #define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5) | ||
| 164 | #define S5PC100_CLKGATE_D14_SPI0 (1<<6) | ||
| 165 | #define S5PC100_CLKGATE_D14_SPI1 (1<<7) | ||
| 166 | #define S5PC100_CLKGATE_D14_SPI2 (1<<8) | ||
| 167 | #define S5PC100_CLKGATE_D14_IRDA (1<<9) | ||
| 168 | #define S5PC100_CLKGATE_D14_CCAN0 (1<<10) | ||
| 169 | #define S5PC100_CLKGATE_D14_CCAN1 (1<<11) | ||
| 170 | #define S5PC100_CLKGATE_D14_HSITX (1<<12) | ||
| 171 | #define S5PC100_CLKGATE_D14_HSIRX (1<<13) | ||
| 172 | |||
| 173 | /* HCLKD1/PCLKD1 Clock Gate 5 Registers */ | ||
| 174 | #define S5PC100_CLKGATE_D15_IIS0 (1<<0) | ||
| 175 | #define S5PC100_CLKGATE_D15_IIS1 (1<<1) | ||
| 176 | #define S5PC100_CLKGATE_D15_IIS2 (1<<2) | ||
| 177 | #define S5PC100_CLKGATE_D15_AC97 (1<<3) | ||
| 178 | #define S5PC100_CLKGATE_D15_PCM0 (1<<4) | ||
| 179 | #define S5PC100_CLKGATE_D15_PCM1 (1<<5) | ||
| 180 | #define S5PC100_CLKGATE_D15_SPDIF (1<<6) | ||
| 181 | #define S5PC100_CLKGATE_D15_TSADC (1<<7) | ||
| 182 | #define S5PC100_CLKGATE_D15_KEYIF (1<<8) | ||
| 183 | #define S5PC100_CLKGATE_D15_CG (1<<9) | ||
| 184 | |||
| 185 | /* HCLKD2 Clock Gate 0 Registers */ | ||
| 186 | #define S5PC100_CLKGATE_D20_HCLKD2 (1<<0) | ||
| 187 | #define S5PC100_CLKGATE_D20_I2SD2 (1<<1) | ||
| 188 | |||
| 189 | /* Special Clock Gate 0 Registers */ | ||
| 190 | #define S5PC100_CLKGATE_SCLK0_HPM (1<<0) | ||
| 191 | #define S5PC100_CLKGATE_SCLK0_PWI (1<<1) | ||
| 192 | #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2) | ||
| 193 | #define S5PC100_CLKGATE_SCLK0_UART (1<<3) | ||
| 194 | #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4) | ||
| 195 | #define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5) | ||
| 196 | #define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6) | ||
| 197 | #define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7) | ||
| 198 | #define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8) | ||
| 199 | #define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9) | ||
| 200 | #define S5PC100_CLKGATE_SCLK0_IRDA (1<<10) | ||
| 201 | #define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11) | ||
| 202 | #define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12) | ||
| 203 | #define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13) | ||
| 204 | #define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14) | ||
| 205 | #define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15) | ||
| 206 | #define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16) | ||
| 207 | #define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17) | ||
| 208 | |||
| 209 | /* Special Clock Gate 1 Registers */ | ||
| 210 | #define S5PC100_CLKGATE_SCLK1_LCD (1<<0) | ||
| 211 | #define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1) | ||
| 212 | #define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2) | ||
| 213 | #define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3) | ||
| 214 | #define S5PC100_CLKGATE_SCLK1_TV54 (1<<4) | ||
| 215 | #define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5) | ||
| 216 | #define S5PC100_CLKGATE_SCLK1_MIXER (1<<6) | ||
| 217 | #define S5PC100_CLKGATE_SCLK1_HDMI (1<<7) | ||
| 218 | #define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8) | ||
| 219 | #define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9) | ||
| 220 | #define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10) | ||
| 221 | #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11) | ||
| 222 | #define S5PC100_CLKGATE_SCLK1_CAM (1<<12) | ||
| 223 | |||
| 224 | #define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000) | ||
| 225 | #define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008) | ||
| 226 | #define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100) | ||
| 227 | #define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104) | ||
| 228 | #define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200) | ||
| 229 | #define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300) | ||
| 230 | #define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304) | ||
| 231 | #define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308) | ||
| 232 | #define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400) | ||
| 233 | #define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414) | ||
| 234 | #define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420) | ||
| 235 | |||
| 236 | #define S5PC100_SWRESET_RESETVAL 0xc100 | ||
| 237 | #define S5PC100_OTHER_SYS_INT 24 | ||
| 238 | #define S5PC100_OTHER_STA_TYPE 23 | ||
| 239 | #define STA_TYPE_EXPON 0 | ||
| 240 | #define STA_TYPE_SFR 1 | ||
| 241 | |||
| 242 | #define S5PC100_SLEEP_CFG_OSC_EN 0 | ||
| 243 | |||
| 244 | /* OTHERS Resgister */ | ||
| 245 | #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16) | ||
| 246 | #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28) | ||
| 247 | |||
| 248 | /* MIPI D-PHY Control Register 0 */ | ||
| 249 | #define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1) | ||
| 250 | #define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0) | ||
| 251 | |||
| 252 | #endif /* _PLAT_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h b/arch/arm/plat-s5pc1xx/include/plat/regs-power.h deleted file mode 100644 index 02ffa491b53a..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/regs-power.h +++ /dev/null | |||
| @@ -1,84 +0,0 @@ | |||
| 1 | /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Jongse Won <jongse.won@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX clock register definitions | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __ASM_ARM_REGS_PWR | ||
| 14 | #define __ASM_ARM_REGS_PWR __FILE__ | ||
| 15 | |||
| 16 | #define S5PC1XX_PWRREG(x) (S5PC1XX_VA_PWR + (x)) | ||
| 17 | |||
| 18 | /* s5pc100 (0xE0108000) register for power management */ | ||
| 19 | #define S5PC100_PWR_CFG S5PC1XX_PWRREG(0x0) | ||
| 20 | #define S5PC100_EINT_WAKEUP_MASK S5PC1XX_PWRREG(0x4) | ||
| 21 | #define S5PC100_NORMAL_CFG S5PC1XX_PWRREG(0x10) | ||
| 22 | #define S5PC100_STOP_CFG S5PC1XX_PWRREG(0x14) | ||
| 23 | #define S5PC100_SLEEP_CFG S5PC1XX_PWRREG(0x18) | ||
| 24 | #define S5PC100_STOP_MEM_CFG S5PC1XX_PWRREG(0x1C) | ||
| 25 | #define S5PC100_OSC_FREQ S5PC1XX_PWRREG(0x100) | ||
| 26 | #define S5PC100_OSC_STABLE S5PC1XX_PWRREG(0x104) | ||
| 27 | #define S5PC100_PWR_STABLE S5PC1XX_PWRREG(0x108) | ||
| 28 | #define S5PC100_MTC_STABLE S5PC1XX_PWRREG(0x110) | ||
| 29 | #define S5PC100_CLAMP_STABLE S5PC1XX_PWRREG(0x114) | ||
| 30 | #define S5PC100_OTHERS S5PC1XX_PWRREG(0x200) | ||
| 31 | #define S5PC100_RST_STAT S5PC1XX_PWRREG(0x300) | ||
| 32 | #define S5PC100_WAKEUP_STAT S5PC1XX_PWRREG(0x304) | ||
| 33 | #define S5PC100_BLK_PWR_STAT S5PC1XX_PWRREG(0x308) | ||
| 34 | #define S5PC100_INFORM0 S5PC1XX_PWRREG(0x400) | ||
| 35 | #define S5PC100_INFORM1 S5PC1XX_PWRREG(0x404) | ||
| 36 | #define S5PC100_INFORM2 S5PC1XX_PWRREG(0x408) | ||
| 37 | #define S5PC100_INFORM3 S5PC1XX_PWRREG(0x40C) | ||
| 38 | #define S5PC100_INFORM4 S5PC1XX_PWRREG(0x410) | ||
| 39 | #define S5PC100_INFORM5 S5PC1XX_PWRREG(0x414) | ||
| 40 | #define S5PC100_INFORM6 S5PC1XX_PWRREG(0x418) | ||
| 41 | #define S5PC100_INFORM7 S5PC1XX_PWRREG(0x41C) | ||
| 42 | #define S5PC100_DCGIDX_MAP0 S5PC1XX_PWRREG(0x500) | ||
| 43 | #define S5PC100_DCGIDX_MAP1 S5PC1XX_PWRREG(0x504) | ||
| 44 | #define S5PC100_DCGIDX_MAP2 S5PC1XX_PWRREG(0x508) | ||
| 45 | #define S5PC100_DCGPERF_MAP0 S5PC1XX_PWRREG(0x50C) | ||
| 46 | #define S5PC100_DCGPERF_MAP1 S5PC1XX_PWRREG(0x510) | ||
| 47 | #define S5PC100_DVCIDX_MAP S5PC1XX_PWRREG(0x514) | ||
| 48 | #define S5PC100_FREQ_CPU S5PC1XX_PWRREG(0x518) | ||
| 49 | #define S5PC100_FREQ_DPM S5PC1XX_PWRREG(0x51C) | ||
| 50 | #define S5PC100_DVSEMCLK_EN S5PC1XX_PWRREG(0x520) | ||
| 51 | #define S5PC100_APLL_CON_L8 S5PC1XX_PWRREG(0x600) | ||
| 52 | #define S5PC100_APLL_CON_L7 S5PC1XX_PWRREG(0x604) | ||
| 53 | #define S5PC100_APLL_CON_L6 S5PC1XX_PWRREG(0x608) | ||
| 54 | #define S5PC100_APLL_CON_L5 S5PC1XX_PWRREG(0x60C) | ||
| 55 | #define S5PC100_APLL_CON_L4 S5PC1XX_PWRREG(0x610) | ||
| 56 | #define S5PC100_APLL_CON_L3 S5PC1XX_PWRREG(0x614) | ||
| 57 | #define S5PC100_APLL_CON_L2 S5PC1XX_PWRREG(0x618) | ||
| 58 | #define S5PC100_APLL_CON_L1 S5PC1XX_PWRREG(0x61C) | ||
| 59 | #define S5PC100_IEM_CONTROL S5PC1XX_PWRREG(0x620) | ||
| 60 | #define S5PC100_CLKDIV_IEM_L8 S5PC1XX_PWRREG(0x700) | ||
| 61 | #define S5PC100_CLKDIV_IEM_L7 S5PC1XX_PWRREG(0x704) | ||
| 62 | #define S5PC100_CLKDIV_IEM_L6 S5PC1XX_PWRREG(0x708) | ||
| 63 | #define S5PC100_CLKDIV_IEM_L5 S5PC1XX_PWRREG(0x70C) | ||
| 64 | #define S5PC100_CLKDIV_IEM_L4 S5PC1XX_PWRREG(0x710) | ||
| 65 | #define S5PC100_CLKDIV_IEM_L3 S5PC1XX_PWRREG(0x714) | ||
| 66 | #define S5PC100_CLKDIV_IEM_L2 S5PC1XX_PWRREG(0x718) | ||
| 67 | #define S5PC100_CLKDIV_IEM_L1 S5PC1XX_PWRREG(0x71C) | ||
| 68 | #define S5PC100_IEM_HPMCLK_DIV S5PC1XX_PWRREG(0x724) | ||
| 69 | |||
| 70 | /* PWR_CFG */ | ||
| 71 | #define S5PC100_PWRCFG_CFG_DEEP_IDLE (1 << 31) | ||
| 72 | #define S5PC100_PWRCFG_CFG_WFI_MASK (3 << 5) | ||
| 73 | #define S5PC100_PWRCFG_CFG_WFI_IDLE (0 << 5) | ||
| 74 | #define S5PC100_PWRCFG_CFG_WFI_DEEP_IDLE (1 << 5) | ||
| 75 | #define S5PC100_PWRCFG_CFG_WFI_STOP (2 << 5) | ||
| 76 | #define S5PC100_PWRCFG_CFG_WFI_SLEEP (3 << 5) | ||
| 77 | |||
| 78 | /* SLEEP_CFG */ | ||
| 79 | #define S5PC100_SLEEP_OSC_EN_SLEEP (1 << 0) | ||
| 80 | |||
| 81 | /* OTHERS */ | ||
| 82 | #define S5PC100_PMU_INT_DISABLE (1 << 24) | ||
| 83 | |||
| 84 | #endif /* __ASM_ARM_REGS_PWR */ | ||
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h deleted file mode 100644 index 2531f34a56f3..000000000000 --- a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h +++ /dev/null | |||
| @@ -1,64 +0,0 @@ | |||
| 1 | /* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * Header file for s5pc100 cpu support | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/include/plat/s3c6400.h | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* Common init code for S5PC100 related SoCs */ | ||
| 16 | extern int s5pc100_init(void); | ||
| 17 | extern void s5pc100_map_io(void); | ||
| 18 | extern void s5pc100_init_clocks(int xtal); | ||
| 19 | extern int s5pc100_register_baseclocks(unsigned long xtal); | ||
| 20 | extern void s5pc100_init_irq(void); | ||
| 21 | extern void s5pc100_init_io(struct map_desc *mach_desc, int size); | ||
| 22 | extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
| 23 | extern void s5pc100_register_clocks(void); | ||
| 24 | extern void s5pc100_setup_clocks(void); | ||
| 25 | extern struct sysdev_class s5pc100_sysclass; | ||
| 26 | |||
| 27 | #define s5pc100_init_uarts s5pc100_common_init_uarts | ||
| 28 | |||
| 29 | /* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */ | ||
| 30 | extern void s5pc1xx_init_irq(u32 *vic_valid, int num); | ||
| 31 | extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size); | ||
| 32 | |||
| 33 | /* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */ | ||
| 34 | extern struct clk clk_hpll; | ||
| 35 | extern struct clk clk_hd0; | ||
| 36 | extern struct clk clk_pd0; | ||
| 37 | extern struct clk clk_54m; | ||
| 38 | extern void s5pc1xx_register_clocks(void); | ||
| 39 | extern int s5pc100_sclk0_ctrl(struct clk *clk, int enable); | ||
| 40 | extern int s5pc100_sclk1_ctrl(struct clk *clk, int enable); | ||
| 41 | |||
| 42 | /* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */ | ||
| 43 | extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[]; | ||
| 44 | extern struct platform_device s3c_device_g2d; | ||
| 45 | extern struct platform_device s3c_device_g3d; | ||
| 46 | extern struct platform_device s3c_device_vpp; | ||
| 47 | extern struct platform_device s3c_device_tvenc; | ||
| 48 | extern struct platform_device s3c_device_tvscaler; | ||
| 49 | extern struct platform_device s3c_device_rotator; | ||
| 50 | extern struct platform_device s3c_device_jpeg; | ||
| 51 | extern struct platform_device s3c_device_onenand; | ||
| 52 | extern struct platform_device s3c_device_usb_otghcd; | ||
| 53 | extern struct platform_device s3c_device_keypad; | ||
| 54 | extern struct platform_device s3c_device_ts; | ||
| 55 | extern struct platform_device s3c_device_g3d; | ||
| 56 | extern struct platform_device s3c_device_smc911x; | ||
| 57 | extern struct platform_device s3c_device_fimc0; | ||
| 58 | extern struct platform_device s3c_device_fimc1; | ||
| 59 | extern struct platform_device s3c_device_mfc; | ||
| 60 | extern struct platform_device s3c_device_ac97; | ||
| 61 | extern struct platform_device s3c_device_fimc0; | ||
| 62 | extern struct platform_device s3c_device_fimc1; | ||
| 63 | extern struct platform_device s3c_device_fimc2; | ||
| 64 | |||
diff --git a/arch/arm/plat-s5pc1xx/irq-eint.c b/arch/arm/plat-s5pc1xx/irq-eint.c deleted file mode 100644 index 373122f57d56..000000000000 --- a/arch/arm/plat-s5pc1xx/irq-eint.c +++ /dev/null | |||
| @@ -1,281 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-s5pc1xx/irq-eint.c | ||
| 3 | * | ||
| 4 | * Copyright 2009 Samsung Electronics Co. | ||
| 5 | * Byungho Min <bhmin@samsung.com> | ||
| 6 | * Kyungin Park <kyungmin.park@samsung.com> | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/irq-eint.c | ||
| 9 | * | ||
| 10 | * S5PC1XX - Interrupt handling for IRQ_EINT(x) | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | #include <linux/sysdev.h> | ||
| 22 | #include <linux/pm.h> | ||
| 23 | #include <linux/gpio.h> | ||
| 24 | |||
| 25 | #include <asm/hardware/vic.h> | ||
| 26 | |||
| 27 | #include <mach/map.h> | ||
| 28 | |||
| 29 | #include <plat/gpio-cfg.h> | ||
| 30 | #include <plat/gpio-ext.h> | ||
| 31 | #include <plat/pm.h> | ||
| 32 | #include <plat/regs-gpio.h> | ||
| 33 | #include <plat/regs-irqtype.h> | ||
| 34 | |||
| 35 | /* | ||
| 36 | * bank is a group of external interrupt | ||
| 37 | * bank0 means EINT0 ... EINT7 | ||
| 38 | * bank1 means EINT8 ... EINT15 | ||
| 39 | * bank2 means EINT16 ... EINT23 | ||
| 40 | * bank3 means EINT24 ... EINT31 | ||
| 41 | */ | ||
| 42 | |||
| 43 | static inline int s3c_get_eint(unsigned int irq) | ||
| 44 | { | ||
| 45 | int real; | ||
| 46 | |||
| 47 | if (irq < IRQ_EINT16_31) | ||
| 48 | real = (irq - IRQ_EINT0); | ||
| 49 | else | ||
| 50 | real = (irq - S3C_IRQ_EINT_BASE) + IRQ_EINT16_31 - IRQ_EINT0; | ||
| 51 | |||
| 52 | return real; | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline int s3c_get_bank(unsigned int irq) | ||
| 56 | { | ||
| 57 | return s3c_get_eint(irq) >> 3; | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline int s3c_eint_to_bit(unsigned int irq) | ||
| 61 | { | ||
| 62 | int real, bit; | ||
| 63 | |||
| 64 | real = s3c_get_eint(irq); | ||
| 65 | bit = 1 << (real & (8 - 1)); | ||
| 66 | |||
| 67 | return bit; | ||
| 68 | } | ||
| 69 | |||
| 70 | static inline void s3c_irq_eint_mask(unsigned int irq) | ||
| 71 | { | ||
| 72 | u32 mask; | ||
| 73 | u32 bank = s3c_get_bank(irq); | ||
| 74 | |||
| 75 | mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 76 | mask |= s3c_eint_to_bit(irq); | ||
| 77 | __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 78 | } | ||
| 79 | |||
| 80 | static void s3c_irq_eint_unmask(unsigned int irq) | ||
| 81 | { | ||
| 82 | u32 mask; | ||
| 83 | u32 bank = s3c_get_bank(irq); | ||
| 84 | |||
| 85 | mask = __raw_readl(S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 86 | mask &= ~(s3c_eint_to_bit(irq)); | ||
| 87 | __raw_writel(mask, S5PC1XX_WKUP_INT_MASK(bank)); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline void s3c_irq_eint_ack(unsigned int irq) | ||
| 91 | { | ||
| 92 | u32 bank = s3c_get_bank(irq); | ||
| 93 | |||
| 94 | __raw_writel(s3c_eint_to_bit(irq), S5PC1XX_WKUP_INT_PEND(bank)); | ||
| 95 | } | ||
| 96 | |||
| 97 | static void s3c_irq_eint_maskack(unsigned int irq) | ||
| 98 | { | ||
| 99 | /* compiler should in-line these */ | ||
| 100 | s3c_irq_eint_mask(irq); | ||
| 101 | s3c_irq_eint_ack(irq); | ||
| 102 | } | ||
| 103 | |||
| 104 | static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type) | ||
| 105 | { | ||
| 106 | u32 bank = s3c_get_bank(irq); | ||
| 107 | int real = s3c_get_eint(irq); | ||
| 108 | int gpio, shift, sfn; | ||
| 109 | u32 ctrl, con = 0; | ||
| 110 | |||
| 111 | switch (type) { | ||
| 112 | case IRQ_TYPE_NONE: | ||
| 113 | printk(KERN_WARNING "No edge setting!\n"); | ||
| 114 | break; | ||
| 115 | |||
| 116 | case IRQ_TYPE_EDGE_RISING: | ||
| 117 | con = S5PC1XX_WKUP_INT_RISEEDGE; | ||
| 118 | break; | ||
| 119 | |||
| 120 | case IRQ_TYPE_EDGE_FALLING: | ||
| 121 | con = S5PC1XX_WKUP_INT_FALLEDGE; | ||
| 122 | break; | ||
| 123 | |||
| 124 | case IRQ_TYPE_EDGE_BOTH: | ||
| 125 | con = S5PC1XX_WKUP_INT_BOTHEDGE; | ||
| 126 | break; | ||
| 127 | |||
| 128 | case IRQ_TYPE_LEVEL_LOW: | ||
| 129 | con = S5PC1XX_WKUP_INT_LOWLEV; | ||
| 130 | break; | ||
| 131 | |||
| 132 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 133 | con = S5PC1XX_WKUP_INT_HILEV; | ||
| 134 | break; | ||
| 135 | |||
| 136 | default: | ||
| 137 | printk(KERN_ERR "No such irq type %d", type); | ||
| 138 | return -EINVAL; | ||
| 139 | } | ||
| 140 | |||
| 141 | gpio = real & (8 - 1); | ||
| 142 | shift = gpio << 2; | ||
| 143 | |||
| 144 | ctrl = __raw_readl(S5PC1XX_WKUP_INT_CON(bank)); | ||
| 145 | ctrl &= ~(0x7 << shift); | ||
| 146 | ctrl |= con << shift; | ||
| 147 | __raw_writel(ctrl, S5PC1XX_WKUP_INT_CON(bank)); | ||
| 148 | |||
| 149 | switch (real) { | ||
| 150 | case 0 ... 7: | ||
| 151 | gpio = S5PC100_GPH0(gpio); | ||
| 152 | break; | ||
| 153 | case 8 ... 15: | ||
| 154 | gpio = S5PC100_GPH1(gpio); | ||
| 155 | break; | ||
| 156 | case 16 ... 23: | ||
| 157 | gpio = S5PC100_GPH2(gpio); | ||
| 158 | break; | ||
| 159 | case 24 ... 31: | ||
| 160 | gpio = S5PC100_GPH3(gpio); | ||
| 161 | break; | ||
| 162 | default: | ||
| 163 | return -EINVAL; | ||
| 164 | } | ||
| 165 | |||
| 166 | sfn = S3C_GPIO_SFN(0x2); | ||
| 167 | s3c_gpio_cfgpin(gpio, sfn); | ||
| 168 | |||
| 169 | return 0; | ||
| 170 | } | ||
| 171 | |||
| 172 | static struct irq_chip s3c_irq_eint = { | ||
| 173 | .name = "EINT", | ||
| 174 | .mask = s3c_irq_eint_mask, | ||
| 175 | .unmask = s3c_irq_eint_unmask, | ||
| 176 | .mask_ack = s3c_irq_eint_maskack, | ||
| 177 | .ack = s3c_irq_eint_ack, | ||
| 178 | .set_type = s3c_irq_eint_set_type, | ||
| 179 | .set_wake = s3c_irqext_wake, | ||
| 180 | }; | ||
| 181 | |||
| 182 | /* s3c_irq_demux_eint | ||
| 183 | * | ||
| 184 | * This function demuxes the IRQ from external interrupts, | ||
| 185 | * from IRQ_EINT(16) to IRQ_EINT(31). It is designed to be inlined into | ||
| 186 | * the specific handlers s3c_irq_demux_eintX_Y. | ||
| 187 | */ | ||
| 188 | static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end) | ||
| 189 | { | ||
| 190 | u32 status = __raw_readl(S5PC1XX_WKUP_INT_PEND((start >> 3))); | ||
| 191 | u32 mask = __raw_readl(S5PC1XX_WKUP_INT_MASK((start >> 3))); | ||
| 192 | unsigned int irq; | ||
| 193 | |||
| 194 | status &= ~mask; | ||
| 195 | status &= (1 << (end - start + 1)) - 1; | ||
| 196 | |||
| 197 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | ||
| 198 | if (status & 1) | ||
| 199 | generic_handle_irq(irq); | ||
| 200 | |||
| 201 | status >>= 1; | ||
| 202 | } | ||
| 203 | } | ||
| 204 | |||
| 205 | static void s3c_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) | ||
| 206 | { | ||
| 207 | s3c_irq_demux_eint(16, 23); | ||
| 208 | s3c_irq_demux_eint(24, 31); | ||
| 209 | } | ||
| 210 | |||
| 211 | /* | ||
| 212 | * Handle EINT0 ... EINT15 at VIC directly | ||
| 213 | */ | ||
| 214 | static void s3c_irq_vic_eint_mask(unsigned int irq) | ||
| 215 | { | ||
| 216 | void __iomem *base = get_irq_chip_data(irq); | ||
| 217 | unsigned int real; | ||
| 218 | |||
| 219 | s3c_irq_eint_mask(irq); | ||
| 220 | real = s3c_get_eint(irq); | ||
| 221 | writel(1 << real, base + VIC_INT_ENABLE_CLEAR); | ||
| 222 | } | ||
| 223 | |||
| 224 | static void s3c_irq_vic_eint_unmask(unsigned int irq) | ||
| 225 | { | ||
| 226 | void __iomem *base = get_irq_chip_data(irq); | ||
| 227 | unsigned int real; | ||
| 228 | |||
| 229 | s3c_irq_eint_unmask(irq); | ||
| 230 | real = s3c_get_eint(irq); | ||
| 231 | writel(1 << real, base + VIC_INT_ENABLE); | ||
| 232 | } | ||
| 233 | |||
| 234 | static inline void s3c_irq_vic_eint_ack(unsigned int irq) | ||
| 235 | { | ||
| 236 | u32 bit; | ||
| 237 | u32 bank = s3c_get_bank(irq); | ||
| 238 | |||
| 239 | bit = s3c_eint_to_bit(irq); | ||
| 240 | __raw_writel(bit, S5PC1XX_WKUP_INT_PEND(bank)); | ||
| 241 | } | ||
| 242 | |||
| 243 | static void s3c_irq_vic_eint_maskack(unsigned int irq) | ||
| 244 | { | ||
| 245 | /* compiler should in-line these */ | ||
| 246 | s3c_irq_vic_eint_mask(irq); | ||
| 247 | s3c_irq_vic_eint_ack(irq); | ||
| 248 | } | ||
| 249 | |||
| 250 | static struct irq_chip s3c_irq_vic_eint = { | ||
| 251 | .name = "EINT", | ||
| 252 | .mask = s3c_irq_vic_eint_mask, | ||
| 253 | .unmask = s3c_irq_vic_eint_unmask, | ||
| 254 | .mask_ack = s3c_irq_vic_eint_maskack, | ||
| 255 | .ack = s3c_irq_vic_eint_ack, | ||
| 256 | .set_type = s3c_irq_eint_set_type, | ||
| 257 | .set_wake = s3c_irqext_wake, | ||
| 258 | }; | ||
| 259 | |||
| 260 | static int __init s5pc1xx_init_irq_eint(void) | ||
| 261 | { | ||
| 262 | int irq; | ||
| 263 | |||
| 264 | for (irq = IRQ_EINT0; irq <= IRQ_EINT15; irq++) { | ||
| 265 | set_irq_chip(irq, &s3c_irq_vic_eint); | ||
| 266 | set_irq_handler(irq, handle_level_irq); | ||
| 267 | set_irq_flags(irq, IRQF_VALID); | ||
| 268 | } | ||
| 269 | |||
| 270 | for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { | ||
| 271 | set_irq_chip(irq, &s3c_irq_eint); | ||
| 272 | set_irq_handler(irq, handle_level_irq); | ||
| 273 | set_irq_flags(irq, IRQF_VALID); | ||
| 274 | } | ||
| 275 | |||
| 276 | set_irq_chained_handler(IRQ_EINT16_31, s3c_irq_demux_eint16_31); | ||
| 277 | |||
| 278 | return 0; | ||
| 279 | } | ||
| 280 | |||
| 281 | arch_initcall(s5pc1xx_init_irq_eint); | ||
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c deleted file mode 100644 index bfc524827819..000000000000 --- a/arch/arm/plat-s5pc1xx/irq.c +++ /dev/null | |||
| @@ -1,75 +0,0 @@ | |||
| 1 | /* arch/arm/plat-s5pc1xx/irq.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC1XX - Interrupt handling | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/irq.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/irq.h> | ||
| 18 | #include <linux/io.h> | ||
| 19 | |||
| 20 | #include <asm/hardware/vic.h> | ||
| 21 | |||
| 22 | #include <mach/map.h> | ||
| 23 | #include <plat/irq-vic-timer.h> | ||
| 24 | #include <plat/irq-uart.h> | ||
| 25 | #include <plat/cpu.h> | ||
| 26 | |||
| 27 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | ||
| 28 | * are consecutive when looking up the interrupt in the demux routines. | ||
| 29 | */ | ||
| 30 | static struct s3c_uart_irq uart_irqs[] = { | ||
| 31 | [0] = { | ||
| 32 | .regs = (void *)S3C_VA_UART0, | ||
| 33 | .base_irq = IRQ_S3CUART_BASE0, | ||
| 34 | .parent_irq = IRQ_UART0, | ||
| 35 | }, | ||
| 36 | [1] = { | ||
| 37 | .regs = (void *)S3C_VA_UART1, | ||
| 38 | .base_irq = IRQ_S3CUART_BASE1, | ||
| 39 | .parent_irq = IRQ_UART1, | ||
| 40 | }, | ||
| 41 | [2] = { | ||
| 42 | .regs = (void *)S3C_VA_UART2, | ||
| 43 | .base_irq = IRQ_S3CUART_BASE2, | ||
| 44 | .parent_irq = IRQ_UART2, | ||
| 45 | }, | ||
| 46 | [3] = { | ||
| 47 | .regs = (void *)S3C_VA_UART3, | ||
| 48 | .base_irq = IRQ_S3CUART_BASE3, | ||
| 49 | .parent_irq = IRQ_UART3, | ||
| 50 | }, | ||
| 51 | }; | ||
| 52 | |||
| 53 | void __init s5pc1xx_init_irq(u32 *vic_valid, int num) | ||
| 54 | { | ||
| 55 | int i; | ||
| 56 | |||
| 57 | printk(KERN_DEBUG "%s: initialising interrupts\n", __func__); | ||
| 58 | |||
| 59 | /* initialise the pair of VICs */ | ||
| 60 | for (i = 0; i < num; i++) | ||
| 61 | vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET), | ||
| 62 | vic_valid[i], 0); | ||
| 63 | |||
| 64 | /* add the timer sub-irqs */ | ||
| 65 | |||
| 66 | s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0); | ||
| 67 | s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1); | ||
| 68 | s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2); | ||
| 69 | s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3); | ||
| 70 | s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4); | ||
| 71 | |||
| 72 | s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs)); | ||
| 73 | } | ||
| 74 | |||
| 75 | |||
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c deleted file mode 100644 index 2bf6c57a96a2..000000000000 --- a/arch/arm/plat-s5pc1xx/s5pc100-clock.c +++ /dev/null | |||
| @@ -1,876 +0,0 @@ | |||
| 1 | /* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c | ||
| 2 | * | ||
| 3 | * Copyright 2009 Samsung Electronics, Co. | ||
| 4 | * Byungho Min <bhmin@samsung.com> | ||
| 5 | * | ||
| 6 | * S5PC100 based common clock support | ||
| 7 | * | ||
| 8 | * Based on plat-s3c64xx/s3c6400-clock.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/list.h> | ||
| 19 | #include <linux/errno.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/sysdev.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <mach/map.h> | ||
| 27 | |||
| 28 | #include <plat/cpu-freq.h> | ||
| 29 | |||
| 30 | #include <plat/regs-clock.h> | ||
| 31 | #include <plat/clock.h> | ||
| 32 | #include <plat/clock-clksrc.h> | ||
| 33 | #include <plat/cpu.h> | ||
| 34 | #include <plat/pll.h> | ||
| 35 | #include <plat/devs.h> | ||
| 36 | #include <plat/s5pc100.h> | ||
| 37 | |||
| 38 | /* fin_apll, fin_mpll and fin_epll are all the same clock, which we call | ||
| 39 | * ext_xtal_mux for want of an actual name from the manual. | ||
| 40 | */ | ||
| 41 | |||
| 42 | static struct clk clk_ext_xtal_mux = { | ||
| 43 | .name = "ext_xtal", | ||
| 44 | .id = -1, | ||
| 45 | }; | ||
| 46 | |||
| 47 | #define clk_fin_apll clk_ext_xtal_mux | ||
| 48 | #define clk_fin_mpll clk_ext_xtal_mux | ||
| 49 | #define clk_fin_epll clk_ext_xtal_mux | ||
| 50 | #define clk_fin_hpll clk_ext_xtal_mux | ||
| 51 | |||
| 52 | #define clk_fout_mpll clk_mpll | ||
| 53 | #define clk_vclk_54m clk_54m | ||
| 54 | |||
| 55 | /* APLL */ | ||
| 56 | static struct clk clk_fout_apll = { | ||
| 57 | .name = "fout_apll", | ||
| 58 | .id = -1, | ||
| 59 | .rate = 27000000, | ||
| 60 | }; | ||
| 61 | |||
| 62 | static struct clk *clk_src_apll_list[] = { | ||
| 63 | [0] = &clk_fin_apll, | ||
| 64 | [1] = &clk_fout_apll, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct clksrc_sources clk_src_apll = { | ||
| 68 | .sources = clk_src_apll_list, | ||
| 69 | .nr_sources = ARRAY_SIZE(clk_src_apll_list), | ||
| 70 | }; | ||
| 71 | |||
| 72 | static struct clksrc_clk clk_mout_apll = { | ||
| 73 | .clk = { | ||
| 74 | .name = "mout_apll", | ||
| 75 | .id = -1, | ||
| 76 | }, | ||
| 77 | .sources = &clk_src_apll, | ||
| 78 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 0, .size = 1, }, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static unsigned long s5pc100_clk_dout_apll_get_rate(struct clk *clk) | ||
| 82 | { | ||
| 83 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 84 | unsigned int ratio; | ||
| 85 | |||
| 86 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_APLL_MASK; | ||
| 87 | ratio >>= S5PC100_CLKDIV0_APLL_SHIFT; | ||
| 88 | |||
| 89 | return rate / (ratio + 1); | ||
| 90 | } | ||
| 91 | |||
| 92 | static struct clk clk_dout_apll = { | ||
| 93 | .name = "dout_apll", | ||
| 94 | .id = -1, | ||
| 95 | .parent = &clk_mout_apll.clk, | ||
| 96 | .ops = &(struct clk_ops) { | ||
| 97 | .get_rate = s5pc100_clk_dout_apll_get_rate, | ||
| 98 | }, | ||
| 99 | }; | ||
| 100 | |||
| 101 | static unsigned long s5pc100_clk_arm_get_rate(struct clk *clk) | ||
| 102 | { | ||
| 103 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 104 | unsigned int ratio; | ||
| 105 | |||
| 106 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_ARM_MASK; | ||
| 107 | ratio >>= S5PC100_CLKDIV0_ARM_SHIFT; | ||
| 108 | |||
| 109 | return rate / (ratio + 1); | ||
| 110 | } | ||
| 111 | |||
| 112 | static unsigned long s5pc100_clk_arm_round_rate(struct clk *clk, | ||
| 113 | unsigned long rate) | ||
| 114 | { | ||
| 115 | unsigned long parent = clk_get_rate(clk->parent); | ||
| 116 | u32 div; | ||
| 117 | |||
| 118 | if (parent < rate) | ||
| 119 | return rate; | ||
| 120 | |||
| 121 | div = (parent / rate) - 1; | ||
| 122 | if (div > S5PC100_CLKDIV0_ARM_MASK) | ||
| 123 | div = S5PC100_CLKDIV0_ARM_MASK; | ||
| 124 | |||
| 125 | return parent / (div + 1); | ||
| 126 | } | ||
| 127 | |||
| 128 | static int s5pc100_clk_arm_set_rate(struct clk *clk, unsigned long rate) | ||
| 129 | { | ||
| 130 | unsigned long parent = clk_get_rate(clk->parent); | ||
| 131 | u32 div; | ||
| 132 | u32 val; | ||
| 133 | |||
| 134 | if (rate < parent / (S5PC100_CLKDIV0_ARM_MASK + 1)) | ||
| 135 | return -EINVAL; | ||
| 136 | |||
| 137 | rate = clk_round_rate(clk, rate); | ||
| 138 | div = clk_get_rate(clk->parent) / rate; | ||
| 139 | |||
| 140 | val = __raw_readl(S5PC100_CLKDIV0); | ||
| 141 | val &= S5PC100_CLKDIV0_ARM_MASK; | ||
| 142 | val |= (div - 1); | ||
| 143 | __raw_writel(val, S5PC100_CLKDIV0); | ||
| 144 | |||
| 145 | return 0; | ||
| 146 | } | ||
| 147 | |||
| 148 | static struct clk clk_arm = { | ||
| 149 | .name = "armclk", | ||
| 150 | .id = -1, | ||
| 151 | .parent = &clk_dout_apll, | ||
| 152 | .ops = &(struct clk_ops) { | ||
| 153 | .get_rate = s5pc100_clk_arm_get_rate, | ||
| 154 | .set_rate = s5pc100_clk_arm_set_rate, | ||
| 155 | .round_rate = s5pc100_clk_arm_round_rate, | ||
| 156 | }, | ||
| 157 | }; | ||
| 158 | |||
| 159 | static unsigned long s5pc100_clk_dout_d0_bus_get_rate(struct clk *clk) | ||
| 160 | { | ||
| 161 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 162 | unsigned int ratio; | ||
| 163 | |||
| 164 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_D0_MASK; | ||
| 165 | ratio >>= S5PC100_CLKDIV0_D0_SHIFT; | ||
| 166 | |||
| 167 | return rate / (ratio + 1); | ||
| 168 | } | ||
| 169 | |||
| 170 | static struct clk clk_dout_d0_bus = { | ||
| 171 | .name = "dout_d0_bus", | ||
| 172 | .id = -1, | ||
| 173 | .parent = &clk_arm, | ||
| 174 | .ops = &(struct clk_ops) { | ||
| 175 | .get_rate = s5pc100_clk_dout_d0_bus_get_rate, | ||
| 176 | }, | ||
| 177 | }; | ||
| 178 | |||
| 179 | static unsigned long s5pc100_clk_dout_pclkd0_get_rate(struct clk *clk) | ||
| 180 | { | ||
| 181 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 182 | unsigned int ratio; | ||
| 183 | |||
| 184 | ratio = __raw_readl(S5PC100_CLKDIV0) & S5PC100_CLKDIV0_PCLKD0_MASK; | ||
| 185 | ratio >>= S5PC100_CLKDIV0_PCLKD0_SHIFT; | ||
| 186 | |||
| 187 | return rate / (ratio + 1); | ||
| 188 | } | ||
| 189 | |||
| 190 | static struct clk clk_dout_pclkd0 = { | ||
| 191 | .name = "dout_pclkd0", | ||
| 192 | .id = -1, | ||
| 193 | .parent = &clk_dout_d0_bus, | ||
| 194 | .ops = &(struct clk_ops) { | ||
| 195 | .get_rate = s5pc100_clk_dout_pclkd0_get_rate, | ||
| 196 | }, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static unsigned long s5pc100_clk_dout_apll2_get_rate(struct clk *clk) | ||
| 200 | { | ||
| 201 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 202 | unsigned int ratio; | ||
| 203 | |||
| 204 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_APLL2_MASK; | ||
| 205 | ratio >>= S5PC100_CLKDIV1_APLL2_SHIFT; | ||
| 206 | |||
| 207 | return rate / (ratio + 1); | ||
| 208 | } | ||
| 209 | |||
| 210 | static struct clk clk_dout_apll2 = { | ||
| 211 | .name = "dout_apll2", | ||
| 212 | .id = -1, | ||
| 213 | .parent = &clk_mout_apll.clk, | ||
| 214 | .ops = &(struct clk_ops) { | ||
| 215 | .get_rate = s5pc100_clk_dout_apll2_get_rate, | ||
| 216 | }, | ||
| 217 | }; | ||
| 218 | |||
| 219 | /* MPLL */ | ||
| 220 | static struct clk *clk_src_mpll_list[] = { | ||
| 221 | [0] = &clk_fin_mpll, | ||
| 222 | [1] = &clk_fout_mpll, | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct clksrc_sources clk_src_mpll = { | ||
| 226 | .sources = clk_src_mpll_list, | ||
| 227 | .nr_sources = ARRAY_SIZE(clk_src_mpll_list), | ||
| 228 | }; | ||
| 229 | |||
| 230 | static struct clksrc_clk clk_mout_mpll = { | ||
| 231 | .clk = { | ||
| 232 | .name = "mout_mpll", | ||
| 233 | .id = -1, | ||
| 234 | }, | ||
| 235 | .sources = &clk_src_mpll, | ||
| 236 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 4, .size = 1, }, | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct clk *clkset_am_list[] = { | ||
| 240 | [0] = &clk_mout_mpll.clk, | ||
| 241 | [1] = &clk_dout_apll2, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static struct clksrc_sources clk_src_am = { | ||
| 245 | .sources = clkset_am_list, | ||
| 246 | .nr_sources = ARRAY_SIZE(clkset_am_list), | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct clksrc_clk clk_mout_am = { | ||
| 250 | .clk = { | ||
| 251 | .name = "mout_am", | ||
| 252 | .id = -1, | ||
| 253 | }, | ||
| 254 | .sources = &clk_src_am, | ||
| 255 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 16, .size = 1, }, | ||
| 256 | }; | ||
| 257 | |||
| 258 | static unsigned long s5pc100_clk_dout_d1_bus_get_rate(struct clk *clk) | ||
| 259 | { | ||
| 260 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 261 | unsigned int ratio; | ||
| 262 | |||
| 263 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 264 | |||
| 265 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_D1_MASK; | ||
| 266 | ratio >>= S5PC100_CLKDIV1_D1_SHIFT; | ||
| 267 | |||
| 268 | return rate / (ratio + 1); | ||
| 269 | } | ||
| 270 | |||
| 271 | static struct clk clk_dout_d1_bus = { | ||
| 272 | .name = "dout_d1_bus", | ||
| 273 | .id = -1, | ||
| 274 | .parent = &clk_mout_am.clk, | ||
| 275 | .ops = &(struct clk_ops) { | ||
| 276 | .get_rate = s5pc100_clk_dout_d1_bus_get_rate, | ||
| 277 | }, | ||
| 278 | }; | ||
| 279 | |||
| 280 | static struct clk *clkset_onenand_list[] = { | ||
| 281 | [0] = &clk_dout_d0_bus, | ||
| 282 | [1] = &clk_dout_d1_bus, | ||
| 283 | }; | ||
| 284 | |||
| 285 | static struct clksrc_sources clk_src_onenand = { | ||
| 286 | .sources = clkset_onenand_list, | ||
| 287 | .nr_sources = ARRAY_SIZE(clkset_onenand_list), | ||
| 288 | }; | ||
| 289 | |||
| 290 | static struct clksrc_clk clk_mout_onenand = { | ||
| 291 | .clk = { | ||
| 292 | .name = "mout_onenand", | ||
| 293 | .id = -1, | ||
| 294 | }, | ||
| 295 | .sources = &clk_src_onenand, | ||
| 296 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 24, .size = 1, }, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static unsigned long s5pc100_clk_dout_pclkd1_get_rate(struct clk *clk) | ||
| 300 | { | ||
| 301 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 302 | unsigned int ratio; | ||
| 303 | |||
| 304 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 305 | |||
| 306 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_PCLKD1_MASK; | ||
| 307 | ratio >>= S5PC100_CLKDIV1_PCLKD1_SHIFT; | ||
| 308 | |||
| 309 | return rate / (ratio + 1); | ||
| 310 | } | ||
| 311 | |||
| 312 | static struct clk clk_dout_pclkd1 = { | ||
| 313 | .name = "dout_pclkd1", | ||
| 314 | .id = -1, | ||
| 315 | .parent = &clk_dout_d1_bus, | ||
| 316 | .ops = &(struct clk_ops) { | ||
| 317 | .get_rate = s5pc100_clk_dout_pclkd1_get_rate, | ||
| 318 | }, | ||
| 319 | }; | ||
| 320 | |||
| 321 | static unsigned long s5pc100_clk_dout_mpll2_get_rate(struct clk *clk) | ||
| 322 | { | ||
| 323 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 324 | unsigned int ratio; | ||
| 325 | |||
| 326 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 327 | |||
| 328 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL2_MASK; | ||
| 329 | ratio >>= S5PC100_CLKDIV1_MPLL2_SHIFT; | ||
| 330 | |||
| 331 | return rate / (ratio + 1); | ||
| 332 | } | ||
| 333 | |||
| 334 | static struct clk clk_dout_mpll2 = { | ||
| 335 | .name = "dout_mpll2", | ||
| 336 | .id = -1, | ||
| 337 | .parent = &clk_mout_am.clk, | ||
| 338 | .ops = &(struct clk_ops) { | ||
| 339 | .get_rate = s5pc100_clk_dout_mpll2_get_rate, | ||
| 340 | }, | ||
| 341 | }; | ||
| 342 | |||
| 343 | static unsigned long s5pc100_clk_dout_cam_get_rate(struct clk *clk) | ||
| 344 | { | ||
| 345 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 346 | unsigned int ratio; | ||
| 347 | |||
| 348 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 349 | |||
| 350 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_CAM_MASK; | ||
| 351 | ratio >>= S5PC100_CLKDIV1_CAM_SHIFT; | ||
| 352 | |||
| 353 | return rate / (ratio + 1); | ||
| 354 | } | ||
| 355 | |||
| 356 | static struct clk clk_dout_cam = { | ||
| 357 | .name = "dout_cam", | ||
| 358 | .id = -1, | ||
| 359 | .parent = &clk_dout_mpll2, | ||
| 360 | .ops = &(struct clk_ops) { | ||
| 361 | .get_rate = s5pc100_clk_dout_cam_get_rate, | ||
| 362 | }, | ||
| 363 | }; | ||
| 364 | |||
| 365 | static unsigned long s5pc100_clk_dout_mpll_get_rate(struct clk *clk) | ||
| 366 | { | ||
| 367 | unsigned long rate = clk_get_rate(clk->parent); | ||
| 368 | unsigned int ratio; | ||
| 369 | |||
| 370 | printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate); | ||
| 371 | |||
| 372 | ratio = __raw_readl(S5PC100_CLKDIV1) & S5PC100_CLKDIV1_MPLL_MASK; | ||
| 373 | ratio >>= S5PC100_CLKDIV1_MPLL_SHIFT; | ||
| 374 | |||
| 375 | return rate / (ratio + 1); | ||
| 376 | } | ||
| 377 | |||
| 378 | static struct clk clk_dout_mpll = { | ||
| 379 | .name = "dout_mpll", | ||
| 380 | .id = -1, | ||
| 381 | .parent = &clk_mout_am.clk, | ||
| 382 | .ops = &(struct clk_ops) { | ||
| 383 | .get_rate = s5pc100_clk_dout_mpll_get_rate, | ||
| 384 | }, | ||
| 385 | }; | ||
| 386 | |||
| 387 | /* EPLL */ | ||
| 388 | static struct clk clk_fout_epll = { | ||
| 389 | .name = "fout_epll", | ||
| 390 | .id = -1, | ||
| 391 | }; | ||
| 392 | |||
| 393 | static struct clk *clk_src_epll_list[] = { | ||
| 394 | [0] = &clk_fin_epll, | ||
| 395 | [1] = &clk_fout_epll, | ||
| 396 | }; | ||
| 397 | |||
| 398 | static struct clksrc_sources clk_src_epll = { | ||
| 399 | .sources = clk_src_epll_list, | ||
| 400 | .nr_sources = ARRAY_SIZE(clk_src_epll_list), | ||
| 401 | }; | ||
| 402 | |||
| 403 | static struct clksrc_clk clk_mout_epll = { | ||
| 404 | .clk = { | ||
| 405 | .name = "mout_epll", | ||
| 406 | .id = -1, | ||
| 407 | }, | ||
| 408 | .sources = &clk_src_epll, | ||
| 409 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 8, .size = 1, }, | ||
| 410 | }; | ||
| 411 | |||
| 412 | /* HPLL */ | ||
| 413 | static struct clk clk_fout_hpll = { | ||
| 414 | .name = "fout_hpll", | ||
| 415 | .id = -1, | ||
| 416 | }; | ||
| 417 | |||
| 418 | static struct clk *clk_src_hpll_list[] = { | ||
| 419 | [0] = &clk_27m, | ||
| 420 | [1] = &clk_fout_hpll, | ||
| 421 | }; | ||
| 422 | |||
| 423 | static struct clksrc_sources clk_src_hpll = { | ||
| 424 | .sources = clk_src_hpll_list, | ||
| 425 | .nr_sources = ARRAY_SIZE(clk_src_hpll_list), | ||
| 426 | }; | ||
| 427 | |||
| 428 | static struct clksrc_clk clk_mout_hpll = { | ||
| 429 | .clk = { | ||
| 430 | .name = "mout_hpll", | ||
| 431 | .id = -1, | ||
| 432 | }, | ||
| 433 | .sources = &clk_src_hpll, | ||
| 434 | .reg_src = { .reg = S5PC100_CLKSRC0, .shift = 12, .size = 1, }, | ||
| 435 | }; | ||
| 436 | |||
| 437 | /* Peripherals */ | ||
| 438 | /* | ||
| 439 | * The peripheral clocks are all controlled via clocksource followed | ||
| 440 | * by an optional divider and gate stage. We currently roll this into | ||
| 441 | * one clock which hides the intermediate clock from the mux. | ||
| 442 | * | ||
| 443 | * Note, the JPEG clock can only be an even divider... | ||
| 444 | * | ||
| 445 | * The scaler and LCD clocks depend on the S5PC100 version, and also | ||
| 446 | * have a common parent divisor so are not included here. | ||
| 447 | */ | ||
| 448 | |||
| 449 | static struct clk clk_iis_cd0 = { | ||
| 450 | .name = "iis_cdclk0", | ||
| 451 | .id = -1, | ||
| 452 | }; | ||
| 453 | |||
| 454 | static struct clk clk_iis_cd1 = { | ||
| 455 | .name = "iis_cdclk1", | ||
| 456 | .id = -1, | ||
| 457 | }; | ||
| 458 | |||
| 459 | static struct clk clk_iis_cd2 = { | ||
| 460 | .name = "iis_cdclk2", | ||
| 461 | .id = -1, | ||
| 462 | }; | ||
| 463 | |||
| 464 | static struct clk clk_pcm_cd0 = { | ||
| 465 | .name = "pcm_cdclk0", | ||
| 466 | .id = -1, | ||
| 467 | }; | ||
| 468 | |||
| 469 | static struct clk clk_pcm_cd1 = { | ||
| 470 | .name = "pcm_cdclk1", | ||
| 471 | .id = -1, | ||
| 472 | }; | ||
| 473 | |||
| 474 | static struct clk *clkset_audio0_list[] = { | ||
| 475 | &clk_mout_epll.clk, | ||
| 476 | &clk_dout_mpll, | ||
| 477 | &clk_fin_epll, | ||
| 478 | &clk_iis_cd0, | ||
| 479 | &clk_pcm_cd0, | ||
| 480 | &clk_mout_hpll.clk, | ||
| 481 | }; | ||
| 482 | |||
| 483 | static struct clksrc_sources clkset_audio0 = { | ||
| 484 | .sources = clkset_audio0_list, | ||
| 485 | .nr_sources = ARRAY_SIZE(clkset_audio0_list), | ||
| 486 | }; | ||
| 487 | |||
| 488 | static struct clk *clkset_spi_list[] = { | ||
| 489 | &clk_mout_epll.clk, | ||
| 490 | &clk_dout_mpll2, | ||
| 491 | &clk_fin_epll, | ||
| 492 | &clk_mout_hpll.clk, | ||
| 493 | }; | ||
| 494 | |||
| 495 | static struct clksrc_sources clkset_spi = { | ||
| 496 | .sources = clkset_spi_list, | ||
| 497 | .nr_sources = ARRAY_SIZE(clkset_spi_list), | ||
| 498 | }; | ||
| 499 | |||
| 500 | static struct clk *clkset_uart_list[] = { | ||
| 501 | &clk_mout_epll.clk, | ||
| 502 | &clk_dout_mpll, | ||
| 503 | }; | ||
| 504 | |||
| 505 | static struct clksrc_sources clkset_uart = { | ||
| 506 | .sources = clkset_uart_list, | ||
| 507 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
| 508 | }; | ||
| 509 | |||
| 510 | static struct clk *clkset_audio1_list[] = { | ||
| 511 | &clk_mout_epll.clk, | ||
| 512 | &clk_dout_mpll, | ||
| 513 | &clk_fin_epll, | ||
| 514 | &clk_iis_cd1, | ||
| 515 | &clk_pcm_cd1, | ||
| 516 | &clk_mout_hpll.clk, | ||
| 517 | }; | ||
| 518 | |||
| 519 | static struct clksrc_sources clkset_audio1 = { | ||
| 520 | .sources = clkset_audio1_list, | ||
| 521 | .nr_sources = ARRAY_SIZE(clkset_audio1_list), | ||
| 522 | }; | ||
| 523 | |||
| 524 | static struct clk *clkset_audio2_list[] = { | ||
| 525 | &clk_mout_epll.clk, | ||
| 526 | &clk_dout_mpll, | ||
| 527 | &clk_fin_epll, | ||
| 528 | &clk_iis_cd2, | ||
| 529 | &clk_mout_hpll.clk, | ||
| 530 | }; | ||
| 531 | |||
| 532 | static struct clksrc_sources clkset_audio2 = { | ||
| 533 | .sources = clkset_audio2_list, | ||
| 534 | .nr_sources = ARRAY_SIZE(clkset_audio2_list), | ||
| 535 | }; | ||
| 536 | |||
| 537 | static struct clksrc_clk clksrc_audio[] = { | ||
| 538 | { | ||
| 539 | .clk = { | ||
| 540 | .name = "audio-bus", | ||
| 541 | .id = 0, | ||
| 542 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO0, | ||
| 543 | .enable = s5pc100_sclk1_ctrl, | ||
| 544 | }, | ||
| 545 | .sources = &clkset_audio0, | ||
| 546 | .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 12, .size = 4, }, | ||
| 547 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 12, .size = 3, }, | ||
| 548 | }, { | ||
| 549 | .clk = { | ||
| 550 | .name = "audio-bus", | ||
| 551 | .id = 1, | ||
| 552 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO1, | ||
| 553 | .enable = s5pc100_sclk1_ctrl, | ||
| 554 | }, | ||
| 555 | .sources = &clkset_audio1, | ||
| 556 | .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 16, .size = 4, }, | ||
| 557 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 16, .size = 3, }, | ||
| 558 | }, { | ||
| 559 | .clk = { | ||
| 560 | .name = "audio-bus", | ||
| 561 | .id = 2, | ||
| 562 | .ctrlbit = S5PC100_CLKGATE_SCLK1_AUDIO2, | ||
| 563 | .enable = s5pc100_sclk1_ctrl, | ||
| 564 | }, | ||
| 565 | .sources = &clkset_audio2, | ||
| 566 | .reg_div = { .reg = S5PC100_CLKDIV4, .shift = 20, .size = 4, }, | ||
| 567 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 20, .size = 3, }, | ||
| 568 | }, | ||
| 569 | }; | ||
| 570 | |||
| 571 | static struct clk *clkset_spdif_list[] = { | ||
| 572 | &clksrc_audio[0].clk, | ||
| 573 | &clksrc_audio[1].clk, | ||
| 574 | &clksrc_audio[2].clk, | ||
| 575 | }; | ||
| 576 | |||
| 577 | static struct clksrc_sources clkset_spdif = { | ||
| 578 | .sources = clkset_spdif_list, | ||
| 579 | .nr_sources = ARRAY_SIZE(clkset_spdif_list), | ||
| 580 | }; | ||
| 581 | |||
| 582 | static struct clk *clkset_lcd_fimc_list[] = { | ||
| 583 | &clk_mout_epll.clk, | ||
| 584 | &clk_dout_mpll, | ||
| 585 | &clk_mout_hpll.clk, | ||
| 586 | &clk_vclk_54m, | ||
| 587 | }; | ||
| 588 | |||
| 589 | static struct clksrc_sources clkset_lcd_fimc = { | ||
| 590 | .sources = clkset_lcd_fimc_list, | ||
| 591 | .nr_sources = ARRAY_SIZE(clkset_lcd_fimc_list), | ||
| 592 | }; | ||
| 593 | |||
| 594 | static struct clk *clkset_mmc_list[] = { | ||
| 595 | &clk_mout_epll.clk, | ||
| 596 | &clk_dout_mpll, | ||
| 597 | &clk_fin_epll, | ||
| 598 | &clk_mout_hpll.clk , | ||
| 599 | }; | ||
| 600 | |||
| 601 | static struct clksrc_sources clkset_mmc = { | ||
| 602 | .sources = clkset_mmc_list, | ||
| 603 | .nr_sources = ARRAY_SIZE(clkset_mmc_list), | ||
| 604 | }; | ||
| 605 | |||
| 606 | static struct clk *clkset_usbhost_list[] = { | ||
| 607 | &clk_mout_epll.clk, | ||
| 608 | &clk_dout_mpll, | ||
| 609 | &clk_mout_hpll.clk, | ||
| 610 | &clk_48m, | ||
| 611 | }; | ||
| 612 | |||
| 613 | static struct clksrc_sources clkset_usbhost = { | ||
| 614 | .sources = clkset_usbhost_list, | ||
| 615 | .nr_sources = ARRAY_SIZE(clkset_usbhost_list), | ||
| 616 | }; | ||
| 617 | |||
| 618 | static struct clksrc_clk clksrc_clks[] = { | ||
| 619 | { | ||
| 620 | .clk = { | ||
| 621 | .name = "spi_bus", | ||
| 622 | .id = 0, | ||
| 623 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0, | ||
| 624 | .enable = s5pc100_sclk0_ctrl, | ||
| 625 | |||
| 626 | }, | ||
| 627 | .sources = &clkset_spi, | ||
| 628 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 4, .size = 4, }, | ||
| 629 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 4, .size = 2, }, | ||
| 630 | }, { | ||
| 631 | .clk = { | ||
| 632 | .name = "spi_bus", | ||
| 633 | .id = 1, | ||
| 634 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1, | ||
| 635 | .enable = s5pc100_sclk0_ctrl, | ||
| 636 | }, | ||
| 637 | .sources = &clkset_spi, | ||
| 638 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 8, .size = 4, }, | ||
| 639 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 8, .size = 2, }, | ||
| 640 | }, { | ||
| 641 | .clk = { | ||
| 642 | .name = "spi_bus", | ||
| 643 | .id = 2, | ||
| 644 | .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2, | ||
| 645 | .enable = s5pc100_sclk0_ctrl, | ||
| 646 | }, | ||
| 647 | .sources = &clkset_spi, | ||
| 648 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 12, .size = 4, }, | ||
| 649 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 12, .size = 2, }, | ||
| 650 | }, { | ||
| 651 | .clk = { | ||
| 652 | .name = "uclk1", | ||
| 653 | .id = -1, | ||
| 654 | .ctrlbit = S5PC100_CLKGATE_SCLK0_UART, | ||
| 655 | .enable = s5pc100_sclk0_ctrl, | ||
| 656 | }, | ||
| 657 | .sources = &clkset_uart, | ||
| 658 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 0, .size = 3, }, | ||
| 659 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 0, .size = 1, }, | ||
| 660 | }, { | ||
| 661 | .clk = { | ||
| 662 | .name = "spdif", | ||
| 663 | .id = -1, | ||
| 664 | }, | ||
| 665 | .sources = &clkset_spdif, | ||
| 666 | .reg_src = { .reg = S5PC100_CLKSRC3, .shift = 24, .size = 2, }, | ||
| 667 | }, { | ||
| 668 | .clk = { | ||
| 669 | .name = "lcd", | ||
| 670 | .id = -1, | ||
| 671 | .ctrlbit = S5PC100_CLKGATE_SCLK1_LCD, | ||
| 672 | .enable = s5pc100_sclk1_ctrl, | ||
| 673 | }, | ||
| 674 | .sources = &clkset_lcd_fimc, | ||
| 675 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 12, .size = 4, }, | ||
| 676 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 12, .size = 2, }, | ||
| 677 | }, { | ||
| 678 | .clk = { | ||
| 679 | .name = "fimc", | ||
| 680 | .id = 0, | ||
| 681 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC0, | ||
| 682 | .enable = s5pc100_sclk1_ctrl, | ||
| 683 | }, | ||
| 684 | .sources = &clkset_lcd_fimc, | ||
| 685 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 16, .size = 4, }, | ||
| 686 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 16, .size = 2, }, | ||
| 687 | }, { | ||
| 688 | .clk = { | ||
| 689 | .name = "fimc", | ||
| 690 | .id = 1, | ||
| 691 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC1, | ||
| 692 | .enable = s5pc100_sclk1_ctrl, | ||
| 693 | }, | ||
| 694 | .sources = &clkset_lcd_fimc, | ||
| 695 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 20, .size = 4, }, | ||
| 696 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 20, .size = 2, }, | ||
| 697 | }, { | ||
| 698 | .clk = { | ||
| 699 | .name = "fimc", | ||
| 700 | .id = 2, | ||
| 701 | .ctrlbit = S5PC100_CLKGATE_SCLK1_FIMC2, | ||
| 702 | .enable = s5pc100_sclk1_ctrl, | ||
| 703 | }, | ||
| 704 | .sources = &clkset_lcd_fimc, | ||
| 705 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 24, .size = 4, }, | ||
| 706 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 24, .size = 2, }, | ||
| 707 | }, { | ||
| 708 | .clk = { | ||
| 709 | .name = "mmc_bus", | ||
| 710 | .id = 0, | ||
| 711 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0, | ||
| 712 | .enable = s5pc100_sclk0_ctrl, | ||
| 713 | }, | ||
| 714 | .sources = &clkset_mmc, | ||
| 715 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 0, .size = 4, }, | ||
| 716 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 0, .size = 2, }, | ||
| 717 | }, { | ||
| 718 | .clk = { | ||
| 719 | .name = "mmc_bus", | ||
| 720 | .id = 1, | ||
| 721 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1, | ||
| 722 | .enable = s5pc100_sclk0_ctrl, | ||
| 723 | }, | ||
| 724 | .sources = &clkset_mmc, | ||
| 725 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 4, .size = 4, }, | ||
| 726 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 4, .size = 2, }, | ||
| 727 | }, { | ||
| 728 | .clk = { | ||
| 729 | .name = "mmc_bus", | ||
| 730 | .id = 2, | ||
| 731 | .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2, | ||
| 732 | .enable = s5pc100_sclk0_ctrl, | ||
| 733 | }, | ||
| 734 | .sources = &clkset_mmc, | ||
| 735 | .reg_div = { .reg = S5PC100_CLKDIV3, .shift = 8, .size = 4, }, | ||
| 736 | .reg_src = { .reg = S5PC100_CLKSRC2, .shift = 8, .size = 2, }, | ||
| 737 | }, { | ||
| 738 | .clk = { | ||
| 739 | .name = "usbhost", | ||
| 740 | .id = -1, | ||
| 741 | .ctrlbit = S5PC100_CLKGATE_SCLK0_USBHOST, | ||
| 742 | .enable = s5pc100_sclk0_ctrl, | ||
| 743 | }, | ||
| 744 | .sources = &clkset_usbhost, | ||
| 745 | .reg_div = { .reg = S5PC100_CLKDIV2, .shift = 20, .size = 4, }, | ||
| 746 | .reg_src = { .reg = S5PC100_CLKSRC1, .shift = 20, .size = 2, }, | ||
| 747 | } | ||
| 748 | }; | ||
| 749 | |||
| 750 | /* Clock initialisation code */ | ||
| 751 | |||
| 752 | static struct clksrc_clk *init_parents[] = { | ||
| 753 | &clk_mout_apll, | ||
| 754 | &clk_mout_mpll, | ||
| 755 | &clk_mout_am, | ||
| 756 | &clk_mout_onenand, | ||
| 757 | &clk_mout_epll, | ||
| 758 | &clk_mout_hpll, | ||
| 759 | }; | ||
| 760 | |||
| 761 | #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) | ||
| 762 | |||
| 763 | void __init_or_cpufreq s5pc100_setup_clocks(void) | ||
| 764 | { | ||
| 765 | struct clk *xtal_clk; | ||
| 766 | unsigned long xtal; | ||
| 767 | unsigned long armclk; | ||
| 768 | unsigned long hclkd0; | ||
| 769 | unsigned long hclk; | ||
| 770 | unsigned long pclkd0; | ||
| 771 | unsigned long pclk; | ||
| 772 | unsigned long apll, mpll, epll, hpll; | ||
| 773 | unsigned int ptr; | ||
| 774 | u32 clkdiv0, clkdiv1; | ||
| 775 | |||
| 776 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
| 777 | |||
| 778 | clkdiv0 = __raw_readl(S5PC100_CLKDIV0); | ||
| 779 | clkdiv1 = __raw_readl(S5PC100_CLKDIV1); | ||
| 780 | |||
| 781 | printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); | ||
| 782 | |||
| 783 | xtal_clk = clk_get(NULL, "xtal"); | ||
| 784 | BUG_ON(IS_ERR(xtal_clk)); | ||
| 785 | |||
| 786 | xtal = clk_get_rate(xtal_clk); | ||
| 787 | clk_put(xtal_clk); | ||
| 788 | |||
| 789 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
| 790 | |||
| 791 | apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_APLL_CON)); | ||
| 792 | mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_MPLL_CON)); | ||
| 793 | epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_EPLL_CON)); | ||
| 794 | hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON)); | ||
| 795 | |||
| 796 | printk(KERN_INFO "S5PC100: Apll=%ld.%03ld Mhz, Mpll=%ld.%03ld Mhz" | ||
| 797 | ", Epll=%ld.%03ld Mhz, Hpll=%ld.%03ld Mhz\n", | ||
| 798 | print_mhz(apll), print_mhz(mpll), | ||
| 799 | print_mhz(epll), print_mhz(hpll)); | ||
| 800 | |||
| 801 | armclk = apll / GET_DIV(clkdiv0, S5PC100_CLKDIV0_APLL); | ||
| 802 | armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM); | ||
| 803 | hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0); | ||
| 804 | pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0); | ||
| 805 | hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1); | ||
| 806 | pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1); | ||
| 807 | |||
| 808 | printk(KERN_INFO "S5PC100: ARMCLK=%ld.%03ld MHz, HCLKD0=%ld.%03ld MHz," | ||
| 809 | " PCLKD0=%ld.%03ld MHz\n, HCLK=%ld.%03ld MHz," | ||
| 810 | " PCLK=%ld.%03ld MHz\n", | ||
| 811 | print_mhz(armclk), print_mhz(hclkd0), | ||
| 812 | print_mhz(pclkd0), print_mhz(hclk), print_mhz(pclk)); | ||
| 813 | |||
| 814 | clk_fout_apll.rate = apll; | ||
| 815 | clk_fout_mpll.rate = mpll; | ||
| 816 | clk_fout_epll.rate = epll; | ||
| 817 | clk_fout_hpll.rate = hpll; | ||
| 818 | |||
| 819 | clk_h.rate = hclk; | ||
| 820 | clk_p.rate = pclk; | ||
| 821 | clk_f.rate = armclk; | ||
| 822 | |||
| 823 | for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) | ||
| 824 | s3c_set_clksrc(init_parents[ptr], true); | ||
| 825 | |||
| 826 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++) | ||
| 827 | s3c_set_clksrc(clksrc_audio + ptr, true); | ||
| 828 | |||
| 829 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++) | ||
| 830 | s3c_set_clksrc(clksrc_clks + ptr, true); | ||
| 831 | } | ||
| 832 | |||
| 833 | static struct clk *clks[] __initdata = { | ||
| 834 | &clk_ext_xtal_mux, | ||
| 835 | &clk_dout_apll, | ||
| 836 | &clk_dout_d0_bus, | ||
| 837 | &clk_dout_pclkd0, | ||
| 838 | &clk_dout_apll2, | ||
| 839 | &clk_mout_apll.clk, | ||
| 840 | &clk_mout_mpll.clk, | ||
| 841 | &clk_mout_epll.clk, | ||
| 842 | &clk_mout_hpll.clk, | ||
| 843 | &clk_mout_am.clk, | ||
| 844 | &clk_dout_d1_bus, | ||
| 845 | &clk_mout_onenand.clk, | ||
| 846 | &clk_dout_pclkd1, | ||
| 847 | &clk_dout_mpll2, | ||
| 848 | &clk_dout_cam, | ||
| 849 | &clk_dout_mpll, | ||
| 850 | &clk_fout_epll, | ||
| 851 | &clk_iis_cd0, | ||
| 852 | &clk_iis_cd1, | ||
| 853 | &clk_iis_cd2, | ||
| 854 | &clk_pcm_cd0, | ||
| 855 | &clk_pcm_cd1, | ||
| 856 | &clk_arm, | ||
| 857 | }; | ||
| 858 | |||
| 859 | void __init s5pc100_register_clocks(void) | ||
| 860 | { | ||
| 861 | struct clk *clkp; | ||
| 862 | int ret; | ||
| 863 | int ptr; | ||
| 864 | |||
| 865 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { | ||
| 866 | clkp = clks[ptr]; | ||
| 867 | ret = s3c24xx_register_clock(clkp); | ||
| 868 | if (ret < 0) { | ||
| 869 | printk(KERN_ERR "Failed to register clock %s (%d)\n", | ||
| 870 | clkp->name, ret); | ||
| 871 | } | ||
| 872 | } | ||
| 873 | |||
| 874 | s3c_register_clksrc(clksrc_audio, ARRAY_SIZE(clksrc_audio)); | ||
| 875 | s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks)); | ||
| 876 | } | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 229919e9744c..2753fb3e4f73 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | 6 | ||
| 7 | config PLAT_SAMSUNG | 7 | config PLAT_SAMSUNG |
| 8 | bool | 8 | bool |
| 9 | depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX || ARCH_S5PC1XX | 9 | depends on ARCH_S3C2410 || ARCH_S3C24A0 || ARCH_S3C64XX |
| 10 | select NO_IOPORT | 10 | select NO_IOPORT |
| 11 | default y | 11 | default y |
| 12 | help | 12 | help |
| @@ -170,6 +170,11 @@ config S3C_DEV_I2C1 | |||
| 170 | help | 170 | help |
| 171 | Compile in platform device definitions for I2C channel 1 | 171 | Compile in platform device definitions for I2C channel 1 |
| 172 | 172 | ||
| 173 | config S3C_DEV_I2C2 | ||
| 174 | bool | ||
| 175 | help | ||
| 176 | Compile in platform device definitions for I2C channel 2 | ||
| 177 | |||
| 173 | config S3C_DEV_FB | 178 | config S3C_DEV_FB |
| 174 | bool | 179 | bool |
| 175 | help | 180 | help |
| @@ -185,11 +190,22 @@ config S3C_DEV_USB_HSOTG | |||
| 185 | help | 190 | help |
| 186 | Compile in platform device definition for USB high-speed OtG | 191 | Compile in platform device definition for USB high-speed OtG |
| 187 | 192 | ||
| 193 | config S3C_DEV_WDT | ||
| 194 | bool | ||
| 195 | default y if ARCH_S3C2410 | ||
| 196 | help | ||
| 197 | Complie in platform device definition for Watchdog Timer | ||
| 198 | |||
| 188 | config S3C_DEV_NAND | 199 | config S3C_DEV_NAND |
| 189 | bool | 200 | bool |
| 190 | help | 201 | help |
| 191 | Compile in platform device definition for NAND controller | 202 | Compile in platform device definition for NAND controller |
| 192 | 203 | ||
| 204 | config S3C_DEV_ONENAND | ||
| 205 | bool | ||
| 206 | help | ||
| 207 | Compile in platform device definition for OneNAND controller | ||
| 208 | |||
| 193 | config S3C_DEV_RTC | 209 | config S3C_DEV_RTC |
| 194 | bool | 210 | bool |
| 195 | help | 211 | help |
| @@ -269,4 +285,12 @@ config SAMSUNG_PM_CHECK_CHUNKSIZE | |||
| 269 | 285 | ||
| 270 | See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> | 286 | See <file:Documentation/arm/Samsung-S3C24XX/Suspend.txt> |
| 271 | 287 | ||
| 288 | config SAMSUNG_WAKEMASK | ||
| 289 | bool | ||
| 290 | depends on PM | ||
| 291 | help | ||
| 292 | Compile support for wakeup-mask controls found on the S3C6400 | ||
| 293 | and above. This code allows a set of interrupt to wakeup-mask | ||
| 294 | mappings. See <plat/wakeup-mask.h> | ||
| 295 | |||
| 272 | endif | 296 | endif |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 48288499a3b9..b1d82cc5e716 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
| @@ -36,11 +36,14 @@ obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o | |||
| 36 | obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o | 36 | obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o |
| 37 | obj-y += dev-i2c0.o | 37 | obj-y += dev-i2c0.o |
| 38 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o | 38 | obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o |
| 39 | obj-$(CONFIG_S3C_DEV_I2C2) += dev-i2c2.o | ||
| 39 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o | 40 | obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o |
| 40 | obj-y += dev-uart.o | 41 | obj-y += dev-uart.o |
| 41 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o | 42 | obj-$(CONFIG_S3C_DEV_USB_HOST) += dev-usb.o |
| 42 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o | 43 | obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o |
| 44 | obj-$(CONFIG_S3C_DEV_WDT) += dev-wdt.o | ||
| 43 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o | 45 | obj-$(CONFIG_S3C_DEV_NAND) += dev-nand.o |
| 46 | obj-$(CONFIG_S3C_DEV_ONENAND) += dev-onenand.o | ||
| 44 | obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o | 47 | obj-$(CONFIG_S3C_DEV_RTC) += dev-rtc.o |
| 45 | 48 | ||
| 46 | obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o | 49 | obj-$(CONFIG_SAMSUNG_DEV_ADC) += dev-adc.o |
| @@ -58,6 +61,8 @@ obj-$(CONFIG_PM) += pm.o | |||
| 58 | obj-$(CONFIG_PM) += pm-gpio.o | 61 | obj-$(CONFIG_PM) += pm-gpio.o |
| 59 | obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o | 62 | obj-$(CONFIG_SAMSUNG_PM_CHECK) += pm-check.o |
| 60 | 63 | ||
| 64 | obj-$(CONFIG_SAMSUNG_WAKEMASK) += wakeup-mask.o | ||
| 65 | |||
| 61 | # PWM support | 66 | # PWM support |
| 62 | 67 | ||
| 63 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 68 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 210030d5cfe1..04d9521ddc9f 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c | |||
| @@ -66,6 +66,7 @@ struct adc_device { | |||
| 66 | struct s3c_adc_client *cur; | 66 | struct s3c_adc_client *cur; |
| 67 | struct s3c_adc_client *ts_pend; | 67 | struct s3c_adc_client *ts_pend; |
| 68 | void __iomem *regs; | 68 | void __iomem *regs; |
| 69 | spinlock_t lock; | ||
| 69 | 70 | ||
| 70 | unsigned int prescale; | 71 | unsigned int prescale; |
| 71 | 72 | ||
| @@ -74,7 +75,7 @@ struct adc_device { | |||
| 74 | 75 | ||
| 75 | static struct adc_device *adc_dev; | 76 | static struct adc_device *adc_dev; |
| 76 | 77 | ||
| 77 | static LIST_HEAD(adc_pending); | 78 | static LIST_HEAD(adc_pending); /* protected by adc_device.lock */ |
| 78 | 79 | ||
| 79 | #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) | 80 | #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg) |
| 80 | 81 | ||
| @@ -145,7 +146,7 @@ int s3c_adc_start(struct s3c_adc_client *client, | |||
| 145 | if (client->is_ts && adc->ts_pend) | 146 | if (client->is_ts && adc->ts_pend) |
| 146 | return -EAGAIN; | 147 | return -EAGAIN; |
| 147 | 148 | ||
| 148 | local_irq_save(flags); | 149 | spin_lock_irqsave(&adc->lock, flags); |
| 149 | 150 | ||
| 150 | client->channel = channel; | 151 | client->channel = channel; |
| 151 | client->nr_samples = nr_samples; | 152 | client->nr_samples = nr_samples; |
| @@ -157,7 +158,8 @@ int s3c_adc_start(struct s3c_adc_client *client, | |||
| 157 | 158 | ||
| 158 | if (!adc->cur) | 159 | if (!adc->cur) |
| 159 | s3c_adc_try(adc); | 160 | s3c_adc_try(adc); |
| 160 | local_irq_restore(flags); | 161 | |
| 162 | spin_unlock_irqrestore(&adc->lock, flags); | ||
| 161 | 163 | ||
| 162 | return 0; | 164 | return 0; |
| 163 | } | 165 | } |
| @@ -237,6 +239,10 @@ EXPORT_SYMBOL_GPL(s3c_adc_register); | |||
| 237 | 239 | ||
| 238 | void s3c_adc_release(struct s3c_adc_client *client) | 240 | void s3c_adc_release(struct s3c_adc_client *client) |
| 239 | { | 241 | { |
| 242 | unsigned long flags; | ||
| 243 | |||
| 244 | spin_lock_irqsave(&adc_dev->lock, flags); | ||
| 245 | |||
| 240 | /* We should really check that nothing is in progress. */ | 246 | /* We should really check that nothing is in progress. */ |
| 241 | if (adc_dev->cur == client) | 247 | if (adc_dev->cur == client) |
| 242 | adc_dev->cur = NULL; | 248 | adc_dev->cur = NULL; |
| @@ -255,6 +261,8 @@ void s3c_adc_release(struct s3c_adc_client *client) | |||
| 255 | 261 | ||
| 256 | if (adc_dev->cur == NULL) | 262 | if (adc_dev->cur == NULL) |
| 257 | s3c_adc_try(adc_dev); | 263 | s3c_adc_try(adc_dev); |
| 264 | |||
| 265 | spin_unlock_irqrestore(&adc_dev->lock, flags); | ||
| 258 | kfree(client); | 266 | kfree(client); |
| 259 | } | 267 | } |
| 260 | EXPORT_SYMBOL_GPL(s3c_adc_release); | 268 | EXPORT_SYMBOL_GPL(s3c_adc_release); |
| @@ -264,7 +272,6 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
| 264 | struct adc_device *adc = pw; | 272 | struct adc_device *adc = pw; |
| 265 | struct s3c_adc_client *client = adc->cur; | 273 | struct s3c_adc_client *client = adc->cur; |
| 266 | enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; | 274 | enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data; |
| 267 | unsigned long flags; | ||
| 268 | unsigned data0, data1; | 275 | unsigned data0, data1; |
| 269 | 276 | ||
| 270 | if (!client) { | 277 | if (!client) { |
| @@ -296,12 +303,12 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw) | |||
| 296 | client->select_cb(client, 1); | 303 | client->select_cb(client, 1); |
| 297 | s3c_adc_convert(adc); | 304 | s3c_adc_convert(adc); |
| 298 | } else { | 305 | } else { |
| 299 | local_irq_save(flags); | 306 | spin_lock(&adc->lock); |
| 300 | (client->select_cb)(client, 0); | 307 | (client->select_cb)(client, 0); |
| 301 | adc->cur = NULL; | 308 | adc->cur = NULL; |
| 302 | 309 | ||
| 303 | s3c_adc_try(adc); | 310 | s3c_adc_try(adc); |
| 304 | local_irq_restore(flags); | 311 | spin_unlock(&adc->lock); |
| 305 | } | 312 | } |
| 306 | 313 | ||
| 307 | exit: | 314 | exit: |
| @@ -326,6 +333,8 @@ static int s3c_adc_probe(struct platform_device *pdev) | |||
| 326 | return -ENOMEM; | 333 | return -ENOMEM; |
| 327 | } | 334 | } |
| 328 | 335 | ||
| 336 | spin_lock_init(&adc->lock); | ||
| 337 | |||
| 329 | adc->pdev = pdev; | 338 | adc->pdev = pdev; |
| 330 | adc->prescale = S3C2410_ADCCON_PRSCVL(49); | 339 | adc->prescale = S3C2410_ADCCON_PRSCVL(49); |
| 331 | 340 | ||
| @@ -407,13 +416,17 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev) | |||
| 407 | static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) | 416 | static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) |
| 408 | { | 417 | { |
| 409 | struct adc_device *adc = platform_get_drvdata(pdev); | 418 | struct adc_device *adc = platform_get_drvdata(pdev); |
| 419 | unsigned long flags; | ||
| 410 | u32 con; | 420 | u32 con; |
| 411 | 421 | ||
| 422 | spin_lock_irqsave(&adc->lock, flags); | ||
| 423 | |||
| 412 | con = readl(adc->regs + S3C2410_ADCCON); | 424 | con = readl(adc->regs + S3C2410_ADCCON); |
| 413 | con |= S3C2410_ADCCON_STDBM; | 425 | con |= S3C2410_ADCCON_STDBM; |
| 414 | writel(con, adc->regs + S3C2410_ADCCON); | 426 | writel(con, adc->regs + S3C2410_ADCCON); |
| 415 | 427 | ||
| 416 | disable_irq(adc->irq); | 428 | disable_irq(adc->irq); |
| 429 | spin_unlock_irqrestore(&adc->lock, flags); | ||
| 417 | clk_disable(adc->clk); | 430 | clk_disable(adc->clk); |
| 418 | 431 | ||
| 419 | return 0; | 432 | return 0; |
| @@ -422,6 +435,7 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state) | |||
| 422 | static int s3c_adc_resume(struct platform_device *pdev) | 435 | static int s3c_adc_resume(struct platform_device *pdev) |
| 423 | { | 436 | { |
| 424 | struct adc_device *adc = platform_get_drvdata(pdev); | 437 | struct adc_device *adc = platform_get_drvdata(pdev); |
| 438 | unsigned long flags; | ||
| 425 | 439 | ||
| 426 | clk_enable(adc->clk); | 440 | clk_enable(adc->clk); |
| 427 | enable_irq(adc->irq); | 441 | enable_irq(adc->irq); |
diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c new file mode 100644 index 000000000000..07036dee09e7 --- /dev/null +++ b/arch/arm/plat-samsung/dev-i2c2.c | |||
| @@ -0,0 +1,70 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/dev-i2c2.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
| 4 | * http://www.samsung.com/ | ||
| 5 | * | ||
| 6 | * S3C series device definition for i2c device 2 | ||
| 7 | * | ||
| 8 | * Based on plat-samsung/dev-i2c0.c | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/gfp.h> | ||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/string.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | |||
| 20 | #include <mach/irqs.h> | ||
| 21 | #include <mach/map.h> | ||
| 22 | |||
| 23 | #include <plat/regs-iic.h> | ||
| 24 | #include <plat/iic.h> | ||
| 25 | #include <plat/devs.h> | ||
| 26 | #include <plat/cpu.h> | ||
| 27 | |||
| 28 | static struct resource s3c_i2c_resource[] = { | ||
| 29 | [0] = { | ||
| 30 | .start = S3C_PA_IIC2, | ||
| 31 | .end = S3C_PA_IIC2 + SZ_4K - 1, | ||
| 32 | .flags = IORESOURCE_MEM, | ||
| 33 | }, | ||
| 34 | [1] = { | ||
| 35 | .start = IRQ_CAN0, | ||
| 36 | .end = IRQ_CAN0, | ||
| 37 | .flags = IORESOURCE_IRQ, | ||
| 38 | }, | ||
| 39 | }; | ||
| 40 | |||
| 41 | struct platform_device s3c_device_i2c2 = { | ||
| 42 | .name = "s3c2410-i2c", | ||
| 43 | .id = 2, | ||
| 44 | .num_resources = ARRAY_SIZE(s3c_i2c_resource), | ||
| 45 | .resource = s3c_i2c_resource, | ||
| 46 | }; | ||
| 47 | |||
| 48 | static struct s3c2410_platform_i2c default_i2c_data2 __initdata = { | ||
| 49 | .flags = 0, | ||
| 50 | .bus_num = 2, | ||
| 51 | .slave_addr = 0x10, | ||
| 52 | .frequency = 100*1000, | ||
| 53 | .sda_delay = 100, | ||
| 54 | }; | ||
| 55 | |||
| 56 | void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd) | ||
| 57 | { | ||
| 58 | struct s3c2410_platform_i2c *npd; | ||
| 59 | |||
| 60 | if (!pd) | ||
| 61 | pd = &default_i2c_data2; | ||
| 62 | |||
| 63 | npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL); | ||
| 64 | if (!npd) | ||
| 65 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
| 66 | else if (!npd->cfg_gpio) | ||
| 67 | npd->cfg_gpio = s3c_i2c2_cfg_gpio; | ||
| 68 | |||
| 69 | s3c_device_i2c2.dev.platform_data = npd; | ||
| 70 | } | ||
diff --git a/arch/arm/plat-samsung/dev-onenand.c b/arch/arm/plat-samsung/dev-onenand.c new file mode 100644 index 000000000000..45ec73287d8c --- /dev/null +++ b/arch/arm/plat-samsung/dev-onenand.c | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-samsung/dev-onenand.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008-2010 Samsung Electronics | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * | ||
| 7 | * S3C64XX/S5PC100 series device definition for OneNAND devices | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/mtd/mtd.h> | ||
| 17 | #include <linux/mtd/onenand.h> | ||
| 18 | |||
| 19 | #include <mach/irqs.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | static struct resource s3c_onenand_resources[] = { | ||
| 23 | [0] = { | ||
| 24 | .start = S3C_PA_ONENAND, | ||
| 25 | .end = S3C_PA_ONENAND + 0x400 - 1, | ||
| 26 | .flags = IORESOURCE_MEM, | ||
| 27 | }, | ||
| 28 | [1] = { | ||
| 29 | .start = S3C_PA_ONENAND_BUF, | ||
| 30 | .end = S3C_PA_ONENAND_BUF + S3C_SZ_ONENAND_BUF - 1, | ||
| 31 | .flags = IORESOURCE_MEM, | ||
| 32 | }, | ||
| 33 | [2] = { | ||
| 34 | .start = IRQ_ONENAND, | ||
| 35 | .end = IRQ_ONENAND, | ||
| 36 | .flags = IORESOURCE_IRQ, | ||
| 37 | }, | ||
| 38 | }; | ||
| 39 | |||
| 40 | struct platform_device s3c_device_onenand = { | ||
| 41 | .name = "samsung-onenand", | ||
| 42 | .id = 0, | ||
| 43 | .num_resources = ARRAY_SIZE(s3c_onenand_resources), | ||
| 44 | .resource = s3c_onenand_resources, | ||
| 45 | }; | ||
| 46 | |||
| 47 | void s3c_onenand_set_platdata(struct onenand_platform_data *pdata) | ||
| 48 | { | ||
| 49 | struct onenand_platform_data *pd; | ||
| 50 | |||
| 51 | pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL); | ||
| 52 | if (!pd) | ||
| 53 | printk(KERN_ERR "%s: no memory for platform data\n", __func__); | ||
| 54 | s3c_device_onenand.dev.platform_data = pd; | ||
| 55 | } | ||
diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c new file mode 100644 index 000000000000..5efca87cddbd --- /dev/null +++ b/arch/arm/plat-samsung/dev-wdt.c | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /* linux/arch/arm/plat-samsung/dev-wdt.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * S3C series device definition for the watchdog timer | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | |||
| 16 | #include <mach/irqs.h> | ||
| 17 | #include <mach/map.h> | ||
| 18 | |||
| 19 | #include <plat/devs.h> | ||
| 20 | |||
| 21 | static struct resource s3c_wdt_resource[] = { | ||
| 22 | [0] = { | ||
| 23 | .start = S3C_PA_WDT, | ||
| 24 | .end = S3C_PA_WDT + SZ_1M - 1, | ||
| 25 | .flags = IORESOURCE_MEM, | ||
| 26 | }, | ||
| 27 | [1] = { | ||
| 28 | .start = IRQ_WDT, | ||
| 29 | .end = IRQ_WDT, | ||
| 30 | .flags = IORESOURCE_IRQ, | ||
| 31 | } | ||
| 32 | }; | ||
| 33 | |||
| 34 | struct platform_device s3c_device_wdt = { | ||
| 35 | .name = "s3c2410-wdt", | ||
| 36 | .id = -1, | ||
| 37 | .num_resources = ARRAY_SIZE(s3c_wdt_resource), | ||
| 38 | .resource = s3c_wdt_resource, | ||
| 39 | }; | ||
| 40 | EXPORT_SYMBOL(s3c_device_wdt); | ||
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index ef69e56b2885..e6144e4b9118 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
| @@ -45,6 +45,7 @@ extern struct platform_device s3c_device_lcd; | |||
| 45 | extern struct platform_device s3c_device_wdt; | 45 | extern struct platform_device s3c_device_wdt; |
| 46 | extern struct platform_device s3c_device_i2c0; | 46 | extern struct platform_device s3c_device_i2c0; |
| 47 | extern struct platform_device s3c_device_i2c1; | 47 | extern struct platform_device s3c_device_i2c1; |
| 48 | extern struct platform_device s3c_device_i2c2; | ||
| 48 | extern struct platform_device s3c_device_rtc; | 49 | extern struct platform_device s3c_device_rtc; |
| 49 | extern struct platform_device s3c_device_adc; | 50 | extern struct platform_device s3c_device_adc; |
| 50 | extern struct platform_device s3c_device_sdi; | 51 | extern struct platform_device s3c_device_sdi; |
| @@ -57,9 +58,20 @@ extern struct platform_device s3c_device_hsmmc2; | |||
| 57 | extern struct platform_device s3c_device_spi0; | 58 | extern struct platform_device s3c_device_spi0; |
| 58 | extern struct platform_device s3c_device_spi1; | 59 | extern struct platform_device s3c_device_spi1; |
| 59 | 60 | ||
| 61 | extern struct platform_device s5pc100_device_spi0; | ||
| 62 | extern struct platform_device s5pc100_device_spi1; | ||
| 63 | extern struct platform_device s5pc100_device_spi2; | ||
| 64 | extern struct platform_device s5pv210_device_spi0; | ||
| 65 | extern struct platform_device s5pv210_device_spi1; | ||
| 66 | extern struct platform_device s5p6440_device_spi0; | ||
| 67 | extern struct platform_device s5p6440_device_spi1; | ||
| 68 | |||
| 60 | extern struct platform_device s3c_device_hwmon; | 69 | extern struct platform_device s3c_device_hwmon; |
| 61 | 70 | ||
| 62 | extern struct platform_device s3c_device_nand; | 71 | extern struct platform_device s3c_device_nand; |
| 72 | extern struct platform_device s3c_device_onenand; | ||
| 73 | extern struct platform_device s3c64xx_device_onenand1; | ||
| 74 | extern struct platform_device s5pc110_device_onenand; | ||
| 63 | 75 | ||
| 64 | extern struct platform_device s3c_device_usbgadget; | 76 | extern struct platform_device s3c_device_usbgadget; |
| 65 | extern struct platform_device s3c_device_usb_hsotg; | 77 | extern struct platform_device s3c_device_usb_hsotg; |
| @@ -76,10 +88,18 @@ extern struct platform_device s5p6442_device_pcm0; | |||
| 76 | extern struct platform_device s5p6442_device_pcm1; | 88 | extern struct platform_device s5p6442_device_pcm1; |
| 77 | extern struct platform_device s5p6442_device_iis0; | 89 | extern struct platform_device s5p6442_device_iis0; |
| 78 | extern struct platform_device s5p6442_device_iis1; | 90 | extern struct platform_device s5p6442_device_iis1; |
| 91 | extern struct platform_device s5p6442_device_spi; | ||
| 79 | 92 | ||
| 80 | extern struct platform_device s5p6440_device_pcm; | 93 | extern struct platform_device s5p6440_device_pcm; |
| 81 | extern struct platform_device s5p6440_device_iis; | 94 | extern struct platform_device s5p6440_device_iis; |
| 82 | 95 | ||
| 96 | extern struct platform_device s5pc100_device_ac97; | ||
| 97 | extern struct platform_device s5pc100_device_pcm0; | ||
| 98 | extern struct platform_device s5pc100_device_pcm1; | ||
| 99 | extern struct platform_device s5pc100_device_iis0; | ||
| 100 | extern struct platform_device s5pc100_device_iis1; | ||
| 101 | extern struct platform_device s5pc100_device_iis2; | ||
| 102 | |||
| 83 | /* s3c2440 specific devices */ | 103 | /* s3c2440 specific devices */ |
| 84 | 104 | ||
| 85 | #ifdef CONFIG_CPU_S3C2440 | 105 | #ifdef CONFIG_CPU_S3C2440 |
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 1f85649d8c18..27d3b497b55b 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h | |||
| @@ -84,4 +84,11 @@ extern void s3c64xx_fb_gpio_setup_24bpp(void); | |||
| 84 | */ | 84 | */ |
| 85 | extern void s5pc100_fb_gpio_setup_24bpp(void); | 85 | extern void s5pc100_fb_gpio_setup_24bpp(void); |
| 86 | 86 | ||
| 87 | /** | ||
| 88 | * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD | ||
| 89 | * | ||
| 90 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | ||
| 91 | */ | ||
| 92 | extern void s5pv210_fb_gpio_setup_24bpp(void); | ||
| 93 | |||
| 87 | #endif /* __PLAT_S3C_FB_H */ | 94 | #endif /* __PLAT_S3C_FB_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/iic-core.h b/arch/arm/plat-samsung/include/plat/iic-core.h index 36397ca20962..f182669b8e8e 100644 --- a/arch/arm/plat-samsung/include/plat/iic-core.h +++ b/arch/arm/plat-samsung/include/plat/iic-core.h | |||
| @@ -32,4 +32,11 @@ static inline void s3c_i2c1_setname(char *name) | |||
| 32 | #endif | 32 | #endif |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline void s3c_i2c2_setname(char *name) | ||
| 36 | { | ||
| 37 | #ifdef CONFIG_S3C_DEV_I2C2 | ||
| 38 | s3c_device_i2c2.name = name; | ||
| 39 | #endif | ||
| 40 | } | ||
| 41 | |||
| 35 | #endif /* __ASM_ARCH_IIC_H */ | 42 | #endif /* __ASM_ARCH_IIC_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h index 3083df00dee6..133308bf595d 100644 --- a/arch/arm/plat-samsung/include/plat/iic.h +++ b/arch/arm/plat-samsung/include/plat/iic.h | |||
| @@ -54,9 +54,11 @@ struct s3c2410_platform_i2c { | |||
| 54 | */ | 54 | */ |
| 55 | extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); | 55 | extern void s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *i2c); |
| 56 | extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); | 56 | extern void s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *i2c); |
| 57 | extern void s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *i2c); | ||
| 57 | 58 | ||
| 58 | /* defined by architecture to configure gpio */ | 59 | /* defined by architecture to configure gpio */ |
| 59 | extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); | 60 | extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); |
| 60 | extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); | 61 | extern void s3c_i2c1_cfg_gpio(struct platform_device *dev); |
| 62 | extern void s3c_i2c2_cfg_gpio(struct platform_device *dev); | ||
| 61 | 63 | ||
| 62 | #endif /* __ASM_ARCH_IIC_H */ | 64 | #endif /* __ASM_ARCH_IIC_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/onenand-core.h b/arch/arm/plat-samsung/include/plat/onenand-core.h new file mode 100644 index 000000000000..7701cb7020c8 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/onenand-core.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-samsung/onenand-core.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2010 Samsung Electronics | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * Marek Szyprowski <m.szyprowski@samsung.com> | ||
| 7 | * | ||
| 8 | * Samsung OneNAD Controller core functions | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_ONENAND_CORE_H | ||
| 16 | #define __ASM_ARCH_ONENAND_CORE_H __FILE__ | ||
| 17 | |||
| 18 | /* These functions are only for use with the core support code, such as | ||
| 19 | * the cpu specific initialisation code | ||
| 20 | */ | ||
| 21 | |||
| 22 | /* re-define device name depending on support. */ | ||
| 23 | static inline void s3c_onenand_setname(char *name) | ||
| 24 | { | ||
| 25 | #ifdef CONFIG_S3C_DEV_ONENAND | ||
| 26 | s3c_device_onenand.name = name; | ||
| 27 | #endif | ||
| 28 | } | ||
| 29 | |||
| 30 | static inline void s3c64xx_onenand1_setname(char *name) | ||
| 31 | { | ||
| 32 | #ifdef CONFIG_S3C64XX_DEV_ONENAND1 | ||
| 33 | s3c64xx_device_onenand1.name = name; | ||
| 34 | #endif | ||
| 35 | } | ||
| 36 | |||
| 37 | #endif /* __ASM_ARCH_ONENAND_CORE_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/regs-onenand.h b/arch/arm/plat-samsung/include/plat/regs-onenand.h new file mode 100644 index 000000000000..930ea8b88ed3 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-onenand.h | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-s3c/include/plat/regs-onenand.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2010 Samsung Electronics | ||
| 5 | * Kyungmin Park <kyungmin.park@samsung.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #ifndef __SAMSUNG_ONENAND_H__ | ||
| 12 | #define __SAMSUNG_ONENAND_H__ | ||
| 13 | |||
| 14 | #include <mach/hardware.h> | ||
| 15 | |||
| 16 | /* | ||
| 17 | * OneNAND Controller | ||
| 18 | */ | ||
| 19 | #define MEM_CFG_OFFSET 0x0000 | ||
| 20 | #define BURST_LEN_OFFSET 0x0010 | ||
| 21 | #define MEM_RESET_OFFSET 0x0020 | ||
| 22 | #define INT_ERR_STAT_OFFSET 0x0030 | ||
| 23 | #define INT_ERR_MASK_OFFSET 0x0040 | ||
| 24 | #define INT_ERR_ACK_OFFSET 0x0050 | ||
| 25 | #define ECC_ERR_STAT_OFFSET 0x0060 | ||
| 26 | #define MANUFACT_ID_OFFSET 0x0070 | ||
| 27 | #define DEVICE_ID_OFFSET 0x0080 | ||
| 28 | #define DATA_BUF_SIZE_OFFSET 0x0090 | ||
| 29 | #define BOOT_BUF_SIZE_OFFSET 0x00A0 | ||
| 30 | #define BUF_AMOUNT_OFFSET 0x00B0 | ||
| 31 | #define TECH_OFFSET 0x00C0 | ||
| 32 | #define FBA_WIDTH_OFFSET 0x00D0 | ||
| 33 | #define FPA_WIDTH_OFFSET 0x00E0 | ||
| 34 | #define FSA_WIDTH_OFFSET 0x00F0 | ||
| 35 | #define TRANS_SPARE_OFFSET 0x0140 | ||
| 36 | #define DBS_DFS_WIDTH_OFFSET 0x0160 | ||
| 37 | #define INT_PIN_ENABLE_OFFSET 0x01A0 | ||
| 38 | #define ACC_CLOCK_OFFSET 0x01C0 | ||
| 39 | #define FLASH_VER_ID_OFFSET 0x01F0 | ||
| 40 | #define FLASH_AUX_CNTRL_OFFSET 0x0300 /* s3c64xx only */ | ||
| 41 | |||
| 42 | #define ONENAND_MEM_RESET_HOT 0x3 | ||
| 43 | #define ONENAND_MEM_RESET_COLD 0x2 | ||
| 44 | #define ONENAND_MEM_RESET_WARM 0x1 | ||
| 45 | |||
| 46 | #define CACHE_OP_ERR (1 << 13) | ||
| 47 | #define RST_CMP (1 << 12) | ||
| 48 | #define RDY_ACT (1 << 11) | ||
| 49 | #define INT_ACT (1 << 10) | ||
| 50 | #define UNSUP_CMD (1 << 9) | ||
| 51 | #define LOCKED_BLK (1 << 8) | ||
| 52 | #define BLK_RW_CMP (1 << 7) | ||
| 53 | #define ERS_CMP (1 << 6) | ||
| 54 | #define PGM_CMP (1 << 5) | ||
| 55 | #define LOAD_CMP (1 << 4) | ||
| 56 | #define ERS_FAIL (1 << 3) | ||
| 57 | #define PGM_FAIL (1 << 2) | ||
| 58 | #define INT_TO (1 << 1) | ||
| 59 | #define LD_FAIL_ECC_ERR (1 << 0) | ||
| 60 | |||
| 61 | #define TSRF (1 << 0) | ||
| 62 | |||
| 63 | #endif | ||
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h index d17724149315..e5aba8f95b79 100644 --- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h +++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h | |||
| @@ -63,5 +63,9 @@ struct s3c64xx_spi_info { | |||
| 63 | * has some chips attached to it. | 63 | * has some chips attached to it. |
| 64 | */ | 64 | */ |
| 65 | extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | 65 | extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); |
| 66 | extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
| 67 | extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
| 68 | extern void s5p6440_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
| 69 | extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); | ||
| 66 | 70 | ||
| 67 | #endif /* __S3C64XX_PLAT_SPI_H */ | 71 | #endif /* __S3C64XX_PLAT_SPI_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index 7d07cd7aa4f2..13f9fb20900a 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h | |||
| @@ -75,6 +75,9 @@ extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | |||
| 75 | extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | 75 | extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w); |
| 76 | extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | 76 | extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w); |
| 77 | extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | 77 | extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); |
| 78 | extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | ||
| 79 | extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | ||
| 80 | extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | ||
| 78 | 81 | ||
| 79 | /* S3C6400 SDHCI setup */ | 82 | /* S3C6400 SDHCI setup */ |
| 80 | 83 | ||
| @@ -218,4 +221,56 @@ static inline void s5pc100_default_sdhci1(void) { } | |||
| 218 | static inline void s5pc100_default_sdhci2(void) { } | 221 | static inline void s5pc100_default_sdhci2(void) { } |
| 219 | #endif /* CONFIG_S5PC100_SETUP_SDHCI */ | 222 | #endif /* CONFIG_S5PC100_SETUP_SDHCI */ |
| 220 | 223 | ||
| 224 | |||
| 225 | /* S5PC110 SDHCI setup */ | ||
| 226 | #ifdef CONFIG_S5PV210_SETUP_SDHCI | ||
| 227 | extern char *s5pv210_hsmmc_clksrcs[4]; | ||
| 228 | |||
| 229 | extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev, | ||
| 230 | void __iomem *r, | ||
| 231 | struct mmc_ios *ios, | ||
| 232 | struct mmc_card *card); | ||
| 233 | |||
| 234 | #ifdef CONFIG_S3C_DEV_HSMMC | ||
| 235 | static inline void s5pv210_default_sdhci0(void) | ||
| 236 | { | ||
| 237 | s3c_hsmmc0_def_platdata.clocks = s5pv210_hsmmc_clksrcs; | ||
| 238 | s3c_hsmmc0_def_platdata.cfg_gpio = s5pv210_setup_sdhci0_cfg_gpio; | ||
| 239 | s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; | ||
| 240 | } | ||
| 241 | #else | ||
| 242 | static inline void s5pc100_default_sdhci0(void) { } | ||
| 243 | #endif /* CONFIG_S3C_DEV_HSMMC */ | ||
| 244 | |||
| 245 | #ifdef CONFIG_S3C_DEV_HSMMC1 | ||
| 246 | static inline void s5pv210_default_sdhci1(void) | ||
| 247 | { | ||
| 248 | s3c_hsmmc1_def_platdata.clocks = s5pv210_hsmmc_clksrcs; | ||
| 249 | s3c_hsmmc1_def_platdata.cfg_gpio = s5pv210_setup_sdhci1_cfg_gpio; | ||
| 250 | s3c_hsmmc1_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; | ||
| 251 | } | ||
| 252 | #else | ||
| 253 | static inline void s5pv210_default_sdhci1(void) { } | ||
| 254 | #endif /* CONFIG_S3C_DEV_HSMMC1 */ | ||
| 255 | |||
| 256 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
| 257 | static inline void s5pv210_default_sdhci2(void) | ||
| 258 | { | ||
| 259 | s3c_hsmmc2_def_platdata.clocks = s5pv210_hsmmc_clksrcs; | ||
| 260 | s3c_hsmmc2_def_platdata.cfg_gpio = s5pv210_setup_sdhci2_cfg_gpio; | ||
| 261 | s3c_hsmmc2_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; | ||
| 262 | } | ||
| 263 | #else | ||
| 264 | static inline void s5pv210_default_sdhci2(void) { } | ||
| 265 | #endif /* CONFIG_S3C_DEV_HSMMC2 */ | ||
| 266 | |||
| 267 | #else | ||
| 268 | static inline void s5pv210_default_sdhci0(void) { } | ||
| 269 | static inline void s5pv210_default_sdhci1(void) { } | ||
| 270 | static inline void s5pv210_default_sdhci2(void) { } | ||
| 271 | #endif /* CONFIG_S5PC100_SETUP_SDHCI */ | ||
| 272 | |||
| 273 | |||
| 274 | |||
| 275 | |||
| 221 | #endif /* __PLAT_S3C_SDHCI_H */ | 276 | #endif /* __PLAT_S3C_SDHCI_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/wakeup-mask.h b/arch/arm/plat-samsung/include/plat/wakeup-mask.h new file mode 100644 index 000000000000..43e4acd2e1c6 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/wakeup-mask.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* arch/arm/plat-samsung/include/plat/wakeup-mask.h | ||
| 2 | * | ||
| 3 | * Copyright 2010 Ben Dooks <ben-linux@fluff.org> | ||
| 4 | * | ||
| 5 | * Support for wakeup mask interrupts on newer SoCs | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __PLAT_WAKEUP_MASK_H | ||
| 14 | #define __PLAT_WAKEUP_MASK_H __file__ | ||
| 15 | |||
| 16 | /* if no irq yet defined, but still want to mask */ | ||
| 17 | #define NO_WAKEUP_IRQ (0x90000000) | ||
| 18 | |||
| 19 | /** | ||
| 20 | * struct samsung_wakeup_mask - wakeup mask information | ||
| 21 | * @irq: The interrupt associated with this wakeup. | ||
| 22 | * @bit: The bit, as a (1 << bitno) controlling this source. | ||
| 23 | */ | ||
| 24 | struct samsung_wakeup_mask { | ||
| 25 | unsigned int irq; | ||
| 26 | u32 bit; | ||
| 27 | }; | ||
| 28 | |||
| 29 | /** | ||
| 30 | * samsung_sync_wakemask - sync wakeup mask information for pm | ||
| 31 | * @reg: The register that is used. | ||
| 32 | * @masks: The list of masks to use. | ||
| 33 | * @nr_masks: The number of entries pointed to buy @masks. | ||
| 34 | * | ||
| 35 | * Synchronise the wakeup mask information at suspend time from the list | ||
| 36 | * of interrupts and control bits in @masks. We do this at suspend time | ||
| 37 | * as overriding the relevant irq chips is harder and the register is only | ||
| 38 | * required to be correct before we enter sleep. | ||
| 39 | */ | ||
| 40 | extern void samsung_sync_wakemask(void __iomem *reg, | ||
| 41 | struct samsung_wakeup_mask *masks, | ||
| 42 | int nr_masks); | ||
| 43 | |||
| 44 | #endif /* __PLAT_WAKEUP_MASK_H */ | ||
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index d50ab9d2af53..7df03f87fbfa 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c | |||
| @@ -331,8 +331,10 @@ void s3c_pm_save_gpios(void) | |||
| 331 | 331 | ||
| 332 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { | 332 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { |
| 333 | ourchip = s3c_gpiolib_getchip(gpio_nr); | 333 | ourchip = s3c_gpiolib_getchip(gpio_nr); |
| 334 | if (!ourchip) | 334 | if (!ourchip) { |
| 335 | gpio_nr++; | ||
| 335 | continue; | 336 | continue; |
| 337 | } | ||
| 336 | 338 | ||
| 337 | s3c_pm_save_gpio(ourchip); | 339 | s3c_pm_save_gpio(ourchip); |
| 338 | 340 | ||
| @@ -369,8 +371,10 @@ void s3c_pm_restore_gpios(void) | |||
| 369 | 371 | ||
| 370 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { | 372 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { |
| 371 | ourchip = s3c_gpiolib_getchip(gpio_nr); | 373 | ourchip = s3c_gpiolib_getchip(gpio_nr); |
| 372 | if (!ourchip) | 374 | if (!ourchip) { |
| 375 | gpio_nr++; | ||
| 373 | continue; | 376 | continue; |
| 377 | } | ||
| 374 | 378 | ||
| 375 | s3c_pm_resume_gpio(ourchip); | 379 | s3c_pm_resume_gpio(ourchip); |
| 376 | 380 | ||
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c new file mode 100644 index 000000000000..2e09b6ad84ca --- /dev/null +++ b/arch/arm/plat-samsung/wakeup-mask.c | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* arch/arm/plat-samsung/wakeup-mask.c | ||
| 2 | * | ||
| 3 | * Copyright 2010 Ben Dooks <ben-linux@fluff.org> | ||
| 4 | * | ||
| 5 | * Support for wakeup mask interrupts on newer SoCs | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/spinlock.h> | ||
| 14 | #include <linux/sysdev.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | |||
| 19 | #include <plat/wakeup-mask.h> | ||
| 20 | #include <plat/pm.h> | ||
| 21 | |||
| 22 | void samsung_sync_wakemask(void __iomem *reg, | ||
| 23 | struct samsung_wakeup_mask *mask, int nr_mask) | ||
| 24 | { | ||
| 25 | struct irq_desc *desc; | ||
| 26 | u32 val; | ||
| 27 | |||
| 28 | val = __raw_readl(reg); | ||
| 29 | |||
| 30 | for (; nr_mask > 0; nr_mask--, mask++) { | ||
| 31 | if (mask->irq == NO_WAKEUP_IRQ) { | ||
| 32 | val |= mask->bit; | ||
| 33 | continue; | ||
| 34 | } | ||
| 35 | |||
| 36 | desc = irq_to_desc(mask->irq); | ||
| 37 | |||
| 38 | /* bit of a liberty to read this directly from irq_desc. */ | ||
| 39 | if (desc->wake_depth > 0) | ||
| 40 | val &= ~mask->bit; | ||
| 41 | else | ||
| 42 | val |= mask->bit; | ||
| 43 | } | ||
| 44 | |||
| 45 | printk(KERN_INFO "wakemask %08x => %08x\n", __raw_readl(reg), val); | ||
| 46 | __raw_writel(val, reg); | ||
| 47 | } | ||