Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] Fix scheduling latency issue on 24K, 34K and 74K cores
  [MIPS] Add macros to encode processor revisions.
  [MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.
  [MIPS] SMTC: Fix cut'n'paste bug in Kconfig.debug
  [MIPS] Change libgcc-style functions from lib-y to obj-y
  [MIPS] Fix timer/performance interrupt detection
  [MIPS] AP/SP: Avoid triggering the 34K E125 performance issue
  [MIPS] 64-bit TO_PHYS_MASK macro for RM9000 processors

5 files changed, 19 insertions, 12 deletions

diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 72d5c198e790..3efe117721aa 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -37,7 +37,7 @@ config DEBUG_STACK_USAGE
 
           This option will slow down process creation somewhat.
 
-config CONFIG_SMTC_IDLE_HOOK_DEBUG
+config SMTC_IDLE_HOOK_DEBUG
         bool "Enable additional debug checks before going into CPU idle loop"
         depends on DEBUG_KERNEL && MIPS_MT_SMTC
         help
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0fc90ba16ae1..b12eeee0e974 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -137,13 +137,24 @@ static inline void check_wait(void)
         case CPU_4KEC:
         case CPU_4KSC:
         case CPU_5KC:
-        case CPU_24K:
         case CPU_25KF:
+        case CPU_PR4450:
+                cpu_wait = r4k_wait;
+                break;
+
+        case CPU_24K:
         case CPU_34K:
+                cpu_wait = r4k_wait;
+                if (read_c0_config7() & MIPS_CONF7_WII)
+                        cpu_wait = r4k_wait_irqoff;
+                break;
+
         case CPU_74K:
-        case CPU_PR4450:
                 cpu_wait = r4k_wait;
+                if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
+                        cpu_wait = r4k_wait_irqoff;
                 break;
+
         case CPU_TX49XX:
                 cpu_wait = r4k_wait_irqoff;
                 break;
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index b1233644fcca..3ea7863c4519 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1372,12 +1372,12 @@ void __init per_cpu_trap_init(void)
          */
         if (cpu_has_mips_r2) {
                 cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
-                cp0_perfcount_irq = -1;
-        } else {
-                cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
                 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
-                if (cp0_perfcount_irq != cp0_compare_irq)
+                if (cp0_perfcount_irq == cp0_compare_irq)
                         cp0_perfcount_irq = -1;
+        } else {
+                cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
+                cp0_perfcount_irq = -1;
         }
 
 #ifdef CONFIG_MIPS_MT_SMTC
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index c9ee9d2d5856..9e66354dee8b 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1436,10 +1436,6 @@ static int __init vpe_module_init(void)
                         write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() & ~VPECONTROL_TE);
 
                         if (i != 0) {
-                                write_vpe_c0_status((read_c0_status() &
-                                                     ~(ST0_IM | ST0_IE | ST0_KSU))
-                                                    | ST0_CU0);
-
                                 /*
                                  * Set config to be the same as vpe0,
                                  * particularly kseg0 coherency alg
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 5dad13efba7e..1c1aa9f92f6c 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -9,4 +9,4 @@ obj-y			+= iomap.o
 obj-$(CONFIG_PCI)       += iomap-pci.o
 
 # libgcc-style stuff needed in the kernel
-lib-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o
+obj-y += ashldi3.o ashrdi3.o lshrdi3.o ucmpdi2.o