Merge with mainline to remove plat-omap/Kconfig conflict

Conflicts:
	arch/arm/plat-omap/Kconfig

1186 files changed, 44463 insertions, 22959 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 9d055b4f0585..215e46073c45 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -3,11 +3,9 @@
 #
 
 config OPROFILE
-        tristate "OProfile system profiling (EXPERIMENTAL)"
+        tristate "OProfile system profiling"
         depends on PROFILING
         depends on HAVE_OPROFILE
-        depends on TRACING_SUPPORT
-        select TRACING
         select RING_BUFFER
         select RING_BUFFER_ALLOW_SWAP
         help
@@ -17,20 +15,6 @@ config OPROFILE
 
           If unsure, say N.
 
-config OPROFILE_IBS
-        bool "OProfile AMD IBS support (EXPERIMENTAL)"
-        default n
-        depends on OPROFILE && SMP && X86
-        help
-          Instruction-Based Sampling (IBS) is a new profiling
-          technique that provides rich, precise program performance
-          information. IBS is introduced by AMD Family10h processors
-          (AMD Opteron Quad-Core processor "Barcelona") to overcome
-          the limitations of conventional performance counter
-          sampling.
-
-          If unsure, say N.
-
 config OPROFILE_EVENT_MULTIPLEX
         bool "OProfile multiplexing support (EXPERIMENTAL)"
         default n
@@ -121,6 +105,14 @@ config HAVE_DMA_ATTRS
 config USE_GENERIC_SMP_HELPERS
         bool
 
+config HAVE_REGS_AND_STACK_ACCESS_API
+        bool
+        help
+          This symbol should be selected by an architecure if it supports
+          the API needed to access registers and stack entries from pt_regs,
+          declared in asm/ptrace.h
+          For example the kprobes-based event tracer needs this API.
+
 config HAVE_CLK
         bool
         help
diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h
index 3f0c59f6d8aa..71a243294142 100644
--- a/arch/alpha/include/asm/pgtable.h
+++ b/arch/alpha/include/asm/pgtable.h
@@ -329,7 +329,7 @@ extern pgd_t swapper_pg_dir[1024];
  * tables contain all the necessary information.
  */
 extern inline void update_mmu_cache(struct vm_area_struct * vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/alpha/kernel/pci.c b/arch/alpha/kernel/pci.c
index a91ba28999b5..c9ab94ee1ca8 100644
--- a/arch/alpha/kernel/pci.c
+++ b/arch/alpha/kernel/pci.c
@@ -126,8 +126,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
 #define MB                      (1024*KB)
 #define GB                      (1024*MB)
 
-void
-pcibios_align_resource(void *data, struct resource *res,
+resource_size_t
+pcibios_align_resource(void *data, const struct resource *res,
                        resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
@@ -184,7 +184,7 @@ pcibios_align_resource(void *data, struct resource *res,
                 }
         }
 
-        res->start = start;
+        return start;
 }
 #undef KB
 #undef MB
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 184a6bd54825..3b181284970f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,6 +12,7 @@ config ARM
         select HAVE_IDE
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
+        select GENERIC_ATOMIC64 if (!CPU_32v6K)
         select HAVE_OPROFILE
         select HAVE_ARCH_KGDB
         select HAVE_KPROBES if (!XIP_KERNEL)
@@ -20,6 +21,8 @@ config ARM
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_LZO
+        select HAVE_PERF_EVENTS
+        select PERF_USE_VMALLOC
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -52,6 +55,9 @@ config HAVE_TCM
         bool
         select GENERIC_ALLOCATOR
 
+config HAVE_PROC_CPU
+        bool
+
 config NO_IOPORT
         bool
 
@@ -161,6 +167,11 @@ config ARCH_MTD_XIP
 config GENERIC_HARDIRQS_NO__DO_IRQ
         def_bool y
 
+config ARM_L1_CACHE_SHIFT_6
+        bool
+        help
+          Setting ARM L1 cache line size to 64 Bytes.
+
 if OPROFILE
 
 config OPROFILE_ARMV6
@@ -550,10 +561,20 @@ config ARCH_W90X900
           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 
+config ARCH_NUC93X
+        bool "Nuvoton NUC93X CPU"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        help
+          Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
+          low-power and high performance MPEG-4/JPEG multimedia controller chip.
+
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
         select CPU_ARM926T
         select HAVE_CLK
+        select COMMON_CLKDEV
         help
           This enables support for Philips PNX4008 mobile platform.
 
@@ -638,6 +659,7 @@ config ARCH_S5PC1XX
         select GENERIC_GPIO
         select HAVE_CLK
         select CPU_V7
+        select ARM_L1_CACHE_SHIFT_6
         help
           Samsung S5PC1XX series based systems
 
@@ -785,6 +807,8 @@ source "arch/arm/plat-nomadik/Kconfig"
 
 source "arch/arm/mach-ns9xxx/Kconfig"
 
+source "arch/arm/mach-nuc93x/Kconfig"
+
 source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
@@ -867,6 +891,11 @@ config XSCALE_PMU
         depends on CPU_XSCALE && !XSCALE_PMU_TIMER
         default y
 
+config CPU_HAS_PMU
+        depends on CPU_V6 || CPU_V7 || XSCALE_PMU
+        default y
+        bool
+
 if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
@@ -921,6 +950,19 @@ config ARM_ERRATA_460075
           ACTLR register. Note that setting specific bits in the ACTLR register
           may not be available in non-secure mode.
 
+config PL310_ERRATA_588369
+        bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+        depends on CACHE_L2X0 && ARCH_OMAP4
+        help
+           The PL310 L2 cache controller implements three types of Clean &
+           Invalidate maintenance operations: by Physical Address
+           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+           They are architecturally defined to behave as the execution of a
+           clean operation followed immediately by an invalidate operation,
+           both performing to the same memory location. This functionality
+           is not correctly implemented in PL310 as clean lines are not
+           invalidated as a result of these operations. Note that this errata
+           uses Texas Instrument's secure monitor api.
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1171,6 +1213,14 @@ config HIGHPTE
         depends on HIGHMEM
         depends on !OUTER_CACHE
 
+config HW_PERF_EVENTS
+        bool "Enable hardware performance counter support for perf events"
+        depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
+        default y
+        help
+          Enable hardware performance counter support for perf events. If
+          disabled, perf events will use software events only.
+
 source "mm/Kconfig"
 
 config LEDS
@@ -1230,6 +1280,7 @@ config ALIGNMENT_TRAP
         bool
         depends on CPU_CP15_MMU
         default y if !ARCH_EBSA110
+        select HAVE_PROC_CPU if PROC_FS
         help
           ARM processors cannot fetch/store information which is not
           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 356d702c0808..81f54ca30788 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -171,6 +171,7 @@ machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_U8500)            := ux500
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
+machine-$(CONFIG_ARCH_NUC93X)           := nuc93x
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
 
 # Platform directory name.  This list is sorted alphanumerically
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 2d4d88ba73bf..97c89e7de7d3 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -5,7 +5,7 @@
 #
 
 HEAD    = head.o
-OBJS    = misc.o
+OBJS    = misc.o decompress.o
 FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
 
 #
@@ -106,10 +106,6 @@ lib1funcs = $(obj)/lib1funcs.o
 $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
         $(call cmd,shipped)
 
-# Don't allow any static data in misc.o, which
-# would otherwise mess up our GOT table
-CFLAGS_misc.o := -Dstatic=
-
 $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
                 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
         $(call if_changed,ld)
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
new file mode 100644
index 000000000000..0da382f33157
--- /dev/null
+++ b/arch/arm/boot/compressed/decompress.c
@@ -0,0 +1,45 @@
+#define _LINUX_STRING_H_
+
+#include <linux/compiler.h>     /* for inline */
+#include <linux/types.h>        /* for size_t */
+#include <linux/stddef.h>       /* for NULL */
+#include <linux/linkage.h>
+#include <asm/string.h>
+
+extern unsigned long free_mem_ptr;
+extern unsigned long free_mem_end_ptr;
+extern void error(char *);
+
+#define STATIC static
+
+#define ARCH_HAS_DECOMP_WDOG
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+#ifdef CONFIG_KERNEL_GZIP
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZO
+#include "../../../../lib/decompress_unlzo.c"
+#endif
+
+void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
+{
+        decompress(input, len, NULL, NULL, output, NULL, error);
+}
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 56a0d116d271..d32bc71c1f78 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -23,8 +23,8 @@ unsigned int __machine_arch_type;
 #include <linux/compiler.h>     /* for inline */
 #include <linux/types.h>        /* for size_t */
 #include <linux/stddef.h>       /* for NULL */
-#include <asm/string.h>
 #include <linux/linkage.h>
+#include <asm/string.h>
 
 #include <asm/unaligned.h>
 
@@ -117,57 +117,7 @@ static void putstr(const char *ptr)
 
 #endif
 
-#define __ptr_t void *
-
-#define memzero(s,n) __memzero(s,n)
-
-/*
- * Optimised C version of memzero for the ARM.
- */
-void __memzero (__ptr_t s, size_t n)
-{
-        union { void *vp; unsigned long *ulp; unsigned char *ucp; } u;
-        int i;
-
-        u.vp = s;
-
-        for (i = n >> 5; i > 0; i--) {
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-        }
-
-        if (n & 1 << 4) {
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-        }
-
-        if (n & 1 << 3) {
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-        }
-
-        if (n & 1 << 2)
-                *u.ulp++ = 0;
-
-        if (n & 1 << 1) {
-                *u.ucp++ = 0;
-                *u.ucp++ = 0;
-        }
-
-        if (n & 1)
-                *u.ucp++ = 0;
-}
-
-static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
-                            size_t __n)
+void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
         int i = 0;
         unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
@@ -204,59 +154,20 @@ static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
 /*
  * gzip delarations
  */
-#define STATIC static
-
-/* Diagnostic functions */
-#ifdef DEBUG
-#  define Assert(cond,msg) {if(!(cond)) error(msg);}
-#  define Trace(x) fprintf x
-#  define Tracev(x) {if (verbose) fprintf x ;}
-#  define Tracevv(x) {if (verbose>1) fprintf x ;}
-#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
-#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
-#else
-#  define Assert(cond,msg)
-#  define Trace(x)
-#  define Tracev(x)
-#  define Tracevv(x)
-#  define Tracec(c,x)
-#  define Tracecv(c,x)
-#endif
-
-static void error(char *m);
-
 extern char input_data[];
 extern char input_data_end[];
 
-static unsigned char *output_data;
-static unsigned long output_ptr;
-
-static void error(char *m);
+unsigned char *output_data;
+unsigned long output_ptr;
 
-static void putstr(const char *);
-
-static unsigned long free_mem_ptr;
-static unsigned long free_mem_end_ptr;
-
-#ifdef STANDALONE_DEBUG
-#define NO_INFLATE_MALLOC
-#endif
-
-#define ARCH_HAS_DECOMP_WDOG
-
-#ifdef CONFIG_KERNEL_GZIP
-#include "../../../../lib/decompress_inflate.c"
-#endif
-
-#ifdef CONFIG_KERNEL_LZO
-#include "../../../../lib/decompress_unlzo.c"
-#endif
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
 
 #ifndef arch_error
 #define arch_error(x)
 #endif
 
-static void error(char *x)
+void error(char *x)
 {
         arch_error(x);
 
@@ -272,6 +183,8 @@ asmlinkage void __div0(void)
         error("Attempting division by 0!");
 }
 
+extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
+
 #ifndef STANDALONE_DEBUG
 
 unsigned long
@@ -292,8 +205,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
         output_ptr = get_unaligned_le32(tmp);
 
         putstr("Uncompressing Linux...");
-        decompress(input_data, input_data_end - input_data,
-                        NULL, NULL, output_data, NULL, error);
+        do_decompress(input_data, input_data_end - input_data,
+                        output_data, error);
         putstr(" done, booting the kernel.\n");
         return output_ptr;
 }
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index a5924b9b88bd..7ca9ecff652f 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -14,6 +14,13 @@ SECTIONS
   /DISCARD/ : {
     *(.ARM.exidx*)
     *(.ARM.extab*)
+    /*
+     * Discard any r/w data - this produces a link error if we have any,
+     * which is required for PIC decompression.  Local data generates
+     * GOTOFF relocations, which prevents it being relocated independently
+     * of the text/got segments.
+     */
+    *(.data)
   }
 
   . = TEXT_START;
@@ -40,7 +47,6 @@ SECTIONS
   .got                  : { *(.got) }
   _got_end = .;
   .got.plt              : { *(.got.plt) }
-  .data                 : { *(.data) }
   _edata = .;
 
   . = BSS_START;
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
index aae5bc01acc8..446b696196e3 100644
--- a/arch/arm/common/clkdev.c
+++ b/arch/arm/common/clkdev.c
@@ -99,6 +99,16 @@ void clkdev_add(struct clk_lookup *cl)
 }
 EXPORT_SYMBOL(clkdev_add);
 
+void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
+{
+        mutex_lock(&clocks_mutex);
+        while (num--) {
+                list_add_tail(&cl->node, &clocks);
+                cl++;
+        }
+        mutex_unlock(&clocks_mutex);
+}
+
 #define MAX_DEV_ID      20
 #define MAX_CON_ID      16
 
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index cc32c1e54a59..cc0a932bbea9 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
                  * We don't need to sync the DMA buffer since
                  * it was allocated via the coherent allocators.
                  */
-                dma_cache_maint(ptr, size, dir);
+                __dma_single_cpu_to_dev(ptr, size, dir);
         }
 
         return dma_addr;
@@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
                         __cpuc_flush_dcache_area(ptr, size);
                 }
                 free_safe_buffer(dev->archdata.dmabounce, buf);
+        } else {
+                __dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir);
         }
 }
 
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index f232941de8ab..1cf999ade4bc 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -18,6 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
@@ -28,48 +29,6 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
-static void vic_ack_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-        /* moreover, clear the soft-triggered, in case it was the reason */
-        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
-}
-
-static void vic_mask_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-}
-
-static void vic_unmask_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE);
-}
-
-/**
- * vic_init2 - common initialisation code
- * @base: Base of the VIC.
- *
- * Common initialisation code for registeration
- * and resume.
-*/
-static void vic_init2(void __iomem *base)
-{
-        int i;
-
-        for (i = 0; i < 16; i++) {
-                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                writel(VIC_VECT_CNTL_ENABLE | i, reg);
-        }
-
-        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-}
-
 #if defined(CONFIG_PM)
 /**
  * struct vic_device - VIC PM device
@@ -99,13 +58,34 @@ struct vic_device {
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 
+static int vic_id;
+
 static inline struct vic_device *to_vic(struct sys_device *sys)
 {
         return container_of(sys, struct vic_device, sysdev);
 }
+#endif /* CONFIG_PM */
 
-static int vic_id;
+/**
+ * vic_init2 - common initialisation code
+ * @base: Base of the VIC.
+ *
+ * Common initialisation code for registeration
+ * and resume.
+*/
+static void vic_init2(void __iomem *base)
+{
+        int i;
+
+        for (i = 0; i < 16; i++) {
+                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                writel(VIC_VECT_CNTL_ENABLE | i, reg);
+        }
+
+        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+}
 
+#if defined(CONFIG_PM)
 static int vic_class_resume(struct sys_device *dev)
 {
         struct vic_device *vic = to_vic(dev);
@@ -159,31 +139,6 @@ struct sysdev_class vic_class = {
 };
 
 /**
- * vic_pm_register - Register a VIC for later power management control
- * @base: The base address of the VIC.
- * @irq: The base IRQ for the VIC.
- * @resume_sources: bitmask of interrupts allowed for resume sources.
- *
- * Register the VIC with the system device tree so that it can be notified
- * of suspend and resume requests and ensure that the correct actions are
- * taken to re-instate the settings on resume.
- */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
-{
-        struct vic_device *v;
-
-        if (vic_id >= ARRAY_SIZE(vic_devices))
-                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-        else {
-                v = &vic_devices[vic_id];
-                v->base = base;
-                v->resume_sources = resume_sources;
-                v->irq = irq;
-                vic_id++;
-        }
-}
-
-/**
  * vic_pm_init - initicall to register VIC pm
  *
  * This is called via late_initcall() to register
@@ -219,9 +174,60 @@ static int __init vic_pm_init(void)
 
         return 0;
 }
-
 late_initcall(vic_pm_init);
 
+/**
+ * vic_pm_register - Register a VIC for later power management control
+ * @base: The base address of the VIC.
+ * @irq: The base IRQ for the VIC.
+ * @resume_sources: bitmask of interrupts allowed for resume sources.
+ *
+ * Register the VIC with the system device tree so that it can be notified
+ * of suspend and resume requests and ensure that the correct actions are
+ * taken to re-instate the settings on resume.
+ */
+static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+{
+        struct vic_device *v;
+
+        if (vic_id >= ARRAY_SIZE(vic_devices))
+                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
+        else {
+                v = &vic_devices[vic_id];
+                v->base = base;
+                v->resume_sources = resume_sources;
+                v->irq = irq;
+                vic_id++;
+        }
+}
+#else
+static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
+#endif /* CONFIG_PM */
+
+static void vic_ack_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+        /* moreover, clear the soft-triggered, in case it was the reason */
+        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
+}
+
+static void vic_mask_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+}
+
+static void vic_unmask_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE);
+}
+
+#if defined(CONFIG_PM)
 static struct vic_device *vic_from_irq(unsigned int irq)
 {
         struct vic_device *v = vic_devices;
@@ -255,10 +261,7 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
 
         return 0;
 }
-
 #else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-
 #define vic_set_wake NULL
 #endif /* CONFIG_PM */
 
@@ -270,9 +273,62 @@ static struct irq_chip vic_chip = {
         .set_wake = vic_set_wake,
 };
 
-/* The PL190 cell from ARM has been modified by ST, so handle both here */
-static void vik_init_st(void __iomem *base, unsigned int irq_start,
-                         u32 vic_sources);
+/*
+ * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
+ * The original cell has 32 interrupts, while the modified one has 64,
+ * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
+ * the probe function is called twice, with base set to offset 000
+ *  and 020 within the page. We call this "second block".
+ */
+static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
+                                u32 vic_sources)
+{
+        unsigned int i;
+        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
+
+        /* Disable all interrupts initially. */
+
+        writel(0, base + VIC_INT_SELECT);
+        writel(0, base + VIC_INT_ENABLE);
+        writel(~0, base + VIC_INT_ENABLE_CLEAR);
+        writel(0, base + VIC_IRQ_STATUS);
+        writel(0, base + VIC_ITCR);
+        writel(~0, base + VIC_INT_SOFT_CLEAR);
+
+        /*
+         * Make sure we clear all existing interrupts. The vector registers
+         * in this cell are after the second block of general registers,
+         * so we can address them using standard offsets, but only from
+         * the second base address, which is 0x20 in the page
+         */
+        if (vic_2nd_block) {
+                writel(0, base + VIC_PL190_VECT_ADDR);
+                for (i = 0; i < 19; i++) {
+                        unsigned int value;
+
+                        value = readl(base + VIC_PL190_VECT_ADDR);
+                        writel(value, base + VIC_PL190_VECT_ADDR);
+                }
+                /* ST has 16 vectors as well, but we don't enable them by now */
+                for (i = 0; i < 16; i++) {
+                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                        writel(0, reg);
+                }
+
+                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+        }
+
+        for (i = 0; i < 32; i++) {
+                if (vic_sources & (1 << i)) {
+                        unsigned int irq = irq_start + i;
+
+                        set_irq_chip(irq, &vic_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+}
 
 /**
  * vic_init - initialise a vectored interrupt controller
@@ -299,7 +355,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
         switch(vendor) {
         case AMBA_VENDOR_ST:
-                vik_init_st(base, irq_start, vic_sources);
+                vic_init_st(base, irq_start, vic_sources);
                 return;
         default:
                 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
@@ -343,60 +399,3 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
         vic_pm_register(base, irq_start, resume_sources);
 }
-
-/*
- * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
- * The original cell has 32 interrupts, while the modified one has 64,
- * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
- * the probe function is called twice, with base set to offset 000
- *  and 020 within the page. We call this "second block".
- */
-static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
-                                u32 vic_sources)
-{
-        unsigned int i;
-        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
-
-        /* Disable all interrupts initially. */
-
-        writel(0, base + VIC_INT_SELECT);
-        writel(0, base + VIC_INT_ENABLE);
-        writel(~0, base + VIC_INT_ENABLE_CLEAR);
-        writel(0, base + VIC_IRQ_STATUS);
-        writel(0, base + VIC_ITCR);
-        writel(~0, base + VIC_INT_SOFT_CLEAR);
-
-        /*
-         * Make sure we clear all existing interrupts. The vector registers
-         * in this cell are after the second block of general registers,
-         * so we can address them using standard offsets, but only from
-         * the second base address, which is 0x20 in the page
-         */
-        if (vic_2nd_block) {
-                writel(0, base + VIC_PL190_VECT_ADDR);
-                for (i = 0; i < 19; i++) {
-                        unsigned int value;
-
-                        value = readl(base + VIC_PL190_VECT_ADDR);
-                        writel(value, base + VIC_PL190_VECT_ADDR);
-                }
-                /* ST has 16 vectors as well, but we don't enable them by now */
-                for (i = 0; i < 16; i++) {
-                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                        writel(0, reg);
-                }
-
-                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-        }
-
-        for (i = 0; i < 32; i++) {
-                if (vic_sources & (1 << i)) {
-                        unsigned int irq = irq_start + i;
-
-                        set_irq_chip(irq, &vic_chip);
-                        set_irq_chip_data(irq, base);
-                        set_irq_handler(irq, handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-}
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig
new file mode 100644
index 000000000000..76d724b8041a
--- /dev/null
+++ b/arch/arm/configs/at572d940hfek_defconfig
@@ -0,0 +1,1640 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc7
+# Fri Dec  5 10:58:47 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-AT572D940HF"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+# CONFIG_TASK_DELAY_ACCT is not set
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_ARCH_AT572D940HF=y
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT572D940HF Board Type
+#
+CONFIG_MACH_AT572D940HFEB=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
+CONFIG_NUM_SERIAL=3
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_RESOURCES_64BIT=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_TCPPROBE=m
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_DEBUG_DEVICES=y
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=m
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_MTD_OOPS=m
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_RAM=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_ABSENT=m
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x4000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=m
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=m
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+CONFIG_MTD_M25P80=m
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_BLOCK2MTD=m
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
+# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
+# CONFIG_MTD_NAND_ATMEL is not set
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_ALAUDA=m
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
+CONFIG_ATMEL_SSC=m
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+CONFIG_WLAN_PRE80211=y
+CONFIG_STRIP=m
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+# CONFIG_MOUSE_BCM5974 is not set
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOUSE_GPIO=m
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_RISCOM8 is not set
+CONFIG_SPECIALIX=m
+CONFIG_RIO=m
+# CONFIG_RIO_OLDPCI is not set
+CONFIG_STALDRV=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=y
+CONFIG_NVRAM=m
+CONFIG_R3964=m
+CONFIG_RAW_DRIVER=m
+CONFIG_MAX_RAW_DEVS=256
+CONFIG_TCG_TPM=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_ATMEL=m
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_DS1682=m
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=m
+CONFIG_SENSORS_PCF8574=m
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_MAX6875=m
+CONFIG_SENSORS_TSL2550=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_BITBANG=m
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_AT25=m
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_PCM_OSS_PLUGINS is not set
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_VIRMIDI=m
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+# CONFIG_SND_AT73C213 is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BRIGHT=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DELL=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=m
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+CONFIG_RTC_DRV_DS1305=y
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+CONFIG_REISERFS_CHECK=y
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+# CONFIG_UBIFS_FS is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 7ac3fbf0fe04..a96bca290cd1 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -242,10 +242,13 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_GIC=y
 
 #
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index d0daeab2234e..e8ddec2cb158 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -235,6 +235,234 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 #define smp_mb__before_atomic_inc()     smp_mb()
 #define smp_mb__after_atomic_inc()      smp_mb()
 
+#ifndef CONFIG_GENERIC_ATOMIC64
+typedef struct {
+        u64 __aligned(8) counter;
+} atomic64_t;
+
+#define ATOMIC64_INIT(i) { (i) }
+
+static inline u64 atomic64_read(atomic64_t *v)
+{
+        u64 result;
+
+        __asm__ __volatile__("@ atomic64_read\n"
+"       ldrexd  %0, %H0, [%1]"
+        : "=&r" (result)
+        : "r" (&v->counter)
+        );
+
+        return result;
+}
+
+static inline void atomic64_set(atomic64_t *v, u64 i)
+{
+        u64 tmp;
+
+        __asm__ __volatile__("@ atomic64_set\n"
+"1:     ldrexd  %0, %H0, [%1]\n"
+"       strexd  %0, %2, %H2, [%1]\n"
+"       teq     %0, #0\n"
+"       bne     1b"
+        : "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline void atomic64_add(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        __asm__ __volatile__("@ atomic64_add\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       adds    %0, %0, %3\n"
+"       adc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_add_return\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       adds    %0, %0, %3\n"
+"       adc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline void atomic64_sub(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        __asm__ __volatile__("@ atomic64_sub\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       subs    %0, %0, %3\n"
+"       sbc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_sub_return\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       subs    %0, %0, %3\n"
+"       sbc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
+{
+        u64 oldval;
+        unsigned long res;
+
+        smp_mb();
+
+        do {
+                __asm__ __volatile__("@ atomic64_cmpxchg\n"
+                "ldrexd         %1, %H1, [%2]\n"
+                "mov            %0, #0\n"
+                "teq            %1, %3\n"
+                "teqeq          %H1, %H3\n"
+                "strexdeq       %0, %4, %H4, [%2]"
+                : "=&r" (res), "=&r" (oldval)
+                : "r" (&ptr->counter), "r" (old), "r" (new)
+                : "cc");
+        } while (res);
+
+        smp_mb();
+
+        return oldval;
+}
+
+static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_xchg\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       strexd  %1, %3, %H3, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&ptr->counter), "r" (new)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline u64 atomic64_dec_if_positive(atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_dec_if_positive\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       subs    %0, %0, #1\n"
+"       sbc     %H0, %H0, #0\n"
+"       teq     %H0, #0\n"
+"       bmi     2f\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b\n"
+"2:"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
+{
+        u64 val;
+        unsigned long tmp;
+        int ret = 1;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_add_unless\n"
+"1:     ldrexd  %0, %H0, [%3]\n"
+"       teq     %0, %4\n"
+"       teqeq   %H0, %H4\n"
+"       moveq   %1, #0\n"
+"       beq     2f\n"
+"       adds    %0, %0, %5\n"
+"       adc     %H0, %H0, %H5\n"
+"       strexd  %2, %0, %H0, [%3]\n"
+"       teq     %2, #0\n"
+"       bne     1b\n"
+"2:"
+        : "=&r" (val), "=&r" (ret), "=&r" (tmp)
+        : "r" (&v->counter), "r" (u), "r" (a)
+        : "cc");
+
+        if (ret)
+                smp_mb();
+
+        return ret;
+}
+
+#define atomic64_add_negative(a, v)     (atomic64_add_return((a), (v)) < 0)
+#define atomic64_inc(v)                 atomic64_add(1LL, (v))
+#define atomic64_inc_return(v)          atomic64_add_return(1LL, (v))
+#define atomic64_inc_and_test(v)        (atomic64_inc_return(v) == 0)
+#define atomic64_sub_and_test(a, v)     (atomic64_sub_return((a), (v)) == 0)
+#define atomic64_dec(v)                 atomic64_sub(1LL, (v))
+#define atomic64_dec_return(v)          atomic64_sub_return(1LL, (v))
+#define atomic64_dec_and_test(v)        (atomic64_dec_return((v)) == 0)
+#define atomic64_inc_not_zero(v)        atomic64_add_unless((v), 1LL, 0LL)
+
+#else /* !CONFIG_GENERIC_ATOMIC64 */
+#include <asm-generic/atomic64.h>
+#endif
 #include <asm-generic/atomic-long.h>
 #endif
 #endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index c77d2fa1f6e5..72da7e045c6b 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -42,7 +42,8 @@
 #endif
 
 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
-    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
+    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
+    defined(CONFIG_CPU_ARM1026)
 # define MULTI_CACHE 1
 #endif
 
@@ -196,21 +197,6 @@
  *      DMA Cache Coherency
  *      ===================
  *
- *      dma_inv_range(start, end)
- *
- *              Invalidate (discard) the specified virtual address range.
- *              May not write back any entries.  If 'start' or 'end'
- *              are not cache line aligned, those lines must be written
- *              back.
- *              - start  - virtual start address
- *              - end    - virtual end address
- *
- *      dma_clean_range(start, end)
- *
- *              Clean (write back) the specified virtual address range.
- *              - start  - virtual start address
- *              - end    - virtual end address
- *
  *      dma_flush_range(start, end)
  *
  *              Clean and invalidate the specified virtual address range.
@@ -227,8 +213,9 @@ struct cpu_cache_fns {
         void (*coherent_user_range)(unsigned long, unsigned long);
         void (*flush_kern_dcache_area)(void *, size_t);
 
-        void (*dma_inv_range)(const void *, const void *);
-        void (*dma_clean_range)(const void *, const void *);
+        void (*dma_map_area)(const void *, size_t, int);
+        void (*dma_unmap_area)(const void *, size_t, int);
+
         void (*dma_flush_range)(const void *, const void *);
 };
 
@@ -258,8 +245,8 @@ extern struct cpu_cache_fns cpu_cache;
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
-#define dmac_inv_range                  cpu_cache.dma_inv_range
-#define dmac_clean_range                cpu_cache.dma_clean_range
+#define dmac_map_area                   cpu_cache.dma_map_area
+#define dmac_unmap_area         cpu_cache.dma_unmap_area
 #define dmac_flush_range                cpu_cache.dma_flush_range
 
 #else
@@ -284,12 +271,12 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
-#define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
-#define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
+#define dmac_map_area                   __glue(_CACHE,_dma_map_area)
+#define dmac_unmap_area         __glue(_CACHE,_dma_unmap_area)
 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 
-extern void dmac_inv_range(const void *, const void *);
-extern void dmac_clean_range(const void *, const void *);
+extern void dmac_map_area(const void *, size_t, int);
+extern void dmac_unmap_area(const void *, size_t, int);
 extern void dmac_flush_range(const void *, const void *);
 
 #endif
@@ -330,12 +317,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
  * processes address space.  Really, we want to allow our "user
  * space" model to handle this.
  */
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-        do {                                                    \
-                memcpy(dst, src, len);                          \
-                flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
-        } while (0)
-
+extern void copy_to_user_page(struct vm_area_struct *, struct page *,
+        unsigned long, void *, const void *, unsigned long);
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
         do {                                                    \
                 memcpy(dst, src, len);                          \
@@ -369,17 +352,6 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
         }
 }
 
-static inline void
-vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                         unsigned long uaddr, void *kaddr,
-                         unsigned long len, int write)
-{
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
-                unsigned long addr = (unsigned long)kaddr;
-                __cpuc_coherent_kern_range(addr, addr + len);
-        }
-}
-
 #ifndef CONFIG_CPU_CACHE_VIPT
 #define flush_cache_mm(mm) \
                 vivt_flush_cache_mm(mm)
@@ -387,15 +359,10 @@ vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                 vivt_flush_cache_range(vma,start,end)
 #define flush_cache_page(vma,addr,pfn) \
                 vivt_flush_cache_page(vma,addr,pfn)
-#define flush_ptrace_access(vma,page,ua,ka,len,write) \
-                vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
 #else
 extern void flush_cache_mm(struct mm_struct *mm);
 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
-extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                                unsigned long uaddr, void *kaddr,
-                                unsigned long len, int write);
 #endif
 
 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
@@ -446,6 +413,16 @@ static inline void __flush_icache_all(void)
             : "r" (0));
 #endif
 }
+static inline void flush_kernel_vmap_range(void *addr, int size)
+{
+        if ((cache_is_vivt() || cache_is_vipt_aliasing()))
+          __cpuc_flush_dcache_area(addr, (size_t)size);
+}
+static inline void invalidate_kernel_vmap_range(void *addr, int size)
+{
+        if ((cache_is_vivt() || cache_is_vipt_aliasing()))
+          __cpuc_flush_dcache_area(addr, (size_t)size);
+}
 
 #define ARCH_HAS_FLUSH_ANON_PAGE
 static inline void flush_anon_page(struct vm_area_struct *vma,
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index b6ec7c627b39..7a0690da5e63 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -27,4 +27,7 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
 void clkdev_add(struct clk_lookup *cl);
 void clkdev_drop(struct clk_lookup *cl);
 
+void clkdev_add_table(struct clk_lookup *, size_t);
+int clk_add_alias(const char *, const char *, char *, struct device *);
+
 #endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index a96300bf83fd..256ee1c9f51a 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -57,18 +57,58 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
 #endif
 
 /*
- * DMA-consistent mapping functions.  These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices.  This is the "generic" version.  The PCI specific version
- * is in pci.h
+ * The DMA API is built upon the notion of "buffer ownership".  A buffer
+ * is either exclusively owned by the CPU (and therefore may be accessed
+ * by it) or exclusively owned by the DMA device.  These helper functions
+ * represent the transitions between these two ownership states.
  *
- * Note: Drivers should NOT use this function directly, as it will break
- * platforms with CONFIG_DMABOUNCE.
- * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
+ * Note, however, that on later ARMs, this notion does not work due to
+ * speculative prefetches.  We model our approach on the assumption that
+ * the CPU does do speculative prefetches, which means we clean caches
+ * before transfers and delay cache invalidation until transfer completion.
+ *
+ * Private support functions: these are not part of the API and are
+ * liable to change.  Drivers must not use these.
  */
-extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
-extern void dma_cache_maint_page(struct page *page, unsigned long offset,
-                                 size_t size, int rw);
+static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        extern void ___dma_single_cpu_to_dev(const void *, size_t,
+                enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_single_cpu_to_dev(kaddr, size, dir);
+}
+
+static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        extern void ___dma_single_dev_to_cpu(const void *, size_t,
+                enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_single_dev_to_cpu(kaddr, size, dir);
+}
+
+static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        extern void ___dma_page_cpu_to_dev(struct page *, unsigned long,
+                size_t, enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_page_cpu_to_dev(page, off, size, dir);
+}
+
+static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        extern void ___dma_page_dev_to_cpu(struct page *, unsigned long,
+                size_t, enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_page_dev_to_cpu(page, off, size, dir);
+}
 
 /*
  * Return whether the given device DMA address mask can be supported
@@ -304,8 +344,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
 {
         BUG_ON(!valid_dma_direction(dir));
 
-        if (!arch_is_coherent())
-                dma_cache_maint(cpu_addr, size, dir);
+        __dma_single_cpu_to_dev(cpu_addr, size, dir);
 
         return virt_to_dma(dev, cpu_addr);
 }
@@ -329,8 +368,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 {
         BUG_ON(!valid_dma_direction(dir));
 
-        if (!arch_is_coherent())
-                dma_cache_maint_page(page, offset, size, dir);
+        __dma_page_cpu_to_dev(page, offset, size, dir);
 
         return page_to_dma(dev, page) + offset;
 }
@@ -352,7 +390,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir)
 {
-        /* nothing to do */
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
 }
 
 /**
@@ -372,7 +410,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir)
 {
-        /* nothing to do */
+        __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
+                size, dir);
 }
 #endif /* CONFIG_DMABOUNCE */
 
@@ -400,7 +439,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
 {
         BUG_ON(!valid_dma_direction(dir));
 
-        dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
+        if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
+                return;
+
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void dma_sync_single_range_for_device(struct device *dev,
@@ -412,8 +454,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
         if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
                 return;
 
-        if (!arch_is_coherent())
-                dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
+        __dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void dma_sync_single_for_cpu(struct device *dev,
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index d2a59cfc30ce..c980156f3263 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -69,9 +69,16 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 /*
  * __arm_ioremap takes CPU physical address.
  * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
+ * The _caller variety takes a __builtin_return_address(0) value for
+ * /proc/vmalloc to use - and should only be used in non-inline functions.
  */
-extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
-extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
+extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
+        size_t, unsigned int, void *);
+extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
+        void *);
+
+extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
+extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
 extern void __iounmap(volatile void __iomem *addr);
 
 /*
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index b2cc1fcd0400..8bffc3ff3acf 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -46,12 +46,4 @@ struct sys_timer {
 extern struct sys_timer *system_timer;
 extern void timer_tick(void);
 
-/*
- * Kernel time keeping support.
- */
-struct timespec;
-extern int (*set_rtc)(void);
-extern void save_time_delta(struct timespec *delta, struct timespec *rtc);
-extern void restore_time_delta(struct timespec *delta, struct timespec *rtc);
-
 #endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 5421d82a2572..4312ee5e3d0b 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -76,6 +76,17 @@
  */
 #define IOREMAP_MAX_ORDER       24
 
+/*
+ * Size of DMA-consistent memory region.  Must be multiple of 2M,
+ * between 2MB and 14MB inclusive.
+ */
+#ifndef CONSISTENT_DMA_SIZE
+#define CONSISTENT_DMA_SIZE     SZ_2M
+#endif
+
+#define CONSISTENT_END          (0xffe00000UL)
+#define CONSISTENT_BASE         (CONSISTENT_END - CONSISTENT_DMA_SIZE)
+
 #else /* CONFIG_MMU */
 
 /*
@@ -93,11 +104,11 @@
 #endif
 
 #ifndef PHYS_OFFSET
-#define PHYS_OFFSET             (CONFIG_DRAM_BASE)
+#define PHYS_OFFSET             UL(CONFIG_DRAM_BASE)
 #endif
 
 #ifndef END_MEM
-#define END_MEM                 (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE)
+#define END_MEM                 (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
 #endif
 
 #ifndef PAGE_OFFSET
@@ -113,14 +124,6 @@
 #endif /* !CONFIG_MMU */
 
 /*
- * Size of DMA-consistent memory region.  Must be multiple of 2M,
- * between 2MB and 14MB inclusive.
- */
-#ifndef CONSISTENT_DMA_SIZE
-#define CONSISTENT_DMA_SIZE SZ_2M
-#endif
-
-/*
  * Physical vs virtual RAM address space conversion.  These are
  * private definitions which should NOT be used outside memory.h
  * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index b561584d04a1..68870c776671 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -6,6 +6,7 @@
 typedef struct {
 #ifdef CONFIG_CPU_HAS_ASID
         unsigned int id;
+        spinlock_t id_lock;
 #endif
         unsigned int kvm_seq;
 } mm_context_t;
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index de6cefb329dd..a0b3cac0547c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -43,12 +43,23 @@ void __check_kvm_seq(struct mm_struct *mm);
 #define ASID_FIRST_VERSION      (1 << ASID_BITS)
 
 extern unsigned int cpu_last_asid;
+#ifdef CONFIG_SMP
+DECLARE_PER_CPU(struct mm_struct *, current_mm);
+#endif
 
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 void __new_context(struct mm_struct *mm);
 
 static inline void check_context(struct mm_struct *mm)
 {
+        /*
+         * This code is executed with interrupts enabled. Therefore,
+         * mm->context.id cannot be updated to the latest ASID version
+         * on a different CPU (and condition below not triggered)
+         * without first getting an IPI to reset the context. The
+         * alternative is to take a read_lock on mm->context.id_lock
+         * (after changing its type to rwlock_t).
+         */
         if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
                 __new_context(mm);
 
@@ -108,6 +119,10 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                 __flush_icache_all();
 #endif
         if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
+#ifdef CONFIG_SMP
+                struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
+                *crt_mm = next;
+#endif
                 check_context(next);
                 cpu_switch_mm(next->pgd, next);
                 if (cache_is_vivt())
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 3a32af4cce30..a485ac3c8696 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -117,11 +117,12 @@
 #endif
 
 struct page;
+struct vm_area_struct;
 
 struct cpu_user_fns {
         void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr);
         void (*cpu_copy_user_highpage)(struct page *to, struct page *from,
-                        unsigned long vaddr);
+                        unsigned long vaddr, struct vm_area_struct *vma);
 };
 
 #ifdef MULTI_USER
@@ -137,7 +138,7 @@ extern struct cpu_user_fns cpu_user;
 
 extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr);
 extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
-                        unsigned long vaddr);
+                        unsigned long vaddr, struct vm_area_struct *vma);
 #endif
 
 #define clear_user_highpage(page,vaddr)         \
@@ -145,7 +146,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 
 #define __HAVE_ARCH_COPY_USER_HIGHPAGE
 #define copy_user_highpage(to,from,vaddr,vma)   \
-        __cpu_copy_user_highpage(to, from, vaddr)
+        __cpu_copy_user_highpage(to, from, vaddr, vma)
 
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
new file mode 100644
index 000000000000..49e3049aba32
--- /dev/null
+++ b/arch/arm/include/asm/perf_event.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/arch/arm/include/asm/perf_event.h
+ *
+ *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARM_PERF_EVENT_H__
+#define __ARM_PERF_EVENT_H__
+
+/*
+ * NOP: on *most* (read: all supported) ARM platforms, the performance
+ * counter interrupts are regular interrupts and not an NMI. This
+ * means that when we receive the interrupt we can call
+ * perf_event_do_pending() that handles all of the work with
+ * interrupts enabled.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+/* ARM performance counters start from 1 (in the cp15 accesses) so use the
+ * same indexes here for consistency. */
+#define PERF_EVENT_INDEX_OFFSET 1
+
+#endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index b011f2e939aa..013cfcdc4839 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -86,8 +86,8 @@ extern unsigned int kobjsize(const void *objp);
  * All 32bit addresses are effectively valid for vmalloc...
  * Sort of meaningless for non-VM targets.
  */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
+#define VMALLOC_START   0UL
+#define VMALLOC_END     0xffffffffUL
 
 #define FIRST_USER_ADDRESS      (0)
 
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
new file mode 100644
index 000000000000..2829b9f981a1
--- /dev/null
+++ b/arch/arm/include/asm/pmu.h
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/include/asm/pmu.h
+ *
+ *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARM_PMU_H__
+#define __ARM_PMU_H__
+
+#ifdef CONFIG_CPU_HAS_PMU
+
+struct pmu_irqs {
+        const int   *irqs;
+        int         num_irqs;
+};
+
+/**
+ * reserve_pmu() - reserve the hardware performance counters
+ *
+ * Reserve the hardware performance counters in the system for exclusive use.
+ * The 'struct pmu_irqs' for the system is returned on success, ERR_PTR()
+ * encoded error on failure.
+ */
+extern const struct pmu_irqs *
+reserve_pmu(void);
+
+/**
+ * release_pmu() - Relinquish control of the performance counters
+ *
+ * Release the performance counters and allow someone else to use them.
+ * Callers must have disabled the counters and released IRQs before calling
+ * this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as
+ * a cookie.
+ */
+extern int
+release_pmu(const struct pmu_irqs *irqs);
+
+/**
+ * init_pmu() - Initialise the PMU.
+ *
+ * Initialise the system ready for PMU enabling. This should typically set the
+ * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
+ * the actual hardware initialisation.
+ */
+extern int
+init_pmu(void);
+
+#else /* CONFIG_CPU_HAS_PMU */
+
+static inline const struct pmu_irqs *
+reserve_pmu(void)
+{
+        return ERR_PTR(-ENODEV);
+}
+
+static inline int
+release_pmu(const struct pmu_irqs *irqs)
+{
+        return -ENODEV;
+}
+
+static inline int
+init_pmu(void)
+{
+        return -ENODEV;
+}
+
+#endif /* CONFIG_CPU_HAS_PMU */
+
+#endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 5ccce0a9b03c..f392fb4437af 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -223,18 +223,6 @@ extern struct meminfo meminfo;
 #define bank_phys_end(bank)     ((bank)->start + (bank)->size)
 #define bank_phys_size(bank)    (bank)->size
 
-/*
- * Early command line parameters.
- */
-struct early_params {
-        const char *arg;
-        void (*fn)(char **p);
-};
-
-#define __early_param(name,fn)                                  \
-static struct early_params __early_##fn __used                  \
-__attribute__((__section__(".early_param.init"))) = { name, fn }
-
 #endif  /*  __KERNEL__  */
 
 #endif
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 59303e200845..e6215305544a 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,4 +13,9 @@ static inline int tlb_ops_need_broadcast(void)
         return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+static inline int cache_ops_need_broadcast(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
+}
+
 #endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index c91c64cab922..17eb355707dd 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -5,6 +5,22 @@
 #error SMP not supported on pre-ARMv6 CPUs
 #endif
 
+static inline void dsb_sev(void)
+{
+#if __LINUX_ARM_ARCH__ >= 7
+        __asm__ __volatile__ (
+                "dsb\n"
+                "sev"
+        );
+#elif defined(CONFIG_CPU_32v6K)
+        __asm__ __volatile__ (
+                "mcr p15, 0, %0, c7, c10, 4\n"
+                "sev"
+                : : "r" (0)
+        );
+#endif
+}
+
 /*
  * ARMv6 Spin-locking.
  *
@@ -69,13 +85,11 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
 
         __asm__ __volatile__(
 "       str     %1, [%0]\n"
-#ifdef CONFIG_CPU_32v6K
-"       mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
-"       sev"
-#endif
         :
         : "r" (&lock->lock), "r" (0)
         : "cc");
+
+        dsb_sev();
 }
 
 /*
@@ -132,13 +146,11 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
 
         __asm__ __volatile__(
         "str    %1, [%0]\n"
-#ifdef CONFIG_CPU_32v6K
-"       mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
-"       sev\n"
-#endif
         :
         : "r" (&rw->lock), "r" (0)
         : "cc");
+
+        dsb_sev();
 }
 
 /* write_can_lock - would write_trylock() succeed? */
@@ -188,14 +200,12 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
 "       strex   %1, %0, [%2]\n"
 "       teq     %1, #0\n"
 "       bne     1b"
-#ifdef CONFIG_CPU_32v6K
-"\n     cmp     %0, #0\n"
-"       mcreq   p15, 0, %0, c7, c10, 4\n"
-"       seveq"
-#endif
         : "=&r" (tmp), "=&r" (tmp2)
         : "r" (&rw->lock)
         : "cc");
+
+        if (tmp == 0)
+                dsb_sev();
 }
 
 static inline int arch_read_trylock(arch_rwlock_t *rw)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 058e7e90881d..ca88e6a84707 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -73,8 +73,7 @@ extern unsigned int mem_fclk_21285;
 
 struct pt_regs;
 
-void die(const char *msg, struct pt_regs *regs, int err)
-                __attribute__((noreturn));
+void die(const char *msg, struct pt_regs *regs, int err);
 
 struct siginfo;
 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 2dfb7d7a66e9..b74970ec02c4 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -115,7 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *);
 extern void iwmmxt_task_release(struct thread_info *);
 extern void iwmmxt_task_switch(struct thread_info *);
 
-extern void vfp_sync_state(struct thread_info *thread);
+extern void vfp_sync_hwstate(struct thread_info *);
+extern void vfp_flush_hwstate(struct thread_info *);
 
 #endif
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index c2f1605de359..e085e2c545eb 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -529,7 +529,8 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
-extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
+extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+        pte_t *ptep);
 
 #endif
 
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index dd00f747e2ad..26d302c28e13 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -17,6 +17,7 @@ obj-y		:= compat.o elf.o entry-armv.o entry-common.o irq.o \
                    process.o ptrace.o return_address.o setup.o signal.o \
                    sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_LEDS)              += leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -46,6 +47,8 @@ obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
+obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
+obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 
 ifneq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 4a881258bb17..883511522fca 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -12,6 +12,7 @@
  */
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/dma-mapping.h>
 #include <asm/mach/arch.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
@@ -112,5 +113,9 @@ int main(void)
 #ifdef MULTI_PABORT
   DEFINE(PROCESSOR_PABT_FUNC,   offsetof(struct processor, _prefetch_abort));
 #endif
+  BLANK();
+  DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
+  DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
+  DEFINE(DMA_FROM_DEVICE,       DMA_FROM_DEVICE);
   return 0; 
 }
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 809681900ec8..bd397e0b663e 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -616,15 +616,17 @@ char * __init pcibios_setup(char *str)
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might be mirrored at 0x0100-0x03ff..
  */
-void pcibios_align_resource(void *data, struct resource *res,
-                            resource_size_t size, resource_size_t align)
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
 {
         resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO && start & 0x300)
                 start = (start + 0x3ff) & ~0x3ff;
 
-        res->start = (start + align - 1) & ~(align - 1);
+        start = (start + align - 1) & ~(align - 1);
+
+        return start;
 }
 
 /**
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
new file mode 100644
index 000000000000..31a316c1777b
--- /dev/null
+++ b/arch/arm/kernel/leds.c
@@ -0,0 +1,115 @@
+/*
+ * LED support code, ripped out of arch/arm/kernel/time.c
+ *
+ *  Copyright (C) 1994-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <asm/leds.h>
+
+static void dummy_leds_event(led_event_t evt)
+{
+}
+
+void (*leds_event)(led_event_t) = dummy_leds_event;
+
+struct leds_evt_name {
+        const char      name[8];
+        int             on;
+        int             off;
+};
+
+static const struct leds_evt_name evt_names[] = {
+        { "amber", led_amber_on, led_amber_off },
+        { "blue",  led_blue_on,  led_blue_off  },
+        { "green", led_green_on, led_green_off },
+        { "red",   led_red_on,   led_red_off   },
+};
+
+static ssize_t leds_store(struct sys_device *dev,
+                        struct sysdev_attribute *attr,
+                        const char *buf, size_t size)
+{
+        int ret = -EINVAL, len = strcspn(buf, " ");
+
+        if (len > 0 && buf[len] == '\0')
+                len--;
+
+        if (strncmp(buf, "claim", len) == 0) {
+                leds_event(led_claim);
+                ret = size;
+        } else if (strncmp(buf, "release", len) == 0) {
+                leds_event(led_release);
+                ret = size;
+        } else {
+                int i;
+
+                for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
+                        if (strlen(evt_names[i].name) != len ||
+                            strncmp(buf, evt_names[i].name, len) != 0)
+                                continue;
+                        if (strncmp(buf+len, " on", 3) == 0) {
+                                leds_event(evt_names[i].on);
+                                ret = size;
+                        } else if (strncmp(buf+len, " off", 4) == 0) {
+                                leds_event(evt_names[i].off);
+                                ret = size;
+                        }
+                        break;
+                }
+        }
+        return ret;
+}
+
+static SYSDEV_ATTR(event, 0200, NULL, leds_store);
+
+static int leds_suspend(struct sys_device *dev, pm_message_t state)
+{
+        leds_event(led_stop);
+        return 0;
+}
+
+static int leds_resume(struct sys_device *dev)
+{
+        leds_event(led_start);
+        return 0;
+}
+
+static int leds_shutdown(struct sys_device *dev)
+{
+        leds_event(led_halted);
+        return 0;
+}
+
+static struct sysdev_class leds_sysclass = {
+        .name           = "leds",
+        .shutdown       = leds_shutdown,
+        .suspend        = leds_suspend,
+        .resume         = leds_resume,
+};
+
+static struct sys_device leds_device = {
+        .id             = 0,
+        .cls            = &leds_sysclass,
+};
+
+static int __init leds_init(void)
+{
+        int ret;
+        ret = sysdev_class_register(&leds_sysclass);
+        if (ret == 0)
+                ret = sysdev_register(&leds_device);
+        if (ret == 0)
+                ret = sysdev_create_file(&leds_device, &attr_event);
+        return ret;
+}
+
+device_initcall(leds_init);
+
+EXPORT_SYMBOL(leds_event);
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
new file mode 100644
index 000000000000..c54ceb3d1f97
--- /dev/null
+++ b/arch/arm/kernel/perf_event.c
@@ -0,0 +1,2276 @@
+#undef DEBUG
+
+/*
+ * ARM performance counter support.
+ *
+ * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
+ *
+ * ARMv7 support: Jean Pihet <jpihet@mvista.com>
+ * 2010 (c) MontaVista Software, LLC.
+ *
+ * This code is based on the sparc64 perf event code, which is in turn based
+ * on the x86 code. Callchain code is based on the ARM OProfile backtrace
+ * code.
+ */
+#define pr_fmt(fmt) "hw perfevents: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+
+#include <asm/cputype.h>
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+#include <asm/stacktrace.h>
+
+static const struct pmu_irqs *pmu_irqs;
+
+/*
+ * Hardware lock to serialize accesses to PMU registers. Needed for the
+ * read/modify/write sequences.
+ */
+DEFINE_SPINLOCK(pmu_lock);
+
+/*
+ * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
+ * another platform that supports more, we need to increase this to be the
+ * largest of all platforms.
+ *
+ * ARMv7 supports up to 32 events:
+ *  cycle counter CCNT + 31 events counters CNT0..30.
+ *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
+ */
+#define ARMPMU_MAX_HWEVENTS             33
+
+/* The events for a given CPU. */
+struct cpu_hw_events {
+        /*
+         * The events that are active on the CPU for the given index. Index 0
+         * is reserved.
+         */
+        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
+
+        /*
+         * A 1 bit for an index indicates that the counter is being used for
+         * an event. A 0 means that the counter can be used.
+         */
+        unsigned long           used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
+
+        /*
+         * A 1 bit for an index indicates that the counter is actively being
+         * used.
+         */
+        unsigned long           active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+
+struct arm_pmu {
+        char            *name;
+        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
+        void            (*enable)(struct hw_perf_event *evt, int idx);
+        void            (*disable)(struct hw_perf_event *evt, int idx);
+        int             (*event_map)(int evt);
+        u64             (*raw_event)(u64);
+        int             (*get_event_idx)(struct cpu_hw_events *cpuc,
+                                         struct hw_perf_event *hwc);
+        u32             (*read_counter)(int idx);
+        void            (*write_counter)(int idx, u32 val);
+        void            (*start)(void);
+        void            (*stop)(void);
+        int             num_events;
+        u64             max_period;
+};
+
+/* Set at runtime when we know what CPU type we are. */
+static const struct arm_pmu *armpmu;
+
+#define HW_OP_UNSUPPORTED               0xFFFF
+
+#define C(_x) \
+        PERF_COUNT_HW_CACHE_##_x
+
+#define CACHE_OP_UNSUPPORTED            0xFFFF
+
+static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                     [PERF_COUNT_HW_CACHE_OP_MAX]
+                                     [PERF_COUNT_HW_CACHE_RESULT_MAX];
+
+static int
+armpmu_map_cache_event(u64 config)
+{
+        unsigned int cache_type, cache_op, cache_result, ret;
+
+        cache_type = (config >>  0) & 0xff;
+        if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+                return -EINVAL;
+
+        cache_op = (config >>  8) & 0xff;
+        if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+                return -EINVAL;
+
+        cache_result = (config >> 16) & 0xff;
+        if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return -EINVAL;
+
+        ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
+
+        if (ret == CACHE_OP_UNSUPPORTED)
+                return -ENOENT;
+
+        return ret;
+}
+
+static int
+armpmu_event_set_period(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx)
+{
+        s64 left = atomic64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int ret = 0;
+
+        if (unlikely(left <= -period)) {
+                left = period;
+                atomic64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (unlikely(left <= 0)) {
+                left += period;
+                atomic64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (left > (s64)armpmu->max_period)
+                left = armpmu->max_period;
+
+        atomic64_set(&hwc->prev_count, (u64)-left);
+
+        armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
+
+        perf_event_update_userpage(event);
+
+        return ret;
+}
+
+static u64
+armpmu_event_update(struct perf_event *event,
+                    struct hw_perf_event *hwc,
+                    int idx)
+{
+        int shift = 64 - 32;
+        s64 prev_raw_count, new_raw_count;
+        s64 delta;
+
+again:
+        prev_raw_count = atomic64_read(&hwc->prev_count);
+        new_raw_count = armpmu->read_counter(idx);
+
+        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                             new_raw_count) != prev_raw_count)
+                goto again;
+
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+
+        atomic64_add(delta, &event->count);
+        atomic64_sub(delta, &hwc->period_left);
+
+        return new_raw_count;
+}
+
+static void
+armpmu_disable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        WARN_ON(idx < 0);
+
+        clear_bit(idx, cpuc->active_mask);
+        armpmu->disable(hwc, idx);
+
+        barrier();
+
+        armpmu_event_update(event, hwc, idx);
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
+static void
+armpmu_read(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        /* Don't read disabled counters! */
+        if (hwc->idx < 0)
+                return;
+
+        armpmu_event_update(event, hwc, hwc->idx);
+}
+
+static void
+armpmu_unthrottle(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        /*
+         * Set the period again. Some counters can't be stopped, so when we
+         * were throttled we simply disabled the IRQ source and the counter
+         * may have been left counting. If we don't do this step then we may
+         * get an interrupt too soon or *way* too late if the overflow has
+         * happened since disabling.
+         */
+        armpmu_event_set_period(event, hwc, hwc->idx);
+        armpmu->enable(hwc, hwc->idx);
+}
+
+static int
+armpmu_enable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx;
+        int err = 0;
+
+        /* If we don't have a space for the counter then finish early. */
+        idx = armpmu->get_event_idx(cpuc, hwc);
+        if (idx < 0) {
+                err = idx;
+                goto out;
+        }
+
+        /*
+         * If there is an event in the counter we are going to use then make
+         * sure it is disabled.
+         */
+        event->hw.idx = idx;
+        armpmu->disable(hwc, idx);
+        cpuc->events[idx] = event;
+        set_bit(idx, cpuc->active_mask);
+
+        /* Set the period for the event. */
+        armpmu_event_set_period(event, hwc, idx);
+
+        /* Enable the event. */
+        armpmu->enable(hwc, idx);
+
+        /* Propagate our changes to the userspace mapping. */
+        perf_event_update_userpage(event);
+
+out:
+        return err;
+}
+
+static struct pmu pmu = {
+        .enable     = armpmu_enable,
+        .disable    = armpmu_disable,
+        .unthrottle = armpmu_unthrottle,
+        .read       = armpmu_read,
+};
+
+static int
+validate_event(struct cpu_hw_events *cpuc,
+               struct perf_event *event)
+{
+        struct hw_perf_event fake_event = event->hw;
+
+        if (event->pmu && event->pmu != &pmu)
+                return 0;
+
+        return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
+}
+
+static int
+validate_group(struct perf_event *event)
+{
+        struct perf_event *sibling, *leader = event->group_leader;
+        struct cpu_hw_events fake_pmu;
+
+        memset(&fake_pmu, 0, sizeof(fake_pmu));
+
+        if (!validate_event(&fake_pmu, leader))
+                return -ENOSPC;
+
+        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+                if (!validate_event(&fake_pmu, sibling))
+                        return -ENOSPC;
+        }
+
+        if (!validate_event(&fake_pmu, event))
+                return -ENOSPC;
+
+        return 0;
+}
+
+static int
+armpmu_reserve_hardware(void)
+{
+        int i;
+        int err;
+
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs)) {
+                pr_warning("unable to reserve pmu\n");
+                return PTR_ERR(pmu_irqs);
+        }
+
+        init_pmu();
+
+        if (pmu_irqs->num_irqs < 1) {
+                pr_err("no irqs for PMUs defined\n");
+                return -ENODEV;
+        }
+
+        for (i = 0; i < pmu_irqs->num_irqs; ++i) {
+                err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq,
+                                  IRQF_DISABLED, "armpmu", NULL);
+                if (err) {
+                        pr_warning("unable to request IRQ%d for ARM "
+                                   "perf counters\n", pmu_irqs->irqs[i]);
+                        break;
+                }
+        }
+
+        if (err) {
+                for (i = i - 1; i >= 0; --i)
+                        free_irq(pmu_irqs->irqs[i], NULL);
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
+        }
+
+        return err;
+}
+
+static void
+armpmu_release_hardware(void)
+{
+        int i;
+
+        for (i = pmu_irqs->num_irqs - 1; i >= 0; --i)
+                free_irq(pmu_irqs->irqs[i], NULL);
+        armpmu->stop();
+
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
+}
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+
+static void
+hw_perf_event_destroy(struct perf_event *event)
+{
+        if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
+                armpmu_release_hardware();
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+}
+
+static int
+__hw_perf_event_init(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        int mapping, err;
+
+        /* Decode the generic type into an ARM event identifier. */
+        if (PERF_TYPE_HARDWARE == event->attr.type) {
+                mapping = armpmu->event_map(event->attr.config);
+        } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+                mapping = armpmu_map_cache_event(event->attr.config);
+        } else if (PERF_TYPE_RAW == event->attr.type) {
+                mapping = armpmu->raw_event(event->attr.config);
+        } else {
+                pr_debug("event type %x not supported\n", event->attr.type);
+                return -EOPNOTSUPP;
+        }
+
+        if (mapping < 0) {
+                pr_debug("event %x:%llx not supported\n", event->attr.type,
+                         event->attr.config);
+                return mapping;
+        }
+
+        /*
+         * Check whether we need to exclude the counter from certain modes.
+         * The ARM performance counters are on all of the time so if someone
+         * has asked us for some excludes then we have to fail.
+         */
+        if (event->attr.exclude_kernel || event->attr.exclude_user ||
+            event->attr.exclude_hv || event->attr.exclude_idle) {
+                pr_debug("ARM performance counters do not support "
+                         "mode exclusion\n");
+                return -EPERM;
+        }
+
+        /*
+         * We don't assign an index until we actually place the event onto
+         * hardware. Use -1 to signify that we haven't decided where to put it
+         * yet. For SMP systems, each core has it's own PMU so we can't do any
+         * clever allocation or constraints checking at this point.
+         */
+        hwc->idx = -1;
+
+        /*
+         * Store the event encoding into the config_base field. config and
+         * event_base are unused as the only 2 things we need to know are
+         * the event mapping and the counter to use. The counter to use is
+         * also the indx and the config_base is the event type.
+         */
+        hwc->config_base            = (unsigned long)mapping;
+        hwc->config                 = 0;
+        hwc->event_base             = 0;
+
+        if (!hwc->sample_period) {
+                hwc->sample_period  = armpmu->max_period;
+                hwc->last_period    = hwc->sample_period;
+                atomic64_set(&hwc->period_left, hwc->sample_period);
+        }
+
+        err = 0;
+        if (event->group_leader != event) {
+                err = validate_group(event);
+                if (err)
+                        return -EINVAL;
+        }
+
+        return err;
+}
+
+const struct pmu *
+hw_perf_event_init(struct perf_event *event)
+{
+        int err = 0;
+
+        if (!armpmu)
+                return ERR_PTR(-ENODEV);
+
+        event->destroy = hw_perf_event_destroy;
+
+        if (!atomic_inc_not_zero(&active_events)) {
+                if (atomic_read(&active_events) > perf_max_events) {
+                        atomic_dec(&active_events);
+                        return ERR_PTR(-ENOSPC);
+                }
+
+                mutex_lock(&pmu_reserve_mutex);
+                if (atomic_read(&active_events) == 0) {
+                        err = armpmu_reserve_hardware();
+                }
+
+                if (!err)
+                        atomic_inc(&active_events);
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+
+        if (err)
+                return ERR_PTR(err);
+
+        err = __hw_perf_event_init(event);
+        if (err)
+                hw_perf_event_destroy(event);
+
+        return err ? ERR_PTR(err) : &pmu;
+}
+
+void
+hw_perf_enable(void)
+{
+        /* Enable all of the perf events on hardware. */
+        int idx;
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+        if (!armpmu)
+                return;
+
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+
+                if (!event)
+                        continue;
+
+                armpmu->enable(&event->hw, idx);
+        }
+
+        armpmu->start();
+}
+
+void
+hw_perf_disable(void)
+{
+        if (armpmu)
+                armpmu->stop();
+}
+
+/*
+ * ARMv6 Performance counter handling code.
+ *
+ * ARMv6 has 2 configurable performance counters and a single cycle counter.
+ * They all share a single reset bit but can be written to zero so we can use
+ * that for a reset.
+ *
+ * The counters can't be individually enabled or disabled so when we remove
+ * one event and replace it with another we could get spurious counts from the
+ * wrong event. However, we can take advantage of the fact that the
+ * performance counters can export events to the event bus, and the event bus
+ * itself can be monitored. This requires that we *don't* export the events to
+ * the event bus. The procedure for disabling a configurable counter is:
+ *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
+ *        effectively stops the counter from counting.
+ *      - disable the counter's interrupt generation (each counter has it's
+ *        own interrupt enable bit).
+ * Once stopped, the counter value can be written as 0 to reset.
+ *
+ * To enable a counter:
+ *      - enable the counter's interrupt generation.
+ *      - set the new event type.
+ *
+ * Note: the dedicated cycle counter only counts cycles and can't be
+ * enabled/disabled independently of the others. When we want to disable the
+ * cycle counter, we have to just disable the interrupt reporting and start
+ * ignoring that counter. When re-enabling, we have to reset the value and
+ * enable the interrupt.
+ */
+
+enum armv6_perf_types {
+        ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
+        ARMV6_PERFCTR_IBUF_STALL            = 0x1,
+        ARMV6_PERFCTR_DDEP_STALL            = 0x2,
+        ARMV6_PERFCTR_ITLB_MISS             = 0x3,
+        ARMV6_PERFCTR_DTLB_MISS             = 0x4,
+        ARMV6_PERFCTR_BR_EXEC               = 0x5,
+        ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
+        ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
+        ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
+        ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
+        ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
+        ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
+        ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
+        ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
+        ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
+        ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
+        ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
+        ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
+        ARMV6_PERFCTR_NOP                   = 0x20,
+};
+
+enum armv6_counters {
+        ARMV6_CYCLE_COUNTER = 1,
+        ARMV6_COUNTER0,
+        ARMV6_COUNTER1,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+enum armv6mpcore_perf_types {
+        ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
+        ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
+        ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
+        ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
+        ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
+        ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
+        ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
+        ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
+        ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
+        ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
+        ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
+        ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
+        ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
+        ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
+        ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
+        ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+static inline unsigned long
+armv6_pmcr_read(void)
+{
+        u32 val;
+        asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void
+armv6_pmcr_write(unsigned long val)
+{
+        asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
+}
+
+#define ARMV6_PMCR_ENABLE               (1 << 0)
+#define ARMV6_PMCR_CTR01_RESET          (1 << 1)
+#define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
+#define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
+#define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
+#define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
+#define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
+#define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
+#define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
+#define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
+#define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
+#define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
+#define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
+#define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
+
+#define ARMV6_PMCR_OVERFLOWED_MASK \
+        (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
+         ARMV6_PMCR_CCOUNT_OVERFLOW)
+
+static inline int
+armv6_pmcr_has_overflowed(unsigned long pmcr)
+{
+        return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
+}
+
+static inline int
+armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
+                                  enum armv6_counters counter)
+{
+        int ret = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
+        else if (ARMV6_COUNTER0 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
+        else if (ARMV6_COUNTER1 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return ret;
+}
+
+static inline u32
+armv6pmu_read_counter(int counter)
+{
+        unsigned long value = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return value;
+}
+
+static inline void
+armv6pmu_write_counter(int counter,
+                       u32 value)
+{
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+}
+
+void
+armv6pmu_enable_event(struct hw_perf_event *hwc,
+                      int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = 0;
+                evt     = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
+                          ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
+                          ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the event
+         * that we're interested in.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t
+armv6pmu_handle_irq(int irq_num,
+                    void *dev)
+{
+        unsigned long pmcr = armv6_pmcr_read();
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        if (!armv6_pmcr_has_overflowed(pmcr))
+                return IRQ_NONE;
+
+        regs = get_irq_regs();
+
+        /*
+         * The interrupts are cleared by writing the overflow flags back to
+         * the control register. All of the other bits don't have any effect
+         * if they are rewritten, so write the whole value back.
+         */
+        armv6_pmcr_write(pmcr);
+
+        data.addr = 0;
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts enabled. For
+         * platforms that can have the PMU interrupts raised as a PMI, this
+         * will not work.
+         */
+        perf_event_do_pending();
+
+        return IRQ_HANDLED;
+}
+
+static void
+armv6pmu_start(void)
+{
+        unsigned long flags, val;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val |= ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+void
+armv6pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline int
+armv6pmu_event_map(int config)
+{
+        int mapping = armv6_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static inline int
+armv6mpcore_pmu_event_map(int config)
+{
+        int mapping = armv6mpcore_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static u64
+armv6pmu_raw_event(u64 config)
+{
+        return config & 0xff;
+}
+
+static int
+armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                       struct hw_perf_event *event)
+{
+        /* Always place a cycle counter into the cycle counter. */
+        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
+                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV6_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * counter0 and counter1.
+                 */
+                if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
+                        return ARMV6_COUNTER1;
+                }
+
+                if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
+                        return ARMV6_COUNTER0;
+                }
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static void
+armv6pmu_disable_event(struct hw_perf_event *hwc,
+                       int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+                evt     = 0;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the number
+         * of ETM bus signal assertion cycles. The external reporting should
+         * be disabled and so this should never increment.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
+                              int idx)
+{
+        unsigned long val, mask, flags, evt = 0;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
+         * simply disable the interrupt reporting.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static const struct arm_pmu armv6pmu = {
+        .name                   = "v6",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6pmu_disable_event,
+        .event_map              = armv6pmu_event_map,
+        .raw_event              = armv6pmu_raw_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+/*
+ * ARMv6mpcore is almost identical to single core ARMv6 with the exception
+ * that some of the events have different enumerations and that there is no
+ * *hack* to stop the programmable counters. To stop the counters we simply
+ * disable the interrupt reporting and update the event. When unthrottling we
+ * reset the period and enable the interrupt reporting.
+ */
+static const struct arm_pmu armv6mpcore_pmu = {
+        .name                   = "v6mpcore",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6mpcore_pmu_disable_event,
+        .event_map              = armv6mpcore_pmu_event_map,
+        .raw_event              = armv6pmu_raw_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+/*
+ * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
+ *
+ * Copied from ARMv6 code, with the low level code inspired
+ *  by the ARMv7 Oprofile code.
+ *
+ * Cortex-A8 has up to 4 configurable performance counters and
+ *  a single cycle counter.
+ * Cortex-A9 has up to 31 configurable performance counters and
+ *  a single cycle counter.
+ *
+ * All counters can be enabled/disabled and IRQ masked separately. The cycle
+ *  counter and all 4 performance counters together can be reset separately.
+ */
+
+#define ARMV7_PMU_CORTEX_A8_NAME                "ARMv7 Cortex-A8"
+
+#define ARMV7_PMU_CORTEX_A9_NAME                "ARMv7 Cortex-A9"
+
+/* Common ARMv7 event types */
+enum armv7_perf_types {
+        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
+        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
+        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
+        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
+        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
+        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
+        ARMV7_PERFCTR_DREAD                     = 0x06,
+        ARMV7_PERFCTR_DWRITE                    = 0x07,
+
+        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
+        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
+        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
+        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+         * It counts:
+         *  - all branch instructions,
+         *  - instructions that explicitly write the PC,
+         *  - exception generating instructions.
+         */
+        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
+        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
+        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
+
+        ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
+
+        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
+};
+
+/* ARMv7 Cortex-A8 specific event types */
+enum armv7_a8_perf_types {
+        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
+
+        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
+
+        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
+        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
+        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
+        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
+        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
+        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
+        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
+        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
+        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
+        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
+        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
+        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
+        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
+        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
+        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
+        ARMV7_PERFCTR_L1_INST                   = 0x50,
+        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
+        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
+        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
+        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
+        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
+        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
+        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
+        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
+        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
+        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
+
+        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
+        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
+        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
+};
+
+/* ARMv7 Cortex-A9 specific event types */
+enum armv7_a9_perf_types {
+        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
+        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
+        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
+
+        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
+        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
+
+        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
+        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
+        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
+        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
+        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
+        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
+        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
+        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
+        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
+
+        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
+
+        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
+        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
+        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
+        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
+        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
+
+        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
+        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
+        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
+        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
+        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
+        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
+        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
+
+        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
+        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
+
+        ARMV7_PERFCTR_ISB_INST                  = 0x90,
+        ARMV7_PERFCTR_DSB_INST                  = 0x91,
+        ARMV7_PERFCTR_DMB_INST                  = 0x92,
+        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
+
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
+        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
+        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
+        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
+        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
+};
+
+/*
+ * Cortex-A8 HW events mapping
+ *
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Cortex-A9 HW events mapping
+ */
+static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        =
+                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
+        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Perf Events counters
+ */
+enum armv7_counters {
+        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
+        ARMV7_COUNTER0                  = 2,    /* First event counter */
+};
+
+/*
+ * The cycle counter is ARMV7_CYCLE_COUNTER.
+ * The first event counter is ARMV7_COUNTER0.
+ * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
+ */
+#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
+
+/*
+ * ARMv7 low level PMNC access
+ */
+
+/*
+ * Per-CPU PMNC: config reg
+ */
+#define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
+#define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
+#define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
+#define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
+#define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
+#define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
+#define ARMV7_PMNC_N_MASK       0x1f
+#define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
+
+/*
+ * Available counters
+ */
+#define ARMV7_CNT0              0       /* First event counter */
+#define ARMV7_CCNT              31      /* Cycle counter */
+
+/* Perf Event to low level counters mapping */
+#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
+
+/*
+ * CNTENS: counters enable reg
+ */
+#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * CNTENC: counters disable reg
+ */
+#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENS: counters overflow interrupt enable reg
+ */
+#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENC: counters overflow interrupt disable reg
+ */
+#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * EVTSEL: Event selection reg
+ */
+#define ARMV7_EVTSEL_MASK       0x7f            /* Mask for writable bits */
+
+/*
+ * SELECT: Counter selection reg
+ */
+#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
+
+/*
+ * FLAG: counters overflow flag status reg
+ */
+#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
+#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
+#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
+
+static inline unsigned long armv7_pmnc_read(void)
+{
+        u32 val;
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void armv7_pmnc_write(unsigned long val)
+{
+        val &= ARMV7_PMNC_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
+}
+
+static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
+{
+        return pmnc & ARMV7_OVERFLOWED_MASK;
+}
+
+static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
+                                        enum armv7_counters counter)
+{
+        int ret;
+
+        if (counter == ARMV7_CYCLE_COUNTER)
+                ret = pmnc & ARMV7_FLAG_C;
+        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
+                ret = pmnc & ARMV7_FLAG_P(counter);
+        else
+                pr_err("CPU%u checking wrong counter %d overflow status\n",
+                        smp_processor_id(), counter);
+
+        return ret;
+}
+
+static inline int armv7_pmnc_select_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
+                pr_err("CPU%u selecting wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7pmu_read_counter(int idx)
+{
+        unsigned long value = 0;
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
+                                     : "=r" (value));
+        } else
+                pr_err("CPU%u reading wrong counter %d\n",
+                        smp_processor_id(), idx);
+
+        return value;
+}
+
+static inline void armv7pmu_write_counter(int idx, u32 value)
+{
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
+                                     : : "r" (value));
+        } else
+                pr_err("CPU%u writing wrong counter %d\n",
+                        smp_processor_id(), idx);
+}
+
+static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
+{
+        if (armv7_pmnc_select_counter(idx) == idx) {
+                val &= ARMV7_EVTSEL_MASK;
+                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+        }
+}
+
+static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENS_C;
+        else
+                val = ARMV7_CNTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
+{
+        u32 val;
+
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENC_C;
+        else
+                val = ARMV7_CNTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENS_C;
+        else
+                val = ARMV7_INTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENC_C;
+        else
+                val = ARMV7_INTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+        u32 val;
+
+        /* Read */
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+        /* Write to clear flags */
+        val &= ARMV7_FLAG_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+        return val;
+}
+
+#ifdef DEBUG
+static void armv7_pmnc_dump_regs(void)
+{
+        u32 val;
+        unsigned int cnt;
+
+        printk(KERN_INFO "PMNC registers dump:\n");
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+        printk(KERN_INFO "PMNC  =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
+        printk(KERN_INFO "CNTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
+        printk(KERN_INFO "INTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+        printk(KERN_INFO "FLAGS =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
+        printk(KERN_INFO "SELECT=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+        printk(KERN_INFO "CCNT  =0x%08x\n", val);
+
+        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
+                armv7_pmnc_select_counter(cnt);
+                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+        }
+}
+#endif
+
+void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Enable counter and interrupt, and set the counter to count
+         * the event that we're interested in.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Set event (if destined for PMNx counters)
+         * We don't need to set the event if it's a cycle count
+         */
+        if (idx != ARMV7_CYCLE_COUNTER)
+                armv7_pmnc_write_evtsel(idx, hwc->config_base);
+
+        /*
+         * Enable interrupt for this counter
+         */
+        armv7_pmnc_enable_intens(idx);
+
+        /*
+         * Enable counter
+         */
+        armv7_pmnc_enable_counter(idx);
+
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Disable counter and interrupt
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Disable interrupt for this counter
+         */
+        armv7_pmnc_disable_intens(idx);
+
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /*
+         * Get and reset the IRQ flags
+         */
+        pmnc = armv7_pmnc_getreset_flags();
+
+        /*
+         * Did an overflow occur?
+         */
+        if (!armv7_pmnc_has_overflowed(pmnc))
+                return IRQ_NONE;
+
+        /*
+         * Handle the counter(s) overflow(s)
+         */
+        regs = get_irq_regs();
+
+        data.addr = 0;
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts enabled. For
+         * platforms that can have the PMU interrupts raised as a PMI, this
+         * will not work.
+         */
+        perf_event_do_pending();
+
+        return IRQ_HANDLED;
+}
+
+static void armv7pmu_start(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        /* Enable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_stop(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        /* Disable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline int armv7_a8_pmu_event_map(int config)
+{
+        int mapping = armv7_a8_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static inline int armv7_a9_pmu_event_map(int config)
+{
+        int mapping = armv7_a9_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static u64 armv7pmu_raw_event(u64 config)
+{
+        return config & 0xff;
+}
+
+static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                                  struct hw_perf_event *event)
+{
+        int idx;
+
+        /* Always place a cycle counter into the cycle counter. */
+        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
+                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV7_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * the events counters
+                 */
+                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
+                        if (!test_and_set_bit(idx, cpuc->used_mask))
+                                return idx;
+                }
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static struct arm_pmu armv7pmu = {
+        .handle_irq             = armv7pmu_handle_irq,
+        .enable                 = armv7pmu_enable_event,
+        .disable                = armv7pmu_disable_event,
+        .raw_event              = armv7pmu_raw_event,
+        .read_counter           = armv7pmu_read_counter,
+        .write_counter          = armv7pmu_write_counter,
+        .get_event_idx          = armv7pmu_get_event_idx,
+        .start                  = armv7pmu_start,
+        .stop                   = armv7pmu_stop,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static u32 __init armv7_reset_read_pmnc(void)
+{
+        u32 nb_cnt;
+
+        /* Initialize & Reset PMNC: C and P bits */
+        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
+
+        /* Read the nb of CNTx counters supported from PMNC */
+        nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
+
+        /* Add the CPU cycles counter and return */
+        return nb_cnt + 1;
+}
+
+static int __init
+init_hw_perf_events(void)
+{
+        unsigned long cpuid = read_cpuid_id();
+        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+        unsigned long part_number = (cpuid & 0xFFF0);
+
+        /* We only support ARM CPUs implemented by ARM at the moment. */
+        if (0x41 == implementor) {
+                switch (part_number) {
+                case 0xB360:    /* ARM1136 */
+                case 0xB560:    /* ARM1156 */
+                case 0xB760:    /* ARM1176 */
+                        armpmu = &armv6pmu;
+                        memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
+                                        sizeof(armv6_perf_cache_map));
+                        perf_max_events = armv6pmu.num_events;
+                        break;
+                case 0xB020:    /* ARM11mpcore */
+                        armpmu = &armv6mpcore_pmu;
+                        memcpy(armpmu_perf_cache_map,
+                               armv6mpcore_perf_cache_map,
+                               sizeof(armv6mpcore_perf_cache_map));
+                        perf_max_events = armv6mpcore_pmu.num_events;
+                        break;
+                case 0xC080:    /* Cortex-A8 */
+                        armv7pmu.name = ARMV7_PMU_CORTEX_A8_NAME;
+                        memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
+                                sizeof(armv7_a8_perf_cache_map));
+                        armv7pmu.event_map = armv7_a8_pmu_event_map;
+                        armpmu = &armv7pmu;
+
+                        /* Reset PMNC and read the nb of CNTx counters
+                            supported */
+                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        perf_max_events = armv7pmu.num_events;
+                        break;
+                case 0xC090:    /* Cortex-A9 */
+                        armv7pmu.name = ARMV7_PMU_CORTEX_A9_NAME;
+                        memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
+                                sizeof(armv7_a9_perf_cache_map));
+                        armv7pmu.event_map = armv7_a9_pmu_event_map;
+                        armpmu = &armv7pmu;
+
+                        /* Reset PMNC and read the nb of CNTx counters
+                            supported */
+                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        perf_max_events = armv7pmu.num_events;
+                        break;
+                default:
+                        pr_info("no hardware support available\n");
+                        perf_max_events = -1;
+                }
+        }
+
+        if (armpmu)
+                pr_info("enabled with %s PMU driver, %d counters available\n",
+                        armpmu->name, armpmu->num_events);
+
+        return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+/*
+ * Callchain handling code.
+ */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+                u64 ip)
+{
+        if (entry->nr < PERF_MAX_STACK_DEPTH)
+                entry->ip[entry->nr++] = ip;
+}
+
+/*
+ * The registers we're interested in are at the end of the variable
+ * length saved register structure. The fp points at the end of this
+ * structure so the address of this struct is:
+ * (struct frame_tail *)(xxx->fp)-1
+ *
+ * This code has been adapted from the ARM OProfile support.
+ */
+struct frame_tail {
+        struct frame_tail   *fp;
+        unsigned long       sp;
+        unsigned long       lr;
+} __attribute__((packed));
+
+/*
+ * Get the return address for a single stackframe and return a pointer to the
+ * next frame tail.
+ */
+static struct frame_tail *
+user_backtrace(struct frame_tail *tail,
+               struct perf_callchain_entry *entry)
+{
+        struct frame_tail buftail;
+
+        /* Also check accessibility of one struct frame_tail beyond */
+        if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
+                return NULL;
+        if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
+                return NULL;
+
+        callchain_store(entry, buftail.lr);
+
+        /*
+         * Frame pointers should strictly progress back up the stack
+         * (towards higher addresses).
+         */
+        if (tail >= buftail.fp)
+                return NULL;
+
+        return buftail.fp - 1;
+}
+
+static void
+perf_callchain_user(struct pt_regs *regs,
+                    struct perf_callchain_entry *entry)
+{
+        struct frame_tail *tail;
+
+        callchain_store(entry, PERF_CONTEXT_USER);
+
+        if (!user_mode(regs))
+                regs = task_pt_regs(current);
+
+        tail = (struct frame_tail *)regs->ARM_fp - 1;
+
+        while (tail && !((unsigned long)tail & 0x3))
+                tail = user_backtrace(tail, entry);
+}
+
+/*
+ * Gets called by walk_stackframe() for every stackframe. This will be called
+ * whist unwinding the stackframe and is like a subroutine return so we use
+ * the PC.
+ */
+static int
+callchain_trace(struct stackframe *fr,
+                void *data)
+{
+        struct perf_callchain_entry *entry = data;
+        callchain_store(entry, fr->pc);
+        return 0;
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+                      struct perf_callchain_entry *entry)
+{
+        struct stackframe fr;
+
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        fr.fp = regs->ARM_fp;
+        fr.sp = regs->ARM_sp;
+        fr.lr = regs->ARM_lr;
+        fr.pc = regs->ARM_pc;
+        walk_stackframe(&fr, callchain_trace, entry);
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+                  struct perf_callchain_entry *entry)
+{
+        int is_user;
+
+        if (!regs)
+                return;
+
+        is_user = user_mode(regs);
+
+        if (!current || !current->pid)
+                return;
+
+        if (is_user && current->state != TASK_RUNNING)
+                return;
+
+        if (!is_user)
+                perf_callchain_kernel(regs, entry);
+
+        if (current->mm)
+                perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+        struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+        entry->nr = 0;
+        perf_do_callchain(regs, entry);
+        return entry;
+}
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
new file mode 100644
index 000000000000..a124312e343f
--- /dev/null
+++ b/arch/arm/kernel/pmu.c
@@ -0,0 +1,103 @@
+/*
+ *  linux/arch/arm/kernel/pmu.c
+ *
+ *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/cpumask.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/pmu.h>
+
+/*
+ * Define the IRQs for the system. We could use something like a platform
+ * device but that seems fairly heavyweight for this. Also, the performance
+ * counters can't be removed or hotplugged.
+ *
+ * Ordering is important: init_pmu() will use the ordering to set the affinity
+ * to the corresponding core. e.g. the first interrupt will go to cpu 0, the
+ * second goes to cpu 1 etc.
+ */
+static const int irqs[] = {
+#if defined(CONFIG_ARCH_OMAP2)
+        3,
+#elif defined(CONFIG_ARCH_BCMRING)
+        IRQ_PMUIRQ,
+#elif defined(CONFIG_MACH_REALVIEW_EB)
+        IRQ_EB11MP_PMU_CPU0,
+        IRQ_EB11MP_PMU_CPU1,
+        IRQ_EB11MP_PMU_CPU2,
+        IRQ_EB11MP_PMU_CPU3,
+#elif defined(CONFIG_ARCH_OMAP3)
+        INT_34XX_BENCH_MPU_EMUL,
+#elif defined(CONFIG_ARCH_IOP32X)
+        IRQ_IOP32X_CORE_PMU,
+#elif defined(CONFIG_ARCH_IOP33X)
+        IRQ_IOP33X_CORE_PMU,
+#elif defined(CONFIG_ARCH_PXA)
+        IRQ_PMU,
+#endif
+};
+
+static const struct pmu_irqs pmu_irqs = {
+        .irqs       = irqs,
+        .num_irqs   = ARRAY_SIZE(irqs),
+};
+
+static volatile long pmu_lock;
+
+const struct pmu_irqs *
+reserve_pmu(void)
+{
+        return test_and_set_bit_lock(0, &pmu_lock) ? ERR_PTR(-EBUSY) :
+                &pmu_irqs;
+}
+EXPORT_SYMBOL_GPL(reserve_pmu);
+
+int
+release_pmu(const struct pmu_irqs *irqs)
+{
+        if (WARN_ON(irqs != &pmu_irqs))
+                return -EINVAL;
+        clear_bit_unlock(0, &pmu_lock);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(release_pmu);
+
+static int
+set_irq_affinity(int irq,
+                 unsigned int cpu)
+{
+#ifdef CONFIG_SMP
+        int err = irq_set_affinity(irq, cpumask_of(cpu));
+        if (err)
+                pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                           irq, cpu);
+        return err;
+#else
+        return 0;
+#endif
+}
+
+int
+init_pmu(void)
+{
+        int i, err = 0;
+
+        for (i = 0; i < pmu_irqs.num_irqs; ++i) {
+                err = set_irq_affinity(pmu_irqs.irqs[i], i);
+                if (err)
+                        break;
+        }
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(init_pmu);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index a2ea3854cb3c..08f899fb76a6 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -499,10 +499,41 @@ static struct undef_hook thumb_break_hook = {
         .fn             = break_trap,
 };
 
+static int thumb2_break_trap(struct pt_regs *regs, unsigned int instr)
+{
+        unsigned int instr2;
+        void __user *pc;
+
+        /* Check the second half of the instruction.  */
+        pc = (void __user *)(instruction_pointer(regs) + 2);
+
+        if (processor_mode(regs) == SVC_MODE) {
+                instr2 = *(u16 *) pc;
+        } else {
+                get_user(instr2, (u16 __user *)pc);
+        }
+
+        if (instr2 == 0xa000) {
+                ptrace_break(current, regs);
+                return 0;
+        } else {
+                return 1;
+        }
+}
+
+static struct undef_hook thumb2_break_hook = {
+        .instr_mask     = 0xffff,
+        .instr_val      = 0xf7f0,
+        .cpsr_mask      = PSR_T_BIT,
+        .cpsr_val       = PSR_T_BIT,
+        .fn             = thumb2_break_trap,
+};
+
 static int __init ptrace_break_init(void)
 {
         register_undef_hook(&arm_break_hook);
         register_undef_hook(&thumb_break_hook);
+        register_undef_hook(&thumb2_break_hook);
         return 0;
 }
 
@@ -669,7 +700,7 @@ static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
         union vfp_state *vfp = &thread->vfpstate;
         struct user_vfp __user *ufp = data;
 
-        vfp_sync_state(thread);
+        vfp_sync_hwstate(thread);
 
         /* copy the floating point registers */
         if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
@@ -692,7 +723,7 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
         union vfp_state *vfp = &thread->vfpstate;
         struct user_vfp __user *ufp = data;
 
-        vfp_sync_state(thread);
+        vfp_sync_hwstate(thread);
 
         /* copy the floating point registers */
         if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
@@ -703,6 +734,8 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
         if (get_user(vfp->hard.fpscr, &ufp->fpscr))
                 return -EFAULT;
 
+        vfp_flush_hwstate(thread);
+
         return 0;
 }
 #endif
@@ -712,26 +745,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         int ret;
 
         switch (request) {
-                /*
-                 * read word at location "addr" in the child process.
-                 */
-                case PTRACE_PEEKTEXT:
-                case PTRACE_PEEKDATA:
-                        ret = generic_ptrace_peekdata(child, addr, data);
-                        break;
-
                 case PTRACE_PEEKUSR:
                         ret = ptrace_read_user(child, addr, (unsigned long __user *)data);
                         break;
 
-                /*
-                 * write the word at location addr.
-                 */
-                case PTRACE_POKETEXT:
-                case PTRACE_POKEDATA:
-                        ret = generic_ptrace_pokedata(child, addr, data);
-                        break;
-
                 case PTRACE_POKEUSR:
                         ret = ptrace_write_user(child, addr, data);
                         break;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index c6c57b640b6b..c91c77b54dea 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/fs.h>
+#include <linux/proc_fs.h>
 
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -102,6 +103,7 @@ struct cpu_cache_fns cpu_cache;
 #endif
 #ifdef CONFIG_OUTER_CACHE
 struct outer_cache_fns outer_cache;
+EXPORT_SYMBOL(outer_cache);
 #endif
 
 struct stack {
@@ -117,7 +119,7 @@ EXPORT_SYMBOL(elf_platform);
 
 static const char *cpu_name;
 static const char *machine_name;
-static char __initdata command_line[COMMAND_LINE_SIZE];
+static char __initdata cmd_line[COMMAND_LINE_SIZE];
 
 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
@@ -417,10 +419,11 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
  * Pick out the memory size.  We look for mem=size@start,
  * where start and size are "size[KkMm]"
  */
-static void __init early_mem(char **p)
+static int __init early_mem(char *p)
 {
         static int usermem __initdata = 0;
         unsigned long size, start;
+        char *endp;
 
         /*
          * If the user specifies memory size, we
@@ -433,52 +436,15 @@ static void __init early_mem(char **p)
         }
 
         start = PHYS_OFFSET;
-        size  = memparse(*p, p);
-        if (**p == '@')
-                start = memparse(*p + 1, p);
+        size  = memparse(p, &endp);
+        if (*endp == '@')
+                start = memparse(endp + 1, NULL);
 
         arm_add_memory(start, size);
-}
-__early_param("mem=", early_mem);
 
-/*
- * Initial parsing of the command line.
- */
-static void __init parse_cmdline(char **cmdline_p, char *from)
-{
-        char c = ' ', *to = command_line;
-        int len = 0;
-
-        for (;;) {
-                if (c == ' ') {
-                        extern struct early_params __early_begin, __early_end;
-                        struct early_params *p;
-
-                        for (p = &__early_begin; p < &__early_end; p++) {
-                                int arglen = strlen(p->arg);
-
-                                if (memcmp(from, p->arg, arglen) == 0) {
-                                        if (to != command_line)
-                                                to -= 1;
-                                        from += arglen;
-                                        p->fn(&from);
-
-                                        while (*from != ' ' && *from != '\0')
-                                                from++;
-                                        break;
-                                }
-                        }
-                }
-                c = *from++;
-                if (!c)
-                        break;
-                if (COMMAND_LINE_SIZE <= ++len)
-                        break;
-                *to++ = c;
-        }
-        *to = '\0';
-        *cmdline_p = command_line;
+        return 0;
 }
+early_param("mem", early_mem);
 
 static void __init
 setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
@@ -739,9 +705,15 @@ void __init setup_arch(char **cmdline_p)
         init_mm.end_data   = (unsigned long) _edata;
         init_mm.brk        = (unsigned long) _end;
 
-        memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-        boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
-        parse_cmdline(cmdline_p, from);
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+
+        /* populate cmd_line too for later use, preserving boot_command_line */
+        strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
+        *cmdline_p = cmd_line;
+
+        parse_early_param();
+
         paging_init(mdesc);
         request_standard_resources(&meminfo, mdesc);
 
@@ -782,9 +754,21 @@ static int __init topology_init(void)
 
         return 0;
 }
-
 subsys_initcall(topology_init);
 
+#ifdef CONFIG_HAVE_PROC_CPU
+static int __init proc_cpu_init(void)
+{
+        struct proc_dir_entry *res;
+
+        res = proc_mkdir("cpu", NULL);
+        if (!res)
+                return -ENOMEM;
+        return 0;
+}
+fs_initcall(proc_cpu_init);
+#endif
+
 static const char *hwcap_str[] = {
         "swp",
         "half",
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index d38cdf2c8276..28753805d2d1 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -10,11 +10,6 @@
  *
  *  This file contains the ARM-specific time handling details:
  *  reading the RTC at bootup, etc...
- *
- *  1994-07-02  Alan Modra
- *              fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
- *  1998-12-20  Updated NTP code according to technical memorandum Jan '96
- *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -77,11 +72,6 @@ unsigned long profile_pc(struct pt_regs *regs)
 EXPORT_SYMBOL(profile_pc);
 #endif
 
-/*
- * hook for setting the RTC's idea of the current time.
- */
-int (*set_rtc)(void);
-
 #ifndef CONFIG_GENERIC_TIME
 static unsigned long dummy_gettimeoffset(void)
 {
@@ -89,140 +79,6 @@ static unsigned long dummy_gettimeoffset(void)
 }
 #endif
 
-static unsigned long next_rtc_update;
-
-/*
- * If we have an externally synchronized linux clock, then update
- * CMOS clock accordingly every ~11 minutes.  set_rtc() has to be
- * called as close as possible to 500 ms before the new second
- * starts.
- */
-static inline void do_set_rtc(void)
-{
-        if (!ntp_synced() || set_rtc == NULL)
-                return;
-
-        if (next_rtc_update &&
-            time_before((unsigned long)xtime.tv_sec, next_rtc_update))
-                return;
-
-        if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) &&
-            xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1))
-                return;
-
-        if (set_rtc())
-                /*
-                 * rtc update failed.  Try again in 60s
-                 */
-                next_rtc_update = xtime.tv_sec + 60;
-        else
-                next_rtc_update = xtime.tv_sec + 660;
-}
-
-#ifdef CONFIG_LEDS
-
-static void dummy_leds_event(led_event_t evt)
-{
-}
-
-void (*leds_event)(led_event_t) = dummy_leds_event;
-
-struct leds_evt_name {
-        const char      name[8];
-        int             on;
-        int             off;
-};
-
-static const struct leds_evt_name evt_names[] = {
-        { "amber", led_amber_on, led_amber_off },
-        { "blue",  led_blue_on,  led_blue_off  },
-        { "green", led_green_on, led_green_off },
-        { "red",   led_red_on,   led_red_off   },
-};
-
-static ssize_t leds_store(struct sys_device *dev,
-                        struct sysdev_attribute *attr,
-                        const char *buf, size_t size)
-{
-        int ret = -EINVAL, len = strcspn(buf, " ");
-
-        if (len > 0 && buf[len] == '\0')
-                len--;
-
-        if (strncmp(buf, "claim", len) == 0) {
-                leds_event(led_claim);
-                ret = size;
-        } else if (strncmp(buf, "release", len) == 0) {
-                leds_event(led_release);
-                ret = size;
-        } else {
-                int i;
-
-                for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
-                        if (strlen(evt_names[i].name) != len ||
-                            strncmp(buf, evt_names[i].name, len) != 0)
-                                continue;
-                        if (strncmp(buf+len, " on", 3) == 0) {
-                                leds_event(evt_names[i].on);
-                                ret = size;
-                        } else if (strncmp(buf+len, " off", 4) == 0) {
-                                leds_event(evt_names[i].off);
-                                ret = size;
-                        }
-                        break;
-                }
-        }
-        return ret;
-}
-
-static SYSDEV_ATTR(event, 0200, NULL, leds_store);
-
-static int leds_suspend(struct sys_device *dev, pm_message_t state)
-{
-        leds_event(led_stop);
-        return 0;
-}
-
-static int leds_resume(struct sys_device *dev)
-{
-        leds_event(led_start);
-        return 0;
-}
-
-static int leds_shutdown(struct sys_device *dev)
-{
-        leds_event(led_halted);
-        return 0;
-}
-
-static struct sysdev_class leds_sysclass = {
-        .name           = "leds",
-        .shutdown       = leds_shutdown,
-        .suspend        = leds_suspend,
-        .resume         = leds_resume,
-};
-
-static struct sys_device leds_device = {
-        .id             = 0,
-        .cls            = &leds_sysclass,
-};
-
-static int __init leds_init(void)
-{
-        int ret;
-        ret = sysdev_class_register(&leds_sysclass);
-        if (ret == 0)
-                ret = sysdev_register(&leds_device);
-        if (ret == 0)
-                ret = sysdev_create_file(&leds_device, &attr_event);
-        return ret;
-}
-
-device_initcall(leds_init);
-
-EXPORT_SYMBOL(leds_event);
-#endif
-
 #ifdef CONFIG_LEDS_TIMER
 static inline void do_leds(void)
 {
@@ -295,39 +151,6 @@ int do_settimeofday(struct timespec *tv)
 EXPORT_SYMBOL(do_settimeofday);
 #endif /* !CONFIG_GENERIC_TIME */
 
-/**
- * save_time_delta - Save the offset between system time and RTC time
- * @delta: pointer to timespec to store delta
- * @rtc: pointer to timespec for current RTC time
- *
- * Return a delta between the system time and the RTC time, such
- * that system time can be restored later with restore_time_delta()
- */
-void save_time_delta(struct timespec *delta, struct timespec *rtc)
-{
-        set_normalized_timespec(delta,
-                                xtime.tv_sec - rtc->tv_sec,
-                                xtime.tv_nsec - rtc->tv_nsec);
-}
-EXPORT_SYMBOL(save_time_delta);
-
-/**
- * restore_time_delta - Restore the current system time
- * @delta: delta returned by save_time_delta()
- * @rtc: pointer to timespec for current RTC time
- */
-void restore_time_delta(struct timespec *delta, struct timespec *rtc)
-{
-        struct timespec ts;
-
-        set_normalized_timespec(&ts,
-                                delta->tv_sec + rtc->tv_sec,
-                                delta->tv_nsec + rtc->tv_nsec);
-
-        do_settimeofday(&ts);
-}
-EXPORT_SYMBOL(restore_time_delta);
-
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
  * Kernel system timer support.
@@ -336,7 +159,6 @@ void timer_tick(void)
 {
         profile_tick(CPU_PROFILING);
         do_leds();
-        do_set_rtc();
         write_seqlock(&xtime_lock);
         do_timer(1);
         write_sequnlock(&xtime_lock);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 3f361a783f43..1621e5327b2a 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -12,15 +12,17 @@
  *  'linux/arch/arm/lib/traps.S'.  Mostly a debugging aid, but will probably
  *  kill the offending process.
  */
-#include <linux/module.h>
 #include <linux/signal.h>
-#include <linux/spinlock.h>
 #include <linux/personality.h>
 #include <linux/kallsyms.h>
-#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
 #include <linux/hardirq.h>
+#include <linux/kdebug.h>
+#include <linux/module.h>
+#include <linux/kexec.h>
+#include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/uaccess.h>
 
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
@@ -224,14 +226,21 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
 #define S_SMP ""
 #endif
 
-static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
+static int __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
 {
         struct task_struct *tsk = thread->task;
         static int die_counter;
+        int ret;
 
         printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
                str, err, ++die_counter);
         sysfs_printk_last_file();
+
+        /* trap and error numbers are mostly meaningless on ARM */
+        ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV);
+        if (ret == NOTIFY_STOP)
+                return ret;
+
         print_modules();
         __show_regs(regs);
         printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n",
@@ -243,6 +252,8 @@ static void __die(const char *str, int err, struct thread_info *thread, struct p
                 dump_backtrace(regs, tsk);
                 dump_instr(KERN_EMERG, regs);
         }
+
+        return ret;
 }
 
 DEFINE_SPINLOCK(die_lock);
@@ -250,16 +261,21 @@ DEFINE_SPINLOCK(die_lock);
 /*
  * This function is protected against re-entrancy.
  */
-NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
+void die(const char *str, struct pt_regs *regs, int err)
 {
         struct thread_info *thread = current_thread_info();
+        int ret;
 
         oops_enter();
 
         spin_lock_irq(&die_lock);
         console_verbose();
         bust_spinlocks(1);
-        __die(str, err, thread, regs);
+        ret = __die(str, err, thread, regs);
+
+        if (regs && kexec_should_crash(thread->task))
+                crash_kexec(regs);
+
         bust_spinlocks(0);
         add_taint(TAINT_DIE);
         spin_unlock_irq(&die_lock);
@@ -267,11 +283,10 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
 
         if (in_interrupt())
                 panic("Fatal exception in interrupt");
-
         if (panic_on_oops)
                 panic("Fatal exception");
-
-        do_exit(SIGSEGV);
+        if (ret != NOTIFY_STOP)
+                do_exit(SIGSEGV);
 }
 
 void arm_notify_die(const char *str, struct pt_regs *regs,
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 4957e13ef55b..b16c07914b55 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -43,10 +43,6 @@ SECTIONS
 
                 INIT_SETUP(16)
 
-                __early_begin = .;
-                        *(.early_param.init)
-                __early_end = .;
-
                 INIT_CALLS
                 CON_INITCALL
                 SECURITY_INITCALL
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0b2ee953f164..2db43a5ddd9b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -89,6 +89,12 @@ config ARCH_AT91CAP9
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
 
+config ARCH_AT572D940HF
+        bool "AT572D940HF"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91X40
         bool "AT91x40"
 
@@ -390,6 +396,23 @@ endif
 
 # ----------------------------------------------------------
 
+if ARCH_AT572D940HF
+
+comment "AT572D940HF Board Type"
+
+config MACH_AT572D940HFEB
+        bool "AT572D940HF-EK"
+        depends on ARCH_AT572D940HF
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
+        help
+          Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
+          <http://www.atmel.com/products/diopsis/default.asp>
+
+endif
+
+# ----------------------------------------------------------
+
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 709fbad4a3ee..027dd570dcc3 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
  obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -69,6 +70,9 @@ obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
 
+# AT572D940HF board-specific support
+obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
+
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
 
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
new file mode 100644
index 000000000000..a6b9c68c003a
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf.c
@@ -0,0 +1,377 @@
+/*
+ * arch/arm/mach-at91/at572d940hf.c
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at572d940hf.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at572d940hf_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT572D940HF_SRAM_BASE),
+                .length         = AT572D940HF_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk macb_clk = {
+        .name           = "macb_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+        .name           = "udc_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+        .name           = "ssc2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc0_clk = {
+        .name           = "tc0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+        .name           = "tc1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+        .name           = "tc2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc3_clk = {
+        .name           = "ssc3_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mAgicV_clk = {
+        .name           = "mAgicV_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_MSIRQ0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &macb_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &mmc_clk,
+        &udc_clk,
+        &twi0_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &ssc2_clk,
+        &tc0_clk,
+        &tc1_clk,
+        &tc2_clk,
+        &ohci_clk,
+        &ssc3_clk,
+        &twi1_clk,
+        &can0_clk,
+        &can1_clk,
+        &mAgicV_clk,
+        /* irq0 .. irq2 */
+};
+
+/*
+ * The five programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+static struct clk pck3 = {
+        .name           = "pck3",
+        .pmc_mask       = AT91_PMC_PCK3,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 3,
+};
+
+static struct clk mAgicV_mem_clk = {
+        .name           = "mAgicV_mem_clk",
+        .pmc_mask       = AT91_PMC_PCK4,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 4,
+};
+
+/* HClocks */
+static struct clk hck0 = {
+        .name           = "hck0",
+        .pmc_mask       = AT91_PMC_HCK0,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 0,
+};
+static struct clk hck1 = {
+        .name           = "hck1",
+        .pmc_mask       = AT91_PMC_HCK1,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 1,
+};
+
+static void __init at572d940hf_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+        clk_register(&pck3);
+        clk_register(&mAgicV_mem_clk);
+
+        clk_register(&hck0);
+        clk_register(&hck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at572d940hf_gpio[] = {
+        {
+                .id             = AT572D940HF_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT572D940HF_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT572D940HF_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }
+};
+
+static void at572d940hf_reset(void)
+{
+        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT572D940HF processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at572d940hf_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
+
+        at91_arch_reset = at572d940hf_reset;
+        at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
+                        | (1 << AT572D940HF_ID_IRQ2);
+
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+
+        /* Register the processor-specific clocks */
+        at572d940hf_register_clocks();
+
+        /* Register GPIO subsystem */
+        at91_gpio_init(at572d940hf_gpio, 3);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller */
+        7,      /* System Peripherals */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        3,      /* Ethernet */
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface 0 */
+        6,      /* Serial Peripheral Interface 0 */
+        6,      /* Serial Peripheral Interface 1 */
+        5,      /* Serial Synchronous Controller 0 */
+        5,      /* Serial Synchronous Controller 1 */
+        5,      /* Serial Synchronous Controller 2 */
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        3,      /* USB Host port */
+        3,      /* Serial Synchronous Controller 3 */
+        0,      /* Two-Wire Interface 1 */
+        0,      /* CAN Controller 0 */
+        0,      /* CAN Controller 1 */
+        0,      /* mAgicV HALT line */
+        0,      /* mAgicV SIRQ0 line */
+        0,      /* mAgicV exception line */
+        0,      /* mAgicV end of DMA line */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+};
+
+void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at572d940hf_default_irq_priority;
+
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
+
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
new file mode 100644
index 000000000000..0fc20a240782
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf_devices.c
@@ -0,0 +1,970 @@
+/*
+ * arch/arm/mach-at91/at572d940hf_devices.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ * Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at572d940hf.h>
+#include <mach/at572d940hf_matrix.h>
+#include <mach/at91sam9_smc.h>
+
+#include "generic.h"
+#include "sam9_smc.h"
+
+
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_data;
+
+static struct resource usbh_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_UHP_BASE,
+                .end    = AT572D940HF_UHP_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_UHP,
+                .end    = AT572D940HF_ID_UHP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_usbh_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &usbh_data,
+        },
+        .resource       = usbh_resources,
+        .num_resources  = ARRAY_SIZE(usbh_resources),
+};
+
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+        if (!data)
+                return;
+
+        usbh_data = *data;
+        platform_device_register(&at572d940hf_usbh_device);
+
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+
+static struct resource udc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_UDP,
+                .end    = AT572D940HF_BASE_UDP + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_UDP,
+                .end    = AT572D940HF_ID_UDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_udc_device = {
+        .name           = "at91_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &udc_data,
+        },
+        .resource       = udc_resources,
+        .num_resources  = ARRAY_SIZE(udc_resources),
+};
+
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->vbus_pin) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+        }
+
+        /* Pullup pin is handled internally */
+
+        udc_data = *data;
+        platform_device_register(&at572d940hf_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = DMA_BIT_MASK(32);
+static struct at91_eth_data eth_data;
+
+static struct resource eth_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_EMAC,
+                .end    = AT572D940HF_BASE_EMAC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_EMAC,
+                .end    = AT572D940HF_ID_EMAC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_eth_device = {
+        .name           = "macb",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &eth_dmamask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+                        .platform_data          = &eth_data,
+        },
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
+};
+
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+
+        /* Only RMII is supported */
+        data->is_rmii = 1;
+
+        /* Pins used for RMII */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXCK_EREFCK */
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA20, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA23, 0);    /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA21, 0);    /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA22, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* EMDC */
+
+        eth_data = *data;
+        platform_device_register(&at572d940hf_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = DMA_BIT_MASK(32);
+static struct at91_mmc_data mmc_data;
+
+static struct resource mmc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_MCI,
+                .end    = AT572D940HF_BASE_MCI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_MCI,
+                .end    = AT572D940HF_ID_MCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_mmc_device = {
+        .name           = "at91_mci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &mmc_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &mmc_data,
+        },
+        .resource       = mmc_resources,
+        .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+{
+        if (!data)
+                return;
+
+        /* input/irq */
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 1);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        if (data->wp_pin)
+                at91_set_gpio_input(data->wp_pin, 1);
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
+
+        /* CLK */
+        at91_set_A_periph(AT91_PIN_PC22, 0);
+
+        /* CMD */
+        at91_set_A_periph(AT91_PIN_PC23, 1);
+
+        /* DAT0, maybe DAT1..DAT3 */
+        at91_set_A_periph(AT91_PIN_PC24, 1);
+        if (data->wire4) {
+                at91_set_A_periph(AT91_PIN_PC25, 1);
+                at91_set_A_periph(AT91_PIN_PC26, 1);
+                at91_set_A_periph(AT91_PIN_PC27, 1);
+        }
+
+        mmc_data = *data;
+        platform_device_register(&at572d940hf_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
+static struct atmel_nand_data nand_data;
+
+#define NAND_BASE       AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+        {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at572d940hf_nand_device = {
+        .name           = "atmel_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct atmel_nand_data *data)
+{
+        unsigned long csa;
+
+        if (!data)
+                return;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+
+        at91_set_A_periph(AT91_PIN_PB28, 0);            /* A[22] */
+        at91_set_B_periph(AT91_PIN_PA28, 0);            /* NANDOE */
+        at91_set_B_periph(AT91_PIN_PA29, 0);            /* NANDWE */
+
+        nand_data = *data;
+        platform_device_register(&at572d940hf_nand_device);
+}
+
+#else
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+/*
+ * Prefer the GPIO code since the TWI controller isn't robust
+ * (gets overruns and underruns under load) and can only issue
+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
+ */
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+
+static struct i2c_gpio_platform_data pdata = {
+        .sda_pin                = AT91_PIN_PC7,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PC8,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+
+static struct platform_device at572d940hf_twi_device {
+        .name                   = "i2c-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &pdata,
+};
+
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+        at91_set_GPIO_periph(AT91_PIN_PC7, 1);          /* TWD (SDA) */
+        at91_set_multi_drive(AT91_PIN_PC7, 1);
+
+        at91_set_GPIO_periph(AT91_PIN_PA8, 1);          /* TWCK (SCL) */
+        at91_set_multi_drive(AT91_PIN_PC8, 1);
+
+        i2c_register_board_info(0, devices, nr_devices);
+        platform_device_register(&at572d940hf_twi_device);
+}
+
+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TWI0,
+                .end    = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TWI0,
+                .end    = AT572D940HF_ID_TWI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_twi0_device = {
+        .name           = "at91_i2c",
+        .id             = 0,
+        .resource       = twi0_resources,
+        .num_resources  = ARRAY_SIZE(twi0_resources),
+};
+
+static struct resource twi1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TWI1,
+                .end    = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TWI1,
+                .end    = AT572D940HF_ID_TWI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_twi1_device = {
+        .name           = "at91_i2c",
+        .id             = 1,
+        .resource       = twi1_resources,
+        .num_resources  = ARRAY_SIZE(twi1_resources),
+};
+
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+        /* pins used for TWI0 interface */
+        at91_set_A_periph(AT91_PIN_PC7, 0);             /* TWD */
+        at91_set_multi_drive(AT91_PIN_PC7, 1);
+
+        at91_set_A_periph(AT91_PIN_PC8, 0);             /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PC8, 1);
+
+        /* pins used for TWI1 interface */
+        at91_set_A_periph(AT91_PIN_PC20, 0);            /* TWD */
+        at91_set_multi_drive(AT91_PIN_PC20, 1);
+
+        at91_set_A_periph(AT91_PIN_PC21, 0);            /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PC21, 1);
+
+        i2c_register_board_info(0, devices, nr_devices);
+        platform_device_register(&at572d940hf_twi0_device);
+        platform_device_register(&at572d940hf_twi1_device);
+}
+#else
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_SPI0,
+                .end    = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_SPI0,
+                .end    = AT572D940HF_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_SPI1,
+                .end    = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_SPI1,
+                .end    = AT572D940HF_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+
+        spi_register_board_info(devices, nr_devices);
+
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
+
+                at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
+                platform_device_register(&at572d940hf_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PC0, 0);     /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PC1, 0);     /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PC2, 0);     /* SPI1_SPCK */
+
+                at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
+                platform_device_register(&at572d940hf_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TCB,
+                .end    = AT572D940HF_BASE_TCB + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TC0,
+                .end    = AT572D940HF_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT572D940HF_ID_TC1,
+                .end    = AT572D940HF_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT572D940HF_ID_TC2,
+                .end    = AT572D940HF_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
+        platform_device_register(&at572d940hf_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  RTT
+ * -------------------------------------------------------------------- */
+
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at572d940hf_rtt_device = {
+        .name           = "at91_rtt",
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
+};
+
+static void __init at91_add_device_rtt(void)
+{
+        platform_device_register(&at572d940hf_rtt_device);
+}
+
+
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct platform_device at572d940hf_wdt_device = {
+        .name           = "at91_wdt",
+        .id             = -1,
+        .num_resources  = 0,
+};
+
+static void __init at91_add_device_watchdog(void)
+{
+        platform_device_register(&at572d940hf_wdt_device);
+}
+#else
+static void __init at91_add_device_watchdog(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &dbgu_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &dbgu_data,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
+        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
+}
+
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US0,
+                .end    = AT572D940HF_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US0,
+                .end    = AT572D940HF_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart0_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &uart0_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart0_data,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PA8, 1);             /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PA10, 0);    /* RTS0 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PA9, 0);     /* CTS0 */
+}
+
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US1,
+                .end    = AT572D940HF_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US1,
+                .end    = AT572D940HF_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart1_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .dma_mask               = &uart1_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart1_data,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PC10, 1);            /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PC9 , 0);            /* RXD1 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PC12, 0);    /* RTS1 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PC11, 0);    /* CTS1 */
+}
+
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US2,
+                .end    = AT572D940HF_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US2,
+                .end    = AT572D940HF_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart2_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .dma_mask               = &uart2_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart2_data,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PC15, 1);            /* TXD2 */
+        at91_set_A_periph(AT91_PIN_PC14, 0);            /* RXD2 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PC17, 0);    /* RTS2 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PC16, 0);    /* CTS2 */
+}
+
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
+{
+        struct platform_device *pdev;
+
+        switch (id) {
+                case 0:         /* DBGU */
+                        pdev = &at572d940hf_dbgu_device;
+                        configure_dbgu_pins();
+                        at91_clock_associate("mck", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US0:
+                        pdev = &at572d940hf_uart0_device;
+                        configure_usart0_pins(pins);
+                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US1:
+                        pdev = &at572d940hf_uart1_device;
+                        configure_usart1_pins(pins);
+                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US2:
+                        pdev = &at572d940hf_uart2_device;
+                        configure_usart2_pins(pins);
+                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
+                        break;
+                default:
+                        return;
+        }
+        pdev->id = portnr;              /* update to mapped ID */
+
+        if (portnr < ATMEL_MAX_UART)
+                at91_uarts[portnr] = pdev;
+}
+
+void __init at91_set_serial_console(unsigned portnr)
+{
+        if (portnr < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[portnr];
+}
+
+void __init at91_add_device_serial(void)
+{
+        int i;
+
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+
+#else
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init at91_set_serial_console(unsigned portnr) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  mAgic
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_MAGICV
+static struct resource mAgic_resources[] = {
+        {
+                .start = AT91_MAGIC_PM_BASE,
+                .end   = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_I_BASE,
+                .end   = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_F_BASE,
+                .end   = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_DB_BASE,
+                .end   = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_REGS_BASE,
+                .end   = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_EXTPAGE_BASE,
+                .end   = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = AT572D940HF_ID_MSIRQ0,
+                .end    = AT572D940HF_ID_MSIRQ0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MHALT,
+                .end    = AT572D940HF_ID_MHALT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MEXC,
+                .end    = AT572D940HF_ID_MEXC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MEDMA,
+                .end    = AT572D940HF_ID_MEDMA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mAgic_device = {
+        .name           = "mAgic",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mAgic_resources),
+        .resource       = mAgic_resources,
+};
+
+void __init at91_add_device_mAgic(void)
+{
+        platform_device_register(&mAgic_device);
+}
+#else
+void __init at91_add_device_mAgic(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        at91_add_device_rtt();
+        at91_add_device_watchdog();
+        at91_add_device_tc();
+        return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
new file mode 100644
index 000000000000..5daff277f53e
--- /dev/null
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -0,0 +1,328 @@
+/*
+ * linux/arch/arm/mach-at91/board-at572d940hf_ek.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ds1305.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+
+static void __init eb_map_io(void)
+{
+        /* Initialize processor: 12.500 MHz crystal */
+        at572d940hf_initialize(12000000);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx & Tx only) */
+        at91_register_uart(AT572D940HF_ID_US0, 1, 0);
+
+        /* USART1 on ttyS2. (Rx & Tx only) */
+        at91_register_uart(AT572D940HF_ID_US1, 2, 0);
+
+        /* USART2 on ttyS3. (Tx & Rx only */
+        at91_register_uart(AT572D940HF_ID_US2, 3, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init eb_init_irq(void)
+{
+        at572d940hf_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host Port
+ */
+static struct at91_usbh_data __initdata eb_usbh_data = {
+        .ports          = 2,
+};
+
+
+/*
+ * USB Device Port
+ */
+static struct at91_udc_data __initdata eb_udc_data = {
+        .vbus_pin       = 0,            /* no VBUS detection,UDC always on */
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata eb_mmc_data = {
+        .wire4          = 1,
+/*      .det_pin        = ... not connected */
+/*      .wp_pin         = ... not connected */
+/*      .vcc_pin        = ... not connected */
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata eb_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PB25,
+        .is_rmii        = 1,
+};
+
+/*
+ * NOR flash
+ */
+
+static struct mtd_partition eb_nor_partitions[] = {
+        {
+                .name           = "Raw Environment",
+                .offset         = 0,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "OS FS",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 3 * SZ_1M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "APP FS",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+
+static void nor_flash_set_vpp(struct map_info* mi, int i) {
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 4,
+        .parts          = eb_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(eb_nor_partitions),
+        .set_vpp        = nor_flash_set_vpp,
+};
+
+static struct resource nor_flash_resources[] = {
+        {
+                .start  = AT91_CHIPSELECT_0,
+                .end    = AT91_CHIPSELECT_0 + SZ_16M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data = &nor_flash_data,
+                        },
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+
+static struct sam9_smc_config __initdata eb_nor_smc_config = {
+        .ncs_read_setup         = 1,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 1,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 7,
+        .nrd_pulse              = 7,
+        .ncs_write_pulse        = 7,
+        .nwe_pulse              = 7,
+
+        .read_cycle             = 9,
+        .write_cycle            = 9,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
+        .tdf_cycles             = 1,
+};
+
+static void __init eb_add_device_nor(void)
+{
+        /* configure chip-select 0 (NOR) */
+        sam9_smc_configure(0, &eb_nor_smc_config);
+        platform_device_register(&nor_flash);
+}
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata eb_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = SZ_16M,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(eb_nand_partition);
+        return eb_nand_partition;
+}
+
+static struct atmel_nand_data __initdata eb_nand_data = {
+        .ale            = 22,
+        .cle            = 21,
+/*      .det_pin        = ... not connected */
+/*      .rdy_pin        = AT91_PIN_PC16, */
+        .enable_pin     = AT91_PIN_PA15,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+static struct sam9_smc_config __initdata eb_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 0,
+        .ncs_write_setup        = 1,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 3,
+        .nrd_pulse              = 3,
+        .ncs_write_pulse        = 3,
+        .nwe_pulse              = 3,
+
+        .read_cycle             = 5,
+        .write_cycle            = 5,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+        .tdf_cycles             = 12,
+};
+
+static void __init eb_add_device_nand(void)
+{
+        /* setup bus-width (8 or 16) */
+        if (eb_nand_data.bus_width_16)
+                eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
+        else
+                eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+        /* configure chip-select 3 (NAND) */
+        sam9_smc_configure(3, &eb_nand_smc_config);
+
+        at91_add_device_nand(&eb_nand_data);
+}
+
+
+/*
+ * SPI devices
+ */
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_ID_IRQ1,
+                .end    = AT572D940HF_ID_IRQ1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ds1305_platform_data ds1306_data = {
+        .is_ds1306      = true,
+        .en_1hz         = false,
+};
+
+static struct spi_board_info eb_spi_devices[] = {
+        {       /* RTC Dallas DS1306 */
+                .modalias       = "rtc-ds1305",
+                .chip_select    = 3,
+                .mode           = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
+                .max_speed_hz   = 500000,
+                .bus_num        = 0,
+                .irq            = AT572D940HF_ID_IRQ1,
+                .platform_data  = (void *) &ds1306_data,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* Dataflash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+};
+
+static void __init eb_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&eb_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&eb_udc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* NOR */
+        eb_add_device_nor();
+        /* NAND */
+        eb_add_device_nand();
+        /* SPI */
+        at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &eb_mmc_data);
+        /* Ethernet */
+        at91_add_device_eth(&eb_eth_data);
+        /* mAgic */
+        at91_add_device_mAgic();
+}
+
+MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
+        /* Maintainer: Atmel <costa.antonior@gmail.com> */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = eb_map_io,
+        .init_irq       = eb_init_irq,
+        .init_machine   = eb_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index c042dcf4725f..7f7da439341f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -29,6 +29,7 @@
 #include <mach/cpu.h>
 
 #include "clock.h"
+#include "generic.h"
 
 
 /*
@@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
-                   cpu_is_at91sam9g10()) {
+                   cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         } else if (cpu_is_at91cap9()) {
@@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock)
         /*
          * USB HS clock init
          */
-        if (cpu_has_utmi())
+        if (cpu_has_utmi()) {
                 /*
                  * multiplier is hard-wired to 40
                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                  */
                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+        }
 
         /*
          * USB FS clock init
@@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock)
                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
         } else {
-                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
         }
 
         /* Register the PMC's standard clocks */
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index 1ba3b95ff359..6cf4b78e175d 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -22,7 +22,7 @@ struct clk {
         struct clk      *parent;
         u32             pmc_mask;
         void            (*mode)(struct clk *, int);
-        unsigned        id:2;           /* PCK0..3, or 32k/main/a/b */
+        unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
         unsigned        type;           /* clock type */
         u16             users;
 };
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 88e413b38480..65c3dc5ba0d0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
 extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
+extern void __init at572d940hf_initialize(unsigned long main_clock);
 
  /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
+extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
new file mode 100644
index 000000000000..2d9b0af9c4d5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach/at572d940hf.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef AT572D940HF_H
+#define AT572D940HF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT572D940HF_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC     5       /* MACB ethernet controller */
+#define AT572D940HF_ID_US0      6       /* USART 0 */
+#define AT572D940HF_ID_US1      7       /* USART 1 */
+#define AT572D940HF_ID_US2      8       /* USART 2 */
+#define AT572D940HF_ID_MCI      9       /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP      10      /* USB Device Port */
+#define AT572D940HF_ID_TWI0     11      /* Two-Wire Interface 0 */
+#define AT572D940HF_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT572D940HF_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT572D940HF_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT572D940HF_ID_TC0      17      /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1      18      /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2      19      /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP      20      /* USB Host port */
+#define AT572D940HF_ID_SSC3     21      /* Serial Synchronous Controller 3 */
+#define AT572D940HF_ID_TWI1     22      /* Two-Wire Interface 1 */
+#define AT572D940HF_ID_CAN0     23      /* CAN Controller 0 */
+#define AT572D940HF_ID_CAN1     24      /* CAN Controller 1 */
+#define AT572D940HF_ID_MHALT    25      /* mAgicV HALT line */
+#define AT572D940HF_ID_MSIRQ0   26      /* mAgicV SIRQ0 line */
+#define AT572D940HF_ID_MEXC     27      /* mAgicV exception line */
+#define AT572D940HF_ID_MEDMA    28      /* mAgicV end of DMA line */
+#define AT572D940HF_ID_IRQ0     29      /* External Interrupt Source (IRQ0) */
+#define AT572D940HF_ID_IRQ1     30      /* External Interrupt Source (IRQ1) */
+#define AT572D940HF_ID_IRQ2     31      /* External Interrupt Source (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB    0xfffa0000
+#define AT572D940HF_BASE_TC0    0xfffa0000
+#define AT572D940HF_BASE_TC1    0xfffa0040
+#define AT572D940HF_BASE_TC2    0xfffa0080
+#define AT572D940HF_BASE_UDP    0xfffa4000
+#define AT572D940HF_BASE_MCI    0xfffa8000
+#define AT572D940HF_BASE_TWI0   0xfffac000
+#define AT572D940HF_BASE_US0    0xfffb0000
+#define AT572D940HF_BASE_US1    0xfffb4000
+#define AT572D940HF_BASE_US2    0xfffb8000
+#define AT572D940HF_BASE_SSC0   0xfffbc000
+#define AT572D940HF_BASE_SSC1   0xfffc0000
+#define AT572D940HF_BASE_SSC2   0xfffc4000
+#define AT572D940HF_BASE_SPI0   0xfffc8000
+#define AT572D940HF_BASE_SPI1   0xfffcc000
+#define AT572D940HF_BASE_SSC3   0xfffd0000
+#define AT572D940HF_BASE_TWI1   0xfffd4000
+#define AT572D940HF_BASE_EMAC   0xfffd8000
+#define AT572D940HF_BASE_CAN0   0xfffdc000
+#define AT572D940HF_BASE_CAN1   0xfffe0000
+#define AT91_BASE_SYS           0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT572D940HF_ID_US0
+#define AT91_USART1     AT572D940HF_ID_US1
+#define AT91_USART2     AT572D940HF_ID_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT572D940HF_SRAM_SIZE   (48 * SZ_1K)    /* Internal SRAM size (48Kb) */
+
+#define AT572D940HF_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT572D940HF_UHP_BASE    0x00500000      /* USB Host controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
new file mode 100644
index 000000000000..b6751df09488
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach//at572d940hf_matrix.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef AT572D940HF_MATRIX_H
+#define AT572D940HF_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0x7  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SFR0        (AT91_MATRIX + 0x110)   /* Special Function Register 0 */
+#define AT91_MATRIX_SFR1        (AT91_MATRIX + 0x114)   /* Special Function Register 1 */
+#define AT91_MATRIX_SFR2        (AT91_MATRIX + 0x118)   /* Special Function Register 2 */
+#define AT91_MATRIX_SFR3        (AT91_MATRIX + 0x11C)   /* Special Function Register 3 */
+#define AT91_MATRIX_SFR4        (AT91_MATRIX + 0x120)   /* Special Function Register 4 */
+#define AT91_MATRIX_SFR5        (AT91_MATRIX + 0x124)   /* Special Function Register 5 */
+#define AT91_MATRIX_SFR6        (AT91_MATRIX + 0x128)   /* Special Function Register 6 */
+#define AT91_MATRIX_SFR7        (AT91_MATRIX + 0x12C)   /* Special Function Register 7 */
+#define AT91_MATRIX_SFR8        (AT91_MATRIX + 0x130)   /* Special Function Register 8 */
+#define AT91_MATRIX_SFR9        (AT91_MATRIX + 0x134)   /* Special Function Register 9 */
+#define AT91_MATRIX_SFR10       (AT91_MATRIX + 0x138)   /* Special Function Register 10 */
+#define AT91_MATRIX_SFR11       (AT91_MATRIX + 0x13C)   /* Special Function Register 11 */
+#define AT91_MATRIX_SFR12       (AT91_MATRIX + 0x140)   /* Special Function Register 12 */
+#define AT91_MATRIX_SFR13       (AT91_MATRIX + 0x144)   /* Special Function Register 13 */
+#define AT91_MATRIX_SFR14       (AT91_MATRIX + 0x148)   /* Special Function Register 14 */
+#define AT91_MATRIX_SFR15       (AT91_MATRIX + 0x14C)   /* Special Function Register 15 */
+
+
+/*
+ * The following registers / bits are not defined in the Datasheet (Revision A)
+ */
+
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x100)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 64589eaaaee8..e46f93e34aab 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -32,6 +32,7 @@
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
 #define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_PCK4           (1 << 12)               /* Programmable Clock 4 [AT572D940HF only] */
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index bb6f6a7ba5e0..ceaec6c16eb2 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -87,7 +87,7 @@ struct at91_eth_data {
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
 #define eth_platform_data       at91_eth_data
 #endif
 
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
+ /* AT572D940HF DSP */
+extern void __init at91_add_device_mAgic(void);
+
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
 
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c22df30ed5e5..5a0650101d45 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -33,6 +33,8 @@
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
 
+#define ARCH_ID_AT572D940HF     0x0e0303e0
+
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91cap9_revC()  (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT572D940HF
+#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
+#else
+#define cpu_is_at572d940hf() (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a0df8b022df2..3d64a75e3ed5 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,8 @@
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
+#elif defined(CONFIG_ARCH_AT572D940HF)
+#include <mach/at572d940hf.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..05a6e8af80c4 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,6 +82,11 @@
 #define AT91X40_MASTER_CLOCK    40000000
 #define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 
+#elif defined(CONFIG_ARCH_AT572D940HF)
+
+#define AT572D940HF_MASTER_CLOCK        80000000
+#define CLOCK_TICK_RATE         (AT572D940HF_MASTER_CLOCK/16)
+
 #endif
 
 #endif
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index e590bbe0a7b4..72e405df0fb0 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -142,8 +142,7 @@ void __init bcmring_amba_init(void)
 
         chipcHw_busInterfaceClockEnable(bus_clock);
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index b476395d2cd4..38e9033d2e86 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -37,6 +37,8 @@
 #include <mach/nand.h>
 #include <mach/keyscan.h>
 
+#include <media/tvp514x.h>
+
 static inline int have_imager(void)
 {
         /* REVISIT when it's supported, trigger via Kconfig */
@@ -306,6 +308,73 @@ static void dm365evm_mmc_configure(void)
         davinci_cfg_reg(DM365_SD1_DATA0);
 }
 
+static struct tvp514x_platform_data tvp5146_pdata = {
+        .clk_polarity = 0,
+        .hs_polarity = 1,
+        .vs_polarity = 1
+};
+
+#define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
+/* Inputs available at the TVP5146 */
+static struct v4l2_input tvp5146_inputs[] = {
+        {
+                .index = 0,
+                .name = "Composite",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = TVP514X_STD_ALL,
+        },
+        {
+                .index = 1,
+                .name = "S-Video",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = TVP514X_STD_ALL,
+        },
+};
+
+/*
+ * this is the route info for connecting each input to decoder
+ * ouput that goes to vpfe. There is a one to one correspondence
+ * with tvp5146_inputs
+ */
+static struct vpfe_route tvp5146_routes[] = {
+        {
+                .input = INPUT_CVBS_VI2B,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+        },
+{
+                .input = INPUT_SVIDEO_VI2C_VI1C,
+                .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
+        },
+};
+
+static struct vpfe_subdev_info vpfe_sub_devs[] = {
+        {
+                .name = "tvp5146",
+                .grp_id = 0,
+                .num_inputs = ARRAY_SIZE(tvp5146_inputs),
+                .inputs = tvp5146_inputs,
+                .routes = tvp5146_routes,
+                .can_route = 1,
+                .ccdc_if_params = {
+                        .if_type = VPFE_BT656,
+                        .hdpol = VPFE_PINPOL_POSITIVE,
+                        .vdpol = VPFE_PINPOL_POSITIVE,
+                },
+                .board_info = {
+                        I2C_BOARD_INFO("tvp5146", 0x5d),
+                        .platform_data = &tvp5146_pdata,
+                },
+        },
+};
+
+static struct vpfe_config vpfe_cfg = {
+        .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
+        .sub_devs = vpfe_sub_devs,
+        .i2c_adapter_id = 1,
+        .card_name = "DM365 EVM",
+        .ccdc = "ISIF",
+};
+
 static void __init evm_init_i2c(void)
 {
         davinci_init_i2c(&i2c_pdata);
@@ -497,6 +566,8 @@ static struct davinci_uart_config uart_config __initdata = {
 
 static void __init dm365_evm_map_io(void)
 {
+        /* setup input configuration for VPFE input devices */
+        dm365_set_vpfe_config(&vpfe_cfg);
         dm365_init();
 }
 
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index dedf4d4f3a27..d84e85414d20 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -125,7 +125,6 @@ static struct clk vpss_slave_clk = {
         .lpsc = DAVINCI_LPSC_VPSSSLV,
 };
 
-
 static struct clk clkout1_clk = {
         .name = "clkout1",
         .parent = &pll1_aux_clk,
@@ -665,6 +664,17 @@ static struct platform_device dm355_asp1_device = {
         .resource       = dm355_asp1_resources,
 };
 
+static void dm355_ccdc_setup_pinmux(void)
+{
+        davinci_cfg_reg(DM355_VIN_PCLK);
+        davinci_cfg_reg(DM355_VIN_CAM_WEN);
+        davinci_cfg_reg(DM355_VIN_CAM_VD);
+        davinci_cfg_reg(DM355_VIN_CAM_HD);
+        davinci_cfg_reg(DM355_VIN_YIN_EN);
+        davinci_cfg_reg(DM355_VIN_CINL_EN);
+        davinci_cfg_reg(DM355_VIN_CINH_EN);
+}
+
 static struct resource dm355_vpss_resources[] = {
         {
                 /* VPSS BL Base address */
@@ -701,6 +711,10 @@ static struct resource vpfe_resources[] = {
                 .end            = IRQ_VDINT1,
                 .flags          = IORESOURCE_IRQ,
         },
+};
+
+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct resource dm355_ccdc_resource[] = {
         /* CCDC Base address */
         {
                 .flags          = IORESOURCE_MEM,
@@ -708,8 +722,18 @@ static struct resource vpfe_resources[] = {
                 .end            = 0x01c70600 + 0x1ff,
         },
 };
+static struct platform_device dm355_ccdc_dev = {
+        .name           = "dm355_ccdc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm355_ccdc_resource),
+        .resource       = dm355_ccdc_resource,
+        .dev = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = dm355_ccdc_setup_pinmux,
+        },
+};
 
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 static struct platform_device vpfe_capture_dev = {
         .name           = CAPTURE_DRV_NAME,
         .id             = -1,
@@ -857,20 +881,13 @@ static int __init dm355_init_devices(void)
         if (!cpu_is_davinci_dm355())
                 return 0;
 
+        /* Add ccdc clock aliases */
+        clk_add_alias("master", dm355_ccdc_dev.name, "vpss_master", NULL);
+        clk_add_alias("slave", dm355_ccdc_dev.name, "vpss_master", NULL);
         davinci_cfg_reg(DM355_INT_EDMA_CC);
         platform_device_register(&dm355_edma_device);
         platform_device_register(&dm355_vpss_device);
-        /*
-         * setup Mux configuration for vpfe input and register
-         * vpfe capture platform device
-         */
-        davinci_cfg_reg(DM355_VIN_PCLK);
-        davinci_cfg_reg(DM355_VIN_CAM_WEN);
-        davinci_cfg_reg(DM355_VIN_CAM_VD);
-        davinci_cfg_reg(DM355_VIN_CAM_HD);
-        davinci_cfg_reg(DM355_VIN_YIN_EN);
-        davinci_cfg_reg(DM355_VIN_CINL_EN);
-        davinci_cfg_reg(DM355_VIN_CINH_EN);
+        platform_device_register(&dm355_ccdc_dev);
         platform_device_register(&vpfe_capture_dev);
 
         return 0;
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index f53735cb922e..ce9da43a628b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1008,6 +1008,97 @@ void __init dm365_init(void)
         davinci_common_init(&davinci_soc_info_dm365);
 }
 
+static struct resource dm365_vpss_resources[] = {
+        {
+                /* VPSS ISP5 Base address */
+                .name           = "isp5",
+                .start          = 0x01c70000,
+                .end            = 0x01c70000 + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+        {
+                /* VPSS CLK Base address */
+                .name           = "vpss",
+                .start          = 0x01c70200,
+                .end            = 0x01c70200 + 0xff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device dm365_vpss_device = {
+       .name                   = "vpss",
+       .id                     = -1,
+       .dev.platform_data      = "dm365_vpss",
+       .num_resources          = ARRAY_SIZE(dm365_vpss_resources),
+       .resource               = dm365_vpss_resources,
+};
+
+static struct resource vpfe_resources[] = {
+        {
+                .start          = IRQ_VDINT0,
+                .end            = IRQ_VDINT0,
+                .flags          = IORESOURCE_IRQ,
+        },
+        {
+                .start          = IRQ_VDINT1,
+                .end            = IRQ_VDINT1,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct platform_device vpfe_capture_dev = {
+        .name           = CAPTURE_DRV_NAME,
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(vpfe_resources),
+        .resource       = vpfe_resources,
+        .dev = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+static void dm365_isif_setup_pinmux(void)
+{
+        davinci_cfg_reg(DM365_VIN_CAM_WEN);
+        davinci_cfg_reg(DM365_VIN_CAM_VD);
+        davinci_cfg_reg(DM365_VIN_CAM_HD);
+        davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
+        davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
+}
+
+static struct resource isif_resource[] = {
+        /* ISIF Base address */
+        {
+                .start          = 0x01c71000,
+                .end            = 0x01c71000 + 0x1ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        /* ISIF Linearization table 0 */
+        {
+                .start          = 0x1C7C000,
+                .end            = 0x1C7C000 + 0x2ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        /* ISIF Linearization table 1 */
+        {
+                .start          = 0x1C7C400,
+                .end            = 0x1C7C400 + 0x2ff,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+static struct platform_device dm365_isif_dev = {
+        .name           = "isif",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(isif_resource),
+        .resource       = isif_resource,
+        .dev = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = dm365_isif_setup_pinmux,
+        },
+};
+
 static int __init dm365_init_devices(void)
 {
         if (!cpu_is_davinci_dm365())
@@ -1016,7 +1107,16 @@ static int __init dm365_init_devices(void)
         davinci_cfg_reg(DM365_INT_EDMA_CC);
         platform_device_register(&dm365_edma_device);
         platform_device_register(&dm365_emac_device);
-
+        /* Add isif clock alias */
+        clk_add_alias("master", dm365_isif_dev.name, "vpss_master", NULL);
+        platform_device_register(&dm365_vpss_device);
+        platform_device_register(&dm365_isif_dev);
+        platform_device_register(&vpfe_capture_dev);
         return 0;
 }
 postcore_initcall(dm365_init_devices);
+
+void dm365_set_vpfe_config(struct vpfe_config *cfg)
+{
+       vpfe_capture_dev.dev.platform_data = cfg;
+}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 2cd008156dea..92aeb5600680 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -612,6 +612,11 @@ static struct resource vpfe_resources[] = {
                 .end            = IRQ_VDINT1,
                 .flags          = IORESOURCE_IRQ,
         },
+};
+
+static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct resource dm644x_ccdc_resource[] = {
+        /* CCDC Base address */
         {
                 .start          = 0x01c70400,
                 .end            = 0x01c70400 + 0xff,
@@ -619,7 +624,17 @@ static struct resource vpfe_resources[] = {
         },
 };
 
-static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
+static struct platform_device dm644x_ccdc_dev = {
+        .name           = "dm644x_ccdc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),
+        .resource       = dm644x_ccdc_resource,
+        .dev = {
+                .dma_mask               = &vpfe_capture_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
 static struct platform_device vpfe_capture_dev = {
         .name           = CAPTURE_DRV_NAME,
         .id             = -1,
@@ -769,9 +784,13 @@ static int __init dm644x_init_devices(void)
         if (!cpu_is_davinci_dm644x())
                 return 0;
 
+        /* Add ccdc clock aliases */
+        clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL);
+        clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL);
         platform_device_register(&dm644x_edma_device);
         platform_device_register(&dm644x_emac_device);
         platform_device_register(&dm644x_vpss_device);
+        platform_device_register(&dm644x_ccdc_dev);
         platform_device_register(&vpfe_capture_dev);
 
         return 0;
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index f1710a30e7ba..9fc5a64a5364 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -18,6 +18,7 @@
 #include <mach/emac.h>
 #include <mach/asp.h>
 #include <mach/keyscan.h>
+#include <media/davinci/vpfe_capture.h>
 
 #define DM365_EMAC_BASE                 (0x01D07000)
 #define DM365_EMAC_CNTRL_OFFSET         (0x0000)
@@ -36,4 +37,5 @@ void __init dm365_init_asp(struct snd_platform_data *pdata);
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
 void __init dm365_init_rtc(void);
 
+void dm365_set_vpfe_config(struct vpfe_config *cfg);
 #endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 41c89386e39b..c45ba1f62a11 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -27,7 +27,7 @@
 /*
  * I/O mapping
  */
-#define IO_PHYS                         0x01c00000
+#define IO_PHYS                         0x01c00000UL
 #define IO_OFFSET                       0xfd000000 /* Virtual IO = 0xfec00000 */
 #define IO_SIZE                         0x00400000
 #define IO_VIRT                         (IO_PHYS + IO_OFFSET)
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 49912b48b1b0..a1c0b6b99edf 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -24,7 +24,7 @@ void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
         if (BETWEEN(p, IO_PHYS, IO_SIZE))
                 return XLATE(p, IO_PHYS, IO_VIRT);
 
-        return __arm_ioremap(p, size, type);
+        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(davinci_ioremap);
 
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
index 8b2c974755c6..a28792cf761e 100644
--- a/arch/arm/mach-dove/include/mach/vmalloc.h
+++ b/arch/arm/mach-dove/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-dove/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfd800000
+#define VMALLOC_END     0xfd800000UL
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 9167c3d2a5ed..3a08b18f6433 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -161,6 +161,20 @@ config MACH_MICRO9S
           Say 'Y' here if you want your kernel to support the
           Contec Micro9-Slim board.
 
+config MACH_SIM_ONE
+        bool "Support Simplemachines Sim.One board"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the
+          Simplemachines Sim.One board.
+
+config MACH_SNAPPER_CL15
+        bool "Support Bluewater Systems Snapper CL15 Module"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the Bluewater
+          Systems Snapper CL15 Module.
+
 config MACH_TS72XX
         bool "Support Technologic Systems TS-72xx SBC"
         depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index eae6199a9891..33ee2c863d18 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -10,4 +10,6 @@ obj-$(CONFIG_MACH_ADSSPHERE)	+= adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
 obj-$(CONFIG_MACH_MICRO9)       += micro9.o
+obj-$(CONFIG_MACH_SIM_ONE)      += simone.o
+obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o
 obj-$(CONFIG_MACH_TS72XX)       += ts72xx.o
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 1d0f9d8aff2e..5f80092b6ace 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -10,6 +10,8 @@
  * your option) any later version.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -445,37 +447,39 @@ static void __init ep93xx_dma_clock_init(void)
 static int __init ep93xx_clock_init(void)
 {
         u32 value;
-        int i;
 
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
-        if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
+        /* Determine the bootloader configured pll1 rate */
+        value = __raw_readl(EP93XX_SYSCON_CLKSET1);
+        if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
                 clk_pll1.rate = clk_xtali.rate;
-        } else {
+        else
                 clk_pll1.rate = calc_pll_rate(value);
-        }
+
+        /* Initialize the pll1 derived clocks */
         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
         ep93xx_dma_clock_init();
 
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
-        if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
+        /* Determine the bootloader configured pll2 rate */
+        value = __raw_readl(EP93XX_SYSCON_CLKSET2);
+        if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
                 clk_pll2.rate = clk_xtali.rate;
-        } else if (value & 0x00040000) {                /* PLL2 enabled?  */
+        else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
                 clk_pll2.rate = calc_pll_rate(value);
-        } else {
+        else
                 clk_pll2.rate = 0;
-        }
+
+        /* Initialize the pll2 derived clocks */
         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
-        printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
+        pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
-        printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
+        pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
                 clk_f.rate / 1000000, clk_h.rate / 1000000,
                 clk_p.rate / 1000000);
 
-        for (i = 0; i < ARRAY_SIZE(clocks); i++)
-                clkdev_add(&clocks[i]);
+        clkdev_add_table(clocks, ARRAY_SIZE(clocks));
         return 0;
 }
 arch_initcall(ep93xx_clock_init);
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 1f0d66561bbe..90fb591cbffa 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -14,12 +14,15 @@
  * your option) any later version.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/timex.h>
+#include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
@@ -35,7 +38,6 @@
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
 
 #include <asm/hardware/vic.h>
 
@@ -82,13 +84,40 @@ void __init ep93xx_map_io(void)
  * to use this timer for something else.  We also use timer 4 for keeping
  * track of lost jiffies.
  */
-static unsigned int last_jiffy_time;
-
+#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
+#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
+#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
+#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
+#define EP93XX_TIMER123_CONTROL_ENABLE  (1 << 7)
+#define EP93XX_TIMER123_CONTROL_MODE    (1 << 6)
+#define EP93XX_TIMER123_CONTROL_CLKSEL  (1 << 3)
+#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
+#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
+#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
+#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
+#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
+#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
+#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
+#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
+#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
+#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
+#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
+#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
+
+#define EP93XX_TIMER123_CLOCK           508469
+#define EP93XX_TIMER4_CLOCK             983040
+
+#define TIMER1_RELOAD                   ((EP93XX_TIMER123_CLOCK / HZ) - 1)
 #define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
 
+static unsigned int last_jiffy_time;
+
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
+        /* Writing any value clears the timer interrupt */
         __raw_writel(1, EP93XX_TIMER1_CLEAR);
+
+        /* Recover lost jiffies */
         while ((signed long)
                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
                                                 >= TIMER4_TICKS_PER_JIFFY) {
@@ -107,13 +136,18 @@ static struct irqaction ep93xx_timer_irq = {
 
 static void __init ep93xx_timer_init(void)
 {
+        u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
+                    EP93XX_TIMER123_CONTROL_CLKSEL;
+
         /* Enable periodic HZ timer.  */
-        __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
-        __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
-        __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
+        __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+        __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
+        __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
+                        EP93XX_TIMER1_CONTROL);
 
         /* Enable lost jiffy timer.  */
-        __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
+        __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
+                        EP93XX_TIMER4_VALUE_HIGH);
 
         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 }
@@ -135,237 +169,16 @@ struct sys_timer ep93xx_timer = {
 
 
 /*************************************************************************
- * GPIO handling for EP93xx
- *************************************************************************/
-static unsigned char gpio_int_unmasked[3];
-static unsigned char gpio_int_enabled[3];
-static unsigned char gpio_int_type1[3];
-static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debounce[3];
-
-/* Port ordering is: A B F */
-static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
-static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
-static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
-static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
-static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
-
-void ep93xx_gpio_update_int_params(unsigned port)
-{
-        BUG_ON(port > 2);
-
-        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
-
-        __raw_writeb(gpio_int_type2[port],
-                EP93XX_GPIO_REG(int_type2_register_offset[port]));
-
-        __raw_writeb(gpio_int_type1[port],
-                EP93XX_GPIO_REG(int_type1_register_offset[port]));
-
-        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
-                EP93XX_GPIO_REG(int_en_register_offset[port]));
-}
-
-void ep93xx_gpio_int_mask(unsigned line)
-{
-        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-}
-
-void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if (enable)
-                gpio_int_debounce[port] |= port_mask;
-        else
-                gpio_int_debounce[port] &= ~port_mask;
-
-        __raw_writeb(gpio_int_debounce[port],
-                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
-}
-EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
-
-/*************************************************************************
  * EP93xx IRQ handling
  *************************************************************************/
-static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned char status;
-        int i;
-
-        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-
-        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-}
-
-static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        /*
-         * map discontiguous hw irq range to continous sw irq range:
-         *
-         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
-         */
-        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
-        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
-
-        generic_handle_irq(gpio_irq);
-}
-
-static void ep93xx_gpio_irq_ack(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-                ep93xx_gpio_update_int_params(port);
-        }
-
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-
-        gpio_int_unmasked[port] &= ~port_mask;
-        ep93xx_gpio_update_int_params(port);
-
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-
-        gpio_int_unmasked[port] &= ~(1 << (line & 7));
-        ep93xx_gpio_update_int_params(port);
-}
-
-static void ep93xx_gpio_irq_unmask(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-
-        gpio_int_unmasked[port] |= 1 << (line & 7);
-        ep93xx_gpio_update_int_params(port);
-}
-
-
-/*
- * gpio_int_type1 controls whether the interrupt is level (0) or
- * edge (1) triggered, while gpio_int_type2 controls whether it
- * triggers on low/falling (0) or high/rising (1).
- */
-static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-        struct irq_desc *desc = irq_desc + irq;
-        const int gpio = irq_to_gpio(irq);
-        const int port = gpio >> 3;
-        const int port_mask = 1 << (gpio & 7);
-
-        gpio_direction_input(gpio);
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_edge_irq;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_edge_irq;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_level_irq;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_level_irq;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                gpio_int_type1[port] |= port_mask;
-                /* set initial polarity based on current input level */
-                if (gpio_get_value(gpio))
-                        gpio_int_type2[port] &= ~port_mask; /* falling */
-                else
-                        gpio_int_type2[port] |= port_mask; /* rising */
-                desc->handle_irq = handle_edge_irq;
-                break;
-        default:
-                pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
-                       type, gpio);
-                return -EINVAL;
-        }
-
-        gpio_int_enabled[port] |= port_mask;
-
-        desc->status &= ~IRQ_TYPE_SENSE_MASK;
-        desc->status |= type & IRQ_TYPE_SENSE_MASK;
-
-        ep93xx_gpio_update_int_params(port);
-
-        return 0;
-}
-
-static struct irq_chip ep93xx_gpio_irq_chip = {
-        .name           = "GPIO",
-        .ack            = ep93xx_gpio_irq_ack,
-        .mask_ack       = ep93xx_gpio_irq_mask_ack,
-        .mask           = ep93xx_gpio_irq_mask,
-        .unmask         = ep93xx_gpio_irq_unmask,
-        .set_type       = ep93xx_gpio_irq_type,
-};
-
+extern void ep93xx_gpio_init_irq(void);
 
 void __init ep93xx_init_irq(void)
 {
-        int gpio_irq;
-
         vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
         vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
 
-        for (gpio_irq = gpio_to_irq(0);
-             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
-                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
-                set_irq_handler(gpio_irq, handle_level_irq);
-                set_irq_flags(gpio_irq, IRQF_VALID);
-        }
-
-        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+        ep93xx_gpio_init_irq();
 }
 
 
@@ -572,9 +385,9 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
          * CMOS driver.
          */
         if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
-                pr_warning("ep93xx: sda != EEDAT, open drain has no effect\n");
+                pr_warning("sda != EEDAT, open drain has no effect\n");
         if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
-                pr_warning("ep93xx: scl != EECLK, open drain has no effect\n");
+                pr_warning("scl != EECLK, open drain has no effect\n");
 
         __raw_writel((data->sda_is_open_drain << 1) |
                      (data->scl_is_open_drain << 0),
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index dbcac9c40a28..8904ca4e2e24 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -28,6 +28,8 @@
  * with this implementation.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -173,7 +175,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
 
         switch (m2p_channel_state(ch)) {
         case STATE_IDLE:
-                pr_crit("m2p_irq: dma interrupt without a dma buffer\n");
+                pr_crit("dma interrupt without a dma buffer\n");
                 BUG();
                 break;
 
@@ -197,7 +199,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
                 break;
 
         case STATE_NEXT:
-                pr_crit("m2p_irq: dma interrupt while next\n");
+                pr_crit("dma interrupt while next\n");
                 BUG();
                 break;
         }
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index a4a7be308000..d22d67ac8b99 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -118,12 +118,33 @@ static void __init edb93xx_register_i2c(void)
         }
 }
 
+
+/*************************************************************************
+ * EDB93xx pwm
+ *************************************************************************/
+static void __init edb93xx_register_pwm(void)
+{
+        if (machine_is_edb9301() ||
+            machine_is_edb9302() || machine_is_edb9302a()) {
+                /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */
+                ep93xx_register_pwm(0, 1);
+        } else if (machine_is_edb9307() || machine_is_edb9307a()) {
+                /* EP9307 only has pwm.0 (PWMOUT) */
+                ep93xx_register_pwm(1, 0);
+        } else {
+                /* EP9312 and EP9315 have both */
+                ep93xx_register_pwm(1, 1);
+        }
+}
+
+
 static void __init edb93xx_init_machine(void)
 {
         ep93xx_init_devices();
         edb93xx_register_flash();
         ep93xx_register_eth(&edb93xx_eth_data, 1);
         edb93xx_register_i2c();
+        edb93xx_register_pwm();
 }
 
 
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 1ea8871e03a9..cc377ae8c428 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -13,6 +13,8 @@
  *  published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
@@ -22,6 +24,235 @@
 
 #include <mach/hardware.h>
 
+/*************************************************************************
+ * GPIO handling for EP93xx
+ *************************************************************************/
+static unsigned char gpio_int_unmasked[3];
+static unsigned char gpio_int_enabled[3];
+static unsigned char gpio_int_type1[3];
+static unsigned char gpio_int_type2[3];
+static unsigned char gpio_int_debounce[3];
+
+/* Port ordering is: A B F */
+static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
+static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
+static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
+static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
+static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
+
+void ep93xx_gpio_update_int_params(unsigned port)
+{
+        BUG_ON(port > 2);
+
+        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
+
+        __raw_writeb(gpio_int_type2[port],
+                EP93XX_GPIO_REG(int_type2_register_offset[port]));
+
+        __raw_writeb(gpio_int_type1[port],
+                EP93XX_GPIO_REG(int_type1_register_offset[port]));
+
+        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
+                EP93XX_GPIO_REG(int_en_register_offset[port]));
+}
+
+void ep93xx_gpio_int_mask(unsigned line)
+{
+        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
+}
+
+void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+
+        if (enable)
+                gpio_int_debounce[port] |= port_mask;
+        else
+                gpio_int_debounce[port] &= ~port_mask;
+
+        __raw_writeb(gpio_int_debounce[port],
+                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
+}
+EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
+
+static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned char status;
+        int i;
+
+        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
+        for (i = 0; i < 8; i++) {
+                if (status & (1 << i)) {
+                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
+                        generic_handle_irq(gpio_irq);
+                }
+        }
+
+        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
+        for (i = 0; i < 8; i++) {
+                if (status & (1 << i)) {
+                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
+                        generic_handle_irq(gpio_irq);
+                }
+        }
+}
+
+static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        /*
+         * map discontiguous hw irq range to continous sw irq range:
+         *
+         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
+         */
+        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
+        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
+
+        generic_handle_irq(gpio_irq);
+}
+
+static void ep93xx_gpio_irq_ack(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+
+        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+                ep93xx_gpio_update_int_params(port);
+        }
+
+        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+
+static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+
+        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+
+        gpio_int_unmasked[port] &= ~port_mask;
+        ep93xx_gpio_update_int_params(port);
+
+        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+
+static void ep93xx_gpio_irq_mask(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+
+        gpio_int_unmasked[port] &= ~(1 << (line & 7));
+        ep93xx_gpio_update_int_params(port);
+}
+
+static void ep93xx_gpio_irq_unmask(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+
+        gpio_int_unmasked[port] |= 1 << (line & 7);
+        ep93xx_gpio_update_int_params(port);
+}
+
+/*
+ * gpio_int_type1 controls whether the interrupt is level (0) or
+ * edge (1) triggered, while gpio_int_type2 controls whether it
+ * triggers on low/falling (0) or high/rising (1).
+ */
+static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        const int gpio = irq_to_gpio(irq);
+        const int port = gpio >> 3;
+        const int port_mask = 1 << (gpio & 7);
+
+        gpio_direction_input(gpio);
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                gpio_int_type1[port] |= port_mask;
+                gpio_int_type2[port] |= port_mask;
+                desc->handle_irq = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                gpio_int_type1[port] |= port_mask;
+                gpio_int_type2[port] &= ~port_mask;
+                desc->handle_irq = handle_edge_irq;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                gpio_int_type1[port] &= ~port_mask;
+                gpio_int_type2[port] |= port_mask;
+                desc->handle_irq = handle_level_irq;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                gpio_int_type1[port] &= ~port_mask;
+                gpio_int_type2[port] &= ~port_mask;
+                desc->handle_irq = handle_level_irq;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                gpio_int_type1[port] |= port_mask;
+                /* set initial polarity based on current input level */
+                if (gpio_get_value(gpio))
+                        gpio_int_type2[port] &= ~port_mask; /* falling */
+                else
+                        gpio_int_type2[port] |= port_mask; /* rising */
+                desc->handle_irq = handle_edge_irq;
+                break;
+        default:
+                pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
+                return -EINVAL;
+        }
+
+        gpio_int_enabled[port] |= port_mask;
+
+        desc->status &= ~IRQ_TYPE_SENSE_MASK;
+        desc->status |= type & IRQ_TYPE_SENSE_MASK;
+
+        ep93xx_gpio_update_int_params(port);
+
+        return 0;
+}
+
+static struct irq_chip ep93xx_gpio_irq_chip = {
+        .name           = "GPIO",
+        .ack            = ep93xx_gpio_irq_ack,
+        .mask_ack       = ep93xx_gpio_irq_mask_ack,
+        .mask           = ep93xx_gpio_irq_mask,
+        .unmask         = ep93xx_gpio_irq_unmask,
+        .set_type       = ep93xx_gpio_irq_type,
+};
+
+void __init ep93xx_gpio_init_irq(void)
+{
+        int gpio_irq;
+
+        for (gpio_irq = gpio_to_irq(0);
+             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
+                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
+                set_irq_handler(gpio_irq, handle_level_irq);
+                set_irq_flags(gpio_irq, IRQF_VALID);
+        }
+
+        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+}
+
+
+/*************************************************************************
+ * gpiolib interface for EP93xx on-chip GPIOs
+ *************************************************************************/
 struct ep93xx_gpio_chip {
         struct gpio_chip        chip;
 
@@ -31,10 +262,6 @@ struct ep93xx_gpio_chip {
 
 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
 
-/* From core.c */
-extern void ep93xx_gpio_int_mask(unsigned line);
-extern void ep93xx_gpio_update_int_params(unsigned port);
-
 static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index d55194a4c093..93e2ecc79ceb 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -92,21 +92,6 @@
 
 /* APB peripherals */
 #define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
-#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
-#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
-#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
-#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
-#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
-#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
-#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
-#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
-#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
-#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
-#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
-#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
-#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
-#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
-#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
 
 #define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
 
@@ -167,8 +152,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
+#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
 #define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
index aed21cd3fe2d..1b3f25d03d39 100644
--- a/arch/arm/mach-ep93xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-ep93xx/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
new file mode 100644
index 000000000000..cd93990f1b99
--- /dev/null
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-ep93xx/simone.c
+ * Simplemachines Sim.One support.
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on the 2.6.24.7 support:
+ *   Copyright (C) 2009 Simplemachines
+ *   MMC support by Peter Ivanov <ivanovp@gmail.com>, 2007
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct physmap_flash_data simone_flash_data = {
+        .width          = 2,
+};
+
+static struct resource simone_flash_resource = {
+        .start          = EP93XX_CS6_PHYS_BASE,
+        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device simone_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = &simone_flash_resource,
+        .dev = {
+                .platform_data  = &simone_flash_data,
+        },
+};
+
+static struct ep93xx_eth_data simone_eth_data = {
+        .phy_id         = 1,
+};
+
+static struct ep93xxfb_mach_info simone_fb_info = {
+        .num_modes      = EP93XXFB_USE_MODEDB,
+        .bpp            = 16,
+        .flags          = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
+};
+
+static struct i2c_gpio_platform_data simone_i2c_gpio_data = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 0,
+        .timeout                = 0,
+};
+
+static struct i2c_board_info __initdata simone_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+        },
+};
+
+static void __init simone_init_machine(void)
+{
+        ep93xx_init_devices();
+
+        platform_device_register(&simone_flash);
+        ep93xx_register_eth(&simone_eth_data, 1);
+        ep93xx_register_fb(&simone_fb_info);
+        ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
+                            ARRAY_SIZE(simone_i2c_board_info));
+}
+
+MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
+/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = simone_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
new file mode 100644
index 000000000000..51134b0382ca
--- /dev/null
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-ep93xx/snappercl15.c
+ * Bluewater Systems Snapper CL15 system module
+ *
+ * Copyright (C) 2009 Bluewater Systems Ltd
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * NAND code adapted from driver by:
+ *   Andre Renaud <andre@bluewatersys.com>
+ *   James R. McKaskill
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/fb.h>
+
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
+#include <mach/hardware.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#define SNAPPERCL15_NAND_BASE   (EP93XX_CS7_PHYS_BASE + SZ_16M)
+
+#define SNAPPERCL15_NAND_WPN    (1 << 8)  /* Write protect (active low) */
+#define SNAPPERCL15_NAND_ALE    (1 << 9)  /* Address latch */
+#define SNAPPERCL15_NAND_CLE    (1 << 10) /* Command latch */
+#define SNAPPERCL15_NAND_CEN    (1 << 11) /* Chip enable (active low) */
+#define SNAPPERCL15_NAND_RDY    (1 << 14) /* Device ready */
+
+#define NAND_CTRL_ADDR(chip)    (chip->IO_ADDR_W + 0x40)
+
+static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                      unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+        static u16 nand_state = SNAPPERCL15_NAND_WPN;
+        u16 set;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN;
+
+                if (ctrl & NAND_NCE)
+                        set &= ~SNAPPERCL15_NAND_CEN;
+                if (ctrl & NAND_CLE)
+                        set |= SNAPPERCL15_NAND_CLE;
+                if (ctrl & NAND_ALE)
+                        set |= SNAPPERCL15_NAND_ALE;
+
+                nand_state &= ~(SNAPPERCL15_NAND_CEN |
+                                SNAPPERCL15_NAND_CLE |
+                                SNAPPERCL15_NAND_ALE);
+                nand_state |= set;
+                __raw_writew(nand_state, NAND_CTRL_ADDR(chip));
+        }
+
+        if (cmd != NAND_CMD_NONE)
+                __raw_writew((cmd & 0xff) | nand_state, chip->IO_ADDR_W);
+}
+
+static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
+}
+
+static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
+
+static struct mtd_partition snappercl15_nand_parts[] = {
+        {
+                .name           = "Kernel",
+                .offset         = 0,
+                .size           = SZ_2M,
+        },
+        {
+                .name           = "Filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct platform_nand_data snappercl15_nand_data = {
+        .chip = {
+                .nr_chips               = 1,
+                .part_probe_types       = snappercl15_nand_part_probes,
+                .partitions             = snappercl15_nand_parts,
+                .nr_partitions          = ARRAY_SIZE(snappercl15_nand_parts),
+                .options                = NAND_NO_AUTOINCR,
+                .chip_delay             = 25,
+        },
+        .ctrl = {
+                .dev_ready              = snappercl15_nand_dev_ready,
+                .cmd_ctrl               = snappercl15_nand_cmd_ctrl,
+        },
+};
+
+static struct resource snappercl15_nand_resource[] = {
+        {
+                .start          = SNAPPERCL15_NAND_BASE,
+                .end            = SNAPPERCL15_NAND_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device snappercl15_nand_device = {
+        .name                   = "gen_nand",
+        .id                     = -1,
+        .dev.platform_data      = &snappercl15_nand_data,
+        .resource               = snappercl15_nand_resource,
+        .num_resources          = ARRAY_SIZE(snappercl15_nand_resource),
+};
+
+static struct ep93xx_eth_data snappercl15_eth_data = {
+        .phy_id                 = 1,
+};
+
+static struct i2c_gpio_platform_data snappercl15_i2c_gpio_data = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 0,
+        .timeout                = 0,
+};
+
+static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
+        {
+                /* Audio codec */
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+static struct ep93xxfb_mach_info snappercl15_fb_info = {
+        .num_modes              = EP93XXFB_USE_MODEDB,
+        .bpp                    = 16,
+};
+
+static void __init snappercl15_init_machine(void)
+{
+        ep93xx_init_devices();
+        ep93xx_register_eth(&snappercl15_eth_data, 1);
+        ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
+                            ARRAY_SIZE(snappercl15_i2c_data));
+        ep93xx_register_fb(&snappercl15_fb_info);
+        platform_device_register(&snappercl15_nand_device);
+}
+
+MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
+        /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = snappercl15_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 41febc796b1c..e3bc3f6f6b10 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -32,12 +32,13 @@ unsigned int mem_fclk_21285 = 50000000;
 
 EXPORT_SYMBOL(mem_fclk_21285);
 
-static void __init early_fclk(char **arg)
+static int __init early_fclk(char *arg)
 {
-        mem_fclk_21285 = simple_strtoul(*arg, arg, 0);
+        mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
+        return 0;
 }
 
-__early_param("mem_fclk_21285=", early_fclk);
+early_param("mem_fclk_21285", early_fclk);
 
 static int __init parse_tag_memclk(const struct tag *tag)
 {
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index e7263854bc7b..fe3bd5ac8b10 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -86,7 +86,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
         unsigned int reg_both, reg_level, reg_type;
 
         reg_type = __raw_readl(base + GPIO_INT_TYPE);
-        reg_level = __raw_readl(base + GPIO_INT_BOTH_EDGE);
+        reg_level = __raw_readl(base + GPIO_INT_LEVEL);
         reg_both = __raw_readl(base + GPIO_INT_BOTH_EDGE);
 
         switch (type) {
@@ -117,7 +117,7 @@ static int gpio_set_irq_type(unsigned int irq, unsigned int type)
         }
 
         __raw_writel(reg_type, base + GPIO_INT_TYPE);
-        __raw_writel(reg_level, base + GPIO_INT_BOTH_EDGE);
+        __raw_writel(reg_level, base + GPIO_INT_LEVEL);
         __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
 
         gpio_ack_irq(irq);
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h
index 83e536d9436c..45371eb86fcb 100644
--- a/arch/arm/mach-gemini/include/mach/vmalloc.h
+++ b/arch/arm/mach-gemini/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * (at your option) any later version.
  */
 
-#define VMALLOC_END     0xF0000000
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index a0f60e55da6a..8b390e36ba69 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -144,8 +144,7 @@ static int __init integrator_init(void)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 3f35293d457a..66ef86d6d9e3 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -558,9 +558,7 @@ static void __init intcp_init(void)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(cp_lookups); i++)
-                clkdev_add(&cp_lookups[i]);
-
+        clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 529580997814..48642e66c566 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -61,9 +61,9 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                                  (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                 break;
         case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
-                retval = __arm_ioremap(IOP13XX_PBI_LOWER_MEM_PA +
+                retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA +
                                        (cookie - IOP13XX_PBI_LOWER_MEM_RA),
-                                       size, mtype);
+                                       size, mtype, __builtin_return_address(0));
                 break;
         case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
                 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
@@ -75,7 +75,8 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
-                retval = __arm_ioremap(cookie, size, mtype);
+                retval = __arm_ioremap_caller(cookie, size, mtype,
+                                __builtin_return_address(0));
         }
 
         return retval;
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
index 85ceb09d85f0..c4862d48e583 100644
--- a/arch/arm/mach-iop32x/include/mach/vmalloc.h
+++ b/arch/arm/mach-iop32x/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-iop32x/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
index f9f99dea9bc4..48331dc23704 100644
--- a/arch/arm/mach-iop33x/include/mach/vmalloc.h
+++ b/arch/arm/mach-iop33x/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-iop33x/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
index d195e35aed3b..61c8dae24f95 100644
--- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h
+++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
-#define VMALLOC_END         0xfb000000
+#define VMALLOC_END         0xfb000000UL
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
index dd519f678d10..896c56a1c00e 100644
--- a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * specific static I/O.
  */
 
-#define VMALLOC_END     (0xec000000)
+#define VMALLOC_END     (0xec000000UL)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 3bbf40f6d964..71728d36d501 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -427,6 +427,17 @@ static void __init ixp4xx_clocksource_init(void)
 }
 
 /*
+ * sched_clock()
+ */
+unsigned long long sched_clock(void)
+{
+        cycle_t cyc = ixp4xx_get_cycles(NULL);
+        struct clocksource *cs = &clocksource_ixp4xx;
+
+        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+}
+
+/*
  * clockevents
  */
 static int ixp4xx_set_next_event(unsigned long evt,
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
index 7b3580b53adf..9bcd64d59854 100644
--- a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
@@ -1,5 +1,5 @@
 /*
  * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (0xFF000000)
+#define VMALLOC_END       (0xff000000UL)
 
diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
index 8f48260dcdad..bf162ca3d2c1 100644
--- a/arch/arm/mach-kirkwood/include/mach/vmalloc.h
+++ b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-kirkwood/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
index 3fbd49490bb9..d62da7358b16 100644
--- a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
+++ b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  *  version 2 as published by the Free Software Foundation.
  *
  */
-#define VMALLOC_END       (0xe8000000)
+#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-loki/include/mach/vmalloc.h b/arch/arm/mach-loki/include/mach/vmalloc.h
index 8dc3bfcbf9f0..5dcbd865443f 100644
--- a/arch/arm/mach-loki/include/mach/vmalloc.h
+++ b/arch/arm/mach-loki/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-loki/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 2a46ed5cc2a2..886e05648f08 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -88,11 +88,3 @@ unsigned long clk_get_rate(struct clk *clk)
         return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index eefffbe683b0..016ae94691c0 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -68,5 +68,3 @@ struct clk clk_##_name = {					\
 
 extern struct clk clk_pxa168_gpio;
 extern struct clk clk_pxa168_timers;
-
-extern void clks_register(struct clk_lookup *, size_t);
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
index b60ccaf9fee7..1d0bac003ad0 100644
--- a/arch/arm/mach-mmp/include/mach/vmalloc.h
+++ b/arch/arm/mach-mmp/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 37dbdde17fac..1873c821df90 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -94,7 +94,7 @@ static int __init pxa168_init(void)
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa168_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
-                clks_register(ARRAY_AND_SIZE(pxa168_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index d4049508a4df..46f2d69bef3c 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -131,7 +131,7 @@ static int __init pxa910_init(void)
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa910_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
-                clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 1c5e7dac086f..05f96b780aa6 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -76,5 +76,6 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
                         mtype = MT_DEVICE_NONSHARED;
         }
 
-        return __arm_ioremap(phys_addr, size, mtype);
+        return __arm_ioremap_caller(phys_addr, size, mtype,
+                __builtin_return_address(0));
 }
diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
index 1c4954386a84..ba26fe98e640 100644
--- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
+++ b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index d1b588519ad2..6cf2d4a7511d 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -570,7 +570,6 @@ static struct clk_lookup lookups[] __initdata = {
 int __init mx1_clocks_init(unsigned long fref)
 {
         unsigned int reg;
-        int i;
 
         /* disable clocks we are able to */
         __raw_writel(0, SCM_GCCR);
@@ -592,8 +591,7 @@ int __init mx1_clocks_init(unsigned long fref)
         reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
         clko_clk.parent = (struct clk *)clko_clocks[reg];
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         clk_enable(&hclk);
         clk_enable(&fclk);
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 91901b5d56c2..e82b489d1215 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -968,7 +968,6 @@ static struct clk_lookup lookups[] = {
  */
 int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
-        int i;
         u32 cscr;
 
         external_low_reference = lref;
@@ -986,8 +985,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
         else
                 spll_clk.parent = &fpm_clk;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clock gates */
         __raw_writel(0, CCM_PCCR0);
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index b010bf9ceaab..18c53a6487fa 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -719,7 +719,6 @@ static void __init to2_adjust_clocks(void)
 int __init mx27_clocks_init(unsigned long fref)
 {
         u32 cscr = __raw_readl(CCM_CSCR);
-        int i;
 
         external_high_reference = fref;
 
@@ -736,8 +735,7 @@ int __init mx27_clocks_init(unsigned long fref)
 
         to2_adjust_clocks();
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clocks we do not need */
         __raw_writel(0, CCM_PCCR0);
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 6acc88bcdc40..37e1359ad0c0 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -218,10 +218,7 @@ static struct clk_lookup lookups[] = {
 
 int __init mx25_clocks_init(void)
 {
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clocks except the ones we need to survive, namely:
          * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 7584b4c6c556..f3f41fa4f21b 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -485,15 +485,13 @@ static struct clk_lookup lookups[] = {
 
 int __init mx35_clocks_init()
 {
-        int i;
         unsigned int ll = 0;
 
 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
         ll = (3 << 16);
 #endif
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clocks except the ones we need to survive, namely:
          * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 27a318af0d20..b5c39a016db7 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -578,12 +578,10 @@ static struct clk_lookup lookups[] = {
 int __init mx31_clocks_init(unsigned long fref)
 {
         u32 reg;
-        int i;
 
         ckih_rate = fref;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* change the csi_clk parent if necessary */
         reg = __raw_readl(MXC_CCM_CCMR);
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
index ecfa37fef8ad..5c85075d8a56 100644
--- a/arch/arm/mach-mxc91231/clock.c
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -624,7 +624,6 @@ static struct clk_lookup lookups[] = {
 int __init mxc91231_clocks_init(unsigned long fref)
 {
         void __iomem *gpt_base;
-        int i;
 
         ckih_rate = fref;
 
@@ -632,8 +631,7 @@ int __init mxc91231_clocks_init(unsigned long fref)
         sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
         sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
         mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index f93c59634191..9bf33b30a025 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -86,11 +86,19 @@ static struct amba_device cpu8815_amba_gpio[] = {
         },
 };
 
+static struct amba_device cpu8815_amba_rng = {
+        .dev = {
+                .init_name = "rng",
+        },
+        __MEM_4K_RESOURCE(NOMADIK_RNG_BASE),
+};
+
 static struct amba_device *amba_devs[] __initdata = {
         cpu8815_amba_gpio + 0,
         cpu8815_amba_gpio + 1,
         cpu8815_amba_gpio + 2,
         cpu8815_amba_gpio + 3,
+        &cpu8815_amba_rng
 };
 
 static int __init cpu8815_init(void)
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
index be12e31ea528..f83d574d9445 100644
--- a/arch/arm/mach-nomadik/include/mach/vmalloc.h
+++ b/arch/arm/mach-nomadik/include/mach/vmalloc.h
@@ -1,2 +1,2 @@
 
-#define VMALLOC_END       0xe8000000
+#define VMALLOC_END       0xe8000000UL
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
index fe964d3bcc47..c8651974c4b0 100644
--- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
@@ -11,6 +11,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END     (0xf0000000)
+#define VMALLOC_END     (0xf0000000UL)
 
 #endif /* ifndef __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-nuc93x/Kconfig b/arch/arm/mach-nuc93x/Kconfig
new file mode 100644
index 000000000000..2bc40a280fad
--- /dev/null
+++ b/arch/arm/mach-nuc93x/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_NUC93X
+
+config CPU_NUC932
+        bool
+        help
+          Support for NUC932 of Nuvoton NUC93X CPUs.
+
+menu "NUC932 Machines"
+
+config MACH_NUC932EVB
+        bool "Nuvoton NUC932 Evaluation Board"
+        default y
+        select CPU_NUC932
+        help
+           Say Y here if you are using the Nuvoton NUC932EVB
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-nuc93x/Makefile b/arch/arm/mach-nuc93x/Makefile
new file mode 100644
index 000000000000..440e2dec6c8a
--- /dev/null
+++ b/arch/arm/mach-nuc93x/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y                           := irq.o time.o dev.o cpu.o clock.o
+# NUC932 CPU support files
+
+obj-$(CONFIG_CPU_NUC932)        += nuc932.o
+
+# machine support
+
+obj-$(CONFIG_MACH_NUC932EVB)    += mach-nuc932evb.o
diff --git a/arch/arm/mach-nuc93x/Makefile.boot b/arch/arm/mach-nuc93x/Makefile.boot
new file mode 100644
index 000000000000..a057b546b6e5
--- /dev/null
+++ b/arch/arm/mach-nuc93x/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y      := 0x00008000
+params_phys-y   := 0x00000100
+
diff --git a/arch/arm/mach-nuc93x/clock.c b/arch/arm/mach-nuc93x/clock.c
new file mode 100644
index 000000000000..0521efbc48c9
--- /dev/null
+++ b/arch/arm/mach-nuc93x/clock.c
@@ -0,0 +1,83 @@
+/*
+ * linux/arch/arm/mach-nuc93x/clock.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#include "clock.h"
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (clk->enabled++ == 0)
+                (clk->enable)(clk, 1);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        WARN_ON(clk->enabled == 0);
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (--clk->enabled == 0)
+                (clk->enable)(clk, 0);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 27000000;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void nuc93x_clk_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->cken;
+        unsigned long clken;
+
+        clken = __raw_readl(NUC93X_VA_CLKPWR);
+
+        if (enable)
+                clken |= clocks;
+        else
+                clken &= ~clocks;
+
+        __raw_writel(clken, NUC93X_VA_CLKPWR);
+}
+
+void clks_register(struct clk_lookup *clks, size_t num)
+{
+        int i;
+
+        for (i = 0; i < num; i++)
+                clkdev_add(&clks[i]);
+}
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h
new file mode 100644
index 000000000000..18e51be4816f
--- /dev/null
+++ b/arch/arm/mach-nuc93x/clock.h
@@ -0,0 +1,36 @@
+/*
+ * linux/arch/arm/mach-nuc93x/clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <asm/clkdev.h>
+
+void nuc93x_clk_enable(struct clk *clk, int enable);
+void clks_register(struct clk_lookup *clks, size_t num);
+
+struct clk {
+        unsigned long           cken;
+        unsigned int            enabled;
+        void                    (*enable)(struct clk *, int enable);
+};
+
+#define DEFINE_CLK(_name, _ctrlbit)                     \
+struct clk clk_##_name = {                              \
+                .enable = nuc93x_clk_enable,            \
+                .cken   = (1 << _ctrlbit),              \
+        }
+
+#define DEF_CLKLOOK(_clk, _devname, _conname)           \
+        {                                               \
+                .clk            = _clk,                 \
+                .dev_id         = _devname,             \
+                .con_id         = _conname,             \
+        }
+
diff --git a/arch/arm/mach-nuc93x/cpu.c b/arch/arm/mach-nuc93x/cpu.c
new file mode 100644
index 000000000000..f6ff5d87354c
--- /dev/null
+++ b/arch/arm/mach-nuc93x/cpu.c
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/mach-nuc93x/cpu.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC93x series cpu common support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-ebi.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* Initial IO mappings */
+
+static struct map_desc nuc93x_iodesc[] __initdata = {
+        IODESC_ENT(IRQ),
+        IODESC_ENT(GCR),
+        IODESC_ENT(UART),
+        IODESC_ENT(TIMER),
+        IODESC_ENT(EBI),
+};
+
+/* Initial nuc932 clock declarations. */
+static DEFINE_CLK(audio, 2);
+static DEFINE_CLK(sd, 3);
+static DEFINE_CLK(jpg, 4);
+static DEFINE_CLK(video, 5);
+static DEFINE_CLK(vpost, 6);
+static DEFINE_CLK(2d, 7);
+static DEFINE_CLK(gpu, 8);
+static DEFINE_CLK(gdma, 9);
+static DEFINE_CLK(adc, 10);
+static DEFINE_CLK(uart, 11);
+static DEFINE_CLK(spi, 12);
+static DEFINE_CLK(pwm, 13);
+static DEFINE_CLK(timer, 14);
+static DEFINE_CLK(wdt, 15);
+static DEFINE_CLK(ac97, 16);
+static DEFINE_CLK(i2s, 16);
+static DEFINE_CLK(usbck, 17);
+static DEFINE_CLK(usb48, 18);
+static DEFINE_CLK(usbh, 19);
+static DEFINE_CLK(i2c, 20);
+static DEFINE_CLK(ext, 0);
+
+static struct clk_lookup nuc932_clkregs[] = {
+       DEF_CLKLOOK(&clk_audio, "nuc932-audio", NULL),
+       DEF_CLKLOOK(&clk_sd, "nuc932-sd", NULL),
+       DEF_CLKLOOK(&clk_jpg, "nuc932-jpg", "NULL"),
+       DEF_CLKLOOK(&clk_video, "nuc932-video", "NULL"),
+       DEF_CLKLOOK(&clk_vpost, "nuc932-vpost", NULL),
+       DEF_CLKLOOK(&clk_2d, "nuc932-2d", NULL),
+       DEF_CLKLOOK(&clk_gpu, "nuc932-gpu", NULL),
+       DEF_CLKLOOK(&clk_gdma, "nuc932-gdma", "NULL"),
+       DEF_CLKLOOK(&clk_adc, "nuc932-adc", NULL),
+       DEF_CLKLOOK(&clk_uart, NULL, "uart"),
+       DEF_CLKLOOK(&clk_spi, "nuc932-spi", NULL),
+       DEF_CLKLOOK(&clk_pwm, "nuc932-pwm", NULL),
+       DEF_CLKLOOK(&clk_timer, NULL, "timer"),
+       DEF_CLKLOOK(&clk_wdt, "nuc932-wdt", NULL),
+       DEF_CLKLOOK(&clk_ac97, "nuc932-ac97", NULL),
+       DEF_CLKLOOK(&clk_i2s, "nuc932-i2s", NULL),
+       DEF_CLKLOOK(&clk_usbck, "nuc932-usbck", NULL),
+       DEF_CLKLOOK(&clk_usb48, "nuc932-usb48", NULL),
+       DEF_CLKLOOK(&clk_usbh, "nuc932-usbh", NULL),
+       DEF_CLKLOOK(&clk_i2c, "nuc932-i2c", NULL),
+       DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+};
+
+/* Initial serial platform data */
+
+struct plat_serial8250_port nuc93x_uart_data[] = {
+        NUC93X_8250PORT(UART0),
+        {},
+};
+
+struct platform_device nuc93x_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = nuc93x_uart_data,
+        },
+};
+
+/*Init NUC93x evb io*/
+
+void __init nuc93x_map_io(struct map_desc *mach_desc, int mach_size)
+{
+        unsigned long idcode = 0x0;
+
+        iotable_init(mach_desc, mach_size);
+        iotable_init(nuc93x_iodesc, ARRAY_SIZE(nuc93x_iodesc));
+
+        idcode = __raw_readl(NUC93XPDID);
+        if (idcode == NUC932_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
+        else
+                printk(KERN_ERR "CPU type detect error!\n");
+
+}
+
+/*Init NUC93x clock*/
+
+void __init nuc93x_init_clocks(void)
+{
+        clks_register(nuc932_clkregs, ARRAY_SIZE(nuc932_clkregs));
+}
+
diff --git a/arch/arm/mach-nuc93x/cpu.h b/arch/arm/mach-nuc93x/cpu.h
new file mode 100644
index 000000000000..9def28197bc9
--- /dev/null
+++ b/arch/arm/mach-nuc93x/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-nuc93x/cpu.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Header file for NUC93X CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define IODESC_ENT(y)                                   \
+{                                                       \
+        .virtual = (unsigned long)NUC93X_VA_##y,        \
+        .pfn     = __phys_to_pfn(NUC93X_PA_##y),        \
+        .length  = NUC93X_SZ_##y,                       \
+        .type    = MT_DEVICE,                           \
+}
+
+#define NUC93X_8250PORT(name)                                   \
+{                                                               \
+        .membase        = name##_BA,                            \
+        .mapbase        = name##_PA,                            \
+        .irq            = IRQ_##name,                           \
+        .uartclk        = 57139200,                             \
+        .regshift       = 2,                                    \
+        .iotype         = UPIO_MEM,                             \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+}
+
+/*Cpu identifier register*/
+
+#define NUC93XPDID      NUC93X_VA_GCR
+#define NUC932_CPUID    0x29550091
+
+/* extern file from cpu.c */
+
+extern void nuc93x_clock_source(struct device *dev, unsigned char *src);
+extern void nuc93x_init_clocks(void);
+extern void nuc93x_map_io(struct map_desc *mach_desc, int mach_size);
+extern void nuc93x_board_init(struct platform_device **device, int size);
+extern struct platform_device nuc93x_serial_device;
+
diff --git a/arch/arm/mach-nuc93x/dev.c b/arch/arm/mach-nuc93x/dev.c
new file mode 100644
index 000000000000..a962ae9578d6
--- /dev/null
+++ b/arch/arm/mach-nuc93x/dev.c
@@ -0,0 +1,42 @@
+/*
+ * linux/arch/arm/mach-nuc93x/dev.c
+ *
+ * Copyright (C) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+
+#include "cpu.h"
+
+/*Here should be your evb resourse,such as LCD*/
+
+static struct platform_device *nuc93x_public_dev[] __initdata = {
+        &nuc93x_serial_device,
+};
+
+/* Provide adding specific CPU platform devices API */
+
+void __init nuc93x_board_init(struct platform_device **device, int size)
+{
+        platform_add_devices(device, size);
+        platform_add_devices(nuc93x_public_dev, ARRAY_SIZE(nuc93x_public_dev));
+}
+
diff --git a/arch/arm/mach-nuc93x/include/mach/clkdev.h b/arch/arm/mach-nuc93x/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/entry-macro.S b/arch/arm/mach-nuc93x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1352cbda3797
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/entry-macro.S
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ */
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                mov     \base, #AIC_BA
+
+                ldr     \irqnr, [ \base, #AIC_IPER]
+                ldr     \irqnr, [ \base, #AIC_ISNR]
+                cmp     \irqnr, #0
+
+        .endm
+
+        /* currently don't need an disable_fiq macro */
+
+        .macro  disable_fiq
+        .endm
diff --git a/arch/arm/mach-nuc93x/include/mach/hardware.h b/arch/arm/mach-nuc93x/include/mach/hardware.h
new file mode 100644
index 000000000000..fb5c6fcb142e
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/hardware.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
new file mode 100644
index 000000000000..72e5051c7534
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/io.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/io.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+
+#define __mem_pci(a)    (a)
+#define __io(a)         __typesafe_io(a)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/irqs.h b/arch/arm/mach-nuc93x/include/mach/irqs.h
new file mode 100644
index 000000000000..7c4aa71edb44
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/irqs.h
@@ -0,0 +1,59 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/irqs.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define NUC93X_IRQ(x)   (x)
+
+/* Main cpu interrupts */
+
+#define IRQ_WDT         NUC93X_IRQ(1)
+#define IRQ_IRQ0        NUC93X_IRQ(2)
+#define IRQ_IRQ1        NUC93X_IRQ(3)
+#define IRQ_IRQ2        NUC93X_IRQ(4)
+#define IRQ_IRQ3        NUC93X_IRQ(5)
+#define IRQ_USBH        NUC93X_IRQ(6)
+#define IRQ_APU         NUC93X_IRQ(7)
+#define IRQ_VPOST       NUC93X_IRQ(8)
+#define IRQ_ADC         NUC93X_IRQ(9)
+#define IRQ_UART0       NUC93X_IRQ(10)
+#define IRQ_TIMER0      NUC93X_IRQ(11)
+#define IRQ_GPU0        NUC93X_IRQ(12)
+#define IRQ_GPU1        NUC93X_IRQ(13)
+#define IRQ_GPU2        NUC93X_IRQ(14)
+#define IRQ_GPU3        NUC93X_IRQ(15)
+#define IRQ_GPU4        NUC93X_IRQ(16)
+#define IRQ_VIN         NUC93X_IRQ(17)
+#define IRQ_USBD        NUC93X_IRQ(18)
+#define IRQ_VRAMLD      NUC93X_IRQ(19)
+#define IRQ_GDMA0       NUC93X_IRQ(20)
+#define IRQ_GDMA1       NUC93X_IRQ(21)
+#define IRQ_SDIO        NUC93X_IRQ(22)
+#define IRQ_FMI         NUC93X_IRQ(22)
+#define IRQ_JPEG        NUC93X_IRQ(23)
+#define IRQ_SPI0        NUC93X_IRQ(24)
+#define IRQ_SPI1        NUC93X_IRQ(25)
+#define IRQ_RTC         NUC93X_IRQ(26)
+#define IRQ_PWM0        NUC93X_IRQ(27)
+#define IRQ_PWM1        NUC93X_IRQ(28)
+#define IRQ_PWM2        NUC93X_IRQ(29)
+#define IRQ_PWM3        NUC93X_IRQ(30)
+#define IRQ_I2SAC97     NUC93X_IRQ(31)
+#define IRQ_CAP0        IRQ_PWM0
+#define IRQ_CAP1        IRQ_PWM1
+#define IRQ_CAP2        IRQ_PWM2
+#define IRQ_CAP3        IRQ_PWM3
+#define NR_IRQS         (IRQ_I2SAC97 + 1)
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/map.h b/arch/arm/mach-nuc93x/include/mach/map.h
new file mode 100644
index 000000000000..fd0b5e89f0e7
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/map.h
@@ -0,0 +1,139 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/map.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+#define MAP_OFFSET      (0xfff00000)
+#define CLK_OFFSET      (0x10)
+
+#ifndef __ASSEMBLY__
+#define NUC93X_ADDR(x)  ((void __iomem *)(0xF0000000 + ((x)&(~MAP_OFFSET))))
+#else
+#define NUC93X_ADDR(x)  (0xF0000000 + ((x)&(~MAP_OFFSET)))
+#endif
+
+ /*
+  * nuc932 hardware register definition
+  */
+
+#define NUC93X_PA_IRQ           (0xFFF83000)
+#define NUC93X_PA_GCR           (0xFFF00000)
+#define NUC93X_PA_EBI           (0xFFF01000)
+#define NUC93X_PA_UART          (0xFFF80000)
+#define NUC93X_PA_TIMER         (0xFFF81000)
+#define NUC93X_PA_GPIO          (0xFFF84000)
+#define NUC93X_PA_GDMA          (0xFFF03000)
+#define NUC93X_PA_USBHOST       (0xFFF0d000)
+#define NUC93X_PA_I2C           (0xFFF89000)
+#define NUC93X_PA_LCD           (0xFFF06000)
+#define NUC93X_PA_GE            (0xFFF05000)
+#define NUC93X_PA_ADC           (0xFFF85000)
+#define NUC93X_PA_RTC           (0xFFF87000)
+#define NUC93X_PA_PWM           (0xFFF82000)
+#define NUC93X_PA_ACTL          (0xFFF0a000)
+#define NUC93X_PA_USBDEV        (0xFFF0C000)
+#define NUC93X_PA_JEPEG         (0xFFF0e000)
+#define NUC93X_PA_CACHE_T       (0xFFF60000)
+#define NUC93X_PA_VRAM          (0xFFF0b000)
+#define NUC93X_PA_DMAC          (0xFFF09000)
+#define NUC93X_PA_I2SM          (0xFFF08000)
+#define NUC93X_PA_CACHE         (0xFFF02000)
+#define NUC93X_PA_GPU           (0xFFF04000)
+#define NUC93X_PA_VIDEOIN       (0xFFF07000)
+#define NUC93X_PA_SPI0          (0xFFF86000)
+#define NUC93X_PA_SPI1          (0xFFF88000)
+
+ /*
+  * nuc932 virtual address mapping.
+  * interrupt controller is the first thing we put in, to make
+  * the assembly code for the irq detection easier
+  */
+
+#define NUC93X_VA_IRQ           NUC93X_ADDR(0x00000000)
+#define NUC93X_SZ_IRQ           SZ_4K
+
+#define NUC93X_VA_GCR           NUC93X_ADDR(NUC93X_PA_IRQ)
+#define NUC93X_VA_CLKPWR        (NUC93X_VA_GCR+CLK_OFFSET)
+#define NUC93X_SZ_GCR           SZ_4K
+
+/* EBI management */
+
+#define NUC93X_VA_EBI           NUC93X_ADDR(NUC93X_PA_EBI)
+#define NUC93X_SZ_EBI           SZ_4K
+
+/* UARTs */
+
+#define NUC93X_VA_UART          NUC93X_ADDR(NUC93X_PA_UART)
+#define NUC93X_SZ_UART          SZ_4K
+
+/* Timers */
+
+#define NUC93X_VA_TIMER NUC93X_ADDR(NUC93X_PA_TIMER)
+#define NUC93X_SZ_TIMER SZ_4K
+
+/* GPIO ports */
+
+#define NUC93X_VA_GPIO          NUC93X_ADDR(NUC93X_PA_GPIO)
+#define NUC93X_SZ_GPIO          SZ_4K
+
+/* GDMA control */
+
+#define NUC93X_VA_GDMA          NUC93X_ADDR(NUC93X_PA_GDMA)
+#define NUC93X_SZ_GDMA          SZ_4K
+
+/* I2C hardware controller */
+
+#define NUC93X_VA_I2C           NUC93X_ADDR(NUC93X_PA_I2C)
+#define NUC93X_SZ_I2C           SZ_4K
+
+/* LCD controller*/
+
+#define NUC93X_VA_LCD           NUC93X_ADDR(NUC93X_PA_LCD)
+#define NUC93X_SZ_LCD           SZ_4K
+
+/* 2D controller*/
+
+#define NUC93X_VA_GE            NUC93X_ADDR(NUC93X_PA_GE)
+#define NUC93X_SZ_GE            SZ_4K
+
+/* ADC */
+
+#define NUC93X_VA_ADC           NUC93X_ADDR(NUC93X_PA_ADC)
+#define NUC93X_SZ_ADC           SZ_4K
+
+/* RTC */
+
+#define NUC93X_VA_RTC           NUC93X_ADDR(NUC93X_PA_RTC)
+#define NUC93X_SZ_RTC           SZ_4K
+
+/* Pulse Width Modulation(PWM) Registers */
+
+#define NUC93X_VA_PWM           NUC93X_ADDR(NUC93X_PA_PWM)
+#define NUC93X_SZ_PWM           SZ_4K
+
+/* Audio Controller controller */
+
+#define NUC93X_VA_ACTL          NUC93X_ADDR(NUC93X_PA_ACTL)
+#define NUC93X_SZ_ACTL          SZ_4K
+
+/* USB Device port */
+
+#define NUC93X_VA_USBDEV        NUC93X_ADDR(NUC93X_PA_USBDEV)
+#define NUC93X_SZ_USBDEV        SZ_4K
+
+/* USB host controller*/
+#define NUC93X_VA_USBHOST       NUC93X_ADDR(NUC93X_PA_USBHOST)
+#define NUC93X_SZ_USBHOST       SZ_4K
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h
new file mode 100644
index 000000000000..323ab0db3f7d
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/memory.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/memory.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-clock.h b/arch/arm/mach-nuc93x/include/mach/regs-clock.h
new file mode 100644
index 000000000000..5cb2954fbec2
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-clock.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H
+
+/* Clock Control Registers  */
+#define CLK_BA          NUC93X_VA_CLKPWR
+#define REG_CLKEN       (CLK_BA + 0x00)
+#define REG_CLKSEL      (CLK_BA + 0x04)
+#define REG_CLKDIV      (CLK_BA + 0x08)
+#define REG_PLLCON0     (CLK_BA + 0x0C)
+#define REG_PLLCON1     (CLK_BA + 0x10)
+#define REG_PMCON       (CLK_BA + 0x14)
+#define REG_IRQWAKECON  (CLK_BA + 0x18)
+#define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
+#define REG_IPSRST      (CLK_BA + 0x20)
+#define REG_CLKEN1      (CLK_BA + 0x24)
+#define REG_CLKDIV1     (CLK_BA + 0x28)
+
+/* Define PLL freq setting */
+#define PLL_DISABLE             0x12B63
+#define PLL_66MHZ               0x2B63
+#define PLL_100MHZ              0x4F64
+#define PLL_120MHZ              0x4F63
+#define PLL_166MHZ              0x4124
+#define PLL_200MHZ              0x4F24
+
+/* Define AHB:CPUFREQ ratio */
+#define AHB_CPUCLK_1_1          0x00
+#define AHB_CPUCLK_1_2          0x01
+#define AHB_CPUCLK_1_4          0x02
+#define AHB_CPUCLK_1_8          0x03
+
+/* Define APB:AHB ratio */
+#define APB_AHB_1_2             0x01
+#define APB_AHB_1_4             0x02
+#define APB_AHB_1_8             0x03
+
+/* Define clock skew */
+#define DEFAULTSKEW             0x48
+
+#endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
new file mode 100644
index 000000000000..3c72550e28e4
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-ebi.h
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_EBI_H
+#define __ASM_ARCH_REGS_EBI_H
+
+/* EBI Control Registers */
+
+#define EBI_BA          NUC93X_VA_EBI
+#define REG_EBICON      (EBI_BA + 0x00)
+#define REG_ROMCON      (EBI_BA + 0x04)
+#define REG_SDCONF0     (EBI_BA + 0x08)
+#define REG_SDCONF1     (EBI_BA + 0x0C)
+#define REG_SDTIME0     (EBI_BA + 0x10)
+#define REG_SDTIME1     (EBI_BA + 0x14)
+#define REG_EXT0CON     (EBI_BA + 0x18)
+#define REG_EXT1CON     (EBI_BA + 0x1C)
+#define REG_EXT2CON     (EBI_BA + 0x20)
+#define REG_EXT3CON     (EBI_BA + 0x24)
+#define REG_EXT4CON     (EBI_BA + 0x28)
+#define REG_CKSKEW      (EBI_BA + 0x2C)
+
+#endif /*  __ASM_ARCH_REGS_EBI_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h
new file mode 100644
index 000000000000..23021592de51
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-irq.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef ___ASM_ARCH_REGS_IRQ_H
+#define ___ASM_ARCH_REGS_IRQ_H
+
+/* Advance Interrupt Controller (AIC) Registers */
+
+#define AIC_BA                  NUC93X_VA_IRQ
+
+#define REG_AIC_IRQSC           (AIC_BA+0x80)
+#define REG_AIC_GEN             (AIC_BA+0x84)
+#define REG_AIC_GASR            (AIC_BA+0x88)
+#define REG_AIC_GSCR            (AIC_BA+0x8C)
+#define REG_AIC_IRSR            (AIC_BA+0x100)
+#define REG_AIC_IASR            (AIC_BA+0x104)
+#define REG_AIC_ISR             (AIC_BA+0x108)
+#define REG_AIC_IPER            (AIC_BA+0x10C)
+#define REG_AIC_ISNR            (AIC_BA+0x110)
+#define REG_AIC_IMR             (AIC_BA+0x114)
+#define REG_AIC_OISR            (AIC_BA+0x118)
+#define REG_AIC_MECR            (AIC_BA+0x120)
+#define REG_AIC_MDCR            (AIC_BA+0x124)
+#define REG_AIC_SSCR            (AIC_BA+0x128)
+#define REG_AIC_SCCR            (AIC_BA+0x12C)
+#define REG_AIC_EOSCR           (AIC_BA+0x130)
+#define AIC_IPER                (0x10C)
+#define AIC_ISNR                (0x110)
+
+#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-serial.h b/arch/arm/mach-nuc93x/include/mach/regs-serial.h
new file mode 100644
index 000000000000..767a047a8bc2
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-serial.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-serial.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define UART0_BA        NUC93X_VA_UART
+#define UART1_BA        (NUC93X_VA_UART+0x100)
+
+#define UART0_PA        NUC93X_PA_UART
+#define UART1_PA        (NUC93X_PA_UART+0x100)
+
+
+#ifndef __ASSEMBLY__
+
+struct nuc93x_uart_clksrc {
+        const char      *name;
+        unsigned int    divisor;
+        unsigned int    min_baud;
+        unsigned int    max_baud;
+};
+
+struct nuc93x_uartcfg {
+        unsigned char   hwport;
+        unsigned char   unused;
+        unsigned short  flags;
+        unsigned long   uart_flags;
+
+        unsigned long   ucon;
+        unsigned long   ulcon;
+        unsigned long   ufcon;
+
+        struct nuc93x_uart_clksrc *clocks;
+        unsigned int    clocks_size;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-timer.h b/arch/arm/mach-nuc93x/include/mach/regs-timer.h
new file mode 100644
index 000000000000..394be9614d36
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-timer.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-timer.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H
+
+/* Timer Registers */
+
+#define TMR_BA                  NUC93X_VA_TIMER
+#define REG_TCSR0               (TMR_BA+0x00)
+#define REG_TICR0               (TMR_BA+0x08)
+#define REG_TDR0                (TMR_BA+0x10)
+#define REG_TISR                (TMR_BA+0x18)
+#define REG_WTCR                (TMR_BA+0x1C)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/system.h b/arch/arm/mach-nuc93x/include/mach/system.h
new file mode 100644
index 000000000000..d26bd9a52844
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/system.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/machnuc93x/include/mach/system.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <asm/proc-fns.h>
+
+static void arch_idle(void)
+{
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+        cpu_reset(0);
+}
+
diff --git a/arch/arm/mach-nuc93x/include/mach/timex.h b/arch/arm/mach-nuc93x/include/mach/timex.h
new file mode 100644
index 000000000000..0c719cc91aa9
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/timex.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/timex.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE Now, I don't use it. */
+
+#define CLOCK_TICK_RATE 27000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
new file mode 100644
index 000000000000..73082cd61e84
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/uncompress.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+/* Defines for UART registers */
+
+#include <mach/regs-serial.h>
+#include <mach/map.h>
+#include <linux/serial_reg.h>
+
+#define arch_decomp_wdog()
+
+#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
+static u32 * uart_base = (u32 *)UART0_PA;
+
+static void putc(int ch)
+{
+        /* Check THRE and TEMT bits before we transmit the character.
+         */
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+
+        *uart_base = ch;
+}
+
+static inline void flush(void)
+{
+}
+
+static void arch_decomp_setup(void)
+{
+}
+
+#endif/* __ASM_NUC93X_UNCOMPRESS_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..98a21b81dec0
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END       (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
new file mode 100644
index 000000000000..a7a88ea4ec31
--- /dev/null
+++ b/arch/arm/mach-nuc93x/irq.c
@@ -0,0 +1,66 @@
+/*
+ * linux/arch/arm/mach-nuc93x/irq.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+static void nuc93x_irq_mask(unsigned int irq)
+{
+        __raw_writel(1 << irq, REG_AIC_MDCR);
+}
+
+/*
+ * By the w90p910 spec,any irq,only write 1
+ * to REG_AIC_EOSCR for ACK
+ */
+
+static void nuc93x_irq_ack(unsigned int irq)
+{
+        __raw_writel(0x01, REG_AIC_EOSCR);
+}
+
+static void nuc93x_irq_unmask(unsigned int irq)
+{
+        __raw_writel(1 << irq, REG_AIC_MECR);
+
+}
+
+static struct irq_chip nuc93x_irq_chip = {
+        .ack       = nuc93x_irq_ack,
+        .mask      = nuc93x_irq_mask,
+        .unmask    = nuc93x_irq_unmask,
+};
+
+void __init nuc93x_init_irq(void)
+{
+        int irqno;
+
+        __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
+
+        for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
+                set_irq_chip(irqno, &nuc93x_irq_chip);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
new file mode 100644
index 000000000000..9f79266f08e2
--- /dev/null
+++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c
@@ -0,0 +1,45 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc910evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+
+#include "nuc932.h"
+
+static void __init nuc932evb_map_io(void)
+{
+        nuc932_map_io();
+        nuc932_init_clocks();
+        nuc932_init_uartclk();
+}
+
+static void __init nuc932evb_init(void)
+{
+        nuc932_board_init();
+}
+
+MACHINE_START(NUC932EVB, "NUC932EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = NUC93X_PA_UART,
+        .io_pg_offst    = (((u32)NUC93X_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc932evb_map_io,
+        .init_irq       = nuc93x_init_irq,
+        .init_machine   = nuc932evb_init,
+        .timer          = &nuc93x_timer,
+MACHINE_END
diff --git a/arch/arm/mach-nuc93x/nuc932.c b/arch/arm/mach-nuc93x/nuc932.c
new file mode 100644
index 000000000000..3966ead686fc
--- /dev/null
+++ b/arch/arm/mach-nuc93x/nuc932.c
@@ -0,0 +1,65 @@
+/*
+ * linux/arch/arm/mach-nuc93x/nuc932.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC932 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* define specific CPU platform device */
+
+static struct platform_device *nuc932_dev[] __initdata = {
+};
+
+/* define specific CPU platform io map */
+
+static struct map_desc nuc932evb_iodesc[] __initdata = {
+};
+
+/*Init NUC932 evb io*/
+
+void __init nuc932_map_io(void)
+{
+        nuc93x_map_io(nuc932evb_iodesc, ARRAY_SIZE(nuc932evb_iodesc));
+}
+
+/*Init NUC932 clock*/
+
+void __init nuc932_init_clocks(void)
+{
+        nuc93x_init_clocks();
+}
+
+/*enable NUC932 uart clock*/
+
+void __init nuc932_init_uartclk(void)
+{
+        struct clk *ck_uart = clk_get(NULL, "uart");
+        BUG_ON(IS_ERR(ck_uart));
+
+        clk_enable(ck_uart);
+}
+
+/*Init NUC932 board info*/
+
+void __init nuc932_board_init(void)
+{
+        nuc93x_board_init(nuc932_dev, ARRAY_SIZE(nuc932_dev));
+}
diff --git a/arch/arm/mach-nuc93x/nuc932.h b/arch/arm/mach-nuc93x/nuc932.h
new file mode 100644
index 000000000000..9a66edd5338f
--- /dev/null
+++ b/arch/arm/mach-nuc93x/nuc932.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-nuc93x/nuc932.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC93x CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct map_desc;
+struct sys_timer;
+
+/* core initialisation functions */
+
+extern void nuc93x_init_irq(void);
+extern struct sys_timer nuc93x_timer;
+
+/* extern file from nuc932.c */
+
+extern void nuc932_board_init(void);
+extern void nuc932_init_clocks(void);
+extern void nuc932_map_io(void);
+extern void nuc932_init_uartclk(void);
diff --git a/arch/arm/mach-nuc93x/time.c b/arch/arm/mach-nuc93x/time.c
new file mode 100644
index 000000000000..2f90f9dc6e30
--- /dev/null
+++ b/arch/arm/mach-nuc93x/time.c
@@ -0,0 +1,100 @@
+/*
+ * linux/arch/arm/mach-nuc93x/time.c
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+#include <mach/system.h>
+#include <mach/map.h>
+#include <mach/regs-timer.h>
+
+#define RESETINT        0x01
+#define PERIOD          (0x01 << 27)
+#define ONESHOT         (0x00 << 27)
+#define COUNTEN         (0x01 << 30)
+#define INTEN           (0x01 << 29)
+
+#define TICKS_PER_SEC   100
+#define PRESCALE        0x63 /* Divider = prescale + 1 */
+
+unsigned int timer0_load;
+
+static unsigned long nuc93x_gettimeoffset(void)
+{
+        return 0;
+}
+
+/*IRQ handler for the timer*/
+
+static irqreturn_t nuc93x_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+        __raw_writel(0x01, REG_TISR); /* clear TIF0 */
+        return IRQ_HANDLED;
+}
+
+static struct irqaction nuc93x_timer_irq = {
+        .name           = "nuc93x Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = nuc93x_timer_interrupt,
+};
+
+/*Set up timer reg.*/
+
+static void nuc93x_timer_setup(void)
+{
+        struct clk *ck_ext = clk_get(NULL, "ext");
+        struct clk *ck_timer = clk_get(NULL, "timer");
+        unsigned int rate, val = 0;
+
+        BUG_ON(IS_ERR(ck_ext) || IS_ERR(ck_timer));
+
+        clk_enable(ck_timer);
+        rate = clk_get_rate(ck_ext);
+        clk_put(ck_ext);
+        rate = rate / (PRESCALE + 0x01);
+
+         /* set a known state */
+        __raw_writel(0x00, REG_TCSR0);
+        __raw_writel(RESETINT, REG_TISR);
+
+        timer0_load = (rate / TICKS_PER_SEC);
+        __raw_writel(timer0_load, REG_TICR0);
+
+        val |= (PERIOD | COUNTEN | INTEN | PRESCALE);;
+        __raw_writel(val, REG_TCSR0);
+
+}
+
+static void __init nuc93x_timer_init(void)
+{
+        nuc93x_timer_setup();
+        setup_irq(IRQ_TIMER0, &nuc93x_timer_irq);
+}
+
+struct sys_timer nuc93x_timer = {
+        .init           = nuc93x_timer_init,
+        .offset         = nuc93x_gettimeoffset,
+        .resume         = nuc93x_timer_setup
+};
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 029c6c9b3a6d..180ac112e527 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -30,6 +30,7 @@
 #include <plat/timer-gp.h>
 #include <plat/usb.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 
 static struct platform_device sdp4430_lcd_device = {
         .name           = "sdp4430_lcd",
@@ -48,6 +49,59 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
+#ifdef CONFIG_CACHE_L2X0
+noinline void omap_smc1(u32 fn, u32 arg)
+{
+        register u32 r12 asm("r12") = fn;
+        register u32 r0 asm("r0") = arg;
+
+        /* This is common routine cache secure monitor API used to
+         * modify the PL310 secure registers.
+         * r0 contains the value to be modified and "r12" contains
+         * the monitor API number. It uses few CPU registers
+         * internally and hence they need be backed up including
+         * link register "lr".
+         * Explicitly save r11 and r12 the compiler generated code
+         * won't save it.
+         */
+        asm volatile(
+                "stmfd r13!, {r11,r12}\n"
+                "dsb\n"
+                "smc\n"
+                "ldmfd r13!, {r11,r12}\n"
+                : "+r" (r0), "+r" (r12)
+                :
+                : "r4", "r5", "r10", "lr", "cc");
+}
+EXPORT_SYMBOL(omap_smc1);
+
+static int __init omap_l2_cache_init(void)
+{
+        void __iomem *l2cache_base;
+
+        /* To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        /* Static mapping, never released */
+        l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
+        BUG_ON(!l2cache_base);
+
+        /* Enable PL310 L2 Cache controller */
+        omap_smc1(0x102, 0x1);
+
+        /* 32KB way size, 16-way associativity,
+        * parity disabled
+        */
+        l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+
+        return 0;
+}
+early_initcall(omap_l2_cache_init);
+#endif
+
 static void __init gic_init_irq(void)
 {
         void __iomem *base;
diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h
index 7147a297e97f..06b50aeff7b9 100644
--- a/arch/arm/mach-orion5x/include/mach/vmalloc.h
+++ b/arch/arm/mach-orion5x/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-orion5x/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END       0xfd800000
+#define VMALLOC_END       0xfd800000UL
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 898c0e88acbc..9d1975fa4d9f 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -22,8 +22,9 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <asm/clkdev.h>
 
+#include <mach/hardware.h>
 #include <mach/clock.h>
 #include "clock.h"
 
@@ -56,18 +57,19 @@ static void propagate_rate(struct clk *clk)
         }
 }
 
-static inline void clk_reg_disable(struct clk *clk)
+static void clk_reg_disable(struct clk *clk)
 {
         if (clk->enable_reg)
                 __raw_writel(__raw_readl(clk->enable_reg) &
                              ~(1 << clk->enable_shift), clk->enable_reg);
 }
 
-static inline void clk_reg_enable(struct clk *clk)
+static int clk_reg_enable(struct clk *clk)
 {
         if (clk->enable_reg)
                 __raw_writel(__raw_readl(clk->enable_reg) |
                              (1 << clk->enable_shift), clk->enable_reg);
+        return 0;
 }
 
 static inline void clk_reg_disable1(struct clk *clk)
@@ -636,31 +638,34 @@ static struct clk flash_ck = {
 static struct clk i2c0_ck = {
         .name = "i2c0_ck",
         .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
+        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
         .enable_shift = 0,
         .enable_reg = I2CCLKCTRL_REG,
+        .rate = 13000000,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 static struct clk i2c1_ck = {
         .name = "i2c1_ck",
         .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
+        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
         .enable_shift = 1,
         .enable_reg = I2CCLKCTRL_REG,
+        .rate = 13000000,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 static struct clk i2c2_ck = {
         .name = "i2c2_ck",
         .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
+        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
         .enable_shift = 2,
         .enable_reg = USB_OTG_CLKCTRL_REG,
+        .rate = 13000000,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 static struct clk spi0_ck = {
@@ -738,16 +743,16 @@ static struct clk wdt_ck = {
         .name = "wdt_ck",
         .parent = &per_ck,
         .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
         .enable_shift = 0,
         .enable_reg = TIMCLKCTRL_REG,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 /* These clocks are visible outside this module
  * and can be initialized
  */
-static struct clk *onchip_clks[] = {
+static struct clk *onchip_clks[] __initdata = {
         &ck_13MHz,
         &ck_pll1,
         &ck_pll4,
@@ -777,49 +782,74 @@ static struct clk *onchip_clks[] = {
         &wdt_ck,
 };
 
-static int local_clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-            && clk->user_rate)
-                ret = clk->set_rate(clk, clk->user_rate);
-        return ret;
-}
+static struct clk_lookup onchip_clkreg[] = {
+        { .clk = &ck_13MHz,     .con_id = "ck_13MHz"    },
+        { .clk = &ck_pll1,      .con_id = "ck_pll1"     },
+        { .clk = &ck_pll4,      .con_id = "ck_pll4"     },
+        { .clk = &ck_pll5,      .con_id = "ck_pll5"     },
+        { .clk = &ck_pll3,      .con_id = "ck_pll3"     },
+        { .clk = &vfp9_ck,      .con_id = "vfp9_ck"     },
+        { .clk = &m2hclk_ck,    .con_id = "m2hclk_ck"   },
+        { .clk = &hclk_ck,      .con_id = "hclk_ck"     },
+        { .clk = &dma_ck,       .con_id = "dma_ck"      },
+        { .clk = &flash_ck,     .con_id = "flash_ck"    },
+        { .clk = &dum_ck,       .con_id = "dum_ck"      },
+        { .clk = &keyscan_ck,   .con_id = "keyscan_ck"  },
+        { .clk = &pwm1_ck,      .con_id = "pwm1_ck"     },
+        { .clk = &pwm2_ck,      .con_id = "pwm2_ck"     },
+        { .clk = &jpeg_ck,      .con_id = "jpeg_ck"     },
+        { .clk = &ms_ck,        .con_id = "ms_ck"       },
+        { .clk = &touch_ck,     .con_id = "touch_ck"    },
+        { .clk = &i2c0_ck,      .dev_id = "pnx-i2c.0"   },
+        { .clk = &i2c1_ck,      .dev_id = "pnx-i2c.1"   },
+        { .clk = &i2c2_ck,      .dev_id = "pnx-i2c.2"   },
+        { .clk = &spi0_ck,      .con_id = "spi0_ck"     },
+        { .clk = &spi1_ck,      .con_id = "spi1_ck"     },
+        { .clk = &uart3_ck,     .con_id = "uart3_ck"    },
+        { .clk = &uart4_ck,     .con_id = "uart4_ck"    },
+        { .clk = &uart5_ck,     .con_id = "uart5_ck"    },
+        { .clk = &uart6_ck,     .con_id = "uart6_ck"    },
+        { .clk = &wdt_ck,       .dev_id = "pnx4008-watchdog" },
+};
 
 static void local_clk_disable(struct clk *clk)
 {
-        if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-                clk->set_rate(clk, 0);
-}
+        if (WARN_ON(clk->usecount == 0))
+                return;
 
-static void local_clk_unuse(struct clk *clk)
-{
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                local_clk_disable(clk);
+        if (!(--clk->usecount)) {
+                if (clk->disable)
+                        clk->disable(clk);
+                else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
+                        clk->set_rate(clk, 0);
                 if (clk->parent)
-                        local_clk_unuse(clk->parent);
+                        local_clk_disable(clk->parent);
         }
 }
 
-static int local_clk_use(struct clk *clk)
+static int local_clk_enable(struct clk *clk)
 {
         int ret = 0;
-        if (clk->usecount++ == 0) {
-                if (clk->parent)
-                        ret = local_clk_use(clk->parent);
 
-                if (ret != 0) {
-                        clk->usecount--;
-                        goto out;
+        if (clk->usecount == 0) {
+                if (clk->parent) {
+                        ret = local_clk_enable(clk->parent);
+                        if (ret != 0)
+                                goto out;
                 }
 
-                ret = local_clk_enable(clk);
+                if (clk->enable)
+                        ret = clk->enable(clk);
+                else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
+                            && clk->user_rate)
+                        ret = clk->set_rate(clk, clk->user_rate);
 
                 if (ret != 0 && clk->parent) {
-                        local_clk_unuse(clk->parent);
-                        clk->usecount--;
+                        local_clk_disable(clk->parent);
+                        goto out;
                 }
+
+                clk->usecount++;
         }
 out:
         return ret;
@@ -866,35 +896,6 @@ out:
 
 EXPORT_SYMBOL(clk_set_rate);
 
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *clk = ERR_PTR(-ENOENT);
-        struct clk **clkp;
-
-        clock_lock();
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-                if (strcmp(id, (*clkp)->name) == 0
-                    && try_module_get((*clkp)->owner)) {
-                        clk = (*clkp);
-                        break;
-                }
-        }
-        clock_unlock();
-
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-        clock_lock();
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-        clock_unlock();
-}
-EXPORT_SYMBOL(clk_put);
-
 unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long ret;
@@ -907,10 +908,10 @@ EXPORT_SYMBOL(clk_get_rate);
 
 int clk_enable(struct clk *clk)
 {
-        int ret = 0;
+        int ret;
 
         clock_lock();
-        ret = local_clk_use(clk);
+        ret = local_clk_enable(clk);
         clock_unlock();
         return ret;
 }
@@ -920,7 +921,7 @@ EXPORT_SYMBOL(clk_enable);
 void clk_disable(struct clk *clk)
 {
         clock_lock();
-        local_clk_unuse(clk);
+        local_clk_disable(clk);
         clock_unlock();
 }
 
@@ -967,18 +968,24 @@ static int __init clk_init(void)
 
         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
              clkp++) {
-                if (((*clkp)->flags & NEEDS_INITIALIZATION)
-                    && ((*clkp)->set_rate)) {
-                        (*clkp)->user_rate = (*clkp)->rate;
-                        local_set_rate((*clkp), (*clkp)->user_rate);
-                        if ((*clkp)->set_parent)
-                                (*clkp)->set_parent((*clkp), (*clkp)->parent);
+                struct clk *clk = *clkp;
+                if (clk->flags & NEEDS_INITIALIZATION) {
+                        if (clk->set_rate) {
+                                clk->user_rate = clk->rate;
+                                local_set_rate(clk, clk->user_rate);
+                                if (clk->set_parent)
+                                        clk->set_parent(clk, clk->parent);
+                        }
+                        if (clk->enable && clk->usecount)
+                                clk->enable(clk);
+                        if (clk->disable && !clk->usecount)
+                                clk->disable(clk);
                 }
                 pr_debug("%s: clock %s, rate %ld\n",
-                        __func__, (*clkp)->name, (*clkp)->rate);
+                        __func__, clk->name, clk->rate);
         }
 
-        local_clk_use(&ck_pll4);
+        local_clk_enable(&ck_pll4);
 
         /* if ck_13MHz is not used, disable it. */
         if (ck_13MHz.usecount == 0)
@@ -987,6 +994,8 @@ static int __init clk_init(void)
         /* Disable autoclocking */
         __raw_writeb(0xff, AUTOCLK_CTRL);
 
+        clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
+
         return 0;
 }
 
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
index cd58f372cfd0..39720d6c0d01 100644
--- a/arch/arm/mach-pnx4008/clock.h
+++ b/arch/arm/mach-pnx4008/clock.h
@@ -14,8 +14,6 @@
 #define __ARCH_ARM_PNX4008_CLOCK_H__
 
 struct clk {
-        struct list_head node;
-        struct module *owner;
         const char *name;
         struct clk *parent;
         struct clk *propagate_next;
@@ -29,9 +27,11 @@ struct clk {
         u8 enable_shift1;
         u32 enable_reg1;
         u32 parent_switch_reg;
-         u32(*round_rate) (struct clk *, u32);
+        u32(*round_rate) (struct clk *, u32);
         int (*set_rate) (struct clk *, u32);
         int (*set_parent) (struct clk * clk, struct clk * parent);
+        int (*enable)(struct clk *);
+        void (*disable)(struct clk *);
 };
 
 /* Flags */
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index f3fea29c00d3..8103f9644e2d 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -18,120 +18,24 @@
 #include <mach/irqs.h>
 #include <mach/i2c.h>
 
-static int set_clock_run(struct platform_device *pdev)
-{
-        struct clk *clk;
-        char name[10];
-        int retval = 0;
-
-        snprintf(name, 10, "i2c%d_ck", pdev->id);
-        clk = clk_get(&pdev->dev, name);
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, 1);
-                clk_put(clk);
-        } else
-                retval = -ENOENT;
-
-        return retval;
-}
-
-static int set_clock_stop(struct platform_device *pdev)
-{
-        struct clk *clk;
-        char name[10];
-        int retval = 0;
-
-        snprintf(name, 10, "i2c%d_ck", pdev->id);
-        clk = clk_get(&pdev->dev, name);
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, 0);
-                clk_put(clk);
-        } else
-                retval = -ENOENT;
-
-        return retval;
-}
-
-static int i2c_pnx_suspend(struct platform_device *pdev, pm_message_t state)
-{
-        int retval = 0;
-#ifdef CONFIG_PM
-        retval = set_clock_run(pdev);
-#endif
-        return retval;
-}
-
-static int i2c_pnx_resume(struct platform_device *pdev)
-{
-        int retval = 0;
-#ifdef CONFIG_PM
-        retval = set_clock_run(pdev);
-#endif
-        return retval;
-}
-
-static u32 calculate_input_freq(struct platform_device *pdev)
-{
-        return HCLK_MHZ;
-}
-
-
-static struct i2c_pnx_algo_data pnx_algo_data0 = {
+static struct i2c_pnx_data i2c0_data = {
+        .name = I2C_CHIP_NAME "0",
         .base = PNX4008_I2C1_BASE,
         .irq = I2C_1_INT,
 };
 
-static struct i2c_pnx_algo_data pnx_algo_data1 = {
+static struct i2c_pnx_data i2c1_data = {
+        .name = I2C_CHIP_NAME "1",
         .base = PNX4008_I2C2_BASE,
         .irq = I2C_2_INT,
 };
 
-static struct i2c_pnx_algo_data pnx_algo_data2 = {
+static struct i2c_pnx_data i2c2_data = {
+        .name = "USB-I2C",
         .base = (PNX4008_USB_CONFIG_BASE + 0x300),
         .irq = USB_I2C_INT,
 };
 
-static struct i2c_adapter pnx_adapter0 = {
-        .name = I2C_CHIP_NAME "0",
-        .algo_data = &pnx_algo_data0,
-};
-static struct i2c_adapter pnx_adapter1 = {
-        .name = I2C_CHIP_NAME "1",
-        .algo_data = &pnx_algo_data1,
-};
-
-static struct i2c_adapter pnx_adapter2 = {
-        .name = "USB-I2C",
-        .algo_data = &pnx_algo_data2,
-};
-
-static struct i2c_pnx_data i2c0_data = {
-        .suspend = i2c_pnx_suspend,
-        .resume = i2c_pnx_resume,
-        .calculate_input_freq = calculate_input_freq,
-        .set_clock_run = set_clock_run,
-        .set_clock_stop = set_clock_stop,
-        .adapter = &pnx_adapter0,
-};
-
-static struct i2c_pnx_data i2c1_data = {
-        .suspend = i2c_pnx_suspend,
-        .resume = i2c_pnx_resume,
-        .calculate_input_freq = calculate_input_freq,
-        .set_clock_run = set_clock_run,
-        .set_clock_stop = set_clock_stop,
-        .adapter = &pnx_adapter1,
-};
-
-static struct i2c_pnx_data i2c2_data = {
-        .suspend = i2c_pnx_suspend,
-        .resume = i2c_pnx_resume,
-        .calculate_input_freq = calculate_input_freq,
-        .set_clock_run = set_clock_run,
-        .set_clock_stop = set_clock_stop,
-        .adapter = &pnx_adapter2,
-};
-
 static struct platform_device i2c0_device = {
         .name = "pnx-i2c",
         .id = 0,
diff --git a/arch/arm/mach-pnx4008/include/mach/clkdev.h b/arch/arm/mach-pnx4008/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
index 5ff0196c0f16..b383c7de7ab4 100644
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ b/arch/arm/mach-pnx4008/include/mach/timex.h
@@ -14,60 +14,6 @@
 #ifndef __PNX4008_TIMEX_H
 #define __PNX4008_TIMEX_H
 
-#include <linux/io.h>
-#include <mach/hardware.h>
-
 #define CLOCK_TICK_RATE         1000000
 
-#define TICKS2USECS(x)  (x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
 #endif
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index b3d8d53e32ef..1f0585329be4 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
 #include <mach/pm.h>
 #include <mach/clock.h>
 
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index fc0ba183fe12..0c8aad4bb0dc 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -30,6 +30,8 @@
 #include <asm/mach/time.h>
 #include <asm/errno.h>
 
+#include "time.h"
+
 /*! Note: all timers are UPCOUNTING */
 
 /*!
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
new file mode 100644
index 000000000000..75e88c570aa7
--- /dev/null
+++ b/arch/arm/mach-pnx4008/time.h
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/timex.h
+ *
+ * PNX4008 timers header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef PNX_TIME_H
+#define PNX_TIME_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+#define TICKS2USECS(x)  (x)
+
+/* MilliSecond Timer - Chapter 21 Page 202 */
+
+#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
+#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
+#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
+#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
+#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
+#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
+
+/* High Speed Timer - Chpater 22, Page 205 */
+
+#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
+#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
+#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
+#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
+#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
+#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
+#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
+#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
+#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
+#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
+#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
+#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
+
+/* IMPORTANT: both timers are UPCOUNTING */
+
+/* xSTIM_MCTRL bit definitions */
+#define MR0_INT        1
+#define RESET_COUNT0   (1<<1)
+#define STOP_COUNT0    (1<<2)
+#define MR1_INT        (1<<3)
+#define RESET_COUNT1   (1<<4)
+#define STOP_COUNT1    (1<<5)
+#define MR2_INT        (1<<6)
+#define RESET_COUNT2   (1<<7)
+#define STOP_COUNT2    (1<<8)
+
+/* xSTIM_CTRL bit definitions */
+#define COUNT_ENAB     1
+#define RESET_COUNT    (1<<1)
+#define DEBUG_EN       (1<<2)
+
+/* xSTIM_INT bit definitions */
+#define MATCH0_INT     1
+#define MATCH1_INT     (1<<1)
+#define MATCH2_INT     (1<<2)
+#define RTC_TICK0      (1<<4)
+#define RTC_TICK1      (1<<5)
+
+#endif
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 49ae38292310..abba0089a2ae 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -78,11 +78,3 @@ const struct clkops clk_cken_ops = {
         .enable         = clk_cken_enable,
         .disable        = clk_cken_disable,
 };
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 978a3667e90d..d8488742b807 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -67,7 +67,3 @@ extern void clk_pxa3xx_cken_enable(struct clk *);
 extern void clk_pxa3xx_cken_disable(struct clk *);
 #endif
 
-void clks_register(struct clk_lookup *clks, size_t num);
-int clk_add_alias(const char *alias, const char *alias_name, char *id,
-        struct device *dev);
-
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 91417f035069..96ed13081639 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -128,6 +128,6 @@ static struct clk_lookup eseries_clkregs[] = {
 
 void eseries_register_clks(void)
 {
-        clks_register(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
+        clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
 }
 
diff --git a/arch/arm/mach-pxa/include/mach/camera.h b/arch/arm/mach-pxa/include/mach/camera.h
index 31abe6d514b8..6709b1cd7c77 100644
--- a/arch/arm/mach-pxa/include/mach/camera.h
+++ b/arch/arm/mach-pxa/include/mach/camera.h
@@ -35,8 +35,6 @@
 #define PXA_CAMERA_VSP          0x400
 
 struct pxacamera_platform_data {
-        int (*init)(struct device *);
-
         unsigned long flags;
         unsigned long mclk_10khz;
 };
diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h
index e90c5eeb81dd..bfecfbf5f460 100644
--- a/arch/arm/mach-pxa/include/mach/vmalloc.h
+++ b/arch/arm/mach-pxa/include/mach/vmalloc.h
@@ -8,4 +8,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (0xe8000000)
+#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 2c1b0b70d01d..0b9ad30bfd51 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -349,7 +349,7 @@ static int __init pxa25x_init(void)
 
                 reset_status = RCSR;
 
-                clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
+                clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
 
                 if ((ret = pxa_init_dma(IRQ_DMA, 16)))
                         return ret;
@@ -370,7 +370,7 @@ static int __init pxa25x_init(void)
 
         /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
         if (cpu_is_pxa255())
-                clks_register(&pxa25x_hwuart_clkreg, 1);
+                clkdev_add(&pxa25x_hwuart_clkreg);
 
         return ret;
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6a0b73167e03..d783123e2d48 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -392,7 +392,7 @@ static int __init pxa27x_init(void)
 
                 reset_status = RCSR;
 
-                clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
+                clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 
                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
                         return ret;
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index f4af6e2bef89..40bb16501d86 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -102,12 +102,12 @@ static int __init pxa300_init(void)
         if (cpu_is_pxa300() || cpu_is_pxa310()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa300_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(common_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(common_clkregs));
         }
 
         if (cpu_is_pxa310()) {
                 mfp_init_addr(pxa310_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(pxa310_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa310_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index c7373e74a109..8d614ecd8e99 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -90,7 +90,7 @@ static int __init pxa320_init(void)
         if (cpu_is_pxa320()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa320_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(pxa320_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa320_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index fcb0721f4669..4d7c03e72504 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -634,7 +634,7 @@ static int __init pxa3xx_init(void)
                  */
                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 
-                clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
+                clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 
                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
                         return ret;
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 9f293438e020..90bd4ef71b2c 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -346,10 +346,7 @@ static struct clk_lookup lookups[] = {
 
 static int __init clk_init(void)
 {
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
         return 0;
 }
 arch_initcall(clk_init);
diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h
index fe0de1b507ac..a2a4c6861407 100644
--- a/arch/arm/mach-realview/include/mach/vmalloc.h
+++ b/arch/arm/mach-realview/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END             0xf8000000
+#define VMALLOC_END             0xf8000000UL
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
index 4d4fe4849589..914656820794 100644
--- a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END       (0xe0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h
index ec8fdc5a3606..b3d002398480 100644
--- a/arch/arm/mach-sa1100/include/mach/vmalloc.h
+++ b/arch/arm/mach-sa1100/include/mach/vmalloc.h
@@ -1,4 +1,4 @@
 /*
  * arch/arm/mach-sa1100/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (0xe8000000)
+#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 111f7ea32b38..5af71d5ba665 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -610,34 +610,34 @@ EXPORT_SYMBOL(clk_get_rate);
 
 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
 {
-        if (rate >= 18900000)
+        if (rate <= 18900000)
                 return 18900000;
-        if (rate >= 20800000)
+        if (rate <= 20800000)
                 return 20800000;
-        if (rate >= 23100000)
+        if (rate <= 23100000)
                 return 23100000;
-        if (rate >= 26000000)
+        if (rate <= 26000000)
                 return 26000000;
-        if (rate >= 29700000)
+        if (rate <= 29700000)
                 return 29700000;
-        if (rate >= 34700000)
+        if (rate <= 34700000)
                 return 34700000;
-        if (rate >= 41600000)
+        if (rate <= 41600000)
                 return 41600000;
-        if (rate >= 52000000)
+        if (rate <= 52000000)
                 return 52000000;
         return -EINVAL;
 }
 
 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
 {
-        if (rate >= 13000000)
+        if (rate <= 13000000)
                 return 13000000;
-        if (rate >= 52000000)
+        if (rate <= 52000000)
                 return 52000000;
-        if (rate >= 104000000)
+        if (rate <= 104000000)
                 return 104000000;
-        if (rate >= 208000000)
+        if (rate <= 208000000)
                 return 208000000;
         return -EINVAL;
 }
@@ -1276,11 +1276,8 @@ static struct clk_lookup lookups[] = {
 
 static void __init clk_register(void)
 {
-        int i;
-
         /* Register the lookups */
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 }
 
 /*
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 653e25be3dd8..01b50313914c 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2009 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -19,6 +19,7 @@
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <mach/coh901318.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -29,6 +30,7 @@
 
 #include <mach/hardware.h>
 #include <mach/syscon.h>
+#include <mach/dma_channels.h>
 
 #include "clock.h"
 #include "mmc.h"
@@ -372,8 +374,1019 @@ static struct resource ave_resources[] = {
         },
 };
 
+static struct resource dma_resource[] = {
+        {
+                .start = U300_DMAC_BASE,
+                .end = U300_DMAC_BASE + PAGE_SIZE - 1,
+                .flags =  IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_DMA,
+                .end = IRQ_U300_DMA,
+                .flags =  IORESOURCE_IRQ,
+        }
+};
+
+#ifdef CONFIG_MACH_U300_BS335
+/* points out all dma slave channels.
+ * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
+ * Select all channels from A to B, end of list is marked with -1,-1
+ */
+static int dma_slave_channels[] = {
+        U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
+        U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
+
+/* points out all dma memcpy channels. */
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
+
+#else /* CONFIG_MACH_U300_BS335 */
+
+static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
+
+#endif
+
+/** register dma for memory access
+ *
+ * active  1 means dma intends to access memory
+ *         0 means dma wont access memory
+ */
+static void coh901318_access_memory_state(struct device *dev, bool active)
+{
+}
+
+#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
+                        COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
+                        COH901318_CX_CFG_LCR_DISABLE | \
+                        COH901318_CX_CFG_TC_IRQ_ENABLE | \
+                        COH901318_CX_CFG_BE_IRQ_ENABLE)
+#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_ENABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+
+const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
+        {
+                .number = U300_DMA_MSL_TX_0,
+                .name = "MSL TX 0",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_TX_1,
+                .name = "MSL TX 1",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_2,
+                .name = "MSL TX 2",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .desc_nbr_max = 10,
+        },
+        {
+                .number = U300_DMA_MSL_TX_3,
+                .name = "MSL TX 3",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_4,
+                .name = "MSL TX 4",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_5,
+                .name = "MSL TX 5",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_TX_6,
+                .name = "MSL TX 6",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_RX_0,
+                .name = "MSL RX 0",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
+        },
+        {
+                .number = U300_DMA_MSL_RX_1,
+                .name = "MSL RX 1",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_2,
+                .name = "MSL RX 2",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_3,
+                .name = "MSL RX 3",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_4,
+                .name = "MSL RX 4",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_5,
+                .name = "MSL RX 5",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_6,
+                .name = "MSL RX 6",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
+        },
+        {
+                .number = U300_DMA_MMCSD_RX_TX,
+                .name = "MMCSD RX TX",
+                .priority_high = 0,
+                .dev_addr =  U300_MMCSD_BASE + 0x080,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+
+        },
+        {
+                .number = U300_DMA_MSPRO_TX,
+                .name = "MSPRO TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_MSPRO_RX,
+                .name = "MSPRO RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART0_TX,
+                .name = "UART0 TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART0_RX,
+                .name = "UART0 RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_APEX_TX,
+                .name = "APEX TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_APEX_RX,
+                .name = "APEX RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_PCM_I2S0_TX,
+                .name = "PCM I2S0 TX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S0_BASE + 0x14,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_PCM_I2S0_RX,
+                .name = "PCM I2S0 RX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S0_BASE + 0x10,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_PCM_I2S1_TX,
+                .name = "PCM I2S1 TX",
+                .priority_high = 1,
+                .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_PCM_I2S1_RX,
+                .name = "PCM I2S1 RX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S1_BASE + 0x10,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_XGAM_CDI,
+                .name = "XGAM CDI",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_XGAM_PDI,
+                .name = "XGAM PDI",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_SPI_TX,
+                .name = "SPI TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_SPI_RX,
+                .name = "SPI RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_0,
+                .name = "GENERAL 00",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_1,
+                .name = "GENERAL 01",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_2,
+                .name = "GENERAL 02",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_3,
+                .name = "GENERAL 03",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_4,
+                .name = "GENERAL 04",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_5,
+                .name = "GENERAL 05",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_6,
+                .name = "GENERAL 06",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_7,
+                .name = "GENERAL 07",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_8,
+                .name = "GENERAL 08",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+#ifdef CONFIG_MACH_U300_BS335
+        {
+                .number = U300_DMA_UART1_TX,
+                .name = "UART1 TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART1_RX,
+                .name = "UART1 RX",
+                .priority_high = 0,
+        }
+#else
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_9,
+                .name = "GENERAL 09",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_10,
+                .name = "GENERAL 10",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        }
+#endif
+};
+
+
+static struct coh901318_platform coh901318_platform = {
+        .chans_slave = dma_slave_channels,
+        .chans_memcpy = dma_memcpy_channels,
+        .access_memory_state = coh901318_access_memory_state,
+        .chan_conf = chan_config,
+        .max_channels = U300_DMA_CHANNELS,
+};
+
 static struct platform_device wdog_device = {
-        .name = "wdog",
+        .name = "coh901327_wdog",
         .id = -1,
         .num_resources = ARRAY_SIZE(wdog_resources),
         .resource = wdog_resources,
@@ -428,11 +1441,23 @@ static struct platform_device ave_device = {
         .resource = ave_resources,
 };
 
+static struct platform_device dma_device = {
+        .name           = "coh901318",
+        .id             = -1,
+        .resource       = dma_resource,
+        .num_resources  = ARRAY_SIZE(dma_resource),
+        .dev = {
+                .platform_data = &coh901318_platform,
+                .coherent_dma_mask = ~0,
+        },
+};
+
 /*
  * Notice that AMBA devices are initialized before platform devices.
  *
  */
 static struct platform_device *platform_devs[] __initdata = {
+        &dma_device,
         &i2c0_device,
         &i2c1_device,
         &keypad_device,
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
index 0b35826b7d1d..5f61fd45a0c8 100644
--- a/arch/arm/mach-u300/gpio.c
+++ b/arch/arm/mach-u300/gpio.c
@@ -546,7 +546,7 @@ static void gpio_set_initial_values(void)
         for (i = 0; i < U300_GPIO_MAX; i++) {
                 val = 0;
                 for (j = 0; j < 8; j++)
-                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
+                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
                 local_irq_save(flags);
                 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
                 local_irq_restore(flags);
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
new file mode 100644
index 000000000000..b239149ba0d0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -0,0 +1,69 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/dma_channels.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Map file for the U300 dma driver.
+ * Author: Per Friden <per.friden@stericsson.com>
+ */
+
+#ifndef DMA_CHANNELS_H
+#define DMA_CHANNELS_H
+
+#define U300_DMA_MSL_TX_0             0
+#define U300_DMA_MSL_TX_1             1
+#define U300_DMA_MSL_TX_2             2
+#define U300_DMA_MSL_TX_3             3
+#define U300_DMA_MSL_TX_4             4
+#define U300_DMA_MSL_TX_5             5
+#define U300_DMA_MSL_TX_6             6
+#define U300_DMA_MSL_RX_0             7
+#define U300_DMA_MSL_RX_1             8
+#define U300_DMA_MSL_RX_2             9
+#define U300_DMA_MSL_RX_3             10
+#define U300_DMA_MSL_RX_4             11
+#define U300_DMA_MSL_RX_5             12
+#define U300_DMA_MSL_RX_6             13
+#define U300_DMA_MMCSD_RX_TX          14
+#define U300_DMA_MSPRO_TX             15
+#define U300_DMA_MSPRO_RX             16
+#define U300_DMA_UART0_TX             17
+#define U300_DMA_UART0_RX             18
+#define U300_DMA_APEX_TX              19
+#define U300_DMA_APEX_RX              20
+#define U300_DMA_PCM_I2S0_TX          21
+#define U300_DMA_PCM_I2S0_RX          22
+#define U300_DMA_PCM_I2S1_TX          23
+#define U300_DMA_PCM_I2S1_RX          24
+#define U300_DMA_XGAM_CDI             25
+#define U300_DMA_XGAM_PDI             26
+#define U300_DMA_SPI_TX               27
+#define U300_DMA_SPI_RX               28
+#define U300_DMA_GENERAL_PURPOSE_0    29
+#define U300_DMA_GENERAL_PURPOSE_1    30
+#define U300_DMA_GENERAL_PURPOSE_2    31
+#define U300_DMA_GENERAL_PURPOSE_3    32
+#define U300_DMA_GENERAL_PURPOSE_4    33
+#define U300_DMA_GENERAL_PURPOSE_5    34
+#define U300_DMA_GENERAL_PURPOSE_6    35
+#define U300_DMA_GENERAL_PURPOSE_7    36
+#define U300_DMA_GENERAL_PURPOSE_8    37
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_DMA_UART1_TX             38
+#define U300_DMA_UART1_RX             39
+#else
+#define U300_DMA_GENERAL_PURPOSE_9    38
+#define U300_DMA_GENERAL_PURPOSE_10   39
+#endif
+
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_DMA_DEVICE_CHANNELS      32
+#else
+#define U300_DMA_DEVICE_CHANNELS      30
+#endif
+#define U300_DMA_CHANNELS             40
+
+
+#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
index b00c51a66fbe..ec423b92b81d 100644
--- a/arch/arm/mach-u300/include/mach/vmalloc.h
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -9,4 +9,4 @@
  * End must be above the I/O registers and on an even 2MiB boundary.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index aa5afbcc90f9..803aec1d6728 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -22,6 +22,7 @@
 #include <asm/mach/arch.h>
 
 #include <plat/mtu.h>
+#include <plat/i2c.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -108,11 +109,96 @@ static struct amba_device pl022_device = {
         .periphid = SSP_PER_ID,
 };
 
+static struct amba_device pl031_device = {
+        .dev = {
+                .init_name = "pl031",
+        },
+        .res = {
+                .start = U8500_RTC_BASE,
+                .end = U8500_RTC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_RTC_RTT, NO_IRQ},
+};
+
+#define U8500_I2C_RESOURCES(id, size)           \
+static struct resource u8500_i2c_resources_##id[] = {   \
+        [0] = {                                 \
+                .start  = U8500_I2C##id##_BASE, \
+                .end    = U8500_I2C##id##_BASE + size - 1, \
+                .flags  = IORESOURCE_MEM,       \
+        },                                      \
+        [1] = {                                 \
+                .start  = IRQ_I2C##id,          \
+                .end    = IRQ_I2C##id,          \
+                .flags  = IORESOURCE_IRQ        \
+        }                                       \
+}
+
+U8500_I2C_RESOURCES(0, SZ_4K);
+U8500_I2C_RESOURCES(1, SZ_4K);
+U8500_I2C_RESOURCES(2, SZ_4K);
+U8500_I2C_RESOURCES(3, SZ_4K);
+
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
+static struct nmk_i2c_controller u8500_i2c_##id = { \
+        /*                              \
+         * slave data setup time, which is      \
+         * 250 ns,100ns,10ns which is 14,6,2    \
+         * respectively for a 48 Mhz    \
+         * i2c clock                    \
+         */                             \
+        .slsu           = _slsu,        \
+        /* Tx FIFO threshold */         \
+        .tft            = _tft,         \
+        /* Rx FIFO threshold */         \
+        .rft            = _rft,         \
+        /* std. mode operation */       \
+        .clk_freq       = clk,          \
+        .sm             = _sm,          \
+}
+
+/*
+ * The board uses 4 i2c controllers, initialize all of
+ * them with slave data setup time of 250 ns,
+ * Tx & Rx FIFO threshold values as 1 and standard
+ * mode of operation
+ */
+U8500_I2C_CONTROLLER(0, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+
+#define U8500_I2C_PDEVICE(cid)          \
+static struct platform_device i2c_controller##cid = { \
+        .name = "nmk-i2c",              \
+        .id      = cid,                 \
+        .num_resources = 2,             \
+        .resource = u8500_i2c_resources_##cid,  \
+        .dev = {                        \
+                .platform_data = &u8500_i2c_##cid \
+        }                               \
+}
+
+U8500_I2C_PDEVICE(0);
+U8500_I2C_PDEVICE(1);
+U8500_I2C_PDEVICE(2);
+U8500_I2C_PDEVICE(3);
+
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
         &uart1_device,
         &uart2_device,
         &pl022_device,
+        &pl031_device,
+};
+
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
+        &i2c_controller0,
+        &i2c_controller1,
+        &i2c_controller2,
+        &i2c_controller3,
 };
 
 static void __init u8500_timer_init(void)
@@ -139,6 +225,8 @@ static void __init u8500_init_machine(void)
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
                 amba_device_register(amba_devs[i], &iomem_resource);
 
+        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+
         spi_register_board_info(u8500_spi_devices,
                         ARRAY_SIZE(u8500_spi_devices));
 
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 20b6ebb6783a..8359a73d0041 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -85,11 +85,8 @@ static struct clk_lookup lookups[] = {
 
 static int __init clk_init(void)
 {
-        int i;
-
         /* register the clock lookups */
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
         return 0;
 }
 arch_initcall(clk_init);
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
index 5f05e5850f71..397bc1f9ed94 100644
--- a/arch/arm/mach-ux500/cpu-u8500.c
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -33,6 +33,7 @@ static struct platform_device *platform_devs[] __initdata = {
 
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 494408b96785..09cbfda8aee5 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -8,12 +8,13 @@
  * published by the Free Software Foundation.
  *
  */
+#include <mach/hardware.h>
+
         .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @MMU enabled?
-        moveq   \rx, #0x80000000        @MMU off, Physical address
-        movne   \rx, #0xF0000000        @MMU on, Virtual address
-        orr     \rx, \rx, #0x7000
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =U8500_UART2_BASE                  @ no, physical address
+        ldrne   \rx, =IO_ADDRESS(U8500_UART2_BASE)      @ yes, virtual address
         .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
index 86cdbbce1842..a4945cb41172 100644
--- a/arch/arm/mach-ux500/include/mach/vmalloc.h
+++ b/arch/arm/mach-ux500/include/mach/vmalloc.h
@@ -15,4 +15,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END     0xf0000000
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e13be7c444ca..9ddb49b1cb71 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -851,8 +851,7 @@ void __init versatile_init(void)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         platform_device_register(&versatile_flash_device);
         platform_device_register(&versatile_i2c_device);
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
index b785994bab0a..2c371ff22e51 100644
--- a/arch/arm/mach-w90x900/clock.c
+++ b/arch/arm/mach-w90x900/clock.c
@@ -90,12 +90,3 @@ void nuc900_subclk_enable(struct clk *clk, int enable)
 
         __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
 }
-
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
index f5816a06eed6..c56ddab3d912 100644
--- a/arch/arm/mach-w90x900/clock.h
+++ b/arch/arm/mach-w90x900/clock.h
@@ -14,7 +14,6 @@
 
 void nuc900_clk_enable(struct clk *clk, int enable);
 void nuc900_subclk_enable(struct clk *clk, int enable);
-void clks_register(struct clk_lookup *clks, size_t num);
 
 struct clk {
         unsigned long           cken;
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 20dc0c96214d..642207e18198 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -45,6 +45,7 @@ static struct map_desc nuc900_iodesc[] __initdata = {
         IODESC_ENT(UART),
         IODESC_ENT(TIMER),
         IODESC_ENT(EBI),
+        IODESC_ENT(GPIO),
 };
 
 /* Initial clock declarations. */
@@ -68,6 +69,11 @@ static DEFINE_CLK(gdma, 27);
 static DEFINE_CLK(adc, 28);
 static DEFINE_CLK(usi, 29);
 static DEFINE_CLK(ext, 0);
+static DEFINE_CLK(timer0, 19);
+static DEFINE_CLK(timer1, 20);
+static DEFINE_CLK(timer2, 21);
+static DEFINE_CLK(timer3, 22);
+static DEFINE_CLK(timer4, 23);
 
 static struct clk_lookup nuc900_clkregs[] = {
         DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
@@ -90,6 +96,11 @@ static struct clk_lookup nuc900_clkregs[] = {
         DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
         DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
         DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+        DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
+        DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
+        DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
+        DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
+        DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
 };
 
 /* Initial serial platform data */
@@ -208,6 +219,6 @@ void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
 
 void __init nuc900_init_clocks(void)
 {
-        clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
+        clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
 }
 
diff --git a/arch/arm/mach-w90x900/include/mach/vmalloc.h b/arch/arm/mach-w90x900/include/mach/vmalloc.h
index 2f9dfb928533..b067e44500a4 100644
--- a/arch/arm/mach-w90x900/include/mach/vmalloc.h
+++ b/arch/arm/mach-w90x900/include/mach/vmalloc.h
@@ -18,6 +18,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END       (0xe0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index baf638487a2d..c4ed9f93f646 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -399,7 +399,7 @@ config CPU_V6
 config CPU_32v6K
         bool "Support ARM V6K processor extensions" if !SMP
         depends on CPU_V6
-        default y if SMP && !ARCH_MX3
+        default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)
         help
           Say Y here if your ARMv6 processor supports the 'K' extension.
           This enables the kernel to use some instructions not present
@@ -410,7 +410,7 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
-        select CPU_32v6K
+        select CPU_32v6K if !ARCH_OMAP2
         select CPU_32v7
         select CPU_ABRT_EV7
         select CPU_PABRT_V7
@@ -754,7 +754,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
         default y
         select OUTER_CACHE
         help
@@ -779,5 +779,5 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT
         int
-        default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
+        default 6 if ARM_L1_CACHE_SHIFT_6
         default 5
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index b270d6228fe2..edddd66faac6 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -11,6 +11,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/moduleparam.h>
 #include <linux/compiler.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
@@ -77,6 +78,8 @@ static unsigned long ai_dword;
 static unsigned long ai_multi;
 static int ai_usermode;
 
+core_param(alignment, ai_usermode, int, 0600);
+
 #define UM_WARN         (1 << 0)
 #define UM_FIXUP        (1 << 1)
 #define UM_SIGNAL       (1 << 2)
@@ -898,11 +901,7 @@ static int __init alignment_init(void)
 #ifdef CONFIG_PROC_FS
         struct proc_dir_entry *res;
 
-        res = proc_mkdir("cpu", NULL);
-        if (!res)
-                return -ENOMEM;
-
-        res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
+        res = create_proc_entry("cpu/alignment", S_IWUSR | S_IRUGO, NULL);
         if (!res)
                 return -ENOMEM;
 
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index a89444a3c016..7148e53e6078 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(fa_dma_inv_range)
+fa_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
@@ -180,7 +180,7 @@ ENTRY(fa_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(fa_dma_clean_range)
+fa_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -205,6 +205,30 @@ ENTRY(fa_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(fa_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     fa_dma_clean_range
+        bcs     fa_dma_inv_range
+        b       fa_dma_flush_range
+ENDPROC(fa_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(fa_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(fa_dma_unmap_area)
+
         __INITDATA
 
         .type   fa_cache_fns, #object
@@ -215,7 +239,7 @@ ENTRY(fa_cache_fns)
         .long   fa_coherent_kern_range
         .long   fa_coherent_user_range
         .long   fa_flush_kern_dcache_area
-        .long   fa_dma_inv_range
-        .long   fa_dma_clean_range
+        .long   fa_dma_map_area
+        .long   fa_dma_unmap_area
         .long   fa_dma_flush_range
         .size   fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index cb8fc6573b1b..07334632d3e2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -42,6 +42,57 @@ static inline void cache_sync(void)
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
+static inline void l2x0_clean_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+}
+
+static inline void l2x0_inv_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+
+#ifdef CONFIG_PL310_ERRATA_588369
+static void debug_writel(unsigned long val)
+{
+        extern void omap_smc1(u32 fn, u32 arg);
+
+        /*
+         * Texas Instrument secure monitor api to modify the
+         * PL310 Debug Control Register.
+         */
+        omap_smc1(0x100, val);
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+
+        /* Clean by PA followed by Invalidate by PA */
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+#else
+
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
+}
+#endif
+
 static inline void l2x0_inv_all(void)
 {
         unsigned long flags;
@@ -62,23 +113,24 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
         spin_lock_irqsave(&l2x0_lock, flags);
         if (start & (CACHE_LINE_SIZE - 1)) {
                 start &= ~(CACHE_LINE_SIZE - 1);
-                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                debug_writel(0x03);
+                l2x0_flush_line(start);
+                debug_writel(0x00);
                 start += CACHE_LINE_SIZE;
         }
 
         if (end & (CACHE_LINE_SIZE - 1)) {
                 end &= ~(CACHE_LINE_SIZE - 1);
-                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                writel(end, base + L2X0_CLEAN_INV_LINE_PA);
+                debug_writel(0x03);
+                l2x0_flush_line(end);
+                debug_writel(0x00);
         }
 
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_INV_LINE_PA, 1);
-                        writel(start, base + L2X0_INV_LINE_PA);
+                        l2x0_inv_line(start);
                         start += CACHE_LINE_SIZE;
                 }
 
@@ -103,8 +155,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-                        writel(start, base + L2X0_CLEAN_LINE_PA);
+                        l2x0_clean_line(start);
                         start += CACHE_LINE_SIZE;
                 }
 
@@ -128,11 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
+                debug_writel(0x03);
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                        writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                        l2x0_flush_line(start);
                         start += CACHE_LINE_SIZE;
                 }
+                debug_writel(0x00);
 
                 if (blk_end < end) {
                         spin_unlock_irqrestore(&l2x0_lock, flags);
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 2a482731ea36..c2ff3c599fee 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -84,20 +84,6 @@ ENTRY(v3_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
- *      dma_inv_range(start, end)
- *
- *      Invalidate (discard) the specified virtual address range.
- *      May not write back any entries.  If 'start' or 'end'
- *      are not cache line aligned, those lines must be written
- *      back.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v3_dma_inv_range)
-        /* FALLTHROUGH */
-
-/*
  *      dma_flush_range(start, end)
  *
  *      Clean and invalidate the specified virtual address range.
@@ -108,18 +94,29 @@ ENTRY(v3_dma_inv_range)
 ENTRY(v3_dma_flush_range)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c0, 0           @ flush ID cache
+        mov     pc, lr
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v3_dma_unmap_area)
+        teq     r2, #DMA_TO_DEVICE
+        bne     v3_dma_flush_range
         /* FALLTHROUGH */
 
 /*
- *      dma_clean_range(start, end)
- *
- *      Clean (write back) the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
  */
-ENTRY(v3_dma_clean_range)
+ENTRY(v3_dma_map_area)
         mov     pc, lr
+ENDPROC(v3_dma_unmap_area)
+ENDPROC(v3_dma_map_area)
 
         __INITDATA
 
@@ -131,7 +128,7 @@ ENTRY(v3_cache_fns)
         .long   v3_coherent_kern_range
         .long   v3_coherent_user_range
         .long   v3_flush_kern_dcache_area
-        .long   v3_dma_inv_range
-        .long   v3_dma_clean_range
+        .long   v3_dma_map_area
+        .long   v3_dma_unmap_area
         .long   v3_dma_flush_range
         .size   v3_cache_fns, . - v3_cache_fns
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 5c7da3e372e9..4810f7e3e813 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -94,20 +94,6 @@ ENTRY(v4_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
- *      dma_inv_range(start, end)
- *
- *      Invalidate (discard) the specified virtual address range.
- *      May not write back any entries.  If 'start' or 'end'
- *      are not cache line aligned, those lines must be written
- *      back.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v4_dma_inv_range)
-        /* FALLTHROUGH */
-
-/*
  *      dma_flush_range(start, end)
  *
  *      Clean and invalidate the specified virtual address range.
@@ -120,18 +106,29 @@ ENTRY(v4_dma_flush_range)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
 #endif
+        mov     pc, lr
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4_dma_unmap_area)
+        teq     r2, #DMA_TO_DEVICE
+        bne     v4_dma_flush_range
         /* FALLTHROUGH */
 
 /*
- *      dma_clean_range(start, end)
- *
- *      Clean (write back) the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
  */
-ENTRY(v4_dma_clean_range)
+ENTRY(v4_dma_map_area)
         mov     pc, lr
+ENDPROC(v4_dma_unmap_area)
+ENDPROC(v4_dma_map_area)
 
         __INITDATA
 
@@ -143,7 +140,7 @@ ENTRY(v4_cache_fns)
         .long   v4_coherent_kern_range
         .long   v4_coherent_user_range
         .long   v4_flush_kern_dcache_area
-        .long   v4_dma_inv_range
-        .long   v4_dma_clean_range
+        .long   v4_dma_map_area
+        .long   v4_dma_unmap_area
         .long   v4_dma_flush_range
         .size   v4_cache_fns, . - v4_cache_fns
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 3dbedf1ec0e7..df8368afa102 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(v4wb_dma_inv_range)
+v4wb_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -194,7 +194,7 @@ ENTRY(v4wb_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(v4wb_dma_clean_range)
+v4wb_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -216,6 +216,30 @@ ENTRY(v4wb_dma_clean_range)
         .globl  v4wb_dma_flush_range
         .set    v4wb_dma_flush_range, v4wb_coherent_kern_range
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wb_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     v4wb_dma_clean_range
+        bcs     v4wb_dma_inv_range
+        b       v4wb_dma_flush_range
+ENDPROC(v4wb_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wb_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(v4wb_dma_unmap_area)
+
         __INITDATA
 
         .type   v4wb_cache_fns, #object
@@ -226,7 +250,7 @@ ENTRY(v4wb_cache_fns)
         .long   v4wb_coherent_kern_range
         .long   v4wb_coherent_user_range
         .long   v4wb_flush_kern_dcache_area
-        .long   v4wb_dma_inv_range
-        .long   v4wb_dma_clean_range
+        .long   v4wb_dma_map_area
+        .long   v4wb_dma_unmap_area
         .long   v4wb_dma_flush_range
         .size   v4wb_cache_fns, . - v4wb_cache_fns
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index b3b7410270b4..45c70312f43b 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -142,23 +142,12 @@ ENTRY(v4wt_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(v4wt_dma_inv_range)
+v4wt_dma_inv_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
         blo     1b
-        /* FALLTHROUGH */
-
-/*
- *      dma_clean_range(start, end)
- *
- *      Clean the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v4wt_dma_clean_range)
         mov     pc, lr
 
 /*
@@ -172,6 +161,29 @@ ENTRY(v4wt_dma_clean_range)
         .globl  v4wt_dma_flush_range
         .equ    v4wt_dma_flush_range, v4wt_dma_inv_range
 
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wt_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v4wt_dma_inv_range
+        /* FALLTHROUGH */
+
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wt_dma_map_area)
+        mov     pc, lr
+ENDPROC(v4wt_dma_unmap_area)
+ENDPROC(v4wt_dma_map_area)
+
         __INITDATA
 
         .type   v4wt_cache_fns, #object
@@ -182,7 +194,7 @@ ENTRY(v4wt_cache_fns)
         .long   v4wt_coherent_kern_range
         .long   v4wt_coherent_user_range
         .long   v4wt_flush_kern_dcache_area
-        .long   v4wt_dma_inv_range
-        .long   v4wt_dma_clean_range
+        .long   v4wt_dma_map_area
+        .long   v4wt_dma_unmap_area
         .long   v4wt_dma_flush_range
         .size   v4wt_cache_fns, . - v4wt_cache_fns
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 4ba0a24ce6f5..9d89c67a1cc3 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v6_dma_inv_range)
+v6_dma_inv_range:
         tst     r0, #D_CACHE_LINE_SIZE - 1
         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -228,7 +228,7 @@ ENTRY(v6_dma_inv_range)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v6_dma_clean_range)
+v6_dma_clean_range:
         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef HARVARD_CACHE
@@ -263,6 +263,32 @@ ENTRY(v6_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v6_dma_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v6_dma_inv_range
+        b       v6_dma_clean_range
+ENDPROC(v6_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v6_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v6_dma_inv_range
+        mov     pc, lr
+ENDPROC(v6_dma_unmap_area)
+
         __INITDATA
 
         .type   v6_cache_fns, #object
@@ -273,7 +299,7 @@ ENTRY(v6_cache_fns)
         .long   v6_coherent_kern_range
         .long   v6_coherent_user_range
         .long   v6_flush_kern_dcache_area
-        .long   v6_dma_inv_range
-        .long   v6_dma_clean_range
+        .long   v6_dma_map_area
+        .long   v6_dma_unmap_area
         .long   v6_dma_flush_range
         .size   v6_cache_fns, . - v6_cache_fns
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 9073db849fb4..bcd64f265870 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -216,7 +216,7 @@ ENDPROC(v7_flush_kern_dcache_area)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v7_dma_inv_range)
+v7_dma_inv_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         tst     r0, r3
@@ -240,7 +240,7 @@ ENDPROC(v7_dma_inv_range)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v7_dma_clean_range)
+v7_dma_clean_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
@@ -271,6 +271,32 @@ ENTRY(v7_dma_flush_range)
         mov     pc, lr
 ENDPROC(v7_dma_flush_range)
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v7_dma_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v7_dma_inv_range
+        b       v7_dma_clean_range
+ENDPROC(v7_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v7_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v7_dma_inv_range
+        mov     pc, lr
+ENDPROC(v7_dma_unmap_area)
+
         __INITDATA
 
         .type   v7_cache_fns, #object
@@ -281,7 +307,7 @@ ENTRY(v7_cache_fns)
         .long   v7_coherent_kern_range
         .long   v7_coherent_user_range
         .long   v7_flush_kern_dcache_area
-        .long   v7_dma_inv_range
-        .long   v7_dma_clean_range
+        .long   v7_dma_map_area
+        .long   v7_dma_unmap_area
         .long   v7_dma_flush_range
         .size   v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a9e22e31eaa1..b0ee9ba3cfab 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -10,12 +10,17 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/percpu.h>
 
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
 
 static DEFINE_SPINLOCK(cpu_asid_lock);
 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
+#ifdef CONFIG_SMP
+DEFINE_PER_CPU(struct mm_struct *, current_mm);
+#endif
 
 /*
  * We fork()ed a process, and we need a new context for the child
@@ -26,13 +31,109 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
         mm->context.id = 0;
+        spin_lock_init(&mm->context.id_lock);
 }
 
+static void flush_context(void)
+{
+        /* set the reserved ASID before flushing the TLB */
+        asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (0));
+        isb();
+        local_flush_tlb_all();
+        if (icache_is_vivt_asid_tagged()) {
+                __flush_icache_all();
+                dsb();
+        }
+}
+
+#ifdef CONFIG_SMP
+
+static void set_mm_context(struct mm_struct *mm, unsigned int asid)
+{
+        unsigned long flags;
+
+        /*
+         * Locking needed for multi-threaded applications where the
+         * same mm->context.id could be set from different CPUs during
+         * the broadcast. This function is also called via IPI so the
+         * mm->context.id_lock has to be IRQ-safe.
+         */
+        spin_lock_irqsave(&mm->context.id_lock, flags);
+        if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
+                /*
+                 * Old version of ASID found. Set the new one and
+                 * reset mm_cpumask(mm).
+                 */
+                mm->context.id = asid;
+                cpumask_clear(mm_cpumask(mm));
+        }
+        spin_unlock_irqrestore(&mm->context.id_lock, flags);
+
+        /*
+         * Set the mm_cpumask(mm) bit for the current CPU.
+         */
+        cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+}
+
+/*
+ * Reset the ASID on the current CPU. This function call is broadcast
+ * from the CPU handling the ASID rollover and holding cpu_asid_lock.
+ */
+static void reset_context(void *info)
+{
+        unsigned int asid;
+        unsigned int cpu = smp_processor_id();
+        struct mm_struct *mm = per_cpu(current_mm, cpu);
+
+        /*
+         * Check if a current_mm was set on this CPU as it might still
+         * be in the early booting stages and using the reserved ASID.
+         */
+        if (!mm)
+                return;
+
+        smp_rmb();
+        asid = cpu_last_asid + cpu + 1;
+
+        flush_context();
+        set_mm_context(mm, asid);
+
+        /* set the new ASID */
+        asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id));
+        isb();
+}
+
+#else
+
+static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
+{
+        mm->context.id = asid;
+        cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
+}
+
+#endif
+
 void __new_context(struct mm_struct *mm)
 {
         unsigned int asid;
 
         spin_lock(&cpu_asid_lock);
+#ifdef CONFIG_SMP
+        /*
+         * Check the ASID again, in case the change was broadcast from
+         * another CPU before we acquired the lock.
+         */
+        if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
+                cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+                spin_unlock(&cpu_asid_lock);
+                return;
+        }
+#endif
+        /*
+         * At this point, it is guaranteed that the current mm (with
+         * an old ASID) isn't active on any other CPU since the ASIDs
+         * are changed simultaneously via IPI.
+         */
         asid = ++cpu_last_asid;
         if (asid == 0)
                 asid = cpu_last_asid = ASID_FIRST_VERSION;
@@ -42,20 +143,15 @@ void __new_context(struct mm_struct *mm)
          * to start a new version and flush the TLB.
          */
         if (unlikely((asid & ~ASID_MASK) == 0)) {
-                asid = ++cpu_last_asid;
-                /* set the reserved ASID before flushing the TLB */
-                asm("mcr        p15, 0, %0, c13, c0, 1  @ set reserved context ID\n"
-                    :
-                    : "r" (0));
-                isb();
-                flush_tlb_all();
-                if (icache_is_vivt_asid_tagged()) {
-                        __flush_icache_all();
-                        dsb();
-                }
+                asid = cpu_last_asid + smp_processor_id() + 1;
+                flush_context();
+#ifdef CONFIG_SMP
+                smp_wmb();
+                smp_call_function(reset_context, NULL, 1);
+#endif
+                cpu_last_asid += NR_CPUS;
         }
-        spin_unlock(&cpu_asid_lock);
 
-        cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
-        mm->context.id = asid;
+        set_mm_context(mm, asid);
+        spin_unlock(&cpu_asid_lock);
 }
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c
index 70997d5bee2d..5eb4fd93893d 100644
--- a/arch/arm/mm/copypage-feroceon.c
+++ b/arch/arm/mm/copypage-feroceon.c
@@ -68,12 +68,13 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
 }
 
 void feroceon_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
         kto = kmap_atomic(to, KM_USER0);
         kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
         feroceon_copy_user_page(kto, kfrom);
         kunmap_atomic(kfrom, KM_USER1);
         kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
index de9c06854ad7..f72303e1d804 100644
--- a/arch/arm/mm/copypage-v3.c
+++ b/arch/arm/mm/copypage-v3.c
@@ -38,7 +38,7 @@ v3_copy_user_page(void *kto, const void *kfrom)
 }
 
 void v3_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 7370a7142b04..598c51ad5071 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -69,7 +69,7 @@ mc_copy_user_page(void *from, void *to)
 }
 
 void v4_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
index 9ab098414227..7c2eb55cd4a9 100644
--- a/arch/arm/mm/copypage-v4wb.c
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -48,12 +48,13 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
 }
 
 void v4wb_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
         kto = kmap_atomic(to, KM_USER0);
         kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
         v4wb_copy_user_page(kto, kfrom);
         kunmap_atomic(kfrom, KM_USER1);
         kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index 300efafd6643..172e6a55458e 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -44,7 +44,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
 }
 
 void v4wt_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 0fa1319273de..8bca4dea6dfa 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -34,7 +34,7 @@ static DEFINE_SPINLOCK(v6_lock);
  * attack the kernel's existing mapping of these pages.
  */
 static void v6_copy_user_highpage_nonaliasing(struct page *to,
-        struct page *from, unsigned long vaddr)
+        struct page *from, unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
@@ -81,7 +81,7 @@ static void discard_old_kernel_data(void *kto)
  * Copy the page, taking account of the cache colour.
  */
 static void v6_copy_user_highpage_aliasing(struct page *to,
-        struct page *from, unsigned long vaddr)
+        struct page *from, unsigned long vaddr, struct vm_area_struct *vma)
 {
         unsigned int offset = CACHE_COLOUR(vaddr);
         unsigned long kfrom, kto;
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c
index bc4525f5ab23..747ad4140fc7 100644
--- a/arch/arm/mm/copypage-xsc3.c
+++ b/arch/arm/mm/copypage-xsc3.c
@@ -71,12 +71,13 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
 }
 
 void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
         kto = kmap_atomic(to, KM_USER0);
         kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
         xsc3_mc_copy_user_page(kto, kfrom);
         kunmap_atomic(kfrom, KM_USER1);
         kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 76824d3e966a..9920c0ae2096 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -91,7 +91,7 @@ mc_copy_user_page(void *from, void *to)
 }
 
 void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 26325cb5d368..0da7eccf7749 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -29,9 +29,6 @@
 #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
 #endif
 
-#define CONSISTENT_END  (0xffe00000)
-#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE)
-
 #define CONSISTENT_OFFSET(x)    (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
@@ -404,78 +401,44 @@ EXPORT_SYMBOL(dma_free_coherent);
  * platforms with CONFIG_DMABOUNCE.
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
-void dma_cache_maint(const void *start, size_t size, int direction)
+void ___dma_single_cpu_to_dev(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
 {
-        void (*inner_op)(const void *, const void *);
-        void (*outer_op)(unsigned long, unsigned long);
-
-        BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1));
-
-        switch (direction) {
-        case DMA_FROM_DEVICE:           /* invalidate only */
-                inner_op = dmac_inv_range;
-                outer_op = outer_inv_range;
-                break;
-        case DMA_TO_DEVICE:             /* writeback only */
-                inner_op = dmac_clean_range;
-                outer_op = outer_clean_range;
-                break;
-        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                inner_op = dmac_flush_range;
-                outer_op = outer_flush_range;
-                break;
-        default:
-                BUG();
-        }
+        unsigned long paddr;
+
+        BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
 
-        inner_op(start, start + size);
-        outer_op(__pa(start), __pa(start) + size);
+        dmac_map_area(kaddr, size, dir);
+
+        paddr = __pa(kaddr);
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(paddr, paddr + size);
+        } else {
+                outer_clean_range(paddr, paddr + size);
+        }
+        /* FIXME: non-speculating: flush on bidirectional mappings? */
 }
-EXPORT_SYMBOL(dma_cache_maint);
+EXPORT_SYMBOL(___dma_single_cpu_to_dev);
 
-static void dma_cache_maint_contiguous(struct page *page, unsigned long offset,
-                                       size_t size, int direction)
+void ___dma_single_dev_to_cpu(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
 {
-        void *vaddr;
-        unsigned long paddr;
-        void (*inner_op)(const void *, const void *);
-        void (*outer_op)(unsigned long, unsigned long);
-
-        switch (direction) {
-        case DMA_FROM_DEVICE:           /* invalidate only */
-                inner_op = dmac_inv_range;
-                outer_op = outer_inv_range;
-                break;
-        case DMA_TO_DEVICE:             /* writeback only */
-                inner_op = dmac_clean_range;
-                outer_op = outer_clean_range;
-                break;
-        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                inner_op = dmac_flush_range;
-                outer_op = outer_flush_range;
-                break;
-        default:
-                BUG();
-        }
+        BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
 
-        if (!PageHighMem(page)) {
-                vaddr = page_address(page) + offset;
-                inner_op(vaddr, vaddr + size);
-        } else {
-                vaddr = kmap_high_get(page);
-                if (vaddr) {
-                        vaddr += offset;
-                        inner_op(vaddr, vaddr + size);
-                        kunmap_high(page);
-                }
+        /* FIXME: non-speculating: not required */
+        /* don't bother invalidating if DMA to device */
+        if (dir != DMA_TO_DEVICE) {
+                unsigned long paddr = __pa(kaddr);
+                outer_inv_range(paddr, paddr + size);
         }
 
-        paddr = page_to_phys(page) + offset;
-        outer_op(paddr, paddr + size);
+        dmac_unmap_area(kaddr, size, dir);
 }
+EXPORT_SYMBOL(___dma_single_dev_to_cpu);
 
-void dma_cache_maint_page(struct page *page, unsigned long offset,
-                          size_t size, int dir)
+static void dma_cache_maint_page(struct page *page, unsigned long offset,
+        size_t size, enum dma_data_direction dir,
+        void (*op)(const void *, size_t, int))
 {
         /*
          * A single sg entry may refer to multiple physically contiguous
@@ -486,20 +449,62 @@ void dma_cache_maint_page(struct page *page, unsigned long offset,
         size_t left = size;
         do {
                 size_t len = left;
-                if (PageHighMem(page) && len + offset > PAGE_SIZE) {
-                        if (offset >= PAGE_SIZE) {
-                                page += offset / PAGE_SIZE;
-                                offset %= PAGE_SIZE;
+                void *vaddr;
+
+                if (PageHighMem(page)) {
+                        if (len + offset > PAGE_SIZE) {
+                                if (offset >= PAGE_SIZE) {
+                                        page += offset / PAGE_SIZE;
+                                        offset %= PAGE_SIZE;
+                                }
+                                len = PAGE_SIZE - offset;
                         }
-                        len = PAGE_SIZE - offset;
+                        vaddr = kmap_high_get(page);
+                        if (vaddr) {
+                                vaddr += offset;
+                                op(vaddr, len, dir);
+                                kunmap_high(page);
+                        }
+                } else {
+                        vaddr = page_address(page) + offset;
+                        op(vaddr, len, dir);
                 }
-                dma_cache_maint_contiguous(page, offset, len, dir);
                 offset = 0;
                 page++;
                 left -= len;
         } while (left);
 }
-EXPORT_SYMBOL(dma_cache_maint_page);
+
+void ___dma_page_cpu_to_dev(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        unsigned long paddr;
+
+        dma_cache_maint_page(page, off, size, dir, dmac_map_area);
+
+        paddr = page_to_phys(page) + off;
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(paddr, paddr + size);
+        } else {
+                outer_clean_range(paddr, paddr + size);
+        }
+        /* FIXME: non-speculating: flush on bidirectional mappings? */
+}
+EXPORT_SYMBOL(___dma_page_cpu_to_dev);
+
+void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        unsigned long paddr = page_to_phys(page) + off;
+
+        /* FIXME: non-speculating: not required */
+        /* don't bother invalidating if DMA to device */
+        if (dir != DMA_TO_DEVICE)
+                outer_inv_range(paddr, paddr + size);
+
+        dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+}
+EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
 /**
  * dma_map_sg - map a set of SG buffers for streaming mode DMA
@@ -573,8 +578,12 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
         int i;
 
         for_each_sg(sg, s, nents, i) {
-                dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
-                                        sg_dma_len(s), dir);
+                if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
+                                            sg_dma_len(s), dir))
+                        continue;
+
+                __dma_page_dev_to_cpu(sg_page(s), s->offset,
+                                      s->length, dir);
         }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_cpu);
@@ -597,9 +606,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
                                         sg_dma_len(s), dir))
                         continue;
 
-                if (!arch_is_coherent())
-                        dma_cache_maint_page(sg_page(s), s->offset,
-                                             s->length, dir);
+                __dma_page_cpu_to_dev(sg_page(s), s->offset,
+                                      s->length, dir);
         }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 56ee15321b00..c9b97e9836a2 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -36,28 +36,12 @@ static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
  * Therefore those configurations which might call adjust_pte (those
  * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
  */
-static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
+static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
+        unsigned long pfn, pte_t *ptep)
 {
-        pgd_t *pgd;
-        pmd_t *pmd;
-        pte_t *pte, entry;
+        pte_t entry = *ptep;
         int ret;
 
-        pgd = pgd_offset(vma->vm_mm, address);
-        if (pgd_none(*pgd))
-                goto no_pgd;
-        if (pgd_bad(*pgd))
-                goto bad_pgd;
-
-        pmd = pmd_offset(pgd, address);
-        if (pmd_none(*pmd))
-                goto no_pmd;
-        if (pmd_bad(*pmd))
-                goto bad_pmd;
-
-        pte = pte_offset_map(pmd, address);
-        entry = *pte;
-
         /*
          * If this page is present, it's actually being shared.
          */
@@ -68,33 +52,55 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
          * fault (ie, is old), we can safely ignore any issues.
          */
         if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
-                unsigned long pfn = pte_pfn(entry);
                 flush_cache_page(vma, address, pfn);
                 outer_flush_range((pfn << PAGE_SHIFT),
                                   (pfn << PAGE_SHIFT) + PAGE_SIZE);
                 pte_val(entry) &= ~L_PTE_MT_MASK;
                 pte_val(entry) |= shared_pte_mask;
-                set_pte_at(vma->vm_mm, address, pte, entry);
+                set_pte_at(vma->vm_mm, address, ptep, entry);
                 flush_tlb_page(vma, address);
         }
-        pte_unmap(pte);
+
         return ret;
+}
+
+static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
+        unsigned long pfn)
+{
+        spinlock_t *ptl;
+        pgd_t *pgd;
+        pmd_t *pmd;
+        pte_t *pte;
+        int ret;
+
+        pgd = pgd_offset(vma->vm_mm, address);
+        if (pgd_none_or_clear_bad(pgd))
+                return 0;
+
+        pmd = pmd_offset(pgd, address);
+        if (pmd_none_or_clear_bad(pmd))
+                return 0;
 
-bad_pgd:
-        pgd_ERROR(*pgd);
-        pgd_clear(pgd);
-no_pgd:
-        return 0;
-
-bad_pmd:
-        pmd_ERROR(*pmd);
-        pmd_clear(pmd);
-no_pmd:
-        return 0;
+        /*
+         * This is called while another page table is mapped, so we
+         * must use the nested version.  This also means we need to
+         * open-code the spin-locking.
+         */
+        ptl = pte_lockptr(vma->vm_mm, pmd);
+        pte = pte_offset_map_nested(pmd, address);
+        spin_lock(ptl);
+
+        ret = do_adjust_pte(vma, address, pfn, pte);
+
+        spin_unlock(ptl);
+        pte_unmap_nested(pte);
+
+        return ret;
 }
 
 static void
-make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
+make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
+        unsigned long addr, pte_t *ptep, unsigned long pfn)
 {
         struct mm_struct *mm = vma->vm_mm;
         struct vm_area_struct *mpnt;
@@ -122,11 +128,11 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne
                 if (!(mpnt->vm_flags & VM_MAYSHARE))
                         continue;
                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
-                aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
+                aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
         }
         flush_dcache_mmap_unlock(mapping);
         if (aliases)
-                adjust_pte(vma, addr);
+                do_adjust_pte(vma, addr, pfn, ptep);
         else
                 flush_cache_page(vma, addr, pfn);
 }
@@ -144,9 +150,10 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne
  *
  * Note that the pte lock will be held.
  */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+        pte_t *ptep)
 {
-        unsigned long pfn = pte_pfn(pte);
+        unsigned long pfn = pte_pfn(*ptep);
         struct address_space *mapping;
         struct page *page;
 
@@ -168,7 +175,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 #endif
         if (mapping) {
                 if (cache_is_vivt())
-                        make_coherent(mapping, vma, addr, pfn);
+                        make_coherent(mapping, vma, addr, ptep, pfn);
                 else if (vma->vm_flags & VM_EXEC)
                         __flush_icache_all();
         }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 10e06801afb3..9d40c341e07e 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -18,6 +18,7 @@
 #include <linux/page-flags.h>
 #include <linux/sched.h>
 #include <linux/highmem.h>
+#include <linux/perf_event.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -302,6 +303,12 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         fault = __do_page_fault(mm, addr, fsr, tsk);
         up_read(&mm->mmap_sem);
 
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, addr);
+        if (fault & VM_FAULT_MAJOR)
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, regs, addr);
+        else if (fault & VM_FAULT_MINOR)
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, regs, addr);
+
         /*
          * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
          */
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 6f3a4b7a3b82..e34f095e2090 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -13,6 +13,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
+#include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
 
@@ -87,13 +88,26 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
         if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
                 __flush_icache_all();
 }
+#else
+#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+#endif
 
+#ifdef CONFIG_SMP
+static void flush_ptrace_access_other(void *args)
+{
+        __flush_icache_all();
+}
+#endif
+
+static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                         unsigned long uaddr, void *kaddr,
-                         unsigned long len, int write)
+                         unsigned long uaddr, void *kaddr, unsigned long len)
 {
         if (cache_is_vivt()) {
-                vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write);
+                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+                        unsigned long addr = (unsigned long)kaddr;
+                        __cpuc_coherent_kern_range(addr, addr + len);
+                }
                 return;
         }
 
@@ -104,16 +118,37 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
         }
 
         /* VIPT non-aliasing cache */
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) &&
-            vma->vm_flags & VM_EXEC) {
+        if (vma->vm_flags & VM_EXEC) {
                 unsigned long addr = (unsigned long)kaddr;
-                /* only flushing the kernel mapping on non-aliasing VIPT */
                 __cpuc_coherent_kern_range(addr, addr + len);
+#ifdef CONFIG_SMP
+                if (cache_ops_need_broadcast())
+                        smp_call_function(flush_ptrace_access_other,
+                                          NULL, 1);
+#endif
         }
 }
-#else
-#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+
+/*
+ * Copy user data from/to a page which is mapped into a different
+ * processes address space.  Really, we want to allow our "user
+ * space" model to handle this.
+ *
+ * Note that this code needs to run on the current CPU.
+ */
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                       unsigned long uaddr, void *dst, const void *src,
+                       unsigned long len)
+{
+#ifdef CONFIG_SMP
+        preempt_disable();
 #endif
+        memcpy(dst, src, len);
+        flush_ptrace_access(vma, page, uaddr, dst, len);
+#ifdef CONFIG_SMP
+        preempt_enable();
+#endif
+}
 
 void __flush_dcache_page(struct address_space *mapping, struct page *page)
 {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index a04ffbbbe253..7829cb5425f5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -23,6 +23,7 @@
 #include <asm/setup.h>
 #include <asm/sizes.h>
 #include <asm/tlb.h>
+#include <asm/fixmap.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,19 +33,21 @@
 static unsigned long phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
-static void __init early_initrd(char **p)
+static int __init early_initrd(char *p)
 {
         unsigned long start, size;
+        char *endp;
 
-        start = memparse(*p, p);
-        if (**p == ',') {
-                size = memparse((*p) + 1, p);
+        start = memparse(p, &endp);
+        if (*endp == ',') {
+                size = memparse(endp + 1, NULL);
 
                 phys_initrd_start = start;
                 phys_initrd_size = size;
         }
+        return 0;
 }
-__early_param("initrd=", early_initrd);
+early_param("initrd", early_initrd);
 
 static int __init parse_tag_initrd(const struct tag *tag)
 {
@@ -560,7 +563,7 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
  */
 void __init mem_init(void)
 {
-        unsigned int codesize, datasize, initsize;
+        unsigned long reserved_pages, free_pages;
         int i, node;
 
 #ifndef CONFIG_DISCONTIGMEM
@@ -596,6 +599,33 @@ void __init mem_init(void)
         totalram_pages += totalhigh_pages;
 #endif
 
+        reserved_pages = free_pages = 0;
+
+        for_each_online_node(node) {
+                pg_data_t *n = NODE_DATA(node);
+                struct page *map = pgdat_page_nr(n, 0) - n->node_start_pfn;
+
+                for_each_nodebank(i, &meminfo, node) {
+                        struct membank *bank = &meminfo.bank[i];
+                        unsigned int pfn1, pfn2;
+                        struct page *page, *end;
+
+                        pfn1 = bank_pfn_start(bank);
+                        pfn2 = bank_pfn_end(bank);
+
+                        page = map + pfn1;
+                        end  = map + pfn2;
+
+                        do {
+                                if (PageReserved(page))
+                                        reserved_pages++;
+                                else if (!page_count(page))
+                                        free_pages++;
+                                page++;
+                        } while (page < end);
+                }
+        }
+
         /*
          * Since our memory may not be contiguous, calculate the
          * real number of pages we have in this system
@@ -608,16 +638,71 @@ void __init mem_init(void)
         }
         printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
 
-        codesize = _etext - _text;
-        datasize = _end - _data;
-        initsize = __init_end - __init_begin;
-
-        printk(KERN_NOTICE "Memory: %luKB available (%dK code, "
-                "%dK data, %dK init, %luK highmem)\n",
-                nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10,
-                datasize >> 10, initsize >> 10,
+        printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
+                nr_free_pages() << (PAGE_SHIFT-10),
+                free_pages << (PAGE_SHIFT-10),
+                reserved_pages << (PAGE_SHIFT-10),
                 totalhigh_pages << (PAGE_SHIFT-10));
 
+#define MLK(b, t) b, t, ((t) - (b)) >> 10
+#define MLM(b, t) b, t, ((t) - (b)) >> 20
+#define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K)
+
+        printk(KERN_NOTICE "Virtual kernel memory layout:\n"
+                        "    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+                        "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#ifdef CONFIG_MMU
+                        "    DMA     : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+#endif
+                        "    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+                        "    lowmem  : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+#ifdef CONFIG_HIGHMEM
+                        "    pkmap   : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+#endif
+                        "    modules : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+                        "      .init : 0x%p" " - 0x%p" "   (%4d kB)\n"
+                        "      .text : 0x%p" " - 0x%p" "   (%4d kB)\n"
+                        "      .data : 0x%p" " - 0x%p" "   (%4d kB)\n",
+
+                        MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
+                                (PAGE_SIZE)),
+                        MLK(FIXADDR_START, FIXADDR_TOP),
+#ifdef CONFIG_MMU
+                        MLM(CONSISTENT_BASE, CONSISTENT_END),
+#endif
+                        MLM(VMALLOC_START, VMALLOC_END),
+                        MLM(PAGE_OFFSET, (unsigned long)high_memory),
+#ifdef CONFIG_HIGHMEM
+                        MLM(PKMAP_BASE, (PKMAP_BASE) + (LAST_PKMAP) *
+                                (PAGE_SIZE)),
+#endif
+                        MLM(MODULES_VADDR, MODULES_END),
+
+                        MLK_ROUNDUP(__init_begin, __init_end),
+                        MLK_ROUNDUP(_text, _etext),
+                        MLK_ROUNDUP(_data, _edata));
+
+#undef MLK
+#undef MLM
+#undef MLK_ROUNDUP
+
+        /*
+         * Check boundaries twice: Some fundamental inconsistencies can
+         * be detected at build time already.
+         */
+#ifdef CONFIG_MMU
+        BUILD_BUG_ON(VMALLOC_END                        > CONSISTENT_BASE);
+        BUG_ON(VMALLOC_END                              > CONSISTENT_BASE);
+
+        BUILD_BUG_ON(TASK_SIZE                          > MODULES_VADDR);
+        BUG_ON(TASK_SIZE                                > MODULES_VADDR);
+#endif
+
+#ifdef CONFIG_HIGHMEM
+        BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > PAGE_OFFSET);
+        BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE      > PAGE_OFFSET);
+#endif
+
         if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
                 extern int sysctl_overcommit_memory;
                 /*
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 0ab75c60f7cf..28c8b950ef04 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -139,8 +139,8 @@ void __check_kvm_seq(struct mm_struct *mm)
  * which requires the new ioremap'd region to be referenced, the CPU will
  * reference the _old_ region.
  *
- * Note that get_vm_area() allocates a guard 4K page, so we need to mask
- * the size back to 1MB aligned or we will overflow in the loop below.
+ * Note that get_vm_area_caller() allocates a guard 4K page, so we need to
+ * mask the size back to 1MB aligned or we will overflow in the loop below.
  */
 static void unmap_area_sections(unsigned long virt, unsigned long size)
 {
@@ -254,22 +254,8 @@ remap_area_supersections(unsigned long virt, unsigned long pfn,
 }
 #endif
 
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- *
- * 'flags' are the extra L_PTE_ flags that you want to specify for this
- * mapping.  See <asm/pgtable.h> for more information.
- */
-void __iomem *
-__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
-                  unsigned int mtype)
+void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
+        unsigned long offset, size_t size, unsigned int mtype, void *caller)
 {
         const struct mem_type *type;
         int err;
@@ -291,7 +277,7 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
          */
         size = PAGE_ALIGN(offset + size);
 
-        area = get_vm_area(size, VM_IOREMAP);
+        area = get_vm_area_caller(size, VM_IOREMAP, caller);
         if (!area)
                 return NULL;
         addr = (unsigned long)area->addr;
@@ -318,10 +304,9 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
         flush_cache_vmap(addr, addr + size);
         return (void __iomem *) (offset + addr);
 }
-EXPORT_SYMBOL(__arm_ioremap_pfn);
 
-void __iomem *
-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+        unsigned int mtype, void *caller)
 {
         unsigned long last_addr;
         unsigned long offset = phys_addr & ~PAGE_MASK;
@@ -334,7 +319,33 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
         if (!size || last_addr < phys_addr)
                 return NULL;
 
-        return __arm_ioremap_pfn(pfn, offset, size, mtype);
+        return __arm_ioremap_pfn_caller(pfn, offset, size, mtype,
+                        caller);
+}
+
+/*
+ * Remap an arbitrary physical address space into the kernel virtual
+ * address space. Needed when the kernel wants to access high addresses
+ * directly.
+ *
+ * NOTE! We need to allow non-page-aligned mappings too: we will obviously
+ * have to convert them into an offset in a page-aligned mapping, but the
+ * caller shouldn't need to know that small detail.
+ */
+void __iomem *
+__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
+                  unsigned int mtype)
+{
+        return __arm_ioremap_pfn_caller(pfn, offset, size, mtype,
+                        __builtin_return_address(0));
+}
+EXPORT_SYMBOL(__arm_ioremap_pfn);
+
+void __iomem *
+__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+{
+        return __arm_ioremap_caller(phys_addr, size, mtype,
+                        __builtin_return_address(0));
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 761ffede6a23..9d4da6ac28eb 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -100,18 +100,17 @@ static struct cachepolicy cache_policies[] __initdata = {
  * writebuffer to be turned off.  (Note: the write
  * buffer should not be on and the cache off).
  */
-static void __init early_cachepolicy(char **p)
+static int __init early_cachepolicy(char *p)
 {
         int i;
 
         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
                 int len = strlen(cache_policies[i].policy);
 
-                if (memcmp(*p, cache_policies[i].policy, len) == 0) {
+                if (memcmp(p, cache_policies[i].policy, len) == 0) {
                         cachepolicy = i;
                         cr_alignment &= ~cache_policies[i].cr_mask;
                         cr_no_alignment &= ~cache_policies[i].cr_mask;
-                        *p += len;
                         break;
                 }
         }
@@ -130,36 +129,37 @@ static void __init early_cachepolicy(char **p)
         }
         flush_cache_all();
         set_cr(cr_alignment);
+        return 0;
 }
-__early_param("cachepolicy=", early_cachepolicy);
+early_param("cachepolicy", early_cachepolicy);
 
-static void __init early_nocache(char **__unused)
+static int __init early_nocache(char *__unused)
 {
         char *p = "buffered";
         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
-        early_cachepolicy(&p);
+        early_cachepolicy(p);
+        return 0;
 }
-__early_param("nocache", early_nocache);
+early_param("nocache", early_nocache);
 
-static void __init early_nowrite(char **__unused)
+static int __init early_nowrite(char *__unused)
 {
         char *p = "uncached";
         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
-        early_cachepolicy(&p);
+        early_cachepolicy(p);
+        return 0;
 }
-__early_param("nowb", early_nowrite);
+early_param("nowb", early_nowrite);
 
-static void __init early_ecc(char **p)
+static int __init early_ecc(char *p)
 {
-        if (memcmp(*p, "on", 2) == 0) {
+        if (memcmp(p, "on", 2) == 0)
                 ecc_mask = PMD_PROTECTION;
-                *p += 2;
-        } else if (memcmp(*p, "off", 3) == 0) {
+        else if (memcmp(p, "off", 3) == 0)
                 ecc_mask = 0;
-                *p += 3;
-        }
+        return 0;
 }
-__early_param("ecc=", early_ecc);
+early_param("ecc", early_ecc);
 
 static int __init noalign_setup(char *__unused)
 {
@@ -670,9 +670,9 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M;
  * bytes. This can be used to increase (or decrease) the vmalloc
  * area - the default is 128m.
  */
-static void __init early_vmalloc(char **arg)
+static int __init early_vmalloc(char *arg)
 {
-        vmalloc_reserve = memparse(*arg, arg);
+        vmalloc_reserve = memparse(arg, NULL);
 
         if (vmalloc_reserve < SZ_16M) {
                 vmalloc_reserve = SZ_16M;
@@ -687,8 +687,9 @@ static void __init early_vmalloc(char **arg)
                         "vmalloc area is too big, limiting to %luMB\n",
                         vmalloc_reserve >> 20);
         }
+        return 0;
 }
-__early_param("vmalloc=", early_vmalloc);
+early_param("vmalloc", early_vmalloc);
 
 #define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
 
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 374a8311bc84..9bfeb6b9509a 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -74,6 +74,12 @@ void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
+void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
+                           size_t size, unsigned int mtype, void *caller)
+{
+        return __arm_ioremap_pfn(pfn, offset, size, mtype);
+}
+
 void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
                             unsigned int mtype)
 {
@@ -81,6 +87,12 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
+void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+                            unsigned int mtype, void *caller)
+{
+        return __arm_ioremap(phys_addr, size, mtype);
+}
+
 void __iounmap(volatile void __iomem *addr)
 {
 }
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 8012e24282b2..72507c630ceb 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020_dma_inv_range)
+arm1020_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -295,7 +295,7 @@ ENTRY(arm1020_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020_dma_clean_range)
+arm1020_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -330,6 +330,30 @@ ENTRY(arm1020_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1020_dma_clean_range
+        bcs     arm1020_dma_inv_range
+        b       arm1020_dma_flush_range
+ENDPROC(arm1020_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1020_dma_unmap_area)
+
 ENTRY(arm1020_cache_fns)
         .long   arm1020_flush_kern_cache_all
         .long   arm1020_flush_user_cache_all
@@ -337,8 +361,8 @@ ENTRY(arm1020_cache_fns)
         .long   arm1020_coherent_kern_range
         .long   arm1020_coherent_user_range
         .long   arm1020_flush_kern_dcache_area
-        .long   arm1020_dma_inv_range
-        .long   arm1020_dma_clean_range
+        .long   arm1020_dma_map_area
+        .long   arm1020_dma_unmap_area
         .long   arm1020_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 41fe25d234f5..d27829805609 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020e_dma_inv_range)
+arm1020e_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -284,7 +284,7 @@ ENTRY(arm1020e_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020e_dma_clean_range)
+arm1020e_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -316,6 +316,30 @@ ENTRY(arm1020e_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020e_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1020e_dma_clean_range
+        bcs     arm1020e_dma_inv_range
+        b       arm1020e_dma_flush_range
+ENDPROC(arm1020e_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020e_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1020e_dma_unmap_area)
+
 ENTRY(arm1020e_cache_fns)
         .long   arm1020e_flush_kern_cache_all
         .long   arm1020e_flush_user_cache_all
@@ -323,8 +347,8 @@ ENTRY(arm1020e_cache_fns)
         .long   arm1020e_coherent_kern_range
         .long   arm1020e_coherent_user_range
         .long   arm1020e_flush_kern_dcache_area
-        .long   arm1020e_dma_inv_range
-        .long   arm1020e_dma_clean_range
+        .long   arm1020e_dma_map_area
+        .long   arm1020e_dma_unmap_area
         .long   arm1020e_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 20a5b1b31a70..ce13e4a827de 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1022_dma_inv_range)
+arm1022_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -273,7 +273,7 @@ ENTRY(arm1022_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1022_dma_clean_range)
+arm1022_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -305,6 +305,30 @@ ENTRY(arm1022_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1022_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1022_dma_clean_range
+        bcs     arm1022_dma_inv_range
+        b       arm1022_dma_flush_range
+ENDPROC(arm1022_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1022_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1022_dma_unmap_area)
+
 ENTRY(arm1022_cache_fns)
         .long   arm1022_flush_kern_cache_all
         .long   arm1022_flush_user_cache_all
@@ -312,8 +336,8 @@ ENTRY(arm1022_cache_fns)
         .long   arm1022_coherent_kern_range
         .long   arm1022_coherent_user_range
         .long   arm1022_flush_kern_dcache_area
-        .long   arm1022_dma_inv_range
-        .long   arm1022_dma_clean_range
+        .long   arm1022_dma_map_area
+        .long   arm1022_dma_unmap_area
         .long   arm1022_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 96aedb10fcc4..636672a29c6d 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1026_dma_inv_range)
+arm1026_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -267,7 +267,7 @@ ENTRY(arm1026_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1026_dma_clean_range)
+arm1026_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -299,6 +299,30 @@ ENTRY(arm1026_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1026_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1026_dma_clean_range
+        bcs     arm1026_dma_inv_range
+        b       arm1026_dma_flush_range
+ENDPROC(arm1026_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1026_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1026_dma_unmap_area)
+
 ENTRY(arm1026_cache_fns)
         .long   arm1026_flush_kern_cache_all
         .long   arm1026_flush_user_cache_all
@@ -306,8 +330,8 @@ ENTRY(arm1026_cache_fns)
         .long   arm1026_coherent_kern_range
         .long   arm1026_coherent_user_range
         .long   arm1026_flush_kern_dcache_area
-        .long   arm1026_dma_inv_range
-        .long   arm1026_dma_clean_range
+        .long   arm1026_dma_map_area
+        .long   arm1026_dma_unmap_area
         .long   arm1026_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 471669e2d7cb..8be81992645d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm920_dma_inv_range)
+arm920_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -262,7 +262,7 @@ ENTRY(arm920_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm920_dma_clean_range)
+arm920_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -288,6 +288,30 @@ ENTRY(arm920_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm920_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm920_dma_clean_range
+        bcs     arm920_dma_inv_range
+        b       arm920_dma_flush_range
+ENDPROC(arm920_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm920_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm920_dma_unmap_area)
+
 ENTRY(arm920_cache_fns)
         .long   arm920_flush_kern_cache_all
         .long   arm920_flush_user_cache_all
@@ -295,8 +319,8 @@ ENTRY(arm920_cache_fns)
         .long   arm920_coherent_kern_range
         .long   arm920_coherent_user_range
         .long   arm920_flush_kern_dcache_area
-        .long   arm920_dma_inv_range
-        .long   arm920_dma_clean_range
+        .long   arm920_dma_map_area
+        .long   arm920_dma_unmap_area
         .long   arm920_dma_flush_range
 
 #endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index ee111b00fa41..c0ff8e4b1074 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm922_dma_inv_range)
+arm922_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -264,7 +264,7 @@ ENTRY(arm922_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm922_dma_clean_range)
+arm922_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -290,6 +290,30 @@ ENTRY(arm922_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm922_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm922_dma_clean_range
+        bcs     arm922_dma_inv_range
+        b       arm922_dma_flush_range
+ENDPROC(arm922_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm922_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm922_dma_unmap_area)
+
 ENTRY(arm922_cache_fns)
         .long   arm922_flush_kern_cache_all
         .long   arm922_flush_user_cache_all
@@ -297,8 +321,8 @@ ENTRY(arm922_cache_fns)
         .long   arm922_coherent_kern_range
         .long   arm922_coherent_user_range
         .long   arm922_flush_kern_dcache_area
-        .long   arm922_dma_inv_range
-        .long   arm922_dma_clean_range
+        .long   arm922_dma_map_area
+        .long   arm922_dma_unmap_area
         .long   arm922_dma_flush_range
 
 #endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 8deb5bde58e4..3c6cffe400f6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm925_dma_inv_range)
+arm925_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -308,7 +308,7 @@ ENTRY(arm925_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm925_dma_clean_range)
+arm925_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -341,6 +341,30 @@ ENTRY(arm925_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm925_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm925_dma_clean_range
+        bcs     arm925_dma_inv_range
+        b       arm925_dma_flush_range
+ENDPROC(arm925_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm925_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm925_dma_unmap_area)
+
 ENTRY(arm925_cache_fns)
         .long   arm925_flush_kern_cache_all
         .long   arm925_flush_user_cache_all
@@ -348,8 +372,8 @@ ENTRY(arm925_cache_fns)
         .long   arm925_coherent_kern_range
         .long   arm925_coherent_user_range
         .long   arm925_flush_kern_dcache_area
-        .long   arm925_dma_inv_range
-        .long   arm925_dma_clean_range
+        .long   arm925_dma_map_area
+        .long   arm925_dma_unmap_area
         .long   arm925_dma_flush_range
 
 ENTRY(cpu_arm925_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 64db6e275a44..75b707c9cce1 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm926_dma_inv_range)
+arm926_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -271,7 +271,7 @@ ENTRY(arm926_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm926_dma_clean_range)
+arm926_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -304,6 +304,30 @@ ENTRY(arm926_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm926_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm926_dma_clean_range
+        bcs     arm926_dma_inv_range
+        b       arm926_dma_flush_range
+ENDPROC(arm926_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm926_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm926_dma_unmap_area)
+
 ENTRY(arm926_cache_fns)
         .long   arm926_flush_kern_cache_all
         .long   arm926_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(arm926_cache_fns)
         .long   arm926_coherent_kern_range
         .long   arm926_coherent_user_range
         .long   arm926_flush_kern_dcache_area
-        .long   arm926_dma_inv_range
-        .long   arm926_dma_clean_range
+        .long   arm926_dma_map_area
+        .long   arm926_dma_unmap_area
         .long   arm926_dma_flush_range
 
 ENTRY(cpu_arm926_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 8196b9f401fb..1af1657819eb 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area)
  *      - start - virtual start address
  *      - end   - virtual end address
  */
-ENTRY(arm940_dma_inv_range)
+arm940_dma_inv_range:
         mov     ip, #0
         mov     r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -192,7 +192,7 @@ ENTRY(arm940_dma_inv_range)
  *      - start - virtual start address
  *      - end   - virtual end address
  */
-ENTRY(arm940_dma_clean_range)
+arm940_dma_clean_range:
 ENTRY(cpu_arm940_dcache_clean_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -233,6 +233,30 @@ ENTRY(arm940_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm940_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm940_dma_clean_range
+        bcs     arm940_dma_inv_range
+        b       arm940_dma_flush_range
+ENDPROC(arm940_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm940_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm940_dma_unmap_area)
+
 ENTRY(arm940_cache_fns)
         .long   arm940_flush_kern_cache_all
         .long   arm940_flush_user_cache_all
@@ -240,8 +264,8 @@ ENTRY(arm940_cache_fns)
         .long   arm940_coherent_kern_range
         .long   arm940_coherent_user_range
         .long   arm940_flush_kern_dcache_area
-        .long   arm940_dma_inv_range
-        .long   arm940_dma_clean_range
+        .long   arm940_dma_map_area
+        .long   arm940_dma_unmap_area
         .long   arm940_dma_flush_range
 
         __INIT
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 9a951239c86c..1664b6aaff79 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area)
  *      - end   - virtual end address
  * (same as arm926)
  */
-ENTRY(arm946_dma_inv_range)
+arm946_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -240,7 +240,7 @@ ENTRY(arm946_dma_inv_range)
  *
  * (same as arm926)
  */
-ENTRY(arm946_dma_clean_range)
+arm946_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -275,6 +275,30 @@ ENTRY(arm946_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm946_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm946_dma_clean_range
+        bcs     arm946_dma_inv_range
+        b       arm946_dma_flush_range
+ENDPROC(arm946_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm946_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm946_dma_unmap_area)
+
 ENTRY(arm946_cache_fns)
         .long   arm946_flush_kern_cache_all
         .long   arm946_flush_user_cache_all
@@ -282,8 +306,8 @@ ENTRY(arm946_cache_fns)
         .long   arm946_coherent_kern_range
         .long   arm946_coherent_user_range
         .long   arm946_flush_kern_dcache_area
-        .long   arm946_dma_inv_range
-        .long   arm946_dma_clean_range
+        .long   arm946_dma_map_area
+        .long   arm946_dma_unmap_area
         .long   arm946_dma_flush_range
 
 
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index dbc39383e66a..53e632343849 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
  * (same as v4wb)
  */
         .align  5
-ENTRY(feroceon_dma_inv_range)
+feroceon_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -288,7 +288,7 @@ ENTRY(feroceon_dma_inv_range)
         mov     pc, lr
 
         .align  5
-ENTRY(feroceon_range_dma_inv_range)
+feroceon_range_dma_inv_range:
         mrs     r2, cpsr
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -314,7 +314,7 @@ ENTRY(feroceon_range_dma_inv_range)
  * (same as v4wb)
  */
         .align  5
-ENTRY(feroceon_dma_clean_range)
+feroceon_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -324,7 +324,7 @@ ENTRY(feroceon_dma_clean_range)
         mov     pc, lr
 
         .align  5
-ENTRY(feroceon_range_dma_clean_range)
+feroceon_range_dma_clean_range:
         mrs     r2, cpsr
         cmp     r1, r0
         subne   r1, r1, #1                      @ top address is inclusive
@@ -367,6 +367,44 @@ ENTRY(feroceon_range_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     feroceon_dma_clean_range
+        bcs     feroceon_dma_inv_range
+        b       feroceon_dma_flush_range
+ENDPROC(feroceon_dma_map_area)
+
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_range_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     feroceon_range_dma_clean_range
+        bcs     feroceon_range_dma_inv_range
+        b       feroceon_range_dma_flush_range
+ENDPROC(feroceon_range_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(feroceon_dma_unmap_area)
+
 ENTRY(feroceon_cache_fns)
         .long   feroceon_flush_kern_cache_all
         .long   feroceon_flush_user_cache_all
@@ -374,8 +412,8 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
         .long   feroceon_flush_kern_dcache_area
-        .long   feroceon_dma_inv_range
-        .long   feroceon_dma_clean_range
+        .long   feroceon_dma_map_area
+        .long   feroceon_dma_unmap_area
         .long   feroceon_dma_flush_range
 
 ENTRY(feroceon_range_cache_fns)
@@ -385,8 +423,8 @@ ENTRY(feroceon_range_cache_fns)
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
         .long   feroceon_range_flush_kern_dcache_area
-        .long   feroceon_range_dma_inv_range
-        .long   feroceon_range_dma_clean_range
+        .long   feroceon_range_dma_map_area
+        .long   feroceon_dma_unmap_area
         .long   feroceon_range_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 9674d36cc97d..caa31154e7db 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(mohawk_dma_inv_range)
+mohawk_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
         tst     r1, #CACHE_DLINESIZE - 1
@@ -241,7 +241,7 @@ ENTRY(mohawk_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(mohawk_dma_clean_range)
+mohawk_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -268,6 +268,30 @@ ENTRY(mohawk_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(mohawk_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     mohawk_dma_clean_range
+        bcs     mohawk_dma_inv_range
+        b       mohawk_dma_flush_range
+ENDPROC(mohawk_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(mohawk_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(mohawk_dma_unmap_area)
+
 ENTRY(mohawk_cache_fns)
         .long   mohawk_flush_kern_cache_all
         .long   mohawk_flush_user_cache_all
@@ -275,8 +299,8 @@ ENTRY(mohawk_cache_fns)
         .long   mohawk_coherent_kern_range
         .long   mohawk_coherent_user_range
         .long   mohawk_flush_kern_dcache_area
-        .long   mohawk_dma_inv_range
-        .long   mohawk_dma_clean_range
+        .long   mohawk_dma_map_area
+        .long   mohawk_dma_unmap_area
         .long   mohawk_dma_flush_range
 
 ENTRY(cpu_mohawk_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 8e4f6dca8997..e5797f1c1db7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xsc3_dma_inv_range)
+xsc3_dma_inv_range:
         tst     r0, #CACHELINESIZE - 1
         bic     r0, r0, #CACHELINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean L1 D line
@@ -278,7 +278,7 @@ ENTRY(xsc3_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xsc3_dma_clean_range)
+xsc3_dma_clean_range:
         bic     r0, r0, #CACHELINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
         add     r0, r0, #CACHELINESIZE
@@ -304,6 +304,30 @@ ENTRY(xsc3_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xsc3_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     xsc3_dma_clean_range
+        bcs     xsc3_dma_inv_range
+        b       xsc3_dma_flush_range
+ENDPROC(xsc3_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xsc3_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(xsc3_dma_unmap_area)
+
 ENTRY(xsc3_cache_fns)
         .long   xsc3_flush_kern_cache_all
         .long   xsc3_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(xsc3_cache_fns)
         .long   xsc3_coherent_kern_range
         .long   xsc3_coherent_user_range
         .long   xsc3_flush_kern_dcache_area
-        .long   xsc3_dma_inv_range
-        .long   xsc3_dma_clean_range
+        .long   xsc3_dma_map_area
+        .long   xsc3_dma_unmap_area
         .long   xsc3_dma_flush_range
 
 ENTRY(cpu_xsc3_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 93df47265f2d..63037e2162f2 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xscale_dma_inv_range)
+xscale_dma_inv_range:
         tst     r0, #CACHELINESIZE - 1
         bic     r0, r0, #CACHELINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -336,7 +336,7 @@ ENTRY(xscale_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xscale_dma_clean_range)
+xscale_dma_clean_range:
         bic     r0, r0, #CACHELINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHELINESIZE
@@ -363,6 +363,43 @@ ENTRY(xscale_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     xscale_dma_clean_range
+        bcs     xscale_dma_inv_range
+        b       xscale_dma_flush_range
+ENDPROC(xscale_dma_map_area)
+
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_a0_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        beq     xscale_dma_clean_range
+        b       xscale_dma_flush_range
+ENDPROC(xscsale_dma_a0_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(xscale_dma_unmap_area)
+
 ENTRY(xscale_cache_fns)
         .long   xscale_flush_kern_cache_all
         .long   xscale_flush_user_cache_all
@@ -370,8 +407,8 @@ ENTRY(xscale_cache_fns)
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
         .long   xscale_flush_kern_dcache_area
-        .long   xscale_dma_inv_range
-        .long   xscale_dma_clean_range
+        .long   xscale_dma_map_area
+        .long   xscale_dma_unmap_area
         .long   xscale_dma_flush_range
 
 /*
@@ -394,8 +431,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
         .long   xscale_flush_kern_dcache_area
-        .long   xscale_dma_flush_range
-        .long   xscale_dma_clean_range
+        .long   xscale_dma_a0_map_area
+        .long   xscale_dma_unmap_area
         .long   xscale_dma_flush_range
 
 ENTRY(cpu_xscale_dcache_clean_area)
diff --git a/arch/arm/oprofile/op_model_arm11_core.c b/arch/arm/oprofile/op_model_arm11_core.c
index ad80752cb9fb..ef3e2653b90c 100644
--- a/arch/arm/oprofile/op_model_arm11_core.c
+++ b/arch/arm/oprofile/op_model_arm11_core.c
@@ -132,7 +132,7 @@ static irqreturn_t arm11_pmu_interrupt(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-int arm11_request_interrupts(int *irqs, int nr)
+int arm11_request_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
         int ret = 0;
@@ -153,7 +153,7 @@ int arm11_request_interrupts(int *irqs, int nr)
         return ret;
 }
 
-void arm11_release_interrupts(int *irqs, int nr)
+void arm11_release_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
 
diff --git a/arch/arm/oprofile/op_model_arm11_core.h b/arch/arm/oprofile/op_model_arm11_core.h
index 6f8538e5a960..1902b99d9dfd 100644
--- a/arch/arm/oprofile/op_model_arm11_core.h
+++ b/arch/arm/oprofile/op_model_arm11_core.h
@@ -39,7 +39,7 @@
 int arm11_setup_pmu(void);
 int arm11_start_pmu(void);
 int arm11_stop_pmu(void);
-int arm11_request_interrupts(int *, int);
-void arm11_release_interrupts(int *, int);
+int arm11_request_interrupts(const int *, int);
+void arm11_release_interrupts(const int *, int);
 
 #endif
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c
index 4ce0f9801e2e..f73ce875a395 100644
--- a/arch/arm/oprofile/op_model_mpcore.c
+++ b/arch/arm/oprofile/op_model_mpcore.c
@@ -32,6 +32,7 @@
 /* #define DEBUG */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
@@ -43,6 +44,7 @@
 #include <mach/hardware.h>
 #include <mach/board-eb.h>
 #include <asm/system.h>
+#include <asm/pmu.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
@@ -58,6 +60,7 @@
  * Bitmask of used SCU counters
  */
 static unsigned int scu_em_used;
+static const struct pmu_irqs *pmu_irqs;
 
 /*
  * 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number)
@@ -225,33 +228,40 @@ static int em_setup_ctrs(void)
         return 0;
 }
 
-static int arm11_irqs[] = {
-        [0]     = IRQ_EB11MP_PMU_CPU0,
-        [1]     = IRQ_EB11MP_PMU_CPU1,
-        [2]     = IRQ_EB11MP_PMU_CPU2,
-        [3]     = IRQ_EB11MP_PMU_CPU3
-};
-
 static int em_start(void)
 {
         int ret;
 
-        ret = arm11_request_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs)) {
+                ret = PTR_ERR(pmu_irqs);
+                goto out;
+        }
+
+        ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
         if (ret == 0) {
                 em_call_function(arm11_start_pmu);
 
                 ret = scu_start();
-                if (ret)
-                        arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
+                if (ret) {
+                        arm11_release_interrupts(pmu_irqs->irqs,
+                                                 pmu_irqs->num_irqs);
+                } else {
+                        release_pmu(pmu_irqs);
+                        pmu_irqs = NULL;
+                }
         }
+
+out:
         return ret;
 }
 
 static void em_stop(void)
 {
         em_call_function(arm11_stop_pmu);
-        arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
+        arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
         scu_stop();
+        release_pmu(pmu_irqs);
 }
 
 /*
@@ -283,15 +293,7 @@ static int em_setup(void)
         em_route_irq(IRQ_EB11MP_PMU_SCU6, 3);
         em_route_irq(IRQ_EB11MP_PMU_SCU7, 3);
 
-        /*
-         * Send CP15 PMU interrupts to the owner CPU.
-         */
-        em_route_irq(IRQ_EB11MP_PMU_CPU0, 0);
-        em_route_irq(IRQ_EB11MP_PMU_CPU1, 1);
-        em_route_irq(IRQ_EB11MP_PMU_CPU2, 2);
-        em_route_irq(IRQ_EB11MP_PMU_CPU3, 3);
-
-        return 0;
+        return init_pmu();
 }
 
 struct op_arm_model_spec op_mpcore_spec = {
diff --git a/arch/arm/oprofile/op_model_v6.c b/arch/arm/oprofile/op_model_v6.c
index f7d2ec5ee9a1..a22357a2fd08 100644
--- a/arch/arm/oprofile/op_model_v6.c
+++ b/arch/arm/oprofile/op_model_v6.c
@@ -19,39 +19,47 @@
 /* #define DEBUG */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/pmu.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
 #include "op_model_arm11_core.h"
 
-static int irqs[] = {
-#ifdef CONFIG_ARCH_OMAP2
-        3,
-#endif
-#ifdef CONFIG_ARCH_BCMRING
-        IRQ_PMUIRQ, /* for BCMRING, ARM PMU interrupt is 43 */
-#endif
-};
+static const struct pmu_irqs *pmu_irqs;
 
 static void armv6_pmu_stop(void)
 {
         arm11_stop_pmu();
-        arm11_release_interrupts(irqs, ARRAY_SIZE(irqs));
+        arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
 }
 
 static int armv6_pmu_start(void)
 {
         int ret;
 
-        ret = arm11_request_interrupts(irqs, ARRAY_SIZE(irqs));
-        if (ret >= 0)
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs)) {
+                ret = PTR_ERR(pmu_irqs);
+                goto out;
+        }
+
+        ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        if (ret >= 0) {
                 ret = arm11_start_pmu();
+        } else {
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
+        }
 
+out:
         return ret;
 }
 
diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c
index 2088a6c0cc0e..8642d0891ae1 100644
--- a/arch/arm/oprofile/op_model_v7.c
+++ b/arch/arm/oprofile/op_model_v7.c
@@ -11,11 +11,14 @@
  */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/smp.h>
 
+#include <asm/pmu.h>
+
 #include "op_counter.h"
 #include "op_arm_model.h"
 #include "op_model_v7.h"
@@ -295,7 +298,7 @@ static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-int armv7_request_interrupts(int *irqs, int nr)
+int armv7_request_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
         int ret = 0;
@@ -318,7 +321,7 @@ int armv7_request_interrupts(int *irqs, int nr)
         return ret;
 }
 
-void armv7_release_interrupts(int *irqs, int nr)
+void armv7_release_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
 
@@ -362,12 +365,7 @@ static void armv7_pmnc_dump_regs(void)
 }
 #endif
 
-
-static int irqs[] = {
-#ifdef CONFIG_ARCH_OMAP3
-        INT_34XX_BENCH_MPU_EMUL,
-#endif
-};
+static const struct pmu_irqs *pmu_irqs;
 
 static void armv7_pmnc_stop(void)
 {
@@ -375,19 +373,29 @@ static void armv7_pmnc_stop(void)
         armv7_pmnc_dump_regs();
 #endif
         armv7_stop_pmnc();
-        armv7_release_interrupts(irqs, ARRAY_SIZE(irqs));
+        armv7_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
 }
 
 static int armv7_pmnc_start(void)
 {
         int ret;
 
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs))
+                return PTR_ERR(pmu_irqs);
+
 #ifdef DEBUG
         armv7_pmnc_dump_regs();
 #endif
-        ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs));
-        if (ret >= 0)
+        ret = armv7_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        if (ret >= 0) {
                 armv7_start_pmnc();
+        } else {
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
+        }
 
         return ret;
 }
diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h
index 0e19bcc2e100..9ca334b39c75 100644
--- a/arch/arm/oprofile/op_model_v7.h
+++ b/arch/arm/oprofile/op_model_v7.h
@@ -97,7 +97,7 @@
 int armv7_setup_pmu(void);
 int armv7_start_pmu(void);
 int armv7_stop_pmu(void);
-int armv7_request_interrupts(int *, int);
-void armv7_release_interrupts(int *, int);
+int armv7_request_interrupts(const int *, int);
+void armv7_release_interrupts(const int *, int);
 
 #endif
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 724ab9ce2526..1d34a02048bd 100644
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -17,12 +17,14 @@
 /* #define DEBUG */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
 #include <asm/cputype.h>
+#include <asm/pmu.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
@@ -33,17 +35,6 @@
 #define PMU_RESET       (CCNT_RESET | PMN_RESET)
 #define PMU_CNT64       0x008   /* Make CCNT count every 64th cycle */
 
-/* TODO do runtime detection */
-#ifdef CONFIG_ARCH_IOP32X
-#define XSCALE_PMU_IRQ  IRQ_IOP32X_CORE_PMU
-#endif
-#ifdef CONFIG_ARCH_IOP33X
-#define XSCALE_PMU_IRQ  IRQ_IOP33X_CORE_PMU
-#endif
-#ifdef CONFIG_ARCH_PXA
-#define XSCALE_PMU_IRQ  IRQ_PMU
-#endif
-
 /*
  * Different types of events that can be counted by the XScale PMU
  * as used by Oprofile userspace. Here primarily for documentation
@@ -367,6 +358,8 @@ static irqreturn_t xscale_pmu_interrupt(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
+static const struct pmu_irqs *pmu_irqs;
+
 static void xscale_pmu_stop(void)
 {
         u32 pmnc = read_pmnc();
@@ -374,20 +367,30 @@ static void xscale_pmu_stop(void)
         pmnc &= ~PMU_ENABLE;
         write_pmnc(pmnc);
 
-        free_irq(XSCALE_PMU_IRQ, results);
+        free_irq(pmu_irqs->irqs[0], results);
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
 }
 
 static int xscale_pmu_start(void)
 {
         int ret;
-        u32 pmnc = read_pmnc();
+        u32 pmnc;
+
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs))
+                return PTR_ERR(pmu_irqs);
+
+        pmnc = read_pmnc();
 
-        ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, IRQF_DISABLED,
-                        "XScale PMU", (void *)results);
+        ret = request_irq(pmu_irqs->irqs[0], xscale_pmu_interrupt,
+                          IRQF_DISABLED, "XScale PMU", (void *)results);
 
         if (ret < 0) {
                 printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n",
-                        XSCALE_PMU_IRQ);
+                       pmu_irqs->irqs[0]);
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
                 return ret;
         }
 
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
index ed0bbece0d61..e15bc17db90b 100644
--- a/arch/arm/plat-iop/io.c
+++ b/arch/arm/plat-iop/io.c
@@ -34,7 +34,8 @@ void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
                 retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
-                retval = __arm_ioremap(cookie, size, mtype);
+                retval = __arm_ioremap_caller(cookie, size, mtype,
+                                __builtin_return_address(0));
         }
 
         return retval;
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 996cbac6932c..6cee38df58b2 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,3 +13,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+ifdef CONFIG_SND_IMX_SOC
+obj-y += ssi-fiq.o
+obj-y += ssi-fiq-ksym.o
+endif
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 62d97623412f..44243a278434 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -21,6 +21,6 @@
 #define __ASM_ARCH_MXC_VMALLOC_H__
 
 /* vmalloc ending address */
-#define VMALLOC_END       0xF4000000
+#define VMALLOC_END       0xf4000000UL
 
 #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/plat-mxc/ssi-fiq-ksym.c
new file mode 100644
index 000000000000..b5fad454da78
--- /dev/null
+++ b/arch/arm/plat-mxc/ssi-fiq-ksym.c
@@ -0,0 +1,20 @@
+/*
+ * Exported ksyms for the SSI FIQ handler
+ *
+ * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+
+#include <mach/ssi.h>
+
+EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);
+EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);
+EXPORT_SYMBOL(imx_ssi_fiq_start);
+EXPORT_SYMBOL(imx_ssi_fiq_end);
+EXPORT_SYMBOL(imx_ssi_fiq_base);
+
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
new file mode 100644
index 000000000000..4ddce565b353
--- /dev/null
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -0,0 +1,134 @@
+/*
+ *  Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * r8  = bit 0-15: tx offset, bit 16-31: tx buffer size
+ * r9  = bit 0-15: rx offset, bit 16-31: rx buffer size
+ */
+
+#define SSI_STX0        0x00
+#define SSI_SRX0        0x08
+#define SSI_SISR        0x14
+#define SSI_SIER        0x18
+#define SSI_SACNT       0x38
+
+#define SSI_SACNT_AC97EN        (1 << 0)
+
+#define SSI_SIER_TFE0_EN        (1 << 0)
+#define SSI_SISR_TFE0           (1 << 0)
+#define SSI_SISR_RFF0           (1 << 2)
+#define SSI_SIER_RFF0_EN        (1 << 2)
+
+                .text
+                .global imx_ssi_fiq_start
+                .global imx_ssi_fiq_end
+                .global imx_ssi_fiq_base
+                .global imx_ssi_fiq_rx_buffer
+                .global imx_ssi_fiq_tx_buffer
+
+imx_ssi_fiq_start:
+                ldr r12, imx_ssi_fiq_base
+
+                /* TX */
+                ldr r11, imx_ssi_fiq_tx_buffer
+
+                /* shall we send? */
+                ldr r13, [r12, #SSI_SIER]
+                tst r13, #SSI_SIER_TFE0_EN
+                beq 1f
+
+                /* TX FIFO empty? */
+                ldr r13, [r12, #SSI_SISR]
+                tst r13, #SSI_SISR_TFE0
+                beq 1f
+
+                mov r10, #0x10000
+                sub r10, #1
+                and r10, r10, r8        /* r10: current buffer offset */
+
+                add r11, r11, r10
+
+                ldrh r13, [r11]
+                strh r13, [r12, #SSI_STX0]
+
+                ldrh r13, [r11, #2]
+                strh r13, [r12, #SSI_STX0]
+
+                ldrh r13, [r11, #4]
+                strh r13, [r12, #SSI_STX0]
+
+                ldrh r13, [r11, #6]
+                strh r13, [r12, #SSI_STX0]
+
+                add r10, #8
+                lsr r13, r8, #16        /* r13: buffer size */
+                cmp r10, r13
+                lslgt r8, r13, #16
+                addle r8, #8
+1:
+                /* RX */
+
+                /* shall we receive? */
+                ldr r13, [r12, #SSI_SIER]
+                tst r13, #SSI_SIER_RFF0_EN
+                beq 1f
+
+                /* RX FIFO full? */
+                ldr r13, [r12, #SSI_SISR]
+                tst r13, #SSI_SISR_RFF0
+                beq 1f
+
+                ldr r11, imx_ssi_fiq_rx_buffer
+
+                mov r10, #0x10000
+                sub r10, #1
+                and r10, r10, r9        /* r10: current buffer offset */
+
+                add r11, r11, r10
+
+                ldr r13, [r12, #SSI_SACNT]
+                tst r13, #SSI_SACNT_AC97EN
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11]
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11, #2]
+
+                /* dummy read to skip slot 12 */
+                ldrne r13, [r12, #SSI_SRX0]
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11, #4]
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11, #6]
+
+                /* dummy read to skip slot 12 */
+                ldrne r13, [r12, #SSI_SRX0]
+
+                add r10, #8
+                lsr r13, r9, #16        /* r13: buffer size */
+                cmp r10, r13
+                lslgt r9, r13, #16
+                addle r9, #8
+
+1:
+                @ return from FIQ
+                subs    pc, lr, #4
+imx_ssi_fiq_base:
+                .word 0x0
+imx_ssi_fiq_rx_buffer:
+                .word 0x0
+imx_ssi_fiq_tx_buffer:
+                .word 0x0
+imx_ssi_fiq_end:
+
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h
new file mode 100644
index 000000000000..1621db67a53d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/i2c.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PLAT_I2C_H
+#define __PLAT_I2C_H
+
+enum i2c_freq_mode {
+        I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
+        I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
+        I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
+        I2C_FREQ_MODE_HIGH_SPEED        /* up to 3.4 Mb/s */
+};
+
+/**
+ * struct nmk_i2c_controller - client specific controller configuration
+ * @clk_freq:   clock frequency for the operation mode
+ * @slsu:       Slave data setup time in ns.
+ *              The needed setup time for three modes of operation
+ *              are 250ns, 100ns and 10ns respectively thus leading
+ *              to the values of 14, 6, 2 for a 48 MHz i2c clk
+ * @tft:        Tx FIFO Threshold in bytes
+ * @rft:        Rx FIFO Threshold in bytes
+ * @sm:         speed mode
+ */
+struct nmk_i2c_controller {
+        unsigned long   clk_freq;
+        unsigned short  slsu;
+        unsigned char   tft;
+        unsigned char   rft;
+        enum i2c_freq_mode      sm;
+};
+
+#endif  /* __PLAT_I2C_H */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index be9484a28b12..6da796ef82bd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -31,6 +31,7 @@ config ARCH_OMAP3
         depends on ARCH_OMAP2PLUS
         select CPU_V7
         select USB_ARCH_HAS_EHCI
+        select ARM_L1_CACHE_SHIFT_6
 
 config ARCH_OMAP4
         bool "TI OMAP4"
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index 8fc15d33089a..2302474a3748 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -40,6 +40,7 @@
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
 #define OMAP44XX_SCU_BASE               0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
+#define OMAP44XX_L2CACHE_BASE           0x48242000
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
 #define OMAP44XX_MCPDM_BASE             0x40132000
 #define OMAP44XX_MCPDM_L3_BASE          0x49032000
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 2c494cf8e378..b0078cf96281 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -124,7 +124,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
         }
 #endif
-        return __arm_ioremap(p, size, type);
+        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(omap_ioremap);
 
diff --git a/arch/arm/plat-s3c/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h
index bfd2ca6e3074..299d95f365c9 100644
--- a/arch/arm/plat-s3c/include/mach/vmalloc.h
+++ b/arch/arm/plat-s3c/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END       (0xe0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
index 5d2f19a09e44..e593a2a801c6 100644
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -1126,9 +1126,8 @@ static int __init clk_init(void)
                         if (ops && ops->set_parent)
                                 ops->set_parent(cl->clk, cl->clk->parent);
                 }
-
-                clkdev_add(cl);
         }
+        clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
         return 0;
 }
 
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
index 541b880c1863..943c1a29d641 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
@@ -9,4 +9,4 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-#define VMALLOC_END       (0xF0000000)
+#define VMALLOC_END       0xf0000000UL
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 5a79fc6ee818..31c2f4c30a95 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Thu Jan 28 22:15:54 2010
+# Last update: Sat Feb 20 14:16:15 2010
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2257,7 +2257,7 @@ oratisalog		MACH_ORATISALOG		ORATISALOG		2268
 oratismadi              MACH_ORATISMADI         ORATISMADI              2269
 oratisot16              MACH_ORATISOT16         ORATISOT16              2270
 oratisdesk              MACH_ORATISDESK         ORATISDESK              2271
-v2_ca9                  MACH_V2P_CA9            V2P_CA9                 2272
+vexpress                MACH_VEXPRESS           VEXPRESS                2272
 sintexo                 MACH_SINTEXO            SINTEXO                 2273
 cm3389                  MACH_CM3389             CM3389                  2274
 omap3_cio               MACH_OMAP3_CIO          OMAP3_CIO               2275
@@ -2636,3 +2636,45 @@ hw90240			MACH_HW90240		HW90240			2648
 dm365_leopard           MACH_DM365_LEOPARD      DM365_LEOPARD           2649
 mityomapl138            MACH_MITYOMAPL138       MITYOMAPL138            2650
 scat110                 MACH_SCAT110            SCAT110                 2651
+acer_a1                 MACH_ACER_A1            ACER_A1                 2652
+cmcontrol               MACH_CMCONTROL          CMCONTROL               2653
+pelco_lamar             MACH_PELCO_LAMAR        PELCO_LAMAR             2654
+rfp43                   MACH_RFP43              RFP43                   2655
+sk86r0301               MACH_SK86R0301          SK86R0301               2656
+ctpxa                   MACH_CTPXA              CTPXA                   2657
+epb_arm9_a              MACH_EPB_ARM9_A         EPB_ARM9_A              2658
+guruplug                MACH_GURUPLUG           GURUPLUG                2659
+spear310                MACH_SPEAR310           SPEAR310                2660
+spear320                MACH_SPEAR320           SPEAR320                2661
+robotx                  MACH_ROBOTX             ROBOTX                  2662
+lsxhl                   MACH_LSXHL              LSXHL                   2663
+smartlite               MACH_SMARTLITE          SMARTLITE               2664
+cws2                    MACH_CWS2               CWS2                    2665
+m619                    MACH_M619               M619                    2666
+smartview               MACH_SMARTVIEW          SMARTVIEW               2667
+lsa_salsa               MACH_LSA_SALSA          LSA_SALSA               2668
+kizbox                  MACH_KIZBOX             KIZBOX                  2669
+htccharmer              MACH_HTCCHARMER         HTCCHARMER              2670
+guf_neso_lt             MACH_GUF_NESO_LT        GUF_NESO_LT             2671
+pm9g45                  MACH_PM9G45             PM9G45                  2672
+htcpanther              MACH_HTCPANTHER         HTCPANTHER              2673
+htcpanther_cdma         MACH_HTCPANTHER_CDMA    HTCPANTHER_CDMA         2674
+reb01                   MACH_REB01              REB01                   2675
+aquila                  MACH_AQUILA             AQUILA                  2676
+spark_sls_hw2           MACH_SPARK_SLS_HW2      SPARK_SLS_HW2           2677
+sheeva_esata            MACH_ESATA_SHEEVAPLUG   ESATA_SHEEVAPLUG        2678
+surf7x30                MACH_SURF7X30           SURF7X30                2679
+micro2440               MACH_MICRO2440          MICRO2440               2680
+am2440                  MACH_AM2440             AM2440                  2681
+tq2440                  MACH_TQ2440             TQ2440                  2682
+lpc2478oem              MACH_LPC2478OEM         LPC2478OEM              2683
+ak880x                  MACH_AK880X             AK880X                  2684
+cobra3530               MACH_COBRA3530          COBRA3530               2685
+pmppb                   MACH_PMPPB              PMPPB                   2686
+u6715                   MACH_U6715              U6715                   2687
+axar1500_sender         MACH_AXAR1500_SENDER    AXAR1500_SENDER         2688
+g30_dvb                 MACH_G30_DVB            G30_DVB                 2689
+vc088x                  MACH_VC088X             VC088X                  2690
+mioa702                 MACH_MIOA702            MIOA702                 2691
+hpmin                   MACH_HPMIN              HPMIN                   2692
+ak880xak                MACH_AK880XAK           AK880XAK                2693
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index a63c4be99b36..7f3f59fcaa21 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -433,7 +433,11 @@ static inline void vfp_pm_init(void) { }
  * saved one. This function is used by the ptrace mechanism.
  */
 #ifdef CONFIG_SMP
-void vfp_sync_state(struct thread_info *thread)
+void vfp_sync_hwstate(struct thread_info *thread)
+{
+}
+
+void vfp_flush_hwstate(struct thread_info *thread)
 {
         /*
          * On SMP systems, the VFP state is automatically saved at every
@@ -444,35 +448,48 @@ void vfp_sync_state(struct thread_info *thread)
         thread->vfpstate.hard.cpu = NR_CPUS;
 }
 #else
-void vfp_sync_state(struct thread_info *thread)
+void vfp_sync_hwstate(struct thread_info *thread)
 {
         unsigned int cpu = get_cpu();
-        u32 fpexc = fmrx(FPEXC);
 
         /*
-         * If VFP is enabled, the previous state was already saved and
-         * last_VFP_context updated.
+         * If the thread we're interested in is the current owner of the
+         * hardware VFP state, then we need to save its state.
          */
-        if (fpexc & FPEXC_EN)
-                goto out;
+        if (last_VFP_context[cpu] == &thread->vfpstate) {
+                u32 fpexc = fmrx(FPEXC);
 
-        if (!last_VFP_context[cpu])
-                goto out;
+                /*
+                 * Save the last VFP state on this CPU.
+                 */
+                fmxr(FPEXC, fpexc | FPEXC_EN);
+                vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);
+                fmxr(FPEXC, fpexc);
+        }
 
-        /*
-         * Save the last VFP state on this CPU.
-         */
-        fmxr(FPEXC, fpexc | FPEXC_EN);
-        vfp_save_state(last_VFP_context[cpu], fpexc);
-        fmxr(FPEXC, fpexc);
+        put_cpu();
+}
+
+void vfp_flush_hwstate(struct thread_info *thread)
+{
+        unsigned int cpu = get_cpu();
 
         /*
-         * Set the context to NULL to force a reload the next time the thread
-         * uses the VFP.
+         * If the thread we're interested in is the current owner of the
+         * hardware VFP state, then we need to save its state.
          */
-        last_VFP_context[cpu] = NULL;
+        if (last_VFP_context[cpu] == &thread->vfpstate) {
+                u32 fpexc = fmrx(FPEXC);
+
+                fmxr(FPEXC, fpexc & ~FPEXC_EN);
+
+                /*
+                 * Set the context to NULL to force a reload the next time
+                 * the thread uses the VFP.
+                 */
+                last_VFP_context[cpu] = NULL;
+        }
 
-out:
         put_cpu();
 }
 #endif
diff --git a/arch/avr32/include/asm/pgtable.h b/arch/avr32/include/asm/pgtable.h
index fecdda16f444..a9ae30c41e74 100644
--- a/arch/avr32/include/asm/pgtable.h
+++ b/arch/avr32/include/asm/pgtable.h
@@ -325,7 +325,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 
 struct vm_area_struct;
 extern void update_mmu_cache(struct vm_area_struct * vma,
-                             unsigned long address, pte_t pte);
+                             unsigned long address, pte_t *ptep);
 
 /*
  * Encode and decode a swap entry
diff --git a/arch/avr32/mm/tlb.c b/arch/avr32/mm/tlb.c
index 06677be98ffb..0da23109f817 100644
--- a/arch/avr32/mm/tlb.c
+++ b/arch/avr32/mm/tlb.c
@@ -101,7 +101,7 @@ static void update_dtlb(unsigned long address, pte_t pte)
 }
 
 void update_mmu_cache(struct vm_area_struct *vma,
-                      unsigned long address, pte_t pte)
+                      unsigned long address, pte_t *ptep)
 {
         unsigned long flags;
 
@@ -110,7 +110,7 @@ void update_mmu_cache(struct vm_area_struct *vma,
                 return;
 
         local_irq_save(flags);
-        update_dtlb(address, pte);
+        update_dtlb(address, *ptep);
         local_irq_restore(flags);
 }
 
diff --git a/arch/cris/arch-v32/drivers/pci/bios.c b/arch/cris/arch-v32/drivers/pci/bios.c
index 77ee319193c3..d4b9c36ddc0f 100644
--- a/arch/cris/arch-v32/drivers/pci/bios.c
+++ b/arch/cris/arch-v32/drivers/pci/bios.c
@@ -41,18 +41,16 @@ int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
         return 0;
 }
 
-void
-pcibios_align_resource(void *data, struct resource *res,
+resource_size_t
+pcibios_align_resource(void *data, const struct resource *res,
                        resource_size_t size, resource_size_t align)
 {
-        if (res->flags & IORESOURCE_IO) {
-                resource_size_t start = res->start;
+        resource_size_t start = res->start;
 
-                if (start & 0x300) {
-                        start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
-        }
+        if ((res->flags & IORESOURCE_IO) && (start & 0x300))
+                start = (start + 0x3ff) & ~0x3ff;
+
+        return start
 }
 
 int pcibios_enable_resources(struct pci_dev *dev, int mask)
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
index 1fcce00f01f4..99ea6cd1b143 100644
--- a/arch/cris/include/asm/pgtable.h
+++ b/arch/cris/include/asm/pgtable.h
@@ -270,7 +270,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
  * Actually I am not sure on what this could be used for.
  */
 static inline void update_mmu_cache(struct vm_area_struct * vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
index 22c60692b551..c18b0d32e636 100644
--- a/arch/frv/include/asm/pgtable.h
+++ b/arch/frv/include/asm/pgtable.h
@@ -505,7 +505,7 @@ static inline int pte_file(pte_t pte)
 /*
  * preload information about a newly instantiated PTE into the SCR0/SCR1 PGE cache
  */
-static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
         struct mm_struct *mm;
         unsigned long ampr;
diff --git a/arch/frv/mb93090-mb00/pci-frv.c b/arch/frv/mb93090-mb00/pci-frv.c
index 566bdeb499d1..1ed15d7fea20 100644
--- a/arch/frv/mb93090-mb00/pci-frv.c
+++ b/arch/frv/mb93090-mb00/pci-frv.c
@@ -32,18 +32,16 @@
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-void
-pcibios_align_resource(void *data, struct resource *res,
+resource_size_t
+pcibios_align_resource(void *data, const struct resource *res,
                        resource_size_t size, resource_size_t align)
 {
-        if (res->flags & IORESOURCE_IO) {
-                resource_size_t start = res->start;
+        resource_size_t start = res->start;
 
-                if (start & 0x300) {
-                        start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
-        }
+        if ((res->flags & IORESOURCE_IO) && (start & 0x300))
+                start = (start + 0x3ff) & ~0x3ff;
+
+        return start
 }
 
 
diff --git a/arch/h8300/mm/memory.c b/arch/h8300/mm/memory.c
index ccd6ade816dd..40d8aa811e4e 100644
--- a/arch/h8300/mm/memory.c
+++ b/arch/h8300/mm/memory.c
@@ -44,8 +44,8 @@ void cache_push_v (unsigned long vaddr, int len)
 {
 }
 
-/* Map some physical address range into the kernel address space. The
- * code is copied and adapted from map_chunk().
+/*
+ * Map some physical address range into the kernel address space.
  */
 
 unsigned long kernel_map(unsigned long paddr, unsigned long size,
diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
index 7ae58892ba8d..93997bd5edc3 100644
--- a/arch/ia64/include/asm/acpi.h
+++ b/arch/ia64/include/asm/acpi.h
@@ -94,9 +94,11 @@ ia64_acpi_release_global_lock (unsigned int *lock)
 #define acpi_noirq 0    /* ACPI always enabled on IA64 */
 #define acpi_pci_disabled 0 /* ACPI PCI always enabled on IA64 */
 #define acpi_strict 1   /* no ACPI spec workarounds on IA64 */
+#define acpi_ht 0       /* no HT-only mode on IA64 */
 #endif
 #define acpi_processor_cstate_check(x) (x) /* no idle limits on IA64 :) */
 static inline void disable_acpi(void) { }
+static inline void pci_acpi_crs_quirks(void) { }
 
 const char *acpi_get_sysname (void);
 int acpi_request_vector (u32 int_type);
diff --git a/arch/ia64/include/asm/elf.h b/arch/ia64/include/asm/elf.h
index e14108b19c09..4c41656ede87 100644
--- a/arch/ia64/include/asm/elf.h
+++ b/arch/ia64/include/asm/elf.h
@@ -201,7 +201,9 @@ extern void ia64_elf_core_copy_regs (struct pt_regs *src, elf_gregset_t dst);
    relevant until we have real hardware to play with... */
 #define ELF_PLATFORM    NULL
 
-#define SET_PERSONALITY(ex)     set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex)     \
+        set_personality((current->personality & ~PER_MASK) | PER_LINUX)
+
 #define elf_read_implies_exec(ex, executable_stack)                                     \
         ((executable_stack!=EXSTACK_DISABLE_X) && ((ex).e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK) != 0)
 
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h
index 69bf13857a9f..c3286f42e501 100644
--- a/arch/ia64/include/asm/pgtable.h
+++ b/arch/ia64/include/asm/pgtable.h
@@ -462,7 +462,7 @@ pte_same (pte_t a, pte_t b)
         return pte_val(a) == pte_val(b);
 }
 
-#define update_mmu_cache(vma, address, pte) do { } while (0)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
 
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 extern void paging_init (void);
diff --git a/arch/ia64/kernel/kprobes.c b/arch/ia64/kernel/kprobes.c
index 9adac441ac9b..7026b29e277a 100644
--- a/arch/ia64/kernel/kprobes.c
+++ b/arch/ia64/kernel/kprobes.c
@@ -870,7 +870,7 @@ static int __kprobes pre_kprobes_handler(struct die_args *args)
                 return 1;
 
 ss_probe:
-#if !defined(CONFIG_PREEMPT) || defined(CONFIG_FREEZER)
+#if !defined(CONFIG_PREEMPT)
         if (p->ainsn.inst_flag == INST_FLAG_BOOSTABLE && !p->post_handler) {
                 /* Boost up -- we can execute copied instructions directly */
                 ia64_psr(regs)->ri = p->ainsn.slot;
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index a35c661e5e89..47a192781b0a 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -61,7 +61,7 @@ unsigned long long sched_clock(void)
 
 #ifdef CONFIG_PARAVIRT
 static void
-paravirt_clocksource_resume(void)
+paravirt_clocksource_resume(struct clocksource *cs)
 {
         if (pv_time_ops.clocksource_resume)
                 pv_time_ops.clocksource_resume();
diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index df639db779f9..64aff520b899 100644
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -320,9 +320,9 @@ static __devinit acpi_status add_window(struct acpi_resource *res, void *data)
 static void __devinit
 pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
 {
-        int i, j;
+        int i;
 
-        j = 0;
+        pci_bus_remove_resources(bus);
         for (i = 0; i < ctrl->windows; i++) {
                 struct resource *res = &ctrl->window[i].resource;
                 /* HP's firmware has a hack to work around a Windows bug.
@@ -330,13 +330,7 @@ pcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl)
                 if ((res->flags & IORESOURCE_MEM) &&
                     (res->end - res->start < 16))
                         continue;
-                if (j >= PCI_BUS_NUM_RESOURCES) {
-                        dev_warn(&bus->dev,
-                                 "ignoring host bridge window %pR (no space)\n",
-                                 res);
-                        continue;
-                }
-                bus->resource[j++] = res;
+                pci_bus_add_resource(bus, res, 0);
         }
 }
 
@@ -452,13 +446,12 @@ EXPORT_SYMBOL(pcibios_bus_to_resource);
 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 {
         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
-        struct resource *devr = &dev->resource[idx];
+        struct resource *devr = &dev->resource[idx], *busr;
 
         if (!dev->bus)
                 return 0;
-        for (i=0; i<PCI_BUS_NUM_RESOURCES; i++) {
-                struct resource *busr = dev->bus->resource[i];
 
+        pci_bus_for_each_resource(dev->bus, busr, i) {
                 if (!busr || ((busr->flags ^ devr->flags) & type_mask))
                         continue;
                 if ((devr->start) && (devr->start >= busr->start) &&
@@ -547,10 +540,11 @@ pcibios_disable_device (struct pci_dev *dev)
                 acpi_pci_irq_disable(dev);
 }
 
-void
-pcibios_align_resource (void *data, struct resource *res,
+resource_size_t
+pcibios_align_resource (void *data, const struct resource *res,
                         resource_size_t size, resource_size_t align)
 {
+        return res->start;
 }
 
 /*
diff --git a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
index ece1bf994499..e456f062f241 100644
--- a/arch/ia64/sn/kernel/setup.c
+++ b/arch/ia64/sn/kernel/setup.c
@@ -71,7 +71,7 @@ EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 DEFINE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
 EXPORT_PER_CPU_SYMBOL(__sn_hub_info);
 
-DEFINE_PER_CPU(short [MAX_COMPACT_NODES], __sn_cnodeid_to_nasid);
+DEFINE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_COMPACT_NODES]);
 EXPORT_PER_CPU_SYMBOL(__sn_cnodeid_to_nasid);
 
 DEFINE_PER_CPU(struct nodepda_s *, __sn_nodepda);
diff --git a/arch/m32r/include/asm/tlbflush.h b/arch/m32r/include/asm/tlbflush.h
index 0ef95307784e..92614b0ccf17 100644
--- a/arch/m32r/include/asm/tlbflush.h
+++ b/arch/m32r/include/asm/tlbflush.h
@@ -92,6 +92,6 @@ static __inline__ void __flush_tlb_all(void)
         );
 }
 
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 #endif  /* _ASM_M32R_TLBFLUSH_H */
diff --git a/arch/m32r/mm/fault-nommu.c b/arch/m32r/mm/fault-nommu.c
index 88469178ea6b..888aab1157ed 100644
--- a/arch/m32r/mm/fault-nommu.c
+++ b/arch/m32r/mm/fault-nommu.c
@@ -95,7 +95,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
  * update_mmu_cache()
  *======================================================================*/
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
-        pte_t pte)
+        pte_t *ptep)
 {
         BUG();
 }
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c
index 7274b47f4c22..28ee389e5f5a 100644
--- a/arch/m32r/mm/fault.c
+++ b/arch/m32r/mm/fault.c
@@ -336,7 +336,7 @@ vmalloc_fault:
 
                 addr = (address & PAGE_MASK);
                 set_thread_fault_code(error_code);
-                update_mmu_cache(NULL, addr, *pte_k);
+                update_mmu_cache(NULL, addr, pte_k);
                 set_thread_fault_code(0);
                 return;
         }
@@ -349,7 +349,7 @@ vmalloc_fault:
 #define ITLB_END        (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
 #define DTLB_END        (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
-        pte_t pte)
+        pte_t *ptep)
 {
         volatile unsigned long *entry1, *entry2;
         unsigned long pte_data, flags;
@@ -365,7 +365,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
 
         vaddr = (vaddr & PAGE_MASK) | get_asid();
 
-        pte_data = pte_val(pte);
+        pte_data = pte_val(*ptep);
 
 #ifdef CONFIG_CHIP_OPSP
         entry1 = (unsigned long *)ITLB_BASE;
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index ecdc19a299b2..b5da298ba61d 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -536,10 +536,6 @@ config GVPIOEXT_PLIP
           Say Y to enable doing IP over the parallel port on your GVP
           IO-Extender card, N otherwise.
 
-config MAC_SCC
-        tristate "Macintosh serial support"
-        depends on MAC
-
 config MAC_HID
         bool
         depends on INPUT_ADBHID
@@ -595,7 +591,7 @@ config DN_SERIAL
 
 config SERIAL_CONSOLE
         bool "Support for serial port console"
-        depends on (AMIGA || ATARI || MAC || SUN3 || SUN3X || VME || APOLLO) && (ATARI_MFPSER=y || ATARI_MIDI=y || MAC_SCC=y || AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y || SERIAL=y || MVME147_SCC || SERIAL167 || MVME162_SCC || BVME6000_SCC || DN_SERIAL)
+        depends on (AMIGA || ATARI || SUN3 || SUN3X || VME || APOLLO) && (ATARI_MFPSER=y || ATARI_MIDI=y || AMIGA_BUILTIN_SERIAL=y || GVPIOEXT=y || MULTIFACE_III_TTY=y || SERIAL=y || MVME147_SCC || SERIAL167 || MVME162_SCC || BVME6000_SCC || DN_SERIAL)
         ---help---
           If you say Y here, it will be possible to use a serial port as the
           system console (the system console is the device which receives all
diff --git a/arch/m68k/amiga/config.c b/arch/m68k/amiga/config.c
index 6c74751c7b82..d2cc35d98532 100644
--- a/arch/m68k/amiga/config.c
+++ b/arch/m68k/amiga/config.c
@@ -480,7 +480,7 @@ static void __init amiga_sched_init(irq_handler_t timer_routine)
         static struct resource sched_res = {
                 .name = "timer", .start = 0x00bfd400, .end = 0x00bfd5ff,
         };
-        jiffy_ticks = (amiga_eclock+HZ/2)/HZ;
+        jiffy_ticks = DIV_ROUND_CLOSEST(amiga_eclock, HZ);
 
         if (request_resource(&mb_resources._ciab, &sched_res))
                 printk("Cannot allocate ciab.ta{lo,hi}\n");
diff --git a/arch/m68k/configs/mac_defconfig b/arch/m68k/configs/mac_defconfig
index 9991b64fea57..c5f3232ff916 100644
--- a/arch/m68k/configs/mac_defconfig
+++ b/arch/m68k/configs/mac_defconfig
@@ -701,6 +701,11 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
 #
 # Non-8250 serial port support
 #
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_PMACZILOG=y
+CONFIG_SERIAL_PMACZILOG_TTYS=y
+CONFIG_SERIAL_PMACZILOG_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -834,9 +839,7 @@ CONFIG_HIDRAW=y
 #
 # Character devices
 #
-CONFIG_MAC_SCC=y
 CONFIG_MAC_HID=y
-CONFIG_SERIAL_CONSOLE=y
 
 #
 # File systems
diff --git a/arch/m68k/configs/multi_defconfig b/arch/m68k/configs/multi_defconfig
index 69c43e2d8b45..a8bfa3fa71cf 100644
--- a/arch/m68k/configs/multi_defconfig
+++ b/arch/m68k/configs/multi_defconfig
@@ -822,6 +822,11 @@ CONFIG_A2232=y
 #
 # Non-8250 serial port support
 #
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_PMACZILOG=y
+CONFIG_SERIAL_PMACZILOG_TTYS=y
+CONFIG_SERIAL_PMACZILOG_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -982,7 +987,6 @@ CONFIG_ATARI_MIDI=y
 CONFIG_ATARI_DSP56K=m
 CONFIG_AMIGA_BUILTIN_SERIAL=y
 CONFIG_MULTIFACE_III_TTY=m
-CONFIG_MAC_SCC=y
 CONFIG_MAC_HID=y
 CONFIG_MVME147_SCC=y
 CONFIG_SERIAL167=y
diff --git a/arch/m68k/include/asm/machw.h b/arch/m68k/include/asm/machw.h
index 2b4de0c2ce4a..a22095164927 100644
--- a/arch/m68k/include/asm/machw.h
+++ b/arch/m68k/include/asm/machw.h
@@ -21,29 +21,4 @@
 #define VIDEOMEMSIZE    (4096*1024)
 #define VIDEOMEMMASK    (-4096*1024)
 
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if 0
-/*
-** SCC Z8530
-*/
-
-#define MAC_SCC_BAS (0x50F04000)
-struct MAC_SCC
- {
-  u_char cha_a_ctrl;
-  u_char char_dummy1;
-  u_char cha_a_data;
-  u_char char_dummy2;
-  u_char cha_b_ctrl;
-  u_char char_dummy3;
-  u_char cha_b_data;
- };
-# define mac_scc ((*(volatile struct SCC*)MAC_SCC_BAS))
-#endif
-
-#endif /* __ASSEMBLY__ */
-
 #endif /* linux/machw.h */
diff --git a/arch/m68k/include/asm/macints.h b/arch/m68k/include/asm/macints.h
index 679c48ab4407..ebe1b70fe90c 100644
--- a/arch/m68k/include/asm/macints.h
+++ b/arch/m68k/include/asm/macints.h
@@ -37,7 +37,6 @@
 
 #define VIA1_SOURCE_BASE        8
 #define VIA2_SOURCE_BASE        16
-#define MAC_SCC_SOURCE_BASE     24
 #define PSC3_SOURCE_BASE        24
 #define PSC4_SOURCE_BASE        32
 #define PSC5_SOURCE_BASE        40
@@ -96,26 +95,12 @@
 #define IRQ_PSC3_2        (26)
 #define IRQ_PSC3_3        (27)
 
-/* Level 4 (SCC) interrupts */
-#define IRQ_SCC              (32)
-#define IRQ_SCCA             (33)
-#define IRQ_SCCB             (34)
-#if 0 /* FIXME: are there multiple interrupt conditions on the SCC ?? */
-/* SCC interrupts */
-#define IRQ_SCCB_TX          (32)
-#define IRQ_SCCB_STAT        (33)
-#define IRQ_SCCB_RX          (34)
-#define IRQ_SCCB_SPCOND      (35)
-#define IRQ_SCCA_TX          (36)
-#define IRQ_SCCA_STAT        (37)
-#define IRQ_SCCA_RX          (38)
-#define IRQ_SCCA_SPCOND      (39)
-#endif
-
 /* Level 4 (PSC, AV Macs only) interrupts */
 #define IRQ_PSC4_0        (32)
 #define IRQ_PSC4_1        (33)
+#define IRQ_MAC_SCC_A     IRQ_PSC4_1
 #define IRQ_PSC4_2        (34)
+#define IRQ_MAC_SCC_B     IRQ_PSC4_2
 #define IRQ_PSC4_3        (35)
 #define IRQ_MAC_MACE_DMA  IRQ_PSC4_3
 
@@ -146,6 +131,9 @@
 #define IRQ_BABOON_2      (66)
 #define IRQ_BABOON_3      (67)
 
+/* On non-PSC machines, the serial ports share an IRQ */
+#define IRQ_MAC_SCC       IRQ_AUTO_4
+
 #define SLOT2IRQ(x)       (x + 47)
 #define IRQ2SLOT(x)       (x - 47)
 
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index aca0e28581c7..87174c904d2b 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -115,7 +115,7 @@ extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
  * they are updated on demand.
  */
 static inline void update_mmu_cache(struct vm_area_struct *vma,
-                                    unsigned long address, pte_t pte)
+                                    unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h
index ee4011c23281..21605c736f69 100644
--- a/arch/m68k/include/asm/ptrace.h
+++ b/arch/m68k/include/asm/ptrace.h
@@ -71,6 +71,8 @@ struct switch_stack {
 #define PTRACE_GETFPREGS          14
 #define PTRACE_SETFPREGS          15
 
+#define PTRACE_GET_THREAD_AREA    25
+
 #define PTRACE_SINGLEBLOCK      33      /* resume execution until next branch */
 
 #ifdef __KERNEL__
diff --git a/arch/m68k/include/asm/sigcontext.h b/arch/m68k/include/asm/sigcontext.h
index 523db2a51cf3..1320eaa4cc2a 100644
--- a/arch/m68k/include/asm/sigcontext.h
+++ b/arch/m68k/include/asm/sigcontext.h
@@ -15,9 +15,15 @@ struct sigcontext {
         unsigned long  sc_pc;
         unsigned short sc_formatvec;
 #ifndef __uClinux__
+# ifdef __mcoldfire__
+        unsigned long  sc_fpregs[2][2]; /* room for two fp registers */
+        unsigned long  sc_fpcntl[3];
+        unsigned char  sc_fpstate[16+6*8];
+# else
         unsigned long  sc_fpregs[2*3];  /* room for two fp registers */
         unsigned long  sc_fpcntl[3];
         unsigned char  sc_fpstate[216];
+# endif
 #endif
 };
 
diff --git a/arch/m68k/include/asm/siginfo.h b/arch/m68k/include/asm/siginfo.h
index ca7dde8fd223..851d3d784b53 100644
--- a/arch/m68k/include/asm/siginfo.h
+++ b/arch/m68k/include/asm/siginfo.h
@@ -1,97 +1,6 @@
 #ifndef _M68K_SIGINFO_H
 #define _M68K_SIGINFO_H
 
-#ifndef __uClinux__
-#define HAVE_ARCH_SIGINFO_T
-#define HAVE_ARCH_COPY_SIGINFO
-#endif
-
 #include <asm-generic/siginfo.h>
 
-#ifndef __uClinux__
-
-typedef struct siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[SI_PAD_SIZE];
-
-                /* kill() */
-                struct {
-                        __kernel_pid_t _pid;    /* sender's pid */
-                        __kernel_uid_t _uid;    /* backwards compatibility */
-                        __kernel_uid32_t _uid32; /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        timer_t _tid;           /* timer id */
-                        int _overrun;           /* overrun count */
-                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
-                        sigval_t _sigval;       /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        __kernel_pid_t _pid;    /* sender's pid */
-                        __kernel_uid_t _uid;    /* backwards compatibility */
-                        sigval_t _sigval;
-                        __kernel_uid32_t _uid32; /* sender's uid */
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        __kernel_pid_t _pid;    /* which child */
-                        __kernel_uid_t _uid;    /* backwards compatibility */
-                        int _status;            /* exit code */
-                        clock_t _utime;
-                        clock_t _stime;
-                        __kernel_uid32_t _uid32; /* sender's uid */
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        void *_addr; /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} siginfo_t;
-
-#define UID16_SIGINFO_COMPAT_NEEDED
-
-/*
- * How these fields are to be accessed.
- */
-#undef si_uid
-#ifdef __KERNEL__
-#define si_uid          _sifields._kill._uid32
-#define si_uid16        _sifields._kill._uid
-#else
-#define si_uid          _sifields._kill._uid
-#endif
-
-#ifdef __KERNEL__
-
-#include <linux/string.h>
-
-static inline void copy_siginfo(struct siginfo *to, struct siginfo *from)
-{
-        if (from->si_code < 0)
-                memcpy(to, from, sizeof(*to));
-        else
-                /* _sigchld is currently the largest know union member */
-                memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
-}
-
-#endif /* __KERNEL__ */
-#endif /* !__uClinux__ */
-
 #endif
diff --git a/arch/m68k/include/asm/swab.h b/arch/m68k/include/asm/swab.h
index 5b754aace744..b7b37a40defc 100644
--- a/arch/m68k/include/asm/swab.h
+++ b/arch/m68k/include/asm/swab.h
@@ -14,7 +14,7 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
 }
 
 #define __arch_swab32 __arch_swab32
-#elif !defined(__uClinux__)
+#elif !defined(__mcoldfire__)
 
 static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
 {
diff --git a/arch/m68k/include/asm/thread_info_mm.h b/arch/m68k/include/asm/thread_info_mm.h
index 167e518db41b..67266c683453 100644
--- a/arch/m68k/include/asm/thread_info_mm.h
+++ b/arch/m68k/include/asm/thread_info_mm.h
@@ -16,6 +16,7 @@ struct thread_info {
         struct exec_domain      *exec_domain;   /* execution domain */
         int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
         __u32 cpu; /* should always be 0 on m68k */
+        unsigned long           tp_value;       /* thread pointer */
         struct restart_block    restart_block;
 };
 #endif /* __ASSEMBLY__ */
diff --git a/arch/m68k/include/asm/thread_info_no.h b/arch/m68k/include/asm/thread_info_no.h
index a6512bfdd01d..884776f686ca 100644
--- a/arch/m68k/include/asm/thread_info_no.h
+++ b/arch/m68k/include/asm/thread_info_no.h
@@ -37,6 +37,7 @@ struct thread_info {
         unsigned long      flags;               /* low level flags */
         int                cpu;                 /* cpu we're on */
         int                preempt_count;       /* 0 => preemptable, <0 => BUG */
+        unsigned long      tp_value;            /* thread pointer */
         struct restart_block restart_block;
 };
 
diff --git a/arch/m68k/include/asm/ucontext.h b/arch/m68k/include/asm/ucontext.h
index e4e22669edc0..00dcc5176c57 100644
--- a/arch/m68k/include/asm/ucontext.h
+++ b/arch/m68k/include/asm/ucontext.h
@@ -7,7 +7,11 @@ typedef greg_t gregset_t[NGREG];
 
 typedef struct fpregset {
         int f_fpcntl[3];
+#ifdef __mcoldfire__
+        int f_fpregs[8][2];
+#else
         int f_fpregs[8*3];
+#endif
 } fpregset_t;
 
 struct mcontext {
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 48b87f5ced50..d72a71dabecb 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -336,10 +336,14 @@
 #define __NR_pwritev            330
 #define __NR_rt_tgsigqueueinfo  331
 #define __NR_perf_event_open    332
+#define __NR_get_thread_area    333
+#define __NR_set_thread_area    334
+#define __NR_atomic_cmpxchg_32  335
+#define __NR_atomic_barrier     336
 
 #ifdef __KERNEL__
 
-#define NR_syscalls             333
+#define NR_syscalls             337
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/m68k/include/asm/virtconvert.h b/arch/m68k/include/asm/virtconvert.h
index 3f834b3ab5bd..f35229b8651d 100644
--- a/arch/m68k/include/asm/virtconvert.h
+++ b/arch/m68k/include/asm/virtconvert.h
@@ -31,12 +31,7 @@ static inline void *phys_to_virt(unsigned long address)
 #define page_to_phys(page) \
         __pa(PAGE_OFFSET + (((page) - pg_data_map[0].node_mem_map) << PAGE_SHIFT))
 #else
-#define page_to_phys(_page) ({                                          \
-        struct page *__page = _page;                                    \
-        struct pglist_data *pgdat;                                      \
-        pgdat = pg_data_table[page_to_nid(__page)];                     \
-        page_to_pfn(__page) << PAGE_SHIFT;                              \
-})
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 #endif
 #else
 #define page_to_phys(page)      (((page) - mem_map) << PAGE_SHIFT)
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index 77fc7c16bf48..e136b8cbe9b9 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -761,4 +761,8 @@ sys_call_table:
         .long sys_pwritev               /* 330 */
         .long sys_rt_tgsigqueueinfo
         .long sys_perf_event_open
+        .long sys_get_thread_area
+        .long sys_set_thread_area
+        .long sys_atomic_cmpxchg_32     /* 335 */
+        .long sys_atomic_barrier
 
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index 05296593e718..17c3f325255d 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -251,6 +251,10 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
 
         p->thread.usp = usp;
         p->thread.ksp = (unsigned long)childstack;
+
+        if (clone_flags & CLONE_SETTLS)
+                task_thread_info(p)->tp_value = regs->d5;
+
         /*
          * Must save the current SFC/DFC value, NOT the value when
          * the parent was last descheduled - RGH  10-08-96
diff --git a/arch/m68k/kernel/ptrace.c b/arch/m68k/kernel/ptrace.c
index 1fc217e5f06b..616e59752c29 100644
--- a/arch/m68k/kernel/ptrace.c
+++ b/arch/m68k/kernel/ptrace.c
@@ -245,6 +245,11 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                         ret = -EFAULT;
                 break;
 
+        case PTRACE_GET_THREAD_AREA:
+                ret = put_user(task_thread_info(child)->tp_value,
+                               (unsigned long __user *)data);
+                break;
+
         default:
                 ret = ptrace_request(child, request, addr, data);
                 break;
diff --git a/arch/m68k/kernel/signal.c b/arch/m68k/kernel/signal.c
index de2d05ddd86d..4b387538706f 100644
--- a/arch/m68k/kernel/signal.c
+++ b/arch/m68k/kernel/signal.c
@@ -897,10 +897,17 @@ static void setup_rt_frame (int sig, struct k_sigaction *ka, siginfo_t *info,
 
         /* Set up to return from userspace.  */
         err |= __put_user(frame->retcode, &frame->pretcode);
+#ifdef __mcoldfire__
+        /* movel #__NR_rt_sigreturn,d0; trap #0 */
+        err |= __put_user(0x203c0000, (long __user *)(frame->retcode + 0));
+        err |= __put_user(0x00004e40 + (__NR_rt_sigreturn << 16),
+                          (long __user *)(frame->retcode + 4));
+#else
         /* moveq #,d0; notb d0; trap #0 */
         err |= __put_user(0x70004600 + ((__NR_rt_sigreturn ^ 0xff) << 16),
                           (long __user *)(frame->retcode + 0));
         err |= __put_user(0x4e40, (short __user *)(frame->retcode + 4));
+#endif
 
         if (err)
                 goto give_sigsegv;
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 218f441de667..e3ad2d671973 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -28,6 +28,11 @@
 #include <asm/traps.h>
 #include <asm/page.h>
 #include <asm/unistd.h>
+#include <linux/elf.h>
+#include <asm/tlb.h>
+
+asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
+                             unsigned long error_code);
 
 asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
         unsigned long prot, unsigned long flags,
@@ -595,3 +600,79 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
                         : "d" (__a), "d" (__b), "d" (__c));
         return __res;
 }
+
+asmlinkage unsigned long sys_get_thread_area(void)
+{
+        return current_thread_info()->tp_value;
+}
+
+asmlinkage int sys_set_thread_area(unsigned long tp)
+{
+        current_thread_info()->tp_value = tp;
+        return 0;
+}
+
+/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
+   D1 (newval).  */
+asmlinkage int
+sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
+                      unsigned long __user * mem)
+{
+        /* This was borrowed from ARM's implementation.  */
+        for (;;) {
+                struct mm_struct *mm = current->mm;
+                pgd_t *pgd;
+                pmd_t *pmd;
+                pte_t *pte;
+                spinlock_t *ptl;
+                unsigned long mem_value;
+
+                down_read(&mm->mmap_sem);
+                pgd = pgd_offset(mm, (unsigned long)mem);
+                if (!pgd_present(*pgd))
+                        goto bad_access;
+                pmd = pmd_offset(pgd, (unsigned long)mem);
+                if (!pmd_present(*pmd))
+                        goto bad_access;
+                pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl);
+                if (!pte_present(*pte) || !pte_dirty(*pte)
+                    || !pte_write(*pte)) {
+                        pte_unmap_unlock(pte, ptl);
+                        goto bad_access;
+                }
+
+                mem_value = *mem;
+                if (mem_value == oldval)
+                        *mem = newval;
+
+                pte_unmap_unlock(pte, ptl);
+                up_read(&mm->mmap_sem);
+                return mem_value;
+
+              bad_access:
+                up_read(&mm->mmap_sem);
+                /* This is not necessarily a bad access, we can get here if
+                   a memory we're trying to write to should be copied-on-write.
+                   Make the kernel do the necessary page stuff, then re-iterate.
+                   Simulate a write access fault to do that.  */
+                {
+                        /* The first argument of the function corresponds to
+                           D1, which is the first field of struct pt_regs.  */
+                        struct pt_regs *fp = (struct pt_regs *)&newval;
+
+                        /* '3' is an RMW flag.  */
+                        if (do_page_fault(fp, (unsigned long)mem, 3))
+                                /* If the do_page_fault() failed, we don't
+                                   have anything meaningful to return.
+                                   There should be a SIGSEGV pending for
+                                   the process.  */
+                                return 0xdeadbeef;
+                }
+        }
+}
+
+asmlinkage int sys_atomic_barrier(void)
+{
+        /* no code needed for uniprocs */
+        return 0;
+}
diff --git a/arch/m68k/mac/Makefile b/arch/m68k/mac/Makefile
index daebd80bdef0..b8d4c835f9a2 100644
--- a/arch/m68k/mac/Makefile
+++ b/arch/m68k/mac/Makefile
@@ -3,4 +3,4 @@
 #
 
 obj-y           := config.o macints.o iop.o via.o oss.o psc.o \
-                        baboon.o macboing.o debug.o misc.o
+                        baboon.o macboing.o misc.o
diff --git a/arch/m68k/mac/config.c b/arch/m68k/mac/config.c
index be017984a456..0356da9bf763 100644
--- a/arch/m68k/mac/config.c
+++ b/arch/m68k/mac/config.c
@@ -23,6 +23,8 @@
 #include <linux/init.h>
 #include <linux/vt_kern.h>
 #include <linux/platform_device.h>
+#include <linux/adb.h>
+#include <linux/cuda.h>
 
 #define BOOTINFO_COMPAT_1_0
 #include <asm/setup.h>
@@ -44,12 +46,7 @@
 #include <asm/mac_oss.h>
 #include <asm/mac_psc.h>
 
-/* platform device info */
-
-#define SWIM_IO_SIZE 0x2000     /* SWIM IO resource size */
-
 /* Mac bootinfo struct */
-
 struct mac_booter_data mac_bi_data;
 
 /* The phys. video addr. - might be bogus on some machines */
@@ -70,8 +67,6 @@ extern void baboon_init(void);
 
 extern void mac_mksound(unsigned int, unsigned int);
 
-extern void nubus_sweep_video(void);
-
 static void mac_get_model(char *str);
 static void mac_identify(void);
 static void mac_report_hardware(void);
@@ -168,12 +163,6 @@ void __init config_mac(void)
 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
         mach_beep = mac_mksound;
 #endif
-#ifdef CONFIG_HEARTBEAT
-#if 0
-        mach_heartbeat = mac_heartbeat;
-        mach_heartbeat_irq = IRQ_MAC_TIMER;
-#endif
-#endif
 
         /*
          * Determine hardware present
@@ -191,27 +180,19 @@ void __init config_mac(void)
         if (macintosh_config->ident == MAC_MODEL_IICI
             || macintosh_config->ident == MAC_MODEL_IIFX)
                 mach_l2_flush = mac_cache_card_flush;
-
-        /*
-         * Check for machine specific fixups.
-         */
-
-#ifdef OLD_NUBUS_CODE
-        nubus_sweep_video();
-#endif
 }
 
 
 /*
- *      Macintosh Table: hardcoded model configuration data.
+ * Macintosh Table: hardcoded model configuration data.
  *
- *      Much of this was defined by Alan, based on who knows what docs.
- *      I've added a lot more, and some of that was pure guesswork based
- *      on hardware pages present on the Mac web site. Possibly wildly
- *      inaccurate, so look here if a new Mac model won't run. Example: if
- *      a Mac crashes immediately after the VIA1 registers have been dumped
- *      to the screen, it probably died attempting to read DirB on a RBV.
- *      Meaning it should have MAC_VIA_IIci here :-)
+ * Much of this was defined by Alan, based on who knows what docs.
+ * I've added a lot more, and some of that was pure guesswork based
+ * on hardware pages present on the Mac web site. Possibly wildly
+ * inaccurate, so look here if a new Mac model won't run. Example: if
+ * a Mac crashes immediately after the VIA1 registers have been dumped
+ * to the screen, it probably died attempting to read DirB on a RBV.
+ * Meaning it should have MAC_VIA_IIci here :-)
  */
 
 struct mac_model *macintosh_config;
@@ -219,7 +200,7 @@ EXPORT_SYMBOL(macintosh_config);
 
 static struct mac_model mac_data_table[] = {
         /*
-         *      We'll pretend to be a Macintosh II, that's pretty safe.
+         * We'll pretend to be a Macintosh II, that's pretty safe.
          */
 
         {
@@ -230,12 +211,11 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_IWM
+                .floppy_type    = MAC_FLOPPY_IWM,
         },
 
         /*
-         *      Original MacII hardware
-         *
+         * Original Mac II hardware
          */
 
         {
@@ -246,7 +226,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_IWM
+                .floppy_type    = MAC_FLOPPY_IWM,
         }, {
                 .ident          = MAC_MODEL_IIX,
                 .name           = "IIx",
@@ -255,7 +235,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_IICX,
                 .name           = "IIcx",
@@ -264,7 +244,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_SE30,
                 .name           = "SE/30",
@@ -273,13 +253,13 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
-         *      Weirdified MacII hardware - all subtly different. Gee thanks
-         *      Apple. All these boxes seem to have VIA2 in a different place to
-         *      the MacII (+1A000 rather than +4000)
+         * Weirdified Mac II hardware - all subtly different. Gee thanks
+         * Apple. All these boxes seem to have VIA2 in a different place to
+         * the Mac II (+1A000 rather than +4000)
          * CSA: see http://developer.apple.com/technotes/hw/hw_09.html
          */
 
@@ -291,7 +271,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_IIFX,
                 .name           = "IIfx",
@@ -300,7 +280,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_IOP,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_IOP
+                .floppy_type    = MAC_FLOPPY_SWIM_IOP,
         }, {
                 .ident          = MAC_MODEL_IISI,
                 .name           = "IIsi",
@@ -309,7 +289,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_IIVI,
                 .name           = "IIvi",
@@ -318,7 +298,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_IIVX,
                 .name           = "IIvx",
@@ -327,11 +307,11 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
-         *      Classic models (guessing: similar to SE/30 ?? Nope, similar to LC ...)
+         * Classic models (guessing: similar to SE/30? Nope, similar to LC...)
          */
 
         {
@@ -342,7 +322,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_CCL,
                 .name           = "Color Classic",
@@ -351,11 +331,11 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
-         *      Some Mac LC machines. Basically the same as the IIci, ADB like IIsi
+         * Some Mac LC machines. Basically the same as the IIci, ADB like IIsi
          */
 
         {
@@ -366,7 +346,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_LCII,
                 .name           = "LC II",
@@ -375,7 +355,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_LCIII,
                 .name           = "LC III",
@@ -384,17 +364,17 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
-         *      Quadra. Video is at 0xF9000000, via is like a MacII. We label it differently
-         *      as some of the stuff connected to VIA2 seems different. Better SCSI chip and
-         *      onboard ethernet using a NatSemi SONIC except the 660AV and 840AV which use an
-         *      AMD 79C940 (MACE).
-         *      The 700, 900 and 950 have some I/O chips in the wrong place to
-         *      confuse us. The 840AV has a SCSI location of its own (same as
-         *      the 660AV).
+         * Quadra. Video is at 0xF9000000, via is like a MacII. We label it
+         * differently as some of the stuff connected to VIA2 seems different.
+         * Better SCSI chip and onboard ethernet using a NatSemi SONIC except
+         * the 660AV and 840AV which use an AMD 79C940 (MACE).
+         * The 700, 900 and 950 have some I/O chips in the wrong place to
+         * confuse us. The 840AV has a SCSI location of its own (same as
+         * the 660AV).
          */
 
         {
@@ -405,7 +385,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_QUADRA,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_Q605_ACC,
                 .name           = "Quadra 605",
@@ -414,7 +394,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_QUADRA,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_Q610,
                 .name           = "Quadra 610",
@@ -424,7 +404,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_Q630,
                 .name           = "Quadra 630",
@@ -435,7 +415,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_Q650,
                 .name           = "Quadra 650",
@@ -445,9 +425,9 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         },
-        /*      The Q700 does have a NS Sonic */
+        /* The Q700 does have a NS Sonic */
         {
                 .ident          = MAC_MODEL_Q700,
                 .name           = "Quadra 700",
@@ -457,7 +437,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_Q800,
                 .name           = "Quadra 800",
@@ -467,7 +447,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_Q840,
                 .name           = "Quadra 840AV",
@@ -477,7 +457,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_PSC,
                 .ether_type     = MAC_ETHER_MACE,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_AV
+                .floppy_type    = MAC_FLOPPY_AV,
         }, {
                 .ident          = MAC_MODEL_Q900,
                 .name           = "Quadra 900",
@@ -487,7 +467,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_IOP,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_IOP
+                .floppy_type    = MAC_FLOPPY_SWIM_IOP,
         }, {
                 .ident          = MAC_MODEL_Q950,
                 .name           = "Quadra 950",
@@ -497,60 +477,60 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_IOP,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_IOP
+                .floppy_type    = MAC_FLOPPY_SWIM_IOP,
         },
 
         /*
-         *      Performa - more LC type machines
+         * Performa - more LC type machines
          */
 
         {
                 .ident          = MAC_MODEL_P460,
-                .name           =  "Performa 460",
+                .name           = "Performa 460",
                 .adb_type       = MAC_ADB_IISI,
                 .via_type       = MAC_VIA_IIci,
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_P475,
-                .name           =  "Performa 475",
+                .name           = "Performa 475",
                 .adb_type       = MAC_ADB_CUDA,
                 .via_type       = MAC_VIA_QUADRA,
                 .scsi_type      = MAC_SCSI_QUADRA,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_P475F,
-                .name           =  "Performa 475",
+                .name           = "Performa 475",
                 .adb_type       = MAC_ADB_CUDA,
                 .via_type       = MAC_VIA_QUADRA,
                 .scsi_type      = MAC_SCSI_QUADRA,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_P520,
-                .name           =  "Performa 520",
+                .name           = "Performa 520",
                 .adb_type       = MAC_ADB_CUDA,
                 .via_type       = MAC_VIA_IIci,
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_P550,
-                .name           =  "Performa 550",
+                .name           = "Performa 550",
                 .adb_type       = MAC_ADB_CUDA,
                 .via_type       = MAC_VIA_IIci,
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
-        /* These have the comm slot, and therefore the possibility of SONIC ethernet */
+        /* These have the comm slot, and therefore possibly SONIC ethernet */
         {
                 .ident          = MAC_MODEL_P575,
                 .name           = "Performa 575",
@@ -560,7 +540,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_II,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_P588,
                 .name           = "Performa 588",
@@ -571,7 +551,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_II,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_TV,
                 .name           = "TV",
@@ -580,7 +560,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_P600,
                 .name           = "Performa 600",
@@ -589,14 +569,14 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_II,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
-         *      Centris - just guessing again; maybe like Quadra
+         * Centris - just guessing again; maybe like Quadra.
+         * The C610 may or may not have SONIC. We probe to make sure.
          */
 
-        /* The C610 may or may not have SONIC.  We probe to make sure */
         {
                 .ident          = MAC_MODEL_C610,
                 .name           = "Centris 610",
@@ -606,7 +586,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_C650,
                 .name           = "Centris 650",
@@ -616,7 +596,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR1,
         }, {
                 .ident          = MAC_MODEL_C660,
                 .name           = "Centris 660AV",
@@ -626,7 +606,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_PSC,
                 .ether_type     = MAC_ETHER_MACE,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_AV
+                .floppy_type    = MAC_FLOPPY_AV,
         },
 
         /*
@@ -643,7 +623,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB145,
                 .name           = "PowerBook 145",
@@ -652,7 +632,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB150,
                 .name           = "PowerBook 150",
@@ -662,7 +642,7 @@ static struct mac_model mac_data_table[] = {
                 .ide_type       = MAC_IDE_PB,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB160,
                 .name           = "PowerBook 160",
@@ -671,7 +651,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB165,
                 .name           = "PowerBook 165",
@@ -680,7 +660,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB165C,
                 .name           = "PowerBook 165c",
@@ -689,7 +669,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB170,
                 .name           = "PowerBook 170",
@@ -698,7 +678,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB180,
                 .name           = "PowerBook 180",
@@ -707,7 +687,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB180C,
                 .name           = "PowerBook 180c",
@@ -716,7 +696,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB190,
                 .name           = "PowerBook 190",
@@ -726,7 +706,7 @@ static struct mac_model mac_data_table[] = {
                 .ide_type       = MAC_IDE_BABOON,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB520,
                 .name           = "PowerBook 520",
@@ -736,7 +716,7 @@ static struct mac_model mac_data_table[] = {
                 .scc_type       = MAC_SCC_QUADRA,
                 .ether_type     = MAC_ETHER_SONIC,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
@@ -757,7 +737,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB230,
                 .name           = "PowerBook Duo 230",
@@ -766,7 +746,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB250,
                 .name           = "PowerBook Duo 250",
@@ -775,7 +755,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB270C,
                 .name           = "PowerBook Duo 270c",
@@ -784,7 +764,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB280,
                 .name           = "PowerBook Duo 280",
@@ -793,7 +773,7 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         }, {
                 .ident          = MAC_MODEL_PB280C,
                 .name           = "PowerBook Duo 280c",
@@ -802,17 +782,44 @@ static struct mac_model mac_data_table[] = {
                 .scsi_type      = MAC_SCSI_OLD,
                 .scc_type       = MAC_SCC_QUADRA,
                 .nubus_type     = MAC_NUBUS,
-                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2
+                .floppy_type    = MAC_FLOPPY_SWIM_ADDR2,
         },
 
         /*
-         *      Other stuff ??
+         * Other stuff?
          */
+
         {
                 .ident          = -1
         }
 };
 
+static struct resource scc_a_rsrcs[] = {
+        { .flags = IORESOURCE_MEM },
+        { .flags = IORESOURCE_IRQ },
+};
+
+static struct resource scc_b_rsrcs[] = {
+        { .flags = IORESOURCE_MEM },
+        { .flags = IORESOURCE_IRQ },
+};
+
+struct platform_device scc_a_pdev = {
+        .name           = "scc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(scc_a_rsrcs),
+        .resource       = scc_a_rsrcs,
+};
+EXPORT_SYMBOL(scc_a_pdev);
+
+struct platform_device scc_b_pdev = {
+        .name           = "scc",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(scc_b_rsrcs),
+        .resource       = scc_b_rsrcs,
+};
+EXPORT_SYMBOL(scc_b_pdev);
+
 static void __init mac_identify(void)
 {
         struct mac_model *m;
@@ -823,7 +830,8 @@ static void __init mac_identify(void)
                 /* no bootinfo model id -> NetBSD booter was used! */
                 /* XXX FIXME: breaks for model > 31 */
                 model = (mac_bi_data.cpuid >> 2) & 63;
-                printk(KERN_WARNING "No bootinfo model ID, using cpuid instead (hey, use Penguin!)\n");
+                printk(KERN_WARNING "No bootinfo model ID, using cpuid instead "
+                       "(obsolete bootloader?)\n");
         }
 
         macintosh_config = mac_data_table;
@@ -834,10 +842,29 @@ static void __init mac_identify(void)
                 }
         }
 
-        /* We need to pre-init the IOPs, if any. Otherwise */
-        /* the serial console won't work if the user had   */
-        /* the serial ports set to "Faster" mode in MacOS. */
+        /* Set up serial port resources for the console initcall. */
+
+        scc_a_rsrcs[0].start = (resource_size_t) mac_bi_data.sccbase + 2;
+        scc_a_rsrcs[0].end   = scc_a_rsrcs[0].start;
+        scc_b_rsrcs[0].start = (resource_size_t) mac_bi_data.sccbase;
+        scc_b_rsrcs[0].end   = scc_b_rsrcs[0].start;
 
+        switch (macintosh_config->scc_type) {
+        case MAC_SCC_PSC:
+                scc_a_rsrcs[1].start = scc_a_rsrcs[1].end = IRQ_MAC_SCC_A;
+                scc_b_rsrcs[1].start = scc_b_rsrcs[1].end = IRQ_MAC_SCC_B;
+                break;
+        default:
+                scc_a_rsrcs[1].start = scc_a_rsrcs[1].end = IRQ_MAC_SCC;
+                scc_b_rsrcs[1].start = scc_b_rsrcs[1].end = IRQ_MAC_SCC;
+                break;
+        }
+
+        /*
+         * We need to pre-init the IOPs, if any. Otherwise
+         * the serial console won't work if the user had
+         * the serial ports set to "Faster" mode in MacOS.
+         */
         iop_preinit();
 
         printk(KERN_INFO "Detected Macintosh model: %d \n", model);
@@ -846,7 +873,8 @@ static void __init mac_identify(void)
          * Report booter data:
          */
         printk(KERN_DEBUG " Penguin bootinfo data:\n");
-        printk(KERN_DEBUG " Video: addr 0x%lx row 0x%lx depth %lx dimensions %ld x %ld\n",
+        printk(KERN_DEBUG " Video: addr 0x%lx "
+                "row 0x%lx depth %lx dimensions %ld x %ld\n",
                 mac_bi_data.videoaddr, mac_bi_data.videorow,
                 mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF,
                 mac_bi_data.dimensions >> 16);
@@ -863,6 +891,10 @@ static void __init mac_identify(void)
         oss_init();
         psc_init();
         baboon_init();
+
+#ifdef CONFIG_ADB_CUDA
+        find_via_cuda();
+#endif
 }
 
 static void __init mac_report_hardware(void)
@@ -876,23 +908,50 @@ static void mac_get_model(char *str)
         strcat(str, macintosh_config->name);
 }
 
-static struct resource swim_resources[1];
+static struct resource swim_rsrc = { .flags = IORESOURCE_MEM };
 
-static struct platform_device swim_device = {
+static struct platform_device swim_pdev = {
         .name           = "swim",
         .id             = -1,
-        .num_resources  = ARRAY_SIZE(swim_resources),
-        .resource       = swim_resources,
+        .num_resources  = 1,
+        .resource       = &swim_rsrc,
 };
 
-static struct platform_device *mac_platform_devices[] __initdata = {
-        &swim_device
+static struct platform_device esp_0_pdev = {
+        .name           = "mac_esp",
+        .id             = 0,
+};
+
+static struct platform_device esp_1_pdev = {
+        .name           = "mac_esp",
+        .id             = 1,
+};
+
+static struct platform_device sonic_pdev = {
+        .name           = "macsonic",
+        .id             = -1,
+};
+
+static struct platform_device mace_pdev = {
+        .name           = "macmace",
+        .id             = -1,
 };
 
 int __init mac_platform_init(void)
 {
         u8 *swim_base;
 
+        /*
+         * Serial devices
+         */
+
+        platform_device_register(&scc_a_pdev);
+        platform_device_register(&scc_b_pdev);
+
+        /*
+         * Floppy device
+         */
+
         switch (macintosh_config->floppy_type) {
         case MAC_FLOPPY_SWIM_ADDR1:
                 swim_base = (u8 *)(VIA1_BASE + 0x1E000);
@@ -901,16 +960,47 @@ int __init mac_platform_init(void)
                 swim_base = (u8 *)(VIA1_BASE + 0x16000);
                 break;
         default:
-                return 0;
+                swim_base = NULL;
+                break;
         }
 
-        swim_resources[0].name = "swim-regs";
-        swim_resources[0].start = (resource_size_t)swim_base;
-        swim_resources[0].end = (resource_size_t)(swim_base + SWIM_IO_SIZE);
-        swim_resources[0].flags = IORESOURCE_MEM;
+        if (swim_base) {
+                swim_rsrc.start = (resource_size_t) swim_base,
+                swim_rsrc.end   = (resource_size_t) swim_base + 0x2000,
+                platform_device_register(&swim_pdev);
+        }
+
+        /*
+         * SCSI device(s)
+         */
+
+        switch (macintosh_config->scsi_type) {
+        case MAC_SCSI_QUADRA:
+        case MAC_SCSI_QUADRA3:
+                platform_device_register(&esp_0_pdev);
+                break;
+        case MAC_SCSI_QUADRA2:
+                platform_device_register(&esp_0_pdev);
+                if ((macintosh_config->ident == MAC_MODEL_Q900) ||
+                    (macintosh_config->ident == MAC_MODEL_Q950))
+                        platform_device_register(&esp_1_pdev);
+                break;
+        }
+
+        /*
+         * Ethernet device
+         */
+
+        switch (macintosh_config->ether_type) {
+        case MAC_ETHER_SONIC:
+                platform_device_register(&sonic_pdev);
+                break;
+        case MAC_ETHER_MACE:
+                platform_device_register(&mace_pdev);
+                break;
+        }
 
-        return platform_add_devices(mac_platform_devices,
-                                    ARRAY_SIZE(mac_platform_devices));
+        return 0;
 }
 
 arch_initcall(mac_platform_init);
diff --git a/arch/m68k/mac/debug.c b/arch/m68k/mac/debug.c
deleted file mode 100644
index bce074ceb768..000000000000
--- a/arch/m68k/mac/debug.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * linux/arch/m68k/mac/debug.c
- *
- * Shamelessly stolen (SCC code and general framework) from:
- *
- * linux/arch/m68k/atari/debug.c
- *
- * Atari debugging and serial console stuff
- *
- * Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/tty.h>
-#include <linux/console.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-
-#define BOOTINFO_COMPAT_1_0
-#include <asm/setup.h>
-#include <asm/bootinfo.h>
-#include <asm/macints.h>
-
-extern unsigned long mac_videobase;
-extern unsigned long mac_rowbytes;
-
-extern void mac_serial_print(const char *);
-
-#define DEBUG_HEADS
-#undef DEBUG_SCREEN
-#define DEBUG_SERIAL
-
-/*
- * These two auxiliary debug functions should go away ASAP. Only usage:
- * before the console output is up (after head.S come some other crucial
- * setup routines :-) it permits writing 'data' to the screen as bit patterns
- * (good luck reading those). Helped to figure that the bootinfo contained
- * garbage data on the amount and size of memory chunks ...
- *
- * The 'pos' argument now simply means 'linefeed after print' ...
- */
-
-#ifdef DEBUG_SCREEN
-static int peng, line;
-#endif
-
-#if 0
-
-void mac_debugging_short(int pos, short num)
-{
-#ifdef DEBUG_SCREEN
-        unsigned char *pengoffset;
-        unsigned char *pptr;
-        int i;
-#endif
-
-#ifdef DEBUG_SERIAL
-        printk("debug: %d !\n", num);
-#endif
-
-#ifdef DEBUG_SCREEN
-        if (!MACH_IS_MAC) {
-                /* printk("debug: %d !\n", num); */
-                return;
-        }
-
-        /* calculate current offset */
-        pengoffset = (unsigned char *)mac_videobase +
-                (150+line*2) * mac_rowbytes + 80 * peng;
-
-        pptr = pengoffset;
-
-        for (i = 0; i < 8 * sizeof(short); i++) { /* # of bits */
-                /*        value        mask for bit i, reverse order */
-                *pptr++ = (num & (1 << (8*sizeof(short)-i-1)) ? 0xFF : 0x00);
-        }
-
-        peng++;
-
-        if (pos) {
-                line++;
-                peng = 0;
-        }
-#endif
-}
-
-void mac_debugging_long(int pos, long addr)
-{
-#ifdef DEBUG_SCREEN
-        unsigned char *pengoffset;
-        unsigned char *pptr;
-        int i;
-#endif
-
-#ifdef DEBUG_SERIAL
-        printk("debug: #%ld !\n", addr);
-#endif
-
-#ifdef DEBUG_SCREEN
-        if (!MACH_IS_MAC) {
-                /* printk("debug: #%ld !\n", addr); */
-                return;
-        }
-
-        pengoffset=(unsigned char *)(mac_videobase+(150+line*2)*mac_rowbytes)
-                    +80*peng;
-
-        pptr = pengoffset;
-
-        for (i = 0; i < 8 * sizeof(long); i++) { /* # of bits */
-                *pptr++ = (addr & (1 << (8*sizeof(long)-i-1)) ? 0xFF : 0x00);
-        }
-
-        peng++;
-
-        if (pos) {
-                line++;
-                peng = 0;
-        }
-#endif
-}
-
-#endif  /*  0  */
-
-#ifdef DEBUG_SERIAL
-/*
- * TODO: serial debug code
- */
-
-struct mac_SCC {
-        u_char cha_b_ctrl;
-        u_char char_dummy1;
-        u_char cha_a_ctrl;
-        u_char char_dummy2;
-        u_char cha_b_data;
-        u_char char_dummy3;
-        u_char cha_a_data;
-};
-
-# define scc (*((volatile struct mac_SCC*)mac_bi_data.sccbase))
-
-static int scc_port = -1;
-
-static struct console mac_console_driver = {
-        .name   = "debug",
-        .flags  = CON_PRINTBUFFER,
-        .index  = -1,
-};
-
-/*
- * Crude hack to get console output to the screen before the framebuffer
- * is initialized (happens a lot later in 2.1!).
- * We just use the console routines declared in head.S, this will interfere
- * with regular framebuffer console output and should be used exclusively
- * to debug kernel problems manifesting before framebuffer init (aka WSOD)
- *
- * To keep this hack from interfering with the regular console driver, either
- * deregister this driver before/on framebuffer console init, or silence this
- * function after the fbcon driver is running (will lose console messages!?).
- * To debug real early bugs, need to write a 'mac_register_console_hack()'
- * that is called from start_kernel() before setup_arch() and just registers
- * this driver if Mac.
- */
-
-static void mac_debug_console_write(struct console *co, const char *str,
-                                    unsigned int count)
-{
-        mac_serial_print(str);
-}
-
-
-
-/* Mac: loops_per_jiffy min. 19000 ^= .5 us; MFPDELAY was 0.6 us*/
-
-#define uSEC 1
-
-static inline void mac_sccb_out(char c)
-{
-        int i;
-
-        do {
-                for (i = uSEC; i > 0; --i)
-                        barrier();
-        } while (!(scc.cha_b_ctrl & 0x04)); /* wait for tx buf empty */
-        for (i = uSEC; i > 0; --i)
-                barrier();
-        scc.cha_b_data = c;
-}
-
-static inline void mac_scca_out(char c)
-{
-        int i;
-
-        do {
-                for (i = uSEC; i > 0; --i)
-                        barrier();
-        } while (!(scc.cha_a_ctrl & 0x04)); /* wait for tx buf empty */
-        for (i = uSEC; i > 0; --i)
-                barrier();
-        scc.cha_a_data = c;
-}
-
-static void mac_sccb_console_write(struct console *co, const char *str,
-                                   unsigned int count)
-{
-        while (count--) {
-                if (*str == '\n')
-                        mac_sccb_out('\r');
-                mac_sccb_out(*str++);
-        }
-}
-
-static void mac_scca_console_write(struct console *co, const char *str,
-                                   unsigned int count)
-{
-        while (count--) {
-                if (*str == '\n')
-                        mac_scca_out('\r');
-                mac_scca_out(*str++);
-        }
-}
-
-
-/* The following two functions do a quick'n'dirty initialization of the MFP or
- * SCC serial ports. They're used by the debugging interface, kgdb, and the
- * serial console code. */
-#define SCCB_WRITE(reg,val)                             \
-        do {                                            \
-                int i;                                  \
-                scc.cha_b_ctrl = (reg);                 \
-                for (i = uSEC; i > 0; --i)              \
-                        barrier();                      \
-                scc.cha_b_ctrl = (val);                 \
-                for (i = uSEC; i > 0; --i)              \
-                        barrier();                      \
-        } while(0)
-
-#define SCCA_WRITE(reg,val)                             \
-        do {                                            \
-                int i;                                  \
-                scc.cha_a_ctrl = (reg);                 \
-                for (i = uSEC; i > 0; --i)              \
-                        barrier();                      \
-                scc.cha_a_ctrl = (val);                 \
-                for (i = uSEC; i > 0; --i)              \
-                        barrier();                      \
-        } while(0)
-
-/* loops_per_jiffy isn't initialized yet, so we can't use udelay(). This does a
- * delay of ~ 60us. */
-/* Mac: loops_per_jiffy min. 19000 ^= .5 us; MFPDELAY was 0.6 us*/
-#define LONG_DELAY()                                    \
-        do {                                            \
-                int i;                                  \
-                for (i = 60*uSEC; i > 0; --i)           \
-                    barrier();                          \
-        } while(0)
-
-static void __init mac_init_scc_port(int cflag, int port)
-{
-        /*
-         * baud rates: 1200, 1800, 2400, 4800, 9600, 19.2k, 38.4k, 57.6k, 115.2k
-         */
-
-        static int clksrc_table[9] =
-                /* reg 11: 0x50 = BRG, 0x00 = RTxC, 0x28 = TRxC */
-                { 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 };
-        static int clkmode_table[9] =
-                /* reg 4: 0x40 = x16, 0x80 = x32, 0xc0 = x64 */
-                { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0xc0, 0x80 };
-        static int div_table[9] =
-                /* reg12 (BRG low) */
-                { 94, 62, 46, 22, 10, 4, 1, 0, 0 };
-
-        int baud = cflag & CBAUD;
-        int clksrc, clkmode, div, reg3, reg5;
-
-        if (cflag & CBAUDEX)
-                baud += B38400;
-        if (baud < B1200 || baud > B38400+2)
-                baud = B9600; /* use default 9600bps for non-implemented rates */
-        baud -= B1200; /* tables starts at 1200bps */
-
-        clksrc  = clksrc_table[baud];
-        clkmode = clkmode_table[baud];
-        div     = div_table[baud];
-
-        reg3 = (((cflag & CSIZE) == CS8) ? 0xc0 : 0x40);
-        reg5 = (((cflag & CSIZE) == CS8) ? 0x60 : 0x20) | 0x82 /* assert DTR/RTS */;
-
-        if (port == 1) {
-                (void)scc.cha_b_ctrl;   /* reset reg pointer */
-                SCCB_WRITE(9, 0xc0);    /* reset */
-                LONG_DELAY();           /* extra delay after WR9 access */
-                SCCB_WRITE(4, (cflag & PARENB) ? ((cflag & PARODD) ? 0x01 : 0x03) : 0 |
-                           0x04 /* 1 stopbit */ |
-                           clkmode);
-                SCCB_WRITE(3, reg3);
-                SCCB_WRITE(5, reg5);
-                SCCB_WRITE(9, 0);       /* no interrupts */
-                LONG_DELAY();           /* extra delay after WR9 access */
-                SCCB_WRITE(10, 0);      /* NRZ mode */
-                SCCB_WRITE(11, clksrc); /* main clock source */
-                SCCB_WRITE(12, div);    /* BRG value */
-                SCCB_WRITE(13, 0);      /* BRG high byte */
-                SCCB_WRITE(14, 1);
-                SCCB_WRITE(3, reg3 | 1);
-                SCCB_WRITE(5, reg5 | 8);
-        } else if (port == 0) {
-                (void)scc.cha_a_ctrl;   /* reset reg pointer */
-                SCCA_WRITE(9, 0xc0);    /* reset */
-                LONG_DELAY();           /* extra delay after WR9 access */
-                SCCA_WRITE(4, (cflag & PARENB) ? ((cflag & PARODD) ? 0x01 : 0x03) : 0 |
-                          0x04 /* 1 stopbit */ |
-                          clkmode);
-                SCCA_WRITE(3, reg3);
-                SCCA_WRITE(5, reg5);
-                SCCA_WRITE(9, 0);       /* no interrupts */
-                LONG_DELAY();           /* extra delay after WR9 access */
-                SCCA_WRITE(10, 0);      /* NRZ mode */
-                SCCA_WRITE(11, clksrc); /* main clock source */
-                SCCA_WRITE(12, div);    /* BRG value */
-                SCCA_WRITE(13, 0);      /* BRG high byte */
-                SCCA_WRITE(14, 1);
-                SCCA_WRITE(3, reg3 | 1);
-                SCCA_WRITE(5, reg5 | 8);
-        }
-}
-#endif /* DEBUG_SERIAL */
-
-static int __init mac_debug_setup(char *arg)
-{
-        if (!MACH_IS_MAC)
-                return 0;
-
-#ifdef DEBUG_SERIAL
-        if (!strcmp(arg, "ser") || !strcmp(arg, "ser1")) {
-                /* Mac modem port */
-                mac_init_scc_port(B9600|CS8, 0);
-                mac_console_driver.write = mac_scca_console_write;
-                scc_port = 0;
-        } else if (!strcmp(arg, "ser2")) {
-                /* Mac printer port */
-                mac_init_scc_port(B9600|CS8, 1);
-                mac_console_driver.write = mac_sccb_console_write;
-                scc_port = 1;
-        }
-#endif
-#ifdef DEBUG_HEADS
-        if (!strcmp(arg, "scn") || !strcmp(arg, "con")) {
-                /* display, using head.S console routines */
-                mac_console_driver.write = mac_debug_console_write;
-        }
-#endif
-        if (mac_console_driver.write)
-                register_console(&mac_console_driver);
-        return 0;
-}
-
-early_param("debug", mac_debug_setup);
diff --git a/arch/m68k/mac/macints.c b/arch/m68k/mac/macints.c
index 23711074e0e2..900d899f3323 100644
--- a/arch/m68k/mac/macints.c
+++ b/arch/m68k/mac/macints.c
@@ -34,9 +34,7 @@
  *
  *      3       - unused (?)
  *
- *      4       - SCC (slot number determined by reading RR3 on the SSC itself)
- *                - slot 1: SCC channel A
- *                - slot 2: SCC channel B
+ *      4       - SCC
  *
  *      5       - unused (?)
  *                [serial errors or special conditions seem to raise level 6
@@ -55,8 +53,6 @@
  *                - slot 5: Slot $E
  *
  *      4       - SCC IOP
- *                - slot 1: SCC channel A
- *                - slot 2: SCC channel B
  *
  *      5       - ISM IOP (ADB?)
  *
@@ -136,13 +132,8 @@
 #include <asm/irq_regs.h>
 #include <asm/mac_oss.h>
 
-#define DEBUG_SPURIOUS
 #define SHUTUP_SONIC
 
-/* SCC interrupt mask */
-
-static int scc_mask;
-
 /*
  * VIA/RBV hooks
  */
@@ -191,13 +182,6 @@ extern void baboon_irq_disable(int);
 extern void baboon_irq_clear(int);
 
 /*
- * SCC interrupt routines
- */
-
-static void scc_irq_enable(unsigned int);
-static void scc_irq_disable(unsigned int);
-
-/*
  * console_loglevel determines NMI handler function
  */
 
@@ -221,8 +205,6 @@ void __init mac_init_IRQ(void)
 #ifdef DEBUG_MACINTS
         printk("mac_init_IRQ(): Setting things up...\n");
 #endif
-        scc_mask = 0;
-
         m68k_setup_irq_controller(&mac_irq_controller, IRQ_USER,
                                   NUM_MAC_SOURCES - IRQ_USER);
         /* Make sure the SONIC interrupt is cleared or things get ugly */
@@ -283,15 +265,16 @@ void mac_enable_irq(unsigned int irq)
                         via_irq_enable(irq);
                 break;
         case 3:
-        case 4:
         case 5:
         case 6:
                 if (psc_present)
                         psc_irq_enable(irq);
                 else if (oss_present)
                         oss_irq_enable(irq);
-                else if (irq_src == 4)
-                        scc_irq_enable(irq);
+                break;
+        case 4:
+                if (psc_present)
+                        psc_irq_enable(irq);
                 break;
         case 8:
                 if (baboon_present)
@@ -316,15 +299,16 @@ void mac_disable_irq(unsigned int irq)
                         via_irq_disable(irq);
                 break;
         case 3:
-        case 4:
         case 5:
         case 6:
                 if (psc_present)
                         psc_irq_disable(irq);
                 else if (oss_present)
                         oss_irq_disable(irq);
-                else if (irq_src == 4)
-                        scc_irq_disable(irq);
+                break;
+        case 4:
+                if (psc_present)
+                        psc_irq_disable(irq);
                 break;
         case 8:
                 if (baboon_present)
@@ -347,7 +331,6 @@ void mac_clear_irq(unsigned int irq)
                         via_irq_clear(irq);
                 break;
         case 3:
-        case 4:
         case 5:
         case 6:
                 if (psc_present)
@@ -355,6 +338,10 @@ void mac_clear_irq(unsigned int irq)
                 else if (oss_present)
                         oss_irq_clear(irq);
                 break;
+        case 4:
+                if (psc_present)
+                        psc_irq_clear(irq);
+                break;
         case 8:
                 if (baboon_present)
                         baboon_irq_clear(irq);
@@ -374,13 +361,17 @@ int mac_irq_pending(unsigned int irq)
                 else
                         return via_irq_pending(irq);
         case 3:
-        case 4:
         case 5:
         case 6:
                 if (psc_present)
                         return psc_irq_pending(irq);
                 else if (oss_present)
                         return oss_irq_pending(irq);
+                break;
+        case 4:
+                if (psc_present)
+                        psc_irq_pending(irq);
+                break;
         }
         return 0;
 }
@@ -448,59 +439,3 @@ irqreturn_t mac_nmi_handler(int irq, void *dev_id)
         in_nmi--;
         return IRQ_HANDLED;
 }
-
-/*
- * Simple routines for masking and unmasking
- * SCC interrupts in cases where this can't be
- * done in hardware (only the PSC can do that.)
- */
-
-static void scc_irq_enable(unsigned int irq)
-{
-        int irq_idx = IRQ_IDX(irq);
-
-        scc_mask |= (1 << irq_idx);
-}
-
-static void scc_irq_disable(unsigned int irq)
-{
-        int irq_idx = IRQ_IDX(irq);
-
-        scc_mask &= ~(1 << irq_idx);
-}
-
-/*
- * SCC master interrupt handler. We have to do a bit of magic here
- * to figure out what channel gave us the interrupt; putting this
- * here is cleaner than hacking it into drivers/char/macserial.c.
- */
-
-void mac_scc_dispatch(int irq, void *dev_id)
-{
-        volatile unsigned char *scc = (unsigned char *) mac_bi_data.sccbase + 2;
-        unsigned char reg;
-        unsigned long flags;
-
-        /* Read RR3 from the chip. Always do this on channel A */
-        /* This must be an atomic operation so disable irqs.   */
-
-        local_irq_save(flags);
-        *scc = 3;
-        reg = *scc;
-        local_irq_restore(flags);
-
-        /* Now dispatch. Bits 0-2 are for channel B and */
-        /* bits 3-5 are for channel A. We can safely    */
-        /* ignore the remaining bits here.              */
-        /*                                              */
-        /* Note that we're ignoring scc_mask for now.   */
-        /* If we actually mask the ints then we tend to */
-        /* get hammered by very persistent SCC irqs,    */
-        /* and since they're autovector interrupts they */
-        /* pretty much kill the system.                 */
-
-        if (reg & 0x38)
-                m68k_handle_int(IRQ_SCCA);
-        if (reg & 0x07)
-                m68k_handle_int(IRQ_SCCB);
-}
diff --git a/arch/m68k/mac/oss.c b/arch/m68k/mac/oss.c
index f3d23d6ebcf8..a9c0f5ab4cc0 100644
--- a/arch/m68k/mac/oss.c
+++ b/arch/m68k/mac/oss.c
@@ -33,7 +33,6 @@ static irqreturn_t oss_irq(int, void *);
 static irqreturn_t oss_nubus_irq(int, void *);
 
 extern irqreturn_t via1_irq(int, void *);
-extern irqreturn_t mac_scc_dispatch(int, void *);
 
 /*
  * Initialize the OSS
@@ -69,9 +68,6 @@ void __init oss_register_interrupts(void)
         if (request_irq(OSS_IRQLEV_SCSI, oss_irq, IRQ_FLG_LOCK,
                         "scsi", (void *) oss))
                 pr_err("Couldn't register %s interrupt\n", "scsi");
-        if (request_irq(OSS_IRQLEV_IOPSCC, mac_scc_dispatch, IRQ_FLG_LOCK,
-                        "scc", mac_scc_dispatch))
-                pr_err("Couldn't register %s interrupt\n", "scc");
         if (request_irq(OSS_IRQLEV_NUBUS, oss_nubus_irq, IRQ_FLG_LOCK,
                         "nubus", (void *) oss))
                 pr_err("Couldn't register %s interrupt\n", "nubus");
@@ -172,9 +168,7 @@ void oss_irq_enable(int irq) {
         printk("oss_irq_enable(%d)\n", irq);
 #endif
         switch(irq) {
-                case IRQ_SCC:
-                case IRQ_SCCA:
-                case IRQ_SCCB:
+                case IRQ_MAC_SCC:
                         oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_IOPSCC;
                         break;
                 case IRQ_MAC_ADB:
@@ -212,9 +206,7 @@ void oss_irq_disable(int irq) {
         printk("oss_irq_disable(%d)\n", irq);
 #endif
         switch(irq) {
-                case IRQ_SCC:
-                case IRQ_SCCA:
-                case IRQ_SCCB:
+                case IRQ_MAC_SCC:
                         oss->irq_level[OSS_IOPSCC] = OSS_IRQLEV_DISABLED;
                         break;
                 case IRQ_MAC_ADB:
@@ -250,9 +242,7 @@ void oss_irq_disable(int irq) {
 void oss_irq_clear(int irq) {
         /* FIXME: how to do this on OSS? */
         switch(irq) {
-                case IRQ_SCC:
-                case IRQ_SCCA:
-                case IRQ_SCCB:
+                case IRQ_MAC_SCC:
                         oss->irq_pending &= ~OSS_IP_IOPSCC;
                         break;
                 case IRQ_MAC_ADB:
@@ -280,9 +270,7 @@ void oss_irq_clear(int irq) {
 int oss_irq_pending(int irq)
 {
         switch(irq) {
-                case IRQ_SCC:
-                case IRQ_SCCA:
-                case IRQ_SCCB:
+                case IRQ_MAC_SCC:
                         return oss->irq_pending & OSS_IP_IOPSCC;
                         break;
                 case IRQ_MAC_ADB:
diff --git a/arch/m68k/mac/via.c b/arch/m68k/mac/via.c
index 11bce3cb6482..e71166daec6a 100644
--- a/arch/m68k/mac/via.c
+++ b/arch/m68k/mac/via.c
@@ -84,8 +84,6 @@ void via_irq_enable(int irq);
 void via_irq_disable(int irq);
 void via_irq_clear(int irq);
 
-extern irqreturn_t mac_scc_dispatch(int, void *);
-
 /*
  * Initialize the VIAs
  *
@@ -311,11 +309,6 @@ void __init via_register_interrupts(void)
         if (request_irq(IRQ_AUTO_2, via2_irq, IRQ_FLG_LOCK|IRQ_FLG_FAST,
                         "via2", (void *) via2))
                 pr_err("Couldn't register %s interrupt\n", "via2");
-        if (!psc_present) {
-                if (request_irq(IRQ_AUTO_4, mac_scc_dispatch, IRQ_FLG_LOCK,
-                                "scc", mac_scc_dispatch))
-                        pr_err("Couldn't register %s interrupt\n", "scc");
-        }
         if (request_irq(IRQ_MAC_NUBUS, via_nubus_irq,
                         IRQ_FLG_LOCK|IRQ_FLG_FAST, "nubus", (void *) via2))
                 pr_err("Couldn't register %s interrupt\n", "nubus");
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index df620ac2a296..69345849454b 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -99,8 +99,7 @@ static inline void free_io_area(void *addr)
 #endif
 
 /*
- * Map some physical address range into the kernel address space. The
- * code is copied and adapted from map_chunk().
+ * Map some physical address range into the kernel address space.
  */
 /* Rewritten by Andreas Schwab to remove all races. */
 
@@ -116,7 +115,7 @@ void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cachefla
         /*
          * Don't allow mappings that wrap..
          */
-        if (!size || size > physaddr + size)
+        if (!size || physaddr > (unsigned long)(-size))
                 return NULL;
 
 #ifdef CONFIG_AMIGA
diff --git a/arch/m68knommu/kernel/process.c b/arch/m68knommu/kernel/process.c
index 5c9ecd427090..959cb249c759 100644
--- a/arch/m68knommu/kernel/process.c
+++ b/arch/m68knommu/kernel/process.c
@@ -221,6 +221,10 @@ int copy_thread(unsigned long clone_flags,
 
         p->thread.usp = usp;
         p->thread.ksp = (unsigned long)childstack;
+
+        if (clone_flags & CLONE_SETTLS)
+                task_thread_info(p)->tp_value = regs->d5;
+
         /*
          * Must save the current SFC/DFC value, NOT the value when
          * the parent was last descheduled - RGH  10-08-96
diff --git a/arch/m68knommu/kernel/ptrace.c b/arch/m68knommu/kernel/ptrace.c
index 4d3828959fb0..85ed2f988f98 100644
--- a/arch/m68knommu/kernel/ptrace.c
+++ b/arch/m68knommu/kernel/ptrace.c
@@ -319,6 +319,11 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 }
 #endif
 
+        case PTRACE_GET_THREAD_AREA:
+                ret = put_user(task_thread_info(child)->tp_value,
+                               (unsigned long __user *)data);
+                break;
+
                 default:
                         ret = -EIO;
                         break;
diff --git a/arch/m68knommu/kernel/sys_m68k.c b/arch/m68knommu/kernel/sys_m68k.c
index b67cbc735a9b..923dd4aab875 100644
--- a/arch/m68knommu/kernel/sys_m68k.c
+++ b/arch/m68knommu/kernel/sys_m68k.c
@@ -190,3 +190,39 @@ int kernel_execve(const char *filename, char *const argv[], char *const envp[])
                         : "d" (__a), "d" (__b), "d" (__c));
         return __res;
 }
+
+asmlinkage unsigned long sys_get_thread_area(void)
+{
+        return current_thread_info()->tp_value;
+}
+
+asmlinkage int sys_set_thread_area(unsigned long tp)
+{
+        current_thread_info()->tp_value = tp;
+        return 0;
+}
+
+/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
+   D1 (newval).  */
+asmlinkage int
+sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
+                      unsigned long __user * mem)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long mem_value;
+
+        down_read(&mm->mmap_sem);
+
+        mem_value = *mem;
+        if (mem_value == oldval)
+                *mem = newval;
+
+        up_read(&mm->mmap_sem);
+        return mem_value;
+}
+
+asmlinkage int sys_atomic_barrier(void)
+{
+        /* no code needed for uniprocs */
+        return 0;
+}
diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S
index 486837efa3d7..56dd01ded148 100644
--- a/arch/m68knommu/kernel/syscalltable.S
+++ b/arch/m68knommu/kernel/syscalltable.S
@@ -351,6 +351,10 @@ ENTRY(sys_call_table)
         .long sys_pwritev               /* 330 */
         .long sys_rt_tgsigqueueinfo
         .long sys_perf_event_open
+        .long sys_get_thread_area
+        .long sys_set_thread_area
+        .long sys_atomic_cmpxchg_32     /* 335 */
+        .long sys_atomic_barrier
 
         .rept NR_syscalls-(.-sys_call_table)/4
                 .long sys_ni_syscall
diff --git a/arch/m68knommu/mm/memory.c b/arch/m68knommu/mm/memory.c
index f93b88b51f9f..d5b9e1357808 100644
--- a/arch/m68knommu/mm/memory.c
+++ b/arch/m68knommu/mm/memory.c
@@ -24,7 +24,6 @@
 
 /*
  * Map some physical address range into the kernel address space.
- * The code is copied and adapted from map_chunk().
  */
 
 unsigned long kernel_map(unsigned long paddr, unsigned long size,
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index cd5837e298b2..b008168ae946 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -130,6 +130,7 @@ config CMDLINE_FORCE
 
 config OF
         def_bool y
+        select OF_FLATTREE
 
 config PROC_DEVICETREE
         bool "Support for device tree in /proc"
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index fc9997b73c09..267c7c779e53 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -217,7 +217,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
  * Little endian
  */
 
-#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a));
+#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
 #define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
 
 #define in_le32(a) __le32_to_cpu(__raw_readl(a))
diff --git a/arch/microblaze/include/asm/prom.h b/arch/microblaze/include/asm/prom.h
index ef3ec1d6ceb3..03f45a963204 100644
--- a/arch/microblaze/include/asm/prom.h
+++ b/arch/microblaze/include/asm/prom.h
@@ -26,31 +26,11 @@
 #include <asm/irq.h>
 #include <asm/atomic.h>
 
-#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
-#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
-
-#define of_compat_cmp(s1, s2, l)        strncasecmp((s1), (s2), (l))
-#define of_prop_cmp(s1, s2)             strcmp((s1), (s2))
-#define of_node_cmp(s1, s2)             strcasecmp((s1), (s2))
-
-extern struct device_node *of_chosen;
-
 #define HAVE_ARCH_DEVTREE_FIXUPS
 
-extern struct device_node *allnodes;    /* temporary while merging */
-extern rwlock_t devtree_lock;   /* temporary while merging */
-
-/* For updating the device tree at runtime */
-extern void of_attach_node(struct device_node *);
-extern void of_detach_node(struct device_node *);
-
 /* Other Prototypes */
 extern int early_uartlite_console(void);
 
-extern struct resource *request_OF_resource(struct device_node *node,
-                                int index, const char *name_postfix);
-extern int release_OF_resource(struct device_node *node, int index);
-
 /*
  * OF address retreival & translation
  */
diff --git a/arch/microblaze/include/asm/tlbflush.h b/arch/microblaze/include/asm/tlbflush.h
index eb31a0e8a772..10ec70cd8735 100644
--- a/arch/microblaze/include/asm/tlbflush.h
+++ b/arch/microblaze/include/asm/tlbflush.h
@@ -38,7 +38,7 @@ static inline void local_flush_tlb_range(struct vm_area_struct *vma,
 
 #define flush_tlb_kernel_range(start, end)      do { } while (0)
 
-#define update_mmu_cache(vma, addr, pte)        do { } while (0)
+#define update_mmu_cache(vma, addr, ptep)       do { } while (0)
 
 #define flush_tlb_all local_flush_tlb_all
 #define flush_tlb_mm local_flush_tlb_mm
diff --git a/arch/microblaze/kernel/cpu/cache.c b/arch/microblaze/kernel/cpu/cache.c
index d9d63831cc2f..2a56bccce4e0 100644
--- a/arch/microblaze/kernel/cpu/cache.c
+++ b/arch/microblaze/kernel/cpu/cache.c
@@ -172,16 +172,15 @@ do {									\
 /* It is used only first parameter for OP - for wic, wdc */
 #define CACHE_RANGE_LOOP_1(start, end, line_length, op)                 \
 do {                                                                    \
-        int step = -line_length;                                        \
-        int count = end - start;                                        \
-        BUG_ON(count <= 0);                                             \
+        int volatile temp;                                              \
+        BUG_ON(end - start <= 0);                                       \
                                                                         \
-        __asm__ __volatile__ (" 1:      addk    %0, %0, %1;             \
-                                        " #op " %0, r0;                 \
-                                        bgtid   %1, 1b;                 \
-                                        addk    %1, %1, %2;             \
-                                        " : : "r" (start), "r" (count), \
-                                        "r" (step) : "memory");         \
+        __asm__ __volatile__ (" 1:      " #op " %1, r0;                 \
+                                        cmpu    %0, %1, %2;             \
+                                        bgtid   %0, 1b;                 \
+                                        addk    %1, %1, %3;             \
+                                " : : "r" (temp), "r" (start), "r" (end),\
+                                        "r" (line_length) : "memory");  \
 } while (0);
 
 static void __flush_icache_range_msr_irq(unsigned long start, unsigned long end)
@@ -313,16 +312,6 @@ static void __invalidate_dcache_all_wb(void)
         pr_debug("%s\n", __func__);
         CACHE_ALL_LOOP2(cpuinfo.dcache_size, cpuinfo.dcache_line_length,
                                         wdc.clear)
-
-#if 0
-        unsigned int i;
-
-        pr_debug("%s\n", __func__);
-
-        /* Just loop through cache size and invalidate it */
-        for (i = 0; i < cpuinfo.dcache_size; i += cpuinfo.dcache_line_length)
-                        __invalidate_dcache(0, i);
-#endif
 }
 
 static void __invalidate_dcache_range_wb(unsigned long start,
diff --git a/arch/microblaze/kernel/of_platform.c b/arch/microblaze/kernel/of_platform.c
index acf4574d0f18..1c6d684996d7 100644
--- a/arch/microblaze/kernel/of_platform.c
+++ b/arch/microblaze/kernel/of_platform.c
@@ -185,7 +185,7 @@ EXPORT_SYMBOL(of_find_device_by_node);
 static int of_dev_phandle_match(struct device *dev, void *data)
 {
         phandle *ph = data;
-        return to_of_device(dev)->node->linux_phandle == *ph;
+        return to_of_device(dev)->node->phandle == *ph;
 }
 
 struct of_device *of_find_device_by_phandle(phandle ph)
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
index b817df172aa9..a15ef6d67ca9 100644
--- a/arch/microblaze/kernel/prom.c
+++ b/arch/microblaze/kernel/prom.c
@@ -42,698 +42,21 @@
 #include <asm/sections.h>
 #include <asm/pci-bridge.h>
 
-static int __initdata dt_root_addr_cells;
-static int __initdata dt_root_size_cells;
-
-typedef u32 cell_t;
-
-static struct boot_param_header *initial_boot_params;
-
-/* export that to outside world */
-struct device_node *of_chosen;
-
-static inline char *find_flat_dt_string(u32 offset)
-{
-        return ((char *)initial_boot_params) +
-                initial_boot_params->off_dt_strings + offset;
-}
-
-/**
- * This function is used to scan the flattened device-tree, it is
- * used to extract the memory informations at boot before we can
- * unflatten the tree
- */
-int __init of_scan_flat_dt(int (*it)(unsigned long node,
-                                     const char *uname, int depth,
-                                     void *data),
-                           void *data)
-{
-        unsigned long p = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-        int rc = 0;
-        int depth = -1;
-
-        do {
-                u32 tag = *((u32 *)p);
-                char *pathp;
-
-                p += 4;
-                if (tag == OF_DT_END_NODE) {
-                        depth--;
-                        continue;
-                }
-                if (tag == OF_DT_NOP)
-                        continue;
-                if (tag == OF_DT_END)
-                        break;
-                if (tag == OF_DT_PROP) {
-                        u32 sz = *((u32 *)p);
-                        p += 8;
-                        if (initial_boot_params->version < 0x10)
-                                p = _ALIGN(p, sz >= 8 ? 8 : 4);
-                        p += sz;
-                        p = _ALIGN(p, 4);
-                        continue;
-                }
-                if (tag != OF_DT_BEGIN_NODE) {
-                        printk(KERN_WARNING "Invalid tag %x scanning flattened"
-                                " device tree !\n", tag);
-                        return -EINVAL;
-                }
-                depth++;
-                pathp = (char *)p;
-                p = _ALIGN(p + strlen(pathp) + 1, 4);
-                if ((*pathp) == '/') {
-                        char *lp, *np;
-                        for (lp = NULL, np = pathp; *np; np++)
-                                if ((*np) == '/')
-                                        lp = np+1;
-                        if (lp != NULL)
-                                pathp = lp;
-                }
-                rc = it(p, pathp, depth, data);
-                if (rc != 0)
-                        break;
-        } while (1);
-
-        return rc;
-}
-
-unsigned long __init of_get_flat_dt_root(void)
-{
-        unsigned long p = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-
-        while (*((u32 *)p) == OF_DT_NOP)
-                p += 4;
-        BUG_ON(*((u32 *)p) != OF_DT_BEGIN_NODE);
-        p += 4;
-        return _ALIGN(p + strlen((char *)p) + 1, 4);
-}
-
-/**
- * This function can be used within scan_flattened_dt callback to get
- * access to properties
- */
-void *__init of_get_flat_dt_prop(unsigned long node, const char *name,
-                                unsigned long *size)
-{
-        unsigned long p = node;
-
-        do {
-                u32 tag = *((u32 *)p);
-                u32 sz, noff;
-                const char *nstr;
-
-                p += 4;
-                if (tag == OF_DT_NOP)
-                        continue;
-                if (tag != OF_DT_PROP)
-                        return NULL;
-
-                sz = *((u32 *)p);
-                noff = *((u32 *)(p + 4));
-                p += 8;
-                if (initial_boot_params->version < 0x10)
-                        p = _ALIGN(p, sz >= 8 ? 8 : 4);
-
-                nstr = find_flat_dt_string(noff);
-                if (nstr == NULL) {
-                        printk(KERN_WARNING "Can't find property index"
-                                " name !\n");
-                        return NULL;
-                }
-                if (strcmp(name, nstr) == 0) {
-                        if (size)
-                                *size = sz;
-                        return (void *)p;
-                }
-                p += sz;
-                p = _ALIGN(p, 4);
-        } while (1);
-}
-
-int __init of_flat_dt_is_compatible(unsigned long node, const char *compat)
-{
-        const char *cp;
-        unsigned long cplen, l;
-
-        cp = of_get_flat_dt_prop(node, "compatible", &cplen);
-        if (cp == NULL)
-                return 0;
-        while (cplen > 0) {
-                if (strncasecmp(cp, compat, strlen(compat)) == 0)
-                        return 1;
-                l = strlen(cp) + 1;
-                cp += l;
-                cplen -= l;
-        }
-
-        return 0;
-}
-
-static void *__init unflatten_dt_alloc(unsigned long *mem, unsigned long size,
-                                        unsigned long align)
-{
-        void *res;
-
-        *mem = _ALIGN(*mem, align);
-        res = (void *)*mem;
-        *mem += size;
-
-        return res;
-}
-
-static unsigned long __init unflatten_dt_node(unsigned long mem,
-                                        unsigned long *p,
-                                        struct device_node *dad,
-                                        struct device_node ***allnextpp,
-                                        unsigned long fpsize)
-{
-        struct device_node *np;
-        struct property *pp, **prev_pp = NULL;
-        char *pathp;
-        u32 tag;
-        unsigned int l, allocl;
-        int has_name = 0;
-        int new_format = 0;
-
-        tag = *((u32 *)(*p));
-        if (tag != OF_DT_BEGIN_NODE) {
-                printk("Weird tag at start of node: %x\n", tag);
-                return mem;
-        }
-        *p += 4;
-        pathp = (char *)*p;
-        l = allocl = strlen(pathp) + 1;
-        *p = _ALIGN(*p + l, 4);
-
-        /* version 0x10 has a more compact unit name here instead of the full
-         * path. we accumulate the full path size using "fpsize", we'll rebuild
-         * it later. We detect this because the first character of the name is
-         * not '/'.
-         */
-        if ((*pathp) != '/') {
-                new_format = 1;
-                if (fpsize == 0) {
-                        /* root node: special case. fpsize accounts for path
-                         * plus terminating zero. root node only has '/', so
-                         * fpsize should be 2, but we want to avoid the first
-                         * level nodes to have two '/' so we use fpsize 1 here
-                         */
-                        fpsize = 1;
-                        allocl = 2;
-                } else {
-                        /* account for '/' and path size minus terminal 0
-                         * already in 'l'
-                         */
-                        fpsize += l;
-                        allocl = fpsize;
-                }
-        }
-
-        np = unflatten_dt_alloc(&mem, sizeof(struct device_node) + allocl,
-                                __alignof__(struct device_node));
-        if (allnextpp) {
-                memset(np, 0, sizeof(*np));
-                np->full_name = ((char *)np) + sizeof(struct device_node);
-                if (new_format) {
-                        char *p2 = np->full_name;
-                        /* rebuild full path for new format */
-                        if (dad && dad->parent) {
-                                strcpy(p2, dad->full_name);
-#ifdef DEBUG
-                                if ((strlen(p2) + l + 1) != allocl) {
-                                        pr_debug("%s: p: %d, l: %d, a: %d\n",
-                                                pathp, (int)strlen(p2),
-                                                l, allocl);
-                                }
-#endif
-                                p2 += strlen(p2);
-                        }
-                        *(p2++) = '/';
-                        memcpy(p2, pathp, l);
-                } else
-                        memcpy(np->full_name, pathp, l);
-                prev_pp = &np->properties;
-                **allnextpp = np;
-                *allnextpp = &np->allnext;
-                if (dad != NULL) {
-                        np->parent = dad;
-                        /* we temporarily use the next field as `last_child'*/
-                        if (dad->next == NULL)
-                                dad->child = np;
-                        else
-                                dad->next->sibling = np;
-                        dad->next = np;
-                }
-                kref_init(&np->kref);
-        }
-        while (1) {
-                u32 sz, noff;
-                char *pname;
-
-                tag = *((u32 *)(*p));
-                if (tag == OF_DT_NOP) {
-                        *p += 4;
-                        continue;
-                }
-                if (tag != OF_DT_PROP)
-                        break;
-                *p += 4;
-                sz = *((u32 *)(*p));
-                noff = *((u32 *)((*p) + 4));
-                *p += 8;
-                if (initial_boot_params->version < 0x10)
-                        *p = _ALIGN(*p, sz >= 8 ? 8 : 4);
-
-                pname = find_flat_dt_string(noff);
-                if (pname == NULL) {
-                        printk(KERN_INFO
-                                "Can't find property name in list !\n");
-                        break;
-                }
-                if (strcmp(pname, "name") == 0)
-                        has_name = 1;
-                l = strlen(pname) + 1;
-                pp = unflatten_dt_alloc(&mem, sizeof(struct property),
-                                        __alignof__(struct property));
-                if (allnextpp) {
-                        if (strcmp(pname, "linux,phandle") == 0) {
-                                np->node = *((u32 *)*p);
-                                if (np->linux_phandle == 0)
-                                        np->linux_phandle = np->node;
-                        }
-                        if (strcmp(pname, "ibm,phandle") == 0)
-                                np->linux_phandle = *((u32 *)*p);
-                        pp->name = pname;
-                        pp->length = sz;
-                        pp->value = (void *)*p;
-                        *prev_pp = pp;
-                        prev_pp = &pp->next;
-                }
-                *p = _ALIGN((*p) + sz, 4);
-        }
-        /* with version 0x10 we may not have the name property, recreate
-         * it here from the unit name if absent
-         */
-        if (!has_name) {
-                char *p1 = pathp, *ps = pathp, *pa = NULL;
-                int sz;
-
-                while (*p1) {
-                        if ((*p1) == '@')
-                                pa = p1;
-                        if ((*p1) == '/')
-                                ps = p1 + 1;
-                        p1++;
-                }
-                if (pa < ps)
-                        pa = p1;
-                sz = (pa - ps) + 1;
-                pp = unflatten_dt_alloc(&mem, sizeof(struct property) + sz,
-                                        __alignof__(struct property));
-                if (allnextpp) {
-                        pp->name = "name";
-                        pp->length = sz;
-                        pp->value = pp + 1;
-                        *prev_pp = pp;
-                        prev_pp = &pp->next;
-                        memcpy(pp->value, ps, sz - 1);
-                        ((char *)pp->value)[sz - 1] = 0;
-                        pr_debug("fixed up name for %s -> %s\n", pathp,
-                                (char *)pp->value);
-                }
-        }
-        if (allnextpp) {
-                *prev_pp = NULL;
-                np->name = of_get_property(np, "name", NULL);
-                np->type = of_get_property(np, "device_type", NULL);
-
-                if (!np->name)
-                        np->name = "<NULL>";
-                if (!np->type)
-                        np->type = "<NULL>";
-        }
-        while (tag == OF_DT_BEGIN_NODE) {
-                mem = unflatten_dt_node(mem, p, np, allnextpp, fpsize);
-                tag = *((u32 *)(*p));
-        }
-        if (tag != OF_DT_END_NODE) {
-                printk(KERN_INFO "Weird tag at end of node: %x\n", tag);
-                return mem;
-        }
-        *p += 4;
-        return mem;
-}
-
-/**
- * unflattens the device-tree passed by the firmware, creating the
- * tree of struct device_node. It also fills the "name" and "type"
- * pointers of the nodes so the normal device-tree walking functions
- * can be used (this used to be done by finish_device_tree)
- */
-void __init unflatten_device_tree(void)
-{
-        unsigned long start, mem, size;
-        struct device_node **allnextp = &allnodes;
-
-        pr_debug(" -> unflatten_device_tree()\n");
-
-        /* First pass, scan for size */
-        start = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-        size = unflatten_dt_node(0, &start, NULL, NULL, 0);
-        size = (size | 3) + 1;
-
-        pr_debug("  size is %lx, allocating...\n", size);
-
-        /* Allocate memory for the expanded device tree */
-        mem = lmb_alloc(size + 4, __alignof__(struct device_node));
-        mem = (unsigned long) __va(mem);
-
-        ((u32 *)mem)[size / 4] = 0xdeadbeef;
-
-        pr_debug("  unflattening %lx...\n", mem);
-
-        /* Second pass, do actual unflattening */
-        start = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-        unflatten_dt_node(mem, &start, NULL, &allnextp, 0);
-        if (*((u32 *)start) != OF_DT_END)
-                printk(KERN_WARNING "Weird tag at end of tree: %08x\n",
-                        *((u32 *)start));
-        if (((u32 *)mem)[size / 4] != 0xdeadbeef)
-                printk(KERN_WARNING "End of tree marker overwritten: %08x\n",
-                        ((u32 *)mem)[size / 4]);
-        *allnextp = NULL;
-
-        /* Get pointer to OF "/chosen" node for use everywhere */
-        of_chosen = of_find_node_by_path("/chosen");
-        if (of_chosen == NULL)
-                of_chosen = of_find_node_by_path("/chosen@0");
-
-        pr_debug(" <- unflatten_device_tree()\n");
-}
-
-#define early_init_dt_scan_drconf_memory(node) 0
-
-static int __init early_init_dt_scan_cpus(unsigned long node,
-                                          const char *uname, int depth,
-                                          void *data)
-{
-        static int logical_cpuid;
-        char *type = of_get_flat_dt_prop(node, "device_type", NULL);
-        const u32 *intserv;
-        int i, nthreads;
-        int found = 0;
-
-        /* We are scanning "cpu" nodes only */
-        if (type == NULL || strcmp(type, "cpu") != 0)
-                return 0;
-
-        /* Get physical cpuid */
-        intserv = of_get_flat_dt_prop(node, "reg", NULL);
-        nthreads = 1;
-
-        /*
-         * Now see if any of these threads match our boot cpu.
-         * NOTE: This must match the parsing done in smp_setup_cpu_maps.
-         */
-        for (i = 0; i < nthreads; i++) {
-                /*
-                 * version 2 of the kexec param format adds the phys cpuid of
-                 * booted proc.
-                 */
-                if (initial_boot_params && initial_boot_params->version >= 2) {
-                        if (intserv[i] ==
-                                        initial_boot_params->boot_cpuid_phys) {
-                                found = 1;
-                                break;
-                        }
-                } else {
-                        /*
-                         * Check if it's the boot-cpu, set it's hw index now,
-                         * unfortunately this format did not support booting
-                         * off secondary threads.
-                         */
-                        if (of_get_flat_dt_prop(node,
-                                        "linux,boot-cpu", NULL) != NULL) {
-                                found = 1;
-                                break;
-                        }
-                }
-
-#ifdef CONFIG_SMP
-                /* logical cpu id is always 0 on UP kernels */
-                logical_cpuid++;
-#endif
-        }
-
-        if (found) {
-                pr_debug("boot cpu: logical %d physical %d\n", logical_cpuid,
-                        intserv[i]);
-                boot_cpuid = logical_cpuid;
-        }
-
-        return 0;
-}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-static void __init early_init_dt_check_for_initrd(unsigned long node)
-{
-        unsigned long l;
-        u32 *prop;
-
-        pr_debug("Looking for initrd properties... ");
-
-        prop = of_get_flat_dt_prop(node, "linux,initrd-start", &l);
-        if (prop) {
-                initrd_start = (unsigned long)
-                                        __va((u32)of_read_ulong(prop, l/4));
-
-                prop = of_get_flat_dt_prop(node, "linux,initrd-end", &l);
-                if (prop) {
-                        initrd_end = (unsigned long)
-                                        __va((u32)of_read_ulong(prop, 1/4));
-                        initrd_below_start_ok = 1;
-                } else {
-                        initrd_start = 0;
-                }
-        }
-
-        pr_debug("initrd_start=0x%lx  initrd_end=0x%lx\n",
-                                        initrd_start, initrd_end);
-}
-#else
-static inline void early_init_dt_check_for_initrd(unsigned long node)
-{
-}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-static int __init early_init_dt_scan_chosen(unsigned long node,
-                                const char *uname, int depth, void *data)
-{
-        unsigned long l;
-        char *p;
-
-        pr_debug("search \"chosen\", depth: %d, uname: %s\n", depth, uname);
-
-        if (depth != 1 ||
-                (strcmp(uname, "chosen") != 0 &&
-                                strcmp(uname, "chosen@0") != 0))
-                return 0;
-
-#ifdef CONFIG_KEXEC
-        lprop = (u64 *)of_get_flat_dt_prop(node,
-                                "linux,crashkernel-base", NULL);
-        if (lprop)
-                crashk_res.start = *lprop;
-
-        lprop = (u64 *)of_get_flat_dt_prop(node,
-                                "linux,crashkernel-size", NULL);
-        if (lprop)
-                crashk_res.end = crashk_res.start + *lprop - 1;
-#endif
-
-        early_init_dt_check_for_initrd(node);
-
-        /* Retreive command line */
-        p = of_get_flat_dt_prop(node, "bootargs", &l);
-        if (p != NULL && l > 0)
-                strlcpy(cmd_line, p, min((int)l, COMMAND_LINE_SIZE));
-
-#ifdef CONFIG_CMDLINE
-#ifndef CONFIG_CMDLINE_FORCE
-        if (p == NULL || l == 0 || (l == 1 && (*p) == 0))
-#endif
-                strlcpy(cmd_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
-#endif /* CONFIG_CMDLINE */
-
-        pr_debug("Command line is: %s\n", cmd_line);
-
-        /* break now */
-        return 1;
-}
-
-static int __init early_init_dt_scan_root(unsigned long node,
-                                const char *uname, int depth, void *data)
-{
-        u32 *prop;
-
-        if (depth != 0)
-                return 0;
-
-        prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
-        dt_root_size_cells = (prop == NULL) ? 1 : *prop;
-        pr_debug("dt_root_size_cells = %x\n", dt_root_size_cells);
-
-        prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
-        dt_root_addr_cells = (prop == NULL) ? 2 : *prop;
-        pr_debug("dt_root_addr_cells = %x\n", dt_root_addr_cells);
-
-        /* break now */
-        return 1;
-}
-
-static u64 __init dt_mem_next_cell(int s, cell_t **cellp)
+void __init early_init_dt_scan_chosen_arch(unsigned long node)
 {
-        cell_t *p = *cellp;
-
-        *cellp = p + s;
-        return of_read_number(p, s);
+        /* No Microblaze specific code here */
 }
 
-static int __init early_init_dt_scan_memory(unsigned long node,
-                                const char *uname, int depth, void *data)
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
 {
-        char *type = of_get_flat_dt_prop(node, "device_type", NULL);
-        cell_t *reg, *endp;
-        unsigned long l;
-
-        /* Look for the ibm,dynamic-reconfiguration-memory node */
-/*      if (depth == 1 &&
-                strcmp(uname, "ibm,dynamic-reconfiguration-memory") == 0)
-                return early_init_dt_scan_drconf_memory(node);
-*/
-        /* We are scanning "memory" nodes only */
-        if (type == NULL) {
-                /*
-                 * The longtrail doesn't have a device_type on the
-                 * /memory node, so look for the node called /memory@0.
-                 */
-                if (depth != 1 || strcmp(uname, "memory@0") != 0)
-                        return 0;
-        } else if (strcmp(type, "memory") != 0)
-                return 0;
-
-        reg = (cell_t *)of_get_flat_dt_prop(node, "linux,usable-memory", &l);
-        if (reg == NULL)
-                reg = (cell_t *)of_get_flat_dt_prop(node, "reg", &l);
-        if (reg == NULL)
-                return 0;
-
-        endp = reg + (l / sizeof(cell_t));
-
-        pr_debug("memory scan node %s, reg size %ld, data: %x %x %x %x,\n",
-                uname, l, reg[0], reg[1], reg[2], reg[3]);
-
-        while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
-                u64 base, size;
-
-                base = dt_mem_next_cell(dt_root_addr_cells, &reg);
-                size = dt_mem_next_cell(dt_root_size_cells, &reg);
-
-                if (size == 0)
-                        continue;
-                pr_debug(" - %llx ,  %llx\n", (unsigned long long)base,
-                        (unsigned long long)size);
-
-                lmb_add(base, size);
-        }
-        return 0;
+        lmb_add(base, size);
 }
 
-#ifdef CONFIG_PHYP_DUMP
-/**
- * phyp_dump_calculate_reserve_size() - reserve variable boot area 5% or arg
- *
- * Function to find the largest size we need to reserve
- * during early boot process.
- *
- * It either looks for boot param and returns that OR
- * returns larger of 256 or 5% rounded down to multiples of 256MB.
- *
- */
-static inline unsigned long phyp_dump_calculate_reserve_size(void)
+u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
 {
-        unsigned long tmp;
-
-        if (phyp_dump_info->reserve_bootvar)
-                return phyp_dump_info->reserve_bootvar;
-
-        /* divide by 20 to get 5% of value */
-        tmp = lmb_end_of_DRAM();
-        do_div(tmp, 20);
-
-        /* round it down in multiples of 256 */
-        tmp = tmp & ~0x0FFFFFFFUL;
-
-        return (tmp > PHYP_DUMP_RMR_END ? tmp : PHYP_DUMP_RMR_END);
+        return lmb_alloc(size, align);
 }
 
-/**
- * phyp_dump_reserve_mem() - reserve all not-yet-dumped mmemory
- *
- * This routine may reserve memory regions in the kernel only
- * if the system is supported and a dump was taken in last
- * boot instance or if the hardware is supported and the
- * scratch area needs to be setup. In other instances it returns
- * without reserving anything. The memory in case of dump being
- * active is freed when the dump is collected (by userland tools).
- */
-static void __init phyp_dump_reserve_mem(void)
-{
-        unsigned long base, size;
-        unsigned long variable_reserve_size;
-
-        if (!phyp_dump_info->phyp_dump_configured) {
-                printk(KERN_ERR "Phyp-dump not supported on this hardware\n");
-                return;
-        }
-
-        if (!phyp_dump_info->phyp_dump_at_boot) {
-                printk(KERN_INFO "Phyp-dump disabled at boot time\n");
-                return;
-        }
-
-        variable_reserve_size = phyp_dump_calculate_reserve_size();
-
-        if (phyp_dump_info->phyp_dump_is_active) {
-                /* Reserve *everything* above RMR.Area freed by userland tools*/
-                base = variable_reserve_size;
-                size = lmb_end_of_DRAM() - base;
-
-                /* XXX crashed_ram_end is wrong, since it may be beyond
-                 * the memory_limit, it will need to be adjusted. */
-                lmb_reserve(base, size);
-
-                phyp_dump_info->init_reserve_start = base;
-                phyp_dump_info->init_reserve_size = size;
-        } else {
-                size = phyp_dump_info->cpu_state_size +
-                        phyp_dump_info->hpte_region_size +
-                        variable_reserve_size;
-                base = lmb_end_of_DRAM() - size;
-                lmb_reserve(base, size);
-                phyp_dump_info->init_reserve_start = base;
-                phyp_dump_info->init_reserve_size = size;
-        }
-}
-#else
-static inline void __init phyp_dump_reserve_mem(void) {}
-#endif /* CONFIG_PHYP_DUMP  && CONFIG_PPC_RTAS */
-
 #ifdef CONFIG_EARLY_PRINTK
 /* MS this is Microblaze specifig function */
 static int __init early_init_dt_scan_serial(unsigned long node,
@@ -775,11 +98,6 @@ void __init early_init_devtree(void *params)
         /* Setup flat device-tree pointer */
         initial_boot_params = params;
 
-#ifdef CONFIG_PHYP_DUMP
-        /* scan tree to see if dump occured during last boot */
-        of_scan_flat_dt(early_init_dt_scan_phyp_dump, NULL);
-#endif
-
         /* Retrieve various informations from the /chosen node of the
          * device-tree, including the platform type, initrd location and
          * size, TCE reserve, and more ...
@@ -799,33 +117,18 @@ void __init early_init_devtree(void *params)
 
         pr_debug("Phys. mem: %lx\n", (unsigned long) lmb_phys_mem_size());
 
-        pr_debug("Scanning CPUs ...\n");
-
-        /* Retreive CPU related informations from the flat tree
-         * (altivec support, boot CPU ID, ...)
-         */
-        of_scan_flat_dt(early_init_dt_scan_cpus, NULL);
-
         pr_debug(" <- early_init_devtree()\n");
 }
 
-/**
- * Indicates whether the root node has a given value in its
- * compatible property.
- */
-int machine_is_compatible(const char *compat)
+#ifdef CONFIG_BLK_DEV_INITRD
+void __init early_init_dt_setup_initrd_arch(unsigned long start,
+                unsigned long end)
 {
-        struct device_node *root;
-        int rc = 0;
-
-        root = of_find_node_by_path("/");
-        if (root) {
-                rc = of_device_is_compatible(root, compat);
-                of_node_put(root);
-        }
-        return rc;
+        initrd_start = (unsigned long)__va(start);
+        initrd_end = (unsigned long)__va(end);
+        initrd_below_start_ok = 1;
 }
-EXPORT_SYMBOL(machine_is_compatible);
+#endif
 
 /*******
  *
@@ -838,273 +141,6 @@ EXPORT_SYMBOL(machine_is_compatible);
  *
  *******/
 
-/**
- *      of_find_node_by_phandle - Find a node given a phandle
- *      @handle:        phandle of the node to find
- *
- *      Returns a node pointer with refcount incremented, use
- *      of_node_put() on it when done.
- */
-struct device_node *of_find_node_by_phandle(phandle handle)
-{
-        struct device_node *np;
-
-        read_lock(&devtree_lock);
-        for (np = allnodes; np != NULL; np = np->allnext)
-                if (np->linux_phandle == handle)
-                        break;
-        of_node_get(np);
-        read_unlock(&devtree_lock);
-        return np;
-}
-EXPORT_SYMBOL(of_find_node_by_phandle);
-
-/**
- *      of_node_get - Increment refcount of a node
- *      @node:  Node to inc refcount, NULL is supported to
- *              simplify writing of callers
- *
- *      Returns node.
- */
-struct device_node *of_node_get(struct device_node *node)
-{
-        if (node)
-                kref_get(&node->kref);
-        return node;
-}
-EXPORT_SYMBOL(of_node_get);
-
-static inline struct device_node *kref_to_device_node(struct kref *kref)
-{
-        return container_of(kref, struct device_node, kref);
-}
-
-/**
- *      of_node_release - release a dynamically allocated node
- *      @kref:  kref element of the node to be released
- *
- *      In of_node_put() this function is passed to kref_put()
- *      as the destructor.
- */
-static void of_node_release(struct kref *kref)
-{
-        struct device_node *node = kref_to_device_node(kref);
-        struct property *prop = node->properties;
-
-        /* We should never be releasing nodes that haven't been detached. */
-        if (!of_node_check_flag(node, OF_DETACHED)) {
-                printk(KERN_INFO "WARNING: Bad of_node_put() on %s\n",
-                        node->full_name);
-                dump_stack();
-                kref_init(&node->kref);
-                return;
-        }
-
-        if (!of_node_check_flag(node, OF_DYNAMIC))
-                return;
-
-        while (prop) {
-                struct property *next = prop->next;
-                kfree(prop->name);
-                kfree(prop->value);
-                kfree(prop);
-                prop = next;
-
-                if (!prop) {
-                        prop = node->deadprops;
-                        node->deadprops = NULL;
-                }
-        }
-        kfree(node->full_name);
-        kfree(node->data);
-        kfree(node);
-}
-
-/**
- *      of_node_put - Decrement refcount of a node
- *      @node:  Node to dec refcount, NULL is supported to
- *              simplify writing of callers
- *
- */
-void of_node_put(struct device_node *node)
-{
-        if (node)
-                kref_put(&node->kref, of_node_release);
-}
-EXPORT_SYMBOL(of_node_put);
-
-/*
- * Plug a device node into the tree and global list.
- */
-void of_attach_node(struct device_node *np)
-{
-        unsigned long flags;
-
-        write_lock_irqsave(&devtree_lock, flags);
-        np->sibling = np->parent->child;
-        np->allnext = allnodes;
-        np->parent->child = np;
-        allnodes = np;
-        write_unlock_irqrestore(&devtree_lock, flags);
-}
-
-/*
- * "Unplug" a node from the device tree.  The caller must hold
- * a reference to the node.  The memory associated with the node
- * is not freed until its refcount goes to zero.
- */
-void of_detach_node(struct device_node *np)
-{
-        struct device_node *parent;
-        unsigned long flags;
-
-        write_lock_irqsave(&devtree_lock, flags);
-
-        parent = np->parent;
-        if (!parent)
-                goto out_unlock;
-
-        if (allnodes == np)
-                allnodes = np->allnext;
-        else {
-                struct device_node *prev;
-                for (prev = allnodes;
-                     prev->allnext != np;
-                     prev = prev->allnext)
-                        ;
-                prev->allnext = np->allnext;
-        }
-
-        if (parent->child == np)
-                parent->child = np->sibling;
-        else {
-                struct device_node *prevsib;
-                for (prevsib = np->parent->child;
-                     prevsib->sibling != np;
-                     prevsib = prevsib->sibling)
-                        ;
-                prevsib->sibling = np->sibling;
-        }
-
-        of_node_set_flag(np, OF_DETACHED);
-
-out_unlock:
-        write_unlock_irqrestore(&devtree_lock, flags);
-}
-
-/*
- * Add a property to a node
- */
-int prom_add_property(struct device_node *np, struct property *prop)
-{
-        struct property **next;
-        unsigned long flags;
-
-        prop->next = NULL;
-        write_lock_irqsave(&devtree_lock, flags);
-        next = &np->properties;
-        while (*next) {
-                if (strcmp(prop->name, (*next)->name) == 0) {
-                        /* duplicate ! don't insert it */
-                        write_unlock_irqrestore(&devtree_lock, flags);
-                        return -1;
-                }
-                next = &(*next)->next;
-        }
-        *next = prop;
-        write_unlock_irqrestore(&devtree_lock, flags);
-
-#ifdef CONFIG_PROC_DEVICETREE
-        /* try to add to proc as well if it was initialized */
-        if (np->pde)
-                proc_device_tree_add_prop(np->pde, prop);
-#endif /* CONFIG_PROC_DEVICETREE */
-
-        return 0;
-}
-
-/*
- * Remove a property from a node.  Note that we don't actually
- * remove it, since we have given out who-knows-how-many pointers
- * to the data using get-property.  Instead we just move the property
- * to the "dead properties" list, so it won't be found any more.
- */
-int prom_remove_property(struct device_node *np, struct property *prop)
-{
-        struct property **next;
-        unsigned long flags;
-        int found = 0;
-
-        write_lock_irqsave(&devtree_lock, flags);
-        next = &np->properties;
-        while (*next) {
-                if (*next == prop) {
-                        /* found the node */
-                        *next = prop->next;
-                        prop->next = np->deadprops;
-                        np->deadprops = prop;
-                        found = 1;
-                        break;
-                }
-                next = &(*next)->next;
-        }
-        write_unlock_irqrestore(&devtree_lock, flags);
-
-        if (!found)
-                return -ENODEV;
-
-#ifdef CONFIG_PROC_DEVICETREE
-        /* try to remove the proc node as well */
-        if (np->pde)
-                proc_device_tree_remove_prop(np->pde, prop);
-#endif /* CONFIG_PROC_DEVICETREE */
-
-        return 0;
-}
-
-/*
- * Update a property in a node.  Note that we don't actually
- * remove it, since we have given out who-knows-how-many pointers
- * to the data using get-property.  Instead we just move the property
- * to the "dead properties" list, and add the new property to the
- * property list
- */
-int prom_update_property(struct device_node *np,
-                         struct property *newprop,
-                         struct property *oldprop)
-{
-        struct property **next;
-        unsigned long flags;
-        int found = 0;
-
-        write_lock_irqsave(&devtree_lock, flags);
-        next = &np->properties;
-        while (*next) {
-                if (*next == oldprop) {
-                        /* found the node */
-                        newprop->next = oldprop->next;
-                        *next = newprop;
-                        oldprop->next = np->deadprops;
-                        np->deadprops = oldprop;
-                        found = 1;
-                        break;
-                }
-                next = &(*next)->next;
-        }
-        write_unlock_irqrestore(&devtree_lock, flags);
-
-        if (!found)
-                return -ENODEV;
-
-#ifdef CONFIG_PROC_DEVICETREE
-        /* try to add to proc as well if it was initialized */
-        if (np->pde)
-                proc_device_tree_update_prop(np->pde, newprop, oldprop);
-#endif /* CONFIG_PROC_DEVICETREE */
-
-        return 0;
-}
-
 #if defined(CONFIG_DEBUG_FS) && defined(DEBUG)
 static struct debugfs_blob_wrapper flat_dt_blob;
 
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 8b5d174685f0..591ca0cd4c24 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -41,7 +41,7 @@ config AR7
         select SYS_SUPPORTS_32BIT_KERNEL
         select SYS_SUPPORTS_LITTLE_ENDIAN
         select SYS_SUPPORTS_ZBOOT_UART16550
-        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
         select GCD
         select VLYNQ
         help
@@ -180,7 +180,7 @@ config LASAT
 
 config MACH_LOONGSON
         bool "Loongson family of machines"
-        select SYS_SUPPORTS_ZBOOT_UART16550
+        select SYS_SUPPORTS_ZBOOT
         help
           This enables the support of Loongson family of machines.
 
@@ -1295,7 +1295,6 @@ config CPU_CAVIUM_OCTEON
         select SYS_SUPPORTS_SMP
         select NR_CPUS_DEFAULT_16
         select WEAK_ORDERING
-        select WEAK_REORDERING_BEYOND_LLSC
         select CPU_SUPPORTS_HIGHMEM
         select CPU_SUPPORTS_HUGEPAGES
         help
@@ -1726,6 +1725,9 @@ config SB1_PASS_2_1_WORKAROUNDS
 config 64BIT_PHYS_ADDR
         bool
 
+config ARCH_PHYS_ADDR_T_64BIT
+       def_bool 64BIT_PHYS_ADDR
+
 config CPU_HAS_SMARTMIPS
         depends on SYS_SUPPORTS_SMARTMIPS
         bool "Support for the SmartMIPS ASE"
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index d2b88a0be519..43dc27997730 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -102,4 +102,30 @@ config RUNTIME_DEBUG
           arch/mips/include/asm/debug.h for debugging macros.
           If unsure, say N.
 
+config DEBUG_ZBOOT
+        bool "Enable compressed kernel support debugging"
+        depends on DEBUG_KERNEL && SYS_SUPPORTS_ZBOOT
+        default n
+        help
+          If you want to add compressed kernel support to a new board, and the
+          board supports uart16550 compatible serial port, please select
+          SYS_SUPPORTS_ZBOOT_UART16550 for your board and enable this option to
+          debug it.
+
+          If your board doesn't support uart16550 compatible serial port, you
+          can try to select SYS_SUPPORTS_ZBOOT and use the other methods to
+          debug it. for example, add a new serial port support just as
+          arch/mips/boot/compressed/uart-16550.c does.
+
+          After the compressed kernel support works, please disable this option
+          to reduce the kernel image size and speed up the booting procedure a
+          little.
+
+config SPINLOCK_TEST
+        bool "Enable spinlock timing tests in debugfs"
+        depends on DEBUG_FS
+        default n
+        help
+          Add several files to the debugfs to test spinlock speed.
+
 endmenu
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 1893efd43fca..2f2eac233322 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -185,6 +185,15 @@ libs-$(CONFIG_SNIPROM)		+= arch/mips/fw/sni/
 libs-y                          += arch/mips/fw/lib/
 
 #
+# Kernel compression
+#
+ifdef SYS_SUPPORTS_ZBOOT
+COMPRESSION_FNAME               = vmlinuz
+else
+COMPRESSION_FNAME               = vmlinux
+endif
+
+#
 # Board-dependent options and extra files
 #
 
@@ -332,11 +341,11 @@ load-$(CONFIG_WR_PPMC)		+= 0xffffffff80100000
 #
 # Loongson family
 #
-core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/
+core-$(CONFIG_MACH_LOONGSON) += arch/mips/loongson/
 cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \
                     -mno-branch-likely
-load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000
-load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
+load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
+load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
 
 #
 # MIPS Malta board
@@ -344,7 +353,7 @@ load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000
 core-$(CONFIG_MIPS_MALTA)       += arch/mips/mti-malta/
 cflags-$(CONFIG_MIPS_MALTA)     += -I$(srctree)/arch/mips/include/asm/mach-malta
 load-$(CONFIG_MIPS_MALTA)       += 0xffffffff80100000
-all-$(CONFIG_MIPS_MALTA)        := vmlinuz.bin
+all-$(CONFIG_MIPS_MALTA)        := $(COMPRESSION_FNAME).bin
 
 #
 # MIPS SIM
@@ -594,7 +603,7 @@ load-$(CONFIG_SNI_RM)		+= 0xffffffff80600000
 else
 load-$(CONFIG_SNI_RM)           += 0xffffffff80030000
 endif
-all-$(CONFIG_SNI_RM)            := vmlinuz.ecoff
+all-$(CONFIG_SNI_RM)            := $(COMPRESSION_FNAME).ecoff
 
 #
 # Common TXx9
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 00b498e97c83..df3b1a7eb15d 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,5 +1,5 @@
-# au1000-style gpio
-config ALCHEMY_GPIO_AU1000
+# au1000-style gpio and interrupt controllers
+config ALCHEMY_GPIOINT_AU1000
         bool
 
 # select this in your board config if you don't want to use the gpio
@@ -20,12 +20,14 @@ config MIPS_MTX1
         select HW_HAS_PCI
         select SOC_AU1500
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_BOSPORUS
         bool "Alchemy Bosporus board"
         select SOC_AU1500
         select DMA_NONCOHERENT
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_DB1000
         bool "Alchemy DB1000 board"
@@ -33,12 +35,14 @@ config MIPS_DB1000
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_DB1100
         bool "Alchemy DB1100 board"
         select SOC_AU1100
         select DMA_NONCOHERENT
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_DB1200
         bool "Alchemy DB1200 board"
@@ -46,6 +50,7 @@ config MIPS_DB1200
         select DMA_COHERENT
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_DB1500
         bool "Alchemy DB1500 board"
@@ -55,6 +60,7 @@ config MIPS_DB1500
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_BIG_ENDIAN
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_DB1550
         bool "Alchemy DB1550 board"
@@ -63,12 +69,14 @@ config MIPS_DB1550
         select DMA_NONCOHERENT
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_MIRAGE
         bool "Alchemy Mirage board"
         select DMA_NONCOHERENT
         select SOC_AU1500
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_PB1000
         bool "Alchemy PB1000 board"
@@ -77,6 +85,7 @@ config MIPS_PB1000
         select HW_HAS_PCI
         select SWAP_IO_SPACE
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_PB1100
         bool "Alchemy PB1100 board"
@@ -85,6 +94,7 @@ config MIPS_PB1100
         select HW_HAS_PCI
         select SWAP_IO_SPACE
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_PB1200
         bool "Alchemy PB1200 board"
@@ -92,6 +102,7 @@ config MIPS_PB1200
         select DMA_NONCOHERENT
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_PB1500
         bool "Alchemy PB1500 board"
@@ -99,6 +110,7 @@ config MIPS_PB1500
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_PB1550
         bool "Alchemy PB1550 board"
@@ -107,39 +119,41 @@ config MIPS_PB1550
         select HW_HAS_PCI
         select MIPS_DISABLE_OBSOLETE_IDE
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 config MIPS_XXS1500
         bool "MyCable XXS1500 board"
         select DMA_NONCOHERENT
         select SOC_AU1500
         select SYS_SUPPORTS_LITTLE_ENDIAN
+        select SYS_HAS_EARLY_PRINTK
 
 endchoice
 
 config SOC_AU1000
         bool
         select SOC_AU1X00
-        select ALCHEMY_GPIO_AU1000
+        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1100
         bool
         select SOC_AU1X00
-        select ALCHEMY_GPIO_AU1000
+        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1500
         bool
         select SOC_AU1X00
-        select ALCHEMY_GPIO_AU1000
+        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1550
         bool
         select SOC_AU1X00
-        select ALCHEMY_GPIO_AU1000
+        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1200
         bool
         select SOC_AU1X00
-        select ALCHEMY_GPIO_AU1000
+        select ALCHEMY_GPIOINT_AU1000
 
 config SOC_AU1X00
         bool
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index b67fb512529d..06c0e65a54b5 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -5,14 +5,15 @@
 # Makefile for the Alchemy Au1xx0 CPUs, generic files.
 #
 
-obj-y += prom.o irq.o puts.o time.o reset.o \
-        clocks.o platform.o power.o setup.o \
+obj-y += prom.o time.o clocks.o platform.o power.o setup.o \
         sleeper.o dma.o dbdma.o
 
+obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o
+
 # optional gpiolib support
 ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
  ifeq ($(CONFIG_GPIOLIB),y)
-  obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o
+  obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o
  endif
 endif
 
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index d8991854530e..460c6285c1bb 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -40,8 +40,6 @@
 static unsigned int au1x00_clock; /*  Hz */
 static unsigned long uart_baud_base;
 
-static DEFINE_SPINLOCK(time_lock);
-
 /*
  * Set the au1000_clock
  */
@@ -84,9 +82,6 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
 unsigned long au1xxx_calc_clock(void)
 {
         unsigned long cpu_speed;
-        unsigned long flags;
-
-        spin_lock_irqsave(&time_lock, flags);
 
         /*
          * On early Au1000, sys_cpupll was write-only. Since these
@@ -108,8 +103,6 @@ unsigned long au1xxx_calc_clock(void)
         set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
                                                           & 0x03) + 2) * 16));
 
-        spin_unlock_irqrestore(&time_lock, flags);
-
         set_au1x00_speed(cpu_speed);
 
         return cpu_speed;
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index f9201ca2295b..99ae84ce5af3 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -30,6 +30,7 @@
  *
  */
 
+#include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
@@ -58,7 +59,6 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
 
 static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
 static int dbdma_initialized;
-static void au1xxx_dbdma_init(void);
 
 static dbdev_tab_t dbdev_tab[] = {
 #ifdef CONFIG_SOC_AU1550
@@ -237,7 +237,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
        void (*callback)(int, void *), void *callparam)
 {
         unsigned long   flags;
-        u32             used, chan, rv;
+        u32             used, chan;
         u32             dcp;
         int             i;
         dbdev_tab_t     *stp, *dtp;
@@ -250,8 +250,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
          * which can't be done successfully during board set up.
          */
         if (!dbdma_initialized)
-                au1xxx_dbdma_init();
-        dbdma_initialized = 1;
+                return 0;
 
         stp = find_dbdev_id(srcid);
         if (stp == NULL)
@@ -261,7 +260,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                 return 0;
 
         used = 0;
-        rv = 0;
 
         /* Check to see if we can get both channels. */
         spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
@@ -282,63 +280,65 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
                 used++;
         spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
 
-        if (!used) {
-                /* Let's see if we can allocate a channel for it. */
-                ctp = NULL;
-                chan = 0;
-                spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
-                for (i = 0; i < NUM_DBDMA_CHANS; i++)
-                        if (chan_tab_ptr[i] == NULL) {
-                                /*
-                                 * If kmalloc fails, it is caught below same
-                                 * as a channel not available.
-                                 */
-                                ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
-                                chan_tab_ptr[i] = ctp;
-                                break;
-                        }
-                spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
-
-                if (ctp != NULL) {
-                        memset(ctp, 0, sizeof(chan_tab_t));
-                        ctp->chan_index = chan = i;
-                        dcp = DDMA_CHANNEL_BASE;
-                        dcp += (0x0100 * chan);
-                        ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
-                        cp = (au1x_dma_chan_t *)dcp;
-                        ctp->chan_src = stp;
-                        ctp->chan_dest = dtp;
-                        ctp->chan_callback = callback;
-                        ctp->chan_callparam = callparam;
-
-                        /* Initialize channel configuration. */
-                        i = 0;
-                        if (stp->dev_intlevel)
-                                i |= DDMA_CFG_SED;
-                        if (stp->dev_intpolarity)
-                                i |= DDMA_CFG_SP;
-                        if (dtp->dev_intlevel)
-                                i |= DDMA_CFG_DED;
-                        if (dtp->dev_intpolarity)
-                                i |= DDMA_CFG_DP;
-                        if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
-                                (dtp->dev_flags & DEV_FLAGS_SYNC))
-                                        i |= DDMA_CFG_SYNC;
-                        cp->ddma_cfg = i;
-                        au_sync();
+        if (used)
+                return 0;
 
-                        /* Return a non-zero value that can be used to
-                         * find the channel information in subsequent
-                         * operations.
+        /* Let's see if we can allocate a channel for it. */
+        ctp = NULL;
+        chan = 0;
+        spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
+        for (i = 0; i < NUM_DBDMA_CHANS; i++)
+                if (chan_tab_ptr[i] == NULL) {
+                        /*
+                         * If kmalloc fails, it is caught below same
+                         * as a channel not available.
                          */
-                        rv = (u32)(&chan_tab_ptr[chan]);
-                } else {
-                        /* Release devices */
-                        stp->dev_flags &= ~DEV_FLAGS_INUSE;
-                        dtp->dev_flags &= ~DEV_FLAGS_INUSE;
+                        ctp = kmalloc(sizeof(chan_tab_t), GFP_ATOMIC);
+                        chan_tab_ptr[i] = ctp;
+                        break;
                 }
+        spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
+
+        if (ctp != NULL) {
+                memset(ctp, 0, sizeof(chan_tab_t));
+                ctp->chan_index = chan = i;
+                dcp = DDMA_CHANNEL_BASE;
+                dcp += (0x0100 * chan);
+                ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
+                cp = (au1x_dma_chan_t *)dcp;
+                ctp->chan_src = stp;
+                ctp->chan_dest = dtp;
+                ctp->chan_callback = callback;
+                ctp->chan_callparam = callparam;
+
+                /* Initialize channel configuration. */
+                i = 0;
+                if (stp->dev_intlevel)
+                        i |= DDMA_CFG_SED;
+                if (stp->dev_intpolarity)
+                        i |= DDMA_CFG_SP;
+                if (dtp->dev_intlevel)
+                        i |= DDMA_CFG_DED;
+                if (dtp->dev_intpolarity)
+                        i |= DDMA_CFG_DP;
+                if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
+                        (dtp->dev_flags & DEV_FLAGS_SYNC))
+                                i |= DDMA_CFG_SYNC;
+                cp->ddma_cfg = i;
+                au_sync();
+
+                /*
+                 * Return a non-zero value that can be used to find the channel
+                 * information in subsequent operations.
+                 */
+                return (u32)(&chan_tab_ptr[chan]);
         }
-        return rv;
+
+        /* Release devices */
+        stp->dev_flags &= ~DEV_FLAGS_INUSE;
+        dtp->dev_flags &= ~DEV_FLAGS_INUSE;
+
+        return 0;
 }
 EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
 
@@ -572,7 +572,7 @@ EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
  * This updates the source pointer and byte count.  Normally used
  * for memory to fifo transfers.
  */
-u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
+u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
 {
         chan_tab_t              *ctp;
         au1x_ddma_desc_t        *dp;
@@ -598,7 +598,7 @@ u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
                 return 0;
 
         /* Load up buffer address and byte count. */
-        dp->dscr_source0 = virt_to_phys(buf);
+        dp->dscr_source0 = buf & ~0UL;
         dp->dscr_cmd1 = nbytes;
         /* Check flags */
         if (flags & DDMA_FLAGS_IE)
@@ -625,14 +625,13 @@ u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
         /* Return something non-zero. */
         return nbytes;
 }
-EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
+EXPORT_SYMBOL(au1xxx_dbdma_put_source);
 
 /* Put a destination buffer into the DMA ring.
  * This updates the destination pointer and byte count.  Normally used
  * to place an empty buffer into the ring for fifo to memory transfers.
  */
-u32
-_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
+u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
 {
         chan_tab_t              *ctp;
         au1x_ddma_desc_t        *dp;
@@ -662,7 +661,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
         if (flags & DDMA_FLAGS_NOIE)
                 dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
 
-        dp->dscr_dest0 = virt_to_phys(buf);
+        dp->dscr_dest0 = buf & ~0UL;
         dp->dscr_cmd1 = nbytes;
 #if 0
         printk(KERN_DEBUG "cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
@@ -688,7 +687,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
         /* Return something non-zero. */
         return nbytes;
 }
-EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
+EXPORT_SYMBOL(au1xxx_dbdma_put_dest);
 
 /*
  * Get a destination buffer into the DMA ring.
@@ -871,28 +870,6 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
         return IRQ_RETVAL(1);
 }
 
-static void au1xxx_dbdma_init(void)
-{
-        int irq_nr;
-
-        dbdma_gptr->ddma_config = 0;
-        dbdma_gptr->ddma_throttle = 0;
-        dbdma_gptr->ddma_inten = 0xffff;
-        au_sync();
-
-#if defined(CONFIG_SOC_AU1550)
-        irq_nr = AU1550_DDMA_INT;
-#elif defined(CONFIG_SOC_AU1200)
-        irq_nr = AU1200_DDMA_INT;
-#else
-        #error Unknown Au1x00 SOC
-#endif
-
-        if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
-                        "Au1xxx dbdma", (void *)dbdma_gptr))
-                printk(KERN_ERR "Can't get 1550 dbdma irq");
-}
-
 void au1xxx_dbdma_dump(u32 chanid)
 {
         chan_tab_t       *ctp;
@@ -906,7 +883,7 @@ void au1xxx_dbdma_dump(u32 chanid)
         dtp = ctp->chan_dest;
         cp = ctp->chan_ptr;
 
-        printk(KERN_DEBUG "Chan %x, stp %x (dev %d)  dtp %x (dev %d) \n",
+        printk(KERN_DEBUG "Chan %x, stp %x (dev %d)  dtp %x (dev %d)\n",
                           (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp,
                           dtp - dbdev_tab);
         printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n",
@@ -1041,4 +1018,38 @@ void au1xxx_dbdma_resume(void)
         }
 }
 #endif  /* CONFIG_PM */
+
+static int __init au1xxx_dbdma_init(void)
+{
+        int irq_nr, ret;
+
+        dbdma_gptr->ddma_config = 0;
+        dbdma_gptr->ddma_throttle = 0;
+        dbdma_gptr->ddma_inten = 0xffff;
+        au_sync();
+
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1550:
+                irq_nr = AU1550_DDMA_INT;
+                break;
+        case ALCHEMY_CPU_AU1200:
+                irq_nr = AU1200_DDMA_INT;
+                break;
+        default:
+                return -ENODEV;
+        }
+
+        ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED,
+                        "Au1xxx dbdma", (void *)dbdma_gptr);
+        if (ret)
+                printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
+        else {
+                dbdma_initialized = 1;
+                printk(KERN_INFO "Alchemy DBDMA initialized\n");
+        }
+
+        return ret;
+}
+subsys_initcall(au1xxx_dbdma_init);
+
 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index d6fbda232e6a..d5278877891d 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -29,6 +29,8 @@
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  *
  */
+
+#include <linux/init.h>
 #include <linux/module.h>
 #include <linux/kernel.h>
 #include <linux/errno.h>
@@ -188,17 +190,14 @@ int request_au1000_dma(int dev_id, const char *dev_str,
                 dev = &dma_dev_table[dev_id];
 
         if (irqhandler) {
-                chan->irq = AU1000_DMA_INT_BASE + i;
                 chan->irq_dev = irq_dev_id;
                 ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
                                   chan->irq_dev);
                 if (ret) {
-                        chan->irq = 0;
                         chan->irq_dev = NULL;
                         return ret;
                 }
         } else {
-                chan->irq = 0;
                 chan->irq_dev = NULL;
         }
 
@@ -226,13 +225,40 @@ void free_au1000_dma(unsigned int dmanr)
         }
 
         disable_dma(dmanr);
-        if (chan->irq)
+        if (chan->irq_dev)
                 free_irq(chan->irq, chan->irq_dev);
 
-        chan->irq = 0;
         chan->irq_dev = NULL;
         chan->dev_id = -1;
 }
 EXPORT_SYMBOL(free_au1000_dma);
 
+static int __init au1000_dma_init(void)
+{
+        int base, i;
+
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                base = AU1000_DMA_INT_BASE;
+                break;
+        case ALCHEMY_CPU_AU1500:
+                base = AU1500_DMA_INT_BASE;
+                break;
+        case ALCHEMY_CPU_AU1100:
+                base = AU1100_DMA_INT_BASE;
+                break;
+        default:
+                goto out;
+        }
+
+        for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
+                au1000_dma_table[i].irq = base + i;
+
+        printk(KERN_INFO "Alchemy DMA initialized\n");
+
+out:
+        return 0;
+}
+arch_initcall(au1000_dma_init);
+
 #endif /* AU1000 AU1500 AU1100 */
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
index 1bfa91f939f4..c8e1a94d4a95 100644
--- a/arch/mips/alchemy/common/gpiolib-au1000.c
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -36,7 +36,6 @@
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/gpio.h>
 
-#if !defined(CONFIG_SOC_AU1000)
 static int gpio2_get(struct gpio_chip *chip, unsigned offset)
 {
         return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
@@ -63,7 +62,7 @@ static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
 {
         return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
 }
-#endif /* !defined(CONFIG_SOC_AU1000) */
+
 
 static int gpio1_get(struct gpio_chip *chip, unsigned offset)
 {
@@ -104,7 +103,6 @@ struct gpio_chip alchemy_gpio_chip[] = {
                 .base                   = ALCHEMY_GPIO1_BASE,
                 .ngpio                  = ALCHEMY_GPIO1_NUM,
         },
-#if !defined(CONFIG_SOC_AU1000)
         [1] = {
                 .label                  = "alchemy-gpio2",
                 .direction_input        = gpio2_direction_input,
@@ -115,15 +113,13 @@ struct gpio_chip alchemy_gpio_chip[] = {
                 .base                   = ALCHEMY_GPIO2_BASE,
                 .ngpio                  = ALCHEMY_GPIO2_NUM,
         },
-#endif
 };
 
 static int __init alchemy_gpiolib_init(void)
 {
         gpiochip_add(&alchemy_gpio_chip[0]);
-#if !defined(CONFIG_SOC_AU1000)
-        gpiochip_add(&alchemy_gpio_chip[1]);
-#endif
+        if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
+                gpiochip_add(&alchemy_gpio_chip[1]);
 
         return 0;
 }
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index d670928afcfd..b2821ace4d00 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -39,168 +39,180 @@
 
 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
 
+/* NOTE on interrupt priorities: The original writers of this code said:
+ *
+ * Because of the tight timing of SETUP token to reply transactions,
+ * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
+ * needs the highest priority.
+ */
+
 /* per-processor fixed function irqs */
-struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = {
-
-#if defined(CONFIG_SOC_AU1000)
-        { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
-
-#elif defined(CONFIG_SOC_AU1500)
-
-        { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
-
-#elif defined(CONFIG_SOC_AU1100)
-
-        { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
+struct au1xxx_irqmap {
+        int im_irq;
+        int im_type;
+        int im_request;         /* set 1 to get higher priority */
+};
+
+struct au1xxx_irqmap au1000_irqmap[] __initdata = {
+        { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
+        { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
-
-#elif defined(CONFIG_SOC_AU1550)
-
-        { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
+        { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
+        { -1, },
+};
+
+struct au1xxx_irqmap au1500_irqmap[] __initdata = {
+        { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
+        { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
+        { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
+        { -1, },
+};
+
+struct au1xxx_irqmap au1100_irqmap[] __initdata = {
+        { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
+        { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
+        { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
+        { -1, },
+};
+
+struct au1xxx_irqmap au1550_irqmap[] __initdata = {
+        { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
+        { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
         { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
-        { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-
-#elif defined(CONFIG_SOC_AU1200)
-
-        { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
-        { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
-        { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-        { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
-
-#else
-#error "Error: Unknown Alchemy SOC"
-#endif
+        { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
+        { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { -1, },
+};
+
+struct au1xxx_irqmap au1200_irqmap[] __initdata = {
+        { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
+        { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
+        { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
+        { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
+        { -1, },
 };
 
 
@@ -306,7 +318,7 @@ static void au1x_ic1_unmask(unsigned int irq_nr)
  * nowhere in the current kernel sources is it disabled.        --mlau
  */
 #if defined(CONFIG_MIPS_PB1000)
-        if (irq_nr == AU1000_GPIO_15)
+        if (irq_nr == AU1000_GPIO15_INT)
                 au_writel(0x4000, PB1000_MDR); /* enable int */
 #endif
         au_sync();
@@ -378,11 +390,13 @@ static void au1x_ic1_maskack(unsigned int irq_nr)
 
 static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
 {
-        unsigned int bit = irq - AU1000_INTC1_INT_BASE;
+        int bit = irq - AU1000_INTC1_INT_BASE;
         unsigned long wakemsk, flags;
 
-        /* only GPIO 0-7 can act as wakeup source: */
-        if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))
+        /* only GPIO 0-7 can act as wakeup source.  Fortunately these
+         * are wired up identically on all supported variants.
+         */
+        if ((bit < 0) || (bit > 7))
                 return -EINVAL;
 
         local_irq_save(flags);
@@ -504,11 +518,11 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
 asmlinkage void plat_irq_dispatch(void)
 {
         unsigned int pending = read_c0_status() & read_c0_cause();
-        unsigned long s, off, bit;
+        unsigned long s, off;
 
         if (pending & CAUSEF_IP7) {
-                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
-                return;
+                off = MIPS_CPU_IRQ_BASE + 7;
+                goto handle;
         } else if (pending & CAUSEF_IP2) {
                 s = IC0_REQ0INT;
                 off = AU1000_INTC0_INT_BASE;
@@ -524,58 +538,20 @@ asmlinkage void plat_irq_dispatch(void)
         } else
                 goto spurious;
 
-        bit = 0;
         s = au_readl(s);
         if (unlikely(!s)) {
 spurious:
                 spurious_interrupt();
                 return;
         }
-#ifdef AU1000_USB_DEV_REQ_INT
-        /*
-         * Because of the tight timing of SETUP token to reply
-         * transactions, the USB devices-side packet complete
-         * interrupt needs the highest priority.
-         */
-        bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
-        if ((pending & CAUSEF_IP2) && (s & bit)) {
-                do_IRQ(AU1000_USB_DEV_REQ_INT);
-                return;
-        }
-#endif
-        do_IRQ(__ffs(s) + off);
+        off += __ffs(s);
+handle:
+        do_IRQ(off);
 }
 
-/* setup edge/level and assign request 0/1 */
-void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
+static void __init au1000_init_irq(struct au1xxx_irqmap *map)
 {
         unsigned int bit, irq_nr;
-
-        while (count--) {
-                irq_nr = map[count].im_irq;
-
-                if (((irq_nr < AU1000_INTC0_INT_BASE) ||
-                     (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
-                    ((irq_nr < AU1000_INTC1_INT_BASE) ||
-                     (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
-                        continue;
-
-                if (irq_nr >= AU1000_INTC1_INT_BASE) {
-                        bit = irq_nr - AU1000_INTC1_INT_BASE;
-                        if (map[count].im_request)
-                                au_writel(1 << bit, IC1_ASSIGNCLR);
-                } else {
-                        bit = irq_nr - AU1000_INTC0_INT_BASE;
-                        if (map[count].im_request)
-                                au_writel(1 << bit, IC0_ASSIGNCLR);
-                }
-
-                au1x_ic_settype(irq_nr, map[count].im_type);
-        }
-}
-
-void __init arch_init_irq(void)
-{
         int i;
 
         /*
@@ -585,7 +561,7 @@ void __init arch_init_irq(void)
         au_writel(0xffffffff, IC0_CFG1CLR);
         au_writel(0xffffffff, IC0_CFG2CLR);
         au_writel(0xffffffff, IC0_MASKCLR);
-        au_writel(0xffffffff, IC0_ASSIGNSET);
+        au_writel(0xffffffff, IC0_ASSIGNCLR);
         au_writel(0xffffffff, IC0_WAKECLR);
         au_writel(0xffffffff, IC0_SRCSET);
         au_writel(0xffffffff, IC0_FALLINGCLR);
@@ -596,7 +572,7 @@ void __init arch_init_irq(void)
         au_writel(0xffffffff, IC1_CFG1CLR);
         au_writel(0xffffffff, IC1_CFG2CLR);
         au_writel(0xffffffff, IC1_MASKCLR);
-        au_writel(0xffffffff, IC1_ASSIGNSET);
+        au_writel(0xffffffff, IC1_ASSIGNCLR);
         au_writel(0xffffffff, IC1_WAKECLR);
         au_writel(0xffffffff, IC1_SRCSET);
         au_writel(0xffffffff, IC1_FALLINGCLR);
@@ -619,11 +595,43 @@ void __init arch_init_irq(void)
         /*
          * Initialize IC0, which is fixed per processor.
          */
-        au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
+        while (map->im_irq != -1) {
+                irq_nr = map->im_irq;
 
-        /* Boards can register additional (GPIO-based) IRQs.
-        */
-        board_init_irq();
+                if (irq_nr >= AU1000_INTC1_INT_BASE) {
+                        bit = irq_nr - AU1000_INTC1_INT_BASE;
+                        if (map->im_request)
+                                au_writel(1 << bit, IC1_ASSIGNSET);
+                } else {
+                        bit = irq_nr - AU1000_INTC0_INT_BASE;
+                        if (map->im_request)
+                                au_writel(1 << bit, IC0_ASSIGNSET);
+                }
+
+                au1x_ic_settype(irq_nr, map->im_type);
+                ++map;
+        }
 
         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
 }
+
+void __init arch_init_irq(void)
+{
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                au1000_init_irq(au1000_irqmap);
+                break;
+        case ALCHEMY_CPU_AU1500:
+                au1000_init_irq(au1500_irqmap);
+                break;
+        case ALCHEMY_CPU_AU1100:
+                au1000_init_irq(au1100_irqmap);
+                break;
+        case ALCHEMY_CPU_AU1550:
+                au1000_init_irq(au1550_irqmap);
+                break;
+        case ALCHEMY_CPU_AU1200:
+                au1000_init_irq(au1200_irqmap);
+                break;
+        }
+}
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 117f99f70649..2580e77624d2 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -19,39 +19,40 @@
 #include <asm/mach-au1x00/au1xxx.h>
 #include <asm/mach-au1x00/au1xxx_dbdma.h>
 #include <asm/mach-au1x00/au1100_mmc.h>
-
-#define PORT(_base, _irq)                               \
-        {                                               \
-                .iobase         = _base,                \
-                .membase        = (void __iomem *)_base,\
-                .mapbase        = CPHYSADDR(_base),     \
-                .irq            = _irq,                 \
-                .regshift       = 2,                    \
-                .iotype         = UPIO_AU,              \
-                .flags          = UPF_SKIP_TEST         \
+#include <asm/mach-au1x00/au1xxx_eth.h>
+
+#define PORT(_base, _irq)                                       \
+        {                                                       \
+                .mapbase        = _base,                        \
+                .irq            = _irq,                         \
+                .regshift       = 2,                            \
+                .iotype         = UPIO_AU,                      \
+                .flags          = UPF_SKIP_TEST | UPF_IOREMAP | \
+                                  UPF_FIXED_TYPE,               \
+                .type           = PORT_16550A,                  \
         }
 
 static struct plat_serial8250_port au1x00_uart_data[] = {
 #if defined(CONFIG_SERIAL_8250_AU1X00)
 #if defined(CONFIG_SOC_AU1000)
-        PORT(UART0_ADDR, AU1000_UART0_INT),
-        PORT(UART1_ADDR, AU1000_UART1_INT),
-        PORT(UART2_ADDR, AU1000_UART2_INT),
-        PORT(UART3_ADDR, AU1000_UART3_INT),
+        PORT(UART0_PHYS_ADDR, AU1000_UART0_INT),
+        PORT(UART1_PHYS_ADDR, AU1000_UART1_INT),
+        PORT(UART2_PHYS_ADDR, AU1000_UART2_INT),
+        PORT(UART3_PHYS_ADDR, AU1000_UART3_INT),
 #elif defined(CONFIG_SOC_AU1500)
-        PORT(UART0_ADDR, AU1500_UART0_INT),
-        PORT(UART3_ADDR, AU1500_UART3_INT),
+        PORT(UART0_PHYS_ADDR, AU1500_UART0_INT),
+        PORT(UART3_PHYS_ADDR, AU1500_UART3_INT),
 #elif defined(CONFIG_SOC_AU1100)
-        PORT(UART0_ADDR, AU1100_UART0_INT),
-        PORT(UART1_ADDR, AU1100_UART1_INT),
-        PORT(UART3_ADDR, AU1100_UART3_INT),
+        PORT(UART0_PHYS_ADDR, AU1100_UART0_INT),
+        PORT(UART1_PHYS_ADDR, AU1100_UART1_INT),
+        PORT(UART3_PHYS_ADDR, AU1100_UART3_INT),
 #elif defined(CONFIG_SOC_AU1550)
-        PORT(UART0_ADDR, AU1550_UART0_INT),
-        PORT(UART1_ADDR, AU1550_UART1_INT),
-        PORT(UART3_ADDR, AU1550_UART3_INT),
+        PORT(UART0_PHYS_ADDR, AU1550_UART0_INT),
+        PORT(UART1_PHYS_ADDR, AU1550_UART1_INT),
+        PORT(UART3_PHYS_ADDR, AU1550_UART3_INT),
 #elif defined(CONFIG_SOC_AU1200)
-        PORT(UART0_ADDR, AU1200_UART0_INT),
-        PORT(UART1_ADDR, AU1200_UART1_INT),
+        PORT(UART0_PHYS_ADDR, AU1200_UART0_INT),
+        PORT(UART1_PHYS_ADDR, AU1200_UART1_INT),
 #endif
 #endif  /* CONFIG_SERIAL_8250_AU1X00 */
         { },
@@ -73,8 +74,8 @@ static struct resource au1xxx_usb_ohci_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = AU1000_USB_HOST_INT,
-                .end            = AU1000_USB_HOST_INT,
+                .start          = FOR_PLATFORM_C_USB_HOST_INT,
+                .end            = FOR_PLATFORM_C_USB_HOST_INT,
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -132,8 +133,8 @@ static struct resource au1xxx_usb_ehci_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .start          = AU1000_USB_HOST_INT,
-                .end            = AU1000_USB_HOST_INT,
+                .start          = AU1200_USB_INT,
+                .end            = AU1200_USB_INT,
                 .flags          = IORESOURCE_IRQ,
         },
 };
@@ -308,11 +309,6 @@ static struct platform_device au1200_mmc1_device = {
 #endif /* #ifndef CONFIG_MIPS_DB1200 */
 #endif /* #ifdef CONFIG_SOC_AU1200 */
 
-static struct platform_device au1x00_pcmcia_device = {
-        .name           = "au1x00-pcmcia",
-        .id             = 0,
-};
-
 /* All Alchemy demoboards with I2C have this #define in their headers */
 #ifdef SMBUS_PSC_BASE
 static struct resource pbdb_smbus_resources[] = {
@@ -331,10 +327,92 @@ static struct platform_device pbdb_smbus_device = {
 };
 #endif
 
+/* Macro to help defining the Ethernet MAC resources */
+#define MAC_RES(_base, _enable, _irq)                   \
+        {                                               \
+                .start  = CPHYSADDR(_base),             \
+                .end    = CPHYSADDR(_base + 0xffff),    \
+                .flags  = IORESOURCE_MEM,               \
+        },                                              \
+        {                                               \
+                .start  = CPHYSADDR(_enable),           \
+                .end    = CPHYSADDR(_enable + 0x3),     \
+                .flags  = IORESOURCE_MEM,               \
+        },                                              \
+        {                                               \
+                .start  = _irq,                         \
+                .end    = _irq,                         \
+                .flags  = IORESOURCE_IRQ                \
+        }
+
+static struct resource au1xxx_eth0_resources[] = {
+#if defined(CONFIG_SOC_AU1000)
+        MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT),
+#elif defined(CONFIG_SOC_AU1100)
+        MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT),
+#elif defined(CONFIG_SOC_AU1550)
+        MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT),
+#elif defined(CONFIG_SOC_AU1500)
+        MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT),
+#endif
+};
+
+
+static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
+        .phy1_search_mac0 = 1,
+};
+
+static struct platform_device au1xxx_eth0_device = {
+        .name           = "au1000-eth",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(au1xxx_eth0_resources),
+        .resource       = au1xxx_eth0_resources,
+        .dev.platform_data = &au1xxx_eth0_platform_data,
+};
+
+#ifndef CONFIG_SOC_AU1100
+static struct resource au1xxx_eth1_resources[] = {
+#if defined(CONFIG_SOC_AU1000)
+        MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT),
+#elif defined(CONFIG_SOC_AU1550)
+        MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT),
+#elif defined(CONFIG_SOC_AU1500)
+        MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT),
+#endif
+};
+
+static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
+        .phy1_search_mac0 = 1,
+};
+
+static struct platform_device au1xxx_eth1_device = {
+        .name           = "au1000-eth",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(au1xxx_eth1_resources),
+        .resource       = au1xxx_eth1_resources,
+        .dev.platform_data = &au1xxx_eth1_platform_data,
+};
+#endif
+
+void __init au1xxx_override_eth_cfg(unsigned int port,
+                        struct au1000_eth_platform_data *eth_data)
+{
+        if (!eth_data || port > 1)
+                return;
+
+        if (port == 0)
+                memcpy(&au1xxx_eth0_platform_data, eth_data,
+                        sizeof(struct au1000_eth_platform_data));
+#ifndef CONFIG_SOC_AU1100
+        else
+                memcpy(&au1xxx_eth1_platform_data, eth_data,
+                        sizeof(struct au1000_eth_platform_data));
+#endif
+}
+
 static struct platform_device *au1xxx_platform_devices[] __initdata = {
         &au1xx0_uart_device,
         &au1xxx_usb_ohci_device,
-        &au1x00_pcmcia_device,
 #ifdef CONFIG_FB_AU1100
         &au1100_lcd_device,
 #endif
@@ -351,6 +429,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = {
 #ifdef SMBUS_PSC_BASE
         &pbdb_smbus_device,
 #endif
+        &au1xxx_eth0_device,
 };
 
 static int __init au1xxx_platform_init(void)
@@ -362,6 +441,12 @@ static int __init au1xxx_platform_init(void)
         for (i = 0; au1x00_uart_data[i].flags; i++)
                 au1x00_uart_data[i].uartclk = uartclk;
 
+#ifndef CONFIG_SOC_AU1100
+        /* Register second MAC if enabled in pinfunc */
+        if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
+                platform_device_register(&au1xxx_eth1_device);
+#endif
+
         return platform_add_devices(au1xxx_platform_devices,
                                     ARRAY_SIZE(au1xxx_platform_devices));
 }
diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c
index 18b310b475ca..c29511b11d44 100644
--- a/arch/mips/alchemy/common/prom.c
+++ b/arch/mips/alchemy/common/prom.c
@@ -43,29 +43,15 @@ int prom_argc;
 char **prom_argv;
 char **prom_envp;
 
-char * __init_or_module prom_getcmdline(void)
-{
-        return &(arcs_cmdline[0]);
-}
-
 void prom_init_cmdline(void)
 {
-        char *cp;
-        int actr;
-
-        actr = 1; /* Always ignore argv[0] */
+        int i;
 
-        cp = &(arcs_cmdline[0]);
-        while (actr < prom_argc) {
-                strcpy(cp, prom_argv[actr]);
-                cp += strlen(prom_argv[actr]);
-                *cp++ = ' ';
-                actr++;
+        for (i = 1; i < prom_argc; i++) {
+                strlcat(arcs_cmdline, prom_argv[i], COMMAND_LINE_SIZE);
+                if (i < (prom_argc - 1))
+                        strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
         }
-        if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
-                --cp;
-        if (prom_argc > 1)
-                *cp = '\0';
 }
 
 char *prom_getenv(char *envname)
@@ -121,14 +107,12 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
 int prom_get_ethernet_addr(char *ethernet_addr)
 {
         char *ethaddr_str;
-        char *argptr;
 
         /* Check the environment variables first */
         ethaddr_str = prom_getenv("ethaddr");
         if (!ethaddr_str) {
                 /* Check command line */
-                argptr = prom_getcmdline();
-                ethaddr_str = strstr(argptr, "ethaddr=");
+                ethaddr_str = strstr(arcs_cmdline, "ethaddr=");
                 if (!ethaddr_str)
                         return -1;
 
diff --git a/arch/mips/alchemy/common/puts.c b/arch/mips/alchemy/common/puts.c
deleted file mode 100644
index 55bbe24d45b6..000000000000
--- a/arch/mips/alchemy/common/puts.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Low level UART routines to directly access Alchemy UART.
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <asm/mach-au1x00/au1000.h>
-
-#define SERIAL_BASE   UART_BASE
-#define SER_CMD       0x7
-#define SER_DATA      0x1
-#define TX_BUSY       0x20
-
-#define TIMEOUT       0xffffff
-#define SLOW_DOWN
-
-static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
-
-#ifdef SLOW_DOWN
-static inline void slow_down(void)
-{
-        int k;
-
-        for (k = 0; k < 10000; k++);
-}
-#else
-#define slow_down()
-#endif
-
-void
-prom_putchar(const unsigned char c)
-{
-        unsigned char ch;
-        int i = 0;
-
-        do {
-                ch = com1[SER_CMD];
-                slow_down();
-                i++;
-                if (i > TIMEOUT)
-                        break;
-        } while (0 == (ch & TX_BUSY));
-
-        com1[SER_DATA] = c;
-}
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
deleted file mode 100644
index 4791011e8f92..000000000000
--- a/arch/mips/alchemy/common/reset.c
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Au1xx0 reset routines.
- *
- * Copyright 2001, 2006, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/gpio.h>
-
-#include <asm/cacheflush.h>
-#include <asm/mach-au1x00/au1000.h>
-
-void au1000_restart(char *command)
-{
-        /* Set all integrated peripherals to disabled states */
-        extern void board_reset(void);
-        u32 prid = read_c0_prid();
-
-        printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
-
-        switch (prid & 0xFF000000) {
-        case 0x00000000: /* Au1000 */
-                au_writel(0x02, 0xb0000010); /* ac97_enable */
-                au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
-                asm("sync");
-                au_writel(0x00, 0xb017fffc); /* usbh_enable */
-                au_writel(0x00, 0xb0200058); /* usbd_enable */
-                au_writel(0x00, 0xb0300040); /* ir_enable */
-                au_writel(0x00, 0xb4004104); /* mac dma */
-                au_writel(0x00, 0xb4004114); /* mac dma */
-                au_writel(0x00, 0xb4004124); /* mac dma */
-                au_writel(0x00, 0xb4004134); /* mac dma */
-                au_writel(0x00, 0xb0520000); /* macen0 */
-                au_writel(0x00, 0xb0520004); /* macen1 */
-                au_writel(0x00, 0xb1000008); /* i2s_enable  */
-                au_writel(0x00, 0xb1100100); /* uart0_enable */
-                au_writel(0x00, 0xb1200100); /* uart1_enable */
-                au_writel(0x00, 0xb1300100); /* uart2_enable */
-                au_writel(0x00, 0xb1400100); /* uart3_enable */
-                au_writel(0x02, 0xb1600100); /* ssi0_enable */
-                au_writel(0x02, 0xb1680100); /* ssi1_enable */
-                au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
-                au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
-                au_writel(0x00, 0xb1900028); /* sys_clksrc */
-                au_writel(0x10, 0xb1900060); /* sys_cpupll */
-                au_writel(0x00, 0xb1900064); /* sys_auxpll */
-                au_writel(0x00, 0xb1900100); /* sys_pininputen */
-                break;
-        case 0x01000000: /* Au1500 */
-                au_writel(0x02, 0xb0000010); /* ac97_enable */
-                au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
-                asm("sync");
-                au_writel(0x00, 0xb017fffc); /* usbh_enable */
-                au_writel(0x00, 0xb0200058); /* usbd_enable */
-                au_writel(0x00, 0xb4004104); /* mac dma */
-                au_writel(0x00, 0xb4004114); /* mac dma */
-                au_writel(0x00, 0xb4004124); /* mac dma */
-                au_writel(0x00, 0xb4004134); /* mac dma */
-                au_writel(0x00, 0xb1520000); /* macen0 */
-                au_writel(0x00, 0xb1520004); /* macen1 */
-                au_writel(0x00, 0xb1100100); /* uart0_enable */
-                au_writel(0x00, 0xb1400100); /* uart3_enable */
-                au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
-                au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
-                au_writel(0x00, 0xb1900028); /* sys_clksrc */
-                au_writel(0x10, 0xb1900060); /* sys_cpupll */
-                au_writel(0x00, 0xb1900064); /* sys_auxpll */
-                au_writel(0x00, 0xb1900100); /* sys_pininputen */
-                break;
-        case 0x02000000: /* Au1100 */
-                au_writel(0x02, 0xb0000010); /* ac97_enable */
-                au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
-                asm("sync");
-                au_writel(0x00, 0xb017fffc); /* usbh_enable */
-                au_writel(0x00, 0xb0200058); /* usbd_enable */
-                au_writel(0x00, 0xb0300040); /* ir_enable */
-                au_writel(0x00, 0xb4004104); /* mac dma */
-                au_writel(0x00, 0xb4004114); /* mac dma */
-                au_writel(0x00, 0xb4004124); /* mac dma */
-                au_writel(0x00, 0xb4004134); /* mac dma */
-                au_writel(0x00, 0xb0520000); /* macen0 */
-                au_writel(0x00, 0xb1000008); /* i2s_enable  */
-                au_writel(0x00, 0xb1100100); /* uart0_enable */
-                au_writel(0x00, 0xb1200100); /* uart1_enable */
-                au_writel(0x00, 0xb1400100); /* uart3_enable */
-                au_writel(0x02, 0xb1600100); /* ssi0_enable */
-                au_writel(0x02, 0xb1680100); /* ssi1_enable */
-                au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
-                au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
-                au_writel(0x00, 0xb1900028); /* sys_clksrc */
-                au_writel(0x10, 0xb1900060); /* sys_cpupll */
-                au_writel(0x00, 0xb1900064); /* sys_auxpll */
-                au_writel(0x00, 0xb1900100); /* sys_pininputen */
-                break;
-        case 0x03000000: /* Au1550 */
-                au_writel(0x00, 0xb1a00004); /* psc 0 */
-                au_writel(0x00, 0xb1b00004); /* psc 1 */
-                au_writel(0x00, 0xb0a00004); /* psc 2 */
-                au_writel(0x00, 0xb0b00004); /* psc 3 */
-                au_writel(0x00, 0xb017fffc); /* usbh_enable */
-                au_writel(0x00, 0xb0200058); /* usbd_enable */
-                au_writel(0x00, 0xb4004104); /* mac dma */
-                au_writel(0x00, 0xb4004114); /* mac dma */
-                au_writel(0x00, 0xb4004124); /* mac dma */
-                au_writel(0x00, 0xb4004134); /* mac dma */
-                au_writel(0x00, 0xb1520000); /* macen0 */
-                au_writel(0x00, 0xb1520004); /* macen1 */
-                au_writel(0x00, 0xb1100100); /* uart0_enable */
-                au_writel(0x00, 0xb1200100); /* uart1_enable */
-                au_writel(0x00, 0xb1400100); /* uart3_enable */
-                au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
-                au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
-                au_writel(0x00, 0xb1900028); /* sys_clksrc */
-                au_writel(0x10, 0xb1900060); /* sys_cpupll */
-                au_writel(0x00, 0xb1900064); /* sys_auxpll */
-                au_writel(0x00, 0xb1900100); /* sys_pininputen */
-                break;
-        }
-
-        set_c0_status(ST0_BEV | ST0_ERL);
-        change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
-        flush_cache_all();
-        write_c0_wired(0);
-
-        /* Give board a chance to do a hardware reset */
-        board_reset();
-
-        /* Jump to the beggining in case board_reset() is empty */
-        __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
-}
-
-void au1000_halt(void)
-{
-#if defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550)
-        /* Power off system */
-        printk(KERN_NOTICE "\n** Powering off...\n");
-        au_writew(au_readw(0xAF00001C) | (3 << 14), 0xAF00001C);
-        au_sync();
-        while (1); /* should not get here */
-#else
-        printk(KERN_NOTICE "\n** You can safely turn off the power\n");
-#ifdef CONFIG_MIPS_MIRAGE
-        gpio_direction_output(210, 1);
-#endif
-#ifdef CONFIG_MIPS_DB1200
-        au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
-#endif
-#ifdef CONFIG_PM
-        au_sleep();
-
-        /* Should not get here */
-        printk(KERN_ERR "Unable to put CPU in sleep mode\n");
-        while (1);
-#else
-        while (1)
-                __asm__(".set\tmips3\n\t"
-                        "wait\n\t"
-                        ".set\tmips0");
-#endif
-#endif /* defined(CONFIG_MIPS_PB1550) || defined(CONFIG_MIPS_DB1550) */
-}
-
-void au1000_power_off(void)
-{
-        au1000_halt();
-}
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 6184baa56786..561e5da2658b 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -29,18 +29,13 @@
 #include <linux/ioport.h>
 #include <linux/jiffies.h>
 #include <linux/module.h>
-#include <linux/pm.h>
 
 #include <asm/mipsregs.h>
-#include <asm/reboot.h>
 #include <asm/time.h>
 
 #include <au1000.h>
 
 extern void __init board_setup(void);
-extern void au1000_restart(char *);
-extern void au1000_halt(void);
-extern void au1000_power_off(void);
 extern void set_cpuspec(void);
 
 void __init plat_mem_setup(void)
@@ -57,10 +52,6 @@ void __init plat_mem_setup(void)
         /* this is faster than wasting cycles trying to approximate it */
         preset_lpj = (est_freq >> 1) / HZ;
 
-        _machine_restart = au1000_restart;
-        _machine_halt = au1000_halt;
-        pm_power_off = au1000_power_off;
-
         board_setup();  /* board specific setup */
 
         if (au1xxx_cpu_needs_config_od())
@@ -78,37 +69,20 @@ void __init plat_mem_setup(void)
         iomem_resource.end = IOMEM_RESOURCE_END;
 }
 
-#if defined(CONFIG_64BIT_PHYS_ADDR)
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
 /* This routine should be valid for all Au1x based boards */
 phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
 {
+        u32 start = (u32)Au1500_PCI_MEM_START;
+        u32 end   = (u32)Au1500_PCI_MEM_END;
+
         /* Don't fixup 36-bit addresses */
         if ((phys_addr >> 32) != 0)
                 return phys_addr;
 
-#ifdef CONFIG_PCI
-        {
-                u32 start = (u32)Au1500_PCI_MEM_START;
-                u32 end   = (u32)Au1500_PCI_MEM_END;
-
-                /* Check for PCI memory window */
-                if (phys_addr >= start && (phys_addr + size - 1) <= end)
-                        return (phys_t)
-                               ((phys_addr - start) + Au1500_PCI_MEM_START);
-        }
-#endif
-
-        /*
-         * All Au1xx0 SOCs have a PCMCIA controller.
-         * We setup our 32-bit pseudo addresses to be equal to the
-         * 36-bit addr >> 4, to make it easier to check the address
-         * and fix it.
-         * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000.
-         * The pseudo address we use is 0xF400 0000. Any address over
-         * 0xF400 0000 is a PCMCIA pseudo address.
-         */
-        if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF))
-                return (phys_t)(phys_addr << 4);
+        /* Check for PCI memory window */
+        if (phys_addr >= start && (phys_addr + size - 1) <= end)
+                return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
 
         /* default nop */
         return phys_addr;
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 379a664809b0..2aecb2fdf982 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
+ * Copyright (C) 2008-2009 Manuel Lauss <manuel.lauss@gmail.com>
  *
  * Previous incarnations were:
  * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
@@ -85,7 +85,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
         .name           = "rtcmatch2",
         .features       = CLOCK_EVT_FEAT_ONESHOT,
         .rating         = 100,
-        .irq            = AU1000_RTC_MATCH2_INT,
         .set_next_event = au1x_rtcmatch2_set_next_event,
         .set_mode       = au1x_rtcmatch2_set_mode,
         .cpumask        = cpu_all_mask,
@@ -98,11 +97,13 @@ static struct irqaction au1x_rtcmatch2_irqaction = {
         .dev_id         = &au1x_rtcmatch2_clockdev,
 };
 
-void __init plat_time_init(void)
+static int __init alchemy_time_init(unsigned int m2int)
 {
         struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
         unsigned long t;
 
+        au1x_rtcmatch2_clockdev.irq = m2int;
+
         /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
          * has been detected.  If so install the rtcmatch2 clocksource,
          * otherwise don't bother.  Note that both bits being set is by
@@ -148,13 +149,18 @@ void __init plat_time_init(void)
         cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
         cd->min_delta_ns = clockevent_delta2ns(8, cd);  /* ~0.25ms */
         clockevents_register_device(cd);
-        setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);
+        setup_irq(m2int, &au1x_rtcmatch2_irqaction);
 
         printk(KERN_INFO "Alchemy clocksource installed\n");
 
-        return;
+        return 0;
 
 cntr_err:
+        return -1;
+}
+
+static void __init alchemy_setup_c0timer(void)
+{
         /*
          * MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this
          * function is called.  Because the Alchemy counters are unusable
@@ -166,3 +172,22 @@ cntr_err:
         r4k_clockevent_init();
         init_r4k_clocksource();
 }
+
+static int alchemy_m2inttab[] __initdata = {
+        AU1000_RTC_MATCH2_INT,
+        AU1500_RTC_MATCH2_INT,
+        AU1100_RTC_MATCH2_INT,
+        AU1550_RTC_MATCH2_INT,
+        AU1200_RTC_MATCH2_INT,
+};
+
+void __init plat_time_init(void)
+{
+        int t;
+
+        t = alchemy_get_cputype();
+        if (t == ALCHEMY_CPU_UNKNOWN)
+                alchemy_setup_c0timer();
+        else if (alchemy_time_init(alchemy_m2inttab[t]))
+                alchemy_setup_c0timer();
+}
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
index 730f9f2b30e8..ecbd37f9ee87 100644
--- a/arch/mips/alchemy/devboards/Makefile
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -2,7 +2,7 @@
 # Alchemy Develboards
 #
 
-obj-y += prom.o
+obj-y += prom.o bcsr.o platform.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_MIPS_PB1000)       += pb1000/
 obj-$(CONFIG_MIPS_PB1100)       += pb1100/
@@ -11,8 +11,10 @@ obj-$(CONFIG_MIPS_PB1500)	+= pb1500/
 obj-$(CONFIG_MIPS_PB1550)       += pb1550/
 obj-$(CONFIG_MIPS_DB1000)       += db1x00/
 obj-$(CONFIG_MIPS_DB1100)       += db1x00/
-obj-$(CONFIG_MIPS_DB1200)       += pb1200/
+obj-$(CONFIG_MIPS_DB1200)       += db1200/
 obj-$(CONFIG_MIPS_DB1500)       += db1x00/
 obj-$(CONFIG_MIPS_DB1550)       += db1x00/
 obj-$(CONFIG_MIPS_BOSPORUS)     += db1x00/
 obj-$(CONFIG_MIPS_MIRAGE)       += db1x00/
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
new file mode 100644
index 000000000000..3bc4fd2155d7
--- /dev/null
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -0,0 +1,148 @@
+/*
+ * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
+ *
+ * All Alchemy development boards (except, of course, the weird PB1000)
+ * have a few registers in a CPLD with standardised layout; they mostly
+ * only differ in base address.
+ * All registers are 16bits wide with 32bit spacing.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+static struct bcsr_reg {
+        void __iomem *raddr;
+        spinlock_t lock;
+} bcsr_regs[BCSR_CNT];
+
+static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */
+static int bcsr_csc_base;       /* linux-irq of first cascaded irq */
+
+void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
+{
+        int i;
+
+        bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
+        bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
+
+        bcsr_virt = (void __iomem *)bcsr1_phys;
+
+        for (i = 0; i < BCSR_CNT; i++) {
+                if (i >= BCSR_HEXLEDS)
+                        bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
+                                        (0x04 * (i - BCSR_HEXLEDS));
+                else
+                        bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
+                                        (0x04 * i);
+
+                spin_lock_init(&bcsr_regs[i].lock);
+        }
+}
+
+unsigned short bcsr_read(enum bcsr_id reg)
+{
+        unsigned short r;
+        unsigned long flags;
+
+        spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
+        r = __raw_readw(bcsr_regs[reg].raddr);
+        spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
+        return r;
+}
+EXPORT_SYMBOL_GPL(bcsr_read);
+
+void bcsr_write(enum bcsr_id reg, unsigned short val)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
+        __raw_writew(val, bcsr_regs[reg].raddr);
+        wmb();
+        spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
+}
+EXPORT_SYMBOL_GPL(bcsr_write);
+
+void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set)
+{
+        unsigned short r;
+        unsigned long flags;
+
+        spin_lock_irqsave(&bcsr_regs[reg].lock, flags);
+        r = __raw_readw(bcsr_regs[reg].raddr);
+        r &= ~clr;
+        r |= set;
+        __raw_writew(r, bcsr_regs[reg].raddr);
+        wmb();
+        spin_unlock_irqrestore(&bcsr_regs[reg].lock, flags);
+}
+EXPORT_SYMBOL_GPL(bcsr_mod);
+
+/*
+ * DB1200/PB1200 CPLD IRQ muxer
+ */
+static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
+{
+        unsigned short bisr = __raw_readw(bcsr_virt + BCSR_REG_INTSTAT);
+
+        for ( ; bisr; bisr &= bisr - 1)
+                generic_handle_irq(bcsr_csc_base + __ffs(bisr));
+}
+
+/* NOTE: both the enable and mask bits must be cleared, otherwise the
+ * CPLD generates tons of spurious interrupts (at least on my DB1200).
+ *      -- mlau
+ */
+static void bcsr_irq_mask(unsigned int irq_nr)
+{
+        unsigned short v = 1 << (irq_nr - bcsr_csc_base);
+        __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
+        __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
+        wmb();
+}
+
+static void bcsr_irq_maskack(unsigned int irq_nr)
+{
+        unsigned short v = 1 << (irq_nr - bcsr_csc_base);
+        __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
+        __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
+        __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT);  /* ack */
+        wmb();
+}
+
+static void bcsr_irq_unmask(unsigned int irq_nr)
+{
+        unsigned short v = 1 << (irq_nr - bcsr_csc_base);
+        __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
+        __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
+        wmb();
+}
+
+static struct irq_chip bcsr_irq_type = {
+        .name           = "CPLD",
+        .mask           = bcsr_irq_mask,
+        .mask_ack       = bcsr_irq_maskack,
+        .unmask         = bcsr_irq_unmask,
+};
+
+void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
+{
+        unsigned int irq;
+
+        /* mask & disable & ack all */
+        __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
+        __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
+        __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
+        wmb();
+
+        bcsr_csc_base = csc_start;
+
+        for (irq = csc_start; irq <= csc_end; irq++)
+                set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
+                        handle_level_irq, "level");
+
+        set_irq_chained_handler(hook_irq, bcsr_csc_handler);
+}
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
new file mode 100644
index 000000000000..17840a5e2738
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/Makefile
@@ -0,0 +1 @@
+obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
new file mode 100644
index 000000000000..3cb95a98ab31
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -0,0 +1,561 @@
+/*
+ * DBAu1200 board platform device registration
+ *
+ * Copyright (C) 2008-2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/mmc/host.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/smc91x.h>
+
+#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1550_spi.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-db1x00/db1200.h>
+
+#include "../platform.h"
+
+static struct mtd_partition db1200_spiflash_parts[] = {
+        {
+                .name   = "DB1200 SPI flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data db1200_spiflash_data = {
+        .name           = "s25fl001",
+        .parts          = db1200_spiflash_parts,
+        .nr_parts       = ARRAY_SIZE(db1200_spiflash_parts),
+        .type           = "m25p10",
+};
+
+static struct spi_board_info db1200_spi_devs[] __initdata = {
+        {
+                /* TI TMP121AIDBVR temp sensor */
+                .modalias       = "tmp121",
+                .max_speed_hz   = 2000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = 0,
+        },
+        {
+                /* Spansion S25FL001D0FMA SPI flash */
+                .modalias       = "m25p80",
+                .max_speed_hz   = 50000000,
+                .bus_num        = 0,
+                .chip_select    = 1,
+                .mode           = 0,
+                .platform_data  = &db1200_spiflash_data,
+        },
+};
+
+static struct i2c_board_info db1200_i2c_devs[] __initdata = {
+        {
+                /* AT24C04-10 I2C eeprom */
+                I2C_BOARD_INFO("24c04", 0x52),
+        },
+        {
+                /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
+                I2C_BOARD_INFO("ne1619", 0x2d),
+        },
+        {
+                /* I2S audio codec WM8731 */
+                I2C_BOARD_INFO("wm8731", 0x1b),
+        },
+};
+
+/**********************************************************************/
+
+static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                 unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+
+        ioaddr &= 0xffffff00;
+
+        if (ctrl & NAND_CLE) {
+                ioaddr += MEM_STNAND_CMD;
+        } else if (ctrl & NAND_ALE) {
+                ioaddr += MEM_STNAND_ADDR;
+        } else {
+                /* assume we want to r/w real data  by default */
+                ioaddr += MEM_STNAND_DATA;
+        }
+        this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+        if (cmd != NAND_CMD_NONE) {
+                __raw_writeb(cmd, this->IO_ADDR_W);
+                wmb();
+        }
+}
+
+static int au1200_nand_device_ready(struct mtd_info *mtd)
+{
+        return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
+}
+
+static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition db1200_nand_parts[] = {
+        {
+                .name   = "NAND FS 0",
+                .offset = 0,
+                .size   = 8 * 1024 * 1024,
+        },
+        {
+                .name   = "NAND FS 1",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL
+        },
+};
+
+struct platform_nand_data db1200_nand_platdata = {
+        .chip = {
+                .nr_chips       = 1,
+                .chip_offset    = 0,
+                .nr_partitions  = ARRAY_SIZE(db1200_nand_parts),
+                .partitions     = db1200_nand_parts,
+                .chip_delay     = 20,
+                .part_probe_types = db1200_part_probes,
+        },
+        .ctrl = {
+                .dev_ready      = au1200_nand_device_ready,
+                .cmd_ctrl       = au1200_nand_cmd_ctrl,
+        },
+};
+
+static struct resource db1200_nand_res[] = {
+        [0] = {
+                .start  = DB1200_NAND_PHYS_ADDR,
+                .end    = DB1200_NAND_PHYS_ADDR + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device db1200_nand_dev = {
+        .name           = "gen_nand",
+        .num_resources  = ARRAY_SIZE(db1200_nand_res),
+        .resource       = db1200_nand_res,
+        .id             = -1,
+        .dev            = {
+                .platform_data = &db1200_nand_platdata,
+        }
+};
+
+/**********************************************************************/
+
+static struct smc91x_platdata db1200_eth_data = {
+        .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
+static struct resource db1200_eth_res[] = {
+        [0] = {
+                .start  = DB1200_ETH_PHYS_ADDR,
+                .end    = DB1200_ETH_PHYS_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DB1200_ETH_INT,
+                .end    = DB1200_ETH_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device db1200_eth_dev = {
+        .dev    = {
+                .platform_data  = &db1200_eth_data,
+        },
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(db1200_eth_res),
+        .resource       = db1200_eth_res,
+};
+
+/**********************************************************************/
+
+static struct resource db1200_ide_res[] = {
+        [0] = {
+                .start  = DB1200_IDE_PHYS_ADDR,
+                .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DB1200_IDE_INT,
+                .end    = DB1200_IDE_INT,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static u64 ide_dmamask = DMA_32BIT_MASK;
+
+static struct platform_device db1200_ide_dev = {
+        .name           = "au1200-ide",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &ide_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+        },
+        .num_resources  = ARRAY_SIZE(db1200_ide_res),
+        .resource       = db1200_ide_res,
+};
+
+/**********************************************************************/
+
+static struct platform_device db1200_rtc_dev = {
+        .name   = "rtc-au1xxx",
+        .id     = -1,
+};
+
+/**********************************************************************/
+
+/* SD carddetects:  they're supposed to be edge-triggered, but ack
+ * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
+ * is disabled and its counterpart enabled.  The 500ms timeout is
+ * because the carddetect isn't debounced in hardware.
+ */
+static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
+{
+        void(*mmc_cd)(struct mmc_host *, unsigned long);
+
+        if (irq == DB1200_SD0_INSERT_INT) {
+                disable_irq_nosync(DB1200_SD0_INSERT_INT);
+                enable_irq(DB1200_SD0_EJECT_INT);
+        } else {
+                disable_irq_nosync(DB1200_SD0_EJECT_INT);
+                enable_irq(DB1200_SD0_INSERT_INT);
+        }
+
+        /* link against CONFIG_MMC=m */
+        mmc_cd = symbol_get(mmc_detect_change);
+        if (mmc_cd) {
+                mmc_cd(ptr, msecs_to_jiffies(500));
+                symbol_put(mmc_detect_change);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int db1200_mmc_cd_setup(void *mmc_host, int en)
+{
+        int ret;
+
+        if (en) {
+                ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
+                                  IRQF_DISABLED, "sd_insert", mmc_host);
+                if (ret)
+                        goto out;
+
+                ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
+                                  IRQF_DISABLED, "sd_eject", mmc_host);
+                if (ret) {
+                        free_irq(DB1200_SD0_INSERT_INT, mmc_host);
+                        goto out;
+                }
+
+                if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
+                        enable_irq(DB1200_SD0_EJECT_INT);
+                else
+                        enable_irq(DB1200_SD0_INSERT_INT);
+
+        } else {
+                free_irq(DB1200_SD0_INSERT_INT, mmc_host);
+                free_irq(DB1200_SD0_EJECT_INT, mmc_host);
+        }
+        ret = 0;
+out:
+        return ret;
+}
+
+static void db1200_mmc_set_power(void *mmc_host, int state)
+{
+        if (state) {
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
+                msleep(400);    /* stabilization time */
+        } else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
+}
+
+static int db1200_mmc_card_readonly(void *mmc_host)
+{
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
+}
+
+static int db1200_mmc_card_inserted(void *mmc_host)
+{
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
+}
+
+static void db1200_mmcled_set(struct led_classdev *led,
+                              enum led_brightness brightness)
+{
+        if (brightness != LED_OFF)
+                bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
+        else
+                bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
+}
+
+static struct led_classdev db1200_mmc_led = {
+        .brightness_set = db1200_mmcled_set,
+};
+
+/* needed by arch/mips/alchemy/common/platform.c */
+struct au1xmmc_platform_data au1xmmc_platdata[] = {
+        [0] = {
+                .cd_setup       = db1200_mmc_cd_setup,
+                .set_power      = db1200_mmc_set_power,
+                .card_inserted  = db1200_mmc_card_inserted,
+                .card_readonly  = db1200_mmc_card_readonly,
+                .led            = &db1200_mmc_led,
+        },
+};
+
+/**********************************************************************/
+
+static struct resource au1200_psc0_res[] = {
+        [0] = {
+                .start  = PSC0_PHYS_ADDR,
+                .end    = PSC0_PHYS_ADDR + 0x000fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1200_PSC0_INT,
+                .end    = AU1200_PSC0_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DSCR_CMD0_PSC0_TX,
+                .end    = DSCR_CMD0_PSC0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DSCR_CMD0_PSC0_RX,
+                .end    = DSCR_CMD0_PSC0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1200_i2c_dev = {
+        .name           = "au1xpsc_smbus",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1200_psc0_res),
+        .resource       = au1200_psc0_res,
+};
+
+static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
+{
+        if (cs)
+                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
+        else
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
+}
+
+static struct au1550_spi_info db1200_spi_platdata = {
+        .mainclk_hz     = 50000000,     /* PSC0 clock */
+        .num_chipselect = 2,
+        .activate_cs    = db1200_spi_cs_en,
+};
+
+static u64 spi_dmamask = DMA_32BIT_MASK;
+
+static struct platform_device db1200_spi_dev = {
+        .dev    = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_32BIT_MASK,
+                .platform_data          = &db1200_spi_platdata,
+        },
+        .name           = "au1550-spi",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1200_psc0_res),
+        .resource       = au1200_psc0_res,
+};
+
+static struct resource au1200_psc1_res[] = {
+        [0] = {
+                .start  = PSC1_PHYS_ADDR,
+                .end    = PSC1_PHYS_ADDR + 0x000fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1200_PSC1_INT,
+                .end    = AU1200_PSC1_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DSCR_CMD0_PSC1_TX,
+                .end    = DSCR_CMD0_PSC1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DSCR_CMD0_PSC1_RX,
+                .end    = DSCR_CMD0_PSC1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1200_audio_dev = {
+        /* name assigned later based on switch setting */
+        .id             = 1,    /* PSC ID */
+        .num_resources  = ARRAY_SIZE(au1200_psc1_res),
+        .resource       = au1200_psc1_res,
+};
+
+static struct platform_device *db1200_devs[] __initdata = {
+        NULL,           /* PSC0, selected by S6.8 */
+        &db1200_ide_dev,
+        &db1200_eth_dev,
+        &db1200_rtc_dev,
+        &db1200_nand_dev,
+        &db1200_audio_dev,
+};
+
+static int __init db1200_dev_init(void)
+{
+        unsigned long pfc;
+        unsigned short sw;
+        int swapped;
+
+        i2c_register_board_info(0, db1200_i2c_devs,
+                                ARRAY_SIZE(db1200_i2c_devs));
+        spi_register_board_info(db1200_spi_devs,
+                                ARRAY_SIZE(db1200_i2c_devs));
+
+        /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
+         *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
+         */
+
+        /* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
+         * this pin is claimed by PSC0 (unused though, but pinmux doesn't
+         * allow to free it without crippling the SPI interface).
+         * As a result, in SPI mode, OTG simply won't work (PSC0 uses
+         * it as an input pin which is pulled high on the boards).
+         */
+        pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
+
+        /* switch off OTG VBUS supply */
+        gpio_request(215, "otg-vbus");
+        gpio_direction_output(215, 1);
+
+        printk(KERN_INFO "DB1200 device configuration:\n");
+
+        sw = bcsr_read(BCSR_SWITCHES);
+        if (sw & BCSR_SWITCHES_DIP_8) {
+                db1200_devs[0] = &db1200_i2c_dev;
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
+
+                pfc |= (2 << 17);       /* GPIO2 block owns GPIO215 */
+
+                printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
+                printk(KERN_INFO "   OTG port VBUS supply available!\n");
+        } else {
+                db1200_devs[0] = &db1200_spi_dev;
+                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
+
+                pfc |= (1 << 17);       /* PSC0 owns GPIO215 */
+
+                printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
+                printk(KERN_INFO "   OTG port VBUS supply disabled\n");
+        }
+        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
+        wmb();
+
+        /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
+         * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
+         */
+        sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
+        if (sw == BCSR_SWITCHES_DIP_8) {
+                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
+                db1200_audio_dev.name = "au1xpsc_i2s";
+                printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
+        } else {
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
+                db1200_audio_dev.name = "au1xpsc_ac97";
+                printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
+        }
+
+        /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
+        __raw_writel(PSC_SEL_CLK_SERCLK,
+                (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    DB1200_PC0_INT,
+                                    DB1200_PC0_INSERT_INT,
+                                    /*DB1200_PC0_STSCHG_INT*/0,
+                                    DB1200_PC0_EJECT_INT,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
+                                    DB1200_PC1_INT,
+                                    DB1200_PC1_INSERT_INT,
+                                    /*DB1200_PC1_STSCHG_INT*/0,
+                                    DB1200_PC1_EJECT_INT,
+                                    1);
+
+        swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
+        db1x_register_norflash(64 << 20, 2, swapped);
+
+        return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
+}
+device_initcall(db1200_dev_init);
+
+/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
+int board_au1200fb_panel(void)
+{
+        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
+}
+
+int board_au1200fb_panel_init(void)
+{
+        /* Apply power */
+        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                                BCSR_BOARD_LCDBL);
+        return 0;
+}
+
+int board_au1200fb_panel_shutdown(void)
+{
+        /* Remove power */
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                             BCSR_BOARD_LCDBL, 0);
+        return 0;
+}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
new file mode 100644
index 000000000000..379536e3abd1
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -0,0 +1,118 @@
+/*
+ * Alchemy/AMD/RMI DB1200 board setup.
+ *
+ * Licensed under the terms outlined in the file COPYING in the root of
+ * this source archive.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-db1x00/db1200.h>
+
+const char *get_system_type(void)
+{
+        return "Alchemy Db1200";
+}
+
+void __init board_setup(void)
+{
+        unsigned long freq0, clksrc, div, pfc;
+        unsigned short whoami;
+
+        bcsr_init(DB1200_BCSR_PHYS_ADDR,
+                  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
+
+        whoami = bcsr_read(BCSR_WHOAMI);
+        printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
+                "  Board-ID %d  Daughtercard ID %d\n",
+                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
+
+        /* SMBus/SPI on PSC0, Audio on PSC1 */
+        pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
+        pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
+        pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
+        pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
+        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
+        wmb();
+
+        /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
+         * CPU clock; all other clock generators off/unused.
+         */
+        div = (get_au1x00_speed() + 25000000) / 50000000;
+        if (div & 1)
+                div++;
+        div = ((div >> 1) - 1) & 0xff;
+
+        freq0 = div << SYS_FC_FRDIV0_BIT;
+        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
+        wmb();
+        freq0 |= SYS_FC_FE0;    /* enable F0 */
+        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
+        wmb();
+
+        /* psc0_intclk comes 1:1 from F0 */
+        clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
+        __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
+        wmb();
+}
+
+/* use the hexleds to count the number of times the cpu has entered
+ * wait, the dots to indicate whether the CPU is currently idle or
+ * active (dots off = sleeping, dots on = working) for cases where
+ * the number doesn't change for a long(er) period of time.
+ */
+static void db1200_wait(void)
+{
+        __asm__("       .set    push                    \n"
+                "       .set    mips3                   \n"
+                "       .set    noreorder               \n"
+                "       cache   0x14, 0(%0)             \n"
+                "       cache   0x14, 32(%0)            \n"
+                "       cache   0x14, 64(%0)            \n"
+                /* dots off: we're about to call wait */
+                "       lui     $26, 0xb980             \n"
+                "       ori     $27, $0, 3              \n"
+                "       sb      $27, 0x18($26)          \n"
+                "       sync                            \n"
+                "       nop                             \n"
+                "       wait                            \n"
+                "       nop                             \n"
+                "       nop                             \n"
+                "       nop                             \n"
+                "       nop                             \n"
+                "       nop                             \n"
+                /* dots on: there's work to do, increment cntr */
+                "       lui     $26, 0xb980             \n"
+                "       sb      $0, 0x18($26)           \n"
+                "       lui     $26, 0xb9c0             \n"
+                "       lb      $27, 0($26)             \n"
+                "       addiu   $27, $27, 1             \n"
+                "       sb      $27, 0($26)             \n"
+                "       sync                            \n"
+                "       .set    pop                     \n"
+                : : "r" (db1200_wait));
+}
+
+static int __init db1200_arch_init(void)
+{
+        /* GPIO7 is low-level triggered CPLD cascade */
+        set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+        bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
+
+        /* do not autoenable these: CPLD has broken edge int handling,
+         * and the CD handler setup requires manual enabling to work
+         * around that.
+         */
+        irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
+        irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
+
+        if (cpu_wait)
+                cpu_wait = db1200_wait;
+
+        return 0;
+}
+arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
index 432241ab8677..613c0c0c8be9 100644
--- a/arch/mips/alchemy/devboards/db1x00/Makefile
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -5,4 +5,4 @@
 # Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
 #
 
-obj-y := board_setup.o irqmap.o
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index de30d8ea7176..50c9bef99daa 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -29,59 +29,139 @@
 
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
 
 #include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_eth.h>
 #include <asm/mach-db1x00/db1x00.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/reboot.h>
 
 #include <prom.h>
 
+#ifdef CONFIG_MIPS_DB1500
+char irq_tab_alchemy[][5] __initdata = {
+        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371   */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
+};
+
+#endif
 
-static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
+
+#ifdef CONFIG_MIPS_DB1550
+char irq_tab_alchemy[][5] __initdata = {
+        [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
+        [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
+        [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
+};
+#endif
+
+
+#ifdef CONFIG_MIPS_BOSPORUS
+char irq_tab_alchemy[][5] __initdata = {
+        [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI  */
+        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741   */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
+};
+
+/*
+ * Micrel/Kendin 5 port switch attached to MAC0,
+ * MAC0 is associated with PHY address 5 (== WAN port)
+ * MAC1 is not associated with any PHY, since it's connected directly
+ * to the switch.
+ * no interrupts are used
+ */
+static struct au1000_eth_platform_data eth0_pdata = {
+        .phy_static_config      = 1,
+        .phy_addr               = 5,
+};
+
+static void bosporus_power_off(void)
+{
+        printk(KERN_INFO "It's now safe to turn off power\n");
+        while (1)
+                asm volatile (".set mips3 ; wait ; .set mips0");
+}
 
 const char *get_system_type(void)
 {
-#ifdef CONFIG_MIPS_BOSPORUS
         return "Alchemy Bosporus Gateway Reference";
-#else
-        return "Alchemy Db1x00";
+}
 #endif
+
+
+#ifdef CONFIG_MIPS_MIRAGE
+char irq_tab_alchemy[][5] __initdata = {
+        [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
+        [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
+};
+
+static void mirage_power_off(void)
+{
+        alchemy_gpio_direction_output(210, 1);
+}
+
+const char *get_system_type(void)
+{
+        return "Alchemy Mirage";
+}
+#endif
+
+
+#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
+static void mips_softreset(void)
+{
+        asm volatile ("jr\t%0" : : "r"(0xbfc00000));
 }
 
-void board_reset(void)
+#else
+
+const char *get_system_type(void)
 {
-        /* Hit BCSR.SW_RESET[RESET] */
-        bcsr->swreset = 0x0000;
+        return "Alchemy Db1x00";
 }
+#endif
+
 
 void __init board_setup(void)
 {
-        u32 pin_func = 0;
-        char *argptr;
-
-        argptr = prom_getcmdline();
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
+        unsigned long bcsr1, bcsr2;
+        u32 pin_func;
+
+        bcsr1 = DB1000_BCSR_PHYS_ADDR;
+        bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
+
+        pin_func = 0;
+
+#ifdef CONFIG_MIPS_DB1000
+        printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1500
+        printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
 #endif
+#ifdef CONFIG_MIPS_DB1100
+        printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
+#endif
+#ifdef CONFIG_MIPS_BOSPORUS
+        au1xxx_override_eth_cfg(0, &eth0_pdata);
 
-#ifdef CONFIG_FB_AU1100
-        argptr = strstr(argptr, "video=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                /* default panel */
-                /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
-        }
+        printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
 #endif
+#ifdef CONFIG_MIPS_MIRAGE
+        printk(KERN_INFO "AMD Alchemy Mirage Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1550
+        printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
 
-#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
-        /* au1000 does not support vra, au1500 and au1100 do */
-        strcat(argptr, " au1000_audio=vra");
-        argptr = prom_getcmdline();
+        bcsr1 = DB1550_BCSR_PHYS_ADDR;
+        bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
 #endif
 
+        /* initialize board register space */
+        bcsr_init(bcsr1, bcsr2);
+
         /* Not valid for Au1550 */
 #if defined(CONFIG_IRDA) && \
    (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
@@ -89,11 +169,10 @@ void __init board_setup(void)
         pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
         au_writel(pin_func, SYS_PINFUNC);
         /* Power off until the driver is in use */
-        bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK;
-        bcsr->resets |=  BCSR_RESETS_IRDA_MODE_OFF;
-        au_sync();
+        bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
+                                BCSR_RESETS_IRDA_MODE_OFF);
 #endif
-        bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */
+        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
 
         /* Enable GPIO[31:0] inputs */
         alchemy_gpio1_input_enable();
@@ -120,26 +199,53 @@ void __init board_setup(void)
          * be part of the audio driver.
          */
         alchemy_gpio_direction_output(209, 1);
-#endif
-
-        au_sync();
 
-#ifdef CONFIG_MIPS_DB1000
-        printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1500
-        printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1100
-        printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
+        pm_power_off = mirage_power_off;
+        _machine_halt = mirage_power_off;
+        _machine_restart = (void(*)(char *))mips_softreset;
 #endif
+
 #ifdef CONFIG_MIPS_BOSPORUS
-        printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
+        pm_power_off = bosporus_power_off;
+        _machine_halt = bosporus_power_off;
+        _machine_restart = (void(*)(char *))mips_softreset;
 #endif
-#ifdef CONFIG_MIPS_MIRAGE
-        printk(KERN_INFO "AMD Alchemy Mirage Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1550
-        printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
+        au_sync();
+}
+
+static int __init db1x00_init_irq(void)
+{
+#if defined(CONFIG_MIPS_MIRAGE)
+        set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
+#elif defined(CONFIG_MIPS_DB1550)
+        set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
+        set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
+        set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
+        set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
+        set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#elif defined(CONFIG_MIPS_DB1500)
+        set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#elif defined(CONFIG_MIPS_DB1100)
+        set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#elif defined(CONFIG_MIPS_DB1000)
+        set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 #endif
+        return 0;
 }
+arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/irqmap.c b/arch/mips/alchemy/devboards/db1x00/irqmap.c
deleted file mode 100644
index 0b09025087c6..000000000000
--- a/arch/mips/alchemy/devboards/db1x00/irqmap.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Au1xxx irq map table
- *
- * Copyright 2003 Embedded Edge, LLC
- *              dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-#ifdef CONFIG_MIPS_DB1500
-char irq_tab_alchemy[][5] __initdata = {
-        [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT371   */
-        [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
-};
-#endif
-
-#ifdef CONFIG_MIPS_BOSPORUS
-char irq_tab_alchemy[][5] __initdata = {
-        [11] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 11 - miniPCI  */
-        [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - SN1741   */
-        [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
-};
-#endif
-
-#ifdef CONFIG_MIPS_MIRAGE
-char irq_tab_alchemy[][5] __initdata = {
-        [11] = { -1, INTD, INTX, INTX, INTX }, /* IDSEL 11 - SMI VGX */
-        [12] = { -1, INTX, INTX, INTC, INTX }, /* IDSEL 12 - PNX1300 */
-        [13] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 13 - miniPCI */
-};
-#endif
-
-#ifdef CONFIG_MIPS_DB1550
-char irq_tab_alchemy[][5] __initdata = {
-        [11] = { -1, INTC, INTX, INTX, INTX }, /* IDSEL 11 - on-board HPT371 */
-        [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
-        [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
-};
-#endif
-
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-
-#ifndef CONFIG_MIPS_MIRAGE
-#ifdef CONFIG_MIPS_DB1550
-        { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
-        { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
-#else
-        { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */
-        { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */
-        { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
-
-        { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */
-        { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */
-        { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
-#endif
-#else
-        { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */
-#endif
-
-};
-
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
-}
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
new file mode 100644
index 000000000000..978d5ab3d678
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -0,0 +1,118 @@
+/*
+ * DBAu1xxx board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include "../platform.h"
+
+/* DB1xxx PCMCIA interrupt sources:
+ * CD0/1        GPIO0/3
+ * STSCHG0/1    GPIO1/4
+ * CARD0/1      GPIO2/5
+ * Db1550:      0/1, 21/22, 3/5
+ */
+
+#define DB1XXX_HAS_PCMCIA
+#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
+
+#if defined(CONFIG_MIPS_DB1000)
+#define DB1XXX_PCMCIA_CD0       AU1000_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1000_GPIO1_INT
+#define DB1XXX_PCMCIA_CARD0     AU1000_GPIO2_INT
+#define DB1XXX_PCMCIA_CD1       AU1000_GPIO3_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1000_GPIO4_INT
+#define DB1XXX_PCMCIA_CARD1     AU1000_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#elif defined(CONFIG_MIPS_DB1100)
+#define DB1XXX_PCMCIA_CD0       AU1100_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1100_GPIO1_INT
+#define DB1XXX_PCMCIA_CARD0     AU1100_GPIO2_INT
+#define DB1XXX_PCMCIA_CD1       AU1100_GPIO3_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1100_GPIO4_INT
+#define DB1XXX_PCMCIA_CARD1     AU1100_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#elif defined(CONFIG_MIPS_DB1500)
+#define DB1XXX_PCMCIA_CD0       AU1500_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1500_GPIO1_INT
+#define DB1XXX_PCMCIA_CARD0     AU1500_GPIO2_INT
+#define DB1XXX_PCMCIA_CD1       AU1500_GPIO3_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1500_GPIO4_INT
+#define DB1XXX_PCMCIA_CARD1     AU1500_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#elif defined(CONFIG_MIPS_DB1550)
+#define DB1XXX_PCMCIA_CD0       AU1550_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1550_GPIO21_INT
+#define DB1XXX_PCMCIA_CARD0     AU1550_GPIO3_INT
+#define DB1XXX_PCMCIA_CD1       AU1550_GPIO1_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1550_GPIO22_INT
+#define DB1XXX_PCMCIA_CARD1     AU1550_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x08000000 /* 128MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#else
+/* other board: no PCMCIA */
+#undef DB1XXX_HAS_PCMCIA
+#undef F_SWAPPED
+#define F_SWAPPED 0
+#if defined(CONFIG_MIPS_BOSPORUS)
+#define BOARD_FLASH_SIZE        0x01000000 /* 16MB */
+#define BOARD_FLASH_WIDTH       2 /* 16-bits */
+#elif defined(CONFIG_MIPS_MIRAGE)
+#define BOARD_FLASH_SIZE        0x04000000 /* 64MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#endif
+#endif
+
+static int __init db1xxx_dev_init(void)
+{
+#ifdef DB1XXX_HAS_PCMCIA
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    DB1XXX_PCMCIA_CARD0,
+                                    DB1XXX_PCMCIA_CD0,
+                                    /*DB1XXX_PCMCIA_STSCHG0*/0,
+                                    0,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
+                                    DB1XXX_PCMCIA_CARD1,
+                                    DB1XXX_PCMCIA_CD1,
+                                    /*DB1XXX_PCMCIA_STSCHG1*/0,
+                                    0,
+                                    1);
+#endif
+        db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
+        return 0;
+}
+device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index cd273545e810..b5311d8a29ab 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -31,11 +31,7 @@
 #include <asm/mach-pb1x00/pb1000.h>
 #include <prom.h>
 
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-        { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 },
-};
-
+#include "../platform.h"
 
 const char *get_system_type(void)
 {
@@ -46,25 +42,14 @@ void board_reset(void)
 {
 }
 
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
-}
-
 void __init board_setup(void)
 {
         u32 pin_func, static_cfg0;
         u32 sys_freqctrl, sys_clksrc;
         u32 prid = read_c0_prid();
 
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        char *argptr = prom_getcmdline();
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
+        sys_freqctrl = 0;
+        sys_clksrc = 0;
 
         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
         au_writel(8, SYS_AUXPLL);
@@ -193,3 +178,16 @@ void __init board_setup(void)
                 break;
         }
 }
+
+static int __init pb1000_init_irq(void)
+{
+        set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
+        return 0;
+}
+arch_initcall(pb1000_init_irq);
+
+static int __init pb1000_device_init(void)
+{
+        return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
+}
+device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
index c586dd7e91dc..7e3756c83fe5 100644
--- a/arch/mips/alchemy/devboards/pb1100/Makefile
+++ b/arch/mips/alchemy/devboards/pb1100/Makefile
@@ -5,4 +5,4 @@
 # Makefile for the Alchemy Semiconductor Pb1100 board.
 #
 
-obj-y := board_setup.o
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 61263081ef58..c7b4caa81a35 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -29,19 +29,11 @@
 #include <linux/interrupt.h>
 
 #include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-pb1x00/pb1100.h>
+#include <asm/mach-db1x00/bcsr.h>
 
 #include <prom.h>
 
 
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-        { AU1000_GPIO_9,  IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */
-        { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */
-        { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */
-        { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */
-};
-
-
 const char *get_system_type(void)
 {
         return "Alchemy Pb1100";
@@ -49,43 +41,15 @@ const char *get_system_type(void)
 
 void board_reset(void)
 {
-        /* Hit BCSR.RST_VDDI[SOFT_RESET] */
-        au_writel(0x00000000, PB1100_RST_VDDI);
-}
-
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
+        bcsr_write(BCSR_SYSTEM, 0);
 }
 
 void __init board_setup(void)
 {
         volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
-        char *argptr;
-
-        argptr = prom_getcmdline();
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
-
-#ifdef CONFIG_FB_AU1100
-        argptr = strstr(argptr, "video=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                /* default panel */
-                /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
-        }
-#endif
 
-#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
-        /* au1000 does not support vra, au1500 and au1100 do */
-        strcat(argptr, " au1000_audio=vra");
-        argptr = prom_getcmdline();
-#endif
+        bcsr_init(DB1000_BCSR_PHYS_ADDR,
+                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
 
         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
         au_writel(8, SYS_AUXPLL);
@@ -155,3 +119,14 @@ void __init board_setup(void)
                 au_sync();
         }
 }
+
+static int __init pb1100_init_irq(void)
+{
+        set_irq_type(AU1100_GPIO9_INT,  IRQF_TRIGGER_LOW); /* PCCD# */
+        set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
+        set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
+        set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
+
+        return 0;
+}
+arch_initcall(pb1100_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
new file mode 100644
index 000000000000..2c8dc29759fd
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -0,0 +1,50 @@
+/*
+ * Pb1100 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int __init pb1100_dev_init(void)
+{
+        int swapped;
+
+        /* PCMCIA. single socket, identical to Pb1500 */
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    AU1100_GPIO11_INT,   /* card */
+                                    AU1100_GPIO9_INT,    /* insert */
+                                    /*AU1100_GPIO10_INT*/0, /* stschg */
+                                    0,                   /* eject */
+                                    0);                  /* id */
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+
+        return 0;
+}
+device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index c8c3a99fb68a..2ea9b02ef09f 100644
--- a/arch/mips/alchemy/devboards/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -2,6 +2,6 @@
 # Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
 #
 
-obj-y := board_setup.o irqmap.o platform.o
+obj-y := board_setup.o platform.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 94e6b7e7753d..3184063f8042 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -25,11 +25,23 @@
  */
 
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/sched.h>
 
-#include <prom.h>
-#include <au1xxx.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/mach-pb1x00/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/mach-db1x00/db1200.h>
+#define PB1200_INT_BEGIN DB1200_INT_BEGIN
+#define PB1200_INT_END DB1200_INT_END
+#endif
 
+#include <prom.h>
 
 const char *get_system_type(void)
 {
@@ -38,25 +50,15 @@ const char *get_system_type(void)
 
 void board_reset(void)
 {
-        bcsr->resets = 0;
-        bcsr->system = 0;
+        bcsr_write(BCSR_RESETS, 0);
+        bcsr_write(BCSR_SYSTEM, 0);
 }
 
 void __init board_setup(void)
 {
-        char *argptr;
-
-        argptr = prom_getcmdline();
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
-#ifdef CONFIG_FB_AU1200
-        strcat(argptr, " video=au1200fb:panel:bs");
-#endif
+        printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
+        bcsr_init(PB1200_BCSR_PHYS_ADDR,
+                  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
 
 #if 0
         {
@@ -82,7 +84,7 @@ void __init board_setup(void)
                 u32 pin_func;
 
                 /* Select SMBus in CPLD */
-                bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
 
                 pin_func = au_readl(SYS_PINFUNC);
                 au_sync();
@@ -116,38 +118,54 @@ void __init board_setup(void)
 
         /*
          * The Pb1200 development board uses external MUX for PSC0 to
-         * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
+         * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
          */
 #ifdef CONFIG_I2C_AU1550
-        bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
+        bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
 #endif
         au_sync();
+}
 
-#ifdef CONFIG_MIPS_PB1200
-        printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
-#endif
-#ifdef CONFIG_MIPS_DB1200
-        printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
-#endif
+static int __init pb1200_init_irq(void)
+{
+        /* We have a problem with CPLD rev 3. */
+        if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
+                printk(KERN_ERR "updated to latest revision. This software will\n");
+                printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                panic("Game over.  Your score is 0.");
+        }
+
+        set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+        bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
+
+        return 0;
 }
+arch_initcall(pb1200_init_irq);
+
 
 int board_au1200fb_panel(void)
 {
-        BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-        int p;
-
-        p = bcsr->switches;
-        p >>= 8;
-        p &= 0x0F;
-        return p;
+        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
 }
 
 int board_au1200fb_panel_init(void)
 {
         /* Apply power */
-        BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-
-        bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
+        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                                BCSR_BOARD_LCDBL);
         /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
         return 0;
 }
@@ -155,10 +173,8 @@ int board_au1200fb_panel_init(void)
 int board_au1200fb_panel_shutdown(void)
 {
         /* Remove power */
-        BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-
-        bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
-                         BCSR_BOARD_LCDBL);
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                             BCSR_BOARD_LCDBL, 0);
         /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
         return 0;
 }
diff --git a/arch/mips/alchemy/devboards/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c
deleted file mode 100644
index fe47498da280..000000000000
--- a/arch/mips/alchemy/devboards/pb1200/irqmap.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Au1xxx irq map table
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach-au1x00/au1000.h>
-
-#ifdef CONFIG_MIPS_PB1200
-#include <asm/mach-pb1x00/pb1200.h>
-#endif
-
-#ifdef CONFIG_MIPS_DB1200
-#include <asm/mach-db1x00/db1200.h>
-#define PB1200_INT_BEGIN DB1200_INT_BEGIN
-#define PB1200_INT_END DB1200_INT_END
-#endif
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-        /* This is external interrupt cascade */
-        { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 },
-};
-
-
-/*
- * Support for External interrupts on the Pb1200 Development platform.
- */
-
-static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
-{
-        unsigned short bisr = bcsr->int_status;
-
-        for ( ; bisr; bisr &= bisr - 1)
-                generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
-}
-
-/* NOTE: both the enable and mask bits must be cleared, otherwise the
- * CPLD generates tons of spurious interrupts (at least on the DB1200).
- */
-static void pb1200_mask_irq(unsigned int irq_nr)
-{
-        bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
-        bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
-        au_sync();
-}
-
-static void pb1200_maskack_irq(unsigned int irq_nr)
-{
-        bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
-        bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
-        bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN);    /* ack */
-        au_sync();
-}
-
-static void pb1200_unmask_irq(unsigned int irq_nr)
-{
-        bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
-        bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
-        au_sync();
-}
-
-static struct irq_chip pb1200_cpld_irq_type = {
-#ifdef CONFIG_MIPS_PB1200
-        .name = "Pb1200 Ext",
-#endif
-#ifdef CONFIG_MIPS_DB1200
-        .name = "Db1200 Ext",
-#endif
-        .mask           = pb1200_mask_irq,
-        .mask_ack       = pb1200_maskack_irq,
-        .unmask         = pb1200_unmask_irq,
-};
-
-void __init board_init_irq(void)
-{
-        unsigned int irq;
-
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
-
-#ifdef CONFIG_MIPS_PB1200
-        /* We have a problem with CPLD rev 3. */
-        if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
-                printk(KERN_ERR "updated to latest revision. This software will\n");
-                printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                printk(KERN_ERR "WARNING!!!\n");
-                panic("Game over.  Your score is 0.");
-        }
-#endif
-        /* mask & disable & ack all */
-        bcsr->intclr_mask = 0xffff;
-        bcsr->intclr = 0xffff;
-        bcsr->int_status = 0xffff;
-        au_sync();
-
-        for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++)
-                set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
-                                         handle_level_irq, "level");
-
-        set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler);
-}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index b93dff4a6789..3ef2dceeb796 100644
--- a/arch/mips/alchemy/devboards/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -26,27 +26,30 @@
 
 #include <asm/mach-au1x00/au1xxx.h>
 #include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
 
 static int mmc_activity;
 
 static void pb1200mmc0_set_power(void *mmc_host, int state)
 {
         if (state)
-                bcsr->board |= BCSR_BOARD_SD0PWR;
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
         else
-                bcsr->board &= ~BCSR_BOARD_SD0PWR;
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
 
-        au_sync_delay(1);
+        msleep(1);
 }
 
 static int pb1200mmc0_card_readonly(void *mmc_host)
 {
-        return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0;
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
 }
 
 static int pb1200mmc0_card_inserted(void *mmc_host)
 {
-        return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0;
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
 }
 
 static void pb1200_mmcled_set(struct led_classdev *led,
@@ -54,10 +57,10 @@ static void pb1200_mmcled_set(struct led_classdev *led,
 {
         if (brightness != LED_OFF) {
                 if (++mmc_activity == 1)
-                        bcsr->disk_leds &= ~(1 << 8);
+                        bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
         } else {
                 if (--mmc_activity == 0)
-                        bcsr->disk_leds |= (1 << 8);
+                        bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
         }
 }
 
@@ -65,27 +68,25 @@ static struct led_classdev pb1200mmc_led = {
         .brightness_set = pb1200_mmcled_set,
 };
 
-#ifndef CONFIG_MIPS_DB1200
 static void pb1200mmc1_set_power(void *mmc_host, int state)
 {
         if (state)
-                bcsr->board |= BCSR_BOARD_SD1PWR;
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
         else
-                bcsr->board &= ~BCSR_BOARD_SD1PWR;
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
 
-        au_sync_delay(1);
+        msleep(1);
 }
 
 static int pb1200mmc1_card_readonly(void *mmc_host)
 {
-        return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0;
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
 }
 
 static int pb1200mmc1_card_inserted(void *mmc_host)
 {
-        return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0;
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
 }
-#endif
 
 const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
         [0] = {
@@ -95,7 +96,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
                 .cd_setup       = NULL,         /* use poll-timer in driver */
                 .led            = &pb1200mmc_led,
         },
-#ifndef CONFIG_MIPS_DB1200
         [1] = {
                 .set_power      = pb1200mmc1_set_power,
                 .card_inserted  = pb1200mmc1_card_inserted,
@@ -103,7 +103,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
                 .cd_setup       = NULL,         /* use poll-timer in driver */
                 .led            = &pb1200mmc_led,
         },
-#endif
 };
 
 static struct resource ide_resources[] = {
@@ -169,8 +168,36 @@ static struct platform_device *board_platform_devices[] __initdata = {
 
 static int __init board_register_devices(void)
 {
+        int swapped;
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    PB1200_PC0_INT,
+                                    PB1200_PC0_INSERT_INT,
+                                    /*PB1200_PC0_STSCHG_INT*/0,
+                                    PB1200_PC0_EJECT_INT,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
+                                    PB1200_PC1_INT,
+                                    PB1200_PC1_INSERT_INT,
+                                    /*PB1200_PC1_STSCHG_INT*/0,
+                                    PB1200_PC1_EJECT_INT,
+                                    1);
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1200_SWAPBOOT;
+        db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
+
         return platform_add_devices(board_platform_devices,
                                     ARRAY_SIZE(board_platform_devices));
 }
-
-arch_initcall(board_register_devices);
+device_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
index 173b419a7479..e83b151b5b63 100644
--- a/arch/mips/alchemy/devboards/pb1500/Makefile
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -5,4 +5,4 @@
 # Makefile for the Alchemy Semiconductor Pb1500 board.
 #
 
-obj-y := board_setup.o
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index d7a56569e7ed..fa9770ac358a 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -29,22 +29,14 @@
 #include <linux/interrupt.h>
 
 #include <asm/mach-au1x00/au1000.h>
-#include <asm/mach-pb1x00/pb1500.h>
+#include <asm/mach-db1x00/bcsr.h>
 
 #include <prom.h>
 
 
 char irq_tab_alchemy[][5] __initdata = {
-        [12] = { -1, INTA, INTX, INTX, INTX },   /* IDSEL 12 - HPT370   */
-        [13] = { -1, INTA, INTB, INTC, INTD },   /* IDSEL 13 - PCI slot */
-};
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-        { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
-        { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
+        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff },   /* IDSEL 12 - HPT370        */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD },   /* IDSEL 13 - PCI slot */
 };
 
 
@@ -55,35 +47,16 @@ const char *get_system_type(void)
 
 void board_reset(void)
 {
-        /* Hit BCSR.RST_VDDI[SOFT_RESET] */
-        au_writel(0x00000000, PB1500_RST_VDDI);
-}
-
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
+        bcsr_write(BCSR_SYSTEM, 0);
 }
 
 void __init board_setup(void)
 {
         u32 pin_func;
         u32 sys_freqctrl, sys_clksrc;
-        char *argptr;
-
-        argptr = prom_getcmdline();
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
 
-#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
-        /* au1000 does not support vra, au1500 and au1100 do */
-        strcat(argptr, " au1000_audio=vra");
-        argptr = prom_getcmdline();
-#endif
+        bcsr_init(DB1000_BCSR_PHYS_ADDR,
+                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
 
         sys_clksrc = sys_freqctrl = pin_func = 0;
         /* Set AUX clock to 12 MHz * 8 = 96 MHz */
@@ -163,3 +136,18 @@ void __init board_setup(void)
                 au_sync();
         }
 }
+
+static int __init pb1500_init_irq(void)
+{
+        set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
+        set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
+        set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
+        set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+
+        return 0;
+}
+arch_initcall(pb1500_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
new file mode 100644
index 000000000000..d443bc7aa76e
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -0,0 +1,49 @@
+/*
+ * Pb1500 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int __init pb1500_dev_init(void)
+{
+        int swapped;
+
+        /* PCMCIA. single socket, identical to Pb1500 */
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    AU1500_GPIO11_INT,   /* card */
+                                    AU1500_GPIO9_INT,    /* insert */
+                                    /*AU1500_GPIO10_INT*/0, /* stschg */
+                                    0,                   /* eject */
+                                    0);                  /* id */
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+
+        return 0;
+}
+device_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
index cff95bcdb2ca..9661b6ec5dd3 100644
--- a/arch/mips/alchemy/devboards/pb1550/Makefile
+++ b/arch/mips/alchemy/devboards/pb1550/Makefile
@@ -5,4 +5,4 @@
 # Makefile for the Alchemy Semiconductor Pb1550 board.
 #
 
-obj-y := board_setup.o
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index b6e9e7d247a3..1e8fb3ddd726 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -32,18 +32,15 @@
 
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-pb1x00/pb1550.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-au1x00/gpio.h>
 
 #include <prom.h>
 
 
 char irq_tab_alchemy[][5] __initdata = {
-        [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left)  */
-        [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
-};
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-        { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
-        { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
+        [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left)  */
+        [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
 };
 
 const char *get_system_type(void)
@@ -53,28 +50,17 @@ const char *get_system_type(void)
 
 void board_reset(void)
 {
-        /* Hit BCSR.SYSTEM[RESET] */
-        au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
-}
-
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
+        bcsr_write(BCSR_SYSTEM, 0);
 }
 
 void __init board_setup(void)
 {
         u32 pin_func;
 
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        char *argptr;
-        argptr = prom_getcmdline();
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
+        bcsr_init(PB1550_BCSR_PHYS_ADDR,
+                  PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
+
+        alchemy_gpio2_enable();
 
         /*
          * Enable PSC1 SYNC for AC'97.  Normaly done in audio driver,
@@ -85,8 +71,21 @@ void __init board_setup(void)
         pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
         au_writel(pin_func, SYS_PINFUNC);
 
-        au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
-        au_sync();
+        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
 
         printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
 }
+
+static int __init pb1550_init_irq(void)
+{
+        set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
+
+        /* enable both PCMCIA card irqs in the shared line */
+        alchemy_gpio2_enable_int(201);
+        alchemy_gpio2_enable_int(202);
+
+        return 0;
+}
+arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
new file mode 100644
index 000000000000..d7150d0f49c0
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -0,0 +1,69 @@
+/*
+ * Pb1550 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-pb1x00/pb1550.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int __init pb1550_dev_init(void)
+{
+        int swapped;
+
+        /* Pb1550, like all others, also has statuschange irqs; however they're
+        * wired up on one of the Au1550's shared GPIO201_205 line, which also
+        * services the PCMCIA card interrupts.  So we ignore statuschange and
+        * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
+        * drivers are used to shared irqs and b) statuschange isn't really use-
+        * ful anyway.
+        */
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    AU1550_GPIO201_205_INT,
+                                    AU1550_GPIO0_INT,
+                                    0,
+                                    0,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
+                                    AU1550_GPIO201_205_INT,
+                                    AU1550_GPIO1_INT,
+                                    0,
+                                    0,
+                                    1);
+
+        swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
+        db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
+
+        return 0;
+}
+device_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/platform.c b/arch/mips/alchemy/devboards/platform.c
new file mode 100644
index 000000000000..49a4b3244d8e
--- /dev/null
+++ b/arch/mips/alchemy/devboards/platform.c
@@ -0,0 +1,222 @@
+/*
+ * devoard misc stuff.
+ */
+
+#include <linux/init.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/map.h>
+#include <linux/mtd/physmap.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+static void db1x_power_off(void)
+{
+        bcsr_write(BCSR_RESETS, 0);
+        bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET);
+}
+
+static void db1x_reset(char *c)
+{
+        bcsr_write(BCSR_RESETS, 0);
+        bcsr_write(BCSR_SYSTEM, 0);
+}
+
+static int __init db1x_poweroff_setup(void)
+{
+        if (!pm_power_off)
+                pm_power_off = db1x_power_off;
+        if (!_machine_halt)
+                _machine_halt = db1x_power_off;
+        if (!_machine_restart)
+                _machine_restart = db1x_reset;
+
+        return 0;
+}
+late_initcall(db1x_poweroff_setup);
+
+/* register a pcmcia socket */
+int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
+                                       phys_addr_t pcmcia_attr_end,
+                                       phys_addr_t pcmcia_mem_start,
+                                       phys_addr_t pcmcia_mem_end,
+                                       phys_addr_t pcmcia_io_start,
+                                       phys_addr_t pcmcia_io_end,
+                                       int card_irq,
+                                       int cd_irq,
+                                       int stschg_irq,
+                                       int eject_irq,
+                                       int id)
+{
+        int cnt, i, ret;
+        struct resource *sr;
+        struct platform_device *pd;
+
+        cnt = 5;
+        if (eject_irq)
+                cnt++;
+        if (stschg_irq)
+                cnt++;
+
+        sr = kzalloc(sizeof(struct resource) * cnt, GFP_KERNEL);
+        if (!sr)
+                return -ENOMEM;
+
+        pd = platform_device_alloc("db1xxx_pcmcia", id);
+        if (!pd) {
+                ret = -ENOMEM;
+                goto out;
+        }
+
+        sr[0].name      = "pcmcia-attr";
+        sr[0].flags     = IORESOURCE_MEM;
+        sr[0].start     = pcmcia_attr_start;
+        sr[0].end       = pcmcia_attr_end;
+
+        sr[1].name      = "pcmcia-mem";
+        sr[1].flags     = IORESOURCE_MEM;
+        sr[1].start     = pcmcia_mem_start;
+        sr[1].end       = pcmcia_mem_end;
+
+        sr[2].name      = "pcmcia-io";
+        sr[2].flags     = IORESOURCE_MEM;
+        sr[2].start     = pcmcia_io_start;
+        sr[2].end       = pcmcia_io_end;
+
+        sr[3].name      = "insert";
+        sr[3].flags     = IORESOURCE_IRQ;
+        sr[3].start = sr[3].end = cd_irq;
+
+        sr[4].name      = "card";
+        sr[4].flags     = IORESOURCE_IRQ;
+        sr[4].start = sr[4].end = card_irq;
+
+        i = 5;
+        if (stschg_irq) {
+                sr[i].name      = "stschg";
+                sr[i].flags     = IORESOURCE_IRQ;
+                sr[i].start = sr[i].end = stschg_irq;
+                i++;
+        }
+        if (eject_irq) {
+                sr[i].name      = "eject";
+                sr[i].flags     = IORESOURCE_IRQ;
+                sr[i].start = sr[i].end = eject_irq;
+        }
+
+        pd->resource = sr;
+        pd->num_resources = cnt;
+
+        ret = platform_device_add(pd);
+        if (!ret)
+                return 0;
+
+        platform_device_put(pd);
+out:
+        kfree(sr);
+        return ret;
+}
+
+#define YAMON_SIZE      0x00100000
+#define YAMON_ENV_SIZE  0x00040000
+
+int __init db1x_register_norflash(unsigned long size, int width,
+                                  int swapped)
+{
+        struct physmap_flash_data *pfd;
+        struct platform_device *pd;
+        struct mtd_partition *parts;
+        struct resource *res;
+        int ret, i;
+
+        if (size < (8 * 1024 * 1024))
+                return -EINVAL;
+
+        ret = -ENOMEM;
+        parts = kzalloc(sizeof(struct mtd_partition) * 5, GFP_KERNEL);
+        if (!parts)
+                goto out;
+
+        res = kzalloc(sizeof(struct resource), GFP_KERNEL);
+        if (!res)
+                goto out1;
+
+        pfd = kzalloc(sizeof(struct physmap_flash_data), GFP_KERNEL);
+        if (!pfd)
+                goto out2;
+
+        pd = platform_device_alloc("physmap-flash", 0);
+        if (!pd)
+                goto out3;
+
+        /* NOR flash ends at 0x20000000, regardless of size */
+        res->start = 0x20000000 - size;
+        res->end = 0x20000000 - 1;
+        res->flags = IORESOURCE_MEM;
+
+        /* partition setup.  Most Develboards have a switch which allows
+         * to swap the physical locations of the 2 NOR flash banks.
+         */
+        i = 0;
+        if (!swapped) {
+                /* first NOR chip */
+                parts[i].offset = 0;
+                parts[i].name = "User FS";
+                parts[i].size = size / 2;
+                i++;
+        }
+
+        parts[i].offset = MTDPART_OFS_APPEND;
+        parts[i].name = "User FS 2";
+        parts[i].size = (size / 2) - (0x20000000 - 0x1fc00000);
+        i++;
+
+        parts[i].offset = MTDPART_OFS_APPEND;
+        parts[i].name = "YAMON";
+        parts[i].size = YAMON_SIZE;
+        parts[i].mask_flags = MTD_WRITEABLE;
+        i++;
+
+        parts[i].offset = MTDPART_OFS_APPEND;
+        parts[i].name = "raw kernel";
+        parts[i].size = 0x00400000 - YAMON_SIZE - YAMON_ENV_SIZE;
+        i++;
+
+        parts[i].offset = MTDPART_OFS_APPEND;
+        parts[i].name = "YAMON Env";
+        parts[i].size = YAMON_ENV_SIZE;
+        parts[i].mask_flags = MTD_WRITEABLE;
+        i++;
+
+        if (swapped) {
+                parts[i].offset = MTDPART_OFS_APPEND;
+                parts[i].name = "User FS";
+                parts[i].size = size / 2;
+                i++;
+        }
+
+        pfd->width = width;
+        pfd->parts = parts;
+        pfd->nr_parts = 5;
+
+        pd->dev.platform_data = pfd;
+        pd->resource = res;
+        pd->num_resources = 1;
+
+        ret = platform_device_add(pd);
+        if (!ret)
+                return ret;
+
+        platform_device_put(pd);
+out3:
+        kfree(pfd);
+out2:
+        kfree(res);
+out1:
+        kfree(parts);
+out:
+        return ret;
+}
diff --git a/arch/mips/alchemy/devboards/platform.h b/arch/mips/alchemy/devboards/platform.h
new file mode 100644
index 000000000000..5ac055d2cda9
--- /dev/null
+++ b/arch/mips/alchemy/devboards/platform.h
@@ -0,0 +1,21 @@
+#ifndef _DEVBOARD_PLATFORM_H_
+#define _DEVBOARD_PLATFORM_H_
+
+#include <linux/init.h>
+
+int __init db1x_register_pcmcia_socket(phys_addr_t pcmcia_attr_start,
+                                       phys_addr_t pcmcia_attr_len,
+                                       phys_addr_t pcmcia_mem_start,
+                                       phys_addr_t pcmcia_mem_end,
+                                       phys_addr_t pcmcia_io_start,
+                                       phys_addr_t pcmcia_io_end,
+                                       int card_irq,
+                                       int cd_irq,
+                                       int stschg_irq,
+                                       int eject_irq,
+                                       int id);
+
+int __init db1x_register_norflash(unsigned long size, int width,
+                                  int swapped);
+
+#endif
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index 632f9862a0fb..4bbd3133e451 100644
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -10,6 +10,7 @@
 #include <linux/sysfs.h>
 #include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/gpio.h>
+#include <asm/mach-db1x00/bcsr.h>
 
 /*
  * Generic suspend userspace interface for Alchemy development boards.
@@ -26,6 +27,20 @@ static unsigned long db1x_pm_last_wakesrc;
 
 static int db1x_pm_enter(suspend_state_t state)
 {
+        unsigned short bcsrs[16];
+        int i, j, hasint;
+
+        /* save CPLD regs */
+        hasint = bcsr_read(BCSR_WHOAMI);
+        hasint = BCSR_WHOAMI_BOARD(hasint) >= BCSR_WHOAMI_DB1200;
+        j = (hasint) ? BCSR_MASKSET : BCSR_SYSTEM;
+
+        for (i = BCSR_STATUS; i <= j; i++)
+                bcsrs[i] = bcsr_read(i);
+
+        /* shut off hexleds */
+        bcsr_write(BCSR_HEXCLEAR, 3);
+
         /* enable GPIO based wakeup */
         alchemy_gpio1_input_enable();
 
@@ -52,6 +67,23 @@ static int db1x_pm_enter(suspend_state_t state)
         /* ...and now the sandman can come! */
         au_sleep();
 
+
+        /* restore CPLD regs */
+        for (i = BCSR_STATUS; i <= BCSR_SYSTEM; i++)
+                bcsr_write(i, bcsrs[i]);
+
+        /* restore CPLD int registers */
+        if (hasint) {
+                bcsr_write(BCSR_INTCLR, 0xffff);
+                bcsr_write(BCSR_MASKCLR, 0xffff);
+                bcsr_write(BCSR_INTSTAT, 0xffff);
+                bcsr_write(BCSR_INTSET, bcsrs[BCSR_INTSET]);
+                bcsr_write(BCSR_MASKSET, bcsrs[BCSR_MASKSET]);
+        }
+
+        /* light up hexleds */
+        bcsr_write(BCSR_HEXCLEAR, 0);
+
         return 0;
 }
 
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
index 0042bd6b1d7d..b30df5c97ad3 100644
--- a/arch/mips/alchemy/devboards/prom.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -60,3 +60,8 @@ void __init prom_init(void)
                 strict_strtoul(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
+
+void prom_putchar(unsigned char c)
+{
+    alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
index 7c67b3d33bec..4a53815b3c6c 100644
--- a/arch/mips/alchemy/mtx-1/Makefile
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -6,7 +6,7 @@
 # Makefile for 4G Systems MTX-1 board.
 #
 
-lib-y := init.o board_setup.o irqmap.o
+lib-y := init.o board_setup.o
 obj-y := platform.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 45b61c9b82b9..a9f0336e1f1f 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -30,32 +30,43 @@
 
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
 
+#include <asm/reboot.h>
 #include <asm/mach-au1x00/au1000.h>
 
 #include <prom.h>
 
+char irq_tab_alchemy[][5] __initdata = {
+        [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
+        [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
+        [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
+        [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
+        [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
+        [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
+        [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
+        [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
+};
+
 extern int (*board_pci_idsel)(unsigned int devsel, int assert);
 int mtx1_pci_idsel(unsigned int devsel, int assert);
 
-void board_reset(void)
+static void mtx1_reset(char *c)
 {
         /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
         au_writel(0x00000000, 0xAE00001C);
 }
 
-void __init board_setup(void)
+static void mtx1_power_off(void)
 {
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        char *argptr;
-        argptr = prom_getcmdline();
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
+        printk(KERN_ALERT "It's now safe to remove power\n");
+        while (1)
+                asm volatile (".set mips3 ; wait ; .set mips1");
+}
 
+void __init board_setup(void)
+{
         alchemy_gpio2_enable();
 
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
@@ -86,6 +97,10 @@ void __init board_setup(void)
         alchemy_gpio_direction_output(211, 1);  /* green on */
         alchemy_gpio_direction_output(212, 0);  /* red off */
 
+        pm_power_off = mtx1_power_off;
+        _machine_halt = mtx1_power_off;
+        _machine_restart = mtx1_reset;
+
         printk(KERN_INFO "4G Systems MTX-1 Board\n");
 }
 
@@ -109,3 +124,15 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
         au_sync_udelay(1);
         return 1;
 }
+
+static int __init mtx1_init_irq(void)
+{
+        set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+
+        return 0;
+}
+arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index 5e871c8d9e96..f8d25575fa05 100644
--- a/arch/mips/alchemy/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -32,6 +32,7 @@
 #include <linux/init.h>
 
 #include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
 
 #include <prom.h>
 
@@ -58,3 +59,8 @@ void __init prom_init(void)
                 strict_strtoul(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c
deleted file mode 100644
index f1ab12ab3433..000000000000
--- a/arch/mips/alchemy/mtx-1/irqmap.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Au1xxx irq map table
- *
- * Copyright 2003 Embedded Edge, LLC
- *              dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <asm/mach-au1x00/au1000.h>
-
-char irq_tab_alchemy[][5] __initdata = {
-        [0] = { -1, INTA, INTA, INTX, INTX }, /* IDSEL 00 - AdapterA-Slot0 (top) */
-        [1] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
-        [2] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 02 - AdapterB-Slot0 (top) */
-        [3] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
-        [4] = { -1, INTA, INTB, INTX, INTX }, /* IDSEL 04 - AdapterC-Slot0 (top) */
-        [5] = { -1, INTB, INTA, INTX, INTX }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
-        [6] = { -1, INTC, INTD, INTX, INTX }, /* IDSEL 06 - AdapterD-Slot0 (top) */
-        [7] = { -1, INTD, INTC, INTX, INTX }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
-};
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-       { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
-       { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
-       { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
-       { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
-       { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
-};
-
-
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
-}
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
index db3c526f64d8..4dc81d794cb8 100644
--- a/arch/mips/alchemy/xxs1500/Makefile
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -5,4 +5,6 @@
 # Makefile for MyCable XXS1500 board.
 #
 
-lib-y := init.o board_setup.o irqmap.o
+lib-y := init.o board_setup.o platform.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 4de2d48caed8..47b42927607b 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -25,31 +25,35 @@
 
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/interrupt.h>
 #include <linux/delay.h>
+#include <linux/pm.h>
 
+#include <asm/reboot.h>
 #include <asm/mach-au1x00/au1000.h>
 
 #include <prom.h>
 
-void board_reset(void)
+static void xxs1500_reset(char *c)
 {
         /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
         au_writel(0x00000000, 0xAE00001C);
 }
 
+static void xxs1500_power_off(void)
+{
+        printk(KERN_ALERT "It's now safe to remove power\n");
+        while (1)
+                asm volatile (".set mips3 ; wait ; .set mips1");
+}
+
 void __init board_setup(void)
 {
         u32 pin_func;
 
-#ifdef CONFIG_SERIAL_8250_CONSOLE
-        char *argptr;
-        argptr = prom_getcmdline();
-        argptr = strstr(argptr, "console=");
-        if (argptr == NULL) {
-                argptr = prom_getcmdline();
-                strcat(argptr, " console=ttyS0,115200");
-        }
-#endif
+        pm_power_off = xxs1500_power_off;
+        _machine_halt = xxs1500_power_off;
+        _machine_restart = xxs1500_reset;
 
         alchemy_gpio1_input_enable();
         alchemy_gpio2_enable();
@@ -68,22 +72,6 @@ void __init board_setup(void)
         /* Enable DTR = USB power up */
         au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
 
-#ifdef CONFIG_PCMCIA_XXS1500
-        /* GPIO 0, 1, and 4 are inputs */
-        alchemy_gpio_direction_input(0);
-        alchemy_gpio_direction_input(1);
-        alchemy_gpio_direction_input(4);
-
-        /* GPIO2 208/9/10/11 are inputs */
-        alchemy_gpio_direction_input(208);
-        alchemy_gpio_direction_input(209);
-        alchemy_gpio_direction_input(210);
-        alchemy_gpio_direction_input(211);
-
-        /* Turn off power */
-        alchemy_gpio_direction_output(214, 0);
-#endif
-
 #ifdef CONFIG_PCI
 #if defined(__MIPSEB__)
         au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
@@ -92,3 +80,23 @@ void __init board_setup(void)
 #endif
 #endif
 }
+
+static int __init xxs1500_init_irq(void)
+{
+        set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
+
+        set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
+        set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
+        set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
+
+        return 0;
+}
+arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 456fa142c093..15125c2fda7d 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -30,6 +30,7 @@
 #include <linux/kernel.h>
 
 #include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
 
 #include <prom.h>
 
@@ -56,3 +57,8 @@ void __init prom_init(void)
                 strict_strtoul(memsize_str, 0, &memsize);
         add_memory_region(0, memsize, BOOT_MEM_RAM);
 }
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c
deleted file mode 100644
index 0f0f3012e5fd..000000000000
--- a/arch/mips/alchemy/xxs1500/irqmap.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Au1xxx irq map table
- *
- * Copyright 2003 Embedded Edge, LLC
- *              dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <asm/mach-au1x00/au1000.h>
-
-struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
-        { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
-        { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
-        { AU1500_GPIO_207, IRQF_TRIGGER_LOW, 0 },
-
-        { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
-        { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
-        { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 },
-        { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 },
-        { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* CF interrupt */
-        { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 },
-};
-
-void __init board_init_irq(void)
-{
-        au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
-}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
new file mode 100644
index 000000000000..e87c45cde61b
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -0,0 +1,63 @@
+/*
+ * XXS1500 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+static struct resource xxs1500_pcmcia_res[] = {
+        {
+                .name   = "pcmcia-io",
+                .flags  = IORESOURCE_MEM,
+                .start  = PCMCIA_IO_PHYS_ADDR,
+                .end    = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
+        },
+        {
+                .name   = "pcmcia-attr",
+                .flags  = IORESOURCE_MEM,
+                .start  = PCMCIA_ATTR_PHYS_ADDR,
+                .end    = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+        },
+        {
+                .name   = "pcmcia-mem",
+                .flags  = IORESOURCE_MEM,
+                .start  = PCMCIA_MEM_PHYS_ADDR,
+                .end    = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+        },
+};
+
+static struct platform_device xxs1500_pcmcia_dev = {
+        .name           = "xxs1500_pcmcia",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(xxs1500_pcmcia_res),
+        .resource       = xxs1500_pcmcia_res,
+};
+
+static struct platform_device *xxs1500_devs[] __initdata = {
+        &xxs1500_pcmcia_dev,
+};
+
+static int __init xxs1500_dev_init(void)
+{
+        return platform_add_devices(xxs1500_devs,
+                                    ARRAY_SIZE(xxs1500_devs));
+}
+device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/ar7/clock.c b/arch/mips/ar7/clock.c
index cc65c8eb391b..fc0e7154e8d6 100644
--- a/arch/mips/ar7/clock.c
+++ b/arch/mips/ar7/clock.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -24,6 +25,8 @@
 #include <linux/delay.h>
 #include <linux/gcd.h>
 #include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/addrspace.h>
 #include <asm/mach-ar7/ar7.h>
@@ -94,12 +97,16 @@ struct tnetd7200_clocks {
         struct tnetd7200_clock usb;
 };
 
-int ar7_cpu_clock = 150000000;
-EXPORT_SYMBOL(ar7_cpu_clock);
-int ar7_bus_clock = 125000000;
-EXPORT_SYMBOL(ar7_bus_clock);
-int ar7_dsp_clock;
-EXPORT_SYMBOL(ar7_dsp_clock);
+static struct clk bus_clk = {
+        .rate   = 125000000,
+};
+
+static struct clk cpu_clk = {
+        .rate   = 150000000,
+};
+
+static struct clk dsp_clk;
+static struct clk vbus_clk;
 
 static void approximate(int base, int target, int *prediv,
                         int *postdiv, int *mul)
@@ -185,7 +192,7 @@ static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
                 base_clock = AR7_XTAL_CLOCK;
                 break;
         case BOOT_PLL_SOURCE_CPU:
-                base_clock = ar7_cpu_clock;
+                base_clock = cpu_clk.rate;
                 break;
         }
 
@@ -212,11 +219,11 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
         u32 *bootcr, u32 frequency)
 {
         int prediv, postdiv, mul;
-        int base_clock = ar7_bus_clock;
+        int base_clock = bus_clk.rate;
 
         switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
         case BOOT_PLL_SOURCE_BUS:
-                base_clock = ar7_bus_clock;
+                base_clock = bus_clk.rate;
                 break;
         case BOOT_PLL_SOURCE_REF:
                 base_clock = AR7_REF_CLOCK;
@@ -225,7 +232,7 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
                 base_clock = AR7_XTAL_CLOCK;
                 break;
         case BOOT_PLL_SOURCE_CPU:
-                base_clock = ar7_cpu_clock;
+                base_clock = cpu_clk.rate;
                 break;
         }
 
@@ -247,18 +254,18 @@ static void __init tnetd7300_init_clocks(void)
                                         ioremap_nocache(UR8_REGS_CLOCKS,
                                         sizeof(struct tnetd7300_clocks));
 
-        ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
+        bus_clk.rate = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
                 &clocks->bus, bootcr, AR7_AFE_CLOCK);
 
         if (*bootcr & BOOT_PLL_ASYNC_MODE)
-                ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
+                cpu_clk.rate = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
                         &clocks->cpu, bootcr, AR7_AFE_CLOCK);
         else
-                ar7_cpu_clock = ar7_bus_clock;
+                cpu_clk.rate = bus_clk.rate;
 
-        if (ar7_dsp_clock == 250000000)
+        if (dsp_clk.rate == 250000000)
                 tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
-                        bootcr, ar7_dsp_clock);
+                        bootcr, dsp_clk.rate);
 
         iounmap(clocks);
         iounmap(bootcr);
@@ -343,20 +350,20 @@ static void __init tnetd7200_init_clocks(void)
                 printk(KERN_INFO "Clocks: Setting DSP clock\n");
                 calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
                         &dsp_prediv, &dsp_postdiv, &dsp_mul);
-                ar7_bus_clock =
+                bus_clk.rate =
                         ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
                 tnetd7200_set_clock(dsp_base, &clocks->dsp,
                         dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
-                        ar7_bus_clock);
+                        bus_clk.rate);
 
                 printk(KERN_INFO "Clocks: Setting CPU clock\n");
                 calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
                         &cpu_postdiv, &cpu_mul);
-                ar7_cpu_clock =
+                cpu_clk.rate =
                         ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
                 tnetd7200_set_clock(cpu_base, &clocks->cpu,
                         cpu_prediv, cpu_postdiv, -1, cpu_mul,
-                        ar7_cpu_clock);
+                        cpu_clk.rate);
 
         } else
                 if (*bootcr & BOOT_PLL_2TO1_MODE) {
@@ -365,48 +372,90 @@ static void __init tnetd7200_init_clocks(void)
                         printk(KERN_INFO "Clocks: Setting CPU clock\n");
                         calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
                                 &cpu_postdiv, &cpu_mul);
-                        ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
+                        cpu_clk.rate = ((cpu_base / cpu_prediv) * cpu_mul)
                                                                 / cpu_postdiv;
                         tnetd7200_set_clock(cpu_base, &clocks->cpu,
                                 cpu_prediv, cpu_postdiv, -1, cpu_mul,
-                                ar7_cpu_clock);
+                                cpu_clk.rate);
 
                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
                         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
                                 &dsp_postdiv, &dsp_mul);
-                        ar7_bus_clock = ar7_cpu_clock / 2;
+                        bus_clk.rate = cpu_clk.rate / 2;
                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
-                                dsp_mul * 2, ar7_bus_clock);
+                                dsp_mul * 2, bus_clk.rate);
                 } else {
                         printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
 
                         printk(KERN_INFO "Clocks: Setting DSP clock\n");
                         calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
                                 &dsp_postdiv, &dsp_mul);
-                        ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
+                        bus_clk.rate = ((dsp_base / dsp_prediv) * dsp_mul)
                                                                 / dsp_postdiv;
                         tnetd7200_set_clock(dsp_base, &clocks->dsp,
                                 dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
-                                dsp_mul * 2, ar7_bus_clock);
+                                dsp_mul * 2, bus_clk.rate);
 
-                        ar7_cpu_clock = ar7_bus_clock;
+                        cpu_clk.rate = bus_clk.rate;
                 }
 
         printk(KERN_INFO "Clocks: Setting USB clock\n");
-        usb_base = ar7_bus_clock;
+        usb_base = bus_clk.rate;
         calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
                 &usb_postdiv, &usb_mul);
         tnetd7200_set_clock(usb_base, &clocks->usb,
                 usb_prediv, usb_postdiv, -1, usb_mul,
                 TNETD7200_DEF_USB_CLK);
 
-        ar7_dsp_clock = ar7_cpu_clock;
+        dsp_clk.rate = cpu_clk.rate;
 
         iounmap(clocks);
         iounmap(bootcr);
 }
 
+/*
+ * Linux clock API
+ */
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        if (!strcmp(id, "bus"))
+                return &bus_clk;
+        /* cpmac and vbus share the same rate */
+        if (!strcmp(id, "cpmac"))
+                return &vbus_clk;
+        if (!strcmp(id, "cpu"))
+                return &cpu_clk;
+        if (!strcmp(id, "dsp"));
+                return &dsp_clk;
+        if (!strcmp(id, "vbus"))
+                return &vbus_clk;
+        return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
 int __init ar7_init_clocks(void)
 {
         switch (ar7_chip_id()) {
@@ -415,12 +464,14 @@ int __init ar7_init_clocks(void)
                 tnetd7200_init_clocks();
                 break;
         case AR7_CHIP_7300:
-                ar7_dsp_clock = tnetd7300_dsp_clock();
+                dsp_clk.rate = tnetd7300_dsp_clock();
                 tnetd7300_init_clocks();
                 break;
         default:
                 break;
         }
+        /* adjust vbus clock rate */
+        vbus_clk.rate = bus_clk.rate / 2;
 
         return 0;
 }
diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c
index 74e14a3dbf4a..c32fbb57441a 100644
--- a/arch/mips/ar7/gpio.c
+++ b/arch/mips/ar7/gpio.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
+ * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -18,31 +19,113 @@
  */
 
 #include <linux/module.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-ar7/gpio.h>
 
-static const char *ar7_gpio_list[AR7_GPIO_MAX];
+struct ar7_gpio_chip {
+        void __iomem            *regs;
+        struct gpio_chip        chip;
+};
 
-int gpio_request(unsigned gpio, const char *label)
+static int ar7_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
 {
-        if (gpio >= AR7_GPIO_MAX)
-                return -EINVAL;
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_in = gpch->regs + AR7_GPIO_INPUT;
 
-        if (ar7_gpio_list[gpio])
-                return -EBUSY;
+        return readl(gpio_in) & (1 << gpio);
+}
+
+static void ar7_gpio_set_value(struct gpio_chip *chip,
+                                unsigned gpio, int value)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_out = gpch->regs + AR7_GPIO_OUTPUT;
+        unsigned tmp;
+
+        tmp = readl(gpio_out) & ~(1 << gpio);
+        if (value)
+                tmp |= 1 << gpio;
+        writel(tmp, gpio_out);
+}
+
+static int ar7_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
+{
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
 
-        if (label)
-                ar7_gpio_list[gpio] = label;
-        else
-                ar7_gpio_list[gpio] = "busy";
+        writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
 
         return 0;
 }
-EXPORT_SYMBOL(gpio_request);
 
-void gpio_free(unsigned gpio)
+static int ar7_gpio_direction_output(struct gpio_chip *chip,
+                                        unsigned gpio, int value)
 {
-        BUG_ON(!ar7_gpio_list[gpio]);
-        ar7_gpio_list[gpio] = NULL;
+        struct ar7_gpio_chip *gpch =
+                                container_of(chip, struct ar7_gpio_chip, chip);
+        void __iomem *gpio_dir = gpch->regs + AR7_GPIO_DIR;
+
+        ar7_gpio_set_value(chip, gpio, value);
+        writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
+
+        return 0;
+}
+
+static struct ar7_gpio_chip ar7_gpio_chip = {
+        .chip = {
+                .label                  = "ar7-gpio",
+                .direction_input        = ar7_gpio_direction_input,
+                .direction_output       = ar7_gpio_direction_output,
+                .set                    = ar7_gpio_set_value,
+                .get                    = ar7_gpio_get_value,
+                .base                   = 0,
+                .ngpio                  = AR7_GPIO_MAX,
+        }
+};
+
+int ar7_gpio_enable(unsigned gpio)
+{
+        void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
+
+        writel(readl(gpio_en) | (1 << gpio), gpio_en);
+
+        return 0;
+}
+EXPORT_SYMBOL(ar7_gpio_enable);
+
+int ar7_gpio_disable(unsigned gpio)
+{
+        void __iomem *gpio_en = ar7_gpio_chip.regs + AR7_GPIO_ENABLE;
+
+        writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
+
+        return 0;
+}
+EXPORT_SYMBOL(ar7_gpio_disable);
+
+static int __init ar7_gpio_init(void)
+{
+        int ret;
+
+        ar7_gpio_chip.regs = ioremap_nocache(AR7_REGS_GPIO,
+                                        AR7_REGS_GPIO + 0x10);
+
+        if (!ar7_gpio_chip.regs) {
+                printk(KERN_ERR "ar7-gpio: failed to ioremap regs\n");
+                return -ENOMEM;
+        }
+
+        ret = gpiochip_add(&ar7_gpio_chip.chip);
+        if (ret) {
+                printk(KERN_ERR "ar7-gpio: failed to add gpiochip\n");
+                return ret;
+        }
+        printk(KERN_INFO "ar7-gpio: registered %d GPIOs\n",
+                                ar7_gpio_chip.chip.ngpio);
+        return ret;
 }
-EXPORT_SYMBOL(gpio_free);
+arch_initcall(ar7_gpio_init);
diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c
index 696c723dc6d4..28abfeef09d6 100644
--- a/arch/mips/ar7/memory.c
+++ b/arch/mips/ar7/memory.c
@@ -62,8 +62,7 @@ void __init prom_meminit(void)
         unsigned long pages;
 
         pages = memsize() >> PAGE_SHIFT;
-        add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT,
-                          BOOT_MEM_RAM);
+        add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT, BOOT_MEM_RAM);
 }
 
 void __init prom_free_prom_memory(void)
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index f70a10a8cc96..246df7aca2e7 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -34,45 +34,50 @@
 #include <linux/etherdevice.h>
 #include <linux/phy.h>
 #include <linux/phy_fixed.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
 
 #include <asm/addrspace.h>
 #include <asm/mach-ar7/ar7.h>
 #include <asm/mach-ar7/gpio.h>
 #include <asm/mach-ar7/prom.h>
 
+/*****************************************************************************
+ * VLYNQ Bus
+ ****************************************************************************/
 struct plat_vlynq_data {
         struct plat_vlynq_ops ops;
         int gpio_bit;
         int reset_bit;
 };
 
-
 static int vlynq_on(struct vlynq_device *dev)
 {
-        int result;
+        int ret;
         struct plat_vlynq_data *pdata = dev->dev.platform_data;
 
-        result = gpio_request(pdata->gpio_bit, "vlynq");
-        if (result)
+        ret = gpio_request(pdata->gpio_bit, "vlynq");
+        if (ret)
                 goto out;
 
         ar7_device_reset(pdata->reset_bit);
 
-        result = ar7_gpio_disable(pdata->gpio_bit);
-        if (result)
+        ret = ar7_gpio_disable(pdata->gpio_bit);
+        if (ret)
                 goto out_enabled;
 
-        result = ar7_gpio_enable(pdata->gpio_bit);
-        if (result)
+        ret = ar7_gpio_enable(pdata->gpio_bit);
+        if (ret)
                 goto out_enabled;
 
-        result = gpio_direction_output(pdata->gpio_bit, 0);
-        if (result)
+        ret = gpio_direction_output(pdata->gpio_bit, 0);
+        if (ret)
                 goto out_gpio_enabled;
 
         msleep(50);
 
         gpio_set_value(pdata->gpio_bit, 1);
+
         msleep(50);
 
         return 0;
@@ -83,320 +88,384 @@ out_enabled:
         ar7_device_disable(pdata->reset_bit);
         gpio_free(pdata->gpio_bit);
 out:
-        return result;
+        return ret;
 }
 
 static void vlynq_off(struct vlynq_device *dev)
 {
         struct plat_vlynq_data *pdata = dev->dev.platform_data;
+
         ar7_gpio_disable(pdata->gpio_bit);
         gpio_free(pdata->gpio_bit);
         ar7_device_disable(pdata->reset_bit);
 }
 
-static struct resource physmap_flash_resource = {
-        .name = "mem",
-        .flags = IORESOURCE_MEM,
-        .start = 0x10000000,
-        .end = 0x107fffff,
-};
-
-static struct resource cpmac_low_res[] = {
+static struct resource vlynq_low_res[] = {
         {
-                .name = "regs",
-                .flags = IORESOURCE_MEM,
-                .start = AR7_REGS_MAC0,
-                .end = AR7_REGS_MAC0 + 0x7ff,
+                .name   = "regs",
+                .flags  = IORESOURCE_MEM,
+                .start  = AR7_REGS_VLYNQ0,
+                .end    = AR7_REGS_VLYNQ0 + 0xff,
         },
         {
-                .name = "irq",
-                .flags = IORESOURCE_IRQ,
-                .start = 27,
-                .end = 27,
+                .name   = "irq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 29,
+                .end    = 29,
         },
-};
-
-static struct resource cpmac_high_res[] = {
         {
-                .name = "regs",
-                .flags = IORESOURCE_MEM,
-                .start = AR7_REGS_MAC1,
-                .end = AR7_REGS_MAC1 + 0x7ff,
+                .name   = "mem",
+                .flags  = IORESOURCE_MEM,
+                .start  = 0x04000000,
+                .end    = 0x04ffffff,
         },
         {
-                .name = "irq",
-                .flags = IORESOURCE_IRQ,
-                .start = 41,
-                .end = 41,
+                .name   = "devirq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 80,
+                .end    = 111,
         },
 };
 
-static struct resource vlynq_low_res[] = {
+static struct resource vlynq_high_res[] = {
         {
-                .name = "regs",
-                .flags = IORESOURCE_MEM,
-                .start = AR7_REGS_VLYNQ0,
-                .end = AR7_REGS_VLYNQ0 + 0xff,
+                .name   = "regs",
+                .flags  = IORESOURCE_MEM,
+                .start  = AR7_REGS_VLYNQ1,
+                .end    = AR7_REGS_VLYNQ1 + 0xff,
         },
         {
-                .name = "irq",
-                .flags = IORESOURCE_IRQ,
-                .start = 29,
-                .end = 29,
+                .name   = "irq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 33,
+                .end    = 33,
         },
         {
-                .name = "mem",
-                .flags = IORESOURCE_MEM,
-                .start = 0x04000000,
-                .end = 0x04ffffff,
+                .name   = "mem",
+                .flags  = IORESOURCE_MEM,
+                .start  = 0x0c000000,
+                .end    = 0x0cffffff,
         },
         {
-                .name = "devirq",
-                .flags = IORESOURCE_IRQ,
-                .start = 80,
-                .end = 111,
+                .name   = "devirq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 112,
+                .end    = 143,
         },
 };
 
-static struct resource vlynq_high_res[] = {
-        {
-                .name = "regs",
-                .flags = IORESOURCE_MEM,
-                .start = AR7_REGS_VLYNQ1,
-                .end = AR7_REGS_VLYNQ1 + 0xff,
+static struct plat_vlynq_data vlynq_low_data = {
+        .ops = {
+                .on     = vlynq_on,
+                .off    = vlynq_off,
         },
-        {
-                .name = "irq",
-                .flags = IORESOURCE_IRQ,
-                .start = 33,
-                .end = 33,
+        .reset_bit      = 20,
+        .gpio_bit       = 18,
+};
+
+static struct plat_vlynq_data vlynq_high_data = {
+        .ops = {
+                .on     = vlynq_on,
+                .off    = vlynq_off,
         },
-        {
-                .name = "mem",
-                .flags = IORESOURCE_MEM,
-                .start = 0x0c000000,
-                .end = 0x0cffffff,
+        .reset_bit      = 26,
+        .gpio_bit       = 19,
+};
+
+static struct platform_device vlynq_low = {
+        .id             = 0,
+        .name           = "vlynq",
+        .dev = {
+                .platform_data  = &vlynq_low_data,
         },
-        {
-                .name = "devirq",
-                .flags = IORESOURCE_IRQ,
-                .start = 112,
-                .end = 143,
+        .resource       = vlynq_low_res,
+        .num_resources  = ARRAY_SIZE(vlynq_low_res),
+};
+
+static struct platform_device vlynq_high = {
+        .id             = 1,
+        .name           = "vlynq",
+        .dev = {
+                .platform_data  = &vlynq_high_data,
         },
+        .resource       = vlynq_high_res,
+        .num_resources  = ARRAY_SIZE(vlynq_high_res),
 };
 
-static struct resource usb_res[] = {
-        {
-                .name = "regs",
-                .flags = IORESOURCE_MEM,
-                .start = AR7_REGS_USB,
-                .end = AR7_REGS_USB + 0xff,
+/*****************************************************************************
+ * Flash
+ ****************************************************************************/
+static struct resource physmap_flash_resource = {
+        .name   = "mem",
+        .flags  = IORESOURCE_MEM,
+        .start  = 0x10000000,
+        .end    = 0x107fffff,
+};
+
+static struct physmap_flash_data physmap_flash_data = {
+        .width  = 2,
+};
+
+static struct platform_device physmap_flash = {
+        .name           = "physmap-flash",
+        .dev = {
+                .platform_data  = &physmap_flash_data,
         },
+        .resource       = &physmap_flash_resource,
+        .num_resources  = 1,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct resource cpmac_low_res[] = {
         {
-                .name = "irq",
-                .flags = IORESOURCE_IRQ,
-                .start = 32,
-                .end = 32,
+                .name   = "regs",
+                .flags  = IORESOURCE_MEM,
+                .start  = AR7_REGS_MAC0,
+                .end    = AR7_REGS_MAC0 + 0x7ff,
         },
         {
-                .name = "mem",
-                .flags = IORESOURCE_MEM,
-                .start = 0x03400000,
-                .end = 0x03401fff,
+                .name   = "irq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 27,
+                .end    = 27,
         },
 };
 
-static struct physmap_flash_data physmap_flash_data = {
-        .width = 2,
+static struct resource cpmac_high_res[] = {
+        {
+                .name   = "regs",
+                .flags  = IORESOURCE_MEM,
+                .start  = AR7_REGS_MAC1,
+                .end    = AR7_REGS_MAC1 + 0x7ff,
+        },
+        {
+                .name   = "irq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 41,
+                .end    = 41,
+        },
 };
 
 static struct fixed_phy_status fixed_phy_status __initdata = {
-        .link = 1,
-        .speed = 100,
-        .duplex = 1,
+        .link           = 1,
+        .speed          = 100,
+        .duplex         = 1,
 };
 
 static struct plat_cpmac_data cpmac_low_data = {
-        .reset_bit = 17,
-        .power_bit = 20,
-        .phy_mask = 0x80000000,
+        .reset_bit      = 17,
+        .power_bit      = 20,
+        .phy_mask       = 0x80000000,
 };
 
 static struct plat_cpmac_data cpmac_high_data = {
-        .reset_bit = 21,
-        .power_bit = 22,
-        .phy_mask = 0x7fffffff,
-};
-
-static struct plat_vlynq_data vlynq_low_data = {
-        .ops.on = vlynq_on,
-        .ops.off = vlynq_off,
-        .reset_bit = 20,
-        .gpio_bit = 18,
-};
-
-static struct plat_vlynq_data vlynq_high_data = {
-        .ops.on = vlynq_on,
-        .ops.off = vlynq_off,
-        .reset_bit = 16,
-        .gpio_bit = 19,
-};
-
-static struct platform_device physmap_flash = {
-        .id = 0,
-        .name = "physmap-flash",
-        .dev.platform_data = &physmap_flash_data,
-        .resource = &physmap_flash_resource,
-        .num_resources = 1,
+        .reset_bit      = 21,
+        .power_bit      = 22,
+        .phy_mask       = 0x7fffffff,
 };
 
 static u64 cpmac_dma_mask = DMA_BIT_MASK(32);
+
 static struct platform_device cpmac_low = {
-        .id = 0,
-        .name = "cpmac",
+        .id             = 0,
+        .name           = "cpmac",
         .dev = {
-                .dma_mask = &cpmac_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &cpmac_low_data,
+                .dma_mask               = &cpmac_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &cpmac_low_data,
         },
-        .resource = cpmac_low_res,
-        .num_resources = ARRAY_SIZE(cpmac_low_res),
+        .resource       = cpmac_low_res,
+        .num_resources  = ARRAY_SIZE(cpmac_low_res),
 };
 
 static struct platform_device cpmac_high = {
-        .id = 1,
-        .name = "cpmac",
+        .id             = 1,
+        .name           = "cpmac",
         .dev = {
-                .dma_mask = &cpmac_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &cpmac_high_data,
+                .dma_mask               = &cpmac_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &cpmac_high_data,
         },
-        .resource = cpmac_high_res,
-        .num_resources = ARRAY_SIZE(cpmac_high_res),
+        .resource       = cpmac_high_res,
+        .num_resources  = ARRAY_SIZE(cpmac_high_res),
 };
 
-static struct platform_device vlynq_low = {
-        .id = 0,
-        .name = "vlynq",
-        .dev.platform_data = &vlynq_low_data,
-        .resource = vlynq_low_res,
-        .num_resources = ARRAY_SIZE(vlynq_low_res),
-};
+static inline unsigned char char2hex(char h)
+{
+        switch (h) {
+        case '0': case '1': case '2': case '3': case '4':
+        case '5': case '6': case '7': case '8': case '9':
+                return h - '0';
+        case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
+                return h - 'A' + 10;
+        case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
+                return h - 'a' + 10;
+        default:
+                return 0;
+        }
+}
 
-static struct platform_device vlynq_high = {
-        .id = 1,
-        .name = "vlynq",
-        .dev.platform_data = &vlynq_high_data,
-        .resource = vlynq_high_res,
-        .num_resources = ARRAY_SIZE(vlynq_high_res),
+static void cpmac_get_mac(int instance, unsigned char *dev_addr)
+{
+        int i;
+        char name[5], default_mac[ETH_ALEN], *mac;
+
+        mac = NULL;
+        sprintf(name, "mac%c", 'a' + instance);
+        mac = prom_getenv(name);
+        if (!mac) {
+                sprintf(name, "mac%c", 'a');
+                mac = prom_getenv(name);
+        }
+        if (!mac) {
+                random_ether_addr(default_mac);
+                mac = default_mac;
+        }
+        for (i = 0; i < 6; i++)
+                dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
+                        char2hex(mac[i * 3 + 1]);
+}
+
+/*****************************************************************************
+ * USB
+ ****************************************************************************/
+static struct resource usb_res[] = {
+        {
+                .name   = "regs",
+                .flags  = IORESOURCE_MEM,
+                .start  = AR7_REGS_USB,
+                .end    = AR7_REGS_USB + 0xff,
+        },
+        {
+                .name   = "irq",
+                .flags  = IORESOURCE_IRQ,
+                .start  = 32,
+                .end    = 32,
+        },
+        {
+                .name   = "mem",
+                .flags  = IORESOURCE_MEM,
+                .start  = 0x03400000,
+                .end    = 0x03401fff,
+        },
 };
 
+static struct platform_device ar7_udc = {
+        .name           = "ar7_udc",
+        .resource       = usb_res,
+        .num_resources  = ARRAY_SIZE(usb_res),
+};
 
+/*****************************************************************************
+ * LEDs
+ ****************************************************************************/
 static struct gpio_led default_leds[] = {
         {
-                .name = "status",
-                .gpio = 8,
-                .active_low = 1,
+                .name                   = "status",
+                .gpio                   = 8,
+                .active_low             = 1,
         },
 };
 
 static struct gpio_led dsl502t_leds[] = {
         {
-                .name = "status",
-                .gpio = 9,
-                .active_low = 1,
+                .name                   = "status",
+                .gpio                   = 9,
+                .active_low             = 1,
         },
         {
-                .name = "ethernet",
-                .gpio = 7,
-                .active_low = 1,
+                .name                   = "ethernet",
+                .gpio                   = 7,
+                .active_low             = 1,
         },
         {
-                .name = "usb",
-                .gpio = 12,
-                .active_low = 1,
+                .name                   = "usb",
+                .gpio                   = 12,
+                .active_low             = 1,
         },
 };
 
 static struct gpio_led dg834g_leds[] = {
         {
-                .name = "ppp",
-                .gpio = 6,
-                .active_low = 1,
+                .name                   = "ppp",
+                .gpio                   = 6,
+                .active_low             = 1,
         },
         {
-                .name = "status",
-                .gpio = 7,
-                .active_low = 1,
+                .name                   = "status",
+                .gpio                   = 7,
+                .active_low             = 1,
         },
         {
-                .name = "adsl",
-                .gpio = 8,
-                .active_low = 1,
+                .name                   = "adsl",
+                .gpio                   = 8,
+                .active_low             = 1,
         },
         {
-                .name = "wifi",
-                .gpio = 12,
-                .active_low = 1,
+                .name                   = "wifi",
+                .gpio                   = 12,
+                .active_low             = 1,
         },
         {
-                .name = "power",
-                .gpio = 14,
-                .active_low = 1,
-                .default_trigger = "default-on",
+                .name                   = "power",
+                .gpio                   = 14,
+                .active_low             = 1,
+                .default_trigger        = "default-on",
         },
 };
 
 static struct gpio_led fb_sl_leds[] = {
         {
-                .name = "1",
-                .gpio = 7,
+                .name                   = "1",
+                .gpio                   = 7,
         },
         {
-                .name = "2",
-                .gpio = 13,
-                .active_low = 1,
+                .name                   = "2",
+                .gpio                   = 13,
+                .active_low             = 1,
         },
         {
-                .name = "3",
-                .gpio = 10,
-                .active_low = 1,
+                .name                   = "3",
+                .gpio                   = 10,
+                .active_low             = 1,
         },
         {
-                .name = "4",
-                .gpio = 12,
-                .active_low = 1,
+                .name                   = "4",
+                .gpio                   = 12,
+                .active_low             = 1,
         },
         {
-                .name = "5",
-                .gpio = 9,
-                .active_low = 1,
+                .name                   = "5",
+                .gpio                   = 9,
+                .active_low             = 1,
         },
 };
 
 static struct gpio_led fb_fon_leds[] = {
         {
-                .name = "1",
-                .gpio = 8,
+                .name                   = "1",
+                .gpio                   = 8,
         },
         {
-                .name = "2",
-                .gpio = 3,
-                .active_low = 1,
+                .name                   = "2",
+                .gpio                   = 3,
+                .active_low             = 1,
         },
         {
-                .name = "3",
-                .gpio = 5,
+                .name                   = "3",
+                .gpio                   = 5,
         },
         {
-                .name = "4",
-                .gpio = 4,
-                .active_low = 1,
+                .name                   = "4",
+                .gpio                   = 4,
+                .active_low             = 1,
         },
         {
-                .name = "5",
-                .gpio = 11,
-                .active_low = 1,
+                .name                   = "5",
+                .gpio                   = 11,
+                .active_low             = 1,
         },
 };
 
@@ -404,69 +473,11 @@ static struct gpio_led_platform_data ar7_led_data;
 
 static struct platform_device ar7_gpio_leds = {
         .name = "leds-gpio",
-        .id = -1,
         .dev = {
                 .platform_data = &ar7_led_data,
         }
 };
 
-static struct platform_device ar7_udc = {
-        .id = -1,
-        .name = "ar7_udc",
-        .resource = usb_res,
-        .num_resources = ARRAY_SIZE(usb_res),
-};
-
-static struct resource ar7_wdt_res = {
-        .name = "regs",
-        .start = -1, /* Filled at runtime */
-        .end = -1, /* Filled at runtime */
-        .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device ar7_wdt = {
-        .id = -1,
-        .name  = "ar7_wdt",
-        .resource = &ar7_wdt_res,
-        .num_resources = 1,
-};
-
-static inline unsigned char char2hex(char h)
-{
-        switch (h) {
-        case '0': case '1': case '2': case '3': case '4':
-        case '5': case '6': case '7': case '8': case '9':
-                return h - '0';
-        case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
-                return h - 'A' + 10;
-        case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
-                return h - 'a' + 10;
-        default:
-                return 0;
-        }
-}
-
-static void cpmac_get_mac(int instance, unsigned char *dev_addr)
-{
-        int i;
-        char name[5], default_mac[ETH_ALEN], *mac;
-
-        mac = NULL;
-        sprintf(name, "mac%c", 'a' + instance);
-        mac = prom_getenv(name);
-        if (!mac) {
-                sprintf(name, "mac%c", 'a');
-                mac = prom_getenv(name);
-        }
-        if (!mac) {
-                random_ether_addr(default_mac);
-                mac = default_mac;
-        }
-        for (i = 0; i < 6; i++)
-                dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
-                        char2hex(mac[i * 3 + 1]);
-}
-
 static void __init detect_leds(void)
 {
         char *prid, *usb_prod;
@@ -499,111 +510,149 @@ static void __init detect_leds(void)
         }
 }
 
-static int __init ar7_register_devices(void)
+/*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct resource ar7_wdt_res = {
+        .name           = "regs",
+        .flags          = IORESOURCE_MEM,
+        .start          = -1,   /* Filled at runtime */
+        .end            = -1,   /* Filled at runtime */
+};
+
+static struct platform_device ar7_wdt = {
+        .name           = "ar7_wdt",
+        .resource       = &ar7_wdt_res,
+        .num_resources  = 1,
+};
+
+/*****************************************************************************
+ * Init
+ ****************************************************************************/
+static int __init ar7_register_uarts(void)
 {
-        u16 chip_id;
-        int res;
-        u32 *bootcr, val;
 #ifdef CONFIG_SERIAL_8250
-        static struct uart_port uart_port[2] __initdata;
-
-        memset(uart_port, 0, sizeof(struct uart_port) * 2);
-
-        uart_port[0].type = PORT_16550A;
-        uart_port[0].line = 0;
-        uart_port[0].irq = AR7_IRQ_UART0;
-        uart_port[0].uartclk = ar7_bus_freq() / 2;
-        uart_port[0].iotype = UPIO_MEM32;
-        uart_port[0].mapbase = AR7_REGS_UART0;
-        uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
-        uart_port[0].regshift = 2;
-        res = early_serial_setup(&uart_port[0]);
+        static struct uart_port uart_port __initdata;
+        struct clk *bus_clk;
+        int res;
+
+        memset(&uart_port, 0, sizeof(struct uart_port));
+
+        bus_clk = clk_get(NULL, "bus");
+        if (IS_ERR(bus_clk))
+                panic("unable to get bus clk\n");
+
+        uart_port.type          = PORT_16550A;
+        uart_port.uartclk       = clk_get_rate(bus_clk) / 2;
+        uart_port.iotype        = UPIO_MEM32;
+        uart_port.regshift      = 2;
+
+        uart_port.line          = 0;
+        uart_port.irq           = AR7_IRQ_UART0;
+        uart_port.mapbase       = AR7_REGS_UART0;
+        uart_port.membase       = ioremap(uart_port.mapbase, 256);
+
+        res = early_serial_setup(&uart_port);
         if (res)
                 return res;
 
-
         /* Only TNETD73xx have a second serial port */
         if (ar7_has_second_uart()) {
-                uart_port[1].type = PORT_16550A;
-                uart_port[1].line = 1;
-                uart_port[1].irq = AR7_IRQ_UART1;
-                uart_port[1].uartclk = ar7_bus_freq() / 2;
-                uart_port[1].iotype = UPIO_MEM32;
-                uart_port[1].mapbase = UR8_REGS_UART1;
-                uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
-                uart_port[1].regshift = 2;
-                res = early_serial_setup(&uart_port[1]);
+                uart_port.line          = 1;
+                uart_port.irq           = AR7_IRQ_UART1;
+                uart_port.mapbase       = UR8_REGS_UART1;
+                uart_port.membase       = ioremap(uart_port.mapbase, 256);
+
+                res = early_serial_setup(&uart_port);
                 if (res)
                         return res;
         }
-#endif /* CONFIG_SERIAL_8250 */
+#endif
+
+        return 0;
+}
+
+static int __init ar7_register_devices(void)
+{
+        void __iomem *bootcr;
+        u32 val;
+        u16 chip_id;
+        int res;
+
+        res = ar7_register_uarts();
+        if (res)
+                pr_err("unable to setup uart(s): %d\n", res);
+
         res = platform_device_register(&physmap_flash);
         if (res)
-                return res;
+                pr_warning("unable to register physmap-flash: %d\n", res);
 
         ar7_device_disable(vlynq_low_data.reset_bit);
         res = platform_device_register(&vlynq_low);
         if (res)
-                return res;
+                pr_warning("unable to register vlynq-low: %d\n", res);
 
         if (ar7_has_high_vlynq()) {
                 ar7_device_disable(vlynq_high_data.reset_bit);
                 res = platform_device_register(&vlynq_high);
                 if (res)
-                        return res;
+                        pr_warning("unable to register vlynq-high: %d\n", res);
         }
 
         if (ar7_has_high_cpmac()) {
-                res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status);
-                if (res && res != -ENODEV)
-                        return res;
-                cpmac_get_mac(1, cpmac_high_data.dev_addr);
-                res = platform_device_register(&cpmac_high);
-                if (res)
-                        return res;
-        } else {
+                if (!res) {
+                        cpmac_get_mac(1, cpmac_high_data.dev_addr);
+
+                        res = platform_device_register(&cpmac_high);
+                        if (res)
+                                pr_warning("unable to register cpmac-high: %d\n", res);
+                } else
+                        pr_warning("unable to add cpmac-high phy: %d\n", res);
+        } else
                 cpmac_low_data.phy_mask = 0xffffffff;
-        }
 
         res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
-        if (res && res != -ENODEV)
-                return res;
-
-        cpmac_get_mac(0, cpmac_low_data.dev_addr);
-        res = platform_device_register(&cpmac_low);
-        if (res)
-                return res;
+        if (!res) {
+                cpmac_get_mac(0, cpmac_low_data.dev_addr);
+                res = platform_device_register(&cpmac_low);
+                if (res)
+                        pr_warning("unable to register cpmac-low: %d\n", res);
+        } else
+                pr_warning("unable to add cpmac-low phy: %d\n", res);
 
         detect_leds();
         res = platform_device_register(&ar7_gpio_leds);
         if (res)
-                return res;
+                pr_warning("unable to register leds: %d\n", res);
 
         res = platform_device_register(&ar7_udc);
-
-        chip_id = ar7_chip_id();
-        switch (chip_id) {
-        case AR7_CHIP_7100:
-        case AR7_CHIP_7200:
-                ar7_wdt_res.start = AR7_REGS_WDT;
-                break;
-        case AR7_CHIP_7300:
-                ar7_wdt_res.start = UR8_REGS_WDT;
-                break;
-        default:
-                break;
-        }
-
-        ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
-
-        bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
-        val = *bootcr;
-        iounmap(bootcr);
+        if (res)
+                pr_warning("unable to register usb slave: %d\n", res);
 
         /* Register watchdog only if enabled in hardware */
-        if (val & AR7_WDT_HW_ENA)
+        bootcr = ioremap_nocache(AR7_REGS_DCL, 4);
+        val = readl(bootcr);
+        iounmap(bootcr);
+        if (val & AR7_WDT_HW_ENA) {
+                chip_id = ar7_chip_id();
+                switch (chip_id) {
+                case AR7_CHIP_7100:
+                case AR7_CHIP_7200:
+                        ar7_wdt_res.start = AR7_REGS_WDT;
+                        break;
+                case AR7_CHIP_7300:
+                        ar7_wdt_res.start = UR8_REGS_WDT;
+                        break;
+                default:
+                        break;
+                }
+
+                ar7_wdt_res.end = ar7_wdt_res.start + 0x20;
                 res = platform_device_register(&ar7_wdt);
+                if (res)
+                        pr_warning("unable to register watchdog: %d\n", res);
+        }
 
-        return res;
+        return 0;
 }
 arch_initcall(ar7_register_devices);
diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c
index c1fdd3682812..52385790e5c1 100644
--- a/arch/mips/ar7/prom.c
+++ b/arch/mips/ar7/prom.c
@@ -32,8 +32,8 @@
 #define MAX_ENTRY 80
 
 struct env_var {
-        char *name;
-        char *value;
+        char    *name;
+        char    *value;
 };
 
 static struct env_var adam2_env[MAX_ENTRY];
@@ -41,6 +41,7 @@ static struct env_var adam2_env[MAX_ENTRY];
 char *prom_getenv(const char *name)
 {
         int i;
+
         for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
                 if (!strcmp(name, adam2_env[i].name))
                         return adam2_env[i].value;
@@ -49,65 +50,50 @@ char *prom_getenv(const char *name)
 }
 EXPORT_SYMBOL(prom_getenv);
 
-char * __init prom_getcmdline(void)
-{
-        return &(arcs_cmdline[0]);
-}
-
 static void  __init ar7_init_cmdline(int argc, char *argv[])
 {
-        char *cp;
-        int actr;
-
-        actr = 1; /* Always ignore argv[0] */
+        int i;
 
-        cp = &(arcs_cmdline[0]);
-        while (actr < argc) {
-                strcpy(cp, argv[actr]);
-                cp += strlen(argv[actr]);
-                *cp++ = ' ';
-                actr++;
-        }
-        if (cp != &(arcs_cmdline[0])) {
-                /* get rid of trailing space */
-                --cp;
-                *cp = '\0';
+        for (i = 1; i < argc; i++) {
+                strlcat(arcs_cmdline, argv[i], COMMAND_LINE_SIZE);
+                if (i < (argc - 1))
+                        strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
         }
 }
 
 struct psbl_rec {
-        u32 psbl_size;
-        u32 env_base;
-        u32 env_size;
-        u32 ffs_base;
-        u32 ffs_size;
+        u32     psbl_size;
+        u32     env_base;
+        u32     env_size;
+        u32     ffs_base;
+        u32     ffs_size;
 };
 
 static __initdata char psp_env_version[] = "TIENV0.8";
 
 struct psp_env_chunk {
-        u8 num;
-        u8 ctrl;
-        u16 csum;
-        u8 len;
-        char data[11];
+        u8      num;
+        u8      ctrl;
+        u16     csum;
+        u8      len;
+        char    data[11];
 } __attribute__ ((packed));
 
 struct psp_var_map_entry {
-        u8 num;
-        char *value;
+        u8      num;
+        char    *value;
 };
 
 static struct psp_var_map_entry psp_var_map[] = {
-        { 1, "cpufrequency" },
-        { 2, "memsize" },
-        { 3, "flashsize" },
-        { 4, "modetty0" },
-        { 5, "modetty1" },
-        { 8, "maca" },
-        { 9, "macb" },
-        { 28, "sysfrequency" },
-        { 38, "mipsfrequency" },
+        {  1,   "cpufrequency" },
+        {  2,   "memsize" },
+        {  3,   "flashsize" },
+        {  4,   "modetty0" },
+        {  5,   "modetty1" },
+        {  8,   "maca" },
+        {  9,   "macb" },
+        { 28,   "sysfrequency" },
+        { 38,   "mipsfrequency" },
 };
 
 /*
@@ -154,6 +140,7 @@ static char * __init lookup_psp_var_map(u8 num)
 static void __init add_adam2_var(char *name, char *value)
 {
         int i;
+
         for (i = 0; i < MAX_ENTRY; i++) {
                 if (!adam2_env[i].name) {
                         adam2_env[i].name = name;
@@ -216,7 +203,7 @@ static void __init console_config(void)
         char parity = '\0', bits = '\0', flow = '\0';
         char *s, *p;
 
-        if (strstr(prom_getcmdline(), "console="))
+        if (strstr(arcs_cmdline, "console="))
                 return;
 
         s = prom_getenv("modetty0");
@@ -250,7 +237,7 @@ static void __init console_config(void)
         else
                 sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
                         bits);
-        strcat(prom_getcmdline(), console_string);
+        strlcat(arcs_cmdline, console_string, COMMAND_LINE_SIZE);
 #endif
 }
 
@@ -279,4 +266,3 @@ int prom_putchar(char c)
         serial_out(UART_TX, c);
         return 1;
 }
-
diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c
index 39f6b5b96463..3a801d2cb6e5 100644
--- a/arch/mips/ar7/setup.c
+++ b/arch/mips/ar7/setup.c
@@ -26,8 +26,8 @@
 
 static void ar7_machine_restart(char *command)
 {
-        u32 *softres_reg = ioremap(AR7_REGS_RESET +
-                                          AR7_RESET_SOFTWARE, 1);
+        u32 *softres_reg = ioremap(AR7_REGS_RESET + AR7_RESET_SOFTWARE, 1);
+
         writel(1, softres_reg);
 }
 
@@ -41,6 +41,7 @@ static void ar7_machine_power_off(void)
 {
         u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
         u32 power_state = readl(power_reg) | (3 << 30);
+
         writel(power_state, power_reg);
         ar7_machine_halt();
 }
@@ -49,14 +50,14 @@ const char *get_system_type(void)
 {
         u16 chip_id = ar7_chip_id();
         switch (chip_id) {
-        case AR7_CHIP_7300:
-                return "TI AR7 (TNETD7300)";
         case AR7_CHIP_7100:
                 return "TI AR7 (TNETD7100)";
         case AR7_CHIP_7200:
                 return "TI AR7 (TNETD7200)";
+        case AR7_CHIP_7300:
+                return "TI AR7 (TNETD7300)";
         default:
-                return "TI AR7 (Unknown)";
+                return "TI AR7 (unknown)";
         }
 }
 
@@ -70,7 +71,6 @@ console_initcall(ar7_init_console);
  * Initializes basic routines and structures pointers, memory size (as
  * given by the bios and saves the command line.
  */
-
 void __init plat_mem_setup(void)
 {
         unsigned long io_base;
@@ -88,6 +88,5 @@ void __init plat_mem_setup(void)
         prom_meminit();
 
         printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
-                                        get_system_type(),
-                ar7_chip_id(), ar7_chip_rev());
+                        get_system_type(), ar7_chip_id(), ar7_chip_rev());
 }
diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c
index a1fba894daa2..5fb8a0134085 100644
--- a/arch/mips/ar7/time.c
+++ b/arch/mips/ar7/time.c
@@ -20,11 +20,21 @@
 
 #include <linux/init.h>
 #include <linux/time.h>
+#include <linux/err.h>
+#include <linux/clk.h>
 
 #include <asm/time.h>
 #include <asm/mach-ar7/ar7.h>
 
 void __init plat_time_init(void)
 {
-        mips_hpt_frequency = ar7_cpu_freq() / 2;
+        struct clk *cpu_clk;
+
+        cpu_clk = clk_get(NULL, "cpu");
+        if (IS_ERR(cpu_clk)) {
+                printk(KERN_ERR "unable to get cpu clock\n");
+                return;
+        }
+
+        mips_hpt_frequency = clk_get_rate(cpu_clk) / 2;
 }
diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c
index 9b798800258c..e4a5ee9c9721 100644
--- a/arch/mips/bcm47xx/gpio.c
+++ b/arch/mips/bcm47xx/gpio.c
@@ -59,4 +59,3 @@ int gpio_to_irq(unsigned gpio)
                 return -EINVAL;
 }
 EXPORT_SYMBOL_GPL(gpio_to_irq);
-
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
index c51405e57921..0fa646c5a844 100644
--- a/arch/mips/bcm47xx/prom.c
+++ b/arch/mips/bcm47xx/prom.c
@@ -141,6 +141,14 @@ static __init void prom_init_mem(void)
                         break;
         }
 
+        /* Ignoring the last page when ddr size is 128M. Cached
+         * accesses to last page is causing the processor to prefetch
+         * using address above 128M stepping out of the ddr address
+         * space.
+         */
+        if (mem == 0x8000000)
+                mem -= 0x1000;
+
         add_memory_region(0, mem, BOOT_MEM_RAM);
 }
 
@@ -155,4 +163,3 @@ void __init prom_init(void)
 void __init prom_free_prom_memory(void)
 {
 }
-
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 2f580fa160c9..d442e11625fa 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -121,4 +121,3 @@ void __init plat_mem_setup(void)
         _machine_halt = bcm47xx_machine_halt;
         pm_power_off = bcm47xx_machine_halt;
 }
-
diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c
index ef00e7f58c24..74d06965326f 100644
--- a/arch/mips/bcm47xx/wgt634u.c
+++ b/arch/mips/bcm47xx/wgt634u.c
@@ -164,4 +164,3 @@ static int __init wgt634u_init(void)
 }
 
 module_init(wgt634u_init);
-
diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 1fe412c43171..ea17941168ca 100644
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -836,4 +836,3 @@ int __init board_register_devices(void)
 
         return 0;
 }
-
diff --git a/arch/mips/bcm63xx/timer.c b/arch/mips/bcm63xx/timer.c
index ba522bdcde4b..5f1135981568 100644
--- a/arch/mips/bcm63xx/timer.c
+++ b/arch/mips/bcm63xx/timer.c
@@ -17,8 +17,8 @@
 #include <bcm63xx_timer.h>
 #include <bcm63xx_regs.h>
 
-static DEFINE_SPINLOCK(timer_reg_lock);
-static DEFINE_SPINLOCK(timer_data_lock);
+static DEFINE_RAW_SPINLOCK(timer_reg_lock);
+static DEFINE_RAW_SPINLOCK(timer_data_lock);
 static struct clk *periph_clk;
 
 static struct timer_data {
@@ -31,23 +31,23 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id)
         u32 stat;
         int i;
 
-        spin_lock(&timer_reg_lock);
+        raw_spin_lock(&timer_reg_lock);
         stat = bcm_timer_readl(TIMER_IRQSTAT_REG);
         bcm_timer_writel(stat, TIMER_IRQSTAT_REG);
-        spin_unlock(&timer_reg_lock);
+        raw_spin_unlock(&timer_reg_lock);
 
         for (i = 0; i < BCM63XX_TIMER_COUNT; i++) {
                 if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i)))
                         continue;
 
-                spin_lock(&timer_data_lock);
+                raw_spin_lock(&timer_data_lock);
                 if (!timer_data[i].cb) {
-                        spin_unlock(&timer_data_lock);
+                        raw_spin_unlock(&timer_data_lock);
                         continue;
                 }
 
                 timer_data[i].cb(timer_data[i].data);
-                spin_unlock(&timer_data_lock);
+                raw_spin_unlock(&timer_data_lock);
         }
 
         return IRQ_HANDLED;
@@ -61,7 +61,7 @@ int bcm63xx_timer_enable(int id)
         if (id >= BCM63XX_TIMER_COUNT)
                 return -EINVAL;
 
-        spin_lock_irqsave(&timer_reg_lock, flags);
+        raw_spin_lock_irqsave(&timer_reg_lock, flags);
 
         reg = bcm_timer_readl(TIMER_CTLx_REG(id));
         reg |= TIMER_CTL_ENABLE_MASK;
@@ -71,7 +71,7 @@ int bcm63xx_timer_enable(int id)
         reg |= TIMER_IRQSTAT_TIMER_IR_EN(id);
         bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
 
-        spin_unlock_irqrestore(&timer_reg_lock, flags);
+        raw_spin_unlock_irqrestore(&timer_reg_lock, flags);
         return 0;
 }
 
@@ -85,7 +85,7 @@ int bcm63xx_timer_disable(int id)
         if (id >= BCM63XX_TIMER_COUNT)
                 return -EINVAL;
 
-        spin_lock_irqsave(&timer_reg_lock, flags);
+        raw_spin_lock_irqsave(&timer_reg_lock, flags);
 
         reg = bcm_timer_readl(TIMER_CTLx_REG(id));
         reg &= ~TIMER_CTL_ENABLE_MASK;
@@ -95,7 +95,7 @@ int bcm63xx_timer_disable(int id)
         reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id);
         bcm_timer_writel(reg, TIMER_IRQSTAT_REG);
 
-        spin_unlock_irqrestore(&timer_reg_lock, flags);
+        raw_spin_unlock_irqrestore(&timer_reg_lock, flags);
         return 0;
 }
 
@@ -110,7 +110,7 @@ int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
                 return -EINVAL;
 
         ret = 0;
-        spin_lock_irqsave(&timer_data_lock, flags);
+        raw_spin_lock_irqsave(&timer_data_lock, flags);
         if (timer_data[id].cb) {
                 ret = -EBUSY;
                 goto out;
@@ -120,7 +120,7 @@ int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data)
         timer_data[id].data = data;
 
 out:
-        spin_unlock_irqrestore(&timer_data_lock, flags);
+        raw_spin_unlock_irqrestore(&timer_data_lock, flags);
         return ret;
 }
 
@@ -133,9 +133,9 @@ void bcm63xx_timer_unregister(int id)
         if (id >= BCM63XX_TIMER_COUNT)
                 return;
 
-        spin_lock_irqsave(&timer_data_lock, flags);
+        raw_spin_lock_irqsave(&timer_data_lock, flags);
         timer_data[id].cb = NULL;
-        spin_unlock_irqrestore(&timer_data_lock, flags);
+        raw_spin_unlock_irqrestore(&timer_data_lock, flags);
 }
 
 EXPORT_SYMBOL(bcm63xx_timer_unregister);
@@ -159,7 +159,7 @@ int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
         if (countdown & ~TIMER_CTL_COUNTDOWN_MASK)
                 return -EINVAL;
 
-        spin_lock_irqsave(&timer_reg_lock, flags);
+        raw_spin_lock_irqsave(&timer_reg_lock, flags);
         reg = bcm_timer_readl(TIMER_CTLx_REG(id));
 
         if (monotonic)
@@ -171,7 +171,7 @@ int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us)
         reg |= countdown;
         bcm_timer_writel(reg, TIMER_CTLx_REG(id));
 
-        spin_unlock_irqrestore(&timer_reg_lock, flags);
+        raw_spin_unlock_irqrestore(&timer_reg_lock, flags);
         return 0;
 }
 
diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index 9df903d714d7..790ddd397620 100644
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -9,7 +9,7 @@
 # modified by Cort (cort@cs.nmt.edu)
 #
 # Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University
-# Author: Wu Zhangjin <wuzj@lemote.com>
+# Author: Wu Zhangjin <wuzhangjin@gmail.com>
 #
 
 # compressed kernel load addr: VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE
@@ -27,15 +27,18 @@ BOOT_HEAP_SIZE := 0x400000
 KBUILD_CFLAGS := $(shell echo $(KBUILD_CFLAGS) | sed -e "s/-pg//")
 
 KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \
-        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull" \
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"VMLINUX_LOAD_ADDRESS_ULL=$(VMLINUX_LOAD_ADDRESS)ull"
 
 KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \
-        -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \
-        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE)
+        -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) \
+        -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ )
 
 obj-y := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o
 
+ifdef CONFIG_DEBUG_ZBOOT
 obj-$(CONFIG_SYS_SUPPORTS_ZBOOT_UART16550) += $(obj)/uart-16550.o
+obj-$(CONFIG_MACH_ALCHEMY)                 += $(obj)/uart-alchemy.o
+endif
 
 OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S
 $(obj)/vmlinux.bin: $(KBUILD_IMAGE)
diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c
index ff4dc7a33a9f..134a6162e394 100644
--- a/arch/mips/boot/compressed/dbg.c
+++ b/arch/mips/boot/compressed/dbg.c
@@ -5,11 +5,11 @@
  * please select SYS_SUPPORTS_ZBOOT_UART16550 for your machine. othewise, you
  * need to implement your own putc().
  */
-
+#include <linux/compiler.h>
 #include <linux/init.h>
 #include <linux/types.h>
 
-void __attribute__ ((weak)) putc(char c)
+void __weak putc(char c)
 {
 }
 
diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 55d02b3a6712..5db43c58b1bf 100644
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -5,8 +5,8 @@
  * Author: Matt Porter <mporter@mvista.com> Derived from
  * arch/ppc/boot/prep/misc.c
  *
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/boot/compressed/uart-alchemy.c b/arch/mips/boot/compressed/uart-alchemy.c
new file mode 100644
index 000000000000..1bff22fa089b
--- /dev/null
+++ b/arch/mips/boot/compressed/uart-alchemy.c
@@ -0,0 +1,7 @@
+#include <asm/mach-au1x00/au1000.h>
+
+void putc(char c)
+{
+        /* all current (Jan. 2010) in-kernel boards */
+        alchemy_uart_putchar(UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index 4b92bfc662db..be531ec1f206 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -41,7 +41,7 @@ struct bar1_index_state {
 };
 
 #ifdef CONFIG_PCI
-static DEFINE_SPINLOCK(bar1_lock);
+static DEFINE_RAW_SPINLOCK(bar1_lock);
 static struct bar1_index_state bar1_state[32];
 #endif
 
@@ -198,7 +198,7 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
                 start_index = 31;
 
         /* Only one processor can access the Bar register at once */
-        spin_lock_irqsave(&bar1_lock, flags);
+        raw_spin_lock_irqsave(&bar1_lock, flags);
 
         /* Look through Bar1 for existing mapping that will work */
         for (index = start_index; index >= 0; index--) {
@@ -250,7 +250,7 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
                (unsigned long long) physical);
 
 done_unlock:
-        spin_unlock_irqrestore(&bar1_lock, flags);
+        raw_spin_unlock_irqrestore(&bar1_lock, flags);
 done:
         pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
         return result;
@@ -324,14 +324,14 @@ void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
                       "Attempt to unmap an invalid address (0x%llx)\n",
                       dma_addr);
 
-        spin_lock_irqsave(&bar1_lock, flags);
+        raw_spin_lock_irqsave(&bar1_lock, flags);
         bar1_state[index].ref_count--;
         if (bar1_state[index].ref_count == 0)
                 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
         else if (unlikely(bar1_state[index].ref_count < 0))
                 panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
                       (int) index);
-        spin_unlock_irqrestore(&bar1_lock, flags);
+        raw_spin_unlock_irqrestore(&bar1_lock, flags);
 done:
         pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
         return;
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 25666da17b22..fdf5f19bfdb0 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -253,7 +253,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
          * impossible requests up front. (NOP for address_min == 0)
          */
         if (alignment)
-                address_min = __ALIGN_MASK(address_min, (alignment - 1));
+                address_min = ALIGN(address_min, alignment);
 
         /*
          * Reject inconsistent args.  We have adjusted these, so this
@@ -291,7 +291,7 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
                  * satisfy request.
                  */
                 usable_base =
-                    __ALIGN_MASK(max(address_min, ent_addr), alignment - 1);
+                    ALIGN(max(address_min, ent_addr), alignment);
                 usable_max = min(address_max, ent_addr + ent_size);
                 /*
                  * We should be able to allocate block at address
@@ -671,7 +671,7 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
          * coallesced when they are freed.  The alloc routine does the
          * same rounding up on all allocations.
          */
-        size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1));
+        size = ALIGN(size, CVMX_BOOTMEM_ALIGNMENT_SIZE);
 
         addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr,
                                                 alignment,
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
index e5838890cba5..8b18a20cc7b3 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -115,4 +115,3 @@ int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
 
         return 1;
 }
-
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 6f2acf09328d..c424cd158dc6 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -13,9 +13,8 @@
 #include <asm/octeon/cvmx-pexp-defs.h>
 #include <asm/octeon/cvmx-npi-defs.h>
 
-DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
-DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
-DEFINE_SPINLOCK(octeon_irq_msi_lock);
+static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
+static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
 
 static int octeon_coreid_for_cpu(int cpu)
 {
@@ -51,9 +50,6 @@ static void octeon_irq_core_eoi(unsigned int irq)
          */
         if (desc->status & IRQ_DISABLED)
                 return;
-
-        /* There is a race here.  We should fix it.  */
-
         /*
          * We don't need to disable IRQs to make these atomic since
          * they are already disabled earlier in the low level
@@ -141,19 +137,12 @@ static void octeon_irq_ciu0_enable(unsigned int irq)
         uint64_t en0;
         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
 
-        /*
-         * A read lock is used here to make sure only one core is ever
-         * updating the CIU enable bits at a time. During an enable
-         * the cores don't interfere with each other. During a disable
-         * the write lock stops any enables that might cause a
-         * problem.
-         */
-        read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
+        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
         en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
         en0 |= 1ull << bit;
         cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
         cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-        read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
 }
 
 static void octeon_irq_ciu0_disable(unsigned int irq)
@@ -162,7 +151,7 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
         unsigned long flags;
         uint64_t en0;
         int cpu;
-        write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
+        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
@@ -174,7 +163,7 @@ static void octeon_irq_ciu0_disable(unsigned int irq)
          * of them are done.
          */
         cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
-        write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
 }
 
 /*
@@ -193,7 +182,7 @@ static void octeon_irq_ciu0_enable_v2(unsigned int irq)
  * Disable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu0_disable_v2(unsigned int irq)
+static void octeon_irq_ciu0_ack_v2(unsigned int irq)
 {
         int index = cvmx_get_core_num() * 2;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
@@ -202,6 +191,43 @@ static void octeon_irq_ciu0_disable_v2(unsigned int irq)
 }
 
 /*
+ * CIU timer type interrupts must be acknoleged by writing a '1' bit
+ * to their sum0 bit.
+ */
+static void octeon_irq_ciu0_timer_ack(unsigned int irq)
+{
+        int index = cvmx_get_core_num() * 2;
+        uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+        cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
+}
+
+static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
+{
+        octeon_irq_ciu0_timer_ack(irq);
+        octeon_irq_ciu0_ack(irq);
+}
+
+static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
+{
+        octeon_irq_ciu0_timer_ack(irq);
+        octeon_irq_ciu0_ack_v2(irq);
+}
+
+/*
+ * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu0_eoi_v2(unsigned int irq)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        int index = cvmx_get_core_num() * 2;
+        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+
+        if ((desc->status & IRQ_DISABLED) == 0)
+                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+}
+
+/*
  * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
  * registers.
  */
@@ -223,7 +249,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
         unsigned long flags;
         int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
 
-        write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
+        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 uint64_t en0 =
@@ -239,7 +265,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
          * of them are done.
          */
         cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
-        write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
 
         return 0;
 }
@@ -272,8 +298,8 @@ static struct irq_chip octeon_irq_chip_ciu0_v2 = {
         .name = "CIU0",
         .enable = octeon_irq_ciu0_enable_v2,
         .disable = octeon_irq_ciu0_disable_all_v2,
-        .ack = octeon_irq_ciu0_disable_v2,
-        .eoi = octeon_irq_ciu0_enable_v2,
+        .ack = octeon_irq_ciu0_ack_v2,
+        .eoi = octeon_irq_ciu0_eoi_v2,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu0_set_affinity_v2,
 #endif
@@ -290,6 +316,28 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
 #endif
 };
 
+static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
+        .name = "CIU0-T",
+        .enable = octeon_irq_ciu0_enable_v2,
+        .disable = octeon_irq_ciu0_disable_all_v2,
+        .ack = octeon_irq_ciu0_timer_ack_v2,
+        .eoi = octeon_irq_ciu0_eoi_v2,
+#ifdef CONFIG_SMP
+        .set_affinity = octeon_irq_ciu0_set_affinity_v2,
+#endif
+};
+
+static struct irq_chip octeon_irq_chip_ciu0_timer = {
+        .name = "CIU0-T",
+        .enable = octeon_irq_ciu0_enable,
+        .disable = octeon_irq_ciu0_disable,
+        .ack = octeon_irq_ciu0_timer_ack_v1,
+        .eoi = octeon_irq_ciu0_eoi,
+#ifdef CONFIG_SMP
+        .set_affinity = octeon_irq_ciu0_set_affinity,
+#endif
+};
+
 
 static void octeon_irq_ciu1_ack(unsigned int irq)
 {
@@ -322,19 +370,12 @@ static void octeon_irq_ciu1_enable(unsigned int irq)
         uint64_t en1;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
 
-        /*
-         * A read lock is used here to make sure only one core is ever
-         * updating the CIU enable bits at a time.  During an enable
-         * the cores don't interfere with each other.  During a disable
-         * the write lock stops any enables that might cause a
-         * problem.
-         */
-        read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
+        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
         en1 |= 1ull << bit;
         cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
         cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
-        read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
 }
 
 static void octeon_irq_ciu1_disable(unsigned int irq)
@@ -343,7 +384,7 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
         unsigned long flags;
         uint64_t en1;
         int cpu;
-        write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
+        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
@@ -355,7 +396,7 @@ static void octeon_irq_ciu1_disable(unsigned int irq)
          * of them are done.
          */
         cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
-        write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
 }
 
 /*
@@ -374,7 +415,7 @@ static void octeon_irq_ciu1_enable_v2(unsigned int irq)
  * Disable the irq on the current core for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu1_disable_v2(unsigned int irq)
+static void octeon_irq_ciu1_ack_v2(unsigned int irq)
 {
         int index = cvmx_get_core_num() * 2 + 1;
         u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
@@ -383,6 +424,20 @@ static void octeon_irq_ciu1_disable_v2(unsigned int irq)
 }
 
 /*
+ * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * registers.
+ */
+static void octeon_irq_ciu1_eoi_v2(unsigned int irq)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        int index = cvmx_get_core_num() * 2 + 1;
+        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
+
+        if ((desc->status & IRQ_DISABLED) == 0)
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+}
+
+/*
  * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
  * registers.
  */
@@ -405,7 +460,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
         unsigned long flags;
         int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
 
-        write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
+        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
         for_each_online_cpu(cpu) {
                 int coreid = octeon_coreid_for_cpu(cpu);
                 uint64_t en1 =
@@ -422,7 +477,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq,
          * of them are done.
          */
         cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
-        write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
+        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
 
         return 0;
 }
@@ -455,8 +510,8 @@ static struct irq_chip octeon_irq_chip_ciu1_v2 = {
         .name = "CIU0",
         .enable = octeon_irq_ciu1_enable_v2,
         .disable = octeon_irq_ciu1_disable_all_v2,
-        .ack = octeon_irq_ciu1_disable_v2,
-        .eoi = octeon_irq_ciu1_enable_v2,
+        .ack = octeon_irq_ciu1_ack_v2,
+        .eoi = octeon_irq_ciu1_eoi_v2,
 #ifdef CONFIG_SMP
         .set_affinity = octeon_irq_ciu1_set_affinity_v2,
 #endif
@@ -475,6 +530,8 @@ static struct irq_chip octeon_irq_chip_ciu1 = {
 
 #ifdef CONFIG_PCI_MSI
 
+static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
+
 static void octeon_irq_msi_ack(unsigned int irq)
 {
         if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
@@ -515,12 +572,12 @@ static void octeon_irq_msi_enable(unsigned int irq)
                  */
                 uint64_t en;
                 unsigned long flags;
-                spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+                raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
                 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
                 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
                 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+                raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
         }
 }
 
@@ -537,12 +594,12 @@ static void octeon_irq_msi_disable(unsigned int irq)
                  */
                 uint64_t en;
                 unsigned long flags;
-                spin_lock_irqsave(&octeon_irq_msi_lock, flags);
+                raw_spin_lock_irqsave(&octeon_irq_msi_lock, flags);
                 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
                 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
                 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
                 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
-                spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
+                raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
         }
 }
 
@@ -559,6 +616,7 @@ void __init arch_init_irq(void)
 {
         int irq;
         struct irq_chip *chip0;
+        struct irq_chip *chip0_timer;
         struct irq_chip *chip1;
 
 #ifdef CONFIG_SMP
@@ -574,9 +632,11 @@ void __init arch_init_irq(void)
             OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
             OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
                 chip0 = &octeon_irq_chip_ciu0_v2;
+                chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
                 chip1 = &octeon_irq_chip_ciu1_v2;
         } else {
                 chip0 = &octeon_irq_chip_ciu0;
+                chip0_timer = &octeon_irq_chip_ciu0_timer;
                 chip1 = &octeon_irq_chip_ciu1;
         }
 
@@ -590,7 +650,21 @@ void __init arch_init_irq(void)
 
         /* 24 - 87 CIU_INT_SUM0 */
         for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
-                set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
+                switch (irq) {
+                case OCTEON_IRQ_GMX_DRP0:
+                case OCTEON_IRQ_GMX_DRP1:
+                case OCTEON_IRQ_IPD_DRP:
+                case OCTEON_IRQ_KEY_ZERO:
+                case OCTEON_IRQ_TIMER0:
+                case OCTEON_IRQ_TIMER1:
+                case OCTEON_IRQ_TIMER2:
+                case OCTEON_IRQ_TIMER3:
+                        set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
+                        break;
+                default:
+                        set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
+                        break;
+                }
         }
 
         /* 88 - 151 CIU_INT_SUM1 */
diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index cfdb4c2ac5c3..62ac30eef5e8 100644
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -9,6 +9,7 @@
 
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/i2c.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
@@ -159,6 +160,90 @@ out:
 }
 device_initcall(octeon_rng_device_init);
 
+static struct i2c_board_info __initdata octeon_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+        },
+};
+
+static int __init octeon_i2c_devices_init(void)
+{
+        return i2c_register_board_info(0, octeon_i2c_devices,
+                                       ARRAY_SIZE(octeon_i2c_devices));
+}
+arch_initcall(octeon_i2c_devices_init);
+
+#define OCTEON_I2C_IO_BASE 0x1180000001000ull
+#define OCTEON_I2C_IO_UNIT_OFFSET 0x200
+
+static struct octeon_i2c_data octeon_i2c_data[2];
+
+static int __init octeon_i2c_device_init(void)
+{
+        struct platform_device *pd;
+        int ret = 0;
+        int port, num_ports;
+
+        struct resource i2c_resources[] = {
+                {
+                        .flags  = IORESOURCE_MEM,
+                }, {
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX))
+                num_ports = 2;
+        else
+                num_ports = 1;
+
+        for (port = 0; port < num_ports; port++) {
+                octeon_i2c_data[port].sys_freq = octeon_get_clock_rate();
+                /*FIXME: should be examined. At the moment is set for 100Khz */
+                octeon_i2c_data[port].i2c_freq = 100000;
+
+                pd = platform_device_alloc("i2c-octeon", port);
+                if (!pd) {
+                        ret = -ENOMEM;
+                        goto out;
+                }
+
+                pd->dev.platform_data = octeon_i2c_data + port;
+
+                i2c_resources[0].start =
+                        OCTEON_I2C_IO_BASE + (port * OCTEON_I2C_IO_UNIT_OFFSET);
+                i2c_resources[0].end = i2c_resources[0].start + 0x1f;
+                switch (port) {
+                case 0:
+                        i2c_resources[1].start = OCTEON_IRQ_TWSI;
+                        i2c_resources[1].end = OCTEON_IRQ_TWSI;
+                        break;
+                case 1:
+                        i2c_resources[1].start = OCTEON_IRQ_TWSI2;
+                        i2c_resources[1].end = OCTEON_IRQ_TWSI2;
+                        break;
+                default:
+                        BUG();
+                }
+
+                ret = platform_device_add_resources(pd,
+                                                    i2c_resources,
+                                                    ARRAY_SIZE(i2c_resources));
+                if (ret)
+                        goto fail;
+
+                ret = platform_device_add(pd);
+                if (ret)
+                        goto fail;
+        }
+        return ret;
+fail:
+        platform_device_put(pd);
+out:
+        return ret;
+}
+device_initcall(octeon_i2c_device_init);
+
 /* Octeon SMI/MDIO interface.  */
 static int __init octeon_mdiobus_device_init(void)
 {
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index c198efdf583e..51e980290ce1 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -327,7 +327,7 @@ static void octeon_cpu_die(unsigned int cpu)
                                    avail_coremask);
         }
 
-        pr_info("Reset core %d. Available Coremask = %x \n", coreid,
+        pr_info("Reset core %d. Available Coremask = %x\n", coreid,
                 avail_coremask);
         cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
         cvmx_write_csr(CVMX_CIU_PP_RST, 0);
diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c
index cfce7af1bca9..85ec9cc31d66 100644
--- a/arch/mips/cobalt/pci.c
+++ b/arch/mips/cobalt/pci.c
@@ -25,7 +25,7 @@ static struct resource cobalt_mem_resource = {
 
 static struct resource cobalt_io_resource = {
         .start  = 0x1000,
-        .end    = GT_DEF_PCI0_IO_SIZE - 1,
+        .end    = 0xffffffUL,
         .name   = "PCI I/O",
         .flags  = IORESOURCE_IO,
 };
diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig
index 68e90cd6b2d4..f66d406aadce 100644
--- a/arch/mips/configs/db1000_defconfig
+++ b/arch/mips/configs/db1000_defconfig
@@ -1,78 +1,102 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:24 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 08:46:14 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-CONFIG_MIPS_DB1000=y
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+CONFIG_MIPS_DB1000=y
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1000=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1000=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -85,6 +109,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -92,11 +117,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -106,184 +134,244 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-db1000"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
+# CONFIG_PCMCIA_IOCTL is not set
 
 #
 # PC-card bridges
 #
 # CONFIG_PCMCIA_AU1X00 is not set
-
-#
-# PCI Hotplug Support
-#
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -294,110 +382,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -407,27 +410,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -436,25 +436,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -467,6 +467,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -492,14 +493,13 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -516,174 +516,115 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Plug and Play support
+# UBI - Unsorted block images
 #
-# CONFIG_PNPACPI is not set
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
 
 #
-# Block devices
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 # CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-
-#
-# Misc devices
-#
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
-#
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_PCMCIA_AXNET=m
-
-#
-# Wan interfaces
-#
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
 # CONFIG_WAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -691,16 +632,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -710,35 +649,33 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_CS=m
+# CONFIG_SERIAL_8250_CS is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
@@ -750,198 +687,291 @@ CONFIG_SERIAL_8250_AU1X00=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
 # PCMCIA character devices
 #
-CONFIG_SYNCLINK_CS=m
+# CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
-# CONFIG_SOUND is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
+# Console display driver support
 #
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Miscellaneous USB options
 #
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# USB Gadget Support
+# USB Host Controller Drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# MMC/SD Card support
+# USB Device Class drivers
 #
-# CONFIG_MMC is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# LED devices
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-# CONFIG_NEW_LEDS is not set
 
 #
-# LED drivers
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# LED Triggers
+# USB Imaging devices
 #
+# CONFIG_USB_MDC800 is not set
 
 #
-# InfiniBand support
+# USB port drivers
 #
+# CONFIG_USB_SERIAL is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# USB Miscellaneous drivers
 #
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
 
 #
-# Real Time Clock
+# OTG and related infrastructure
 #
-# CONFIG_RTC_CLASS is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# DMA Engine support
+# RTC interfaces
 #
-# CONFIG_DMA_ENGINE is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
 CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -960,74 +990,65 @@ CONFIG_GENERIC_ACL=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
+CONFIG_NLS_CODEPAGE_850=y
 # CONFIG_NLS_CODEPAGE_852 is not set
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
@@ -1045,10 +1066,10 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1250=y
 # CONFIG_NLS_CODEPAGE_1251 is not set
 # CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1058,38 +1079,75 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1097,67 +1155,29 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
index 90812830e940..abb9a5805adc 100644
--- a/arch/mips/configs/db1100_defconfig
+++ b/arch/mips/configs/db1100_defconfig
@@ -1,78 +1,102 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:24 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 08:50:15 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-CONFIG_MIPS_DB1100=y
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+CONFIG_MIPS_DB1100=y
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1100=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -85,6 +109,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -92,11 +117,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -106,173 +134,242 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-db1100"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
-CONFIG_SLAB=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_MMU=y
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+# CONFIG_PCMCIA_IOCTL is not set
 
 #
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# PCI Hotplug Support
+# PC-card bridges
 #
+# CONFIG_PCMCIA_AU1X00 is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -283,110 +380,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -396,27 +408,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -425,25 +434,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -456,6 +465,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -481,14 +491,13 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -505,161 +514,123 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
+# UBI - Unsorted block images
 #
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
 
 #
-# Misc devices
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_IDE_PROC_FS=y
 
 #
-# ATA/ATAPI/MFM/RLL support
+# IDE chipset support/bugfixes
 #
-# CONFIG_IDE is not set
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
 # CONFIG_WAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -667,16 +638,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -686,34 +655,33 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=m
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
@@ -725,78 +693,91 @@ CONFIG_SERIAL_8250_AU1X00=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
 
 #
-# TPM devices
+# PCMCIA character devices
 #
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_AU1100=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
@@ -804,9 +785,10 @@ CONFIG_FB_AU1100=y
 # CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
+# CONFIG_FONT_8x8 is not set
 CONFIG_FONT_8x16=y
 # CONFIG_FONT_6x11 is not set
 # CONFIG_FONT_7x14 is not set
@@ -816,132 +798,186 @@ CONFIG_FONT_8x16=y
 # CONFIG_FONT_SUN8x16 is not set
 # CONFIG_FONT_SUN12x22 is not set
 # CONFIG_FONT_10x18 is not set
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
+# CONFIG_LOGO is not set
 # CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
-#
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Miscellaneous USB options
 #
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# USB Gadget Support
+# USB Host Controller Drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# MMC/SD Card support
+# USB Device Class drivers
 #
-# CONFIG_MMC is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# LED devices
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-# CONFIG_NEW_LEDS is not set
 
 #
-# LED drivers
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# LED Triggers
+# USB Imaging devices
 #
+# CONFIG_USB_MDC800 is not set
 
 #
-# InfiniBand support
+# USB port drivers
 #
+# CONFIG_USB_SERIAL is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# USB Miscellaneous drivers
 #
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
 
 #
-# Real Time Clock
+# OTG and related infrastructure
 #
-# CONFIG_RTC_CLASS is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# DMA Engine support
+# RTC interfaces
 #
-# CONFIG_DMA_ENGINE is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -960,69 +996,76 @@ CONFIG_GENERIC_ACL=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
 # CONFIG_NLS_CODEPAGE_737 is not set
@@ -1062,34 +1105,71 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1097,67 +1177,32 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index dabf03032e06..991c20adf471 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -1,78 +1,102 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:25 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 10:18:09 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-CONFIG_MIPS_DB1200=y
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+CONFIG_MIPS_DB1200=y
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1200=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_COHERENT=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1200=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -85,6 +109,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -92,11 +117,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -106,180 +134,235 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-db1200"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED=y
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
 # CONFIG_RELAY is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
+# CONFIG_PCMCIA_IOCTL is not set
 
 #
 # PC-card bridges
 #
-CONFIG_PCMCIA_AU1X00=m
-
-#
-# PCI Hotplug Support
-#
+# CONFIG_PCMCIA_AU1X00 is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_MISC is not set
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=y
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
 # CONFIG_PM is not set
-
-#
-# Networking
-#
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -290,107 +373,25 @@ CONFIG_IP_FIB_HASH=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK is not set
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -400,21 +401,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -423,25 +427,25 @@ CONFIG_NET_CLS_ROUTE=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
 # CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -454,6 +458,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -479,19 +484,21 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -503,224 +510,134 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_AU1550 is not set
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
 
 #
-# Misc devices
-#
-
-#
-# ATA/ATAPI/MFM/RLL support
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_UB=y
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_IDEDISK_MULTI_MODE=y
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_IDECD is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
 CONFIG_BLK_DEV_IDE_AU1XXX=y
 CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y
 # CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set
-CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128
-# CONFIG_IDE_ARM is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
 # CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=m
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-CONFIG_BLK_DEV_SR=y
-# CONFIG_BLK_DEV_SR_VENDOR is not set
-CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-CONFIG_SCSI_SCAN_ASYNC=y
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
+# CONFIG_VETH is not set
 # CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 # CONFIG_MIPS_AU1X00_ENET is not set
-# CONFIG_SMC91X is not set
+CONFIG_SMC91X=y
 # CONFIG_DM9000 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
-#
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -728,16 +645,14 @@ CONFIG_MII=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -747,28 +662,26 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=y
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
 
 #
 # Serial drivers
@@ -776,33 +689,22 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 # CONFIG_SERIAL_8250_CS is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
 # CONFIG_SERIAL_8250_EXTENDED is not set
 CONFIG_SERIAL_8250_AU1X00=y
 
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
@@ -811,223 +713,624 @@ CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
 
 #
-# TPM devices
+# I2C Algorithms
 #
-# CONFIG_TCG_TPM is not set
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C support
+# I2C Hardware Bus support
 #
-# CONFIG_I2C is not set
 
 #
-# SPI support
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+CONFIG_I2C_AU1550=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
 
 #
-# Dallas's 1-wire bus
+# External I2C/SMBus adapter drivers
 #
-# CONFIG_W1 is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
-# Hardware Monitoring support
+# Other I2C/SMBus bus drivers
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
 
 #
-# Multimedia devices
+# Miscellaneous I2C Chip support
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
 
 #
-# Digital Video Broadcasting Devices
+# SPI Master Controller Drivers
 #
-# CONFIG_DVB is not set
+CONFIG_SPI_AU1550=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+CONFIG_SENSORS_ADM1025=y
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+CONFIG_SENSORS_LM70=y
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_AB4500_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
 # CONFIG_FB_MODE_HELPERS is not set
 # CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
 # CONFIG_FB_S1D13XXX is not set
 CONFIG_FB_AU1200=y
 # CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
 # Console display driver support
 #
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+# CONFIG_VGA_CONSOLE is not set
 CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AU1XPSC=y
+CONFIG_SND_SOC_AU1XPSC_I2S=y
+CONFIG_SND_SOC_AU1XPSC_AC97=y
+CONFIG_SND_SOC_DB1200=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_WM8731=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 
 #
-# Logo configuration
+# Miscellaneous USB options
 #
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# Sound
+# USB Host Controller Drivers
 #
-# CONFIG_SOUND is not set
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# HID Devices
+# USB Device Class drivers
 #
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# USB support
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Gadget Support
+# USB Imaging devices
 #
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_MDC800 is not set
 
 #
-# MMC/SD Card support
+# USB port drivers
 #
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_AU1X=y
+# CONFIG_MMC_UNSAFE_RESUME is not set
 
 #
-# LED devices
+# MMC/SD/SDIO Card Drivers
 #
-# CONFIG_NEW_LEDS is not set
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
 
 #
-# LED drivers
+# MMC/SD/SDIO Host Controller Drivers
 #
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AU1X=y
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 
 #
-# LED Triggers
+# LED drivers
 #
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
 
 #
-# InfiniBand support
+# LED Triggers
 #
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# iptables trigger is under Netfilter config (LED target)
 #
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# Real Time Clock
+# RTC interfaces
 #
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Engine support
+# I2C RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
-CONFIG_JFS_FS=y
-# CONFIG_JFS_POSIX_ACL is not set
-# CONFIG_JFS_SECURITY is not set
-# CONFIG_JFS_DEBUG is not set
-# CONFIG_JFS_STATISTICS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_FUSE_FS is not set
-CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
 #
-CONFIG_ISO9660_FS=m
+CONFIG_ISO9660_FS=y
 CONFIG_JOLIET=y
 CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
+CONFIG_UDF_FS=y
 CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
 #
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
@@ -1036,21 +1339,17 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
@@ -1059,27 +1358,36 @@ CONFIG_CONFIGFS_FS=m
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
 # CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
 CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
 CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
+CONFIG_ROOT_NFS=y
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
@@ -1087,93 +1395,140 @@ CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=y
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+CONFIG_NLS_CODEPAGE_1250=y
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 CONFIG_CMDLINE_BOOL=y
-CONFIG_CMDLINE="mem=48M"
+CONFIG_CMDLINE="console=ttyS0,115200"
 # CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1181,67 +1536,32 @@ CONFIG_CMDLINE="mem=48M"
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
 # CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
index a15131373138..5424c9167bf2 100644
--- a/arch/mips/configs/db1500_defconfig
+++ b/arch/mips/configs/db1500_defconfig
@@ -1,80 +1,104 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:26 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 08:46:33 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-CONFIG_MIPS_DB1500=y
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+CONFIG_MIPS_DB1500=y
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1500=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -87,6 +111,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -94,11 +119,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -108,137 +136,207 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-db1500"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
 CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_LEGACY is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-CONFIG_CARDBUS=y
+# CONFIG_PCMCIA_IOCTL is not set
+# CONFIG_CARDBUS is not set
 
 #
 # PC-card bridges
@@ -246,51 +344,49 @@ CONFIG_CARDBUS=y
 # CONFIG_YENTA is not set
 # CONFIG_PD6729 is not set
 # CONFIG_I82092 is not set
-CONFIG_PCMCIA_AU1X00=m
-
-#
-# PCI Hotplug Support
-#
+# CONFIG_PCMCIA_AU1X00 is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 # CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -301,110 +397,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -414,27 +425,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -443,25 +451,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -474,6 +482,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -499,14 +508,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -524,152 +533,152 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
+# LPDDR flash memory drivers
 #
-# CONFIG_PNPACPI is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
 # CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=m
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_XFER_MODE=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_DELKIN is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
 # CONFIG_BLK_DEV_IDECD is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
 # CONFIG_IDE_GENERIC is not set
-# CONFIG_BLK_DEV_IDEPCI is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+CONFIG_BLK_DEV_HPT366=y
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+CONFIG_BLK_DEV_IDEDMA=y
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# You can enable one or both FireWire driver stacks.
 #
-# CONFIG_I2O is not set
 
 #
-# Network device support
+# The newer stack is recommended.
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
@@ -677,88 +686,51 @@ CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=m
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=m
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
+# CONFIG_WLAN is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_NET_RADIO is not set
 
 #
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -766,16 +738,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -785,33 +755,34 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI is not set
 # CONFIG_SERIAL_8250_CS is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
@@ -825,301 +796,143 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 
 #
 # PCMCIA character devices
 #
-CONFIG_SYNCLINK_CS=m
+# CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
-#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_SEQUENCER_OSS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DUMMY is not set
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# PCI devices
-#
-# CONFIG_SND_AD1889 is not set
-# CONFIG_SND_ALS300 is not set
-# CONFIG_SND_ALI5451 is not set
-# CONFIG_SND_ATIIXP is not set
-# CONFIG_SND_ATIIXP_MODEM is not set
-# CONFIG_SND_AU8810 is not set
-# CONFIG_SND_AU8820 is not set
-# CONFIG_SND_AU8830 is not set
-# CONFIG_SND_AZT3328 is not set
-# CONFIG_SND_BT87X is not set
-# CONFIG_SND_CA0106 is not set
-# CONFIG_SND_CMIPCI is not set
-# CONFIG_SND_CS4281 is not set
-# CONFIG_SND_CS46XX is not set
-# CONFIG_SND_DARLA20 is not set
-# CONFIG_SND_GINA20 is not set
-# CONFIG_SND_LAYLA20 is not set
-# CONFIG_SND_DARLA24 is not set
-# CONFIG_SND_GINA24 is not set
-# CONFIG_SND_LAYLA24 is not set
-# CONFIG_SND_MONA is not set
-# CONFIG_SND_MIA is not set
-# CONFIG_SND_ECHO3G is not set
-# CONFIG_SND_INDIGO is not set
-# CONFIG_SND_INDIGOIO is not set
-# CONFIG_SND_INDIGODJ is not set
-# CONFIG_SND_EMU10K1 is not set
-# CONFIG_SND_EMU10K1X is not set
-# CONFIG_SND_ENS1370 is not set
-# CONFIG_SND_ENS1371 is not set
-# CONFIG_SND_ES1938 is not set
-# CONFIG_SND_ES1968 is not set
-# CONFIG_SND_FM801 is not set
-# CONFIG_SND_HDA_INTEL is not set
-# CONFIG_SND_HDSP is not set
-# CONFIG_SND_HDSPM is not set
-# CONFIG_SND_ICE1712 is not set
-# CONFIG_SND_ICE1724 is not set
-# CONFIG_SND_INTEL8X0 is not set
-# CONFIG_SND_INTEL8X0M is not set
-# CONFIG_SND_KORG1212 is not set
-# CONFIG_SND_MAESTRO3 is not set
-# CONFIG_SND_MIXART is not set
-# CONFIG_SND_NM256 is not set
-# CONFIG_SND_PCXHR is not set
-# CONFIG_SND_RIPTIDE is not set
-# CONFIG_SND_RME32 is not set
-# CONFIG_SND_RME96 is not set
-# CONFIG_SND_RME9652 is not set
-# CONFIG_SND_SONICVIBES is not set
-# CONFIG_SND_TRIDENT is not set
-# CONFIG_SND_VIA82XX is not set
-# CONFIG_SND_VIA82XX_MODEM is not set
-# CONFIG_SND_VX222 is not set
-# CONFIG_SND_YMFPCI is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-
-#
-# ALSA MIPS devices
-#
-CONFIG_SND_AU1X00=m
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-
-#
-# PCMCIA devices
-#
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
-
-#
-# SoC audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# Open Sound System
-#
-CONFIG_SOUND_PRIME=y
-# CONFIG_OBSOLETE_OSS is not set
-# CONFIG_SOUND_BT878 is not set
-# CONFIG_SOUND_ICH is not set
-# CONFIG_SOUND_TRIDENT is not set
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_VIA82CXXX is not set
-CONFIG_AC97_BUS=m
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB support
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
 #
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
 CONFIG_USB=y
 # CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
 # Miscellaneous USB options
 #
 # CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
 # CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
 # USB Host Controller Drivers
 #
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
 # CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
 # CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
 CONFIG_USB_OHCI_HCD=y
 # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
 # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
 CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 # CONFIG_USB_UHCI_HCD is not set
 # CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
 # USB Device Class drivers
 #
 # CONFIG_USB_ACM is not set
 # CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
 
 #
-# may also be needed; see USB_STORAGE Help for more information
+# also be needed; see USB_STORAGE Help for more info
 #
 # CONFIG_USB_LIBUSUAL is not set
 
 #
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-CONFIG_USB_YEALINK=m
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
-#
 # USB Imaging devices
 #
 # CONFIG_USB_MDC800 is not set
 
 #
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_USB_MON=y
-
-#
 # USB port drivers
 #
-
-#
-# USB Serial Converter support
-#
 # CONFIG_USB_SERIAL is not set
 
 #
@@ -1128,7 +941,7 @@ CONFIG_USB_MON=y
 # CONFIG_USB_EMI62 is not set
 # CONFIG_USB_EMI26 is not set
 # CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_SEVSEG is not set
 # CONFIG_USB_RIO500 is not set
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
@@ -1136,112 +949,107 @@ CONFIG_USB_MON=y
 # CONFIG_USB_LED is not set
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
 # CONFIG_USB_IDMOUSE is not set
 # CONFIG_USB_FTDI_ELAN is not set
 # CONFIG_USB_APPLEDISPLAY is not set
-CONFIG_USB_LD=m
+# CONFIG_USB_LD is not set
 # CONFIG_USB_TRANCEVIBRATOR is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
 # CONFIG_USB_GADGET is not set
 
 #
-# MMC/SD Card support
+# OTG and related infrastructure
 #
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
 # CONFIG_MMC is not set
-
-#
-# LED devices
-#
+# CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# InfiniBand support
-#
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
-#
-
-#
-# Real Time Clock
+# RTC interfaces
 #
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Engine support
+# SPI RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
 
 #
-# DMA Clients
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# DMA Devices
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Auxiliary Display support
-#
-
-#
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1260,74 +1068,81 @@ CONFIG_GENERIC_ACL=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
+CONFIG_NLS_CODEPAGE_850=y
 # CONFIG_NLS_CODEPAGE_852 is not set
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
@@ -1345,10 +1160,10 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1250=y
 # CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1358,38 +1173,76 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1397,67 +1250,32 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
index 6b64339c0014..949b6dcf634b 100644
--- a/arch/mips/configs/db1550_defconfig
+++ b/arch/mips/configs/db1550_defconfig
@@ -1,79 +1,103 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:27 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 08:58:22 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-CONFIG_MIPS_DB1550=y
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+CONFIG_MIPS_DB1550=y
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1550=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -86,6 +110,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -93,11 +118,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -107,137 +135,205 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-db1550"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-CONFIG_CARDBUS=y
+# CONFIG_PCMCIA_IOCTL is not set
+# CONFIG_CARDBUS is not set
 
 #
 # PC-card bridges
@@ -245,51 +341,49 @@ CONFIG_CARDBUS=y
 # CONFIG_YENTA is not set
 # CONFIG_PD6729 is not set
 # CONFIG_I82092 is not set
-CONFIG_PCMCIA_AU1X00=m
-
-#
-# PCI Hotplug Support
-#
+# CONFIG_PCMCIA_AU1X00 is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 # CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -300,110 +394,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -413,27 +422,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -442,25 +448,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -473,6 +479,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -498,20 +505,23 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
 # CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -523,105 +533,96 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_VERIFY_WRITE is not set
 # CONFIG_MTD_NAND_ECC_SMC is not set
-CONFIG_MTD_NAND_IDS=m
-CONFIG_MTD_NAND_AU1550=m
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_AU1550=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
 # CONFIG_MTD_NAND_CAFE is not set
 # CONFIG_MTD_NAND_NANDSIM is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 # CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=m
-# CONFIG_TIFM_CORE is not set
+# CONFIG_BLK_DEV_LOOP is not set
 
 #
-# ATA/ATAPI/MFM/RLL support
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=y
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_DELKIN is not set
-# CONFIG_BLK_DEV_IDECD is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
 CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
 # CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_GENERIC is not set
 # CONFIG_BLK_DEV_OPTI621 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_PCI_AUTO is not set
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_BLK_DEV_ALI15X3 is not set
 # CONFIG_BLK_DEV_AMD74XX is not set
 # CONFIG_BLK_DEV_CMD64X is not set
 # CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
 # CONFIG_BLK_DEV_CS5520 is not set
 # CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
-# CONFIG_BLK_DEV_HPT366 is not set
+CONFIG_BLK_DEV_HPT366=y
 # CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
-CONFIG_BLK_DEV_IT8213=m
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
 # CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
@@ -631,82 +632,65 @@ CONFIG_BLK_DEV_IT8213=m
 # CONFIG_BLK_DEV_SLC90E66 is not set
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
-CONFIG_BLK_DEV_TC86C001=m
-# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
 CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# You can enable one or both FireWire driver stacks.
 #
-# CONFIG_I2O is not set
 
 #
-# Network device support
+# The newer stack is recommended.
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
@@ -714,96 +698,53 @@ CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=m
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=m
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
+# CONFIG_WLAN is not set
 
 #
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_PCMCIA_AXNET=m
 
 #
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -811,16 +752,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -830,26 +769,27 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
@@ -866,199 +806,420 @@ CONFIG_SERIAL_8250_AU1X00=y
 #
 # Non-8250 serial port support
 #
+# CONFIG_SERIAL_MAX3100 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 
 #
 # PCMCIA character devices
 #
-CONFIG_SYNCLINK_CS=m
+# CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
 
 #
-# TPM devices
+# I2C Algorithms
 #
-# CONFIG_TCG_TPM is not set
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C support
+# I2C Hardware Bus support
 #
-# CONFIG_I2C is not set
 
 #
-# SPI support
+# PC SMBus host controller drivers
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
 
 #
-# Dallas's 1-wire bus
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-# CONFIG_W1 is not set
+CONFIG_I2C_AU1550=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
 
 #
-# Hardware Monitoring support
+# External I2C/SMBus adapter drivers
 #
-# CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
-# Multimedia devices
+# Other I2C/SMBus bus drivers
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Miscellaneous I2C Chip support
 #
-# CONFIG_DVB is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
 
 #
-# Graphics support
+# SPI Master Controller Drivers
 #
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+CONFIG_SPI_AU1550=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
 
 #
-# Sound
+# SPI Protocol Masters
 #
-# CONFIG_SOUND is not set
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 
 #
-# HID Devices
+# PPS support
 #
-# CONFIG_HID is not set
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# USB support
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_AB4500_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
 #
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AU1XPSC=y
+# CONFIG_SND_SOC_DB1200 is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Miscellaneous USB options
 #
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# USB Gadget Support
+# USB Host Controller Drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# MMC/SD Card support
+# USB Device Class drivers
 #
-# CONFIG_MMC is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# LED devices
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-# CONFIG_NEW_LEDS is not set
 
 #
-# LED drivers
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# LED Triggers
+# USB Imaging devices
 #
+# CONFIG_USB_MDC800 is not set
 
 #
-# InfiniBand support
+# USB port drivers
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_USB_SERIAL is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# USB Miscellaneous drivers
 #
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# Real Time Clock
+# RTC interfaces
 #
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Engine support
+# I2C RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1077,75 +1238,82 @@ CONFIG_GENERIC_ACL=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
 # CONFIG_NLS_CODEPAGE_860 is not set
@@ -1162,10 +1330,10 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1250=y
 # CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1175,38 +1343,75 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1214,67 +1419,32 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig
index b71a0a4fb95f..4caa0e0fee81 100644
--- a/arch/mips/configs/lemote2f_defconfig
+++ b/arch/mips/configs/lemote2f_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc6
-# Mon Nov  9 23:42:42 2009
+# Linux kernel version: 2.6.33-rc2
+# Mon Jan  4 13:41:09 2010
 #
 CONFIG_MIPS=y
 
@@ -27,6 +27,7 @@ CONFIG_MACH_LOONGSON=y
 # CONFIG_PNX8550_STB810 is not set
 # CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
 # CONFIG_SGI_IP28 is not set
@@ -51,6 +52,9 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y
 # CONFIG_LEMOTE_FULOONG2E is not set
 CONFIG_LEMOTE_MACH2F=y
 CONFIG_CS5536=y
+CONFIG_CS5536_MFGPT=y
+CONFIG_LOONGSON_SUSPEND=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
@@ -63,13 +67,8 @@ CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CMOS_UPDATE=y
 CONFIG_SCHED_OMIT_FRAME_POINTER=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CEVT_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_CSRC_R4K=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
-CONFIG_EARLY_PRINTK=y
 CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_I8259=y
 # CONFIG_NO_IOPORT is not set
@@ -109,13 +108,15 @@ CONFIG_CPU_LOONGSON2F=y
 # CONFIG_CPU_SB1 is not set
 # CONFIG_CPU_CAVIUM_OCTEON is not set
 CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
 CONFIG_CPU_LOONGSON2=y
 CONFIG_SYS_HAS_CPU_LOONGSON2F=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_CPUFREQ=y
+CONFIG_CPU_SUPPORTS_ADDRWINCFG=y
+CONFIG_CPU_SUPPORTS_UNCACHED_ACCELERATED=y
 
 #
 # Kernel type
@@ -137,7 +138,6 @@ CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_FLATMEM_MANUAL is not set
@@ -146,17 +146,11 @@ CONFIG_SPARSEMEM_MANUAL=y
 CONFIG_SPARSEMEM=y
 CONFIG_HAVE_MEMORY_PRESENT=y
 CONFIG_SPARSEMEM_STATIC=y
-
-#
-# Memory hotplug is currently incompatible with Software Suspend
-#
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=0
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_TICK_ONESHOT=y
@@ -175,7 +169,7 @@ CONFIG_HZ=250
 # CONFIG_PREEMPT_NONE is not set
 # CONFIG_PREEMPT_VOLUNTARY is not set
 CONFIG_PREEMPT=y
-# CONFIG_KEXEC is not set
+CONFIG_KEXEC=y
 # CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -194,9 +188,9 @@ CONFIG_LOCALVERSION=""
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_BZIP2=y
 CONFIG_HAVE_KERNEL_LZMA=y
-# CONFIG_KERNEL_GZIP is not set
+CONFIG_KERNEL_GZIP=y
 # CONFIG_KERNEL_BZIP2 is not set
-CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZMA is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -211,6 +205,7 @@ CONFIG_AUDIT=y
 #
 CONFIG_TREE_RCU=y
 # CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
 # CONFIG_RCU_TRACE is not set
 CONFIG_RCU_FANOUT=64
 # CONFIG_RCU_FANOUT_EXACT is not set
@@ -224,7 +219,11 @@ CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
 # CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -256,14 +255,18 @@ CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=m
 CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_SYSCALL_WRAPPERS=y
 
 #
 # GCOV-based kernel profiling
 #
-# CONFIG_SLOW_WORK is not set
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_SLOW_WORK_DEBUG is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -283,14 +286,41 @@ CONFIG_BLOCK_COMPAT=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_DEADLINE=m
 CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
 CONFIG_FREEZER=y
 
 #
@@ -314,7 +344,7 @@ CONFIG_MMU=y
 CONFIG_BINFMT_ELF=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_HAVE_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
+CONFIG_BINFMT_MISC=m
 CONFIG_MIPS32_COMPAT=y
 CONFIG_COMPAT=y
 CONFIG_SYSVIPC_COMPAT=y
@@ -335,9 +365,34 @@ CONFIG_SUSPEND_FREEZER=y
 CONFIG_HIBERNATION_NVS=y
 CONFIG_HIBERNATION=y
 CONFIG_PM_STD_PARTITION="/dev/hda3"
-# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_CPUFREQ=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=m
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+
+#
+# CPUFreq processor drivers
+#
+CONFIG_LOONGSON2_CPUFREQ=m
 CONFIG_NET=y
-CONFIG_COMPAT_NETLINK_MESSAGES=y
 
 #
 # Networking options
@@ -346,11 +401,12 @@ CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
 CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
+CONFIG_XFRM_USER=m
 # CONFIG_XFRM_SUB_POLICY is not set
 # CONFIG_XFRM_MIGRATE is not set
 # CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
+CONFIG_NET_KEY=m
+# CONFIG_NET_KEY_MIGRATE is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_ADVANCED_ROUTER=y
@@ -361,12 +417,13 @@ CONFIG_IP_MULTIPLE_TABLES=y
 CONFIG_IP_ROUTE_MULTIPATH=y
 CONFIG_IP_ROUTE_VERBOSE=y
 # CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE=m
+# CONFIG_NET_IPGRE_BROADCAST is not set
 CONFIG_IP_MROUTE=y
 CONFIG_IP_PIMSM_V1=y
 CONFIG_IP_PIMSM_V2=y
-# CONFIG_ARPD is not set
+CONFIG_ARPD=y
 CONFIG_SYN_COOKIES=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
@@ -399,30 +456,34 @@ CONFIG_DEFAULT_BIC=y
 # CONFIG_DEFAULT_WESTWOOD is not set
 # CONFIG_DEFAULT_RENO is not set
 CONFIG_DEFAULT_TCP_CONG="bic"
-# CONFIG_TCP_MD5SIG is not set
+CONFIG_TCP_MD5SIG=y
 CONFIG_IPV6=m
 CONFIG_IPV6_PRIVACY=y
-# CONFIG_IPV6_ROUTER_PREF is not set
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
 # CONFIG_IPV6_OPTIMISTIC_DAD is not set
 # CONFIG_INET6_AH is not set
 # CONFIG_INET6_ESP is not set
 # CONFIG_INET6_IPCOMP is not set
 # CONFIG_IPV6_MIP6 is not set
 # CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_TUNNEL=m
 CONFIG_INET6_XFRM_MODE_TRANSPORT=m
 CONFIG_INET6_XFRM_MODE_TUNNEL=m
 CONFIG_INET6_XFRM_MODE_BEET=m
 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
 CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
 CONFIG_IPV6_NDISC_NODETYPE=y
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
 # CONFIG_IPV6_MROUTE is not set
 CONFIG_NETWORK_SECMARK=y
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
 CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
 
 #
 # Core Netfilter Configuration
@@ -446,17 +507,22 @@ CONFIG_NETFILTER_ADVANCED=y
 #
 # CONFIG_IP6_NF_QUEUE is not set
 # CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
 # CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
 # CONFIG_DECNET is not set
+CONFIG_LLC=m
 # CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
+CONFIG_IPX=m
+# CONFIG_IPX_INTERN is not set
 # CONFIG_ATALK is not set
 # CONFIG_X25 is not set
 # CONFIG_LAPB is not set
@@ -518,26 +584,61 @@ CONFIG_NET_SCH_FIFO=y
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+# CONFIG_BT_MRVL is not set
 # CONFIG_AF_RXRPC is not set
 CONFIG_FIB_RULES=y
 CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
 # CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_WIRELESS_EXT=y
+CONFIG_CFG80211_WEXT=y
 CONFIG_WIRELESS_EXT_SYSFS=y
-# CONFIG_LIB80211 is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
+CONFIG_LIB80211=m
+CONFIG_LIB80211_DEBUG=y
+CONFIG_MAC80211=m
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
 # CONFIG_WIMAX is not set
 CONFIG_RFKILL=m
-# CONFIG_RFKILL_INPUT is not set
+CONFIG_RFKILL_LEDS=y
+CONFIG_RFKILL_INPUT=y
 # CONFIG_NET_9P is not set
 
 #
@@ -555,7 +656,7 @@ CONFIG_FW_LOADER=y
 CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
+CONFIG_CONNECTOR=m
 # CONFIG_MTD is not set
 # CONFIG_PARPORT is not set
 # CONFIG_PNP is not set
@@ -566,7 +667,12 @@ CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_DRBD is not set
 # CONFIG_BLK_DEV_NBD is not set
 # CONFIG_BLK_DEV_SX8 is not set
 # CONFIG_BLK_DEV_UB is not set
@@ -577,19 +683,7 @@ CONFIG_BLK_DEV_RAM_SIZE=8192
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_BLK_DEV_HD is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_PHANTOM is not set
-# CONFIG_SGI_IOC4 is not set
-# CONFIG_TIFM_CORE is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_HP_ILO is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_CB710_CORE is not set
+# CONFIG_MISC_DEVICES is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
 
@@ -619,8 +713,7 @@ CONFIG_BLK_DEV_IDEDMA_SFF=y
 #
 CONFIG_BLK_DEV_IDEPCI=y
 # CONFIG_IDEPCI_PCIBUS_ORDER is not set
-# CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_GENERIC is not set
 # CONFIG_BLK_DEV_OPTI621 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
 # CONFIG_BLK_DEV_AEC62XX is not set
@@ -700,7 +793,29 @@ CONFIG_SCSI_WAIT_SCAN=m
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
-# CONFIG_MD is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_RAID6_PQ=m
+# CONFIG_ASYNC_RAID6_TEST is not set
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_DEBUG=y
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_UEVENT=y
 # CONFIG_FUSION is not set
 
 #
@@ -712,19 +827,19 @@ CONFIG_SCSI_WAIT_SCAN=m
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
 # CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
 # CONFIG_IFB is not set
-# CONFIG_DUMMY is not set
+CONFIG_DUMMY=m
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
+CONFIG_TUN=m
+CONFIG_VETH=m
 # CONFIG_ARCNET is not set
 # CONFIG_PHYLIB is not set
 CONFIG_NET_ETHERNET=y
@@ -738,6 +853,7 @@ CONFIG_MII=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
 # CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
 # CONFIG_NET_VENDOR_RACAL is not set
 # CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
@@ -769,7 +885,7 @@ CONFIG_NET_PCI=y
 # CONFIG_8139CP is not set
 CONFIG_8139TOO=y
 # CONFIG_8139TOO_PIO is not set
-CONFIG_8139TOO_TUNE_TWISTER=y
+# CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
 # CONFIG_8139_OLD_RX_RESET is not set
 # CONFIG_R6040 is not set
@@ -795,6 +911,7 @@ CONFIG_NETDEV_1000=y
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 CONFIG_R8169=y
+CONFIG_R8169_VLAN=y
 # CONFIG_SIS190 is not set
 # CONFIG_SKGE is not set
 # CONFIG_SKY2 is not set
@@ -810,15 +927,31 @@ CONFIG_R8169=y
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
 CONFIG_WLAN=y
-CONFIG_WLAN_PRE80211=y
-# CONFIG_STRIP is not set
-# CONFIG_WAVELAN is not set
-CONFIG_WLAN_80211=y
-# CONFIG_LIBERTAS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
 # CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
 # CONFIG_PRISM54 is not set
 # CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
 # CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_HERMES is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
@@ -831,17 +964,39 @@ CONFIG_WLAN_80211=y
 # CONFIG_USB_KAWETH is not set
 # CONFIG_USB_PEGASUS is not set
 # CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_CDC_EEM=m
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=m
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
 # CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 # CONFIG_NET_FC is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
@@ -849,8 +1004,9 @@ CONFIG_WLAN_80211=y
 # Input device support
 #
 CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_FF_MEMLESS=m
+CONFIG_INPUT_POLLDEV=m
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
@@ -884,7 +1040,7 @@ CONFIG_MOUSE_PS2_SYNAPTICS=y
 # CONFIG_MOUSE_PS2_SENTELIC is not set
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
+CONFIG_MOUSE_APPLETOUCH=m
 # CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_INPORT is not set
 # CONFIG_MOUSE_LOGIBM is not set
@@ -904,6 +1060,7 @@ CONFIG_SERIO_I8042=y
 # CONFIG_SERIO_PCIPS2 is not set
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -934,8 +1091,7 @@ CONFIG_SERIAL_NONSTANDARD=y
 #
 # Serial drivers
 #
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250=m
 # CONFIG_SERIAL_8250_PCI is not set
 CONFIG_SERIAL_8250_NR_UARTS=16
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
@@ -953,8 +1109,7 @@ CONFIG_SERIAL_8250_FOURPORT=y
 #
 # Non-8250 serial port support
 #
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_CORE=m
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
@@ -1033,14 +1188,18 @@ CONFIG_VIDEO_MEDIA=m
 #
 # Multimedia drivers
 #
+CONFIG_IR_CORE=m
+CONFIG_VIDEO_IR=m
 # CONFIG_MEDIA_ATTACH is not set
 CONFIG_VIDEO_V4L2=m
 CONFIG_VIDEO_V4L1=m
+CONFIG_VIDEOBUF_GEN=m
+CONFIG_VIDEOBUF_VMALLOC=m
 CONFIG_VIDEO_CAPTURE_DRIVERS=y
 # CONFIG_VIDEO_ADV_DEBUG is not set
 # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
 CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
+CONFIG_VIDEO_VIVI=m
 # CONFIG_VIDEO_PMS is not set
 # CONFIG_VIDEO_CPIA is not set
 # CONFIG_VIDEO_CPIA2 is not set
@@ -1049,52 +1208,55 @@ CONFIG_V4L_USB_DRIVERS=y
 CONFIG_USB_VIDEO_CLASS=m
 CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
 CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_STV06XX is not set
+CONFIG_USB_M5602=m
+CONFIG_USB_STV06XX=m
 # CONFIG_USB_GL860 is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
+CONFIG_USB_GSPCA_CONEX=m
+CONFIG_USB_GSPCA_ETOMS=m
+CONFIG_USB_GSPCA_FINEPIX=m
 # CONFIG_USB_GSPCA_JEILINJ is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_MR97310A is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_OV534 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SN9C20X is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_SQ905 is not set
-# CONFIG_USB_GSPCA_SQ905C is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
+CONFIG_USB_GSPCA_MARS=m
+CONFIG_USB_GSPCA_MR97310A=m
+CONFIG_USB_GSPCA_OV519=m
+CONFIG_USB_GSPCA_OV534=m
+CONFIG_USB_GSPCA_PAC207=m
+# CONFIG_USB_GSPCA_PAC7302 is not set
+CONFIG_USB_GSPCA_PAC7311=m
+CONFIG_USB_GSPCA_SN9C20X=m
+CONFIG_USB_GSPCA_SN9C20X_EVDEV=y
+CONFIG_USB_GSPCA_SONIXB=m
+CONFIG_USB_GSPCA_SONIXJ=m
+CONFIG_USB_GSPCA_SPCA500=m
+CONFIG_USB_GSPCA_SPCA501=m
+CONFIG_USB_GSPCA_SPCA505=m
+CONFIG_USB_GSPCA_SPCA506=m
+CONFIG_USB_GSPCA_SPCA508=m
+CONFIG_USB_GSPCA_SPCA561=m
+CONFIG_USB_GSPCA_SQ905=m
+CONFIG_USB_GSPCA_SQ905C=m
+CONFIG_USB_GSPCA_STK014=m
+# CONFIG_USB_GSPCA_STV0680 is not set
+CONFIG_USB_GSPCA_SUNPLUS=m
+CONFIG_USB_GSPCA_T613=m
+CONFIG_USB_GSPCA_TV8532=m
+CONFIG_USB_GSPCA_VC032X=m
+CONFIG_USB_GSPCA_ZC3XX=m
 # CONFIG_VIDEO_HDPVR is not set
 # CONFIG_USB_VICAM is not set
 # CONFIG_USB_IBMCAM is not set
 # CONFIG_USB_KONICAWC is not set
 # CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
+CONFIG_USB_ET61X251=m
 # CONFIG_USB_OV511 is not set
 # CONFIG_USB_SE401 is not set
-# CONFIG_USB_SN9C102 is not set
+CONFIG_USB_SN9C102=m
 # CONFIG_USB_STV680 is not set
-# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_ZC0301=m
 # CONFIG_USB_PWC is not set
 CONFIG_USB_PWC_INPUT_EVDEV=y
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
+CONFIG_USB_ZR364XX=m
+CONFIG_USB_STKWEBCAM=m
+CONFIG_USB_S2255=m
 # CONFIG_RADIO_ADAPTERS is not set
 # CONFIG_DAB is not set
 
@@ -1132,6 +1294,7 @@ CONFIG_FB_TILEBLITTING=y
 # CONFIG_FB_CYBER2000 is not set
 # CONFIG_FB_ASILIANT is not set
 # CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_NVIDIA is not set
 # CONFIG_FB_RIVA is not set
@@ -1161,7 +1324,7 @@ CONFIG_FB_SIS_315=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_GENERIC=m
 
 #
 # Display device support
@@ -1193,28 +1356,44 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_LOGO_LINUX_CLUT224=y
 CONFIG_SOUND=m
-# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
 CONFIG_SND=m
 CONFIG_SND_TIMER=m
 CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
 # CONFIG_SND_RTCTIMER is not set
 # CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
 # CONFIG_SND_VERBOSE_PRINTK is not set
 # CONFIG_SND_DEBUG is not set
 CONFIG_SND_VMASTER=y
-# CONFIG_SND_RAWMIDI_SEQ is not set
+CONFIG_SND_RAWMIDI_SEQ=m
 # CONFIG_SND_OPL3_LIB_SEQ is not set
 # CONFIG_SND_OPL4_LIB_SEQ is not set
 # CONFIG_SND_SBAWE_SEQ is not set
 # CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_MPU401_UART=m
 CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_VIRMIDI=m
+# CONFIG_SND_MTPAV is not set
+CONFIG_SND_SERIAL_U16550=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_AC97_POWER_SAVE=y
+CONFIG_SND_AC97_POWER_SAVE_DEFAULT=10
 CONFIG_SND_PCI=y
 # CONFIG_SND_AD1889 is not set
 # CONFIG_SND_ALS300 is not set
@@ -1281,7 +1460,10 @@ CONFIG_SND_CS5535AUDIO=m
 # CONFIG_SND_VX222 is not set
 # CONFIG_SND_YMFPCI is not set
 # CONFIG_SND_MIPS is not set
-# CONFIG_SND_USB is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
 # CONFIG_SND_SOC is not set
 # CONFIG_SOUND_PRIME is not set
 CONFIG_AC97_BUS=m
@@ -1299,32 +1481,41 @@ CONFIG_USB_HIDDEV=y
 #
 # Special HID drivers
 #
-# CONFIG_HID_A4TECH is not set
-# CONFIG_HID_APPLE is not set
-# CONFIG_HID_BELKIN is not set
-# CONFIG_HID_CHERRY is not set
-# CONFIG_HID_CHICONY is not set
-# CONFIG_HID_CYPRESS is not set
-# CONFIG_HID_DRAGONRISE is not set
-# CONFIG_HID_EZKEY is not set
-# CONFIG_HID_KYE is not set
-# CONFIG_HID_GYRATION is not set
-# CONFIG_HID_TWINHAN is not set
-# CONFIG_HID_KENSINGTON is not set
-# CONFIG_HID_LOGITECH is not set
-# CONFIG_HID_MICROSOFT is not set
-# CONFIG_HID_MONTEREY is not set
-# CONFIG_HID_NTRIG is not set
-# CONFIG_HID_PANTHERLORD is not set
-# CONFIG_HID_PETALYNX is not set
-# CONFIG_HID_SAMSUNG is not set
-# CONFIG_HID_SONY is not set
-# CONFIG_HID_SUNPLUS is not set
-# CONFIG_HID_GREENASIA is not set
-# CONFIG_HID_SMARTJOYPLUS is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_HID_THRUSTMASTER is not set
-# CONFIG_HID_ZEROPLUS is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EZKEY=m
+CONFIG_HID_KYE=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LOGITECH=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_THRUSTMASTER=m
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=m
+CONFIG_HID_ZEROPLUS=m
+CONFIG_ZEROPLUS_FF=y
 CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1344,7 +1535,7 @@ CONFIG_USB_SUSPEND=y
 CONFIG_USB_OTG_WHITELIST=y
 # CONFIG_USB_OTG_BLACKLIST_HUB is not set
 CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
+CONFIG_USB_WUSB=m
 # CONFIG_USB_WUSB_CBAF is not set
 
 #
@@ -1366,14 +1557,15 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 CONFIG_USB_UHCI_HCD=m
 # CONFIG_USB_SL811_HCD is not set
 # CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_WHCI_HCD=m
+CONFIG_USB_HWA_HCD=m
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
 
 #
 # USB Device Class drivers
 #
 CONFIG_USB_ACM=m
-# CONFIG_USB_PRINTER is not set
+CONFIG_USB_PRINTER=m
 CONFIG_USB_WDM=m
 # CONFIG_USB_TMC is not set
 
@@ -1397,7 +1589,7 @@ CONFIG_USB_STORAGE_ALAUDA=m
 # CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
+CONFIG_USB_LIBUSUAL=y
 
 #
 # USB Imaging devices
@@ -1467,7 +1659,7 @@ CONFIG_USB_SERIAL_GENERIC=y
 # CONFIG_USB_LEGOTOWER is not set
 # CONFIG_USB_LCD is not set
 # CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
+CONFIG_USB_LED=m
 # CONFIG_USB_CYPRESS_CY7C63 is not set
 # CONFIG_USB_CYTHERM is not set
 # CONFIG_USB_IDMOUSE is not set
@@ -1480,16 +1672,95 @@ CONFIG_USB_SERIAL_GENERIC=y
 # CONFIG_USB_TEST is not set
 # CONFIG_USB_ISIGHTFW is not set
 # CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=m
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
 
 #
 # OTG and related infrastructure
 #
 # CONFIG_NOP_USB_XCEIV is not set
-# CONFIG_UWB is not set
-# CONFIG_MMC is not set
+CONFIG_UWB=m
+CONFIG_UWB_HWA=m
+CONFIG_UWB_WHCI=m
+# CONFIG_UWB_WLP is not set
+# CONFIG_UWB_I1480U is not set
+CONFIG_MMC=m
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=m
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 # CONFIG_ACCESSIBILITY is not set
 # CONFIG_INFINIBAND is not set
 # CONFIG_RTC_CLASS is not set
@@ -1504,22 +1775,18 @@ CONFIG_STAGING=y
 # CONFIG_STAGING_EXCLUDE_BUILD is not set
 # CONFIG_ET131X is not set
 # CONFIG_USB_IP_COMMON is not set
-# CONFIG_PRISM2_USB is not set
+# CONFIG_W35UND is not set
 # CONFIG_ECHO is not set
+# CONFIG_OTUS is not set
 # CONFIG_COMEDI is not set
 # CONFIG_ASUS_OLED is not set
 # CONFIG_ALTERA_PCIE_CHDMA is not set
-# CONFIG_RTL8187SE is not set
-# CONFIG_RTL8192SU is not set
+# CONFIG_R8187SE is not set
 # CONFIG_RTL8192E is not set
 # CONFIG_INPUT_MIMIO is not set
 # CONFIG_TRANZPORT is not set
 
 #
-# Android
-#
-
-#
 # Qualcomm MSM Camera And Video
 #
 
@@ -1527,7 +1794,6 @@ CONFIG_STAGING=y
 # Camera Sensor Selection
 #
 # CONFIG_INPUT_GPIO is not set
-# CONFIG_DST is not set
 # CONFIG_POHMELFS is not set
 # CONFIG_B3DFG is not set
 # CONFIG_PLAN9AUTH is not set
@@ -1544,28 +1810,55 @@ CONFIG_STAGING=y
 #
 # CONFIG_RAR_REGISTER is not set
 # CONFIG_IIO is not set
+# CONFIG_RAMZSWAP is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_STRIP is not set
+# CONFIG_WAVELAN is not set
 CONFIG_FB_SM7XX=y
-CONFIG_FB_SM7XX_ACCEL=y
+# CONFIG_FB_SM7XX_ACCEL is not set
 
 #
 # File systems
 #
-# CONFIG_EXT2_FS is not set
+CONFIG_EXT2_FS=m
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
 CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
 CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+# CONFIG_REISERFS_FS_POSIX_ACL is not set
+# CONFIG_REISERFS_FS_SECURITY is not set
+CONFIG_JFS_FS=m
+CONFIG_JFS_POSIX_ACL=y
+# CONFIG_JFS_SECURITY is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
 CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
+CONFIG_XFS_FS=m
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
+CONFIG_BTRFS_FS=m
+# CONFIG_BTRFS_FS_POSIX_ACL is not set
 # CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
@@ -1575,17 +1868,25 @@ CONFIG_INOTIFY_USER=y
 CONFIG_QUOTA=y
 # CONFIG_QUOTA_NETLINK_INTERFACE is not set
 CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_QUOTA_TREE=m
 # CONFIG_QFMT_V1 is not set
-# CONFIG_QFMT_V2 is not set
+CONFIG_QFMT_V2=m
 CONFIG_QUOTACTL=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
 # CONFIG_FUSE_FS is not set
 
 #
 # Caches
 #
-# CONFIG_FSCACHE is not set
+CONFIG_FSCACHE=m
+# CONFIG_FSCACHE_STATS is not set
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_HISTOGRAM is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1599,11 +1900,13 @@ CONFIG_ZISOFS=y
 # DOS/FAT/NT Filesystems
 #
 CONFIG_FAT_FS=m
-# CONFIG_MSDOS_FS is not set
+CONFIG_MSDOS_FS=m
 CONFIG_VFAT_FS=m
 CONFIG_FAT_DEFAULT_CODEPAGE=437
 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
 
 #
 # Pseudo filesystems
@@ -1616,23 +1919,60 @@ CONFIG_SYSFS=y
 CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_EMBEDDED=y
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
+# CONFIG_NFS_FSCACHE is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+# CONFIG_NFSD_V3_ACL is not set
+CONFIG_NFSD_V4=y
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
 CONFIG_NFS_ACL_SUPPORT=m
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=m
-# CONFIG_RPCSEC_GSS_KRB5 is not set
+CONFIG_SUNRPC_GSS=m
+CONFIG_RPCSEC_GSS_KRB5=m
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
 # CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+# CONFIG_CIFS_WEAK_PW_HASH is not set
+# CONFIG_CIFS_UPCALL is not set
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
@@ -1643,45 +1983,45 @@ CONFIG_SUNRPC=m
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
 CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf-8"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
 # CONFIG_DLM is not set
 
 #
@@ -1695,125 +2035,155 @@ CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
 CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 # CONFIG_DEBUG_KERNEL is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
 
 #
 # Security options
 #
-# CONFIG_KEYS is not set
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
+CONFIG_CRYPTO_FIPS=y
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
 CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER=m
 CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
 CONFIG_CRYPTO_RNG2=y
 CONFIG_CRYPTO_PCOMP=y
-CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER=m
 CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
 CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
 
 #
 # Authenticated Encryption with Associated Data
 #
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
 
 #
 # Block modes
 #
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CTR=m
 # CONFIG_CRYPTO_CTS is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
 
 #
 # Hash modes
 #
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
 # CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
 
 #
 # Ciphers
 #
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
 
 #
 # Compression
 #
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=m
 
 #
 # Random Number Generation
 #
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_ANSI_CPRNG=m
 CONFIG_CRYPTO_HW=y
 # CONFIG_CRYPTO_DEV_HIFN_795X is not set
-# CONFIG_BINARY_PRINTF is not set
+CONFIG_BINARY_PRINTF=y
 
 #
 # Library routines
@@ -1821,14 +2191,20 @@ CONFIG_CRYPTO_HW=y
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
+CONFIG_CRC16=y
 CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
+CONFIG_LIBCRC32C=m
 CONFIG_AUDIT_GENERIC=y
-CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
index ddf67f639194..97382b698b9b 100644
--- a/arch/mips/configs/pb1100_defconfig
+++ b/arch/mips/configs/pb1100_defconfig
@@ -1,79 +1,103 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:37 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 09:53:29 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-CONFIG_MIPS_PB1100=y
-# CONFIG_MIPS_PB1500 is not set
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+CONFIG_MIPS_PB1100=y
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1100=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1100=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -86,6 +110,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -93,11 +118,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -107,184 +135,244 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-pb1100"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 # CONFIG_PCI is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
+# CONFIG_PCMCIA_IOCTL is not set
 
 #
 # PC-card bridges
 #
 # CONFIG_PCMCIA_AU1X00 is not set
-
-#
-# PCI Hotplug Support
-#
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
 # CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -295,110 +383,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -408,27 +411,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -437,25 +437,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -468,6 +468,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -493,14 +494,13 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -517,166 +517,136 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_UB=y
 # CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
 
 #
-# Misc devices
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
 
 #
-# ATA/ATAPI/MFM/RLL support
+# IDE chipset support/bugfixes
 #
-# CONFIG_IDE is not set
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-CONFIG_PHYLIB=m
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
-# CONFIG_MIPS_AU1X00_ENET is not set
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
-#
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -684,16 +654,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -703,28 +671,26 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
 CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
 CONFIG_VT_CONSOLE=y
 CONFIG_HW_CONSOLE=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
 
 #
 # Serial drivers
@@ -743,198 +709,288 @@ CONFIG_SERIAL_8250_AU1X00=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 
 #
 # PCMCIA character devices
 #
-CONFIG_SYNCLINK_CS=m
+# CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
-# CONFIG_SOUND is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# HID Devices
-#
-# CONFIG_HID is not set
-
-#
-# USB support
+# Console display driver support
 #
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 # CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Miscellaneous USB options
 #
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# USB Gadget Support
+# USB Host Controller Drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# MMC/SD Card support
+# USB Device Class drivers
 #
-# CONFIG_MMC is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# LED devices
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-# CONFIG_NEW_LEDS is not set
 
 #
-# LED drivers
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# LED Triggers
+# USB Imaging devices
 #
+# CONFIG_USB_MDC800 is not set
 
 #
-# InfiniBand support
+# USB port drivers
 #
+# CONFIG_USB_SERIAL is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# USB Miscellaneous drivers
 #
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
 
 #
-# Real Time Clock
+# OTG and related infrastructure
 #
-# CONFIG_RTC_CLASS is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# DMA Engine support
+# RTC interfaces
 #
-# CONFIG_DMA_ENGINE is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -953,69 +1009,76 @@ CONFIG_GENERIC_ACL=y
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_437 is not set
 # CONFIG_NLS_CODEPAGE_737 is not set
@@ -1055,34 +1118,71 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
 # CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1090,67 +1190,32 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
new file mode 100644
index 000000000000..e9ad77320f16
--- /dev/null
+++ b/arch/mips/configs/pb1200_defconfig
@@ -0,0 +1,1568 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.33
+# Fri Feb 26 10:23:34 2010
+#
+CONFIG_MIPS=y
+
+#
+# Machine selection
+#
+CONFIG_MACH_ALCHEMY=y
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
+# CONFIG_MIPS_COBALT is not set
+# CONFIG_MACH_DECSTATION is not set
+# CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
+# CONFIG_MIPS_MALTA is not set
+# CONFIG_MIPS_SIM is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
+# CONFIG_PNX8550_JBS is not set
+# CONFIG_PNX8550_STB810 is not set
+# CONFIG_PMC_MSP is not set
+# CONFIG_PMC_YOSEMITE is not set
+# CONFIG_POWERTV is not set
+# CONFIG_SGI_IP22 is not set
+# CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
+# CONFIG_SGI_IP32 is not set
+# CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
+# CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
+# CONFIG_SNI_RM is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+CONFIG_MIPS_PB1200=y
+# CONFIG_MIPS_PB1500 is not set
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1200=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_IRQ_CPU=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+
+#
+# CPU selection
+#
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_R3000 is not set
+# CONFIG_CPU_TX39XX is not set
+# CONFIG_CPU_VR41XX is not set
+# CONFIG_CPU_R4300 is not set
+# CONFIG_CPU_R4X00 is not set
+# CONFIG_CPU_TX49XX is not set
+# CONFIG_CPU_R5000 is not set
+# CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
+# CONFIG_CPU_R6000 is not set
+# CONFIG_CPU_NEVADA is not set
+# CONFIG_CPU_R8000 is not set
+# CONFIG_CPU_R10000 is not set
+# CONFIG_CPU_RM7000 is not set
+# CONFIG_CPU_RM9000 is not set
+# CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPSR1=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+
+#
+# Kernel type
+#
+CONFIG_32BIT=y
+# CONFIG_64BIT is not set
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_MIPS_MT_DISABLED=y
+# CONFIG_MIPS_MT_SMP is not set
+# CONFIG_MIPS_MT_SMTC is not set
+CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_48 is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_128 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_256 is not set
+# CONFIG_HZ_1000 is not set
+# CONFIG_HZ_1024 is not set
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_HZ=100
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-pb1200"
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, ISA, TC)
+#
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_MMU=y
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+# CONFIG_PCMCIA_IOCTL is not set
+
+#
+# PC-card bridges
+#
+# CONFIG_PCMCIA_AU1X00 is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_TRAD_SIGNALS=y
+
+#
+# Power management options
+#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_PM is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_AU1550 is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_UB=y
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_ATAPI=y
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDE_AU1XXX=y
+CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y
+# CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_MIPS_AU1X00_ENET is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_SERIAL_8250_EXTENDED is not set
+CONFIG_SERIAL_8250_AU1X00=y
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_AU1550=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_AU1550=y
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+CONFIG_HWMON_VID=y
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+CONFIG_SENSORS_ADM1025=y
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+CONFIG_SENSORS_LM70=y
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_UCB1400_CORE is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_AB4500_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_AU1200=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_AU1XPSC=y
+CONFIG_SND_SOC_AU1XPSC_I2S=y
+CONFIG_SND_SOC_AU1XPSC_AC97=y
+CONFIG_SND_SOC_DB1200=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_AC97_CODEC=y
+CONFIG_SND_SOC_WM8731=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AU1X=y
+# CONFIG_MMC_AT91 is not set
+# CONFIG_MMC_ATMELMCI is not set
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+CONFIG_NLS_CODEPAGE_1250=y
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
index 5ec60836b645..7497d3306b91 100644
--- a/arch/mips/configs/pb1500_defconfig
+++ b/arch/mips/configs/pb1500_defconfig
@@ -1,78 +1,102 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:37 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 10:05:27 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-CONFIG_MIPS_PB1500=y
-# CONFIG_MIPS_PB1550 is not set
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+CONFIG_MIPS_PB1500=y
+# CONFIG_MIPS_PB1550 is not set
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1500=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1500=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -85,6 +109,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -92,11 +117,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -106,190 +134,255 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-pb1500"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
 CONFIG_PCMCIA_IOCTL=y
-CONFIG_CARDBUS=y
+# CONFIG_CARDBUS is not set
 
 #
 # PC-card bridges
 #
 # CONFIG_YENTA is not set
-CONFIG_PD6729=m
+# CONFIG_PD6729 is not set
 # CONFIG_I82092 is not set
 # CONFIG_PCMCIA_AU1X00 is not set
-CONFIG_PCCARD_NONSTATIC=m
-
-#
-# PCI Hotplug Support
-#
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 # CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -300,110 +393,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -413,27 +421,24 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -442,25 +447,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -473,6 +478,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -498,14 +504,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -523,30 +529,20 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
 # CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
+# LPDDR flash memory drivers
 #
-# CONFIG_PARPORT is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
@@ -554,67 +550,66 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
-
-#
-# Misc devices
-#
-CONFIG_SGI_IOC4=m
-# CONFIG_TIFM_CORE is not set
 
 #
-# ATA/ATAPI/MFM/RLL support
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=y
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_DELKIN is not set
-# CONFIG_BLK_DEV_IDECD is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
 CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
 # CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_GENERIC is not set
 # CONFIG_BLK_DEV_OPTI621 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_PCI_AUTO is not set
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_BLK_DEV_ALI15X3 is not set
 # CONFIG_BLK_DEV_AMD74XX is not set
 # CONFIG_BLK_DEV_CMD64X is not set
 # CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
 # CONFIG_BLK_DEV_CS5520 is not set
 # CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
 CONFIG_BLK_DEV_HPT366=y
 # CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
-CONFIG_BLK_DEV_IT8213=m
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
 # CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
@@ -624,82 +619,65 @@ CONFIG_BLK_DEV_IT8213=m
 # CONFIG_BLK_DEV_SLC90E66 is not set
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
-CONFIG_BLK_DEV_TC86C001=m
-# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
 CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# You can enable one or both FireWire driver stacks.
 #
-# CONFIG_I2O is not set
 
 #
-# Network device support
+# The newer stack is recommended.
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
@@ -707,96 +685,51 @@ CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=m
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=m
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
+# CONFIG_WLAN is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_NET_RADIO is not set
 
 #
-# PCMCIA network device support
-#
-CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
-CONFIG_PCMCIA_3C574=m
-CONFIG_PCMCIA_FMVJ18X=m
-CONFIG_PCMCIA_PCNET=m
-CONFIG_PCMCIA_NMCLAN=m
-CONFIG_PCMCIA_SMC91C92=m
-CONFIG_PCMCIA_XIRC2PS=m
-CONFIG_PCMCIA_AXNET=m
-
-#
-# Wan interfaces
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_NET_PCMCIA is not set
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -804,16 +737,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -823,33 +754,34 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI is not set
 # CONFIG_SERIAL_8250_CS is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
@@ -863,282 +795,450 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 
 #
 # PCMCIA character devices
 #
-CONFIG_SYNCLINK_CS=m
+# CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
 # CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
+CONFIG_DEVPORT=y
 # CONFIG_I2C is not set
-
-#
-# SPI support
-#
 # CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
 
 #
-# Dallas's 1-wire bus
+# PPS support
 #
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
 # CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+CONFIG_FB_S1D13XXX=y
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_VIA is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
+# Display device support
 #
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
-#
-# CONFIG_HID is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# USB support
+# Console display driver support
 #
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+# CONFIG_LOGO is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Miscellaneous USB options
 #
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+CONFIG_USB_OTG_WHITELIST=y
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# USB Gadget Support
+# USB Host Controller Drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# MMC/SD Card support
+# USB Device Class drivers
 #
-# CONFIG_MMC is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# LED devices
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-# CONFIG_NEW_LEDS is not set
 
 #
-# LED drivers
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# LED Triggers
+# USB Imaging devices
 #
+# CONFIG_USB_MDC800 is not set
 
 #
-# InfiniBand support
+# USB port drivers
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_USB_SERIAL is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# USB Miscellaneous drivers
 #
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
 
 #
-# Real Time Clock
+# OTG and related infrastructure
 #
-# CONFIG_RTC_CLASS is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# DMA Engine support
+# RTC interfaces
 #
-# CONFIG_DMA_ENGINE is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
 #
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
 #
+CONFIG_FAT_FS=y
 # CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
 # CONFIG_NLS_CODEPAGE_860 is not set
@@ -1155,10 +1255,10 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1250=y
 # CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1168,38 +1268,75 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1207,67 +1344,32 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
index 6647642b5d97..aa526f53cb1b 100644
--- a/arch/mips/configs/pb1550_defconfig
+++ b/arch/mips/configs/pb1550_defconfig
@@ -1,79 +1,103 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20
-# Tue Feb 20 21:47:37 2007
+# Linux kernel version: 2.6.33
+# Fri Feb 26 10:06:07 2010
 #
 CONFIG_MIPS=y
 
 #
 # Machine selection
 #
-CONFIG_ZONE_DMA=y
 CONFIG_MACH_ALCHEMY=y
-# CONFIG_MIPS_MTX1 is not set
-# CONFIG_MIPS_BOSPORUS is not set
-# CONFIG_MIPS_PB1000 is not set
-# CONFIG_MIPS_PB1100 is not set
-# CONFIG_MIPS_PB1500 is not set
-CONFIG_MIPS_PB1550=y
-# CONFIG_MIPS_PB1200 is not set
-# CONFIG_MIPS_DB1000 is not set
-# CONFIG_MIPS_DB1100 is not set
-# CONFIG_MIPS_DB1500 is not set
-# CONFIG_MIPS_DB1550 is not set
-# CONFIG_MIPS_DB1200 is not set
-# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_AR7 is not set
+# CONFIG_BCM47XX is not set
+# CONFIG_BCM63XX is not set
 # CONFIG_MIPS_COBALT is not set
 # CONFIG_MACH_DECSTATION is not set
 # CONFIG_MACH_JAZZ is not set
+# CONFIG_LASAT is not set
+# CONFIG_MACH_LOONGSON is not set
 # CONFIG_MIPS_MALTA is not set
-# CONFIG_WR_PPMC is not set
 # CONFIG_MIPS_SIM is not set
-# CONFIG_MOMENCO_JAGUAR_ATX is not set
-# CONFIG_MIPS_XXS1500 is not set
+# CONFIG_NEC_MARKEINS is not set
+# CONFIG_MACH_VR41XX is not set
+# CONFIG_NXP_STB220 is not set
+# CONFIG_NXP_STB225 is not set
 # CONFIG_PNX8550_JBS is not set
 # CONFIG_PNX8550_STB810 is not set
-# CONFIG_MACH_VR41XX is not set
+# CONFIG_PMC_MSP is not set
 # CONFIG_PMC_YOSEMITE is not set
-# CONFIG_MARKEINS is not set
+# CONFIG_POWERTV is not set
 # CONFIG_SGI_IP22 is not set
 # CONFIG_SGI_IP27 is not set
+# CONFIG_SGI_IP28 is not set
 # CONFIG_SGI_IP32 is not set
-# CONFIG_SIBYTE_BIGSUR is not set
-# CONFIG_SIBYTE_SWARM is not set
-# CONFIG_SIBYTE_SENTOSA is not set
-# CONFIG_SIBYTE_RHONE is not set
-# CONFIG_SIBYTE_CARMEL is not set
-# CONFIG_SIBYTE_LITTLESUR is not set
 # CONFIG_SIBYTE_CRHINE is not set
+# CONFIG_SIBYTE_CARMEL is not set
 # CONFIG_SIBYTE_CRHONE is not set
+# CONFIG_SIBYTE_RHONE is not set
+# CONFIG_SIBYTE_SWARM is not set
+# CONFIG_SIBYTE_LITTLESUR is not set
+# CONFIG_SIBYTE_SENTOSA is not set
+# CONFIG_SIBYTE_BIGSUR is not set
 # CONFIG_SNI_RM is not set
-# CONFIG_TOSHIBA_JMR3927 is not set
-# CONFIG_TOSHIBA_RBTX4927 is not set
-# CONFIG_TOSHIBA_RBTX4938 is not set
+# CONFIG_MACH_TX39XX is not set
+# CONFIG_MACH_TX49XX is not set
+# CONFIG_MIKROTIK_RB532 is not set
+# CONFIG_WR_PPMC is not set
+# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
+# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
+CONFIG_ALCHEMY_GPIOINT_AU1000=y
+# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
+# CONFIG_MIPS_MTX1 is not set
+# CONFIG_MIPS_BOSPORUS is not set
+# CONFIG_MIPS_DB1000 is not set
+# CONFIG_MIPS_DB1100 is not set
+# CONFIG_MIPS_DB1200 is not set
+# CONFIG_MIPS_DB1500 is not set
+# CONFIG_MIPS_DB1550 is not set
+# CONFIG_MIPS_MIRAGE is not set
+# CONFIG_MIPS_PB1000 is not set
+# CONFIG_MIPS_PB1100 is not set
+# CONFIG_MIPS_PB1200 is not set
+# CONFIG_MIPS_PB1500 is not set
+CONFIG_MIPS_PB1550=y
+# CONFIG_MIPS_XXS1500 is not set
+CONFIG_SOC_AU1550=y
+CONFIG_SOC_AU1X00=y
+CONFIG_LOONGSON_UART_BASE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_TIME=y
-CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
-# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_CEVT_R4K_LIB=y
+CONFIG_CSRC_R4K_LIB=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_DMA_NEED_PCI_MAP_STATE=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_GPIO=y
 # CONFIG_CPU_BIG_ENDIAN is not set
 CONFIG_CPU_LITTLE_ENDIAN=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SOC_AU1550=y
-CONFIG_SOC_AU1X00=y
+CONFIG_IRQ_CPU=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 
 #
 # CPU selection
 #
+# CONFIG_CPU_LOONGSON2E is not set
+# CONFIG_CPU_LOONGSON2F is not set
 CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_MIPS32_R2 is not set
 # CONFIG_CPU_MIPS64_R1 is not set
@@ -86,6 +110,7 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_TX49XX is not set
 # CONFIG_CPU_R5000 is not set
 # CONFIG_CPU_R5432 is not set
+# CONFIG_CPU_R5500 is not set
 # CONFIG_CPU_R6000 is not set
 # CONFIG_CPU_NEVADA is not set
 # CONFIG_CPU_R8000 is not set
@@ -93,11 +118,14 @@ CONFIG_CPU_MIPS32_R1=y
 # CONFIG_CPU_RM7000 is not set
 # CONFIG_CPU_RM9000 is not set
 # CONFIG_CPU_SB1 is not set
+# CONFIG_CPU_CAVIUM_OCTEON is not set
+CONFIG_SYS_SUPPORTS_ZBOOT=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_CPU_MIPS32=y
 CONFIG_CPU_MIPSR1=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_HARDWARE_WATCHPOINTS=y
 
 #
 # Kernel type
@@ -107,190 +135,255 @@ CONFIG_32BIT=y
 CONFIG_PAGE_SIZE_4KB=y
 # CONFIG_PAGE_SIZE_8KB is not set
 # CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_32KB is not set
 # CONFIG_PAGE_SIZE_64KB is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_MIPS_MT_DISABLED=y
 # CONFIG_MIPS_MT_SMP is not set
 # CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
 CONFIG_64BIT_PHYS_ADDR=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 # CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
-CONFIG_RESOURCES_64BIT=y
-CONFIG_ZONE_DMA_FLAG=1
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 # CONFIG_HZ_48 is not set
-# CONFIG_HZ_100 is not set
+CONFIG_HZ_100=y
 # CONFIG_HZ_128 is not set
 # CONFIG_HZ_250 is not set
 # CONFIG_HZ_256 is not set
-CONFIG_HZ_1000=y
+# CONFIG_HZ_1000 is not set
 # CONFIG_HZ_1024 is not set
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_HZ=1000
+CONFIG_HZ=100
 CONFIG_PREEMPT_NONE=y
 # CONFIG_PREEMPT_VOLUNTARY is not set
 # CONFIG_PREEMPT is not set
 # CONFIG_KEXEC is not set
+# CONFIG_SECCOMP is not set
 CONFIG_LOCKDEP_SUPPORT=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 
 #
-# Code maturity level options
+# General setup
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION="-pb1550"
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_BZIP2 is not set
+CONFIG_KERNEL_LZMA=y
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
 CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
 # CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_RELAY=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 CONFIG_EMBEDDED=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
+# CONFIG_PCSPKR_PLATFORM is not set
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
 CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
 CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
+# CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
 
 #
-# Loadable module support
+# GCOV-based kernel profiling
 #
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
 
 #
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 # CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # Bus options (PCI, PCMCIA, EISA, ISA, TC)
 #
 CONFIG_HW_HAS_PCI=y
 CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_LEGACY=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 CONFIG_MMU=y
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
 CONFIG_PCMCIA_LOAD_CIS=y
 CONFIG_PCMCIA_IOCTL=y
-CONFIG_CARDBUS=y
+# CONFIG_CARDBUS is not set
 
 #
 # PC-card bridges
 #
 # CONFIG_YENTA is not set
-CONFIG_PD6729=m
+# CONFIG_PD6729 is not set
 # CONFIG_I82092 is not set
 # CONFIG_PCMCIA_AU1X00 is not set
-CONFIG_PCCARD_NONSTATIC=m
-
-#
-# PCI Hotplug Support
-#
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
 # CONFIG_HOTPLUG_PCI is not set
 
 #
 # Executable file formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
 # CONFIG_BINFMT_MISC is not set
 CONFIG_TRAD_SIGNALS=y
 
 #
 # Power management options
 #
-# CONFIG_PM is not set
-
-#
-# Networking
-#
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_HIBERNATION is not set
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 
 #
 # Networking options
 #
-# CONFIG_NETDEBUG is not set
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
+CONFIG_PACKET_MMAP=y
 CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-CONFIG_XFRM_MIGRATE=y
-CONFIG_NET_KEY=y
-CONFIG_NET_KEY_MIGRATE=y
+# CONFIG_NET_KEY is not set
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
 # CONFIG_IP_MROUTE is not set
@@ -301,110 +394,25 @@ CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
 # CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=m
-CONFIG_INET_XFRM_MODE_TUNNEL=m
-CONFIG_INET_XFRM_MODE_BEET=m
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
-CONFIG_TCP_MD5SIG=y
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
+# CONFIG_TCP_MD5SIG is not set
 # CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_NETWORK_SECMARK=y
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK_ENABLED=m
-CONFIG_NF_CONNTRACK_SUPPORT=y
-# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_SECMARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_SECMARK=m
-CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-# CONFIG_IP_NF_QUEUE is not set
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
 # CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -414,27 +422,30 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
 
 #
 # Network testing
 #
 # CONFIG_NET_PKTGEN is not set
 # CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
 # CONFIG_IRDA is not set
 # CONFIG_BT is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-CONFIG_WIRELESS_EXT=y
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
 
 #
 # Device Drivers
@@ -443,25 +454,25 @@ CONFIG_WIRELESS_EXT=y
 #
 # Generic Driver Options
 #
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
 CONFIG_STANDALONE=y
 CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=m
-
-#
-# Memory Technology Devices (MTD)
-#
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_CONCAT is not set
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
 
 #
 # User Modules And Translation Layers
@@ -474,6 +485,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
 
 #
 # RAM/ROM/Flash chip drivers
@@ -499,14 +511,14 @@ CONFIG_MTD_CFI_UTIL=y
 # CONFIG_MTD_RAM is not set
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
 
 #
 # Mapping drivers for chip access
 #
 # CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_ALCHEMY=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
@@ -524,30 +536,30 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_MTD_DOC2000 is not set
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_AU1550=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 # CONFIG_MTD_ONENAND is not set
 
 #
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
+# LPDDR flash memory drivers
 #
-# CONFIG_PNPACPI is not set
+# CONFIG_MTD_LPDDR is not set
 
 #
-# Block devices
+# UBI - Unsorted block images
 #
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
 # CONFIG_BLK_DEV_DAC960 is not set
@@ -555,67 +567,66 @@ CONFIG_MTD_ALCHEMY=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_CDROM_PKTCDVD_BUFFERS=8
-# CONFIG_CDROM_PKTCDVD_WCACHE is not set
-CONFIG_ATA_OVER_ETH=m
 
 #
-# Misc devices
-#
-CONFIG_SGI_IOC4=m
-# CONFIG_TIFM_CORE is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=y
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
 
 #
-# Please see Documentation/ide.txt for help/info on IDE drives
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
+CONFIG_IDE_XFER_MODE=y
+CONFIG_IDE_ATAPI=y
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_DELKIN is not set
-# CONFIG_BLK_DEV_IDECD is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
 
 #
 # IDE chipset support/bugfixes
 #
-CONFIG_IDE_GENERIC=y
+# CONFIG_IDE_GENERIC is not set
+# CONFIG_BLK_DEV_PLATFORM is not set
+CONFIG_BLK_DEV_IDEDMA_SFF=y
+
+#
+# PCI IDE chipsets support
+#
 CONFIG_BLK_DEV_IDEPCI=y
-# CONFIG_IDEPCI_SHARE_IRQ is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
 # CONFIG_BLK_DEV_OFFBOARD is not set
-CONFIG_BLK_DEV_GENERIC=y
+# CONFIG_BLK_DEV_GENERIC is not set
 # CONFIG_BLK_DEV_OPTI621 is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
-# CONFIG_IDEDMA_PCI_AUTO is not set
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_BLK_DEV_ALI15X3 is not set
 # CONFIG_BLK_DEV_AMD74XX is not set
 # CONFIG_BLK_DEV_CMD64X is not set
 # CONFIG_BLK_DEV_TRIFLEX is not set
-# CONFIG_BLK_DEV_CY82C693 is not set
 # CONFIG_BLK_DEV_CS5520 is not set
 # CONFIG_BLK_DEV_CS5530 is not set
-# CONFIG_BLK_DEV_HPT34X is not set
 CONFIG_BLK_DEV_HPT366=y
 # CONFIG_BLK_DEV_JMICRON is not set
 # CONFIG_BLK_DEV_SC1200 is not set
 # CONFIG_BLK_DEV_PIIX is not set
-CONFIG_BLK_DEV_IT8213=m
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
 # CONFIG_BLK_DEV_IT821X is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_PDC202XX_OLD is not set
@@ -625,82 +636,65 @@ CONFIG_BLK_DEV_IT8213=m
 # CONFIG_BLK_DEV_SLC90E66 is not set
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
-CONFIG_BLK_DEV_TC86C001=m
-# CONFIG_IDE_ARM is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
 CONFIG_BLK_DEV_IDEDMA=y
-# CONFIG_IDEDMA_IVB is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
 
 #
 # SCSI device support
 #
-CONFIG_RAID_ATTRS=m
+# CONFIG_RAID_ATTRS is not set
 # CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
 # CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
 # CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
 # CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
 # CONFIG_FUSION is not set
 
 #
 # IEEE 1394 (FireWire) support
 #
-# CONFIG_IEEE1394 is not set
 
 #
-# I2O device support
+# You can enable one or both FireWire driver stacks.
 #
-# CONFIG_I2O is not set
 
 #
-# Network device support
+# The newer stack is recommended.
 #
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
 CONFIG_NETDEVICES=y
 # CONFIG_DUMMY is not set
 # CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
-
-#
-# ARCnet devices
-#
+# CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-
-#
-# PHY device support
-#
 CONFIG_PHYLIB=y
 
 #
 # MII PHY device drivers
 #
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-# CONFIG_BROADCOM_PHY is not set
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
 # CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-# CONFIG_MII is not set
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
 CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNGEM is not set
@@ -708,88 +702,51 @@ CONFIG_MIPS_AU1X00_ENET=y
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set
-
-#
-# Tulip family network device support
-#
+# CONFIG_ETHOC is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
 # CONFIG_NET_TULIP is not set
 # CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_NET_PCI is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-# CONFIG_ACENIC is not set
-# CONFIG_DL2K is not set
-# CONFIG_E1000 is not set
-# CONFIG_NS83820 is not set
-# CONFIG_HAMACHI is not set
-# CONFIG_YELLOWFIN is not set
-# CONFIG_R8169 is not set
-# CONFIG_SIS190 is not set
-# CONFIG_SKGE is not set
-# CONFIG_SKY2 is not set
-# CONFIG_SK98LIN is not set
-# CONFIG_TIGON3 is not set
-# CONFIG_BNX2 is not set
-CONFIG_QLA3XXX=m
-# CONFIG_ATL1 is not set
-
-#
-# Ethernet (10000 Mbit)
-#
-# CONFIG_CHELSIO_T1 is not set
-CONFIG_CHELSIO_T3=m
-# CONFIG_IXGB is not set
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-CONFIG_NETXEN_NIC=m
-
-#
-# Token Ring devices
-#
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
+# CONFIG_WLAN is not set
 
 #
-# Wireless LAN (non-hamradio)
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_NET_RADIO is not set
 
 #
-# PCMCIA network device support
+# USB Network Adapters
 #
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
 # CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
 # CONFIG_WAN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-# CONFIG_PPP_BSDCOMP is not set
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
+# CONFIG_PPP is not set
 # CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
+# CONFIG_VMXNET3 is not set
 # CONFIG_ISDN is not set
-
-#
-# Telephony Support
-#
 # CONFIG_PHONE is not set
 
 #
@@ -797,16 +754,14 @@ CONFIG_SLHC=m
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
 CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
@@ -816,33 +771,34 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
 # CONFIG_INPUT_TOUCHSCREEN is not set
 # CONFIG_INPUT_MISC is not set
 
 #
 # Hardware I/O ports
 #
-CONFIG_SERIO=y
-# CONFIG_SERIO_I8042 is not set
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_PCIPS2 is not set
-# CONFIG_SERIO_LIBPS2 is not set
-CONFIG_SERIO_RAW=m
+# CONFIG_SERIO is not set
 # CONFIG_GAMEPORT is not set
 
 #
 # Character devices
 #
-# CONFIG_VT is not set
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_AU1X00_GPIO is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_PCI is not set
 # CONFIG_SERIAL_8250_CS is not set
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
@@ -856,282 +812,492 @@ CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_JSM is not set
 CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
 # CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
 # CONFIG_HW_RANDOM is not set
-# CONFIG_RTC is not set
-# CONFIG_GEN_RTC is not set
-# CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
 # CONFIG_APPLICOM is not set
-# CONFIG_DRM is not set
 
 #
 # PCMCIA character devices
 #
-CONFIG_SYNCLINK_CS=m
+# CONFIG_SYNCLINK_CS is not set
 # CONFIG_CARDMAN_4000 is not set
 # CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
 # CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
 
 #
-# TPM devices
+# I2C Algorithms
 #
-# CONFIG_TCG_TPM is not set
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
 
 #
-# I2C support
+# I2C Hardware Bus support
 #
-# CONFIG_I2C is not set
 
 #
-# SPI support
+# PC SMBus host controller drivers
 #
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
 
 #
-# Dallas's 1-wire bus
+# I2C system bus drivers (mostly embedded / system-on-chip)
 #
-# CONFIG_W1 is not set
+CONFIG_I2C_AU1550=y
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
-# Hardware Monitoring support
+# Other I2C/SMBus bus drivers
 #
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
-# CONFIG_HWMON_VID is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 
 #
-# Multimedia devices
+# Sonics Silicon Backplane
 #
-# CONFIG_VIDEO_DEV is not set
+# CONFIG_SSB is not set
 
 #
-# Digital Video Broadcasting Devices
+# Multifunction device drivers
 #
-# CONFIG_DVB is not set
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
-# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
 # CONFIG_BACKLIGHT_LCD_SUPPORT is not set
 
 #
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# HID Devices
+# Display device support
 #
-# CONFIG_HID is not set
+# CONFIG_DISPLAY_SUPPORT is not set
 
 #
-# USB support
+# Console display driver support
 #
+CONFIG_VGA_CONSOLE=y
+# CONFIG_VGACON_SOFT_SCROLLBACK is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
 CONFIG_USB_ARCH_HAS_HCD=y
 CONFIG_USB_ARCH_HAS_OHCI=y
 CONFIG_USB_ARCH_HAS_EHCI=y
-# CONFIG_USB is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
 
 #
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+# Miscellaneous USB options
 #
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
 
 #
-# USB Gadget Support
+# USB Host Controller Drivers
 #
-# CONFIG_USB_GADGET is not set
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
 
 #
-# MMC/SD Card support
+# USB Device Class drivers
 #
-# CONFIG_MMC is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
 
 #
-# LED devices
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
 #
-# CONFIG_NEW_LEDS is not set
 
 #
-# LED drivers
+# also be needed; see USB_STORAGE Help for more info
 #
+# CONFIG_USB_LIBUSUAL is not set
 
 #
-# LED Triggers
+# USB Imaging devices
 #
+# CONFIG_USB_MDC800 is not set
 
 #
-# InfiniBand support
+# USB port drivers
 #
-# CONFIG_INFINIBAND is not set
+# CONFIG_USB_SERIAL is not set
 
 #
-# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+# USB Miscellaneous drivers
 #
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
 
 #
-# Real Time Clock
+# RTC interfaces
 #
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
 
 #
-# DMA Engine support
+# I2C RTC drivers
 #
-# CONFIG_DMA_ENGINE is not set
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
 
 #
-# DMA Clients
+# SPI RTC drivers
 #
 
 #
-# DMA Devices
+# Platform RTC drivers
 #
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
 
 #
-# Auxiliary Display support
+# on-CPU RTC drivers
 #
+CONFIG_RTC_DRV_AU1XXX=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
 
 #
-# Virtualization
+# TI VLYNQ
 #
+# CONFIG_STAGING is not set
 
 #
 # File systems
 #
 CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-# CONFIG_EXT2_FS_SECURITY is not set
+# CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
+# CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_FUSE_FS=m
-CONFIG_GENERIC_ACL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
 
 #
 # CD-ROM/DVD Filesystems
 #
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_UDF_NLS=y
 
 #
 # DOS/FAT/NT Filesystems
 #
+CONFIG_FAT_FS=y
 # CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
 # Pseudo filesystems
 #
 CONFIG_PROC_FS=y
-CONFIG_PROC_KCORE=y
+# CONFIG_PROC_KCORE is not set
 CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
 CONFIG_SYSFS=y
 CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-CONFIG_CONFIGFS_FS=m
-
-#
-# Miscellaneous filesystems
-#
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_HFSPLUS_FS is not set
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=m
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
 # CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
 # CONFIG_HPFS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
+CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
 # CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=m
-# CONFIG_NFSD_V3 is not set
-# CONFIG_NFSD_TCP is not set
 CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
 CONFIG_LOCKD=y
-CONFIG_EXPORTFS=m
+CONFIG_LOCKD_V4=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
 # CONFIG_RPCSEC_GSS_KRB5 is not set
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_CIFS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=m
+CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
+CONFIG_NLS_CODEPAGE_437=y
 # CONFIG_NLS_CODEPAGE_737 is not set
 # CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
 # CONFIG_NLS_CODEPAGE_855 is not set
 # CONFIG_NLS_CODEPAGE_857 is not set
 # CONFIG_NLS_CODEPAGE_860 is not set
@@ -1148,10 +1314,10 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_CODEPAGE_949 is not set
 # CONFIG_NLS_CODEPAGE_874 is not set
 # CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
+CONFIG_NLS_CODEPAGE_1250=y
 # CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
 # CONFIG_NLS_ISO8859_2 is not set
 # CONFIG_NLS_ISO8859_3 is not set
 # CONFIG_NLS_ISO8859_4 is not set
@@ -1161,38 +1327,75 @@ CONFIG_NLS_DEFAULT="iso8859-1"
 # CONFIG_NLS_ISO8859_9 is not set
 # CONFIG_NLS_ISO8859_13 is not set
 # CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
+CONFIG_NLS_ISO8859_15=y
 # CONFIG_NLS_KOI8_R is not set
 # CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-CONFIG_DLM=m
-CONFIG_DLM_TCP=y
-# CONFIG_DLM_SCTP is not set
-# CONFIG_DLM_DEBUG is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
 #
 CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 # CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
 # CONFIG_MAGIC_SYSRQ is not set
+CONFIG_STRIP_ASM_SYMS=y
 # CONFIG_UNUSED_SYMBOLS is not set
 # CONFIG_DEBUG_FS is not set
 # CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CROSSCOMPILE=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_DETECT_SOFTLOCKUP is not set
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_EARLY_PRINTK=y
 # CONFIG_CMDLINE_BOOL is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_RUNTIME_DEBUG is not set
+CONFIG_DEBUG_ZBOOT=y
 
 #
 # Security options
@@ -1200,67 +1403,32 @@ CONFIG_CROSSCOMPILE=y
 CONFIG_KEYS=y
 CONFIG_KEYS_DEBUG_PROC_KEYS=y
 # CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_TGR192=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_CAMELLIA=m
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
+CONFIG_SECURITYFS=y
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
 
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=y
 CONFIG_CRC32=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=m
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_PLIST=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/mips/dec/kn01-berr.c b/arch/mips/dec/kn01-berr.c
index b0dc6d53edd6..94d23b4a7dc3 100644
--- a/arch/mips/dec/kn01-berr.c
+++ b/arch/mips/dec/kn01-berr.c
@@ -46,7 +46,7 @@
  * There is no default value -- it has to be initialized.
  */
 u16 cached_kn01_csr;
-DEFINE_SPINLOCK(kn01_lock);
+static DEFINE_RAW_SPINLOCK(kn01_lock);
 
 
 static inline void dec_kn01_be_ack(void)
@@ -54,12 +54,12 @@ static inline void dec_kn01_be_ack(void)
         volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
         unsigned long flags;
 
-        spin_lock_irqsave(&kn01_lock, flags);
+        raw_spin_lock_irqsave(&kn01_lock, flags);
 
         *csr = cached_kn01_csr | KN01_CSR_MEMERR;       /* Clear bus IRQ. */
         iob();
 
-        spin_unlock_irqrestore(&kn01_lock, flags);
+        raw_spin_unlock_irqrestore(&kn01_lock, flags);
 }
 
 static int dec_kn01_be_backend(struct pt_regs *regs, int is_fixup, int invoker)
@@ -182,7 +182,7 @@ void __init dec_kn01_be_init(void)
         volatile u16 *csr = (void *)CKSEG1ADDR(KN01_SLOT_BASE + KN01_CSR);
         unsigned long flags;
 
-        spin_lock_irqsave(&kn01_lock, flags);
+        raw_spin_lock_irqsave(&kn01_lock, flags);
 
         /* Preset write-only bits of the Control Register cache. */
         cached_kn01_csr = *csr;
@@ -194,7 +194,7 @@ void __init dec_kn01_be_init(void)
         *csr = cached_kn01_csr;
         iob();
 
-        spin_unlock_irqrestore(&kn01_lock, flags);
+        raw_spin_unlock_irqrestore(&kn01_lock, flags);
 
         /* Clear any leftover errors from the firmware. */
         dec_kn01_be_ack();
diff --git a/arch/mips/dec/prom/locore.S b/arch/mips/dec/prom/locore.S
index d9acdcefee81..f72b5741025f 100644
--- a/arch/mips/dec/prom/locore.S
+++ b/arch/mips/dec/prom/locore.S
@@ -27,4 +27,3 @@ NESTED(genexcept_early, 0, sp)
         jr      k0
          rfe
 END(genexcept_early)
-
diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index dd75d673447e..519197ede089 100644
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -137,7 +137,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 {
         int result;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 int temp;
@@ -189,7 +189,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
 {
         int result;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 int temp;
@@ -249,7 +249,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
 {
         int result;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 int temp;
@@ -516,7 +516,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v)
 {
         long result;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 long temp;
@@ -568,7 +568,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
 {
         long result;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 long temp;
@@ -628,7 +628,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
 {
         long result;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 long temp;
@@ -788,9 +788,9 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
  * atomic*_return operations are serializing but not the non-*_return
  * versions.
  */
-#define smp_mb__before_atomic_dec()     smp_llsc_mb()
+#define smp_mb__before_atomic_dec()     smp_mb__before_llsc()
 #define smp_mb__after_atomic_dec()      smp_llsc_mb()
-#define smp_mb__before_atomic_inc()     smp_llsc_mb()
+#define smp_mb__before_atomic_inc()     smp_mb__before_llsc()
 #define smp_mb__after_atomic_inc()      smp_llsc_mb()
 
 #include <asm-generic/atomic-long.h>
diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index 8e9ac313ca3b..c0884f02d3a6 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -88,12 +88,20 @@
                 : /* no output */               \
                 : "m" (*(int *)CKSEG1)          \
                 : "memory")
-
-#define fast_wmb()      __sync()
-#define fast_rmb()      __sync()
-#define fast_mb()       __sync()
-#ifdef CONFIG_SGI_IP28
-#define fast_iob()                              \
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+# define OCTEON_SYNCW_STR       ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
+# define __syncw()      __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
+
+# define fast_wmb()     __syncw()
+# define fast_rmb()     barrier()
+# define fast_mb()      __sync()
+# define fast_iob()     do { } while (0)
+#else /* ! CONFIG_CPU_CAVIUM_OCTEON */
+# define fast_wmb()     __sync()
+# define fast_rmb()     __sync()
+# define fast_mb()      __sync()
+# ifdef CONFIG_SGI_IP28
+#  define fast_iob()                            \
         __asm__ __volatile__(                   \
                 ".set   push\n\t"               \
                 ".set   noreorder\n\t"          \
@@ -104,13 +112,14 @@
                 : /* no output */               \
                 : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
                 : "memory")
-#else
-#define fast_iob()                              \
+# else
+#  define fast_iob()                            \
         do {                                    \
                 __sync();                       \
                 __fast_iob();                   \
         } while (0)
-#endif
+# endif
+#endif /* CONFIG_CPU_CAVIUM_OCTEON */
 
 #ifdef CONFIG_CPU_HAS_WB
 
@@ -131,25 +140,42 @@
 #endif /* !CONFIG_CPU_HAS_WB */
 
 #if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
-#define __WEAK_ORDERING_MB      "       sync    \n"
+# ifdef CONFIG_CPU_CAVIUM_OCTEON
+#  define smp_mb()      __sync()
+#  define smp_rmb()     barrier()
+#  define smp_wmb()     __syncw()
+# else
+#  define smp_mb()      __asm__ __volatile__("sync" : : :"memory")
+#  define smp_rmb()     __asm__ __volatile__("sync" : : :"memory")
+#  define smp_wmb()     __asm__ __volatile__("sync" : : :"memory")
+# endif
 #else
-#define __WEAK_ORDERING_MB      "               \n"
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
 #endif
+
 #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
 #define __WEAK_LLSC_MB          "       sync    \n"
 #else
 #define __WEAK_LLSC_MB          "               \n"
 #endif
 
-#define smp_mb()        __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-#define smp_rmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-#define smp_wmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-
 #define set_mb(var, value) \
         do { var = value; smp_mb(); } while (0)
 
 #define smp_llsc_mb()   __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define smp_llsc_rmb()  __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define smp_llsc_wmb()  __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
+
+#ifdef CONFIG_CPU_CAVIUM_OCTEON
+#define smp_mb__before_llsc() smp_wmb()
+/* Cause previous writes to become visible on all CPUs as soon as possible */
+#define nudge_writes() __asm__ __volatile__(".set push\n\t"             \
+                                            ".set arch=octeon\n\t"      \
+                                            "syncw\n\t"                 \
+                                            ".set pop" : : : "memory")
+#else
+#define smp_mb__before_llsc() smp_llsc_mb()
+#define nudge_writes() mb()
+#endif
 
 #endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 84a383806b2c..9255cfbee459 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -42,7 +42,7 @@
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
-#define smp_mb__before_clear_bit()      smp_llsc_mb()
+#define smp_mb__before_clear_bit()      smp_mb__before_llsc()
 #define smp_mb__after_clear_bit()       smp_llsc_mb()
 
 /*
@@ -258,7 +258,7 @@ static inline int test_and_set_bit(unsigned long nr,
         unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -395,7 +395,7 @@ static inline int test_and_clear_bit(unsigned long nr,
         unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
@@ -485,7 +485,7 @@ static inline int test_and_change_bit(unsigned long nr,
         unsigned short bit = nr & SZLONG_MASK;
         unsigned long res;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 815a438a268d..ed9aaaaf0749 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -72,14 +72,14 @@
  */
 extern void __cmpxchg_called_with_bad_pointer(void);
 
-#define __cmpxchg(ptr, old, new, barrier)                               \
+#define __cmpxchg(ptr, old, new, pre_barrier, post_barrier)             \
 ({                                                                      \
         __typeof__(ptr) __ptr = (ptr);                                  \
         __typeof__(*(ptr)) __old = (old);                               \
         __typeof__(*(ptr)) __new = (new);                               \
         __typeof__(*(ptr)) __res = 0;                                   \
                                                                         \
-        barrier;                                                        \
+        pre_barrier;                                                    \
                                                                         \
         switch (sizeof(*(__ptr))) {                                     \
         case 4:                                                         \
@@ -96,13 +96,13 @@ extern void __cmpxchg_called_with_bad_pointer(void);
                 break;                                                  \
         }                                                               \
                                                                         \
-        barrier;                                                        \
+        post_barrier;                                                   \
                                                                         \
         __res;                                                          \
 })
 
-#define cmpxchg(ptr, old, new)          __cmpxchg(ptr, old, new, smp_llsc_mb())
-#define cmpxchg_local(ptr, old, new)    __cmpxchg(ptr, old, new, )
+#define cmpxchg(ptr, old, new)          __cmpxchg(ptr, old, new, smp_mb__before_llsc(), smp_llsc_mb())
+#define cmpxchg_local(ptr, old, new)    __cmpxchg(ptr, old, new, , )
 
 #define cmpxchg64(ptr, o, n)                                            \
   ({                                                                    \
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 272c5ef35bbb..ac73cede3a0a 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,6 +95,9 @@
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
+#ifndef kernel_uses_smartmips_rixi
+#define kernel_uses_smartmips_rixi 0
+#endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 #endif
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index cf373a95fe4a..a5acda416946 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -224,7 +224,7 @@ enum cpu_type_enum {
          * MIPS64 class processors
          */
         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-        CPU_CAVIUM_OCTEON,
+        CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
 
         CPU_LAST
 };
diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h
index 559db66b9790..4c51401b5537 100644
--- a/arch/mips/include/asm/current.h
+++ b/arch/mips/include/asm/current.h
@@ -1,23 +1 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2002 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CURRENT_H
-#define _ASM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct * get_current(void)
-{
-        return current_thread_info()->task;
-}
-
-#define current         get_current()
-
-#endif /* _ASM_CURRENT_H */
+#include <asm-generic/current.h>
diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 28fa717ac423..88d9ffd74258 100644
--- a/arch/mips/include/asm/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -80,7 +80,6 @@
 struct pt_regs;
 
 extern u16 cached_kn01_csr;
-extern spinlock_t kn01_lock;
 
 extern void dec_kn01_be_init(void);
 extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
diff --git a/arch/mips/include/asm/device.h b/arch/mips/include/asm/device.h
index d8f9872b0e2d..06746c5e8099 100644
--- a/arch/mips/include/asm/device.h
+++ b/arch/mips/include/asm/device.h
@@ -4,4 +4,3 @@
  * This file is released under the GPLv2
  */
 #include <asm-generic/device.h>
-
diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 7a6a35dbe529..e53d7bed5cda 100644
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -334,14 +334,14 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
 
 #define ELF_HWCAP       (0)
 
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-
-   For the moment, we have only optimizations for the Intel generations,
-   but that could change... */
+/*
+ * This yields a string that ld.so will use to load implementation
+ * specific libraries for optimization.  This is more specific in
+ * intent than poking at uname or /proc/cpuinfo.
+ */
 
-#define ELF_PLATFORM  (NULL)
+#define ELF_PLATFORM  __elf_platform
+extern const char *__elf_platform;
 
 /*
  * See comments in asm-alpha/elf.h, this is the same thing
diff --git a/arch/mips/include/asm/ftrace.h b/arch/mips/include/asm/ftrace.h
index 3986cd8704f3..ce35c9af0c28 100644
--- a/arch/mips/include/asm/ftrace.h
+++ b/arch/mips/include/asm/ftrace.h
@@ -4,7 +4,7 @@
  * more details.
  *
  * Copyright (C) 2009 DSLab, Lanzhou University, China
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  */
 
 #ifndef _ASM_MIPS_FTRACE_H
diff --git a/arch/mips/include/asm/i8259.h b/arch/mips/include/asm/i8259.h
index 8572a2d90484..c7e278447c0a 100644
--- a/arch/mips/include/asm/i8259.h
+++ b/arch/mips/include/asm/i8259.h
@@ -35,7 +35,7 @@
 #define SLAVE_ICW4_DEFAULT      0x01
 #define PIC_ICW4_AEOI           2
 
-extern spinlock_t i8259A_lock;
+extern raw_spinlock_t i8259A_lock;
 
 extern int i8259A_irq_pending(unsigned int irq);
 extern void make_8259A_irq(unsigned int irq);
@@ -51,7 +51,7 @@ static inline int i8259_irq(void)
 {
         int irq;
 
-        spin_lock(&i8259A_lock);
+        raw_spin_lock(&i8259A_lock);
 
         /* Perform an interrupt acknowledge cycle on controller 1. */
         outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
@@ -78,7 +78,7 @@ static inline int i8259_irq(void)
                         irq = -1;
         }
 
-        spin_unlock(&i8259A_lock);
+        raw_spin_unlock(&i8259A_lock);
 
         return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
 }
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 436878e4e063..c98bf514ec7d 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -447,6 +447,24 @@ __BUILDIO(q, u64)
 #define readl_relaxed                   readl
 #define readq_relaxed                   readq
 
+#define readb_be(addr)                                                  \
+        __raw_readb((__force unsigned *)(addr))
+#define readw_be(addr)                                                  \
+        be16_to_cpu(__raw_readw((__force unsigned *)(addr)))
+#define readl_be(addr)                                                  \
+        be32_to_cpu(__raw_readl((__force unsigned *)(addr)))
+#define readq_be(addr)                                                  \
+        be64_to_cpu(__raw_readq((__force unsigned *)(addr)))
+
+#define writeb_be(val, addr)                                            \
+        __raw_writeb((val), (__force unsigned *)(addr))
+#define writew_be(val, addr)                                            \
+        __raw_writew(cpu_to_be16((val)), (__force unsigned *)(addr))
+#define writel_be(val, addr)                                            \
+        __raw_writel(cpu_to_be32((val)), (__force unsigned *)(addr))
+#define writeq_be(val, addr)                                            \
+        __raw_writeq(cpu_to_be64((val)), (__force unsigned *)(addr))
+
 /*
  * Some code tests for these symbols
  */
diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 21cbbc706448..f1cf38943497 100644
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -105,26 +105,9 @@ static inline u8 ar7_chip_rev(void)
         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
 }
 
-static inline int ar7_cpu_freq(void)
-{
-        return ar7_cpu_clock;
-}
-
-static inline int ar7_bus_freq(void)
-{
-        return ar7_bus_clock;
-}
-
-static inline int ar7_vbus_freq(void)
-{
-        return ar7_bus_clock / 2;
-}
-#define ar7_cpmac_freq ar7_vbus_freq
-
-static inline int ar7_dsp_freq(void)
-{
-        return ar7_dsp_clock;
-}
+struct clk {
+        unsigned int    rate;
+};
 
 static inline int ar7_has_high_cpmac(void)
 {
diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h
index cbe9c4f126df..73f9b162c970 100644
--- a/arch/mips/include/asm/mach-ar7/gpio.h
+++ b/arch/mips/include/asm/mach-ar7/gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2007-2009 Florian Fainelli <florian@openwrt.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -22,88 +22,18 @@
 #include <asm/mach-ar7/ar7.h>
 
 #define AR7_GPIO_MAX 32
+#define NR_BUILTIN_GPIO AR7_GPIO_MAX
 
-extern int gpio_request(unsigned gpio, const char *label);
-extern void gpio_free(unsigned gpio);
+#define gpio_to_irq(gpio)       NULL
 
-/* Common GPIO layer */
-static inline int gpio_get_value(unsigned gpio)
-{
-        void __iomem *gpio_in =
-                (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
 
-        return readl(gpio_in) & (1 << gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        void __iomem *gpio_out =
-                (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
-        unsigned tmp;
-
-        tmp = readl(gpio_out) & ~(1 << gpio);
-        if (value)
-                tmp |= 1 << gpio;
-        writel(tmp, gpio_out);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        void __iomem *gpio_dir =
-                (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
-
-        if (gpio >= AR7_GPIO_MAX)
-                return -EINVAL;
-
-        writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
-
-        return 0;
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        void __iomem *gpio_dir =
-                (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
-
-        if (gpio >= AR7_GPIO_MAX)
-                return -EINVAL;
-
-        gpio_set_value(gpio, value);
-        writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
-
-        return 0;
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return -EINVAL;
-}
+#define gpio_cansleep __gpio_cansleep
 
 /* Board specific GPIO functions */
-static inline int ar7_gpio_enable(unsigned gpio)
-{
-        void __iomem *gpio_en =
-                (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
-
-        writel(readl(gpio_en) | (1 << gpio), gpio_en);
-
-        return 0;
-}
-
-static inline int ar7_gpio_disable(unsigned gpio)
-{
-        void __iomem *gpio_en =
-                (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
-
-        writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
-
-        return 0;
-}
+int ar7_gpio_enable(unsigned gpio);
+int ar7_gpio_disable(unsigned gpio);
 
 #include <asm-generic/gpio.h>
 
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 854e95f1b07c..ae07423e6e82 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -130,6 +130,56 @@ static inline int au1xxx_cpu_needs_config_od(void)
         return 0;
 }
 
+#define ALCHEMY_CPU_UNKNOWN     -1
+#define ALCHEMY_CPU_AU1000      0
+#define ALCHEMY_CPU_AU1500      1
+#define ALCHEMY_CPU_AU1100      2
+#define ALCHEMY_CPU_AU1550      3
+#define ALCHEMY_CPU_AU1200      4
+
+static inline int alchemy_get_cputype(void)
+{
+        switch (read_c0_prid() & 0xffff0000) {
+        case 0x00030000:
+                return ALCHEMY_CPU_AU1000;
+                break;
+        case 0x01030000:
+                return ALCHEMY_CPU_AU1500;
+                break;
+        case 0x02030000:
+                return ALCHEMY_CPU_AU1100;
+                break;
+        case 0x03030000:
+                return ALCHEMY_CPU_AU1550;
+                break;
+        case 0x04030000:
+        case 0x05030000:
+                return ALCHEMY_CPU_AU1200;
+                break;
+        }
+
+        return ALCHEMY_CPU_UNKNOWN;
+}
+
+static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
+{
+        void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
+        int timeout, i;
+
+        /* check LSR TX_EMPTY bit */
+        timeout = 0xffffff;
+        do {
+                if (__raw_readl(base + 0x1c) & 0x20)
+                        break;
+                /* slow down */
+                for (i = 10000; i; i--)
+                        asm volatile ("nop");
+        } while (--timeout);
+
+        __raw_writel(c, base + 0x04);   /* tx */
+        wmb();
+}
+
 /* arch/mips/au1000/common/clocks.c */
 extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
@@ -143,20 +193,332 @@ void au_sleep(void);
 void save_au1xxx_intctl(void);
 void restore_au1xxx_intctl(void);
 
-/*
- * Every board describes its IRQ mapping with this table.
- */
-struct au1xxx_irqmap {
-        int     im_irq;
-        int     im_type;
-        int     im_request;
+
+/* SOC Interrupt numbers */
+
+#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
+#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
+#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)
+#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
+#define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
+
+enum soc_au1000_ints {
+        AU1000_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1000_UART0_INT        = AU1000_FIRST_INT,
+        AU1000_UART1_INT,
+        AU1000_UART2_INT,
+        AU1000_UART3_INT,
+        AU1000_SSI0_INT,
+        AU1000_SSI1_INT,
+        AU1000_DMA_INT_BASE,
+
+        AU1000_TOY_INT          = AU1000_FIRST_INT + 14,
+        AU1000_TOY_MATCH0_INT,
+        AU1000_TOY_MATCH1_INT,
+        AU1000_TOY_MATCH2_INT,
+        AU1000_RTC_INT,
+        AU1000_RTC_MATCH0_INT,
+        AU1000_RTC_MATCH1_INT,
+        AU1000_RTC_MATCH2_INT,
+        AU1000_IRDA_TX_INT,
+        AU1000_IRDA_RX_INT,
+        AU1000_USB_DEV_REQ_INT,
+        AU1000_USB_DEV_SUS_INT,
+        AU1000_USB_HOST_INT,
+        AU1000_ACSYNC_INT,
+        AU1000_MAC0_DMA_INT,
+        AU1000_MAC1_DMA_INT,
+        AU1000_I2S_UO_INT,
+        AU1000_AC97C_INT,
+        AU1000_GPIO0_INT,
+        AU1000_GPIO1_INT,
+        AU1000_GPIO2_INT,
+        AU1000_GPIO3_INT,
+        AU1000_GPIO4_INT,
+        AU1000_GPIO5_INT,
+        AU1000_GPIO6_INT,
+        AU1000_GPIO7_INT,
+        AU1000_GPIO8_INT,
+        AU1000_GPIO9_INT,
+        AU1000_GPIO10_INT,
+        AU1000_GPIO11_INT,
+        AU1000_GPIO12_INT,
+        AU1000_GPIO13_INT,
+        AU1000_GPIO14_INT,
+        AU1000_GPIO15_INT,
+        AU1000_GPIO16_INT,
+        AU1000_GPIO17_INT,
+        AU1000_GPIO18_INT,
+        AU1000_GPIO19_INT,
+        AU1000_GPIO20_INT,
+        AU1000_GPIO21_INT,
+        AU1000_GPIO22_INT,
+        AU1000_GPIO23_INT,
+        AU1000_GPIO24_INT,
+        AU1000_GPIO25_INT,
+        AU1000_GPIO26_INT,
+        AU1000_GPIO27_INT,
+        AU1000_GPIO28_INT,
+        AU1000_GPIO29_INT,
+        AU1000_GPIO30_INT,
+        AU1000_GPIO31_INT,
 };
 
-/* core calls this function to let boards initialize other IRQ sources */
-void board_init_irq(void);
+enum soc_au1100_ints {
+        AU1100_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1100_UART0_INT        = AU1100_FIRST_INT,
+        AU1100_UART1_INT,
+        AU1100_SD_INT,
+        AU1100_UART3_INT,
+        AU1100_SSI0_INT,
+        AU1100_SSI1_INT,
+        AU1100_DMA_INT_BASE,
+
+        AU1100_TOY_INT          = AU1100_FIRST_INT + 14,
+        AU1100_TOY_MATCH0_INT,
+        AU1100_TOY_MATCH1_INT,
+        AU1100_TOY_MATCH2_INT,
+        AU1100_RTC_INT,
+        AU1100_RTC_MATCH0_INT,
+        AU1100_RTC_MATCH1_INT,
+        AU1100_RTC_MATCH2_INT,
+        AU1100_IRDA_TX_INT,
+        AU1100_IRDA_RX_INT,
+        AU1100_USB_DEV_REQ_INT,
+        AU1100_USB_DEV_SUS_INT,
+        AU1100_USB_HOST_INT,
+        AU1100_ACSYNC_INT,
+        AU1100_MAC0_DMA_INT,
+        AU1100_GPIO208_215_INT,
+        AU1100_LCD_INT,
+        AU1100_AC97C_INT,
+        AU1100_GPIO0_INT,
+        AU1100_GPIO1_INT,
+        AU1100_GPIO2_INT,
+        AU1100_GPIO3_INT,
+        AU1100_GPIO4_INT,
+        AU1100_GPIO5_INT,
+        AU1100_GPIO6_INT,
+        AU1100_GPIO7_INT,
+        AU1100_GPIO8_INT,
+        AU1100_GPIO9_INT,
+        AU1100_GPIO10_INT,
+        AU1100_GPIO11_INT,
+        AU1100_GPIO12_INT,
+        AU1100_GPIO13_INT,
+        AU1100_GPIO14_INT,
+        AU1100_GPIO15_INT,
+        AU1100_GPIO16_INT,
+        AU1100_GPIO17_INT,
+        AU1100_GPIO18_INT,
+        AU1100_GPIO19_INT,
+        AU1100_GPIO20_INT,
+        AU1100_GPIO21_INT,
+        AU1100_GPIO22_INT,
+        AU1100_GPIO23_INT,
+        AU1100_GPIO24_INT,
+        AU1100_GPIO25_INT,
+        AU1100_GPIO26_INT,
+        AU1100_GPIO27_INT,
+        AU1100_GPIO28_INT,
+        AU1100_GPIO29_INT,
+        AU1100_GPIO30_INT,
+        AU1100_GPIO31_INT,
+};
 
-/* boards call this to register additional (GPIO) interrupts */
-void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
+enum soc_au1500_ints {
+        AU1500_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1500_UART0_INT        = AU1500_FIRST_INT,
+        AU1500_PCI_INTA,
+        AU1500_PCI_INTB,
+        AU1500_UART3_INT,
+        AU1500_PCI_INTC,
+        AU1500_PCI_INTD,
+        AU1500_DMA_INT_BASE,
+
+        AU1500_TOY_INT          = AU1500_FIRST_INT + 14,
+        AU1500_TOY_MATCH0_INT,
+        AU1500_TOY_MATCH1_INT,
+        AU1500_TOY_MATCH2_INT,
+        AU1500_RTC_INT,
+        AU1500_RTC_MATCH0_INT,
+        AU1500_RTC_MATCH1_INT,
+        AU1500_RTC_MATCH2_INT,
+        AU1500_PCI_ERR_INT,
+        AU1500_RESERVED_INT,
+        AU1500_USB_DEV_REQ_INT,
+        AU1500_USB_DEV_SUS_INT,
+        AU1500_USB_HOST_INT,
+        AU1500_ACSYNC_INT,
+        AU1500_MAC0_DMA_INT,
+        AU1500_MAC1_DMA_INT,
+        AU1500_AC97C_INT        = AU1500_FIRST_INT + 31,
+        AU1500_GPIO0_INT,
+        AU1500_GPIO1_INT,
+        AU1500_GPIO2_INT,
+        AU1500_GPIO3_INT,
+        AU1500_GPIO4_INT,
+        AU1500_GPIO5_INT,
+        AU1500_GPIO6_INT,
+        AU1500_GPIO7_INT,
+        AU1500_GPIO8_INT,
+        AU1500_GPIO9_INT,
+        AU1500_GPIO10_INT,
+        AU1500_GPIO11_INT,
+        AU1500_GPIO12_INT,
+        AU1500_GPIO13_INT,
+        AU1500_GPIO14_INT,
+        AU1500_GPIO15_INT,
+        AU1500_GPIO200_INT,
+        AU1500_GPIO201_INT,
+        AU1500_GPIO202_INT,
+        AU1500_GPIO203_INT,
+        AU1500_GPIO20_INT,
+        AU1500_GPIO204_INT,
+        AU1500_GPIO205_INT,
+        AU1500_GPIO23_INT,
+        AU1500_GPIO24_INT,
+        AU1500_GPIO25_INT,
+        AU1500_GPIO26_INT,
+        AU1500_GPIO27_INT,
+        AU1500_GPIO28_INT,
+        AU1500_GPIO206_INT,
+        AU1500_GPIO207_INT,
+        AU1500_GPIO208_215_INT,
+};
+
+enum soc_au1550_ints {
+        AU1550_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1550_UART0_INT        = AU1550_FIRST_INT,
+        AU1550_PCI_INTA,
+        AU1550_PCI_INTB,
+        AU1550_DDMA_INT,
+        AU1550_CRYPTO_INT,
+        AU1550_PCI_INTC,
+        AU1550_PCI_INTD,
+        AU1550_PCI_RST_INT,
+        AU1550_UART1_INT,
+        AU1550_UART3_INT,
+        AU1550_PSC0_INT,
+        AU1550_PSC1_INT,
+        AU1550_PSC2_INT,
+        AU1550_PSC3_INT,
+        AU1550_TOY_INT,
+        AU1550_TOY_MATCH0_INT,
+        AU1550_TOY_MATCH1_INT,
+        AU1550_TOY_MATCH2_INT,
+        AU1550_RTC_INT,
+        AU1550_RTC_MATCH0_INT,
+        AU1550_RTC_MATCH1_INT,
+        AU1550_RTC_MATCH2_INT,
+
+        AU1550_NAND_INT         = AU1550_FIRST_INT + 23,
+        AU1550_USB_DEV_REQ_INT,
+        AU1550_USB_DEV_SUS_INT,
+        AU1550_USB_HOST_INT,
+        AU1550_MAC0_DMA_INT,
+        AU1550_MAC1_DMA_INT,
+        AU1550_GPIO0_INT        = AU1550_FIRST_INT + 32,
+        AU1550_GPIO1_INT,
+        AU1550_GPIO2_INT,
+        AU1550_GPIO3_INT,
+        AU1550_GPIO4_INT,
+        AU1550_GPIO5_INT,
+        AU1550_GPIO6_INT,
+        AU1550_GPIO7_INT,
+        AU1550_GPIO8_INT,
+        AU1550_GPIO9_INT,
+        AU1550_GPIO10_INT,
+        AU1550_GPIO11_INT,
+        AU1550_GPIO12_INT,
+        AU1550_GPIO13_INT,
+        AU1550_GPIO14_INT,
+        AU1550_GPIO15_INT,
+        AU1550_GPIO200_INT,
+        AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
+        AU1550_GPIO16_INT,
+        AU1550_GPIO17_INT,
+        AU1550_GPIO20_INT,
+        AU1550_GPIO21_INT,
+        AU1550_GPIO22_INT,
+        AU1550_GPIO23_INT,
+        AU1550_GPIO24_INT,
+        AU1550_GPIO25_INT,
+        AU1550_GPIO26_INT,
+        AU1550_GPIO27_INT,
+        AU1550_GPIO28_INT,
+        AU1550_GPIO206_INT,
+        AU1550_GPIO207_INT,
+        AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
+};
+
+enum soc_au1200_ints {
+        AU1200_FIRST_INT        = AU1000_INTC0_INT_BASE,
+        AU1200_UART0_INT        = AU1200_FIRST_INT,
+        AU1200_SWT_INT,
+        AU1200_SD_INT,
+        AU1200_DDMA_INT,
+        AU1200_MAE_BE_INT,
+        AU1200_GPIO200_INT,
+        AU1200_GPIO201_INT,
+        AU1200_GPIO202_INT,
+        AU1200_UART1_INT,
+        AU1200_MAE_FE_INT,
+        AU1200_PSC0_INT,
+        AU1200_PSC1_INT,
+        AU1200_AES_INT,
+        AU1200_CAMERA_INT,
+        AU1200_TOY_INT,
+        AU1200_TOY_MATCH0_INT,
+        AU1200_TOY_MATCH1_INT,
+        AU1200_TOY_MATCH2_INT,
+        AU1200_RTC_INT,
+        AU1200_RTC_MATCH0_INT,
+        AU1200_RTC_MATCH1_INT,
+        AU1200_RTC_MATCH2_INT,
+        AU1200_GPIO203_INT,
+        AU1200_NAND_INT,
+        AU1200_GPIO204_INT,
+        AU1200_GPIO205_INT,
+        AU1200_GPIO206_INT,
+        AU1200_GPIO207_INT,
+        AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
+        AU1200_USB_INT,
+        AU1200_LCD_INT,
+        AU1200_MAE_BOTH_INT,
+        AU1200_GPIO0_INT,
+        AU1200_GPIO1_INT,
+        AU1200_GPIO2_INT,
+        AU1200_GPIO3_INT,
+        AU1200_GPIO4_INT,
+        AU1200_GPIO5_INT,
+        AU1200_GPIO6_INT,
+        AU1200_GPIO7_INT,
+        AU1200_GPIO8_INT,
+        AU1200_GPIO9_INT,
+        AU1200_GPIO10_INT,
+        AU1200_GPIO11_INT,
+        AU1200_GPIO12_INT,
+        AU1200_GPIO13_INT,
+        AU1200_GPIO14_INT,
+        AU1200_GPIO15_INT,
+        AU1200_GPIO16_INT,
+        AU1200_GPIO17_INT,
+        AU1200_GPIO18_INT,
+        AU1200_GPIO19_INT,
+        AU1200_GPIO20_INT,
+        AU1200_GPIO21_INT,
+        AU1200_GPIO22_INT,
+        AU1200_GPIO23_INT,
+        AU1200_GPIO24_INT,
+        AU1200_GPIO25_INT,
+        AU1200_GPIO26_INT,
+        AU1200_GPIO27_INT,
+        AU1200_GPIO28_INT,
+        AU1200_GPIO29_INT,
+        AU1200_GPIO30_INT,
+        AU1200_GPIO31_INT,
+};
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
@@ -549,78 +911,16 @@ void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
 
 #define IC1_TESTBIT             0xB1800080
 
-/* Interrupt Numbers */
+
 /* Au1000 */
 #ifdef CONFIG_SOC_AU1000
-enum soc_au1000_ints {
-        AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1000_UART0_INT        = AU1000_FIRST_INT,
-        AU1000_UART1_INT,                               /* au1000 */
-        AU1000_UART2_INT,                               /* au1000 */
-        AU1000_UART3_INT,
-        AU1000_SSI0_INT,                                /* au1000 */
-        AU1000_SSI1_INT,                                /* au1000 */
-        AU1000_DMA_INT_BASE,
-
-        AU1000_TOY_INT          = AU1000_FIRST_INT + 14,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1000_IRDA_TX_INT,                             /* au1000 */
-        AU1000_IRDA_RX_INT,                             /* au1000 */
-        AU1000_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_SUS_INT,
-        AU1000_USB_HOST_INT,
-        AU1000_ACSYNC_INT,
-        AU1000_MAC0_DMA_INT,
-        AU1000_MAC1_DMA_INT,
-        AU1000_I2S_UO_INT,                              /* au1000 */
-        AU1000_AC97C_INT,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1000_GPIO_16,
-        AU1000_GPIO_17,
-        AU1000_GPIO_18,
-        AU1000_GPIO_19,
-        AU1000_GPIO_20,
-        AU1000_GPIO_21,
-        AU1000_GPIO_22,
-        AU1000_GPIO_23,
-        AU1000_GPIO_24,
-        AU1000_GPIO_25,
-        AU1000_GPIO_26,
-        AU1000_GPIO_27,
-        AU1000_GPIO_28,
-        AU1000_GPIO_29,
-        AU1000_GPIO_30,
-        AU1000_GPIO_31,
-};
 
 #define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
-#define UART2_ADDR              0xB1300000
 #define UART3_ADDR              0xB1400000
 
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017FFFC
+#define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
 
 #define AU1000_ETH0_BASE        0xB0500000
 #define AU1000_ETH1_BASE        0xB0510000
@@ -631,78 +931,13 @@ enum soc_au1000_ints {
 
 /* Au1500 */
 #ifdef CONFIG_SOC_AU1500
-enum soc_au1500_ints {
-        AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1500_UART0_INT        = AU1500_FIRST_INT,
-        AU1000_PCI_INTA,                                /* au1500 */
-        AU1000_PCI_INTB,                                /* au1500 */
-        AU1500_UART3_INT,
-        AU1000_PCI_INTC,                                /* au1500 */
-        AU1000_PCI_INTD,                                /* au1500 */
-        AU1000_DMA_INT_BASE,
-
-        AU1000_TOY_INT          = AU1500_FIRST_INT + 14,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1500_PCI_ERR_INT,
-        AU1500_RESERVED_INT,
-        AU1000_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_SUS_INT,
-        AU1000_USB_HOST_INT,
-        AU1000_ACSYNC_INT,
-        AU1500_MAC0_DMA_INT,
-        AU1500_MAC1_DMA_INT,
-        AU1000_AC97C_INT        = AU1500_FIRST_INT + 31,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1500_GPIO_200,
-        AU1500_GPIO_201,
-        AU1500_GPIO_202,
-        AU1500_GPIO_203,
-        AU1500_GPIO_20,
-        AU1500_GPIO_204,
-        AU1500_GPIO_205,
-        AU1500_GPIO_23,
-        AU1500_GPIO_24,
-        AU1500_GPIO_25,
-        AU1500_GPIO_26,
-        AU1500_GPIO_27,
-        AU1500_GPIO_28,
-        AU1500_GPIO_206,
-        AU1500_GPIO_207,
-        AU1500_GPIO_208_215,
-};
-
-/* shortcuts */
-#define INTA AU1000_PCI_INTA
-#define INTB AU1000_PCI_INTB
-#define INTC AU1000_PCI_INTC
-#define INTD AU1000_PCI_INTD
 
 #define UART0_ADDR              0xB1100000
 #define UART3_ADDR              0xB1400000
 
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017fffc
+#define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
 
 #define AU1500_ETH0_BASE        0xB1500000
 #define AU1500_ETH1_BASE        0xB1510000
@@ -713,74 +948,13 @@ enum soc_au1500_ints {
 
 /* Au1100 */
 #ifdef CONFIG_SOC_AU1100
-enum soc_au1100_ints {
-        AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1100_UART0_INT        = AU1100_FIRST_INT,
-        AU1100_UART1_INT,
-        AU1100_SD_INT,
-        AU1100_UART3_INT,
-        AU1000_SSI0_INT,
-        AU1000_SSI1_INT,
-        AU1000_DMA_INT_BASE,
-
-        AU1000_TOY_INT          = AU1100_FIRST_INT + 14,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1000_IRDA_TX_INT,
-        AU1000_IRDA_RX_INT,
-        AU1000_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_SUS_INT,
-        AU1000_USB_HOST_INT,
-        AU1000_ACSYNC_INT,
-        AU1100_MAC0_DMA_INT,
-        AU1100_GPIO_208_215,
-        AU1100_LCD_INT,
-        AU1000_AC97C_INT,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1000_GPIO_16,
-        AU1000_GPIO_17,
-        AU1000_GPIO_18,
-        AU1000_GPIO_19,
-        AU1000_GPIO_20,
-        AU1000_GPIO_21,
-        AU1000_GPIO_22,
-        AU1000_GPIO_23,
-        AU1000_GPIO_24,
-        AU1000_GPIO_25,
-        AU1000_GPIO_26,
-        AU1000_GPIO_27,
-        AU1000_GPIO_28,
-        AU1000_GPIO_29,
-        AU1000_GPIO_30,
-        AU1000_GPIO_31,
-};
 
 #define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
 #define UART3_ADDR              0xB1400000
 
 #define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
 #define USB_HOST_CONFIG         0xB017FFFC
+#define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
 
 #define AU1100_ETH0_BASE        0xB0500000
 #define AU1100_MAC0_ENABLE      0xB0520000
@@ -788,87 +962,12 @@ enum soc_au1100_ints {
 #endif /* CONFIG_SOC_AU1100 */
 
 #ifdef CONFIG_SOC_AU1550
-enum soc_au1550_ints {
-        AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1550_UART0_INT        = AU1550_FIRST_INT,
-        AU1550_PCI_INTA,
-        AU1550_PCI_INTB,
-        AU1550_DDMA_INT,
-        AU1550_CRYPTO_INT,
-        AU1550_PCI_INTC,
-        AU1550_PCI_INTD,
-        AU1550_PCI_RST_INT,
-        AU1550_UART1_INT,
-        AU1550_UART3_INT,
-        AU1550_PSC0_INT,
-        AU1550_PSC1_INT,
-        AU1550_PSC2_INT,
-        AU1550_PSC3_INT,
-        AU1000_TOY_INT,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-
-        AU1550_NAND_INT                 = AU1550_FIRST_INT + 23,
-        AU1550_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_REQ_INT          = AU1550_USB_DEV_REQ_INT,
-        AU1550_USB_DEV_SUS_INT,
-        AU1000_USB_DEV_SUS_INT          = AU1550_USB_DEV_SUS_INT,
-        AU1550_USB_HOST_INT,
-        AU1000_USB_HOST_INT             = AU1550_USB_HOST_INT,
-        AU1550_MAC0_DMA_INT,
-        AU1550_MAC1_DMA_INT,
-        AU1000_GPIO_0                   = AU1550_FIRST_INT + 32,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1550_GPIO_200,
-        AU1500_GPIO_201_205,                    /* Logical or of GPIO201:205 */
-        AU1500_GPIO_16,
-        AU1500_GPIO_17,
-        AU1500_GPIO_20,
-        AU1500_GPIO_21,
-        AU1500_GPIO_22,
-        AU1500_GPIO_23,
-        AU1500_GPIO_24,
-        AU1500_GPIO_25,
-        AU1500_GPIO_26,
-        AU1500_GPIO_27,
-        AU1500_GPIO_28,
-        AU1500_GPIO_206,
-        AU1500_GPIO_207,
-        AU1500_GPIO_208_218,                    /* Logical or of GPIO208:218 */
-};
-
-/* shortcuts */
-#define INTA AU1550_PCI_INTA
-#define INTB AU1550_PCI_INTB
-#define INTC AU1550_PCI_INTC
-#define INTD AU1550_PCI_INTD
-
 #define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
-#define UART3_ADDR              0xB1400000
 
 #define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
 #define USB_OHCI_LEN            0x00060000
 #define USB_HOST_CONFIG         0xB4027ffc
+#define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
 
 #define AU1550_ETH0_BASE        0xB0500000
 #define AU1550_ETH1_BASE        0xB0510000
@@ -877,78 +976,10 @@ enum soc_au1550_ints {
 #define NUM_ETH_INTERFACES 2
 #endif /* CONFIG_SOC_AU1550 */
 
+
 #ifdef CONFIG_SOC_AU1200
-enum soc_au1200_ints {
-        AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1200_UART0_INT        = AU1200_FIRST_INT,
-        AU1200_SWT_INT,
-        AU1200_SD_INT,
-        AU1200_DDMA_INT,
-        AU1200_MAE_BE_INT,
-        AU1200_GPIO_200,
-        AU1200_GPIO_201,
-        AU1200_GPIO_202,
-        AU1200_UART1_INT,
-        AU1200_MAE_FE_INT,
-        AU1200_PSC0_INT,
-        AU1200_PSC1_INT,
-        AU1200_AES_INT,
-        AU1200_CAMERA_INT,
-        AU1000_TOY_INT,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1200_GPIO_203,
-        AU1200_NAND_INT,
-        AU1200_GPIO_204,
-        AU1200_GPIO_205,
-        AU1200_GPIO_206,
-        AU1200_GPIO_207,
-        AU1200_GPIO_208_215,                    /* Logical OR of 208:215 */
-        AU1200_USB_INT,
-        AU1000_USB_HOST_INT     = AU1200_USB_INT,
-        AU1200_LCD_INT,
-        AU1200_MAE_BOTH_INT,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1000_GPIO_16,
-        AU1000_GPIO_17,
-        AU1000_GPIO_18,
-        AU1000_GPIO_19,
-        AU1000_GPIO_20,
-        AU1000_GPIO_21,
-        AU1000_GPIO_22,
-        AU1000_GPIO_23,
-        AU1000_GPIO_24,
-        AU1000_GPIO_25,
-        AU1000_GPIO_26,
-        AU1000_GPIO_27,
-        AU1000_GPIO_28,
-        AU1000_GPIO_29,
-        AU1000_GPIO_30,
-        AU1000_GPIO_31,
-};
 
 #define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
 
 #define USB_UOC_BASE            0x14020020
 #define USB_UOC_LEN             0x20
@@ -974,15 +1005,9 @@ enum soc_au1200_ints {
 #define USBMSRMCFG_RDCOMB       30
 #define USBMSRMCFG_PFEN         31
 
-#endif /* CONFIG_SOC_AU1200 */
-
-#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
-#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
-#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_BASE + 32)
-#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
+#define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
 
-#define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
-#define INTX                    0xFF                    /* not valid */
+#endif /* CONFIG_SOC_AU1200 */
 
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE                0xB1900000
@@ -1231,14 +1256,6 @@ enum soc_au1200_ints {
 #define MAC_RX_BUFF3_STATUS     0x30
 #define MAC_RX_BUFF3_ADDR       0x34
 
-/* UARTS 0-3 */
-#define UART_BASE               UART0_ADDR
-#ifdef  CONFIG_SOC_AU1200
-#define UART_DEBUG_BASE         UART1_ADDR
-#else
-#define UART_DEBUG_BASE         UART3_ADDR
-#endif
-
 #define UART_RX         0       /* Receive buffer */
 #define UART_TX         4       /* Transmit buffer */
 #define UART_IER        8       /* Interrupt Enable Register */
@@ -1251,84 +1268,6 @@ enum soc_au1200_ints {
 #define UART_CLK        0x28    /* Baud Rate Clock Divider */
 #define UART_MOD_CNTRL  0x100   /* Module Control */
 
-#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK   0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1    0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4    0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8    0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0    0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4    0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12   0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC    0x40    /* Set break control */
-#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
-#define UART_LCR_EPAR   0x10    /* Even parity select */
-#define UART_LCR_PARITY 0x08    /* Parity Enable */
-#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT   0x40    /* Transmitter empty */
-#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
-#define UART_LSR_BI     0x10    /* Break interrupt indicator */
-#define UART_LSR_FE     0x08    /* Frame error indicator */
-#define UART_LSR_PE     0x04    /* Parity error indicator */
-#define UART_LSR_OE     0x02    /* Overrun error indicator */
-#define UART_LSR_DR     0x01    /* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
-#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
-#define UART_IIR_MSI    0x00    /* Modem status interrupt */
-#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
-#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
-#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
-#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
-#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
-#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
-#define UART_MCR_OUT2   0x08    /* Out2 complement */
-#define UART_MCR_OUT1   0x04    /* Out1 complement */
-#define UART_MCR_RTS    0x02    /* RTS complement */
-#define UART_MCR_DTR    0x01    /* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
-#define UART_MSR_RI     0x40    /* Ring Indicator */
-#define UART_MSR_DSR    0x20    /* Data Set Ready */
-#define UART_MSR_CTS    0x10    /* Clear to Send */
-#define UART_MSR_DDCD   0x08    /* Delta DCD */
-#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
-#define UART_MSR_DDSR   0x02    /* Delta DSR */
-#define UART_MSR_DCTS   0x01    /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
 /* SSIO */
 #define SSI0_STATUS             0xB1600000
 #  define SSI_STATUS_BF         (1 << 4)
@@ -1720,7 +1659,7 @@ enum soc_au1200_ints {
 #define IOPORT_RESOURCE_START   0x00001000      /* skip legacy probing */
 #define IOPORT_RESOURCE_END     0xffffffff
 #define IOMEM_RESOURCE_START    0x10000000
-#define IOMEM_RESOURCE_END      0xffffffff
+#define IOMEM_RESOURCE_END      0xfffffffffULL
 
 #else /* Au1000 and Au1100 and Au1200 */
 
@@ -1728,7 +1667,7 @@ enum soc_au1200_ints {
 #define IOPORT_RESOURCE_START   0x10000000
 #define IOPORT_RESOURCE_END     0xffffffff
 #define IOMEM_RESOURCE_START    0x10000000
-#define IOMEM_RESOURCE_END      0xffffffff
+#define IOMEM_RESOURCE_END      0xfffffffffULL
 
 #define PCI_IO_START    0
 #define PCI_IO_END      0
@@ -1739,53 +1678,4 @@ enum soc_au1200_ints {
 
 #endif
 
-#ifndef _LANGUAGE_ASSEMBLY
-typedef volatile struct {
-        /* 0x0000 */ u32 toytrim;
-        /* 0x0004 */ u32 toywrite;
-        /* 0x0008 */ u32 toymatch0;
-        /* 0x000C */ u32 toymatch1;
-        /* 0x0010 */ u32 toymatch2;
-        /* 0x0014 */ u32 cntrctrl;
-        /* 0x0018 */ u32 scratch0;
-        /* 0x001C */ u32 scratch1;
-        /* 0x0020 */ u32 freqctrl0;
-        /* 0x0024 */ u32 freqctrl1;
-        /* 0x0028 */ u32 clksrc;
-        /* 0x002C */ u32 pinfunc;
-        /* 0x0030 */ u32 reserved0;
-        /* 0x0034 */ u32 wakemsk;
-        /* 0x0038 */ u32 endian;
-        /* 0x003C */ u32 powerctrl;
-        /* 0x0040 */ u32 toyread;
-        /* 0x0044 */ u32 rtctrim;
-        /* 0x0048 */ u32 rtcwrite;
-        /* 0x004C */ u32 rtcmatch0;
-        /* 0x0050 */ u32 rtcmatch1;
-        /* 0x0054 */ u32 rtcmatch2;
-        /* 0x0058 */ u32 rtcread;
-        /* 0x005C */ u32 wakesrc;
-        /* 0x0060 */ u32 cpupll;
-        /* 0x0064 */ u32 auxpll;
-        /* 0x0068 */ u32 reserved1;
-        /* 0x006C */ u32 reserved2;
-        /* 0x0070 */ u32 reserved3;
-        /* 0x0074 */ u32 reserved4;
-        /* 0x0078 */ u32 slppwr;
-        /* 0x007C */ u32 sleep;
-        /* 0x0080 */ u32 reserved5[32];
-        /* 0x0100 */ u32 trioutrd;
-#define trioutclr trioutrd
-        /* 0x0104 */ u32 reserved6;
-        /* 0x0108 */ u32 outputrd;
-#define outputset outputrd
-        /* 0x010C */ u32 outputclr;
-        /* 0x0110 */ u32 pinstaterd;
-#define pininputen pinstaterd
-} AU1X00_SYS;
-
-static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
-
-#endif
-
 #endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index c35e20918490..94000a3b6f0b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -46,6 +46,7 @@ struct au1xmmc_platform_data {
         int(*card_readonly)(void *mmc_host);
         void(*set_power)(void *mmc_host, int state);
         struct led_classdev *led;
+        unsigned long mask_host_caps;
 };
 
 #define SD0_BASE        0xB0600000
@@ -205,4 +206,3 @@ struct au1xmmc_platform_data {
 
 
 #endif /* __ASM_AU1100_MMC_H */
-
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index d206000fbfe2..8c6b1105ce0b 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -339,8 +339,8 @@ u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
 
 /* Put buffers on source/destination descriptors. */
-u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
-u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
+u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
+u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags);
 
 /* Get a buffer from the destination descriptor. */
 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
@@ -363,25 +363,6 @@ void au1xxx_dbdma_suspend(void);
 void au1xxx_dbdma_resume(void);
 #endif
 
-
-/*
- * Some compatibilty macros -- needed to make changes to API
- * without breaking existing drivers.
- */
-#define au1xxx_dbdma_put_source(chanid, buf, nbytes)                    \
-        _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)       \
-        _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
-#define put_source_flags(chanid, buf, nbytes, flags)                    \
-        au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
-
-#define au1xxx_dbdma_put_dest(chanid, buf, nbytes)                      \
-        _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)         \
-        _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
-#define put_dest_flags(chanid, buf, nbytes, flags)                      \
-        au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
-
 /*
  *      Flags for the put_source/put_dest functions.
  */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
new file mode 100644
index 000000000000..bae9b758fcde
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h
@@ -0,0 +1,17 @@
+#ifndef __AU1X00_ETH_DATA_H
+#define __AU1X00_ETH_DATA_H
+
+/* Platform specific PHY configuration passed to the MAC driver */
+struct au1000_eth_platform_data {
+        int phy_static_config;
+        int phy_search_highest_addr;
+        int phy1_search_mac0;
+        int phy_addr;
+        int phy_busid;
+        int phy_irq;
+};
+
+void __init au1xxx_override_eth_cfg(unsigned port,
+                        struct au1000_eth_platform_data *eth_data);
+
+#endif /* __AU1X00_ETH_DATA_H */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 91595fa89034..62d2f136d941 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -35,15 +35,13 @@ static inline int au1000_gpio2_to_irq(int gpio)
         return -ENXIO;
 }
 
-#ifdef CONFIG_SOC_AU1000
 static inline int au1000_irq_to_gpio(int irq)
 {
-        if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
-                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
+        if ((irq >= AU1000_GPIO0_INT) && (irq <= AU1000_GPIO31_INT))
+                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO0_INT) + 0;
 
         return -ENXIO;
 }
-#endif
 
 static inline int au1500_gpio1_to_irq(int gpio)
 {
@@ -71,27 +69,25 @@ static inline int au1500_gpio2_to_irq(int gpio)
         return -ENXIO;
 }
 
-#ifdef CONFIG_SOC_AU1500
 static inline int au1500_irq_to_gpio(int irq)
 {
         switch (irq) {
-        case AU1000_GPIO_0 ... AU1000_GPIO_15:
-        case AU1500_GPIO_20:
-        case AU1500_GPIO_23 ... AU1500_GPIO_28:
-                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
-        case AU1500_GPIO_200 ... AU1500_GPIO_203:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
-        case AU1500_GPIO_204 ... AU1500_GPIO_205:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
-        case AU1500_GPIO_206 ... AU1500_GPIO_207:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
-        case AU1500_GPIO_208_215:
+        case AU1500_GPIO0_INT ... AU1500_GPIO15_INT:
+        case AU1500_GPIO20_INT:
+        case AU1500_GPIO23_INT ... AU1500_GPIO28_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO0_INT) + 0;
+        case AU1500_GPIO200_INT ... AU1500_GPIO203_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO200_INT) + 0;
+        case AU1500_GPIO204_INT ... AU1500_GPIO205_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO204_INT) + 4;
+        case AU1500_GPIO206_INT ... AU1500_GPIO207_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO206_INT) + 6;
+        case AU1500_GPIO208_215_INT:
                 return ALCHEMY_GPIO2_BASE + 8;
         }
 
         return -ENXIO;
 }
-#endif
 
 static inline int au1100_gpio1_to_irq(int gpio)
 {
@@ -108,19 +104,17 @@ static inline int au1100_gpio2_to_irq(int gpio)
         return -ENXIO;
 }
 
-#ifdef CONFIG_SOC_AU1100
 static inline int au1100_irq_to_gpio(int irq)
 {
         switch (irq) {
-        case AU1000_GPIO_0 ... AU1000_GPIO_31:
-                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
-        case AU1100_GPIO_208_215:
+        case AU1100_GPIO0_INT ... AU1100_GPIO31_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1100_GPIO0_INT) + 0;
+        case AU1100_GPIO208_215_INT:
                 return ALCHEMY_GPIO2_BASE + 8;
         }
 
         return -ENXIO;
 }
-#endif
 
 static inline int au1550_gpio1_to_irq(int gpio)
 {
@@ -149,24 +143,22 @@ static inline int au1550_gpio2_to_irq(int gpio)
         return -ENXIO;
 }
 
-#ifdef CONFIG_SOC_AU1550
 static inline int au1550_irq_to_gpio(int irq)
 {
         switch (irq) {
-        case AU1000_GPIO_0 ... AU1000_GPIO_15:
-                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
-        case AU1550_GPIO_200:
-        case AU1500_GPIO_201_205:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
-        case AU1500_GPIO_16 ... AU1500_GPIO_28:
-                return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
-        case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
+        case AU1550_GPIO0_INT ... AU1550_GPIO15_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO0_INT) + 0;
+        case AU1550_GPIO200_INT:
+        case AU1550_GPIO201_205_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO200_INT) + 0;
+        case AU1550_GPIO16_INT ... AU1550_GPIO28_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1550_GPIO16_INT) + 16;
+        case AU1550_GPIO206_INT ... AU1550_GPIO208_215_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO206_INT) + 6;
         }
 
         return -ENXIO;
 }
-#endif
 
 static inline int au1200_gpio1_to_irq(int gpio)
 {
@@ -187,23 +179,21 @@ static inline int au1200_gpio2_to_irq(int gpio)
         return -ENXIO;
 }
 
-#ifdef CONFIG_SOC_AU1200
 static inline int au1200_irq_to_gpio(int irq)
 {
         switch (irq) {
-        case AU1000_GPIO_0 ... AU1000_GPIO_31:
-                return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
-        case AU1200_GPIO_200 ... AU1200_GPIO_202:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
-        case AU1200_GPIO_203:
+        case AU1200_GPIO0_INT ... AU1200_GPIO31_INT:
+                return ALCHEMY_GPIO1_BASE + (irq - AU1200_GPIO0_INT) + 0;
+        case AU1200_GPIO200_INT ... AU1200_GPIO202_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO200_INT) + 0;
+        case AU1200_GPIO203_INT:
                 return ALCHEMY_GPIO2_BASE + 3;
-        case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
-                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
+        case AU1200_GPIO204_INT ... AU1200_GPIO208_215_INT:
+                return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO204_INT) + 4;
         }
 
         return -ENXIO;
 }
-#endif
 
 /*
  * GPIO1 block macros for common linux gpio functions.
@@ -246,19 +236,19 @@ static inline int alchemy_gpio1_is_valid(int gpio)
 
 static inline int alchemy_gpio1_to_irq(int gpio)
 {
-#if defined(CONFIG_SOC_AU1000)
-        return au1000_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1100)
-        return au1100_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1500)
-        return au1500_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1550)
-        return au1550_gpio1_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1200)
-        return au1200_gpio1_to_irq(gpio);
-#else
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                return au1000_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1100:
+                return au1100_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1500:
+                return au1500_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1550:
+                return au1550_gpio1_to_irq(gpio);
+        case ALCHEMY_CPU_AU1200:
+                return au1200_gpio1_to_irq(gpio);
+        }
         return -ENXIO;
-#endif
 }
 
 /*
@@ -316,19 +306,19 @@ static inline int alchemy_gpio2_is_valid(int gpio)
 
 static inline int alchemy_gpio2_to_irq(int gpio)
 {
-#if defined(CONFIG_SOC_AU1000)
-        return au1000_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1100)
-        return au1100_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1500)
-        return au1500_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1550)
-        return au1550_gpio2_to_irq(gpio);
-#elif defined(CONFIG_SOC_AU1200)
-        return au1200_gpio2_to_irq(gpio);
-#else
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                return au1000_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1100:
+                return au1100_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1500:
+                return au1500_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1550:
+                return au1550_gpio2_to_irq(gpio);
+        case ALCHEMY_CPU_AU1200:
+                return au1200_gpio2_to_irq(gpio);
+        }
         return -ENXIO;
-#endif
 }
 
 /**********************************************************************/
@@ -384,10 +374,13 @@ static inline void alchemy_gpio2_enable_int(int gpio2)
 
         gpio2 -= ALCHEMY_GPIO2_BASE;
 
-#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
         /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
-        gpio2 -= 8;
-#endif
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1500:
+                gpio2 -= 8;
+        }
+
         local_irq_save(flags);
         __alchemy_gpio2_mod_int(gpio2, 1);
         local_irq_restore(flags);
@@ -405,10 +398,13 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
 
         gpio2 -= ALCHEMY_GPIO2_BASE;
 
-#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
         /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
-        gpio2 -= 8;
-#endif
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1100:
+        case ALCHEMY_CPU_AU1500:
+                gpio2 -= 8;
+        }
+
         local_irq_save(flags);
         __alchemy_gpio2_mod_int(gpio2, 0);
         local_irq_restore(flags);
@@ -494,19 +490,19 @@ static inline int alchemy_gpio_to_irq(int gpio)
 
 static inline int alchemy_irq_to_gpio(int irq)
 {
-#if defined(CONFIG_SOC_AU1000)
-        return au1000_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1100)
-        return au1100_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1500)
-        return au1500_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1550)
-        return au1550_irq_to_gpio(irq);
-#elif defined(CONFIG_SOC_AU1200)
-        return au1200_irq_to_gpio(irq);
-#else
+        switch (alchemy_get_cputype()) {
+        case ALCHEMY_CPU_AU1000:
+                return au1000_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1100:
+                return au1100_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1500:
+                return au1500_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1550:
+                return au1550_irq_to_gpio(irq);
+        case ALCHEMY_CPU_AU1200:
+                return au1200_irq_to_gpio(irq);
+        }
         return -ENXIO;
-#endif
 }
 
 /**********************************************************************/
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index f9b7d41c659a..c3f60cdc3203 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,7 +1,7 @@
 #ifndef _ALCHEMY_GPIO_H_
 #define _ALCHEMY_GPIO_H_
 
-#if defined(CONFIG_ALCHEMY_GPIO_AU1000)
+#if defined(CONFIG_ALCHEMY_GPIOINT_AU1000)
 
 #include <asm/mach-au1x00/gpio-au1000.h>
 
diff --git a/arch/mips/include/asm/mach-au1x00/ioremap.h b/arch/mips/include/asm/mach-au1x00/ioremap.h
index 364cea2dc71f..75a94ad3ac91 100644
--- a/arch/mips/include/asm/mach-au1x00/ioremap.h
+++ b/arch/mips/include/asm/mach-au1x00/ioremap.h
@@ -11,7 +11,7 @@
 
 #include <linux/types.h>
 
-#ifdef CONFIG_64BIT_PHYS_ADDR
+#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_PCI)
 extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
 #else
 static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h
index e38715577c51..4c0e09cf1735 100644
--- a/arch/mips/include/asm/mach-au1x00/prom.h
+++ b/arch/mips/include/asm/mach-au1x00/prom.h
@@ -6,7 +6,6 @@ extern char **prom_argv;
 extern char **prom_envp;
 
 extern void prom_init_cmdline(void);
-extern char *prom_getcmdline(void);
 extern char *prom_getenv(char *envname);
 extern int prom_get_ethernet_addr(char *ethernet_addr);
 
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index ed4ccec87dd4..85fd27509aac 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -770,4 +770,3 @@
 #define DMIPSPLLCFG_N2_MASK             (0x7 << DMIPSPLLCFG_N2_SHIFT)
 
 #endif /* BCM63XX_REGS_H_ */
-
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 425e708d4fb9..bbf054042395 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -58,6 +58,9 @@
 #define cpu_has_vint            0
 #define cpu_has_veic            0
 #define cpu_hwrena_impl_bits    0xc0000000
+
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
+
 #define ARCH_HAS_READ_CURRENT_TIMER 1
 #define ARCH_HAS_IRQ_PER_CPU    1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
new file mode 100644
index 000000000000..618d2de02ed3
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -0,0 +1,238 @@
+/*
+ * bcsr.h -- Db1xxx/Pb1xxx Devboard CPLD registers ("BCSR") abstraction.
+ *
+ * All Alchemy development boards (except, of course, the weird PB1000)
+ * have a few registers in a CPLD with standardised layout; they mostly
+ * only differ in base address and bit meanings in the RESETS and BOARD
+ * registers.
+ *
+ * All data taken from the official AMD board documentation sheets.
+ */
+
+#ifndef _DB1XXX_BCSR_H_
+#define _DB1XXX_BCSR_H_
+
+
+/* BCSR base addresses on various boards. BCSR base 2 refers to the
+ * physical address of the first HEXLEDS register, which is usually
+ * a variable offset from the WHOAMI register.
+ */
+
+/* DB1000, DB1100, DB1500, PB1100, PB1500 */
+#define DB1000_BCSR_PHYS_ADDR   0x0E000000
+#define DB1000_BCSR_HEXLED_OFS  0x01000000
+
+#define DB1550_BCSR_PHYS_ADDR   0x0F000000
+#define DB1550_BCSR_HEXLED_OFS  0x00400000
+
+#define PB1550_BCSR_PHYS_ADDR   0x0F000000
+#define PB1550_BCSR_HEXLED_OFS  0x00800000
+
+#define DB1200_BCSR_PHYS_ADDR   0x19800000
+#define DB1200_BCSR_HEXLED_OFS  0x00400000
+
+#define PB1200_BCSR_PHYS_ADDR   0x0D800000
+#define PB1200_BCSR_HEXLED_OFS  0x00400000
+
+
+enum bcsr_id {
+        /* BCSR base 1 */
+        BCSR_WHOAMI     = 0,
+        BCSR_STATUS,
+        BCSR_SWITCHES,
+        BCSR_RESETS,
+        BCSR_PCMCIA,
+        BCSR_BOARD,
+        BCSR_LEDS,
+        BCSR_SYSTEM,
+        /* Au1200/1300 based boards */
+        BCSR_INTCLR,
+        BCSR_INTSET,
+        BCSR_MASKCLR,
+        BCSR_MASKSET,
+        BCSR_SIGSTAT,
+        BCSR_INTSTAT,
+
+        /* BCSR base 2 */
+        BCSR_HEXLEDS,
+        BCSR_RSVD1,
+        BCSR_HEXCLEAR,
+
+        BCSR_CNT,
+};
+
+/* register offsets, valid for all Db1xxx/Pb1xxx boards */
+#define BCSR_REG_WHOAMI         0x00
+#define BCSR_REG_STATUS         0x04
+#define BCSR_REG_SWITCHES       0x08
+#define BCSR_REG_RESETS         0x0c
+#define BCSR_REG_PCMCIA         0x10
+#define BCSR_REG_BOARD          0x14
+#define BCSR_REG_LEDS           0x18
+#define BCSR_REG_SYSTEM         0x1c
+/* Au1200/Au1300 based boards: CPLD IRQ muxer */
+#define BCSR_REG_INTCLR         0x20
+#define BCSR_REG_INTSET         0x24
+#define BCSR_REG_MASKCLR        0x28
+#define BCSR_REG_MASKSET        0x2c
+#define BCSR_REG_SIGSTAT        0x30
+#define BCSR_REG_INTSTAT        0x34
+
+/* hexled control, offset from BCSR base 2 */
+#define BCSR_REG_HEXLEDS        0x00
+#define BCSR_REG_HEXCLEAR       0x08
+
+/*
+ * Register Bits and Pieces.
+ */
+#define BCSR_WHOAMI_DCID(x)             ((x) & 0xf)
+#define BCSR_WHOAMI_CPLD(x)             (((x) >> 4) & 0xf)
+#define BCSR_WHOAMI_BOARD(x)            (((x) >> 8) & 0xf)
+
+/* register "WHOAMI" bits 11:8 identify the board */
+enum bcsr_whoami_boards {
+        BCSR_WHOAMI_PB1500 = 1,
+        BCSR_WHOAMI_PB1500R2,
+        BCSR_WHOAMI_PB1100,
+        BCSR_WHOAMI_DB1000,
+        BCSR_WHOAMI_DB1100,
+        BCSR_WHOAMI_DB1500,
+        BCSR_WHOAMI_DB1550,
+        BCSR_WHOAMI_PB1550_DDR,
+        BCSR_WHOAMI_PB1550 = BCSR_WHOAMI_PB1550_DDR,
+        BCSR_WHOAMI_PB1550_SDR,
+        BCSR_WHOAMI_PB1200_DDR1,
+        BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1,
+        BCSR_WHOAMI_PB1200_DDR2,
+        BCSR_WHOAMI_DB1200,
+};
+
+/* STATUS reg.  Unless otherwise noted, they're valid on all boards.
+ * PB1200 = DB1200.
+ */
+#define BCSR_STATUS_PC0VS               0x0003
+#define BCSR_STATUS_PC1VS               0x000C
+#define BCSR_STATUS_PC0FI               0x0010
+#define BCSR_STATUS_PC1FI               0x0020
+#define BCSR_STATUS_PB1550_SWAPBOOT     0x0040
+#define BCSR_STATUS_SRAMWIDTH           0x0080
+#define BCSR_STATUS_FLASHBUSY           0x0100
+#define BCSR_STATUS_ROMBUSY             0x0400
+#define BCSR_STATUS_SD0WP               0x0400  /* DB1200 */
+#define BCSR_STATUS_SD1WP               0x0800
+#define BCSR_STATUS_USBOTGID            0x0800  /* PB/DB1550 */
+#define BCSR_STATUS_DB1000_SWAPBOOT     0x2000
+#define BCSR_STATUS_DB1200_SWAPBOOT     0x0040  /* DB1200 */
+#define BCSR_STATUS_IDECBLID            0x0200  /* DB1200 */
+#define BCSR_STATUS_DB1200_U0RXD        0x1000  /* DB1200 */
+#define BCSR_STATUS_DB1200_U1RXD        0x2000  /* DB1200 */
+#define BCSR_STATUS_FLASHDEN            0xC000
+#define BCSR_STATUS_DB1550_U0RXD        0x1000  /* DB1550 */
+#define BCSR_STATUS_DB1550_U3RXD        0x2000  /* DB1550 */
+#define BCSR_STATUS_PB1550_U0RXD        0x1000  /* PB1550 */
+#define BCSR_STATUS_PB1550_U1RXD        0x2000  /* PB1550 */
+#define BCSR_STATUS_PB1550_U3RXD        0x8000  /* PB1550 */
+
+
+/* DB/PB1000,1100,1500,1550 */
+#define BCSR_RESETS_PHY0                0x0001
+#define BCSR_RESETS_PHY1                0x0002
+#define BCSR_RESETS_DC                  0x0004
+#define BCSR_RESETS_FIR_SEL             0x2000
+#define BCSR_RESETS_IRDA_MODE_MASK      0xC000
+#define BCSR_RESETS_IRDA_MODE_FULL      0x0000
+#define BCSR_RESETS_PB1550_WSCFSM       0x2000
+#define BCSR_RESETS_IRDA_MODE_OFF       0x4000
+#define BCSR_RESETS_IRDA_MODE_2_3       0x8000
+#define BCSR_RESETS_IRDA_MODE_1_3       0xC000
+#define BCSR_RESETS_DMAREQ              0x8000  /* PB1550 */
+
+#define BCSR_BOARD_PCIM66EN             0x0001
+#define BCSR_BOARD_SD0PWR               0x0040
+#define BCSR_BOARD_SD1PWR               0x0080
+#define BCSR_BOARD_PCIM33               0x0100
+#define BCSR_BOARD_PCIEXTARB            0x0200
+#define BCSR_BOARD_GPIO200RST           0x0400
+#define BCSR_BOARD_PCICLKOUT            0x0800
+#define BCSR_BOARD_PCICFG               0x1000
+#define BCSR_BOARD_SPISEL               0x4000  /* PB/DB1550 */
+#define BCSR_BOARD_SD0WP                0x4000  /* DB1100 */
+#define BCSR_BOARD_SD1WP                0x8000  /* DB1100 */
+
+
+/* DB/PB1200 */
+#define BCSR_RESETS_ETH                 0x0001
+#define BCSR_RESETS_CAMERA              0x0002
+#define BCSR_RESETS_DC                  0x0004
+#define BCSR_RESETS_IDE                 0x0008
+#define BCSR_RESETS_TV                  0x0010  /* DB1200 */
+/* Not resets but in the same register */
+#define BCSR_RESETS_PWMR1MUX            0x0800  /* DB1200 */
+#define BCSR_RESETS_PB1200_WSCFSM       0x0800  /* PB1200 */
+#define BCSR_RESETS_PSC0MUX             0x1000
+#define BCSR_RESETS_PSC1MUX             0x2000
+#define BCSR_RESETS_SPISEL              0x4000
+#define BCSR_RESETS_SD1MUX              0x8000  /* PB1200 */
+
+#define BCSR_BOARD_LCDVEE               0x0001
+#define BCSR_BOARD_LCDVDD               0x0002
+#define BCSR_BOARD_LCDBL                0x0004
+#define BCSR_BOARD_CAMSNAP              0x0010
+#define BCSR_BOARD_CAMPWR               0x0020
+#define BCSR_BOARD_SD0PWR               0x0040
+
+
+#define BCSR_SWITCHES_DIP               0x00FF
+#define BCSR_SWITCHES_DIP_1             0x0080
+#define BCSR_SWITCHES_DIP_2             0x0040
+#define BCSR_SWITCHES_DIP_3             0x0020
+#define BCSR_SWITCHES_DIP_4             0x0010
+#define BCSR_SWITCHES_DIP_5             0x0008
+#define BCSR_SWITCHES_DIP_6             0x0004
+#define BCSR_SWITCHES_DIP_7             0x0002
+#define BCSR_SWITCHES_DIP_8             0x0001
+#define BCSR_SWITCHES_ROTARY            0x0F00
+
+
+#define BCSR_PCMCIA_PC0VPP              0x0003
+#define BCSR_PCMCIA_PC0VCC              0x000C
+#define BCSR_PCMCIA_PC0DRVEN            0x0010
+#define BCSR_PCMCIA_PC0RST              0x0080
+#define BCSR_PCMCIA_PC1VPP              0x0300
+#define BCSR_PCMCIA_PC1VCC              0x0C00
+#define BCSR_PCMCIA_PC1DRVEN            0x1000
+#define BCSR_PCMCIA_PC1RST              0x8000
+
+
+#define BCSR_LEDS_DECIMALS              0x0003
+#define BCSR_LEDS_LED0                  0x0100
+#define BCSR_LEDS_LED1                  0x0200
+#define BCSR_LEDS_LED2                  0x0400
+#define BCSR_LEDS_LED3                  0x0800
+
+
+#define BCSR_SYSTEM_RESET               0x8000  /* clear to reset */
+#define BCSR_SYSTEM_PWROFF              0x4000  /* set to power off */
+#define BCSR_SYSTEM_VDDI                0x001F  /* PB1xxx boards */
+
+
+
+
+/* initialize BCSR for a board. Provide the PHYSICAL addresses of both
+ * BCSR spaces.
+ */
+void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys);
+
+/* read a board register */
+unsigned short bcsr_read(enum bcsr_id reg);
+
+/* write to a board register */
+void bcsr_write(enum bcsr_id reg, unsigned short val);
+
+/* modify a register. clear bits set in 'clr', set bits set in 'set' */
+void bcsr_mod(enum bcsr_id reg, unsigned short clr, unsigned short set);
+
+/* install CPLD IRQ demuxer (DB1200/PB1200) */
+void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq);
+
+#endif
diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index 27f26102b1bb..3404248f5094 100644
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -25,133 +25,9 @@
 #define __ASM_DB1200_H
 
 #include <linux/types.h>
+#include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1xxx_psc.h>
 
-#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
-
-/*
- * SPI and SMB are muxed on the DBAu1200 board.
- * Refer to board documentation.
- */
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
-/*
- * AC'97 and I2S are muxed on the DBAu1200 board.
- * Refer to board documentation.
- */
-#define AC97_PSC_BASE           PSC1_BASE_ADDR
-#define I2S_PSC_BASE            PSC1_BASE_ADDR
-
-#define BCSR_KSEG1_ADDR         0xB9800000
-
-typedef volatile struct
-{
-        /*00*/  u16 whoami;
-                u16 reserved0;
-        /*04*/  u16 status;
-                u16 reserved1;
-        /*08*/  u16 switches;
-                u16 reserved2;
-        /*0C*/  u16 resets;
-                u16 reserved3;
-
-        /*10*/  u16 pcmcia;
-                u16 reserved4;
-        /*14*/  u16 board;
-                u16 reserved5;
-        /*18*/  u16 disk_leds;
-                u16 reserved6;
-        /*1C*/  u16 system;
-                u16 reserved7;
-
-        /*20*/  u16 intclr;
-                u16 reserved8;
-        /*24*/  u16 intset;
-                u16 reserved9;
-        /*28*/  u16 intclr_mask;
-                u16 reserved10;
-        /*2C*/  u16 intset_mask;
-                u16 reserved11;
-
-        /*30*/  u16 sig_status;
-                u16 reserved12;
-        /*34*/  u16 int_status;
-                u16 reserved13;
-        /*38*/  u16 reserved14;
-                u16 reserved15;
-        /*3C*/  u16 reserved16;
-                u16 reserved17;
-
-} BCSR;
-
-static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-
-/*
- * Register bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID        0x000F
-#define BCSR_WHOAMI_CPLD        0x00F0
-#define BCSR_WHOAMI_BOARD       0x0F00
-
-#define BCSR_STATUS_PCMCIA0VS   0x0003
-#define BCSR_STATUS_PCMCIA1VS   0x000C
-#define BCSR_STATUS_SWAPBOOT    0x0040
-#define BCSR_STATUS_FLASHBUSY   0x0100
-#define BCSR_STATUS_IDECBLID    0x0200
-#define BCSR_STATUS_SD0WP       0x0400
-#define BCSR_STATUS_U0RXD       0x1000
-#define BCSR_STATUS_U1RXD       0x2000
-
-#define BCSR_SWITCHES_OCTAL     0x00FF
-#define BCSR_SWITCHES_DIP_1     0x0080
-#define BCSR_SWITCHES_DIP_2     0x0040
-#define BCSR_SWITCHES_DIP_3     0x0020
-#define BCSR_SWITCHES_DIP_4     0x0010
-#define BCSR_SWITCHES_DIP_5     0x0008
-#define BCSR_SWITCHES_DIP_6     0x0004
-#define BCSR_SWITCHES_DIP_7     0x0002
-#define BCSR_SWITCHES_DIP_8     0x0001
-#define BCSR_SWITCHES_ROTARY    0x0F00
-
-#define BCSR_RESETS_ETH         0x0001
-#define BCSR_RESETS_CAMERA      0x0002
-#define BCSR_RESETS_DC          0x0004
-#define BCSR_RESETS_IDE         0x0008
-#define BCSR_RESETS_TV          0x0010
-/* Not resets but in the same register */
-#define BCSR_RESETS_PWMR1MUX    0x0800
-#define BCSR_RESETS_PCS0MUX     0x1000
-#define BCSR_RESETS_PCS1MUX     0x2000
-#define BCSR_RESETS_SPISEL      0x4000
-
-#define BCSR_PCMCIA_PC0VPP      0x0003
-#define BCSR_PCMCIA_PC0VCC      0x000C
-#define BCSR_PCMCIA_PC0DRVEN    0x0010
-#define BCSR_PCMCIA_PC0RST      0x0080
-#define BCSR_PCMCIA_PC1VPP      0x0300
-#define BCSR_PCMCIA_PC1VCC      0x0C00
-#define BCSR_PCMCIA_PC1DRVEN    0x1000
-#define BCSR_PCMCIA_PC1RST      0x8000
-
-#define BCSR_BOARD_LCDVEE       0x0001
-#define BCSR_BOARD_LCDVDD       0x0002
-#define BCSR_BOARD_LCDBL        0x0004
-#define BCSR_BOARD_CAMSNAP      0x0010
-#define BCSR_BOARD_CAMPWR       0x0020
-#define BCSR_BOARD_SD0PWR       0x0040
-
-#define BCSR_LEDS_DECIMALS      0x0003
-#define BCSR_LEDS_LED0          0x0100
-#define BCSR_LEDS_LED1          0x0200
-#define BCSR_LEDS_LED2          0x0400
-#define BCSR_LEDS_LED3          0x0800
-
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
 /* Bit positions for the different interrupt sources */
 #define BCSR_INT_IDE            0x0001
 #define BCSR_INT_ETH            0x0002
@@ -168,17 +44,15 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
 #define BCSR_INT_SD0INSERT      0x1000
 #define BCSR_INT_SD0EJECT       0x2000
 
-#define SMC91C111_PHYS_ADDR     0x19000300
-#define SMC91C111_INT           DB1200_ETH_INT
-
 #define IDE_PHYS_ADDR           0x18800000
 #define IDE_REG_SHIFT           5
-#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
-#define IDE_INT                 DB1200_IDE_INT
 #define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
 #define IDE_RQSIZE              128
 
-#define NAND_PHYS_ADDR          0x20000000
+#define DB1200_IDE_PHYS_ADDR    IDE_PHYS_ADDR
+#define DB1200_IDE_PHYS_LEN     (16 << IDE_REG_SHIFT)
+#define DB1200_ETH_PHYS_ADDR    0x19000300
+#define DB1200_NAND_PHYS_ADDR   0x20000000
 
 /*
  * External Interrupts for DBAu1200 as of 8/6/2004.
@@ -188,7 +62,7 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
  *   Example: IDE bis pos is  = 64 - 64
  *            ETH bit pos is  = 65 - 64
  */
-enum external_pb1200_ints {
+enum external_db1200_ints {
         DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
 
         DB1200_IDE_INT          = DB1200_INT_BEGIN,
@@ -209,22 +83,4 @@ enum external_pb1200_ints {
         DB1200_INT_END          = DB1200_INT_BEGIN + 15,
 };
 
-
-/*
- * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
- */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-#define BOARD_PC0_INT   DB1200_PC0_INT
-#define BOARD_PC1_INT   DB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
-
-/* NAND chip select */
-#define NAND_CS 1
-
 #endif /* __ASM_DB1200_H */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
index 1a515b8c870f..a919dac525a1 100644
--- a/arch/mips/include/asm/mach-db1x00/db1x00.h
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -41,111 +41,11 @@
 #define SMBUS_PSC_BASE          PSC2_BASE_ADDR
 #define I2S_PSC_BASE            PSC3_BASE_ADDR
 
-#define BCSR_KSEG1_ADDR         0xAF000000
 #define NAND_PHYS_ADDR          0x20000000
 
-#else
-#define BCSR_KSEG1_ADDR 0xAE000000
 #endif
 
 /*
- * Overlay data structure of the DBAu1x00 board registers.
- * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
- */
-typedef volatile struct
-{
-        /*00*/  unsigned short whoami;
-        unsigned short reserved0;
-        /*04*/  unsigned short status;
-        unsigned short reserved1;
-        /*08*/  unsigned short switches;
-        unsigned short reserved2;
-        /*0C*/  unsigned short resets;
-        unsigned short reserved3;
-        /*10*/  unsigned short pcmcia;
-        unsigned short reserved4;
-        /*14*/  unsigned short specific;
-        unsigned short reserved5;
-        /*18*/  unsigned short leds;
-        unsigned short reserved6;
-        /*1C*/  unsigned short swreset;
-        unsigned short reserved7;
-
-} BCSR;
-
-
-/*
- * Register/mask bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID                0x000F
-#define BCSR_WHOAMI_CPLD                0x00F0
-#define BCSR_WHOAMI_BOARD               0x0F00
-
-#define BCSR_STATUS_PC0VS               0x0003
-#define BCSR_STATUS_PC1VS               0x000C
-#define BCSR_STATUS_PC0FI               0x0010
-#define BCSR_STATUS_PC1FI               0x0020
-#define BCSR_STATUS_FLASHBUSY           0x0100
-#define BCSR_STATUS_ROMBUSY             0x0400
-#define BCSR_STATUS_SWAPBOOT            0x2000
-#define BCSR_STATUS_FLASHDEN            0xC000
-
-#define BCSR_SWITCHES_DIP               0x00FF
-#define BCSR_SWITCHES_DIP_1             0x0080
-#define BCSR_SWITCHES_DIP_2             0x0040
-#define BCSR_SWITCHES_DIP_3             0x0020
-#define BCSR_SWITCHES_DIP_4             0x0010
-#define BCSR_SWITCHES_DIP_5             0x0008
-#define BCSR_SWITCHES_DIP_6             0x0004
-#define BCSR_SWITCHES_DIP_7             0x0002
-#define BCSR_SWITCHES_DIP_8             0x0001
-#define BCSR_SWITCHES_ROTARY            0x0F00
-
-#define BCSR_RESETS_PHY0                0x0001
-#define BCSR_RESETS_PHY1                0x0002
-#define BCSR_RESETS_DC                  0x0004
-#define BCSR_RESETS_FIR_SEL             0x2000
-#define BCSR_RESETS_IRDA_MODE_MASK      0xC000
-#define BCSR_RESETS_IRDA_MODE_FULL      0x0000
-#define BCSR_RESETS_IRDA_MODE_OFF       0x4000
-#define BCSR_RESETS_IRDA_MODE_2_3       0x8000
-#define BCSR_RESETS_IRDA_MODE_1_3       0xC000
-
-#define BCSR_PCMCIA_PC0VPP              0x0003
-#define BCSR_PCMCIA_PC0VCC              0x000C
-#define BCSR_PCMCIA_PC0DRVEN            0x0010
-#define BCSR_PCMCIA_PC0RST              0x0080
-#define BCSR_PCMCIA_PC1VPP              0x0300
-#define BCSR_PCMCIA_PC1VCC              0x0C00
-#define BCSR_PCMCIA_PC1DRVEN            0x1000
-#define BCSR_PCMCIA_PC1RST              0x8000
-
-#define BCSR_BOARD_PCIM66EN             0x0001
-#define BCSR_BOARD_SD0_PWR              0x0040
-#define BCSR_BOARD_SD1_PWR              0x0080
-#define BCSR_BOARD_PCIM33               0x0100
-#define BCSR_BOARD_GPIO200RST           0x0400
-#define BCSR_BOARD_PCICFG               0x1000
-#define BCSR_BOARD_SD0_WP               0x4000
-#define BCSR_BOARD_SD1_WP               0x8000
-
-#define BCSR_LEDS_DECIMALS              0x0003
-#define BCSR_LEDS_LED0                  0x0100
-#define BCSR_LEDS_LED1                  0x0200
-#define BCSR_LEDS_LED2                  0x0400
-#define BCSR_LEDS_LED3                  0x0800
-
-#define BCSR_SWRESET_RESET              0x0080
-
-/* PCMCIA DBAu1x00 specific defines */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-/*
  * NAND defines
  *
  * Timing values as described in databook, * ns value stripped of the
diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 9947e57c91de..16210cedd929 100644
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2009 Wu Zhangjin <wuzj@lemote.com>
+ * Copyright (C) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
  * Copyright (C) 2009 Philippe Vachon <philippe@cowpig.ca>
  * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
  *
diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
index 6305bea7e18e..21c4ecedebe7 100644
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -2,7 +2,7 @@
  * the read/write interfaces for Virtual Support Module(VSM)
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  */
 
 #ifndef _CS5536_VSM_H
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index ee8bc8376972..1cf7b1401ee4 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -1,12 +1,11 @@
 /*
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
- *
  */
 
 #ifndef __ASM_MACH_LOONGSON_LOONGSON_H
@@ -23,7 +22,7 @@ extern void mach_prepare_reboot(void);
 extern void mach_prepare_shutdown(void);
 
 /* environment arguments from bootloader */
-extern unsigned long bus_clock, cpu_clock_freq;
+extern unsigned long cpu_clock_freq;
 extern unsigned long memsize, highmemsize;
 
 /* loongson-specific command line, env and memory initialization */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index acf8359cb135..43213388c174 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index e9960f341b96..3b23ee8647d6 100644
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index a199a4f6de4e..bc99dab4ef63 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -1,23 +1,12 @@
 /*
  * Copyright (c) 2008 Zhang Le <r0bertz@gentoo.org>
- * Copyright (c) 2009 Wu Zhangjin <wuzj@lemote.com>
+ * Copyright (c) 2009 Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute it
  * and/or modify it under the terms of the GNU General
  * Public License as published by the Free Software
  * Foundation; either version 2 of the License, or (at your
  * option) any later version.
- *
- * This program is distributed in the hope that it will be
- * useful, but WITHOUT ANY WARRANTY; without even the implied
- * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- * PURPOSE.  See the GNU General Public License for more
- * details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this program; if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
- * 02139, USA.
  */
 
 #ifndef __ASM_MACH_LOONGSON_PCI_H_
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h
deleted file mode 100644
index b1a60f1cbd02..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1100.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Alchemy Semi Pb1100 Referrence Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1100_H
-#define __ASM_PB1100_H
-
-#define PB1100_IDENT            0xAE000000
-#define BOARD_STATUS_REG        0xAE000004
-#  define PB1100_ROM_SEL        (1 << 15)
-#  define PB1100_ROM_SIZ        (1 << 14)
-#  define PB1100_SWAP_BOOT      (1 << 13)
-#  define PB1100_FLASH_WP       (1 << 12)
-#  define PB1100_ROM_H_STS      (1 << 11)
-#  define PB1100_ROM_L_STS      (1 << 10)
-#  define PB1100_FLASH_H_STS    (1 << 9)
-#  define PB1100_FLASH_L_STS    (1 << 8)
-#  define PB1100_SRAM_SIZ       (1 << 7)
-#  define PB1100_TSC_BUSY       (1 << 6)
-#  define PB1100_PCMCIA_VS_MASK (3 << 4)
-#  define PB1100_RS232_CD       (1 << 3)
-#  define PB1100_RS232_CTS      (1 << 2)
-#  define PB1100_RS232_DSR      (1 << 1)
-#  define PB1100_RS232_RI       (1 << 0)
-
-#define PB1100_IRDA_RS232       0xAE00000C
-#  define PB1100_IRDA_FULL      (0 << 14)       /* full power           */
-#  define PB1100_IRDA_SHUTDOWN  (1 << 14)
-#  define PB1100_IRDA_TT        (2 << 14)       /* 2/3 power            */
-#  define PB1100_IRDA_OT        (3 << 14)       /* 1/3 power            */
-#  define PB1100_IRDA_FIR       (1 << 13)
-
-#define PCMCIA_BOARD_REG        0xAE000010
-#  define PB1100_SD_WP1_RO      (1 << 15)       /* read only            */
-#  define PB1100_SD_WP0_RO      (1 << 14)       /* read only            */
-#  define PB1100_SD_PWR1        (1 << 11)       /* applies power to SD1 */
-#  define PB1100_SD_PWR0        (1 << 10)       /* applies power to SD0 */
-#  define PB1100_SEL_SD_CONN1   (1 << 9)
-#  define PB1100_SEL_SD_CONN0   (1 << 8)
-#  define PC_DEASSERT_RST       (1 << 7)
-#  define PC_DRV_EN             (1 << 4)
-
-#define PB1100_G_CONTROL        0xAE000014      /* graphics control     */
-
-#define PB1100_RST_VDDI         0xAE00001C
-#  define PB1100_SOFT_RESET     (1 << 15)       /* clear to reset the board */
-#  define PB1100_VDDI_MASK      0x1F
-
-#define PB1100_LEDS             0xAE000018
-
-/*
- * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
- * 7:0  is the LED Display's decimal points.
- */
-#define PB1100_HEX_LED          0xAE000018
-
-/* PCMCIA Pb1100 specific defines */
-#define PCMCIA_MAX_SOCK  0
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
-
-#endif /* __ASM_PB1100_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
index c8618df88cb5..962eb55dc880 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1200.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -25,6 +25,7 @@
 #define __ASM_PB1200_H
 
 #include <linux/types.h>
+#include <asm/mach-au1x00/au1000.h>
 #include <asm/mach-au1x00/au1xxx_psc.h>
 
 #define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
@@ -43,113 +44,8 @@
  * Refer to board documentation.
  */
 #define AC97_PSC_BASE       PSC1_BASE_ADDR
-#define I2S_PSC_BASE            PSC1_BASE_ADDR
+#define I2S_PSC_BASE    PSC1_BASE_ADDR
 
-#define BCSR_KSEG1_ADDR 0xAD800000
-
-typedef volatile struct
-{
-        /*00*/  u16 whoami;
-                u16 reserved0;
-        /*04*/  u16 status;
-                u16 reserved1;
-        /*08*/  u16 switches;
-                u16 reserved2;
-        /*0C*/  u16 resets;
-                u16 reserved3;
-
-        /*10*/  u16 pcmcia;
-                u16 reserved4;
-        /*14*/  u16 board;
-                u16 reserved5;
-        /*18*/  u16 disk_leds;
-                u16 reserved6;
-        /*1C*/  u16 system;
-                u16 reserved7;
-
-        /*20*/  u16 intclr;
-                u16 reserved8;
-        /*24*/  u16 intset;
-                u16 reserved9;
-        /*28*/  u16 intclr_mask;
-                u16 reserved10;
-        /*2C*/  u16 intset_mask;
-                u16 reserved11;
-
-        /*30*/  u16 sig_status;
-                u16 reserved12;
-        /*34*/  u16 int_status;
-                u16 reserved13;
-        /*38*/  u16 reserved14;
-                u16 reserved15;
-        /*3C*/  u16 reserved16;
-                u16 reserved17;
-
-} BCSR;
-
-static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-
-/*
- * Register bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID        0x000F
-#define BCSR_WHOAMI_CPLD        0x00F0
-#define BCSR_WHOAMI_BOARD       0x0F00
-
-#define BCSR_STATUS_PCMCIA0VS   0x0003
-#define BCSR_STATUS_PCMCIA1VS   0x000C
-#define BCSR_STATUS_SWAPBOOT    0x0040
-#define BCSR_STATUS_FLASHBUSY   0x0100
-#define BCSR_STATUS_IDECBLID    0x0200
-#define BCSR_STATUS_SD0WP       0x0400
-#define BCSR_STATUS_SD1WP       0x0800
-#define BCSR_STATUS_U0RXD       0x1000
-#define BCSR_STATUS_U1RXD       0x2000
-
-#define BCSR_SWITCHES_OCTAL     0x00FF
-#define BCSR_SWITCHES_DIP_1     0x0080
-#define BCSR_SWITCHES_DIP_2     0x0040
-#define BCSR_SWITCHES_DIP_3     0x0020
-#define BCSR_SWITCHES_DIP_4     0x0010
-#define BCSR_SWITCHES_DIP_5     0x0008
-#define BCSR_SWITCHES_DIP_6     0x0004
-#define BCSR_SWITCHES_DIP_7     0x0002
-#define BCSR_SWITCHES_DIP_8     0x0001
-#define BCSR_SWITCHES_ROTARY    0x0F00
-
-#define BCSR_RESETS_ETH         0x0001
-#define BCSR_RESETS_CAMERA      0x0002
-#define BCSR_RESETS_DC          0x0004
-#define BCSR_RESETS_IDE         0x0008
-/* not resets but in the same register */
-#define BCSR_RESETS_WSCFSM      0x0800
-#define BCSR_RESETS_PCS0MUX     0x1000
-#define BCSR_RESETS_PCS1MUX     0x2000
-#define BCSR_RESETS_SPISEL      0x4000
-#define BCSR_RESETS_SD1MUX      0x8000
-
-#define BCSR_PCMCIA_PC0VPP      0x0003
-#define BCSR_PCMCIA_PC0VCC      0x000C
-#define BCSR_PCMCIA_PC0DRVEN    0x0010
-#define BCSR_PCMCIA_PC0RST      0x0080
-#define BCSR_PCMCIA_PC1VPP      0x0300
-#define BCSR_PCMCIA_PC1VCC      0x0C00
-#define BCSR_PCMCIA_PC1DRVEN    0x1000
-#define BCSR_PCMCIA_PC1RST      0x8000
-
-#define BCSR_BOARD_LCDVEE       0x0001
-#define BCSR_BOARD_LCDVDD       0x0002
-#define BCSR_BOARD_LCDBL        0x0004
-#define BCSR_BOARD_CAMSNAP      0x0010
-#define BCSR_BOARD_CAMPWR       0x0020
-#define BCSR_BOARD_SD0PWR       0x0040
-#define BCSR_BOARD_SD1PWR       0x0080
-
-#define BCSR_LEDS_DECIMALS      0x00FF
-#define BCSR_LEDS_LED0          0x0100
-#define BCSR_LEDS_LED1          0x0200
-#define BCSR_LEDS_LED2          0x0400
-#define BCSR_LEDS_LED3          0x0800
 
 #define BCSR_SYSTEM_VDDI        0x001F
 #define BCSR_SYSTEM_POWEROFF    0x4000
@@ -239,20 +135,6 @@ enum external_pb1200_ints {
         PB1200_INT_END          = PB1200_INT_BEGIN + 15
 };
 
-/*
- * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
- */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-#define BOARD_PC0_INT   PB1200_PC0_INT
-#define BOARD_PC1_INT   PB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
-
 /* NAND chip select */
 #define NAND_CS 1
 
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h
deleted file mode 100644
index da51a2eb7b82..000000000000
--- a/arch/mips/include/asm/mach-pb1x00/pb1500.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Alchemy Semi Pb1500 Referrence Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1500_H
-#define __ASM_PB1500_H
-
-#define IDENT_BOARD_REG         0xAE000000
-#define BOARD_STATUS_REG        0xAE000004
-#define PCI_BOARD_REG           0xAE000010
-#define PCMCIA_BOARD_REG        0xAE000010
-#  define PC_DEASSERT_RST             0x80
-#  define PC_DRV_EN                   0x10
-#define PB1500_G_CONTROL        0xAE000014
-#define PB1500_RST_VDDI         0xAE00001C
-#define PB1500_LEDS             0xAE000018
-
-#define PB1500_HEX_LED          0xAF000004
-#define PB1500_HEX_LED_BLANK    0xAF000008
-
-/* PCMCIA Pb1500 specific defines */
-#define PCMCIA_MAX_SOCK  0
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
-
-#endif /* __ASM_PB1500_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
index 6704a11497db..58796410bd6e 100644
--- a/arch/mips/include/asm/mach-pb1x00/pb1550.h
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -40,102 +40,6 @@
 #define SMBUS_PSC_BASE          PSC2_BASE_ADDR
 #define I2S_PSC_BASE            PSC3_BASE_ADDR
 
-#define BCSR_PHYS_ADDR 0xAF000000
-
-typedef volatile struct
-{
-        /*00*/  u16 whoami;
-                u16 reserved0;
-        /*04*/  u16 status;
-                u16 reserved1;
-        /*08*/  u16 switches;
-                u16 reserved2;
-        /*0C*/  u16 resets;
-                u16 reserved3;
-        /*10*/  u16 pcmcia;
-                u16 reserved4;
-        /*14*/  u16 pci;
-                u16 reserved5;
-        /*18*/  u16 leds;
-                u16 reserved6;
-        /*1C*/  u16 system;
-                u16 reserved7;
-
-} BCSR;
-
-static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
-
-/*
- * Register bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID        0x000F
-#define BCSR_WHOAMI_CPLD        0x00F0
-#define BCSR_WHOAMI_BOARD       0x0F00
-
-#define BCSR_STATUS_PCMCIA0VS   0x0003
-#define BCSR_STATUS_PCMCIA1VS   0x000C
-#define BCSR_STATUS_PCMCIA0FI   0x0010
-#define BCSR_STATUS_PCMCIA1FI   0x0020
-#define BCSR_STATUS_SWAPBOOT    0x0040
-#define BCSR_STATUS_SRAMWIDTH   0x0080
-#define BCSR_STATUS_FLASHBUSY   0x0100
-#define BCSR_STATUS_ROMBUSY     0x0200
-#define BCSR_STATUS_USBOTGID    0x0800
-#define BCSR_STATUS_U0RXD       0x1000
-#define BCSR_STATUS_U1RXD       0x2000
-#define BCSR_STATUS_U3RXD       0x8000
-
-#define BCSR_SWITCHES_OCTAL     0x00FF
-#define BCSR_SWITCHES_DIP_1     0x0080
-#define BCSR_SWITCHES_DIP_2     0x0040
-#define BCSR_SWITCHES_DIP_3     0x0020
-#define BCSR_SWITCHES_DIP_4     0x0010
-#define BCSR_SWITCHES_DIP_5     0x0008
-#define BCSR_SWITCHES_DIP_6     0x0004
-#define BCSR_SWITCHES_DIP_7     0x0002
-#define BCSR_SWITCHES_DIP_8     0x0001
-#define BCSR_SWITCHES_ROTARY    0x0F00
-
-#define BCSR_RESETS_PHY0        0x0001
-#define BCSR_RESETS_PHY1        0x0002
-#define BCSR_RESETS_DC          0x0004
-#define BCSR_RESETS_WSC         0x2000
-#define BCSR_RESETS_SPISEL      0x4000
-#define BCSR_RESETS_DMAREQ      0x8000
-
-#define BCSR_PCMCIA_PC0VPP      0x0003
-#define BCSR_PCMCIA_PC0VCC      0x000C
-#define BCSR_PCMCIA_PC0DRVEN    0x0010
-#define BCSR_PCMCIA_PC0RST      0x0080
-#define BCSR_PCMCIA_PC1VPP      0x0300
-#define BCSR_PCMCIA_PC1VCC      0x0C00
-#define BCSR_PCMCIA_PC1DRVEN    0x1000
-#define BCSR_PCMCIA_PC1RST      0x8000
-
-#define BCSR_PCI_M66EN          0x0001
-#define BCSR_PCI_M33            0x0100
-#define BCSR_PCI_EXTERNARB      0x0200
-#define BCSR_PCI_GPIO200RST     0x0400
-#define BCSR_PCI_CLKOUT         0x0800
-#define BCSR_PCI_CFGHOST        0x1000
-
-#define BCSR_LEDS_DECIMALS      0x00FF
-#define BCSR_LEDS_LED0          0x0100
-#define BCSR_LEDS_LED1          0x0200
-#define BCSR_LEDS_LED2          0x0400
-#define BCSR_LEDS_LED3          0x0800
-
-#define BCSR_SYSTEM_VDDI        0x001F
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
 #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
 #define PB1550_BOTH_BANKS
 #elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
index 657f089b1724..6d70264557b2 100644
--- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -123,4 +123,3 @@
 #define PNX833X_GPIO_15_INT                     (PNX833X_GPIO_IRQ_BASE + 15)
 
 #endif
-
diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
index 629a57413657..4fd652ceb52a 100644
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -251,4 +251,3 @@
                                                  * channel 3. */
 #define irq_mpeg_d              (ibase+0)       /* MPEG Decoder Interrupt */
 #endif  /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
-
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index f4ab3139d737..49382d5e891a 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -251,6 +251,14 @@
 #define PL_256M         28
 
 /*
+ * PageGrain bits
+ */
+#define PG_RIE          (_ULCAST_(1) <<  31)
+#define PG_XIE          (_ULCAST_(1) <<  30)
+#define PG_ELPA         (_ULCAST_(1) <<  29)
+#define PG_ESP          (_ULCAST_(1) <<  28)
+
+/*
  * R4x00 interrupt enable / cause bits
  */
 #define IE_SW0          (_ULCAST_(1) <<  8)
@@ -576,6 +584,10 @@
 #define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
 #define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
 
+#define MIPS_CONF4_MMUSIZEEXT   (_ULCAST_(255) << 0)
+#define MIPS_CONF4_MMUEXTDEF    (_ULCAST_(3) << 14)
+#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
+
 #define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
 
 #define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
@@ -826,6 +838,9 @@ do {									\
 #define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
 
+#define read_c0_pagegrain()     __read_32bit_c0_register($5, 1)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
+
 #define read_c0_wired()         __read_32bit_c0_register($6, 0)
 #define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
 
diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
index 7989b9ffc1d2..d92406ae2841 100644
--- a/arch/mips/include/asm/msc01_ic.h
+++ b/arch/mips/include/asm/msc01_ic.h
@@ -145,4 +145,3 @@ extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_i
 extern void ll_msc_irq(void);
 
 #endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
-
diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h
index c3ca959aa4d9..af0e51a9f68a 100644
--- a/arch/mips/include/asm/nile4.h
+++ b/arch/mips/include/asm/nile4.h
@@ -307,4 +307,3 @@ extern u8 nile4_i8259_iack(void);
 extern void nile4_dump_irq_status(void);        /* Debug */
 
 #endif
-
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index ef24a7b4ea57..cba6fbed9f43 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -99,6 +99,8 @@ static inline int octeon_has_feature(enum octeon_feature feature)
                 return !cvmx_fuse_read(90);
 
         case OCTEON_FEATURE_PCIE:
+        case OCTEON_FEATURE_MGMT_PORT:
+        case OCTEON_FEATURE_RAID:
                 return OCTEON_IS_MODEL(OCTEON_CN56XX)
                         || OCTEON_IS_MODEL(OCTEON_CN52XX);
 
@@ -110,12 +112,6 @@ static inline int octeon_has_feature(enum octeon_feature feature)
         case OCTEON_FEATURE_TRA:
                 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
                          || OCTEON_IS_MODEL(OCTEON_CN50XX));
-        case OCTEON_FEATURE_MGMT_PORT:
-                return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
-        case OCTEON_FEATURE_RAID:
-                return OCTEON_IS_MODEL(OCTEON_CN56XX)
-                        || OCTEON_IS_MODEL(OCTEON_CN52XX);
         case OCTEON_FEATURE_USB:
                 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
                          || OCTEON_IS_MODEL(OCTEON_CN58XX));
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 4d0a8c61fc3e..ca6214b5ccb9 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -213,6 +213,11 @@ struct octeon_cf_data {
         int             dma_engine;     /* -1 for no DMA */
 };
 
+struct octeon_i2c_data {
+        unsigned int    sys_freq;
+        unsigned int    i2c_freq;
+};
+
 extern void octeon_write_lcd(const char *s);
 extern void octeon_check_cpu_bist(void);
 extern int octeon_get_boot_debug_flag(void);
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index f266295cce51..ac32572430f4 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -107,18 +107,6 @@ typedef struct { unsigned long pte; } pte_t;
 typedef struct page *pgtable_t;
 
 /*
- * For 3-level pagetables we defines these ourselves, for 2-level the
- * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
- */
-#ifdef CONFIG_64BIT
-
-typedef struct { unsigned long pmd; } pmd_t;
-#define pmd_val(x)      ((x).pmd)
-#define __pmd(x)        ((pmd_t) { (x) } )
-
-#endif
-
-/*
  * Right now we don't support 4-level pagetables, so all pud-related
  * definitions come from <asm-generic/pgtable-nopud.h>.
  */
diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h
index 1d9bb8c5ab24..da3920fce9ad 100644
--- a/arch/mips/include/asm/param.h
+++ b/arch/mips/include/asm/param.h
@@ -9,23 +9,8 @@
 #ifndef _ASM_PARAM_H
 #define _ASM_PARAM_H
 
-#ifdef __KERNEL__
-
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
 #define EXEC_PAGESIZE   65536
 
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
+#include <asm-generic/param.h>
 
 #endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h
index f52656826cce..cf252af64590 100644
--- a/arch/mips/include/asm/parport.h
+++ b/arch/mips/include/asm/parport.h
@@ -1,15 +1 @@
-/*
- * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-#ifndef _ASM_PARPORT_H
-#define _ASM_PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports(autoirq, autodma);
-}
-
-#endif /* _ASM_PARPORT_H */
+#include <asm-generic/parport.h>
diff --git a/arch/mips/include/asm/pgalloc.h b/arch/mips/include/asm/pgalloc.h
index 3738f4b48cbd..881d18b4e298 100644
--- a/arch/mips/include/asm/pgalloc.h
+++ b/arch/mips/include/asm/pgalloc.h
@@ -31,7 +31,7 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
  */
 extern void pmd_init(unsigned long page, unsigned long pagetable);
 
-#ifdef CONFIG_64BIT
+#ifndef __PAGETABLE_PMD_FOLDED
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 {
@@ -104,7 +104,7 @@ do {							\
         tlb_remove_page((tlb), pte);                    \
 } while (0)
 
-#ifdef CONFIG_64BIT
+#ifndef __PAGETABLE_PMD_FOLDED
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 {
diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 55813d6150c7..ae90412556d0 100644
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -127,8 +127,8 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 #else
-#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pte_pfn(x)              ((unsigned long)((x).pte >> _PFN_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot))
 #endif
 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 8eda30b467da..26dc69d792a6 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -16,7 +16,11 @@
 #include <asm/cachectl.h>
 #include <asm/fixmap.h>
 
+#ifdef CONFIG_PAGE_SIZE_64KB
+#include <asm-generic/pgtable-nopmd.h>
+#else
 #include <asm-generic/pgtable-nopud.h>
+#endif
 
 /*
  * Each address space has 2 4K pages as its page directory, giving 1024
@@ -37,13 +41,20 @@
  * fault address - VMALLOC_START.
  */
 
+
+/* PGDIR_SHIFT determines what a third-level page table entry can map */
+#ifdef __PAGETABLE_PMD_FOLDED
+#define PGDIR_SHIFT     (PAGE_SHIFT + PAGE_SHIFT + PTE_ORDER - 3)
+#else
+
 /* PMD_SHIFT determines the size of the area a second-level page table can map */
 #define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
 #define PMD_SIZE        (1UL << PMD_SHIFT)
 #define PMD_MASK        (~(PMD_SIZE-1))
 
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
+
 #define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
+#endif
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
@@ -92,12 +103,14 @@
 #ifdef CONFIG_PAGE_SIZE_64KB
 #define PGD_ORDER               0
 #define PUD_ORDER               aieeee_attempt_to_allocate_pud
-#define PMD_ORDER               0
+#define PMD_ORDER               aieeee_attempt_to_allocate_pmd
 #define PTE_ORDER               0
 #endif
 
 #define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
+#ifndef __PAGETABLE_PMD_FOLDED
 #define PTRS_PER_PMD    ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
+#endif
 #define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
 #if PGDIR_SIZE >= TASK_SIZE
@@ -122,15 +135,30 @@
 
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
+#ifndef __PAGETABLE_PMD_FOLDED
 #define pmd_ERROR(e) \
         printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
+#endif
 #define pgd_ERROR(e) \
         printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
 
 extern pte_t invalid_pte_table[PTRS_PER_PTE];
 extern pte_t empty_bad_page_table[PTRS_PER_PTE];
+
+
+#ifndef __PAGETABLE_PMD_FOLDED
+/*
+ * For 3-level pagetables we defines these ourselves, for 2-level the
+ * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
+ */
+typedef struct { unsigned long pmd; } pmd_t;
+#define pmd_val(x)      ((x).pmd)
+#define __pmd(x)        ((pmd_t) { (x) } )
+
+
 extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
 extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
+#endif
 
 /*
  * Empty pgd/pmd entries point to the invalid_pte_table.
@@ -151,6 +179,7 @@ static inline void pmd_clear(pmd_t *pmdp)
 {
         pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
 }
+#ifndef __PAGETABLE_PMD_FOLDED
 
 /*
  * Empty pud entries point to the invalid_pmd_table.
@@ -174,6 +203,7 @@ static inline void pud_clear(pud_t *pudp)
 {
         pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
 }
+#endif
 
 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 
@@ -181,8 +211,8 @@ static inline void pud_clear(pud_t *pudp)
 #define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
 #define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
 #else
-#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
+#define pte_pfn(x)              ((unsigned long)((x).pte >> _PFN_SHIFT))
+#define pfn_pte(pfn, prot)      __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot))
 #endif
 
 #define __pgd_offset(address)   pgd_index(address)
@@ -198,6 +228,7 @@ static inline void pud_clear(pud_t *pudp)
 /* to find an entry in a page-table-directory */
 #define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
 
+#ifndef __PAGETABLE_PMD_FOLDED
 static inline unsigned long pud_page_vaddr(pud_t pud)
 {
         return pud_val(pud);
@@ -210,6 +241,7 @@ static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
 {
         return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
 }
+#endif
 
 /* Find an entry in the third-level page table.. */
 #define __pte_offset(address)                                           \
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 1073e6df8621..e9fe7e97ce4c 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -50,7 +50,7 @@
 #define _CACHE_SHIFT                3
 #define _CACHE_MASK                 (7<<3)
 
-#else
+#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 
 #define _PAGE_PRESENT               (1<<0)  /* implemented in software */
 #define _PAGE_READ                  (1<<1)  /* implemented in software */
@@ -59,8 +59,6 @@
 #define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
 #define _PAGE_FILE                  (1<<4)  /* set:pagecache unset:swap */
 
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-
 #define _PAGE_GLOBAL                (1<<8)
 #define _PAGE_VALID                 (1<<9)
 #define _PAGE_SILENT_READ           (1<<9)  /* synonym                 */
@@ -69,21 +67,113 @@
 #define _CACHE_UNCACHED             (1<<11)
 #define _CACHE_MASK                 (1<<11)
 
+#else /* 'Normal' r4K case */
+/*
+ * When using the RI/XI bit support, we have 13 bits of flags below
+ * the physical address. The RI/XI bits are placed such that a SRL 5
+ * can strip off the software bits, then a ROTR 2 can move the RI/XI
+ * into bits [63:62]. This also limits physical address to 56 bits,
+ * which is more than we need right now.
+ */
+
+/* implemented in software */
+#define _PAGE_PRESENT_SHIFT     (0)
+#define _PAGE_PRESENT           (1 << _PAGE_PRESENT_SHIFT)
+/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */
+#define _PAGE_READ_SHIFT        (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1)
+#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; })
+/* implemented in software */
+#define _PAGE_WRITE_SHIFT       (_PAGE_READ_SHIFT + 1)
+#define _PAGE_WRITE             (1 << _PAGE_WRITE_SHIFT)
+/* implemented in software */
+#define _PAGE_ACCESSED_SHIFT    (_PAGE_WRITE_SHIFT + 1)
+#define _PAGE_ACCESSED          (1 << _PAGE_ACCESSED_SHIFT)
+/* implemented in software */
+#define _PAGE_MODIFIED_SHIFT    (_PAGE_ACCESSED_SHIFT + 1)
+#define _PAGE_MODIFIED          (1 << _PAGE_MODIFIED_SHIFT)
+/* set:pagecache unset:swap */
+#define _PAGE_FILE              (_PAGE_MODIFIED)
+
+#ifdef CONFIG_HUGETLB_PAGE
+/* huge tlb page */
+#define _PAGE_HUGE_SHIFT        (_PAGE_MODIFIED_SHIFT + 1)
+#define _PAGE_HUGE              (1 << _PAGE_HUGE_SHIFT)
 #else
+#define _PAGE_HUGE_SHIFT        (_PAGE_MODIFIED_SHIFT)
+#define _PAGE_HUGE              ({BUG(); 1; })  /* Dummy value */
+#endif
 
-#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
-#define _PAGE_HUGE                  (1<<5)  /* huge tlb page */
-#define _PAGE_GLOBAL                (1<<6)
-#define _PAGE_VALID                 (1<<7)
-#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
-#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE          (1<<8)
-#define _CACHE_SHIFT                9
-#define _CACHE_MASK                 (7<<9)
+/* Page cannot be executed */
+#define _PAGE_NO_EXEC_SHIFT     (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT)
+#define _PAGE_NO_EXEC           ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; })
+
+/* Page cannot be read */
+#define _PAGE_NO_READ_SHIFT     (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT)
+#define _PAGE_NO_READ           ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; })
+
+#define _PAGE_GLOBAL_SHIFT      (_PAGE_NO_READ_SHIFT + 1)
+#define _PAGE_GLOBAL            (1 << _PAGE_GLOBAL_SHIFT)
+
+#define _PAGE_VALID_SHIFT       (_PAGE_GLOBAL_SHIFT + 1)
+#define _PAGE_VALID             (1 << _PAGE_VALID_SHIFT)
+/* synonym                 */
+#define _PAGE_SILENT_READ       (_PAGE_VALID)
+
+/* The MIPS dirty bit      */
+#define _PAGE_DIRTY_SHIFT       (_PAGE_VALID_SHIFT + 1)
+#define _PAGE_DIRTY             (1 << _PAGE_DIRTY_SHIFT)
+#define _PAGE_SILENT_WRITE      (_PAGE_DIRTY)
+
+#define _CACHE_SHIFT            (_PAGE_DIRTY_SHIFT + 1)
+#define _CACHE_MASK             (7 << _CACHE_SHIFT)
+
+#define _PFN_SHIFT              (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3)
 
-#endif
 #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
 
+#ifndef _PFN_SHIFT
+#define _PFN_SHIFT                  PAGE_SHIFT
+#endif
+#define _PFN_MASK               (~((1 << (_PFN_SHIFT)) - 1))
+
+#ifndef _PAGE_NO_READ
+#define _PAGE_NO_READ ({BUG(); 0; })
+#define _PAGE_NO_READ_SHIFT ({BUG(); 0; })
+#endif
+#ifndef _PAGE_NO_EXEC
+#define _PAGE_NO_EXEC ({BUG(); 0; })
+#endif
+#ifndef _PAGE_GLOBAL_SHIFT
+#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL)
+#endif
+
+
+#ifndef __ASSEMBLY__
+/*
+ * pte_to_entrylo converts a page table entry (PTE) into a Mips
+ * entrylo0/1 value.
+ */
+static inline uint64_t pte_to_entrylo(unsigned long pte_val)
+{
+        if (kernel_uses_smartmips_rixi) {
+                int sa;
+#ifdef CONFIG_32BIT
+                sa = 31 - _PAGE_NO_READ_SHIFT;
+#else
+                sa = 63 - _PAGE_NO_READ_SHIFT;
+#endif
+                /*
+                 * C has no way to express that this is a DSRL
+                 * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2.  Luckily
+                 * in the fast path this is done in assembly
+                 */
+                return (pte_val >> _PAGE_GLOBAL_SHIFT) |
+                        ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa);
+        }
+
+        return pte_val >> _PAGE_GLOBAL_SHIFT;
+}
+#endif
 
 /*
  * Cache attributes
@@ -130,9 +220,9 @@
 
 #endif
 
-#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
+#define __READABLE      (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ))
 #define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
 
-#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
+#define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
 
 #endif /* _ASM_PGTABLE_BITS_H */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 1854336e56a2..7e40f3778179 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -22,23 +22,24 @@ struct mm_struct;
 struct vm_area_struct;
 
 #define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
                                  _page_cachable_default)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | \
-                                 _page_cachable_default)
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
+#define PAGE_COPY       __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
+                                 (kernel_uses_smartmips_rixi ?  _PAGE_NO_EXEC : 0) | _page_cachable_default)
+#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \
                                  _page_cachable_default)
 #define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
                                  _PAGE_GLOBAL | _page_cachable_default)
-#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
+#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \
                                  _page_cachable_default)
 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
                         __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
 
 /*
- * MIPS can't do page protection for execute, and considers that the same like
- * read. Also, write permissions imply read permissions. This is the closest
- * we can get by reasonable means..
+ * If _PAGE_NO_EXEC is not defined, we can't do page protection for
+ * execute, and consider it to be the same as read. Also, write
+ * permissions imply read permissions. This is the closest we can get
+ * by reasonable means..
  */
 
 /*
@@ -177,7 +178,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
  */
 #define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
 
-#ifdef CONFIG_64BIT
+#ifndef __PAGETABLE_PMD_FOLDED
 /*
  * (puds are folded into pgds so this doesn't get actually called,
  * but the define is needed for a generic inline function.)
@@ -298,8 +299,13 @@ static inline pte_t pte_mkdirty(pte_t pte)
 static inline pte_t pte_mkyoung(pte_t pte)
 {
         pte_val(pte) |= _PAGE_ACCESSED;
-        if (pte_val(pte) & _PAGE_READ)
-                pte_val(pte) |= _PAGE_SILENT_READ;
+        if (kernel_uses_smartmips_rixi) {
+                if (!(pte_val(pte) & _PAGE_NO_READ))
+                        pte_val(pte) |= _PAGE_SILENT_READ;
+        } else {
+                if (pte_val(pte) & _PAGE_READ)
+                        pte_val(pte) |= _PAGE_SILENT_READ;
+        }
         return pte;
 }
 
@@ -362,8 +368,9 @@ extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
         pte_t pte);
 
 static inline void update_mmu_cache(struct vm_area_struct *vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
+        pte_t pte = *ptep;
         __update_tlb(vma, address, pte);
         __update_cache(vma, address, pte);
 }
diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 14ca7dc382a8..54ef1a96d7ce 100644
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -118,7 +118,6 @@
 #define ZSP_DUET                'D'     /* one DUET zsp engine */
 #define ZSP_TRIAD               'T'     /* two TRIAD zsp engines */
 
-extern char *prom_getcmdline(void);
 extern char *prom_getenv(char *name);
 extern void prom_init_cmdline(void);
 extern void prom_meminit(void);
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
index c07ebd8eb9e7..a0cb0caff152 100644
--- a/arch/mips/include/asm/serial.h
+++ b/arch/mips/include/asm/serial.h
@@ -1,22 +1 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SERIAL_H
-#define _ASM_SERIAL_H
-
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD (1843200 / 16)
-
-#endif /* _ASM_SERIAL_H */
+#include <asm-generic/serial.h>
diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index 63741ca1e422..2a2f1bddc276 100644
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -33,14 +33,6 @@ extern int prom_flags;
 extern void prom_putchar(char c);
 extern char prom_getchar(void);
 
-/* Memory descriptor management. */
-#define PROM_MAX_PMEMBLOCKS    32
-struct prom_pmemblock {
-        LONG    base;           /* Within KSEG0 or XKPHYS. */
-        ULONG   size;           /* In bytes. */
-        ULONG   type;           /* free or prom memory */
-};
-
 /* Get next memory descriptor after CURR, returns first descriptor
  * in chain is CURR is NULL.
  */
@@ -51,7 +43,6 @@ extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
  * array.
  */
 extern void prom_meminit(void);
-extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
 
 /* PROM device tree library routines. */
 #define PROM_NULL_COMPONENT ((pcomponent *) 0)
@@ -62,20 +53,6 @@ extern pcomponent *ArcGetPeer(pcomponent *this);
 /* Get child component of THIS. */
 extern pcomponent *ArcGetChild(pcomponent *this);
 
-/* Get parent component of CHILD. */
-extern pcomponent *prom_getparent(pcomponent *child);
-
-/* Copy component opaque data of component THIS into BUFFER
- * if component THIS has opaque data.  Returns success or
- * failure status.
- */
-extern long prom_getcdata(void *buffer, pcomponent *this);
-
-/* Other misc. component routines. */
-extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data);
-extern long prom_delcomponent(pcomponent *this);
-extern pcomponent *prom_componentbypath(char *path);
-
 /* This is called at prom_init time to identify the
  * ARC architecture we are running on
  */
@@ -88,35 +65,13 @@ extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
 /* ARCS command line parsing. */
 extern void prom_init_cmdline(void);
 
-/* Acquiring info about the current time, etc. */
-extern struct linux_tinfo *prom_gettinfo(void);
-extern unsigned long prom_getrtime(void);
-
 /* File operations. */
-extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt);
-extern long prom_open(char *name, enum linux_omode md, unsigned long *fd);
-extern long prom_close(unsigned long fd);
 extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
-extern long prom_getrstatus(unsigned long fd);
 extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
-extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm);
-extern long prom_mount(char *name, enum linux_mountops op);
-extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf);
-extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk);
-
-/* Running stand-along programs. */
-extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr);
-extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp);
-extern long prom_exec(char *name, long argc, char **argv, char **envp);
 
 /* Misc. routines. */
-extern VOID prom_halt(VOID) __attribute__((noreturn));
-extern VOID prom_powerdown(VOID) __attribute__((noreturn));
-extern VOID prom_restart(VOID) __attribute__((noreturn));
 extern VOID ArcReboot(VOID) __attribute__((noreturn));
 extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
-extern long prom_cfgsave(VOID);
-extern struct linux_sysid *prom_getsysid(VOID);
 extern VOID ArcFlushAllCaches(VOID);
 extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
 
diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
index ebefe797fc1d..2d1a26d3436a 100644
--- a/arch/mips/include/asm/sibyte/bigsur.h
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -46,4 +46,3 @@
 #endif
 
 #endif /* __ASM_SIBYTE_BIGSUR_H */
-
diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index 081e8b1c4ad0..1e76cf137995 100644
--- a/arch/mips/include/asm/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -420,4 +420,3 @@
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 #endif
-
diff --git a/arch/mips/include/asm/sn/klkernvars.h b/arch/mips/include/asm/sn/klkernvars.h
index 5de4c5e8ab30..6af25ba41ade 100644
--- a/arch/mips/include/asm/sn/klkernvars.h
+++ b/arch/mips/include/asm/sn/klkernvars.h
@@ -26,4 +26,3 @@ typedef struct kern_vars_s {
 #endif /* !__ASSEMBLY__ */
 
 #endif /* __ASM_SN_KLKERNVARS_H */
-
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 795ac6c23203..7165333ad043 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,4 +11,3 @@
 
 #endif /* CONFIG_SPARSEMEM */
 #endif /* _MIPS_SPARSEMEM_H */
-
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 21ef9efbde43..396e402fbe2c 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -36,9 +36,9 @@
 
 static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 {
-        unsigned int counters = ACCESS_ONCE(lock->lock);
+        u32 counters = ACCESS_ONCE(lock->lock);
 
-        return ((counters >> 14) ^ counters) & 0x1fff;
+        return ((counters >> 16) ^ counters) & 0xffff;
 }
 
 #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
@@ -47,9 +47,9 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock)
 
 static inline int arch_spin_is_contended(arch_spinlock_t *lock)
 {
-        unsigned int counters = ACCESS_ONCE(lock->lock);
+        u32 counters = ACCESS_ONCE(lock->lock);
 
-        return (((counters >> 14) - counters) & 0x1fff) > 1;
+        return (((counters >> 16) - counters) & 0xffff) > 1;
 }
 #define arch_spin_is_contended  arch_spin_is_contended
 
@@ -57,6 +57,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         int my_ticket;
         int tmp;
+        int inc = 0x10000;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__ (
@@ -64,25 +65,24 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       addiu   %[my_ticket], %[ticket], 0x4000         \n"
+                "       addu    %[my_ticket], %[ticket], %[inc]         \n"
                 "       sc      %[my_ticket], %[ticket_ptr]             \n"
                 "       beqzl   %[my_ticket], 1b                        \n"
                 "        nop                                            \n"
-                "       srl     %[my_ticket], %[ticket], 14             \n"
-                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
-                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       srl     %[my_ticket], %[ticket], 16             \n"
+                "       andi    %[ticket], %[ticket], 0xffff            \n"
+                "       andi    %[my_ticket], %[my_ticket], 0xffff      \n"
                 "       bne     %[ticket], %[my_ticket], 4f             \n"
                 "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
                 "2:                                                     \n"
                 "       .subsection 2                                   \n"
-                "4:     andi    %[ticket], %[ticket], 0x1fff            \n"
+                "4:     andi    %[ticket], %[ticket], 0xffff            \n"
                 "       sll     %[ticket], 5                            \n"
                 "                                                       \n"
                 "6:     bnez    %[ticket], 6b                           \n"
                 "        subu   %[ticket], 1                            \n"
                 "                                                       \n"
-                "       lw      %[ticket], %[ticket_ptr]                \n"
-                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       lhu     %[ticket], %[serving_now_ptr]           \n"
                 "       beq     %[ticket], %[my_ticket], 2b             \n"
                 "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
                 "       b       4b                                      \n"
@@ -90,36 +90,33 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
                 "       .previous                                       \n"
                 "       .set pop                                        \n"
                 : [ticket_ptr] "+m" (lock->lock),
+                  [serving_now_ptr] "+m" (lock->h.serving_now),
                   [ticket] "=&r" (tmp),
-                  [my_ticket] "=&r" (my_ticket));
+                  [my_ticket] "=&r" (my_ticket)
+                : [inc] "r" (inc));
         } else {
                 __asm__ __volatile__ (
                 "       .set push               # arch_spin_lock        \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
-                "       ll      %[ticket], %[ticket_ptr]                \n"
-                "1:     addiu   %[my_ticket], %[ticket], 0x4000         \n"
+                "1:     ll      %[ticket], %[ticket_ptr]                \n"
+                "       addu    %[my_ticket], %[ticket], %[inc]         \n"
                 "       sc      %[my_ticket], %[ticket_ptr]             \n"
-                "       beqz    %[my_ticket], 3f                        \n"
-                "        nop                                            \n"
-                "       srl     %[my_ticket], %[ticket], 14             \n"
-                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
-                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       beqz    %[my_ticket], 1b                        \n"
+                "        srl    %[my_ticket], %[ticket], 16             \n"
+                "       andi    %[ticket], %[ticket], 0xffff            \n"
+                "       andi    %[my_ticket], %[my_ticket], 0xffff      \n"
                 "       bne     %[ticket], %[my_ticket], 4f             \n"
                 "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
                 "2:                                                     \n"
                 "       .subsection 2                                   \n"
-                "3:     b       1b                                      \n"
-                "        ll     %[ticket], %[ticket_ptr]                \n"
-                "                                                       \n"
                 "4:     andi    %[ticket], %[ticket], 0x1fff            \n"
                 "       sll     %[ticket], 5                            \n"
                 "                                                       \n"
                 "6:     bnez    %[ticket], 6b                           \n"
                 "        subu   %[ticket], 1                            \n"
                 "                                                       \n"
-                "       lw      %[ticket], %[ticket_ptr]                \n"
-                "       andi    %[ticket], %[ticket], 0x1fff            \n"
+                "       lhu     %[ticket], %[serving_now_ptr]           \n"
                 "       beq     %[ticket], %[my_ticket], 2b             \n"
                 "        subu   %[ticket], %[my_ticket], %[ticket]      \n"
                 "       b       4b                                      \n"
@@ -127,8 +124,10 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
                 "       .previous                                       \n"
                 "       .set pop                                        \n"
                 : [ticket_ptr] "+m" (lock->lock),
+                  [serving_now_ptr] "+m" (lock->h.serving_now),
                   [ticket] "=&r" (tmp),
-                  [my_ticket] "=&r" (my_ticket));
+                  [my_ticket] "=&r" (my_ticket)
+                : [inc] "r" (inc));
         }
 
         smp_llsc_mb();
@@ -136,47 +135,16 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
 
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
-        int tmp;
-
-        smp_llsc_mb();
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__ (
-                "                               # arch_spin_unlock      \n"
-                "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       addiu   %[ticket], %[ticket], 1                 \n"
-                "       ori     %[ticket], %[ticket], 0x2000            \n"
-                "       xori    %[ticket], %[ticket], 0x2000            \n"
-                "       sc      %[ticket], %[ticket_ptr]                \n"
-                "       beqzl   %[ticket], 1b                           \n"
-                : [ticket_ptr] "+m" (lock->lock),
-                  [ticket] "=&r" (tmp));
-        } else {
-                __asm__ __volatile__ (
-                "       .set push               # arch_spin_unlock      \n"
-                "       .set noreorder                                  \n"
-                "                                                       \n"
-                "       ll      %[ticket], %[ticket_ptr]                \n"
-                "1:     addiu   %[ticket], %[ticket], 1                 \n"
-                "       ori     %[ticket], %[ticket], 0x2000            \n"
-                "       xori    %[ticket], %[ticket], 0x2000            \n"
-                "       sc      %[ticket], %[ticket_ptr]                \n"
-                "       beqz    %[ticket], 2f                           \n"
-                "        nop                                            \n"
-                "                                                       \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        ll     %[ticket], %[ticket_ptr]                \n"
-                "       .previous                                       \n"
-                "       .set pop                                        \n"
-                : [ticket_ptr] "+m" (lock->lock),
-                  [ticket] "=&r" (tmp));
-        }
+        unsigned int serving_now = lock->h.serving_now + 1;
+        wmb();
+        lock->h.serving_now = (u16)serving_now;
+        nudge_writes();
 }
 
 static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
 {
         int tmp, tmp2, tmp3;
+        int inc = 0x10000;
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__ (
@@ -184,11 +152,11 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
                 "       .set noreorder                                  \n"
                 "                                                       \n"
                 "1:     ll      %[ticket], %[ticket_ptr]                \n"
-                "       srl     %[my_ticket], %[ticket], 14             \n"
-                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
-                "       andi    %[now_serving], %[ticket], 0x1fff       \n"
+                "       srl     %[my_ticket], %[ticket], 16             \n"
+                "       andi    %[my_ticket], %[my_ticket], 0xffff      \n"
+                "       andi    %[now_serving], %[ticket], 0xffff       \n"
                 "       bne     %[my_ticket], %[now_serving], 3f        \n"
-                "        addiu  %[ticket], %[ticket], 0x4000            \n"
+                "        addu   %[ticket], %[ticket], %[inc]            \n"
                 "       sc      %[ticket], %[ticket_ptr]                \n"
                 "       beqzl   %[ticket], 1b                           \n"
                 "        li     %[ticket], 1                            \n"
@@ -201,33 +169,33 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
                 : [ticket_ptr] "+m" (lock->lock),
                   [ticket] "=&r" (tmp),
                   [my_ticket] "=&r" (tmp2),
-                  [now_serving] "=&r" (tmp3));
+                  [now_serving] "=&r" (tmp3)
+                : [inc] "r" (inc));
         } else {
                 __asm__ __volatile__ (
                 "       .set push               # arch_spin_trylock     \n"
                 "       .set noreorder                                  \n"
                 "                                                       \n"
-                "       ll      %[ticket], %[ticket_ptr]                \n"
-                "1:     srl     %[my_ticket], %[ticket], 14             \n"
-                "       andi    %[my_ticket], %[my_ticket], 0x1fff      \n"
-                "       andi    %[now_serving], %[ticket], 0x1fff       \n"
+                "1:     ll      %[ticket], %[ticket_ptr]                \n"
+                "       srl     %[my_ticket], %[ticket], 16             \n"
+                "       andi    %[my_ticket], %[my_ticket], 0xffff      \n"
+                "       andi    %[now_serving], %[ticket], 0xffff       \n"
                 "       bne     %[my_ticket], %[now_serving], 3f        \n"
-                "        addiu  %[ticket], %[ticket], 0x4000            \n"
+                "        addu   %[ticket], %[ticket], %[inc]            \n"
                 "       sc      %[ticket], %[ticket_ptr]                \n"
-                "       beqz    %[ticket], 4f                           \n"
+                "       beqz    %[ticket], 1b                           \n"
                 "        li     %[ticket], 1                            \n"
                 "2:                                                     \n"
                 "       .subsection 2                                   \n"
                 "3:     b       2b                                      \n"
                 "        li     %[ticket], 0                            \n"
-                "4:     b       1b                                      \n"
-                "        ll     %[ticket], %[ticket_ptr]                \n"
                 "       .previous                                       \n"
                 "       .set pop                                        \n"
                 : [ticket_ptr] "+m" (lock->lock),
                   [ticket] "=&r" (tmp),
                   [my_ticket] "=&r" (tmp2),
-                  [now_serving] "=&r" (tmp3));
+                  [now_serving] "=&r" (tmp3)
+                : [inc] "r" (inc));
         }
 
         smp_llsc_mb();
@@ -305,7 +273,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
 {
         unsigned int tmp;
 
-        smp_llsc_mb();
+        smp_mb__before_llsc();
 
         if (R10000_LLSC_WAR) {
                 __asm__ __volatile__(
diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index ee197c2f9c98..c52f36013a9d 100644
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -5,16 +5,28 @@
 # error "please don't include this file directly"
 #endif
 
-typedef struct {
+#include <linux/types.h>
+
+#include <asm/byteorder.h>
+
+typedef union {
         /*
-         * bits  0..13: serving_now
-         * bits 14    : junk data
-         * bits 15..28: ticket
+         * bits  0..15 : serving_now
+         * bits 16..31 : ticket
          */
-        unsigned int lock;
+        u32 lock;
+        struct {
+#ifdef __BIG_ENDIAN
+                u16 ticket;
+                u16 serving_now;
+#else
+                u16 serving_now;
+                u16 ticket;
+#endif
+        } h;
 } arch_spinlock_t;
 
-#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { .lock = 0 }
 
 typedef struct {
         volatile unsigned int lock;
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
index 83b5509e09e8..bb937ccfba1e 100644
--- a/arch/mips/include/asm/system.h
+++ b/arch/mips/include/asm/system.h
@@ -95,6 +95,8 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
 {
         __u32 retval;
 
+        smp_mb__before_llsc();
+
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long dummy;
 
@@ -147,6 +149,8 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
 {
         __u64 retval;
 
+        smp_mb__before_llsc();
+
         if (kernel_uses_llsc && R10000_LLSC_WAR) {
                 unsigned long dummy;
 
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 827dc22be2ea..64887d3c7ec3 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -42,7 +42,6 @@ struct txx9_board_vec {
 };
 extern struct txx9_board_vec *txx9_board_vec;
 extern int (*txx9_irq_dispatch)(int pending);
-char *prom_getcmdline(void);
 const char *prom_getenv(const char *name);
 void txx9_wdt_init(unsigned long base);
 void txx9_wdt_now(unsigned long base);
diff --git a/arch/mips/mm/uasm.h b/arch/mips/include/asm/uasm.h
index 3d153edaa51e..b99bd07e199b 100644
--- a/arch/mips/mm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -92,9 +92,11 @@ Ip_u2s3u1(_sd);
 Ip_u2u1u3(_sll);
 Ip_u2u1u3(_sra);
 Ip_u2u1u3(_srl);
+Ip_u2u1u3(_rotr);
 Ip_u3u1u2(_subu);
 Ip_u2s3u1(_sw);
 Ip_0(_tlbp);
+Ip_0(_tlbr);
 Ip_0(_tlbwi);
 Ip_0(_tlbwr);
 Ip_u3u1u2(_xor);
@@ -129,6 +131,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh)
 # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh)
 # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh)
 # define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd)
 # define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd)
 # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val)
@@ -142,6 +145,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \
 # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh)
 # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh)
 # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh)
+# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh)
 # define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd)
 # define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd)
 # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val)
diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h
index 8a4b20e88b81..9bc07b9f30fb 100644
--- a/arch/mips/include/asm/ucontext.h
+++ b/arch/mips/include/asm/ucontext.h
@@ -1,21 +1 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Low level exception handling
- *
- * Copyright (C) 1998, 1999 by Ralf Baechle
- */
-#ifndef _ASM_UCONTEXT_H
-#define _ASM_UCONTEXT_H
-
-struct ucontext {
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        stack_t           uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
-
-#endif /* _ASM_UCONTEXT_H */
+#include <asm-generic/ucontext.h>
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 7bd32d04c2cc..ee18028efe92 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -20,17 +20,17 @@
 #include <asm/jazz.h>
 #include <asm/pgtable.h>
 
-static DEFINE_SPINLOCK(r4030_lock);
+static DEFINE_RAW_SPINLOCK(r4030_lock);
 
 static void enable_r4030_irq(unsigned int irq)
 {
         unsigned int mask = 1 << (irq - JAZZ_IRQ_START);
         unsigned long flags;
 
-        spin_lock_irqsave(&r4030_lock, flags);
+        raw_spin_lock_irqsave(&r4030_lock, flags);
         mask |= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
         r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
-        spin_unlock_irqrestore(&r4030_lock, flags);
+        raw_spin_unlock_irqrestore(&r4030_lock, flags);
 }
 
 void disable_r4030_irq(unsigned int irq)
@@ -38,10 +38,10 @@ void disable_r4030_irq(unsigned int irq)
         unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START));
         unsigned long flags;
 
-        spin_lock_irqsave(&r4030_lock, flags);
+        raw_spin_lock_irqsave(&r4030_lock, flags);
         mask &= r4030_read_reg16(JAZZ_IO_IRQ_ENABLE);
         r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, mask);
-        spin_unlock_irqrestore(&r4030_lock, flags);
+        raw_spin_unlock_irqrestore(&r4030_lock, flags);
 }
 
 static struct irq_chip r4030_irq_type = {
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 9326af5186fe..ef20957ca14b 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -93,6 +93,7 @@ obj-$(CONFIG_GPIO_TXX9)		+= gpio_txx9.o
 
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_EARLY_PRINTK)      += early_printk.o
+obj-$(CONFIG_SPINLOCK_TEST)     += spinlock_test.o
 
 CFLAGS_cpu-bugs64.o     = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
 
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 2c1e1d02338b..ca6c83218caa 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -188,11 +188,15 @@ void output_mm_defines(void)
         DEFINE(_PTE_T_SIZE, sizeof(pte_t));
         BLANK();
         DEFINE(_PGD_T_LOG2, PGD_T_LOG2);
+#ifndef __PAGETABLE_PMD_FOLDED
         DEFINE(_PMD_T_LOG2, PMD_T_LOG2);
+#endif
         DEFINE(_PTE_T_LOG2, PTE_T_LOG2);
         BLANK();
         DEFINE(_PGD_ORDER, PGD_ORDER);
+#ifndef __PAGETABLE_PMD_FOLDED
         DEFINE(_PMD_ORDER, PMD_ORDER);
+#endif
         DEFINE(_PTE_ORDER, PTE_ORDER);
         BLANK();
         DEFINE(_PMD_SHIFT, PMD_SHIFT);
diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index f5d265eb6eae..392ef3756c56 100644
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -25,7 +25,7 @@
 #include <asm/gt64120.h>
 #include <asm/time.h>
 
-static DEFINE_SPINLOCK(gt641xx_timer_lock);
+static DEFINE_RAW_SPINLOCK(gt641xx_timer_lock);
 static unsigned int gt641xx_base_clock;
 
 void gt641xx_set_base_clock(unsigned int clock)
@@ -49,7 +49,7 @@ static int gt641xx_timer0_set_next_event(unsigned long delta,
 {
         u32 ctrl;
 
-        spin_lock(&gt641xx_timer_lock);
+        raw_spin_lock(&gt641xx_timer_lock);
 
         ctrl = GT_READ(GT_TC_CONTROL_OFS);
         ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
@@ -58,7 +58,7 @@ static int gt641xx_timer0_set_next_event(unsigned long delta,
         GT_WRITE(GT_TC0_OFS, delta);
         GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
 
-        spin_unlock(&gt641xx_timer_lock);
+        raw_spin_unlock(&gt641xx_timer_lock);
 
         return 0;
 }
@@ -68,7 +68,7 @@ static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
 {
         u32 ctrl;
 
-        spin_lock(&gt641xx_timer_lock);
+        raw_spin_lock(&gt641xx_timer_lock);
 
         ctrl = GT_READ(GT_TC_CONTROL_OFS);
         ctrl &= ~(GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
@@ -86,7 +86,7 @@ static void gt641xx_timer0_set_mode(enum clock_event_mode mode,
 
         GT_WRITE(GT_TC_CONTROL_OFS, ctrl);
 
-        spin_unlock(&gt641xx_timer_lock);
+        raw_spin_unlock(&gt641xx_timer_lock);
 }
 
 static void gt641xx_timer0_event_handler(struct clock_event_device *dev)
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 758ad426c57f..be5bb16be4e0 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -162,6 +162,7 @@ void __init check_wait(void)
         case CPU_BCM6348:
         case CPU_BCM6358:
         case CPU_CAVIUM_OCTEON:
+        case CPU_CAVIUM_OCTEON_PLUS:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -700,6 +701,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
         return config3 & MIPS_CONF_M;
 }
 
+static inline unsigned int decode_config4(struct cpuinfo_mips *c)
+{
+        unsigned int config4;
+
+        config4 = read_c0_config4();
+
+        if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
+            && cpu_has_tlb)
+                c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
+
+        return config4 & MIPS_CONF_M;
+}
+
 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 {
         int ok;
@@ -718,6 +732,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
                 ok = decode_config2(c);
         if (ok)
                 ok = decode_config3(c);
+        if (ok)
+                ok = decode_config4(c);
 
         mips_probe_watch_registers(c);
 }
@@ -731,9 +747,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 __cpu_name[cpu] = "MIPS 4Kc";
                 break;
         case PRID_IMP_4KEC:
-                c->cputype = CPU_4KEC;
-                __cpu_name[cpu] = "MIPS 4KEc";
-                break;
         case PRID_IMP_4KECR2:
                 c->cputype = CPU_4KEC;
                 __cpu_name[cpu] = "MIPS 4KEc";
@@ -899,12 +912,18 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
         case PRID_IMP_CAVIUM_CN38XX:
         case PRID_IMP_CAVIUM_CN31XX:
         case PRID_IMP_CAVIUM_CN30XX:
+                c->cputype = CPU_CAVIUM_OCTEON;
+                __cpu_name[cpu] = "Cavium Octeon";
+                goto platform;
         case PRID_IMP_CAVIUM_CN58XX:
         case PRID_IMP_CAVIUM_CN56XX:
         case PRID_IMP_CAVIUM_CN50XX:
         case PRID_IMP_CAVIUM_CN52XX:
-                c->cputype = CPU_CAVIUM_OCTEON;
-                __cpu_name[cpu] = "Cavium Octeon";
+                c->cputype = CPU_CAVIUM_OCTEON_PLUS;
+                __cpu_name[cpu] = "Cavium Octeon+";
+platform:
+                if (cpu == 0)
+                        __elf_platform = "octeon";
                 break;
         default:
                 printk(KERN_INFO "Unknown Octeon chip!\n");
@@ -914,6 +933,7 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 }
 
 const char *__cpu_name[NR_CPUS];
+const char *__elf_platform;
 
 __cpuinit void cpu_probe(void)
 {
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 68b067040d8b..e9e64e0ff7aa 100644
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2007-2008 Steven Rostedt <srostedt@redhat.com>
  * Copyright (C) 2009 DSLab, Lanzhou University, China
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * Thanks goes to Steven Rostedt for writing the original x86 version.
  */
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 01c0885a8061..27799113332c 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -29,7 +29,7 @@
  */
 
 static int i8259A_auto_eoi = -1;
-DEFINE_SPINLOCK(i8259A_lock);
+DEFINE_RAW_SPINLOCK(i8259A_lock);
 static void disable_8259A_irq(unsigned int irq);
 static void enable_8259A_irq(unsigned int irq);
 static void mask_and_ack_8259A(unsigned int irq);
@@ -65,13 +65,13 @@ static void disable_8259A_irq(unsigned int irq)
 
         irq -= I8259A_IRQ_BASE;
         mask = 1 << irq;
-        spin_lock_irqsave(&i8259A_lock, flags);
+        raw_spin_lock_irqsave(&i8259A_lock, flags);
         cached_irq_mask |= mask;
         if (irq & 8)
                 outb(cached_slave_mask, PIC_SLAVE_IMR);
         else
                 outb(cached_master_mask, PIC_MASTER_IMR);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 }
 
 static void enable_8259A_irq(unsigned int irq)
@@ -81,13 +81,13 @@ static void enable_8259A_irq(unsigned int irq)
 
         irq -= I8259A_IRQ_BASE;
         mask = ~(1 << irq);
-        spin_lock_irqsave(&i8259A_lock, flags);
+        raw_spin_lock_irqsave(&i8259A_lock, flags);
         cached_irq_mask &= mask;
         if (irq & 8)
                 outb(cached_slave_mask, PIC_SLAVE_IMR);
         else
                 outb(cached_master_mask, PIC_MASTER_IMR);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 }
 
 int i8259A_irq_pending(unsigned int irq)
@@ -98,12 +98,12 @@ int i8259A_irq_pending(unsigned int irq)
 
         irq -= I8259A_IRQ_BASE;
         mask = 1 << irq;
-        spin_lock_irqsave(&i8259A_lock, flags);
+        raw_spin_lock_irqsave(&i8259A_lock, flags);
         if (irq < 8)
                 ret = inb(PIC_MASTER_CMD) & mask;
         else
                 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 
         return ret;
 }
@@ -151,7 +151,7 @@ static void mask_and_ack_8259A(unsigned int irq)
 
         irq -= I8259A_IRQ_BASE;
         irqmask = 1 << irq;
-        spin_lock_irqsave(&i8259A_lock, flags);
+        raw_spin_lock_irqsave(&i8259A_lock, flags);
         /*
          * Lightweight spurious IRQ detection. We do not want
          * to overdo spurious IRQ handling - it's usually a sign
@@ -183,7 +183,7 @@ handle_real_irq:
                 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
         }
         smtc_im_ack_irq(irq);
-        spin_unlock_irqrestore(&i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
         return;
 
 spurious_8259A_irq:
@@ -264,7 +264,7 @@ static void init_8259A(int auto_eoi)
 
         i8259A_auto_eoi = auto_eoi;
 
-        spin_lock_irqsave(&i8259A_lock, flags);
+        raw_spin_lock_irqsave(&i8259A_lock, flags);
 
         outb(0xff, PIC_MASTER_IMR);     /* mask all of 8259A-1 */
         outb(0xff, PIC_SLAVE_IMR);      /* mask all of 8259A-2 */
@@ -298,7 +298,7 @@ static void init_8259A(int auto_eoi)
         outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
         outb(cached_slave_mask, PIC_SLAVE_IMR);   /* restore slave IRQ mask */
 
-        spin_unlock_irqrestore(&i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
 }
 
 /*
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index ebcc5f7ad9c2..42ef81461bfc 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -27,18 +27,18 @@
 
 #define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
 
-static DEFINE_SPINLOCK(gt641xx_irq_lock);
+static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
 
 static void ack_gt641xx_irq(unsigned int irq)
 {
         unsigned long flags;
         u32 cause;
 
-        spin_lock_irqsave(&gt641xx_irq_lock, flags);
+        raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
         cause = GT_READ(GT_INTRCAUSE_OFS);
         cause &= ~GT641XX_IRQ_TO_BIT(irq);
         GT_WRITE(GT_INTRCAUSE_OFS, cause);
-        spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
 }
 
 static void mask_gt641xx_irq(unsigned int irq)
@@ -46,11 +46,11 @@ static void mask_gt641xx_irq(unsigned int irq)
         unsigned long flags;
         u32 mask;
 
-        spin_lock_irqsave(&gt641xx_irq_lock, flags);
+        raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
         mask = GT_READ(GT_INTRMASK_OFS);
         mask &= ~GT641XX_IRQ_TO_BIT(irq);
         GT_WRITE(GT_INTRMASK_OFS, mask);
-        spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
 }
 
 static void mask_ack_gt641xx_irq(unsigned int irq)
@@ -58,7 +58,7 @@ static void mask_ack_gt641xx_irq(unsigned int irq)
         unsigned long flags;
         u32 cause, mask;
 
-        spin_lock_irqsave(&gt641xx_irq_lock, flags);
+        raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
         mask = GT_READ(GT_INTRMASK_OFS);
         mask &= ~GT641XX_IRQ_TO_BIT(irq);
         GT_WRITE(GT_INTRMASK_OFS, mask);
@@ -66,7 +66,7 @@ static void mask_ack_gt641xx_irq(unsigned int irq)
         cause = GT_READ(GT_INTRCAUSE_OFS);
         cause &= ~GT641XX_IRQ_TO_BIT(irq);
         GT_WRITE(GT_INTRCAUSE_OFS, cause);
-        spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
 }
 
 static void unmask_gt641xx_irq(unsigned int irq)
@@ -74,11 +74,11 @@ static void unmask_gt641xx_irq(unsigned int irq)
         unsigned long flags;
         u32 mask;
 
-        spin_lock_irqsave(&gt641xx_irq_lock, flags);
+        raw_spin_lock_irqsave(&gt641xx_irq_lock, flags);
         mask = GT_READ(GT_INTRMASK_OFS);
         mask |= GT641XX_IRQ_TO_BIT(irq);
         GT_WRITE(GT_INTRMASK_OFS, mask);
-        spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
 }
 
 static struct irq_chip gt641xx_irq_chip = {
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index f042563c924f..bde79ef602e6 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -9,7 +9,6 @@
 #include <linux/mm.h>
 #include <linux/errno.h>
 #include <linux/file.h>
-#include <linux/smp_lock.h>
 #include <linux/highuid.h>
 #include <linux/resource.h>
 #include <linux/highmem.h>
diff --git a/arch/mips/kernel/mcount.S b/arch/mips/kernel/mcount.S
index 0a9cfdb271dd..6851fc97a511 100644
--- a/arch/mips/kernel/mcount.S
+++ b/arch/mips/kernel/mcount.S
@@ -6,7 +6,7 @@
  * more details.
  *
  * Copyright (C) 2009 Lemote Inc. & DSLab, Lanzhou University, China
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  */
 
 #include <asm/regdef.h>
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 3952b8323efa..dd18b26a358a 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -500,4 +500,3 @@ done_restore:
          nop
         END(octeon_mult_restore)
         .set pop
-
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index 364f066cb497..dcaed1bbbfe5 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -28,7 +28,6 @@
 #include <linux/vmalloc.h>
 #include <linux/elf.h>
 #include <linux/seq_file.h>
-#include <linux/smp_lock.h>
 #include <linux/syscalls.h>
 #include <linux/moduleloader.h>
 #include <linux/interrupt.h>
diff --git a/arch/mips/kernel/spinlock_test.c b/arch/mips/kernel/spinlock_test.c
new file mode 100644
index 000000000000..da61134dfc53
--- /dev/null
+++ b/arch/mips/kernel/spinlock_test.c
@@ -0,0 +1,141 @@
+#include <linux/init.h>
+#include <linux/kthread.h>
+#include <linux/hrtimer.h>
+#include <linux/fs.h>
+#include <linux/debugfs.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+
+static int ss_get(void *data, u64 *val)
+{
+        ktime_t start, finish;
+        int loops;
+        int cont;
+        DEFINE_RAW_SPINLOCK(ss_spin);
+
+        loops = 1000000;
+        cont = 1;
+
+        start = ktime_get();
+
+        while (cont) {
+                raw_spin_lock(&ss_spin);
+                loops--;
+                if (loops == 0)
+                        cont = 0;
+                raw_spin_unlock(&ss_spin);
+        }
+
+        finish = ktime_get();
+
+        *val = ktime_us_delta(finish, start);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fops_ss, ss_get, NULL, "%llu\n");
+
+
+
+struct spin_multi_state {
+        raw_spinlock_t lock;
+        atomic_t start_wait;
+        atomic_t enter_wait;
+        atomic_t exit_wait;
+        int loops;
+};
+
+struct spin_multi_per_thread {
+        struct spin_multi_state *state;
+        ktime_t start;
+};
+
+static int multi_other(void *data)
+{
+        int loops;
+        int cont;
+        struct spin_multi_per_thread *pt = data;
+        struct spin_multi_state *s = pt->state;
+
+        loops = s->loops;
+        cont = 1;
+
+        atomic_dec(&s->enter_wait);
+
+        while (atomic_read(&s->enter_wait))
+                ; /* spin */
+
+        pt->start = ktime_get();
+
+        atomic_dec(&s->start_wait);
+
+        while (atomic_read(&s->start_wait))
+                ; /* spin */
+
+        while (cont) {
+                raw_spin_lock(&s->lock);
+                loops--;
+                if (loops == 0)
+                        cont = 0;
+                raw_spin_unlock(&s->lock);
+        }
+
+        atomic_dec(&s->exit_wait);
+        while (atomic_read(&s->exit_wait))
+                ; /* spin */
+        return 0;
+}
+
+static int multi_get(void *data, u64 *val)
+{
+        ktime_t finish;
+        struct spin_multi_state ms;
+        struct spin_multi_per_thread t1, t2;
+
+        ms.lock = __RAW_SPIN_LOCK_UNLOCKED("multi_get");
+        ms.loops = 1000000;
+
+        atomic_set(&ms.start_wait, 2);
+        atomic_set(&ms.enter_wait, 2);
+        atomic_set(&ms.exit_wait, 2);
+        t1.state = &ms;
+        t2.state = &ms;
+
+        kthread_run(multi_other, &t2, "multi_get");
+
+        multi_other(&t1);
+
+        finish = ktime_get();
+
+        *val = ktime_us_delta(finish, t1.start);
+
+        return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(fops_multi, multi_get, NULL, "%llu\n");
+
+
+extern struct dentry *mips_debugfs_dir;
+static int __init spinlock_test(void)
+{
+        struct dentry *d;
+
+        if (!mips_debugfs_dir)
+                return -ENODEV;
+
+        d = debugfs_create_file("spin_single", S_IRUGO,
+                                mips_debugfs_dir, NULL,
+                                &fops_ss);
+        if (!d)
+                return -ENOMEM;
+
+        d = debugfs_create_file("spin_multi", S_IRUGO,
+                                mips_debugfs_dir, NULL,
+                                &fops_multi);
+        if (!d)
+                return -ENOMEM;
+
+        return 0;
+}
+device_initcall(spinlock_test);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 31b204b26ba0..4e00f9bc23ee 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -50,6 +50,7 @@
 #include <asm/types.h>
 #include <asm/stacktrace.h>
 #include <asm/irq.h>
+#include <asm/uasm.h>
 
 extern void check_wait(void);
 extern asmlinkage void r4k_wait(void);
@@ -1271,21 +1272,25 @@ unsigned long ebase;
 unsigned long exception_handlers[32];
 unsigned long vi_handlers[64];
 
-/*
- * As a side effect of the way this is implemented we're limited
- * to interrupt handlers in the address range from
- * KSEG0 <= x < KSEG0 + 256mb on the Nevada.  Oh well ...
- */
-void *set_except_vector(int n, void *addr)
+void __init *set_except_vector(int n, void *addr)
 {
         unsigned long handler = (unsigned long) addr;
         unsigned long old_handler = exception_handlers[n];
 
         exception_handlers[n] = handler;
         if (n == 0 && cpu_has_divec) {
-                *(u32 *)(ebase + 0x200) = 0x08000000 |
-                                          (0x03ffffff & (handler >> 2));
-                local_flush_icache_range(ebase + 0x200, ebase + 0x204);
+                unsigned long jump_mask = ~((1 << 28) - 1);
+                u32 *buf = (u32 *)(ebase + 0x200);
+                unsigned int k0 = 26;
+                if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
+                        uasm_i_j(&buf, handler & ~jump_mask);
+                        uasm_i_nop(&buf);
+                } else {
+                        UASM_i_LA(&buf, k0, handler);
+                        uasm_i_jr(&buf, k0);
+                        uasm_i_nop(&buf);
+                }
+                local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
         }
         return (void *)old_handler;
 }
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 60477529362e..2bd2151c586a 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -38,7 +38,6 @@
 #include <linux/vmalloc.h>
 #include <linux/elf.h>
 #include <linux/seq_file.h>
-#include <linux/smp_lock.h>
 #include <linux/syscalls.h>
 #include <linux/moduleloader.h>
 #include <linux/interrupt.h>
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
index 91df55371127..2f0757738fdb 100644
--- a/arch/mips/lasat/picvue.h
+++ b/arch/mips/lasat/picvue.h
@@ -42,4 +42,3 @@ void pvc_move(u8 cmd);
 
 void pvc_clear(void);
 void pvc_home(void);
-
diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 7ad47f227477..1a06defc4f7f 100644
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -10,7 +10,7 @@
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -21,12 +21,11 @@
 
 #include <loongson.h>
 
-int prom_argc;
-/* pmon passes arguments in 32bit pointers */
-int *_prom_argv;
-
 void __init prom_init_cmdline(void)
 {
+        int prom_argc;
+        /* pmon passes arguments in 32bit pointers */
+        int *_prom_argv;
         int i;
         long l;
 
diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
index b49485f187e0..b3fd5eab6548 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_acc.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -5,7 +5,7 @@
  * Author : jlliu, liujl@lemote.com
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
index 74f9c59d36af..eaf8b86e3318 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_ehci.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -5,7 +5,7 @@
  * Author : jlliu, liujl@lemote.com
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
index 3f61594b3884..9a96b5664c78 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_ide.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -5,7 +5,7 @@
  * Author : jlliu, liujl@lemote.com
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
index b6f17f538e48..f5c0818831b2 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_isa.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -5,7 +5,7 @@
  * Author : jlliu, liujl@lemote.com
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index 6cb44dbaeec2..8c807c965199 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -5,7 +5,7 @@
  * Author: Yanhua, yanh@lemote.com
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu zhangjin, wuzj@lemote.com
+ * Author: Wu zhangjin, wuzhangjin@gmail.com
  *
  * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
  *
diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
index 8fdb02b6e90f..db5900aadd6b 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_ohci.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -5,7 +5,7 @@
  * Author : jlliu, liujl@lemote.com
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
index e23f3d7d2c1d..6dfeab11af08 100644
--- a/arch/mips/loongson/common/cs5536/cs5536_pci.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -5,7 +5,7 @@
  * Author : jlliu, liujl@lemote.com
  *
  * Copyright (C) 2009 Lemote, Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index 23e7a8f8897f..a71736f00443 100644
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -2,7 +2,7 @@
  *
  *  Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
  *  Copyright (c) 2009 Lemote Inc.
- *  Author: Wu Zhangjin, wuzj@lemote.com
+ *  Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index 196d947d929a..ae4cff97a56c 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -9,8 +9,8 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
@@ -23,13 +23,10 @@
 
 #include <loongson.h>
 
-unsigned long bus_clock, cpu_clock_freq;
+unsigned long cpu_clock_freq;
 EXPORT_SYMBOL(cpu_clock_freq);
 unsigned long memsize, highmemsize;
 
-/* pmon passes arguments in 32bit pointers */
-int *_prom_envp;
-
 #define parse_even_earlier(res, option, p)                              \
 do {                                                                    \
         if (strncmp(option, (char *)p, strlen(option)) == 0)            \
@@ -39,6 +36,10 @@ do {									\
 
 void __init prom_init_env(void)
 {
+        /* pmon passes arguments in 32bit pointers */
+        int *_prom_envp;
+        unsigned long bus_clock;
+        unsigned int processor_id;
         long l;
 
         /* firmware arguments are initialized in head.S */
@@ -55,6 +56,22 @@ void __init prom_init_env(void)
         }
         if (memsize == 0)
                 memsize = 256;
+        if (bus_clock == 0)
+                bus_clock = 66000000;
+        if (cpu_clock_freq == 0) {
+                processor_id = (&current_cpu_data)->processor_id;
+                switch (processor_id & PRID_REV_MASK) {
+                case PRID_REV_LOONGSON2E:
+                        cpu_clock_freq = 533080000;
+                        break;
+                case PRID_REV_LOONGSON2F:
+                        cpu_clock_freq = 797000000;
+                        break;
+                default:
+                        cpu_clock_freq = 100000000;
+                        break;
+                }
+        }
 
         pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n",
                 bus_clock, cpu_clock_freq, memsize, highmemsize);
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index a2abd9355737..19d341591254 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 0ed52b3f5314..853f184b793e 100644
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -1,6 +1,6 @@
 /*
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org>
  *
@@ -35,6 +35,10 @@ const char *get_system_type(void)
         return system_types[mips_machtype];
 }
 
+void __weak __init mach_prom_init_machtype(void)
+{
+}
+
 void __init prom_init_machtype(void)
 {
         char *p, str[MACHTYPE_LEN];
@@ -43,8 +47,10 @@ void __init prom_init_machtype(void)
         mips_machtype = LOONGSON_MACHTYPE;
 
         p = strstr(arcs_cmdline, "machtype=");
-        if (!p)
+        if (!p) {
+                mach_prom_init_machtype();
                 return;
+        }
         p += strlen("machtype=");
         strncpy(str, p, MACHTYPE_LEN);
         p = strstr(str, " ");
diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index ceacd092b446..ec2f7964a0b0 100644
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -16,10 +16,11 @@
 
 void __init prom_init_memory(void)
 {
-    add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+        add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
+
+        add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
+                                20), BOOT_MEM_RESERVED);
 
-    add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize <<
-                            20), BOOT_MEM_RESERVED);
 #ifdef CONFIG_CPU_SUPPORTS_ADDRWINCFG
         {
                 int bit;
diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
index be81777eb94d..ed007a2e0e1f 100644
--- a/arch/mips/loongson/common/platform.c
+++ b/arch/mips/loongson/common/platform.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/pm.c b/arch/mips/loongson/common/pm.c
index b625fec8a4d5..6c1fd9001712 100644
--- a/arch/mips/loongson/common/pm.c
+++ b/arch/mips/loongson/common/pm.c
@@ -2,7 +2,7 @@
  * loongson-specific suspend support
  *
  *  Copyright (C) 2009 Lemote Inc.
- *  Author: Wu Zhangjin <wuzj@lemote.com>
+ *  Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index d57f1719da95..4bd9c18b07a5 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -6,8 +6,8 @@
  *
  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
- * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology
- * Author: Zhangjin Wu, wuzj@lemote.com
+ * Copyright (C) 2009 Lemote, Inc.
+ * Author: Zhangjin Wu, wuzhangjin@gmail.com
  */
 #include <linux/init.h>
 #include <linux/pm.h>
@@ -25,18 +25,26 @@ static void loongson_restart(char *command)
         ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
 }
 
-static void loongson_halt(void)
+static void loongson_poweroff(void)
 {
         mach_prepare_shutdown();
-        while (1)
-                ;
+        unreachable();
+}
+
+static void loongson_halt(void)
+{
+        pr_notice("\n\n** You can safely turn off the power now **\n\n");
+        while (1) {
+                if (cpu_wait)
+                        cpu_wait();
+        }
 }
 
 static int __init mips_reboot_setup(void)
 {
         _machine_restart = loongson_restart;
         _machine_halt = loongson_halt;
-        pm_power_off = loongson_halt;
+        pm_power_off = loongson_poweroff;
 
         return 0;
 }
diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
index 23b66a5f88cb..7580873143c8 100644
--- a/arch/mips/loongson/common/serial.c
+++ b/arch/mips/loongson/common/serial.c
@@ -7,7 +7,7 @@
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Yan hua (yanhua@lemote.com)
- * Author: Wu Zhangjin (wuzj@lemote.com)
+ * Author: Wu Zhangjin (wuzhangjin@gmail.com)
  */
 
 #include <linux/io.h>
diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 35f0b66a94f5..9fdd01f6c56a 100644
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -2,8 +2,8 @@
  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  *  This program is free software; you can redistribute  it and/or modify it
  *  under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
index 78ff66ae749e..d69ea54bc3d1 100644
--- a/arch/mips/loongson/common/uart_base.c
+++ b/arch/mips/loongson/common/uart_base.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index fc16c677d476..bc39ec62c8c2 100644
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -1,8 +1,8 @@
 /* Board-specific reboot/shutdown routines
  * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile
index 4d84b27dc41b..8699a53f0477 100644
--- a/arch/mips/loongson/lemote-2f/Makefile
+++ b/arch/mips/loongson/lemote-2f/Makefile
@@ -2,7 +2,7 @@
 # Makefile for lemote loongson2f family machines
 #
 
-obj-y += irq.o reset.o ec_kb3310b.o
+obj-y += machtype.o irq.o reset.o ec_kb3310b.o
 
 #
 # Suspend Support
diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.c b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
index 4d84111a2cd4..64057244eec5 100644
--- a/arch/mips/loongson/lemote-2f/ec_kb3310b.c
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.c
@@ -75,6 +75,8 @@ int ec_query_seq(unsigned char cmd)
                 udelay(EC_REG_DELAY);
         }
 
+        spin_unlock_irqrestore(&port_access_lock, flags);
+
         if (timeout <= 0) {
                 printk(KERN_ERR "%s: deadable error : timeout...\n", __func__);
                 ret = -EINVAL;
@@ -83,8 +85,6 @@ int ec_query_seq(unsigned char cmd)
                            "(%x/%d)ec issued command %d status : 0x%x\n",
                            timeout, EC_CMD_TIMEOUT - timeout, cmd, status);
 
-        spin_unlock_irqrestore(&port_access_lock, flags);
-
         return ret;
 }
 EXPORT_SYMBOL_GPL(ec_query_seq);
diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
index 77d32f9cf31e..882dfcd42c00 100644
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -38,7 +38,7 @@ int mach_i8259_irq(void)
         irq = -1;
 
         if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
-                spin_lock(&i8259A_lock);
+                raw_spin_lock(&i8259A_lock);
                 isr = inb(PIC_MASTER_CMD) &
                         ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
                 if (!isr)
@@ -56,7 +56,7 @@ int mach_i8259_irq(void)
                         if (~inb(PIC_MASTER_ISR) & 0x80)
                                 irq = -1;
                 }
-                spin_unlock(&i8259A_lock);
+                raw_spin_unlock(&i8259A_lock);
         }
 
         return irq;
diff --git a/arch/mips/loongson/lemote-2f/machtype.c b/arch/mips/loongson/lemote-2f/machtype.c
new file mode 100644
index 000000000000..e860a2705c27
--- /dev/null
+++ b/arch/mips/loongson/lemote-2f/machtype.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2009 Lemote Inc.
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <asm/bootinfo.h>
+
+#include <loongson.h>
+
+void __init mach_prom_init_machtype(void)
+{
+        /* We share the same kernel image file among Lemote 2F family
+         * of machines, and provide the machtype= kernel command line
+         * to users to indicate their machine, this command line will
+         * be passed by the latest PMON automatically. and fortunately,
+         * up to now, we can get the machine type from the PMON_VER=
+         * commandline directly except the NAS machine, In the old
+         * machines, this will help the users a lot.
+         *
+         * If no "machtype=" passed, get machine type from "PMON_VER=".
+         *      PMON_VER=LM8089         Lemote 8.9'' netbook
+         *               LM8101         Lemote 10.1'' netbook
+         *      (The above two netbooks have the same kernel support)
+         *               LM6XXX         Lemote FuLoong(2F) box series
+         *               LM9XXX         Lemote LynLoong PC series
+         */
+        if (strstr(arcs_cmdline, "PMON_VER=LM")) {
+                if (strstr(arcs_cmdline, "PMON_VER=LM8"))
+                        mips_machtype = MACH_LEMOTE_YL2F89;
+                else if (strstr(arcs_cmdline, "PMON_VER=LM6"))
+                        mips_machtype = MACH_LEMOTE_FL2F;
+                else if (strstr(arcs_cmdline, "PMON_VER=LM9"))
+                        mips_machtype = MACH_LEMOTE_LL2F;
+                else
+                        mips_machtype = MACH_LEMOTE_NAS;
+
+                strcat(arcs_cmdline, " machtype=");
+                strcat(arcs_cmdline, get_system_type());
+                strcat(arcs_cmdline, " ");
+        }
+}
diff --git a/arch/mips/loongson/lemote-2f/pm.c b/arch/mips/loongson/lemote-2f/pm.c
index d7af2e616592..cac4d382ea73 100644
--- a/arch/mips/loongson/lemote-2f/pm.c
+++ b/arch/mips/loongson/lemote-2f/pm.c
@@ -2,7 +2,7 @@
  *  Lemote loongson2f family machines' specific suspend support
  *
  *  Copyright (C) 2009 Lemote Inc.
- *  Author: Wu Zhangjin <wuzj@lemote.com>
+ *  Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
index 51d1a60d5349..36020a07e180 100644
--- a/arch/mips/loongson/lemote-2f/reset.c
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -3,7 +3,7 @@
  * Copyright (c) 2009 Philippe Vachon <philippe@cowpig.ca>
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin, wuzj@lemote.com
+ * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * This program is free software; you can redistribute  it and/or modify it
  * under  the terms of  the GNU General  Public License as published by the
diff --git a/arch/mips/math-emu/ieee754d.c b/arch/mips/math-emu/ieee754d.c
index 7e900f30987e..a0325337b76c 100644
--- a/arch/mips/math-emu/ieee754d.c
+++ b/arch/mips/math-emu/ieee754d.c
@@ -135,4 +135,3 @@ ieee754sp ieee754sp_dump(char *m, ieee754sp x)
         printk("\n");
         return x;
 }
-
diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c
index 6d2d89f32472..2f22fd7fd784 100644
--- a/arch/mips/math-emu/ieee754dp.c
+++ b/arch/mips/math-emu/ieee754dp.c
@@ -148,7 +148,6 @@ ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
 
                         switch(ieee754_csr.rm) {
                         case IEEE754_RN:
-                                return ieee754dp_zero(sn);
                         case IEEE754_RZ:
                                 return ieee754dp_zero(sn);
                         case IEEE754_RU:    /* toward +Infinity */
diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
index 463534045ab6..a19b72185ab9 100644
--- a/arch/mips/math-emu/ieee754sp.c
+++ b/arch/mips/math-emu/ieee754sp.c
@@ -149,7 +149,6 @@ ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
 
                         switch(ieee754_csr.rm) {
                         case IEEE754_RN:
-                                return ieee754sp_zero(sn);
                         case IEEE754_RZ:
                                 return ieee754sp_zero(sn);
                         case IEEE754_RU:      /* toward +Infinity */
diff --git a/arch/mips/math-emu/ieee754xcpt.c b/arch/mips/math-emu/ieee754xcpt.c
index 7d8ef8965067..e02423a0ae23 100644
--- a/arch/mips/math-emu/ieee754xcpt.c
+++ b/arch/mips/math-emu/ieee754xcpt.c
@@ -46,4 +46,3 @@ void ieee754_xcpt(struct ieee754xctx *xcp)
         printk(KERN_DEBUG "floating point exception in \"%s\", type=%s\n",
                 xcp->op, rtnames[xcp->rt]);
 }
-
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index e06f1af760a7..0f9c488044d1 100644
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void)
 
         switch (c->cputype) {
         case CPU_CAVIUM_OCTEON:
+        case CPU_CAVIUM_OCTEON_PLUS:
                 config1 = read_c0_config1();
                 c->icache.linesz = 2 << ((config1 >> 19) & 7);
                 c->icache.sets = 64 << ((config1 >> 22) & 7);
@@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void)
                         c->icache.sets * c->icache.ways * c->icache.linesz;
                 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
                 c->dcache.linesz = 128;
-                if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
-                        c->dcache.sets = 1; /* CN3XXX has one Dcache set */
-                else
+                if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
                         c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
+                else
+                        c->dcache.sets = 1; /* CN3XXX has one Dcache set */
                 c->dcache.ways = 64;
                 dcache_size =
                         c->dcache.sets * c->dcache.ways * c->dcache.linesz;
@@ -305,4 +306,3 @@ asmlinkage void cache_parity_error_octeon_non_recoverable(void)
 {
         cache_parity_error_octeon(1);
 }
-
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index e716cafc346d..be8627bc5b02 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -137,22 +137,43 @@ EXPORT_SYMBOL_GPL(_page_cachable_default);
 
 static inline void setup_protection_map(void)
 {
-        protection_map[0] = PAGE_NONE;
-        protection_map[1] = PAGE_READONLY;
-        protection_map[2] = PAGE_COPY;
-        protection_map[3] = PAGE_COPY;
-        protection_map[4] = PAGE_READONLY;
-        protection_map[5] = PAGE_READONLY;
-        protection_map[6] = PAGE_COPY;
-        protection_map[7] = PAGE_COPY;
-        protection_map[8] = PAGE_NONE;
-        protection_map[9] = PAGE_READONLY;
-        protection_map[10] = PAGE_SHARED;
-        protection_map[11] = PAGE_SHARED;
-        protection_map[12] = PAGE_READONLY;
-        protection_map[13] = PAGE_READONLY;
-        protection_map[14] = PAGE_SHARED;
-        protection_map[15] = PAGE_SHARED;
+        if (kernel_uses_smartmips_rixi) {
+                protection_map[0]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
+                protection_map[1]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
+                protection_map[2]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
+                protection_map[3]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
+                protection_map[4]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ);
+                protection_map[5]  = __pgprot(_page_cachable_default | _PAGE_PRESENT);
+                protection_map[6]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ);
+                protection_map[7]  = __pgprot(_page_cachable_default | _PAGE_PRESENT);
+
+                protection_map[8]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ);
+                protection_map[9]  = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC);
+                protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ);
+                protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE);
+                protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ);
+                protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT);
+                protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE  | _PAGE_NO_READ);
+                protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE);
+
+        } else {
+                protection_map[0] = PAGE_NONE;
+                protection_map[1] = PAGE_READONLY;
+                protection_map[2] = PAGE_COPY;
+                protection_map[3] = PAGE_COPY;
+                protection_map[4] = PAGE_READONLY;
+                protection_map[5] = PAGE_READONLY;
+                protection_map[6] = PAGE_COPY;
+                protection_map[7] = PAGE_COPY;
+                protection_map[8] = PAGE_NONE;
+                protection_map[9] = PAGE_READONLY;
+                protection_map[10] = PAGE_SHARED;
+                protection_map[11] = PAGE_SHARED;
+                protection_map[12] = PAGE_READONLY;
+                protection_map[13] = PAGE_READONLY;
+                protection_map[14] = PAGE_SHARED;
+                protection_map[15] = PAGE_SHARED;
+        }
 }
 
 void __cpuinit cpu_cache_init(void)
diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index e97a7a2fb2c0..b78f7d913ca4 100644
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -99,8 +99,31 @@ good_area:
                 if (!(vma->vm_flags & VM_WRITE))
                         goto bad_area;
         } else {
-                if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
-                        goto bad_area;
+                if (kernel_uses_smartmips_rixi) {
+                        if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) {
+#if 0
+                                pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n",
+                                          raw_smp_processor_id(),
+                                          current->comm, current->pid,
+                                          field, address, write,
+                                          field, regs->cp0_epc);
+#endif
+                                goto bad_area;
+                        }
+                        if (!(vma->vm_flags & VM_READ)) {
+#if 0
+                                pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n",
+                                          raw_smp_processor_id(),
+                                          current->comm, current->pid,
+                                          field, address, write,
+                                          field, regs->cp0_epc);
+#endif
+                                goto bad_area;
+                        }
+                } else {
+                        if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))
+                                goto bad_area;
+                }
         }
 
         /*
diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c
index e274fda329f4..127d732474bf 100644
--- a/arch/mips/mm/highmem.c
+++ b/arch/mips/mm/highmem.c
@@ -1,5 +1,6 @@
 #include <linux/module.h>
 #include <linux/highmem.h>
+#include <linux/sched.h>
 #include <linux/smp.h>
 #include <asm/fixmap.h>
 #include <asm/tlbflush.h>
diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c
index 8c2834f5919d..cd0660c51f28 100644
--- a/arch/mips/mm/hugetlbpage.c
+++ b/arch/mips/mm/hugetlbpage.c
@@ -97,4 +97,3 @@ follow_huge_pmd(struct mm_struct *mm, unsigned long address,
                 page += ((address & ~HPAGE_MASK) >> PAGE_SHIFT);
         return page;
 }
-
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 1651942f7feb..12539af38a99 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -143,7 +143,7 @@ void *kmap_coherent(struct page *page, unsigned long addr)
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
         entrylo = pte.pte_high;
 #else
-        entrylo = pte_val(pte) >> 6;
+        entrylo = pte_to_entrylo(pte_val(pte));
 #endif
 
         ENTER_CRITICAL(flags);
@@ -298,7 +298,7 @@ void __init fixrange_init(unsigned long start, unsigned long end,
 }
 
 #ifndef CONFIG_NEED_MULTIPLE_NODES
-static int __init page_is_ram(unsigned long pagenr)
+int page_is_ram(unsigned long pagenr)
 {
         int i;
 
@@ -477,7 +477,7 @@ unsigned long pgd_current[NR_CPUS];
  * will officially be retired.
  */
 pgd_t swapper_pg_dir[_PTRS_PER_PGD] __page_aligned(_PGD_ORDER);
-#ifdef CONFIG_64BIT
+#ifndef __PAGETABLE_PMD_FOLDED
 pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned(PMD_ORDER);
 #endif
 pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned(PTE_ORDER);
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index f5c73754d664..36272f7d3744 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -35,7 +35,7 @@
 #include <asm/sibyte/sb1250_dma.h>
 #endif
 
-#include "uasm.h"
+#include <asm/uasm.h>
 
 /* Registers used in the assembled routines. */
 #define ZERO 0
diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index 1121019fa456..78eaa4f0b0ec 100644
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -15,23 +15,31 @@
 void pgd_init(unsigned long page)
 {
         unsigned long *p, *end;
+        unsigned long entry;
+
+#ifdef __PAGETABLE_PMD_FOLDED
+        entry = (unsigned long)invalid_pte_table;
+#else
+        entry = (unsigned long)invalid_pmd_table;
+#endif
 
         p = (unsigned long *) page;
         end = p + PTRS_PER_PGD;
 
         while (p < end) {
-                p[0] = (unsigned long) invalid_pmd_table;
-                p[1] = (unsigned long) invalid_pmd_table;
-                p[2] = (unsigned long) invalid_pmd_table;
-                p[3] = (unsigned long) invalid_pmd_table;
-                p[4] = (unsigned long) invalid_pmd_table;
-                p[5] = (unsigned long) invalid_pmd_table;
-                p[6] = (unsigned long) invalid_pmd_table;
-                p[7] = (unsigned long) invalid_pmd_table;
+                p[0] = entry;
+                p[1] = entry;
+                p[2] = entry;
+                p[3] = entry;
+                p[4] = entry;
+                p[5] = entry;
+                p[6] = entry;
+                p[7] = entry;
                 p += 8;
         }
 }
 
+#ifndef __PAGETABLE_PMD_FOLDED
 void pmd_init(unsigned long addr, unsigned long pagetable)
 {
         unsigned long *p, *end;
@@ -40,17 +48,18 @@ void pmd_init(unsigned long addr, unsigned long pagetable)
         end = p + PTRS_PER_PMD;
 
         while (p < end) {
-                p[0] = (unsigned long)pagetable;
-                p[1] = (unsigned long)pagetable;
-                p[2] = (unsigned long)pagetable;
-                p[3] = (unsigned long)pagetable;
-                p[4] = (unsigned long)pagetable;
-                p[5] = (unsigned long)pagetable;
-                p[6] = (unsigned long)pagetable;
-                p[7] = (unsigned long)pagetable;
+                p[0] = pagetable;
+                p[1] = pagetable;
+                p[2] = pagetable;
+                p[3] = pagetable;
+                p[4] = pagetable;
+                p[5] = pagetable;
+                p[6] = pagetable;
+                p[7] = pagetable;
                 p += 8;
         }
 }
+#endif
 
 void __init pagetable_init(void)
 {
@@ -59,8 +68,9 @@ void __init pagetable_init(void)
 
         /* Initialize the entire pgd.  */
         pgd_init((unsigned long)swapper_pg_dir);
+#ifndef __PAGETABLE_PMD_FOLDED
         pmd_init((unsigned long)invalid_pmd_table, (unsigned long)invalid_pte_table);
-
+#endif
         pgd_base = swapper_pg_dir;
         /*
          * Fixed mappings:
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index d73428b18b0a..c618eed933a1 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -303,7 +303,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
                 unsigned long lo;
                 write_c0_pagemask(PM_HUGE_MASK);
                 ptep = (pte_t *)pmdp;
-                lo = pte_val(*ptep) >> 6;
+                lo = pte_to_entrylo(pte_val(*ptep));
                 write_c0_entrylo0(lo);
                 write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
 
@@ -323,8 +323,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
                 ptep++;
                 write_c0_entrylo1(ptep->pte_high);
 #else
-                write_c0_entrylo0(pte_val(*ptep++) >> 6);
-                write_c0_entrylo1(pte_val(*ptep) >> 6);
+                write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++)));
+                write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep)));
 #endif
                 mtc0_tlbw_hazard();
                 if (idx < 0)
@@ -337,40 +337,6 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
         EXIT_CRITICAL(flags);
 }
 
-#if 0
-static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma,
-                                       unsigned long address, pte_t pte)
-{
-        unsigned long flags;
-        unsigned int asid;
-        pgd_t *pgdp;
-        pmd_t *pmdp;
-        pte_t *ptep;
-        int idx;
-
-        ENTER_CRITICAL(flags);
-        address &= (PAGE_MASK << 1);
-        asid = read_c0_entryhi() & ASID_MASK;
-        write_c0_entryhi(address | asid);
-        pgdp = pgd_offset(vma->vm_mm, address);
-        mtc0_tlbw_hazard();
-        tlb_probe();
-        tlb_probe_hazard();
-        pmdp = pmd_offset(pgdp, address);
-        idx = read_c0_index();
-        ptep = pte_offset_map(pmdp, address);
-        write_c0_entrylo0(pte_val(*ptep++) >> 6);
-        write_c0_entrylo1(pte_val(*ptep) >> 6);
-        mtc0_tlbw_hazard();
-        if (idx < 0)
-                tlb_write_random();
-        else
-                tlb_write_indexed();
-        tlbw_use_hazard();
-        EXIT_CRITICAL(flags);
-}
-#endif
-
 void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
         unsigned long entryhi, unsigned long pagemask)
 {
@@ -447,34 +413,6 @@ out:
         return ret;
 }
 
-static void __cpuinit probe_tlb(unsigned long config)
-{
-        struct cpuinfo_mips *c = &current_cpu_data;
-        unsigned int reg;
-
-        /*
-         * If this isn't a MIPS32 / MIPS64 compliant CPU.  Config 1 register
-         * is not supported, we assume R4k style.  Cpu probing already figured
-         * out the number of tlb entries.
-         */
-        if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY)
-                return;
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         * If TLB is shared in SMTC system, total size already
-         * has been calculated and written into cpu_data tlbsize
-         */
-        if((smtc_status & SMTC_TLB_SHARED) == SMTC_TLB_SHARED)
-                return;
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-        reg = read_c0_config1();
-        if (!((config >> 7) & 3))
-                panic("No TLB present");
-
-        c->tlbsize = ((reg >> 25) & 0x3f) + 1;
-}
-
 static int __cpuinitdata ntlb;
 static int __init set_ntlb(char *str)
 {
@@ -486,8 +424,6 @@ __setup("ntlb=", set_ntlb);
 
 void __cpuinit tlb_init(void)
 {
-        unsigned int config = read_c0_config();
-
         /*
          * You should never change this register:
          *   - On R4600 1.7 the tlbp never hits for pages smaller than
@@ -495,13 +431,25 @@ void __cpuinit tlb_init(void)
          *   - The entire mm handling assumes the c0_pagemask register to
          *     be set to fixed-size pages.
          */
-        probe_tlb(config);
         write_c0_pagemask(PM_DEFAULT_MASK);
         write_c0_wired(0);
         if (current_cpu_type() == CPU_R10000 ||
             current_cpu_type() == CPU_R12000 ||
             current_cpu_type() == CPU_R14000)
                 write_c0_framemask(0);
+
+        if (kernel_uses_smartmips_rixi) {
+                /*
+                 * Enable the no read, no exec bits, and enable large virtual
+                 * address.
+                 */
+                u32 pg = PG_RIE | PG_XIE;
+#ifdef CONFIG_64BIT
+                pg |= PG_ELPA;
+#endif
+                write_c0_pagegrain(pg);
+        }
+
         temp_tlb_entry = current_cpu_data.tlbsize - 1;
 
         /* From this point on the ARC firmware is dead.  */
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index badcf5e8d695..0de0e4127d66 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -29,8 +29,7 @@
 
 #include <asm/mmu_context.h>
 #include <asm/war.h>
-
-#include "uasm.h"
+#include <asm/uasm.h>
 
 static inline int r45k_bvahwbug(void)
 {
@@ -77,6 +76,8 @@ enum label_id {
         label_vmalloc_done,
         label_tlbw_hazard,
         label_split,
+        label_tlbl_goaround1,
+        label_tlbl_goaround2,
         label_nopage_tlbl,
         label_nopage_tlbs,
         label_nopage_tlbm,
@@ -93,6 +94,8 @@ UASM_L_LA(_vmalloc)
 UASM_L_LA(_vmalloc_done)
 UASM_L_LA(_tlbw_hazard)
 UASM_L_LA(_split)
+UASM_L_LA(_tlbl_goaround1)
+UASM_L_LA(_tlbl_goaround2)
 UASM_L_LA(_nopage_tlbl)
 UASM_L_LA(_nopage_tlbs)
 UASM_L_LA(_nopage_tlbm)
@@ -397,36 +400,60 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         }
 }
 
-#ifdef CONFIG_HUGETLB_PAGE
-static __cpuinit void build_huge_tlb_write_entry(u32 **p,
-                                                 struct uasm_label **l,
-                                                 struct uasm_reloc **r,
-                                                 unsigned int tmp,
-                                                 enum tlb_write_entry wmode)
+static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
+                                                                  unsigned int reg)
 {
-        /* Set huge page tlb entry size */
-        uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
-        uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
-        uasm_i_mtc0(p, tmp, C0_PAGEMASK);
+        if (kernel_uses_smartmips_rixi) {
+                UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC));
+                UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
+        } else {
+#ifdef CONFIG_64BIT_PHYS_ADDR
+                uasm_i_dsrl(p, reg, reg, ilog2(_PAGE_GLOBAL));
+#else
+                UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL));
+#endif
+        }
+}
 
-        build_tlb_write_entry(p, l, r, wmode);
+#ifdef CONFIG_HUGETLB_PAGE
 
+static __cpuinit void build_restore_pagemask(u32 **p,
+                                             struct uasm_reloc **r,
+                                             unsigned int tmp,
+                                             enum label_id lid)
+{
         /* Reset default page size */
         if (PM_DEFAULT_MASK >> 16) {
                 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
                 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
-                uasm_il_b(p, r, label_leave);
+                uasm_il_b(p, r, lid);
                 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
         } else if (PM_DEFAULT_MASK) {
                 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
-                uasm_il_b(p, r, label_leave);
+                uasm_il_b(p, r, lid);
                 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
         } else {
-                uasm_il_b(p, r, label_leave);
+                uasm_il_b(p, r, lid);
                 uasm_i_mtc0(p, 0, C0_PAGEMASK);
         }
 }
 
+static __cpuinit void build_huge_tlb_write_entry(u32 **p,
+                                                 struct uasm_label **l,
+                                                 struct uasm_reloc **r,
+                                                 unsigned int tmp,
+                                                 enum tlb_write_entry wmode)
+{
+        /* Set huge page tlb entry size */
+        uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
+        uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
+        uasm_i_mtc0(p, tmp, C0_PAGEMASK);
+
+        build_tlb_write_entry(p, l, r, wmode);
+
+        build_restore_pagemask(p, r, tmp, label_leave);
+}
+
 /*
  * Check if Huge PTE is present, if so then jump to LABEL.
  */
@@ -460,15 +487,15 @@ static __cpuinit void build_huge_update_entries(u32 **p,
         if (!small_sequence)
                 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
 
-        UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */
-        uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */
+        build_convert_pte_to_entrylo(p, pte);
+        UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */
         /* convert to entrylo1 */
         if (small_sequence)
                 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
         else
                 UASM_i_ADDU(p, pte, pte, tmp);
 
-        uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */
+        UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */
 }
 
 static __cpuinit void build_huge_handler_tail(u32 **p,
@@ -549,11 +576,13 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
 
         uasm_i_andi(p, tmp, tmp, (PTRS_PER_PGD - 1)<<3);
         uasm_i_daddu(p, ptr, ptr, tmp); /* add in pgd offset */
+#ifndef __PAGETABLE_PMD_FOLDED
         uasm_i_dmfc0(p, tmp, C0_BADVADDR); /* get faulting address */
         uasm_i_ld(p, ptr, 0, ptr); /* get pmd pointer */
         uasm_i_dsrl(p, tmp, tmp, PMD_SHIFT-3); /* get pmd offset in bytes */
         uasm_i_andi(p, tmp, tmp, (PTRS_PER_PMD - 1)<<3);
         uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
+#endif
 }
 
 /*
@@ -684,35 +713,53 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
         if (cpu_has_64bits) {
                 uasm_i_ld(p, tmp, 0, ptep); /* get even pte */
                 uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
-                uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */
-                uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
-                uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */
-                uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
+                if (kernel_uses_smartmips_rixi) {
+                        UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
+                        UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
+                        UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
+                        UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
+                        UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
+                } else {
+                        uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
+                        UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
+                        uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
+                }
+                UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
         } else {
                 int pte_off_even = sizeof(pte_t) / 2;
                 int pte_off_odd = pte_off_even + sizeof(pte_t);
 
                 /* The pte entries are pre-shifted */
                 uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */
-                uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
+                UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
                 uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */
-                uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
+                UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
         }
 #else
         UASM_i_LW(p, tmp, 0, ptep); /* get even pte */
         UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */
         if (r45k_bvahwbug())
                 build_tlb_probe_entry(p);
-        UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */
-        if (r4k_250MHZhwbug())
-                uasm_i_mtc0(p, 0, C0_ENTRYLO0);
-        uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */
-        UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */
-        if (r45k_bvahwbug())
-                uasm_i_mfc0(p, tmp, C0_INDEX);
+        if (kernel_uses_smartmips_rixi) {
+                UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC));
+                UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC));
+                UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
+                if (r4k_250MHZhwbug())
+                        UASM_i_MTC0(p, 0, C0_ENTRYLO0);
+                UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
+                UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC));
+        } else {
+                UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */
+                if (r4k_250MHZhwbug())
+                        UASM_i_MTC0(p, 0, C0_ENTRYLO0);
+                UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */
+                UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */
+                if (r45k_bvahwbug())
+                        uasm_i_mfc0(p, tmp, C0_INDEX);
+        }
         if (r4k_250MHZhwbug())
-                uasm_i_mtc0(p, 0, C0_ENTRYLO1);
-        uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */
+                UASM_i_MTC0(p, 0, C0_ENTRYLO1);
+        UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
 #endif
 }
 
@@ -985,9 +1032,14 @@ static void __cpuinit
 build_pte_present(u32 **p, struct uasm_reloc **r,
                   unsigned int pte, unsigned int ptr, enum label_id lid)
 {
-        uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
-        uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
-        uasm_il_bnez(p, r, pte, lid);
+        if (kernel_uses_smartmips_rixi) {
+                uasm_i_andi(p, pte, pte, _PAGE_PRESENT);
+                uasm_il_beqz(p, r, pte, lid);
+        } else {
+                uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
+                uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
+                uasm_il_bnez(p, r, pte, lid);
+        }
         iPTE_LW(p, pte, ptr);
 }
 
@@ -1272,6 +1324,34 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
         build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
         if (m4kc_tlbp_war())
                 build_tlb_probe_entry(&p);
+
+        if (kernel_uses_smartmips_rixi) {
+                /*
+                 * If the page is not _PAGE_VALID, RI or XI could not
+                 * have triggered it.  Skip the expensive test..
+                 */
+                uasm_i_andi(&p, K0, K0, _PAGE_VALID);
+                uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1);
+                uasm_i_nop(&p);
+
+                uasm_i_tlbr(&p);
+                /* Examine  entrylo 0 or 1 based on ptr. */
+                uasm_i_andi(&p, K0, K1, sizeof(pte_t));
+                uasm_i_beqz(&p, K0, 8);
+
+                UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/
+                UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */
+                /*
+                 * If the entryLo (now in K0) is valid (bit 1), RI or
+                 * XI must have triggered it.
+                 */
+                uasm_i_andi(&p, K0, K0, 2);
+                uasm_il_bnez(&p, &r, K0, label_nopage_tlbl);
+
+                uasm_l_tlbl_goaround1(&l, p);
+                /* Reload the PTE value */
+                iPTE_LW(&p, K0, K1);
+        }
         build_make_valid(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
 
@@ -1284,6 +1364,40 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
         iPTE_LW(&p, K0, K1);
         build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
         build_tlb_probe_entry(&p);
+
+        if (kernel_uses_smartmips_rixi) {
+                /*
+                 * If the page is not _PAGE_VALID, RI or XI could not
+                 * have triggered it.  Skip the expensive test..
+                 */
+                uasm_i_andi(&p, K0, K0, _PAGE_VALID);
+                uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2);
+                uasm_i_nop(&p);
+
+                uasm_i_tlbr(&p);
+                /* Examine  entrylo 0 or 1 based on ptr. */
+                uasm_i_andi(&p, K0, K1, sizeof(pte_t));
+                uasm_i_beqz(&p, K0, 8);
+
+                UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/
+                UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */
+                /*
+                 * If the entryLo (now in K0) is valid (bit 1), RI or
+                 * XI must have triggered it.
+                 */
+                uasm_i_andi(&p, K0, K0, 2);
+                uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2);
+                /* Reload the PTE value */
+                iPTE_LW(&p, K0, K1);
+
+                /*
+                 * We clobbered C0_PAGEMASK, restore it.  On the other branch
+                 * it is restored in build_huge_tlb_write_entry.
+                 */
+                build_restore_pagemask(&p, &r, K0, label_nopage_tlbl);
+
+                uasm_l_tlbl_goaround2(&l, p);
+        }
         uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID));
         build_huge_handler_tail(&p, &r, &l, K0, K1);
 #endif
diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 0a165c5179a1..1581e9852461 100644
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -19,8 +19,7 @@
 #include <asm/inst.h>
 #include <asm/elf.h>
 #include <asm/bugs.h>
-
-#include "uasm.h"
+#include <asm/uasm.h>
 
 enum fields {
         RS = 0x001,
@@ -63,8 +62,9 @@ enum opcode {
         insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal,
         insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0,
         insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd,
-        insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
-        insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins
+        insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw,
+        insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori,
+        insn_dins
 };
 
 struct insn {
@@ -126,9 +126,11 @@ static struct insn insn_table[] __cpuinitdata = {
         { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
         { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
         { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
+        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
         { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
         { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
         { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
+        { insn_tlbr,  M(cop0_op, cop_op, 0, 0, 0, tlbr_op),  0 },
         { insn_tlbwi,  M(cop0_op, cop_op, 0, 0, 0, tlbwi_op),  0 },
         { insn_tlbwr,  M(cop0_op, cop_op, 0, 0, 0, tlbwr_op),  0 },
         { insn_xor,  M(spec_op, 0, 0, 0, 0, xor_op),  RS | RT | RD },
@@ -379,9 +381,11 @@ I_u2s3u1(_sd)
 I_u2u1u3(_sll)
 I_u2u1u3(_sra)
 I_u2u1u3(_srl)
+I_u2u1u3(_rotr)
 I_u3u1u2(_subu)
 I_u2s3u1(_sw)
 I_0(_tlbp)
+I_0(_tlbr)
 I_0(_tlbwi)
 I_0(_tlbwr)
 I_u3u1u2(_xor)
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 4c3fca18a171..2cb5ae790203 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -52,7 +52,7 @@ static unsigned long _msc01_biu_base;
 static unsigned long _gcmp_base;
 static unsigned int ipi_map[NR_CPUS];
 
-static DEFINE_SPINLOCK(mips_irq_lock);
+static DEFINE_RAW_SPINLOCK(mips_irq_lock);
 
 static inline int mips_pcibios_iack(void)
 {
@@ -103,7 +103,7 @@ static inline int get_int(void)
 {
         unsigned long flags;
         int irq;
-        spin_lock_irqsave(&mips_irq_lock, flags);
+        raw_spin_lock_irqsave(&mips_irq_lock, flags);
 
         irq = mips_pcibios_iack();
 
@@ -113,7 +113,7 @@ static inline int get_int(void)
          * on an SMP system,  so leave it up to the generic code...
          */
 
-        spin_unlock_irqrestore(&mips_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&mips_irq_lock, flags);
 
         return irq;
 }
diff --git a/arch/mips/nxp/pnx833x/common/interrupts.c b/arch/mips/nxp/pnx833x/common/interrupts.c
index 3a467c04f811..941916f8aaff 100644
--- a/arch/mips/nxp/pnx833x/common/interrupts.c
+++ b/arch/mips/nxp/pnx833x/common/interrupts.c
@@ -156,19 +156,19 @@ static int irqflags[PNX833X_PIC_NUM_IRQ];	/* initialized by zeroes */
 #define IRQFLAG_STARTED         1
 #define IRQFLAG_DISABLED        2
 
-static DEFINE_SPINLOCK(pnx833x_irq_lock);
+static DEFINE_RAW_SPINLOCK(pnx833x_irq_lock);
 
 static unsigned int pnx833x_startup_pic_irq(unsigned int irq)
 {
         unsigned long flags;
         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
 
-        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 
         irqflags[pic_irq] = IRQFLAG_STARTED;    /* started, not disabled */
         pnx833x_hard_enable_pic_irq(pic_irq);
 
-        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
         return 0;
 }
 
@@ -177,12 +177,12 @@ static void pnx833x_shutdown_pic_irq(unsigned int irq)
         unsigned long flags;
         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
 
-        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 
         irqflags[pic_irq] = 0;                  /* not started */
         pnx833x_hard_disable_pic_irq(pic_irq);
 
-        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
 }
 
 static void pnx833x_enable_pic_irq(unsigned int irq)
@@ -190,13 +190,13 @@ static void pnx833x_enable_pic_irq(unsigned int irq)
         unsigned long flags;
         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
 
-        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 
         irqflags[pic_irq] &= ~IRQFLAG_DISABLED;
         if (irqflags[pic_irq] == IRQFLAG_STARTED)
                 pnx833x_hard_enable_pic_irq(pic_irq);
 
-        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
 }
 
 static void pnx833x_disable_pic_irq(unsigned int irq)
@@ -204,12 +204,12 @@ static void pnx833x_disable_pic_irq(unsigned int irq)
         unsigned long flags;
         unsigned int pic_irq = irq - PNX833X_PIC_IRQ_BASE;
 
-        spin_lock_irqsave(&pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_irq_lock, flags);
 
         irqflags[pic_irq] |= IRQFLAG_DISABLED;
         pnx833x_hard_disable_pic_irq(pic_irq);
 
-        spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_irq_lock, flags);
 }
 
 static void pnx833x_ack_pic_irq(unsigned int irq)
@@ -220,15 +220,15 @@ static void pnx833x_end_pic_irq(unsigned int irq)
 {
 }
 
-static DEFINE_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
+static DEFINE_RAW_SPINLOCK(pnx833x_gpio_pnx833x_irq_lock);
 
 static unsigned int pnx833x_startup_gpio_irq(unsigned int irq)
 {
         int pin = irq - PNX833X_GPIO_IRQ_BASE;
         unsigned long flags;
-        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
         pnx833x_gpio_enable_irq(pin);
-        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
         return 0;
 }
 
@@ -236,18 +236,18 @@ static void pnx833x_enable_gpio_irq(unsigned int irq)
 {
         int pin = irq - PNX833X_GPIO_IRQ_BASE;
         unsigned long flags;
-        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
         pnx833x_gpio_enable_irq(pin);
-        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
 }
 
 static void pnx833x_disable_gpio_irq(unsigned int irq)
 {
         int pin = irq - PNX833X_GPIO_IRQ_BASE;
         unsigned long flags;
-        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
         pnx833x_gpio_disable_irq(pin);
-        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
 }
 
 static void pnx833x_ack_gpio_irq(unsigned int irq)
@@ -258,9 +258,9 @@ static void pnx833x_end_gpio_irq(unsigned int irq)
 {
         int pin = irq - PNX833X_GPIO_IRQ_BASE;
         unsigned long flags;
-        spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_lock_irqsave(&pnx833x_gpio_pnx833x_irq_lock, flags);
         pnx833x_gpio_clear_irq(pin);
-        spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&pnx833x_gpio_pnx833x_irq_lock, flags);
 }
 
 static int pnx833x_set_type_gpio_irq(unsigned int irq, unsigned int flow_type)
@@ -377,4 +377,3 @@ void __init plat_time_init(void)
 
         mips_hpt_frequency *= 500000;
 }
-
diff --git a/arch/mips/nxp/pnx833x/common/prom.c b/arch/mips/nxp/pnx833x/common/prom.c
index 2a41e8fec210..29969f90a6b0 100644
--- a/arch/mips/nxp/pnx833x/common/prom.c
+++ b/arch/mips/nxp/pnx833x/common/prom.c
@@ -62,9 +62,3 @@ char __init *prom_getenv(char *envname)
 void __init prom_free_prom_memory(void)
 {
 }
-
-char * __init prom_getcmdline(void)
-{
-        return arcs_cmdline;
-}
-
diff --git a/arch/mips/nxp/pnx8550/common/prom.c b/arch/mips/nxp/pnx8550/common/prom.c
index 2f567452e7ac..32f70097c3c7 100644
--- a/arch/mips/nxp/pnx8550/common/prom.c
+++ b/arch/mips/nxp/pnx8550/common/prom.c
@@ -124,6 +124,5 @@ void prom_putchar(char c)
         }
 }
 
-EXPORT_SYMBOL(prom_getcmdline);
 EXPORT_SYMBOL(get_ethernet_addr);
 EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 7832ad257a14..f9eb1aba6345 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2004, 2005 Ralf Baechle
  * Copyright (C) 2005 MIPS Technologies, Inc.
  */
+#include <linux/compiler.h>
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/oprofile.h>
@@ -14,9 +15,9 @@
 
 #include "op_impl.h"
 
-extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak));
-extern struct op_mips_model op_model_rm9000_ops __attribute__((weak));
-extern struct op_mips_model op_model_loongson2_ops __attribute__((weak));
+extern struct op_mips_model op_model_mipsxx_ops __weak;
+extern struct op_mips_model op_model_rm9000_ops __weak;
+extern struct op_mips_model op_model_loongson2_ops __weak;
 
 static struct op_mips_model *model;
 
diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 475ff46712ab..29e2326b6257 100644
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Yanhua <yanh@lemote.com>
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -47,8 +47,6 @@ static struct loongson2_register_config {
         int cnt1_enabled, cnt2_enabled;
 } reg;
 
-DEFINE_SPINLOCK(sample_lock);
-
 static char *oprofid = "LoongsonPerf";
 static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
 /* Compute all of the registers in preparation for enabling profiling.  */
@@ -115,7 +113,6 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
         uint64_t counter, counter1, counter2;
         struct pt_regs *regs = get_irq_regs();
         int enabled;
-        unsigned long flags;
 
         /*
          * LOONGSON2 defines two 32-bit performance counters.
@@ -136,8 +133,6 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
         counter1 = counter & 0xffffffff;
         counter2 = counter >> 32;
 
-        spin_lock_irqsave(&sample_lock, flags);
-
         if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
                 if (reg.cnt1_enabled)
                         oprofile_add_sample(regs, 0);
@@ -149,8 +144,6 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
                 counter2 = reg.reset_counter2;
         }
 
-        spin_unlock_irqrestore(&sample_lock, flags);
-
         write_c0_perfcnt((counter2 << 32) | counter1);
 
         return IRQ_HANDLED;
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dd..acacd1407c63 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -51,6 +51,67 @@ static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
          qube_raq_galileo_early_fixup);
 
+static void __devinit cobalt_legacy_ide_resource_fixup(struct pci_dev *dev,
+                                                       struct resource *res)
+{
+        struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
+        unsigned long offset = hose->io_offset;
+        struct resource orig = *res;
+
+        if (!(res->flags & IORESOURCE_IO) ||
+            !(res->flags & IORESOURCE_PCI_FIXED))
+                return;
+
+        res->start -= offset;
+        res->end -= offset;
+        dev_printk(KERN_DEBUG, &dev->dev, "converted legacy %pR to bus %pR\n",
+                   &orig, res);
+}
+
+static void __devinit cobalt_legacy_ide_fixup(struct pci_dev *dev)
+{
+        u32 class;
+        u8 progif;
+
+        /*
+         * If the IDE controller is in legacy mode, pci_setup_device() fills in
+         * the resources with the legacy addresses that normally appear on the
+         * PCI bus, just as if we had read them from a BAR.
+         *
+         * However, with the GT-64111, those legacy addresses, e.g., 0x1f0,
+         * will never appear on the PCI bus because it converts memory accesses
+         * in the PCI I/O region (which is never at address zero) into I/O port
+         * accesses with no address translation.
+         *
+         * For example, if GT_DEF_PCI0_IO_BASE is 0x10000000, a load or store
+         * to physical address 0x100001f0 will become a PCI access to I/O port
+         * 0x100001f0.  There's no way to generate an access to I/O port 0x1f0,
+         * but the VT82C586 IDE controller does respond at 0x100001f0 because
+         * it only decodes the low 24 bits of the address.
+         *
+         * When this quirk runs, the pci_dev resources should contain bus
+         * addresses, not Linux I/O port numbers, so convert legacy addresses
+         * like 0x1f0 to bus addresses like 0x100001f0.  Later, we'll convert
+         * them back with pcibios_fixup_bus() or pcibios_bus_to_resource().
+         */
+        class = dev->class >> 8;
+        if (class != PCI_CLASS_STORAGE_IDE)
+                return;
+
+        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
+        if ((progif & 1) == 0) {
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[0]);
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[1]);
+        }
+        if ((progif & 4) == 0) {
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[2]);
+                cobalt_legacy_ide_resource_fixup(dev, &dev->resource[3]);
+        }
+}
+
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
+          cobalt_legacy_ide_fixup);
+
 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
 {
         unsigned short cfgword;
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index caf2edeb02f0..4b9768d5d729 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -131,7 +131,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
 
         /* Serial short detect enable */
         _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo);
-        _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo);
+        _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 3), lo);
 
         /* setting the USB2.0 micro frame length */
         pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index aa5d3da27212..2bb4057bf6c7 100644
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -1,13 +1,11 @@
 /*
- * fuloong2e specific PCI support.
- *
  * Copyright (C) 1999, 2000, 2004  MIPS Technologies, Inc.
  *      All rights reserved.
  *      Authors: Carsten Langgaard <carstenl@mips.com>
  *               Maciej W. Rozycki <macro@mips.com>
  *
  * Copyright (C) 2009 Lemote Inc.
- * Author: Wu Zhangjin <wuzj@lemote.com>
+ * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 32548b5d68d6..04b31478a6d7 100644
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -206,7 +206,7 @@ static void pci_proc_init(void)
 }
 #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
 
-DEFINE_SPINLOCK(bpci_lock);
+static DEFINE_SPINLOCK(bpci_lock);
 
 /*****************************************************************************
  *
diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
index bea9b6cdfdbf..455f8e50a007 100644
--- a/arch/mips/pci/pci-bcm47xx.c
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -57,4 +57,3 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         dev->irq = res;
         return 0;
 }
-
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 9cb0c807f564..d248b707eff3 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -209,16 +209,14 @@ const char *octeon_get_pci_interrupts(void)
         case CVMX_BOARD_TYPE_NAO38:
                 /* This is really the NAC38 */
                 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
-        case CVMX_BOARD_TYPE_THUNDER:
-                return "";
-        case CVMX_BOARD_TYPE_EBH3000:
-                return "";
         case CVMX_BOARD_TYPE_EBH3100:
         case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
         case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
                 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
         case CVMX_BOARD_TYPE_BBGW_REF:
                 return "AABCD";
+        case CVMX_BOARD_TYPE_THUNDER:
+        case CVMX_BOARD_TYPE_EBH3000:
         default:
                 return "";
         }
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index 9a11c2226891..38bc28005b4a 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -49,8 +49,8 @@ static int pci_initialized;
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-void
-pcibios_align_resource(void *data, struct resource *res,
+resource_size_t
+pcibios_align_resource(void *data, const struct resource *res,
                        resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
@@ -73,7 +73,7 @@ pcibios_align_resource(void *data, struct resource *res,
                         start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
         }
 
-        res->start = start;
+        return start;
 }
 
 static void __devinit pcibios_scanbus(struct pci_controller *hose)
@@ -251,8 +251,6 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev,
         for (i = 0; i < PCI_NUM_RESOURCES; i++) {
                 if (!dev->resource[i].start)
                         continue;
-                if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
-                        continue;
                 if (dev->resource[i].flags & IORESOURCE_IO)
                         offset = hose->io_offset;
                 else if (dev->resource[i].flags & IORESOURCE_MEM)
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
index 5175357d0a25..94c9c2c9fbc1 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -131,4 +131,3 @@ void msp_cic_irq_dispatch(void)
         else
                 do_IRQ(ffs(pending) + intbase - 1);
 }
-
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
index c317a3623ce9..db98d87a0922 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
@@ -303,12 +303,6 @@ char *prom_getenv(char *env_name)
 }
 
 /* PROM commandline functions */
-char *prom_getcmdline(void)
-{
-        return &(arcs_cmdline[0]);
-}
-EXPORT_SYMBOL(prom_getcmdline);
-
 void  __init prom_init_cmdline(void)
 {
         char *cp;
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
index fc990cb31941..d6f8bdff8cbb 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
@@ -127,7 +127,7 @@ static int recv_ack(void)
 
         if (ack) {
                 do_idle();
-                printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM \n");
+                printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM\n");
                 return -1;
         }
 
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
index a31288335fba..d6c7ec469fa8 100644
--- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
@@ -65,4 +65,3 @@
 const char rts = TIOCM_RTS;
 const char dtr = TIOCM_DTR;
 int fd;
-
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
index 678388fd34b1..fd22597edb64 100644
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -345,14 +345,13 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
         return pcibios_enable_resources(dev);
 }
 
-void pcibios_align_resource(void *data, struct resource *res,
-                            resource_size_t size, resource_size_t align)
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
+        resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO) {
-                resource_size_t start = res->start;
-
                 /* We need to avoid collisions with `mirrored' VGA ports
                    and other strange ISA hardware, so we always want the
                    addresses kilobyte aligned.  */
@@ -363,8 +362,9 @@ void pcibios_align_resource(void *data, struct resource *res,
                 }
 
                 start = (start + 1024 - 1) & ~(1024 - 1);
-                res->start = start;
         }
+
+        return start;
 }
 
 struct pci_ops titan_pci_ops = {
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index 326fe7a392e8..efc9e889b349 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -8,7 +8,7 @@
 
 #define LAUNCHSTACK_SIZE 256
 
-static __cpuinitdata DEFINE_SPINLOCK(launch_lock);
+static __cpuinitdata arch_spinlock_t launch_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 
 static unsigned long secondary_sp __cpuinitdata;
 static unsigned long secondary_gp __cpuinitdata;
@@ -20,7 +20,7 @@ static void __init prom_smp_bootstrap(void)
 {
         local_irq_disable();
 
-        while (spin_is_locked(&launch_lock));
+        while (arch_spin_is_locked(&launch_lock));
 
         __asm__ __volatile__(
         "       move    $sp, %0         \n"
@@ -37,7 +37,7 @@ static void __init prom_smp_bootstrap(void)
  */
 void __init prom_grab_secondary(void)
 {
-        spin_lock(&launch_lock);
+        arch_spin_lock(&launch_lock);
 
         pmon_cpustart(1, &prom_smp_bootstrap,
                       launchstack + LAUNCHSTACK_SIZE, 0);
@@ -138,7 +138,7 @@ static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
         secondary_sp = sp;
         secondary_gp = gp;
 
-        spin_unlock(&launch_lock);
+        arch_spin_unlock(&launch_lock);
 }
 
 /*
diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
index 7995df45dc8d..26a6ef19d71f 100644
--- a/arch/mips/power/cpu.c
+++ b/arch/mips/power/cpu.c
@@ -3,9 +3,9 @@
  *
  * Licensed under the GPLv2
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Hu Hongbing <huhb@lemote.com>
- *         Wu Zhangjin <wuzj@lemote.com>
+ *         Wu Zhangjin <wuzhangjin@gmail.com>
  */
 #include <asm/suspend.h>
 #include <asm/fpu.h>
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 0cf86fb32ec3..dbb5c7b4b70f 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -3,9 +3,9 @@
  *
  * Licensed under the GPLv2
  *
- * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
+ * Copyright (C) 2009 Lemote Inc.
  * Author: Hu Hongbing <huhb@lemote.com>
- *         Wu Zhangjin <wuzj@lemote.com>
+ *         Wu Zhangjin <wuzhangjin@gmail.com>
  */
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index 6a882194e063..217424231eb6 100644
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -340,10 +340,6 @@ static void __init platform_configure_usb(void)
 
         switch (asic) {
         case ASIC_ZEUS:
-                fs_update(0x0000, 0x11, 0x02, 0);
-                bcm1_usb2_ctl = 0x803;
-                break;
-
         case ASIC_CRONUS:
         case ASIC_CRONUSLITE:
                 fs_update(0x0000, 0x11, 0x02, 0);
diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
index 80b2eed21ac3..325fab9685d1 100644
--- a/arch/mips/powertv/asic/asic_int.c
+++ b/arch/mips/powertv/asic/asic_int.c
@@ -39,21 +39,21 @@
 
 #include <asm/mach-powertv/asic_regs.h>
 
-static DEFINE_SPINLOCK(asic_irq_lock);
+static DEFINE_RAW_SPINLOCK(asic_irq_lock);
 
 static inline int get_int(void)
 {
         unsigned long flags;
         int irq;
 
-        spin_lock_irqsave(&asic_irq_lock, flags);
+        raw_spin_lock_irqsave(&asic_irq_lock, flags);
 
         irq = (asic_read(int_int_scan) >> 4) - 1;
 
         if (irq == 0 || irq >= NR_IRQS)
                 irq = -1;
 
-        spin_unlock_irqrestore(&asic_irq_lock, flags);
+        raw_spin_unlock_irqrestore(&asic_irq_lock, flags);
 
         return irq;
 }
diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c
index 698b1eafbe98..af2cae0a5ab3 100644
--- a/arch/mips/powertv/powertv_setup.c
+++ b/arch/mips/powertv/powertv_setup.c
@@ -25,14 +25,15 @@
 #include <linux/etherdevice.h>
 #include <linux/if_ether.h>
 #include <linux/ctype.h>
-
 #include <linux/cpu.h>
+#include <linux/time.h>
+
 #include <asm/bootinfo.h>
 #include <asm/irq.h>
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/prom.h>
 #include <asm/dma.h>
-#include <linux/time.h>
+#include <asm/asm.h>
 #include <asm/traps.h>
 #include <asm/asm-offsets.h>
 #include "reset.h"
@@ -41,26 +42,21 @@
 
 /*
  * Macros for loading addresses and storing registers:
- * PTR_LA       Load the address into a register
- * LONG_S       Store the full width of the given register.
- * LONG_L       Load the full width of the given register
- * PTR_ADDIU    Add a constant value to a register used as a pointer
+ * LONG_L_      Stringified version of LONG_L for use in asm() statement
+ * LONG_S_      Stringified version of LONG_S for use in asm() statement
+ * PTR_LA_      Stringified version of PTR_LA for use in asm() statement
  * REG_SIZE     Number of 8-bit bytes in a full width register
  */
+#define LONG_L_         VAL(LONG_L) " "
+#define LONG_S_         VAL(LONG_S) " "
+#define PTR_LA_         VAL(PTR_LA) " "
+
 #ifdef CONFIG_64BIT
 #warning TODO: 64-bit code needs to be verified
-#define PTR_LA          "dla    "
-#define LONG_S          "sd     "
-#define LONG_L          "ld     "
-#define PTR_ADDIU       "daddiu "
 #define REG_SIZE        "8"             /* In bytes */
 #endif
 
 #ifdef CONFIG_32BIT
-#define PTR_LA          "la     "
-#define LONG_S          "sw     "
-#define LONG_L          "lw     "
-#define PTR_ADDIU       "addiu  "
 #define REG_SIZE        "4"             /* In bytes */
 #endif
 
@@ -113,9 +109,9 @@ static int panic_handler(struct notifier_block *notifier_block,
                  * structure. */
                 __asm__ __volatile__ (
                         ".set   noat\n"
-                        LONG_S          "$at, %[at]\n"
-                        LONG_S          "$2, %[v0]\n"
-                        LONG_S          "$3, %[v1]\n"
+                        LONG_S_         "$at, %[at]\n"
+                        LONG_S_         "$2, %[v0]\n"
+                        LONG_S_         "$3, %[v1]\n"
                 :
                         [at] "=m" (at),
                         [v0] "=m" (v0),
@@ -129,54 +125,54 @@ static int panic_handler(struct notifier_block *notifier_block,
                         "move           $at, %[pt_regs]\n"
 
                         /* Argument registers */
-                        LONG_S          "$4, " VAL(PT_R4) "($at)\n"
-                        LONG_S          "$5, " VAL(PT_R5) "($at)\n"
-                        LONG_S          "$6, " VAL(PT_R6) "($at)\n"
-                        LONG_S          "$7, " VAL(PT_R7) "($at)\n"
+                        LONG_S_         "$4, " VAL(PT_R4) "($at)\n"
+                        LONG_S_         "$5, " VAL(PT_R5) "($at)\n"
+                        LONG_S_         "$6, " VAL(PT_R6) "($at)\n"
+                        LONG_S_         "$7, " VAL(PT_R7) "($at)\n"
 
                         /* Temporary regs */
-                        LONG_S          "$8, " VAL(PT_R8) "($at)\n"
-                        LONG_S          "$9, " VAL(PT_R9) "($at)\n"
-                        LONG_S          "$10, " VAL(PT_R10) "($at)\n"
-                        LONG_S          "$11, " VAL(PT_R11) "($at)\n"
-                        LONG_S          "$12, " VAL(PT_R12) "($at)\n"
-                        LONG_S          "$13, " VAL(PT_R13) "($at)\n"
-                        LONG_S          "$14, " VAL(PT_R14) "($at)\n"
-                        LONG_S          "$15, " VAL(PT_R15) "($at)\n"
+                        LONG_S_         "$8, " VAL(PT_R8) "($at)\n"
+                        LONG_S_         "$9, " VAL(PT_R9) "($at)\n"
+                        LONG_S_         "$10, " VAL(PT_R10) "($at)\n"
+                        LONG_S_         "$11, " VAL(PT_R11) "($at)\n"
+                        LONG_S_         "$12, " VAL(PT_R12) "($at)\n"
+                        LONG_S_         "$13, " VAL(PT_R13) "($at)\n"
+                        LONG_S_         "$14, " VAL(PT_R14) "($at)\n"
+                        LONG_S_         "$15, " VAL(PT_R15) "($at)\n"
 
                         /* "Saved" registers */
-                        LONG_S          "$16, " VAL(PT_R16) "($at)\n"
-                        LONG_S          "$17, " VAL(PT_R17) "($at)\n"
-                        LONG_S          "$18, " VAL(PT_R18) "($at)\n"
-                        LONG_S          "$19, " VAL(PT_R19) "($at)\n"
-                        LONG_S          "$20, " VAL(PT_R20) "($at)\n"
-                        LONG_S          "$21, " VAL(PT_R21) "($at)\n"
-                        LONG_S          "$22, " VAL(PT_R22) "($at)\n"
-                        LONG_S          "$23, " VAL(PT_R23) "($at)\n"
+                        LONG_S_         "$16, " VAL(PT_R16) "($at)\n"
+                        LONG_S_         "$17, " VAL(PT_R17) "($at)\n"
+                        LONG_S_         "$18, " VAL(PT_R18) "($at)\n"
+                        LONG_S_         "$19, " VAL(PT_R19) "($at)\n"
+                        LONG_S_         "$20, " VAL(PT_R20) "($at)\n"
+                        LONG_S_         "$21, " VAL(PT_R21) "($at)\n"
+                        LONG_S_         "$22, " VAL(PT_R22) "($at)\n"
+                        LONG_S_         "$23, " VAL(PT_R23) "($at)\n"
 
                         /* Add'l temp regs */
-                        LONG_S          "$24, " VAL(PT_R24) "($at)\n"
-                        LONG_S          "$25, " VAL(PT_R25) "($at)\n"
+                        LONG_S_         "$24, " VAL(PT_R24) "($at)\n"
+                        LONG_S_         "$25, " VAL(PT_R25) "($at)\n"
 
                         /* Kernel temp regs */
-                        LONG_S          "$26, " VAL(PT_R26) "($at)\n"
-                        LONG_S          "$27, " VAL(PT_R27) "($at)\n"
+                        LONG_S_         "$26, " VAL(PT_R26) "($at)\n"
+                        LONG_S_         "$27, " VAL(PT_R27) "($at)\n"
 
                         /* Global pointer, stack pointer, frame pointer and
                          * return address */
-                        LONG_S          "$gp, " VAL(PT_R28) "($at)\n"
-                        LONG_S          "$sp, " VAL(PT_R29) "($at)\n"
-                        LONG_S          "$fp, " VAL(PT_R30) "($at)\n"
-                        LONG_S          "$ra, " VAL(PT_R31) "($at)\n"
+                        LONG_S_         "$gp, " VAL(PT_R28) "($at)\n"
+                        LONG_S_         "$sp, " VAL(PT_R29) "($at)\n"
+                        LONG_S_         "$fp, " VAL(PT_R30) "($at)\n"
+                        LONG_S_         "$ra, " VAL(PT_R31) "($at)\n"
 
                         /* Now we can get the $at and v0 registers back and
                          * store them */
-                        LONG_L          "$8, %[at]\n"
-                        LONG_S          "$8, " VAL(PT_R1) "($at)\n"
-                        LONG_L          "$8, %[v0]\n"
-                        LONG_S          "$8, " VAL(PT_R2) "($at)\n"
-                        LONG_L          "$8, %[v1]\n"
-                        LONG_S          "$8, " VAL(PT_R3) "($at)\n"
+                        LONG_L_         "$8, %[at]\n"
+                        LONG_S_         "$8, " VAL(PT_R1) "($at)\n"
+                        LONG_L_         "$8, %[v0]\n"
+                        LONG_S_         "$8, " VAL(PT_R2) "($at)\n"
+                        LONG_L_         "$8, %[v1]\n"
+                        LONG_S_         "$8, " VAL(PT_R3) "($at)\n"
                 :
                 :
                         [at] "m" (at),
@@ -191,8 +187,8 @@ static int panic_handler(struct notifier_block *notifier_block,
                 __asm__ __volatile__ (
                         ".set   noat\n"
                 "1:\n"
-                        PTR_LA          "$at, 1b\n"
-                        LONG_S          "$at, %[cp0_epc]\n"
+                        PTR_LA_         "$at, 1b\n"
+                        LONG_S_         "$at, %[cp0_epc]\n"
                 :
                         [cp0_epc] "=m" (my_regs.cp0_epc)
                 :
diff --git a/arch/mips/sgi-ip27/ip27-klnuma.c b/arch/mips/sgi-ip27/ip27-klnuma.c
index d9c79d8be81d..c3d30a88daf3 100644
--- a/arch/mips/sgi-ip27/ip27-klnuma.c
+++ b/arch/mips/sgi-ip27/ip27-klnuma.c
@@ -133,4 +133,3 @@ pfn_t node_getfirstfree(cnodeid_t cnode)
                 return (KDM_TO_PHYS(PAGE_ALIGN(SYMMON_STK_ADDR(nasid, 0))) >>
                                                                 PAGE_SHIFT);
 }
-
diff --git a/arch/mips/sgi-ip27/ip27-nmi.c b/arch/mips/sgi-ip27/ip27-nmi.c
index 6c5a630566f9..bc4fa8dd67f3 100644
--- a/arch/mips/sgi-ip27/ip27-nmi.c
+++ b/arch/mips/sgi-ip27/ip27-nmi.c
@@ -17,11 +17,10 @@
 #endif
 
 #define CNODEID_NONE (cnodeid_t)-1
-#define enter_panic_mode()      spin_lock(&nmi_lock)
 
 typedef unsigned long machreg_t;
 
-DEFINE_SPINLOCK(nmi_lock);
+static arch_spinlock_t nmi_lock = __ARCH_SPIN_LOCK_UNLOCKED;
 
 /*
  * Lets see what else we need to do here. Set up sp, gp?
@@ -193,9 +192,9 @@ cont_nmi_dump(void)
         atomic_inc(&nmied_cpus);
 #endif
         /*
-         * Use enter_panic_mode to allow only 1 cpu to proceed
+         * Only allow 1 cpu to proceed
          */
-        enter_panic_mode();
+        arch_spin_lock(&nmi_lock);
 
 #ifdef REAL_NMI_SIGNAL
         /*
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index 5c2bf111ca67..d8b65204d288 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -512,10 +512,6 @@ void __init arch_init_irq(void)
                                 "level");
                         break;
 
-                case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
-                        set_irq_chip_and_handler_name(irq,
-                                &crime_edge_interrupt, handle_edge_irq, "edge");
-                        break;
                 case CRIME_CPUERR_IRQ:
                 case CRIME_MEMERR_IRQ:
                         set_irq_chip_and_handler_name(irq,
@@ -523,12 +519,9 @@ void __init arch_init_irq(void)
                                 "level");
                         break;
 
+                case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
                 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
                 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
-                        set_irq_chip_and_handler_name(irq,
-                                &crime_edge_interrupt, handle_edge_irq, "edge");
-                        break;
-
                 case CRIME_VICE_IRQ:
                         set_irq_chip_and_handler_name(irq,
                                 &crime_edge_interrupt, handle_edge_irq, "edge");
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 4070268aa769..06e25d949768 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -73,14 +73,14 @@ static struct irq_chip bcm1480_irq_type = {
 /* Store the CPU id (not the logical number) */
 int bcm1480_irq_owner[BCM1480_NR_IRQS];
 
-DEFINE_SPINLOCK(bcm1480_imr_lock);
+static DEFINE_RAW_SPINLOCK(bcm1480_imr_lock);
 
 void bcm1480_mask_irq(int cpu, int irq)
 {
         unsigned long flags, hl_spacing;
         u64 cur_ints;
 
-        spin_lock_irqsave(&bcm1480_imr_lock, flags);
+        raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
         hl_spacing = 0;
         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
                 hl_spacing = BCM1480_IMR_HL_SPACING;
@@ -89,7 +89,7 @@ void bcm1480_mask_irq(int cpu, int irq)
         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
         cur_ints |= (((u64) 1) << irq);
         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
-        spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
+        raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 }
 
 void bcm1480_unmask_irq(int cpu, int irq)
@@ -97,7 +97,7 @@ void bcm1480_unmask_irq(int cpu, int irq)
         unsigned long flags, hl_spacing;
         u64 cur_ints;
 
-        spin_lock_irqsave(&bcm1480_imr_lock, flags);
+        raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
         hl_spacing = 0;
         if ((irq >= BCM1480_NR_IRQS_HALF) && (irq <= BCM1480_NR_IRQS)) {
                 hl_spacing = BCM1480_IMR_HL_SPACING;
@@ -106,7 +106,7 @@ void bcm1480_unmask_irq(int cpu, int irq)
         cur_ints = ____raw_readq(IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
         cur_ints &= ~(((u64) 1) << irq);
         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + hl_spacing));
-        spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
+        raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 }
 
 #ifdef CONFIG_SMP
@@ -123,7 +123,7 @@ static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
         cpu = cpu_logical_map(i);
 
         /* Protect against other affinity changers and IMR manipulation */
-        spin_lock_irqsave(&bcm1480_imr_lock, flags);
+        raw_spin_lock_irqsave(&bcm1480_imr_lock, flags);
 
         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
         old_cpu = bcm1480_irq_owner[irq];
@@ -148,7 +148,7 @@ static int bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask)
                         ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING)));
                 }
         }
-        spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
+        raw_spin_unlock_irqrestore(&bcm1480_imr_lock, flags);
 
         return 0;
 }
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 15ea778b5e66..ed2453eab5cb 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -28,7 +28,6 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
-#include <linux/smp_lock.h>
 #include <linux/vmalloc.h>
 #include <linux/fs.h>
 #include <linux/errno.h>
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 5e7f2016cceb..ab44a2f59ee4 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -72,20 +72,20 @@ static struct irq_chip sb1250_irq_type = {
 /* Store the CPU id (not the logical number) */
 int sb1250_irq_owner[SB1250_NR_IRQS];
 
-DEFINE_SPINLOCK(sb1250_imr_lock);
+static DEFINE_RAW_SPINLOCK(sb1250_imr_lock);
 
 void sb1250_mask_irq(int cpu, int irq)
 {
         unsigned long flags;
         u64 cur_ints;
 
-        spin_lock_irqsave(&sb1250_imr_lock, flags);
+        raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
                                         R_IMR_INTERRUPT_MASK));
         cur_ints |= (((u64) 1) << irq);
         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
                                         R_IMR_INTERRUPT_MASK));
-        spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+        raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 }
 
 void sb1250_unmask_irq(int cpu, int irq)
@@ -93,13 +93,13 @@ void sb1250_unmask_irq(int cpu, int irq)
         unsigned long flags;
         u64 cur_ints;
 
-        spin_lock_irqsave(&sb1250_imr_lock, flags);
+        raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
                                         R_IMR_INTERRUPT_MASK));
         cur_ints &= ~(((u64) 1) << irq);
         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
                                         R_IMR_INTERRUPT_MASK));
-        spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+        raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 }
 
 #ifdef CONFIG_SMP
@@ -115,7 +115,7 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
         cpu = cpu_logical_map(i);
 
         /* Protect against other affinity changers and IMR manipulation */
-        spin_lock_irqsave(&sb1250_imr_lock, flags);
+        raw_spin_lock_irqsave(&sb1250_imr_lock, flags);
 
         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
         old_cpu = sb1250_irq_owner[irq];
@@ -137,7 +137,7 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
                                         R_IMR_INTERRUPT_MASK));
         }
-        spin_unlock_irqrestore(&sb1250_imr_lock, flags);
+        raw_spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 
         return 0;
 }
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 31e2583ec622..90c558f7c0fa 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -132,7 +132,7 @@ device_initcall(snirm_setup_devinit);
  * readb/writeb to access them
  */
 
-DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
+static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock);
 #define PIC_CMD    0x00
 #define PIC_IMR    0x01
 #define PIC_ISR    PIC_CMD
@@ -161,13 +161,13 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq)
 
         irq -= RM200_I8259A_IRQ_BASE;
         mask = 1 << irq;
-        spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+        raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
         rm200_cached_irq_mask |= mask;
         if (irq & 8)
                 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
         else
                 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
-        spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
 }
 
 static void sni_rm200_enable_8259A_irq(unsigned int irq)
@@ -177,13 +177,13 @@ static void sni_rm200_enable_8259A_irq(unsigned int irq)
 
         irq -= RM200_I8259A_IRQ_BASE;
         mask = ~(1 << irq);
-        spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+        raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
         rm200_cached_irq_mask &= mask;
         if (irq & 8)
                 writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
         else
                 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
-        spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
 }
 
 static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
@@ -216,7 +216,7 @@ void sni_rm200_mask_and_ack_8259A(unsigned int irq)
 
         irq -= RM200_I8259A_IRQ_BASE;
         irqmask = 1 << irq;
-        spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+        raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
         /*
          * Lightweight spurious IRQ detection. We do not want
          * to overdo spurious IRQ handling - it's usually a sign
@@ -247,7 +247,7 @@ handle_real_irq:
                 writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
                 writeb(0x60+irq, rm200_pic_master + PIC_CMD);
         }
-        spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
         return;
 
 spurious_8259A_irq:
@@ -298,7 +298,7 @@ static inline int sni_rm200_i8259_irq(void)
 {
         int irq;
 
-        spin_lock(&sni_rm200_i8259A_lock);
+        raw_spin_lock(&sni_rm200_i8259A_lock);
 
         /* Perform an interrupt acknowledge cycle on controller 1. */
         writeb(0x0C, rm200_pic_master + PIC_CMD);       /* prepare for poll */
@@ -325,7 +325,7 @@ static inline int sni_rm200_i8259_irq(void)
                         irq = -1;
         }
 
-        spin_unlock(&sni_rm200_i8259A_lock);
+        raw_spin_unlock(&sni_rm200_i8259A_lock);
 
         return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;
 }
@@ -334,7 +334,7 @@ void sni_rm200_init_8259A(void)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+        raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
 
         writeb(0xff, rm200_pic_master + PIC_IMR);
         writeb(0xff, rm200_pic_slave + PIC_IMR);
@@ -352,7 +352,7 @@ void sni_rm200_init_8259A(void)
         writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
         writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
 
-        spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+        raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
 }
 
 /*
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index e27809b6d04f..7174d830dd05 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -399,11 +399,6 @@ const char *get_system_type(void)
         return txx9_system_type;
 }
 
-char * __init prom_getcmdline(void)
-{
-        return &(arcs_cmdline[0]);
-}
-
 const char *__init prom_getenv(const char *name)
 {
         const s32 *str;
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 25e50a7be387..3206f76f300b 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -67,8 +67,6 @@ static void jmr3927_board_init(void);
 
 static void __init jmr3927_mem_setup(void)
 {
-        char *argptr;
-
         set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
 
         _machine_restart = jmr3927_machine_restart;
@@ -97,11 +95,6 @@ static void __init jmr3927_mem_setup(void)
         jmr3927_board_init();
 
         tx3927_sio_init(0, 1 << 1); /* ch1: noCTS */
-#ifdef CONFIG_SERIAL_TXX9_CONSOLE
-        argptr = prom_getcmdline();
-        if (!strstr(argptr, "console="))
-                strcat(argptr, " console=ttyS1,115200");
-#endif
 }
 
 static void __init jmr3927_pci_setup(void)
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index ee468eaee4f7..b15adfc2d726 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -187,8 +187,6 @@ static void __init rbtx4937_clock_init(void);
 
 static void __init rbtx4927_mem_setup(void)
 {
-        char *argptr;
-
         if (TX4927_REV_PCODE() == 0x4927) {
                 rbtx4927_clock_init();
                 tx4927_setup();
@@ -213,11 +211,6 @@ static void __init rbtx4927_mem_setup(void)
         gpio_direction_output(15, 1);
 
         tx4927_sio_init(0, 0);
-#ifdef CONFIG_SERIAL_TXX9_CONSOLE
-        argptr = prom_getcmdline();
-        if (!strstr(argptr, "console="))
-                strcat(argptr, " console=ttyS0,38400");
-#endif
 }
 
 static void __init rbtx4927_clock_init(void)
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index d66509b14284..d6e70dab3bd3 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -153,7 +153,6 @@ static void __init rbtx4938_time_init(void)
 static void __init rbtx4938_mem_setup(void)
 {
         unsigned long long pcfg;
-        char *argptr;
 
         if (txx9_master_clock == 0)
                 txx9_master_clock = 25000000; /* 25MHz */
@@ -168,11 +167,6 @@ static void __init rbtx4938_mem_setup(void)
 #endif
 
         tx4938_sio_init(7372800, 0);
-#ifdef CONFIG_SERIAL_TXX9_CONSOLE
-        argptr = prom_getcmdline();
-        if (!strstr(argptr, "console="))
-                strcat(argptr, " console=ttyS0,38400");
-#endif
 
 #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
         pr_info("PIOSEL: disabling both ATA and NAND selection\n");
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index 6dc30fc827c4..16d88577f3e0 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -466,7 +466,7 @@ static inline int set_kernel_exec(unsigned long vaddr, int enable)
  * the kernel page tables containing the necessary information by tlb-mn10300.S
  */
 extern void update_mmu_cache(struct vm_area_struct *vma,
-                             unsigned long address, pte_t pte);
+                             unsigned long address, pte_t *ptep);
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mn10300/mm/mmu-context.c b/arch/mn10300/mm/mmu-context.c
index 31c9d27a75ae..36ba02191d40 100644
--- a/arch/mn10300/mm/mmu-context.c
+++ b/arch/mn10300/mm/mmu-context.c
@@ -51,9 +51,10 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
 /*
  * preemptively set a TLB entry
  */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 {
         unsigned long pteu, ptel, cnx, flags;
+        pte_t pte = *ptep;
 
         addr &= PAGE_MASK;
         ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2);
diff --git a/arch/mn10300/unit-asb2305/pci-asb2305.c b/arch/mn10300/unit-asb2305/pci-asb2305.c
index 78cd134ddf7d..d6119b879a98 100644
--- a/arch/mn10300/unit-asb2305/pci-asb2305.c
+++ b/arch/mn10300/unit-asb2305/pci-asb2305.c
@@ -31,9 +31,11 @@
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-void pcibios_align_resource(void *data, struct resource *res,
-                            resource_size_t size, resource_size_t align)
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
 {
+        resource_size_t start = res->start;
+
 #if 0
         struct pci_dev *dev = data;
 
@@ -47,14 +49,10 @@ void pcibios_align_resource(void *data, struct resource *res,
                );
 #endif
 
-        if (res->flags & IORESOURCE_IO) {
-                unsigned long start = res->start;
+        if ((res->flags & IORESOURCE_IO) && (start & 0x300))
+                start = (start + 0x3ff) & ~0x3ff;
 
-                if (start & 0x300) {
-                        start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
-        }
+        return start;
 }
 
 
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index 2cb7e75ba1c0..6d8720a0a599 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -331,12 +331,10 @@ static int __init pci_check_direct(void)
 static int __devinit is_valid_resource(struct pci_dev *dev, int idx)
 {
         unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
-        struct resource *devr = &dev->resource[idx];
+        struct resource *devr = &dev->resource[idx], *busr;
 
         if (dev->bus) {
-                for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
-                        struct resource *busr = dev->bus->resource[i];
-
+                pci_bus_for_each_resource(dev->bus, busr, i) {
                         if (!busr || (busr->flags ^ devr->flags) & type_mask)
                                 continue;
 
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 524d9352f17e..f388dc68f605 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -18,7 +18,6 @@ config PARISC
         select BUG
         select HAVE_PERF_EVENTS
         select GENERIC_ATOMIC64 if !64BIT
-        select HAVE_ARCH_TRACEHOOK
         help
           The PA-RISC microprocessor is designed by Hewlett-Packard and used
           in many of their workstations & servers (HP9000 700 and 800 series,
diff --git a/arch/parisc/include/asm/cacheflush.h b/arch/parisc/include/asm/cacheflush.h
index 7a73b615c23d..477277739da5 100644
--- a/arch/parisc/include/asm/cacheflush.h
+++ b/arch/parisc/include/asm/cacheflush.h
@@ -38,6 +38,18 @@ void flush_cache_mm(struct mm_struct *mm);
 
 #define flush_kernel_dcache_range(start,size) \
         flush_kernel_dcache_range_asm((start), (start)+(size));
+/* vmap range flushes and invalidates.  Architecturally, we don't need
+ * the invalidate, because the CPU should refuse to speculate once an
+ * area has been flushed, so invalidate is left empty */
+static inline void flush_kernel_vmap_range(void *vaddr, int size)
+{
+        unsigned long start = (unsigned long)vaddr;
+
+        flush_kernel_dcache_range_asm(start, start + size);
+}
+static inline void invalidate_kernel_vmap_range(void *vaddr, int size)
+{
+}
 
 #define flush_cache_vmap(start, end)            flush_cache_all()
 #define flush_cache_vunmap(start, end)          flush_cache_all()
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index a27d2e200fb2..01c15035e783 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -410,7 +410,7 @@ extern void paging_init (void);
 
 #define PG_dcache_dirty         PG_arch_1
 
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 /* Encode and de-code a swap entry */
 
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index b6ed34de14e1..1054baa2fc69 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -68,9 +68,9 @@ flush_cache_all_local(void)
 EXPORT_SYMBOL(flush_cache_all_local);
 
 void
-update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
-        struct page *page = pte_page(pte);
+        struct page *page = pte_page(*ptep);
 
         if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
             test_bit(PG_dcache_dirty, &page->flags)) {
diff --git a/arch/parisc/kernel/pci.c b/arch/parisc/kernel/pci.c
index f7064abc3bb6..38372e7cbb88 100644
--- a/arch/parisc/kernel/pci.c
+++ b/arch/parisc/kernel/pci.c
@@ -18,7 +18,6 @@
 
 #include <asm/io.h>
 #include <asm/system.h>
-#include <asm/cache.h>          /* for L1_CACHE_BYTES */
 #include <asm/superio.h>
 
 #define DEBUG_RESOURCES 0
@@ -123,6 +122,10 @@ static int __init pcibios_init(void)
         } else {
                 printk(KERN_WARNING "pci_bios != NULL but init() is!\n");
         }
+
+        /* Set the CLS for PCI as early as possible. */
+        pci_cache_line_size = pci_dfl_cache_line_size;
+
         return 0;
 }
 
@@ -171,7 +174,7 @@ void pcibios_set_master(struct pci_dev *dev)
         ** upper byte is PCI_LATENCY_TIMER.
         */
         pci_write_config_word(dev, PCI_CACHE_LINE_SIZE,
-                                (0x80 << 8) | (L1_CACHE_BYTES / sizeof(u32)));
+                              (0x80 << 8) | pci_cache_line_size);
 }
 
 
@@ -254,10 +257,10 @@ EXPORT_SYMBOL(pcibios_bus_to_resource);
  * Since we are just checking candidates, don't use any fields other
  * than res->start.
  */
-void pcibios_align_resource(void *data, struct resource *res,
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                 resource_size_t size, resource_size_t alignment)
 {
-        resource_size_t mask, align;
+        resource_size_t mask, align, start = res->start;
 
         DBG_RES("pcibios_align_resource(%s, (%p) [%lx,%lx]/%x, 0x%lx, 0x%lx)\n",
                 pci_name(((struct pci_dev *) data)),
@@ -269,10 +272,10 @@ void pcibios_align_resource(void *data, struct resource *res,
 
         /* Align to largest of MIN or input size */
         mask = max(alignment, align) - 1;
-        res->start += mask;
-        res->start &= ~mask;
+        start += mask;
+        start &= ~mask;
 
-        /* The caller updates the end field, we don't.  */
+        return start;
 }
 
 
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index ba3948c70072..155d571f5e26 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -58,7 +58,7 @@ config IRQ_PER_CPU
 
 config NR_IRQS
         int "Number of virtual interrupt numbers"
-        range 32 512
+        range 32 32768
         default "512"
         help
           This defines the number of virtual interrupt numbers the kernel
@@ -173,6 +173,7 @@ config PPC_OF
 
 config OF
         def_bool y
+        select OF_FLATTREE
 
 config PPC_UDBG_16550
         bool
@@ -240,6 +241,33 @@ config PPC_OF_PLATFORM_PCI
 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
         def_bool y
 
+config PPC_ADV_DEBUG_REGS
+        bool
+        depends on 40x || BOOKE
+        default y
+
+config PPC_ADV_DEBUG_IACS
+        int
+        depends on PPC_ADV_DEBUG_REGS
+        default 4 if 44x
+        default 2
+
+config PPC_ADV_DEBUG_DACS
+        int
+        depends on PPC_ADV_DEBUG_REGS
+        default 2
+
+config PPC_ADV_DEBUG_DVCS
+        int
+        depends on PPC_ADV_DEBUG_REGS
+        default 2 if 44x
+        default 0
+
+config PPC_ADV_DEBUG_DAC_RANGE
+        bool
+        depends on PPC_ADV_DEBUG_REGS && 44x
+        default y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/powerpc/boot/dts/arches.dts b/arch/powerpc/boot/dts/arches.dts
index 414ef8b7e575..30f41204acfa 100644
--- a/arch/powerpc/boot/dts/arches.dts
+++ b/arch/powerpc/boot/dts/arches.dts
@@ -60,6 +60,7 @@
                         d-cache-size = <32768>;
                         dcr-controller;
                         dcr-access-method = "native";
+                        next-level-cache = <&L2C0>;
                 };
         };
 
@@ -146,6 +147,13 @@
                         dcr-reg = <0x010 0x002>;
                 };
 
+                CRYPTO: crypto@180000 {
+                        compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
+                        reg = <4 0x00180000 0x80400>;
+                        interrupt-parent = <&UIC0>;
+                        interrupts = <0x1d 0x4>;
+                };
+
                 MAL0: mcmal {
                         compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
                         dcr-reg = <0x180 0x062>;
@@ -274,6 +282,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "sgmii";
                                 phy-map = <0xffffffff>;
                                 gpcs-address = <0x0000000a>;
@@ -302,6 +311,7 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
                                 phy-mode = "sgmii";
                                 phy-map = <0x00000000>;
                                 gpcs-address = <0x0000000b>;
@@ -331,6 +341,8 @@
                                 max-frame-size = <9000>;
                                 rx-fifo-size = <4096>;
                                 tx-fifo-size = <2048>;
+                                rx-fifo-size-gige = <16384>;
+                                tx-fifo-size-gige = <16384>; /* emac2&3 only */
                                 phy-mode = "sgmii";
                                 phy-map = <0x00000001>;
                                 gpcs-address = <0x0000000C>;
diff --git a/arch/powerpc/boot/dts/gef_ppc9a.dts b/arch/powerpc/boot/dts/gef_ppc9a.dts
index c86114e93f1e..977f260d5e64 100644
--- a/arch/powerpc/boot/dts/gef_ppc9a.dts
+++ b/arch/powerpc/boot/dts/gef_ppc9a.dts
@@ -341,6 +341,22 @@
                         device_type = "open-pic";
                 };
 
+                msi@41600 {
+                        compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+
                 global-utilities@e0000 {
                         compatible = "fsl,mpc8641-guts";
                         reg = <0xe0000 0x1000>;
diff --git a/arch/powerpc/boot/dts/gef_sbc310.dts b/arch/powerpc/boot/dts/gef_sbc310.dts
index 820c2b355ab1..8e4efff3bda1 100644
--- a/arch/powerpc/boot/dts/gef_sbc310.dts
+++ b/arch/powerpc/boot/dts/gef_sbc310.dts
@@ -32,6 +32,7 @@
                 serial0 = &serial0;
                 serial1 = &serial1;
                 pci0 = &pci0;
+                pci1 = &pci1;
         };
 
         cpus {
@@ -338,6 +339,22 @@
                         device_type = "open-pic";
                 };
 
+                msi@41600 {
+                        compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+
                 global-utilities@e0000 {
                         compatible = "fsl,mpc8641-guts";
                         reg = <0xe0000 0x1000>;
@@ -358,7 +375,7 @@
                 clock-frequency = <33333333>;
                 interrupt-parent = <&mpic>;
                 interrupts = <0x18 0x2>;
-                interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+                interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
                 interrupt-map = <
                         0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
                         0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
index 30911adefc8e..bb7060078fb4 100644
--- a/arch/powerpc/boot/dts/gef_sbc610.dts
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -75,14 +75,48 @@
                 interrupts = <19 2>;
                 interrupt-parent = <&mpic>;
 
-                ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
-                          1 0 0xe8000000 0x08000000     // Paged Flash 0
-                          2 0 0xe0000000 0x08000000     // Paged Flash 1
-                          3 0 0xfc100000 0x00020000     // NVRAM
-                          4 0 0xfc000000 0x00008000     // FPGA
-                          5 0 0xfc008000 0x00008000     // AFIX FPGA
-                          6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
-                          7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
+                ranges = <0 0 0xff000000 0x01000000     // 16MB Boot flash
+                          1 0 0xe8000000 0x08000000     // Paged Flash 0
+                          2 0 0xe0000000 0x08000000     // Paged Flash 1
+                          3 0 0xfc100000 0x00020000     // NVRAM
+                          4 0 0xfc000000 0x00008000     // FPGA
+                          5 0 0xfc008000 0x00008000     // AFIX FPGA
+                          6 0 0xfd000000 0x00800000     // IO FPGA (8-bit)
+                          7 0 0xfd800000 0x00800000>;   // IO FPGA (32-bit)
+
+                /* flash@0,0 is a mirror of part of the memory in flash@1,0
+                flash@0,0 {
+                        compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
+                        reg = <0x0 0x0 0x1000000>;
+                        bank-width = <4>;
+                        device-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                label = "firmware";
+                                reg = <0x0 0x1000000>;
+                                read-only;
+                        };
+                };
+                */
+
+                flash@1,0 {
+                        compatible = "gef,sbc610-paged-flash", "cfi-flash";
+                        reg = <0x1 0x0 0x8000000>;
+                        bank-width = <4>;
+                        device-width = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        partition@0 {
+                                label = "user";
+                                reg = <0x0 0x7800000>;
+                        };
+                        partition@7800000 {
+                                label = "firmware";
+                                reg = <0x7800000 0x800000>;
+                                read-only;
+                        };
+                };
 
                 nvram@3,0 {
                         device_type = "nvram";
@@ -305,6 +339,22 @@
                         device_type = "open-pic";
                 };
 
+                msi@41600 {
+                        compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
+                        reg = <0x41600 0x80>;
+                        msi-available-ranges = <0 0x100>;
+                        interrupts = <
+                                0xe0 0
+                                0xe1 0
+                                0xe2 0
+                                0xe3 0
+                                0xe4 0
+                                0xe5 0
+                                0xe6 0
+                                0xe7 0>;
+                        interrupt-parent = <&mpic>;
+                };
+
                 global-utilities@e0000 {
                         compatible = "fsl,mpc8641-guts";
                         reg = <0xe0000 0x1000>;
diff --git a/arch/powerpc/boot/dts/glacier.dts b/arch/powerpc/boot/dts/glacier.dts
index f6f618939293..d62a4fb6f93c 100644
--- a/arch/powerpc/boot/dts/glacier.dts
+++ b/arch/powerpc/boot/dts/glacier.dts
@@ -1,7 +1,7 @@
 /*
  * Device Tree Source for AMCC Glacier (460GT)
  *
- * Copyright 2008 DENX Software Engineering, Stefan Roese <sr@denx.de>
+ * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without
@@ -42,6 +42,7 @@
                         d-cache-size = <32768>;
                         dcr-controller;
                         dcr-access-method = "native";
+                        next-level-cache = <&L2C0>;
                 };
         };
 
@@ -106,6 +107,16 @@
                 dcr-reg = <0x00c 0x002>;
         };
 
+        L2C0: l2c {
+                compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
+                dcr-reg = <0x020 0x008          /* Internal SRAM DCR's */
+                           0x030 0x008>;        /* L2 cache DCR's */
+                cache-line-size = <32>;         /* 32 bytes */
+                cache-size = <262144>;          /* L2, 256K */
+                interrupt-parent = <&UIC1>;
+                interrupts = <11 1>;
+        };
+
         plb {
                 compatible = "ibm,plb-460gt", "ibm,plb4";
                 #address-cells = <2>;
@@ -118,6 +129,13 @@
                         dcr-reg = <0x010 0x002>;
                 };
 
+                CRYPTO: crypto@180000 {
+                        compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
+                        reg = <4 0x00180000 0x80400>;
+                        interrupt-parent = <&UIC0>;
+                        interrupts = <0x1d 0x4>;
+                };
+
                 MAL0: mcmal {
                         compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
                         dcr-reg = <0x180 0x062>;
@@ -186,6 +204,29 @@
                                                 reg = <0x03fa0000 0x00060000>;
                                         };
                                 };
+
+                                ndfc@3,0 {
+                                        compatible = "ibm,ndfc";
+                                        reg = <0x00000003 0x00000000 0x00002000>;
+                                        ccr = <0x00001000>;
+                                        bank-settings = <0x80002222>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+
+                                        nand {
+                                                #address-cells = <1>;
+                                                #size-cells = <1>;
+
+                                                partition@0 {
+                                                        label = "u-boot";
+                                                        reg = <0x00000000 0x00100000>;
+                                                };
+                                                partition@100000 {
+                                                        label = "user";
+                                                        reg = <0x00000000 0x03f00000>;
+                                                };
+                                        };
+                                };
                         };
 
                         UART0: serial@ef600300 {
@@ -237,6 +278,20 @@
                                 reg = <0xef600700 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x2 0x4>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                rtc@68 {
+                                        compatible = "stm,m41t80";
+                                        reg = <0x68>;
+                                        interrupt-parent = <&UIC2>;
+                                        interrupts = <0x19 0x8>;
+                                };
+                                sttm@48 {
+                                        compatible = "ad,ad7414";
+                                        reg = <0x48>;
+                                        interrupt-parent = <&UIC1>;
+                                        interrupts = <0x14 0x8>;
+                                };
                         };
 
                         IIC1: i2c@ef600800 {
@@ -275,7 +330,7 @@
 
                         EMAC0: ethernet@ef600e00 {
                                 device_type = "network";
-                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                compatible = "ibm,emac-460gt", "ibm,emac4sync";
                                 interrupt-parent = <&EMAC0>;
                                 interrupts = <0x0 0x1>;
                                 #interrupt-cells = <1>;
@@ -283,7 +338,7 @@
                                 #size-cells = <0>;
                                 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
                                                  /*Wake*/   0x1 &UIC2 0x14 0x4>;
-                                reg = <0xef600e00 0x00000074>;
+                                reg = <0xef600e00 0x000000c4>;
                                 local-mac-address = [000000000000]; /* Filled in by U-Boot */
                                 mal-device = <&MAL0>;
                                 mal-tx-channel = <0>;
@@ -305,7 +360,7 @@
 
                         EMAC1: ethernet@ef600f00 {
                                 device_type = "network";
-                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                compatible = "ibm,emac-460gt", "ibm,emac4sync";
                                 interrupt-parent = <&EMAC1>;
                                 interrupts = <0x0 0x1>;
                                 #interrupt-cells = <1>;
@@ -313,7 +368,7 @@
                                 #size-cells = <0>;
                                 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
                                                  /*Wake*/   0x1 &UIC2 0x15 0x4>;
-                                reg = <0xef600f00 0x00000074>;
+                                reg = <0xef600f00 0x000000c4>;
                                 local-mac-address = [000000000000]; /* Filled in by U-Boot */
                                 mal-device = <&MAL0>;
                                 mal-tx-channel = <1>;
@@ -336,7 +391,7 @@
 
                         EMAC2: ethernet@ef601100 {
                                 device_type = "network";
-                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                compatible = "ibm,emac-460gt", "ibm,emac4sync";
                                 interrupt-parent = <&EMAC2>;
                                 interrupts = <0x0 0x1>;
                                 #interrupt-cells = <1>;
@@ -344,7 +399,7 @@
                                 #size-cells = <0>;
                                 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
                                                  /*Wake*/   0x1 &UIC2 0x16 0x4>;
-                                reg = <0xef601100 0x00000074>;
+                                reg = <0xef601100 0x000000c4>;
                                 local-mac-address = [000000000000]; /* Filled in by U-Boot */
                                 mal-device = <&MAL0>;
                                 mal-tx-channel = <2>;
@@ -366,7 +421,7 @@
 
                         EMAC3: ethernet@ef601200 {
                                 device_type = "network";
-                                compatible = "ibm,emac-460gt", "ibm,emac4";
+                                compatible = "ibm,emac-460gt", "ibm,emac4sync";
                                 interrupt-parent = <&EMAC3>;
                                 interrupts = <0x0 0x1>;
                                 #interrupt-cells = <1>;
@@ -374,7 +429,7 @@
                                 #size-cells = <0>;
                                 interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4
                                                  /*Wake*/   0x1 &UIC2 0x17 0x4>;
-                                reg = <0xef601200 0x00000074>;
+                                reg = <0xef601200 0x000000c4>;
                                 local-mac-address = [000000000000]; /* Filled in by U-Boot */
                                 mal-device = <&MAL0>;
                                 mal-tx-channel = <3>;
@@ -414,6 +469,7 @@
                          * later cannot be changed
                          */
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
+                                  0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
                                   0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
 
                         /* Inbound 2GB range starting at 0 */
@@ -444,6 +500,7 @@
                          * later cannot be changed
                          */
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
+                                  0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
 
                         /* Inbound 2GB range starting at 0 */
@@ -485,6 +542,7 @@
                          * later cannot be changed
                          */
                         ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
+                                  0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
                                   0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
 
                         /* Inbound 2GB range starting at 0 */
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 8f345de960cd..8cf2c0c88c05 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -156,7 +156,7 @@
                         compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
                         #address-cells = <1>;
                         #size-cells = <1>;
-                        ranges = <0x00000000 0x00000004 0xe0000000 0x20000000>;
+                        ranges = <0xe0000000 0x00000004 0xe0000000 0x20000000>;
                         clock-frequency = <0>; /* Filled in by zImage */
 
                         EBC0: ebc {
@@ -165,14 +165,47 @@
                                 #address-cells = <2>;
                                 #size-cells = <1>;
                                 clock-frequency = <0>; /* Filled in by zImage */
+                                /* ranges property is supplied by U-Boot */
                                 interrupts = <0x5 0x1>;
                                 interrupt-parent = <&UIC1>;
+
+                                nor_flash@0,0 {
+                                        compatible = "cfi-flash";
+                                        bank-width = <2>;
+                                        reg = <0x00000000 0x00000000 0x01000000>;
+                                        #address-cells = <1>;
+                                        #size-cells = <1>;
+                                        partition@0 {
+                                                label = "kernel";
+                                                reg = <0x00000000 0x001e0000>;
+                                        };
+                                        partition@1e0000 {
+                                                label = "dtb";
+                                                reg = <0x001e0000 0x00020000>;
+                                        };
+                                        partition@200000 {
+                                                label = "root";
+                                                reg = <0x00200000 0x00200000>;
+                                        };
+                                        partition@400000 {
+                                                label = "user";
+                                                reg = <0x00400000 0x00b60000>;
+                                        };
+                                        partition@f60000 {
+                                                label = "env";
+                                                reg = <0x00f60000 0x00040000>;
+                                        };
+                                        partition@fa0000 {
+                                                label = "u-boot";
+                                                reg = <0x00fa0000 0x00060000>;
+                                        };
+                                };
                         };
 
-                        UART0: serial@10000200 {
+                        UART0: serial@f0000200 {
                                 device_type = "serial";
                                 compatible = "ns16550";
-                                reg = <0x10000200 0x00000008>;
+                                reg = <0xf0000200 0x00000008>;
                                 virtual-reg = <0xa0000200>;
                                 clock-frequency = <0>; /* Filled in by zImage */
                                 current-speed = <115200>;
@@ -180,10 +213,10 @@
                                 interrupts = <0x0 0x4>;
                         };
 
-                        UART1: serial@10000300 {
+                        UART1: serial@f0000300 {
                                 device_type = "serial";
                                 compatible = "ns16550";
-                                reg = <0x10000300 0x00000008>;
+                                reg = <0xf0000300 0x00000008>;
                                 virtual-reg = <0xa0000300>;
                                 clock-frequency = <0>;
                                 current-speed = <0>;
@@ -192,10 +225,10 @@
                         };
 
 
-                        UART2: serial@10000600 {
+                        UART2: serial@f0000600 {
                                 device_type = "serial";
                                 compatible = "ns16550";
-                                reg = <0x10000600 0x00000008>;
+                                reg = <0xf0000600 0x00000008>;
                                 virtual-reg = <0xa0000600>;
                                 clock-frequency = <0>;
                                 current-speed = <0>;
@@ -203,27 +236,27 @@
                                 interrupts = <0x5 0x4>;
                         };
 
-                        IIC0: i2c@10000400 {
+                        IIC0: i2c@f0000400 {
                                 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
-                                reg = <0x10000400 0x00000014>;
+                                reg = <0xf0000400 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x2 0x4>;
                         };
 
-                        IIC1: i2c@10000500 {
+                        IIC1: i2c@f0000500 {
                                 compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
-                                reg = <0x10000500 0x00000014>;
+                                reg = <0xf0000500 0x00000014>;
                                 interrupt-parent = <&UIC0>;
                                 interrupts = <0x3 0x4>;
                         };
 
-                        EMAC0: ethernet@10000800 {
+                        EMAC0: ethernet@f0000800 {
                                 linux,network-index = <0x0>;
                                 device_type = "network";
                                 compatible = "ibm,emac-440spe", "ibm,emac4";
                                 interrupt-parent = <&UIC1>;
                                 interrupts = <0x1c 0x4 0x1d 0x4>;
-                                reg = <0x10000800 0x00000074>;
+                                reg = <0xf0000800 0x00000074>;
                                 local-mac-address = [000000000000];
                                 mal-device = <&MAL0>;
                                 mal-tx-channel = <0>;
@@ -248,11 +281,11 @@
                         primary;
                         large-inbound-windows;
                         enable-msi-hole;
-                        reg = <0x0000000c 0x0ec00000   0x00000008       /* Config space access */
-                               0x00000000 0x00000000 0x00000000         /* no IACK cycles */
-                               0x0000000c 0x0ed00000   0x00000004   /* Special cycles */
-                               0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
-                               0x0000000c 0x0ec80100  0x000000fc>;      /* Internal messaging registers */
+                        reg = <0x0000000c 0x0ec00000 0x00000008   /* Config space access */
+                               0x00000000 0x00000000 0x00000000   /* no IACK cycles */
+                               0x0000000c 0x0ed00000 0x00000004   /* Special cycles */
+                               0x0000000c 0x0ec80000 0x00000100   /* Internal registers */
+                               0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
 
                         /* Outbound ranges, one memory and one IO,
                          * later cannot be changed
@@ -453,6 +486,6 @@
         };
 
         chosen {
-                linux,stdout-path = "/plb/opb/serial@10000200";
+                linux,stdout-path = "/plb/opb/serial@f0000200";
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c353dac33416..c9ef6bbe26cf 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -62,17 +62,12 @@
                 interrupt-parent = < &ipic >;
                 #address-cells = <1>;
                 #size-cells = <1>;
-                bank-width = <1>;
                 // ADS has two Hynix 512MB Nand flash chips in a single
-                // stacked package .
+                // stacked package.
                 chips = <2>;
-                nand0@0 {
-                        label = "nand0";
-                        reg = <0x00000000 0x02000000>;  // first 32 MB of chip 0
-                };
-                nand1@20000000 {
-                        label = "nand1";
-                        reg = <0x20000000 0x02000000>;  // first 32 MB of chip 1
+                nand@0 {
+                        label = "nand";
+                        reg = <0x00000000 0x40000000>;  // 512MB + 512MB
                 };
         };
 
@@ -166,6 +161,11 @@
                         interrupt-parent = < &ipic >;
                 };
 
+                reset@e00 {     // Reset module
+                        compatible = "fsl,mpc5121-reset";
+                        reg = <0xe00 0x100>;
+                };
+
                 clock@f00 {     // Clock control
                         compatible = "fsl,mpc5121-clock";
                         reg = <0xf00 0x100>;
@@ -185,17 +185,15 @@
                         interrupt-parent = < &ipic >;
                 };
 
-                mscan@1300 {
+                can@1300 {
                         compatible = "fsl,mpc5121-mscan";
-                        cell-index = <0>;
                         interrupts = <12 0x8>;
                         interrupt-parent = < &ipic >;
                         reg = <0x1300 0x80>;
                 };
 
-                mscan@1380 {
+                can@1380 {
                         compatible = "fsl,mpc5121-mscan";
-                        cell-index = <1>;
                         interrupts = <13 0x8>;
                         interrupt-parent = < &ipic >;
                         reg = <0x1380 0x80>;
@@ -205,17 +203,31 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
-                        cell-index = <0>;
                         reg = <0x1700 0x20>;
                         interrupts = <9 0x8>;
                         interrupt-parent = < &ipic >;
+                        fsl,preserve-clocking;
+
+                        hwmon@4a {
+                                compatible = "adi,ad7414";
+                                reg = <0x4a>;
+                        };
+
+                        eeprom@50 {
+                                compatible = "at,24c32";
+                                reg = <0x50>;
+                        };
+
+                        rtc@68 {
+                                compatible = "stm,m41t62";
+                                reg = <0x68>;
+                        };
                 };
 
                 i2c@1720 {
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
-                        cell-index = <1>;
                         reg = <0x1720 0x20>;
                         interrupts = <10 0x8>;
                         interrupt-parent = < &ipic >;
@@ -225,7 +237,6 @@
                         #address-cells = <1>;
                         #size-cells = <0>;
                         compatible = "fsl,mpc5121-i2c", "fsl-i2c";
-                        cell-index = <2>;
                         reg = <0x1740 0x20>;
                         interrupts = <11 0x8>;
                         interrupt-parent = < &ipic >;
@@ -244,7 +255,7 @@
                 };
 
                 display@2100 {
-                        compatible = "fsl,mpc5121-diu", "fsl-diu";
+                        compatible = "fsl,mpc5121-diu";
                         reg = <0x2100 0x100>;
                         interrupts = <64 0x8>;
                         interrupt-parent = < &ipic >;
@@ -277,7 +288,7 @@
 
                 // USB1 using external ULPI PHY
                 //usb@3000 {
-                //      compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
+                //      compatible = "fsl,mpc5121-usb2-dr";
                 //      reg = <0x3000 0x1000>;
                 //      #address-cells = <1>;
                 //      #size-cells = <0>;
@@ -285,12 +296,11 @@
                 //      interrupts = <43 0x8>;
                 //      dr_mode = "otg";
                 //      phy_type = "ulpi";
-                //      port1;
                 //};
 
                 // USB0 using internal UTMI PHY
                 usb@4000 {
-                        compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";
+                        compatible = "fsl,mpc5121-usb2-dr";
                         reg = <0x4000 0x1000>;
                         #address-cells = <1>;
                         #size-cells = <0>;
@@ -298,7 +308,8 @@
                         interrupts = <44 0x8>;
                         dr_mode = "otg";
                         phy_type = "utmi_wide";
-                        port0;
+                        fsl,invert-drvvbus;
+                        fsl,invert-pwr-fault;
                 };
 
                 // IO control
@@ -365,7 +376,7 @@
                 };
 
                 dma@14000 {
-                        compatible = "fsl,mpc5121-dma2";
+                        compatible = "fsl,mpc5121-dma";
                         reg = <0x14000 0x1800>;
                         interrupts = <65 0x8>;
                         interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts
index 6d892ba74e55..92fb17876e7d 100644
--- a/arch/powerpc/boot/dts/mpc8568mds.dts
+++ b/arch/powerpc/boot/dts/mpc8568mds.dts
@@ -54,9 +54,52 @@
                 reg = <0x0 0x10000000>;
         };
 
-        bcsr@f8000000 {
-                compatible = "fsl,mpc8568mds-bcsr";
-                reg = <0xf8000000 0x8000>;
+        localbus@e0005000 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus",
+                             "simple-bus";
+                reg = <0xe0005000 0x1000>;
+
+                ranges = <0x0 0x0 0xfe000000 0x02000000
+                          0x1 0x0 0xf8000000 0x00008000
+                          0x2 0x0 0xf0000000 0x04000000
+                          0x4 0x0 0xf8008000 0x00008000
+                          0x5 0x0 0xf8010000 0x00008000>;
+
+                nor@0,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "cfi-flash";
+                        reg = <0x0 0x0 0x02000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                };
+
+                bcsr@1,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,mpc8568mds-bcsr";
+                        reg = <1 0 0x8000>;
+                        ranges = <0 1 0 0x8000>;
+
+                        bcsr5: gpio-controller@11 {
+                                #gpio-cells = <2>;
+                                compatible = "fsl,mpc8568mds-bcsr-gpio";
+                                reg = <0x5 0x1>;
+                                gpio-controller;
+                        };
+                };
+
+                pib@4,0 {
+                        compatible = "fsl,mpc8568mds-pib";
+                        reg = <4 0 0x8000>;
+                };
+
+                pib@5,0 {
+                        compatible = "fsl,mpc8568mds-pib";
+                        reg = <5 0 0x8000>;
+                };
         };
 
         soc8568@e0000000 {
@@ -610,4 +653,20 @@
                 sleep = <&pmc 0x00080000   /* controller */
                          &pmc 0x00040000>; /* message unit */
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                green {
+                        gpios = <&bcsr5 1 0>;
+                };
+
+                amber {
+                        gpios = <&bcsr5 2 0>;
+                };
+
+                red {
+                        gpios = <&bcsr5 3 0>;
+                };
+        };
 };
diff --git a/arch/powerpc/configs/44x/katmai_defconfig b/arch/powerpc/configs/44x/katmai_defconfig
index dec901f9cc84..af244e1d255e 100644
--- a/arch/powerpc/configs/44x/katmai_defconfig
+++ b/arch/powerpc/configs/44x/katmai_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.33-rc1
-# Mon Jan  4 14:55:34 2010
+# Linux kernel version: 2.6.33-rc5
+# Tue Jan 26 14:40:58 2010
 #
 # CONFIG_PPC64 is not set
 
@@ -106,6 +106,7 @@ CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_GZIP=y
 # CONFIG_RD_BZIP2 is not set
 # CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
 # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
@@ -442,7 +443,90 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
 CONFIG_CONNECTOR=y
 CONFIG_PROC_EVENTS=y
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 CONFIG_OF_DEVICE=y
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
@@ -500,7 +584,7 @@ CONFIG_HAVE_IDE=y
 #
 
 #
-# See the help texts for more information.
+# The newer stack is recommended.
 #
 # CONFIG_FIREWIRE is not set
 # CONFIG_IEEE1394 is not set
@@ -763,7 +847,6 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
 # CONFIG_EXT4_FS is not set
-CONFIG_EXT4_USE_FOR_EXT23=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
@@ -820,6 +903,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 CONFIG_CRAMFS=y
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
diff --git a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
index a85f927bf225..622d84f48aba 100644
--- a/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
+++ b/arch/powerpc/configs/86xx/gef_ppc9a_defconfig
@@ -1557,7 +1557,52 @@ CONFIG_RTC_DRV_RX8581=y
 #
 # TI VLYNQ
 #
-# CONFIG_STAGING is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ET131X is not set
+# CONFIG_ME4000 is not set
+# CONFIG_MEILHAUS is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_ALTERA_PCIE_CHDMA is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_B3DFG is not set
+# CONFIG_IDE_PHISON is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_HECI is not set
+# CONFIG_USB_CPC is not set
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_HYPERV_STORAGE is not set
+# CONFIG_HYPERV_BLOCK is not set
+# CONFIG_HYPERV_NET is not set
+CONFIG_VME_BUS=y
+
+#
+# VME Bridge Drivers
+#
+CONFIG_VME_TSI148=y
+
+#
+# VME Device Drivers
+#
+# CONFIG_VME_USER is not set
 
 #
 # File systems
diff --git a/arch/powerpc/configs/86xx/gef_sbc610_defconfig b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
index 4554d9bb03e5..62c2b81a4a8f 100644
--- a/arch/powerpc/configs/86xx/gef_sbc610_defconfig
+++ b/arch/powerpc/configs/86xx/gef_sbc610_defconfig
@@ -265,7 +265,7 @@ CONFIG_MMIO_NVRAM=y
 #
 # Kernel options
 #
-# CONFIG_HIGHMEM is not set
+CONFIG_HIGHMEM=y
 CONFIG_TICK_ONESHOT=y
 # CONFIG_NO_HZ is not set
 CONFIG_HIGH_RES_TIMERS=y
@@ -651,7 +651,7 @@ CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_OF_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
 # CONFIG_MTD_AR7_PARTS is not set
 
 #
@@ -671,13 +671,9 @@ CONFIG_MTD_BLOCK=y
 # RAM/ROM/Flash chip drivers
 #
 CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_JEDECPROBE=y
 CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_NOSWAP is not set
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_LE_BYTE_SWAP=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
 CONFIG_MTD_MAP_BANK_WIDTH_1=y
 CONFIG_MTD_MAP_BANK_WIDTH_2=y
 CONFIG_MTD_MAP_BANK_WIDTH_4=y
@@ -688,7 +684,6 @@ CONFIG_MTD_CFI_I1=y
 CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_CFI_I4 is not set
 # CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 # CONFIG_MTD_CFI_STAA is not set
@@ -1652,7 +1647,44 @@ CONFIG_RTC_DRV_RX8581=y
 #
 # TI VLYNQ
 #
-# CONFIG_STAGING is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_ET131X is not set
+# CONFIG_ME4000 is not set
+# CONFIG_MEILHAUS is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_ALTERA_PCIE_CHDMA is not set
+# CONFIG_INPUT_MIMIO is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+# CONFIG_ANDROID is not set
+# CONFIG_DST is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_B3DFG is not set
+# CONFIG_IDE_PHISON is not set
+# CONFIG_PLAN9AUTH is not set
+# CONFIG_HECI is not set
+# CONFIG_VT6655 is not set
+# CONFIG_USB_CPC is not set
+# CONFIG_RDC_17F3101X is not set
+CONFIG_VME_BUS=y
+
+#
+# VME Bridge Drivers
+#
+# CONFIG_VME_CA91CX42 is not set
+CONFIG_VME_TSI148=y
+
+#
+# VME Device Drivers
+#
+# CONFIG_VME_USER is not set
 
 #
 # File systems
@@ -1729,7 +1761,17 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1874,6 +1916,7 @@ CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
diff --git a/arch/powerpc/configs/mpc512x_defconfig b/arch/powerpc/configs/mpc512x_defconfig
new file mode 100644
index 000000000000..a04727295d46
--- /dev/null
+++ b/arch/powerpc/configs/mpc512x_defconfig
@@ -0,0 +1,1694 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.33-rc6
+# Fri Feb  5 11:48:29 2010
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_PPC_BOOK3S_32=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_BOOK3S=y
+CONFIG_6xx=y
+CONFIG_PPC_FPU=y
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+CONFIG_PPC_HAVE_PMU_SUPPORT=y
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_NR_IRQS=512
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DTC=y
+CONFIG_DEFAULT_UIMAGE=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+# CONFIG_FREEZER is not set
+
+#
+# Platform support
+#
+# CONFIG_PPC_CHRP is not set
+CONFIG_PPC_MPC512x=y
+CONFIG_PPC_MPC5121=y
+CONFIG_MPC5121_ADS=y
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_EMBEDDED6xx is not set
+# CONFIG_AMIGAONE is not set
+CONFIG_PPC_OF_BOOT_TRAMPOLINE=y
+CONFIG_IPIC=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
+# CONFIG_SWIOTLB is not set
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_MAX_ACTIVE_REGIONS=32
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_MIGRATION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+# CONFIG_PPC_256K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_FSL_SOC=y
+CONFIG_PPC_PCI_CHOICE=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DOMAINS is not set
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=y
+CONFIG_CAN_DEV=y
+# CONFIG_CAN_CALC_BITTIMING is not set
+CONFIG_CAN_MSCAN=y
+# CONFIG_CAN_SJA1000 is not set
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_EMS_USB is not set
+CONFIG_CAN_DEBUG_DEVICES=y
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CFI_AMDSTD=y
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+CONFIG_MTD_ROM=y
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+CONFIG_MTD_NAND_MPC5121_NFC=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+CONFIG_OF_MDIO=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_XIP=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_ETHOC is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_XILINX_EMACLITE is not set
+CONFIG_FS_ENET=y
+CONFIG_FS_ENET_MPC5121_FEC=y
+CONFIG_FS_ENET_HAS_FEC=y
+CONFIG_FS_ENET_MDIO_FEC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_XILINX_XPS_PS2 is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_MPC52xx=y
+CONFIG_SERIAL_MPC52xx_CONSOLE=y
+CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
+# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_REGULATOR is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+CONFIG_VIDEO_ADV_DEBUG=y
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+CONFIG_VIDEO_IR_I2C=y
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA7110 is not set
+CONFIG_VIDEO_SAA711X=y
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_OF is not set
+# CONFIG_FB_VGA16 is not set
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_FSL_DIU=y
+# CONFIG_FB_IBM_GXT4500 is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_LOGO is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+# CONFIG_DRAGONRISE_FF is not set
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_SMARTJOYPLUS=y
+# CONFIG_SMARTJOYPLUS_FF is not set
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+# CONFIG_THRUSTMASTER_FF is not set
+CONFIG_HID_ZEROPLUS=y
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+# CONFIG_XPS_USB_HCD_XILINX is not set
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PPC_OF=y
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_GENERIC is not set
+CONFIG_RTC_DRV_MPC5121=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_FSL_DMA is not set
+CONFIG_MPC512X_DMA=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_PPC_DISABLE_WERROR is not set
+CONFIG_PPC_WERROR=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_IRQSTACKS is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_PPC_CLOCK=y
+CONFIG_PPC_LIB_RHEAP=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/powerpc/configs/ppc64_defconfig b/arch/powerpc/configs/ppc64_defconfig
index 7b3804a6e363..b5b259960794 100644
--- a/arch/powerpc/configs/ppc64_defconfig
+++ b/arch/powerpc/configs/ppc64_defconfig
@@ -137,8 +137,9 @@ CONFIG_TRACEPOINTS=y
 CONFIG_MARKERS=y
 CONFIG_OPROFILE=y
 CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
+CONFIG_KPROBES=y
 CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_KRETPROBES=y
 CONFIG_HAVE_IOREMAP_PROT=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
@@ -191,6 +192,7 @@ CONFIG_SCANLOG=m
 CONFIG_LPARCFG=y
 CONFIG_PPC_SMLPAR=y
 CONFIG_CMM=y
+CONFIG_DTL=y
 CONFIG_PPC_ISERIES=y
 
 #
@@ -328,9 +330,10 @@ CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
 CONFIG_KEXEC=y
 # CONFIG_PHYP_DUMP is not set
 CONFIG_IRQ_ALL_CPUS=y
-# CONFIG_NUMA is not set
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=8
+CONFIG_MAX_ACTIVE_REGIONS=256
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_DEFAULT=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
@@ -339,6 +342,7 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
 CONFIG_SPARSEMEM_MANUAL=y
 CONFIG_SPARSEMEM=y
+CONFIG_NEED_MULTIPLE_NODES=y
 CONFIG_HAVE_MEMORY_PRESENT=y
 CONFIG_SPARSEMEM_EXTREME=y
 CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
@@ -354,11 +358,12 @@ CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_UNEVICTABLE_LRU=y
+CONFIG_NODES_SPAN_OTHER_NODES=y
 CONFIG_ARCH_MEMORY_PROBE=y
 CONFIG_PPC_HAS_HASH_64K=y
 # CONFIG_PPC_64K_PAGES is not set
 CONFIG_FORCE_MAX_ZONEORDER=13
-# CONFIG_SCHED_SMT is not set
+CONFIG_SCHED_SMT=y
 CONFIG_PROC_DEVICETREE=y
 # CONFIG_CMDLINE_BOOL is not set
 CONFIG_EXTRA_TARGETS=""
@@ -790,12 +795,12 @@ CONFIG_SCSI_IPR=y
 CONFIG_SCSI_IPR_TRACE=y
 CONFIG_SCSI_IPR_DUMP=y
 # CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
+CONFIG_SCSI_QLA_FC=m
 # CONFIG_SCSI_QLA_ISCSI is not set
 CONFIG_SCSI_LPFC=m
 # CONFIG_SCSI_DC395x is not set
 # CONFIG_SCSI_DC390T is not set
-CONFIG_SCSI_DEBUG=m
+# CONFIG_SCSI_DEBUG is not set
 # CONFIG_SCSI_SRP is not set
 # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
 # CONFIG_SCSI_DH is not set
@@ -867,9 +872,8 @@ CONFIG_MD_AUTODETECT=y
 CONFIG_MD_LINEAR=y
 CONFIG_MD_RAID0=y
 CONFIG_MD_RAID1=y
-CONFIG_MD_RAID10=y
-CONFIG_MD_RAID456=y
-CONFIG_MD_RAID5_RESHAPE=y
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
 CONFIG_MD_MULTIPATH=m
 CONFIG_MD_FAULTY=m
 CONFIG_BLK_DEV_DM=y
@@ -984,7 +988,7 @@ CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
-# CONFIG_E1000E is not set
+CONFIG_E1000E=m
 # CONFIG_IP1000 is not set
 # CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
@@ -1006,19 +1010,19 @@ CONFIG_GELIC_WIRELESS=y
 # CONFIG_ATL1E is not set
 # CONFIG_JME is not set
 CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T3=m
 CONFIG_EHEA=m
 # CONFIG_ENIC is not set
-# CONFIG_IXGBE is not set
+CONFIG_IXGBE=m
 CONFIG_IXGB=m
-# CONFIG_S2IO is not set
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
+CONFIG_S2IO=m
+CONFIG_MYRI10GE=m
+CONFIG_NETXEN_NIC=m
 # CONFIG_NIU is not set
 CONFIG_PASEMI_MAC=y
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_CORE=m
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
@@ -1169,7 +1173,7 @@ CONFIG_SERIAL_TXX9=y
 CONFIG_HAS_TXX9_SERIAL=y
 CONFIG_SERIAL_TXX9_NR_UARTS=6
 CONFIG_SERIAL_TXX9_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
+CONFIG_SERIAL_JSM=m
 # CONFIG_SERIAL_OF_PLATFORM is not set
 CONFIG_UNIX98_PTYS=y
 CONFIG_LEGACY_PTYS=y
@@ -1586,7 +1590,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
-# CONFIG_USB_MON is not set
+CONFIG_USB_MON=m
 # CONFIG_USB_WUSB is not set
 # CONFIG_USB_WUSB_CBAF is not set
 
@@ -1686,21 +1690,22 @@ CONFIG_USB_APPLEDISPLAY=m
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_INFINIBAND=m
-# CONFIG_INFINIBAND_USER_MAD is not set
-# CONFIG_INFINIBAND_USER_ACCESS is not set
+CONFIG_INFINIBAND_USER_MAD=m
+CONFIG_INFINIBAND_USER_ACCESS=m
+CONFIG_INFINIBAND_USER_MEM=y
 CONFIG_INFINIBAND_ADDR_TRANS=y
 CONFIG_INFINIBAND_MTHCA=m
 CONFIG_INFINIBAND_MTHCA_DEBUG=y
-# CONFIG_INFINIBAND_IPATH is not set
+CONFIG_INFINIBAND_IPATH=m
 CONFIG_INFINIBAND_EHCA=m
 # CONFIG_INFINIBAND_AMSO1100 is not set
-# CONFIG_MLX4_INFINIBAND is not set
+CONFIG_MLX4_INFINIBAND=m
 # CONFIG_INFINIBAND_NES is not set
 CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_CM is not set
+CONFIG_INFINIBAND_IPOIB_CM=y
 CONFIG_INFINIBAND_IPOIB_DEBUG=y
 # CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
-# CONFIG_INFINIBAND_SRP is not set
+CONFIG_INFINIBAND_SRP=m
 CONFIG_INFINIBAND_ISER=m
 CONFIG_EDAC=y
 
@@ -1798,7 +1803,7 @@ CONFIG_REISERFS_FS=y
 CONFIG_REISERFS_FS_XATTR=y
 CONFIG_REISERFS_FS_POSIX_ACL=y
 CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=y
+CONFIG_JFS_FS=m
 CONFIG_JFS_POSIX_ACL=y
 CONFIG_JFS_SECURITY=y
 # CONFIG_JFS_DEBUG is not set
@@ -1811,14 +1816,22 @@ CONFIG_XFS_POSIX_ACL=y
 # CONFIG_XFS_RT is not set
 # CONFIG_XFS_DEBUG is not set
 # CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
+CONFIG_OCFS2_FS=m
+CONFIG_OCFS2_FS_O2CB=m
+CONFIG_OCFS2_FS_STATS=y
+CONFIG_OCFS2_DEBUG_MASKLOG=y
+# CONFIG_OCFS2_DEBUG_FS is not set
+# CONFIG_OCFS2_COMPAT_JBD is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_NILFS2_FS=m
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
+CONFIG_FUSE_FS=m
 
 #
 # CD-ROM/DVD Filesystems
@@ -1851,7 +1864,7 @@ CONFIG_TMPFS=y
 # CONFIG_TMPFS_POSIX_ACL is not set
 CONFIG_HUGETLBFS=y
 CONFIG_HUGETLB_PAGE=y
-# CONFIG_CONFIGFS_FS is not set
+CONFIG_CONFIGFS_FS=m
 
 #
 # Miscellaneous filesystems
@@ -2075,7 +2088,7 @@ CONFIG_XMON=y
 CONFIG_XMON_DISASSEMBLY=y
 CONFIG_DEBUGGER=y
 CONFIG_IRQSTACKS=y
-# CONFIG_VIRQ_DEBUG is not set
+CONFIG_VIRQ_DEBUG=y
 CONFIG_BOOTX_TEXT=y
 # CONFIG_PPC_EARLY_DEBUG is not set
 
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index ca9ff9aad74a..41de3ddc9f24 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -159,7 +159,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 CONFIG_KMOD=y
 CONFIG_STOP_MACHINE=y
 CONFIG_BLOCK=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_BLK_DEV_BSG=y
 # CONFIG_BLK_DEV_INTEGRITY is not set
 CONFIG_BLOCK_COMPAT=y
@@ -191,6 +191,7 @@ CONFIG_SCANLOG=m
 CONFIG_LPARCFG=y
 CONFIG_PPC_SMLPAR=y
 CONFIG_CMM=y
+CONFIG_DTL=y
 # CONFIG_PPC_ISERIES is not set
 # CONFIG_PPC_PMAC is not set
 # CONFIG_PPC_MAPLE is not set
@@ -255,7 +256,8 @@ CONFIG_KEXEC=y
 # CONFIG_PHYP_DUMP is not set
 CONFIG_IRQ_ALL_CPUS=y
 CONFIG_NUMA=y
-CONFIG_NODES_SHIFT=4
+CONFIG_NODES_SHIFT=8
+CONFIG_MAX_ACTIVE_REGIONS=256
 CONFIG_ARCH_SELECT_MEMORY_MODEL=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_DEFAULT=y
@@ -270,7 +272,9 @@ CONFIG_HAVE_MEMORY_PRESENT=y
 CONFIG_SPARSEMEM_EXTREME=y
 CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
 CONFIG_SPARSEMEM_VMEMMAP=y
-# CONFIG_MEMORY_HOTPLUG is not set
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTPLUG_SPARSE=y
+CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 CONFIG_MIGRATION=y
@@ -705,7 +709,7 @@ CONFIG_MD_LINEAR=y
 CONFIG_MD_RAID0=y
 CONFIG_MD_RAID1=y
 CONFIG_MD_RAID10=m
-# CONFIG_MD_RAID456 is not set
+CONFIG_MD_RAID456=m
 CONFIG_MD_MULTIPATH=m
 CONFIG_MD_FAULTY=m
 CONFIG_BLK_DEV_DM=y
@@ -800,7 +804,7 @@ CONFIG_ACENIC=m
 CONFIG_ACENIC_OMIT_TIGON_I=y
 # CONFIG_DL2K is not set
 CONFIG_E1000=y
-# CONFIG_E1000E is not set
+CONFIG_E1000E=m
 # CONFIG_IP1000 is not set
 # CONFIG_IGB is not set
 # CONFIG_NS83820 is not set
@@ -818,18 +822,18 @@ CONFIG_TIGON3=y
 # CONFIG_ATL1E is not set
 # CONFIG_JME is not set
 CONFIG_NETDEV_10000=y
-# CONFIG_CHELSIO_T1 is not set
-# CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T3=m
 CONFIG_EHEA=y
 # CONFIG_ENIC is not set
-# CONFIG_IXGBE is not set
+CONFIG_IXGBE=m
 CONFIG_IXGB=m
 CONFIG_S2IO=m
-# CONFIG_MYRI10GE is not set
-# CONFIG_NETXEN_NIC is not set
+CONFIG_MYRI10GE=m
+CONFIG_NETXEN_NIC=m
 # CONFIG_NIU is not set
-# CONFIG_MLX4_EN is not set
-# CONFIG_MLX4_CORE is not set
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_CORE=m
 # CONFIG_TEHUTI is not set
 # CONFIG_BNX2X is not set
 # CONFIG_QLGE is not set
@@ -894,7 +898,7 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_EVDEV=m
 # CONFIG_INPUT_EVBUG is not set
 
 #
@@ -1271,7 +1275,7 @@ CONFIG_USB_DEVICEFS=y
 CONFIG_USB_DEVICE_CLASS=y
 # CONFIG_USB_DYNAMIC_MINORS is not set
 # CONFIG_USB_OTG is not set
-CONFIG_USB_MON=y
+CONFIG_USB_MON=m
 # CONFIG_USB_WUSB is not set
 # CONFIG_USB_WUSB_CBAF is not set
 
@@ -1311,7 +1315,7 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
 #
 # may also be needed; see USB_STORAGE Help for more information
 #
-CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE=m
 # CONFIG_USB_STORAGE_DEBUG is not set
 # CONFIG_USB_STORAGE_DATAFAB is not set
 # CONFIG_USB_STORAGE_FREECOM is not set
@@ -1322,7 +1326,7 @@ CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_SDDR55 is not set
 # CONFIG_USB_STORAGE_JUMPSHOT is not set
 # CONFIG_USB_STORAGE_ALAUDA is not set
-CONFIG_USB_STORAGE_ONETOUCH=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
 # CONFIG_USB_STORAGE_KARMA is not set
 # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
 # CONFIG_USB_LIBUSUAL is not set
@@ -1377,17 +1381,17 @@ CONFIG_INFINIBAND_USER_MEM=y
 CONFIG_INFINIBAND_ADDR_TRANS=y
 CONFIG_INFINIBAND_MTHCA=m
 CONFIG_INFINIBAND_MTHCA_DEBUG=y
-# CONFIG_INFINIBAND_IPATH is not set
+CONFIG_INFINIBAND_IPATH=m
 CONFIG_INFINIBAND_EHCA=m
 # CONFIG_INFINIBAND_AMSO1100 is not set
-# CONFIG_MLX4_INFINIBAND is not set
+CONFIG_MLX4_INFINIBAND=m
 # CONFIG_INFINIBAND_NES is not set
 CONFIG_INFINIBAND_IPOIB=m
-# CONFIG_INFINIBAND_IPOIB_CM is not set
+CONFIG_INFINIBAND_IPOIB_CM=y
 CONFIG_INFINIBAND_IPOIB_DEBUG=y
 # CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
 CONFIG_INFINIBAND_SRP=m
-# CONFIG_INFINIBAND_ISER is not set
+CONFIG_INFINIBAND_ISER=m
 # CONFIG_EDAC is not set
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
@@ -1443,6 +1447,9 @@ CONFIG_OCFS2_FS_STATS=y
 CONFIG_OCFS2_DEBUG_MASKLOG=y
 # CONFIG_OCFS2_DEBUG_FS is not set
 # CONFIG_OCFS2_COMPAT_JBD is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_NILFS2_FS=m
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -1455,8 +1462,8 @@ CONFIG_FUSE_FS=m
 # CD-ROM/DVD Filesystems
 #
 CONFIG_ISO9660_FS=y
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 CONFIG_UDF_FS=m
 CONFIG_UDF_NLS=y
 
@@ -1508,14 +1515,14 @@ CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
-CONFIG_NFSD=y
+CONFIG_NFSD=m
 CONFIG_NFSD_V2_ACL=y
 CONFIG_NFSD_V3=y
 CONFIG_NFSD_V3_ACL=y
 CONFIG_NFSD_V4=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
+CONFIG_EXPORTFS=m
 CONFIG_NFS_ACL_SUPPORT=y
 CONFIG_NFS_COMMON=y
 CONFIG_SUNRPC=y
@@ -1681,12 +1688,12 @@ CONFIG_DYNAMIC_PRINTK_DEBUG=y
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
 CONFIG_DEBUG_STACKOVERFLOW=y
-# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_STACK_USAGE=y
 # CONFIG_DEBUG_PAGEALLOC is not set
 # CONFIG_HCALL_STATS is not set
-# CONFIG_CODE_PATCHING_SELFTEST is not set
-# CONFIG_FTR_FIXUP_SELFTEST is not set
-# CONFIG_MSI_BITMAP_SELFTEST is not set
+CONFIG_CODE_PATCHING_SELFTEST=y
+CONFIG_FTR_FIXUP_SELFTEST=y
+CONFIG_MSI_BITMAP_SELFTEST=y
 CONFIG_XMON=y
 CONFIG_XMON_DEFAULT=y
 CONFIG_XMON_DISASSEMBLY=y
diff --git a/arch/powerpc/include/asm/asm-compat.h b/arch/powerpc/include/asm/asm-compat.h
index 8f0fe7971949..c1b475a941eb 100644
--- a/arch/powerpc/include/asm/asm-compat.h
+++ b/arch/powerpc/include/asm/asm-compat.h
@@ -2,6 +2,7 @@
 #define _ASM_POWERPC_ASM_COMPAT_H
 
 #include <asm/types.h>
+#include <asm/ppc-opcode.h>
 
 #ifdef __ASSEMBLY__
 #  define stringify_in_c(...)   __VA_ARGS__
@@ -24,7 +25,7 @@
 #define PPC_LONG        stringify_in_c(.llong)
 #define PPC_LONG_ALIGN  stringify_in_c(.balign 8)
 #define PPC_TLNEI       stringify_in_c(tdnei)
-#define PPC_LLARX       stringify_in_c(ldarx)
+#define PPC_LLARX(t, a, b, eh)  PPC_LDARX(t, a, b, eh)
 #define PPC_STLCX       stringify_in_c(stdcx.)
 #define PPC_CNTLZL      stringify_in_c(cntlzd)
 
@@ -46,7 +47,7 @@
 #define PPC_LONG        stringify_in_c(.long)
 #define PPC_LONG_ALIGN  stringify_in_c(.balign 4)
 #define PPC_TLNEI       stringify_in_c(twnei)
-#define PPC_LLARX       stringify_in_c(lwarx)
+#define PPC_LLARX(t, a, b, eh)  PPC_LWARX(t, a, b, eh)
 #define PPC_STLCX       stringify_in_c(stwcx.)
 #define PPC_CNTLZL      stringify_in_c(cntlzw)
 #define PPC_MTOCRF      stringify_in_c(mtcrf)
diff --git a/arch/powerpc/include/asm/atomic.h b/arch/powerpc/include/asm/atomic.h
index 4012483b1899..b8f152ece025 100644
--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -49,13 +49,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2         # atomic_add_return\n\
         add     %0,%1,%0\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -85,13 +85,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2         # atomic_sub_return\n\
         subf    %0,%1,%0\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -119,13 +119,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_inc_return\n\
         addic   %0,%0,1\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -163,13 +163,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_dec_return\n\
         addic   %0,%0,-1\n"
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -194,7 +194,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
         int t;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_add_unless\n\
         cmpw    0,%0,%3 \n\
         beq-    2f \n\
@@ -202,7 +202,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%1 \n\
         bne-    1b \n"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
 "       subf    %0,%2,%0 \n\
 2:"
         : "=&r" (t)
@@ -227,7 +227,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # atomic_dec_if_positive\n\
         cmpwi   %0,1\n\
         addi    %0,%0,-1\n\
@@ -235,7 +235,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"     : "=&b" (t)
         : "r" (&v->counter)
@@ -286,12 +286,12 @@ static __inline__ long atomic64_add_return(long a, atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%2         # atomic64_add_return\n\
         add     %0,%1,%0\n\
         stdcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -320,12 +320,12 @@ static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%2         # atomic64_sub_return\n\
         subf    %0,%1,%0\n\
         stdcx.  %0,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (a), "r" (&v->counter)
         : "cc", "memory");
@@ -352,12 +352,12 @@ static __inline__ long atomic64_inc_return(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic64_inc_return\n\
         addic   %0,%0,1\n\
         stdcx.  %0,0,%1 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -394,12 +394,12 @@ static __inline__ long atomic64_dec_return(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic64_dec_return\n\
         addic   %0,%0,-1\n\
         stdcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "xer", "memory");
@@ -419,13 +419,13 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
         long t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic64_dec_if_positive\n\
         addic.  %0,%0,-1\n\
         blt-    2f\n\
         stdcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"     : "=&r" (t)
         : "r" (&v->counter)
@@ -451,14 +451,14 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
         long t;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%1         # atomic_add_unless\n\
         cmpd    0,%0,%3 \n\
         beq-    2f \n\
         add     %0,%2,%0 \n"
 "       stdcx.  %0,0,%1 \n\
         bne-    1b \n"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
 "       subf    %0,%2,%0 \n\
 2:"
         : "=&r" (t)
diff --git a/arch/powerpc/include/asm/bitops.h b/arch/powerpc/include/asm/bitops.h
index 56f2f2ea5631..30964ae2d096 100644
--- a/arch/powerpc/include/asm/bitops.h
+++ b/arch/powerpc/include/asm/bitops.h
@@ -65,7 +65,7 @@ static __inline__ void fn(unsigned long mask,	\
         unsigned long *p = (unsigned long *)_p; \
         __asm__ __volatile__ (                  \
         prefix                                  \
-"1:"    PPC_LLARX "%0,0,%3\n"                   \
+"1:"    PPC_LLARX(%0,0,%3,0) "\n"               \
         stringify_in_c(op) "%0,%0,%2\n"         \
         PPC405_ERR77(0,%3)                      \
         PPC_STLCX "%0,0,%3\n"                   \
@@ -78,7 +78,7 @@ static __inline__ void fn(unsigned long mask,	\
 
 DEFINE_BITOP(set_bits, or, "", "")
 DEFINE_BITOP(clear_bits, andc, "", "")
-DEFINE_BITOP(clear_bits_unlock, andc, LWSYNC_ON_SMP, "")
+DEFINE_BITOP(clear_bits_unlock, andc, PPC_RELEASE_BARRIER, "")
 DEFINE_BITOP(change_bits, xor, "", "")
 
 static __inline__ void set_bit(int nr, volatile unsigned long *addr)
@@ -103,31 +103,35 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr)
 
 /* Like DEFINE_BITOP(), with changes to the arguments to 'op' and the output
  * operands. */
-#define DEFINE_TESTOP(fn, op, prefix, postfix)  \
-static __inline__ unsigned long fn(             \
-                unsigned long mask,             \
-                volatile unsigned long *_p)     \
-{                                               \
-        unsigned long old, t;                   \
-        unsigned long *p = (unsigned long *)_p; \
-        __asm__ __volatile__ (                  \
-        prefix                                  \
-"1:"    PPC_LLARX "%0,0,%3\n"                   \
-        stringify_in_c(op) "%1,%0,%2\n"         \
-        PPC405_ERR77(0,%3)                      \
-        PPC_STLCX "%1,0,%3\n"                   \
-        "bne- 1b\n"                             \
-        postfix                                 \
-        : "=&r" (old), "=&r" (t)                \
-        : "r" (mask), "r" (p)                   \
-        : "cc", "memory");                      \
-        return (old & mask);                    \
+#define DEFINE_TESTOP(fn, op, prefix, postfix, eh)      \
+static __inline__ unsigned long fn(                     \
+                unsigned long mask,                     \
+                volatile unsigned long *_p)             \
+{                                                       \
+        unsigned long old, t;                           \
+        unsigned long *p = (unsigned long *)_p;         \
+        __asm__ __volatile__ (                          \
+        prefix                                          \
+"1:"    PPC_LLARX(%0,0,%3,eh) "\n"                      \
+        stringify_in_c(op) "%1,%0,%2\n"                 \
+        PPC405_ERR77(0,%3)                              \
+        PPC_STLCX "%1,0,%3\n"                           \
+        "bne- 1b\n"                                     \
+        postfix                                         \
+        : "=&r" (old), "=&r" (t)                        \
+        : "r" (mask), "r" (p)                           \
+        : "cc", "memory");                              \
+        return (old & mask);                            \
 }
 
-DEFINE_TESTOP(test_and_set_bits, or, LWSYNC_ON_SMP, ISYNC_ON_SMP)
-DEFINE_TESTOP(test_and_set_bits_lock, or, "", ISYNC_ON_SMP)
-DEFINE_TESTOP(test_and_clear_bits, andc, LWSYNC_ON_SMP, ISYNC_ON_SMP)
-DEFINE_TESTOP(test_and_change_bits, xor, LWSYNC_ON_SMP, ISYNC_ON_SMP)
+DEFINE_TESTOP(test_and_set_bits, or, PPC_RELEASE_BARRIER,
+              PPC_ACQUIRE_BARRIER, 0)
+DEFINE_TESTOP(test_and_set_bits_lock, or, "",
+              PPC_ACQUIRE_BARRIER, 1)
+DEFINE_TESTOP(test_and_clear_bits, andc, PPC_RELEASE_BARRIER,
+              PPC_ACQUIRE_BARRIER, 0)
+DEFINE_TESTOP(test_and_change_bits, xor, PPC_RELEASE_BARRIER,
+              PPC_ACQUIRE_BARRIER, 0)
 
 static __inline__ int test_and_set_bit(unsigned long nr,
                                        volatile unsigned long *addr)
@@ -158,7 +162,7 @@ static __inline__ int test_and_change_bit(unsigned long nr,
 
 static __inline__ void __clear_bit_unlock(int nr, volatile unsigned long *addr)
 {
-        __asm__ __volatile__(LWSYNC_ON_SMP "" ::: "memory");
+        __asm__ __volatile__(PPC_RELEASE_BARRIER "" ::: "memory");
         __clear_bit(nr, addr);
 }
 
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 80f315e8a421..abb833b0e58f 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -381,9 +381,9 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 
 /* 64-bit CPUs */
-#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
             CPU_FTR_IABR | CPU_FTR_PPC_LE)
-#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
+#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | \
             CPU_FTR_IABR | \
             CPU_FTR_MMCRA | CPU_FTR_CTRL)
 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
diff --git a/arch/powerpc/include/asm/cputime.h b/arch/powerpc/include/asm/cputime.h
index fa19f3fe05ff..8bdc6a9e5773 100644
--- a/arch/powerpc/include/asm/cputime.h
+++ b/arch/powerpc/include/asm/cputime.h
@@ -73,10 +73,9 @@ static inline unsigned long cputime_to_jiffies(const cputime_t ct)
 static inline cputime_t cputime_to_scaled(const cputime_t ct)
 {
         if (cpu_has_feature(CPU_FTR_SPURR) &&
-            per_cpu(cputime_last_delta, smp_processor_id()))
-                return ct *
-                        per_cpu(cputime_scaled_last_delta, smp_processor_id())/
-                        per_cpu(cputime_last_delta, smp_processor_id());
+            __get_cpu_var(cputime_last_delta))
+                return ct * __get_cpu_var(cputime_scaled_last_delta) /
+                            __get_cpu_var(cputime_last_delta);
         return ct;
 }
 
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h
index cbd4dfa4bce2..96a7d067fbb2 100644
--- a/arch/powerpc/include/asm/feature-fixups.h
+++ b/arch/powerpc/include/asm/feature-fixups.h
@@ -165,7 +165,7 @@ label##2:						\
         .pushsection sect,"a";                          \
         .align 2;                                       \
 label##3:                                               \
-        .long label##1b-label##3b;                      \
+        FTR_ENTRY_OFFSET label##1b-label##3b;           \
         .popsection;
 
 #endif /* __ASM_POWERPC_FEATURE_FIXUPS_H */
diff --git a/arch/powerpc/include/asm/futex.h b/arch/powerpc/include/asm/futex.h
index 9696cc36d2dc..7c589ef81fb0 100644
--- a/arch/powerpc/include/asm/futex.h
+++ b/arch/powerpc/include/asm/futex.h
@@ -11,7 +11,7 @@
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
   __asm__ __volatile ( \
-        LWSYNC_ON_SMP \
+        PPC_RELEASE_BARRIER \
 "1:     lwarx   %0,0,%2\n" \
         insn \
         PPC405_ERR77(0, %2) \
@@ -90,14 +90,14 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
                 return -EFAULT;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2         # futex_atomic_cmpxchg_inatomic\n\
         cmpw    0,%0,%3\n\
         bne-    3f\n"
         PPC405_ERR77(0,%2)
 "2:     stwcx.  %4,0,%2\n\
         bne-    1b\n"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
 "3:     .section .fixup,\"ax\"\n\
 4:      li      %0,%5\n\
         b       3b\n\
diff --git a/arch/powerpc/include/asm/hardirq.h b/arch/powerpc/include/asm/hardirq.h
index fb3c05a0cbbf..3147a2970125 100644
--- a/arch/powerpc/include/asm/hardirq.h
+++ b/arch/powerpc/include/asm/hardirq.h
@@ -1 +1,29 @@
-#include <asm-generic/hardirq.h>
+#ifndef _ASM_POWERPC_HARDIRQ_H
+#define _ASM_POWERPC_HARDIRQ_H
+
+#include <linux/threads.h>
+#include <linux/irq.h>
+
+typedef struct {
+        unsigned int __softirq_pending;
+        unsigned int timer_irqs;
+        unsigned int pmu_irqs;
+        unsigned int mce_exceptions;
+        unsigned int spurious_irqs;
+} ____cacheline_aligned irq_cpustat_t;
+
+DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
+
+#define __ARCH_IRQ_STAT
+
+#define local_softirq_pending() __get_cpu_var(irq_stat).__softirq_pending
+
+static inline void ack_bad_irq(unsigned int irq)
+{
+        printk(KERN_CRIT "unexpected IRQ trap at vector %02x\n", irq);
+}
+
+extern u64 arch_irq_stat_cpu(unsigned int cpu);
+#define arch_irq_stat_cpu       arch_irq_stat_cpu
+
+#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/arch/powerpc/include/asm/local.h b/arch/powerpc/include/asm/local.h
index 84b457a3c1bc..ce58c80e1bcf 100644
--- a/arch/powerpc/include/asm/local.h
+++ b/arch/powerpc/include/asm/local.h
@@ -24,7 +24,7 @@ static __inline__ long local_add_return(long a, local_t *l)
         long t;
 
         __asm__ __volatile__(
-"1:"    PPC_LLARX       "%0,0,%2                # local_add_return\n\
+"1:"    PPC_LLARX(%0,0,%2,0) "                  # local_add_return\n\
         add     %0,%1,%0\n"
         PPC405_ERR77(0,%2)
         PPC_STLCX       "%0,0,%2 \n\
@@ -43,7 +43,7 @@ static __inline__ long local_sub_return(long a, local_t *l)
         long t;
 
         __asm__ __volatile__(
-"1:"    PPC_LLARX       "%0,0,%2                # local_sub_return\n\
+"1:"    PPC_LLARX(%0,0,%2,0) "                  # local_sub_return\n\
         subf    %0,%1,%0\n"
         PPC405_ERR77(0,%2)
         PPC_STLCX       "%0,0,%2 \n\
@@ -60,7 +60,7 @@ static __inline__ long local_inc_return(local_t *l)
         long t;
 
         __asm__ __volatile__(
-"1:"    PPC_LLARX       "%0,0,%1                # local_inc_return\n\
+"1:"    PPC_LLARX(%0,0,%1,0) "                  # local_inc_return\n\
         addic   %0,%0,1\n"
         PPC405_ERR77(0,%1)
         PPC_STLCX       "%0,0,%1 \n\
@@ -87,7 +87,7 @@ static __inline__ long local_dec_return(local_t *l)
         long t;
 
         __asm__ __volatile__(
-"1:"    PPC_LLARX       "%0,0,%1                # local_dec_return\n\
+"1:"    PPC_LLARX(%0,0,%1,0) "                  # local_dec_return\n\
         addic   %0,%0,-1\n"
         PPC405_ERR77(0,%1)
         PPC_STLCX       "%0,0,%1\n\
@@ -117,7 +117,7 @@ static __inline__ int local_add_unless(local_t *l, long a, long u)
         long t;
 
         __asm__ __volatile__ (
-"1:"    PPC_LLARX       "%0,0,%1                # local_add_unless\n\
+"1:"    PPC_LLARX(%0,0,%1,0) "                  # local_add_unless\n\
         cmpw    0,%0,%3 \n\
         beq-    2f \n\
         add     %0,%2,%0 \n"
@@ -147,7 +147,7 @@ static __inline__ long local_dec_if_positive(local_t *l)
         long t;
 
         __asm__ __volatile__(
-"1:"    PPC_LLARX       "%0,0,%1                # local_dec_if_positive\n\
+"1:"    PPC_LLARX(%0,0,%1,0) "                  # local_dec_if_positive\n\
         cmpwi   %0,1\n\
         addi    %0,%0,-1\n\
         blt-    2f\n"
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
new file mode 100644
index 000000000000..e6a30bb1d16a
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -0,0 +1,24 @@
+/*
+ * MPC5121 Prototypes and definitions
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.
+ */
+
+#ifndef __ASM_POWERPC_MPC5121_H__
+#define __ASM_POWERPC_MPC5121_H__
+
+/* MPC512x Reset module registers */
+struct mpc512x_reset_module {
+        u32     rcwlr;  /* Reset Configuration Word Low Register */
+        u32     rcwhr;  /* Reset Configuration Word High Register */
+        u32     reserved1;
+        u32     reserved2;
+        u32     rsr;    /* Reset Status Register */
+        u32     rmr;    /* Reset Mode Register */
+        u32     rpr;    /* Reset Protection Register */
+        u32     rcr;    /* Reset Control Register */
+        u32     rcer;   /* Reset Control Enable Register */
+};
+
+#endif /* __ASM_POWERPC_MPC5121_H__ */
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h
index fb8412057450..42561f4f032d 100644
--- a/arch/powerpc/include/asm/mpc52xx_psc.h
+++ b/arch/powerpc/include/asm/mpc52xx_psc.h
@@ -25,7 +25,11 @@
 #include <asm/types.h>
 
 /* Max number of PSCs */
+#ifdef CONFIG_PPC_MPC512x
+#define MPC52xx_PSC_MAXNUM     12
+#else
 #define MPC52xx_PSC_MAXNUM      6
+#endif
 
 /* Programmable Serial Controller (PSC) status register bits */
 #define MPC52xx_PSC_SR_UNEX_RX  0x0001
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index a002682f3a6d..61913d9a21a0 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -289,7 +289,7 @@ struct mpic
 #ifdef CONFIG_MPIC_U3_HT_IRQS
         /* The fixup table */
         struct mpic_irq_fixup   *fixups;
-        spinlock_t              fixup_lock;
+        raw_spinlock_t  fixup_lock;
 #endif
 
         /* Register access method */
diff --git a/arch/powerpc/include/asm/mutex.h b/arch/powerpc/include/asm/mutex.h
index dabc01c727b8..5399f7e18102 100644
--- a/arch/powerpc/include/asm/mutex.h
+++ b/arch/powerpc/include/asm/mutex.h
@@ -15,7 +15,7 @@ static inline int __mutex_cmpxchg_lock(atomic_t *v, int old, int new)
         PPC405_ERR77(0,%1)
 "       stwcx.  %3,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"
         : "=&r" (t)
@@ -35,7 +35,7 @@ static inline int __mutex_dec_return_lock(atomic_t *v)
         PPC405_ERR77(0,%1)
 "       stwcx.  %0,0,%1\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (t)
         : "r" (&v->counter)
         : "cc", "memory");
@@ -48,7 +48,7 @@ static inline int __mutex_inc_return_unlock(atomic_t *v)
         int t;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%1         # mutex unlock\n\
         addic   %0,%0,1\n"
         PPC405_ERR77(0,%1)
diff --git a/arch/powerpc/include/asm/param.h b/arch/powerpc/include/asm/param.h
index 094f63d4d5ca..965d45427975 100644
--- a/arch/powerpc/include/asm/param.h
+++ b/arch/powerpc/include/asm/param.h
@@ -1,22 +1 @@
-#ifndef _ASM_POWERPC_PARAM_H
-#define _ASM_POWERPC_PARAM_H
-
-#ifdef __KERNEL__
-#define HZ              CONFIG_HZ       /* internal kernel timer frequency */
-#define USER_HZ         100             /* for user interfaces in "ticks" */
-#define CLOCKS_PER_SEC  (USER_HZ)       /* frequency at which times() counts */
-#endif /* __KERNEL__ */
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#endif  /* _ASM_POWERPC_PARAM_H */
+#include <asm-generic/param.h>
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 21207e54825b..89f158731ce3 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -209,7 +209,7 @@ extern void paging_init(void);
  * corresponding HPTE into the hash table ahead of time, instead of
  * waiting for the inevitable extra hash-table miss exception.
  */
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
                       unsigned long end, int write, struct page **pages, int *nr);
diff --git a/arch/powerpc/include/asm/pmac_feature.h b/arch/powerpc/include/asm/pmac_feature.h
index 877c35a4356e..00eedc5a4e61 100644
--- a/arch/powerpc/include/asm/pmac_feature.h
+++ b/arch/powerpc/include/asm/pmac_feature.h
@@ -378,7 +378,7 @@ extern struct macio_chip* macio_find(struct device_node* child, int type);
  * Those are exported by pmac feature for internal use by arch code
  * only like the platform function callbacks, do not use directly in drivers
  */
-extern spinlock_t feature_lock;
+extern raw_spinlock_t feature_lock;
 extern struct device_node *uninorth_node;
 extern u32 __iomem *uninorth_base;
 
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index ef9aa84cac5a..aea714797590 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -22,8 +22,10 @@
 #define PPC_INST_DCBZL                  0x7c2007ec
 #define PPC_INST_ISEL                   0x7c00001e
 #define PPC_INST_ISEL_MASK              0xfc00003e
+#define PPC_INST_LDARX                  0x7c0000a8
 #define PPC_INST_LSWI                   0x7c0004aa
 #define PPC_INST_LSWX                   0x7c00042a
+#define PPC_INST_LWARX                  0x7c000029
 #define PPC_INST_LWSYNC                 0x7c2004ac
 #define PPC_INST_LXVD2X                 0x7c000698
 #define PPC_INST_MCRXR                  0x7c000400
@@ -55,15 +57,31 @@
 #define __PPC_RA(a)     (((a) & 0x1f) << 16)
 #define __PPC_RB(b)     (((b) & 0x1f) << 11)
 #define __PPC_RS(s)     (((s) & 0x1f) << 21)
+#define __PPC_RT(s)     __PPC_RS(s)
 #define __PPC_XS(s)     ((((s) & 0x1f) << 21) | (((s) & 0x20) >> 5))
 #define __PPC_T_TLB(t)  (((t) & 0x3) << 21)
 #define __PPC_WC(w)     (((w) & 0x3) << 21)
+/*
+ * Only use the larx hint bit on 64bit CPUs. Once we verify it doesn't have
+ * any side effects on all 32bit processors, we can do this all the time.
+ */
+#ifdef CONFIG_PPC64
+#define __PPC_EH(eh)    (((eh) & 0x1) << 0)
+#else
+#define __PPC_EH(eh)    0
+#endif
 
 /* Deal with instructions that older assemblers aren't aware of */
 #define PPC_DCBAL(a, b)         stringify_in_c(.long PPC_INST_DCBAL | \
                                         __PPC_RA(a) | __PPC_RB(b))
 #define PPC_DCBZL(a, b)         stringify_in_c(.long PPC_INST_DCBZL | \
                                         __PPC_RA(a) | __PPC_RB(b))
+#define PPC_LDARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LDARX | \
+                                        __PPC_RT(t) | __PPC_RA(a) | \
+                                        __PPC_RB(b) | __PPC_EH(eh))
+#define PPC_LWARX(t, a, b, eh)  stringify_in_c(.long PPC_INST_LWARX | \
+                                        __PPC_RT(t) | __PPC_RA(a) | \
+                                        __PPC_RB(b) | __PPC_EH(eh))
 #define PPC_MSGSND(b)           stringify_in_c(.long PPC_INST_MSGSND | \
                                         __PPC_RB(b))
 #define PPC_RFCI                stringify_in_c(.long PPC_INST_RFCI)
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index 2828f9d0f66d..42fdff0e4b32 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -137,6 +137,11 @@ struct device_node * find_device_pe(struct device_node *dn);
 void eeh_sysfs_add_device(struct pci_dev *pdev);
 void eeh_sysfs_remove_device(struct pci_dev *pdev);
 
+static inline const char *eeh_pci_name(struct pci_dev *pdev) 
+{ 
+        return pdev ? pci_name(pdev) : "<null>";
+} 
+
 #endif /* CONFIG_EEH */
 
 #else /* CONFIG_PCI */
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 9eed29eee604..221ba6240464 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -161,9 +161,41 @@ struct thread_struct {
 #ifdef CONFIG_PPC32
         void            *pgdir;         /* root of page-table tree */
 #endif
-#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
-        unsigned long   dbcr0;          /* debug control register values */
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+        /*
+         * The following help to manage the use of Debug Control Registers
+         * om the BookE platforms.
+         */
+        unsigned long   dbcr0;
         unsigned long   dbcr1;
+#ifdef CONFIG_BOOKE
+        unsigned long   dbcr2;
+#endif
+        /*
+         * The stored value of the DBSR register will be the value at the
+         * last debug interrupt. This register can only be read from the
+         * user (will never be written to) and has value while helping to
+         * describe the reason for the last debug trap.  Torez
+         */
+        unsigned long   dbsr;
+        /*
+         * The following will contain addresses used by debug applications
+         * to help trace and trap on particular address locations.
+         * The bits in the Debug Control Registers above help define which
+         * of the following registers will contain valid data and/or addresses.
+         */
+        unsigned long   iac1;
+        unsigned long   iac2;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+        unsigned long   iac3;
+        unsigned long   iac4;
+#endif
+        unsigned long   dac1;
+        unsigned long   dac2;
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+        unsigned long   dvc1;
+        unsigned long   dvc2;
+#endif
 #endif
         /* FP and VSX 0-31 register set */
         double          fpr[32][TS_FPRWIDTH];
diff --git a/arch/powerpc/include/asm/prom.h b/arch/powerpc/include/asm/prom.h
index 2ab9cbd98826..ddd408a93b5a 100644
--- a/arch/powerpc/include/asm/prom.h
+++ b/arch/powerpc/include/asm/prom.h
@@ -23,21 +23,8 @@
 #include <asm/irq.h>
 #include <asm/atomic.h>
 
-#define OF_ROOT_NODE_ADDR_CELLS_DEFAULT 1
-#define OF_ROOT_NODE_SIZE_CELLS_DEFAULT 1
-
-#define of_compat_cmp(s1, s2, l)        strcasecmp((s1), (s2))
-#define of_prop_cmp(s1, s2)             strcmp((s1), (s2))
-#define of_node_cmp(s1, s2)             strcasecmp((s1), (s2))
-
-extern struct device_node *of_chosen;
-
 #define HAVE_ARCH_DEVTREE_FIXUPS
 
-/* For updating the device tree at runtime */
-extern void of_attach_node(struct device_node *);
-extern void of_detach_node(struct device_node *);
-
 #ifdef CONFIG_PPC32
 /*
  * PCI <-> OF matching functions
@@ -52,11 +39,6 @@ extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
 extern void pci_create_OF_bus_map(void);
 #endif
 
-extern struct resource *request_OF_resource(struct device_node* node,
-                                int index, const char* name_postfix);
-extern int release_OF_resource(struct device_node* node, int index);
-
-
 /*
  * OF address retreival & translation
  */
diff --git a/arch/powerpc/include/asm/ptrace.h b/arch/powerpc/include/asm/ptrace.h
index cbd759e3cd78..b45108126562 100644
--- a/arch/powerpc/include/asm/ptrace.h
+++ b/arch/powerpc/include/asm/ptrace.h
@@ -24,6 +24,12 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+
 #ifndef __ASSEMBLY__
 
 struct pt_regs {
@@ -294,4 +300,75 @@ extern void user_disable_single_step(struct task_struct *);
 
 #define PTRACE_SINGLEBLOCK      0x100   /* resume execution until next branch */
 
+#define PPC_PTRACE_GETHWDBGINFO 0x89
+#define PPC_PTRACE_SETHWDEBUG   0x88
+#define PPC_PTRACE_DELHWDEBUG   0x87
+
+#ifndef __ASSEMBLY__
+
+struct ppc_debug_info {
+        uint32_t version;               /* Only version 1 exists to date */
+        uint32_t num_instruction_bps;
+        uint32_t num_data_bps;
+        uint32_t num_condition_regs;
+        uint32_t data_bp_alignment;
+        uint32_t sizeof_condition;      /* size of the DVC register */
+        uint64_t features;
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * features will have bits indication whether there is support for:
+ */
+#define PPC_DEBUG_FEATURE_INSN_BP_RANGE         0x0000000000000001
+#define PPC_DEBUG_FEATURE_INSN_BP_MASK          0x0000000000000002
+#define PPC_DEBUG_FEATURE_DATA_BP_RANGE         0x0000000000000004
+#define PPC_DEBUG_FEATURE_DATA_BP_MASK          0x0000000000000008
+
+#ifndef __ASSEMBLY__
+
+struct ppc_hw_breakpoint {
+        uint32_t version;               /* currently, version must be 1 */
+        uint32_t trigger_type;          /* only some combinations allowed */
+        uint32_t addr_mode;             /* address match mode */
+        uint32_t condition_mode;        /* break/watchpoint condition flags */
+        uint64_t addr;                  /* break/watchpoint address */
+        uint64_t addr2;                 /* range end or mask */
+        uint64_t condition_value;       /* contents of the DVC register */
+};
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Trigger Type
+ */
+#define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x00000001
+#define PPC_BREAKPOINT_TRIGGER_READ     0x00000002
+#define PPC_BREAKPOINT_TRIGGER_WRITE    0x00000004
+#define PPC_BREAKPOINT_TRIGGER_RW       \
+        (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
+
+/*
+ * Address Mode
+ */
+#define PPC_BREAKPOINT_MODE_EXACT               0x00000000
+#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x00000001
+#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x00000002
+#define PPC_BREAKPOINT_MODE_MASK                0x00000003
+
+/*
+ * Condition Mode
+ */
+#define PPC_BREAKPOINT_CONDITION_MODE   0x00000003
+#define PPC_BREAKPOINT_CONDITION_NONE   0x00000000
+#define PPC_BREAKPOINT_CONDITION_AND    0x00000001
+#define PPC_BREAKPOINT_CONDITION_EXACT  PPC_BREAKPOINT_CONDITION_AND
+#define PPC_BREAKPOINT_CONDITION_OR     0x00000002
+#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
+#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
+#define PPC_BREAKPOINT_CONDITION_BE_SHIFT       16
+#define PPC_BREAKPOINT_CONDITION_BE(n)  \
+        (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
+
 #endif /* _ASM_POWERPC_PTRACE_H */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 3bf783505528..8808d307fe7e 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -248,6 +248,8 @@
 #define DBSR_RET        0x00008000      /* Return Debug Event */
 #define DBSR_CIRPT      0x00000040      /* Critical Interrupt Taken Event */
 #define DBSR_CRET       0x00000020      /* Critical Return Debug Event */
+#define DBSR_IAC12ATS   0x00000002      /* Instr Address Compare 1/2 Toggle */
+#define DBSR_IAC34ATS   0x00000001      /* Instr Address Compare 3/4 Toggle */
 #endif
 #ifdef CONFIG_40x
 #define DBSR_IC         0x80000000      /* Instruction Completion */
@@ -313,6 +315,38 @@
 #define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
 #define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
 #define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
+
+#define dbcr_iac_range(task)    ((task)->thread.dbcr0)
+#define DBCR_IAC12I     DBCR0_IA12                      /* Range Inclusive */
+#define DBCR_IAC12X     (DBCR0_IA12 | DBCR0_IA12X)      /* Range Exclusive */
+#define DBCR_IAC12MODE  (DBCR0_IA12 | DBCR0_IA12X)      /* IAC 1-2 Mode Bits */
+#define DBCR_IAC34I     DBCR0_IA34                      /* Range Inclusive */
+#define DBCR_IAC34X     (DBCR0_IA34 | DBCR0_IA34X)      /* Range Exclusive */
+#define DBCR_IAC34MODE  (DBCR0_IA34 | DBCR0_IA34X)      /* IAC 3-4 Mode Bits */
+
+/* Bit definitions related to the DBCR1. */
+#define DBCR1_DAC1R     0x80000000      /* DAC1 Read Debug Event */
+#define DBCR1_DAC2R     0x40000000      /* DAC2 Read Debug Event */
+#define DBCR1_DAC1W     0x20000000      /* DAC1 Write Debug Event */
+#define DBCR1_DAC2W     0x10000000      /* DAC2 Write Debug Event */
+
+#define dbcr_dac(task)  ((task)->thread.dbcr1)
+#define DBCR_DAC1R      DBCR1_DAC1R
+#define DBCR_DAC1W      DBCR1_DAC1W
+#define DBCR_DAC2R      DBCR1_DAC2R
+#define DBCR_DAC2W      DBCR1_DAC2W
+
+/*
+ * Are there any active Debug Events represented in the
+ * Debug Control Registers?
+ */
+#define DBCR0_ACTIVE_EVENTS     (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
+                                 DBCR0_IAC3 | DBCR0_IAC4)
+#define DBCR1_ACTIVE_EVENTS     (DBCR1_DAC1R | DBCR1_DAC2R | \
+                                 DBCR1_DAC1W | DBCR1_DAC2W)
+#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
+                                           ((dbcr1) & DBCR1_ACTIVE_EVENTS))
+
 #elif defined(CONFIG_BOOKE)
 #define DBCR0_EDM       0x80000000      /* External Debug Mode */
 #define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
@@ -342,19 +376,79 @@
 #define DBCR0_CRET      0x00000020      /* Critical Return Debug Event */
 #define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
 
+#define dbcr_dac(task)  ((task)->thread.dbcr0)
+#define DBCR_DAC1R      DBCR0_DAC1R
+#define DBCR_DAC1W      DBCR0_DAC1W
+#define DBCR_DAC2R      DBCR0_DAC2R
+#define DBCR_DAC2W      DBCR0_DAC2W
+
 /* Bit definitions related to the DBCR1. */
+#define DBCR1_IAC1US    0xC0000000      /* Instr Addr Cmp 1 Sup/User   */
+#define DBCR1_IAC1ER    0x30000000      /* Instr Addr Cmp 1 Eff/Real */
+#define DBCR1_IAC1ER_01 0x10000000      /* reserved */
+#define DBCR1_IAC1ER_10 0x20000000      /* Instr Addr Cmp 1 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC1ER_11 0x30000000      /* Instr Addr Cmp 1 Eff/Real MSR[IS]=1 */
+#define DBCR1_IAC2US    0x0C000000      /* Instr Addr Cmp 2 Sup/User   */
+#define DBCR1_IAC2ER    0x03000000      /* Instr Addr Cmp 2 Eff/Real */
+#define DBCR1_IAC2ER_01 0x01000000      /* reserved */
+#define DBCR1_IAC2ER_10 0x02000000      /* Instr Addr Cmp 2 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC2ER_11 0x03000000      /* Instr Addr Cmp 2 Eff/Real MSR[IS]=1 */
 #define DBCR1_IAC12M    0x00800000      /* Instr Addr 1-2 range enable */
 #define DBCR1_IAC12MX   0x00C00000      /* Instr Addr 1-2 range eXclusive */
 #define DBCR1_IAC12AT   0x00010000      /* Instr Addr 1-2 range Toggle */
+#define DBCR1_IAC3US    0x0000C000      /* Instr Addr Cmp 3 Sup/User   */
+#define DBCR1_IAC3ER    0x00003000      /* Instr Addr Cmp 3 Eff/Real */
+#define DBCR1_IAC3ER_01 0x00001000      /* reserved */
+#define DBCR1_IAC3ER_10 0x00002000      /* Instr Addr Cmp 3 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC3ER_11 0x00003000      /* Instr Addr Cmp 3 Eff/Real MSR[IS]=1 */
+#define DBCR1_IAC4US    0x00000C00      /* Instr Addr Cmp 4 Sup/User   */
+#define DBCR1_IAC4ER    0x00000300      /* Instr Addr Cmp 4 Eff/Real */
+#define DBCR1_IAC4ER_01 0x00000100      /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC4ER_10 0x00000200      /* Instr Addr Cmp 4 Eff/Real MSR[IS]=0 */
+#define DBCR1_IAC4ER_11 0x00000300      /* Instr Addr Cmp 4 Eff/Real MSR[IS]=1 */
 #define DBCR1_IAC34M    0x00000080      /* Instr Addr 3-4 range enable */
 #define DBCR1_IAC34MX   0x000000C0      /* Instr Addr 3-4 range eXclusive */
 #define DBCR1_IAC34AT   0x00000001      /* Instr Addr 3-4 range Toggle */
 
+#define dbcr_iac_range(task)    ((task)->thread.dbcr1)
+#define DBCR_IAC12I     DBCR1_IAC12M    /* Range Inclusive */
+#define DBCR_IAC12X     DBCR1_IAC12MX   /* Range Exclusive */
+#define DBCR_IAC12MODE  DBCR1_IAC12MX   /* IAC 1-2 Mode Bits */
+#define DBCR_IAC34I     DBCR1_IAC34M    /* Range Inclusive */
+#define DBCR_IAC34X     DBCR1_IAC34MX   /* Range Exclusive */
+#define DBCR_IAC34MODE  DBCR1_IAC34MX   /* IAC 3-4 Mode Bits */
+
 /* Bit definitions related to the DBCR2. */
+#define DBCR2_DAC1US    0xC0000000      /* Data Addr Cmp 1 Sup/User   */
+#define DBCR2_DAC1ER    0x30000000      /* Data Addr Cmp 1 Eff/Real */
+#define DBCR2_DAC2US    0x00000000      /* Data Addr Cmp 2 Sup/User   */
+#define DBCR2_DAC2ER    0x00000000      /* Data Addr Cmp 2 Eff/Real */
 #define DBCR2_DAC12M    0x00800000      /* DAC 1-2 range enable */
+#define DBCR2_DAC12MM   0x00400000      /* DAC 1-2 Mask mode*/
 #define DBCR2_DAC12MX   0x00C00000      /* DAC 1-2 range eXclusive */
+#define DBCR2_DAC12MODE 0x00C00000      /* DAC 1-2 Mode Bits */
 #define DBCR2_DAC12A    0x00200000      /* DAC 1-2 Asynchronous */
-#endif
+#define DBCR2_DVC1M     0x000C0000      /* Data Value Comp 1 Mode */
+#define DBCR2_DVC1M_SHIFT       18      /* # of bits to shift DBCR2_DVC1M */
+#define DBCR2_DVC2M     0x00030000      /* Data Value Comp 2 Mode */
+#define DBCR2_DVC2M_SHIFT       16      /* # of bits to shift DBCR2_DVC2M */
+#define DBCR2_DVC1BE    0x00000F00      /* Data Value Comp 1 Byte */
+#define DBCR2_DVC1BE_SHIFT      8       /* # of bits to shift DBCR2_DVC1BE */
+#define DBCR2_DVC2BE    0x0000000F      /* Data Value Comp 2 Byte */
+#define DBCR2_DVC2BE_SHIFT      0       /* # of bits to shift DBCR2_DVC2BE */
+
+/*
+ * Are there any active Debug Events represented in the
+ * Debug Control Registers?
+ */
+#define DBCR0_ACTIVE_EVENTS  (DBCR0_ICMP | DBCR0_IAC1 | DBCR0_IAC2 | \
+                              DBCR0_IAC3 | DBCR0_IAC4 | DBCR0_DAC1R | \
+                              DBCR0_DAC1W  | DBCR0_DAC2R | DBCR0_DAC2W)
+#define DBCR1_ACTIVE_EVENTS     0
+
+#define DBCR_ACTIVE_EVENTS(dbcr0, dbcr1)  (((dbcr0) & DBCR0_ACTIVE_EVENTS) || \
+                                           ((dbcr1) & DBCR1_ACTIVE_EVENTS))
+#endif /* #elif defined(CONFIG_BOOKE) */
 
 /* Bit definitions related to the TCR. */
 #define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index 764094cff681..f9611bd69ed2 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -27,6 +27,7 @@
 #endif
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
+#include <asm/ppc-opcode.h>
 
 #define arch_spin_is_locked(x)          ((x)->slock != 0)
 
@@ -60,13 +61,14 @@ static inline unsigned long __arch_spin_trylock(arch_spinlock_t *lock)
 
         token = LOCK_TOKEN;
         __asm__ __volatile__(
-"1:     lwarx           %0,0,%2\n\
+"1:     " PPC_LWARX(%0,0,%2,1) "\n\
         cmpwi           0,%0,0\n\
         bne-            2f\n\
         stwcx.          %1,0,%2\n\
-        bne-            1b\n\
-        isync\n\
-2:"     : "=&r" (tmp)
+        bne-            1b\n"
+        PPC_ACQUIRE_BARRIER
+"2:"
+        : "=&r" (tmp)
         : "r" (token), "r" (&lock->slock)
         : "cr0", "memory");
 
@@ -144,7 +146,7 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
         SYNC_IO;
         __asm__ __volatile__("# arch_spin_unlock\n\t"
-                                LWSYNC_ON_SMP: : :"memory");
+                                PPC_RELEASE_BARRIER: : :"memory");
         lock->slock = 0;
 }
 
@@ -186,15 +188,15 @@ static inline long __arch_read_trylock(arch_rwlock_t *rw)
         long tmp;
 
         __asm__ __volatile__(
-"1:     lwarx           %0,0,%1\n"
+"1:     " PPC_LWARX(%0,0,%1,1) "\n"
         __DO_SIGN_EXTEND
 "       addic.          %0,%0,1\n\
         ble-            2f\n"
         PPC405_ERR77(0,%1)
 "       stwcx.          %0,0,%1\n\
-        bne-            1b\n\
-        isync\n\
-2:"     : "=&r" (tmp)
+        bne-            1b\n"
+        PPC_ACQUIRE_BARRIER
+"2:"    : "=&r" (tmp)
         : "r" (&rw->lock)
         : "cr0", "xer", "memory");
 
@@ -211,14 +213,14 @@ static inline long __arch_write_trylock(arch_rwlock_t *rw)
 
         token = WRLOCK_TOKEN;
         __asm__ __volatile__(
-"1:     lwarx           %0,0,%2\n\
+"1:     " PPC_LWARX(%0,0,%2,1) "\n\
         cmpwi           0,%0,0\n\
         bne-            2f\n"
         PPC405_ERR77(0,%1)
 "       stwcx.          %1,0,%2\n\
-        bne-            1b\n\
-        isync\n\
-2:"     : "=&r" (tmp)
+        bne-            1b\n"
+        PPC_ACQUIRE_BARRIER
+"2:"    : "=&r" (tmp)
         : "r" (token), "r" (&rw->lock)
         : "cr0", "memory");
 
@@ -269,7 +271,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
 
         __asm__ __volatile__(
         "# read_unlock\n\t"
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx           %0,0,%1\n\
         addic           %0,%0,-1\n"
         PPC405_ERR77(0,%1)
@@ -283,7 +285,7 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
         __asm__ __volatile__("# write_unlock\n\t"
-                                LWSYNC_ON_SMP: : :"memory");
+                                PPC_RELEASE_BARRIER: : :"memory");
         rw->lock = 0;
 }
 
diff --git a/arch/powerpc/include/asm/synch.h b/arch/powerpc/include/asm/synch.h
index 28f6ddbff4cf..d7cab44643c5 100644
--- a/arch/powerpc/include/asm/synch.h
+++ b/arch/powerpc/include/asm/synch.h
@@ -37,11 +37,15 @@ static inline void isync(void)
 #endif
 
 #ifdef CONFIG_SMP
-#define ISYNC_ON_SMP    "\n\tisync\n"
-#define LWSYNC_ON_SMP   stringify_in_c(LWSYNC) "\n"
+#define __PPC_ACQUIRE_BARRIER                           \
+        START_LWSYNC_SECTION(97);                       \
+        isync;                                          \
+        MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
+#define PPC_ACQUIRE_BARRIER     "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
+#define PPC_RELEASE_BARRIER     stringify_in_c(LWSYNC) "\n"
 #else
-#define ISYNC_ON_SMP
-#define LWSYNC_ON_SMP
+#define PPC_ACQUIRE_BARRIER
+#define PPC_RELEASE_BARRIER
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/system.h b/arch/powerpc/include/asm/system.h
index bb8e006a47c6..a6297c67c3d6 100644
--- a/arch/powerpc/include/asm/system.h
+++ b/arch/powerpc/include/asm/system.h
@@ -112,8 +112,13 @@ static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
 #endif
 
 extern int set_dabr(unsigned long dabr);
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+extern void do_send_trap(struct pt_regs *regs, unsigned long address,
+                         unsigned long error_code, int signal_code, int brkpt);
+#else
 extern void do_dabr(struct pt_regs *regs, unsigned long address,
                     unsigned long error_code);
+#endif
 extern void print_backtrace(unsigned long *);
 extern void show_regs(struct pt_regs * regs);
 extern void flush_instruction_cache(void);
@@ -232,12 +237,12 @@ __xchg_u32(volatile void *p, unsigned long val)
         unsigned long prev;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2 \n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %3,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
         : "r" (p), "r" (val)
         : "cc", "memory");
@@ -275,12 +280,12 @@ __xchg_u64(volatile void *p, unsigned long val)
         unsigned long prev;
 
         __asm__ __volatile__(
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%2 \n"
         PPC405_ERR77(0,%2)
 "       stdcx.  %3,0,%2 \n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
         : "r" (p), "r" (val)
         : "cc", "memory");
@@ -366,14 +371,14 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
         unsigned int prev;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
         cmpw    0,%0,%3\n\
         bne-    2f\n"
         PPC405_ERR77(0,%2)
 "       stwcx.  %4,0,%2\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"
         : "=&r" (prev), "+m" (*p)
@@ -412,13 +417,13 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
         unsigned long prev;
 
         __asm__ __volatile__ (
-        LWSYNC_ON_SMP
+        PPC_RELEASE_BARRIER
 "1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
         cmpd    0,%0,%3\n\
         bne-    2f\n\
         stdcx.  %4,0,%2\n\
         bne-    1b"
-        ISYNC_ON_SMP
+        PPC_ACQUIRE_BARRIER
         "\n\
 2:"
         : "=&r" (prev), "+m" (*p)
diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index bbf89701d7a4..8eaec310a25b 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -38,27 +38,33 @@ static inline int pcibus_to_node(struct pci_bus *bus)
                                  cpumask_of_node(pcibus_to_node(bus)))
 
 /* sched_domains SD_NODE_INIT for PPC64 machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 1,                    \
-        .busy_idx               = 3,                    \
-        .idle_idx               = 1,                    \
-        .newidle_idx            = 0,                    \
-        .wake_idx               = 0,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_EXEC       \
-                                | SD_BALANCE_FORK       \
-                                | SD_BALANCE_NEWIDLE    \
-                                | SD_SERIALIZE,         \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
+#define SD_NODE_INIT (struct sched_domain) {                            \
+        .min_interval           = 8,                                    \
+        .max_interval           = 32,                                   \
+        .busy_factor            = 32,                                   \
+        .imbalance_pct          = 125,                                  \
+        .cache_nice_tries       = 1,                                    \
+        .busy_idx               = 3,                                    \
+        .idle_idx               = 1,                                    \
+        .newidle_idx            = 0,                                    \
+        .wake_idx               = 0,                                    \
+        .forkexec_idx           = 0,                                    \
+                                                                        \
+        .flags                  = 1*SD_LOAD_BALANCE                     \
+                                | 1*SD_BALANCE_NEWIDLE                  \
+                                | 1*SD_BALANCE_EXEC                     \
+                                | 1*SD_BALANCE_FORK                     \
+                                | 0*SD_BALANCE_WAKE                     \
+                                | 0*SD_WAKE_AFFINE                      \
+                                | 0*SD_PREFER_LOCAL                     \
+                                | 0*SD_SHARE_CPUPOWER                   \
+                                | 0*SD_POWERSAVINGS_BALANCE             \
+                                | 0*SD_SHARE_PKG_RESOURCES              \
+                                | 1*SD_SERIALIZE                        \
+                                | 0*SD_PREFER_SIBLING                   \
+                                ,                                       \
+        .last_balance           = jiffies,                              \
+        .balance_interval       = 1,                                    \
 }
 
 extern void __init dump_numa_cpu_topology(void);
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index bdcb557d470a..07109d843787 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -791,9 +791,8 @@ _GLOBAL(enter_rtas)
         
         li      r9,1
         rldicr  r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
-        ori     r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
+        ori     r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP|MSR_RI
         andc    r6,r0,r9
-        ori     r6,r6,MSR_RI
         sync                            /* disable interrupts so SRR0/1 */
         mtmsrd  r0                      /* don't get trashed */
 
diff --git a/arch/powerpc/kernel/firmware.c b/arch/powerpc/kernel/firmware.c
index 1679a70bbcad..6b1f4271eb53 100644
--- a/arch/powerpc/kernel/firmware.c
+++ b/arch/powerpc/kernel/firmware.c
@@ -17,5 +17,5 @@
 
 #include <asm/firmware.h>
 
-unsigned long powerpc_firmware_features;
+unsigned long powerpc_firmware_features __read_mostly;
 EXPORT_SYMBOL_GPL(powerpc_firmware_features);
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 7f4bd7f3b6af..25793bb0e782 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -214,11 +214,11 @@ skpinv:	addi	r6,r6,1				/* Increment */
         bl      1f              /* Find our address */
 1:      mflr    r9
         rlwimi  r7,r9,0,20,31
-        addi    r7,r7,24
+        addi    r7,r7,(2f - 1b)
         mtspr   SPRN_SRR0,r7
         mtspr   SPRN_SRR1,r6
         rfi
-
+2:
 /* 4. Clear out PIDs & Search info */
         li      r6,0
         mtspr   SPRN_MAS6,r6
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 9040330b0530..64f6f2031c22 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -73,8 +73,10 @@
 #define CREATE_TRACE_POINTS
 #include <asm/trace.h>
 
+DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
+EXPORT_PER_CPU_SYMBOL(irq_stat);
+
 int __irq_offset_value;
-static int ppc_spurious_interrupts;
 
 #ifdef CONFIG_PPC32
 EXPORT_SYMBOL(__irq_offset_value);
@@ -180,30 +182,64 @@ notrace void raw_local_irq_restore(unsigned long en)
 EXPORT_SYMBOL(raw_local_irq_restore);
 #endif /* CONFIG_PPC64 */
 
+static int show_other_interrupts(struct seq_file *p, int prec)
+{
+        int j;
+
+#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
+        if (tau_initialized) {
+                seq_printf(p, "%*s: ", prec, "TAU");
+                for_each_online_cpu(j)
+                        seq_printf(p, "%10u ", tau_interrupts(j));
+                seq_puts(p, "  PowerPC             Thermal Assist (cpu temp)\n");
+        }
+#endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
+
+        seq_printf(p, "%*s: ", prec, "LOC");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs);
+        seq_printf(p, "  Local timer interrupts\n");
+
+        seq_printf(p, "%*s: ", prec, "SPU");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
+        seq_printf(p, "  Spurious interrupts\n");
+
+        seq_printf(p, "%*s: ", prec, "CNT");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
+        seq_printf(p, "  Performance monitoring interrupts\n");
+
+        seq_printf(p, "%*s: ", prec, "MCE");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
+        seq_printf(p, "  Machine check exceptions\n");
+
+        return 0;
+}
+
 int show_interrupts(struct seq_file *p, void *v)
 {
-        int i = *(loff_t *)v, j;
+        unsigned long flags, any_count = 0;
+        int i = *(loff_t *) v, j, prec;
         struct irqaction *action;
         struct irq_desc *desc;
-        unsigned long flags;
 
+        if (i > nr_irqs)
+                return 0;
+
+        for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
+                j *= 10;
+
+        if (i == nr_irqs)
+                return show_other_interrupts(p, prec);
+
+        /* print header */
         if (i == 0) {
-                seq_puts(p, "           ");
+                seq_printf(p, "%*s", prec + 8, "");
                 for_each_online_cpu(j)
-                        seq_printf(p, "CPU%d       ", j);
+                        seq_printf(p, "CPU%-8d", j);
                 seq_putc(p, '\n');
-        } else if (i == nr_irqs) {
-#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
-                if (tau_initialized){
-                        seq_puts(p, "TAU: ");
-                        for_each_online_cpu(j)
-                                seq_printf(p, "%10u ", tau_interrupts(j));
-                        seq_puts(p, "  PowerPC             Thermal Assist (cpu temp)\n");
-                }
-#endif /* CONFIG_PPC32 && CONFIG_TAU_INT*/
-                seq_printf(p, "BAD: %10u\n", ppc_spurious_interrupts);
-
-                return 0;
         }
 
         desc = irq_to_desc(i);
@@ -211,37 +247,48 @@ int show_interrupts(struct seq_file *p, void *v)
                 return 0;
 
         raw_spin_lock_irqsave(&desc->lock, flags);
-
+        for_each_online_cpu(j)
+                any_count |= kstat_irqs_cpu(i, j);
         action = desc->action;
-        if (!action || !action->handler)
-                goto skip;
+        if (!action && !any_count)
+                goto out;
 
-        seq_printf(p, "%3d: ", i);
-#ifdef CONFIG_SMP
+        seq_printf(p, "%*d: ", prec, i);
         for_each_online_cpu(j)
                 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-#else
-        seq_printf(p, "%10u ", kstat_irqs(i));
-#endif /* CONFIG_SMP */
 
         if (desc->chip)
-                seq_printf(p, " %s ", desc->chip->name);
+                seq_printf(p, "  %-16s", desc->chip->name);
         else
-                seq_puts(p, "  None      ");
+                seq_printf(p, "  %-16s", "None");
+        seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge");
 
-        seq_printf(p, "%s", (desc->status & IRQ_LEVEL) ? "Level " : "Edge  ");
-        seq_printf(p, "    %s", action->name);
+        if (action) {
+                seq_printf(p, "     %s", action->name);
+                while ((action = action->next) != NULL)
+                        seq_printf(p, ", %s", action->name);
+        }
 
-        for (action = action->next; action; action = action->next)
-                seq_printf(p, ", %s", action->name);
         seq_putc(p, '\n');
-
-skip:
+out:
         raw_spin_unlock_irqrestore(&desc->lock, flags);
-
         return 0;
 }
 
+/*
+ * /proc/stat helpers
+ */
+u64 arch_irq_stat_cpu(unsigned int cpu)
+{
+        u64 sum = per_cpu(irq_stat, cpu).timer_irqs;
+
+        sum += per_cpu(irq_stat, cpu).pmu_irqs;
+        sum += per_cpu(irq_stat, cpu).mce_exceptions;
+        sum += per_cpu(irq_stat, cpu).spurious_irqs;
+
+        return sum;
+}
+
 #ifdef CONFIG_HOTPLUG_CPU
 void fixup_irqs(cpumask_t map)
 {
@@ -353,8 +400,7 @@ void do_IRQ(struct pt_regs *regs)
         if (irq != NO_IRQ && irq != NO_IRQ_IGNORE)
                 handle_one_irq(irq);
         else if (irq != NO_IRQ_IGNORE)
-                /* That's not SMP safe ... but who cares ? */
-                ppc_spurious_interrupts++;
+                __get_cpu_var(irq_stat).spurious_irqs++;
 
         irq_exit();
         set_irq_regs(old_regs);
@@ -474,7 +520,7 @@ void do_softirq(void)
  */
 
 static LIST_HEAD(irq_hosts);
-static DEFINE_SPINLOCK(irq_big_lock);
+static DEFINE_RAW_SPINLOCK(irq_big_lock);
 static unsigned int revmap_trees_allocated;
 static DEFINE_MUTEX(revmap_trees_mutex);
 struct irq_map_entry irq_map[NR_IRQS];
@@ -520,14 +566,14 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
         if (host->ops->match == NULL)
                 host->ops->match = default_irq_host_match;
 
-        spin_lock_irqsave(&irq_big_lock, flags);
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
 
         /* If it's a legacy controller, check for duplicates and
          * mark it as allocated (we use irq 0 host pointer for that
          */
         if (revmap_type == IRQ_HOST_MAP_LEGACY) {
                 if (irq_map[0].host != NULL) {
-                        spin_unlock_irqrestore(&irq_big_lock, flags);
+                        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
                         /* If we are early boot, we can't free the structure,
                          * too bad...
                          * this will be fixed once slab is made available early
@@ -541,7 +587,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
         }
 
         list_add(&host->link, &irq_hosts);
-        spin_unlock_irqrestore(&irq_big_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
 
         /* Additional setups per revmap type */
         switch(revmap_type) {
@@ -592,13 +638,13 @@ struct irq_host *irq_find_host(struct device_node *node)
          * the absence of a device node. This isn't a problem so far
          * yet though...
          */
-        spin_lock_irqsave(&irq_big_lock, flags);
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
         list_for_each_entry(h, &irq_hosts, link)
                 if (h->ops->match(h, node)) {
                         found = h;
                         break;
                 }
-        spin_unlock_irqrestore(&irq_big_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
         return found;
 }
 EXPORT_SYMBOL_GPL(irq_find_host);
@@ -967,7 +1013,7 @@ unsigned int irq_alloc_virt(struct irq_host *host,
         if (count == 0 || count > (irq_virq_count - NUM_ISA_INTERRUPTS))
                 return NO_IRQ;
 
-        spin_lock_irqsave(&irq_big_lock, flags);
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
 
         /* Use hint for 1 interrupt if any */
         if (count == 1 && hint >= NUM_ISA_INTERRUPTS &&
@@ -991,7 +1037,7 @@ unsigned int irq_alloc_virt(struct irq_host *host,
                 }
         }
         if (found == NO_IRQ) {
-                spin_unlock_irqrestore(&irq_big_lock, flags);
+                raw_spin_unlock_irqrestore(&irq_big_lock, flags);
                 return NO_IRQ;
         }
  hint_found:
@@ -1000,7 +1046,7 @@ unsigned int irq_alloc_virt(struct irq_host *host,
                 smp_wmb();
                 irq_map[i].host = host;
         }
-        spin_unlock_irqrestore(&irq_big_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
         return found;
 }
 
@@ -1012,7 +1058,7 @@ void irq_free_virt(unsigned int virq, unsigned int count)
         WARN_ON (virq < NUM_ISA_INTERRUPTS);
         WARN_ON (count == 0 || (virq + count) > irq_virq_count);
 
-        spin_lock_irqsave(&irq_big_lock, flags);
+        raw_spin_lock_irqsave(&irq_big_lock, flags);
         for (i = virq; i < (virq + count); i++) {
                 struct irq_host *host;
 
@@ -1025,7 +1071,7 @@ void irq_free_virt(unsigned int virq, unsigned int count)
                 smp_wmb();
                 irq_map[i].host = NULL;
         }
-        spin_unlock_irqrestore(&irq_big_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_big_lock, flags);
 }
 
 int arch_early_irq_init(void)
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index b6bd1eaa1c24..41bada0298c8 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -333,7 +333,7 @@ int kgdb_arch_handle_exception(int vector, int signo, int err_code,
                 atomic_set(&kgdb_cpu_doing_single_step, -1);
                 /* set the trace bit if we're stepping */
                 if (remcom_in_buffer[0] == 's') {
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
                         mtspr(SPRN_DBCR0,
                               mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
                         linux_regs->msr |= MSR_DE;
diff --git a/arch/powerpc/kernel/kprobes.c b/arch/powerpc/kernel/kprobes.c
index c9329786073b..3fd1af902112 100644
--- a/arch/powerpc/kernel/kprobes.c
+++ b/arch/powerpc/kernel/kprobes.c
@@ -36,7 +36,7 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_BOOKE
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 #define MSR_SINGLESTEP  (MSR_DE)
 #else
 #define MSR_SINGLESTEP  (MSR_SE)
@@ -110,7 +110,7 @@ static void __kprobes prepare_singlestep(struct kprobe *p, struct pt_regs *regs)
          * like Decrementer or External Interrupt */
         regs->msr &= ~MSR_EE;
         regs->msr |= MSR_SINGLESTEP;
-#ifdef CONFIG_BOOKE
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
         regs->msr &= ~MSR_CE;
         mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR0_IC | DBCR0_IDM);
 #endif
diff --git a/arch/powerpc/kernel/lparcfg.c b/arch/powerpc/kernel/lparcfg.c
index 79a00bb9c64c..d09d1c615150 100644
--- a/arch/powerpc/kernel/lparcfg.c
+++ b/arch/powerpc/kernel/lparcfg.c
@@ -359,7 +359,7 @@ static void parse_system_parameter_string(struct seq_file *m)
 
         unsigned char *local_buffer = kmalloc(SPLPAR_MAXLENGTH, GFP_KERNEL);
         if (!local_buffer) {
-                printk(KERN_ERR "%s %s kmalloc failure at line %d \n",
+                printk(KERN_ERR "%s %s kmalloc failure at line %d\n",
                        __FILE__, __func__, __LINE__);
                 return;
         }
@@ -383,13 +383,13 @@ static void parse_system_parameter_string(struct seq_file *m)
                 int idx, w_idx;
                 char *workbuffer = kzalloc(SPLPAR_MAXLENGTH, GFP_KERNEL);
                 if (!workbuffer) {
-                        printk(KERN_ERR "%s %s kmalloc failure at line %d \n",
+                        printk(KERN_ERR "%s %s kmalloc failure at line %d\n",
                                __FILE__, __func__, __LINE__);
                         kfree(local_buffer);
                         return;
                 }
 #ifdef LPARCFG_DEBUG
-                printk(KERN_INFO "success calling get-system-parameter \n");
+                printk(KERN_INFO "success calling get-system-parameter\n");
 #endif
                 splpar_strlen = local_buffer[0] * 256 + local_buffer[1];
                 local_buffer += 2;      /* step over strlen value */
@@ -440,7 +440,7 @@ static int lparcfg_count_active_processors(void)
 
         while ((cpus_dn = of_find_node_by_type(cpus_dn, "cpu"))) {
 #ifdef LPARCFG_DEBUG
-                printk(KERN_ERR "cpus_dn %p \n", cpus_dn);
+                printk(KERN_ERR "cpus_dn %p\n", cpus_dn);
 #endif
                 count++;
         }
@@ -725,7 +725,7 @@ static int lparcfg_data(struct seq_file *m, void *v)
         const unsigned int *lp_index_ptr;
         unsigned int lp_index = 0;
 
-        seq_printf(m, "%s %s \n", MODULE_NAME, MODULE_VERS);
+        seq_printf(m, "%s %s\n", MODULE_NAME, MODULE_VERS);
 
         rootdn = of_find_node_by_path("/");
         if (rootdn) {
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c
index ad461e735aec..9cf197f01e94 100644
--- a/arch/powerpc/kernel/nvram_64.c
+++ b/arch/powerpc/kernel/nvram_64.c
@@ -338,8 +338,8 @@ static int __init nvram_create_os_partition(void)
 
         rc = nvram_write_header(new_part);
         if (rc <= 0) {
-                printk(KERN_ERR "nvram_create_os_partition: nvram_write_header \
-                                failed (%d)\n", rc);
+                printk(KERN_ERR "nvram_create_os_partition: nvram_write_header "
+                                "failed (%d)\n", rc);
                 return rc;
         }
 
@@ -349,7 +349,7 @@ static int __init nvram_create_os_partition(void)
         rc = ppc_md.nvram_write((char *)&seq_init, sizeof(seq_init), &tmp_index);
         if (rc <= 0) {
                 printk(KERN_ERR "nvram_create_os_partition: nvram_write "
-                                "failed (%d)\n", rc);
+                       "failed (%d)\n", rc);
                 return rc;
         }
         
diff --git a/arch/powerpc/kernel/of_platform.c b/arch/powerpc/kernel/of_platform.c
index 1a4fc0d11a03..666d08db319e 100644
--- a/arch/powerpc/kernel/of_platform.c
+++ b/arch/powerpc/kernel/of_platform.c
@@ -214,7 +214,7 @@ EXPORT_SYMBOL(of_find_device_by_node);
 static int of_dev_phandle_match(struct device *dev, void *data)
 {
         phandle *ph = data;
-        return to_of_device(dev)->node->linux_phandle == *ph;
+        return to_of_device(dev)->node->phandle == *ph;
 }
 
 struct of_device *of_find_device_by_phandle(phandle ph)
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index cadbed679fbb..2597f9545d8a 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -1047,10 +1047,8 @@ static void __devinit pcibios_fixup_bridge(struct pci_bus *bus)
 
         struct pci_dev *dev = bus->self;
 
-        for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
-                if ((res = bus->resource[i]) == NULL)
-                        continue;
-                if (!res->flags)
+        pci_bus_for_each_resource(bus, res, i) {
+                if (!res || !res->flags)
                         continue;
                 if (i >= 3 && bus->self->transparent)
                         continue;
@@ -1181,21 +1179,20 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-void pcibios_align_resource(void *data, struct resource *res,
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
                                 resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
+        resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO) {
-                resource_size_t start = res->start;
-
                 if (skip_isa_ioresource_align(dev))
-                        return;
-                if (start & 0x300) {
+                        return start;
+                if (start & 0x300)
                         start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
         }
+
+        return start;
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
@@ -1278,9 +1275,8 @@ void pcibios_allocate_bus_resources(struct pci_bus *bus)
         pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
                  pci_domain_nr(bus), bus->number);
 
-        for (i = 0; i < PCI_BUS_NUM_RESOURCES; ++i) {
-                if ((res = bus->resource[i]) == NULL || !res->flags
-                    || res->start > res->end || res->parent)
+        pci_bus_for_each_resource(bus, res, i) {
+                if (!res || !res->flags || res->start > res->end || res->parent)
                         continue;
                 if (bus->parent == NULL)
                         pr = (res->flags & IORESOURCE_IO) ?
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index ccf56ac92de5..d43fc65749c1 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -224,7 +224,7 @@ long sys_pciconfig_iobase(long which, unsigned long in_bus,
          * G5 machines... So when something asks for bus 0 io base
          * (bus 0 is HT root), we return the AGP one instead.
          */
-        if (in_bus == 0 && machine_is_compatible("MacRISC4")) {
+        if (in_bus == 0 && of_machine_is_compatible("MacRISC4")) {
                 struct device_node *agp;
 
                 agp = of_find_compatible_node(NULL, NULL, "u3-agp");
diff --git a/arch/powerpc/kernel/pci_of_scan.c b/arch/powerpc/kernel/pci_of_scan.c
index 4aa17401657b..cd11d5ca80df 100644
--- a/arch/powerpc/kernel/pci_of_scan.c
+++ b/arch/powerpc/kernel/pci_of_scan.c
@@ -304,7 +304,7 @@ static void __devinit __of_scan_bus(struct device_node *node,
         int reglen, devfn;
         struct pci_dev *dev;
 
-        pr_debug("of_scan_bus(%s) bus no %d... \n",
+        pr_debug("of_scan_bus(%s) bus no %d...\n",
                  node->full_name, bus->number);
 
         /* Scan direct children */
diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c
index a3c11cac3d71..95ad9dad298e 100644
--- a/arch/powerpc/kernel/perf_callchain.c
+++ b/arch/powerpc/kernel/perf_callchain.c
@@ -495,9 +495,6 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
 
         entry->nr = 0;
 
-        if (current->pid == 0)          /* idle task? */
-                return entry;
-
         if (!user_mode(regs)) {
                 perf_callchain_kernel(regs, entry);
                 if (current->mm)
diff --git a/arch/powerpc/kernel/perf_event.c b/arch/powerpc/kernel/perf_event.c
index 1eb85fbf53a5..b6cf8f1f4d35 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -718,10 +718,10 @@ static int collect_events(struct perf_event *group, int max_count,
         return n;
 }
 
-static void event_sched_in(struct perf_event *event, int cpu)
+static void event_sched_in(struct perf_event *event)
 {
         event->state = PERF_EVENT_STATE_ACTIVE;
-        event->oncpu = cpu;
+        event->oncpu = smp_processor_id();
         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
         if (is_software_event(event))
                 event->pmu->enable(event);
@@ -735,7 +735,7 @@ static void event_sched_in(struct perf_event *event, int cpu)
  */
 int hw_perf_group_sched_in(struct perf_event *group_leader,
                struct perf_cpu_context *cpuctx,
-               struct perf_event_context *ctx, int cpu)
+               struct perf_event_context *ctx)
 {
         struct cpu_hw_events *cpuhw;
         long i, n, n0;
@@ -766,10 +766,10 @@ int hw_perf_group_sched_in(struct perf_event *group_leader,
                 cpuhw->event[i]->hw.config = cpuhw->events[i];
         cpuctx->active_oncpu += n;
         n = 1;
-        event_sched_in(group_leader, cpu);
+        event_sched_in(group_leader);
         list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
                 if (sub->state != PERF_EVENT_STATE_OFF) {
-                        event_sched_in(sub, cpu);
+                        event_sched_in(sub);
                         ++n;
                 }
         }
diff --git a/arch/powerpc/kernel/pmc.c b/arch/powerpc/kernel/pmc.c
index 0516e2d3e02e..461499b43cff 100644
--- a/arch/powerpc/kernel/pmc.c
+++ b/arch/powerpc/kernel/pmc.c
@@ -37,7 +37,7 @@ static void dummy_perf(struct pt_regs *regs)
 }
 
 
-static DEFINE_SPINLOCK(pmc_owner_lock);
+static DEFINE_RAW_SPINLOCK(pmc_owner_lock);
 static void *pmc_owner_caller; /* mostly for debugging */
 perf_irq_t perf_irq = dummy_perf;
 
@@ -45,7 +45,7 @@ int reserve_pmc_hardware(perf_irq_t new_perf_irq)
 {
         int err = 0;
 
-        spin_lock(&pmc_owner_lock);
+        raw_spin_lock(&pmc_owner_lock);
 
         if (pmc_owner_caller) {
                 printk(KERN_WARNING "reserve_pmc_hardware: "
@@ -59,21 +59,21 @@ int reserve_pmc_hardware(perf_irq_t new_perf_irq)
         perf_irq = new_perf_irq ? new_perf_irq : dummy_perf;
 
  out:
-        spin_unlock(&pmc_owner_lock);
+        raw_spin_unlock(&pmc_owner_lock);
         return err;
 }
 EXPORT_SYMBOL_GPL(reserve_pmc_hardware);
 
 void release_pmc_hardware(void)
 {
-        spin_lock(&pmc_owner_lock);
+        raw_spin_lock(&pmc_owner_lock);
 
         WARN_ON(! pmc_owner_caller);
 
         pmc_owner_caller = NULL;
         perf_irq = dummy_perf;
 
-        spin_unlock(&pmc_owner_lock);
+        raw_spin_unlock(&pmc_owner_lock);
 }
 EXPORT_SYMBOL_GPL(release_pmc_hardware);
 
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 7b816daf3eba..e4d71ced97ef 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -245,6 +245,24 @@ void discard_lazy_cpu_state(void)
 }
 #endif /* CONFIG_SMP */
 
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+void do_send_trap(struct pt_regs *regs, unsigned long address,
+                  unsigned long error_code, int signal_code, int breakpt)
+{
+        siginfo_t info;
+
+        if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
+                        11, SIGSEGV) == NOTIFY_STOP)
+                return;
+
+        /* Deliver the signal to userspace */
+        info.si_signo = SIGTRAP;
+        info.si_errno = breakpt;        /* breakpoint or watchpoint id */
+        info.si_code = signal_code;
+        info.si_addr = (void __user *)address;
+        force_sig_info(SIGTRAP, &info, current);
+}
+#else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 void do_dabr(struct pt_regs *regs, unsigned long address,
                     unsigned long error_code)
 {
@@ -257,12 +275,6 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
         if (debugger_dabr_match(regs))
                 return;
 
-        /* Clear the DAC and struct entries.  One shot trigger */
-#if defined(CONFIG_BOOKE)
-        mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R | DBSR_DAC1W
-                                                        | DBCR0_IDM));
-#endif
-
         /* Clear the DABR */
         set_dabr(0);
 
@@ -273,9 +285,82 @@ void do_dabr(struct pt_regs *regs, unsigned long address,
         info.si_addr = (void __user *)address;
         force_sig_info(SIGTRAP, &info, current);
 }
+#endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 
 static DEFINE_PER_CPU(unsigned long, current_dabr);
 
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+/*
+ * Set the debug registers back to their default "safe" values.
+ */
+static void set_debug_reg_defaults(struct thread_struct *thread)
+{
+        thread->iac1 = thread->iac2 = 0;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+        thread->iac3 = thread->iac4 = 0;
+#endif
+        thread->dac1 = thread->dac2 = 0;
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+        thread->dvc1 = thread->dvc2 = 0;
+#endif
+        thread->dbcr0 = 0;
+#ifdef CONFIG_BOOKE
+        /*
+         * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
+         */
+        thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |   \
+                        DBCR1_IAC3US | DBCR1_IAC4US;
+        /*
+         * Force Data Address Compare User/Supervisor bits to be User-only
+         * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
+         */
+        thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
+#else
+        thread->dbcr1 = 0;
+#endif
+}
+
+static void prime_debug_regs(struct thread_struct *thread)
+{
+        mtspr(SPRN_IAC1, thread->iac1);
+        mtspr(SPRN_IAC2, thread->iac2);
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+        mtspr(SPRN_IAC3, thread->iac3);
+        mtspr(SPRN_IAC4, thread->iac4);
+#endif
+        mtspr(SPRN_DAC1, thread->dac1);
+        mtspr(SPRN_DAC2, thread->dac2);
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+        mtspr(SPRN_DVC1, thread->dvc1);
+        mtspr(SPRN_DVC2, thread->dvc2);
+#endif
+        mtspr(SPRN_DBCR0, thread->dbcr0);
+        mtspr(SPRN_DBCR1, thread->dbcr1);
+#ifdef CONFIG_BOOKE
+        mtspr(SPRN_DBCR2, thread->dbcr2);
+#endif
+}
+/*
+ * Unless neither the old or new thread are making use of the
+ * debug registers, set the debug registers from the values
+ * stored in the new thread.
+ */
+static void switch_booke_debug_regs(struct thread_struct *new_thread)
+{
+        if ((current->thread.dbcr0 & DBCR0_IDM)
+                || (new_thread->dbcr0 & DBCR0_IDM))
+                        prime_debug_regs(new_thread);
+}
+#else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
+static void set_debug_reg_defaults(struct thread_struct *thread)
+{
+        if (thread->dabr) {
+                thread->dabr = 0;
+                set_dabr(0);
+        }
+}
+#endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
+
 int set_dabr(unsigned long dabr)
 {
         __get_cpu_var(current_dabr) = dabr;
@@ -284,7 +369,7 @@ int set_dabr(unsigned long dabr)
                 return ppc_md.set_dabr(dabr);
 
         /* XXX should we have a CPU_FTR_HAS_DABR ? */
-#if defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
         mtspr(SPRN_DAC1, dabr);
 #elif defined(CONFIG_PPC_BOOK3S)
         mtspr(SPRN_DABR, dabr);
@@ -371,10 +456,8 @@ struct task_struct *__switch_to(struct task_struct *prev,
 
 #endif /* CONFIG_SMP */
 
-#if defined(CONFIG_BOOKE)
-        /* If new thread DAC (HW breakpoint) is the same then leave it */
-        if (new->thread.dabr)
-                set_dabr(new->thread.dabr);
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+        switch_booke_debug_regs(&new->thread);
 #else
         if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
                 set_dabr(new->thread.dabr);
@@ -514,7 +597,7 @@ void show_regs(struct pt_regs * regs)
         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
         trap = TRAP(regs);
         if (trap == 0x300 || trap == 0x600)
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
                 printk("DEAR: "REG", ESR: "REG"\n", regs->dar, regs->dsisr);
 #else
                 printk("DAR: "REG", DSISR: "REG"\n", regs->dar, regs->dsisr);
@@ -556,14 +639,7 @@ void flush_thread(void)
 {
         discard_lazy_cpu_state();
 
-        if (current->thread.dabr) {
-                current->thread.dabr = 0;
-                set_dabr(0);
-
-#if defined(CONFIG_BOOKE)
-                current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W);
-#endif
-        }
+        set_debug_reg_defaults(&current->thread);
 }
 
 void
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 4ec300862466..43238b2054b6 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -61,365 +61,12 @@
 #define DBG(fmt...)
 #endif
 
-
-static int __initdata dt_root_addr_cells;
-static int __initdata dt_root_size_cells;
-
 #ifdef CONFIG_PPC64
 int __initdata iommu_is_off;
 int __initdata iommu_force_on;
 unsigned long tce_alloc_start, tce_alloc_end;
 #endif
 
-typedef u32 cell_t;
-
-#if 0
-static struct boot_param_header *initial_boot_params __initdata;
-#else
-struct boot_param_header *initial_boot_params;
-#endif
-
-extern struct device_node *allnodes;    /* temporary while merging */
-
-extern rwlock_t devtree_lock;   /* temporary while merging */
-
-/* export that to outside world */
-struct device_node *of_chosen;
-
-static inline char *find_flat_dt_string(u32 offset)
-{
-        return ((char *)initial_boot_params) +
-                initial_boot_params->off_dt_strings + offset;
-}
-
-/**
- * This function is used to scan the flattened device-tree, it is
- * used to extract the memory informations at boot before we can
- * unflatten the tree
- */
-int __init of_scan_flat_dt(int (*it)(unsigned long node,
-                                     const char *uname, int depth,
-                                     void *data),
-                           void *data)
-{
-        unsigned long p = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-        int rc = 0;
-        int depth = -1;
-
-        do {
-                u32 tag = *((u32 *)p);
-                char *pathp;
-                
-                p += 4;
-                if (tag == OF_DT_END_NODE) {
-                        depth --;
-                        continue;
-                }
-                if (tag == OF_DT_NOP)
-                        continue;
-                if (tag == OF_DT_END)
-                        break;
-                if (tag == OF_DT_PROP) {
-                        u32 sz = *((u32 *)p);
-                        p += 8;
-                        if (initial_boot_params->version < 0x10)
-                                p = _ALIGN(p, sz >= 8 ? 8 : 4);
-                        p += sz;
-                        p = _ALIGN(p, 4);
-                        continue;
-                }
-                if (tag != OF_DT_BEGIN_NODE) {
-                        printk(KERN_WARNING "Invalid tag %x scanning flattened"
-                               " device tree !\n", tag);
-                        return -EINVAL;
-                }
-                depth++;
-                pathp = (char *)p;
-                p = _ALIGN(p + strlen(pathp) + 1, 4);
-                if ((*pathp) == '/') {
-                        char *lp, *np;
-                        for (lp = NULL, np = pathp; *np; np++)
-                                if ((*np) == '/')
-                                        lp = np+1;
-                        if (lp != NULL)
-                                pathp = lp;
-                }
-                rc = it(p, pathp, depth, data);
-                if (rc != 0)
-                        break;          
-        } while(1);
-
-        return rc;
-}
-
-unsigned long __init of_get_flat_dt_root(void)
-{
-        unsigned long p = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-
-        while(*((u32 *)p) == OF_DT_NOP)
-                p += 4;
-        BUG_ON (*((u32 *)p) != OF_DT_BEGIN_NODE);
-        p += 4;
-        return _ALIGN(p + strlen((char *)p) + 1, 4);
-}
-
-/**
- * This  function can be used within scan_flattened_dt callback to get
- * access to properties
- */
-void* __init of_get_flat_dt_prop(unsigned long node, const char *name,
-                                 unsigned long *size)
-{
-        unsigned long p = node;
-
-        do {
-                u32 tag = *((u32 *)p);
-                u32 sz, noff;
-                const char *nstr;
-
-                p += 4;
-                if (tag == OF_DT_NOP)
-                        continue;
-                if (tag != OF_DT_PROP)
-                        return NULL;
-
-                sz = *((u32 *)p);
-                noff = *((u32 *)(p + 4));
-                p += 8;
-                if (initial_boot_params->version < 0x10)
-                        p = _ALIGN(p, sz >= 8 ? 8 : 4);
-
-                nstr = find_flat_dt_string(noff);
-                if (nstr == NULL) {
-                        printk(KERN_WARNING "Can't find property index"
-                               " name !\n");
-                        return NULL;
-                }
-                if (strcmp(name, nstr) == 0) {
-                        if (size)
-                                *size = sz;
-                        return (void *)p;
-                }
-                p += sz;
-                p = _ALIGN(p, 4);
-        } while(1);
-}
-
-int __init of_flat_dt_is_compatible(unsigned long node, const char *compat)
-{
-        const char* cp;
-        unsigned long cplen, l;
-
-        cp = of_get_flat_dt_prop(node, "compatible", &cplen);
-        if (cp == NULL)
-                return 0;
-        while (cplen > 0) {
-                if (strncasecmp(cp, compat, strlen(compat)) == 0)
-                        return 1;
-                l = strlen(cp) + 1;
-                cp += l;
-                cplen -= l;
-        }
-
-        return 0;
-}
-
-static void *__init unflatten_dt_alloc(unsigned long *mem, unsigned long size,
-                                       unsigned long align)
-{
-        void *res;
-
-        *mem = _ALIGN(*mem, align);
-        res = (void *)*mem;
-        *mem += size;
-
-        return res;
-}
-
-static unsigned long __init unflatten_dt_node(unsigned long mem,
-                                              unsigned long *p,
-                                              struct device_node *dad,
-                                              struct device_node ***allnextpp,
-                                              unsigned long fpsize)
-{
-        struct device_node *np;
-        struct property *pp, **prev_pp = NULL;
-        char *pathp;
-        u32 tag;
-        unsigned int l, allocl;
-        int has_name = 0;
-        int new_format = 0;
-
-        tag = *((u32 *)(*p));
-        if (tag != OF_DT_BEGIN_NODE) {
-                printk("Weird tag at start of node: %x\n", tag);
-                return mem;
-        }
-        *p += 4;
-        pathp = (char *)*p;
-        l = allocl = strlen(pathp) + 1;
-        *p = _ALIGN(*p + l, 4);
-
-        /* version 0x10 has a more compact unit name here instead of the full
-         * path. we accumulate the full path size using "fpsize", we'll rebuild
-         * it later. We detect this because the first character of the name is
-         * not '/'.
-         */
-        if ((*pathp) != '/') {
-                new_format = 1;
-                if (fpsize == 0) {
-                        /* root node: special case. fpsize accounts for path
-                         * plus terminating zero. root node only has '/', so
-                         * fpsize should be 2, but we want to avoid the first
-                         * level nodes to have two '/' so we use fpsize 1 here
-                         */
-                        fpsize = 1;
-                        allocl = 2;
-                } else {
-                        /* account for '/' and path size minus terminal 0
-                         * already in 'l'
-                         */
-                        fpsize += l;
-                        allocl = fpsize;
-                }
-        }
-
-
-        np = unflatten_dt_alloc(&mem, sizeof(struct device_node) + allocl,
-                                __alignof__(struct device_node));
-        if (allnextpp) {
-                memset(np, 0, sizeof(*np));
-                np->full_name = ((char*)np) + sizeof(struct device_node);
-                if (new_format) {
-                        char *p = np->full_name;
-                        /* rebuild full path for new format */
-                        if (dad && dad->parent) {
-                                strcpy(p, dad->full_name);
-#ifdef DEBUG
-                                if ((strlen(p) + l + 1) != allocl) {
-                                        DBG("%s: p: %d, l: %d, a: %d\n",
-                                            pathp, (int)strlen(p), l, allocl);
-                                }
-#endif
-                                p += strlen(p);
-                        }
-                        *(p++) = '/';
-                        memcpy(p, pathp, l);
-                } else
-                        memcpy(np->full_name, pathp, l);
-                prev_pp = &np->properties;
-                **allnextpp = np;
-                *allnextpp = &np->allnext;
-                if (dad != NULL) {
-                        np->parent = dad;
-                        /* we temporarily use the next field as `last_child'*/
-                        if (dad->next == 0)
-                                dad->child = np;
-                        else
-                                dad->next->sibling = np;
-                        dad->next = np;
-                }
-                kref_init(&np->kref);
-        }
-        while(1) {
-                u32 sz, noff;
-                char *pname;
-
-                tag = *((u32 *)(*p));
-                if (tag == OF_DT_NOP) {
-                        *p += 4;
-                        continue;
-                }
-                if (tag != OF_DT_PROP)
-                        break;
-                *p += 4;
-                sz = *((u32 *)(*p));
-                noff = *((u32 *)((*p) + 4));
-                *p += 8;
-                if (initial_boot_params->version < 0x10)
-                        *p = _ALIGN(*p, sz >= 8 ? 8 : 4);
-
-                pname = find_flat_dt_string(noff);
-                if (pname == NULL) {
-                        printk("Can't find property name in list !\n");
-                        break;
-                }
-                if (strcmp(pname, "name") == 0)
-                        has_name = 1;
-                l = strlen(pname) + 1;
-                pp = unflatten_dt_alloc(&mem, sizeof(struct property),
-                                        __alignof__(struct property));
-                if (allnextpp) {
-                        if (strcmp(pname, "linux,phandle") == 0) {
-                                np->node = *((u32 *)*p);
-                                if (np->linux_phandle == 0)
-                                        np->linux_phandle = np->node;
-                        }
-                        if (strcmp(pname, "ibm,phandle") == 0)
-                                np->linux_phandle = *((u32 *)*p);
-                        pp->name = pname;
-                        pp->length = sz;
-                        pp->value = (void *)*p;
-                        *prev_pp = pp;
-                        prev_pp = &pp->next;
-                }
-                *p = _ALIGN((*p) + sz, 4);
-        }
-        /* with version 0x10 we may not have the name property, recreate
-         * it here from the unit name if absent
-         */
-        if (!has_name) {
-                char *p = pathp, *ps = pathp, *pa = NULL;
-                int sz;
-
-                while (*p) {
-                        if ((*p) == '@')
-                                pa = p;
-                        if ((*p) == '/')
-                                ps = p + 1;
-                        p++;
-                }
-                if (pa < ps)
-                        pa = p;
-                sz = (pa - ps) + 1;
-                pp = unflatten_dt_alloc(&mem, sizeof(struct property) + sz,
-                                        __alignof__(struct property));
-                if (allnextpp) {
-                        pp->name = "name";
-                        pp->length = sz;
-                        pp->value = pp + 1;
-                        *prev_pp = pp;
-                        prev_pp = &pp->next;
-                        memcpy(pp->value, ps, sz - 1);
-                        ((char *)pp->value)[sz - 1] = 0;
-                        DBG("fixed up name for %s -> %s\n", pathp,
-                                (char *)pp->value);
-                }
-        }
-        if (allnextpp) {
-                *prev_pp = NULL;
-                np->name = of_get_property(np, "name", NULL);
-                np->type = of_get_property(np, "device_type", NULL);
-
-                if (!np->name)
-                        np->name = "<NULL>";
-                if (!np->type)
-                        np->type = "<NULL>";
-        }
-        while (tag == OF_DT_BEGIN_NODE) {
-                mem = unflatten_dt_node(mem, p, np, allnextpp, fpsize);
-                tag = *((u32 *)(*p));
-        }
-        if (tag != OF_DT_END_NODE) {
-                printk("Weird tag at end of node: %x\n", tag);
-                return mem;
-        }
-        *p += 4;
-        return mem;
-}
-
 static int __init early_parse_mem(char *p)
 {
         if (!p)
@@ -446,7 +93,7 @@ static void __init move_device_tree(void)
         DBG("-> move_device_tree\n");
 
         start = __pa(initial_boot_params);
-        size = initial_boot_params->totalsize;
+        size = be32_to_cpu(initial_boot_params->totalsize);
 
         if ((memory_limit && (start + size) > memory_limit) ||
                         overlaps_crashkernel(start, size)) {
@@ -459,54 +106,6 @@ static void __init move_device_tree(void)
         DBG("<- move_device_tree\n");
 }
 
-/**
- * unflattens the device-tree passed by the firmware, creating the
- * tree of struct device_node. It also fills the "name" and "type"
- * pointers of the nodes so the normal device-tree walking functions
- * can be used (this used to be done by finish_device_tree)
- */
-void __init unflatten_device_tree(void)
-{
-        unsigned long start, mem, size;
-        struct device_node **allnextp = &allnodes;
-
-        DBG(" -> unflatten_device_tree()\n");
-
-        /* First pass, scan for size */
-        start = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-        size = unflatten_dt_node(0, &start, NULL, NULL, 0);
-        size = (size | 3) + 1;
-
-        DBG("  size is %lx, allocating...\n", size);
-
-        /* Allocate memory for the expanded device tree */
-        mem = lmb_alloc(size + 4, __alignof__(struct device_node));
-        mem = (unsigned long) __va(mem);
-
-        ((u32 *)mem)[size / 4] = 0xdeadbeef;
-
-        DBG("  unflattening %lx...\n", mem);
-
-        /* Second pass, do actual unflattening */
-        start = ((unsigned long)initial_boot_params) +
-                initial_boot_params->off_dt_struct;
-        unflatten_dt_node(mem, &start, NULL, &allnextp, 0);
-        if (*((u32 *)start) != OF_DT_END)
-                printk(KERN_WARNING "Weird tag at end of tree: %08x\n", *((u32 *)start));
-        if (((u32 *)mem)[size / 4] != 0xdeadbeef)
-                printk(KERN_WARNING "End of tree marker overwritten: %08x\n",
-                       ((u32 *)mem)[size / 4] );
-        *allnextp = NULL;
-
-        /* Get pointer to OF "/chosen" node for use everywhere */
-        of_chosen = of_find_node_by_path("/chosen");
-        if (of_chosen == NULL)
-                of_chosen = of_find_node_by_path("/chosen@0");
-
-        DBG(" <- unflatten_device_tree()\n");
-}
-
 /*
  * ibm,pa-features is a per-cpu property that contains a string of
  * attribute descriptors, each of which has a 2 byte header plus up
@@ -763,48 +362,9 @@ static int __init early_init_dt_scan_cpus(unsigned long node,
         return 0;
 }
 
-#ifdef CONFIG_BLK_DEV_INITRD
-static void __init early_init_dt_check_for_initrd(unsigned long node)
-{
-        unsigned long l;
-        u32 *prop;
-
-        DBG("Looking for initrd properties... ");
-
-        prop = of_get_flat_dt_prop(node, "linux,initrd-start", &l);
-        if (prop) {
-                initrd_start = (unsigned long)__va(of_read_ulong(prop, l/4));
-
-                prop = of_get_flat_dt_prop(node, "linux,initrd-end", &l);
-                if (prop) {
-                        initrd_end = (unsigned long)
-                                        __va(of_read_ulong(prop, l/4));
-                        initrd_below_start_ok = 1;
-                } else {
-                        initrd_start = 0;
-                }
-        }
-
-        DBG("initrd_start=0x%lx  initrd_end=0x%lx\n", initrd_start, initrd_end);
-}
-#else
-static inline void early_init_dt_check_for_initrd(unsigned long node)
-{
-}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-static int __init early_init_dt_scan_chosen(unsigned long node,
-                                            const char *uname, int depth, void *data)
+void __init early_init_dt_scan_chosen_arch(unsigned long node)
 {
         unsigned long *lprop;
-        unsigned long l;
-        char *p;
-
-        DBG("search \"chosen\", depth: %d, uname: %s\n", depth, uname);
-
-        if (depth != 1 ||
-            (strcmp(uname, "chosen") != 0 && strcmp(uname, "chosen@0") != 0))
-                return 0;
 
 #ifdef CONFIG_PPC64
         /* check if iommu is forced on or off */
@@ -815,17 +375,17 @@ static int __init early_init_dt_scan_chosen(unsigned long node,
 #endif
 
         /* mem=x on the command line is the preferred mechanism */
-        lprop = of_get_flat_dt_prop(node, "linux,memory-limit", NULL);
-        if (lprop)
-                memory_limit = *lprop;
+        lprop = of_get_flat_dt_prop(node, "linux,memory-limit", NULL);
+        if (lprop)
+                memory_limit = *lprop;
 
 #ifdef CONFIG_PPC64
-        lprop = of_get_flat_dt_prop(node, "linux,tce-alloc-start", NULL);
-        if (lprop)
-                tce_alloc_start = *lprop;
-        lprop = of_get_flat_dt_prop(node, "linux,tce-alloc-end", NULL);
-        if (lprop)
-                tce_alloc_end = *lprop;
+        lprop = of_get_flat_dt_prop(node, "linux,tce-alloc-start", NULL);
+        if (lprop)
+                tce_alloc_start = *lprop;
+        lprop = of_get_flat_dt_prop(node, "linux,tce-alloc-end", NULL);
+        if (lprop)
+                tce_alloc_end = *lprop;
 #endif
 
 #ifdef CONFIG_KEXEC
@@ -837,51 +397,6 @@ static int __init early_init_dt_scan_chosen(unsigned long node,
         if (lprop)
                 crashk_res.end = crashk_res.start + *lprop - 1;
 #endif
-
-        early_init_dt_check_for_initrd(node);
-
-        /* Retreive command line */
-        p = of_get_flat_dt_prop(node, "bootargs", &l);
-        if (p != NULL && l > 0)
-                strlcpy(cmd_line, p, min((int)l, COMMAND_LINE_SIZE));
-
-#ifdef CONFIG_CMDLINE
-        if (p == NULL || l == 0 || (l == 1 && (*p) == 0))
-                strlcpy(cmd_line, CONFIG_CMDLINE, COMMAND_LINE_SIZE);
-#endif /* CONFIG_CMDLINE */
-
-        DBG("Command line is: %s\n", cmd_line);
-
-        /* break now */
-        return 1;
-}
-
-static int __init early_init_dt_scan_root(unsigned long node,
-                                          const char *uname, int depth, void *data)
-{
-        u32 *prop;
-
-        if (depth != 0)
-                return 0;
-
-        prop = of_get_flat_dt_prop(node, "#size-cells", NULL);
-        dt_root_size_cells = (prop == NULL) ? 1 : *prop;
-        DBG("dt_root_size_cells = %x\n", dt_root_size_cells);
-
-        prop = of_get_flat_dt_prop(node, "#address-cells", NULL);
-        dt_root_addr_cells = (prop == NULL) ? 2 : *prop;
-        DBG("dt_root_addr_cells = %x\n", dt_root_addr_cells);
-        
-        /* break now */
-        return 1;
-}
-
-static u64 __init dt_mem_next_cell(int s, cell_t **cellp)
-{
-        cell_t *p = *cellp;
-
-        *cellp = p + s;
-        return of_read_number(p, s);
 }
 
 #ifdef CONFIG_PPC_PSERIES
@@ -893,22 +408,22 @@ static u64 __init dt_mem_next_cell(int s, cell_t **cellp)
  */
 static int __init early_init_dt_scan_drconf_memory(unsigned long node)
 {
-        cell_t *dm, *ls, *usm;
+        __be32 *dm, *ls, *usm;
         unsigned long l, n, flags;
         u64 base, size, lmb_size;
         unsigned int is_kexec_kdump = 0, rngs;
 
         ls = of_get_flat_dt_prop(node, "ibm,lmb-size", &l);
-        if (ls == NULL || l < dt_root_size_cells * sizeof(cell_t))
+        if (ls == NULL || l < dt_root_size_cells * sizeof(__be32))
                 return 0;
         lmb_size = dt_mem_next_cell(dt_root_size_cells, &ls);
 
         dm = of_get_flat_dt_prop(node, "ibm,dynamic-memory", &l);
-        if (dm == NULL || l < sizeof(cell_t))
+        if (dm == NULL || l < sizeof(__be32))
                 return 0;
 
         n = *dm++;      /* number of entries */
-        if (l < (n * (dt_root_addr_cells + 4) + 1) * sizeof(cell_t))
+        if (l < (n * (dt_root_addr_cells + 4) + 1) * sizeof(__be32))
                 return 0;
 
         /* check if this is a kexec/kdump kernel. */
@@ -963,65 +478,47 @@ static int __init early_init_dt_scan_drconf_memory(unsigned long node)
 #define early_init_dt_scan_drconf_memory(node)  0
 #endif /* CONFIG_PPC_PSERIES */
 
-static int __init early_init_dt_scan_memory(unsigned long node,
-                                            const char *uname, int depth, void *data)
+static int __init early_init_dt_scan_memory_ppc(unsigned long node,
+                                                const char *uname,
+                                                int depth, void *data)
 {
-        char *type = of_get_flat_dt_prop(node, "device_type", NULL);
-        cell_t *reg, *endp;
-        unsigned long l;
-
-        /* Look for the ibm,dynamic-reconfiguration-memory node */
         if (depth == 1 &&
             strcmp(uname, "ibm,dynamic-reconfiguration-memory") == 0)
                 return early_init_dt_scan_drconf_memory(node);
+        
+        return early_init_dt_scan_memory(node, uname, depth, data);
+}
 
-        /* We are scanning "memory" nodes only */
-        if (type == NULL) {
-                /*
-                 * The longtrail doesn't have a device_type on the
-                 * /memory node, so look for the node called /memory@0.
-                 */
-                if (depth != 1 || strcmp(uname, "memory@0") != 0)
-                        return 0;
-        } else if (strcmp(type, "memory") != 0)
-                return 0;
-
-        reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
-        if (reg == NULL)
-                reg = of_get_flat_dt_prop(node, "reg", &l);
-        if (reg == NULL)
-                return 0;
-
-        endp = reg + (l / sizeof(cell_t));
-
-        DBG("memory scan node %s, reg size %ld, data: %x %x %x %x,\n",
-            uname, l, reg[0], reg[1], reg[2], reg[3]);
-
-        while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
-                u64 base, size;
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+#if defined(CONFIG_PPC64)
+        if (iommu_is_off) {
+                if (base >= 0x80000000ul)
+                        return;
+                if ((base + size) > 0x80000000ul)
+                        size = 0x80000000ul - base;
+        }
+#endif
 
-                base = dt_mem_next_cell(dt_root_addr_cells, &reg);
-                size = dt_mem_next_cell(dt_root_size_cells, &reg);
+        lmb_add(base, size);
 
-                if (size == 0)
-                        continue;
-                DBG(" - %llx ,  %llx\n", (unsigned long long)base,
-                    (unsigned long long)size);
-#ifdef CONFIG_PPC64
-                if (iommu_is_off) {
-                        if (base >= 0x80000000ul)
-                                continue;
-                        if ((base + size) > 0x80000000ul)
-                                size = 0x80000000ul - base;
-                }
-#endif
-                lmb_add(base, size);
+        memstart_addr = min((u64)memstart_addr, base);
+}
 
-                memstart_addr = min((u64)memstart_addr, base);
-        }
+u64 __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+        return lmb_alloc(size, align);
+}
 
-        return 0;
+#ifdef CONFIG_BLK_DEV_INITRD
+void __init early_init_dt_setup_initrd_arch(unsigned long start,
+                unsigned long end)
+{
+        initrd_start = (unsigned long)__va(start);
+        initrd_end = (unsigned long)__va(end);
+        initrd_below_start_ok = 1;
 }
+#endif
 
 static void __init early_reserve_mem(void)
 {
@@ -1186,7 +683,7 @@ void __init early_init_devtree(void *params)
         /* Scan memory nodes and rebuild LMBs */
         lmb_init();
         of_scan_flat_dt(early_init_dt_scan_root, NULL);
-        of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+        of_scan_flat_dt(early_init_dt_scan_memory_ppc, NULL);
 
         /* Save command line for /proc/cmdline and then parse parameters */
         strlcpy(boot_command_line, cmd_line, COMMAND_LINE_SIZE);
@@ -1234,25 +731,6 @@ void __init early_init_devtree(void *params)
         DBG(" <- early_init_devtree()\n");
 }
 
-
-/**
- * Indicates whether the root node has a given value in its
- * compatible property.
- */
-int machine_is_compatible(const char *compat)
-{
-        struct device_node *root;
-        int rc = 0;
-
-        root = of_find_node_by_path("/");
-        if (root) {
-                rc = of_device_is_compatible(root, compat);
-                of_node_put(root);
-        }
-        return rc;
-}
-EXPORT_SYMBOL(machine_is_compatible);
-
 /*******
  *
  * New implementation of the OF "find" APIs, return a refcounted
@@ -1265,27 +743,6 @@ EXPORT_SYMBOL(machine_is_compatible);
  *******/
 
 /**
- *      of_find_node_by_phandle - Find a node given a phandle
- *      @handle:        phandle of the node to find
- *
- *      Returns a node pointer with refcount incremented, use
- *      of_node_put() on it when done.
- */
-struct device_node *of_find_node_by_phandle(phandle handle)
-{
-        struct device_node *np;
-
-        read_lock(&devtree_lock);
-        for (np = allnodes; np != 0; np = np->allnext)
-                if (np->linux_phandle == handle)
-                        break;
-        of_node_get(np);
-        read_unlock(&devtree_lock);
-        return np;
-}
-EXPORT_SYMBOL(of_find_node_by_phandle);
-
-/**
  *      of_find_next_cache_node - Find a node's subsidiary cache
  *      @np:    node of type "cpu" or "cache"
  *
@@ -1316,138 +773,6 @@ struct device_node *of_find_next_cache_node(struct device_node *np)
         return NULL;
 }
 
-/**
- *      of_node_get - Increment refcount of a node
- *      @node:  Node to inc refcount, NULL is supported to
- *              simplify writing of callers
- *
- *      Returns node.
- */
-struct device_node *of_node_get(struct device_node *node)
-{
-        if (node)
-                kref_get(&node->kref);
-        return node;
-}
-EXPORT_SYMBOL(of_node_get);
-
-static inline struct device_node * kref_to_device_node(struct kref *kref)
-{
-        return container_of(kref, struct device_node, kref);
-}
-
-/**
- *      of_node_release - release a dynamically allocated node
- *      @kref:  kref element of the node to be released
- *
- *      In of_node_put() this function is passed to kref_put()
- *      as the destructor.
- */
-static void of_node_release(struct kref *kref)
-{
-        struct device_node *node = kref_to_device_node(kref);
-        struct property *prop = node->properties;
-
-        /* We should never be releasing nodes that haven't been detached. */
-        if (!of_node_check_flag(node, OF_DETACHED)) {
-                printk("WARNING: Bad of_node_put() on %s\n", node->full_name);
-                dump_stack();
-                kref_init(&node->kref);
-                return;
-        }
-
-        if (!of_node_check_flag(node, OF_DYNAMIC))
-                return;
-
-        while (prop) {
-                struct property *next = prop->next;
-                kfree(prop->name);
-                kfree(prop->value);
-                kfree(prop);
-                prop = next;
-
-                if (!prop) {
-                        prop = node->deadprops;
-                        node->deadprops = NULL;
-                }
-        }
-        kfree(node->full_name);
-        kfree(node->data);
-        kfree(node);
-}
-
-/**
- *      of_node_put - Decrement refcount of a node
- *      @node:  Node to dec refcount, NULL is supported to
- *              simplify writing of callers
- *
- */
-void of_node_put(struct device_node *node)
-{
-        if (node)
-                kref_put(&node->kref, of_node_release);
-}
-EXPORT_SYMBOL(of_node_put);
-
-/*
- * Plug a device node into the tree and global list.
- */
-void of_attach_node(struct device_node *np)
-{
-        unsigned long flags;
-
-        write_lock_irqsave(&devtree_lock, flags);
-        np->sibling = np->parent->child;
-        np->allnext = allnodes;
-        np->parent->child = np;
-        allnodes = np;
-        write_unlock_irqrestore(&devtree_lock, flags);
-}
-
-/*
- * "Unplug" a node from the device tree.  The caller must hold
- * a reference to the node.  The memory associated with the node
- * is not freed until its refcount goes to zero.
- */
-void of_detach_node(struct device_node *np)
-{
-        struct device_node *parent;
-        unsigned long flags;
-
-        write_lock_irqsave(&devtree_lock, flags);
-
-        parent = np->parent;
-        if (!parent)
-                goto out_unlock;
-
-        if (allnodes == np)
-                allnodes = np->allnext;
-        else {
-                struct device_node *prev;
-                for (prev = allnodes;
-                     prev->allnext != np;
-                     prev = prev->allnext)
-                        ;
-                prev->allnext = np->allnext;
-        }
-
-        if (parent->child == np)
-                parent->child = np->sibling;
-        else {
-                struct device_node *prevsib;
-                for (prevsib = np->parent->child;
-                     prevsib->sibling != np;
-                     prevsib = prevsib->sibling)
-                        ;
-                prevsib->sibling = np->sibling;
-        }
-
-        of_node_set_flag(np, OF_DETACHED);
-
-out_unlock:
-        write_unlock_irqrestore(&devtree_lock, flags);
-}
-
 #ifdef CONFIG_PPC_PSERIES
 /*
  * Fix up the uninitialized fields in a new device node:
@@ -1479,9 +804,9 @@ static int of_finish_dynamic_node(struct device_node *node)
         if (machine_is(powermac))
                 return -ENODEV;
 
-        /* fix up new node's linux_phandle field */
+        /* fix up new node's phandle field */
         if ((ibm_phandle = of_get_property(node, "ibm,phandle", NULL)))
-                node->linux_phandle = *ibm_phandle;
+                node->phandle = *ibm_phandle;
 
 out:
         of_node_put(parent);
@@ -1520,120 +845,6 @@ static int __init prom_reconfig_setup(void)
 __initcall(prom_reconfig_setup);
 #endif
 
-/*
- * Add a property to a node
- */
-int prom_add_property(struct device_node* np, struct property* prop)
-{
-        struct property **next;
-        unsigned long flags;
-
-        prop->next = NULL;      
-        write_lock_irqsave(&devtree_lock, flags);
-        next = &np->properties;
-        while (*next) {
-                if (strcmp(prop->name, (*next)->name) == 0) {
-                        /* duplicate ! don't insert it */
-                        write_unlock_irqrestore(&devtree_lock, flags);
-                        return -1;
-                }
-                next = &(*next)->next;
-        }
-        *next = prop;
-        write_unlock_irqrestore(&devtree_lock, flags);
-
-#ifdef CONFIG_PROC_DEVICETREE
-        /* try to add to proc as well if it was initialized */
-        if (np->pde)
-                proc_device_tree_add_prop(np->pde, prop);
-#endif /* CONFIG_PROC_DEVICETREE */
-
-        return 0;
-}
-
-/*
- * Remove a property from a node.  Note that we don't actually
- * remove it, since we have given out who-knows-how-many pointers
- * to the data using get-property.  Instead we just move the property
- * to the "dead properties" list, so it won't be found any more.
- */
-int prom_remove_property(struct device_node *np, struct property *prop)
-{
-        struct property **next;
-        unsigned long flags;
-        int found = 0;
-
-        write_lock_irqsave(&devtree_lock, flags);
-        next = &np->properties;
-        while (*next) {
-                if (*next == prop) {
-                        /* found the node */
-                        *next = prop->next;
-                        prop->next = np->deadprops;
-                        np->deadprops = prop;
-                        found = 1;
-                        break;
-                }
-                next = &(*next)->next;
-        }
-        write_unlock_irqrestore(&devtree_lock, flags);
-
-        if (!found)
-                return -ENODEV;
-
-#ifdef CONFIG_PROC_DEVICETREE
-        /* try to remove the proc node as well */
-        if (np->pde)
-                proc_device_tree_remove_prop(np->pde, prop);
-#endif /* CONFIG_PROC_DEVICETREE */
-
-        return 0;
-}
-
-/*
- * Update a property in a node.  Note that we don't actually
- * remove it, since we have given out who-knows-how-many pointers
- * to the data using get-property.  Instead we just move the property
- * to the "dead properties" list, and add the new property to the
- * property list
- */
-int prom_update_property(struct device_node *np,
-                         struct property *newprop,
-                         struct property *oldprop)
-{
-        struct property **next;
-        unsigned long flags;
-        int found = 0;
-
-        write_lock_irqsave(&devtree_lock, flags);
-        next = &np->properties;
-        while (*next) {
-                if (*next == oldprop) {
-                        /* found the node */
-                        newprop->next = oldprop->next;
-                        *next = newprop;
-                        oldprop->next = np->deadprops;
-                        np->deadprops = oldprop;
-                        found = 1;
-                        break;
-                }
-                next = &(*next)->next;
-        }
-        write_unlock_irqrestore(&devtree_lock, flags);
-
-        if (!found)
-                return -ENODEV;
-
-#ifdef CONFIG_PROC_DEVICETREE
-        /* try to add to proc as well if it was initialized */
-        if (np->pde)
-                proc_device_tree_update_prop(np->pde, newprop, oldprop);
-#endif /* CONFIG_PROC_DEVICETREE */
-
-        return 0;
-}
-
-
 /* Find the device node for a given logical cpu number, also returns the cpu
  * local thread number (index in ibm,interrupt-server#s) if relevant and
  * asked for (non NULL)
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index bafac2e41ae1..5f306c4946e5 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -654,6 +654,9 @@ static void __init early_cmdline_parse(void)
 #define OV5_CMO                 0x00
 #endif
 
+/* Option Vector 6: IBM PAPR hints */
+#define OV6_LINUX               0x02    /* Linux is our OS */
+
 /*
  * The architecture vector has an array of PVR mask/value pairs,
  * followed by # option vectors - 1, followed by the option vectors.
@@ -665,7 +668,7 @@ static unsigned char ibm_architecture_vec[] = {
         W(0xffffffff), W(0x0f000003),   /* all 2.06-compliant */
         W(0xffffffff), W(0x0f000002),   /* all 2.05-compliant */
         W(0xfffffffe), W(0x0f000001),   /* all 2.04-compliant and earlier */
-        5 - 1,                          /* 5 option vectors */
+        6 - 1,                          /* 6 option vectors */
 
         /* option vector 1: processor architectures supported */
         3 - 2,                          /* length */
@@ -697,12 +700,29 @@ static unsigned char ibm_architecture_vec[] = {
         0,                              /* don't halt */
 
         /* option vector 5: PAPR/OF options */
-        5 - 2,                          /* length */
+        13 - 2,                         /* length */
         0,                              /* don't ignore, don't halt */
         OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES | OV5_DRCONF_MEMORY |
         OV5_DONATE_DEDICATE_CPU | OV5_MSI,
         0,
         OV5_CMO,
+        0,
+        0,
+        0,
+        0,
+        /* WARNING: The offset of the "number of cores" field below
+         * must match by the macro below. Update the definition if
+         * the structure layout changes.
+         */
+#define IBM_ARCH_VEC_NRCORES_OFFSET     100
+        W(NR_CPUS),                     /* number of cores supported */
+
+        /* option vector 6: IBM PAPR hints */
+        4 - 2,                          /* length */
+        0,
+        0,
+        OV6_LINUX,
+
 };
 
 /* Old method - ELF header with PT_NOTE sections */
@@ -792,13 +812,70 @@ static struct fake_elf {
         }
 };
 
+static int __init prom_count_smt_threads(void)
+{
+        phandle node;
+        char type[64];
+        unsigned int plen;
+
+        /* Pick up th first CPU node we can find */
+        for (node = 0; prom_next_node(&node); ) {
+                type[0] = 0;
+                prom_getprop(node, "device_type", type, sizeof(type));
+
+                if (strcmp(type, RELOC("cpu")))
+                        continue;
+                /*
+                 * There is an entry for each smt thread, each entry being
+                 * 4 bytes long.  All cpus should have the same number of
+                 * smt threads, so return after finding the first.
+                 */
+                plen = prom_getproplen(node, "ibm,ppc-interrupt-server#s");
+                if (plen == PROM_ERROR)
+                        break;
+                plen >>= 2;
+                prom_debug("Found 0x%x smt threads per core\n", (unsigned long)plen);
+
+                /* Sanity check */
+                if (plen < 1 || plen > 64) {
+                        prom_printf("Threads per core 0x%x out of bounds, assuming 1\n",
+                                    (unsigned long)plen);
+                        return 1;
+                }
+                return plen;
+        }
+        prom_debug("No threads found, assuming 1 per core\n");
+
+        return 1;
+
+}
+
+
 static void __init prom_send_capabilities(void)
 {
         ihandle elfloader, root;
         prom_arg_t ret;
+        u32 *cores;
 
         root = call_prom("open", 1, 1, ADDR("/"));
         if (root != 0) {
+                /* We need to tell the FW about the number of cores we support.
+                 *
+                 * To do that, we count the number of threads on the first core
+                 * (we assume this is the same for all cores) and use it to
+                 * divide NR_CPUS.
+                 */
+                cores = (u32 *)PTRRELOC(&ibm_architecture_vec[IBM_ARCH_VEC_NRCORES_OFFSET]);
+                if (*cores != NR_CPUS) {
+                        prom_printf("WARNING ! "
+                                    "ibm_architecture_vec structure inconsistent: 0x%x !\n",
+                                    *cores);
+                } else {
+                        *cores = NR_CPUS / prom_count_smt_threads();
+                        prom_printf("Max number of cores passed to firmware: 0x%x\n",
+                                    (unsigned long)*cores);
+                }
+
                 /* try calling the ibm,client-architecture-support method */
                 prom_printf("Calling ibm,client-architecture-support...");
                 if (call_prom_ret("call-method", 3, 2, &ret,
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index ef149880c145..d9b05866615f 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -46,7 +46,7 @@
 /*
  * Set of msr bits that gdb can change on behalf of a process.
  */
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 #define MSR_DEBUGCHANGE 0
 #else
 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
@@ -703,7 +703,7 @@ void user_enable_single_step(struct task_struct *task)
         struct pt_regs *regs = task->thread.regs;
 
         if (regs != NULL) {
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
                 task->thread.dbcr0 &= ~DBCR0_BT;
                 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
                 regs->msr |= MSR_DE;
@@ -720,7 +720,7 @@ void user_enable_block_step(struct task_struct *task)
         struct pt_regs *regs = task->thread.regs;
 
         if (regs != NULL) {
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
                 task->thread.dbcr0 &= ~DBCR0_IC;
                 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
                 regs->msr |= MSR_DE;
@@ -737,17 +737,25 @@ void user_disable_single_step(struct task_struct *task)
         struct pt_regs *regs = task->thread.regs;
 
         if (regs != NULL) {
-#if defined(CONFIG_BOOKE)
-                /* If DAC don't clear DBCRO_IDM or MSR_DE */
-                if (task->thread.dabr)
-                        task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT);
-                else {
-                        task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+                /*
+                 * The logic to disable single stepping should be as
+                 * simple as turning off the Instruction Complete flag.
+                 * And, after doing so, if all debug flags are off, turn
+                 * off DBCR0(IDM) and MSR(DE) .... Torez
+                 */
+                task->thread.dbcr0 &= ~DBCR0_IC;
+                /*
+                 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
+                 */
+                if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
+                                        task->thread.dbcr1)) {
+                        /*
+                         * All debug events were off.....
+                         */
+                        task->thread.dbcr0 &= ~DBCR0_IDM;
                         regs->msr &= ~MSR_DE;
                 }
-#elif defined(CONFIG_40x)
-                task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
-                regs->msr &= ~MSR_DE;
 #else
                 regs->msr &= ~(MSR_SE | MSR_BE);
 #endif
@@ -769,8 +777,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
         if ((data & ~0x7UL) >= TASK_SIZE)
                 return -EIO;
 
-#ifndef CONFIG_BOOKE
-
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
         /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
          *  It was assumed, on previous implementations, that 3 bits were
          *  passed together with the data address, fitting the design of the
@@ -789,21 +796,22 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
 
         /* Move contents to the DABR register */
         task->thread.dabr = data;
-
-#endif
-#if defined(CONFIG_BOOKE)
-
+#else /* CONFIG_PPC_ADV_DEBUG_REGS */
         /* As described above, it was assumed 3 bits were passed with the data
          *  address, but we will assume only the mode bits will be passed
          *  as to not cause alignment restrictions for DAC-based processors.
          */
 
         /* DAC's hold the whole address without any mode flags */
-        task->thread.dabr = data & ~0x3UL;
-
-        if (task->thread.dabr == 0) {
-                task->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W | DBCR0_IDM);
-                task->thread.regs->msr &= ~MSR_DE;
+        task->thread.dac1 = data & ~0x3UL;
+
+        if (task->thread.dac1 == 0) {
+                dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
+                if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
+                                        task->thread.dbcr1)) {
+                        task->thread.regs->msr &= ~MSR_DE;
+                        task->thread.dbcr0 &= ~DBCR0_IDM;
+                }
                 return 0;
         }
 
@@ -814,17 +822,17 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
 
         /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
            register */
-        task->thread.dbcr0 = DBCR0_IDM;
+        task->thread.dbcr0 |= DBCR0_IDM;
 
         /* Check for write and read flags and set DBCR0
            accordingly */
+        dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
         if (data & 0x1UL)
-                task->thread.dbcr0 |= DBSR_DAC1R;
+                dbcr_dac(task) |= DBCR_DAC1R;
         if (data & 0x2UL)
-                task->thread.dbcr0 |= DBSR_DAC1W;
-
+                dbcr_dac(task) |= DBCR_DAC1W;
         task->thread.regs->msr |= MSR_DE;
-#endif
+#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
         return 0;
 }
 
@@ -839,6 +847,394 @@ void ptrace_disable(struct task_struct *child)
         user_disable_single_step(child);
 }
 
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+static long set_intruction_bp(struct task_struct *child,
+                              struct ppc_hw_breakpoint *bp_info)
+{
+        int slot;
+        int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
+        int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
+        int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
+        int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
+
+        if (dbcr_iac_range(child) & DBCR_IAC12MODE)
+                slot2_in_use = 1;
+        if (dbcr_iac_range(child) & DBCR_IAC34MODE)
+                slot4_in_use = 1;
+
+        if (bp_info->addr >= TASK_SIZE)
+                return -EIO;
+
+        if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
+
+                /* Make sure range is valid. */
+                if (bp_info->addr2 >= TASK_SIZE)
+                        return -EIO;
+
+                /* We need a pair of IAC regsisters */
+                if ((!slot1_in_use) && (!slot2_in_use)) {
+                        slot = 1;
+                        child->thread.iac1 = bp_info->addr;
+                        child->thread.iac2 = bp_info->addr2;
+                        child->thread.dbcr0 |= DBCR0_IAC1;
+                        if (bp_info->addr_mode ==
+                                        PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
+                                dbcr_iac_range(child) |= DBCR_IAC12X;
+                        else
+                                dbcr_iac_range(child) |= DBCR_IAC12I;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+                } else if ((!slot3_in_use) && (!slot4_in_use)) {
+                        slot = 3;
+                        child->thread.iac3 = bp_info->addr;
+                        child->thread.iac4 = bp_info->addr2;
+                        child->thread.dbcr0 |= DBCR0_IAC3;
+                        if (bp_info->addr_mode ==
+                                        PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
+                                dbcr_iac_range(child) |= DBCR_IAC34X;
+                        else
+                                dbcr_iac_range(child) |= DBCR_IAC34I;
+#endif
+                } else
+                        return -ENOSPC;
+        } else {
+                /* We only need one.  If possible leave a pair free in
+                 * case a range is needed later
+                 */
+                if (!slot1_in_use) {
+                        /*
+                         * Don't use iac1 if iac1-iac2 are free and either
+                         * iac3 or iac4 (but not both) are free
+                         */
+                        if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
+                                slot = 1;
+                                child->thread.iac1 = bp_info->addr;
+                                child->thread.dbcr0 |= DBCR0_IAC1;
+                                goto out;
+                        }
+                }
+                if (!slot2_in_use) {
+                        slot = 2;
+                        child->thread.iac2 = bp_info->addr;
+                        child->thread.dbcr0 |= DBCR0_IAC2;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+                } else if (!slot3_in_use) {
+                        slot = 3;
+                        child->thread.iac3 = bp_info->addr;
+                        child->thread.dbcr0 |= DBCR0_IAC3;
+                } else if (!slot4_in_use) {
+                        slot = 4;
+                        child->thread.iac4 = bp_info->addr;
+                        child->thread.dbcr0 |= DBCR0_IAC4;
+#endif
+                } else
+                        return -ENOSPC;
+        }
+out:
+        child->thread.dbcr0 |= DBCR0_IDM;
+        child->thread.regs->msr |= MSR_DE;
+
+        return slot;
+}
+
+static int del_instruction_bp(struct task_struct *child, int slot)
+{
+        switch (slot) {
+        case 1:
+                if (child->thread.iac1 == 0)
+                        return -ENOENT;
+
+                if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
+                        /* address range - clear slots 1 & 2 */
+                        child->thread.iac2 = 0;
+                        dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
+                }
+                child->thread.iac1 = 0;
+                child->thread.dbcr0 &= ~DBCR0_IAC1;
+                break;
+        case 2:
+                if (child->thread.iac2 == 0)
+                        return -ENOENT;
+
+                if (dbcr_iac_range(child) & DBCR_IAC12MODE)
+                        /* used in a range */
+                        return -EINVAL;
+                child->thread.iac2 = 0;
+                child->thread.dbcr0 &= ~DBCR0_IAC2;
+                break;
+#if CONFIG_PPC_ADV_DEBUG_IACS > 2
+        case 3:
+                if (child->thread.iac3 == 0)
+                        return -ENOENT;
+
+                if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
+                        /* address range - clear slots 3 & 4 */
+                        child->thread.iac4 = 0;
+                        dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
+                }
+                child->thread.iac3 = 0;
+                child->thread.dbcr0 &= ~DBCR0_IAC3;
+                break;
+        case 4:
+                if (child->thread.iac4 == 0)
+                        return -ENOENT;
+
+                if (dbcr_iac_range(child) & DBCR_IAC34MODE)
+                        /* Used in a range */
+                        return -EINVAL;
+                child->thread.iac4 = 0;
+                child->thread.dbcr0 &= ~DBCR0_IAC4;
+                break;
+#endif
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
+{
+        int byte_enable =
+                (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
+                & 0xf;
+        int condition_mode =
+                bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
+        int slot;
+
+        if (byte_enable && (condition_mode == 0))
+                return -EINVAL;
+
+        if (bp_info->addr >= TASK_SIZE)
+                return -EIO;
+
+        if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
+                slot = 1;
+                if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+                        dbcr_dac(child) |= DBCR_DAC1R;
+                if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+                        dbcr_dac(child) |= DBCR_DAC1W;
+                child->thread.dac1 = (unsigned long)bp_info->addr;
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+                if (byte_enable) {
+                        child->thread.dvc1 =
+                                (unsigned long)bp_info->condition_value;
+                        child->thread.dbcr2 |=
+                                ((byte_enable << DBCR2_DVC1BE_SHIFT) |
+                                 (condition_mode << DBCR2_DVC1M_SHIFT));
+                }
+#endif
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+        } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
+                /* Both dac1 and dac2 are part of a range */
+                return -ENOSPC;
+#endif
+        } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
+                slot = 2;
+                if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+                        dbcr_dac(child) |= DBCR_DAC2R;
+                if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+                        dbcr_dac(child) |= DBCR_DAC2W;
+                child->thread.dac2 = (unsigned long)bp_info->addr;
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+                if (byte_enable) {
+                        child->thread.dvc2 =
+                                (unsigned long)bp_info->condition_value;
+                        child->thread.dbcr2 |=
+                                ((byte_enable << DBCR2_DVC2BE_SHIFT) |
+                                 (condition_mode << DBCR2_DVC2M_SHIFT));
+                }
+#endif
+        } else
+                return -ENOSPC;
+        child->thread.dbcr0 |= DBCR0_IDM;
+        child->thread.regs->msr |= MSR_DE;
+
+        return slot + 4;
+}
+
+static int del_dac(struct task_struct *child, int slot)
+{
+        if (slot == 1) {
+                if (child->thread.dac1 == 0)
+                        return -ENOENT;
+
+                child->thread.dac1 = 0;
+                dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+                if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
+                        child->thread.dac2 = 0;
+                        child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
+                }
+                child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
+#endif
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+                child->thread.dvc1 = 0;
+#endif
+        } else if (slot == 2) {
+                if (child->thread.dac1 == 0)
+                        return -ENOENT;
+
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+                if (child->thread.dbcr2 & DBCR2_DAC12MODE)
+                        /* Part of a range */
+                        return -EINVAL;
+                child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
+#endif
+#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
+                child->thread.dvc2 = 0;
+#endif
+                child->thread.dac2 = 0;
+                dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
+        } else
+                return -EINVAL;
+
+        return 0;
+}
+#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
+
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+static int set_dac_range(struct task_struct *child,
+                         struct ppc_hw_breakpoint *bp_info)
+{
+        int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
+
+        /* We don't allow range watchpoints to be used with DVC */
+        if (bp_info->condition_mode)
+                return -EINVAL;
+
+        /*
+         * Best effort to verify the address range.  The user/supervisor bits
+         * prevent trapping in kernel space, but let's fail on an obvious bad
+         * range.  The simple test on the mask is not fool-proof, and any
+         * exclusive range will spill over into kernel space.
+         */
+        if (bp_info->addr >= TASK_SIZE)
+                return -EIO;
+        if (mode == PPC_BREAKPOINT_MODE_MASK) {
+                /*
+                 * dac2 is a bitmask.  Don't allow a mask that makes a
+                 * kernel space address from a valid dac1 value
+                 */
+                if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
+                        return -EIO;
+        } else {
+                /*
+                 * For range breakpoints, addr2 must also be a valid address
+                 */
+                if (bp_info->addr2 >= TASK_SIZE)
+                        return -EIO;
+        }
+
+        if (child->thread.dbcr0 &
+            (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
+                return -ENOSPC;
+
+        if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
+                child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
+        if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
+                child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
+        child->thread.dac1 = bp_info->addr;
+        child->thread.dac2 = bp_info->addr2;
+        if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
+                child->thread.dbcr2  |= DBCR2_DAC12M;
+        else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
+                child->thread.dbcr2  |= DBCR2_DAC12MX;
+        else    /* PPC_BREAKPOINT_MODE_MASK */
+                child->thread.dbcr2  |= DBCR2_DAC12MM;
+        child->thread.regs->msr |= MSR_DE;
+
+        return 5;
+}
+#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
+
+static long ppc_set_hwdebug(struct task_struct *child,
+                     struct ppc_hw_breakpoint *bp_info)
+{
+        if (bp_info->version != 1)
+                return -ENOTSUPP;
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+        /*
+         * Check for invalid flags and combinations
+         */
+        if ((bp_info->trigger_type == 0) ||
+            (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
+                                       PPC_BREAKPOINT_TRIGGER_RW)) ||
+            (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
+            (bp_info->condition_mode &
+             ~(PPC_BREAKPOINT_CONDITION_MODE |
+               PPC_BREAKPOINT_CONDITION_BE_ALL)))
+                return -EINVAL;
+#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
+        if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
+                return -EINVAL;
+#endif
+
+        if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
+                if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
+                    (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
+                        return -EINVAL;
+                return set_intruction_bp(child, bp_info);
+        }
+        if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
+                return set_dac(child, bp_info);
+
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+        return set_dac_range(child, bp_info);
+#else
+        return -EINVAL;
+#endif
+#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
+        /*
+         * We only support one data breakpoint
+         */
+        if (((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0) ||
+            ((bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0) ||
+            (bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_WRITE) ||
+            (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) ||
+            (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
+                return -EINVAL;
+
+        if (child->thread.dabr)
+                return -ENOSPC;
+
+        if ((unsigned long)bp_info->addr >= TASK_SIZE)
+                return -EIO;
+
+        child->thread.dabr = (unsigned long)bp_info->addr;
+
+        return 1;
+#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
+}
+
+static long ppc_del_hwdebug(struct task_struct *child, long addr, long data)
+{
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+        int rc;
+
+        if (data <= 4)
+                rc = del_instruction_bp(child, (int)data);
+        else
+                rc = del_dac(child, (int)data - 4);
+
+        if (!rc) {
+                if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
+                                        child->thread.dbcr1)) {
+                        child->thread.dbcr0 &= ~DBCR0_IDM;
+                        child->thread.regs->msr &= ~MSR_DE;
+                }
+        }
+        return rc;
+#else
+        if (data != 1)
+                return -EINVAL;
+        if (child->thread.dabr == 0)
+                return -ENOENT;
+
+        child->thread.dabr = 0;
+
+        return 0;
+#endif
+}
+
 /*
  * Here are the old "legacy" powerpc specific getregs/setregs ptrace calls,
  * we mark them as obsolete now, they will be removed in a future version
@@ -932,13 +1328,77 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 break;
         }
 
+        case PPC_PTRACE_GETHWDBGINFO: {
+                struct ppc_debug_info dbginfo;
+
+                dbginfo.version = 1;
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+                dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
+                dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
+                dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
+                dbginfo.data_bp_alignment = 4;
+                dbginfo.sizeof_condition = 4;
+                dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
+                                   PPC_DEBUG_FEATURE_INSN_BP_MASK;
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+                dbginfo.features |=
+                                   PPC_DEBUG_FEATURE_DATA_BP_RANGE |
+                                   PPC_DEBUG_FEATURE_DATA_BP_MASK;
+#endif
+#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
+                dbginfo.num_instruction_bps = 0;
+                dbginfo.num_data_bps = 1;
+                dbginfo.num_condition_regs = 0;
+#ifdef CONFIG_PPC64
+                dbginfo.data_bp_alignment = 8;
+#else
+                dbginfo.data_bp_alignment = 4;
+#endif
+                dbginfo.sizeof_condition = 0;
+                dbginfo.features = 0;
+#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
+
+                if (!access_ok(VERIFY_WRITE, data,
+                               sizeof(struct ppc_debug_info)))
+                        return -EFAULT;
+                ret = __copy_to_user((struct ppc_debug_info __user *)data,
+                                     &dbginfo, sizeof(struct ppc_debug_info)) ?
+                      -EFAULT : 0;
+                break;
+        }
+
+        case PPC_PTRACE_SETHWDEBUG: {
+                struct ppc_hw_breakpoint bp_info;
+
+                if (!access_ok(VERIFY_READ, data,
+                               sizeof(struct ppc_hw_breakpoint)))
+                        return -EFAULT;
+                ret = __copy_from_user(&bp_info,
+                                       (struct ppc_hw_breakpoint __user *)data,
+                                       sizeof(struct ppc_hw_breakpoint)) ?
+                      -EFAULT : 0;
+                if (!ret)
+                        ret = ppc_set_hwdebug(child, &bp_info);
+                break;
+        }
+
+        case PPC_PTRACE_DELHWDEBUG: {
+                ret = ppc_del_hwdebug(child, addr, data);
+                break;
+        }
+
         case PTRACE_GET_DEBUGREG: {
                 ret = -EINVAL;
                 /* We only support one DABR and no IABRS at the moment */
                 if (addr > 0)
                         break;
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+                ret = put_user(child->thread.dac1,
+                               (unsigned long __user *)data);
+#else
                 ret = put_user(child->thread.dabr,
                                (unsigned long __user *)data);
+#endif
                 break;
         }
 
diff --git a/arch/powerpc/kernel/signal.c b/arch/powerpc/kernel/signal.c
index 00b5078da9a3..a0afb555a7c9 100644
--- a/arch/powerpc/kernel/signal.c
+++ b/arch/powerpc/kernel/signal.c
@@ -140,17 +140,15 @@ static int do_signal_pending(sigset_t *oldset, struct pt_regs *regs)
                 return 0;               /* no signals delivered */
         }
 
+#ifndef CONFIG_PPC_ADV_DEBUG_REGS
         /*
          * Reenable the DABR before delivering the signal to
          * user space. The DABR will have been cleared if it
          * triggered inside the kernel.
          */
-        if (current->thread.dabr) {
+        if (current->thread.dabr)
                 set_dabr(current->thread.dabr);
-#if defined(CONFIG_BOOKE)
-                mtspr(SPRN_DBCR0, current->thread.dbcr0);
 #endif
-        }
 
         if (is32) {
                 if (ka.sa.sa_flags & SA_SIGINFO)
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index d670429a1608..266610119f66 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -1078,7 +1078,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
         int i;
         unsigned char tmp;
         unsigned long new_msr = regs->msr;
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
         unsigned long new_dbcr0 = current->thread.dbcr0;
 #endif
 
@@ -1087,13 +1087,17 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
                         return -EFAULT;
                 switch (op.dbg_type) {
                 case SIG_DBG_SINGLE_STEPPING:
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
                         if (op.dbg_value) {
                                 new_msr |= MSR_DE;
                                 new_dbcr0 |= (DBCR0_IDM | DBCR0_IC);
                         } else {
-                                new_msr &= ~MSR_DE;
-                                new_dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
+                                new_dbcr0 &= ~DBCR0_IC;
+                                if (!DBCR_ACTIVE_EVENTS(new_dbcr0,
+                                                current->thread.dbcr1)) {
+                                        new_msr &= ~MSR_DE;
+                                        new_dbcr0 &= ~DBCR0_IDM;
+                                }
                         }
 #else
                         if (op.dbg_value)
@@ -1103,7 +1107,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
 #endif
                         break;
                 case SIG_DBG_BRANCH_TRACING:
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
                         return -EINVAL;
 #else
                         if (op.dbg_value)
@@ -1124,7 +1128,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
            failure is a problem, anyway, and it's very unlikely unless
            the user is really doing something wrong. */
         regs->msr = new_msr;
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
         current->thread.dbcr0 = new_dbcr0;
 #endif
 
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 6c6093d67f30..1b16b9a3e49a 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -265,8 +265,8 @@ void account_system_vtime(struct task_struct *tsk)
                 account_system_time(tsk, 0, delta, deltascaled);
         else
                 account_idle_time(delta);
-        per_cpu(cputime_last_delta, smp_processor_id()) = delta;
-        per_cpu(cputime_scaled_last_delta, smp_processor_id()) = deltascaled;
+        __get_cpu_var(cputime_last_delta) = delta;
+        __get_cpu_var(cputime_scaled_last_delta) = deltascaled;
         local_irq_restore(flags);
 }
 EXPORT_SYMBOL_GPL(account_system_vtime);
@@ -575,6 +575,8 @@ void timer_interrupt(struct pt_regs * regs)
 
         trace_timer_interrupt_entry(regs);
 
+        __get_cpu_var(irq_stat).timer_irqs++;
+
         /* Ensure a positive value is written to the decrementer, or else
          * some CPUs will continuue to take decrementer exceptions */
         set_dec(DECREMENTER_MAX);
@@ -935,8 +937,8 @@ static void register_decrementer_clockevent(int cpu)
         *dec = decrementer_clockevent;
         dec->cpumask = cpumask_of(cpu);
 
-        printk(KERN_DEBUG "clockevent: %s mult[%x] shift[%d] cpu[%d]\n",
-               dec->name, dec->mult, dec->shift, cpu);
+        printk_once(KERN_DEBUG "clockevent: %s mult[%x] shift[%d] cpu[%d]\n",
+                    dec->name, dec->mult, dec->shift, cpu);
 
         clockevents_register_device(dec);
 }
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index d069ff8a7e03..696626a2e835 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -60,13 +60,13 @@
 #endif
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
-int (*__debugger)(struct pt_regs *regs);
-int (*__debugger_ipi)(struct pt_regs *regs);
-int (*__debugger_bpt)(struct pt_regs *regs);
-int (*__debugger_sstep)(struct pt_regs *regs);
-int (*__debugger_iabr_match)(struct pt_regs *regs);
-int (*__debugger_dabr_match)(struct pt_regs *regs);
-int (*__debugger_fault_handler)(struct pt_regs *regs);
+int (*__debugger)(struct pt_regs *regs) __read_mostly;
+int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
+int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
+int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
+int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
+int (*__debugger_dabr_match)(struct pt_regs *regs) __read_mostly;
+int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
 
 EXPORT_SYMBOL(__debugger);
 EXPORT_SYMBOL(__debugger_ipi);
@@ -102,11 +102,11 @@ static inline void pmac_backlight_unblank(void) { }
 int die(const char *str, struct pt_regs *regs, long err)
 {
         static struct {
-                spinlock_t lock;
+                raw_spinlock_t lock;
                 u32 lock_owner;
                 int lock_owner_depth;
         } die = {
-                .lock =                 __SPIN_LOCK_UNLOCKED(die.lock),
+                .lock =                 __RAW_SPIN_LOCK_UNLOCKED(die.lock),
                 .lock_owner =           -1,
                 .lock_owner_depth =     0
         };
@@ -120,7 +120,7 @@ int die(const char *str, struct pt_regs *regs, long err)
 
         if (die.lock_owner != raw_smp_processor_id()) {
                 console_verbose();
-                spin_lock_irqsave(&die.lock, flags);
+                raw_spin_lock_irqsave(&die.lock, flags);
                 die.lock_owner = smp_processor_id();
                 die.lock_owner_depth = 0;
                 bust_spinlocks(1);
@@ -146,6 +146,11 @@ int die(const char *str, struct pt_regs *regs, long err)
 #endif
                 printk("%s\n", ppc_md.name ? ppc_md.name : "");
 
+                sysfs_printk_last_file();
+                if (notify_die(DIE_OOPS, str, regs, err, 255,
+                               SIGSEGV) == NOTIFY_STOP)
+                        return 1;
+
                 print_modules();
                 show_regs(regs);
         } else {
@@ -155,7 +160,7 @@ int die(const char *str, struct pt_regs *regs, long err)
         bust_spinlocks(0);
         die.lock_owner = -1;
         add_taint(TAINT_DIE);
-        spin_unlock_irqrestore(&die.lock, flags);
+        raw_spin_unlock_irqrestore(&die.lock, flags);
 
         if (kexec_should_crash(current) ||
                 kexec_sr_activated(smp_processor_id()))
@@ -294,7 +299,7 @@ static inline int check_io_access(struct pt_regs *regs)
         return 0;
 }
 
-#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 /* On 4xx, the reason for the machine check or program exception
    is in the ESR. */
 #define get_reason(regs)        ((regs)->dsisr)
@@ -478,6 +483,8 @@ void machine_check_exception(struct pt_regs *regs)
 {
         int recover = 0;
 
+        __get_cpu_var(irq_stat).mce_exceptions++;
+
         /* See if any machine dependent calls. In theory, we would want
          * to call the CPU first, and call the ppc_md. one if the CPU
          * one returns a positive number. However there is existing code
@@ -960,6 +967,8 @@ void vsx_unavailable_exception(struct pt_regs *regs)
 
 void performance_monitor_exception(struct pt_regs *regs)
 {
+        __get_cpu_var(irq_stat).pmu_irqs++;
+
         perf_irq(regs);
 }
 
@@ -1024,10 +1033,69 @@ void SoftwareEmulation(struct pt_regs *regs)
 }
 #endif /* CONFIG_8xx */
 
-#if defined(CONFIG_40x) || defined(CONFIG_BOOKE)
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
+{
+        int changed = 0;
+        /*
+         * Determine the cause of the debug event, clear the
+         * event flags and send a trap to the handler. Torez
+         */
+        if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
+                dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
+#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
+                current->thread.dbcr2 &= ~DBCR2_DAC12MODE;
+#endif
+                do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
+                             5);
+                changed |= 0x01;
+        }  else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
+                dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
+                do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
+                             6);
+                changed |= 0x01;
+        }  else if (debug_status & DBSR_IAC1) {
+                current->thread.dbcr0 &= ~DBCR0_IAC1;
+                dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
+                do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
+                             1);
+                changed |= 0x01;
+        }  else if (debug_status & DBSR_IAC2) {
+                current->thread.dbcr0 &= ~DBCR0_IAC2;
+                do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
+                             2);
+                changed |= 0x01;
+        }  else if (debug_status & DBSR_IAC3) {
+                current->thread.dbcr0 &= ~DBCR0_IAC3;
+                dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
+                do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
+                             3);
+                changed |= 0x01;
+        }  else if (debug_status & DBSR_IAC4) {
+                current->thread.dbcr0 &= ~DBCR0_IAC4;
+                do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
+                             4);
+                changed |= 0x01;
+        }
+        /*
+         * At the point this routine was called, the MSR(DE) was turned off.
+         * Check all other debug flags and see if that bit needs to be turned
+         * back on or not.
+         */
+        if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1))
+                regs->msr |= MSR_DE;
+        else
+                /* Make sure the IDM flag is off */
+                current->thread.dbcr0 &= ~DBCR0_IDM;
+
+        if (changed & 0x01)
+                mtspr(SPRN_DBCR0, current->thread.dbcr0);
+}
 
 void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
 {
+        current->thread.dbsr = debug_status;
+
         /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
          * on server, it stops on the target of the branch. In order to simulate
          * the server behaviour, we thus restart right away with a single step
@@ -1071,29 +1139,23 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
                 if (debugger_sstep(regs))
                         return;
 
-                if (user_mode(regs))
-                        current->thread.dbcr0 &= ~(DBCR0_IC);
-
-                _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
-        } else if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
-                regs->msr &= ~MSR_DE;
-
                 if (user_mode(regs)) {
-                        current->thread.dbcr0 &= ~(DBSR_DAC1R | DBSR_DAC1W |
-                                                                DBCR0_IDM);
-                } else {
-                        /* Disable DAC interupts */
-                        mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~(DBSR_DAC1R |
-                                                DBSR_DAC1W | DBCR0_IDM));
-
-                        /* Clear the DAC event */
-                        mtspr(SPRN_DBSR, (DBSR_DAC1R | DBSR_DAC1W));
+                        current->thread.dbcr0 &= ~DBCR0_IC;
+#ifdef CONFIG_PPC_ADV_DEBUG_REGS
+                        if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0,
+                                               current->thread.dbcr1))
+                                regs->msr |= MSR_DE;
+                        else
+                                /* Make sure the IDM bit is off */
+                                current->thread.dbcr0 &= ~DBCR0_IDM;
+#endif
                 }
-                /* Setup and send the trap to the handler */
-                do_dabr(regs, mfspr(SPRN_DAC1), debug_status);
-        }
+
+                _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
+        } else
+                handle_debug(regs, debug_status);
 }
-#endif /* CONFIG_4xx || CONFIG_BOOKE */
+#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
 
 #if !defined(CONFIG_TAU_INT)
 void TAUException(struct pt_regs *regs)
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index e68beac0a171..4d4eeb900486 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -43,62 +43,62 @@ END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
         ld      r7,16(r4)
         ldu     r8,24(r4)
 1:      std     r5,8(r3)
-        ld      r9,8(r4)
         std     r6,16(r3)
+        ld      r9,8(r4)
         ld      r10,16(r4)
         std     r7,24(r3)
-        ld      r11,24(r4)
         std     r8,32(r3)
+        ld      r11,24(r4)
         ld      r12,32(r4)
         std     r9,40(r3)
-        ld      r5,40(r4)
         std     r10,48(r3)
+        ld      r5,40(r4)
         ld      r6,48(r4)
         std     r11,56(r3)
-        ld      r7,56(r4)
         std     r12,64(r3)
+        ld      r7,56(r4)
         ld      r8,64(r4)
         std     r5,72(r3)
-        ld      r9,72(r4)
         std     r6,80(r3)
+        ld      r9,72(r4)
         ld      r10,80(r4)
         std     r7,88(r3)
-        ld      r11,88(r4)
         std     r8,96(r3)
+        ld      r11,88(r4)
         ld      r12,96(r4)
         std     r9,104(r3)
-        ld      r5,104(r4)
         std     r10,112(r3)
+        ld      r5,104(r4)
         ld      r6,112(r4)
         std     r11,120(r3)
-        ld      r7,120(r4)
         stdu    r12,128(r3)
+        ld      r7,120(r4)
         ldu     r8,128(r4)
         bdnz    1b
 
         std     r5,8(r3)
-        ld      r9,8(r4)
         std     r6,16(r3)
+        ld      r9,8(r4)
         ld      r10,16(r4)
         std     r7,24(r3)
-        ld      r11,24(r4)
         std     r8,32(r3)
+        ld      r11,24(r4)
         ld      r12,32(r4)
         std     r9,40(r3)
-        ld      r5,40(r4)
         std     r10,48(r3)
+        ld      r5,40(r4)
         ld      r6,48(r4)
         std     r11,56(r3)
-        ld      r7,56(r4)
         std     r12,64(r3)
+        ld      r7,56(r4)
         ld      r8,64(r4)
         std     r5,72(r3)
-        ld      r9,72(r4)
         std     r6,80(r3)
+        ld      r9,72(r4)
         ld      r10,80(r4)
         std     r7,88(r3)
-        ld      r11,88(r4)
         std     r8,96(r3)
+        ld      r11,88(r4)
         ld      r12,96(r4)
         std     r9,104(r3)
         std     r10,112(r3)
diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S
index 693b14a778fa..578b625d6a3c 100644
--- a/arch/powerpc/lib/copyuser_64.S
+++ b/arch/powerpc/lib/copyuser_64.S
@@ -44,37 +44,55 @@ BEGIN_FTR_SECTION
         andi.   r0,r4,7
         bne     .Lsrc_unaligned
 END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
-        srdi    r7,r5,4
-20:     ld      r9,0(r4)
-        addi    r4,r4,-8
-        mtctr   r7
-        andi.   r5,r5,7
-        bf      cr7*4+0,22f
-        addi    r3,r3,8
-        addi    r4,r4,8
-        mr      r8,r9
-        blt     cr1,72f
-21:     ld      r9,8(r4)
-70:     std     r8,8(r3)
-22:     ldu     r8,16(r4)
-71:     stdu    r9,16(r3)
+        blt     cr1,.Ldo_tail           /* if < 16 bytes to copy */
+        srdi    r0,r5,5
+        cmpdi   cr1,r0,0
+20:     ld      r7,0(r4)
+220:    ld      r6,8(r4)
+        addi    r4,r4,16
+        mtctr   r0
+        andi.   r0,r5,0x10
+        beq     22f
+        addi    r3,r3,16
+        addi    r4,r4,-16
+        mr      r9,r7
+        mr      r8,r6
+        beq     cr1,72f
+21:     ld      r7,16(r4)
+221:    ld      r6,24(r4)
+        addi    r4,r4,32
+70:     std     r9,0(r3)
+270:    std     r8,8(r3)
+22:     ld      r9,0(r4)
+222:    ld      r8,8(r4)
+71:     std     r7,16(r3)
+271:    std     r6,24(r3)
+        addi    r3,r3,32
         bdnz    21b
-72:     std     r8,8(r3)
+72:     std     r9,0(r3)
+272:    std     r8,8(r3)
+        andi.   r5,r5,0xf
         beq+    3f
-        addi    r3,r3,16
+        addi    r4,r4,16
 .Ldo_tail:
-        bf      cr7*4+1,1f
-23:     lwz     r9,8(r4)
+        addi    r3,r3,16
+        bf      cr7*4+0,246f
+244:    ld      r9,0(r4)
+        addi    r4,r4,8
+245:    std     r9,0(r3)
+        addi    r3,r3,8
+246:    bf      cr7*4+1,1f
+23:     lwz     r9,0(r4)
         addi    r4,r4,4
 73:     stw     r9,0(r3)
         addi    r3,r3,4
 1:      bf      cr7*4+2,2f
-44:     lhz     r9,8(r4)
+44:     lhz     r9,0(r4)
         addi    r4,r4,2
 74:     sth     r9,0(r3)
         addi    r3,r3,2
 2:      bf      cr7*4+3,3f
-45:     lbz     r9,8(r4)
+45:     lbz     r9,0(r4)
 75:     stb     r9,0(r3)
 3:      li      r3,0
         blr
@@ -220,7 +238,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 131:
         addi    r3,r3,8
 120:
+320:
 122:
+322:
 124:
 125:
 126:
@@ -229,9 +249,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 129:
 133:
         addi    r3,r3,8
-121:
 132:
         addi    r3,r3,8
+121:
+321:
+344:
 134:
 135:
 138:
@@ -303,18 +325,22 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
 183:
         add     r3,r3,r7
         b       1f
+371:
 180:
         addi    r3,r3,8
 171:
 177:
         addi    r3,r3,8
-170:
-172:
+370:
+372:
 176:
 178:
         addi    r3,r3,4
 185:
         addi    r3,r3,4
+170:
+172:
+345:
 173:
 174:
 175:
@@ -341,11 +367,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
         .section __ex_table,"a"
         .align  3
         .llong  20b,120b
+        .llong  220b,320b
         .llong  21b,121b
+        .llong  221b,321b
         .llong  70b,170b
+        .llong  270b,370b
         .llong  22b,122b
+        .llong  222b,322b
         .llong  71b,171b
+        .llong  271b,371b
         .llong  72b,172b
+        .llong  272b,372b
+        .llong  244b,344b
+        .llong  245b,345b
         .llong  23b,123b
         .llong  73b,173b
         .llong  44b,144b
diff --git a/arch/powerpc/lib/feature-fixups.c b/arch/powerpc/lib/feature-fixups.c
index 7e8865bcd683..e640175b65ae 100644
--- a/arch/powerpc/lib/feature-fixups.c
+++ b/arch/powerpc/lib/feature-fixups.c
@@ -112,7 +112,8 @@ void do_feature_fixups(unsigned long value, void *fixup_start, void *fixup_end)
 
 void do_lwsync_fixups(unsigned long value, void *fixup_start, void *fixup_end)
 {
-        unsigned int *start, *end, *dest;
+        long *start, *end;
+        unsigned int *dest;
 
         if (!(value & CPU_FTR_LWSYNC))
                 return ;
diff --git a/arch/powerpc/mm/40x_mmu.c b/arch/powerpc/mm/40x_mmu.c
index 08dfa8e6d86f..65abfcfaaa9e 100644
--- a/arch/powerpc/mm/40x_mmu.c
+++ b/arch/powerpc/mm/40x_mmu.c
@@ -84,8 +84,8 @@ void __init MMU_init_hw(void)
          * vectors and the kernel live in real-mode.
          */
 
-        mtspr(SPRN_DCCR, 0xF0000000);   /* 512 MB of data space at 0x0. */
-        mtspr(SPRN_ICCR, 0xF0000000);   /* 512 MB of instr. space at 0x0. */
+        mtspr(SPRN_DCCR, 0xFFFF0000);   /* 2GByte of data space at 0x0. */
+        mtspr(SPRN_ICCR, 0xFFFF0000);   /* 2GByte of instr. space at 0x0. */
 }
 
 #define LARGE_PAGE_SIZE_16M     (1<<24)
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
index 056d23a1b105..784a400e0781 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
@@ -37,7 +37,7 @@
 
 #define HPTE_LOCK_BIT 3
 
-static DEFINE_SPINLOCK(native_tlbie_lock);
+static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
 
 static inline void __tlbie(unsigned long va, int psize, int ssize)
 {
@@ -104,7 +104,7 @@ static inline void tlbie(unsigned long va, int psize, int ssize, int local)
         if (use_local)
                 use_local = mmu_psize_defs[psize].tlbiel;
         if (lock_tlbie && !use_local)
-                spin_lock(&native_tlbie_lock);
+                raw_spin_lock(&native_tlbie_lock);
         asm volatile("ptesync": : :"memory");
         if (use_local) {
                 __tlbiel(va, psize, ssize);
@@ -114,7 +114,7 @@ static inline void tlbie(unsigned long va, int psize, int ssize, int local)
                 asm volatile("eieio; tlbsync; ptesync": : :"memory");
         }
         if (lock_tlbie && !use_local)
-                spin_unlock(&native_tlbie_lock);
+                raw_spin_unlock(&native_tlbie_lock);
 }
 
 static inline void native_lock_hpte(struct hash_pte *hptep)
@@ -122,7 +122,7 @@ static inline void native_lock_hpte(struct hash_pte *hptep)
         unsigned long *word = &hptep->v;
 
         while (1) {
-                if (!test_and_set_bit(HPTE_LOCK_BIT, word))
+                if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
                         break;
                 while(test_bit(HPTE_LOCK_BIT, word))
                         cpu_relax();
@@ -133,8 +133,7 @@ static inline void native_unlock_hpte(struct hash_pte *hptep)
 {
         unsigned long *word = &hptep->v;
 
-        asm volatile("lwsync":::"memory");
-        clear_bit(HPTE_LOCK_BIT, word);
+        clear_bit_unlock(HPTE_LOCK_BIT, word);
 }
 
 static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
@@ -434,7 +433,7 @@ static void native_hpte_clear(void)
         /* we take the tlbie lock and hold it.  Some hardware will
          * deadlock if we try to tlbie from two processors at once.
          */
-        spin_lock(&native_tlbie_lock);
+        raw_spin_lock(&native_tlbie_lock);
 
         slots = pteg_count * HPTES_PER_GROUP;
 
@@ -458,7 +457,7 @@ static void native_hpte_clear(void)
         }
 
         asm volatile("eieio; tlbsync; ptesync":::"memory");
-        spin_unlock(&native_tlbie_lock);
+        raw_spin_unlock(&native_tlbie_lock);
         local_irq_restore(flags);
 }
 
@@ -521,7 +520,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                 int lock_tlbie = !cpu_has_feature(CPU_FTR_LOCKLESS_TLBIE);
 
                 if (lock_tlbie)
-                        spin_lock(&native_tlbie_lock);
+                        raw_spin_lock(&native_tlbie_lock);
 
                 asm volatile("ptesync":::"memory");
                 for (i = 0; i < number; i++) {
@@ -536,7 +535,7 @@ static void native_flush_hash_range(unsigned long number, int local)
                 asm volatile("eieio; tlbsync; ptesync":::"memory");
 
                 if (lock_tlbie)
-                        spin_unlock(&native_tlbie_lock);
+                        raw_spin_unlock(&native_tlbie_lock);
         }
 
         local_irq_restore(flags);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index b9b152558f9c..311224cdb7ad 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -494,13 +494,13 @@ EXPORT_SYMBOL(flush_icache_user_range);
  * This must always be called with the pte lock held.
  */
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
-                      pte_t pte)
+                      pte_t *ptep)
 {
 #ifdef CONFIG_PPC_STD_MMU
         unsigned long access = 0, trap;
 
         /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
-        if (!pte_young(pte) || address >= TASK_SIZE)
+        if (!pte_young(*ptep) || address >= TASK_SIZE)
                 return;
 
         /* We try to figure out if we are coming from an instruction
diff --git a/arch/powerpc/mm/mmu_context_hash64.c b/arch/powerpc/mm/mmu_context_hash64.c
index b910d37aea1a..51622daae09d 100644
--- a/arch/powerpc/mm/mmu_context_hash64.c
+++ b/arch/powerpc/mm/mmu_context_hash64.c
@@ -23,7 +23,7 @@
 #include <asm/mmu_context.h>
 
 static DEFINE_SPINLOCK(mmu_context_lock);
-static DEFINE_IDR(mmu_context_idr);
+static DEFINE_IDA(mmu_context_ida);
 
 /*
  * The proto-VSID space has 2^35 - 1 segments available for user mappings.
@@ -39,11 +39,11 @@ int __init_new_context(void)
         int err;
 
 again:
-        if (!idr_pre_get(&mmu_context_idr, GFP_KERNEL))
+        if (!ida_pre_get(&mmu_context_ida, GFP_KERNEL))
                 return -ENOMEM;
 
         spin_lock(&mmu_context_lock);
-        err = idr_get_new_above(&mmu_context_idr, NULL, 1, &index);
+        err = ida_get_new_above(&mmu_context_ida, 1, &index);
         spin_unlock(&mmu_context_lock);
 
         if (err == -EAGAIN)
@@ -53,7 +53,7 @@ again:
 
         if (index > MAX_CONTEXT) {
                 spin_lock(&mmu_context_lock);
-                idr_remove(&mmu_context_idr, index);
+                ida_remove(&mmu_context_ida, index);
                 spin_unlock(&mmu_context_lock);
                 return -ENOMEM;
         }
@@ -85,7 +85,7 @@ int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 void __destroy_context(int context_id)
 {
         spin_lock(&mmu_context_lock);
-        idr_remove(&mmu_context_idr, context_id);
+        ida_remove(&mmu_context_ida, context_id);
         spin_unlock(&mmu_context_lock);
 }
 EXPORT_SYMBOL_GPL(__destroy_context);
diff --git a/arch/powerpc/mm/mmu_context_nohash.c b/arch/powerpc/mm/mmu_context_nohash.c
index 1044a634b6d0..dbc692145ecb 100644
--- a/arch/powerpc/mm/mmu_context_nohash.c
+++ b/arch/powerpc/mm/mmu_context_nohash.c
@@ -56,7 +56,7 @@ static unsigned int next_context, nr_free_contexts;
 static unsigned long *context_map;
 static unsigned long *stale_map[NR_CPUS];
 static struct mm_struct **context_mm;
-static DEFINE_SPINLOCK(context_lock);
+static DEFINE_RAW_SPINLOCK(context_lock);
 
 #define CTX_MAP_SIZE    \
         (sizeof(unsigned long) * (last_context / BITS_PER_LONG + 1))
@@ -121,9 +121,9 @@ static unsigned int steal_context_smp(unsigned int id)
         /* This will happen if you have more CPUs than available contexts,
          * all we can do here is wait a bit and try again
          */
-        spin_unlock(&context_lock);
+        raw_spin_unlock(&context_lock);
         cpu_relax();
-        spin_lock(&context_lock);
+        raw_spin_lock(&context_lock);
 
         /* This will cause the caller to try again */
         return MMU_NO_CONTEXT;
@@ -194,7 +194,7 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
         unsigned long *map;
 
         /* No lockless fast path .. yet */
-        spin_lock(&context_lock);
+        raw_spin_lock(&context_lock);
 
         pr_hard("[%d] activating context for mm @%p, active=%d, id=%d",
                 cpu, next, next->context.active, next->context.id);
@@ -278,7 +278,7 @@ void switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
         /* Flick the MMU and release lock */
         pr_hardcont(" -> %d\n", id);
         set_context(id, next->pgd);
-        spin_unlock(&context_lock);
+        raw_spin_unlock(&context_lock);
 }
 
 /*
@@ -307,7 +307,7 @@ void destroy_context(struct mm_struct *mm)
 
         WARN_ON(mm->context.active != 0);
 
-        spin_lock_irqsave(&context_lock, flags);
+        raw_spin_lock_irqsave(&context_lock, flags);
         id = mm->context.id;
         if (id != MMU_NO_CONTEXT) {
                 __clear_bit(id, context_map);
@@ -318,7 +318,7 @@ void destroy_context(struct mm_struct *mm)
                 context_mm[id] = NULL;
                 nr_free_contexts++;
         }
-        spin_unlock_irqrestore(&context_lock, flags);
+        raw_spin_unlock_irqrestore(&context_lock, flags);
 }
 
 #ifdef CONFIG_SMP
diff --git a/arch/powerpc/mm/tlb_low_64e.S b/arch/powerpc/mm/tlb_low_64e.S
index f288279e679d..8b04c54e596f 100644
--- a/arch/powerpc/mm/tlb_low_64e.S
+++ b/arch/powerpc/mm/tlb_low_64e.S
@@ -1,5 +1,5 @@
 /*
- *  Low leve TLB miss handlers for Book3E
+ *  Low level TLB miss handlers for Book3E
  *
  *  Copyright (C) 2008-2009
  *      Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2fbc680c2c71..e81d5d67f834 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -150,7 +150,7 @@ EXPORT_SYMBOL(local_flush_tlb_page);
  */
 #ifdef CONFIG_SMP
 
-static DEFINE_SPINLOCK(tlbivax_lock);
+static DEFINE_RAW_SPINLOCK(tlbivax_lock);
 
 static int mm_is_core_local(struct mm_struct *mm)
 {
@@ -232,10 +232,10 @@ void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
                 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
                         int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
                         if (lock)
-                                spin_lock(&tlbivax_lock);
+                                raw_spin_lock(&tlbivax_lock);
                         _tlbivax_bcast(vmaddr, pid, tsize, ind);
                         if (lock)
-                                spin_unlock(&tlbivax_lock);
+                                raw_spin_unlock(&tlbivax_lock);
                         goto bail;
                 } else {
                         struct tlb_flush_param p = {
diff --git a/arch/powerpc/platforms/512x/clock.c b/arch/powerpc/platforms/512x/clock.c
index 84544d072043..4c42246b86a7 100644
--- a/arch/powerpc/platforms/512x/clock.c
+++ b/arch/powerpc/platforms/512x/clock.c
@@ -698,8 +698,7 @@ static struct clk_interface mpc5121_clk_functions = {
         .clk_get_parent         = NULL,
 };
 
-static int
-mpc5121_clk_init(void)
+int __init mpc5121_clk_init(void)
 {
         struct device_node *np;
 
@@ -724,6 +723,3 @@ mpc5121_clk_init(void)
         clk_functions = mpc5121_clk_functions;
         return 0;
 }
-
-
-arch_initcall(mpc5121_clk_init);
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index 441abc488851..ee6ae129c25c 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -64,8 +64,9 @@ define_machine(mpc5121_ads) {
         .name                   = "MPC5121 ADS",
         .probe                  = mpc5121_ads_probe,
         .setup_arch             = mpc5121_ads_setup_arch,
-        .init                   = mpc512x_declare_of_platform_devices,
+        .init                   = mpc512x_init,
         .init_IRQ               = mpc5121_ads_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
+        .restart                = mpc512x_restart,
 };
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
index da9b20a63769..4ecf4cf9a51b 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
@@ -79,7 +79,7 @@ cpld_unmask_irq(unsigned int irq)
 }
 
 static struct irq_chip cpld_pic = {
-        .name = " CPLD PIC ",
+        .name = "CPLD PIC",
         .mask = cpld_mask_irq,
         .ack = cpld_mask_irq,
         .unmask = cpld_unmask_irq,
diff --git a/arch/powerpc/platforms/512x/mpc5121_generic.c b/arch/powerpc/platforms/512x/mpc5121_generic.c
index 2479de9e2d12..a6c0e3a2615d 100644
--- a/arch/powerpc/platforms/512x/mpc5121_generic.c
+++ b/arch/powerpc/platforms/512x/mpc5121_generic.c
@@ -51,8 +51,9 @@ static int __init mpc5121_generic_probe(void)
 define_machine(mpc5121_generic) {
         .name                   = "MPC5121 generic",
         .probe                  = mpc5121_generic_probe,
-        .init                   = mpc512x_declare_of_platform_devices,
+        .init                   = mpc512x_init,
         .init_IRQ               = mpc512x_init_IRQ,
         .get_irq                = ipic_get_irq,
         .calibrate_decr         = generic_calibrate_decr,
+        .restart                = mpc512x_restart,
 };
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index 22a5352407e0..b2daca0d1488 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -12,5 +12,8 @@
 #ifndef __MPC512X_H__
 #define __MPC512X_H__
 extern void __init mpc512x_init_IRQ(void);
+extern void __init mpc512x_init(void);
+extern int __init mpc5121_clk_init(void);
 void __init mpc512x_declare_of_platform_devices(void);
+extern void mpc512x_restart(char *cmd);
 #endif                          /* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 434d683df5a0..b7f518a60f03 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -21,9 +21,38 @@
 #include <asm/ipic.h>
 #include <asm/prom.h>
 #include <asm/time.h>
+#include <asm/mpc5121.h>
 
 #include "mpc512x.h"
 
+static struct mpc512x_reset_module __iomem *reset_module_base;
+
+static void __init mpc512x_restart_init(void)
+{
+        struct device_node *np;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
+        if (!np)
+                return;
+
+        reset_module_base = of_iomap(np, 0);
+        of_node_put(np);
+}
+
+void mpc512x_restart(char *cmd)
+{
+        if (reset_module_base) {
+                /* Enable software reset "RSTE" */
+                out_be32(&reset_module_base->rpr, 0x52535445);
+                /* Set software hard reset */
+                out_be32(&reset_module_base->rcr, 0x2);
+        } else {
+                pr_err("Restart module not mapped.\n");
+        }
+        for (;;)
+                ;
+}
+
 void __init mpc512x_init_IRQ(void)
 {
         struct device_node *np;
@@ -53,8 +82,22 @@ static struct of_device_id __initdata of_bus_ids[] = {
 
 void __init mpc512x_declare_of_platform_devices(void)
 {
+        struct device_node *np;
+
         if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
                 printk(KERN_ERR __FILE__ ": "
                         "Error while probing of_platform bus\n");
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-nfc");
+        if (np) {
+                of_platform_device_create(np, NULL, NULL);
+                of_node_put(np);
+        }
 }
 
+void __init mpc512x_init(void)
+{
+        mpc512x_declare_of_platform_devices();
+        mpc5121_clk_init();
+        mpc512x_restart_init();
+}
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 21f61b8c445b..04d105d689f1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -302,11 +302,14 @@ static struct of_device_id mpc85xx_ids[] = {
         { .compatible = "gianfar", },
         { .compatible = "fsl,rapidio-delta", },
         { .compatible = "fsl,mpc8548-guts", },
+        { .compatible = "gpio-leds", },
         {},
 };
 
 static int __init mpc85xx_publish_devices(void)
 {
+        if (machine_is(mpc8568_mds))
+                simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
         if (machine_is(mpc8569_mds))
                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
@@ -338,7 +341,8 @@ static void __init mpc85xx_mds_pic_init(void)
         }
 
         mpic = mpic_alloc(np, r.start,
-                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
+                        MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN |
+                        MPIC_BROKEN_FRR_NIRQS,
                         0, 256, " OpenPIC  ");
         BUG_ON(mpic == NULL);
         of_node_put(np);
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 04160a4cc699..a15f582300d8 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -46,6 +46,7 @@ smp_85xx_kick_cpu(int nr)
         __iomem u32 *bptr_vaddr;
         struct device_node *np;
         int n = 0;
+        int ioremappable;
 
         WARN_ON (nr < 0 || nr >= NR_CPUS);
 
@@ -59,21 +60,37 @@ smp_85xx_kick_cpu(int nr)
                 return;
         }
 
+        /*
+         * A secondary core could be in a spinloop in the bootpage
+         * (0xfffff000), somewhere in highmem, or somewhere in lowmem.
+         * The bootpage and highmem can be accessed via ioremap(), but
+         * we need to directly access the spinloop if its in lowmem.
+         */
+        ioremappable = *cpu_rel_addr > virt_to_phys(high_memory);
+
         /* Map the spin table */
-        bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
+        if (ioremappable)
+                bptr_vaddr = ioremap(*cpu_rel_addr, SIZE_BOOT_ENTRY);
+        else
+                bptr_vaddr = phys_to_virt(*cpu_rel_addr);
 
         local_irq_save(flags);
 
         out_be32(bptr_vaddr + BOOT_ENTRY_PIR, nr);
         out_be32(bptr_vaddr + BOOT_ENTRY_ADDR_LOWER, __pa(__early_start));
 
+        if (!ioremappable)
+                flush_dcache_range((ulong)bptr_vaddr,
+                                (ulong)(bptr_vaddr + SIZE_BOOT_ENTRY));
+
         /* Wait a bit for the CPU to ack. */
         while ((__secondary_hold_acknowledge != nr) && (++n < 1000))
                 mdelay(1);
 
         local_irq_restore(flags);
 
-        iounmap(bptr_vaddr);
+        if (ioremappable)
+                iounmap(bptr_vaddr);
 
         pr_debug("waited %d msecs for CPU #%d.\n", n, nr);
 }
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
index e5da5f62b24a..42e87f08aa01 100644
--- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
@@ -232,7 +232,7 @@ static int socrates_fpga_pic_set_type(unsigned int virq,
 }
 
 static struct irq_chip socrates_fpga_pic_chip = {
-        .name           = " FPGA-PIC ",
+        .name           = "FPGA-PIC",
         .ack            = socrates_fpga_pic_ack,
         .mask           = socrates_fpga_pic_mask,
         .mask_ack       = socrates_fpga_pic_mask_ack,
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index f559918f3c6f..bc33d1859ae7 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -134,7 +134,7 @@ static void stx_gp3_show_cpuinfo(struct seq_file *m)
         pvid = mfspr(SPRN_PVR);
         svid = mfspr(SPRN_SVR);
 
-        seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
+        seq_printf(m, "Vendor\t\t: RPC Electronics STx\n");
         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 
diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
index 1b426050a2f9..0125604d096e 100644
--- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c
+++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c
@@ -80,8 +80,8 @@ static void xes_mpc85xx_configure_l2(void __iomem *l2_base)
         printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n");
 
         ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I;
-        if (machine_is_compatible("MPC8540") ||
-            machine_is_compatible("MPC8560"))
+        if (of_machine_is_compatible("MPC8540") ||
+            of_machine_is_compatible("MPC8560"))
                 /*
                  * Assume L2 SRAM is used fully for cache, so set
                  * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3).
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
index 35b1ec492715..2516c1cf8467 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -40,7 +40,7 @@
 #define DBG_LOW(fmt...) do { } while (0)
 #endif
 
-static DEFINE_SPINLOCK(beat_htab_lock);
+static DEFINE_RAW_SPINLOCK(beat_htab_lock);
 
 static inline unsigned int beat_read_mask(unsigned hpte_group)
 {
@@ -114,18 +114,18 @@ static long beat_lpar_hpte_insert(unsigned long hpte_group,
         if (rflags & _PAGE_NO_CACHE)
                 hpte_r &= ~_PAGE_COHERENT;
 
-        spin_lock(&beat_htab_lock);
+        raw_spin_lock(&beat_htab_lock);
         lpar_rc = beat_read_mask(hpte_group);
         if (lpar_rc == 0) {
                 if (!(vflags & HPTE_V_BOLTED))
                         DBG_LOW(" full\n");
-                spin_unlock(&beat_htab_lock);
+                raw_spin_unlock(&beat_htab_lock);
                 return -1;
         }
 
         lpar_rc = beat_insert_htab_entry(0, hpte_group, lpar_rc << 48,
                 hpte_v, hpte_r, &slot);
-        spin_unlock(&beat_htab_lock);
+        raw_spin_unlock(&beat_htab_lock);
 
         /*
          * Since we try and ioremap PHBs we don't own, the pte insert
@@ -198,17 +198,17 @@ static long beat_lpar_hpte_updatepp(unsigned long slot,
                 "avpnv=%016lx, slot=%016lx, psize: %d, newpp %016lx ... ",
                 want_v & HPTE_V_AVPN, slot, psize, newpp);
 
-        spin_lock(&beat_htab_lock);
+        raw_spin_lock(&beat_htab_lock);
         dummy0 = beat_lpar_hpte_getword0(slot);
         if ((dummy0 & ~0x7FUL) != (want_v & ~0x7FUL)) {
                 DBG_LOW("not found !\n");
-                spin_unlock(&beat_htab_lock);
+                raw_spin_unlock(&beat_htab_lock);
                 return -1;
         }
 
         lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7, &dummy0,
                                         &dummy1);
-        spin_unlock(&beat_htab_lock);
+        raw_spin_unlock(&beat_htab_lock);
         if (lpar_rc != 0 || dummy0 == 0) {
                 DBG_LOW("not found !\n");
                 return -1;
@@ -262,13 +262,13 @@ static void beat_lpar_hpte_updateboltedpp(unsigned long newpp,
         vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
         va = (vsid << 28) | (ea & 0x0fffffff);
 
-        spin_lock(&beat_htab_lock);
+        raw_spin_lock(&beat_htab_lock);
         slot = beat_lpar_hpte_find(va, psize);
         BUG_ON(slot == -1);
 
         lpar_rc = beat_write_htab_entry(0, slot, 0, newpp, 0, 7,
                 &dummy0, &dummy1);
-        spin_unlock(&beat_htab_lock);
+        raw_spin_unlock(&beat_htab_lock);
 
         BUG_ON(lpar_rc != 0);
 }
@@ -285,18 +285,18 @@ static void beat_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
                 slot, va, psize, local);
         want_v = hpte_encode_v(va, psize, MMU_SEGSIZE_256M);
 
-        spin_lock_irqsave(&beat_htab_lock, flags);
+        raw_spin_lock_irqsave(&beat_htab_lock, flags);
         dummy1 = beat_lpar_hpte_getword0(slot);
 
         if ((dummy1 & ~0x7FUL) != (want_v & ~0x7FUL)) {
                 DBG_LOW("not found !\n");
-                spin_unlock_irqrestore(&beat_htab_lock, flags);
+                raw_spin_unlock_irqrestore(&beat_htab_lock, flags);
                 return;
         }
 
         lpar_rc = beat_write_htab_entry(0, slot, 0, 0, HPTE_V_VALID, 0,
                 &dummy1, &dummy2);
-        spin_unlock_irqrestore(&beat_htab_lock, flags);
+        raw_spin_unlock_irqrestore(&beat_htab_lock, flags);
 
         BUG_ON(lpar_rc != 0);
 }
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index 36052a9ebcda..682af97321a8 100644
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -30,7 +30,7 @@
 #include "beat_wrapper.h"
 
 #define MAX_IRQS        NR_IRQS
-static DEFINE_SPINLOCK(beatic_irq_mask_lock);
+static DEFINE_RAW_SPINLOCK(beatic_irq_mask_lock);
 static uint64_t beatic_irq_mask_enable[(MAX_IRQS+255)/64];
 static uint64_t beatic_irq_mask_ack[(MAX_IRQS+255)/64];
 
@@ -65,30 +65,30 @@ static void beatic_mask_irq(unsigned int irq_plug)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&beatic_irq_mask_lock, flags);
+        raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
         beatic_irq_mask_enable[irq_plug/64] &= ~(1UL << (63 - (irq_plug%64)));
         beatic_update_irq_mask(irq_plug);
-        spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
+        raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
 }
 
 static void beatic_unmask_irq(unsigned int irq_plug)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&beatic_irq_mask_lock, flags);
+        raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
         beatic_irq_mask_enable[irq_plug/64] |= 1UL << (63 - (irq_plug%64));
         beatic_update_irq_mask(irq_plug);
-        spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
+        raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
 }
 
 static void beatic_ack_irq(unsigned int irq_plug)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&beatic_irq_mask_lock, flags);
+        raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
         beatic_irq_mask_ack[irq_plug/64] &= ~(1UL << (63 - (irq_plug%64)));
         beatic_update_irq_mask(irq_plug);
-        spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
+        raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
 }
 
 static void beatic_end_irq(unsigned int irq_plug)
@@ -103,14 +103,14 @@ static void beatic_end_irq(unsigned int irq_plug)
 
                 printk(KERN_ERR "IRQ over-downcounted, plug %d\n", irq_plug);
         }
-        spin_lock_irqsave(&beatic_irq_mask_lock, flags);
+        raw_spin_lock_irqsave(&beatic_irq_mask_lock, flags);
         beatic_irq_mask_ack[irq_plug/64] |= 1UL << (63 - (irq_plug%64));
         beatic_update_irq_mask(irq_plug);
-        spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
+        raw_spin_unlock_irqrestore(&beatic_irq_mask_lock, flags);
 }
 
 static struct irq_chip beatic_pic = {
-        .name = " CELL-BEAT ",
+        .name = "CELL-BEAT",
         .unmask = beatic_unmask_irq,
         .mask = beatic_mask_irq,
         .eoi = beatic_end_irq,
diff --git a/arch/powerpc/platforms/cell/cbe_powerbutton.c b/arch/powerpc/platforms/cell/cbe_powerbutton.c
index dcddaa5fcb66..f75a4daa4ca2 100644
--- a/arch/powerpc/platforms/cell/cbe_powerbutton.c
+++ b/arch/powerpc/platforms/cell/cbe_powerbutton.c
@@ -48,7 +48,7 @@ static int __init cbe_powerbutton_init(void)
         int ret = 0;
         struct input_dev *dev;
 
-        if (!machine_is_compatible("IBM,CBPLUS-1.0")) {
+        if (!of_machine_is_compatible("IBM,CBPLUS-1.0")) {
                 printk(KERN_ERR "%s: Not a cell blade.\n", __func__);
                 ret = -ENODEV;
                 goto out;
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 6829cf7e2bda..10eb1a443626 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -88,7 +88,7 @@ static void iic_eoi(unsigned int irq)
 }
 
 static struct irq_chip iic_chip = {
-        .name = " CELL-IIC ",
+        .name = "CELL-IIC",
         .mask = iic_mask,
         .unmask = iic_unmask,
         .eoi = iic_eoi,
@@ -133,7 +133,7 @@ static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
 
 
 static struct irq_chip iic_ioexc_chip = {
-        .name = " CELL-IOEX",
+        .name = "CELL-IOEX",
         .mask = iic_mask,
         .unmask = iic_unmask,
         .eoi = iic_ioexc_eoi,
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index 5e0a191764fc..608fd2b584c9 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -255,7 +255,7 @@ static int __init cbe_sysreset_init(void)
 {
         struct cbe_pmd_regs __iomem *regs;
 
-        sysreset_hack = machine_is_compatible("IBM,CBPLUS-1.0");
+        sysreset_hack = of_machine_is_compatible("IBM,CBPLUS-1.0");
         if (!sysreset_hack)
                 return 0;
 
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c
index 01244f254a11..5876e888e412 100644
--- a/arch/powerpc/platforms/cell/spider-pic.c
+++ b/arch/powerpc/platforms/cell/spider-pic.c
@@ -168,7 +168,7 @@ static int spider_set_irq_type(unsigned int virq, unsigned int type)
 }
 
 static struct irq_chip spider_pic = {
-        .name = " SPIDER   ",
+        .name = "SPIDER",
         .unmask = spider_unmask_irq,
         .mask = spider_mask_irq,
         .ack = spider_ack_irq,
diff --git a/arch/powerpc/platforms/cell/spu_manage.c b/arch/powerpc/platforms/cell/spu_manage.c
index 4c506c1463cd..891f18e337a2 100644
--- a/arch/powerpc/platforms/cell/spu_manage.c
+++ b/arch/powerpc/platforms/cell/spu_manage.c
@@ -457,7 +457,7 @@ neighbour_spu(int cbe, struct device_node *target, struct device_node *avoid)
                         continue;
                 vic_handles = of_get_property(spu_dn, "vicinity", &lenp);
                 for (i=0; i < (lenp / sizeof(phandle)); i++) {
-                        if (vic_handles[i] == target->linux_phandle)
+                        if (vic_handles[i] == target->phandle)
                                 return spu;
                 }
         }
@@ -499,7 +499,7 @@ static void init_affinity_node(int cbe)
 
                         if (strcmp(name, "spe") == 0) {
                                 spu = devnode_spu(cbe, vic_dn);
-                                avoid_ph = last_spu_dn->linux_phandle;
+                                avoid_ph = last_spu_dn->phandle;
                         } else {
                                 /*
                                  * "mic-tm" and "bif0" nodes do not have
@@ -514,7 +514,7 @@ static void init_affinity_node(int cbe)
                                         last_spu->has_mem_affinity = 1;
                                         spu->has_mem_affinity = 1;
                                 }
-                                avoid_ph = vic_dn->linux_phandle;
+                                avoid_ph = vic_dn->phandle;
                         }
 
                         list_add_tail(&spu->aff_list, &last_spu->aff_list);
diff --git a/arch/powerpc/platforms/fsl_uli1575.c b/arch/powerpc/platforms/fsl_uli1575.c
index fd23a1d4b39d..8b0c2082a783 100644
--- a/arch/powerpc/platforms/fsl_uli1575.c
+++ b/arch/powerpc/platforms/fsl_uli1575.c
@@ -222,6 +222,7 @@ static void __devinit quirk_final_uli5249(struct pci_dev *dev)
         int i;
         u8 *dummy;
         struct pci_bus *bus = dev->bus;
+        struct resource *res;
         resource_size_t end = 0;
 
         for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCES+3; i++) {
@@ -230,13 +231,12 @@ static void __devinit quirk_final_uli5249(struct pci_dev *dev)
                         end = pci_resource_end(dev, i);
         }
 
-        for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
-                if ((bus->resource[i]) &&
-                        (bus->resource[i]->flags & IORESOURCE_MEM)) {
-                        if (bus->resource[i]->end == end)
-                                dummy = ioremap(bus->resource[i]->start, 0x4);
+        pci_bus_for_each_resource(bus, res, i) {
+                if (res && res->flags & IORESOURCE_MEM) {
+                        if (res->end == end)
+                                dummy = ioremap(res->start, 0x4);
                         else
-                                dummy = ioremap(bus->resource[i]->end - 3, 0x4);
+                                dummy = ioremap(res->end - 3, 0x4);
                         if (dummy) {
                                 in_8(dummy);
                                 iounmap(dummy);
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c
index 86c4b29eea89..ba446bf355a9 100644
--- a/arch/powerpc/platforms/iseries/irq.c
+++ b/arch/powerpc/platforms/iseries/irq.c
@@ -273,7 +273,7 @@ static void iseries_end_IRQ(unsigned int irq)
 }
 
 static struct irq_chip iseries_pic = {
-        .name   = "iSeries irq controller",
+        .name           = "iSeries",
         .startup        = iseries_startup_IRQ,
         .shutdown       = iseries_shutdown_IRQ,
         .unmask         = iseries_enable_IRQ,
diff --git a/arch/powerpc/platforms/iseries/proc.c b/arch/powerpc/platforms/iseries/proc.c
index 91f4c6cd4b99..06763682db47 100644
--- a/arch/powerpc/platforms/iseries/proc.c
+++ b/arch/powerpc/platforms/iseries/proc.c
@@ -85,7 +85,7 @@ static int proc_titantod_show(struct seq_file *m, void *v)
 
                 seq_printf(m, "  titan elapsed = %lu uSec\n", titan_usec);
                 seq_printf(m, "  tb elapsed    = %lu ticks\n", tb_ticks);
-                seq_printf(m, "  titan jiffies = %lu.%04lu \n", titan_jiffies,
+                seq_printf(m, "  titan jiffies = %lu.%04lu\n", titan_jiffies,
                            titan_jiff_rem_usec);
                 seq_printf(m, "  tb jiffies    = %lu.%04lu\n", tb_jiffies,
                            tb_jiff_rem_usec);
diff --git a/arch/powerpc/platforms/iseries/setup.c b/arch/powerpc/platforms/iseries/setup.c
index a6cd3394feaa..b0863410517f 100644
--- a/arch/powerpc/platforms/iseries/setup.c
+++ b/arch/powerpc/platforms/iseries/setup.c
@@ -256,7 +256,7 @@ static unsigned long iSeries_process_mainstore_vpd(struct MemoryBlock *mb_array,
                 mem_blocks = iSeries_process_Condor_mainstore_vpd(mb_array,
                                 max_entries);
 
-        printk("Mainstore_VPD: numMemoryBlocks = %ld \n", mem_blocks);
+        printk("Mainstore_VPD: numMemoryBlocks = %ld\n", mem_blocks);
         for (i = 0; i < mem_blocks; ++i) {
                 printk("Mainstore_VPD: block %3ld logical chunks %016lx - %016lx\n"
                        "                             abs chunks %016lx - %016lx\n",
diff --git a/arch/powerpc/platforms/pasemi/cpufreq.c b/arch/powerpc/platforms/pasemi/cpufreq.c
index be2527a516ea..d35e0520abf0 100644
--- a/arch/powerpc/platforms/pasemi/cpufreq.c
+++ b/arch/powerpc/platforms/pasemi/cpufreq.c
@@ -304,8 +304,8 @@ static struct cpufreq_driver pas_cpufreq_driver = {
 
 static int __init pas_cpufreq_init(void)
 {
-        if (!machine_is_compatible("PA6T-1682M") &&
-            !machine_is_compatible("pasemi,pwrficient"))
+        if (!of_machine_is_compatible("PA6T-1682M") &&
+            !of_machine_is_compatible("pasemi,pwrficient"))
                 return -ENODEV;
 
         return cpufreq_register_driver(&pas_cpufreq_driver);
diff --git a/arch/powerpc/platforms/powermac/bootx_init.c b/arch/powerpc/platforms/powermac/bootx_init.c
index 9dd789a7370d..84d7fd9bcc69 100644
--- a/arch/powerpc/platforms/powermac/bootx_init.c
+++ b/arch/powerpc/platforms/powermac/bootx_init.c
@@ -539,7 +539,7 @@ void __init bootx_init(unsigned long r3, unsigned long r4)
                 if (model
                     && (strcmp(model, "iMac,1") == 0
                         || strcmp(model, "PowerMac1,1") == 0)) {
-                        bootx_printf("iMac,1 detected, shutting down USB \n");
+                        bootx_printf("iMac,1 detected, shutting down USB\n");
                         out_le32((unsigned __iomem *)0x80880008, 1);    /* XXX */
                 }
         }
@@ -554,7 +554,7 @@ void __init bootx_init(unsigned long r3, unsigned long r4)
         } else
                 space = bi->totalParamsSize;
 
-        bootx_printf("Total space used by parameters & ramdisk: 0x%x \n", space);
+        bootx_printf("Total space used by parameters & ramdisk: 0x%x\n", space);
 
         /* New BootX will have flushed all TLBs and enters kernel with
          * MMU switched OFF, so this should not be useful anymore.
diff --git a/arch/powerpc/platforms/powermac/cpufreq_32.c b/arch/powerpc/platforms/powermac/cpufreq_32.c
index 08d94e4cedd3..d4f127d18141 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_32.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_32.c
@@ -657,31 +657,31 @@ static int __init pmac_cpufreq_setup(void)
         cur_freq = (*value) / 1000;
 
         /*  Check for 7447A based MacRISC3 */
-        if (machine_is_compatible("MacRISC3") &&
+        if (of_machine_is_compatible("MacRISC3") &&
             of_get_property(cpunode, "dynamic-power-step", NULL) &&
             PVR_VER(mfspr(SPRN_PVR)) == 0x8003) {
                 pmac_cpufreq_init_7447A(cpunode);
         /* Check for other MacRISC3 machines */
-        } else if (machine_is_compatible("PowerBook3,4") ||
-                   machine_is_compatible("PowerBook3,5") ||
-                   machine_is_compatible("MacRISC3")) {
+        } else if (of_machine_is_compatible("PowerBook3,4") ||
+                   of_machine_is_compatible("PowerBook3,5") ||
+                   of_machine_is_compatible("MacRISC3")) {
                 pmac_cpufreq_init_MacRISC3(cpunode);
         /* Else check for iBook2 500/600 */
-        } else if (machine_is_compatible("PowerBook4,1")) {
+        } else if (of_machine_is_compatible("PowerBook4,1")) {
                 hi_freq = cur_freq;
                 low_freq = 400000;
                 set_speed_proc = pmu_set_cpu_speed;
                 is_pmu_based = 1;
         }
         /* Else check for TiPb 550 */
-        else if (machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
+        else if (of_machine_is_compatible("PowerBook3,3") && cur_freq == 550000) {
                 hi_freq = cur_freq;
                 low_freq = 500000;
                 set_speed_proc = pmu_set_cpu_speed;
                 is_pmu_based = 1;
         }
         /* Else check for TiPb 400 & 500 */
-        else if (machine_is_compatible("PowerBook3,2")) {
+        else if (of_machine_is_compatible("PowerBook3,2")) {
                 /* We only know about the 400 MHz and the 500Mhz model
                  * they both have 300 MHz as low frequency
                  */
diff --git a/arch/powerpc/platforms/powermac/cpufreq_64.c b/arch/powerpc/platforms/powermac/cpufreq_64.c
index 708c75133377..3ed288e68ec4 100644
--- a/arch/powerpc/platforms/powermac/cpufreq_64.c
+++ b/arch/powerpc/platforms/powermac/cpufreq_64.c
@@ -398,11 +398,11 @@ static int __init g5_neo2_cpufreq_init(struct device_node *cpus)
         int rc = -ENODEV;
 
         /* Check supported platforms */
-        if (machine_is_compatible("PowerMac8,1") ||
-            machine_is_compatible("PowerMac8,2") ||
-            machine_is_compatible("PowerMac9,1"))
+        if (of_machine_is_compatible("PowerMac8,1") ||
+            of_machine_is_compatible("PowerMac8,2") ||
+            of_machine_is_compatible("PowerMac9,1"))
                 use_volts_smu = 1;
-        else if (machine_is_compatible("PowerMac11,2"))
+        else if (of_machine_is_compatible("PowerMac11,2"))
                 use_volts_vdnap = 1;
         else
                 return -ENODEV;
@@ -729,9 +729,9 @@ static int __init g5_cpufreq_init(void)
                 return -ENODEV;
         }
 
-        if (machine_is_compatible("PowerMac7,2") ||
-            machine_is_compatible("PowerMac7,3") ||
-            machine_is_compatible("RackMac3,1"))
+        if (of_machine_is_compatible("PowerMac7,2") ||
+            of_machine_is_compatible("PowerMac7,3") ||
+            of_machine_is_compatible("RackMac3,1"))
                 rc = g5_pm72_cpufreq_init(cpus);
 #ifdef CONFIG_PMAC_SMU
         else
diff --git a/arch/powerpc/platforms/powermac/feature.c b/arch/powerpc/platforms/powermac/feature.c
index fbc9bbd74dbd..9e1b9fd75206 100644
--- a/arch/powerpc/platforms/powermac/feature.c
+++ b/arch/powerpc/platforms/powermac/feature.c
@@ -59,10 +59,10 @@ extern struct device_node *k2_skiplist[2];
  * We use a single global lock to protect accesses. Each driver has
  * to take care of its own locking
  */
-DEFINE_SPINLOCK(feature_lock);
+DEFINE_RAW_SPINLOCK(feature_lock);
 
-#define LOCK(flags)     spin_lock_irqsave(&feature_lock, flags);
-#define UNLOCK(flags)   spin_unlock_irqrestore(&feature_lock, flags);
+#define LOCK(flags)     raw_spin_lock_irqsave(&feature_lock, flags);
+#define UNLOCK(flags)   raw_spin_unlock_irqrestore(&feature_lock, flags);
 
 
 /*
@@ -2426,7 +2426,7 @@ static int __init probe_motherboard(void)
             }
         }
         for(i=0; i<ARRAY_SIZE(pmac_mb_defs); i++) {
-            if (machine_is_compatible(pmac_mb_defs[i].model_string)) {
+            if (of_machine_is_compatible(pmac_mb_defs[i].model_string)) {
                 pmac_mb = pmac_mb_defs[i];
                 goto found;
             }
diff --git a/arch/powerpc/platforms/powermac/nvram.c b/arch/powerpc/platforms/powermac/nvram.c
index c6f0f9e738e5..80a5258d0364 100644
--- a/arch/powerpc/platforms/powermac/nvram.c
+++ b/arch/powerpc/platforms/powermac/nvram.c
@@ -80,7 +80,7 @@ static int is_core_99;
 static int core99_bank = 0;
 static int nvram_partitions[3];
 // XXX Turn that into a sem
-static DEFINE_SPINLOCK(nv_lock);
+static DEFINE_RAW_SPINLOCK(nv_lock);
 
 static int (*core99_write_bank)(int bank, u8* datas);
 static int (*core99_erase_bank)(int bank);
@@ -165,10 +165,10 @@ static unsigned char indirect_nvram_read_byte(int addr)
         unsigned char val;
         unsigned long flags;
 
-        spin_lock_irqsave(&nv_lock, flags);
+        raw_spin_lock_irqsave(&nv_lock, flags);
         out_8(nvram_addr, addr >> 5);
         val = in_8(&nvram_data[(addr & 0x1f) << 4]);
-        spin_unlock_irqrestore(&nv_lock, flags);
+        raw_spin_unlock_irqrestore(&nv_lock, flags);
 
         return val;
 }
@@ -177,10 +177,10 @@ static void indirect_nvram_write_byte(int addr, unsigned char val)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&nv_lock, flags);
+        raw_spin_lock_irqsave(&nv_lock, flags);
         out_8(nvram_addr, addr >> 5);
         out_8(&nvram_data[(addr & 0x1f) << 4], val);
-        spin_unlock_irqrestore(&nv_lock, flags);
+        raw_spin_unlock_irqrestore(&nv_lock, flags);
 }
 
 
@@ -481,7 +481,7 @@ static void core99_nvram_sync(void)
         if (!is_core_99 || !nvram_data || !nvram_image)
                 return;
 
-        spin_lock_irqsave(&nv_lock, flags);
+        raw_spin_lock_irqsave(&nv_lock, flags);
         if (!memcmp(nvram_image, (u8*)nvram_data + core99_bank*NVRAM_SIZE,
                 NVRAM_SIZE))
                 goto bail;
@@ -503,7 +503,7 @@ static void core99_nvram_sync(void)
                 if (core99_write_bank(core99_bank, nvram_image))
                         printk("nvram: Error writing bank %d\n", core99_bank);
  bail:
-        spin_unlock_irqrestore(&nv_lock, flags);
+        raw_spin_unlock_irqrestore(&nv_lock, flags);
 
 #ifdef DEBUG
         mdelay(2000);
diff --git a/arch/powerpc/platforms/powermac/pfunc_base.c b/arch/powerpc/platforms/powermac/pfunc_base.c
index db20de512f3e..f5e3cda6660e 100644
--- a/arch/powerpc/platforms/powermac/pfunc_base.c
+++ b/arch/powerpc/platforms/powermac/pfunc_base.c
@@ -50,13 +50,13 @@ static int macio_do_gpio_write(PMF_STD_ARGS, u8 value, u8 mask)
                 value = ~value;
 
         /* Toggle the GPIO */
-        spin_lock_irqsave(&feature_lock, flags);
+        raw_spin_lock_irqsave(&feature_lock, flags);
         tmp = readb(addr);
         tmp = (tmp & ~mask) | (value & mask);
         DBG("Do write 0x%02x to GPIO %s (%p)\n",
             tmp, func->node->full_name, addr);
         writeb(tmp, addr);
-        spin_unlock_irqrestore(&feature_lock, flags);
+        raw_spin_unlock_irqrestore(&feature_lock, flags);
 
         return 0;
 }
@@ -145,9 +145,9 @@ static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
         struct macio_chip *macio = func->driver_data;
         unsigned long flags;
 
-        spin_lock_irqsave(&feature_lock, flags);
+        raw_spin_lock_irqsave(&feature_lock, flags);
         MACIO_OUT32(offset, (MACIO_IN32(offset) & ~mask) | (value & mask));
-        spin_unlock_irqrestore(&feature_lock, flags);
+        raw_spin_unlock_irqrestore(&feature_lock, flags);
         return 0;
 }
 
@@ -168,9 +168,9 @@ static int macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask)
         struct macio_chip *macio = func->driver_data;
         unsigned long flags;
 
-        spin_lock_irqsave(&feature_lock, flags);
+        raw_spin_lock_irqsave(&feature_lock, flags);
         MACIO_OUT8(offset, (MACIO_IN8(offset) & ~mask) | (value & mask));
-        spin_unlock_irqrestore(&feature_lock, flags);
+        raw_spin_unlock_irqrestore(&feature_lock, flags);
         return 0;
 }
 
@@ -223,12 +223,12 @@ static int macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift,
         if (args == NULL || args->count == 0)
                 return -EINVAL;
 
-        spin_lock_irqsave(&feature_lock, flags);
+        raw_spin_lock_irqsave(&feature_lock, flags);
         tmp = MACIO_IN32(offset);
         val = args->u[0].v << shift;
         tmp = (tmp & ~mask) | (val & mask);
         MACIO_OUT32(offset, tmp);
-        spin_unlock_irqrestore(&feature_lock, flags);
+        raw_spin_unlock_irqrestore(&feature_lock, flags);
         return 0;
 }
 
@@ -243,12 +243,12 @@ static int macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift,
         if (args == NULL || args->count == 0)
                 return -EINVAL;
 
-        spin_lock_irqsave(&feature_lock, flags);
+        raw_spin_lock_irqsave(&feature_lock, flags);
         tmp = MACIO_IN8(offset);
         val = args->u[0].v << shift;
         tmp = (tmp & ~mask) | (val & mask);
         MACIO_OUT8(offset, tmp);
-        spin_unlock_irqrestore(&feature_lock, flags);
+        raw_spin_unlock_irqrestore(&feature_lock, flags);
         return 0;
 }
 
@@ -278,12 +278,12 @@ static int unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&feature_lock, flags);
+        raw_spin_lock_irqsave(&feature_lock, flags);
         /* This is fairly bogus in darwin, but it should work for our needs
          * implemeted that way:
          */
         UN_OUT(offset, (UN_IN(offset) & ~mask) | (value & mask));
-        spin_unlock_irqrestore(&feature_lock, flags);
+        raw_spin_unlock_irqrestore(&feature_lock, flags);
         return 0;
 }
 
diff --git a/arch/powerpc/platforms/powermac/pfunc_core.c b/arch/powerpc/platforms/powermac/pfunc_core.c
index 96d5ce50364e..ede49e78a8da 100644
--- a/arch/powerpc/platforms/powermac/pfunc_core.c
+++ b/arch/powerpc/platforms/powermac/pfunc_core.c
@@ -842,7 +842,7 @@ struct pmf_function *__pmf_find_function(struct device_node *target,
         list_for_each_entry(func, &dev->functions, link) {
                 if (name && strcmp(name, func->name))
                         continue;
-                if (func->phandle && target->node != func->phandle)
+                if (func->phandle && target->phandle != func->phandle)
                         continue;
                 if ((func->flags & flags) == 0)
                         continue;
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 09e827296276..630a533d0e59 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -57,7 +57,7 @@ static int max_irqs;
 static int max_real_irqs;
 static u32 level_mask[4];
 
-static DEFINE_SPINLOCK(pmac_pic_lock);
+static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
 
 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
 static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
@@ -85,7 +85,7 @@ static void pmac_mask_and_ack_irq(unsigned int virq)
         int i = src >> 5;
         unsigned long flags;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         __clear_bit(src, ppc_cached_irq_mask);
         if (__test_and_clear_bit(src, ppc_lost_interrupts))
                 atomic_dec(&ppc_n_lost_interrupts);
@@ -97,7 +97,7 @@ static void pmac_mask_and_ack_irq(unsigned int virq)
                 mb();
         } while((in_le32(&pmac_irq_hw[i]->enable) & bit)
                 != (ppc_cached_irq_mask[i] & bit));
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 }
 
 static void pmac_ack_irq(unsigned int virq)
@@ -107,12 +107,12 @@ static void pmac_ack_irq(unsigned int virq)
         int i = src >> 5;
         unsigned long flags;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         if (__test_and_clear_bit(src, ppc_lost_interrupts))
                 atomic_dec(&ppc_n_lost_interrupts);
         out_le32(&pmac_irq_hw[i]->ack, bit);
         (void)in_le32(&pmac_irq_hw[i]->ack);
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 }
 
 static void __pmac_set_irq_mask(unsigned int irq_nr, int nokicklost)
@@ -152,12 +152,12 @@ static unsigned int pmac_startup_irq(unsigned int virq)
         unsigned long bit = 1UL << (src & 0x1f);
         int i = src >> 5;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         if ((irq_to_desc(virq)->status & IRQ_LEVEL) == 0)
                 out_le32(&pmac_irq_hw[i]->ack, bit);
         __set_bit(src, ppc_cached_irq_mask);
         __pmac_set_irq_mask(src, 0);
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 
         return 0;
 }
@@ -167,10 +167,10 @@ static void pmac_mask_irq(unsigned int virq)
         unsigned long flags;
         unsigned int src = irq_map[virq].hwirq;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         __clear_bit(src, ppc_cached_irq_mask);
         __pmac_set_irq_mask(src, 1);
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 }
 
 static void pmac_unmask_irq(unsigned int virq)
@@ -178,24 +178,24 @@ static void pmac_unmask_irq(unsigned int virq)
         unsigned long flags;
         unsigned int src = irq_map[virq].hwirq;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         __set_bit(src, ppc_cached_irq_mask);
         __pmac_set_irq_mask(src, 0);
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
 }
 
 static int pmac_retrigger(unsigned int virq)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         __pmac_retrigger(irq_map[virq].hwirq);
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
         return 1;
 }
 
 static struct irq_chip pmac_pic = {
-        .name           = " PMAC-PIC ",
+        .name           = "PMAC-PIC",
         .startup        = pmac_startup_irq,
         .mask           = pmac_mask_irq,
         .ack            = pmac_ack_irq,
@@ -210,7 +210,7 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id)
         int irq, bits;
         int rc = IRQ_NONE;
 
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         for (irq = max_irqs; (irq -= 32) >= max_real_irqs; ) {
                 int i = irq >> 5;
                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
@@ -220,12 +220,12 @@ static irqreturn_t gatwick_action(int cpl, void *dev_id)
                 if (bits == 0)
                         continue;
                 irq += __ilog2(bits);
-                spin_unlock_irqrestore(&pmac_pic_lock, flags);
+                raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
                 generic_handle_irq(irq);
-                spin_lock_irqsave(&pmac_pic_lock, flags);
+                raw_spin_lock_irqsave(&pmac_pic_lock, flags);
                 rc = IRQ_HANDLED;
         }
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
         return rc;
 }
 
@@ -244,7 +244,7 @@ static unsigned int pmac_pic_get_irq(void)
                 return NO_IRQ_IGNORE;   /* ignore, already handled */
         }
 #endif /* CONFIG_SMP */
-        spin_lock_irqsave(&pmac_pic_lock, flags);
+        raw_spin_lock_irqsave(&pmac_pic_lock, flags);
         for (irq = max_real_irqs; (irq -= 32) >= 0; ) {
                 int i = irq >> 5;
                 bits = in_le32(&pmac_irq_hw[i]->event) | ppc_lost_interrupts[i];
@@ -256,7 +256,7 @@ static unsigned int pmac_pic_get_irq(void)
                 irq += __ilog2(bits);
                 break;
         }
-        spin_unlock_irqrestore(&pmac_pic_lock, flags);
+        raw_spin_unlock_irqrestore(&pmac_pic_lock, flags);
         if (unlikely(irq < 0))
                 return NO_IRQ;
         return irq_linear_revmap(pmac_pic_host, irq);
diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
index b40c22d697f0..6898e8241cd0 100644
--- a/arch/powerpc/platforms/powermac/smp.c
+++ b/arch/powerpc/platforms/powermac/smp.c
@@ -693,9 +693,9 @@ static void __init smp_core99_setup(int ncpus)
 #ifdef CONFIG_PPC64
 
         /* i2c based HW sync on some G5s */
-        if (machine_is_compatible("PowerMac7,2") ||
-            machine_is_compatible("PowerMac7,3") ||
-            machine_is_compatible("RackMac3,1"))
+        if (of_machine_is_compatible("PowerMac7,2") ||
+            of_machine_is_compatible("PowerMac7,3") ||
+            of_machine_is_compatible("RackMac3,1"))
                 smp_core99_setup_i2c_hwsync(ncpus);
 
         /* pfunc based HW sync on recent G5s */
@@ -713,7 +713,7 @@ static void __init smp_core99_setup(int ncpus)
 #else /* CONFIG_PPC64 */
 
         /* GPIO based HW sync on ppc32 Core99 */
-        if (pmac_tb_freeze == NULL && !machine_is_compatible("MacRISC4")) {
+        if (pmac_tb_freeze == NULL && !of_machine_is_compatible("MacRISC4")) {
                 struct device_node *cpu;
                 const u32 *tbprop = NULL;
 
@@ -750,7 +750,7 @@ static void __init smp_core99_setup(int ncpus)
 #endif
 
         /* 32 bits SMP can't NAP */
-        if (!machine_is_compatible("MacRISC4"))
+        if (!of_machine_is_compatible("MacRISC4"))
                 powersave_nap = 0;
 }
 
@@ -852,7 +852,7 @@ static void __devinit smp_core99_setup_cpu(int cpu_nr)
                 /* If we didn't start the second CPU, we must take
                  * it off the bus
                  */
-                if (machine_is_compatible("MacRISC4") &&
+                if (of_machine_is_compatible("MacRISC4") &&
                     num_online_cpus() < 2)              
                         g5_phy_disable_cpu1();
 #endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/platforms/powermac/time.c b/arch/powerpc/platforms/powermac/time.c
index 1810e4226e56..48211ca134c3 100644
--- a/arch/powerpc/platforms/powermac/time.c
+++ b/arch/powerpc/platforms/powermac/time.c
@@ -317,9 +317,9 @@ void __init pmac_calibrate_decr(void)
          * calibration. That's better since the VIA itself seems
          * to be slightly off. --BenH
          */
-        if (!machine_is_compatible("MacRISC2") &&
-            !machine_is_compatible("MacRISC3") &&
-            !machine_is_compatible("MacRISC4"))
+        if (!of_machine_is_compatible("MacRISC2") &&
+            !of_machine_is_compatible("MacRISC3") &&
+            !of_machine_is_compatible("MacRISC4"))
                 if (via_calibrate_decr())
                         return;
 
@@ -328,7 +328,7 @@ void __init pmac_calibrate_decr(void)
          * probably implement calibration based on the KL timer on these
          * machines anyway... -BenH
          */
-        if (machine_is_compatible("PowerMac3,5"))
+        if (of_machine_is_compatible("PowerMac3,5"))
                 if (via_calibrate_decr())
                         return;
 #endif
diff --git a/arch/powerpc/platforms/powermac/udbg_scc.c b/arch/powerpc/platforms/powermac/udbg_scc.c
index 9490157da62e..d83135a9830e 100644
--- a/arch/powerpc/platforms/powermac/udbg_scc.c
+++ b/arch/powerpc/platforms/powermac/udbg_scc.c
@@ -132,9 +132,9 @@ void udbg_scc_init(int force_scc)
                 scc_inittab[1] = in_8(sccc);
                 out_8(sccc, 12);
                 scc_inittab[3] = in_8(sccc);
-        } else if (machine_is_compatible("RackMac1,1")
-                   || machine_is_compatible("RackMac1,2")
-                   || machine_is_compatible("MacRISC4")) {
+        } else if (of_machine_is_compatible("RackMac1,1")
+                   || of_machine_is_compatible("RackMac1,2")
+                   || of_machine_is_compatible("MacRISC4")) {
                 /* Xserves and G5s default to 57600 */
                 scc_inittab[1] = 0;
                 scc_inittab[3] = 0;
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index ccd8dd03b8c9..7df7fbb7cacb 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -100,7 +100,7 @@ int eeh_subsystem_enabled;
 EXPORT_SYMBOL(eeh_subsystem_enabled);
 
 /* Lock to avoid races due to multiple reports of an error */
-static DEFINE_SPINLOCK(confirm_error_lock);
+static DEFINE_RAW_SPINLOCK(confirm_error_lock);
 
 /* Buffer for reporting slot-error-detail rtas calls. Its here
  * in BSS, and not dynamically alloced, so that it ends up in
@@ -436,7 +436,7 @@ static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
 void eeh_clear_slot (struct device_node *dn, int mode_flag)
 {
         unsigned long flags;
-        spin_lock_irqsave(&confirm_error_lock, flags);
+        raw_spin_lock_irqsave(&confirm_error_lock, flags);
         
         dn = find_device_pe (dn);
         
@@ -447,7 +447,7 @@ void eeh_clear_slot (struct device_node *dn, int mode_flag)
         PCI_DN(dn)->eeh_mode &= ~mode_flag;
         PCI_DN(dn)->eeh_check_count = 0;
         __eeh_clear_slot(dn, mode_flag);
-        spin_unlock_irqrestore(&confirm_error_lock, flags);
+        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 }
 
 /**
@@ -491,7 +491,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
             pdn->eeh_mode & EEH_MODE_NOCHECK) {
                 ignored_check++;
                 pr_debug("EEH: Ignored check (%x) for %s %s\n",
-                         pdn->eeh_mode, pci_name (dev), dn->full_name);
+                         pdn->eeh_mode, eeh_pci_name(dev), dn->full_name);
                 return 0;
         }
 
@@ -506,7 +506,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          * in one slot might report errors simultaneously, and we
          * only want one error recovery routine running.
          */
-        spin_lock_irqsave(&confirm_error_lock, flags);
+        raw_spin_lock_irqsave(&confirm_error_lock, flags);
         rc = 1;
         if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
                 pdn->eeh_check_count ++;
@@ -515,7 +515,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
                         printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
                                 "location=%s driver=%s pci addr=%s\n",
                                 pdn->eeh_check_count, location,
-                                dev->driver->name, pci_name(dev));
+                                dev->driver->name, eeh_pci_name(dev));
                         printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
                                 dev->driver->name);
                         dump_stack();
@@ -575,7 +575,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
          * with other functions on this device, and functions under
          * bridges. */
         eeh_mark_slot (dn, EEH_MODE_ISOLATED);
-        spin_unlock_irqrestore(&confirm_error_lock, flags);
+        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
 
         eeh_send_failure_event (dn, dev);
 
@@ -586,7 +586,7 @@ int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
         return 1;
 
 dn_unlock:
-        spin_unlock_irqrestore(&confirm_error_lock, flags);
+        raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
         return rc;
 }
 
@@ -1064,7 +1064,7 @@ void __init eeh_init(void)
         struct device_node *phb, *np;
         struct eeh_early_enable_info info;
 
-        spin_lock_init(&confirm_error_lock);
+        raw_spin_lock_init(&confirm_error_lock);
         spin_lock_init(&slot_errbuf_lock);
 
         np = of_find_node_by_path("/rtas");
diff --git a/arch/powerpc/platforms/pseries/eeh_driver.c b/arch/powerpc/platforms/pseries/eeh_driver.c
index ef8e45448480..b8d70f5d9aa9 100644
--- a/arch/powerpc/platforms/pseries/eeh_driver.c
+++ b/arch/powerpc/platforms/pseries/eeh_driver.c
@@ -337,7 +337,7 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
                 location = location ? location : "unknown";
                 printk(KERN_ERR "EEH: Error: Cannot find partition endpoint "
                                 "for location=%s pci addr=%s\n",
-                        location, pci_name(event->dev));
+                        location, eeh_pci_name(event->dev));
                 return NULL;
         }
 
@@ -368,7 +368,7 @@ struct pci_dn * handle_eeh_events (struct eeh_event *event)
                 pci_str = pci_name (frozen_pdn->pcidev);
                 drv_str = pcid_name (frozen_pdn->pcidev);
         } else {
-                pci_str = pci_name (event->dev);
+                pci_str = eeh_pci_name(event->dev);
                 drv_str = pcid_name (event->dev);
         }
         
@@ -478,9 +478,9 @@ excess_failures:
          * due to actual, failed cards.
          */
         printk(KERN_ERR
-           "EEH: PCI device at location=%s driver=%s pci addr=%s \n"
+           "EEH: PCI device at location=%s driver=%s pci addr=%s\n"
                 "has failed %d times in the last hour "
-                "and has been permanently disabled. \n"
+                "and has been permanently disabled.\n"
                 "Please try reseating this device or replacing it.\n",
                 location, drv_str, pci_str, frozen_pdn->eeh_freeze_count);
         goto perm_error;
@@ -488,7 +488,7 @@ excess_failures:
 hard_fail:
         printk(KERN_ERR
            "EEH: Unable to recover from failure of PCI device "
-           "at location=%s driver=%s pci addr=%s \n"
+           "at location=%s driver=%s pci addr=%s\n"
            "Please try reseating this device or replacing it.\n",
                 location, drv_str, pci_str);
 
diff --git a/arch/powerpc/platforms/pseries/eeh_event.c b/arch/powerpc/platforms/pseries/eeh_event.c
index ddb80f5d850b..ec5df8f519c7 100644
--- a/arch/powerpc/platforms/pseries/eeh_event.c
+++ b/arch/powerpc/platforms/pseries/eeh_event.c
@@ -80,7 +80,7 @@ static int eeh_event_handler(void * dummy)
         eeh_mark_slot(event->dn, EEH_MODE_RECOVERING);
 
         printk(KERN_INFO "EEH: Detected PCI bus error on device %s\n",
-               pci_name(event->dev));
+               eeh_pci_name(event->dev));
 
         pdn = handle_eeh_events(event);
 
diff --git a/arch/powerpc/platforms/pseries/hotplug-cpu.c b/arch/powerpc/platforms/pseries/hotplug-cpu.c
index 6ea4698d9176..d1b124e44d77 100644
--- a/arch/powerpc/platforms/pseries/hotplug-cpu.c
+++ b/arch/powerpc/platforms/pseries/hotplug-cpu.c
@@ -387,24 +387,12 @@ static char cede_parameters[CEDE_LATENCY_PARAM_MAX_LENGTH];
 
 static int parse_cede_parameters(void)
 {
-        int call_status;
-
         memset(cede_parameters, 0, CEDE_LATENCY_PARAM_MAX_LENGTH);
-        call_status = rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
-                                NULL,
-                                CEDE_LATENCY_TOKEN,
-                                __pa(cede_parameters),
-                                CEDE_LATENCY_PARAM_MAX_LENGTH);
-
-        if (call_status != 0)
-                printk(KERN_INFO "CEDE_LATENCY: \
-                        %s %s Error calling get-system-parameter(0x%x)\n",
-                        __FILE__, __func__, call_status);
-        else
-                printk(KERN_INFO "CEDE_LATENCY: \
-                        get-system-parameter successful.\n");
-
-        return call_status;
+        return rtas_call(rtas_token("ibm,get-system-parameter"), 3, 1,
+                         NULL,
+                         CEDE_LATENCY_TOKEN,
+                         __pa(cede_parameters),
+                         CEDE_LATENCY_PARAM_MAX_LENGTH);
 }
 
 static int __init pseries_cpu_hotplug_init(void)
diff --git a/arch/powerpc/platforms/pseries/hvCall_inst.c b/arch/powerpc/platforms/pseries/hvCall_inst.c
index 2f58c71b7259..1fefae76e295 100644
--- a/arch/powerpc/platforms/pseries/hvCall_inst.c
+++ b/arch/powerpc/platforms/pseries/hvCall_inst.c
@@ -124,8 +124,8 @@ static void probe_hcall_exit(unsigned long opcode, unsigned long retval,
 
         h = &__get_cpu_var(hcall_stats)[opcode / 4];
         h->num_calls++;
-        h->tb_total = mftb() - h->tb_start;
-        h->purr_total = mfspr(SPRN_PURR) - h->purr_start;
+        h->tb_total += mftb() - h->tb_start;
+        h->purr_total += mfspr(SPRN_PURR) - h->purr_start;
 
         put_cpu_var(hcall_stats);
 }
diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index b6fa3e4b51b5..4b7a062dee15 100644
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -165,7 +165,7 @@ int remove_phb_dynamic(struct pci_controller *phb)
         struct resource *res;
         int rc, i;
 
-        pr_debug("PCI: Removing PHB %04x:%02x... \n",
+        pr_debug("PCI: Removing PHB %04x:%02x...\n",
                  pci_domain_nr(b), b->number);
 
         /* We cannot to remove a root bus that has children */
diff --git a/arch/powerpc/platforms/pseries/phyp_dump.c b/arch/powerpc/platforms/pseries/phyp_dump.c
index 15eb6107bcd2..225a50ab14be 100644
--- a/arch/powerpc/platforms/pseries/phyp_dump.c
+++ b/arch/powerpc/platforms/pseries/phyp_dump.c
@@ -150,7 +150,7 @@ static void print_dump_header(const struct phyp_dump_header *ph)
         printk(KERN_INFO "Max auto time= %d\n", ph->maxtime_to_auto);
 
         /*set cpu state and hpte states as well scratch pad area */
-        printk(KERN_INFO " CPU AREA \n");
+        printk(KERN_INFO " CPU AREA\n");
         printk(KERN_INFO "cpu dump_flags =%d\n", ph->cpu_data.dump_flags);
         printk(KERN_INFO "cpu source_type =%d\n", ph->cpu_data.source_type);
         printk(KERN_INFO "cpu error_flags =%d\n", ph->cpu_data.error_flags);
@@ -161,7 +161,7 @@ static void print_dump_header(const struct phyp_dump_header *ph)
         printk(KERN_INFO "cpu length_copied =%llx\n",
                 ph->cpu_data.length_copied);
 
-        printk(KERN_INFO " HPTE AREA \n");
+        printk(KERN_INFO " HPTE AREA\n");
         printk(KERN_INFO "HPTE dump_flags =%d\n", ph->hpte_data.dump_flags);
         printk(KERN_INFO "HPTE source_type =%d\n", ph->hpte_data.source_type);
         printk(KERN_INFO "HPTE error_flags =%d\n", ph->hpte_data.error_flags);
@@ -172,7 +172,7 @@ static void print_dump_header(const struct phyp_dump_header *ph)
         printk(KERN_INFO "HPTE length_copied =%llx\n",
                 ph->hpte_data.length_copied);
 
-        printk(KERN_INFO " SRSD AREA \n");
+        printk(KERN_INFO " SRSD AREA\n");
         printk(KERN_INFO "SRSD dump_flags =%d\n", ph->kernel_data.dump_flags);
         printk(KERN_INFO "SRSD source_type =%d\n", ph->kernel_data.source_type);
         printk(KERN_INFO "SRSD error_flags =%d\n", ph->kernel_data.error_flags);
diff --git a/arch/powerpc/platforms/pseries/smp.c b/arch/powerpc/platforms/pseries/smp.c
index b4886635972c..4e7f89a84561 100644
--- a/arch/powerpc/platforms/pseries/smp.c
+++ b/arch/powerpc/platforms/pseries/smp.c
@@ -144,8 +144,8 @@ static void __devinit smp_pSeries_kick_cpu(int nr)
                 hcpuid = get_hard_smp_processor_id(nr);
                 rc = plpar_hcall_norets(H_PROD, hcpuid);
                 if (rc != H_SUCCESS)
-                        printk(KERN_ERR "Error: Prod to wake up processor %d\
-                                                Ret= %ld\n", nr, rc);
+                        printk(KERN_ERR "Error: Prod to wake up processor %d "
+                                                "Ret= %ld\n", nr, rc);
         }
 }
 
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index f5f79196721c..4ca641042ec3 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -127,7 +127,7 @@ static inline unsigned int lpar_xirr_info_get(void)
 
         lpar_rc = plpar_xirr(&return_value);
         if (lpar_rc != H_SUCCESS)
-                panic(" bad return code xirr - rc = %lx \n", lpar_rc);
+                panic(" bad return code xirr - rc = %lx\n", lpar_rc);
         return (unsigned int)return_value;
 }
 
@@ -424,7 +424,7 @@ static int xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
 }
 
 static struct irq_chip xics_pic_direct = {
-        .name = " XICS     ",
+        .name = "XICS",
         .startup = xics_startup,
         .mask = xics_mask_irq,
         .unmask = xics_unmask_irq,
@@ -433,7 +433,7 @@ static struct irq_chip xics_pic_direct = {
 };
 
 static struct irq_chip xics_pic_lpar = {
-        .name = " XICS     ",
+        .name = "XICS",
         .startup = xics_startup,
         .mask = xics_mask_irq,
         .unmask = xics_unmask_irq,
@@ -510,15 +510,13 @@ static void __init xics_init_host(void)
 /*
  * XICS only has a single IPI, so encode the messages per CPU
  */
-struct xics_ipi_struct {
-        unsigned long value;
-        } ____cacheline_aligned;
-
-static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
+static DEFINE_PER_CPU_SHARED_ALIGNED(unsigned long, xics_ipi_message);
 
 static inline void smp_xics_do_message(int cpu, int msg)
 {
-        set_bit(msg, &xics_ipi_message[cpu].value);
+        unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
+
+        set_bit(msg, tgt);
         mb();
         if (firmware_has_feature(FW_FEATURE_LPAR))
                 lpar_qirr_info(cpu, IPI_PRIORITY);
@@ -544,25 +542,23 @@ void smp_xics_message_pass(int target, int msg)
 
 static irqreturn_t xics_ipi_dispatch(int cpu)
 {
+        unsigned long *tgt = &per_cpu(xics_ipi_message, cpu);
+
         WARN_ON(cpu_is_offline(cpu));
 
         mb();   /* order mmio clearing qirr */
-        while (xics_ipi_message[cpu].value) {
-                if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
-                                       &xics_ipi_message[cpu].value)) {
+        while (*tgt) {
+                if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION, tgt)) {
                         smp_message_recv(PPC_MSG_CALL_FUNCTION);
                 }
-                if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
-                                       &xics_ipi_message[cpu].value)) {
+                if (test_and_clear_bit(PPC_MSG_RESCHEDULE, tgt)) {
                         smp_message_recv(PPC_MSG_RESCHEDULE);
                 }
-                if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
-                                       &xics_ipi_message[cpu].value)) {
+                if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE, tgt)) {
                         smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
                 }
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
-                if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
-                                       &xics_ipi_message[cpu].value)) {
+                if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK, tgt)) {
                         smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
                 }
 #endif
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index a4b41dbde128..ecad10d4e928 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -77,7 +77,7 @@ static void cpm_end_irq(unsigned int irq)
 }
 
 static struct irq_chip cpm_pic = {
-        .name = " CPM PIC ",
+        .name = "CPM PIC",
         .mask = cpm_mask_irq,
         .unmask = cpm_unmask_irq,
         .eoi = cpm_end_irq,
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index 1709ac5aac7c..fcea4ff825dd 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -198,7 +198,7 @@ err_sense:
 }
 
 static struct irq_chip cpm2_pic = {
-        .name = " CPM2 SIU ",
+        .name = "CPM2 SIU",
         .mask = cpm2_mask_irq,
         .unmask = cpm2_unmask_irq,
         .ack = cpm2_ack,
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index c6e11b077108..e094367d7739 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -47,7 +47,7 @@ static struct irq_chip fsl_msi_chip = {
         .mask           = mask_msi_irq,
         .unmask         = unmask_msi_irq,
         .ack            = fsl_msi_end_irq,
-        .name   = " FSL-MSI  ",
+        .name           = "FSL-MSI",
 };
 
 static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
diff --git a/arch/powerpc/sysdev/grackle.c b/arch/powerpc/sysdev/grackle.c
index 5da37c2f22ee..cf27df6e508b 100644
--- a/arch/powerpc/sysdev/grackle.c
+++ b/arch/powerpc/sysdev/grackle.c
@@ -56,9 +56,9 @@ static inline void grackle_set_loop_snoop(struct pci_controller *bp, int enable)
 void __init setup_grackle(struct pci_controller *hose)
 {
         setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0);
-        if (machine_is_compatible("PowerMac1,1"))
+        if (of_machine_is_compatible("PowerMac1,1"))
                 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
-        if (machine_is_compatible("AAPL,PowerBook1998"))
+        if (of_machine_is_compatible("AAPL,PowerBook1998"))
                 grackle_set_loop_snoop(hose, 1);
 #if 0   /* Disabled for now, HW problems ??? */
         grackle_set_stg(hose, 1);
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index 0a55db8a5a29..6323e70e6bf4 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -23,7 +23,7 @@ static unsigned char cached_8259[2] = { 0xff, 0xff };
 #define cached_A1 (cached_8259[0])
 #define cached_21 (cached_8259[1])
 
-static DEFINE_SPINLOCK(i8259_lock);
+static DEFINE_RAW_SPINLOCK(i8259_lock);
 
 static struct irq_host *i8259_host;
 
@@ -42,7 +42,7 @@ unsigned int i8259_irq(void)
         if (pci_intack)
                 irq = readb(pci_intack);
         else {
-                spin_lock(&i8259_lock);
+                raw_spin_lock(&i8259_lock);
                 lock = 1;
 
                 /* Perform an interrupt acknowledge cycle on controller 1. */
@@ -74,7 +74,7 @@ unsigned int i8259_irq(void)
                 irq = NO_IRQ;
 
         if (lock)
-                spin_unlock(&i8259_lock);
+                raw_spin_unlock(&i8259_lock);
         return irq;
 }
 
@@ -82,7 +82,7 @@ static void i8259_mask_and_ack_irq(unsigned int irq_nr)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&i8259_lock, flags);
+        raw_spin_lock_irqsave(&i8259_lock, flags);
         if (irq_nr > 7) {
                 cached_A1 |= 1 << (irq_nr-8);
                 inb(0xA1);      /* DUMMY */
@@ -95,7 +95,7 @@ static void i8259_mask_and_ack_irq(unsigned int irq_nr)
                 outb(cached_21, 0x21);
                 outb(0x20, 0x20);       /* Non-specific EOI */
         }
-        spin_unlock_irqrestore(&i8259_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259_lock, flags);
 }
 
 static void i8259_set_irq_mask(int irq_nr)
@@ -110,13 +110,13 @@ static void i8259_mask_irq(unsigned int irq_nr)
 
         pr_debug("i8259_mask_irq(%d)\n", irq_nr);
 
-        spin_lock_irqsave(&i8259_lock, flags);
+        raw_spin_lock_irqsave(&i8259_lock, flags);
         if (irq_nr < 8)
                 cached_21 |= 1 << irq_nr;
         else
                 cached_A1 |= 1 << (irq_nr-8);
         i8259_set_irq_mask(irq_nr);
-        spin_unlock_irqrestore(&i8259_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259_lock, flags);
 }
 
 static void i8259_unmask_irq(unsigned int irq_nr)
@@ -125,17 +125,17 @@ static void i8259_unmask_irq(unsigned int irq_nr)
 
         pr_debug("i8259_unmask_irq(%d)\n", irq_nr);
 
-        spin_lock_irqsave(&i8259_lock, flags);
+        raw_spin_lock_irqsave(&i8259_lock, flags);
         if (irq_nr < 8)
                 cached_21 &= ~(1 << irq_nr);
         else
                 cached_A1 &= ~(1 << (irq_nr-8));
         i8259_set_irq_mask(irq_nr);
-        spin_unlock_irqrestore(&i8259_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259_lock, flags);
 }
 
 static struct irq_chip i8259_pic = {
-        .name           = " i8259    ",
+        .name           = "i8259",
         .mask           = i8259_mask_irq,
         .disable        = i8259_mask_irq,
         .unmask         = i8259_unmask_irq,
@@ -241,7 +241,7 @@ void i8259_init(struct device_node *node, unsigned long intack_addr)
         unsigned long flags;
 
         /* initialize the controller */
-        spin_lock_irqsave(&i8259_lock, flags);
+        raw_spin_lock_irqsave(&i8259_lock, flags);
 
         /* Mask all first */
         outb(0xff, 0xA1);
@@ -273,7 +273,7 @@ void i8259_init(struct device_node *node, unsigned long intack_addr)
         outb(cached_A1, 0xA1);
         outb(cached_21, 0x21);
 
-        spin_unlock_irqrestore(&i8259_lock, flags);
+        raw_spin_unlock_irqrestore(&i8259_lock, flags);
 
         /* create a legacy host */
         i8259_host = irq_alloc_host(node, IRQ_HOST_MAP_LEGACY,
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 28cdddd2f89e..d7b9b9c69287 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -32,7 +32,7 @@
 
 static struct ipic * primary_ipic;
 static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
-static DEFINE_SPINLOCK(ipic_lock);
+static DEFINE_RAW_SPINLOCK(ipic_lock);
 
 static struct ipic_info ipic_info[] = {
         [1] = {
@@ -530,13 +530,13 @@ static void ipic_unmask_irq(unsigned int virq)
         unsigned long flags;
         u32 temp;
 
-        spin_lock_irqsave(&ipic_lock, flags);
+        raw_spin_lock_irqsave(&ipic_lock, flags);
 
         temp = ipic_read(ipic->regs, ipic_info[src].mask);
         temp |= (1 << (31 - ipic_info[src].bit));
         ipic_write(ipic->regs, ipic_info[src].mask, temp);
 
-        spin_unlock_irqrestore(&ipic_lock, flags);
+        raw_spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
 static void ipic_mask_irq(unsigned int virq)
@@ -546,7 +546,7 @@ static void ipic_mask_irq(unsigned int virq)
         unsigned long flags;
         u32 temp;
 
-        spin_lock_irqsave(&ipic_lock, flags);
+        raw_spin_lock_irqsave(&ipic_lock, flags);
 
         temp = ipic_read(ipic->regs, ipic_info[src].mask);
         temp &= ~(1 << (31 - ipic_info[src].bit));
@@ -556,7 +556,7 @@ static void ipic_mask_irq(unsigned int virq)
          * for nearly all cases. */
         mb();
 
-        spin_unlock_irqrestore(&ipic_lock, flags);
+        raw_spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
 static void ipic_ack_irq(unsigned int virq)
@@ -566,7 +566,7 @@ static void ipic_ack_irq(unsigned int virq)
         unsigned long flags;
         u32 temp;
 
-        spin_lock_irqsave(&ipic_lock, flags);
+        raw_spin_lock_irqsave(&ipic_lock, flags);
 
         temp = 1 << (31 - ipic_info[src].bit);
         ipic_write(ipic->regs, ipic_info[src].ack, temp);
@@ -575,7 +575,7 @@ static void ipic_ack_irq(unsigned int virq)
          * for nearly all cases. */
         mb();
 
-        spin_unlock_irqrestore(&ipic_lock, flags);
+        raw_spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
 static void ipic_mask_irq_and_ack(unsigned int virq)
@@ -585,7 +585,7 @@ static void ipic_mask_irq_and_ack(unsigned int virq)
         unsigned long flags;
         u32 temp;
 
-        spin_lock_irqsave(&ipic_lock, flags);
+        raw_spin_lock_irqsave(&ipic_lock, flags);
 
         temp = ipic_read(ipic->regs, ipic_info[src].mask);
         temp &= ~(1 << (31 - ipic_info[src].bit));
@@ -598,7 +598,7 @@ static void ipic_mask_irq_and_ack(unsigned int virq)
          * for nearly all cases. */
         mb();
 
-        spin_unlock_irqrestore(&ipic_lock, flags);
+        raw_spin_unlock_irqrestore(&ipic_lock, flags);
 }
 
 static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
@@ -660,7 +660,7 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
 
 /* level interrupts and edge interrupts have different ack operations */
 static struct irq_chip ipic_level_irq_chip = {
-        .name           = " IPIC  ",
+        .name           = "IPIC",
         .unmask         = ipic_unmask_irq,
         .mask           = ipic_mask_irq,
         .mask_ack       = ipic_mask_irq,
@@ -668,7 +668,7 @@ static struct irq_chip ipic_level_irq_chip = {
 };
 
 static struct irq_chip ipic_edge_irq_chip = {
-        .name           = " IPIC  ",
+        .name           = "IPIC",
         .unmask         = ipic_unmask_irq,
         .mask           = ipic_mask_irq,
         .mask_ack       = ipic_mask_irq_and_ack,
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index 69bd6f4dff83..8c27d261aba8 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -94,7 +94,7 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip mpc8xx_pic = {
-        .name = " MPC8XX SIU ",
+        .name = "MPC8XX SIU",
         .unmask = mpc8xx_unmask_irq,
         .mask = mpc8xx_mask_irq,
         .ack = mpc8xx_ack,
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 470dc6c11d57..339e8a3e26d2 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -46,7 +46,7 @@
 
 static struct mpic *mpics;
 static struct mpic *mpic_primary;
-static DEFINE_SPINLOCK(mpic_lock);
+static DEFINE_RAW_SPINLOCK(mpic_lock);
 
 #ifdef CONFIG_PPC32     /* XXX for now */
 #ifdef CONFIG_IRQ_ALL_CPUS
@@ -347,10 +347,10 @@ static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
                 unsigned int mask = 1U << (fixup->index & 0x1f);
                 writel(mask, fixup->applebase + soff);
         } else {
-                spin_lock(&mpic->fixup_lock);
+                raw_spin_lock(&mpic->fixup_lock);
                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
                 writel(fixup->data, fixup->base + 4);
-                spin_unlock(&mpic->fixup_lock);
+                raw_spin_unlock(&mpic->fixup_lock);
         }
 }
 
@@ -366,7 +366,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 
         DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
             source, irqflags, fixup->index);
-        spin_lock_irqsave(&mpic->fixup_lock, flags);
+        raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
         /* Enable and configure */
         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
         tmp = readl(fixup->base + 4);
@@ -374,7 +374,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
         if (irqflags & IRQ_LEVEL)
                 tmp |= 0x22;
         writel(tmp, fixup->base + 4);
-        spin_unlock_irqrestore(&mpic->fixup_lock, flags);
+        raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 
 #ifdef CONFIG_PM
         /* use the lowest bit inverted to the actual HW,
@@ -396,12 +396,12 @@ static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
         DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
 
         /* Disable */
-        spin_lock_irqsave(&mpic->fixup_lock, flags);
+        raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
         tmp = readl(fixup->base + 4);
         tmp |= 1;
         writel(tmp, fixup->base + 4);
-        spin_unlock_irqrestore(&mpic->fixup_lock, flags);
+        raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
 
 #ifdef CONFIG_PM
         /* use the lowest bit inverted to the actual HW,
@@ -515,7 +515,7 @@ static void __init mpic_scan_ht_pics(struct mpic *mpic)
         BUG_ON(mpic->fixups == NULL);
 
         /* Init spinlock */
-        spin_lock_init(&mpic->fixup_lock);
+        raw_spin_lock_init(&mpic->fixup_lock);
 
         /* Map U3 config space. We assume all IO-APICs are on the primary bus
          * so we only need to map 64kB.
@@ -573,12 +573,12 @@ static int irq_choose_cpu(const cpumask_t *mask)
 
         if (cpumask_equal(mask, cpu_all_mask)) {
                 static int irq_rover;
-                static DEFINE_SPINLOCK(irq_rover_lock);
+                static DEFINE_RAW_SPINLOCK(irq_rover_lock);
                 unsigned long flags;
 
                 /* Round-robin distribution... */
         do_round_robin:
-                spin_lock_irqsave(&irq_rover_lock, flags);
+                raw_spin_lock_irqsave(&irq_rover_lock, flags);
 
                 while (!cpu_online(irq_rover)) {
                         if (++irq_rover >= NR_CPUS)
@@ -590,7 +590,7 @@ static int irq_choose_cpu(const cpumask_t *mask)
                                 irq_rover = 0;
                 } while (!cpu_online(irq_rover));
 
-                spin_unlock_irqrestore(&irq_rover_lock, flags);
+                raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
         } else {
                 cpuid = cpumask_first_and(mask, cpu_online_mask);
                 if (cpuid >= nr_cpu_ids)
@@ -1368,14 +1368,14 @@ void __init mpic_set_serial_int(struct mpic *mpic, int enable)
         unsigned long flags;
         u32 v;
 
-        spin_lock_irqsave(&mpic_lock, flags);
+        raw_spin_lock_irqsave(&mpic_lock, flags);
         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
         if (enable)
                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
         else
                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
-        spin_unlock_irqrestore(&mpic_lock, flags);
+        raw_spin_unlock_irqrestore(&mpic_lock, flags);
 }
 
 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
@@ -1388,7 +1388,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
         if (!mpic)
                 return;
 
-        spin_lock_irqsave(&mpic_lock, flags);
+        raw_spin_lock_irqsave(&mpic_lock, flags);
         if (mpic_is_ipi(mpic, irq)) {
                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
                         ~MPIC_VECPRI_PRIORITY_MASK;
@@ -1400,7 +1400,7 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
         }
-        spin_unlock_irqrestore(&mpic_lock, flags);
+        raw_spin_unlock_irqrestore(&mpic_lock, flags);
 }
 
 void mpic_setup_this_cpu(void)
@@ -1415,7 +1415,7 @@ void mpic_setup_this_cpu(void)
 
         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
 
-        spin_lock_irqsave(&mpic_lock, flags);
+        raw_spin_lock_irqsave(&mpic_lock, flags);
 
         /* let the mpic know we want intrs. default affinity is 0xffffffff
          * until changed via /proc. That's how it's done on x86. If we want
@@ -1431,7 +1431,7 @@ void mpic_setup_this_cpu(void)
         /* Set current processor priority to 0 */
         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
 
-        spin_unlock_irqrestore(&mpic_lock, flags);
+        raw_spin_unlock_irqrestore(&mpic_lock, flags);
 #endif /* CONFIG_SMP */
 }
 
@@ -1460,7 +1460,7 @@ void mpic_teardown_this_cpu(int secondary)
         BUG_ON(mpic == NULL);
 
         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
-        spin_lock_irqsave(&mpic_lock, flags);
+        raw_spin_lock_irqsave(&mpic_lock, flags);
 
         /* let the mpic know we don't want intrs.  */
         for (i = 0; i < mpic->num_sources ; i++)
@@ -1474,7 +1474,7 @@ void mpic_teardown_this_cpu(int secondary)
          */
         mpic_eoi(mpic);
 
-        spin_unlock_irqrestore(&mpic_lock, flags);
+        raw_spin_unlock_irqrestore(&mpic_lock, flags);
 }
 
 
@@ -1575,7 +1575,7 @@ void mpic_request_ipis(void)
         int i;
         BUG_ON(mpic == NULL);
 
-        printk(KERN_INFO "mpic: requesting IPIs ... \n");
+        printk(KERN_INFO "mpic: requesting IPIs...\n");
 
         for (i = 0; i < 4; i++) {
                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 0f6ab06f8474..3b6a9a43718f 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -60,7 +60,7 @@ static struct irq_chip mpic_pasemi_msi_chip = {
         .eoi            = mpic_end_irq,
         .set_type       = mpic_set_irq_type,
         .set_affinity   = mpic_set_affinity,
-        .name           = "PASEMI-MSI ",
+        .name           = "PASEMI-MSI",
 };
 
 static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index b6bd775d2e22..31acd3b1718b 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -16,6 +16,7 @@
 #include <linux/mv643xx.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
+#include <linux/dma-mapping.h>
 
 #include <asm/prom.h>
 
@@ -189,6 +190,7 @@ static int __init mv64x60_mpsc_device_setup(struct device_node *np, int id)
         pdev = platform_device_alloc(MPSC_CTLR_NAME, port_number);
         if (!pdev)
                 return -ENOMEM;
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
 
         err = platform_device_add_resources(pdev, r, 5);
         if (err)
@@ -302,6 +304,7 @@ static int __init mv64x60_eth_device_setup(struct device_node *np, int id,
         if (!pdev)
                 return -ENOMEM;
 
+        pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
         err = platform_device_add_resources(pdev, r, 1);
         if (err)
                 goto error;
diff --git a/arch/powerpc/sysdev/ppc4xx_soc.c b/arch/powerpc/sysdev/ppc4xx_soc.c
index 5b32adc9a9b2..5c014350bf16 100644
--- a/arch/powerpc/sysdev/ppc4xx_soc.c
+++ b/arch/powerpc/sysdev/ppc4xx_soc.c
@@ -174,7 +174,8 @@ static int __init ppc4xx_l2c_probe(void)
                 | L2C_CFG_CPIM | L2C_CFG_TPIM | L2C_CFG_LIM | L2C_CFG_SMCM;
 
         /* Check for 460EX/GT special handling */
-        if (of_device_is_compatible(np, "ibm,l2-cache-460ex"))
+        if (of_device_is_compatible(np, "ibm,l2-cache-460ex") ||
+            of_device_is_compatible(np, "ibm,l2-cache-460gt"))
                 r |= L2C_CFG_RDBW;
 
         mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r);
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 2acc928d1920..d927da893ec4 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -237,7 +237,7 @@ static void qe_ic_mask_irq(unsigned int virq)
 }
 
 static struct irq_chip qe_ic_irq_chip = {
-        .name = " QEIC  ",
+        .name = "QEIC",
         .unmask = qe_ic_unmask_irq,
         .mask = qe_ic_mask_irq,
         .mask_ack = qe_ic_mask_irq,
@@ -256,7 +256,7 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
         struct irq_chip *chip;
 
         if (qe_ic_info[hw].mask == 0) {
-                printk(KERN_ERR "Can't map reserved IRQ \n");
+                printk(KERN_ERR "Can't map reserved IRQ\n");
                 return -EINVAL;
         }
         /* Default chip */
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index 7c87460179ef..77e4934b88c5 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -157,13 +157,13 @@ int par_io_of_config(struct device_node *np)
         const unsigned int *pio_map;
 
         if (par_io == NULL) {
-                printk(KERN_ERR "par_io not initialized \n");
+                printk(KERN_ERR "par_io not initialized\n");
                 return -1;
         }
 
         ph = of_get_property(np, "pio-handle", NULL);
         if (ph == NULL) {
-                printk(KERN_ERR "pio-handle not available \n");
+                printk(KERN_ERR "pio-handle not available\n");
                 return -1;
         }
 
@@ -171,12 +171,12 @@ int par_io_of_config(struct device_node *np)
 
         pio_map = of_get_property(pio, "pio-map", &pio_map_len);
         if (pio_map == NULL) {
-                printk(KERN_ERR "pio-map is not set! \n");
+                printk(KERN_ERR "pio-map is not set!\n");
                 return -1;
         }
         pio_map_len /= sizeof(unsigned int);
         if ((pio_map_len % 6) != 0) {
-                printk(KERN_ERR "pio-map format wrong! \n");
+                printk(KERN_ERR "pio-map format wrong!\n");
                 return -1;
         }
 
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 6f220a913e42..0038fb78f094 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -177,7 +177,7 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
 }
 
 static struct irq_chip uic_irq_chip = {
-        .name           = " UIC  ",
+        .name           = "UIC",
         .unmask         = uic_unmask_irq,
         .mask           = uic_mask_irq,
         .mask_ack       = uic_mask_ack_irq,
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 4e6152c13764..8bad7d5f32af 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -61,7 +61,7 @@ static int xmon_owner;
 static int xmon_gate;
 #endif /* CONFIG_SMP */
 
-static unsigned long in_xmon = 0;
+static unsigned long in_xmon __read_mostly = 0;
 
 static unsigned long adrs;
 static int size = 1;
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index c80235206c01..0d8cd9bbe101 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -54,6 +54,9 @@ config GENERIC_BUG
         depends on BUG
         default y
 
+config GENERIC_BUG_RELATIVE_POINTERS
+        def_bool y
+
 config NO_IOMEM
         def_bool y
 
@@ -87,6 +90,7 @@ config S390
         select HAVE_SYSCALL_TRACEPOINTS
         select HAVE_DYNAMIC_FTRACE
         select HAVE_FUNCTION_GRAPH_TRACER
+        select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_DEFAULT_NO_SPIN_MUTEXES
         select HAVE_OPROFILE
         select HAVE_KPROBES
@@ -95,6 +99,9 @@ config S390
         select HAVE_ARCH_TRACEHOOK
         select INIT_ALL_POSSIBLE
         select HAVE_PERF_EVENTS
+        select HAVE_KERNEL_GZIP
+        select HAVE_KERNEL_BZIP2
+        select HAVE_KERNEL_LZMA
         select ARCH_INLINE_SPIN_TRYLOCK
         select ARCH_INLINE_SPIN_TRYLOCK_BH
         select ARCH_INLINE_SPIN_LOCK
diff --git a/arch/s390/Kconfig.debug b/arch/s390/Kconfig.debug
index 2283933a9a93..45e0c6199f36 100644
--- a/arch/s390/Kconfig.debug
+++ b/arch/s390/Kconfig.debug
@@ -6,4 +6,17 @@ config TRACE_IRQFLAGS_SUPPORT
 
 source "lib/Kconfig.debug"
 
+config DEBUG_STRICT_USER_COPY_CHECKS
+        bool "Strict user copy size checks"
+        ---help---
+          Enabling this option turns a certain set of sanity checks for user
+          copy operations into compile time warnings.
+
+          The copy_from_user() etc checks are there to help test if there
+          are sufficient security checks on the length argument of
+          the copy operation, by having gcc prove that the argument is
+          within bounds.
+
+          If unsure, or if you run an older (pre 4.4) gcc, say N.
+
 endmenu
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index fc8fb20e7fc0..0da10746e0e5 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -14,6 +14,7 @@
 #
 
 ifndef CONFIG_64BIT
+LD_BFD          := elf32-s390
 LDFLAGS         := -m elf_s390
 KBUILD_CFLAGS   += -m31
 KBUILD_AFLAGS   += -m31
@@ -21,6 +22,7 @@ UTS_MACHINE	:= s390
 STACK_SIZE      := 8192
 CHECKFLAGS      += -D__s390__ -msize-long
 else
+LD_BFD          := elf64-s390
 LDFLAGS         := -m elf64_s390
 MODFLAGS        += -fpic -D__PIC__
 KBUILD_CFLAGS   += -m64
@@ -30,6 +32,8 @@ STACK_SIZE	:= 16384
 CHECKFLAGS      += -D__s390__ -D__s390x__
 endif
 
+export LD_BFD
+
 cflags-$(CONFIG_MARCH_G5)   += $(call cc-option,-march=g5)
 cflags-$(CONFIG_MARCH_Z900) += $(call cc-option,-march=z900)
 cflags-$(CONFIG_MARCH_Z990) += $(call cc-option,-march=z990)
@@ -85,7 +89,9 @@ KBUILD_AFLAGS	+= $(aflags-y)
 OBJCOPYFLAGS    := -O binary
 LDFLAGS_vmlinux := -e start
 
-head-y          := arch/s390/kernel/head.o arch/s390/kernel/init_task.o
+head-y          := arch/s390/kernel/head.o
+head-y          += arch/s390/kernel/$(if $(CONFIG_64BIT),head64.o,head31.o)
+head-y          += arch/s390/kernel/init_task.o
 
 core-y          += arch/s390/mm/ arch/s390/kernel/ arch/s390/crypto/ \
                    arch/s390/appldata/ arch/s390/hypfs/ arch/s390/kvm/
@@ -99,12 +105,12 @@ drivers-$(CONFIG_OPROFILE)	+= arch/s390/oprofile/
 
 boot            := arch/s390/boot
 
-all: image
+all: image bzImage
 
 install: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) $@
 
-image: vmlinux
+image bzImage: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
 
 zfcpdump:
@@ -116,4 +122,5 @@ archclean:
 # Don't use tabs in echo arguments
 define archhelp
   echo  '* image           - Kernel image for IPL ($(boot)/image)'
+  echo  '* bzImage         - Compressed kernel image for IPL ($(boot)/bzImage)'
 endef
diff --git a/arch/s390/boot/Makefile b/arch/s390/boot/Makefile
index 4d97eef36b8d..8800cf090694 100644
--- a/arch/s390/boot/Makefile
+++ b/arch/s390/boot/Makefile
@@ -9,10 +9,18 @@ COMPILE_VERSION := __linux_compile_version_id__`hostname |  \
 EXTRA_CFLAGS  := -DCOMPILE_VERSION=$(COMPILE_VERSION) -gstabs -I.
 
 targets := image
+targets += bzImage
+subdir- := compressed
 
 $(obj)/image: vmlinux FORCE
         $(call if_changed,objcopy)
 
+$(obj)/bzImage: $(obj)/compressed/vmlinux FORCE
+        $(call if_changed,objcopy)
+
+$(obj)/compressed/vmlinux: FORCE
+        $(Q)$(MAKE) $(build)=$(obj)/compressed $@
+
 install: $(CONFIGURE) $(obj)/image
         sh -x  $(srctree)/$(obj)/install.sh $(KERNELRELEASE) $(obj)/image \
               System.map Kerntypes "$(INSTALL_PATH)"
diff --git a/arch/s390/boot/compressed/Makefile b/arch/s390/boot/compressed/Makefile
new file mode 100644
index 000000000000..6e4a67ad07e1
--- /dev/null
+++ b/arch/s390/boot/compressed/Makefile
@@ -0,0 +1,60 @@
+#
+# linux/arch/s390/boot/compressed/Makefile
+#
+# create a compressed vmlinux image from the original vmlinux
+#
+
+BITS := $(if $(CONFIG_64BIT),64,31)
+
+targets := vmlinux.lds vmlinux vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 \
+           vmlinux.bin.lzma misc.o piggy.o sizes.h head$(BITS).o
+
+KBUILD_CFLAGS := -m$(BITS) -D__KERNEL__ $(LINUX_INCLUDE) -O2
+KBUILD_CFLAGS += $(cflags-y)
+KBUILD_CFLAGS += $(call cc-option,-mpacked-stack)
+KBUILD_CFLAGS += $(call cc-option,-ffreestanding)
+
+GCOV_PROFILE := n
+
+OBJECTS := $(addprefix $(objtree)/arch/s390/kernel/, head.o sclp.o ebcdic.o)
+OBJECTS += $(obj)/head$(BITS).o $(obj)/misc.o $(obj)/piggy.o
+
+LDFLAGS_vmlinux := --oformat $(LD_BFD) -e startup -T
+$(obj)/vmlinux: $(obj)/vmlinux.lds $(OBJECTS)
+        $(call if_changed,ld)
+        @:
+
+sed-sizes := -e 's/^\([0-9a-fA-F]*\) . \(__bss_start\|_end\)$$/\#define SZ\2 0x\1/p'
+
+quiet_cmd_sizes = GEN $@
+      cmd_sizes = $(NM) $< | sed -n $(sed-sizes) > $@
+
+$(obj)/sizes.h: vmlinux
+        $(call if_changed,sizes)
+
+AFLAGS_head$(BITS).o += -I$(obj)
+$(obj)/head$(BITS).o: $(obj)/sizes.h
+
+CFLAGS_misc.o += -I$(obj)
+$(obj)/misc.o: $(obj)/sizes.h
+
+OBJCOPYFLAGS_vmlinux.bin :=  -R .comment -S
+$(obj)/vmlinux.bin: vmlinux
+        $(call if_changed,objcopy)
+
+vmlinux.bin.all-y := $(obj)/vmlinux.bin
+
+suffix-$(CONFIG_KERNEL_GZIP)  := gz
+suffix-$(CONFIG_KERNEL_BZIP2) := bz2
+suffix-$(CONFIG_KERNEL_LZMA)  := lzma
+
+$(obj)/vmlinux.bin.gz: $(vmlinux.bin.all-y)
+        $(call if_changed,gzip)
+$(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y)
+        $(call if_changed,bzip2)
+$(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y)
+        $(call if_changed,lzma)
+
+LDFLAGS_piggy.o := -r --format binary --oformat $(LD_BFD) -T
+$(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y)
+        $(call if_changed,ld)
diff --git a/arch/s390/boot/compressed/head31.S b/arch/s390/boot/compressed/head31.S
new file mode 100644
index 000000000000..2a5523a32bcc
--- /dev/null
+++ b/arch/s390/boot/compressed/head31.S
@@ -0,0 +1,51 @@
+/*
+ * Startup glue code to uncompress the kernel
+ *
+ * Copyright IBM Corp. 2010
+ *
+ *   Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
+#include "sizes.h"
+
+__HEAD
+        .globl  startup_continue
+startup_continue:
+        basr    %r13,0                  # get base
+.LPG1:
+        # setup stack
+        l       %r15,.Lstack-.LPG1(%r13)
+        ahi     %r15,-96
+        l       %r1,.Ldecompress-.LPG1(%r13)
+        basr    %r14,%r1
+        # setup registers for memory mover & branch to target
+        lr      %r4,%r2
+        l       %r2,.Loffset-.LPG1(%r13)
+        la      %r4,0(%r2,%r4)
+        l       %r3,.Lmvsize-.LPG1(%r13)
+        lr      %r5,%r3
+        # move the memory mover someplace safe
+        la      %r1,0x200
+        mvc     0(mover_end-mover,%r1),mover-.LPG1(%r13)
+        # decompress image is started at 0x11000
+        lr      %r6,%r2
+        br      %r1
+mover:
+        mvcle   %r2,%r4,0
+        jo      mover
+        br      %r6
+mover_end:
+
+        .align  8
+.Lstack:
+        .long   0x8000 + (1<<(PAGE_SHIFT+THREAD_ORDER))
+.Ldecompress:
+        .long   decompress_kernel
+.Loffset:
+        .long   0x11000
+.Lmvsize:
+        .long   SZ__bss_start
diff --git a/arch/s390/boot/compressed/head64.S b/arch/s390/boot/compressed/head64.S
new file mode 100644
index 000000000000..2982cb140550
--- /dev/null
+++ b/arch/s390/boot/compressed/head64.S
@@ -0,0 +1,48 @@
+/*
+ * Startup glue code to uncompress the kernel
+ *
+ * Copyright IBM Corp. 2010
+ *
+ *   Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
+#include "sizes.h"
+
+__HEAD
+        .globl  startup_continue
+startup_continue:
+        basr    %r13,0                  # get base
+.LPG1:
+        # setup stack
+        lg      %r15,.Lstack-.LPG1(%r13)
+        aghi    %r15,-160
+        brasl   %r14,decompress_kernel
+        # setup registers for memory mover & branch to target
+        lgr     %r4,%r2
+        lg      %r2,.Loffset-.LPG1(%r13)
+        la      %r4,0(%r2,%r4)
+        lg      %r3,.Lmvsize-.LPG1(%r13)
+        lgr     %r5,%r3
+        # move the memory mover someplace safe
+        la      %r1,0x200
+        mvc     0(mover_end-mover,%r1),mover-.LPG1(%r13)
+        # decompress image is started at 0x11000
+        lgr     %r6,%r2
+        br      %r1
+mover:
+        mvcle   %r2,%r4,0
+        jo      mover
+        br      %r6
+mover_end:
+
+        .align  8
+.Lstack:
+        .quad   0x8000 + (1<<(PAGE_SHIFT+THREAD_ORDER))
+.Loffset:
+        .quad   0x11000
+.Lmvsize:
+        .quad   SZ__bss_start
diff --git a/arch/s390/boot/compressed/misc.c b/arch/s390/boot/compressed/misc.c
new file mode 100644
index 000000000000..a97d69525829
--- /dev/null
+++ b/arch/s390/boot/compressed/misc.c
@@ -0,0 +1,158 @@
+/*
+ * Definitions and wrapper functions for kernel decompressor
+ *
+ * Copyright IBM Corp. 2010
+ *
+ * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#include <asm/uaccess.h>
+#include <asm/page.h>
+#include <asm/ipl.h>
+#include "sizes.h"
+
+/*
+ * gzip declarations
+ */
+#define STATIC static
+
+#undef memset
+#undef memcpy
+#undef memmove
+#define memzero(s, n) memset((s), 0, (n))
+
+/* Symbols defined by linker scripts */
+extern char input_data[];
+extern int input_len;
+extern int _text;
+extern int _end;
+
+static void error(char *m);
+
+static unsigned long free_mem_ptr;
+static unsigned long free_mem_end_ptr;
+
+#ifdef CONFIG_HAVE_KERNEL_BZIP2
+#define HEAP_SIZE       0x400000
+#else
+#define HEAP_SIZE       0x10000
+#endif
+
+#ifdef CONFIG_KERNEL_GZIP
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_BZIP2
+#include "../../../../lib/decompress_bunzip2.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZMA
+#include "../../../../lib/decompress_unlzma.c"
+#endif
+
+extern _sclp_print_early(const char *);
+
+int puts(const char *s)
+{
+        _sclp_print_early(s);
+        return 0;
+}
+
+void *memset(void *s, int c, size_t n)
+{
+        char *xs;
+
+        if (c == 0)
+                return __builtin_memset(s, 0, n);
+
+        xs = (char *) s;
+        if (n > 0)
+                do {
+                        *xs++ = c;
+                } while (--n > 0);
+        return s;
+}
+
+void *memcpy(void *__dest, __const void *__src, size_t __n)
+{
+        return __builtin_memcpy(__dest, __src, __n);
+}
+
+void *memmove(void *__dest, __const void *__src, size_t __n)
+{
+        char *d;
+        const char *s;
+
+        if (__dest <= __src)
+                return __builtin_memcpy(__dest, __src, __n);
+        d = __dest + __n;
+        s = __src + __n;
+        while (__n--)
+                *--d = *--s;
+        return __dest;
+}
+
+static void error(char *x)
+{
+        unsigned long long psw = 0x000a0000deadbeefULL;
+
+        puts("\n\n");
+        puts(x);
+        puts("\n\n -- System halted");
+
+        asm volatile("lpsw %0" : : "Q" (psw));
+}
+
+/*
+ * Safe guard the ipl parameter block against a memory area that will be
+ * overwritten. The validity check for the ipl parameter block is complex
+ * (see cio_get_iplinfo and ipl_save_parameters) but if the pointer to
+ * the ipl parameter block intersects with the passed memory area we can
+ * safely assume that we can read from that memory. In that case just copy
+ * the memory to IPL_PARMBLOCK_ORIGIN even if there is no ipl parameter
+ * block.
+ */
+static void check_ipl_parmblock(void *start, unsigned long size)
+{
+        void *src, *dst;
+
+        src = (void *)(unsigned long) S390_lowcore.ipl_parmblock_ptr;
+        if (src + PAGE_SIZE <= start || src >= start + size)
+                return;
+        dst = (void *) IPL_PARMBLOCK_ORIGIN;
+        memmove(dst, src, PAGE_SIZE);
+        S390_lowcore.ipl_parmblock_ptr = IPL_PARMBLOCK_ORIGIN;
+}
+
+unsigned long decompress_kernel(void)
+{
+        unsigned long output_addr;
+        unsigned char *output;
+
+        free_mem_ptr = (unsigned long)&_end;
+        free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
+        output = (unsigned char *) ((free_mem_end_ptr + 4095UL) & -4096UL);
+
+        check_ipl_parmblock((void *) 0, (unsigned long) output + SZ__bss_start);
+
+#ifdef CONFIG_BLK_DEV_INITRD
+        /*
+         * Move the initrd right behind the end of the decompressed
+         * kernel image.
+         */
+        if (INITRD_START && INITRD_SIZE &&
+            INITRD_START < (unsigned long) output + SZ__bss_start) {
+                check_ipl_parmblock(output + SZ__bss_start,
+                                    INITRD_START + INITRD_SIZE);
+                memmove(output + SZ__bss_start,
+                        (void *) INITRD_START, INITRD_SIZE);
+                INITRD_START = (unsigned long) output + SZ__bss_start;
+        }
+#endif
+
+        puts("Uncompressing Linux... ");
+        decompress(input_data, input_len, NULL, NULL, output, NULL, error);
+        puts("Ok, booting the kernel.\n");
+        return (unsigned long) output;
+}
+
diff --git a/arch/s390/boot/compressed/vmlinux.lds.S b/arch/s390/boot/compressed/vmlinux.lds.S
new file mode 100644
index 000000000000..d80f79d8dd9c
--- /dev/null
+++ b/arch/s390/boot/compressed/vmlinux.lds.S
@@ -0,0 +1,55 @@
+#include <asm-generic/vmlinux.lds.h>
+
+#ifdef CONFIG_64BIT
+OUTPUT_FORMAT("elf64-s390", "elf64-s390", "elf64-s390")
+OUTPUT_ARCH(s390:64-bit)
+#else
+OUTPUT_FORMAT("elf32-s390", "elf32-s390", "elf32-s390")
+OUTPUT_ARCH(s390)
+#endif
+
+ENTRY(startup)
+
+SECTIONS
+{
+        /* Be careful parts of head_64.S assume startup_32 is at
+         * address 0.
+         */
+        . = 0;
+        .head.text : {
+                _head = . ;
+                HEAD_TEXT
+                _ehead = . ;
+        }
+        .rodata.compressed : {
+                *(.rodata.compressed)
+        }
+        .text : {
+                _text = .;      /* Text */
+                *(.text)
+                *(.text.*)
+                _etext = . ;
+        }
+        .rodata : {
+                _rodata = . ;
+                *(.rodata)       /* read-only data */
+                *(.rodata.*)
+                _erodata = . ;
+        }
+        .data : {
+                _data = . ;
+                *(.data)
+                *(.data.*)
+                _edata = . ;
+        }
+        . = ALIGN(256);
+        .bss : {
+                _bss = . ;
+                *(.bss)
+                *(.bss.*)
+                *(COMMON)
+                . = ALIGN(8);   /* For convenience during zeroing */
+                _ebss = .;
+        }
+        _end = .;
+}
diff --git a/arch/s390/boot/compressed/vmlinux.scr b/arch/s390/boot/compressed/vmlinux.scr
new file mode 100644
index 000000000000..f02382ae5c48
--- /dev/null
+++ b/arch/s390/boot/compressed/vmlinux.scr
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .rodata.compressed : {
+        input_len = .;
+        LONG(input_data_end - input_data) input_data = .;
+        *(.data)
+        output_len = . - 4;
+        input_data_end = .;
+        }
+}
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index 6be4503201ac..58f46734465f 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -78,14 +78,14 @@ static int setkey_fallback_cip(struct crypto_tfm *tfm, const u8 *in_key,
         struct s390_aes_ctx *sctx = crypto_tfm_ctx(tfm);
         int ret;
 
-        sctx->fallback.blk->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
-        sctx->fallback.blk->base.crt_flags |= (tfm->crt_flags &
+        sctx->fallback.cip->base.crt_flags &= ~CRYPTO_TFM_REQ_MASK;
+        sctx->fallback.cip->base.crt_flags |= (tfm->crt_flags &
                         CRYPTO_TFM_REQ_MASK);
 
         ret = crypto_cipher_setkey(sctx->fallback.cip, in_key, key_len);
         if (ret) {
                 tfm->crt_flags &= ~CRYPTO_TFM_RES_MASK;
-                tfm->crt_flags |= (sctx->fallback.blk->base.crt_flags &
+                tfm->crt_flags |= (sctx->fallback.cip->base.crt_flags &
                                 CRYPTO_TFM_RES_MASK);
         }
         return ret;
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index b416aa11b91e..7ae71cc56973 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -36,6 +36,13 @@ CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
diff --git a/arch/s390/hypfs/hypfs_diag.c b/arch/s390/hypfs/hypfs_diag.c
index 2b92d501425f..87cf523192e9 100644
--- a/arch/s390/hypfs/hypfs_diag.c
+++ b/arch/s390/hypfs/hypfs_diag.c
@@ -488,7 +488,7 @@ out:
 
 static int diag224(void *ptr)
 {
-        int rc = -ENOTSUPP;
+        int rc = -EOPNOTSUPP;
 
         asm volatile(
                 "       diag    %1,%2,0x224\n"
@@ -507,7 +507,7 @@ static int diag224_get_name_table(void)
                 return -ENOMEM;
         if (diag224(diag224_cpu_names)) {
                 kfree(diag224_cpu_names);
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
         }
         EBCASC(diag224_cpu_names + 16, (*diag224_cpu_names + 1) * 16);
         return 0;
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
index 2a113d6a7dfd..451bfbb9db3d 100644
--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -18,8 +18,6 @@
 
 #define ATOMIC_INIT(i)  { (i) }
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-
 #define __CS_LOOP(ptr, op_val, op_string) ({                            \
         int old_val, new_val;                                           \
         asm volatile(                                                   \
@@ -35,26 +33,6 @@
         new_val;                                                        \
 })
 
-#else /* __GNUC__ */
-
-#define __CS_LOOP(ptr, op_val, op_string) ({                            \
-        int old_val, new_val;                                           \
-        asm volatile(                                                   \
-                "       l       %0,0(%3)\n"                             \
-                "0:     lr      %1,%0\n"                                \
-                op_string "     %1,%4\n"                                \
-                "       cs      %0,%1,0(%3)\n"                          \
-                "       jl      0b"                                     \
-                : "=&d" (old_val), "=&d" (new_val),                     \
-                  "=m" (((atomic_t *)(ptr))->counter)                   \
-                : "a" (ptr), "d" (op_val),                              \
-                  "m" (((atomic_t *)(ptr))->counter)                    \
-                : "cc", "memory");                                      \
-        new_val;                                                        \
-})
-
-#endif /* __GNUC__ */
-
 static inline int atomic_read(const atomic_t *v)
 {
         barrier();
@@ -101,19 +79,11 @@ static inline void atomic_set_mask(unsigned long mask, atomic_t *v)
 
 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
 {
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
         asm volatile(
                 "       cs      %0,%2,%1"
                 : "+d" (old), "=Q" (v->counter)
                 : "d" (new), "Q" (v->counter)
                 : "cc", "memory");
-#else /* __GNUC__ */
-        asm volatile(
-                "       cs      %0,%3,0(%2)"
-                : "+d" (old), "=m" (v->counter)
-                : "a" (v), "d" (new), "m" (v->counter)
-                : "cc", "memory");
-#endif /* __GNUC__ */
         return old;
 }
 
@@ -140,8 +110,6 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 
 #ifdef CONFIG_64BIT
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-
 #define __CSG_LOOP(ptr, op_val, op_string) ({                           \
         long long old_val, new_val;                                     \
         asm volatile(                                                   \
@@ -157,26 +125,6 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
         new_val;                                                        \
 })
 
-#else /* __GNUC__ */
-
-#define __CSG_LOOP(ptr, op_val, op_string) ({                           \
-        long long old_val, new_val;                                     \
-        asm volatile(                                                   \
-                "       lg      %0,0(%3)\n"                             \
-                "0:     lgr     %1,%0\n"                                \
-                op_string "     %1,%4\n"                                \
-                "       csg     %0,%1,0(%3)\n"                          \
-                "       jl      0b"                                     \
-                : "=&d" (old_val), "=&d" (new_val),                     \
-                  "=m" (((atomic_t *)(ptr))->counter)                   \
-                : "a" (ptr), "d" (op_val),                              \
-                  "m" (((atomic_t *)(ptr))->counter)                    \
-                : "cc", "memory");                                      \
-        new_val;                                                        \
-})
-
-#endif /* __GNUC__ */
-
 static inline long long atomic64_read(const atomic64_t *v)
 {
         barrier();
@@ -214,19 +162,11 @@ static inline void atomic64_set_mask(unsigned long mask, atomic64_t *v)
 static inline long long atomic64_cmpxchg(atomic64_t *v,
                                              long long old, long long new)
 {
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
         asm volatile(
                 "       csg     %0,%2,%1"
                 : "+d" (old), "=Q" (v->counter)
                 : "d" (new), "Q" (v->counter)
                 : "cc", "memory");
-#else /* __GNUC__ */
-        asm volatile(
-                "       csg     %0,%3,0(%2)"
-                : "+d" (old), "=m" (v->counter)
-                : "a" (v), "d" (new), "m" (v->counter)
-                : "cc", "memory");
-#endif /* __GNUC__ */
         return old;
 }
 
@@ -243,10 +183,8 @@ static inline long long atomic64_read(const atomic64_t *v)
         register_pair rp;
 
         asm volatile(
-                "       lm      %0,%N0,0(%1)"
-                : "=&d" (rp)
-                : "a" (&v->counter), "m" (v->counter)
-                );
+                "       lm      %0,%N0,%1"
+                : "=&d" (rp) : "Q" (v->counter) );
         return rp.pair;
 }
 
@@ -255,10 +193,8 @@ static inline void atomic64_set(atomic64_t *v, long long i)
         register_pair rp = {.pair = i};
 
         asm volatile(
-                "       stm     %1,%N1,0(%2)"
-                : "=m" (v->counter)
-                : "d" (rp), "a" (&v->counter)
-                );
+                "       stm     %1,%N1,%0"
+                : "=Q" (v->counter) : "d" (rp) );
 }
 
 static inline long long atomic64_xchg(atomic64_t *v, long long new)
@@ -267,11 +203,11 @@ static inline long long atomic64_xchg(atomic64_t *v, long long new)
         register_pair rp_old;
 
         asm volatile(
-                "       lm      %0,%N0,0(%2)\n"
-                "0:     cds     %0,%3,0(%2)\n"
+                "       lm      %0,%N0,%1\n"
+                "0:     cds     %0,%2,%1\n"
                 "       jl      0b\n"
-                : "=&d" (rp_old), "+m" (v->counter)
-                : "a" (&v->counter), "d" (rp_new)
+                : "=&d" (rp_old), "=Q" (v->counter)
+                : "d" (rp_new), "Q" (v->counter)
                 : "cc");
         return rp_old.pair;
 }
@@ -283,9 +219,9 @@ static inline long long atomic64_cmpxchg(atomic64_t *v,
         register_pair rp_new = {.pair = new};
 
         asm volatile(
-                "       cds     %0,%3,0(%2)"
-                : "+&d" (rp_old), "+m" (v->counter)
-                : "a" (&v->counter), "d" (rp_new)
+                "       cds     %0,%2,%1"
+                : "+&d" (rp_old), "=Q" (v->counter)
+                : "d" (rp_new), "Q" (v->counter)
                 : "cc");
         return rp_old.pair;
 }
diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h
index b30606f6d523..2e05972c5085 100644
--- a/arch/s390/include/asm/bitops.h
+++ b/arch/s390/include/asm/bitops.h
@@ -71,8 +71,6 @@ extern const char _sb_findmap[];
 #define __BITOPS_AND            "nr"
 #define __BITOPS_XOR            "xr"
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-
 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
         asm volatile(                                           \
                 "       l       %0,%2\n"                        \
@@ -85,22 +83,6 @@ extern const char _sb_findmap[];
                 : "d" (__val), "Q" (*(unsigned long *) __addr)  \
                 : "cc");
 
-#else /* __GNUC__ */
-
-#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
-        asm volatile(                                           \
-                "       l       %0,0(%4)\n"                     \
-                "0:     lr      %1,%0\n"                        \
-                __op_string "   %1,%3\n"                        \
-                "       cs      %0,%1,0(%4)\n"                  \
-                "       jl      0b"                             \
-                : "=&d" (__old), "=&d" (__new),                 \
-                  "=m" (*(unsigned long *) __addr)              \
-                : "d" (__val), "a" (__addr),                    \
-                  "m" (*(unsigned long *) __addr) : "cc");
-
-#endif /* __GNUC__ */
-
 #else /* __s390x__ */
 
 #define __BITOPS_ALIGN          7
@@ -109,8 +91,6 @@ extern const char _sb_findmap[];
 #define __BITOPS_AND            "ngr"
 #define __BITOPS_XOR            "xgr"
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-
 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
         asm volatile(                                           \
                 "       lg      %0,%2\n"                        \
@@ -123,23 +103,6 @@ extern const char _sb_findmap[];
                 : "d" (__val), "Q" (*(unsigned long *) __addr)  \
                 : "cc");
 
-#else /* __GNUC__ */
-
-#define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
-        asm volatile(                                           \
-                "       lg      %0,0(%4)\n"                     \
-                "0:     lgr     %1,%0\n"                        \
-                __op_string "   %1,%3\n"                        \
-                "       csg     %0,%1,0(%4)\n"                  \
-                "       jl      0b"                             \
-                : "=&d" (__old), "=&d" (__new),                 \
-                  "=m" (*(unsigned long *) __addr)              \
-                : "d" (__val), "a" (__addr),                    \
-                  "m" (*(unsigned long *) __addr) : "cc");
-
-
-#endif /* __GNUC__ */
-
 #endif /* __s390x__ */
 
 #define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
@@ -261,9 +224,8 @@ static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
         asm volatile(
-                "       oc      0(1,%1),0(%2)"
-                : "=m" (*(char *) addr) : "a" (addr),
-                  "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
+                "       oc      %O0(1,%R0),%1"
+                : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" );
 }
 
 static inline void 
@@ -290,9 +252,8 @@ __clear_bit(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
         asm volatile(
-                "       nc      0(1,%1),0(%2)"
-                : "=m" (*(char *) addr) : "a" (addr),
-                  "a" (_ni_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc");
+                "       nc      %O0(1,%R0),%1"
+                : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7]) : "cc" );
 }
 
 static inline void 
@@ -318,9 +279,8 @@ static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
 
         addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
         asm volatile(
-                "       xc      0(1,%1),0(%2)"
-                :  "=m" (*(char *) addr) : "a" (addr),
-                   "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
+                "       xc      %O0(1,%R0),%1"
+                : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7]) : "cc" );
 }
 
 static inline void 
@@ -349,10 +309,9 @@ test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
         addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
         ch = *(unsigned char *) addr;
         asm volatile(
-                "       oc      0(1,%1),0(%2)"
-                : "=m" (*(char *) addr)
-                : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
-                  "m" (*(char *) addr) : "cc", "memory");
+                "       oc      %O0(1,%R0),%1"
+                : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7])
+                : "cc", "memory");
         return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_set_bit(X,Y)         test_and_set_bit_simple(X,Y)
@@ -369,10 +328,9 @@ test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
         addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
         ch = *(unsigned char *) addr;
         asm volatile(
-                "       nc      0(1,%1),0(%2)"
-                : "=m" (*(char *) addr)
-                : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
-                  "m" (*(char *) addr) : "cc", "memory");
+                "       nc      %O0(1,%R0),%1"
+                : "=Q" (*(char *) addr) : "Q" (_ni_bitmap[nr & 7])
+                : "cc", "memory");
         return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_clear_bit(X,Y)       test_and_clear_bit_simple(X,Y)
@@ -389,10 +347,9 @@ test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
         addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
         ch = *(unsigned char *) addr;
         asm volatile(
-                "       xc      0(1,%1),0(%2)"
-                : "=m" (*(char *) addr)
-                : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
-                  "m" (*(char *) addr) : "cc", "memory");
+                "       xc      %O0(1,%R0),%1"
+                : "=Q" (*(char *) addr) : "Q" (_oi_bitmap[nr & 7])
+                : "cc", "memory");
         return (ch >> (nr & 7)) & 1;
 }
 #define __test_and_change_bit(X,Y)      test_and_change_bit_simple(X,Y)
@@ -591,11 +548,11 @@ static inline unsigned long __load_ulong_le(const unsigned long *p,
         p = (unsigned long *)((unsigned long) p + offset);
 #ifndef __s390x__
         asm volatile(
-                "       ic      %0,0(%1)\n"
-                "       icm     %0,2,1(%1)\n"
-                "       icm     %0,4,2(%1)\n"
-                "       icm     %0,8,3(%1)"
-                : "=&d" (word) : "a" (p), "m" (*p) : "cc");
+                "       ic      %0,%O1(%R1)\n"
+                "       icm     %0,2,%O1+1(%R1)\n"
+                "       icm     %0,4,%O1+2(%R1)\n"
+                "       icm     %0,8,%O1+3(%R1)"
+                : "=&d" (word) : "Q" (*p) : "cc");
 #else
         asm volatile(
                 "       lrvg    %0,%1"
diff --git a/arch/s390/include/asm/bug.h b/arch/s390/include/asm/bug.h
index b1066b9fb5f8..9beeb9db9b23 100644
--- a/arch/s390/include/asm/bug.h
+++ b/arch/s390/include/asm/bug.h
@@ -5,12 +5,6 @@
 
 #ifdef CONFIG_BUG
 
-#ifdef CONFIG_64BIT
-#define S390_LONG ".quad"
-#else
-#define S390_LONG ".long"
-#endif
-
 #ifdef CONFIG_DEBUG_BUGVERBOSE
 
 #define __EMIT_BUG(x) do {                                      \
@@ -21,7 +15,7 @@
                 "2:     .asciz  \""__FILE__"\"\n"               \
                 ".previous\n"                                   \
                 ".section __bug_table,\"a\"\n"                  \
-                "3:\t"  S390_LONG "\t1b,2b\n"                   \
+                "3:     .long   1b-3b,2b-3b\n"                  \
                 "       .short  %0,%1\n"                        \
                 "       .org    3b+%2\n"                        \
                 ".previous\n"                                   \
@@ -37,7 +31,7 @@
                 "0:     j       0b+2\n"                 \
                 "1:\n"                                  \
                 ".section __bug_table,\"a\"\n"          \
-                "2:\t"  S390_LONG "\t1b\n"              \
+                "2:     .long   1b-2b\n"                \
                 "       .short  %0\n"                   \
                 "       .org    2b+%1\n"                \
                 ".previous\n"                           \
diff --git a/arch/s390/include/asm/crw.h b/arch/s390/include/asm/crw.h
index 2185a6d619d3..749a97e61bea 100644
--- a/arch/s390/include/asm/crw.h
+++ b/arch/s390/include/asm/crw.h
@@ -32,6 +32,7 @@ typedef void (*crw_handler_t)(struct crw *, struct crw *, int);
 extern int crw_register_handler(int rsc, crw_handler_t handler);
 extern void crw_unregister_handler(int rsc);
 extern void crw_handle_channel_report(void);
+void crw_wait_for_channel_report(void);
 
 #define NR_RSCS 16
 
diff --git a/arch/s390/include/asm/etr.h b/arch/s390/include/asm/etr.h
index 80ef58c61970..538e1b36a726 100644
--- a/arch/s390/include/asm/etr.h
+++ b/arch/s390/include/asm/etr.h
@@ -145,11 +145,11 @@ static inline int etr_setr(struct etr_eacr *ctrl)
         int rc = -ENOSYS;
 
         asm volatile(
-                "       .insn   s,0xb2160000,0(%2)\n"
+                "       .insn   s,0xb2160000,%1\n"
                 "0:     la      %0,0\n"
                 "1:\n"
                 EX_TABLE(0b,1b)
-                : "+d" (rc) : "m" (*ctrl), "a" (ctrl));
+                : "+d" (rc) : "Q" (*ctrl));
         return rc;
 }
 
@@ -159,11 +159,11 @@ static inline int etr_stetr(struct etr_aib *aib)
         int rc = -ENOSYS;
 
         asm volatile(
-                "       .insn   s,0xb2170000,0(%2)\n"
+                "       .insn   s,0xb2170000,%1\n"
                 "0:     la      %0,0\n"
                 "1:\n"
                 EX_TABLE(0b,1b)
-                : "+d" (rc) : "m" (*aib), "a" (aib));
+                : "+d" (rc) : "Q" (*aib));
         return rc;
 }
 
@@ -174,11 +174,11 @@ static inline int etr_steai(struct etr_aib *aib, unsigned int func)
         int rc = -ENOSYS;
 
         asm volatile(
-                "       .insn   s,0xb2b30000,0(%2)\n"
+                "       .insn   s,0xb2b30000,%1\n"
                 "0:     la      %0,0\n"
                 "1:\n"
                 EX_TABLE(0b,1b)
-                : "+d" (rc) : "m" (*aib), "a" (aib), "d" (reg0));
+                : "+d" (rc) : "Q" (*aib), "d" (reg0));
         return rc;
 }
 
diff --git a/arch/s390/include/asm/irqflags.h b/arch/s390/include/asm/irqflags.h
index c2fb432f576a..15b3ac253898 100644
--- a/arch/s390/include/asm/irqflags.h
+++ b/arch/s390/include/asm/irqflags.h
@@ -8,8 +8,6 @@
 
 #include <linux/types.h>
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-
 /* store then or system mask. */
 #define __raw_local_irq_stosm(__or)                                     \
 ({                                                                      \
@@ -36,40 +34,6 @@
         asm volatile("ssm   %0" : : "Q" (__mask) : "memory");           \
 })
 
-#else /* __GNUC__ */
-
-/* store then or system mask. */
-#define __raw_local_irq_stosm(__or)                                     \
-({                                                                      \
-        unsigned long __mask;                                           \
-        asm volatile(                                                   \
-                "       stosm   0(%1),%2"                               \
-                : "=m" (__mask)                                         \
-                : "a" (&__mask), "i" (__or) : "memory");                \
-        __mask;                                                         \
-})
-
-/* store then and system mask. */
-#define __raw_local_irq_stnsm(__and)                                    \
-({                                                                      \
-        unsigned long __mask;                                           \
-        asm volatile(                                                   \
-                "       stnsm   0(%1),%2"                               \
-                : "=m" (__mask)                                         \
-                : "a" (&__mask), "i" (__and) : "memory");               \
-        __mask;                                                         \
-})
-
-/* set system mask. */
-#define __raw_local_irq_ssm(__mask)                                     \
-({                                                                      \
-        asm volatile(                                                   \
-                "       ssm     0(%0)"                                  \
-                : : "a" (&__mask), "m" (__mask) : "memory");            \
-})
-
-#endif /* __GNUC__ */
-
 /* interrupt control.. */
 static inline unsigned long raw_local_irq_enable(void)
 {
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index c25dfac7dd76..05527c040b7a 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -1,141 +1,16 @@
 /*
- *  include/asm-s390/lowcore.h
- *
- *  S390 version
- *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Hartmut Penner (hp@de.ibm.com),
- *               Martin Schwidefsky (schwidefsky@de.ibm.com),
- *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
+ *    Copyright IBM Corp. 1999,2010
+ *    Author(s): Hartmut Penner <hp@de.ibm.com>,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Denis Joseph Barrow,
  */
 
 #ifndef _ASM_S390_LOWCORE_H
 #define _ASM_S390_LOWCORE_H
 
-#define __LC_IPL_PARMBLOCK_PTR          0x0014
-#define __LC_EXT_PARAMS                 0x0080
-#define __LC_CPU_ADDRESS                0x0084
-#define __LC_EXT_INT_CODE               0x0086
-
-#define __LC_SVC_ILC                    0x0088
-#define __LC_SVC_INT_CODE               0x008a
-#define __LC_PGM_ILC                    0x008c
-#define __LC_PGM_INT_CODE               0x008e
-
-#define __LC_PER_ATMID                  0x0096
-#define __LC_PER_ADDRESS                0x0098
-#define __LC_PER_ACCESS_ID              0x00a1
-#define __LC_AR_MODE_ID                 0x00a3
-
-#define __LC_SUBCHANNEL_ID              0x00b8
-#define __LC_SUBCHANNEL_NR              0x00ba
-#define __LC_IO_INT_PARM                0x00bc
-#define __LC_IO_INT_WORD                0x00c0
-#define __LC_STFL_FAC_LIST              0x00c8
-#define __LC_MCCK_CODE                  0x00e8
-
-#define __LC_DUMP_REIPL                 0x0e00
-
-#ifndef __s390x__
-#define __LC_EXT_OLD_PSW                0x0018
-#define __LC_SVC_OLD_PSW                0x0020
-#define __LC_PGM_OLD_PSW                0x0028
-#define __LC_MCK_OLD_PSW                0x0030
-#define __LC_IO_OLD_PSW                 0x0038
-#define __LC_EXT_NEW_PSW                0x0058
-#define __LC_SVC_NEW_PSW                0x0060
-#define __LC_PGM_NEW_PSW                0x0068
-#define __LC_MCK_NEW_PSW                0x0070
-#define __LC_IO_NEW_PSW                 0x0078
-#define __LC_SAVE_AREA                  0x0200
-#define __LC_RETURN_PSW                 0x0240
-#define __LC_RETURN_MCCK_PSW            0x0248
-#define __LC_SYNC_ENTER_TIMER           0x0250
-#define __LC_ASYNC_ENTER_TIMER          0x0258
-#define __LC_EXIT_TIMER                 0x0260
-#define __LC_USER_TIMER                 0x0268
-#define __LC_SYSTEM_TIMER               0x0270
-#define __LC_STEAL_TIMER                0x0278
-#define __LC_LAST_UPDATE_TIMER          0x0280
-#define __LC_LAST_UPDATE_CLOCK          0x0288
-#define __LC_CURRENT                    0x0290
-#define __LC_THREAD_INFO                0x0294
-#define __LC_KERNEL_STACK               0x0298
-#define __LC_ASYNC_STACK                0x029c
-#define __LC_PANIC_STACK                0x02a0
-#define __LC_KERNEL_ASCE                0x02a4
-#define __LC_USER_ASCE                  0x02a8
-#define __LC_USER_EXEC_ASCE             0x02ac
-#define __LC_CPUID                      0x02b0
-#define __LC_INT_CLOCK                  0x02c8
-#define __LC_MACHINE_FLAGS              0x02d8
-#define __LC_FTRACE_FUNC                0x02dc
-#define __LC_IRB                        0x0300
-#define __LC_PFAULT_INTPARM             0x0080
-#define __LC_CPU_TIMER_SAVE_AREA        0x00d8
-#define __LC_CLOCK_COMP_SAVE_AREA       0x00e0
-#define __LC_PSW_SAVE_AREA              0x0100
-#define __LC_PREFIX_SAVE_AREA           0x0108
-#define __LC_AREGS_SAVE_AREA            0x0120
-#define __LC_FPREGS_SAVE_AREA           0x0160
-#define __LC_GPREGS_SAVE_AREA           0x0180
-#define __LC_CREGS_SAVE_AREA            0x01c0
-#else /* __s390x__ */
-#define __LC_LAST_BREAK                 0x0110
-#define __LC_EXT_OLD_PSW                0x0130
-#define __LC_SVC_OLD_PSW                0x0140
-#define __LC_PGM_OLD_PSW                0x0150
-#define __LC_MCK_OLD_PSW                0x0160
-#define __LC_IO_OLD_PSW                 0x0170
-#define __LC_RESTART_PSW                0x01a0
-#define __LC_EXT_NEW_PSW                0x01b0
-#define __LC_SVC_NEW_PSW                0x01c0
-#define __LC_PGM_NEW_PSW                0x01d0
-#define __LC_MCK_NEW_PSW                0x01e0
-#define __LC_IO_NEW_PSW                 0x01f0
-#define __LC_SAVE_AREA                  0x0200
-#define __LC_RETURN_PSW                 0x0280
-#define __LC_RETURN_MCCK_PSW            0x0290
-#define __LC_SYNC_ENTER_TIMER           0x02a0
-#define __LC_ASYNC_ENTER_TIMER          0x02a8
-#define __LC_EXIT_TIMER                 0x02b0
-#define __LC_USER_TIMER                 0x02b8
-#define __LC_SYSTEM_TIMER               0x02c0
-#define __LC_STEAL_TIMER                0x02c8
-#define __LC_LAST_UPDATE_TIMER          0x02d0
-#define __LC_LAST_UPDATE_CLOCK          0x02d8
-#define __LC_CURRENT                    0x02e0
-#define __LC_THREAD_INFO                0x02e8
-#define __LC_KERNEL_STACK               0x02f0
-#define __LC_ASYNC_STACK                0x02f8
-#define __LC_PANIC_STACK                0x0300
-#define __LC_KERNEL_ASCE                0x0308
-#define __LC_USER_ASCE                  0x0310
-#define __LC_USER_EXEC_ASCE             0x0318
-#define __LC_CPUID                      0x0320
-#define __LC_INT_CLOCK                  0x0340
-#define __LC_VDSO_PER_CPU               0x0350
-#define __LC_MACHINE_FLAGS              0x0358
-#define __LC_FTRACE_FUNC                0x0360
-#define __LC_IRB                        0x0380
-#define __LC_PASTE                      0x03c0
-#define __LC_PFAULT_INTPARM             0x11b8
-#define __LC_FPREGS_SAVE_AREA           0x1200
-#define __LC_GPREGS_SAVE_AREA           0x1280
-#define __LC_PSW_SAVE_AREA              0x1300
-#define __LC_PREFIX_SAVE_AREA           0x1318
-#define __LC_FP_CREG_SAVE_AREA          0x131c
-#define __LC_TODREG_SAVE_AREA           0x1324
-#define __LC_CPU_TIMER_SAVE_AREA        0x1328
-#define __LC_CLOCK_COMP_SAVE_AREA       0x1331
-#define __LC_AREGS_SAVE_AREA            0x1340
-#define __LC_CREGS_SAVE_AREA            0x1380
-#endif /* __s390x__ */
-
-#ifndef __ASSEMBLY__
-
-#include <asm/cpu.h>
-#include <asm/ptrace.h>
 #include <linux/types.h>
+#include <asm/ptrace.h>
+#include <asm/cpu.h>
 
 void restart_int_handler(void);
 void ext_int_handler(void);
@@ -144,7 +19,12 @@ void pgm_check_handler(void);
 void mcck_int_handler(void);
 void io_int_handler(void);
 
-struct save_area_s390 {
+#ifdef CONFIG_32BIT
+
+#define LC_ORDER 0
+#define LC_PAGES 1
+
+struct save_area {
         u32     ext_save;
         u64     timer;
         u64     clk_cmp;
@@ -156,54 +36,13 @@ struct save_area_s390 {
         u64     fp_regs[4];
         u32     gp_regs[16];
         u32     ctrl_regs[16];
-}  __attribute__((packed));
+} __packed;
 
-struct save_area_s390x {
-        u64     fp_regs[16];
-        u64     gp_regs[16];
-        u8      psw[16];
-        u8      pad1[8];
-        u32     pref_reg;
-        u32     fp_ctrl_reg;
-        u8      pad2[4];
-        u32     tod_reg;
-        u64     timer;
-        u64     clk_cmp;
-        u8      pad3[8];
-        u32     acc_regs[16];
-        u64     ctrl_regs[16];
-}  __attribute__((packed));
-
-union save_area {
-        struct save_area_s390   s390;
-        struct save_area_s390x  s390x;
-};
-
-#define SAVE_AREA_BASE_S390     0xd4
-#define SAVE_AREA_BASE_S390X    0x1200
-
-#ifndef __s390x__
-#define SAVE_AREA_SIZE sizeof(struct save_area_s390)
-#define SAVE_AREA_BASE SAVE_AREA_BASE_S390
-#else
-#define SAVE_AREA_SIZE sizeof(struct save_area_s390x)
-#define SAVE_AREA_BASE SAVE_AREA_BASE_S390X
-#endif
-
-#ifndef __s390x__
-#define LC_ORDER 0
-#else
-#define LC_ORDER 1
-#endif
-
-#define LC_PAGES (1UL << LC_ORDER)
-
-struct _lowcore
-{
-#ifndef __s390x__
-        /* 0x0000 - 0x01ff: defined by architecture */
+struct _lowcore {
         psw_t   restart_psw;                    /* 0x0000 */
-        __u32   ccw2[4];                        /* 0x0008 */
+        psw_t   restart_old_psw;                /* 0x0008 */
+        __u8    pad_0x0010[0x0014-0x0010];      /* 0x0010 */
+        __u32   ipl_parmblock_ptr;              /* 0x0014 */
         psw_t   external_old_psw;               /* 0x0018 */
         psw_t   svc_old_psw;                    /* 0x0020 */
         psw_t   program_old_psw;                /* 0x0028 */
@@ -229,7 +68,9 @@ struct _lowcore
         __u32   monitor_code;                   /* 0x009c */
         __u8    exc_access_id;                  /* 0x00a0 */
         __u8    per_access_id;                  /* 0x00a1 */
-        __u8    pad_0x00a2[0x00b8-0x00a2];      /* 0x00a2 */
+        __u8    op_access_id;                   /* 0x00a2 */
+        __u8    ar_access_id;                   /* 0x00a3 */
+        __u8    pad_0x00a4[0x00b8-0x00a4];      /* 0x00a4 */
         __u16   subchannel_id;                  /* 0x00b8 */
         __u16   subchannel_nr;                  /* 0x00ba */
         __u32   io_int_parm;                    /* 0x00bc */
@@ -245,8 +86,9 @@ struct _lowcore
         __u32   external_damage_code;           /* 0x00f4 */
         __u32   failing_storage_address;        /* 0x00f8 */
         __u8    pad_0x00fc[0x0100-0x00fc];      /* 0x00fc */
-        __u32   st_status_fixed_logout[4];      /* 0x0100 */
-        __u8    pad_0x0110[0x0120-0x0110];      /* 0x0110 */
+        psw_t   psw_save_area;                  /* 0x0100 */
+        __u32   prefixreg_save_area;            /* 0x0108 */
+        __u8    pad_0x010c[0x0120-0x010c];      /* 0x010c */
 
         /* CPU register save area: defined by architecture */
         __u32   access_regs_save_area[16];      /* 0x0120 */
@@ -310,10 +152,32 @@ struct _lowcore
 
         /* Align to the top 1k of prefix area */
         __u8    pad_0x0e08[0x1000-0x0e08];      /* 0x0e08 */
-#else /* !__s390x__ */
-        /* 0x0000 - 0x01ff: defined by architecture */
-        __u32   ccw1[2];                        /* 0x0000 */
-        __u32   ccw2[4];                        /* 0x0008 */
+} __packed;
+
+#else /* CONFIG_32BIT */
+
+#define LC_ORDER 1
+#define LC_PAGES 2
+
+struct save_area {
+        u64     fp_regs[16];
+        u64     gp_regs[16];
+        u8      psw[16];
+        u8      pad1[8];
+        u32     pref_reg;
+        u32     fp_ctrl_reg;
+        u8      pad2[4];
+        u32     tod_reg;
+        u64     timer;
+        u64     clk_cmp;
+        u8      pad3[8];
+        u32     acc_regs[16];
+        u64     ctrl_regs[16];
+} __packed;
+
+struct _lowcore {
+        __u8    pad_0x0000[0x0014-0x0000];      /* 0x0000 */
+        __u32   ipl_parmblock_ptr;              /* 0x0014 */
         __u8    pad_0x0018[0x0080-0x0018];      /* 0x0018 */
         __u32   ext_params;                     /* 0x0080 */
         __u16   cpu_addr;                       /* 0x0084 */
@@ -344,7 +208,9 @@ struct _lowcore
         __u8    pad_0x00f0[0x00f4-0x00f0];      /* 0x00f0 */
         __u32   external_damage_code;           /* 0x00f4 */
         addr_t  failing_storage_address;        /* 0x00f8 */
-        __u8    pad_0x0100[0x0120-0x0100];      /* 0x0100 */
+        __u8    pad_0x0100[0x0110-0x0100];      /* 0x0100 */
+        __u64   breaking_event_addr;            /* 0x0110 */
+        __u8    pad_0x0118[0x0120-0x0118];      /* 0x0118 */
         psw_t   restart_old_psw;                /* 0x0120 */
         psw_t   external_old_psw;               /* 0x0130 */
         psw_t   svc_old_psw;                    /* 0x0140 */
@@ -425,7 +291,7 @@ struct _lowcore
         /* CPU register save area: defined by architecture */
         __u64   floating_pt_save_area[16];      /* 0x1200 */
         __u64   gpregs_save_area[16];           /* 0x1280 */
-        __u32   st_status_fixed_logout[4];      /* 0x1300 */
+        psw_t   psw_save_area;                  /* 0x1300 */
         __u8    pad_0x1310[0x1318-0x1310];      /* 0x1310 */
         __u32   prefixreg_save_area;            /* 0x1318 */
         __u32   fpt_creg_save_area;             /* 0x131c */
@@ -439,10 +305,12 @@ struct _lowcore
 
         /* align to the top of the prefix area */
         __u8    pad_0x1400[0x2000-0x1400];      /* 0x1400 */
-#endif /* !__s390x__ */
-} __attribute__((packed)); /* End structure*/
+} __packed;
+
+#endif /* CONFIG_32BIT */
 
 #define S390_lowcore (*((struct _lowcore *) 0))
+
 extern struct _lowcore *lowcore_ptr[];
 
 static inline void set_prefix(__u32 address)
@@ -458,6 +326,4 @@ static inline __u32 store_prefix(void)
         return address;
 }
 
-#endif
-
-#endif
+#endif /* _ASM_S390_LOWCORE_H */
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index 5e9daf5d7f22..af650fb47206 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -107,9 +107,6 @@ typedef pte_t *pgtable_t;
 #define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-/* default storage key used for all pages */
-extern unsigned int default_storage_key;
-
 static inline void
 page_set_storage_key(unsigned long addr, unsigned int skey)
 {
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index e2fa79cf0614..9b5b9189c15e 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -43,7 +43,7 @@ extern void vmem_map_init(void);
  * The S390 doesn't have any external MMU info: the kernel page
  * tables contain all the necessary information.
  */
-#define update_mmu_cache(vma, address, pte)     do { } while (0)
+#define update_mmu_cache(vma, address, ptep)     do { } while (0)
 
 /*
  * ZERO_PAGE is a global shared page that is always zero: used
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index b42715458312..73e259834e10 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -28,7 +28,7 @@
 
 static inline void get_cpu_id(struct cpuid *ptr)
 {
-        asm volatile("stidp 0(%1)" : "=m" (*ptr) : "a" (ptr));
+        asm volatile("stidp %0" : "=Q" (*ptr));
 }
 
 extern void s390_adjust_jiffies(void);
@@ -184,9 +184,9 @@ static inline void psw_set_key(unsigned int key)
 static inline void __load_psw(psw_t psw)
 {
 #ifndef __s390x__
-        asm volatile("lpsw  0(%0)" : : "a" (&psw), "m" (psw) : "cc");
+        asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 #else
-        asm volatile("lpswe 0(%0)" : : "a" (&psw), "m" (psw) : "cc");
+        asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 #endif
 }
 
@@ -206,17 +206,17 @@ static inline void __load_psw_mask (unsigned long mask)
         asm volatile(
                 "       basr    %0,0\n"
                 "0:     ahi     %0,1f-0b\n"
-                "       st      %0,4(%1)\n"
-                "       lpsw    0(%1)\n"
+                "       st      %0,%O1+4(%R1)\n"
+                "       lpsw    %1\n"
                 "1:"
-                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
+                : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 #else /* __s390x__ */
         asm volatile(
                 "       larl    %0,1f\n"
-                "       stg     %0,8(%1)\n"
-                "       lpswe   0(%1)\n"
+                "       stg     %0,%O1+8(%R1)\n"
+                "       lpswe   %1\n"
                 "1:"
-                : "=&d" (addr) : "a" (&psw), "m" (psw) : "memory", "cc");
+                : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 #endif /* __s390x__ */
 }
  
diff --git a/arch/s390/include/asm/ptrace.h b/arch/s390/include/asm/ptrace.h
index 95dcf183a28d..dd2d913afcae 100644
--- a/arch/s390/include/asm/ptrace.h
+++ b/arch/s390/include/asm/ptrace.h
@@ -492,13 +492,24 @@ struct user_regs_struct
 struct task_struct;
 extern void user_enable_single_step(struct task_struct *);
 extern void user_disable_single_step(struct task_struct *);
+extern void show_regs(struct pt_regs * regs);
 
 #define user_mode(regs) (((regs)->psw.mask & PSW_MASK_PSTATE) != 0)
 #define instruction_pointer(regs) ((regs)->psw.addr & PSW_ADDR_INSN)
 #define user_stack_pointer(regs)((regs)->gprs[15])
 #define regs_return_value(regs)((regs)->gprs[2])
 #define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs * regs);
+
+int regs_query_register_offset(const char *name);
+const char *regs_query_register_name(unsigned int offset);
+unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset);
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n);
+
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+        return regs->gprs[15] & PSW_ADDR_INSN;
+}
+
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/s390/include/asm/qdio.h b/arch/s390/include/asm/qdio.h
index 79d849f014f0..c666bfe5e984 100644
--- a/arch/s390/include/asm/qdio.h
+++ b/arch/s390/include/asm/qdio.h
@@ -13,7 +13,8 @@
 #include <asm/cio.h>
 #include <asm/ccwdev.h>
 
-#define QDIO_MAX_QUEUES_PER_IRQ         32
+/* only use 4 queues to save some cachelines */
+#define QDIO_MAX_QUEUES_PER_IRQ         4
 #define QDIO_MAX_BUFFERS_PER_Q          128
 #define QDIO_MAX_BUFFERS_MASK           (QDIO_MAX_BUFFERS_PER_Q - 1)
 #define QDIO_MAX_ELEMENTS_PER_BUFFER    16
diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h
index 9d2a17971805..423fdda2322d 100644
--- a/arch/s390/include/asm/rwsem.h
+++ b/arch/s390/include/asm/rwsem.h
@@ -124,21 +124,21 @@ static inline void __down_read(struct rw_semaphore *sem)
 
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       ahi     %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       ahi     %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       aghi    %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       aghi    %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count),
-                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS)
+                : "cc", "memory");
         if (old < 0)
                 rwsem_down_read_failed(sem);
 }
@@ -152,25 +152,25 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
 
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     ltr     %1,%0\n"
                 "       jm      1f\n"
-                "       ahi     %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       ahi     %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b\n"
                 "1:"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     ltgr    %1,%0\n"
                 "       jm      1f\n"
-                "       aghi    %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       aghi    %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b\n"
                 "1:"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count),
-                  "i" (RWSEM_ACTIVE_READ_BIAS) : "cc", "memory");
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "i" (RWSEM_ACTIVE_READ_BIAS)
+                : "cc", "memory");
         return old >= 0 ? 1 : 0;
 }
 
@@ -184,20 +184,20 @@ static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
         tmp = RWSEM_ACTIVE_WRITE_BIAS;
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       a       %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       a       %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       ag      %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       ag      %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "m" (tmp)
                 : "cc", "memory");
         if (old != 0)
                 rwsem_down_write_failed(sem);
@@ -217,22 +217,22 @@ static inline int __down_write_trylock(struct rw_semaphore *sem)
 
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%2)\n"
+                "       l       %0,%1\n"
                 "0:     ltr     %0,%0\n"
                 "       jnz     1f\n"
-                "       cs      %0,%4,0(%2)\n"
+                "       cs      %0,%3,%1\n"
                 "       jl      0b\n"
 #else /* __s390x__ */
-                "       lg      %0,0(%2)\n"
+                "       lg      %0,%1\n"
                 "0:     ltgr    %0,%0\n"
                 "       jnz     1f\n"
-                "       csg     %0,%4,0(%2)\n"
+                "       csg     %0,%3,%1\n"
                 "       jl      0b\n"
 #endif /* __s390x__ */
                 "1:"
-                : "=&d" (old), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count),
-                  "d" (RWSEM_ACTIVE_WRITE_BIAS) : "cc", "memory");
+                : "=&d" (old), "=Q" (sem->count)
+                : "Q" (sem->count), "d" (RWSEM_ACTIVE_WRITE_BIAS)
+                : "cc", "memory");
         return (old == RWSEM_UNLOCKED_VALUE) ? 1 : 0;
 }
 
@@ -245,21 +245,20 @@ static inline void __up_read(struct rw_semaphore *sem)
 
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       ahi     %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       ahi     %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       aghi    %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       aghi    %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count),
-                  "i" (-RWSEM_ACTIVE_READ_BIAS)
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "i" (-RWSEM_ACTIVE_READ_BIAS)
                 : "cc", "memory");
         if (new < 0)
                 if ((new & RWSEM_ACTIVE_MASK) == 0)
@@ -276,20 +275,20 @@ static inline void __up_write(struct rw_semaphore *sem)
         tmp = -RWSEM_ACTIVE_WRITE_BIAS;
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       a       %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       a       %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       ag      %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       ag      %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "m" (tmp)
                 : "cc", "memory");
         if (new < 0)
                 if ((new & RWSEM_ACTIVE_MASK) == 0)
@@ -306,20 +305,20 @@ static inline void __downgrade_write(struct rw_semaphore *sem)
         tmp = -RWSEM_WAITING_BIAS;
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       a       %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       a       %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       ag      %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       ag      %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count), "m" (tmp)
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "m" (tmp)
                 : "cc", "memory");
         if (new > 1)
                 rwsem_downgrade_wake(sem);
@@ -334,20 +333,20 @@ static inline void rwsem_atomic_add(long delta, struct rw_semaphore *sem)
 
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       ar      %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       ar      %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       agr     %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       agr     %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count), "d" (delta)
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "d" (delta)
                 : "cc", "memory");
 }
 
@@ -360,20 +359,20 @@ static inline long rwsem_atomic_update(long delta, struct rw_semaphore *sem)
 
         asm volatile(
 #ifndef __s390x__
-                "       l       %0,0(%3)\n"
+                "       l       %0,%2\n"
                 "0:     lr      %1,%0\n"
-                "       ar      %1,%5\n"
-                "       cs      %0,%1,0(%3)\n"
+                "       ar      %1,%4\n"
+                "       cs      %0,%1,%2\n"
                 "       jl      0b"
 #else /* __s390x__ */
-                "       lg      %0,0(%3)\n"
+                "       lg      %0,%2\n"
                 "0:     lgr     %1,%0\n"
-                "       agr     %1,%5\n"
-                "       csg     %0,%1,0(%3)\n"
+                "       agr     %1,%4\n"
+                "       csg     %0,%1,%2\n"
                 "       jl      0b"
 #endif /* __s390x__ */
-                : "=&d" (old), "=&d" (new), "=m" (sem->count)
-                : "a" (&sem->count), "m" (sem->count), "d" (delta)
+                : "=&d" (old), "=&d" (new), "=Q" (sem->count)
+                : "Q" (sem->count), "d" (delta)
                 : "cc", "memory");
         return new;
 }
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index 52a779c337e8..9ab6bd3a65d1 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -14,14 +14,14 @@
 
 #ifdef __KERNEL__
 
-#include <asm/lowcore.h>
-#include <asm/types.h>
-
 #define PARMAREA                0x10400
 #define MEMORY_CHUNKS           256
 
 #ifndef __ASSEMBLY__
 
+#include <asm/lowcore.h>
+#include <asm/types.h>
+
 #ifndef __s390x__
 #define IPL_DEVICE        (*(unsigned long *)  (0x10404))
 #define INITRD_START      (*(unsigned long *)  (0x1040C))
@@ -71,9 +71,12 @@ extern unsigned int user_mode;
 #define MACHINE_FLAG_KVM        (1UL << 9)
 #define MACHINE_FLAG_HPAGE      (1UL << 10)
 #define MACHINE_FLAG_PFMF       (1UL << 11)
+#define MACHINE_FLAG_LPAR       (1UL << 12)
 
 #define MACHINE_IS_VM           (S390_lowcore.machine_flags & MACHINE_FLAG_VM)
 #define MACHINE_IS_KVM          (S390_lowcore.machine_flags & MACHINE_FLAG_KVM)
+#define MACHINE_IS_LPAR         (S390_lowcore.machine_flags & MACHINE_FLAG_LPAR)
+
 #define MACHINE_HAS_DIAG9C      (S390_lowcore.machine_flags & MACHINE_FLAG_DIAG9C)
 
 #ifndef __s390x__
diff --git a/arch/s390/include/asm/sigp.h b/arch/s390/include/asm/sigp.h
index f72d611f7e13..e3bffd4e2d66 100644
--- a/arch/s390/include/asm/sigp.h
+++ b/arch/s390/include/asm/sigp.h
@@ -1,24 +1,19 @@
 /*
- *  include/asm-s390/sigp.h
+ *  Routines and structures for signalling other processors.
  *
- *  S390 version
- *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
- *    Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
- *               Martin Schwidefsky (schwidefsky@de.ibm.com)
- *               Heiko Carstens (heiko.carstens@de.ibm.com)
- *
- *  sigp.h by D.J. Barrow (c) IBM 1999
- *  contains routines / structures for signalling other S/390 processors in an
- *  SMP configuration.
+ *    Copyright IBM Corp. 1999,2010
+ *    Author(s): Denis Joseph Barrow,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Heiko Carstens <heiko.carstens@de.ibm.com>,
  */
 
-#ifndef __SIGP__
-#define __SIGP__
+#ifndef __ASM_SIGP_H
+#define __ASM_SIGP_H
 
 #include <asm/system.h>
 
-/* get real cpu address from logical cpu number */
-extern int __cpu_logical_map[];
+/* Get real cpu address from logical cpu number. */
+extern unsigned short __cpu_logical_map[];
 
 static inline int cpu_logical_map(int cpu)
 {
@@ -29,107 +24,108 @@ static inline int cpu_logical_map(int cpu)
 #endif
 }
 
-typedef enum
-{
-        sigp_unassigned=0x0,
-        sigp_sense,
-        sigp_external_call,
-        sigp_emergency_signal,
-        sigp_start,
-        sigp_stop,
-        sigp_restart,
-        sigp_unassigned1,
-        sigp_unassigned2,
-        sigp_stop_and_store_status,
-        sigp_unassigned3,
-        sigp_initial_cpu_reset,
-        sigp_cpu_reset,
-        sigp_set_prefix,
-        sigp_store_status_at_address,
-        sigp_store_extended_status_at_address
-} sigp_order_code;
-
-typedef __u32 sigp_status_word;
-
-typedef enum
-{
-        sigp_order_code_accepted=0,
-        sigp_status_stored,
-        sigp_busy,
-        sigp_not_operational
-} sigp_ccode;
-
+enum {
+        sigp_sense = 1,
+        sigp_external_call = 2,
+        sigp_emergency_signal = 3,
+        sigp_start = 4,
+        sigp_stop = 5,
+        sigp_restart = 6,
+        sigp_stop_and_store_status = 9,
+        sigp_initial_cpu_reset = 11,
+        sigp_cpu_reset = 12,
+        sigp_set_prefix = 13,
+        sigp_store_status_at_address = 14,
+        sigp_store_extended_status_at_address = 15,
+        sigp_set_architecture = 18,
+        sigp_conditional_emergency_signal = 19,
+        sigp_sense_running = 21,
+};
+
+enum {
+        sigp_order_code_accepted = 0,
+        sigp_status_stored = 1,
+        sigp_busy = 2,
+        sigp_not_operational = 3,
+};
 
 /*
- * Definitions for the external call
+ * Definitions for external call.
  */
-
-/* 'Bit' signals, asynchronous */
-typedef enum
-{
-        ec_schedule=0,
+enum {
+        ec_schedule = 0,
         ec_call_function,
         ec_call_function_single,
-        ec_bit_last
-} ec_bit_sig;
+};
 
 /*
- * Signal processor
+ * Signal processor.
  */
-static inline sigp_ccode
-signal_processor(__u16 cpu_addr, sigp_order_code order_code)
+static inline int raw_sigp(u16 cpu, int order)
 {
         register unsigned long reg1 asm ("1") = 0;
-        sigp_ccode ccode;
+        int ccode;
 
         asm volatile(
                 "       sigp    %1,%2,0(%3)\n"
                 "       ipm     %0\n"
                 "       srl     %0,28\n"
                 :       "=d"    (ccode)
-                : "d" (reg1), "d" (cpu_logical_map(cpu_addr)),
-                  "a" (order_code) : "cc" , "memory");
+                : "d" (reg1), "d" (cpu),
+                  "a" (order) : "cc" , "memory");
         return ccode;
 }
 
 /*
- * Signal processor with parameter
+ * Signal processor with parameter.
  */
-static inline sigp_ccode
-signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code)
+static inline int raw_sigp_p(u32 parameter, u16 cpu, int order)
 {
         register unsigned int reg1 asm ("1") = parameter;
-        sigp_ccode ccode;
+        int ccode;
 
         asm volatile(
                 "       sigp    %1,%2,0(%3)\n"
                 "       ipm     %0\n"
                 "       srl     %0,28\n"
                 : "=d" (ccode)
-                : "d" (reg1), "d" (cpu_logical_map(cpu_addr)),
-                  "a" (order_code) : "cc" , "memory");
+                : "d" (reg1), "d" (cpu),
+                  "a" (order) : "cc" , "memory");
         return ccode;
 }
 
 /*
- * Signal processor with parameter and return status
+ * Signal processor with parameter and return status.
  */
-static inline sigp_ccode
-signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr,
-                    sigp_order_code order_code)
+static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order)
 {
-        register unsigned int reg1 asm ("1") = parameter;
-        sigp_ccode ccode;
+        register unsigned int reg1 asm ("1") = parm;
+        int ccode;
 
         asm volatile(
                 "       sigp    %1,%2,0(%3)\n"
                 "       ipm     %0\n"
                 "       srl     %0,28\n"
                 : "=d" (ccode), "+d" (reg1)
-                : "d" (cpu_logical_map(cpu_addr)), "a" (order_code)
+                : "d" (cpu), "a" (order)
                 : "cc" , "memory");
-        *statusptr = reg1;
+        *status = reg1;
         return ccode;
 }
 
-#endif /* __SIGP__ */
+static inline int sigp(int cpu, int order)
+{
+        return raw_sigp(cpu_logical_map(cpu), order);
+}
+
+static inline int sigp_p(u32 parameter, int cpu, int order)
+{
+        return raw_sigp_p(parameter, cpu_logical_map(cpu), order);
+}
+
+static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order)
+{
+        return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order);
+}
+
+#endif /* __ASM_SIGP_H */
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index 2ab1141eeb50..edc03cb9cd79 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -29,7 +29,43 @@ extern int smp_cpu_polarization[];
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
-extern union save_area *zfcpdump_save_areas[NR_CPUS + 1];
+extern struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
+
+extern void smp_switch_to_ipl_cpu(void (*func)(void *), void *);
+extern void smp_switch_to_cpu(void (*)(void *), void *, unsigned long sp,
+                              int from, int to);
+extern void smp_restart_cpu(void);
+
+/*
+ * returns 1 if (virtual) cpu is scheduled
+ * returns 0 otherwise
+ */
+static inline int smp_vcpu_scheduled(int cpu)
+{
+        u32 status;
+
+        switch (sigp_ps(&status, 0, cpu, sigp_sense_running)) {
+        case sigp_status_stored:
+                /* Check for running status */
+                if (status & 0x400)
+                        return 0;
+                break;
+        case sigp_not_operational:
+                return 0;
+        default:
+                break;
+        }
+        return 1;
+}
+
+#else /* CONFIG_SMP */
+
+static inline void smp_switch_to_ipl_cpu(void (*func)(void *), void *data)
+{
+        func(data);
+}
+
+#define smp_vcpu_scheduled      (1)
 
 #endif /* CONFIG_SMP */
 
diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h
index a587907d77f3..56612fc8186e 100644
--- a/arch/s390/include/asm/spinlock.h
+++ b/arch/s390/include/asm/spinlock.h
@@ -13,8 +13,6 @@
 
 #include <linux/smp.h>
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
-
 static inline int
 _raw_compare_and_swap(volatile unsigned int *lock,
                       unsigned int old, unsigned int new)
@@ -27,22 +25,6 @@ _raw_compare_and_swap(volatile unsigned int *lock,
         return old;
 }
 
-#else /* __GNUC__ */
-
-static inline int
-_raw_compare_and_swap(volatile unsigned int *lock,
-                      unsigned int old, unsigned int new)
-{
-        asm volatile(
-                "       cs      %0,%3,0(%4)"
-                : "=d" (old), "=m" (*lock)
-                : "0" (old), "d" (new), "a" (lock), "m" (*lock)
-                : "cc", "memory" );
-        return old;
-}
-
-#endif /* __GNUC__ */
-
 /*
  * Simple spin lock operations.  There are two variants, one clears IRQ's
  * on the local processor, one does not.
diff --git a/arch/s390/include/asm/swab.h b/arch/s390/include/asm/swab.h
index eb18dc1f327b..6bdee21c077e 100644
--- a/arch/s390/include/asm/swab.h
+++ b/arch/s390/include/asm/swab.h
@@ -47,11 +47,11 @@ static inline __u32 __arch_swab32p(const __u32 *x)
         
         asm volatile(
 #ifndef __s390x__
-                "       icm     %0,8,3(%1)\n"
-                "       icm     %0,4,2(%1)\n"
-                "       icm     %0,2,1(%1)\n"
-                "       ic      %0,0(%1)"
-                : "=&d" (result) : "a" (x), "m" (*x) : "cc");
+                "       icm     %0,8,%O1+3(%R1)\n"
+                "       icm     %0,4,%O1+2(%R1)\n"
+                "       icm     %0,2,%O1+1(%R1)\n"
+                "       ic      %0,%1"
+                : "=&d" (result) : "Q" (*x) : "cc");
 #else /* __s390x__ */
                 "       lrv     %0,%1"
                 : "=d" (result) : "m" (*x));
@@ -77,9 +77,9 @@ static inline __u16 __arch_swab16p(const __u16 *x)
         
         asm volatile(
 #ifndef __s390x__
-                "       icm     %0,2,1(%1)\n"
-                "       ic      %0,0(%1)\n"
-                : "=&d" (result) : "a" (x), "m" (*x) : "cc");
+                "       icm     %0,2,%O+1(%R1)\n"
+                "       ic      %0,%1\n"
+                : "=&d" (result) : "Q" (*x) : "cc");
 #else /* __s390x__ */
                 "       lrvh    %0,%1"
                 : "=d" (result) : "m" (*x));
diff --git a/arch/s390/include/asm/syscall.h b/arch/s390/include/asm/syscall.h
index e0a73d3eb837..8429686951f9 100644
--- a/arch/s390/include/asm/syscall.h
+++ b/arch/s390/include/asm/syscall.h
@@ -15,6 +15,13 @@
 #include <linux/sched.h>
 #include <asm/ptrace.h>
 
+/*
+ * The syscall table always contains 32 bit pointers since we know that the
+ * address of the function to be called is (way) below 4GB.  So the "int"
+ * type here is what we want [need] for both 32 bit and 64 bit systems.
+ */
+extern const unsigned int sys_call_table[];
+
 static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
 {
diff --git a/arch/s390/include/asm/sysinfo.h b/arch/s390/include/asm/sysinfo.h
index 9d70057d828c..22bdb2a0ee5f 100644
--- a/arch/s390/include/asm/sysinfo.h
+++ b/arch/s390/include/asm/sysinfo.h
@@ -87,7 +87,8 @@ struct sysinfo_2_2_2 {
 
 struct sysinfo_3_2_2 {
         char reserved_0[31];
-        unsigned char count;
+        unsigned char :4;
+        unsigned char count:4;
         struct {
                 char reserved_0[4];
                 unsigned short cpus_total;
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
index 379661d2f81a..67ee6c3c6bb3 100644
--- a/arch/s390/include/asm/system.h
+++ b/arch/s390/include/asm/system.h
@@ -24,65 +24,65 @@ extern struct task_struct *__switch_to(void *, void *);
 static inline void save_fp_regs(s390_fp_regs *fpregs)
 {
         asm volatile(
-                "       std     0,8(%1)\n"
-                "       std     2,24(%1)\n"
-                "       std     4,40(%1)\n"
-                "       std     6,56(%1)"
-                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
+                "       std     0,%O0+8(%R0)\n"
+                "       std     2,%O0+24(%R0)\n"
+                "       std     4,%O0+40(%R0)\n"
+                "       std     6,%O0+56(%R0)"
+                : "=Q" (*fpregs) : "Q" (*fpregs));
         if (!MACHINE_HAS_IEEE)
                 return;
         asm volatile(
-                "       stfpc   0(%1)\n"
-                "       std     1,16(%1)\n"
-                "       std     3,32(%1)\n"
-                "       std     5,48(%1)\n"
-                "       std     7,64(%1)\n"
-                "       std     8,72(%1)\n"
-                "       std     9,80(%1)\n"
-                "       std     10,88(%1)\n"
-                "       std     11,96(%1)\n"
-                "       std     12,104(%1)\n"
-                "       std     13,112(%1)\n"
-                "       std     14,120(%1)\n"
-                "       std     15,128(%1)\n"
-                : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory");
+                "       stfpc   %0\n"
+                "       std     1,%O0+16(%R0)\n"
+                "       std     3,%O0+32(%R0)\n"
+                "       std     5,%O0+48(%R0)\n"
+                "       std     7,%O0+64(%R0)\n"
+                "       std     8,%O0+72(%R0)\n"
+                "       std     9,%O0+80(%R0)\n"
+                "       std     10,%O0+88(%R0)\n"
+                "       std     11,%O0+96(%R0)\n"
+                "       std     12,%O0+104(%R0)\n"
+                "       std     13,%O0+112(%R0)\n"
+                "       std     14,%O0+120(%R0)\n"
+                "       std     15,%O0+128(%R0)\n"
+                : "=Q" (*fpregs) : "Q" (*fpregs));
 }
 
 static inline void restore_fp_regs(s390_fp_regs *fpregs)
 {
         asm volatile(
-                "       ld      0,8(%0)\n"
-                "       ld      2,24(%0)\n"
-                "       ld      4,40(%0)\n"
-                "       ld      6,56(%0)"
-                : : "a" (fpregs), "m" (*fpregs));
+                "       ld      0,%O0+8(%R0)\n"
+                "       ld      2,%O0+24(%R0)\n"
+                "       ld      4,%O0+40(%R0)\n"
+                "       ld      6,%O0+56(%R0)"
+                : : "Q" (*fpregs));
         if (!MACHINE_HAS_IEEE)
                 return;
         asm volatile(
-                "       lfpc    0(%0)\n"
-                "       ld      1,16(%0)\n"
-                "       ld      3,32(%0)\n"
-                "       ld      5,48(%0)\n"
-                "       ld      7,64(%0)\n"
-                "       ld      8,72(%0)\n"
-                "       ld      9,80(%0)\n"
-                "       ld      10,88(%0)\n"
-                "       ld      11,96(%0)\n"
-                "       ld      12,104(%0)\n"
-                "       ld      13,112(%0)\n"
-                "       ld      14,120(%0)\n"
-                "       ld      15,128(%0)\n"
-                : : "a" (fpregs), "m" (*fpregs));
+                "       lfpc    %0\n"
+                "       ld      1,%O0+16(%R0)\n"
+                "       ld      3,%O0+32(%R0)\n"
+                "       ld      5,%O0+48(%R0)\n"
+                "       ld      7,%O0+64(%R0)\n"
+                "       ld      8,%O0+72(%R0)\n"
+                "       ld      9,%O0+80(%R0)\n"
+                "       ld      10,%O0+88(%R0)\n"
+                "       ld      11,%O0+96(%R0)\n"
+                "       ld      12,%O0+104(%R0)\n"
+                "       ld      13,%O0+112(%R0)\n"
+                "       ld      14,%O0+120(%R0)\n"
+                "       ld      15,%O0+128(%R0)\n"
+                : : "Q" (*fpregs));
 }
 
 static inline void save_access_regs(unsigned int *acrs)
 {
-        asm volatile("stam 0,15,0(%0)" : : "a" (acrs) : "memory");
+        asm volatile("stam 0,15,%0" : "=Q" (*acrs));
 }
 
 static inline void restore_access_regs(unsigned int *acrs)
 {
-        asm volatile("lam 0,15,0(%0)" : : "a" (acrs));
+        asm volatile("lam 0,15,%0" : : "Q" (*acrs));
 }
 
 #define switch_to(prev,next,last) do {                                       \
@@ -139,48 +139,48 @@ static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
                 shift = (3 ^ (addr & 3)) << 3;
                 addr ^= addr & 3;
                 asm volatile(
-                        "       l       %0,0(%4)\n"
+                        "       l       %0,%4\n"
                         "0:     lr      0,%0\n"
                         "       nr      0,%3\n"
                         "       or      0,%2\n"
-                        "       cs      %0,0,0(%4)\n"
+                        "       cs      %0,0,%4\n"
                         "       jl      0b\n"
-                        : "=&d" (old), "=m" (*(int *) addr)
-                        : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
-                          "m" (*(int *) addr) : "memory", "cc", "0");
+                        : "=&d" (old), "=Q" (*(int *) addr)
+                        : "d" (x << shift), "d" (~(255 << shift)),
+                          "Q" (*(int *) addr) : "memory", "cc", "0");
                 return old >> shift;
         case 2:
                 addr = (unsigned long) ptr;
                 shift = (2 ^ (addr & 2)) << 3;
                 addr ^= addr & 2;
                 asm volatile(
-                        "       l       %0,0(%4)\n"
+                        "       l       %0,%4\n"
                         "0:     lr      0,%0\n"
                         "       nr      0,%3\n"
                         "       or      0,%2\n"
-                        "       cs      %0,0,0(%4)\n"
+                        "       cs      %0,0,%4\n"
                         "       jl      0b\n"
-                        : "=&d" (old), "=m" (*(int *) addr)
-                        : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
-                          "m" (*(int *) addr) : "memory", "cc", "0");
+                        : "=&d" (old), "=Q" (*(int *) addr)
+                        : "d" (x << shift), "d" (~(65535 << shift)),
+                          "Q" (*(int *) addr) : "memory", "cc", "0");
                 return old >> shift;
         case 4:
                 asm volatile(
-                        "       l       %0,0(%3)\n"
-                        "0:     cs      %0,%2,0(%3)\n"
+                        "       l       %0,%3\n"
+                        "0:     cs      %0,%2,%3\n"
                         "       jl      0b\n"
-                        : "=&d" (old), "=m" (*(int *) ptr)
-                        : "d" (x), "a" (ptr), "m" (*(int *) ptr)
+                        : "=&d" (old), "=Q" (*(int *) ptr)
+                        : "d" (x), "Q" (*(int *) ptr)
                         : "memory", "cc");
                 return old;
 #ifdef __s390x__
         case 8:
                 asm volatile(
-                        "       lg      %0,0(%3)\n"
-                        "0:     csg     %0,%2,0(%3)\n"
+                        "       lg      %0,%3\n"
+                        "0:     csg     %0,%2,%3\n"
                         "       jl      0b\n"
                         : "=&d" (old), "=m" (*(long *) ptr)
-                        : "d" (x), "a" (ptr), "m" (*(long *) ptr)
+                        : "d" (x), "Q" (*(long *) ptr)
                         : "memory", "cc");
                 return old;
 #endif /* __s390x__ */
@@ -215,20 +215,20 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
                 shift = (3 ^ (addr & 3)) << 3;
                 addr ^= addr & 3;
                 asm volatile(
-                        "       l       %0,0(%4)\n"
+                        "       l       %0,%2\n"
                         "0:     nr      %0,%5\n"
                         "       lr      %1,%0\n"
                         "       or      %0,%2\n"
                         "       or      %1,%3\n"
-                        "       cs      %0,%1,0(%4)\n"
+                        "       cs      %0,%1,%2\n"
                         "       jnl     1f\n"
                         "       xr      %1,%0\n"
                         "       nr      %1,%5\n"
                         "       jnz     0b\n"
                         "1:"
-                        : "=&d" (prev), "=&d" (tmp)
-                        : "d" (old << shift), "d" (new << shift), "a" (ptr),
-                          "d" (~(255 << shift))
+                        : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
+                        : "d" (old << shift), "d" (new << shift),
+                          "d" (~(255 << shift)), "Q" (*(int *) ptr)
                         : "memory", "cc");
                 return prev >> shift;
         case 2:
@@ -236,33 +236,35 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
                 shift = (2 ^ (addr & 2)) << 3;
                 addr ^= addr & 2;
                 asm volatile(
-                        "       l       %0,0(%4)\n"
+                        "       l       %0,%2\n"
                         "0:     nr      %0,%5\n"
                         "       lr      %1,%0\n"
                         "       or      %0,%2\n"
                         "       or      %1,%3\n"
-                        "       cs      %0,%1,0(%4)\n"
+                        "       cs      %0,%1,%2\n"
                         "       jnl     1f\n"
                         "       xr      %1,%0\n"
                         "       nr      %1,%5\n"
                         "       jnz     0b\n"
                         "1:"
-                        : "=&d" (prev), "=&d" (tmp)
-                        : "d" (old << shift), "d" (new << shift), "a" (ptr),
-                          "d" (~(65535 << shift))
+                        : "=&d" (prev), "=&d" (tmp), "=Q" (*(int *) ptr)
+                        : "d" (old << shift), "d" (new << shift),
+                          "d" (~(65535 << shift)), "Q" (*(int *) ptr)
                         : "memory", "cc");
                 return prev >> shift;
         case 4:
                 asm volatile(
-                        "       cs      %0,%2,0(%3)\n"
-                        : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
+                        "       cs      %0,%3,%1\n"
+                        : "=&d" (prev), "=Q" (*(int *) ptr)
+                        : "0" (old), "d" (new), "Q" (*(int *) ptr)
                         : "memory", "cc");
                 return prev;
 #ifdef __s390x__
         case 8:
                 asm volatile(
-                        "       csg     %0,%2,0(%3)\n"
-                        : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
+                        "       csg     %0,%3,%1\n"
+                        : "=&d" (prev), "=Q" (*(long *) ptr)
+                        : "0" (old), "d" (new), "Q" (*(long *) ptr)
                         : "memory", "cc");
                 return prev;
 #endif /* __s390x__ */
@@ -302,17 +304,17 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 #define __ctl_load(array, low, high) ({                         \
         typedef struct { char _[sizeof(array)]; } addrtype;     \
         asm volatile(                                           \
-                "       lctlg   %1,%2,0(%0)\n"                  \
-                : : "a" (&array), "i" (low), "i" (high),        \
-                    "m" (*(addrtype *)(&array)));               \
+                "       lctlg   %1,%2,%0\n"                     \
+                : : "Q" (*(addrtype *)(&array)),                \
+                    "i" (low), "i" (high));                     \
         })
 
 #define __ctl_store(array, low, high) ({                        \
         typedef struct { char _[sizeof(array)]; } addrtype;     \
         asm volatile(                                           \
-                "       stctg   %2,%3,0(%1)\n"                  \
-                : "=m" (*(addrtype *)(&array))                  \
-                : "a" (&array), "i" (low), "i" (high));         \
+                "       stctg   %1,%2,%0\n"                     \
+                : "=Q" (*(addrtype *)(&array))                  \
+                : "i" (low), "i" (high));                       \
         })
 
 #else /* __s390x__ */
@@ -320,17 +322,17 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 #define __ctl_load(array, low, high) ({                         \
         typedef struct { char _[sizeof(array)]; } addrtype;     \
         asm volatile(                                           \
-                "       lctl    %1,%2,0(%0)\n"                  \
-                : : "a" (&array), "i" (low), "i" (high),        \
-                    "m" (*(addrtype *)(&array)));               \
+                "       lctl    %1,%2,%0\n"                     \
+                : : "Q" (*(addrtype *)(&array)),                \
+                    "i" (low), "i" (high));                     \
 })
 
 #define __ctl_store(array, low, high) ({                        \
         typedef struct { char _[sizeof(array)]; } addrtype;     \
         asm volatile(                                           \
-                "       stctl   %2,%3,0(%1)\n"                  \
-                : "=m" (*(addrtype *)(&array))                  \
-                : "a" (&array), "i" (low), "i" (high));         \
+                "       stctl   %1,%2,%0\n"                     \
+                : "=Q" (*(addrtype *)(&array))                  \
+                : "i" (low), "i" (high));                       \
         })
 
 #endif /* __s390x__ */
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 66069e736842..34f0873d6525 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -73,7 +73,7 @@ struct thread_info {
 /* how to get the thread information struct from C */
 static inline struct thread_info *current_thread_info(void)
 {
-        return (struct thread_info *)((*(unsigned long *) __LC_KERNEL_STACK)-THREAD_SIZE);
+        return (struct thread_info *)(S390_lowcore.kernel_stack - THREAD_SIZE);
 }
 
 #define THREAD_SIZE_ORDER THREAD_ORDER
diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
index 68d9fea34b4b..f174bdaa6b59 100644
--- a/arch/s390/include/asm/timex.h
+++ b/arch/s390/include/asm/timex.h
@@ -20,10 +20,10 @@ static inline int set_clock(__u64 time)
         int cc;
 
         asm volatile(
-                "   sck   0(%2)\n"
+                "   sck   %1\n"
                 "   ipm   %0\n"
                 "   srl   %0,28\n"
-                : "=d" (cc) : "m" (time), "a" (&time) : "cc");
+                : "=d" (cc) : "Q" (time) : "cc");
         return cc;
 }
 
@@ -32,21 +32,21 @@ static inline int store_clock(__u64 *time)
         int cc;
 
         asm volatile(
-                "   stck  0(%2)\n"
+                "   stck  %1\n"
                 "   ipm   %0\n"
                 "   srl   %0,28\n"
-                : "=d" (cc), "=m" (*time) : "a" (time) : "cc");
+                : "=d" (cc), "=Q" (*time) : : "cc");
         return cc;
 }
 
 static inline void set_clock_comparator(__u64 time)
 {
-        asm volatile("sckc 0(%1)" : : "m" (time), "a" (&time));
+        asm volatile("sckc %0" : : "Q" (time));
 }
 
 static inline void store_clock_comparator(__u64 *time)
 {
-        asm volatile("stckc 0(%1)" : "=m" (*time) : "a" (time));
+        asm volatile("stckc %0" : "=Q" (*time));
 }
 
 #define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
@@ -57,11 +57,7 @@ static inline unsigned long long get_clock (void)
 {
         unsigned long long clk;
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
         asm volatile("stck %0" : "=Q" (clk) : : "cc");
-#else /* __GNUC__ */
-        asm volatile("stck 0(%1)" : "=m" (clk) : "a" (&clk) : "cc");
-#endif /* __GNUC__ */
         return clk;
 }
 
@@ -69,13 +65,7 @@ static inline unsigned long long get_clock_xt(void)
 {
         unsigned char clk[16];
 
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
         asm volatile("stcke %0" : "=Q" (clk) : : "cc");
-#else /* __GNUC__ */
-        asm volatile("stcke 0(%1)" : "=m" (clk)
-                                   : "a" (clk) : "cc");
-#endif /* __GNUC__ */
-
         return *((unsigned long long *)&clk[1]);
 }
 
diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h
index cbf0a8745bf4..d6b1ed0ec52b 100644
--- a/arch/s390/include/asm/uaccess.h
+++ b/arch/s390/include/asm/uaccess.h
@@ -265,6 +265,12 @@ __copy_from_user(void *to, const void __user *from, unsigned long n)
                 return uaccess.copy_from_user(n, from, to);
 }
 
+extern void copy_from_user_overflow(void)
+#ifdef CONFIG_DEBUG_STRICT_USER_COPY_CHECKS
+__compiletime_warning("copy_from_user() buffer size is not provably correct")
+#endif
+;
+
 /**
  * copy_from_user: - Copy a block of data from user space.
  * @to:   Destination address, in kernel space.
@@ -284,7 +290,13 @@ __copy_from_user(void *to, const void __user *from, unsigned long n)
 static inline unsigned long __must_check
 copy_from_user(void *to, const void __user *from, unsigned long n)
 {
+        unsigned int sz = __compiletime_object_size(to);
+
         might_fault();
+        if (unlikely(sz != -1 && sz < n)) {
+                copy_from_user_overflow();
+                return n;
+        }
         if (access_ok(VERIFY_READ, from, n))
                 n = __copy_from_user(to, from, n);
         else
diff --git a/arch/s390/include/asm/vdso.h b/arch/s390/include/asm/vdso.h
index 7bdd7c8ebc91..4a76d9480cce 100644
--- a/arch/s390/include/asm/vdso.h
+++ b/arch/s390/include/asm/vdso.h
@@ -7,7 +7,7 @@
 #define VDSO32_LBASE    0
 #define VDSO64_LBASE    0
 
-#define VDSO_VERSION_STRING     LINUX_2.6.26
+#define VDSO_VERSION_STRING     LINUX_2.6.29
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 683f6381cc59..64230bc392fa 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -29,9 +29,12 @@ obj-y	+= $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
 
 extra-y                         += head.o init_task.o vmlinux.lds
+extra-y                         += $(if $(CONFIG_64BIT),head64.o,head31.o)
 
 obj-$(CONFIG_MODULES)           += s390_ksyms.o module.o
 obj-$(CONFIG_SMP)               += smp.o topology.o
+obj-$(CONFIG_SMP)               += $(if $(CONFIG_64BIT),switch_cpu64.o, \
+                                                        switch_cpu.o)
 obj-$(CONFIG_HIBERNATION)       += suspend.o swsusp_asm64.o
 obj-$(CONFIG_AUDIT)             += audit.o
 compat-obj-$(CONFIG_AUDIT)      += compat_audit.o
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index 63e46433e81d..08db736dded0 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -4,18 +4,27 @@
  * and format the required data.
  */
 
-#include <linux/sched.h>
+#define ASM_OFFSETS_C
+
 #include <linux/kbuild.h>
+#include <linux/sched.h>
 #include <asm/vdso.h>
 #include <asm/sigp.h>
 
+/*
+ * Make sure that the compiler is new enough. We want a compiler that
+ * is known to work with the "Q" assembler constraint.
+ */
+#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
+#error Your compiler is too old; please use version 3.3.3 or newer
+#endif
+
 int main(void)
 {
         DEFINE(__THREAD_info, offsetof(struct task_struct, stack));
         DEFINE(__THREAD_ksp, offsetof(struct task_struct, thread.ksp));
         DEFINE(__THREAD_per, offsetof(struct task_struct, thread.per_info));
-        DEFINE(__THREAD_mm_segment,
-               offsetof(struct task_struct, thread.mm_segment));
+        DEFINE(__THREAD_mm_segment, offsetof(struct task_struct, thread.mm_segment));
         BLANK();
         DEFINE(__TASK_pid, offsetof(struct task_struct, pid));
         BLANK();
@@ -52,18 +61,94 @@ int main(void)
         DEFINE(__VDSO_WTOM_NSEC, offsetof(struct vdso_data, wtom_clock_nsec));
         DEFINE(__VDSO_TIMEZONE, offsetof(struct vdso_data, tz_minuteswest));
         DEFINE(__VDSO_ECTG_OK, offsetof(struct vdso_data, ectg_available));
-        DEFINE(__VDSO_ECTG_BASE,
-               offsetof(struct vdso_per_cpu_data, ectg_timer_base));
-        DEFINE(__VDSO_ECTG_USER,
-               offsetof(struct vdso_per_cpu_data, ectg_user_time));
+        DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base));
+        DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time));
         /* constants used by the vdso */
         DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
         DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
         DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
+        BLANK();
         /* constants for SIGP */
         DEFINE(__SIGP_STOP, sigp_stop);
         DEFINE(__SIGP_RESTART, sigp_restart);
         DEFINE(__SIGP_SENSE, sigp_sense);
         DEFINE(__SIGP_INITIAL_CPU_RESET, sigp_initial_cpu_reset);
+        BLANK();
+        /* lowcore offsets */
+        DEFINE(__LC_EXT_PARAMS, offsetof(struct _lowcore, ext_params));
+        DEFINE(__LC_CPU_ADDRESS, offsetof(struct _lowcore, cpu_addr));
+        DEFINE(__LC_EXT_INT_CODE, offsetof(struct _lowcore, ext_int_code));
+        DEFINE(__LC_SVC_ILC, offsetof(struct _lowcore, svc_ilc));
+        DEFINE(__LC_SVC_INT_CODE, offsetof(struct _lowcore, svc_code));
+        DEFINE(__LC_PGM_ILC, offsetof(struct _lowcore, pgm_ilc));
+        DEFINE(__LC_PGM_INT_CODE, offsetof(struct _lowcore, pgm_code));
+        DEFINE(__LC_PER_ATMID, offsetof(struct _lowcore, per_perc_atmid));
+        DEFINE(__LC_PER_ADDRESS, offsetof(struct _lowcore, per_address));
+        DEFINE(__LC_PER_ACCESS_ID, offsetof(struct _lowcore, per_access_id));
+        DEFINE(__LC_AR_MODE_ID, offsetof(struct _lowcore, ar_access_id));
+        DEFINE(__LC_SUBCHANNEL_ID, offsetof(struct _lowcore, subchannel_id));
+        DEFINE(__LC_SUBCHANNEL_NR, offsetof(struct _lowcore, subchannel_nr));
+        DEFINE(__LC_IO_INT_PARM, offsetof(struct _lowcore, io_int_parm));
+        DEFINE(__LC_IO_INT_WORD, offsetof(struct _lowcore, io_int_word));
+        DEFINE(__LC_STFL_FAC_LIST, offsetof(struct _lowcore, stfl_fac_list));
+        DEFINE(__LC_MCCK_CODE, offsetof(struct _lowcore, mcck_interruption_code));
+        DEFINE(__LC_DUMP_REIPL, offsetof(struct _lowcore, ipib));
+        BLANK();
+        DEFINE(__LC_RST_NEW_PSW, offsetof(struct _lowcore, restart_psw));
+        DEFINE(__LC_RST_OLD_PSW, offsetof(struct _lowcore, restart_old_psw));
+        DEFINE(__LC_EXT_OLD_PSW, offsetof(struct _lowcore, external_old_psw));
+        DEFINE(__LC_SVC_OLD_PSW, offsetof(struct _lowcore, svc_old_psw));
+        DEFINE(__LC_PGM_OLD_PSW, offsetof(struct _lowcore, program_old_psw));
+        DEFINE(__LC_MCK_OLD_PSW, offsetof(struct _lowcore, mcck_old_psw));
+        DEFINE(__LC_IO_OLD_PSW, offsetof(struct _lowcore, io_old_psw));
+        DEFINE(__LC_EXT_NEW_PSW, offsetof(struct _lowcore, external_new_psw));
+        DEFINE(__LC_SVC_NEW_PSW, offsetof(struct _lowcore, svc_new_psw));
+        DEFINE(__LC_PGM_NEW_PSW, offsetof(struct _lowcore, program_new_psw));
+        DEFINE(__LC_MCK_NEW_PSW, offsetof(struct _lowcore, mcck_new_psw));
+        DEFINE(__LC_IO_NEW_PSW, offsetof(struct _lowcore, io_new_psw));
+        DEFINE(__LC_SAVE_AREA, offsetof(struct _lowcore, save_area));
+        DEFINE(__LC_RETURN_PSW, offsetof(struct _lowcore, return_psw));
+        DEFINE(__LC_RETURN_MCCK_PSW, offsetof(struct _lowcore, return_mcck_psw));
+        DEFINE(__LC_SYNC_ENTER_TIMER, offsetof(struct _lowcore, sync_enter_timer));
+        DEFINE(__LC_ASYNC_ENTER_TIMER, offsetof(struct _lowcore, async_enter_timer));
+        DEFINE(__LC_EXIT_TIMER, offsetof(struct _lowcore, exit_timer));
+        DEFINE(__LC_USER_TIMER, offsetof(struct _lowcore, user_timer));
+        DEFINE(__LC_SYSTEM_TIMER, offsetof(struct _lowcore, system_timer));
+        DEFINE(__LC_STEAL_TIMER, offsetof(struct _lowcore, steal_timer));
+        DEFINE(__LC_LAST_UPDATE_TIMER, offsetof(struct _lowcore, last_update_timer));
+        DEFINE(__LC_LAST_UPDATE_CLOCK, offsetof(struct _lowcore, last_update_clock));
+        DEFINE(__LC_CURRENT, offsetof(struct _lowcore, current_task));
+        DEFINE(__LC_THREAD_INFO, offsetof(struct _lowcore, thread_info));
+        DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
+        DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
+        DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
+        DEFINE(__LC_KERNEL_ASCE, offsetof(struct _lowcore, kernel_asce));
+        DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
+        DEFINE(__LC_USER_EXEC_ASCE, offsetof(struct _lowcore, user_exec_asce));
+        DEFINE(__LC_CPUID, offsetof(struct _lowcore, cpu_id));
+        DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
+        DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
+        DEFINE(__LC_FTRACE_FUNC, offsetof(struct _lowcore, ftrace_func));
+        DEFINE(__LC_IRB, offsetof(struct _lowcore, irb));
+        DEFINE(__LC_CPU_TIMER_SAVE_AREA, offsetof(struct _lowcore, cpu_timer_save_area));
+        DEFINE(__LC_CLOCK_COMP_SAVE_AREA, offsetof(struct _lowcore, clock_comp_save_area));
+        DEFINE(__LC_PSW_SAVE_AREA, offsetof(struct _lowcore, psw_save_area));
+        DEFINE(__LC_PREFIX_SAVE_AREA, offsetof(struct _lowcore, prefixreg_save_area));
+        DEFINE(__LC_AREGS_SAVE_AREA, offsetof(struct _lowcore, access_regs_save_area));
+        DEFINE(__LC_FPREGS_SAVE_AREA, offsetof(struct _lowcore, floating_pt_save_area));
+        DEFINE(__LC_GPREGS_SAVE_AREA, offsetof(struct _lowcore, gpregs_save_area));
+        DEFINE(__LC_CREGS_SAVE_AREA, offsetof(struct _lowcore, cregs_save_area));
+#ifdef CONFIG_32BIT
+        DEFINE(__LC_PFAULT_INTPARM, offsetof(struct _lowcore, ext_params));
+        DEFINE(SAVE_AREA_BASE, offsetof(struct _lowcore, extended_save_area_addr));
+#else /* CONFIG_32BIT */
+        DEFINE(__LC_PFAULT_INTPARM, offsetof(struct _lowcore, ext_params2));
+        DEFINE(__LC_EXT_PARAMS2, offsetof(struct _lowcore, ext_params2));
+        DEFINE(SAVE_AREA_BASE, offsetof(struct _lowcore, floating_pt_save_area));
+        DEFINE(__LC_PASTE, offsetof(struct _lowcore, paste));
+        DEFINE(__LC_FP_CREG_SAVE_AREA, offsetof(struct _lowcore, fpt_creg_save_area));
+        DEFINE(__LC_LAST_BREAK, offsetof(struct _lowcore, breaking_event_addr));
+        DEFINE(__LC_VDSO_PER_CPU, offsetof(struct _lowcore, vdso_per_cpu_data));
+#endif /* CONFIG_32BIT */
         return 0;
 }
diff --git a/arch/s390/kernel/base.S b/arch/s390/kernel/base.S
index dc7e5259770f..15e46ca94335 100644
--- a/arch/s390/kernel/base.S
+++ b/arch/s390/kernel/base.S
@@ -6,8 +6,8 @@
  *               Michael Holzheu <holzheu@de.ibm.com>
  */
 
+#include <asm/asm-offsets.h>
 #include <asm/ptrace.h>
-#include <asm/lowcore.h>
 
 #ifdef CONFIG_64BIT
 
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index db943a7ec513..b39b27d68b45 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -86,10 +86,17 @@ enum {
         U4_12,  /* 4 bit unsigned value starting at 12 */
         U4_16,  /* 4 bit unsigned value starting at 16 */
         U4_20,  /* 4 bit unsigned value starting at 20 */
+        U4_32,  /* 4 bit unsigned value starting at 32 */
         U8_8,   /* 8 bit unsigned value starting at 8 */
         U8_16,  /* 8 bit unsigned value starting at 16 */
+        U8_24,  /* 8 bit unsigned value starting at 24 */
+        U8_32,  /* 8 bit unsigned value starting at 32 */
+        I8_8,   /* 8 bit signed value starting at 8 */
+        I8_32,  /* 8 bit signed value starting at 32 */
         I16_16, /* 16 bit signed value starting at 16 */
+        I16_32, /* 32 bit signed value starting at 16 */
         U16_16, /* 16 bit unsigned value starting at 16 */
+        U16_32, /* 32 bit unsigned value starting at 16 */
         J16_16, /* PC relative jump offset at 16 */
         J32_16, /* PC relative long offset at 16 */
         I32_16, /* 32 bit signed value starting at 16 */
@@ -104,21 +111,37 @@ enum {
  */
 enum {
         INSTR_INVALID,
-        INSTR_E, INSTR_RIE_RRP, INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU,
-        INSTR_RIL_UP, INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP,
+        INSTR_E,
+        INSTR_RIE_R0IU, INSTR_RIE_R0UU, INSTR_RIE_RRP, INSTR_RIE_RRPU,
+        INSTR_RIE_RRUUU, INSTR_RIE_RUPI, INSTR_RIE_RUPU,
+        INSTR_RIL_RI, INSTR_RIL_RP, INSTR_RIL_RU, INSTR_RIL_UP,
+        INSTR_RIS_R0RDU, INSTR_RIS_R0UU, INSTR_RIS_RURDI, INSTR_RIS_RURDU,
+        INSTR_RI_RI, INSTR_RI_RP, INSTR_RI_RU, INSTR_RI_UP,
         INSTR_RRE_00, INSTR_RRE_0R, INSTR_RRE_AA, INSTR_RRE_AR, INSTR_RRE_F0,
-        INSTR_RRE_FF, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF, INSTR_RRE_RR,
-        INSTR_RRE_RR_OPT, INSTR_RRF_F0FF, INSTR_RRF_FUFF, INSTR_RRF_M0RR,
-        INSTR_RRF_R0RR, INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF,
+        INSTR_RRE_FF, INSTR_RRE_FR, INSTR_RRE_R0, INSTR_RRE_RA, INSTR_RRE_RF,
+        INSTR_RRE_RR, INSTR_RRE_RR_OPT,
+        INSTR_RRF_0UFF, INSTR_RRF_F0FF, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
+        INSTR_RRF_FFRU, INSTR_RRF_FUFF, INSTR_RRF_M0RR, INSTR_RRF_R0RR,
+        INSTR_RRF_RURR, INSTR_RRF_U0FF, INSTR_RRF_U0RF, INSTR_RRF_U0RR,
+        INSTR_RRF_UUFF, INSTR_RRR_F0FF, INSTR_RRS_RRRDU,
         INSTR_RR_FF, INSTR_RR_R0, INSTR_RR_RR, INSTR_RR_U0, INSTR_RR_UR,
-        INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD, INSTR_RSI_RRP,
-        INSTR_RSL_R0RD, INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD,
-        INSTR_RSY_RURD, INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD,
-        INSTR_RS_RRRD, INSTR_RS_RURD, INSTR_RXE_FRRD, INSTR_RXE_RRRD,
-        INSTR_RXF_FRRDF, INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RX_FRRD,
-        INSTR_RX_RRRD, INSTR_RX_URRD, INSTR_SIY_URD, INSTR_SI_URD,
-        INSTR_SSE_RDRD, INSTR_SSF_RRDRD, INSTR_SS_L0RDRD, INSTR_SS_LIRDRD,
-        INSTR_SS_LLRDRD, INSTR_SS_RRRDRD, INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3,
+        INSTR_RSE_CCRD, INSTR_RSE_RRRD, INSTR_RSE_RURD,
+        INSTR_RSI_RRP,
+        INSTR_RSL_R0RD,
+        INSTR_RSY_AARD, INSTR_RSY_CCRD, INSTR_RSY_RRRD, INSTR_RSY_RURD,
+        INSTR_RS_AARD, INSTR_RS_CCRD, INSTR_RS_R0RD, INSTR_RS_RRRD,
+        INSTR_RS_RURD,
+        INSTR_RXE_FRRD, INSTR_RXE_RRRD,
+        INSTR_RXF_FRRDF,
+        INSTR_RXY_FRRD, INSTR_RXY_RRRD, INSTR_RXY_URRD,
+        INSTR_RX_FRRD, INSTR_RX_RRRD, INSTR_RX_URRD,
+        INSTR_SIL_RDI, INSTR_SIL_RDU,
+        INSTR_SIY_IRD, INSTR_SIY_URD,
+        INSTR_SI_URD,
+        INSTR_SSE_RDRD,
+        INSTR_SSF_RRDRD,
+        INSTR_SS_L0RDRD, INSTR_SS_LIRDRD, INSTR_SS_LLRDRD, INSTR_SS_RRRDRD,
+        INSTR_SS_RRRDRD2, INSTR_SS_RRRDRD3,
         INSTR_S_00, INSTR_S_RD,
 };
 
@@ -129,7 +152,7 @@ struct operand {
 };
 
 struct insn {
-        const char name[5];
+        const char name[6];
         unsigned char opfrag;
         unsigned char format;
 };
@@ -170,11 +193,16 @@ static const struct operand operands[] =
         [U4_12]  = {  4, 12, 0 },
         [U4_16]  = {  4, 16, 0 },
         [U4_20]  = {  4, 20, 0 },
+        [U4_32]  = {  4, 32, 0 },
         [U8_8]   = {  8,  8, 0 },
         [U8_16]  = {  8, 16, 0 },
+        [U8_24]  = {  8, 24, 0 },
+        [U8_32]  = {  8, 32, 0 },
         [I16_16] = { 16, 16, OPERAND_SIGNED },
         [U16_16] = { 16, 16, 0 },
+        [U16_32] = { 16, 32, 0 },
         [J16_16] = { 16, 16, OPERAND_PCREL },
+        [I16_32] = { 16, 32, OPERAND_SIGNED },
         [J32_16] = { 32, 16, OPERAND_PCREL },
         [I32_16] = { 32, 16, OPERAND_SIGNED },
         [U32_16] = { 32, 16, 0 },
@@ -183,82 +211,93 @@ static const struct operand operands[] =
 };
 
 static const unsigned char formats[][7] = {
-        [INSTR_E]         = { 0xff, 0,0,0,0,0,0 },             /* e.g. pr    */
-        [INSTR_RIE_RRP]   = { 0xff, R_8,R_12,J16_16,0,0,0 },   /* e.g. brxhg */
-        [INSTR_RIL_RP]    = { 0x0f, R_8,J32_16,0,0,0,0 },      /* e.g. brasl */
-        [INSTR_RIL_UP]    = { 0x0f, U4_8,J32_16,0,0,0,0 },     /* e.g. brcl  */
-        [INSTR_RIL_RI]    = { 0x0f, R_8,I32_16,0,0,0,0 },      /* e.g. afi   */
-        [INSTR_RIL_RU]    = { 0x0f, R_8,U32_16,0,0,0,0 },      /* e.g. alfi  */
-        [INSTR_RI_RI]     = { 0x0f, R_8,I16_16,0,0,0,0 },      /* e.g. ahi   */
-        [INSTR_RI_RP]     = { 0x0f, R_8,J16_16,0,0,0,0 },      /* e.g. brct  */
-        [INSTR_RI_RU]     = { 0x0f, R_8,U16_16,0,0,0,0 },      /* e.g. tml   */
-        [INSTR_RI_UP]     = { 0x0f, U4_8,J16_16,0,0,0,0 },     /* e.g. brc   */
-        [INSTR_RRE_00]    = { 0xff, 0,0,0,0,0,0 },             /* e.g. palb  */
-        [INSTR_RRE_0R]    = { 0xff, R_28,0,0,0,0,0 },          /* e.g. tb    */
-        [INSTR_RRE_AA]    = { 0xff, A_24,A_28,0,0,0,0 },       /* e.g. cpya  */
-        [INSTR_RRE_AR]    = { 0xff, A_24,R_28,0,0,0,0 },       /* e.g. sar   */
-        [INSTR_RRE_F0]    = { 0xff, F_24,0,0,0,0,0 },          /* e.g. sqer  */
-        [INSTR_RRE_FF]    = { 0xff, F_24,F_28,0,0,0,0 },       /* e.g. debr  */
-        [INSTR_RRE_R0]    = { 0xff, R_24,0,0,0,0,0 },          /* e.g. ipm   */
-        [INSTR_RRE_RA]    = { 0xff, R_24,A_28,0,0,0,0 },       /* e.g. ear   */
-        [INSTR_RRE_RF]    = { 0xff, R_24,F_28,0,0,0,0 },       /* e.g. cefbr */
-        [INSTR_RRE_RR]    = { 0xff, R_24,R_28,0,0,0,0 },       /* e.g. lura  */
-        [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 },      /* efpc, sfpc */
-        [INSTR_RRF_F0FF]  = { 0xff, F_16,F_24,F_28,0,0,0 },    /* e.g. madbr */
-        [INSTR_RRF_FUFF]  = { 0xff, F_24,F_16,F_28,U4_20,0,0 },/* e.g. didbr */
-        [INSTR_RRF_RURR]  = { 0xff, R_24,R_28,R_16,U4_20,0,0 },/* e.g. .insn */
-        [INSTR_RRF_R0RR]  = { 0xff, R_24,R_16,R_28,0,0,0 },    /* e.g. idte  */
-        [INSTR_RRF_U0FF]  = { 0xff, F_24,U4_16,F_28,0,0,0 },   /* e.g. fixr  */
-        [INSTR_RRF_U0RF]  = { 0xff, R_24,U4_16,F_28,0,0,0 },   /* e.g. cfebr */
-        [INSTR_RRF_M0RR]  = { 0xff, R_24,R_28,M_16,0,0,0 },    /* e.g. sske  */
-        [INSTR_RR_FF]     = { 0xff, F_8,F_12,0,0,0,0 },        /* e.g. adr   */
-        [INSTR_RR_R0]     = { 0xff, R_8, 0,0,0,0,0 },          /* e.g. spm   */
-        [INSTR_RR_RR]     = { 0xff, R_8,R_12,0,0,0,0 },        /* e.g. lr    */
-        [INSTR_RR_U0]     = { 0xff, U8_8, 0,0,0,0,0 },         /* e.g. svc   */
-        [INSTR_RR_UR]     = { 0xff, U4_8,R_12,0,0,0,0 },       /* e.g. bcr   */
-        [INSTR_RSE_RRRD]  = { 0xff, R_8,R_12,D_20,B_16,0,0 },  /* e.g. lmh   */
-        [INSTR_RSE_CCRD]  = { 0xff, C_8,C_12,D_20,B_16,0,0 },  /* e.g. lmh   */
-        [INSTR_RSE_RURD]  = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, /* e.g. icmh  */
-        [INSTR_RSL_R0RD]  = { 0xff, R_8,D_20,B_16,0,0,0 },     /* e.g. tp    */
-        [INSTR_RSI_RRP]   = { 0xff, R_8,R_12,J16_16,0,0,0 },   /* e.g. brxh  */
-        [INSTR_RSY_RRRD]  = { 0xff, R_8,R_12,D20_20,B_16,0,0 },/* e.g. stmy  */
+        [INSTR_E]         = { 0xff, 0,0,0,0,0,0 },
+        [INSTR_RIE_R0UU]  = { 0xff, R_8,U16_16,U4_32,0,0,0 },
+        [INSTR_RIE_RRPU]  = { 0xff, R_8,R_12,U4_32,J16_16,0,0 },
+        [INSTR_RIE_RRP]   = { 0xff, R_8,R_12,J16_16,0,0,0 },
+        [INSTR_RIE_RRUUU] = { 0xff, R_8,R_12,U8_16,U8_24,U8_32,0 },
+        [INSTR_RIE_RUPI]  = { 0xff, R_8,I8_32,U4_12,J16_16,0,0 },
+        [INSTR_RIL_RI]    = { 0x0f, R_8,I32_16,0,0,0,0 },
+        [INSTR_RIL_RP]    = { 0x0f, R_8,J32_16,0,0,0,0 },
+        [INSTR_RIL_RU]    = { 0x0f, R_8,U32_16,0,0,0,0 },
+        [INSTR_RIL_UP]    = { 0x0f, U4_8,J32_16,0,0,0,0 },
+        [INSTR_RIS_R0RDU] = { 0xff, R_8,U8_32,D_20,B_16,0,0 },
+        [INSTR_RIS_RURDI] = { 0xff, R_8,I8_32,U4_12,D_20,B_16,0 },
+        [INSTR_RIS_RURDU] = { 0xff, R_8,U8_32,U4_12,D_20,B_16,0 },
+        [INSTR_RI_RI]     = { 0x0f, R_8,I16_16,0,0,0,0 },
+        [INSTR_RI_RP]     = { 0x0f, R_8,J16_16,0,0,0,0 },
+        [INSTR_RI_RU]     = { 0x0f, R_8,U16_16,0,0,0,0 },
+        [INSTR_RI_UP]     = { 0x0f, U4_8,J16_16,0,0,0,0 },
+        [INSTR_RRE_00]    = { 0xff, 0,0,0,0,0,0 },
+        [INSTR_RRE_0R]    = { 0xff, R_28,0,0,0,0,0 },
+        [INSTR_RRE_AA]    = { 0xff, A_24,A_28,0,0,0,0 },
+        [INSTR_RRE_AR]    = { 0xff, A_24,R_28,0,0,0,0 },
+        [INSTR_RRE_F0]    = { 0xff, F_24,0,0,0,0,0 },
+        [INSTR_RRE_FF]    = { 0xff, F_24,F_28,0,0,0,0 },
+        [INSTR_RRE_FR]    = { 0xff, F_24,R_28,0,0,0,0 },
+        [INSTR_RRE_R0]    = { 0xff, R_24,0,0,0,0,0 },
+        [INSTR_RRE_RA]    = { 0xff, R_24,A_28,0,0,0,0 },
+        [INSTR_RRE_RF]    = { 0xff, R_24,F_28,0,0,0,0 },
+        [INSTR_RRE_RR]    = { 0xff, R_24,R_28,0,0,0,0 },
+        [INSTR_RRE_RR_OPT]= { 0xff, R_24,RO_28,0,0,0,0 },
+        [INSTR_RRF_0UFF]  = { 0xff, F_24,F_28,U4_20,0,0,0 },
+        [INSTR_RRF_F0FF2] = { 0xff, F_24,F_16,F_28,0,0,0 },
+        [INSTR_RRF_F0FF]  = { 0xff, F_16,F_24,F_28,0,0,0 },
+        [INSTR_RRF_F0FR]  = { 0xff, F_24,F_16,R_28,0,0,0 },
+        [INSTR_RRF_FFRU]  = { 0xff, F_24,F_16,R_28,U4_20,0,0 },
+        [INSTR_RRF_FUFF]  = { 0xff, F_24,F_16,F_28,U4_20,0,0 },
+        [INSTR_RRF_M0RR]  = { 0xff, R_24,R_28,M_16,0,0,0 },
+        [INSTR_RRF_R0RR]  = { 0xff, R_24,R_16,R_28,0,0,0 },
+        [INSTR_RRF_RURR]  = { 0xff, R_24,R_28,R_16,U4_20,0,0 },
+        [INSTR_RRF_U0FF]  = { 0xff, F_24,U4_16,F_28,0,0,0 },
+        [INSTR_RRF_U0RF]  = { 0xff, R_24,U4_16,F_28,0,0,0 },
+        [INSTR_RRF_U0RR]  = { 0xff, R_24,R_28,U4_16,0,0,0 },
+        [INSTR_RRF_UUFF]  = { 0xff, F_24,U4_16,F_28,U4_20,0,0 },
+        [INSTR_RRR_F0FF]  = { 0xff, F_24,F_28,F_16,0,0,0 },
+        [INSTR_RRS_RRRDU] = { 0xff, R_8,R_12,U4_32,D_20,B_16,0 },
+        [INSTR_RR_FF]     = { 0xff, F_8,F_12,0,0,0,0 },
+        [INSTR_RR_R0]     = { 0xff, R_8, 0,0,0,0,0 },
+        [INSTR_RR_RR]     = { 0xff, R_8,R_12,0,0,0,0 },
+        [INSTR_RR_U0]     = { 0xff, U8_8, 0,0,0,0,0 },
+        [INSTR_RR_UR]     = { 0xff, U4_8,R_12,0,0,0,0 },
+        [INSTR_RSE_CCRD]  = { 0xff, C_8,C_12,D_20,B_16,0,0 },
+        [INSTR_RSE_RRRD]  = { 0xff, R_8,R_12,D_20,B_16,0,0 },
+        [INSTR_RSE_RURD]  = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
+        [INSTR_RSI_RRP]   = { 0xff, R_8,R_12,J16_16,0,0,0 },
+        [INSTR_RSL_R0RD]  = { 0xff, D_20,L4_8,B_16,0,0,0 },
+        [INSTR_RSY_AARD]  = { 0xff, A_8,A_12,D20_20,B_16,0,0 },
+        [INSTR_RSY_CCRD]  = { 0xff, C_8,C_12,D20_20,B_16,0,0 },
+        [INSTR_RSY_RRRD]  = { 0xff, R_8,R_12,D20_20,B_16,0,0 },
         [INSTR_RSY_RURD]  = { 0xff, R_8,U4_12,D20_20,B_16,0,0 },
-                                                               /* e.g. icmh  */
-        [INSTR_RSY_AARD]  = { 0xff, A_8,A_12,D20_20,B_16,0,0 },/* e.g. lamy  */
-        [INSTR_RSY_CCRD]  = { 0xff, C_8,C_12,D20_20,B_16,0,0 },/* e.g. lamy  */
-        [INSTR_RS_AARD]   = { 0xff, A_8,A_12,D_20,B_16,0,0 },  /* e.g. lam   */
-        [INSTR_RS_CCRD]   = { 0xff, C_8,C_12,D_20,B_16,0,0 },  /* e.g. lctl  */
-        [INSTR_RS_R0RD]   = { 0xff, R_8,D_20,B_16,0,0,0 },     /* e.g. sll   */
-        [INSTR_RS_RRRD]   = { 0xff, R_8,R_12,D_20,B_16,0,0 },  /* e.g. cs    */
-        [INSTR_RS_RURD]   = { 0xff, R_8,U4_12,D_20,B_16,0,0 }, /* e.g. icm   */
-        [INSTR_RXE_FRRD]  = { 0xff, F_8,D_20,X_12,B_16,0,0 },  /* e.g. axbr  */
-        [INSTR_RXE_RRRD]  = { 0xff, R_8,D_20,X_12,B_16,0,0 },  /* e.g. lg    */
+        [INSTR_RS_AARD]   = { 0xff, A_8,A_12,D_20,B_16,0,0 },
+        [INSTR_RS_CCRD]   = { 0xff, C_8,C_12,D_20,B_16,0,0 },
+        [INSTR_RS_R0RD]   = { 0xff, R_8,D_20,B_16,0,0,0 },
+        [INSTR_RS_RRRD]   = { 0xff, R_8,R_12,D_20,B_16,0,0 },
+        [INSTR_RS_RURD]   = { 0xff, R_8,U4_12,D_20,B_16,0,0 },
+        [INSTR_RXE_FRRD]  = { 0xff, F_8,D_20,X_12,B_16,0,0 },
+        [INSTR_RXE_RRRD]  = { 0xff, R_8,D_20,X_12,B_16,0,0 },
         [INSTR_RXF_FRRDF] = { 0xff, F_32,F_8,D_20,X_12,B_16,0 },
-                                                               /* e.g. madb  */
-        [INSTR_RXY_RRRD]  = { 0xff, R_8,D20_20,X_12,B_16,0,0 },/* e.g. ly    */
-        [INSTR_RXY_FRRD]  = { 0xff, F_8,D20_20,X_12,B_16,0,0 },/* e.g. ley   */
-        [INSTR_RX_FRRD]   = { 0xff, F_8,D_20,X_12,B_16,0,0 },  /* e.g. ae    */
-        [INSTR_RX_RRRD]   = { 0xff, R_8,D_20,X_12,B_16,0,0 },  /* e.g. l     */
-        [INSTR_RX_URRD]   = { 0xff, U4_8,D_20,X_12,B_16,0,0 }, /* e.g. bc    */
-        [INSTR_SI_URD]    = { 0xff, D_20,B_16,U8_8,0,0,0 },    /* e.g. cli   */
-        [INSTR_SIY_URD]   = { 0xff, D20_20,B_16,U8_8,0,0,0 },  /* e.g. tmy   */
-        [INSTR_SSE_RDRD]  = { 0xff, D_20,B_16,D_36,B_32,0,0 }, /* e.g. mvsdk */
+        [INSTR_RXY_FRRD]  = { 0xff, F_8,D20_20,X_12,B_16,0,0 },
+        [INSTR_RXY_RRRD]  = { 0xff, R_8,D20_20,X_12,B_16,0,0 },
+        [INSTR_RXY_URRD]  = { 0xff, U4_8,D20_20,X_12,B_16,0,0 },
+        [INSTR_RX_FRRD]   = { 0xff, F_8,D_20,X_12,B_16,0,0 },
+        [INSTR_RX_RRRD]   = { 0xff, R_8,D_20,X_12,B_16,0,0 },
+        [INSTR_RX_URRD]   = { 0xff, U4_8,D_20,X_12,B_16,0,0 },
+        [INSTR_SIL_RDI]   = { 0xff, D_20,B_16,I16_32,0,0,0 },
+        [INSTR_SIL_RDU]   = { 0xff, D_20,B_16,U16_32,0,0,0 },
+        [INSTR_SIY_IRD]   = { 0xff, D20_20,B_16,I8_8,0,0,0 },
+        [INSTR_SIY_URD]   = { 0xff, D20_20,B_16,U8_8,0,0,0 },
+        [INSTR_SI_URD]    = { 0xff, D_20,B_16,U8_8,0,0,0 },
+        [INSTR_SSE_RDRD]  = { 0xff, D_20,B_16,D_36,B_32,0,0 },
+        [INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 },
         [INSTR_SS_L0RDRD] = { 0xff, D_20,L8_8,B_16,D_36,B_32,0 },
-                                                               /* e.g. mvc   */
         [INSTR_SS_LIRDRD] = { 0xff, D_20,L4_8,B_16,D_36,B_32,U4_12 },
-                                                               /* e.g. srp   */
         [INSTR_SS_LLRDRD] = { 0xff, D_20,L4_8,B_16,D_36,L4_12,B_32 },
-                                                               /* e.g. pack  */
-        [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 },
-                                                               /* e.g. mvck  */
         [INSTR_SS_RRRDRD2]= { 0xff, R_8,D_20,B_16,R_12,D_36,B_32 },
-                                                               /* e.g. plo   */
         [INSTR_SS_RRRDRD3]= { 0xff, R_8,R_12,D_20,B_16,D_36,B_32 },
-                                                               /* e.g. lmd   */
-        [INSTR_S_00]      = { 0xff, 0,0,0,0,0,0 },             /* e.g. hsch  */
-        [INSTR_S_RD]      = { 0xff, D_20,B_16,0,0,0,0 },       /* e.g. lpsw  */
-        [INSTR_SSF_RRDRD] = { 0x00, D_20,B_16,D_36,B_32,R_8,0 },
-                                                               /* e.g. mvcos */
+        [INSTR_SS_RRRDRD] = { 0xff, D_20,R_8,B_16,D_36,B_32,R_12 },
+        [INSTR_S_00]      = { 0xff, 0,0,0,0,0,0 },
+        [INSTR_S_RD]      = { 0xff, D_20,B_16,0,0,0,0 },
 };
 
 static struct insn opcode[] = {
@@ -454,6 +493,8 @@ static struct insn opcode[] = {
 static struct insn opcode_01[] = {
 #ifdef CONFIG_64BIT
         { "sam64", 0x0e, INSTR_E },
+        { "pfpo", 0x0a, INSTR_E },
+        { "ptff", 0x04, INSTR_E },
 #endif
         { "pr", 0x01, INSTR_E },
         { "upt", 0x02, INSTR_E },
@@ -519,6 +560,8 @@ static struct insn opcode_b2[] = {
         { "cutfu", 0xa7, INSTR_RRF_M0RR },
         { "stfle", 0xb0, INSTR_S_RD },
         { "lpswe", 0xb2, INSTR_S_RD },
+        { "srnmt", 0xb9, INSTR_S_RD },
+        { "lfas", 0xbd, INSTR_S_RD },
 #endif
         { "stidp", 0x02, INSTR_S_RD },
         { "sck", 0x04, INSTR_S_RD },
@@ -589,7 +632,6 @@ static struct insn opcode_b2[] = {
         { "clst", 0x5d, INSTR_RRE_RR },
         { "srst", 0x5e, INSTR_RRE_RR },
         { "cmpsc", 0x63, INSTR_RRE_RR },
-        { "cmpsc", 0x63, INSTR_RRE_RR },
         { "siga", 0x74, INSTR_S_RD },
         { "xsch", 0x76, INSTR_S_00 },
         { "rp", 0x77, INSTR_S_RD },
@@ -630,6 +672,57 @@ static struct insn opcode_b3[] = {
         { "cger", 0xc8, INSTR_RRF_U0RF },
         { "cgdr", 0xc9, INSTR_RRF_U0RF },
         { "cgxr", 0xca, INSTR_RRF_U0RF },
+        { "lpdfr", 0x70, INSTR_RRE_FF },
+        { "lndfr", 0x71, INSTR_RRE_FF },
+        { "cpsdr", 0x72, INSTR_RRF_F0FF2 },
+        { "lcdfr", 0x73, INSTR_RRE_FF },
+        { "ldgr", 0xc1, INSTR_RRE_FR },
+        { "lgdr", 0xcd, INSTR_RRE_RF },
+        { "adtr", 0xd2, INSTR_RRR_F0FF },
+        { "axtr", 0xda, INSTR_RRR_F0FF },
+        { "cdtr", 0xe4, INSTR_RRE_FF },
+        { "cxtr", 0xec, INSTR_RRE_FF },
+        { "kdtr", 0xe0, INSTR_RRE_FF },
+        { "kxtr", 0xe8, INSTR_RRE_FF },
+        { "cedtr", 0xf4, INSTR_RRE_FF },
+        { "cextr", 0xfc, INSTR_RRE_FF },
+        { "cdgtr", 0xf1, INSTR_RRE_FR },
+        { "cxgtr", 0xf9, INSTR_RRE_FR },
+        { "cdstr", 0xf3, INSTR_RRE_FR },
+        { "cxstr", 0xfb, INSTR_RRE_FR },
+        { "cdutr", 0xf2, INSTR_RRE_FR },
+        { "cxutr", 0xfa, INSTR_RRE_FR },
+        { "cgdtr", 0xe1, INSTR_RRF_U0RF },
+        { "cgxtr", 0xe9, INSTR_RRF_U0RF },
+        { "csdtr", 0xe3, INSTR_RRE_RF },
+        { "csxtr", 0xeb, INSTR_RRE_RF },
+        { "cudtr", 0xe2, INSTR_RRE_RF },
+        { "cuxtr", 0xea, INSTR_RRE_RF },
+        { "ddtr", 0xd1, INSTR_RRR_F0FF },
+        { "dxtr", 0xd9, INSTR_RRR_F0FF },
+        { "eedtr", 0xe5, INSTR_RRE_RF },
+        { "eextr", 0xed, INSTR_RRE_RF },
+        { "esdtr", 0xe7, INSTR_RRE_RF },
+        { "esxtr", 0xef, INSTR_RRE_RF },
+        { "iedtr", 0xf6, INSTR_RRF_F0FR },
+        { "iextr", 0xfe, INSTR_RRF_F0FR },
+        { "ltdtr", 0xd6, INSTR_RRE_FF },
+        { "ltxtr", 0xde, INSTR_RRE_FF },
+        { "fidtr", 0xd7, INSTR_RRF_UUFF },
+        { "fixtr", 0xdf, INSTR_RRF_UUFF },
+        { "ldetr", 0xd4, INSTR_RRF_0UFF },
+        { "lxdtr", 0xdc, INSTR_RRF_0UFF },
+        { "ledtr", 0xd5, INSTR_RRF_UUFF },
+        { "ldxtr", 0xdd, INSTR_RRF_UUFF },
+        { "mdtr", 0xd0, INSTR_RRR_F0FF },
+        { "mxtr", 0xd8, INSTR_RRR_F0FF },
+        { "qadtr", 0xf5, INSTR_RRF_FUFF },
+        { "qaxtr", 0xfd, INSTR_RRF_FUFF },
+        { "rrdtr", 0xf7, INSTR_RRF_FFRU },
+        { "rrxtr", 0xff, INSTR_RRF_FFRU },
+        { "sfasr", 0x85, INSTR_RRE_R0 },
+        { "sdtr", 0xd3, INSTR_RRR_F0FF },
+        { "sxtr", 0xdb, INSTR_RRR_F0FF },
 #endif
         { "lpebr", 0x00, INSTR_RRE_FF },
         { "lnebr", 0x01, INSTR_RRE_FF },
@@ -780,6 +873,14 @@ static struct insn opcode_b9[] = {
         { "cu24", 0xb1, INSTR_RRF_M0RR },
         { "cu41", 0xb2, INSTR_RRF_M0RR },
         { "cu42", 0xb3, INSTR_RRF_M0RR },
+        { "crt", 0x72, INSTR_RRF_U0RR },
+        { "cgrt", 0x60, INSTR_RRF_U0RR },
+        { "clrt", 0x73, INSTR_RRF_U0RR },
+        { "clgrt", 0x61, INSTR_RRF_U0RR },
+        { "ptf", 0xa2, INSTR_RRE_R0 },
+        { "pfmf", 0xaf, INSTR_RRE_RR },
+        { "trte", 0xbf, INSTR_RRF_M0RR },
+        { "trtre", 0xbd, INSTR_RRF_M0RR },
 #endif
         { "kmac", 0x1e, INSTR_RRE_RR },
         { "lrvr", 0x1f, INSTR_RRE_RR },
@@ -835,6 +936,43 @@ static struct insn opcode_c2[] = {
         { "cfi", 0x0d, INSTR_RIL_RI },
         { "clgfi", 0x0e, INSTR_RIL_RU },
         { "clfi", 0x0f, INSTR_RIL_RU },
+        { "msfi", 0x01, INSTR_RIL_RI },
+        { "msgfi", 0x00, INSTR_RIL_RI },
+#endif
+        { "", 0, INSTR_INVALID }
+};
+
+static struct insn opcode_c4[] = {
+#ifdef CONFIG_64BIT
+        { "lrl", 0x0d, INSTR_RIL_RP },
+        { "lgrl", 0x08, INSTR_RIL_RP },
+        { "lgfrl", 0x0c, INSTR_RIL_RP },
+        { "lhrl", 0x05, INSTR_RIL_RP },
+        { "lghrl", 0x04, INSTR_RIL_RP },
+        { "llgfrl", 0x0e, INSTR_RIL_RP },
+        { "llhrl", 0x02, INSTR_RIL_RP },
+        { "llghrl", 0x06, INSTR_RIL_RP },
+        { "strl", 0x0f, INSTR_RIL_RP },
+        { "stgrl", 0x0b, INSTR_RIL_RP },
+        { "sthrl", 0x07, INSTR_RIL_RP },
+#endif
+        { "", 0, INSTR_INVALID }
+};
+
+static struct insn opcode_c6[] = {
+#ifdef CONFIG_64BIT
+        { "crl", 0x0d, INSTR_RIL_RP },
+        { "cgrl", 0x08, INSTR_RIL_RP },
+        { "cgfrl", 0x0c, INSTR_RIL_RP },
+        { "chrl", 0x05, INSTR_RIL_RP },
+        { "cghrl", 0x04, INSTR_RIL_RP },
+        { "clrl", 0x0f, INSTR_RIL_RP },
+        { "clgrl", 0x0a, INSTR_RIL_RP },
+        { "clgfrl", 0x0e, INSTR_RIL_RP },
+        { "clhrl", 0x07, INSTR_RIL_RP },
+        { "clghrl", 0x06, INSTR_RIL_RP },
+        { "pfdrl", 0x02, INSTR_RIL_UP },
+        { "exrl", 0x00, INSTR_RIL_RP },
 #endif
         { "", 0, INSTR_INVALID }
 };
@@ -842,6 +980,8 @@ static struct insn opcode_c2[] = {
 static struct insn opcode_c8[] = {
 #ifdef CONFIG_64BIT
         { "mvcos", 0x00, INSTR_SSF_RRDRD },
+        { "ectg", 0x01, INSTR_SSF_RRDRD },
+        { "csst", 0x02, INSTR_SSF_RRDRD },
 #endif
         { "", 0, INSTR_INVALID }
 };
@@ -917,6 +1057,12 @@ static struct insn opcode_e3[] = {
         { "llgh", 0x91, INSTR_RXY_RRRD },
         { "llc", 0x94, INSTR_RXY_RRRD },
         { "llh", 0x95, INSTR_RXY_RRRD },
+        { "cgh", 0x34, INSTR_RXY_RRRD },
+        { "laey", 0x75, INSTR_RXY_RRRD },
+        { "ltgf", 0x32, INSTR_RXY_RRRD },
+        { "mfy", 0x5c, INSTR_RXY_RRRD },
+        { "mhy", 0x7c, INSTR_RXY_RRRD },
+        { "pfd", 0x36, INSTR_RXY_URRD },
 #endif
         { "lrv", 0x1e, INSTR_RXY_RRRD },
         { "lrvh", 0x1f, INSTR_RXY_RRRD },
@@ -931,6 +1077,15 @@ static struct insn opcode_e3[] = {
 static struct insn opcode_e5[] = {
 #ifdef CONFIG_64BIT
         { "strag", 0x02, INSTR_SSE_RDRD },
+        { "chhsi", 0x54, INSTR_SIL_RDI },
+        { "chsi", 0x5c, INSTR_SIL_RDI },
+        { "cghsi", 0x58, INSTR_SIL_RDI },
+        { "clhhsi", 0x55, INSTR_SIL_RDU },
+        { "clfhsi", 0x5d, INSTR_SIL_RDU },
+        { "clghsi", 0x59, INSTR_SIL_RDU },
+        { "mvhhi", 0x44, INSTR_SIL_RDI },
+        { "mvhi", 0x4c, INSTR_SIL_RDI },
+        { "mvghi", 0x48, INSTR_SIL_RDI },
 #endif
         { "lasp", 0x00, INSTR_SSE_RDRD },
         { "tprot", 0x01, INSTR_SSE_RDRD },
@@ -977,6 +1132,11 @@ static struct insn opcode_eb[] = {
         { "lmy", 0x98, INSTR_RSY_RRRD },
         { "lamy", 0x9a, INSTR_RSY_AARD },
         { "stamy", 0x9b, INSTR_RSY_AARD },
+        { "asi", 0x6a, INSTR_SIY_IRD },
+        { "agsi", 0x7a, INSTR_SIY_IRD },
+        { "alsi", 0x6e, INSTR_SIY_IRD },
+        { "algsi", 0x7e, INSTR_SIY_IRD },
+        { "ecag", 0x4c, INSTR_RSY_RRRD },
 #endif
         { "rll", 0x1d, INSTR_RSY_RRRD },
         { "mvclu", 0x8e, INSTR_RSY_RRRD },
@@ -988,6 +1148,30 @@ static struct insn opcode_ec[] = {
 #ifdef CONFIG_64BIT
         { "brxhg", 0x44, INSTR_RIE_RRP },
         { "brxlg", 0x45, INSTR_RIE_RRP },
+        { "crb", 0xf6, INSTR_RRS_RRRDU },
+        { "cgrb", 0xe4, INSTR_RRS_RRRDU },
+        { "crj", 0x76, INSTR_RIE_RRPU },
+        { "cgrj", 0x64, INSTR_RIE_RRPU },
+        { "cib", 0xfe, INSTR_RIS_RURDI },
+        { "cgib", 0xfc, INSTR_RIS_RURDI },
+        { "cij", 0x7e, INSTR_RIE_RUPI },
+        { "cgij", 0x7c, INSTR_RIE_RUPI },
+        { "cit", 0x72, INSTR_RIE_R0IU },
+        { "cgit", 0x70, INSTR_RIE_R0IU },
+        { "clrb", 0xf7, INSTR_RRS_RRRDU },
+        { "clgrb", 0xe5, INSTR_RRS_RRRDU },
+        { "clrj", 0x77, INSTR_RIE_RRPU },
+        { "clgrj", 0x65, INSTR_RIE_RRPU },
+        { "clib", 0xff, INSTR_RIS_RURDU },
+        { "clgib", 0xfd, INSTR_RIS_RURDU },
+        { "clij", 0x7f, INSTR_RIE_RUPU },
+        { "clgij", 0x7d, INSTR_RIE_RUPU },
+        { "clfit", 0x73, INSTR_RIE_R0UU },
+        { "clgit", 0x71, INSTR_RIE_R0UU },
+        { "rnsbg", 0x54, INSTR_RIE_RRUUU },
+        { "rxsbg", 0x57, INSTR_RIE_RRUUU },
+        { "rosbg", 0x56, INSTR_RIE_RRUUU },
+        { "risbg", 0x55, INSTR_RIE_RRUUU },
 #endif
         { "", 0, INSTR_INVALID }
 };
@@ -1004,6 +1188,16 @@ static struct insn opcode_ed[] = {
         { "ldy", 0x65, INSTR_RXY_FRRD },
         { "stey", 0x66, INSTR_RXY_FRRD },
         { "stdy", 0x67, INSTR_RXY_FRRD },
+        { "sldt", 0x40, INSTR_RXF_FRRDF },
+        { "slxt", 0x48, INSTR_RXF_FRRDF },
+        { "srdt", 0x41, INSTR_RXF_FRRDF },
+        { "srxt", 0x49, INSTR_RXF_FRRDF },
+        { "tdcet", 0x50, INSTR_RXE_FRRD },
+        { "tdcdt", 0x54, INSTR_RXE_FRRD },
+        { "tdcxt", 0x58, INSTR_RXE_FRRD },
+        { "tdget", 0x51, INSTR_RXE_FRRD },
+        { "tdgdt", 0x55, INSTR_RXE_FRRD },
+        { "tdgxt", 0x59, INSTR_RXE_FRRD },
 #endif
         { "ldeb", 0x04, INSTR_RXE_FRRD },
         { "lxdb", 0x05, INSTR_RXE_FRRD },
@@ -1037,6 +1231,7 @@ static struct insn opcode_ed[] = {
         { "mae", 0x2e, INSTR_RXF_FRRDF },
         { "mse", 0x2f, INSTR_RXF_FRRDF },
         { "sqe", 0x34, INSTR_RXE_FRRD },
+        { "sqd", 0x35, INSTR_RXE_FRRD },
         { "mee", 0x37, INSTR_RXE_FRRD },
         { "mad", 0x3e, INSTR_RXF_FRRDF },
         { "msd", 0x3f, INSTR_RXF_FRRDF },
@@ -1117,6 +1312,12 @@ static struct insn *find_insn(unsigned char *code)
         case 0xc2:
                 table = opcode_c2;
                 break;
+        case 0xc4:
+                table = opcode_c4;
+                break;
+        case 0xc6:
+                table = opcode_c6;
+                break;
         case 0xc8:
                 table = opcode_c8;
                 break;
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index e49e9e0c69fd..31d618a443af 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -214,10 +214,13 @@ static __initdata struct sysinfo_3_2_2 vmms __aligned(PAGE_SIZE);
 
 static noinline __init void detect_machine_type(void)
 {
-        /* No VM information? Looks like LPAR */
-        if (stsi(&vmms, 3, 2, 2) == -ENOSYS)
+        /* Check current-configuration-level */
+        if ((stsi(NULL, 0, 0, 0) >> 28) <= 2) {
+                S390_lowcore.machine_flags |= MACHINE_FLAG_LPAR;
                 return;
-        if (!vmms.count)
+        }
+        /* Get virtual-machine cpu information. */
+        if (stsi(&vmms, 3, 2, 2) == -ENOSYS || !vmms.count)
                 return;
 
         /* Running under KVM? If not we assume z/VM */
@@ -402,8 +405,19 @@ static void __init append_to_cmdline(size_t (*ipl_data)(char *, size_t))
 
 static void __init setup_boot_command_line(void)
 {
+        int i;
+
+        /* convert arch command line to ascii */
+        for (i = 0; i < ARCH_COMMAND_LINE_SIZE; i++)
+                if (COMMAND_LINE[i] & 0x80)
+                        break;
+        if (i < ARCH_COMMAND_LINE_SIZE)
+                EBCASC(COMMAND_LINE, ARCH_COMMAND_LINE_SIZE);
+        COMMAND_LINE[ARCH_COMMAND_LINE_SIZE-1] = 0;
+
         /* copy arch command line */
-        strlcpy(boot_command_line, COMMAND_LINE, ARCH_COMMAND_LINE_SIZE);
+        strlcpy(boot_command_line, strstrip(COMMAND_LINE),
+                ARCH_COMMAND_LINE_SIZE);
 
         /* append IPL PARM data to the boot command line */
         if (MACHINE_IS_VM)
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index e8ef21c51bbe..4348f9bc5393 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -13,7 +13,6 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/cache.h>
-#include <asm/lowcore.h>
 #include <asm/errno.h>
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index f33658f09dd7..29fd0f1e6ec4 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -9,11 +9,9 @@
  *               Heiko Carstens <heiko.carstens@de.ibm.com>
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/cache.h>
-#include <asm/lowcore.h>
 #include <asm/errno.h>
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
diff --git a/arch/s390/kernel/ftrace.c b/arch/s390/kernel/ftrace.c
index 5a82bc68193e..6a83d0581317 100644
--- a/arch/s390/kernel/ftrace.c
+++ b/arch/s390/kernel/ftrace.c
@@ -13,7 +13,7 @@
 #include <linux/kernel.h>
 #include <linux/types.h>
 #include <trace/syscall.h>
-#include <asm/lowcore.h>
+#include <asm/asm-offsets.h>
 
 #ifdef CONFIG_DYNAMIC_FTRACE
 
@@ -200,13 +200,3 @@ out:
         return parent;
 }
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
-
-#ifdef CONFIG_FTRACE_SYSCALLS
-
-extern unsigned int sys_call_table[];
-
-unsigned long __init arch_syscall_addr(int nr)
-{
-        return (unsigned long)sys_call_table[nr];
-}
-#endif
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index c52b4f7742fa..ca4a62bd862f 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -1,5 +1,5 @@
 /*
- * Copyright IBM Corp. 1999,2009
+ * Copyright IBM Corp. 1999,2010
  *
  *    Author(s): Hartmut Penner <hp@de.ibm.com>
  *               Martin Schwidefsky <schwidefsky@de.ibm.com>
@@ -22,12 +22,9 @@
  */
 
 #include <linux/init.h>
-#include <asm/setup.h>
-#include <asm/lowcore.h>
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 #include <asm/page.h>
-#include <asm/cpu.h>
 
 #ifdef CONFIG_64BIT
 #define ARCH_OFFSET     4
@@ -288,19 +285,7 @@ iplstart:
         bz      .Lagain1                # skip dateset trailer
         la      %r5,0(%r4,%r2)
         lr      %r3,%r2
-.Lidebc:
-        tm      0(%r5),0x80             # high order bit set ?
-        bo      .Ldocv                  #  yes -> convert from EBCDIC
-        ahi     %r5,-1
-        bct     %r3,.Lidebc
-        b       .Lnocv
-.Ldocv:
-        l       %r3,.Lcvtab
-        tr      0(256,%r4),0(%r3)       # convert parameters to ascii
-        tr      256(256,%r4),0(%r3)
-        tr      512(256,%r4),0(%r3)
-        tr      768(122,%r4),0(%r3)
-.Lnocv: la      %r3,COMMAND_LINE-PARMAREA(%r12) # load adr. of command line
+        la      %r3,COMMAND_LINE-PARMAREA(%r12) # load adr. of command line
         mvc     0(256,%r3),0(%r4)
         mvc     256(256,%r3),256(%r4)
         mvc     512(256,%r3),512(%r4)
@@ -384,7 +369,6 @@ iplstart:
 .Linitrd:.long _end + 0x400000          # default address of initrd
 .Lparm: .long  PARMAREA
 .Lstartup: .long startup
-.Lcvtab:.long   _ebcasc                 # ebcdic to ascii table
 .Lreset:.byte   0xc3,0xc8,0xc1,0xd5,0xc7,0xc5,0x40,0xd9,0xc4,0xd9,0x40
         .byte   0xc1,0xd3,0xd3,0x40,0xd2,0xc5,0xc5,0xd7,0x40,0xd5,0xd6
         .byte   0xc8,0xd6,0xd3,0xc4     # "change rdr all keep nohold"
@@ -417,13 +401,10 @@ start:
 .sk8x8:
         mvc     0(240,%r8),0(%r9)       # copy iplparms into buffer
 .gotr:
-        l       %r10,.tbl               # EBCDIC to ASCII table
-        tr      0(240,%r8),0(%r10)
         slr     %r0,%r0
         st      %r0,INITRD_SIZE+ARCH_OFFSET-PARMAREA(%r11)
         st      %r0,INITRD_START+ARCH_OFFSET-PARMAREA(%r11)
         j       startup                 # continue with startup
-.tbl:   .long   _ebcasc                 # translate table
 .cmd:   .long   COMMAND_LINE            # address of command line buffer
 .parm:  .long   PARMAREA
 .lowcase:
@@ -467,16 +448,15 @@ start:
 # or linload or SALIPL
 #
         .org    0x10000
-startup:basr    %r13,0                  # get base
+        .globl  startup
+startup:
+        basr    %r13,0                  # get base
 .LPG0:
         xc      0x200(256),0x200        # partially clear lowcore
         xc      0x300(256),0x300
-        l       %r1,5f-.LPG0(%r13)
-        stck    0(%r1)
-        spt     6f-.LPG0(%r13)
-        mvc     __LC_LAST_UPDATE_CLOCK(8),0(%r1)
-        mvc     __LC_LAST_UPDATE_TIMER(8),6f-.LPG0(%r13)
-        mvc     __LC_EXIT_TIMER(8),5f-.LPG0(%r13)
+        stck    __LC_LAST_UPDATE_CLOCK
+        spt     5f-.LPG0(%r13)
+        mvc     __LC_LAST_UPDATE_TIMER(8),5f-.LPG0(%r13)
 #ifndef CONFIG_MARCH_G5
         # check capabilities against MARCH_{G5,Z900,Z990,Z9_109,Z10}
         xc      __LC_STFL_FAC_LIST(8),__LC_STFL_FAC_LIST
@@ -494,7 +474,6 @@ startup:basr	%r13,0			# get base
         cl      %r0,2f+12-.LPG0(%r13)
         je      3f
 1:      l       %r15,.Lstack-.LPG0(%r13)
-        ahi     %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union+THREAD_SIZE
         ahi     %r15,-96
         la      %r2,.Lals_string-.LPG0(%r13)
         l       %r3,.Lsclp_print-.LPG0(%r13)
@@ -505,7 +484,7 @@ startup:basr	%r13,0			# get base
 .Lsclp_print:
         .long   _sclp_print_early
 .Lstack:
-        .long   init_thread_union
+        .long   0x8000 + (1<<(PAGE_SHIFT+THREAD_ORDER))
         .align 16
 2:      .long   0x000a0000,0x8badcccc
 #if defined(CONFIG_64BIT)
@@ -532,13 +511,22 @@ startup:basr	%r13,0			# get base
 3:
 #endif
 
+#ifdef CONFIG_64BIT
+        mvi     __LC_AR_MODE_ID,1       # set esame flag
+        slr     %r0,%r0                 # set cpuid to zero
+        lhi     %r1,2                   # mode 2 = esame (dump)
+        sigp    %r1,%r0,0x12            # switch to esame mode
+        sam64                           # switch to 64 bit mode
+        jg      startup_continue
+#else
+        mvi     __LC_AR_MODE_ID,0       # set ESA flag (mode 0)
         l       %r13,4f-.LPG0(%r13)
         b       0(%r13)
-        .align  4
+        .align  8
 4:      .long   startup_continue
-5:      .long   sched_clock_base_cc
+#endif
         .align  8
-6:      .long   0x7fffffff,0xffffffff
+5:      .long   0x7fffffff,0xffffffff
 
 #
 # params at 10400 (setup.h)
@@ -552,8 +540,4 @@ startup:basr	%r13,0			# get base
         .byte   "root=/dev/ram0 ro"
         .byte   0
 
-#ifdef CONFIG_64BIT
-#include "head64.S"
-#else
-#include "head31.S"
-#endif
+        .org    0x11000
diff --git a/arch/s390/kernel/head31.S b/arch/s390/kernel/head31.S
index 602b508cd4c4..1bbcc499d455 100644
--- a/arch/s390/kernel/head31.S
+++ b/arch/s390/kernel/head31.S
@@ -1,7 +1,7 @@
 /*
  * arch/s390/kernel/head31.S
  *
- * Copyright (C) IBM Corp. 2005,2006
+ * Copyright (C) IBM Corp. 2005,2010
  *
  *   Author(s): Hartmut Penner <hp@de.ibm.com>
  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
@@ -10,13 +10,19 @@
  *
  */
 
-        .org    0x11000
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
 
+__HEAD
+        .globl  startup_continue
 startup_continue:
         basr    %r13,0                  # get base
 .LPG1:
 
-        mvi     __LC_AR_MODE_ID,0       # set ESA flag (mode 0)
+        l       %r1,.Lbase_cc-.LPG1(%r13)
+        mvc     0(8,%r1),__LC_LAST_UPDATE_CLOCK
         lctl    %c0,%c15,.Lctl-.LPG1(%r13) # load control registers
         l       %r12,.Lparmaddr-.LPG1(%r13) # pointer to parameter area
                                         # move IPL device to lowcore
@@ -69,10 +75,12 @@ startup_continue:
 .Lduald:.rept   8
         .long   0x80000000,0,0,0        # invalid access-list entries
         .endr
+.Lbase_cc:
+        .long   sched_clock_base_cc
 
-        .org    0x12000
         .globl  _ehead
 _ehead:
+
 #ifdef CONFIG_SHARED_KERNEL
         .org    0x100000
 #endif
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index d984a2a380c3..39580e768658 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -1,7 +1,7 @@
 /*
  * arch/s390/kernel/head64.S
  *
- * Copyright (C) IBM Corp. 1999,2006
+ * Copyright (C) IBM Corp. 1999,2010
  *
  *   Author(s): Hartmut Penner <hp@de.ibm.com>
  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
@@ -10,80 +10,17 @@
  *
  */
 
-        .org    0x11000
+#include <linux/init.h>
+#include <asm/asm-offsets.h>
+#include <asm/thread_info.h>
+#include <asm/page.h>
 
+__HEAD
+        .globl  startup_continue
 startup_continue:
-        basr    %r13,0                  # get base
-.LPG1:  sll     %r13,1                  # remove high order bit
-        srl     %r13,1
-
-#ifdef CONFIG_ZFCPDUMP
-
-        # check if we have been ipled using zfcp dump:
-
-        tm      0xb9,0x01               # test if subchannel is enabled
-        jno     .nodump                 # subchannel disabled
-        l       %r1,0xb8
-        la      %r5,.Lipl_schib-.LPG1(%r13)
-        stsch   0(%r5)                  # get schib of subchannel
-        jne     .nodump                 # schib not available
-        tm      5(%r5),0x01             # devno valid?
-        jno     .nodump
-        tm      4(%r5),0x80             # qdio capable device?
-        jno     .nodump
-        l       %r2,20(%r0)             # address of ipl parameter block
-        lhi     %r3,0
-        ic      %r3,0x148(%r2)          # get opt field
-        chi     %r3,0x20                # load with dump?
-        jne     .nodump
-
-        # store all prefix registers in case of load with dump:
-
-        la      %r7,0                   # base register for 0 page
-        la      %r8,0                   # first cpu
-        l       %r11,.Lpref_arr_ptr-.LPG1(%r13) # address of prefix array
-        ahi     %r11,4                  # skip boot cpu
-        lr      %r12,%r11
-        ahi     %r12,(CONFIG_NR_CPUS*4) # end of prefix array
-        stap    .Lcurrent_cpu+2-.LPG1(%r13)     # store current cpu addr
-1:
-        cl      %r8,.Lcurrent_cpu-.LPG1(%r13)   # is ipl cpu ?
-        je      4f                              # if yes get next cpu
-2:
-        lr      %r9,%r7
-        sigp    %r9,%r8,0x9             # stop & store status of cpu
-        brc     8,3f                    # accepted
-        brc     4,4f                    # status stored: next cpu
-        brc     2,2b                    # busy:          try again
-        brc     1,4f                    # not op:        next cpu
-3:
-        mvc     0(4,%r11),264(%r7)      # copy prefix register to prefix array
-        ahi     %r11,4                  # next element in prefix array
-        clr     %r11,%r12
-        je      5f                      # no more space in prefix array
-4:
-        ahi     %r8,1                   # next cpu (r8 += 1)
-        chi     %r8,MAX_CPU_ADDRESS     # is last possible cpu ?
-        jle     1b                      # jump if not last cpu
-5:
-        lhi     %r1,2                   # mode 2 = esame (dump)
-        j       6f
-        .align 4
-.Lipl_schib:
-        .rept 13
-        .long 0
-        .endr
-.nodump:
-        lhi     %r1,1                   # mode 1 = esame (normal ipl)
-6:
-#else
-        lhi     %r1,1                   # mode 1 = esame (normal ipl)
-#endif /* CONFIG_ZFCPDUMP */
-        mvi     __LC_AR_MODE_ID,1       # set esame flag
-        slr     %r0,%r0                 # set cpuid to zero
-        sigp    %r1,%r0,0x12            # switch to esame mode
-        sam64                           # switch to 64 bit mode
-        llgfr   %r13,%r13               # clear high-order half of base reg
+        larl    %r1,sched_clock_base_cc
+        mvc     0(8,%r1),__LC_LAST_UPDATE_CLOCK
+        larl    %r13,.LPG1              # get base
         lmh     %r0,%r15,.Lzero64-.LPG1(%r13)   # clear high-order half
         lctlg   %c0,%c15,.Lctl-.LPG1(%r13)      # load control registers
         lg      %r12,.Lparmaddr-.LPG1(%r13)     # pointer to parameter area
@@ -108,6 +45,7 @@ startup_continue:
         lpswe   .Lentry-.LPG1(13)       # jump to _stext in primary-space,
                                         # virtual and never return ...
         .align  16
+.LPG1:
 .Lentry:.quad   0x0000000180000000,_stext
 .Lctl:  .quad   0x04350002              # cr0: various things
         .quad   0                       # cr1: primary space segment table
@@ -130,12 +68,6 @@ startup_continue:
 .Lscan2g:.quad  0x80000000 + 0x20000 - 8        # 2GB + 128K - 8
 .Lnop:  .long   0x07000700
 .Lzero64:.fill  16,4,0x0
-#ifdef CONFIG_ZFCPDUMP
-.Lcurrent_cpu:
-        .long 0x0
-.Lpref_arr_ptr:
-        .long zfcpdump_prefix_array
-#endif /* CONFIG_ZFCPDUMP */
 .Lparmaddr:
         .quad   PARMAREA
         .align  64
@@ -146,9 +78,9 @@ startup_continue:
         .long   0x80000000,0,0,0        # invalid access-list entries
         .endr
 
-        .org    0x12000
         .globl  _ehead
 _ehead:
+
 #ifdef CONFIG_SHARED_KERNEL
         .org    0x100000
 #endif
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 4d73296fed74..7eedbbcb54aa 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -553,7 +553,7 @@ out:
         return rc;
 }
 
-static void ipl_run(struct shutdown_trigger *trigger)
+static void __ipl_run(void *unused)
 {
         diag308(DIAG308_IPL, NULL);
         if (MACHINE_IS_VM)
@@ -562,6 +562,11 @@ static void ipl_run(struct shutdown_trigger *trigger)
                 reipl_ccw_dev(&ipl_info.data.ccw.dev_id);
 }
 
+static void ipl_run(struct shutdown_trigger *trigger)
+{
+        smp_switch_to_ipl_cpu(__ipl_run, NULL);
+}
+
 static int __init ipl_init(void)
 {
         int rc;
@@ -1039,7 +1044,7 @@ static void get_ipl_string(char *dst, struct ipl_parameter_block *ipb,
                 sprintf(dst + pos, " PARM %s", vmparm);
 }
 
-static void reipl_run(struct shutdown_trigger *trigger)
+static void __reipl_run(void *unused)
 {
         struct ccw_dev_id devid;
         static char buf[128];
@@ -1087,6 +1092,11 @@ static void reipl_run(struct shutdown_trigger *trigger)
         disabled_wait((unsigned long) __builtin_return_address(0));
 }
 
+static void reipl_run(struct shutdown_trigger *trigger)
+{
+        smp_switch_to_ipl_cpu(__reipl_run, NULL);
+}
+
 static void reipl_block_ccw_init(struct ipl_parameter_block *ipb)
 {
         ipb->hdr.len = IPL_PARM_BLK_CCW_LEN;
@@ -1369,20 +1379,18 @@ static struct kobj_attribute dump_type_attr =
 
 static struct kset *dump_kset;
 
-static void dump_run(struct shutdown_trigger *trigger)
+static void __dump_run(void *unused)
 {
         struct ccw_dev_id devid;
         static char buf[100];
 
         switch (dump_method) {
         case DUMP_METHOD_CCW_CIO:
-                smp_send_stop();
                 devid.devno = dump_block_ccw->ipl_info.ccw.devno;
                 devid.ssid  = 0;
                 reipl_ccw_dev(&devid);
                 break;
         case DUMP_METHOD_CCW_VM:
-                smp_send_stop();
                 sprintf(buf, "STORE STATUS");
                 __cpcmd(buf, NULL, 0, NULL);
                 sprintf(buf, "IPL %X", dump_block_ccw->ipl_info.ccw.devno);
@@ -1396,10 +1404,17 @@ static void dump_run(struct shutdown_trigger *trigger)
                 diag308(DIAG308_SET, dump_block_fcp);
                 diag308(DIAG308_DUMP, NULL);
                 break;
-        case DUMP_METHOD_NONE:
-                return;
+        default:
+                break;
         }
-        printk(KERN_EMERG "Dump failed!\n");
+}
+
+static void dump_run(struct shutdown_trigger *trigger)
+{
+        if (dump_method == DUMP_METHOD_NONE)
+                return;
+        smp_send_stop();
+        smp_switch_to_ipl_cpu(__dump_run, NULL);
 }
 
 static int __init dump_ccw_init(void)
@@ -1577,7 +1592,7 @@ static void vmcmd_run(struct shutdown_trigger *trigger)
 static int vmcmd_init(void)
 {
         if (!MACHINE_IS_VM)
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
         vmcmd_kset = kset_create_and_add("vmcmd", NULL, firmware_kobj);
         if (!vmcmd_kset)
                 return -ENOMEM;
@@ -1595,7 +1610,7 @@ static void stop_run(struct shutdown_trigger *trigger)
 {
         if (strcmp(trigger->name, ON_PANIC_STR) == 0)
                 disabled_wait((unsigned long) __builtin_return_address(0));
-        while (signal_processor(smp_processor_id(), sigp_stop) == sigp_busy)
+        while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
                 cpu_relax();
         for (;;);
 }
@@ -1902,7 +1917,6 @@ void __init ipl_update_parameters(void)
 void __init ipl_save_parameters(void)
 {
         struct cio_iplinfo iplinfo;
-        unsigned int *ipl_ptr;
         void *src, *dst;
 
         if (cio_get_iplinfo(&iplinfo))
@@ -1913,11 +1927,10 @@ void __init ipl_save_parameters(void)
         if (!iplinfo.is_qdio)
                 return;
         ipl_flags |= IPL_PARMBLOCK_VALID;
-        ipl_ptr = (unsigned int *)__LC_IPL_PARMBLOCK_PTR;
-        src = (void *)(unsigned long)*ipl_ptr;
+        src = (void *)(unsigned long)S390_lowcore.ipl_parmblock_ptr;
         dst = (void *)IPL_PARMBLOCK_ORIGIN;
         memmove(dst, src, PAGE_SIZE);
-        *ipl_ptr = IPL_PARMBLOCK_ORIGIN;
+        S390_lowcore.ipl_parmblock_ptr = IPL_PARMBLOCK_ORIGIN;
 }
 
 static LIST_HEAD(rcall);
diff --git a/arch/s390/kernel/machine_kexec.c b/arch/s390/kernel/machine_kexec.c
index 131d7ee8b416..a922d51df6bf 100644
--- a/arch/s390/kernel/machine_kexec.c
+++ b/arch/s390/kernel/machine_kexec.c
@@ -54,11 +54,11 @@ void machine_shutdown(void)
 {
 }
 
-void machine_kexec(struct kimage *image)
+static void __machine_kexec(void *data)
 {
         relocate_kernel_t data_mover;
+        struct kimage *image = data;
 
-        smp_send_stop();
         pfault_fini();
         s390_reset_system();
 
@@ -68,3 +68,9 @@ void machine_kexec(struct kimage *image)
         (*data_mover)(&image->head, image->start);
         for (;;);
 }
+
+void machine_kexec(struct kimage *image)
+{
+        smp_send_stop();
+        smp_switch_to_ipl_cpu(__machine_kexec, image);
+}
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 7cf464234419..33fdc5a79764 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -992,3 +992,61 @@ const struct user_regset_view *task_user_regset_view(struct task_struct *task)
 #endif
         return &user_s390_view;
 }
+
+static const char *gpr_names[NUM_GPRS] = {
+        "r0", "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
+        "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+};
+
+unsigned long regs_get_register(struct pt_regs *regs, unsigned int offset)
+{
+        if (offset >= NUM_GPRS)
+                return 0;
+        return regs->gprs[offset];
+}
+
+int regs_query_register_offset(const char *name)
+{
+        unsigned long offset;
+
+        if (!name || *name != 'r')
+                return -EINVAL;
+        if (strict_strtoul(name + 1, 10, &offset))
+                return -EINVAL;
+        if (offset >= NUM_GPRS)
+                return -EINVAL;
+        return offset;
+}
+
+const char *regs_query_register_name(unsigned int offset)
+{
+        if (offset >= NUM_GPRS)
+                return NULL;
+        return gpr_names[offset];
+}
+
+static int regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+        unsigned long ksp = kernel_stack_pointer(regs);
+
+        return (addr & ~(THREAD_SIZE - 1)) == (ksp & ~(THREAD_SIZE - 1));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:pt_regs which contains kernel stack pointer.
+ * @n:stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specifined by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+        unsigned long addr;
+
+        addr = kernel_stack_pointer(regs) + n * sizeof(long);
+        if (!regs_within_kernel_stack(regs, addr))
+                return 0;
+        return *(unsigned long *)addr;
+}
diff --git a/arch/s390/kernel/reipl.S b/arch/s390/kernel/reipl.S
index 2f481cc3d1c9..cb899d9f8505 100644
--- a/arch/s390/kernel/reipl.S
+++ b/arch/s390/kernel/reipl.S
@@ -6,7 +6,7 @@
  *    Author(s): Holger Smolinski (Holger.Smolinski@de.ibm.com)
  */
 
-#include <asm/lowcore.h>
+#include <asm/asm-offsets.h>
 
 #
 # do_reipl_asm
diff --git a/arch/s390/kernel/reipl64.S b/arch/s390/kernel/reipl64.S
index 774147824c3d..5e73dee63baa 100644
--- a/arch/s390/kernel/reipl64.S
+++ b/arch/s390/kernel/reipl64.S
@@ -4,7 +4,7 @@
  *               Denis Joseph Barrow,
  */
 
-#include <asm/lowcore.h>
+#include <asm/asm-offsets.h>
 
 #
 # do_reipl_asm
diff --git a/arch/s390/kernel/sclp.S b/arch/s390/kernel/sclp.S
index e27ca63076d1..27af3bf3a009 100644
--- a/arch/s390/kernel/sclp.S
+++ b/arch/s390/kernel/sclp.S
@@ -9,8 +9,10 @@
  */
 
 LC_EXT_NEW_PSW          = 0x58                  # addr of ext int handler
+LC_EXT_NEW_PSW_64       = 0x1b0                 # addr of ext int handler 64 bit
 LC_EXT_INT_PARAM        = 0x80                  # addr of ext int parameter
 LC_EXT_INT_CODE         = 0x86                  # addr of ext int code
+LC_AR_MODE_ID           = 0xa3
 
 #
 # Subroutine which waits synchronously until either an external interruption
@@ -30,8 +32,16 @@ _sclp_wait_int:
 .LbaseS1:
         ahi     %r15,-96                        # create stack frame
         la      %r8,LC_EXT_NEW_PSW              # register int handler
-        mvc     .LoldpswS1-.LbaseS1(8,%r13),0(%r8)
-        mvc     0(8,%r8),.LextpswS1-.LbaseS1(%r13)
+        la      %r9,.LextpswS1-.LbaseS1(%r13)
+#ifdef CONFIG_64BIT
+        tm      LC_AR_MODE_ID,1
+        jno     .Lesa1
+        la      %r8,LC_EXT_NEW_PSW_64           # register int handler 64 bit
+        la      %r9,.LextpswS1_64-.LbaseS1(%r13)
+.Lesa1:
+#endif
+        mvc     .LoldpswS1-.LbaseS1(16,%r13),0(%r8)
+        mvc     0(16,%r8),0(%r9)
         lhi     %r6,0x0200                      # cr mask for ext int (cr0.54)
         ltr     %r2,%r2
         jz      .LsetctS1
@@ -64,15 +74,19 @@ _sclp_wait_int:
 .LtimeoutS1:
         lctl    %c0,%c0,.LctlS1-.LbaseS1(%r13)  # restore interrupt setting
         # restore old handler
-        mvc     0(8,%r8),.LoldpswS1-.LbaseS1(%r13)
+        mvc     0(16,%r8),.LoldpswS1-.LbaseS1(%r13)
         lm      %r6,%r15,120(%r15)              # restore registers
         br      %r14                            # return to caller
 
         .align  8
 .LoldpswS1:
-        .long   0, 0                            # old ext int PSW
+        .long   0, 0, 0, 0                      # old ext int PSW
 .LextpswS1:
         .long   0x00080000, 0x80000000+.LwaitS1 # PSW to handle ext int
+#ifdef CONFIG_64BIT
+.LextpswS1_64:
+        .quad   0x0000000180000000, .LwaitS1    # PSW to handle ext int, 64 bit
+#endif
 .LwaitpswS1:
         .long   0x010a0000, 0x00000000+.LloopS1 # PSW to wait for ext int
 .LtimeS1:
@@ -250,6 +264,13 @@ _sclp_print:
 _sclp_print_early:
         stm     %r6,%r15,24(%r15)               # save registers
         ahi     %r15,-96                        # create stack frame
+#ifdef CONFIG_64BIT
+        tm      LC_AR_MODE_ID,1
+        jno     .Lesa2
+        ahi     %r15,-80
+        stmh    %r6,%r15,96(%r15)               # store upper register halves
+.Lesa2:
+#endif
         lr      %r10,%r2                        # save string pointer
         lhi     %r2,0
         bras    %r14,_sclp_setup                # enable console
@@ -262,6 +283,13 @@ _sclp_print_early:
         lhi     %r2,1
         bras    %r14,_sclp_setup                # disable console
 .LendS5:
+#ifdef CONFIG_64BIT
+        tm      LC_AR_MODE_ID,1
+        jno     .Lesa3
+        lmh     %r6,%r15,96(%r15)               # store upper register halves
+        ahi     %r15,80
+.Lesa3:
+#endif
         lm      %r6,%r15,120(%r15)              # restore registers
         br      %r14
 
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index 8d8957b38ab3..77a63ae419f0 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -396,15 +396,12 @@ static void __init
 setup_lowcore(void)
 {
         struct _lowcore *lc;
-        int lc_pages;
 
         /*
          * Setup lowcore for boot cpu
          */
-        lc_pages = sizeof(void *) == 8 ? 2 : 1;
-        lc = (struct _lowcore *)
-                __alloc_bootmem(lc_pages * PAGE_SIZE, lc_pages * PAGE_SIZE, 0);
-        memset(lc, 0, lc_pages * PAGE_SIZE);
+        BUILD_BUG_ON(sizeof(struct _lowcore) != LC_PAGES * 4096);
+        lc = __alloc_bootmem(LC_PAGES * PAGE_SIZE, LC_PAGES * PAGE_SIZE, 0);
         lc->restart_psw.mask = PSW_BASE_BITS | PSW_DEFAULT_KEY;
         lc->restart_psw.addr =
                 PSW_ADDR_AMODE | (unsigned long) restart_int_handler;
@@ -804,7 +801,7 @@ setup_arch(char **cmdline_p)
         if (MACHINE_IS_VM)
                 pr_info("Linux is running as a z/VM "
                         "guest operating system in 31-bit mode\n");
-        else
+        else if (MACHINE_IS_LPAR)
                 pr_info("Linux is running natively in 31-bit mode\n");
         if (MACHINE_HAS_IEEE)
                 pr_info("The hardware system has IEEE compatible "
@@ -818,7 +815,7 @@ setup_arch(char **cmdline_p)
                         "guest operating system in 64-bit mode\n");
         else if (MACHINE_IS_KVM)
                 pr_info("Linux is running under KVM in 64-bit mode\n");
-        else
+        else if (MACHINE_IS_LPAR)
                 pr_info("Linux is running natively in 64-bit mode\n");
 #endif /* CONFIG_64BIT */
 
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 76a6fdd46c45..8b10127c00ad 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -36,6 +36,7 @@
 #include <linux/cpu.h>
 #include <linux/timex.h>
 #include <linux/bootmem.h>
+#include <asm/asm-offsets.h>
 #include <asm/ipl.h>
 #include <asm/setup.h>
 #include <asm/sigp.h>
@@ -53,7 +54,7 @@
 #include "entry.h"
 
 /* logical cpu to cpu address */
-int __cpu_logical_map[NR_CPUS];
+unsigned short __cpu_logical_map[NR_CPUS];
 
 static struct task_struct *current_set[NR_CPUS];
 
@@ -72,13 +73,13 @@ static int cpu_management;
 
 static DEFINE_PER_CPU(struct cpu, cpu_devices);
 
-static void smp_ext_bitcall(int, ec_bit_sig);
+static void smp_ext_bitcall(int, int);
 
-static int cpu_stopped(int cpu)
+static int raw_cpu_stopped(int cpu)
 {
-        __u32 status;
+        u32 status;
 
-        switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
+        switch (raw_sigp_ps(&status, 0, cpu, sigp_sense)) {
         case sigp_status_stored:
                 /* Check for stopped and check stop state */
                 if (status & 0x50)
@@ -90,6 +91,44 @@ static int cpu_stopped(int cpu)
         return 0;
 }
 
+static inline int cpu_stopped(int cpu)
+{
+        return raw_cpu_stopped(cpu_logical_map(cpu));
+}
+
+void smp_switch_to_ipl_cpu(void (*func)(void *), void *data)
+{
+        struct _lowcore *lc, *current_lc;
+        struct stack_frame *sf;
+        struct pt_regs *regs;
+        unsigned long sp;
+
+        if (smp_processor_id() == 0)
+                func(data);
+        __load_psw_mask(PSW_BASE_BITS | PSW_DEFAULT_KEY);
+        /* Disable lowcore protection */
+        __ctl_clear_bit(0, 28);
+        current_lc = lowcore_ptr[smp_processor_id()];
+        lc = lowcore_ptr[0];
+        if (!lc)
+                lc = current_lc;
+        lc->restart_psw.mask = PSW_BASE_BITS | PSW_DEFAULT_KEY;
+        lc->restart_psw.addr = PSW_ADDR_AMODE | (unsigned long) smp_restart_cpu;
+        if (!cpu_online(0))
+                smp_switch_to_cpu(func, data, 0, stap(), __cpu_logical_map[0]);
+        while (sigp(0, sigp_stop_and_store_status) == sigp_busy)
+                cpu_relax();
+        sp = lc->panic_stack;
+        sp -= sizeof(struct pt_regs);
+        regs = (struct pt_regs *) sp;
+        memcpy(&regs->gprs, &current_lc->gpregs_save_area, sizeof(regs->gprs));
+        regs->psw = lc->psw_save_area;
+        sp -= STACK_FRAME_OVERHEAD;
+        sf = (struct stack_frame *) sp;
+        sf->back_chain = regs->gprs[15];
+        smp_switch_to_cpu(func, data, sp, stap(), __cpu_logical_map[0]);
+}
+
 void smp_send_stop(void)
 {
         int cpu, rc;
@@ -103,7 +142,7 @@ void smp_send_stop(void)
                 if (cpu == smp_processor_id())
                         continue;
                 do {
-                        rc = signal_processor(cpu, sigp_stop);
+                        rc = sigp(cpu, sigp_stop);
                 } while (rc == sigp_busy);
 
                 while (!cpu_stopped(cpu))
@@ -139,13 +178,13 @@ static void do_ext_call_interrupt(__u16 code)
  * Send an external call sigp to another cpu and return without waiting
  * for its completion.
  */
-static void smp_ext_bitcall(int cpu, ec_bit_sig sig)
+static void smp_ext_bitcall(int cpu, int sig)
 {
         /*
          * Set signaling bit in lowcore of target cpu and kick it
          */
         set_bit(sig, (unsigned long *) &lowcore_ptr[cpu]->ext_call_fast);
-        while (signal_processor(cpu, sigp_emergency_signal) == sigp_busy)
+        while (sigp(cpu, sigp_emergency_signal) == sigp_busy)
                 udelay(10);
 }
 
@@ -239,24 +278,8 @@ void smp_ctl_clear_bit(int cr, int bit)
 }
 EXPORT_SYMBOL(smp_ctl_clear_bit);
 
-/*
- * In early ipl state a temp. logically cpu number is needed, so the sigp
- * functions can be used to sense other cpus. Since NR_CPUS is >= 2 on
- * CONFIG_SMP and the ipl cpu is logical cpu 0, it must be 1.
- */
-#define CPU_INIT_NO     1
-
 #ifdef CONFIG_ZFCPDUMP
 
-/*
- * zfcpdump_prefix_array holds prefix registers for the following scenario:
- * 64 bit zfcpdump kernel and 31 bit kernel which is to be dumped. We have to
- * save its prefix registers, since they get lost, when switching from 31 bit
- * to 64 bit.
- */
-unsigned int zfcpdump_prefix_array[NR_CPUS + 1] \
-        __attribute__((__section__(".data")));
-
 static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu)
 {
         if (ipl_info.type != IPL_TYPE_FCP_DUMP)
@@ -266,21 +289,15 @@ static void __init smp_get_save_area(unsigned int cpu, unsigned int phy_cpu)
                            "the dump\n", cpu, NR_CPUS - 1);
                 return;
         }
-        zfcpdump_save_areas[cpu] = kmalloc(sizeof(union save_area), GFP_KERNEL);
-        __cpu_logical_map[CPU_INIT_NO] = (__u16) phy_cpu;
-        while (signal_processor(CPU_INIT_NO, sigp_stop_and_store_status) ==
-               sigp_busy)
+        zfcpdump_save_areas[cpu] = kmalloc(sizeof(struct save_area), GFP_KERNEL);
+        while (raw_sigp(phy_cpu, sigp_stop_and_store_status) == sigp_busy)
                 cpu_relax();
         memcpy(zfcpdump_save_areas[cpu],
                (void *)(unsigned long) store_prefix() + SAVE_AREA_BASE,
-               SAVE_AREA_SIZE);
-#ifdef CONFIG_64BIT
-        /* copy original prefix register */
-        zfcpdump_save_areas[cpu]->s390x.pref_reg = zfcpdump_prefix_array[cpu];
-#endif
+               sizeof(struct save_area));
 }
 
-union save_area *zfcpdump_save_areas[NR_CPUS + 1];
+struct save_area *zfcpdump_save_areas[NR_CPUS + 1];
 EXPORT_SYMBOL_GPL(zfcpdump_save_areas);
 
 #else
@@ -389,8 +406,7 @@ static void __init smp_detect_cpus(void)
                 for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) {
                         if (cpu == boot_cpu_addr)
                                 continue;
-                        __cpu_logical_map[CPU_INIT_NO] = cpu;
-                        if (!cpu_stopped(CPU_INIT_NO))
+                        if (!raw_cpu_stopped(cpu))
                                 continue;
                         smp_get_save_area(c_cpus, cpu);
                         c_cpus++;
@@ -413,8 +429,7 @@ static void __init smp_detect_cpus(void)
                 cpu_addr = info->cpu[cpu].address;
                 if (cpu_addr == boot_cpu_addr)
                         continue;
-                __cpu_logical_map[CPU_INIT_NO] = cpu_addr;
-                if (!cpu_stopped(CPU_INIT_NO)) {
+                if (!raw_cpu_stopped(cpu_addr)) {
                         s_cpus++;
                         continue;
                 }
@@ -533,18 +548,18 @@ static void smp_free_lowcore(int cpu)
 /* Upping and downing of CPUs */
 int __cpuinit __cpu_up(unsigned int cpu)
 {
-        struct task_struct *idle;
         struct _lowcore *cpu_lowcore;
+        struct task_struct *idle;
         struct stack_frame *sf;
-        sigp_ccode ccode;
         u32 lowcore;
+        int ccode;
 
         if (smp_cpu_state[cpu] != CPU_STATE_CONFIGURED)
                 return -EIO;
         if (smp_alloc_lowcore(cpu))
                 return -ENOMEM;
         do {
-                ccode = signal_processor(cpu, sigp_initial_cpu_reset);
+                ccode = sigp(cpu, sigp_initial_cpu_reset);
                 if (ccode == sigp_busy)
                         udelay(10);
                 if (ccode == sigp_not_operational)
@@ -552,7 +567,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
         } while (ccode == sigp_busy);
 
         lowcore = (u32)(unsigned long)lowcore_ptr[cpu];
-        while (signal_processor_p(lowcore, cpu, sigp_set_prefix) == sigp_busy)
+        while (sigp_p(lowcore, cpu, sigp_set_prefix) == sigp_busy)
                 udelay(10);
 
         idle = current_set[cpu];
@@ -578,7 +593,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
         cpu_lowcore->ftrace_func = S390_lowcore.ftrace_func;
         eieio();
 
-        while (signal_processor(cpu, sigp_restart) == sigp_busy)
+        while (sigp(cpu, sigp_restart) == sigp_busy)
                 udelay(10);
 
         while (!cpu_online(cpu))
@@ -640,7 +655,7 @@ void __cpu_die(unsigned int cpu)
         /* Wait until target cpu is down */
         while (!cpu_stopped(cpu))
                 cpu_relax();
-        while (signal_processor_p(0, cpu, sigp_set_prefix) == sigp_busy)
+        while (sigp_p(0, cpu, sigp_set_prefix) == sigp_busy)
                 udelay(10);
         smp_free_lowcore(cpu);
         pr_info("Processor %d stopped\n", cpu);
@@ -649,7 +664,7 @@ void __cpu_die(unsigned int cpu)
 void cpu_die(void)
 {
         idle_task_exit();
-        while (signal_processor(smp_processor_id(), sigp_stop) == sigp_busy)
+        while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
                 cpu_relax();
         for (;;);
 }
@@ -765,7 +780,8 @@ static ssize_t cpu_configure_store(struct sys_device *dev,
         get_online_cpus();
         mutex_lock(&smp_cpu_state_mutex);
         rc = -EBUSY;
-        if (cpu_online(cpu))
+        /* disallow configuration changes of online cpus and cpu 0 */
+        if (cpu_online(cpu) || cpu == 0)
                 goto out;
         rc = 0;
         switch (val) {
diff --git a/arch/s390/kernel/switch_cpu.S b/arch/s390/kernel/switch_cpu.S
new file mode 100644
index 000000000000..469f11b574fa
--- /dev/null
+++ b/arch/s390/kernel/switch_cpu.S
@@ -0,0 +1,58 @@
+/*
+ * 31-bit switch cpu code
+ *
+ * Copyright IBM Corp. 2009
+ *
+ */
+
+#include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
+
+# smp_switch_to_cpu switches to destination cpu and executes the passed function
+# Parameter: %r2 - function to call
+#            %r3 - function parameter
+#            %r4 - stack poiner
+#            %r5 - current cpu
+#            %r6 - destination cpu
+
+        .section .text
+        .align 4
+        .globl smp_switch_to_cpu
+smp_switch_to_cpu:
+        stm     %r6,%r15,__SF_GPRS(%r15)
+        lr      %r1,%r15
+        ahi     %r15,-STACK_FRAME_OVERHEAD
+        st      %r1,__SF_BACKCHAIN(%r15)
+        basr    %r13,0
+0:      la      %r1,.gprregs_addr-0b(%r13)
+        l       %r1,0(%r1)
+        stm     %r0,%r15,0(%r1)
+1:      sigp    %r0,%r6,__SIGP_RESTART  /* start destination CPU */
+        brc     2,1b                    /* busy, try again */
+2:      sigp    %r0,%r5,__SIGP_STOP     /* stop current CPU */
+        brc     2,2b                    /* busy, try again */
+3:      j       3b
+
+        .globl  smp_restart_cpu
+smp_restart_cpu:
+        basr    %r13,0
+0:      la      %r1,.gprregs_addr-0b(%r13)
+        l       %r1,0(%r1)
+        lm      %r0,%r15,0(%r1)
+1:      sigp    %r0,%r5,__SIGP_SENSE    /* Wait for calling CPU */
+        brc     10,1b                   /* busy, accepted (status 0), running */
+        tmll    %r0,0x40                /* Test if calling CPU is stopped */
+        jz      1b
+        ltr     %r4,%r4                 /* New stack ? */
+        jz      1f
+        lr      %r15,%r4
+1:      basr    %r14,%r2
+
+.gprregs_addr:
+        .long   .gprregs
+
+        .section .data,"aw",@progbits
+.gprregs:
+        .rept   16
+        .long   0
+        .endr
diff --git a/arch/s390/kernel/switch_cpu64.S b/arch/s390/kernel/switch_cpu64.S
new file mode 100644
index 000000000000..d94aacc898cb
--- /dev/null
+++ b/arch/s390/kernel/switch_cpu64.S
@@ -0,0 +1,51 @@
+/*
+ * 64-bit switch cpu code
+ *
+ * Copyright IBM Corp. 2009
+ *
+ */
+
+#include <asm/asm-offsets.h>
+#include <asm/ptrace.h>
+
+# smp_switch_to_cpu switches to destination cpu and executes the passed function
+# Parameter: %r2 - function to call
+#            %r3 - function parameter
+#            %r4 - stack poiner
+#            %r5 - current cpu
+#            %r6 - destination cpu
+
+        .section .text
+        .align 4
+        .globl smp_switch_to_cpu
+smp_switch_to_cpu:
+        stmg    %r6,%r15,__SF_GPRS(%r15)
+        lgr     %r1,%r15
+        aghi    %r15,-STACK_FRAME_OVERHEAD
+        stg     %r1,__SF_BACKCHAIN(%r15)
+        larl    %r1,.gprregs
+        stmg    %r0,%r15,0(%r1)
+1:      sigp    %r0,%r6,__SIGP_RESTART  /* start destination CPU */
+        brc     2,1b                    /* busy, try again */
+2:      sigp    %r0,%r5,__SIGP_STOP     /* stop current CPU */
+        brc     2,2b                    /* busy, try again */
+3:      j       3b
+
+        .globl  smp_restart_cpu
+smp_restart_cpu:
+        larl    %r1,.gprregs
+        lmg     %r0,%r15,0(%r1)
+1:      sigp    %r0,%r5,__SIGP_SENSE    /* Wait for calling CPU */
+        brc     10,1b                   /* busy, accepted (status 0), running */
+        tmll    %r0,0x40                /* Test if calling CPU is stopped */
+        jz      1b
+        ltgr    %r4,%r4                 /* New stack ? */
+        jz      1f
+        lgr     %r15,%r4
+1:      basr    %r14,%r2
+
+        .section .data,"aw",@progbits
+.gprregs:
+        .rept   16
+        .quad   0
+        .endr
diff --git a/arch/s390/kernel/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S
index 0c26cc1898ec..b354427e03b7 100644
--- a/arch/s390/kernel/swsusp_asm64.S
+++ b/arch/s390/kernel/swsusp_asm64.S
@@ -176,7 +176,7 @@ pgm_check_entry:
         cgr     %r1,%r2
         je      restore_registers               /* r1 = r2 -> nothing to do */
         larl    %r4,.Lrestart_suspend_psw       /* Set new restart PSW */
-        mvc     __LC_RESTART_PSW(16,%r0),0(%r4)
+        mvc     __LC_RST_NEW_PSW(16,%r0),0(%r4)
 3:
         sigp    %r9,%r1,__SIGP_INITIAL_CPU_RESET
         brc     8,4f    /* accepted */
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 65065ac48ed3..a8f93f1705ad 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -51,14 +51,6 @@
 #define USECS_PER_JIFFY     ((unsigned long) 1000000/HZ)
 #define CLK_TICKS_PER_JIFFY ((unsigned long) USECS_PER_JIFFY << 12)
 
-/*
- * Create a small time difference between the timer interrupts
- * on the different cpus to avoid lock contention.
- */
-#define CPU_DEVIATION       (smp_processor_id() << 12)
-
-#define TICK_SIZE tick
-
 u64 sched_clock_base_cc = -1;   /* Force to data section. */
 EXPORT_SYMBOL_GPL(sched_clock_base_cc);
 
diff --git a/arch/s390/kernel/vdso.c b/arch/s390/kernel/vdso.c
index 5f99e66c51c3..6bc9c197aa91 100644
--- a/arch/s390/kernel/vdso.c
+++ b/arch/s390/kernel/vdso.c
@@ -23,6 +23,7 @@
 #include <linux/security.h>
 #include <linux/bootmem.h>
 #include <linux/compat.h>
+#include <asm/asm-offsets.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
 #include <asm/processor.h>
diff --git a/arch/s390/kvm/diag.c b/arch/s390/kvm/diag.c
index 8300309698fa..9e4c84187cf5 100644
--- a/arch/s390/kvm/diag.c
+++ b/arch/s390/kvm/diag.c
@@ -39,7 +39,7 @@ static int __diag_ipl_functions(struct kvm_vcpu *vcpu)
                 vcpu->run->s390_reset_flags = 0;
                 break;
         default:
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
         }
 
         atomic_clear_mask(CPUSTAT_RUNNING, &vcpu->arch.sie_block->cpuflags);
@@ -62,6 +62,6 @@ int kvm_s390_handle_diag(struct kvm_vcpu *vcpu)
         case 0x308:
                 return __diag_ipl_functions(vcpu);
         default:
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
         }
 }
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index b40096494e46..3ddc30895e31 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -32,7 +32,7 @@ static int handle_lctlg(struct kvm_vcpu *vcpu)
 
         vcpu->stat.instruction_lctlg++;
         if ((vcpu->arch.sie_block->ipb & 0xff) != 0x2f)
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
 
         useraddr = disp2;
         if (base2)
@@ -138,7 +138,7 @@ static int handle_stop(struct kvm_vcpu *vcpu)
                 rc = __kvm_s390_vcpu_store_status(vcpu,
                                                   KVM_S390_STORE_STATUS_NOADDR);
                 if (rc >= 0)
-                        rc = -ENOTSUPP;
+                        rc = -EOPNOTSUPP;
         }
 
         if (vcpu->arch.local_int.action_bits & ACTION_RELOADVCPU_ON_STOP) {
@@ -150,7 +150,7 @@ static int handle_stop(struct kvm_vcpu *vcpu)
         if (vcpu->arch.local_int.action_bits & ACTION_STOP_ON_STOP) {
                 vcpu->arch.local_int.action_bits &= ~ACTION_STOP_ON_STOP;
                 VCPU_EVENT(vcpu, 3, "%s", "cpu stopped");
-                rc = -ENOTSUPP;
+                rc = -EOPNOTSUPP;
         }
 
         spin_unlock_bh(&vcpu->arch.local_int.lock);
@@ -171,9 +171,9 @@ static int handle_validity(struct kvm_vcpu *vcpu)
                          2*PAGE_SIZE);
                 if (rc)
                         /* user will receive sigsegv, exit to user */
-                        rc = -ENOTSUPP;
+                        rc = -EOPNOTSUPP;
         } else
-                rc = -ENOTSUPP;
+                rc = -EOPNOTSUPP;
 
         if (rc)
                 VCPU_EVENT(vcpu, 2, "unhandled validity intercept code %d",
@@ -189,7 +189,7 @@ static int handle_instruction(struct kvm_vcpu *vcpu)
         handler = instruction_handlers[vcpu->arch.sie_block->ipa >> 8];
         if (handler)
                 return handler(vcpu);
-        return -ENOTSUPP;
+        return -EOPNOTSUPP;
 }
 
 static int handle_prog(struct kvm_vcpu *vcpu)
@@ -206,7 +206,7 @@ static int handle_instruction_and_prog(struct kvm_vcpu *vcpu)
         rc = handle_instruction(vcpu);
         rc2 = handle_prog(vcpu);
 
-        if (rc == -ENOTSUPP)
+        if (rc == -EOPNOTSUPP)
                 vcpu->arch.sie_block->icptcode = 0x04;
         if (rc)
                 return rc;
@@ -231,9 +231,9 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu)
         u8 code = vcpu->arch.sie_block->icptcode;
 
         if (code & 3 || (code >> 2) >= ARRAY_SIZE(intercept_funcs))
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
         func = intercept_funcs[code >> 2];
         if (func)
                 return func(vcpu);
-        return -ENOTSUPP;
+        return -EOPNOTSUPP;
 }
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 43486c2408e1..834774d8d5f3 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -10,12 +10,12 @@
  *    Author(s): Carsten Otte <cotte@de.ibm.com>
  */
 
-#include <asm/lowcore.h>
-#include <asm/uaccess.h>
-#include <linux/hrtimer.h>
 #include <linux/interrupt.h>
 #include <linux/kvm_host.h>
+#include <linux/hrtimer.h>
 #include <linux/signal.h>
+#include <asm/asm-offsets.h>
+#include <asm/uaccess.h>
 #include "kvm-s390.h"
 #include "gaccess.h"
 
@@ -187,8 +187,8 @@ static void __do_deliver_interrupt(struct kvm_vcpu *vcpu,
                 if (rc == -EFAULT)
                         exception = 1;
 
-                rc = put_guest_u64(vcpu, __LC_PFAULT_INTPARM,
-                        inti->ext.ext_params2);
+                rc = put_guest_u64(vcpu, __LC_EXT_PARAMS2,
+                                   inti->ext.ext_params2);
                 if (rc == -EFAULT)
                         exception = 1;
                 break;
@@ -342,7 +342,7 @@ int kvm_s390_handle_wait(struct kvm_vcpu *vcpu)
         if (psw_interrupts_disabled(vcpu)) {
                 VCPU_EVENT(vcpu, 3, "%s", "disabled wait");
                 __unset_cpu_idle(vcpu);
-                return -ENOTSUPP; /* disabled wait */
+                return -EOPNOTSUPP; /* disabled wait */
         }
 
         if (psw_extint_disabled(vcpu) ||
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index f8bcaefd7d34..3fa0a10e4668 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -23,6 +23,7 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/timer.h>
+#include <asm/asm-offsets.h>
 #include <asm/lowcore.h>
 #include <asm/pgtable.h>
 #include <asm/nmi.h>
@@ -543,7 +544,7 @@ rerun_vcpu:
                 rc = -EINTR;
         }
 
-        if (rc == -ENOTSUPP) {
+        if (rc == -EOPNOTSUPP) {
                 /* intercept cannot be handled in-kernel, prepare kvm-run */
                 kvm_run->exit_reason         = KVM_EXIT_S390_SIEIC;
                 kvm_run->s390_sieic.icptcode = vcpu->arch.sie_block->icptcode;
@@ -603,45 +604,45 @@ int __kvm_s390_vcpu_store_status(struct kvm_vcpu *vcpu, unsigned long addr)
         } else
                 prefix = 0;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, fp_regs),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, fp_regs),
                         vcpu->arch.guest_fpregs.fprs, 128, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, gp_regs),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, gp_regs),
                         vcpu->arch.guest_gprs, 128, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, psw),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, psw),
                         &vcpu->arch.sie_block->gpsw, 16, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, pref_reg),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, pref_reg),
                         &vcpu->arch.sie_block->prefix, 4, prefix))
                 return -EFAULT;
 
         if (__guestcopy(vcpu,
-                        addr + offsetof(struct save_area_s390x, fp_ctrl_reg),
+                        addr + offsetof(struct save_area, fp_ctrl_reg),
                         &vcpu->arch.guest_fpregs.fpc, 4, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, tod_reg),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, tod_reg),
                         &vcpu->arch.sie_block->todpr, 4, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, timer),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, timer),
                         &vcpu->arch.sie_block->cputm, 8, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, clk_cmp),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, clk_cmp),
                         &vcpu->arch.sie_block->ckc, 8, prefix))
                 return -EFAULT;
 
-        if (__guestcopy(vcpu, addr + offsetof(struct save_area_s390x, acc_regs),
+        if (__guestcopy(vcpu, addr + offsetof(struct save_area, acc_regs),
                         &vcpu->arch.guest_acrs, 64, prefix))
                 return -EFAULT;
 
         if (__guestcopy(vcpu,
-                        addr + offsetof(struct save_area_s390x, ctrl_regs),
+                        addr + offsetof(struct save_area, ctrl_regs),
                         &vcpu->arch.sie_block->gcr, 128, prefix))
                 return -EFAULT;
         return 0;
diff --git a/arch/s390/kvm/priv.c b/arch/s390/kvm/priv.c
index d426aac8095d..28c55677eb39 100644
--- a/arch/s390/kvm/priv.c
+++ b/arch/s390/kvm/priv.c
@@ -323,5 +323,5 @@ int kvm_s390_handle_b2(struct kvm_vcpu *vcpu)
                 else
                         return handler(vcpu);
         }
-        return -ENOTSUPP;
+        return -EOPNOTSUPP;
 }
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index 15ee1111de58..241a48459b66 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -172,7 +172,7 @@ static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
                 rc = 0; /* order accepted */
                 break;
         default:
-                rc = -ENOTSUPP;
+                rc = -EOPNOTSUPP;
         }
         return rc;
 }
@@ -293,7 +293,7 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                 vcpu->stat.instruction_sigp_restart++;
                 /* user space must know about restart */
         default:
-                return -ENOTSUPP;
+                return -EOPNOTSUPP;
         }
 
         if (rc < 0)
diff --git a/arch/s390/lib/Makefile b/arch/s390/lib/Makefile
index 97975ec7a274..cd54a1c352af 100644
--- a/arch/s390/lib/Makefile
+++ b/arch/s390/lib/Makefile
@@ -2,7 +2,7 @@
 # Makefile for s390-specific library files..
 #
 
-lib-y += delay.o string.o uaccess_std.o uaccess_pt.o
+lib-y += delay.o string.o uaccess_std.o uaccess_pt.o usercopy.o
 obj-$(CONFIG_32BIT) += div64.o qrnnd.o ucmpdi2.o
 lib-$(CONFIG_64BIT) += uaccess_mvcos.o
 lib-$(CONFIG_SMP) += spinlock.o
diff --git a/arch/s390/lib/spinlock.c b/arch/s390/lib/spinlock.c
index cff327f109a8..91754ffb9203 100644
--- a/arch/s390/lib/spinlock.c
+++ b/arch/s390/lib/spinlock.c
@@ -43,16 +43,24 @@ void arch_spin_lock_wait(arch_spinlock_t *lp)
 {
         int count = spin_retry;
         unsigned int cpu = ~smp_processor_id();
+        unsigned int owner;
 
         while (1) {
-                if (count-- <= 0) {
-                        unsigned int owner = lp->owner_cpu;
-                        if (owner != 0)
-                                _raw_yield_cpu(~owner);
-                        count = spin_retry;
+                owner = lp->owner_cpu;
+                if (!owner || smp_vcpu_scheduled(~owner)) {
+                        for (count = spin_retry; count > 0; count--) {
+                                if (arch_spin_is_locked(lp))
+                                        continue;
+                                if (_raw_compare_and_swap(&lp->owner_cpu, 0,
+                                                          cpu) == 0)
+                                        return;
+                        }
+                        if (MACHINE_IS_LPAR)
+                                continue;
                 }
-                if (arch_spin_is_locked(lp))
-                        continue;
+                owner = lp->owner_cpu;
+                if (owner)
+                        _raw_yield_cpu(~owner);
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
                         return;
         }
@@ -63,17 +71,27 @@ void arch_spin_lock_wait_flags(arch_spinlock_t *lp, unsigned long flags)
 {
         int count = spin_retry;
         unsigned int cpu = ~smp_processor_id();
+        unsigned int owner;
 
         local_irq_restore(flags);
         while (1) {
-                if (count-- <= 0) {
-                        unsigned int owner = lp->owner_cpu;
-                        if (owner != 0)
-                                _raw_yield_cpu(~owner);
-                        count = spin_retry;
+                owner = lp->owner_cpu;
+                if (!owner || smp_vcpu_scheduled(~owner)) {
+                        for (count = spin_retry; count > 0; count--) {
+                                if (arch_spin_is_locked(lp))
+                                        continue;
+                                local_irq_disable();
+                                if (_raw_compare_and_swap(&lp->owner_cpu, 0,
+                                                          cpu) == 0)
+                                        return;
+                                local_irq_restore(flags);
+                        }
+                        if (MACHINE_IS_LPAR)
+                                continue;
                 }
-                if (arch_spin_is_locked(lp))
-                        continue;
+                owner = lp->owner_cpu;
+                if (owner)
+                        _raw_yield_cpu(~owner);
                 local_irq_disable();
                 if (_raw_compare_and_swap(&lp->owner_cpu, 0, cpu) == 0)
                         return;
@@ -100,8 +118,11 @@ EXPORT_SYMBOL(arch_spin_trylock_retry);
 void arch_spin_relax(arch_spinlock_t *lock)
 {
         unsigned int cpu = lock->owner_cpu;
-        if (cpu != 0)
-                _raw_yield_cpu(~cpu);
+        if (cpu != 0) {
+                if (MACHINE_IS_VM || MACHINE_IS_KVM ||
+                    !smp_vcpu_scheduled(~cpu))
+                        _raw_yield_cpu(~cpu);
+        }
 }
 EXPORT_SYMBOL(arch_spin_relax);
 
diff --git a/arch/s390/lib/usercopy.c b/arch/s390/lib/usercopy.c
new file mode 100644
index 000000000000..14b363fec8a2
--- /dev/null
+++ b/arch/s390/lib/usercopy.c
@@ -0,0 +1,8 @@
+#include <linux/module.h>
+#include <linux/bug.h>
+
+void copy_from_user_overflow(void)
+{
+        WARN(1, "Buffer overflow detected!\n");
+}
+EXPORT_SYMBOL(copy_from_user_overflow);
diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c
index 5c8457129603..6409fd57eb04 100644
--- a/arch/s390/mm/extmem.c
+++ b/arch/s390/mm/extmem.c
@@ -309,7 +309,7 @@ query_segment_type (struct dcss_segment *seg)
         }
 #endif
         if (qout->segcnt > 6) {
-                rc = -ENOTSUPP;
+                rc = -EOPNOTSUPP;
                 goto out_free;
         }
 
@@ -324,11 +324,11 @@ query_segment_type (struct dcss_segment *seg)
                 for (i=0; i<qout->segcnt; i++) {
                         if (((qout->range[i].start & 0xff) != SEG_TYPE_EW) &&
                             ((qout->range[i].start & 0xff) != SEG_TYPE_EN)) {
-                                rc = -ENOTSUPP;
+                                rc = -EOPNOTSUPP;
                                 goto out_free;
                         }
                         if (start != qout->range[i].start >> PAGE_SHIFT) {
-                                rc = -ENOTSUPP;
+                                rc = -EOPNOTSUPP;
                                 goto out_free;
                         }
                         start = (qout->range[i].end >> PAGE_SHIFT) + 1;
@@ -357,7 +357,7 @@ query_segment_type (struct dcss_segment *seg)
  * -ENOSYS  : we are not running on VM
  * -EIO     : could not perform query diagnose
  * -ENOENT  : no such segment
- * -ENOTSUPP: multi-part segment cannot be used with linux
+ * -EOPNOTSUPP: multi-part segment cannot be used with linux
  * -ENOMEM  : out of memory
  * 0 .. 6   : type of segment as defined in include/asm-s390/extmem.h
  */
@@ -515,7 +515,7 @@ __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long
  * -ENOSYS  : we are not running on VM
  * -EIO     : could not perform query or load diagnose
  * -ENOENT  : no such segment
- * -ENOTSUPP: multi-part segment cannot be used with linux
+ * -EOPNOTSUPP: multi-part segment cannot be used with linux
  * -ENOSPC  : segment cannot be used (overlaps with storage)
  * -EBUSY   : segment can temporarily not be used (overlaps with dcss)
  * -ERANGE  : segment cannot be used (exceeds kernel mapping range)
@@ -742,7 +742,7 @@ void segment_warning(int rc, char *seg_name)
                 pr_err("Loading or querying DCSS %s resulted in a "
                        "hardware error\n", seg_name);
                 break;
-        case -ENOTSUPP:
+        case -EOPNOTSUPP:
                 pr_err("DCSS %s has multiple page ranges and cannot be "
                        "loaded or queried\n", seg_name);
                 break;
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index fc102e70d9c2..3040d7c78fe0 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -30,6 +30,7 @@
 #include <linux/kprobes.h>
 #include <linux/uaccess.h>
 #include <linux/hugetlb.h>
+#include <asm/asm-offsets.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
 #include <asm/s390_ext.h>
@@ -59,15 +60,13 @@ static inline int notify_page_fault(struct pt_regs *regs)
 {
         int ret = 0;
 
-#ifdef CONFIG_KPROBES
         /* kprobe_running() needs smp_processor_id() */
-        if (!user_mode(regs)) {
+        if (kprobes_built_in() && !user_mode(regs)) {
                 preempt_disable();
                 if (kprobe_running() && kprobe_fault_handler(regs, 14))
                         ret = 1;
                 preempt_enable();
         }
-#endif
         return ret;
 }
 
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index 765647952221..d5865e4024ce 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -143,33 +143,34 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
 }
 #endif
 
-void free_initmem(void)
+void free_init_pages(char *what, unsigned long begin, unsigned long end)
 {
-        unsigned long addr;
+        unsigned long addr = begin;
 
-        addr = (unsigned long)(&__init_begin);
-        for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
+        if (begin >= end)
+                return;
+        for (; addr < end; addr += PAGE_SIZE) {
                 ClearPageReserved(virt_to_page(addr));
                 init_page_count(virt_to_page(addr));
-                memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
+                memset((void *)(addr & PAGE_MASK), POISON_FREE_INITMEM,
+                       PAGE_SIZE);
                 free_page(addr);
                 totalram_pages++;
-        }
-        printk ("Freeing unused kernel memory: %ldk freed\n",
-                ((unsigned long)&__init_end - (unsigned long)&__init_begin) >> 10);
+        }
+        printk(KERN_INFO "Freeing %s: %luk freed\n", what, (end - begin) >> 10);
+}
+
+void free_initmem(void)
+{
+        free_init_pages("unused kernel memory",
+                        (unsigned long)&__init_begin,
+                        (unsigned long)&__init_end);
 }
 
 #ifdef CONFIG_BLK_DEV_INITRD
 void free_initrd_mem(unsigned long start, unsigned long end)
 {
-        if (start < end)
-                printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
-        for (; start < end; start += PAGE_SIZE) {
-                ClearPageReserved(virt_to_page(start));
-                init_page_count(virt_to_page(start));
-                free_page(start);
-                totalram_pages++;
-        }
+        free_init_pages("initrd memory", start, end);
 }
 #endif
 
diff --git a/arch/score/include/asm/pgtable.h b/arch/score/include/asm/pgtable.h
index 674934b40170..ccf38f06c57d 100644
--- a/arch/score/include/asm/pgtable.h
+++ b/arch/score/include/asm/pgtable.h
@@ -272,8 +272,9 @@ extern void __update_cache(struct vm_area_struct *vma,
         unsigned long address,  pte_t pte);
 
 static inline void update_mmu_cache(struct vm_area_struct *vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
+        pte_t pte = *ptep;
         __update_tlb(vma, address, pte);
         __update_cache(vma, address, pte);
 }
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index dfaf458d6702..7f001bbedb00 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -59,7 +59,7 @@ static unsigned long setup_zero_page(void)
 }
 
 #ifndef CONFIG_NEED_MULTIPLE_NODES
-static int __init page_is_ram(unsigned long pagenr)
+int page_is_ram(unsigned long pagenr)
 {
         if (pagenr >= min_low_pfn && pagenr < max_low_pfn)
                 return 1;
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 2121fbb2ff4c..05cef5061293 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -13,7 +13,6 @@ config SUPERH
         select HAVE_LMB
         select HAVE_OPROFILE
         select HAVE_GENERIC_DMA_COHERENT
-        select HAVE_IOREMAP_PROT if MMU
         select HAVE_ARCH_TRACEHOOK
         select HAVE_DMA_API_DEBUG
         select HAVE_DMA_ATTRS
@@ -22,6 +21,7 @@ config SUPERH
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_BZIP2
         select HAVE_KERNEL_LZMA
+        select HAVE_KERNEL_LZO
         select HAVE_SYSCALL_TRACEPOINTS
         select RTC_LIB
         select GENERIC_ATOMIC64
@@ -35,6 +35,7 @@ config SUPERH32
         def_bool ARCH = "sh"
         select HAVE_KPROBES
         select HAVE_KRETPROBES
+        select HAVE_IOREMAP_PROT if MMU && !X2TLB
         select HAVE_FUNCTION_TRACER
         select HAVE_FTRACE_MCOUNT_RECORD
         select HAVE_DYNAMIC_FTRACE
@@ -42,6 +43,8 @@ config SUPERH32
         select HAVE_FTRACE_NMI_ENTER if DYNAMIC_FTRACE
         select HAVE_FUNCTION_GRAPH_TRACER
         select HAVE_ARCH_KGDB
+        select HAVE_HW_BREAKPOINT
+        select PERF_EVENTS if HAVE_HW_BREAKPOINT
         select ARCH_HIBERNATION_POSSIBLE if MMU
 
 config SUPERH64
@@ -78,11 +81,12 @@ config GENERIC_HARDIRQS
 config GENERIC_HARDIRQS_NO__DO_IRQ
         def_bool y
 
-config GENERIC_IRQ_PROBE
+config IRQ_PER_CPU
         def_bool y
 
-config IRQ_PER_CPU
+config SPARSE_IRQ
         def_bool y
+        depends on SUPERH32
 
 config GENERIC_GPIO
         def_bool n
@@ -548,8 +552,7 @@ config SH_PCLK_FREQ
                               CPU_SUBTYPE_SH7203 || \
                               CPU_SUBTYPE_SH7206 || \
                               CPU_SUBTYPE_SH7263 || \
-                              CPU_SUBTYPE_MXG    || \
-                              CPU_SUBTYPE_SH7786
+                              CPU_SUBTYPE_MXG
         default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
         default "66000000" if CPU_SUBTYPE_SH4_202
         default "50000000"
@@ -563,7 +566,8 @@ config SH_CLK_CPG
 
 config SH_CLK_CPG_LEGACY
         depends on SH_CLK_CPG
-        def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
+        def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
+                      !CPU_SUBTYPE_SH7786
 
 config SH_CLK_MD
         int "CPU Mode Pin Setting"
@@ -725,18 +729,6 @@ config GUSA_RB
           LLSC, this should be more efficient than the other alternative of
           disabling interrupts around the atomic sequence.
 
-config SPARSE_IRQ
-        bool "Support sparse irq numbering"
-        depends on EXPERIMENTAL
-        help
-          This enables support for sparse irqs. This is useful in general
-          as most CPUs have a fairly sparse array of IRQ vectors, which
-          the irq_desc then maps directly on to. Systems with a high
-          number of off-chip IRQs will want to treat this as
-          experimental until they have been independently verified.
-
-          If you don't know what to do here, say N.
-
 endmenu
 
 menu "Boot options"
@@ -822,11 +814,15 @@ config MAPLE
 config PCI
         bool "PCI support"
         depends on SYS_SUPPORTS_PCI
+        select PCI_DOMAINS
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
           your box. If you have PCI, say Y, otherwise N.
 
+config PCI_DOMAINS
+        bool
+
 source "drivers/pci/pcie/Kconfig"
 
 source "drivers/pci/Kconfig"
diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index cd6e3ea598d5..ddf096c7d8bf 100644
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -68,7 +68,8 @@ config SH_STORE_QUEUES
 
 config SPECULATIVE_EXECUTION
         bool "Speculative subroutine return"
-        depends on CPU_SUBTYPE_SH7780 && EXPERIMENTAL
+        depends on EXPERIMENTAL
+        depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || CPU_SUBTYPE_SH7786
         help
           This enables support for a speculative instruction fetch for
           subroutine return. There are various pitfalls associated with
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index db91925c79d1..588579ac2e35 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -83,6 +83,7 @@ defaultimage-$(CONFIG_SH_AP325RXA)		:= uImage
 defaultimage-$(CONFIG_SH_7724_SOLUTION_ENGINE)  := uImage
 defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE)  := vmlinux
 defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE)  := vmlinux
+defaultimage-$(CONFIG_SH_SDK7786)               := vmlinux.bin
 
 # Set some sensible Kbuild defaults
 KBUILD_IMAGE            := $(defaultimage-y)
@@ -143,11 +144,11 @@ machdir-$(CONFIG_SH_AP325RXA)			+= mach-ap325rxa
 machdir-$(CONFIG_SH_KFR2R09)                    += mach-kfr2r09
 machdir-$(CONFIG_SH_ECOVEC)                     += mach-ecovec24
 machdir-$(CONFIG_SH_SDK7780)                    += mach-sdk7780
+machdir-$(CONFIG_SH_SDK7786)                    += mach-sdk7786
 machdir-$(CONFIG_SH_X3PROTO)                    += mach-x3proto
 machdir-$(CONFIG_SH_SH7763RDP)                  += mach-sh7763rdp
 machdir-$(CONFIG_SH_SH4202_MICRODEV)            += mach-microdev
 machdir-$(CONFIG_SH_LANDISK)                    += mach-landisk
-machdir-$(CONFIG_SH_TITAN)                      += mach-titan
 machdir-$(CONFIG_SH_LBOX_RE2)                   += mach-lboxre2
 machdir-$(CONFIG_SH_CAYMAN)                     += mach-cayman
 machdir-$(CONFIG_SH_RSK)                        += mach-rsk
@@ -203,8 +204,9 @@ endif
 libs-$(CONFIG_SUPERH32)         := arch/sh/lib/ $(libs-y)
 libs-$(CONFIG_SUPERH64)         := arch/sh/lib64/ $(libs-y)
 
-BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.srec uImage.bin \
-               zImage vmlinux.srec romImage
+BOOT_TARGETS = uImage uImage.bz2 uImage.gz uImage.lzma uImage.lzo \
+               uImage.srec uImage.bin zImage vmlinux.bin vmlinux.srec \
+               romImage
 PHONY += $(BOOT_TARGETS)
 
 all: $(KBUILD_IMAGE)
@@ -225,10 +227,12 @@ define archhelp
         @echo '  zImage                    - Compressed kernel image'
         @echo '  romImage                  - Compressed ROM image, if supported'
         @echo '  vmlinux.srec              - Create an ELF S-record'
+        @echo '  vmlinux.bin               - Create an uncompressed binary image'
         @echo '* uImage                    - Alias to bootable U-Boot image'
         @echo '  uImage.srec               - Create an S-record for U-Boot'
         @echo '  uImage.bin                - Kernel-only image for U-Boot (bin)'
         @echo '* uImage.gz                 - Kernel-only image for U-Boot (gzip)'
         @echo '  uImage.bz2                - Kernel-only image for U-Boot (bzip2)'
         @echo '  uImage.lzma               - Kernel-only image for U-Boot (lzma)'
+        @echo '  uImage.lzo                - Kernel-only image for U-Boot (lzo)'
 endef
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index aedd9deb5de2..938e87d51482 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -150,6 +150,14 @@ config SH_SDK7780
           Select SDK7780 if configuring for a Renesas SH7780 SDK7780R3
           evaluation board.
 
+config SH_SDK7786
+        bool "SDK7786"
+        depends on CPU_SUBTYPE_SH7786
+        select SYS_SUPPORTS_PCI
+        help
+          Select SDK7786 if configuring for a Renesas Technology Europe
+          SH7786-65nm board.
+
 config SH_HIGHLANDER
         bool "Highlander"
         depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
diff --git a/arch/sh/boards/Makefile b/arch/sh/boards/Makefile
index ce0f26381784..4f90f9b7a922 100644
--- a/arch/sh/boards/Makefile
+++ b/arch/sh/boards/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SH_SHMIN)		+= board-shmin.o
 obj-$(CONFIG_SH_EDOSK7760)      += board-edosk7760.o
 obj-$(CONFIG_SH_ESPT)           += board-espt.o
 obj-$(CONFIG_SH_POLARIS)        += board-polaris.o
+obj-$(CONFIG_SH_TITAN)          += board-titan.o
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index 99ffc5f1c0dd..efba450a0518 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -23,7 +23,7 @@
 #include <asm/heartbeat.h>
 #include <cpu/sh7720.h>
 
-#define LAN9115_READY   (ctrl_inl(0xA8000084UL) & 0x00000001UL)
+#define LAN9115_READY   (__raw_readl(0xA8000084UL) & 0x00000001UL)
 
 /* Prefer cmdline over RedBoot */
 static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
@@ -60,33 +60,33 @@ static void __init setup_chip_select(void)
 {
         /* CS2: LAN (0x08000000 - 0x0bffffff) */
         /* no idle cycles, normal space, 8 bit data bus */
-        ctrl_outl(0x36db0400, CS2BCR);
+        __raw_writel(0x36db0400, CS2BCR);
         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-        ctrl_outl(0x000003c0, CS2WCR);
+        __raw_writel(0x000003c0, CS2WCR);
 
         /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
         /* no idle cycles, normal space, 8 bit data bus */
-        ctrl_outl(0x00000200, CS4BCR);
+        __raw_writel(0x00000200, CS4BCR);
         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-        ctrl_outl(0x00100981, CS4WCR);
+        __raw_writel(0x00100981, CS4WCR);
 
         /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
         /* no idle cycles, normal space, 8 bit data bus */
-        ctrl_outl(0x00000200, CS5ABCR);
+        __raw_writel(0x00000200, CS5ABCR);
         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-        ctrl_outl(0x00100981, CS5AWCR);
+        __raw_writel(0x00100981, CS5AWCR);
 
         /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
         /* no idle cycles, normal space, 8 bit data bus */
-        ctrl_outl(0x00000200, CS5BBCR);
+        __raw_writel(0x00000200, CS5BBCR);
         /* (SW:1.5 WR:3 HW:1.5), ext. wait */
-        ctrl_outl(0x00100981, CS5BWCR);
+        __raw_writel(0x00100981, CS5BWCR);
 
         /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
         /* no idle cycles, normal space, 8 bit data bus */
-        ctrl_outl(0x00000200, CS6ABCR);
+        __raw_writel(0x00000200, CS6ABCR);
         /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
-        ctrl_outl(0x001009C1, CS6AWCR);
+        __raw_writel(0x001009C1, CS6AWCR);
 }
 
 static void __init setup_port_multiplexing(void)
@@ -94,71 +94,71 @@ static void __init setup_port_multiplexing(void)
         /* A7 GPO(LED8);     A6 GPO(LED7);     A5 GPO(LED6);      A4 GPO(LED5);
          * A3 GPO(LED4);     A2 GPO(LED3);     A1 GPO(LED2);      A0 GPO(LED1);
          */
-        ctrl_outw(0x5555, PORT_PACR);   /* 01 01 01 01 01 01 01 01 */
+        __raw_writew(0x5555, PORT_PACR);        /* 01 01 01 01 01 01 01 01 */
 
         /* B7 GPO(RST4);   B6 GPO(RST3);  B5 GPO(RST2);    B4 GPO(RST1);
          * B3 GPO(PB3);    B2 GPO(PB2);   B1 GPO(PB1);     B0 GPO(PB0);
          */
-        ctrl_outw(0x5555, PORT_PBCR);   /* 01 01 01 01 01 01 01 01 */
+        __raw_writew(0x5555, PORT_PBCR);        /* 01 01 01 01 01 01 01 01 */
 
         /* C7 GPO(PC7);   C6 GPO(PC6);    C5 GPO(PC5);     C4 GPO(PC4);
          * C3 LCD_DATA3;  C2 LCD_DATA2;   C1 LCD_DATA1;    C0 LCD_DATA0;
          */
-        ctrl_outw(0x5500, PORT_PCCR);   /* 01 01 01 01 00 00 00 00 */
+        __raw_writew(0x5500, PORT_PCCR);        /* 01 01 01 01 00 00 00 00 */
 
         /* D7 GPO(PD7); D6 GPO(PD6);    D5 GPO(PD5);       D4 GPO(PD4);
          * D3 GPO(PD3); D2 GPO(PD2);    D1 GPO(PD1);       D0 GPO(PD0);
          */
-        ctrl_outw(0x5555, PORT_PDCR);   /* 01 01 01 01 01 01 01 01 */
+        __raw_writew(0x5555, PORT_PDCR);        /* 01 01 01 01 01 01 01 01 */
 
         /* E7 (x);        E6 GPI(nu);    E5 GPI(nu);      E4 LCD_M_DISP;
          * E3 LCD_CL1;    E2 LCD_CL2;    E1 LCD_DON;      E0 LCD_FLM;
          */
-        ctrl_outw(0x3C00, PORT_PECR);   /* 00 11 11 00 00 00 00 00 */
+        __raw_writew(0x3C00, PORT_PECR);        /* 00 11 11 00 00 00 00 00 */
 
         /* F7 (x);           F6 DA1(VLCD);     F5 DA0(nc);        F4 AN3;
          * F3 AN2(MID_AD);   F2 AN1(EARTH_AD); F1 AN0(TEMP);      F0 GPI+(nc);
          */
-        ctrl_outw(0x0002, PORT_PFCR);   /* 00 00 00 00 00 00 00 10 */
+        __raw_writew(0x0002, PORT_PFCR);        /* 00 00 00 00 00 00 00 10 */
 
         /* G7 (x);        G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
          * G3 GPI(KEY1);  G2 GPO(LED11);        G1 GPO(LED10);     G0 GPO(LED9);
          */
-        ctrl_outw(0x03D5, PORT_PGCR);   /* 00 00 00 11 11 01 01 01 */
+        __raw_writew(0x03D5, PORT_PGCR);        /* 00 00 00 11 11 01 01 01 */
 
         /* H7 (x);            H6 /RAS(BRAS);      H5 /CAS(BCAS); H4 CKE(BCKE);
          * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR;   H0 USB1_PWR;
          */
-        ctrl_outw(0x0050, PORT_PHCR);   /* 00 00 00 00 01 01 00 00 */
+        __raw_writew(0x0050, PORT_PHCR);        /* 00 00 00 00 01 01 00 00 */
 
         /* J7 (x);        J6 AUDCK;        J5 ASEBRKAK;     J4 AUDATA3;
          * J3 AUDATA2;    J2 AUDATA1;      J1 AUDATA0;      J0 AUDSYNC;
          */
-        ctrl_outw(0x0000, PORT_PJCR);   /* 00 00 00 00 00 00 00 00 */
+        __raw_writew(0x0000, PORT_PJCR);        /* 00 00 00 00 00 00 00 00 */
 
         /* K7 (x);          K6 (x);          K5 (x);       K4 (x);
          * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
          */
-        ctrl_outw(0x00FF, PORT_PKCR);   /* 00 00 00 00 11 11 11 11 */
+        __raw_writew(0x00FF, PORT_PKCR);        /* 00 00 00 00 11 11 11 11 */
 
         /* L7 TRST;        L6 TMS;           L5 TDO;              L4 TDI;
          * L3 TCK;         L2 (x);           L1 (x);              L0 (x);
          */
-        ctrl_outw(0x0000, PORT_PLCR);   /* 00 00 00 00 00 00 00 00 */
+        __raw_writew(0x0000, PORT_PLCR);        /* 00 00 00 00 00 00 00 00 */
 
         /* M7 GPO(CURRENT_SINK);    M6 GPO(PWR_SWITCH);     M5 GPO(LAN_SPEED);
          * M4 GPO(LAN_RESET);       M3 GPO(BUZZER);         M2 GPO(LCD_BL);
          * M1 CS5B(CAN3_CS);        M0 GPI+(nc);
          */
-        ctrl_outw(0x5552, PORT_PMCR);      /* 01 01 01 01 01 01 00 10 */
+        __raw_writew(0x5552, PORT_PMCR);           /* 01 01 01 01 01 01 00 10 */
 
         /* CURRENT_SINK=off,    PWR_SWITCH=off, LAN_SPEED=100MBit,
          * LAN_RESET=off,       BUZZER=off,     LCD_BL=off
          */
 #if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
-        ctrl_outb(0x30, PORT_PMDR);
+        __raw_writeb(0x30, PORT_PMDR);
 #elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
-        ctrl_outb(0xF0, PORT_PMDR);
+        __raw_writeb(0xF0, PORT_PMDR);
 #else
 #error Unknown revision of PLATFORM_MP_R2
 #endif
@@ -167,8 +167,8 @@ static void __init setup_port_multiplexing(void)
          * P4 GPO(nu);         P3 IRQ3(LAN_IRQ);  P2 IRQ2(CAN3_IRQ);
          * P1 IRQ1(CAN2_IRQ);  P0 IRQ0(CAN1_IRQ)
          */
-        ctrl_outw(0x0100, PORT_PPCR);   /* 00 00 00 01 00 00 00 00 */
-        ctrl_outb(0x10, PORT_PPDR);
+        __raw_writew(0x0100, PORT_PPCR);        /* 00 00 00 01 00 00 00 00 */
+        __raw_writeb(0x10, PORT_PPDR);
 
         /* R7 A25;           R6 A24;         R5 A23;              R4 A22;
          * R3 A21;           R2 A20;         R1 A19;              R0 A0;
@@ -185,22 +185,22 @@ static void __init setup_port_multiplexing(void)
         /* S7 (x);              S6 (x);        S5 (x);       S4 GPO(EEPROM_CS2);
          * S3 GPO(EEPROM_CS1);  S2 SIOF0_TXD;  S1 SIOF0_RXD; S0 SIOF0_SCK;
          */
-        ctrl_outw(0x0140, PORT_PSCR);   /* 00 00 00 01 01 00 00 00 */
+        __raw_writew(0x0140, PORT_PSCR);        /* 00 00 00 01 01 00 00 00 */
 
         /* T7 (x);         T6 (x);        T5 (x);         T4 COM1_CTS;
          * T3 COM1_RTS;    T2 COM1_TXD;   T1 COM1_RXD;    T0 GPO(WDOG)
          */
-        ctrl_outw(0x0001, PORT_PTCR);   /* 00 00 00 00 00 00 00 01 */
+        __raw_writew(0x0001, PORT_PTCR);        /* 00 00 00 00 00 00 00 01 */
 
         /* U7 (x);           U6 (x);       U5 (x);        U4 GPI+(/AC_FAULT);
          * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD;  U0 TOUCH_SCK;
          */
-        ctrl_outw(0x0240, PORT_PUCR);   /* 00 00 00 10 01 00 00 00 */
+        __raw_writew(0x0240, PORT_PUCR);        /* 00 00 00 10 01 00 00 00 */
 
         /* V7 (x);        V6 (x);       V5 (x);           V4 GPO(MID2);
          * V3 GPO(MID1);  V2 CARD_TxD;  V1 CARD_RxD;      V0 GPI+(/BAT_FAULT);
          */
-        ctrl_outw(0x0142, PORT_PVCR);   /* 00 00 00 01 01 00 00 10 */
+        __raw_writew(0x0142, PORT_PVCR);        /* 00 00 00 01 01 00 00 10 */
 }
 
 static void __init mpr2_setup(char **cmdline_p)
@@ -209,24 +209,24 @@ static void __init mpr2_setup(char **cmdline_p)
          * /PCC_CD1, /PCC_CD2,  PCC_BVD1, PCC_BVD2,
          * /IOIS16,  IRQ4,      IRQ5,     USB1d_SUSPEND
          */
-        ctrl_outw(0xAABC, PORT_PSELA);
+        __raw_writew(0xAABC, PORT_PSELA);
         /* set Pin Select Register B:
          * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
          * LCD_VEPWC,  IIC_SDA,    IIC_SCL, Reserved
          */
-        ctrl_outw(0x3C00, PORT_PSELB);
+        __raw_writew(0x3C00, PORT_PSELB);
         /* set Pin Select Register C:
          * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
          */
-        ctrl_outw(0x0000, PORT_PSELC);
+        __raw_writew(0x0000, PORT_PSELC);
         /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
          * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
          */
-        ctrl_outw(0x0000, PORT_PSELD);
+        __raw_writew(0x0000, PORT_PSELD);
         /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
-        ctrl_outw(0x0101, PORT_UTRCTL);
+        __raw_writew(0x0101, PORT_UTRCTL);
         /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
-        ctrl_outw(0xA5C0, PORT_UCLKCR_W);
+        __raw_writew(0xA5C0, PORT_UCLKCR_W);
 
         setup_chip_select();
 
diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c
index 62607eb51004..594866356c24 100644
--- a/arch/sh/boards/board-polaris.c
+++ b/arch/sh/boards/board-polaris.c
@@ -59,15 +59,12 @@ static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
 static struct heartbeat_data heartbeat_data = {
         .bit_pos        = heartbeat_bit_pos,
         .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
-        .regsize        = 8,
 };
 
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PORT_PCDR,
-                .end    = PORT_PCDR,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PORT_PCDR,
+        .end    = PORT_PCDR,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
 };
 
 static struct platform_device heartbeat_device = {
@@ -76,8 +73,8 @@ static struct platform_device heartbeat_device = {
         .dev    = {
                 .platform_data  = &heartbeat_data,
         },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 static struct platform_device *polaris_devices[] __initdata = {
@@ -92,15 +89,15 @@ static int __init polaris_initialise(void)
         printk(KERN_INFO "Configuring Polaris external bus\n");
 
         /* Configure area 5 with 2 wait states */
-        wcr = ctrl_inw(WCR2);
+        wcr = __raw_readw(WCR2);
         wcr &= (~AREA5_WAIT_CTRL);
         wcr |= (WAIT_STATES_10 << 10);
-        ctrl_outw(wcr, WCR2);
+        __raw_writew(wcr, WCR2);
 
         /* Configure area 5 for 32-bit access */
-        bcr_mask = ctrl_inw(BCR2);
+        bcr_mask = __raw_readw(BCR2);
         bcr_mask |= 1 << 10;
-        ctrl_outw(bcr_mask, BCR2);
+        __raw_writew(bcr_mask, BCR2);
 
         return platform_add_devices(polaris_devices,
                                     ARRAY_SIZE(polaris_devices));
@@ -131,13 +128,13 @@ static struct ipr_desc ipr_irq_desc = {
 static void __init init_polaris_irq(void)
 {
         /* Disable all interrupts */
-        ctrl_outw(0, BCR_ILCRA);
-        ctrl_outw(0, BCR_ILCRB);
-        ctrl_outw(0, BCR_ILCRC);
-        ctrl_outw(0, BCR_ILCRD);
-        ctrl_outw(0, BCR_ILCRE);
-        ctrl_outw(0, BCR_ILCRF);
-        ctrl_outw(0, BCR_ILCRG);
+        __raw_writew(0, BCR_ILCRA);
+        __raw_writew(0, BCR_ILCRB);
+        __raw_writew(0, BCR_ILCRC);
+        __raw_writew(0, BCR_ILCRD);
+        __raw_writew(0, BCR_ILCRE);
+        __raw_writew(0, BCR_ILCRF);
+        __raw_writew(0, BCR_ILCRG);
 
         register_ipr_controller(&ipr_irq_desc);
 }
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index e5a8a2fde39c..fe7e686c94ac 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -21,6 +21,7 @@
 #include <linux/i2c-algo-pca.h>
 #include <linux/usb/r8a66597.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <linux/clk.h>
 #include <linux/errno.h>
 #include <mach/sh7785lcr.h>
@@ -32,26 +33,17 @@
  * NOTE: This board has 2 physical memory maps.
  *       Please look at include/asm-sh/sh7785lcr.h or hardware manual.
  */
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PLD_LEDCR,
-                .end    = PLD_LEDCR,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 8,
+static struct resource heartbeat_resource = {
+        .start  = PLD_LEDCR,
+        .end    = PLD_LEDCR,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev    = {
-                .platform_data  = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 static struct mtd_partition nor_flash_partitions[] = {
@@ -341,8 +333,14 @@ static void __init sh7785lcr_setup(char **cmdline_p)
         pm_power_off = sh7785lcr_power_off;
 
         /* sm501 DRAM configuration */
-        sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL;
-        writel(0x000307c2, sm501_reg);
+        sm501_reg = ioremap_nocache(SM107_REG_ADDR, SM501_DRAM_CONTROL);
+        if (!sm501_reg) {
+                printk(KERN_ERR "%s: ioremap error.\n", __func__);
+                return;
+        }
+
+        writel(0x000307c2, sm501_reg + SM501_DRAM_CONTROL);
+        iounmap(sm501_reg);
 }
 
 /* Return the board specific boot mode pin configuration */
diff --git a/arch/sh/boards/board-shmin.c b/arch/sh/boards/board-shmin.c
index b1dcbbc89188..325bed53b87e 100644
--- a/arch/sh/boards/board-shmin.c
+++ b/arch/sh/boards/board-shmin.c
@@ -17,8 +17,8 @@
 
 static void __init init_shmin_irq(void)
 {
-        ctrl_outw(0x2a00, PFC_PHCR);    // IRQ0-3=IRQ
-        ctrl_outw(0x0aaa, INTC_ICR1);   // IRQ0-3=IRQ-mode,Low-active.
+        __raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
+        __raw_writew(0x0aaa, INTC_ICR1);        // IRQ0-3=IRQ-mode,Low-active.
         plat_irq_setup_pins(IRQ_MODE_IRQ);
 }
 
diff --git a/arch/sh/boards/mach-titan/setup.c b/arch/sh/boards/board-titan.c
index 81e7e0f03863..94c36c7bc0b3 100644
--- a/arch/sh/boards/mach-titan/setup.c
+++ b/arch/sh/boards/board-titan.c
@@ -19,26 +19,6 @@ static void __init init_titan_irq(void)
 }
 
 static struct sh_machine_vector mv_titan __initmv = {
-        .mv_name =      "Titan",
-
-        .mv_inb =       titan_inb,
-        .mv_inw =       titan_inw,
-        .mv_inl =       titan_inl,
-        .mv_outb =      titan_outb,
-        .mv_outw =      titan_outw,
-        .mv_outl =      titan_outl,
-
-        .mv_inb_p =     titan_inb_p,
-        .mv_inw_p =     titan_inw,
-        .mv_inl_p =     titan_inl,
-        .mv_outb_p =    titan_outb_p,
-        .mv_outw_p =    titan_outw,
-        .mv_outl_p =    titan_outl,
-
-        .mv_insl =      titan_insl,
-        .mv_outsl =     titan_outsl,
-
-        .mv_ioport_map = titan_ioport_map,
-
-        .mv_init_irq =  init_titan_irq,
+        .mv_name        = "Titan",
+        .mv_init_irq    = init_titan_irq,
 };
diff --git a/arch/sh/boards/board-urquell.c b/arch/sh/boards/board-urquell.c
index 36b8bac9b124..a9bd6e3ee10b 100644
--- a/arch/sh/boards/board-urquell.c
+++ b/arch/sh/boards/board-urquell.c
@@ -2,7 +2,7 @@
  * Renesas Technology Corp. SH7786 Urquell Support.
  *
  * Copyright (C) 2008  Kuninori Morimoto <morimoto.kuninori@renesas.com>
- * Copyright (C) 2009  Paul Mundt
+ * Copyright (C) 2009, 2010  Paul Mundt
  *
  * Based on board-sh7785lcr.c
  * Copyright (C) 2008  Yoshihiro Shimoda
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
+#include <linux/clk.h>
 #include <mach/urquell.h>
 #include <cpu/sh7786.h>
 #include <asm/heartbeat.h>
@@ -50,26 +51,17 @@
  */
 
 /* HeartBeat */
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = BOARDREG(SLEDR),
-                .end    = BOARDREG(SLEDR),
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 16,
+static struct resource heartbeat_resource = {
+        .start  = BOARDREG(SLEDR),
+        .end    = BOARDREG(SLEDR),
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev    = {
-                .platform_data  = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 /* LAN91C111 */
@@ -184,6 +176,27 @@ static int urquell_mode_pins(void)
         return __raw_readw(UBOARDREG(MDSWMR));
 }
 
+static int urquell_clk_init(void)
+{
+        struct clk *clk;
+        int ret;
+
+        /*
+         * Only handle the EXTAL case, anyone interfacing a crystal
+         * resonator will need to provide their own input clock.
+         */
+        if (test_mode_pin(MODE_PIN9))
+                return -EINVAL;
+
+        clk = clk_get(NULL, "extal");
+        if (!clk || IS_ERR(clk))
+                return PTR_ERR(clk);
+        ret = clk_set_rate(clk, 33333333);
+        clk_put(clk);
+
+        return ret;
+}
+
 /* Initialize the board */
 static void __init urquell_setup(char **cmdline_p)
 {
@@ -200,4 +213,5 @@ static struct sh_machine_vector mv_urquell __initmv = {
         .mv_setup       = urquell_setup,
         .mv_init_irq    = urquell_init_irq,
         .mv_mode_pins   = urquell_mode_pins,
+        .mv_clk_init    = urquell_clk_init,
 };
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 1f5fa5c44f6d..57e37e284208 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -159,21 +159,21 @@ static void ap320_wvga_power_on(void *board_data)
         msleep(100);
 
         /* ASD AP-320/325 LCD ON */
-        ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
+        __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
 
         /* backlight */
         gpio_set_value(GPIO_PTS3, 0);
-        ctrl_outw(0x100, FPGA_BKLREG);
+        __raw_writew(0x100, FPGA_BKLREG);
 }
 
 static void ap320_wvga_power_off(void *board_data)
 {
         /* backlight */
-        ctrl_outw(0, FPGA_BKLREG);
+        __raw_writew(0, FPGA_BKLREG);
         gpio_set_value(GPIO_PTS3, 1);
 
         /* ASD AP-320/325 LCD OFF */
-        ctrl_outw(0, FPGA_LCDREG);
+        __raw_writew(0, FPGA_LCDREG);
 }
 
 static struct sh_mobile_lcdc_info lcdc_info = {
@@ -420,7 +420,7 @@ static struct resource sdhi0_cn3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 101,
+                .start  = 100,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -443,7 +443,7 @@ static struct resource sdhi1_cn7_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 24,
+                .start  = 23,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -471,8 +471,8 @@ static struct i2c_board_info ap325rxa_i2c_camera[] = {
 };
 
 static struct ov772x_camera_info ov7725_info = {
-        .buswidth       = SOCAM_DATAWIDTH_8,
-        .flags          = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
+        .flags          = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP | \
+                          OV772X_FLAG_8BIT,
         .edgectrl       = OV772X_AUTO_EDGECTRL(0xf, 0),
 };
 
@@ -595,7 +595,7 @@ static int __init ap325rxa_devices_setup(void)
         gpio_request(GPIO_PTZ4, NULL);
         gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
 
-        ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
+        __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
 
         /* FLCTL */
         gpio_request(GPIO_FN_FCE, NULL);
@@ -613,9 +613,9 @@ static int __init ap325rxa_devices_setup(void)
         gpio_request(GPIO_FN_FWE, NULL);
         gpio_request(GPIO_FN_FRB, NULL);
 
-        ctrl_outw(0, PORT_HIZCRC);
-        ctrl_outw(0xFFFF, PORT_DRVCRA);
-        ctrl_outw(0xFFFF, PORT_DRVCRB);
+        __raw_writew(0, PORT_HIZCRC);
+        __raw_writew(0xFFFF, PORT_DRVCRA);
+        __raw_writew(0xFFFF, PORT_DRVCRB);
 
         platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
 
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index 33f770856319..1394b078db36 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -66,9 +66,9 @@ static void enable_cayman_irq(unsigned int irq)
         reg = EPLD_MASK_BASE + ((irq / 8) << 2);
         bit = 1<<(irq % 8);
         local_irq_save(flags);
-        mask = ctrl_inl(reg);
+        mask = __raw_readl(reg);
         mask |= bit;
-        ctrl_outl(mask, reg);
+        __raw_writel(mask, reg);
         local_irq_restore(flags);
 }
 
@@ -83,9 +83,9 @@ void disable_cayman_irq(unsigned int irq)
         reg = EPLD_MASK_BASE + ((irq / 8) << 2);
         bit = 1<<(irq % 8);
         local_irq_save(flags);
-        mask = ctrl_inl(reg);
+        mask = __raw_readl(reg);
         mask &= ~bit;
-        ctrl_outl(mask, reg);
+        __raw_writel(mask, reg);
         local_irq_restore(flags);
 }
 
@@ -109,8 +109,8 @@ int cayman_irq_demux(int evt)
                 unsigned long status;
                 int i;
 
-                status = ctrl_inl(EPLD_STATUS_BASE) &
-                         ctrl_inl(EPLD_MASK_BASE) & 0xff;
+                status = __raw_readl(EPLD_STATUS_BASE) &
+                         __raw_readl(EPLD_MASK_BASE) & 0xff;
                 if (status == 0) {
                         irq = -1;
                 } else {
@@ -126,8 +126,8 @@ int cayman_irq_demux(int evt)
                 unsigned long status;
                 int i;
 
-                status = ctrl_inl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
-                         ctrl_inl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
+                status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
+                         __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
                 if (status == 0) {
                         irq = -1;
                 } else {
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index f55fc8e795e9..d932667410ab 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -135,3 +135,30 @@ int systemasic_irq_demux(int irq)
         /* Not reached */
         return irq;
 }
+
+void systemasic_irq_init(void)
+{
+        int i, nid = cpu_to_node(boot_cpu_data);
+
+        /* Assign all virtual IRQs to the System ASIC int. handler */
+        for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) {
+                unsigned int irq;
+
+                irq = create_irq_nr(i, nid);
+                if (unlikely(irq == 0)) {
+                        pr_err("%s: failed hooking irq %d for systemasic\n",
+                               __func__, i);
+                        return;
+                }
+
+                if (unlikely(irq != i)) {
+                        pr_err("%s: got irq %d but wanted %d, bailing.\n",
+                               __func__, irq, i);
+                        destroy_irq(irq);
+                        return;
+                }
+
+                set_irq_chip_and_handler(i, &systemasic_int,
+                                         handle_level_irq);
+        }
+}
diff --git a/arch/sh/boards/mach-dreamcast/rtc.c b/arch/sh/boards/mach-dreamcast/rtc.c
index a7433685798d..061d65714fcc 100644
--- a/arch/sh/boards/mach-dreamcast/rtc.c
+++ b/arch/sh/boards/mach-dreamcast/rtc.c
@@ -35,11 +35,11 @@ static void aica_rtc_gettimeofday(struct timespec *ts)
         unsigned long val1, val2;
 
         do {
-                val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
-                        (ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
+                val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
+                        (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
 
-                val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
-                        (ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
+                val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
+                        (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
         } while (val1 != val2);
 
         ts->tv_sec = val1 - TWENTY_YEARS;
@@ -60,14 +60,14 @@ static int aica_rtc_settimeofday(const time_t secs)
         unsigned long adj = secs + TWENTY_YEARS;
 
         do {
-                ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
-                ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L);
+                __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
+                __raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
 
-                val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
-                        (ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
+                val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
+                        (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
 
-                val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) |
-                        (ctrl_inl(AICA_RTC_SECS_L) & 0xffff);
+                val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
+                        (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
         } while (val1 != val2);
 
         return 0;
diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c
index a4b7402d6176..ad1a4db72e04 100644
--- a/arch/sh/boards/mach-dreamcast/setup.c
+++ b/arch/sh/boards/mach-dreamcast/setup.c
@@ -28,25 +28,8 @@
 #include <asm/machvec.h>
 #include <mach/sysasic.h>
 
-extern struct irq_chip systemasic_int;
-extern void aica_time_init(void);
-extern int systemasic_irq_demux(int);
-
 static void __init dreamcast_setup(char **cmdline_p)
 {
-        int i;
-
-        /* Mask all hardware events */
-        /* XXX */
-
-        /* Acknowledge any previous events */
-        /* XXX */
-
-        /* Assign all virtual IRQs to the System ASIC int. handler */
-        for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
-                set_irq_chip_and_handler(i, &systemasic_int,
-                                         handle_level_irq);
-
         board_time_init = aica_time_init;
 }
 
@@ -54,4 +37,5 @@ static struct sh_machine_vector mv_dreamcast __initmv = {
         .mv_name                = "Sega Dreamcast",
         .mv_setup               = dreamcast_setup,
         .mv_irq_demux           = systemasic_irq_demux,
+        .mv_init_irq            = systemasic_irq_init,
 };
diff --git a/arch/sh/boards/mach-ecovec24/sdram.S b/arch/sh/boards/mach-ecovec24/sdram.S
index 833440044407..3963c6f23d52 100644
--- a/arch/sh/boards/mach-ecovec24/sdram.S
+++ b/arch/sh/boards/mach-ecovec24/sdram.S
@@ -37,6 +37,10 @@ ENTRY(ecovec24_sdram_enter_end)
         .balign 4
 ENTRY(ecovec24_sdram_leave_start)
 
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_RSTANDBY, r0
+        bf      resume_rstandby
+
         /* DBSC: put memory in auto-refresh mode */
 
         ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
@@ -49,4 +53,59 @@ ENTRY(ecovec24_sdram_leave_start)
         rts
          nop
 
+resume_rstandby:
+
+        /* DBSC: re-initialize and put in auto-refresh */
+
+        ED 0xFD000108, 0x00000181 /* DBPDCNT0 */
+        ED 0xFD000020, 0x015B0002 /* DBCONF */
+        ED 0xFD000030, 0x03071502 /* DBTR0 */
+        ED 0xFD000034, 0x02020102 /* DBTR1 */
+        ED 0xFD000038, 0x01090405 /* DBTR2 */
+        ED 0xFD00003C, 0x00000002 /* DBTR3 */
+        ED 0xFD000008, 0x00000005 /* DBKIND */
+        ED 0xFD000040, 0x00000001 /* DBRFPDN0 */
+        ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
+        ED 0xFD000018, 0x00000001 /* DBCKECNT */
+
+        mov     #100,r0
+WAIT_400NS:
+        dt      r0
+        bf      WAIT_400NS
+
+        ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
+        ED 0xFD000060, 0x00020000 /* DBMRCNT (EMR2) */
+        ED 0xFD000060, 0x00030000 /* DBMRCNT (EMR3) */
+        ED 0xFD000060, 0x00010004 /* DBMRCNT (EMR) */
+        ED 0xFD000060, 0x00000532 /* DBMRCNT (MRS) */
+        ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
+        ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
+        ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
+        ED 0xFD000060, 0x00000432 /* DBMRCNT (MRS) */
+        ED 0xFD000060, 0x000103c0 /* DBMRCNT (EMR) */
+        ED 0xFD000060, 0x00010040 /* DBMRCNT (EMR) */
+
+        mov     #100,r0
+WAIT_400NS_2:
+        dt      r0
+        bf      WAIT_400NS_2
+
+        ED 0xFD000010, 0x00000001 /* DBEN */
+        ED 0xFD000044, 0x0000050f /* DBRFPDN1 */
+        ED 0xFD000048, 0x236800e6 /* DBRFPDN2 */
+
+        mov.l   DUMMY,r0
+        mov.l   @r0, r1 /* force single dummy read */
+
+        ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
+        ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
+        ED 0xFD000108, 0x00000080 /* DBPDCNT0 */
+        ED 0xFD000040, 0x00010000 /* DBRFPDN0 */
+
+        rts
+         nop
+
+        .balign 4
+DUMMY:  .long   0xac400000
+
 ENTRY(ecovec24_sdram_leave_end)
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 5c246289b4f0..39ed8722d11a 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -64,18 +64,16 @@
 
 /* Heartbeat */
 static unsigned char led_pos[] = { 0, 1, 2, 3 };
+
 static struct heartbeat_data heartbeat_data = {
-        .regsize = 8,
         .nr_bits = 4,
         .bit_pos = led_pos,
 };
 
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = 0xA405012C, /* PTG */
-                .end    = 0xA405012E - 1,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = 0xA405012C, /* PTG */
+        .end    = 0xA405012E - 1,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
 };
 
 static struct platform_device heartbeat_device = {
@@ -84,8 +82,8 @@ static struct platform_device heartbeat_device = {
         .dev = {
                 .platform_data = &heartbeat_data,
         },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 /* MTD */
@@ -455,7 +453,7 @@ static struct resource sdhi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 101,
+                .start  = 100,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -491,7 +489,7 @@ static struct resource sdhi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 24,
+                .start  = 23,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -698,13 +696,13 @@ static struct platform_device camera_devices[] = {
 #define FCLKBCR         0xa415000c
 static void fsimck_init(struct clk *clk)
 {
-        u32 status = ctrl_inl(clk->enable_reg);
+        u32 status = __raw_readl(clk->enable_reg);
 
         /* use external clock */
         status &= ~0x000000ff;
         status |= 0x00000080;
 
-        ctrl_outl(status, clk->enable_reg);
+        __raw_writel(status, clk->enable_reg);
 }
 
 static struct clk_ops fsimck_clk_ops = {
@@ -753,6 +751,26 @@ static struct platform_device fsi_device = {
         },
 };
 
+/* IrDA */
+static struct resource irda_resources[] = {
+        [0] = {
+                .name   = "IrDA",
+                .start  = 0xA45D0000,
+                .end    = 0xA45D0049,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 20,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device irda_device = {
+        .name           = "sh_sir",
+        .num_resources  = ARRAY_SIZE(irda_resources),
+        .resource       = irda_resources,
+};
+
 static struct platform_device *ecovec_devices[] __initdata = {
         &heartbeat_device,
         &nor_flash_device,
@@ -773,8 +791,10 @@ static struct platform_device *ecovec_devices[] __initdata = {
         &camera_devices[1],
         &camera_devices[2],
         &fsi_device,
+        &irda_device,
 };
 
+#ifdef CONFIG_I2C
 #define EEPROM_ADDR 0x50
 static u8 mac_read(struct i2c_adapter *a, u8 command)
 {
@@ -817,6 +837,12 @@ static void __init sh_eth_init(struct sh_eth_plat_data *pd)
                 msleep(10);
         }
 }
+#else
+static void __init sh_eth_init(struct sh_eth_plat_data *pd)
+{
+        pr_err("unable to read sh_eth MAC address\n");
+}
+#endif
 
 #define PORT_HIZA 0xA4050158
 #define IODRIVEA  0xA405018A
@@ -831,7 +857,8 @@ static int __init arch_setup(void)
         struct clk *clk;
 
         /* register board specific self-refresh code */
-        sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
+        sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
+                                        SUSP_SH_RSTANDBY,
                                         &ecovec24_sdram_enter_start,
                                         &ecovec24_sdram_enter_end,
                                         &ecovec24_sdram_leave_start,
@@ -855,7 +882,7 @@ static int __init arch_setup(void)
         gpio_direction_output(GPIO_PTG1, 0);
         gpio_direction_output(GPIO_PTG2, 0);
         gpio_direction_output(GPIO_PTG3, 0);
-        ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
+        __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
 
         /* enable SH-Eth */
         gpio_request(GPIO_PTA1, NULL);
@@ -875,16 +902,16 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_LNKSTA,       NULL);
 
         /* enable USB */
-        ctrl_outw(0x0000, 0xA4D80000);
-        ctrl_outw(0x0000, 0xA4D90000);
+        __raw_writew(0x0000, 0xA4D80000);
+        __raw_writew(0x0000, 0xA4D90000);
         gpio_request(GPIO_PTB3,  NULL);
         gpio_request(GPIO_PTB4,  NULL);
         gpio_request(GPIO_PTB5,  NULL);
         gpio_direction_input(GPIO_PTB3);
         gpio_direction_output(GPIO_PTB4, 0);
         gpio_direction_output(GPIO_PTB5, 0);
-        ctrl_outw(0x0600, 0xa40501d4);
-        ctrl_outw(0x0600, 0xa4050192);
+        __raw_writew(0x0600, 0xa40501d4);
+        __raw_writew(0x0600, 0xa4050192);
 
         if (gpio_get_value(GPIO_PTB3)) {
                 printk(KERN_INFO "USB1 function is selected\n");
@@ -925,7 +952,7 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_LCDVSYN,  NULL);
         gpio_request(GPIO_FN_LCDDON,   NULL);
         gpio_request(GPIO_FN_LCDLCLK,  NULL);
-        ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
+        __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
 
         gpio_request(GPIO_PTE6, NULL);
         gpio_request(GPIO_PTU1, NULL);
@@ -937,7 +964,7 @@ static int __init arch_setup(void)
         gpio_direction_output(GPIO_PTA2, 0);
 
         /* I/O buffer drive ability is high */
-        ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
+        __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
 
         if (gpio_get_value(GPIO_PTE6)) {
                 /* DVI */
@@ -1069,7 +1096,7 @@ static int __init arch_setup(void)
         gpio_direction_output(GPIO_PTB7, 0);
 
         /* I/O buffer drive ability is high for SDHI1 */
-        ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
+        __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
 #else
         /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
         gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
@@ -1107,6 +1134,11 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_FSIOBLRCK,  NULL);
         gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
 
+        /* set SPU2 clock to 83.4 MHz */
+        clk = clk_get(NULL, "spu_clk");
+        clk_set_rate(clk, clk_round_rate(clk, 83333333));
+        clk_put(clk);
+
         /* change parent of FSI B */
         clk = clk_get(NULL, "fsib_clk");
         clk_register(&fsimckb_clk);
@@ -1123,6 +1155,17 @@ static int __init arch_setup(void)
         gpio_request(GPIO_FN_INTC_IRQ1, NULL);
         gpio_direction_input(GPIO_FN_INTC_IRQ1);
 
+        /* set VPU clock to 166 MHz */
+        clk = clk_get(NULL, "vpu_clk");
+        clk_set_rate(clk, clk_round_rate(clk, 166000000));
+        clk_put(clk);
+
+        /* enable IrDA */
+        gpio_request(GPIO_FN_IRDA_OUT, NULL);
+        gpio_request(GPIO_FN_IRDA_IN,  NULL);
+        gpio_request(GPIO_PTU5, NULL);
+        gpio_direction_output(GPIO_PTU5, 0);
+
         /* enable I2C device */
         i2c_register_board_info(0, i2c0_devices,
                                 ARRAY_SIZE(i2c0_devices));
diff --git a/arch/sh/boards/mach-highlander/irq-r7780mp.c b/arch/sh/boards/mach-highlander/irq-r7780mp.c
index 83c28bcd4d2a..9893fd3a1358 100644
--- a/arch/sh/boards/mach-highlander/irq-r7780mp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780mp.c
@@ -64,7 +64,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
 
 unsigned char * __init highlander_plat_irq_setup(void)
 {
-        if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) {
+        if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) {
                 printk(KERN_INFO "Using r7780mp interrupt controller.\n");
                 register_intc_controller(&intc_desc);
                 return irl2irq;
diff --git a/arch/sh/boards/mach-highlander/irq-r7780rp.c b/arch/sh/boards/mach-highlander/irq-r7780rp.c
index b721e86b5af4..0805b2151452 100644
--- a/arch/sh/boards/mach-highlander/irq-r7780rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780rp.c
@@ -57,7 +57,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors,
 
 unsigned char * __init highlander_plat_irq_setup(void)
 {
-        if (ctrl_inw(0xa5000600)) {
+        if (__raw_readw(0xa5000600)) {
                 printk(KERN_INFO "Using r7780rp interrupt controller.\n");
                 register_intc_controller(&intc_desc);
                 return irl2irq;
diff --git a/arch/sh/boards/mach-highlander/irq-r7785rp.c b/arch/sh/boards/mach-highlander/irq-r7785rp.c
index 3811b060a39b..558b24862776 100644
--- a/arch/sh/boards/mach-highlander/irq-r7785rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7785rp.c
@@ -66,20 +66,20 @@ static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
 
 unsigned char * __init highlander_plat_irq_setup(void)
 {
-        if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000)
+        if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
                 return NULL;
 
         printk(KERN_INFO "Using r7785rp interrupt controller.\n");
 
-        ctrl_outw(0x0000, PA_IRLSSR1);  /* FPGA IRLSSR1(CF_CD clear) */
+        __raw_writew(0x0000, PA_IRLSSR1);       /* FPGA IRLSSR1(CF_CD clear) */
 
         /* Setup the FPGA IRL */
-        ctrl_outw(0x0000, PA_IRLPRA);   /* FPGA IRLA */
-        ctrl_outw(0xe598, PA_IRLPRB);   /* FPGA IRLB */
-        ctrl_outw(0x7060, PA_IRLPRC);   /* FPGA IRLC */
-        ctrl_outw(0x0000, PA_IRLPRD);   /* FPGA IRLD */
-        ctrl_outw(0x4321, PA_IRLPRE);   /* FPGA IRLE */
-        ctrl_outw(0xdcba, PA_IRLPRF);   /* FPGA IRLF */
+        __raw_writew(0x0000, PA_IRLPRA);        /* FPGA IRLA */
+        __raw_writew(0xe598, PA_IRLPRB);        /* FPGA IRLB */
+        __raw_writew(0x7060, PA_IRLPRC);        /* FPGA IRLC */
+        __raw_writew(0x0000, PA_IRLPRD);        /* FPGA IRLD */
+        __raw_writew(0x4321, PA_IRLPRE);        /* FPGA IRLE */
+        __raw_writew(0xdcba, PA_IRLPRF);        /* FPGA IRLF */
 
         register_intc_controller(&intc_desc);
         return irl2irq;
diff --git a/arch/sh/boards/mach-highlander/psw.c b/arch/sh/boards/mach-highlander/psw.c
index 37b1a2ee71a5..522786318d36 100644
--- a/arch/sh/boards/mach-highlander/psw.c
+++ b/arch/sh/boards/mach-highlander/psw.c
@@ -24,7 +24,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
         unsigned int l, mask;
         int ret = 0;
 
-        l = ctrl_inw(PA_DBSW);
+        l = __raw_readw(PA_DBSW);
 
         /* Nothing to do if there's no state change */
         if (psw->state) {
@@ -45,7 +45,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
 out:
         /* Clear the switch IRQs */
         l |= (0x7 << 12);
-        ctrl_outw(l, PA_DBSW);
+        __raw_writew(l, PA_DBSW);
 
         return IRQ_RETVAL(ret);
 }
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index f663c14d8885..affd66747ba3 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -311,13 +311,13 @@ device_initcall(r7780rp_devices_setup);
  */
 static int ivdr_clk_enable(struct clk *clk)
 {
-        ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
+        __raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
         return 0;
 }
 
 static void ivdr_clk_disable(struct clk *clk)
 {
-        ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
+        __raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
 }
 
 static struct clk_ops ivdr_clk_ops = {
@@ -337,7 +337,7 @@ static struct clk *r7780rp_clocks[] = {
 static void r7780rp_power_off(void)
 {
         if (mach_is_r7780mp() || mach_is_r7785rp())
-                ctrl_outw(0x0001, PA_POFF);
+                __raw_writew(0x0001, PA_POFF);
 }
 
 /*
@@ -345,7 +345,7 @@ static void r7780rp_power_off(void)
  */
 static void __init highlander_setup(char **cmdline_p)
 {
-        u16 ver = ctrl_inw(PA_VERREG);
+        u16 ver = __raw_readw(PA_VERREG);
         int i;
 
         printk(KERN_INFO "Renesas Solutions Highlander %s support.\n",
@@ -370,12 +370,12 @@ static void __init highlander_setup(char **cmdline_p)
                 clk_enable(clk);
         }
 
-        ctrl_outw(0x0000, PA_OBLED);    /* Clear LED. */
+        __raw_writew(0x0000, PA_OBLED); /* Clear LED. */
 
         if (mach_is_r7780rp())
-                ctrl_outw(0x0001, PA_SDPOW);    /* SD Power ON */
+                __raw_writew(0x0001, PA_SDPOW); /* SD Power ON */
 
-        ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL);     /* Si13112 */
+        __raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL);       /* Si13112 */
 
         pm_power_off = r7780rp_power_off;
 }
diff --git a/arch/sh/boards/mach-hp6xx/hp6xx_apm.c b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
index e85212faf40a..b49535c0ddd9 100644
--- a/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
+++ b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
@@ -53,7 +53,7 @@ static void hp6x0_apm_get_power_status(struct apm_power_info *info)
         info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ?
                          APM_AC_ONLINE : APM_AC_OFFLINE;
 
-        pgdr = ctrl_inb(PGDR);
+        pgdr = __raw_readb(PGDR);
         if (pgdr & PGDR_MAIN_BATTERY_OUT) {
                 info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
                 info->battery_flag      = 0x80;
diff --git a/arch/sh/boards/mach-hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c
index d936c1af7620..4499a3749d40 100644
--- a/arch/sh/boards/mach-hp6xx/pm.c
+++ b/arch/sh/boards/mach-hp6xx/pm.c
@@ -53,17 +53,17 @@ static void pm_enter(void)
         sh_wdt_write_cnt(0);
 
         /* disable PLL1 */
-        frqcr = ctrl_inw(FRQCR);
+        frqcr = __raw_readw(FRQCR);
         frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
-        ctrl_outw(frqcr, FRQCR);
+        __raw_writew(frqcr, FRQCR);
 
         /* enable standby */
-        stbcr = ctrl_inb(STBCR);
-        ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
+        stbcr = __raw_readb(STBCR);
+        __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
 
         /* set self-refresh */
-        mcr = ctrl_inw(MCR);
-        ctrl_outw(mcr & ~MCR_RFSH, MCR);
+        mcr = __raw_readw(MCR);
+        __raw_writew(mcr & ~MCR_RFSH, MCR);
 
         /* set interrupt handler */
         asm volatile("stc vbr, %0" : "=r" (vbr_old));
@@ -73,8 +73,8 @@ static void pm_enter(void)
                &wakeup_start, &wakeup_end - &wakeup_start);
         asm volatile("ldc %0, vbr" : : "r" (vbr_new));
 
-        ctrl_outw(0, RTCNT);
-        ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR);
+        __raw_writew(0, RTCNT);
+        __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
 
         cpu_sleep();
 
@@ -83,14 +83,14 @@ static void pm_enter(void)
         free_page(vbr_new);
 
         /* enable PLL1 */
-        frqcr = ctrl_inw(FRQCR);
+        frqcr = __raw_readw(FRQCR);
         frqcr |= FRQCR_PSTBY;
-        ctrl_outw(frqcr, FRQCR);
+        __raw_writew(frqcr, FRQCR);
         udelay(50);
         frqcr |= FRQCR_PLLEN;
-        ctrl_outw(frqcr, FRQCR);
+        __raw_writew(frqcr, FRQCR);
 
-        ctrl_outb(stbcr, STBCR);
+        __raw_writeb(stbcr, STBCR);
 
         clear_bl_bit();
 }
@@ -115,21 +115,21 @@ static int hp6x0_pm_enter(suspend_state_t state)
         outw(hd64461_stbcr, HD64461_STBCR);
 #endif
 
-        ctrl_outb(0x1f, DACR);
+        __raw_writeb(0x1f, DACR);
 
-        stbcr = ctrl_inb(STBCR);
-        ctrl_outb(0x01, STBCR);
+        stbcr = __raw_readb(STBCR);
+        __raw_writeb(0x01, STBCR);
 
-        stbcr2 = ctrl_inb(STBCR2);
-        ctrl_outb(0x7f , STBCR2);
+        stbcr2 = __raw_readb(STBCR2);
+        __raw_writeb(0x7f , STBCR2);
 
         outw(0xf07f, HD64461_SCPUCR);
 
         pm_enter();
 
         outw(0, HD64461_SCPUCR);
-        ctrl_outb(stbcr, STBCR);
-        ctrl_outb(stbcr2, STBCR2);
+        __raw_writeb(stbcr, STBCR);
+        __raw_writeb(stbcr2, STBCR2);
 
 #ifdef CONFIG_HD64461_ENABLER
         hd64461_stbcr = inw(HD64461_STBCR);
diff --git a/arch/sh/boards/mach-hp6xx/setup.c b/arch/sh/boards/mach-hp6xx/setup.c
index e6dd5e96321e..8c9add5f4cfa 100644
--- a/arch/sh/boards/mach-hp6xx/setup.c
+++ b/arch/sh/boards/mach-hp6xx/setup.c
@@ -149,19 +149,19 @@ static void __init hp6xx_setup(char **cmdline_p)
 
         sh_dac_output(0, DAC_SPEAKER_VOLUME);
         sh_dac_disable(DAC_SPEAKER_VOLUME);
-        v8 = ctrl_inb(DACR);
+        v8 = __raw_readb(DACR);
         v8 &= ~DACR_DAE;
-        ctrl_outb(v8,DACR);
+        __raw_writeb(v8,DACR);
 
-        v8 = ctrl_inb(SCPDR);
+        v8 = __raw_readb(SCPDR);
         v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
         v8 &= ~SCPDR_TS_SCAN_ENABLE;
-        ctrl_outb(v8, SCPDR);
+        __raw_writeb(v8, SCPDR);
 
-        v = ctrl_inw(SCPCR);
+        v = __raw_readw(SCPCR);
         v &= ~SCPCR_TS_MASK;
         v |= SCPCR_TS_ENABLE;
-        ctrl_outw(v, SCPCR);
+        __raw_writew(v, SCPCR);
 }
 device_initcall(hp6xx_devices_setup);
 
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 5d7b5d92475e..b2cd0ed8664e 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -282,7 +282,7 @@ static int camera_power(struct device *dev, int mode)
                  * use 1.8 V for VccQ_VIO
                  * use 2.85V for VccQ_SR
                  */
-                ctrl_outw((ctrl_inw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
+                __raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
 
                 /* reset clear */
                 ret = gpio_request(GPIO_PTB4, NULL);
@@ -351,7 +351,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 101,
+                .start  = 100,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -492,13 +492,13 @@ static int kfr2r09_usb0_gadget_setup(void)
         if (kfr2r09_usb0_gadget_i2c_setup() != 0)
                 return -ENODEV; /* unable to configure using i2c */
 
-        ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
+        __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
         gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
         gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
         gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
         msleep(20); /* wait 20ms to let the clock settle */
         clk_enable(clk_get(NULL, "usb0"));
-        ctrl_outw(0x0600, 0xa40501d4);
+        __raw_writew(0x0600, 0xa40501d4);
 
         return 0;
 }
@@ -526,12 +526,12 @@ static int __init kfr2r09_devices_setup(void)
         gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */
 
         /* setup NOR flash at CS0 */
-        ctrl_outl(0x36db0400, BSC_CS0BCR);
-        ctrl_outl(0x00000500, BSC_CS0WCR);
+        __raw_writel(0x36db0400, BSC_CS0BCR);
+        __raw_writel(0x00000500, BSC_CS0WCR);
 
         /* setup NAND flash at CS4 */
-        ctrl_outl(0x36db0400, BSC_CS4BCR);
-        ctrl_outl(0x00000500, BSC_CS4WCR);
+        __raw_writel(0x36db0400, BSC_CS4BCR);
+        __raw_writel(0x00000500, BSC_CS4WCR);
 
         /* setup KEYSC pins */
         gpio_request(GPIO_FN_KEYOUT0, NULL);
diff --git a/arch/sh/boards/mach-landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c
index 528013188196..01e6abb769b9 100644
--- a/arch/sh/boards/mach-landisk/gio.c
+++ b/arch/sh/boards/mach-landisk/gio.c
@@ -76,39 +76,39 @@ static long gio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
                 break;
 
         case GIODRV_IOCSGIODATA1:       /* write byte */
-                ctrl_outb((unsigned char)(0x0ff & data), addr);
+                __raw_writeb((unsigned char)(0x0ff & data), addr);
                 break;
 
         case GIODRV_IOCSGIODATA2:       /* write word */
                 if (addr & 0x01) {
                         return -EFAULT;
                 }
-                ctrl_outw((unsigned short int)(0x0ffff & data), addr);
+                __raw_writew((unsigned short int)(0x0ffff & data), addr);
                 break;
 
         case GIODRV_IOCSGIODATA4:       /* write long */
                 if (addr & 0x03) {
                         return -EFAULT;
                 }
-                ctrl_outl(data, addr);
+                __raw_writel(data, addr);
                 break;
 
         case GIODRV_IOCGGIODATA1:       /* read byte */
-                data = ctrl_inb(addr);
+                data = __raw_readb(addr);
                 break;
 
         case GIODRV_IOCGGIODATA2:       /* read word */
                 if (addr & 0x01) {
                         return -EFAULT;
                 }
-                data = ctrl_inw(addr);
+                data = __raw_readw(addr);
                 break;
 
         case GIODRV_IOCGGIODATA4:       /* read long */
                 if (addr & 0x03) {
                         return -EFAULT;
                 }
-                data = ctrl_inl(addr);
+                data = __raw_readl(addr);
                 break;
         default:
                 return -EFAULT;
diff --git a/arch/sh/boards/mach-landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c
index 7b284cde1f58..96f38a4187d0 100644
--- a/arch/sh/boards/mach-landisk/irq.c
+++ b/arch/sh/boards/mach-landisk/irq.c
@@ -22,14 +22,14 @@ static void disable_landisk_irq(unsigned int irq)
 {
         unsigned char mask = 0xff ^ (0x01 << (irq - 5));
 
-        ctrl_outb(ctrl_inb(PA_IMASK) & mask, PA_IMASK);
+        __raw_writeb(__raw_readb(PA_IMASK) & mask, PA_IMASK);
 }
 
 static void enable_landisk_irq(unsigned int irq)
 {
         unsigned char value = (0x01 << (irq - 5));
 
-        ctrl_outb(ctrl_inb(PA_IMASK) | value, PA_IMASK);
+        __raw_writeb(__raw_readb(PA_IMASK) | value, PA_IMASK);
 }
 
 static struct irq_chip landisk_irq_chip __read_mostly = {
@@ -52,5 +52,5 @@ void __init init_landisk_IRQ(void)
                                               handle_level_irq, "level");
                 enable_landisk_irq(i);
         }
-        ctrl_outb(0x00, PA_PWRINT_CLR);
+        __raw_writeb(0x00, PA_PWRINT_CLR);
 }
diff --git a/arch/sh/boards/mach-landisk/psw.c b/arch/sh/boards/mach-landisk/psw.c
index e6b0efa098d1..bef83522f958 100644
--- a/arch/sh/boards/mach-landisk/psw.c
+++ b/arch/sh/boards/mach-landisk/psw.c
@@ -25,7 +25,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
         unsigned int sw_value;
         int ret = 0;
 
-        sw_value = (0x0ff & (~ctrl_inb(PA_STATUS)));
+        sw_value = (0x0ff & (~__raw_readb(PA_STATUS)));
 
         /* Nothing to do if there's no state change */
         if (psw->state) {
@@ -42,7 +42,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
 
 out:
         /* Clear the switch IRQs */
-        ctrl_outb(0x00, PA_PWRINT_CLR);
+        __raw_writeb(0x00, PA_PWRINT_CLR);
 
         return IRQ_RETVAL(ret);
 }
diff --git a/arch/sh/boards/mach-landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c
index db22ea2e6d49..50337acc18c5 100644
--- a/arch/sh/boards/mach-landisk/setup.c
+++ b/arch/sh/boards/mach-landisk/setup.c
@@ -25,7 +25,7 @@ void init_landisk_IRQ(void);
 
 static void landisk_power_off(void)
 {
-        ctrl_outb(0x01, PA_SHUTDOWN);
+        __raw_writeb(0x01, PA_SHUTDOWN);
 }
 
 static struct resource cf_ide_resources[3];
@@ -63,7 +63,7 @@ static int __init landisk_devices_setup(void)
         /* open I/O area window */
         paddrbase = virt_to_phys((void *)PA_AREA5_IO);
         prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
-        cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot);
+        cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot));
         if (!cf_ide_base) {
                 printk("allocate_cf_area : can't open CF I/O window!\n");
                 return -ENOMEM;
@@ -88,7 +88,7 @@ __initcall(landisk_devices_setup);
 static void __init landisk_setup(char **cmdline_p)
 {
         /* LED ON */
-        ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED);
+        __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED);
 
         printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
         pm_power_off = landisk_power_off;
diff --git a/arch/sh/boards/mach-lboxre2/setup.c b/arch/sh/boards/mach-lboxre2/setup.c
index 2b0b5818e1e4..79b4e0d77b71 100644
--- a/arch/sh/boards/mach-lboxre2/setup.c
+++ b/arch/sh/boards/mach-lboxre2/setup.c
@@ -56,8 +56,8 @@ static int __init lboxre2_devices_setup(void)
         /* open I/O area window */
         paddrbase = virt_to_phys((void*)PA_AREA5_IO);
         psize = PAGE_SIZE;
-        prot = PAGE_KERNEL_PCC( 1 , _PAGE_PCC_IO16);
-        cf0_io_base = (u32)p3_ioremap(paddrbase, psize, prot.pgprot);
+        prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
+        cf0_io_base = (u32)ioremap_prot(paddrbase, psize, pgprot_val(prot));
         if (!cf0_io_base) {
                 printk(KERN_ERR "%s : can't open CF I/O window!\n" , __func__ );
                 return -ENOMEM;
diff --git a/arch/sh/boards/mach-microdev/io.c b/arch/sh/boards/mach-microdev/io.c
index 52dd748211c7..2960c659020e 100644
--- a/arch/sh/boards/mach-microdev/io.c
+++ b/arch/sh/boards/mach-microdev/io.c
@@ -141,10 +141,10 @@ static inline void delay(void)
 #if defined(CONFIG_PCI)
         /* System board present, just make a dummy SRAM access.  (CS0 will be
            mapped to PCI memory, probably good to avoid it.) */
-        ctrl_inw(0xa6800000);
+        __raw_readw(0xa6800000);
 #else
         /* CS0 will be mapped to flash, ROM etc so safe to access it. */
-        ctrl_inw(0xa0000000);
+        __raw_readw(0xa0000000);
 #endif
 }
 
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index b551963579c1..a26d16669aa2 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -88,7 +88,7 @@ static void disable_microdev_irq(unsigned int irq)
         fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
 
         /* disable interrupts on the FPGA INTC register */
-        ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
+        __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
 }
 
 static void enable_microdev_irq(unsigned int irq)
@@ -107,13 +107,13 @@ static void enable_microdev_irq(unsigned int irq)
         priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
 
         /* set priority for the interrupt */
-        priorities = ctrl_inl(priorityReg);
+        priorities = __raw_readl(priorityReg);
         priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
         priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
-        ctrl_outl(priorities, priorityReg);
+        __raw_writel(priorities, priorityReg);
 
         /* enable interrupts on the FPGA INTC register */
-        ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
+        __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
 }
 
 /* This function sets the desired irq handler to be a MicroDev type */
@@ -134,7 +134,7 @@ extern void __init init_microdev_irq(void)
         int i;
 
         /* disable interrupts on the FPGA INTC register */
-        ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG);
+        __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);
 
         for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
                 make_microdev_irq(i);
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 507c77be476d..be300aaca6fe 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -397,7 +397,7 @@ static struct resource sdhi_cn9_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 101,
+                .start  = 100,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -431,7 +431,7 @@ static struct i2c_board_info migor_i2c_camera[] = {
 };
 
 static struct ov772x_camera_info ov7725_info = {
-        .buswidth       = SOCAM_DATAWIDTH_8,
+        .flags          = OV772X_FLAG_8BIT,
 };
 
 static struct soc_camera_link ov7725_link = {
@@ -496,28 +496,16 @@ static int __init migor_devices_setup(void)
                                         &migor_sdram_enter_end,
                                         &migor_sdram_leave_start,
                                         &migor_sdram_leave_end);
-#ifdef CONFIG_PM
         /* Let D11 LED show STATUS0 */
         gpio_request(GPIO_FN_STATUS0, NULL);
 
         /* Lit D12 LED show PDSTATUS */
         gpio_request(GPIO_FN_PDSTATUS, NULL);
-#else
-        /* Lit D11 LED */
-        gpio_request(GPIO_PTJ7, NULL);
-        gpio_direction_output(GPIO_PTJ7, 1);
-        gpio_export(GPIO_PTJ7, 0);
-
-        /* Lit D12 LED */
-        gpio_request(GPIO_PTJ5, NULL);
-        gpio_direction_output(GPIO_PTJ5, 1);
-        gpio_export(GPIO_PTJ5, 0);
-#endif
 
         /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
         gpio_request(GPIO_FN_IRQ0, NULL);
-        ctrl_outl(0x00003400, BSC_CS4BCR);
-        ctrl_outl(0x00110080, BSC_CS4WCR);
+        __raw_writel(0x00003400, BSC_CS4BCR);
+        __raw_writel(0x00110080, BSC_CS4WCR);
 
         /* KEYSC */
         gpio_request(GPIO_FN_KEYOUT0, NULL);
@@ -533,7 +521,7 @@ static int __init migor_devices_setup(void)
 
         /* NAND Flash */
         gpio_request(GPIO_FN_CS6A_CE2B, NULL);
-        ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
+        __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
         gpio_request(GPIO_PTA1, NULL);
         gpio_direction_input(GPIO_PTA1);
 
@@ -627,7 +615,7 @@ static int __init migor_devices_setup(void)
 #else
         gpio_direction_output(GPIO_PTT0, 1);
 #endif
-        ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
+        __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
 
         platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
 
diff --git a/arch/sh/boards/mach-r2d/irq.c b/arch/sh/boards/mach-r2d/irq.c
index 78d7b27c80da..574f009c3c31 100644
--- a/arch/sh/boards/mach-r2d/irq.c
+++ b/arch/sh/boards/mach-r2d/irq.c
@@ -129,7 +129,7 @@ void __init init_rts7751r2d_IRQ(void)
 {
         struct intc_desc *d;
 
-        switch (ctrl_inw(PA_VERREG) & 0xf0) {
+        switch (__raw_readw(PA_VERREG) & 0xf0) {
 #ifdef CONFIG_RTS7751R2D_PLUS
         case 0x10:
                 printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n");
@@ -147,7 +147,7 @@ void __init init_rts7751r2d_IRQ(void)
 #endif
         default:
                 printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n",
-                       ctrl_inw(PA_VERREG));
+                       __raw_readw(PA_VERREG));
                 return;
         }
 
diff --git a/arch/sh/boards/mach-r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index a625ecb93e47..b84df6a3a93c 100644
--- a/arch/sh/boards/mach-r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
@@ -70,7 +70,7 @@ static struct spi_board_info spi_bus[] = {
 static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state)
 {
         BUG_ON(cs != 0);  /* Single Epson RTC-9701JE attached on CS0 */
-        ctrl_outw(state == BITBANG_CS_ACTIVE, PA_RTCCE);
+        __raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE);
 }
 
 static struct sh_spi_info spi_info = {
@@ -262,7 +262,7 @@ __initcall(rts7751r2d_devices_setup);
 
 static void rts7751r2d_power_off(void)
 {
-        ctrl_outw(0x0001, PA_POWOFF);
+        __raw_writew(0x0001, PA_POWOFF);
 }
 
 /*
@@ -271,14 +271,14 @@ static void rts7751r2d_power_off(void)
 static void __init rts7751r2d_setup(char **cmdline_p)
 {
         void __iomem *sm501_reg;
-        u16 ver = ctrl_inw(PA_VERREG);
+        u16 ver = __raw_readw(PA_VERREG);
 
         printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n");
 
         printk(KERN_INFO "FPGA version:%d (revision:%d)\n",
                                         (ver >> 4) & 0xf, ver & 0xf);
 
-        ctrl_outw(0x0000, PA_OUTPORT);
+        __raw_writew(0x0000, PA_OUTPORT);
         pm_power_off = rts7751r2d_power_off;
 
         /* sm501 dram configuration:
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c
index c37617e63220..4fa08ba10253 100644
--- a/arch/sh/boards/mach-rsk/devices-rsk7203.c
+++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c
@@ -96,7 +96,7 @@ static int __init rsk7203_devices_setup(void)
         gpio_request(GPIO_FN_RXD0, NULL);
 
         /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */
-        ctrl_outl(0x36db0400, 0xfffc0008); /* CS1BCR */
+        __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
         gpio_request(GPIO_FN_IRQ0_PB, NULL);
 
         return platform_add_devices(rsk7203_devices,
diff --git a/arch/sh/boards/mach-sdk7780/irq.c b/arch/sh/boards/mach-sdk7780/irq.c
index 855558163c58..e5f7564f2511 100644
--- a/arch/sh/boards/mach-sdk7780/irq.c
+++ b/arch/sh/boards/mach-sdk7780/irq.c
@@ -37,9 +37,9 @@ void __init init_sdk7780_IRQ(void)
 {
         printk(KERN_INFO "Using SDK7780 interrupt controller.\n");
 
-        ctrl_outw(0xFFFF, FPGA_IRQ0MR);
+        __raw_writew(0xFFFF, FPGA_IRQ0MR);
         /* Setup IRL 0-3 */
-        ctrl_outw(0x0003, FPGA_IMSR);
+        __raw_writew(0x0003, FPGA_IMSR);
         plat_irq_setup_pins(IRQ_MODE_IRL3210);
 
         register_intc_controller(&fpga_intc_desc);
diff --git a/arch/sh/boards/mach-sdk7780/setup.c b/arch/sh/boards/mach-sdk7780/setup.c
index aad94a78dc70..4da38db4b5fe 100644
--- a/arch/sh/boards/mach-sdk7780/setup.c
+++ b/arch/sh/boards/mach-sdk7780/setup.c
@@ -20,27 +20,18 @@
 
 #define GPIO_PECR        0xFFEA0008
 
-//* Heartbeat */
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 16,
-};
-
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+/* Heartbeat */
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev = {
-                .platform_data = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 /* SMC91x */
@@ -83,8 +74,8 @@ device_initcall(sdk7780_devices_setup);
 
 static void __init sdk7780_setup(char **cmdline_p)
 {
-        u16 ver = ctrl_inw(FPGA_FPVERR);
-        u16 dateStamp = ctrl_inw(FPGA_FPDATER);
+        u16 ver = __raw_readw(FPGA_FPVERR);
+        u16 dateStamp = __raw_readw(FPGA_FPDATER);
 
         printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n");
         printk(KERN_INFO "Board version: %d (revision %d), "
@@ -94,7 +85,7 @@ static void __init sdk7780_setup(char **cmdline_p)
                          dateStamp);
 
         /* Setup pin mux'ing for PCIC */
-        ctrl_outw(0x0000, GPIO_PECR);
+        __raw_writew(0x0000, GPIO_PECR);
 }
 
 /*
diff --git a/arch/sh/boards/mach-sdk7786/Makefile b/arch/sh/boards/mach-sdk7786/Makefile
new file mode 100644
index 000000000000..a29f19e85b63
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/Makefile
@@ -0,0 +1 @@
+obj-y   := setup.o fpga.o irq.o
diff --git a/arch/sh/boards/mach-sdk7786/fpga.c b/arch/sh/boards/mach-sdk7786/fpga.c
new file mode 100644
index 000000000000..3e4ec66a0417
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/fpga.c
@@ -0,0 +1,72 @@
+/*
+ * SDK7786 FPGA Support.
+ *
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/bcd.h>
+#include <mach/fpga.h>
+#include <asm/sizes.h>
+
+#define FPGA_REGS_OFFSET        0x03fff800
+#define FPGA_REGS_SIZE          0x490
+
+/*
+ * The FPGA can be mapped in any of the generally available areas,
+ * so we attempt to scan for it using the fixed SRSTR read magic.
+ *
+ * Once the FPGA is located, the rest of the mapping data for the other
+ * components can be determined dynamically from its section mapping
+ * registers.
+ */
+static void __iomem *sdk7786_fpga_probe(void)
+{
+        unsigned long area;
+        void __iomem *base;
+
+        /*
+         * Iterate over all of the areas where the FPGA could be mapped.
+         * The possible range is anywhere from area 0 through 6, area 7
+         * is reserved.
+         */
+        for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) {
+                base = ioremap_nocache(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE);
+                if (!base) {
+                        /* Failed to remap this area, move along. */
+                        continue;
+                }
+
+                if (ioread16(base + SRSTR) == SRSTR_MAGIC)
+                        return base;    /* Found it! */
+
+                iounmap(base);
+        }
+
+        return NULL;
+}
+
+void __iomem *sdk7786_fpga_base;
+
+void __init sdk7786_fpga_init(void)
+{
+        u16 version, date;
+
+        sdk7786_fpga_base = sdk7786_fpga_probe();
+        if (unlikely(!sdk7786_fpga_base)) {
+                panic("FPGA detection failed.\n");
+                return;
+        }
+
+        version = fpga_read_reg(FPGAVR);
+        date = fpga_read_reg(FPGADR);
+
+        pr_info("\tFPGA version:\t%d.%d (built on %d/%d/%d)\n",
+                bcd2bin(version >> 8) & 0xf, bcd2bin(version & 0xf),
+                ((date >> 12) & 0xf) + 2000,
+                (date >> 8) & 0xf, bcd2bin(date & 0xff));
+}
diff --git a/arch/sh/boards/mach-sdk7786/irq.c b/arch/sh/boards/mach-sdk7786/irq.c
new file mode 100644
index 000000000000..46943a0da5b7
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/irq.c
@@ -0,0 +1,48 @@
+/*
+ * SDK7786 FPGA IRQ Controller Support.
+ *
+ * Copyright (C) 2010  Matt Fleming
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/irq.h>
+#include <mach/fpga.h>
+#include <mach/irq.h>
+
+enum {
+        ATA_IRQ_BIT             = 1,
+        SPI_BUSY_BIT            = 2,
+        LIRQ5_BIT               = 3,
+        LIRQ6_BIT               = 4,
+        LIRQ7_BIT               = 5,
+        LIRQ8_BIT               = 6,
+        KEY_IRQ_BIT             = 7,
+        PEN_IRQ_BIT             = 8,
+        ETH_IRQ_BIT             = 9,
+        RTC_ALARM_BIT           = 10,
+        CRYSTAL_FAIL_BIT        = 12,
+        ETH_PME_BIT             = 14,
+};
+
+void __init sdk7786_init_irq(void)
+{
+        unsigned int tmp;
+
+        /* Enable priority encoding for all IRLs */
+        fpga_write_reg(fpga_read_reg(INTMSR) | 0x0303, INTMSR);
+
+        /* Clear FPGA interrupt status registers */
+        fpga_write_reg(0x0000, INTASR);
+        fpga_write_reg(0x0000, INTBSR);
+
+        /* Unmask FPGA interrupts */
+        tmp = fpga_read_reg(INTAMR);
+        tmp &= ~(1 << ETH_IRQ_BIT);
+        fpga_write_reg(tmp, INTAMR);
+
+        plat_irq_setup_pins(IRQ_MODE_IRL7654_MASK);
+        plat_irq_setup_pins(IRQ_MODE_IRL3210_MASK);
+}
diff --git a/arch/sh/boards/mach-sdk7786/setup.c b/arch/sh/boards/mach-sdk7786/setup.c
new file mode 100644
index 000000000000..f094ea2ee783
--- /dev/null
+++ b/arch/sh/boards/mach-sdk7786/setup.c
@@ -0,0 +1,189 @@
+/*
+ * Renesas Technology Europe SDK7786 Support.
+ *
+ * Copyright (C) 2010  Matt Fleming
+ * Copyright (C) 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/smsc911x.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <mach/fpga.h>
+#include <mach/irq.h>
+#include <asm/machvec.h>
+#include <asm/heartbeat.h>
+#include <asm/sizes.h>
+#include <asm/reboot.h>
+
+static struct resource heartbeat_resource = {
+        .start          = 0x07fff8b0,
+        .end            = 0x07fff8b0 + sizeof(u16) - 1,
+        .flags          = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
+};
+
+static struct platform_device heartbeat_device = {
+        .name           = "heartbeat",
+        .id             = -1,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
+};
+
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .name           = "smsc911x-memory",
+                .start          = 0x07ffff00,
+                .end            = 0x07ffff00 + SZ_256 - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .name           = "smsc911x-irq",
+                .start          = evt2irq(0x2c0),
+                .end            = evt2irq(0x2c0),
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_32BIT,
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+};
+
+static struct platform_device smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
+};
+
+static struct resource smbus_fpga_resource = {
+        .start          = 0x07fff9e0,
+        .end            = 0x07fff9e0 + SZ_32 - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device smbus_fpga_device = {
+        .name           = "i2c-sdk7786",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = &smbus_fpga_resource,
+};
+
+static struct resource smbus_pcie_resource = {
+        .start          = 0x07fffc30,
+        .end            = 0x07fffc30 + SZ_32 - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device smbus_pcie_device = {
+        .name           = "i2c-sdk7786",
+        .id             = 1,
+        .num_resources  = 1,
+        .resource       = &smbus_pcie_resource,
+};
+
+static struct i2c_board_info __initdata sdk7786_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("max6900", 0x68),
+        },
+};
+
+static struct platform_device *sh7786_devices[] __initdata = {
+        &heartbeat_device,
+        &smsc911x_device,
+        &smbus_fpga_device,
+        &smbus_pcie_device,
+};
+
+static int sdk7786_i2c_setup(void)
+{
+        unsigned int tmp;
+
+        /*
+         * Hand over I2C control to the FPGA.
+         */
+        tmp = fpga_read_reg(SBCR);
+        tmp &= ~SCBR_I2CCEN;
+        tmp |= SCBR_I2CMEN;
+        fpga_write_reg(tmp, SBCR);
+
+        return i2c_register_board_info(0, sdk7786_i2c_devices,
+                                       ARRAY_SIZE(sdk7786_i2c_devices));
+}
+
+static int __init sdk7786_devices_setup(void)
+{
+        int ret;
+
+        ret = platform_add_devices(sh7786_devices, ARRAY_SIZE(sh7786_devices));
+        if (unlikely(ret != 0))
+                return ret;
+
+        return sdk7786_i2c_setup();
+}
+__initcall(sdk7786_devices_setup);
+
+static int sdk7786_mode_pins(void)
+{
+        return fpga_read_reg(MODSWR);
+}
+
+static int sdk7786_clk_init(void)
+{
+        struct clk *clk;
+        int ret;
+
+        /*
+         * Only handle the EXTAL case, anyone interfacing a crystal
+         * resonator will need to provide their own input clock.
+         */
+        if (test_mode_pin(MODE_PIN9))
+                return -EINVAL;
+
+        clk = clk_get(NULL, "extal");
+        if (!clk || IS_ERR(clk))
+                return PTR_ERR(clk);
+        ret = clk_set_rate(clk, 33333333);
+        clk_put(clk);
+
+        return ret;
+}
+
+static void sdk7786_restart(char *cmd)
+{
+        fpga_write_reg(0xa5a5, SRSTR);
+}
+
+/* Initialize the board */
+static void __init sdk7786_setup(char **cmdline_p)
+{
+        pr_info("Renesas Technology Europe SDK7786 support:\n");
+
+        sdk7786_fpga_init();
+
+        pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
+
+        machine_ops.restart = sdk7786_restart;
+}
+
+/*
+ * The Machine Vector
+ */
+static struct sh_machine_vector mv_sdk7786 __initmv = {
+        .mv_name                = "SDK7786",
+        .mv_setup               = sdk7786_setup,
+        .mv_mode_pins           = sdk7786_mode_pins,
+        .mv_clk_init            = sdk7786_clk_init,
+        .mv_init_irq            = sdk7786_init_irq,
+};
diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c
index 180455642a43..adadc77532ee 100644
--- a/arch/sh/boards/mach-se/7206/io.c
+++ b/arch/sh/boards/mach-se/7206/io.c
@@ -16,7 +16,7 @@
 
 static inline void delay(void)
 {
-        ctrl_inw(0x20000000);  /* P2 ROM Area */
+        __raw_readw(0x20000000);  /* P2 ROM Area */
 }
 
 /* MS7750 requires special versions of in*, out* routines, since
diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c
index aef7f052851a..8d82175d83ab 100644
--- a/arch/sh/boards/mach-se/7206/irq.c
+++ b/arch/sh/boards/mach-se/7206/irq.c
@@ -32,12 +32,12 @@ static void disable_se7206_irq(unsigned int irq)
         unsigned short msk0,msk1;
 
         /* Set the priority in IPR to 0 */
-        val = ctrl_inw(INTC_IPR01);
+        val = __raw_readw(INTC_IPR01);
         val &= mask;
-        ctrl_outw(val, INTC_IPR01);
+        __raw_writew(val, INTC_IPR01);
         /* FPGA mask set */
-        msk0 = ctrl_inw(INTMSK0);
-        msk1 = ctrl_inw(INTMSK1);
+        msk0 = __raw_readw(INTMSK0);
+        msk1 = __raw_readw(INTMSK1);
 
         switch (irq) {
         case IRQ0_IRQ:
@@ -51,8 +51,8 @@ static void disable_se7206_irq(unsigned int irq)
                 msk1 |= 0x00ff;
                 break;
         }
-        ctrl_outw(msk0, INTMSK0);
-        ctrl_outw(msk1, INTMSK1);
+        __raw_writew(msk0, INTMSK0);
+        __raw_writew(msk1, INTMSK1);
 }
 
 static void enable_se7206_irq(unsigned int irq)
@@ -62,13 +62,13 @@ static void enable_se7206_irq(unsigned int irq)
         unsigned short msk0,msk1;
 
         /* Set priority in IPR back to original value */
-        val = ctrl_inw(INTC_IPR01);
+        val = __raw_readw(INTC_IPR01);
         val |= value;
-        ctrl_outw(val, INTC_IPR01);
+        __raw_writew(val, INTC_IPR01);
 
         /* FPGA mask reset */
-        msk0 = ctrl_inw(INTMSK0);
-        msk1 = ctrl_inw(INTMSK1);
+        msk0 = __raw_readw(INTMSK0);
+        msk1 = __raw_readw(INTMSK1);
 
         switch (irq) {
         case IRQ0_IRQ:
@@ -82,19 +82,20 @@ static void enable_se7206_irq(unsigned int irq)
                 msk1 &= ~0x00ff;
                 break;
         }
-        ctrl_outw(msk0, INTMSK0);
-        ctrl_outw(msk1, INTMSK1);
+        __raw_writew(msk0, INTMSK0);
+        __raw_writew(msk1, INTMSK1);
 }
 
 static void eoi_se7206_irq(unsigned int irq)
 {
         unsigned short sts0,sts1;
+        struct irq_desc *desc = irq_to_desc(irq);
 
-        if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+        if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
                 enable_se7206_irq(irq);
         /* FPGA isr clear */
-        sts0 = ctrl_inw(INTSTS0);
-        sts1 = ctrl_inw(INTSTS1);
+        sts0 = __raw_readw(INTSTS0);
+        sts1 = __raw_readw(INTSTS1);
 
         switch (irq) {
         case IRQ0_IRQ:
@@ -108,8 +109,8 @@ static void eoi_se7206_irq(unsigned int irq)
                 sts1 &= ~0x00ff;
                 break;
         }
-        ctrl_outw(sts0, INTSTS0);
-        ctrl_outw(sts1, INTSTS1);
+        __raw_writew(sts0, INTSTS0);
+        __raw_writew(sts1, INTSTS1);
 }
 
 static struct irq_chip se7206_irq_chip __read_mostly = {
@@ -136,11 +137,11 @@ void __init init_se7206_IRQ(void)
         make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
         make_se7206_irq(IRQ1_IRQ); /* ATA */
         make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
-        ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
+        __raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
 
         /* FPGA System register setup*/
-        ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */
-        ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */
+        __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
+        __raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
         /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
-        ctrl_outw(0x0001,INTSEL);
+        __raw_writew(0x0001,INTSEL);
 }
diff --git a/arch/sh/boards/mach-se/7206/setup.c b/arch/sh/boards/mach-se/7206/setup.c
index f5466384972e..8f5c65d43d1d 100644
--- a/arch/sh/boards/mach-se/7206/setup.c
+++ b/arch/sh/boards/mach-se/7206/setup.c
@@ -50,15 +50,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
 static struct heartbeat_data heartbeat_data = {
         .bit_pos        = heartbeat_bit_pos,
         .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
-        .regsize        = 32,
 };
 
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 };
 
 static struct platform_device heartbeat_device = {
@@ -67,8 +64,8 @@ static struct platform_device heartbeat_device = {
         .dev    = {
                 .platform_data  = &heartbeat_data,
         },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 static struct platform_device *se7206_devices[] __initdata = {
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index 051c29d4eae0..d4305c26e9f7 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -16,16 +16,18 @@
 #include <linux/io.h>
 #include <mach-se/mach/se7343.h>
 
+unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
+
 static void disable_se7343_irq(unsigned int irq)
 {
-        unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
-        ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
+        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
 }
 
 static void enable_se7343_irq(unsigned int irq)
 {
-        unsigned int bit = irq - SE7343_FPGA_IRQ_BASE;
-        ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
+        unsigned int bit = (unsigned int)get_irq_chip_data(irq);
+        __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
 }
 
 static struct irq_chip se7343_irq_chip __read_mostly = {
@@ -37,19 +39,16 @@ static struct irq_chip se7343_irq_chip __read_mostly = {
 
 static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
-        unsigned short intv = ctrl_inw(PA_CPLD_ST);
-        struct irq_desc *ext_desc;
-        unsigned int ext_irq = SE7343_FPGA_IRQ_BASE;
+        unsigned short intv = __raw_readw(PA_CPLD_ST);
+        unsigned int ext_irq = 0;
 
         intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
 
-        while (intv) {
-                if (intv & 1) {
-                        ext_desc = irq_desc + ext_irq;
-                        handle_level_irq(ext_irq, ext_desc);
-                }
-                intv >>= 1;
-                ext_irq++;
+        for (; intv; intv >>= 1, ext_irq++) {
+                if (!(intv & 1))
+                        continue;
+
+                generic_handle_irq(se7343_fpga_irq[ext_irq]);
         }
 }
 
@@ -58,16 +57,24 @@ static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
  */
 void __init init_7343se_IRQ(void)
 {
-        int i;
+        int i, irq;
+
+        __raw_writew(0, PA_CPLD_IMSK);  /* disable all irqs */
+        __raw_writew(0x2000, 0xb03fffec);       /* mrshpc irq enable */
 
-        ctrl_outw(0, PA_CPLD_IMSK);     /* disable all irqs */
-        ctrl_outw(0x2000, 0xb03fffec);  /* mrshpc irq enable */
+        for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
+                irq = create_irq();
+                if (irq < 0)
+                        return;
+                se7343_fpga_irq[i] = irq;
 
-        for (i = 0; i < SE7343_FPGA_IRQ_NR; i++)
-                set_irq_chip_and_handler_name(SE7343_FPGA_IRQ_BASE + i,
+                set_irq_chip_and_handler_name(se7343_fpga_irq[i],
                                               &se7343_irq_chip,
                                               handle_level_irq, "level");
 
+                set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
+        }
+
         set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
         set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
         set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c
index 4de56f35f419..d2370af56d77 100644
--- a/arch/sh/boards/mach-se/7343/setup.c
+++ b/arch/sh/boards/mach-se/7343/setup.c
@@ -11,26 +11,17 @@
 #include <asm/irq.h>
 #include <asm/io.h>
 
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 16,
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev = {
-                .platform_data = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 static struct mtd_partition nor_flash_partitions[] = {
@@ -82,7 +73,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .mapbase        = 0x16000000,
                 .regshift       = 1,
                 .flags          = ST16C2550C_FLAGS,
-                .irq            = UARTA_IRQ,
                 .uartclk        = 7372800,
         },
         [1] = {
@@ -90,7 +80,6 @@ static struct plat_serial8250_port serial_platform_data[] = {
                 .mapbase        = 0x17000000,
                 .regshift       = 1,
                 .flags          = ST16C2550C_FLAGS,
-                .irq            = UARTB_IRQ,
                 .uartclk        = 7372800,
         },
         { },
@@ -121,7 +110,7 @@ static struct resource usb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = USB_IRQ,
+                /* Filled in later */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -138,8 +127,8 @@ static struct isp116x_platform_data usb_platform_data = {
 static struct platform_device usb_device = {
         .name                   = "isp116x-hcd",
         .id                     = -1,
-        .num_resources          = ARRAY_SIZE(usb_resources),
-        .resource               = usb_resources,
+        .num_resources          = ARRAY_SIZE(usb_resources),
+        .resource               = usb_resources,
         .dev                    = {
                 .platform_data  = &usb_platform_data,
         },
@@ -155,6 +144,13 @@ static struct platform_device *sh7343se_platform_devices[] __initdata = {
 
 static int __init sh7343se_devices_setup(void)
 {
+        /* Wire-up dynamic vectors */
+        serial_platform_data[0].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTA];
+        serial_platform_data[1].irq = se7343_fpga_irq[SE7343_FPGA_IRQ_UARTB];
+
+        usb_resources[2].start = usb_resources[2].end =
+                se7343_fpga_irq[SE7343_FPGA_IRQ_USB];
+
         return platform_add_devices(sh7343se_platform_devices,
                                     ARRAY_SIZE(sh7343se_platform_devices));
 }
@@ -165,10 +161,10 @@ device_initcall(sh7343se_devices_setup);
  */
 static void __init sh7343se_setup(char **cmdline_p)
 {
-        ctrl_outw(0xf900, FPGA_OUT);    /* FPGA */
+        __raw_writew(0xf900, FPGA_OUT); /* FPGA */
 
-        ctrl_outw(0x0002, PORT_PECR);   /* PORT E 1 = IRQ5 */
-        ctrl_outw(0x0020, PORT_PSELD);
+        __raw_writew(0x0002, PORT_PECR);        /* PORT E 1 = IRQ5 */
+        __raw_writew(0x0020, PORT_PSELD);
 
         printk(KERN_INFO "MS7343CP01 Setup...done\n");
 }
@@ -179,6 +175,5 @@ static void __init sh7343se_setup(char **cmdline_p)
 static struct sh_machine_vector mv_7343se __initmv = {
         .mv_name = "SolutionEngine 7343",
         .mv_setup = sh7343se_setup,
-        .mv_nr_irqs = SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_NR,
         .mv_init_irq = init_7343se_IRQ,
 };
diff --git a/arch/sh/boards/mach-se/770x/irq.c b/arch/sh/boards/mach-se/770x/irq.c
index ec1fea571b52..1028c17b81bc 100644
--- a/arch/sh/boards/mach-se/770x/irq.c
+++ b/arch/sh/boards/mach-se/770x/irq.c
@@ -96,13 +96,13 @@ static struct ipr_desc ipr_irq_desc = {
 void __init init_se_IRQ(void)
 {
         /* Disable all interrupts */
-        ctrl_outw(0, BCR_ILCRA);
-        ctrl_outw(0, BCR_ILCRB);
-        ctrl_outw(0, BCR_ILCRC);
-        ctrl_outw(0, BCR_ILCRD);
-        ctrl_outw(0, BCR_ILCRE);
-        ctrl_outw(0, BCR_ILCRF);
-        ctrl_outw(0, BCR_ILCRG);
+        __raw_writew(0, BCR_ILCRA);
+        __raw_writew(0, BCR_ILCRB);
+        __raw_writew(0, BCR_ILCRC);
+        __raw_writew(0, BCR_ILCRD);
+        __raw_writew(0, BCR_ILCRE);
+        __raw_writew(0, BCR_ILCRF);
+        __raw_writew(0, BCR_ILCRG);
 
         register_ipr_controller(&ipr_irq_desc);
 }
diff --git a/arch/sh/boards/mach-se/770x/setup.c b/arch/sh/boards/mach-se/770x/setup.c
index 527eb6b12610..66d39d1b0901 100644
--- a/arch/sh/boards/mach-se/770x/setup.c
+++ b/arch/sh/boards/mach-se/770x/setup.c
@@ -93,15 +93,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
 static struct heartbeat_data heartbeat_data = {
         .bit_pos        = heartbeat_bit_pos,
         .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
-        .regsize        = 16,
 };
 
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
@@ -110,8 +107,8 @@ static struct platform_device heartbeat_device = {
         .dev    = {
                 .platform_data  = &heartbeat_data,
         },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7710) ||\
diff --git a/arch/sh/boards/mach-se/7721/irq.c b/arch/sh/boards/mach-se/7721/irq.c
index b417acc4dad0..d85022ea3f12 100644
--- a/arch/sh/boards/mach-se/7721/irq.c
+++ b/arch/sh/boards/mach-se/7721/irq.c
@@ -38,7 +38,7 @@ static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
 void __init init_se7721_IRQ(void)
 {
         /* PPCR */
-        ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118);
+        __raw_writew(__raw_readw(0xa4050118) & ~0x00ff, 0xa4050118);
 
         register_intc_controller(&intc_desc);
         intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);
diff --git a/arch/sh/boards/mach-se/7721/setup.c b/arch/sh/boards/mach-se/7721/setup.c
index 55af4c36b43a..7416ad7ee53a 100644
--- a/arch/sh/boards/mach-se/7721/setup.c
+++ b/arch/sh/boards/mach-se/7721/setup.c
@@ -23,15 +23,12 @@ static unsigned char heartbeat_bit_pos[] = { 8, 9, 10, 11, 12, 13, 14, 15 };
 static struct heartbeat_data heartbeat_data = {
         .bit_pos        = heartbeat_bit_pos,
         .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
-        .regsize        = 16,
 };
 
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
@@ -40,8 +37,8 @@ static struct platform_device heartbeat_device = {
         .dev    = {
                 .platform_data  = &heartbeat_data,
         },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 static struct resource cf_ide_resources[] = {
@@ -83,10 +80,10 @@ device_initcall(se7721_devices_setup);
 static void __init se7721_setup(char **cmdline_p)
 {
         /* for USB */
-        ctrl_outw(0x0000, 0xA405010C);  /* PGCR */
-        ctrl_outw(0x0000, 0xA405010E);  /* PHCR */
-        ctrl_outw(0x00AA, 0xA4050118);  /* PPCR */
-        ctrl_outw(0x0000, 0xA4050124);  /* PSELA */
+        __raw_writew(0x0000, 0xA405010C);       /* PGCR */
+        __raw_writew(0x0000, 0xA405010E);       /* PHCR */
+        __raw_writew(0x00AA, 0xA4050118);       /* PPCR */
+        __raw_writew(0x0000, 0xA4050124);       /* PSELA */
 }
 
 /*
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index b221b6842b0d..61605db04ee6 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -21,13 +21,13 @@ unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
 static void disable_se7722_irq(unsigned int irq)
 {
         unsigned int bit = (unsigned int)get_irq_chip_data(irq);
-        ctrl_outw(ctrl_inw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
+        __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
 }
 
 static void enable_se7722_irq(unsigned int irq)
 {
         unsigned int bit = (unsigned int)get_irq_chip_data(irq);
-        ctrl_outw(ctrl_inw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
+        __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
 }
 
 static struct irq_chip se7722_irq_chip __read_mostly = {
@@ -39,7 +39,7 @@ static struct irq_chip se7722_irq_chip __read_mostly = {
 
 static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
-        unsigned short intv = ctrl_inw(IRQ01_STS);
+        unsigned short intv = __raw_readw(IRQ01_STS);
         unsigned int ext_irq = 0;
 
         intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;
@@ -59,8 +59,8 @@ void __init init_se7722_IRQ(void)
 {
         int i, irq;
 
-        ctrl_outw(0, IRQ01_MASK);       /* disable all irqs */
-        ctrl_outw(0x2000, 0xb03fffec);  /* mrshpc irq enable */
+        __raw_writew(0, IRQ01_MASK);       /* disable all irqs */
+        __raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */
 
         for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
                 irq = create_irq();
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index b1cb9425b600..80a4e571b310 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -25,26 +25,17 @@
 #include <cpu/sh7722.h>
 
 /* Heartbeat */
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 16,
-};
-
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev = {
-                .platform_data = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 /* SMC91x */
@@ -165,32 +156,32 @@ device_initcall(se7722_devices_setup);
 
 static void __init se7722_setup(char **cmdline_p)
 {
-        ctrl_outw(0x010D, FPGA_OUT);    /* FPGA */
+        __raw_writew(0x010D, FPGA_OUT);    /* FPGA */
 
-        ctrl_outw(0x0000, PORT_PECR);   /* PORT E 1 = IRQ5 ,E 0 = BS */
-        ctrl_outw(0x1000, PORT_PJCR);   /* PORT J 1 = IRQ1,J 0 =IRQ0 */
+        __raw_writew(0x0000, PORT_PECR);   /* PORT E 1 = IRQ5 ,E 0 = BS */
+        __raw_writew(0x1000, PORT_PJCR);   /* PORT J 1 = IRQ1,J 0 =IRQ0 */
 
         /* LCDC I/O */
-        ctrl_outw(0x0020, PORT_PSELD);
+        __raw_writew(0x0020, PORT_PSELD);
 
         /* SIOF1*/
-        ctrl_outw(0x0003, PORT_PSELB);
-        ctrl_outw(0xe000, PORT_PSELC);
-        ctrl_outw(0x0000, PORT_PKCR);
+        __raw_writew(0x0003, PORT_PSELB);
+        __raw_writew(0xe000, PORT_PSELC);
+        __raw_writew(0x0000, PORT_PKCR);
 
         /* LCDC */
-        ctrl_outw(0x4020, PORT_PHCR);
-        ctrl_outw(0x0000, PORT_PLCR);
-        ctrl_outw(0x0000, PORT_PMCR);
-        ctrl_outw(0x0002, PORT_PRCR);
-        ctrl_outw(0x0000, PORT_PXCR);   /* LCDC,CS6A */
+        __raw_writew(0x4020, PORT_PHCR);
+        __raw_writew(0x0000, PORT_PLCR);
+        __raw_writew(0x0000, PORT_PMCR);
+        __raw_writew(0x0002, PORT_PRCR);
+        __raw_writew(0x0000, PORT_PXCR);   /* LCDC,CS6A */
 
         /* KEYSC */
-        ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */
-        ctrl_outw(0x0000, PORT_PYCR);
-        ctrl_outw(0x0000, PORT_PZCR);
-        ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
-        ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
+        __raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
+        __raw_writew(0x0000, PORT_PYCR);
+        __raw_writew(0x0000, PORT_PZCR);
+        __raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
+        __raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
 }
 
 /*
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index f76cf3b49f23..0942be2daef6 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -72,14 +72,14 @@ static void disable_se7724_irq(unsigned int irq)
 {
         struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
         unsigned int bit = irq - set.base;
-        ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr);
+        __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
 }
 
 static void enable_se7724_irq(unsigned int irq)
 {
         struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
         unsigned int bit = irq - set.base;
-        ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
+        __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
 }
 
 static struct irq_chip se7724_irq_chip __read_mostly = {
@@ -92,19 +92,16 @@ static struct irq_chip se7724_irq_chip __read_mostly = {
 static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
         struct fpga_irq set = get_fpga_irq(irq);
-        unsigned short intv = ctrl_inw(set.sraddr);
-        struct irq_desc *ext_desc;
+        unsigned short intv = __raw_readw(set.sraddr);
         unsigned int ext_irq = set.base;
 
         intv &= set.mask;
 
-        while (intv) {
-                if (intv & 0x0001) {
-                        ext_desc = irq_desc + ext_irq;
-                        handle_level_irq(ext_irq, ext_desc);
-                }
-                intv >>= 1;
-                ext_irq++;
+        for (; intv; intv >>= 1, ext_irq++) {
+                if (!(intv & 1))
+                        continue;
+
+                generic_handle_irq(ext_irq);
         }
 }
 
@@ -113,20 +110,39 @@ static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
  */
 void __init init_se7724_IRQ(void)
 {
-        int i;
-
-        ctrl_outw(0xffff, IRQ0_MR);  /* mask all */
-        ctrl_outw(0xffff, IRQ1_MR);  /* mask all */
-        ctrl_outw(0xffff, IRQ2_MR);  /* mask all */
-        ctrl_outw(0x0000, IRQ0_SR);  /* clear irq */
-        ctrl_outw(0x0000, IRQ1_SR);  /* clear irq */
-        ctrl_outw(0x0000, IRQ2_SR);  /* clear irq */
-        ctrl_outw(0x002a, IRQ_MODE); /* set irq type */
-
-        for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
-                set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
+        int i, nid = cpu_to_node(boot_cpu_data);
+
+        __raw_writew(0xffff, IRQ0_MR);  /* mask all */
+        __raw_writew(0xffff, IRQ1_MR);  /* mask all */
+        __raw_writew(0xffff, IRQ2_MR);  /* mask all */
+        __raw_writew(0x0000, IRQ0_SR);  /* clear irq */
+        __raw_writew(0x0000, IRQ1_SR);  /* clear irq */
+        __raw_writew(0x0000, IRQ2_SR);  /* clear irq */
+        __raw_writew(0x002a, IRQ_MODE); /* set irq type */
+
+        for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) {
+                int irq, wanted;
+
+                wanted = SE7724_FPGA_IRQ_BASE + i;
+
+                irq = create_irq_nr(wanted, nid);
+                if (unlikely(irq == 0)) {
+                        pr_err("%s: failed hooking irq %d for FPGA\n",
+                               __func__, wanted);
+                        return;
+                }
+
+                if (unlikely(irq != wanted)) {
+                        pr_err("%s: got irq %d but wanted %d, bailing.\n",
+                               __func__, irq, wanted);
+                        destroy_irq(irq);
+                        return;
+                }
+
+                set_irq_chip_and_handler_name(irq,
                                               &se7724_irq_chip,
                                               handle_level_irq, "level");
+        }
 
         set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
         set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/sh/boards/mach-se/7724/sdram.S b/arch/sh/boards/mach-se/7724/sdram.S
index 9040167d5022..6fa4734d09c7 100644
--- a/arch/sh/boards/mach-se/7724/sdram.S
+++ b/arch/sh/boards/mach-se/7724/sdram.S
@@ -39,6 +39,10 @@ ENTRY(ms7724se_sdram_leave_start)
 
         /* DBSC: put memory in auto-refresh mode */
 
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_RSTANDBY, r0
+        bf      resume_rstandby
+
         ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
         WAIT 1
         ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
@@ -49,4 +53,79 @@ ENTRY(ms7724se_sdram_leave_start)
         rts
          nop
 
+resume_rstandby:
+
+        /* CPG: setup clocks before restarting external memory */
+
+        ED 0xA4150024, 0x00004000 /* PLLCR */
+
+        mov.l   FRQCRA,r0
+        mov.l   @r0,r3
+        mov.l   KICK,r1
+        or      r1, r3
+        mov.l   r3, @r0
+
+        mov.l   LSTATS,r0
+        mov     #1,r1
+WAIT_LSTATS:
+        mov.l   @r0,r3
+        tst     r1,r3
+        bf      WAIT_LSTATS
+
+        /* DBSC: re-initialize and put in auto-refresh */
+
+        ED 0xFD000108, 0x00000181 /* DBPDCNT0 */
+        ED 0xFD000020, 0x015B0002 /* DBCONF */
+        ED 0xFD000030, 0x03071502 /* DBTR0 */
+        ED 0xFD000034, 0x02020102 /* DBTR1 */
+        ED 0xFD000038, 0x01090405 /* DBTR2 */
+        ED 0xFD00003C, 0x00000002 /* DBTR3 */
+        ED 0xFD000008, 0x00000005 /* DBKIND */
+        ED 0xFD000040, 0x00000001 /* DBRFPDN0 */
+        ED 0xFD000040, 0x00000000 /* DBRFPDN0 */
+        ED 0xFD000018, 0x00000001 /* DBCKECNT */
+
+        mov     #100,r0
+WAIT_400NS:
+        dt      r0
+        bf      WAIT_400NS
+
+        ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
+        ED 0xFD000060, 0x00020000 /* DBMRCNT (EMR2) */
+        ED 0xFD000060, 0x00030000 /* DBMRCNT (EMR3) */
+        ED 0xFD000060, 0x00010004 /* DBMRCNT (EMR) */
+        ED 0xFD000060, 0x00000532 /* DBMRCNT (MRS) */
+        ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
+        ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
+        ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
+        ED 0xFD000060, 0x00000432 /* DBMRCNT (MRS) */
+        ED 0xFD000060, 0x000103c0 /* DBMRCNT (EMR) */
+        ED 0xFD000060, 0x00010040 /* DBMRCNT (EMR) */
+
+        mov     #100,r0
+WAIT_400NS_2:
+        dt      r0
+        bf      WAIT_400NS_2
+
+        ED 0xFD000010, 0x00000001 /* DBEN */
+        ED 0xFD000044, 0x0000050f /* DBRFPDN1 */
+        ED 0xFD000048, 0x236800e6 /* DBRFPDN2 */
+
+        mov.l   DUMMY,r0
+        mov.l   @r0, r1 /* force single dummy read */
+
+        ED 0xFD000014, 0x00000002 /* DBCMDCNT (PALL) */
+        ED 0xFD000014, 0x00000004 /* DBCMDCNT (REF) */
+        ED 0xFD000108, 0x00000080 /* DBPDCNT0 */
+        ED 0xFD000040, 0x00010000 /* DBRFPDN0 */
+
+        rts
+         nop
+
+        .balign 4
+DUMMY:  .long   0xac400000
+FRQCRA: .long   0xa4150000
+KICK:   .long   0x80000000
+LSTATS: .long   0xa4150060
+
 ENTRY(ms7724se_sdram_leave_end)
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 858ecb25d469..66cdbc3c7af9 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -53,26 +53,17 @@
  */
 
 /* Heartbeat */
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 16,
-};
-
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev = {
-                .platform_data = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 /* LAN91C111 */
@@ -265,12 +256,12 @@ static struct platform_device ceu1_device = {
 #define FCLKACR         0xa4150008
 static void fsimck_init(struct clk *clk)
 {
-        u32 status = ctrl_inl(clk->enable_reg);
+        u32 status = __raw_readl(clk->enable_reg);
 
         /* use external clock */
         status &= ~0x000000ff;
         status |= 0x00000080;
-        ctrl_outl(status, clk->enable_reg);
+        __raw_writel(status, clk->enable_reg);
 }
 
 static struct clk_ops fsimck_clk_ops = {
@@ -322,7 +313,7 @@ static struct platform_device fsi_device = {
 /* KEYSC in SoC (Needs SW33-2 set to ON) */
 static struct sh_keysc_info keysc_info = {
         .mode = SH_KEYSC_MODE_1,
-        .scan_timing = 10,
+        .scan_timing = 3,
         .delay = 50,
         .keycodes = {
                 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
@@ -460,7 +451,7 @@ static struct resource sdhi0_cn7_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 101,
+                .start  = 100,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -483,7 +474,7 @@ static struct resource sdhi1_cn8_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = 24,
+                .start  = 23,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -498,6 +489,26 @@ static struct platform_device sdhi1_cn8_device = {
         },
 };
 
+/* IrDA */
+static struct resource irda_resources[] = {
+        [0] = {
+                .name   = "IrDA",
+                .start  = 0xA45D0000,
+                .end    = 0xA45D0049,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 20,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device irda_device = {
+        .name           = "sh_sir",
+        .num_resources  = ARRAY_SIZE(irda_resources),
+        .resource       = irda_resources,
+};
+
 static struct platform_device *ms7724se_devices[] __initdata = {
         &heartbeat_device,
         &smc91x_eth_device,
@@ -512,6 +523,7 @@ static struct platform_device *ms7724se_devices[] __initdata = {
         &fsi_device,
         &sdhi0_cn7_device,
         &sdhi1_cn8_device,
+        &irda_device,
 };
 
 /* I2C device */
@@ -531,7 +543,7 @@ static int __init sh_eth_is_eeprom_ready(void)
         int t = 10000;
 
         while (t--) {
-                if (!ctrl_inw(EEPROM_STAT))
+                if (!__raw_readw(EEPROM_STAT))
                         return 1;
                 udelay(1);
         }
@@ -551,13 +563,13 @@ static void __init sh_eth_init(void)
 
         /* read MAC addr from EEPROM */
         for (i = 0 ; i < 3 ; i++) {
-                ctrl_outw(0x0, EEPROM_OP); /* read */
-                ctrl_outw(i*2, EEPROM_ADR);
-                ctrl_outw(0x1, EEPROM_STRT);
+                __raw_writew(0x0, EEPROM_OP); /* read */
+                __raw_writew(i*2, EEPROM_ADR);
+                __raw_writew(0x1, EEPROM_STRT);
                 if (!sh_eth_is_eeprom_ready())
                         return;
 
-                mac = ctrl_inw(EEPROM_DATA);
+                mac = __raw_readw(EEPROM_DATA);
                 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
                 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
         }
@@ -594,28 +606,29 @@ arch_initcall(arch_setup);
 
 static int __init devices_setup(void)
 {
-        u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
-        struct clk *fsia_clk;
+        u16 sw = __raw_readw(SW4140); /* select camera, monitor */
+        struct clk *clk;
 
         /* register board specific self-refresh code */
-        sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
+        sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF |
+                                        SUSP_SH_RSTANDBY,
                                         &ms7724se_sdram_enter_start,
                                         &ms7724se_sdram_enter_end,
                                         &ms7724se_sdram_leave_start,
                                         &ms7724se_sdram_leave_end);
         /* Reset Release */
-        ctrl_outw(ctrl_inw(FPGA_OUT) &
+        __raw_writew(__raw_readw(FPGA_OUT) &
                   ~((1 << 1)  | /* LAN */
                     (1 << 6)  | /* VIDEO DAC */
                     (1 << 7)  | /* AK4643 */
+                    (1 << 8)  | /* IrDA */
                     (1 << 12) | /* USB0 */
                     (1 << 14)), /* RMII */
                   FPGA_OUT);
 
         /* turn on USB clocks, use external clock */
-        ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
+        __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
 
-#ifdef CONFIG_PM
         /* Let LED9 show STATUS2 */
         gpio_request(GPIO_FN_STATUS2, NULL);
 
@@ -624,28 +637,12 @@ static int __init devices_setup(void)
 
         /* Lit LED11 show PDSTATUS */
         gpio_request(GPIO_FN_PDSTATUS, NULL);
-#else
-        /* Lit LED9 */
-        gpio_request(GPIO_PTJ6, NULL);
-        gpio_direction_output(GPIO_PTJ6, 1);
-        gpio_export(GPIO_PTJ6, 0);
-
-        /* Lit LED10 */
-        gpio_request(GPIO_PTJ5, NULL);
-        gpio_direction_output(GPIO_PTJ5, 1);
-        gpio_export(GPIO_PTJ5, 0);
-
-        /* Lit LED11 */
-        gpio_request(GPIO_PTJ7, NULL);
-        gpio_direction_output(GPIO_PTJ7, 1);
-        gpio_export(GPIO_PTJ7, 0);
-#endif
 
         /* enable USB0 port */
-        ctrl_outw(0x0600, 0xa40501d4);
+        __raw_writew(0x0600, 0xa40501d4);
 
         /* enable USB1 port */
-        ctrl_outw(0x0600, 0xa4050192);
+        __raw_writew(0x0600, 0xa4050192);
 
         /* enable IRQ 0,1,2 */
         gpio_request(GPIO_FN_INTC_IRQ0, NULL);
@@ -693,7 +690,7 @@ static int __init devices_setup(void)
         gpio_request(GPIO_FN_LCDVCPWC, NULL);
         gpio_request(GPIO_FN_LCDRD,    NULL);
         gpio_request(GPIO_FN_LCDLCLK,  NULL);
-        ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
+        __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
 
         /* enable CEU0 */
         gpio_request(GPIO_FN_VIO0_D15, NULL);
@@ -764,13 +761,18 @@ static int __init devices_setup(void)
         gpio_request(GPIO_FN_CLKAUDIOBO, NULL);
         gpio_request(GPIO_FN_FSIIASD,    NULL);
 
+        /* set SPU2 clock to 83.4 MHz */
+        clk = clk_get(NULL, "spu_clk");
+        clk_set_rate(clk, clk_round_rate(clk, 83333333));
+        clk_put(clk);
+
         /* change parent of FSI A */
-        fsia_clk = clk_get(NULL, "fsia_clk");
+        clk = clk_get(NULL, "fsia_clk");
         clk_register(&fsimcka_clk);
-        clk_set_parent(fsia_clk, &fsimcka_clk);
-        clk_set_rate(fsia_clk, 11000);
+        clk_set_parent(clk, &fsimcka_clk);
+        clk_set_rate(clk, 11000);
         clk_set_rate(&fsimcka_clk, 11000);
-        clk_put(fsia_clk);
+        clk_put(clk);
 
         /* SDHI0 connected to cn7 */
         gpio_request(GPIO_FN_SDHI0CD, NULL);
@@ -792,6 +794,10 @@ static int __init devices_setup(void)
         gpio_request(GPIO_FN_SDHI1CMD, NULL);
         gpio_request(GPIO_FN_SDHI1CLK, NULL);
 
+        /* enable IrDA */
+        gpio_request(GPIO_FN_IRDA_OUT, NULL);
+        gpio_request(GPIO_FN_IRDA_IN,  NULL);
+
         /*
          * enable SH-Eth
          *
diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c
index 121744c08714..d5c9edc172a3 100644
--- a/arch/sh/boards/mach-se/7780/irq.c
+++ b/arch/sh/boards/mach-se/7780/irq.c
@@ -24,30 +24,30 @@
 void __init init_se7780_IRQ(void)
 {
         /* enable all interrupt at FPGA */
-        ctrl_outw(0, FPGA_INTMSK1);
+        __raw_writew(0, FPGA_INTMSK1);
         /* mask SM501 interrupt */
-        ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
+        __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
         /* enable all interrupt at FPGA */
-        ctrl_outw(0, FPGA_INTMSK2);
+        __raw_writew(0, FPGA_INTMSK2);
 
         /* set FPGA INTSEL register */
         /* FPGA + 0x06 */
-        ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) |
+        __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
                 (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
 
         /* FPGA + 0x08 */
-        ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
+        __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
                 (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
                 (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
                 (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
 
         /* FPGA + 0x0A */
-        ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
+        __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
 
         plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
 
         /* ICR1: detect low level(for 2ndcut) */
-        ctrl_outl(0xAAAA0000, INTC_ICR1);
+        __raw_writel(0xAAAA0000, INTC_ICR1);
 
         /*
          * FPGA PCISEL register initialize
@@ -63,6 +63,6 @@ void __init init_se7780_IRQ(void)
          *  INTD || INTD  | INTC  |  --   | INTA
          *  -------------------------------------
          */
-        ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
-        ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
+        __raw_writew(0x0013, FPGA_PCI_INTSEL1);
+        __raw_writew(0xE402, FPGA_PCI_INTSEL2);
 }
diff --git a/arch/sh/boards/mach-se/7780/setup.c b/arch/sh/boards/mach-se/7780/setup.c
index 1d3a867e94e3..6f7c207138e1 100644
--- a/arch/sh/boards/mach-se/7780/setup.c
+++ b/arch/sh/boards/mach-se/7780/setup.c
@@ -17,26 +17,17 @@
 #include <asm/heartbeat.h>
 
 /* Heartbeat */
-static struct heartbeat_data heartbeat_data = {
-        .regsize = 16,
-};
-
-static struct resource heartbeat_resources[] = {
-        [0] = {
-                .start  = PA_LED,
-                .end    = PA_LED,
-                .flags  = IORESOURCE_MEM,
-        },
+static struct resource heartbeat_resource = {
+        .start  = PA_LED,
+        .end    = PA_LED,
+        .flags  = IORESOURCE_MEM | IORESOURCE_MEM_16BIT,
 };
 
 static struct platform_device heartbeat_device = {
         .name           = "heartbeat",
         .id             = -1,
-        .dev = {
-                .platform_data = &heartbeat_data,
-        },
-        .num_resources  = ARRAY_SIZE(heartbeat_resources),
-        .resource       = heartbeat_resources,
+        .num_resources  = 1,
+        .resource       = &heartbeat_resource,
 };
 
 /* SMC91x */
@@ -84,14 +75,14 @@ device_initcall(se7780_devices_setup);
 static void __init se7780_setup(char **cmdline_p)
 {
         /* "SH-Linux" on LED Display */
-        ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
-        ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
-        ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
-        ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
-        ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
-        ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
-        ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
-        ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
+        __raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
+        __raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
+        __raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
+        __raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
+        __raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
+        __raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
+        __raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
+        __raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
 
         printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n");
 
@@ -102,15 +93,15 @@ static void __init se7780_setup(char **cmdline_p)
          *   REQ2/GNT2 -> Serial ATA
          *   REQ3/GNT3 -> PCI slot
          */
-        ctrl_outw(0x0213, FPGA_REQSEL);
+        __raw_writew(0x0213, FPGA_REQSEL);
 
         /* GPIO setting */
-        ctrl_outw(0x0000, GPIO_PECR);
-        ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
-        ctrl_outw(0x0c00, GPIO_PMSELR);
+        __raw_writew(0x0000, GPIO_PECR);
+        __raw_writew(__raw_readw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
+        __raw_writew(0x0c00, GPIO_PMSELR);
 
         /* iVDR Power ON */
-        ctrl_outw(0x0001, FPGA_IVDRPW);
+        __raw_writew(0x0001, FPGA_IVDRPW);
 }
 
 /*
diff --git a/arch/sh/boards/mach-sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c
index a8b9f844ab5b..1b200990500c 100644
--- a/arch/sh/boards/mach-sh03/rtc.c
+++ b/arch/sh/boards/mach-sh03/rtc.c
@@ -44,15 +44,15 @@ unsigned long get_cmos_time(void)
         spin_lock(&sh03_rtc_lock);
  again:
         do {
-                sec  = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10;
-                min  = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10;
-                hour = (ctrl_inb(RTC_HOU1) & 0xf) + (ctrl_inb(RTC_HOU10) & 0xf) * 10;
-                day  = (ctrl_inb(RTC_DAY1) & 0xf) + (ctrl_inb(RTC_DAY10) & 0xf) * 10;
-                mon  = (ctrl_inb(RTC_MON1) & 0xf) + (ctrl_inb(RTC_MON10) & 0xf) * 10;
-                year = (ctrl_inb(RTC_YEA1) & 0xf) + (ctrl_inb(RTC_YEA10) & 0xf) * 10
-                     + (ctrl_inb(RTC_YEA100 ) & 0xf) * 100
-                     + (ctrl_inb(RTC_YEA1000) & 0xf) * 1000;
-        } while (sec != (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10);
+                sec  = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10;
+                min  = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
+                hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10;
+                day  = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10;
+                mon  = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10;
+                year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10
+                     + (__raw_readb(RTC_YEA100 ) & 0xf) * 100
+                     + (__raw_readb(RTC_YEA1000) & 0xf) * 1000;
+        } while (sec != (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10);
         if (year == 0 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
             hour > 23 || min > 59 || sec > 59) {
                 printk(KERN_ERR
@@ -60,16 +60,16 @@ unsigned long get_cmos_time(void)
                 printk("year=%d, mon=%d, day=%d, hour=%d, min=%d, sec=%d\n",
                        year, mon, day, hour, min, sec);
 
-                ctrl_outb(0, RTC_SEC1); ctrl_outb(0, RTC_SEC10);
-                ctrl_outb(0, RTC_MIN1); ctrl_outb(0, RTC_MIN10);
-                ctrl_outb(0, RTC_HOU1); ctrl_outb(0, RTC_HOU10);
-                ctrl_outb(6, RTC_WEE1);
-                ctrl_outb(1, RTC_DAY1); ctrl_outb(0, RTC_DAY10);
-                ctrl_outb(1, RTC_MON1); ctrl_outb(0, RTC_MON10);
-                ctrl_outb(0, RTC_YEA1); ctrl_outb(0, RTC_YEA10);
-                ctrl_outb(0, RTC_YEA100);
-                ctrl_outb(2, RTC_YEA1000);
-                ctrl_outb(0, RTC_CTL);
+                __raw_writeb(0, RTC_SEC1); __raw_writeb(0, RTC_SEC10);
+                __raw_writeb(0, RTC_MIN1); __raw_writeb(0, RTC_MIN10);
+                __raw_writeb(0, RTC_HOU1); __raw_writeb(0, RTC_HOU10);
+                __raw_writeb(6, RTC_WEE1);
+                __raw_writeb(1, RTC_DAY1); __raw_writeb(0, RTC_DAY10);
+                __raw_writeb(1, RTC_MON1); __raw_writeb(0, RTC_MON10);
+                __raw_writeb(0, RTC_YEA1); __raw_writeb(0, RTC_YEA10);
+                __raw_writeb(0, RTC_YEA100);
+                __raw_writeb(2, RTC_YEA1000);
+                __raw_writeb(0, RTC_CTL);
                 goto again;
         }
 
@@ -93,9 +93,9 @@ static int set_rtc_mmss(unsigned long nowtime)
         /* gets recalled with irq locally disabled */
         spin_lock(&sh03_rtc_lock);
         for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
-                if (!(ctrl_inb(RTC_CTL) & RTC_BUSY))
+                if (!(__raw_readb(RTC_CTL) & RTC_BUSY))
                         break;
-        cmos_minutes = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10;
+        cmos_minutes = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
         real_seconds = nowtime % 60;
         real_minutes = nowtime / 60;
         if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
@@ -103,10 +103,10 @@ static int set_rtc_mmss(unsigned long nowtime)
         real_minutes %= 60;
 
         if (abs(real_minutes - cmos_minutes) < 30) {
-                ctrl_outb(real_seconds % 10, RTC_SEC1);
-                ctrl_outb(real_seconds / 10, RTC_SEC10);
-                ctrl_outb(real_minutes % 10, RTC_MIN1);
-                ctrl_outb(real_minutes / 10, RTC_MIN10);
+                __raw_writeb(real_seconds % 10, RTC_SEC1);
+                __raw_writeb(real_seconds / 10, RTC_SEC10);
+                __raw_writeb(real_minutes % 10, RTC_MIN1);
+                __raw_writeb(real_minutes / 10, RTC_MIN10);
         } else {
                 printk(KERN_WARNING
                        "set_rtc_mmss: can't update from %d to %d\n",
diff --git a/arch/sh/boards/mach-sh03/setup.c b/arch/sh/boards/mach-sh03/setup.c
index 74cfb4b8b03d..af4a0c012a96 100644
--- a/arch/sh/boards/mach-sh03/setup.c
+++ b/arch/sh/boards/mach-sh03/setup.c
@@ -82,7 +82,7 @@ static int __init sh03_devices_setup(void)
         /* open I/O area window */
         paddrbase = virt_to_phys((void *)PA_AREA5_IO);
         prot = PAGE_KERNEL_PCC(1, _PAGE_PCC_IO16);
-        cf_ide_base = p3_ioremap(paddrbase, PAGE_SIZE, prot.pgprot);
+        cf_ide_base = ioremap_prot(paddrbase, PAGE_SIZE, pgprot_val(prot));
         if (!cf_ide_base) {
                 printk("allocate_cf_area : can't open CF I/O window!\n");
                 return -ENOMEM;
diff --git a/arch/sh/boards/mach-sh7763rdp/irq.c b/arch/sh/boards/mach-sh7763rdp/irq.c
index d8ebfa7d8c76..add698c8f2b4 100644
--- a/arch/sh/boards/mach-sh7763rdp/irq.c
+++ b/arch/sh/boards/mach-sh7763rdp/irq.c
@@ -28,18 +28,18 @@
 void __init init_sh7763rdp_IRQ(void)
 {
         /* GPIO enabled */
-        ctrl_outl(1 << 25, INTC_INT2MSKCR);
+        __raw_writel(1 << 25, INTC_INT2MSKCR);
 
         /* enable GPIO interrupts */
-        ctrl_outl((ctrl_inl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
+        __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
                   INTC_INT2PRI7);
 
         /* USBH enabled */
-        ctrl_outl(1 << 17, INTC_INT2MSKCR1);
+        __raw_writel(1 << 17, INTC_INT2MSKCR1);
 
         /* GETHER enabled */
-        ctrl_outl(1 << 16, INTC_INT2MSKCR1);
+        __raw_writel(1 << 16, INTC_INT2MSKCR1);
 
         /* DMAC enabled */
-        ctrl_outl(1 << 8, INTC_INT2MSKCR);
+        __raw_writel(1 << 8, INTC_INT2MSKCR);
 }
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
index 390534a0b35c..f64a6918224c 100644
--- a/arch/sh/boards/mach-sh7763rdp/setup.c
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -158,50 +158,50 @@ device_initcall(sh7763rdp_devices_setup);
 static void __init sh7763rdp_setup(char **cmdline_p)
 {
         /* Board version check */
-        if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
+        if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
                 printk(KERN_INFO "RTE Standard Configuration\n");
         else
                 printk(KERN_INFO "RTA Standard Configuration\n");
 
         /* USB pin select bits (clear bit 5-2 to 0) */
-        ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
+        __raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
         /* USBH setup port I controls to other (clear bits 4-9 to 0) */
-        ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR);
+        __raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);
 
         /* Select USB Host controller */
-        ctrl_outw(0x00, USB_USBHSC);
+        __raw_writew(0x00, USB_USBHSC);
 
         /* For LCD */
         /* set PTJ7-1, bits 15-2 of PJCR to 0 */
-        ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR);
+        __raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);
         /* set PTI5, bits 11-10 of PICR to 0 */
-        ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR);
-        ctrl_outw(0, PORT_PKCR);
-        ctrl_outw(0, PORT_PLCR);
+        __raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);
+        __raw_writew(0, PORT_PKCR);
+        __raw_writew(0, PORT_PLCR);
         /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
-        ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
+        __raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
         /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
-        ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
+        __raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
 
         /* For HAC */
         /* bit3-0  0100:HAC & SSI1 enable */
-        ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
+        __raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
         /* bit14      1:SSI_HAC_CLK enable */
-        ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
+        __raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
 
         /* SH-Ether */
-        ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
-        ctrl_outw(0x0, PORT_PFCR);
-        ctrl_outw(0x0, PORT_PFCR);
-        ctrl_outw(0x0, PORT_PFCR);
+        __raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
+        __raw_writew(0x0, PORT_PFCR);
+        __raw_writew(0x0, PORT_PFCR);
+        __raw_writew(0x0, PORT_PFCR);
 
         /* MMC */
         /*selects SCIF and MMC other functions */
-        ctrl_outw(0x0001, PORT_PSEL0);
+        __raw_writew(0x0001, PORT_PSEL0);
         /* MMC clock operates */
-        ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1);
-        ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR);
-        ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
+        __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);
+        __raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR);
+        __raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
 }
 
 static struct sh_machine_vector mv_sh7763rdp __initmv = {
diff --git a/arch/sh/boards/mach-snapgear/setup.c b/arch/sh/boards/mach-snapgear/setup.c
index a3277a23cf14..331745dee379 100644
--- a/arch/sh/boards/mach-snapgear/setup.c
+++ b/arch/sh/boards/mach-snapgear/setup.c
@@ -30,7 +30,7 @@
 
 static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
 {
-        (void)ctrl_inb(0xb8000000);     /* dummy read */
+        (void)__raw_readb(0xb8000000);  /* dummy read */
 
         printk("SnapGear: erase switch interrupt!\n");
 
diff --git a/arch/sh/boards/mach-systemh/irq.c b/arch/sh/boards/mach-systemh/irq.c
index 986a0e71d220..523aea5dc94e 100644
--- a/arch/sh/boards/mach-systemh/irq.c
+++ b/arch/sh/boards/mach-systemh/irq.c
@@ -41,13 +41,13 @@ static void disable_systemh_irq(unsigned int irq)
                 unsigned long val, mask = 0x01 << 1;
 
                 /* Clear the "irq"th bit in the mask and set it in the request */
-                val = ctrl_inl((unsigned long)systemh_irq_mask_register);
+                val = __raw_readl((unsigned long)systemh_irq_mask_register);
                 val &= ~mask;
-                ctrl_outl(val, (unsigned long)systemh_irq_mask_register);
+                __raw_writel(val, (unsigned long)systemh_irq_mask_register);
 
-                val = ctrl_inl((unsigned long)systemh_irq_request_register);
+                val = __raw_readl((unsigned long)systemh_irq_request_register);
                 val |= mask;
-                ctrl_outl(val, (unsigned long)systemh_irq_request_register);
+                __raw_writel(val, (unsigned long)systemh_irq_request_register);
         }
 }
 
@@ -57,9 +57,9 @@ static void enable_systemh_irq(unsigned int irq)
                 unsigned long val, mask = 0x01 << 1;
 
                 /* Set "irq"th bit in the mask register */
-                val = ctrl_inl((unsigned long)systemh_irq_mask_register);
+                val = __raw_readl((unsigned long)systemh_irq_mask_register);
                 val |= mask;
-                ctrl_outl(val, (unsigned long)systemh_irq_mask_register);
+                __raw_writel(val, (unsigned long)systemh_irq_mask_register);
         }
 }
 
diff --git a/arch/sh/boards/mach-titan/Makefile b/arch/sh/boards/mach-titan/Makefile
deleted file mode 100644
index 08d753700062..000000000000
--- a/arch/sh/boards/mach-titan/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the Nimble Microsystems TITAN specific parts of the kernel
-#
-
-obj-y    := setup.o io.o
diff --git a/arch/sh/boards/mach-titan/io.c b/arch/sh/boards/mach-titan/io.c
deleted file mode 100644
index 0130e9826aca..000000000000
--- a/arch/sh/boards/mach-titan/io.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- *      I/O routines for Titan
- */
-#include <linux/pci.h>
-#include <asm/machvec.h>
-#include <asm/addrspace.h>
-#include <mach/titan.h>
-#include <asm/io.h>
-
-static inline unsigned int port2adr(unsigned int port)
-{
-        maybebadio((unsigned long)port);
-        return port;
-}
-
-u8 titan_inb(unsigned long port)
-{
-        if (PXSEG(port))
-                return ctrl_inb(port);
-        return ctrl_inw(port2adr(port)) & 0xff;
-}
-
-u8 titan_inb_p(unsigned long port)
-{
-        u8 v;
-
-        if (PXSEG(port))
-                v = ctrl_inb(port);
-        else
-                v = ctrl_inw(port2adr(port)) & 0xff;
-        ctrl_delay();
-        return v;
-}
-
-u16 titan_inw(unsigned long port)
-{
-        if (PXSEG(port))
-                return ctrl_inw(port);
-        else if (port >= 0x2000)
-                return ctrl_inw(port2adr(port));
-        else
-                maybebadio(port);
-        return 0;
-}
-
-u32 titan_inl(unsigned long port)
-{
-        if (PXSEG(port))
-                return ctrl_inl(port);
-        else if (port >= 0x2000)
-                return ctrl_inw(port2adr(port));
-        else
-                maybebadio(port);
-        return 0;
-}
-
-void titan_outb(u8 value, unsigned long port)
-{
-        if (PXSEG(port))
-                ctrl_outb(value, port);
-        else
-                ctrl_outw(value, port2adr(port));
-}
-
-void titan_outb_p(u8 value, unsigned long port)
-{
-        if (PXSEG(port))
-                ctrl_outb(value, port);
-        else
-                ctrl_outw(value, port2adr(port));
-        ctrl_delay();
-}
-
-void titan_outw(u16 value, unsigned long port)
-{
-        if (PXSEG(port))
-                ctrl_outw(value, port);
-        else if (port >= 0x2000)
-                ctrl_outw(value, port2adr(port));
-        else
-                maybebadio(port);
-}
-
-void titan_outl(u32 value, unsigned long port)
-{
-        if (PXSEG(port))
-                ctrl_outl(value, port);
-        else
-                maybebadio(port);
-}
-
-void titan_insl(unsigned long port, void *dst, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void titan_outsl(unsigned long port, const void *src, unsigned long count)
-{
-        maybebadio(port);
-}
-
-void __iomem *titan_ioport_map(unsigned long port, unsigned int size)
-{
-        if (PXSEG(port))
-                return (void __iomem *)port;
-
-        return (void __iomem *)port2adr(port);
-}
diff --git a/arch/sh/boards/mach-x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c
index b5c673c39337..5c9842704c60 100644
--- a/arch/sh/boards/mach-x3proto/ilsel.c
+++ b/arch/sh/boards/mach-x3proto/ilsel.c
@@ -70,10 +70,10 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
         pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n",
                  __func__, bit, addr, shift, set);
 
-        tmp = ctrl_inw(addr);
+        tmp = __raw_readw(addr);
         tmp &= ~(0xf << shift);
         tmp |= set << shift;
-        ctrl_outw(tmp, addr);
+        __raw_writew(tmp, addr);
 }
 
 /**
@@ -142,9 +142,9 @@ void ilsel_disable(unsigned int irq)
 
         addr = mk_ilsel_addr(irq);
 
-        tmp = ctrl_inw(addr);
+        tmp = __raw_readw(addr);
         tmp &= ~(0xf << mk_ilsel_shift(irq));
-        ctrl_outw(tmp, addr);
+        __raw_writew(tmp, addr);
 
         clear_bit(irq, &ilsel_level_map);
 }
diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c
index efe4cb9f8a77..e284592fd42a 100644
--- a/arch/sh/boards/mach-x3proto/setup.c
+++ b/arch/sh/boards/mach-x3proto/setup.c
@@ -149,7 +149,7 @@ static void __init x3proto_init_irq(void)
         plat_irq_setup_pins(IRQ_MODE_IRL3210);
 
         /* Set ICR0.LVLMODE */
-        ctrl_outl(ctrl_inl(0xfe410000) | (1 << 21), 0xfe410000);
+        __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
 }
 
 static struct sh_machine_vector mv_x3proto __initmv = {
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index cb8cf5572e79..1ce63624c9b9 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -21,12 +21,15 @@ CONFIG_ZERO_PAGE_OFFSET	?= 0x00001000
 CONFIG_ENTRY_OFFSET     ?= 0x00001000
 
 suffix-y := bin
-suffix-$(CONFIG_KERNEL_GZIP)  := gz
-suffix-$(CONFIG_KERNEL_BZIP2) := bz2
-suffix-$(CONFIG_KERNEL_LZMA)  := lzma
-
-targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz uImage.bz2 uImage.lzma uImage.bin
-extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma
+suffix-$(CONFIG_KERNEL_GZIP)    := gz
+suffix-$(CONFIG_KERNEL_BZIP2)   := bz2
+suffix-$(CONFIG_KERNEL_LZMA)    := lzma
+suffix-$(CONFIG_KERNEL_LZO)     := lzo
+
+targets := zImage vmlinux.srec romImage uImage uImage.srec uImage.gz \
+           uImage.bz2 uImage.lzma uImage.lzo uImage.bin
+extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma \
+           vmlinux.bin.lzo
 subdir- := compressed romimage
 
 $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
@@ -43,15 +46,8 @@ $(obj)/romImage: $(obj)/romimage/vmlinux FORCE
 $(obj)/romimage/vmlinux: $(obj)/zImage FORCE
         $(Q)$(MAKE) $(build)=$(obj)/romimage $@
 
-KERNEL_MEMORY := 0x00000000
-ifeq ($(CONFIG_PMB_FIXED),y)
-KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
+KERNEL_MEMORY   := $(shell /bin/bash -c 'printf "0x%08x" \
                      $$[$(CONFIG_MEMORY_START) & 0x1fffffff]')
-endif
-ifeq ($(CONFIG_29BIT),y)
-KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
-                     $$[$(CONFIG_MEMORY_START)]')
-endif
 
 KERNEL_LOAD     := $(shell /bin/bash -c 'printf "0x%08x" \
                      $$[$(CONFIG_PAGE_OFFSET)  + \
@@ -80,6 +76,9 @@ $(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
 $(obj)/vmlinux.bin.lzma: $(obj)/vmlinux.bin FORCE
         $(call if_changed,lzma)
 
+$(obj)/vmlinux.bin.lzo: $(obj)/vmlinux.bin FORCE
+        $(call if_changed,lzo)
+
 $(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
         $(call if_changed,uimage,bzip2)
 
@@ -89,6 +88,9 @@ $(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
 $(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
         $(call if_changed,uimage,lzma)
 
+$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
+        $(call if_changed,uimage,lzo)
+
 $(obj)/uImage.bin: $(obj)/vmlinux.bin
         $(call if_changed,uimage,none)
 
diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile
index 6182eca5180a..5d660b90943b 100644
--- a/arch/sh/boot/compressed/Makefile
+++ b/arch/sh/boot/compressed/Makefile
@@ -6,14 +6,11 @@
 
 targets         := vmlinux vmlinux.bin vmlinux.bin.gz \
                    vmlinux.bin.bz2 vmlinux.bin.lzma \
+                   vmlinux.bin.lzo \
                    head_$(BITS).o misc.o piggy.o
 
 OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc.o $(obj)/cache.o
 
-ifdef CONFIG_SH_STANDARD_BIOS
-OBJECTS += $(obj)/../../kernel/sh_bios.o
-endif
-
 #
 # IMAGE_OFFSET is the load offset of the compression loader
 #
@@ -47,6 +44,8 @@ $(obj)/vmlinux.bin.bz2: $(vmlinux.bin.all-y) FORCE
         $(call if_changed,bzip2)
 $(obj)/vmlinux.bin.lzma: $(vmlinux.bin.all-y) FORCE
         $(call if_changed,lzma)
+$(obj)/vmlinux.bin.lzo: $(vmlinux.bin.all-y) FORCE
+        $(call if_changed,lzo)
 
 OBJCOPYFLAGS += -R .empty_zero_page
 
diff --git a/arch/sh/boot/compressed/misc.c b/arch/sh/boot/compressed/misc.c
index b51b1fc4baae..27140a6b365d 100644
--- a/arch/sh/boot/compressed/misc.c
+++ b/arch/sh/boot/compressed/misc.c
@@ -14,7 +14,6 @@
 #include <asm/uaccess.h>
 #include <asm/addrspace.h>
 #include <asm/page.h>
-#include <asm/sh_bios.h>
 
 /*
  * gzip declarations
@@ -62,29 +61,15 @@ static unsigned long free_mem_end_ptr;
 #include "../../../../lib/decompress_unlzma.c"
 #endif
 
-#ifdef CONFIG_SH_STANDARD_BIOS
-size_t strlen(const char *s)
-{
-        int i = 0;
-
-        while (*s++)
-                i++;
-        return i;
-}
+#ifdef CONFIG_KERNEL_LZO
+#include "../../../../lib/decompress_unlzo.c"
+#endif
 
 int puts(const char *s)
 {
-        int len = strlen(s);
-        sh_bios_console_write(s, len);
-        return len;
-}
-#else
-int puts(const char *s)
-{
         /* This should be updated to use the sh-sci routines */
         return 0;
 }
-#endif
 
 void* memset(void* s, int c, size_t n)
 {
@@ -132,7 +117,7 @@ void decompress_kernel(void)
         output_addr = (CONFIG_MEMORY_START + 0x2000);
 #else
         output_addr = __pa((unsigned long)&_text+PAGE_SIZE);
-#ifdef CONFIG_29BIT
+#if defined(CONFIG_29BIT)
         output_addr |= P2SEG;
 #endif
 #endif
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index 50aa0c1f76ea..bcb31ae84a51 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -55,25 +55,22 @@ static struct irq_chip hd64461_irq_chip = {
 
 static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
-        unsigned short intv = ctrl_inw(HD64461_NIRR);
-        struct irq_desc *ext_desc;
+        unsigned short intv = __raw_readw(HD64461_NIRR);
         unsigned int ext_irq = HD64461_IRQBASE;
 
         intv &= (1 << HD64461_IRQ_NUM) - 1;
 
-        while (intv) {
-                if (intv & 1) {
-                        ext_desc = irq_desc + ext_irq;
-                        handle_level_irq(ext_irq, ext_desc);
-                }
-                intv >>= 1;
-                ext_irq++;
+        for (; intv; intv >>= 1, ext_irq++) {
+                if (!(intv & 1))
+                        continue;
+
+                generic_handle_irq(ext_irq);
         }
 }
 
 int __init setup_hd64461(void)
 {
-        int i;
+        int i, nid = cpu_to_node(boot_cpu_data);
 
         if (!MACH_HD64461)
                 return 0;
@@ -90,9 +87,26 @@ int __init setup_hd64461(void)
         __raw_writew(0xffff, HD64461_NIMR);
 
         /*  IRQ 80 -> 95 belongs to HD64461  */
-        for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++)
+        for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
+                unsigned int irq;
+
+                irq = create_irq_nr(i, nid);
+                if (unlikely(irq == 0)) {
+                        pr_err("%s: failed hooking irq %d for HD64461\n",
+                               __func__, i);
+                        return -EBUSY;
+                }
+
+                if (unlikely(irq != i)) {
+                        pr_err("%s: got irq %d but wanted %d, bailing.\n",
+                               __func__, irq, i);
+                        destroy_irq(irq);
+                        return -EINVAL;
+                }
+
                 set_irq_chip_and_handler(i, &hd64461_irq_chip,
                                          handle_level_irq);
+        }
 
         set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
         set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig
new file mode 100644
index 000000000000..9b331eab968e
--- /dev/null
+++ b/arch/sh/configs/sdk7786_defconfig
@@ -0,0 +1,1754 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.33-rc7
+# Tue Feb  9 15:27:06 2010
+#
+CONFIG_SUPERH=y
+CONFIG_SUPERH32=y
+# CONFIG_SUPERH64 is not set
+CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_IRQ_PER_CPU=y
+CONFIG_SPARSE_IRQ=y
+# CONFIG_GENERIC_GPIO is not set
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_SYS_SUPPORTS_NUMA=y
+CONFIG_SYS_SUPPORTS_PCI=y
+CONFIG_SYS_SUPPORTS_TMU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_ARCH_NO_VIRT_TO_BUS=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_DMA_COHERENT=y
+# CONFIG_DMA_NONCOHERENT is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_BZIP2=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+CONFIG_RCU_TRACE=y
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+CONFIG_TREE_RCU_TRACE=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+# CONFIG_CPUSETS is not set
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+# CONFIG_CGROUP_MEM_RES_CTLR_SWAP is not set
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+CONFIG_EVENT_PROFILE=y
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+# CONFIG_DEBUG_CFQ_IOSCHED is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System type
+#
+CONFIG_CPU_SH4=y
+CONFIG_CPU_SH4A=y
+CONFIG_CPU_SHX3=y
+# CONFIG_CPU_SUBTYPE_SH7619 is not set
+# CONFIG_CPU_SUBTYPE_SH7201 is not set
+# CONFIG_CPU_SUBTYPE_SH7203 is not set
+# CONFIG_CPU_SUBTYPE_SH7206 is not set
+# CONFIG_CPU_SUBTYPE_SH7263 is not set
+# CONFIG_CPU_SUBTYPE_MXG is not set
+# CONFIG_CPU_SUBTYPE_SH7705 is not set
+# CONFIG_CPU_SUBTYPE_SH7706 is not set
+# CONFIG_CPU_SUBTYPE_SH7707 is not set
+# CONFIG_CPU_SUBTYPE_SH7708 is not set
+# CONFIG_CPU_SUBTYPE_SH7709 is not set
+# CONFIG_CPU_SUBTYPE_SH7710 is not set
+# CONFIG_CPU_SUBTYPE_SH7712 is not set
+# CONFIG_CPU_SUBTYPE_SH7720 is not set
+# CONFIG_CPU_SUBTYPE_SH7721 is not set
+# CONFIG_CPU_SUBTYPE_SH7750 is not set
+# CONFIG_CPU_SUBTYPE_SH7091 is not set
+# CONFIG_CPU_SUBTYPE_SH7750R is not set
+# CONFIG_CPU_SUBTYPE_SH7750S is not set
+# CONFIG_CPU_SUBTYPE_SH7751 is not set
+# CONFIG_CPU_SUBTYPE_SH7751R is not set
+# CONFIG_CPU_SUBTYPE_SH7760 is not set
+# CONFIG_CPU_SUBTYPE_SH4_202 is not set
+# CONFIG_CPU_SUBTYPE_SH7723 is not set
+# CONFIG_CPU_SUBTYPE_SH7724 is not set
+# CONFIG_CPU_SUBTYPE_SH7757 is not set
+# CONFIG_CPU_SUBTYPE_SH7763 is not set
+# CONFIG_CPU_SUBTYPE_SH7770 is not set
+# CONFIG_CPU_SUBTYPE_SH7780 is not set
+# CONFIG_CPU_SUBTYPE_SH7785 is not set
+CONFIG_CPU_SUBTYPE_SH7786=y
+# CONFIG_CPU_SUBTYPE_SHX3 is not set
+# CONFIG_CPU_SUBTYPE_SH7343 is not set
+# CONFIG_CPU_SUBTYPE_SH7722 is not set
+# CONFIG_CPU_SUBTYPE_SH7366 is not set
+
+#
+# Memory management options
+#
+CONFIG_QUICKLIST=y
+CONFIG_MMU=y
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_MEMORY_START=0x60000000
+CONFIG_MEMORY_SIZE=0x20000000
+# CONFIG_29BIT is not set
+CONFIG_32BIT=y
+CONFIG_PMB=y
+# CONFIG_PMB_LEGACY is not set
+CONFIG_X2TLB=y
+CONFIG_VSYSCALL=y
+# CONFIG_NUMA is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_MAX_ACTIVE_REGIONS=1
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_IOREMAP_FIXED=y
+CONFIG_PAGE_SIZE_4KB=y
+# CONFIG_PAGE_SIZE_8KB is not set
+# CONFIG_PAGE_SIZE_16KB is not set
+# CONFIG_PAGE_SIZE_64KB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_64K is not set
+# CONFIG_HUGETLB_PAGE_SIZE_256K is not set
+CONFIG_HUGETLB_PAGE_SIZE_1MB=y
+# CONFIG_HUGETLB_PAGE_SIZE_4MB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_64MB is not set
+# CONFIG_HUGETLB_PAGE_SIZE_512MB is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+# CONFIG_FLATMEM_MANUAL is not set
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTPLUG_SPARSE=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_NR_QUICK=1
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+
+#
+# Cache configuration
+#
+CONFIG_CACHE_WRITEBACK=y
+# CONFIG_CACHE_WRITETHROUGH is not set
+# CONFIG_CACHE_OFF is not set
+
+#
+# Processor features
+#
+CONFIG_CPU_LITTLE_ENDIAN=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_SH_FPU=y
+CONFIG_SH_STORE_QUEUES=y
+CONFIG_CPU_HAS_INTEVT=y
+CONFIG_CPU_HAS_SR_RB=y
+CONFIG_CPU_HAS_PTEAEX=y
+CONFIG_CPU_HAS_FPU=y
+
+#
+# Board support
+#
+CONFIG_SH_SDK7786=y
+# CONFIG_SH_URQUELL is not set
+
+#
+# Timer and clock configuration
+#
+CONFIG_SH_TIMER_TMU=y
+CONFIG_SH_CLK_CPG=y
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_SH_CPU_FREQ=y
+
+#
+# DMA support
+#
+# CONFIG_SH_DMA is not set
+
+#
+# Companion Chips
+#
+
+#
+# Additional SuperH Device Drivers
+#
+CONFIG_HEARTBEAT=y
+# CONFIG_PUSH_SWITCH is not set
+
+#
+# Kernel features
+#
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=250
+CONFIG_SCHED_HRTICK=y
+CONFIG_KEXEC=y
+# CONFIG_CRASH_DUMP is not set
+CONFIG_SECCOMP=y
+# CONFIG_SMP is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_GUSA=y
+
+#
+# Boot options
+#
+CONFIG_ZERO_PAGE_OFFSET=0x00001000
+CONFIG_BOOT_LINK_OFFSET=0x00800000
+CONFIG_ENTRY_OFFSET=0x00001000
+CONFIG_CMDLINE_OVERWRITE=y
+# CONFIG_CMDLINE_EXTEND is not set
+CONFIG_CMDLINE="console=ttySC1,115200 earlyprintk=sh-sci.1,115200 root=/dev/sda1 nmi_debug=state,debounce rootdelay=10"
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIE_ECRC is not set
+CONFIG_PCIEAER_INJECT=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEBUG=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_LEGACY is not set
+CONFIG_PCI_DEBUG=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options (EXPERIMENTAL)
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_VERBOSE=y
+# CONFIG_HIBERNATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_FW_LOADER is not set
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_SIL24=y
+CONFIG_ATA_SFF=y
+# CONFIG_SATA_SVW is not set
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SX4 is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+CONFIG_PATA_PLATFORM=y
+# CONFIG_PATA_SCH is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# The newer stack is recommended.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_STNIC is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+CONFIG_SMC91X=y
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+CONFIG_SMSC911X=y
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_ATL2 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_SH_KEYSC is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SH_MOBILE is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_SH_MSIOF is not set
+# CONFIG_SPI_SH_SCI is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_SH_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SH_MOBILE_SDHI is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_88PM8607 is not set
+# CONFIG_AB4500_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=m
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+CONFIG_USB_GADGET_M66592=y
+CONFIG_USB_M66592=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+CONFIG_RTC_DRV_MAX6900=y
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SH=y
+# CONFIG_RTC_DRV_GENERIC is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+CONFIG_UIO=m
+# CONFIG_UIO_CIF is not set
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
+# CONFIG_UIO_SMX is not set
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_SERCOS3 is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_FTRACE_SYSCALLS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+CONFIG_KSYM_TRACER=y
+# CONFIG_PROFILE_KSYM_TRACER is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_SH_STANDARD_BIOS is not set
+# CONFIG_STACK_DEBUG is not set
+CONFIG_DEBUG_STACK_USAGE=y
+# CONFIG_4KSTACKS is not set
+CONFIG_DUMP_CODE=y
+CONFIG_DWARF_UNWINDER=y
+# CONFIG_SH_NO_BSS_INIT is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c
index 391cbe1c2956..3cee58e7f1e5 100644
--- a/arch/sh/drivers/dma/dma-pvr2.c
+++ b/arch/sh/drivers/dma/dma-pvr2.c
@@ -40,10 +40,10 @@ static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
 
 static int pvr2_request_dma(struct dma_channel *chan)
 {
-        if (ctrl_inl(PVR2_DMA_MODE) != 0)
+        if (__raw_readl(PVR2_DMA_MODE) != 0)
                 return -EBUSY;
 
-        ctrl_outl(0, PVR2_DMA_LMMODE0);
+        __raw_writel(0, PVR2_DMA_LMMODE0);
 
         return 0;
 }
@@ -60,9 +60,9 @@ static int pvr2_xfer_dma(struct dma_channel *chan)
 
         xfer_complete = 0;
 
-        ctrl_outl(chan->dar, PVR2_DMA_ADDR);
-        ctrl_outl(chan->count, PVR2_DMA_COUNT);
-        ctrl_outl(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
+        __raw_writel(chan->dar, PVR2_DMA_ADDR);
+        __raw_writel(chan->count, PVR2_DMA_COUNT);
+        __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
 
         return 0;
 }
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 37fb5b8bbc3f..827208781ed5 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -52,11 +52,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
  *
  * iterations to complete the transfer.
  */
+static unsigned int ts_shift[] = TS_SHIFT;
 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
 {
-        u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
+        int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
+                ((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
 
-        return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
+        return ts_shift[cnt];
 }
 
 /*
@@ -70,13 +73,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
         struct dma_channel *chan = dev_id;
         u32 chcr;
 
-        chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
 
         if (!(chcr & CHCR_TE))
                 return IRQ_NONE;
 
         chcr &= ~(CHCR_IE | CHCR_DE);
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 
         wake_up(&chan->wait_queue);
 
@@ -115,7 +118,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
                 chan->flags &= ~DMA_TEI_CAPABLE;
         }
 
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 
         chan->flags |= DMA_CONFIGURED;
         return 0;
@@ -126,13 +129,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
         int irq;
         u32 chcr;
 
-        chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
         chcr |= CHCR_DE;
 
         if (chan->flags & DMA_TEI_CAPABLE)
                 chcr |= CHCR_IE;
 
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 
         if (chan->flags & DMA_TEI_CAPABLE) {
                 irq = get_dmte_irq(chan->chan);
@@ -150,9 +153,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
                 disable_irq(irq);
         }
 
-        chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
+        chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
-        ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
+        __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
 }
 
 static int sh_dmac_xfer_dma(struct dma_channel *chan)
@@ -183,12 +186,12 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
          */
         if (chan->sar || (mach_is_dreamcast() &&
                           chan->chan == PVR2_CASCADE_CHAN))
-                ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
+                __raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
         if (chan->dar || (mach_is_dreamcast() &&
                           chan->chan == PVR2_CASCADE_CHAN))
-                ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
+                __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
 
-        ctrl_outl(chan->count >> calc_xmit_shift(chan),
+        __raw_writel(chan->count >> calc_xmit_shift(chan),
                 (dma_base_addr[chan->chan] + TCR));
 
         sh_dmac_enable_dma(chan);
@@ -198,10 +201,10 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
 
 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 {
-        if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
+        if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
                 return 0;
 
-        return ctrl_inl(dma_base_addr[chan->chan] + TCR)
+        return __raw_readl(dma_base_addr[chan->chan] + TCR)
                  << calc_xmit_shift(chan);
 }
 
diff --git a/arch/sh/drivers/dma/dmabrg.c b/arch/sh/drivers/dma/dmabrg.c
index 5e22689c2fcf..72622e307613 100644
--- a/arch/sh/drivers/dma/dmabrg.c
+++ b/arch/sh/drivers/dma/dmabrg.c
@@ -86,8 +86,8 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
         unsigned long dcr;
         unsigned int i;
 
-        dcr = ctrl_inl(DMABRGCR);
-        ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
+        dcr = __raw_readl(DMABRGCR);
+        __raw_writel(dcr & ~0x00ff0003, DMABRGCR);      /* ack all */
         dcr &= dcr >> 8;        /* ignore masked */
 
         /* USB stuff, get it out of the way first */
@@ -109,17 +109,17 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
 static void dmabrg_disable_irq(unsigned int dmairq)
 {
         unsigned long dcr;
-        dcr = ctrl_inl(DMABRGCR);
+        dcr = __raw_readl(DMABRGCR);
         dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
-        ctrl_outl(dcr, DMABRGCR);
+        __raw_writel(dcr, DMABRGCR);
 }
 
 static void dmabrg_enable_irq(unsigned int dmairq)
 {
         unsigned long dcr;
-        dcr = ctrl_inl(DMABRGCR);
+        dcr = __raw_readl(DMABRGCR);
         dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
-        ctrl_outl(dcr, DMABRGCR);
+        __raw_writel(dcr, DMABRGCR);
 }
 
 int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*),
@@ -165,13 +165,13 @@ static int __init dmabrg_init(void)
                 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n");
 #endif
 
-        ctrl_outl(0, DMABRGCR);
-        ctrl_outl(0, DMACHCR0);
-        ctrl_outl(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
+        __raw_writel(0, DMABRGCR);
+        __raw_writel(0, DMACHCR0);
+        __raw_writel(0x94000000, DMARSRA);      /* enable DMABRG in DMAC 0 */
 
         /* enable DMABRG mode, enable the DMAC */
-        or = ctrl_inl(DMAOR);
-        ctrl_outl(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
+        or = __raw_readl(DMAOR);
+        __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
 
         ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED,
                         "DMABRG USB address error", NULL);
diff --git a/arch/sh/drivers/heartbeat.c b/arch/sh/drivers/heartbeat.c
index a9339a6174fc..2acbc793032d 100644
--- a/arch/sh/drivers/heartbeat.c
+++ b/arch/sh/drivers/heartbeat.c
@@ -1,7 +1,7 @@
 /*
  * Generic heartbeat driver for regular LED banks
  *
- * Copyright (C) 2007  Paul Mundt
+ * Copyright (C) 2007 - 2010  Paul Mundt
  *
  * Most SH reference boards include a number of individual LEDs that can
  * be independently controlled (either via a pre-defined hardware
@@ -27,7 +27,7 @@
 #include <asm/heartbeat.h>
 
 #define DRV_NAME "heartbeat"
-#define DRV_VERSION "0.1.1"
+#define DRV_VERSION "0.1.2"
 
 static unsigned char default_bit_pos[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
 
@@ -98,7 +98,7 @@ static int heartbeat_drv_probe(struct platform_device *pdev)
                         return -ENOMEM;
         }
 
-        hd->base = ioremap_nocache(res->start, res->end - res->start + 1);
+        hd->base = ioremap_nocache(res->start, resource_size(res));
         if (unlikely(!hd->base)) {
                 dev_err(&pdev->dev, "ioremap failed\n");
 
@@ -117,8 +117,20 @@ static int heartbeat_drv_probe(struct platform_device *pdev)
         for (i = 0; i < hd->nr_bits; i++)
                 hd->mask |= (1 << hd->bit_pos[i]);
 
-        if (!hd->regsize)
-                hd->regsize = 8;        /* default access size */
+        if (!hd->regsize) {
+                switch (res->flags & IORESOURCE_MEM_TYPE_MASK) {
+                case IORESOURCE_MEM_32BIT:
+                        hd->regsize = 32;
+                        break;
+                case IORESOURCE_MEM_16BIT:
+                        hd->regsize = 16;
+                        break;
+                case IORESOURCE_MEM_8BIT:
+                default:
+                        hd->regsize = 8;
+                        break;
+                }
+        }
 
         setup_timer(&hd->timer, heartbeat_timer, (unsigned long)hd);
         platform_set_drvdata(pdev, hd);
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 08af1f459756..4a59e6890876 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -1,14 +1,14 @@
 #
 # Makefile for the PCI specific kernel interface routines under Linux.
 #
-obj-y                                   += pci.o
+obj-y                                   += common.o pci.o
 
 obj-$(CONFIG_CPU_SUBTYPE_SH7751)        += pci-sh7751.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7751R)       += pci-sh7751.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7763)        += pci-sh7780.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)        += pci-sh7780.o ops-sh4.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)        += pci-sh7780.o ops-sh4.o
-obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += ops-sh7786.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7786)        += pcie-sh7786.o ops-sh7786.o
 obj-$(CONFIG_CPU_SH5)                   += pci-sh5.o ops-sh5.o
 
 obj-$(CONFIG_SH_DREAMCAST)              += ops-dreamcast.o fixups-dreamcast.o \
@@ -25,4 +25,3 @@ obj-$(CONFIG_SH_TITAN)			+= fixups-titan.o
 obj-$(CONFIG_SH_LANDISK)                += fixups-landisk.o
 obj-$(CONFIG_SH_LBOX_RE2)               += fixups-rts7751r2d.o
 obj-$(CONFIG_SH_CAYMAN)                 += fixups-cayman.o
-obj-$(CONFIG_SH_URQUELL)                += pcie-sh7786.o
diff --git a/arch/sh/drivers/pci/common.c b/arch/sh/drivers/pci/common.c
new file mode 100644
index 000000000000..dbf138199871
--- /dev/null
+++ b/arch/sh/drivers/pci/common.c
@@ -0,0 +1,162 @@
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+#include <linux/kernel.h>
+
+/*
+ * These functions are used early on before PCI scanning is done
+ * and all of the pci_dev and pci_bus structures have been created.
+ */
+static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
+        int top_bus, int busnr, int devfn)
+{
+        static struct pci_dev dev;
+        static struct pci_bus bus;
+
+        dev.bus = &bus;
+        dev.sysdata = hose;
+        dev.devfn = devfn;
+        bus.number = busnr;
+        bus.sysdata = hose;
+        bus.ops = hose->pci_ops;
+
+        if(busnr != top_bus)
+                /* Fake a parent bus structure. */
+                bus.parent = &bus;
+        else
+                bus.parent = NULL;
+
+        return &dev;
+}
+
+#define EARLY_PCI_OP(rw, size, type)                                    \
+int __init early_##rw##_config_##size(struct pci_channel *hose,         \
+        int top_bus, int bus, int devfn, int offset, type value)        \
+{                                                                       \
+        return pci_##rw##_config_##size(                                \
+                fake_pci_dev(hose, top_bus, bus, devfn),                \
+                offset, value);                                         \
+}
+
+EARLY_PCI_OP(read, byte, u8 *)
+EARLY_PCI_OP(read, word, u16 *)
+EARLY_PCI_OP(read, dword, u32 *)
+EARLY_PCI_OP(write, byte, u8)
+EARLY_PCI_OP(write, word, u16)
+EARLY_PCI_OP(write, dword, u32)
+
+int __init pci_is_66mhz_capable(struct pci_channel *hose,
+                                int top_bus, int current_bus)
+{
+        u32 pci_devfn;
+        unsigned short vid;
+        int cap66 = -1;
+        u16 stat;
+
+        printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
+
+        for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
+                if (PCI_FUNC(pci_devfn))
+                        continue;
+                if (early_read_config_word(hose, top_bus, current_bus,
+                                           pci_devfn, PCI_VENDOR_ID, &vid) !=
+                    PCIBIOS_SUCCESSFUL)
+                        continue;
+                if (vid == 0xffff)
+                        continue;
+
+                /* check 66MHz capability */
+                if (cap66 < 0)
+                        cap66 = 1;
+                if (cap66) {
+                        early_read_config_word(hose, top_bus, current_bus,
+                                               pci_devfn, PCI_STATUS, &stat);
+                        if (!(stat & PCI_STATUS_66MHZ)) {
+                                printk(KERN_DEBUG
+                                       "PCI: %02x:%02x not 66MHz capable.\n",
+                                       current_bus, pci_devfn);
+                                cap66 = 0;
+                                break;
+                        }
+                }
+        }
+
+        return cap66 > 0;
+}
+
+static void pcibios_enable_err(unsigned long __data)
+{
+        struct pci_channel *hose = (struct pci_channel *)__data;
+
+        del_timer(&hose->err_timer);
+        printk(KERN_DEBUG "PCI: re-enabling error IRQ.\n");
+        enable_irq(hose->err_irq);
+}
+
+static void pcibios_enable_serr(unsigned long __data)
+{
+        struct pci_channel *hose = (struct pci_channel *)__data;
+
+        del_timer(&hose->serr_timer);
+        printk(KERN_DEBUG "PCI: re-enabling system error IRQ.\n");
+        enable_irq(hose->serr_irq);
+}
+
+void pcibios_enable_timers(struct pci_channel *hose)
+{
+        if (hose->err_irq) {
+                init_timer(&hose->err_timer);
+                hose->err_timer.data = (unsigned long)hose;
+                hose->err_timer.function = pcibios_enable_err;
+        }
+
+        if (hose->serr_irq) {
+                init_timer(&hose->serr_timer);
+                hose->serr_timer.data = (unsigned long)hose;
+                hose->serr_timer.function = pcibios_enable_serr;
+        }
+}
+
+/*
+ * A simple handler for the regular PCI status errors, called from IRQ
+ * context.
+ */
+unsigned int pcibios_handle_status_errors(unsigned long addr,
+                                          unsigned int status,
+                                          struct pci_channel *hose)
+{
+        unsigned int cmd = 0;
+
+        if (status & PCI_STATUS_REC_MASTER_ABORT) {
+                printk(KERN_DEBUG "PCI: master abort, pc=0x%08lx\n", addr);
+                cmd |= PCI_STATUS_REC_MASTER_ABORT;
+        }
+
+        if (status & PCI_STATUS_REC_TARGET_ABORT) {
+                printk(KERN_DEBUG "PCI: target abort: ");
+                pcibios_report_status(PCI_STATUS_REC_TARGET_ABORT |
+                                      PCI_STATUS_SIG_TARGET_ABORT |
+                                      PCI_STATUS_REC_MASTER_ABORT, 1);
+                printk("\n");
+
+                cmd |= PCI_STATUS_REC_TARGET_ABORT;
+        }
+
+        if (status & (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY)) {
+                printk(KERN_DEBUG "PCI: parity error detected: ");
+                pcibios_report_status(PCI_STATUS_PARITY |
+                                      PCI_STATUS_DETECTED_PARITY, 1);
+                printk("\n");
+
+                cmd |= PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY;
+
+                /* Now back off of the IRQ for awhile */
+                if (hose->err_irq) {
+                        disable_irq_nosync(hose->err_irq);
+                        hose->err_timer.expires = jiffies + HZ;
+                        add_timer(&hose->err_timer);
+                }
+        }
+
+        return cmd;
+}
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index ed7f489936f1..942ef4f155f5 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -39,7 +39,7 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
                 /*
                  * We also assume that dev->devfn == 0
                  */
-                dev->resource[1].start  = p->io_resource->start  + 0x100;
+                dev->resource[1].start  = p->resources[0].start  + 0x100;
                 dev->resource[1].end    = dev->resource[1].start + 0x200 - 1;
 
                 /*
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
index 15ca65cb667e..08b2d8658a00 100644
--- a/arch/sh/drivers/pci/fixups-r7780rp.c
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -22,15 +22,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 {
         return irq_tab[slot];
 }
-
-int pci_fixup_pcic(struct pci_channel *chan)
-{
-        pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
-        pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
-        pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
-        pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
-        pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
-        pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
-
-        return 0;
-}
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 7898f14d6641..e248516118a9 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -43,7 +43,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
 {
         unsigned long bcr1, mcr;
 
-        bcr1 = ctrl_inl(SH7751_BCR1);
+        bcr1 = __raw_readl(SH7751_BCR1);
         bcr1 |= 0x40080000;     /* Enable Bit 19 BREQEN, set PCIC to slave */
         pci_write_reg(chan, bcr1, SH4_PCIBCR1);
 
@@ -54,7 +54,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
         pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
         pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
 
-        mcr = ctrl_inl(SH7751_MCR);
+        mcr = __raw_readl(SH7751_MCR);
         mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
         pci_write_reg(chan, mcr, SH4_PCIMCR);
 
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
index 250b0edd7365..0930f988ac29 100644
--- a/arch/sh/drivers/pci/fixups-sdk7780.c
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -31,22 +31,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
 {
        return sdk7780_irq_tab[pin-1][slot];
 }
-int pci_fixup_pcic(struct pci_channel *chan)
-{
-        /* Enable all interrupts, so we know what to fix */
-        pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
-
-        /* Set up standard PCI config registers */
-        pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0);       /* PCI */
-        pci_write_reg(chan, 0x08000000, SH4_PCILAR0);   /* SHwy */
-        pci_write_reg(chan, 0x07F00001, SH4_PCILSR0);   /* size 128M w/ MBAR */
-
-        pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
-        pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
-        pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
-
-        pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
-        pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
-
-        return 0;
-}
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
index 475fa9f0fe2c..a4c7d3a4efca 100644
--- a/arch/sh/drivers/pci/fixups-se7751.c
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -97,12 +97,12 @@ int pci_fixup_pcic(struct pci_channel *chan)
         * meaning all calls go straight through... use BUG_ON to
         * catch erroneous assumption.
         */
-        BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);
+        BUG_ON(chan->resources[1].start != SH7751_PCI_MEMORY_BASE);
 
-        PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);
+        PCIC_WRITE(SH7751_PCIMBR, chan->resources[1].start);
 
         /* Set IOBR for window containing area specified in pci.h */
-        PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));
+        PCIC_WRITE(SH7751_PCIIOBR, (chan->resources[0].start & SH7751_PCIIOBR_MASK));
 
         /* All done, may as well say so... */
         printk("SH7751 PCI: Finished initialization of the PCI controller\n");
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 78bebebdc99c..0b81999fb88b 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -16,7 +16,7 @@
  * Direct access to PCI hardware...
  */
 #define CONFIG_CMD(bus, devfn, where) \
-        (P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3))
+        (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
 
 static DEFINE_SPINLOCK(sh4_pci_lock);
 
@@ -102,34 +102,6 @@ struct pci_ops sh4_pci_ops = {
         .write          = sh4_pci_write,
 };
 
-/*
- * Not really related to pci_ops, but it's common and not worth shoving
- * somewhere else for now..
- */
-int __init sh4_pci_check_direct(struct pci_channel *chan)
-{
-        /*
-         * Check if configuration works.
-         */
-        unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR);
-
-        pci_write_reg(chan, P1SEG, SH4_PCIPAR);
-
-        if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) {
-                pci_write_reg(chan, tmp, SH4_PCIPAR);
-                printk(KERN_INFO "PCI: Using configuration type 1\n");
-                request_region(chan->reg_base + SH4_PCIPAR, 8,
-                               "PCI conf1");
-                return 0;
-        }
-
-        pci_write_reg(chan, tmp, SH4_PCIPAR);
-
-        printk(KERN_ERR "PCI: %s failed\n", __func__);
-
-        return -EINVAL;
-}
-
 int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
 {
         /* Nothing to do. */
diff --git a/arch/sh/drivers/pci/pci-dreamcast.c b/arch/sh/drivers/pci/pci-dreamcast.c
index 210f9d4af141..633694193af8 100644
--- a/arch/sh/drivers/pci/pci-dreamcast.c
+++ b/arch/sh/drivers/pci/pci-dreamcast.c
@@ -25,25 +25,25 @@
 #include <asm/irq.h>
 #include <mach/pci.h>
 
-static struct resource gapspci_io_resource = {
-        .name   = "GAPSPCI IO",
-        .start  = GAPSPCI_BBA_CONFIG,
-        .end    = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
-        .flags  = IORESOURCE_IO,
-};
-
-static struct resource gapspci_mem_resource = {
-        .name   = "GAPSPCI mem",
-        .start  = GAPSPCI_DMA_BASE,
-        .end    = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
-        .flags  = IORESOURCE_MEM,
+static struct resource gapspci_resources[] = {
+        {
+                .name   = "GAPSPCI IO",
+                .start  = GAPSPCI_BBA_CONFIG,
+                .end    = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
+                .flags  = IORESOURCE_IO,
+        },  {
+                .name   = "GAPSPCI mem",
+                .start  = GAPSPCI_DMA_BASE,
+                .end    = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
 };
 
 static struct pci_channel dreamcast_pci_controller = {
         .pci_ops        = &gapspci_pci_ops,
-        .io_resource    = &gapspci_io_resource,
+        .resources      = gapspci_resources,
+        .nr_resources   = ARRAY_SIZE(gapspci_resources),
         .io_offset      = 0x00000000,
-        .mem_resource   = &gapspci_mem_resource,
         .mem_offset     = 0x00000000,
 };
 
@@ -95,8 +95,6 @@ static int __init gapspci_init(void)
         outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
         outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
 
-        register_pci_controller(&dreamcast_pci_controller);
-
-        return 0;
+        return register_pci_controller(&dreamcast_pci_controller);
 }
 arch_initcall(gapspci_init);
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 3d5296cde622..cbf763b3015e 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -49,6 +49,17 @@
   #define SH4_PCIINT_MWPD         0x00000002    /* Master Write PERR Detect */
   #define SH4_PCIINT_MRPD         0x00000001    /* Master Read PERR Detect */
 #define SH4_PCIINTM             0x118           /* PCI Interrupt Mask */
+  #define SH4_PCIINTM_TTADIM      BIT(14)       /* Target-target abort interrupt */
+  #define SH4_PCIINTM_TMTOIM      BIT(9)        /* Target retry timeout */
+  #define SH4_PCIINTM_MDEIM       BIT(8)        /* Master function disable error */
+  #define SH4_PCIINTM_APEDIM      BIT(7)        /* Address parity error detection */
+  #define SH4_PCIINTM_SDIM        BIT(6)        /* SERR detection */
+  #define SH4_PCIINTM_DPEITWM     BIT(5)        /* Data parity error for target write */
+  #define SH4_PCIINTM_PEDITRM     BIT(4)        /* PERR detection for target read */
+  #define SH4_PCIINTM_TADIMM      BIT(3)        /* Target abort for master */
+  #define SH4_PCIINTM_MADIMM      BIT(2)        /* Master abort for master */
+  #define SH4_PCIINTM_MWPDIM      BIT(1)        /* Master write data parity error */
+  #define SH4_PCIINTM_MRDPEIM     BIT(0)        /* Master read data parity error */
 #define SH4_PCIALR              0x11C           /* Error Address Register */
 #define SH4_PCICLR              0x120           /* Error Command/Data */
   #define SH4_PCICLR_MPIO         0x80000000
@@ -61,7 +72,7 @@
 #define SH4_PCIAINT             0x130           /* Arbiter Interrupt Register */
   #define SH4_PCIAINT_MBKN        0x00002000    /* Master Broken Interrupt */
   #define SH4_PCIAINT_TBTO        0x00001000    /* Target Bus Time Out */
-  #define SH4_PCIAINT_MBTO        0x00001000    /* Master Bus Time Out */
+  #define SH4_PCIAINT_MBTO        0x00000800    /* Master Bus Time Out */
   #define SH4_PCIAINT_TABT        0x00000008    /* Target Abort */
   #define SH4_PCIAINT_MABT        0x00000004    /* Master Abort */
   #define SH4_PCIAINT_RDPE        0x00000002    /* Read Data Parity Error */
@@ -151,7 +162,6 @@
 
 /* arch/sh/kernel/drivers/pci/ops-sh4.c */
 extern struct pci_ops sh4_pci_ops;
-int sh4_pci_check_direct(struct pci_channel *chan);
 int pci_fixup_pcic(struct pci_channel *chan);
 
 struct sh4_pci_address_space {
@@ -167,13 +177,13 @@ struct sh4_pci_address_map {
 static inline void pci_write_reg(struct pci_channel *chan,
                                  unsigned long val, unsigned long reg)
 {
-        ctrl_outl(val, chan->reg_base + reg);
+        __raw_writel(val, chan->reg_base + reg);
 }
 
 static inline unsigned long pci_read_reg(struct pci_channel *chan,
                                          unsigned long reg)
 {
-        return ctrl_inl(chan->reg_base + reg);
+        return __raw_readl(chan->reg_base + reg);
 }
 
 #endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index 873ed2b44055..0bf296c78795 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -89,14 +89,13 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
         return IRQ_NONE;
 }
 
-static struct resource sh5_io_resource = { /* place holder */ };
-static struct resource sh5_mem_resource = { /* place holder */ };
+static struct resource sh5_pci_resources[2];
 
 static struct pci_channel sh5pci_controller = {
         .pci_ops                = &sh5_pci_ops,
-        .mem_resource           = &sh5_mem_resource,
+        .resources              = sh5_pci_resources,
+        .nr_resources           = ARRAY_SIZE(sh5_pci_resources),
         .mem_offset             = 0x00000000,
-        .io_resource            = &sh5_io_resource,
         .io_offset              = 0x00000000,
 };
 
@@ -210,14 +209,12 @@ static int __init sh5pci_init(void)
         SH5PCI_WRITE(AINTM, ~0);
         SH5PCI_WRITE(PINTM, ~0);
 
-        sh5_io_resource.start = PCI_IO_AREA;
-        sh5_io_resource.end = PCI_IO_AREA + 0x10000;
+        sh5_pci_resources[0].start = PCI_IO_AREA;
+        sh5_pci_resources[0].end = PCI_IO_AREA + 0x10000;
 
-        sh5_mem_resource.start = memStart;
-        sh5_mem_resource.end = memStart + memSize;
+        sh5_pci_resources[1].start = memStart;
+        sh5_pci_resources[1].end = memStart + memSize;
 
-        register_pci_controller(&sh5pci_controller);
-
-        return 0;
+        return register_pci_controller(&sh5pci_controller);
 }
 arch_initcall(sh5pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index f277628221f3..3f01decb4307 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -86,14 +86,14 @@ extern unsigned long pcicr_virt;
 /* #define PCISH5_VCR_REG(x)                ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
 
 /* Write I/O functions */
-#define SH5PCI_WRITE(reg,val)        ctrl_outl((u32)(val),PCISH5_ICR_REG(reg))
-#define SH5PCI_WRITE_SHORT(reg,val)  ctrl_outw((u16)(val),PCISH5_ICR_REG(reg))
-#define SH5PCI_WRITE_BYTE(reg,val)   ctrl_outb((u8)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE(reg,val)        __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_SHORT(reg,val)  __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
+#define SH5PCI_WRITE_BYTE(reg,val)   __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
 
 /* Read I/O functions */
-#define SH5PCI_READ(reg)             ctrl_inl(PCISH5_ICR_REG(reg))
-#define SH5PCI_READ_SHORT(reg)       ctrl_inw(PCISH5_ICR_REG(reg))
-#define SH5PCI_READ_BYTE(reg)        ctrl_inb(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ(reg)             __raw_readl(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_SHORT(reg)       __raw_readw(PCISH5_ICR_REG(reg))
+#define SH5PCI_READ_BYTE(reg)        __raw_readb(PCISH5_ICR_REG(reg))
 
 /* Set PCI config bits */
 #define SET_CONFIG_BITS(bus,devfn,where)  ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 70c1999a0ec4..17811e5d287b 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -44,25 +44,25 @@ static int __init __area_sdram_check(struct pci_channel *chan,
         return 1;
 }
 
-static struct resource sh7751_io_resource = {
-        .name   = "SH7751_IO",
-        .start  = SH7751_PCI_IO_BASE,
-        .end    = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
-        .flags  = IORESOURCE_IO
-};
-
-static struct resource sh7751_mem_resource = {
-        .name   = "SH7751_mem",
-        .start  = SH7751_PCI_MEMORY_BASE,
-        .end    = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM
+static struct resource sh7751_pci_resources[] = {
+        {
+                .name   = "SH7751_IO",
+                .start  = SH7751_PCI_IO_BASE,
+                .end    = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
+                .flags  = IORESOURCE_IO
+        }, {
+                .name   = "SH7751_mem",
+                .start  = SH7751_PCI_MEMORY_BASE,
+                .end    = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
+                .flags  = IORESOURCE_MEM
+        },
 };
 
 static struct pci_channel sh7751_pci_controller = {
         .pci_ops        = &sh4_pci_ops,
-        .mem_resource   = &sh7751_mem_resource,
+        .resources      = sh7751_pci_resources,
+        .nr_resources   = ARRAY_SIZE(sh7751_pci_resources),
         .mem_offset     = 0x00000000,
-        .io_resource    = &sh7751_io_resource,
         .io_offset      = 0x00000000,
         .io_map_base    = SH7751_PCI_IO_BASE,
 };
@@ -79,7 +79,6 @@ static int __init sh7751_pci_init(void)
         struct pci_channel *chan = &sh7751_pci_controller;
         unsigned int id;
         u32 word, reg;
-        int ret;
 
         printk(KERN_NOTICE "PCI: Starting intialization.\n");
 
@@ -93,13 +92,10 @@ static int __init sh7751_pci_init(void)
                 return -ENODEV;
         }
 
-        if ((ret = sh4_pci_check_direct(chan)) != 0)
-                return ret;
-
         /* Set the BCR's to enable PCI access */
-        reg = ctrl_inl(SH7751_BCR1);
+        reg = __raw_readl(SH7751_BCR1);
         reg |= 0x80000;
-        ctrl_outl(reg, SH7751_BCR1);
+        __raw_writel(reg, SH7751_BCR1);
 
         /* Turn the clocks back on (not done in reset)*/
         pci_write_reg(chan, 0, SH4_PCICLKR);
@@ -132,13 +128,13 @@ static int __init sh7751_pci_init(void)
         /* Set the local 16MB PCI memory space window to
          * the lowest PCI mapped address
          */
-        word = chan->mem_resource->start & SH4_PCIMBR_MASK;
+        word = chan->resources[1].start & SH4_PCIMBR_MASK;
         pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
         pci_write_reg(chan, word , SH4_PCIMBR);
 
         /* Make sure the MSB's of IO window are set to access PCI space
          * correctly */
-        word = chan->io_resource->start & SH4_PCIIOBR_MASK;
+        word = chan->resources[0].start & SH4_PCIIOBR_MASK;
         pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
         pci_write_reg(chan, word, SH4_PCIIOBR);
 
@@ -159,13 +155,13 @@ static int __init sh7751_pci_init(void)
                 return -1;
 
         /* configure the wait control registers */
-        word = ctrl_inl(SH7751_WCR1);
+        word = __raw_readl(SH7751_WCR1);
         pci_write_reg(chan, word, SH4_PCIWCR1);
-        word = ctrl_inl(SH7751_WCR2);
+        word = __raw_readl(SH7751_WCR2);
         pci_write_reg(chan, word, SH4_PCIWCR2);
-        word = ctrl_inl(SH7751_WCR3);
+        word = __raw_readl(SH7751_WCR3);
         pci_write_reg(chan, word, SH4_PCIWCR3);
-        word = ctrl_inl(SH7751_MCR);
+        word = __raw_readl(SH7751_MCR);
         pci_write_reg(chan, word, SH4_PCIMCR);
 
         /* NOTE: I'm ignoring the PCI error IRQs for now..
@@ -180,8 +176,6 @@ static int __init sh7751_pci_init(void)
         word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
         pci_write_reg(chan, word, SH4_PCICR);
 
-        register_pci_controller(chan);
-
-        return 0;
+        return register_pci_controller(chan);
 }
 arch_initcall(sh7751_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index 323b92d565fe..ffdcbf10b95e 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -1,7 +1,7 @@
 /*
  * Low-Level PCI Support for the SH7780
  *
- *  Copyright (C) 2005 - 2009  Paul Mundt
+ *  Copyright (C) 2005 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -11,52 +11,240 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/timer.h>
+#include <linux/irq.h>
 #include <linux/errno.h>
 #include <linux/delay.h>
+#include <linux/log2.h>
 #include "pci-sh4.h"
+#include <asm/mmu.h>
+#include <asm/sizes.h>
 
-static struct resource sh7785_io_resource = {
-        .name   = "SH7785_IO",
-        .start  = SH7780_PCI_IO_BASE,
-        .end    = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
-        .flags  = IORESOURCE_IO
-};
-
-static struct resource sh7785_mem_resource = {
-        .name   = "SH7785_mem",
-        .start  = SH7780_PCI_MEMORY_BASE,
-        .end    = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
-        .flags  = IORESOURCE_MEM
+static struct resource sh7785_pci_resources[] = {
+        {
+                .name   = "PCI IO",
+                .start  = 0x1000,
+                .end    = SZ_4M - 1,
+                .flags  = IORESOURCE_IO,
+        }, {
+                .name   = "PCI MEM 0",
+                .start  = 0xfd000000,
+                .end    = 0xfd000000 + SZ_16M - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "PCI MEM 1",
+                .start  = 0x10000000,
+                .end    = 0x10000000 + SZ_64M - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                /*
+                 * 32-bit only resources must be last.
+                 */
+                .name   = "PCI MEM 2",
+                .start  = 0xc0000000,
+                .end    = 0xc0000000 + SZ_512M - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+        },
 };
 
 static struct pci_channel sh7780_pci_controller = {
         .pci_ops        = &sh4_pci_ops,
-        .mem_resource   = &sh7785_mem_resource,
-        .mem_offset     = 0x00000000,
-        .io_resource    = &sh7785_io_resource,
-        .io_offset      = 0x00000000,
-        .io_map_base    = SH7780_PCI_IO_BASE,
+        .resources      = sh7785_pci_resources,
+        .nr_resources   = ARRAY_SIZE(sh7785_pci_resources),
+        .io_offset      = 0,
+        .mem_offset     = 0,
+        .io_map_base    = 0xfe200000,
+        .serr_irq       = evt2irq(0xa00),
+        .err_irq        = evt2irq(0xaa0),
 };
 
-static struct sh4_pci_address_map sh7780_pci_map = {
-        .window0        = {
-#if defined(CONFIG_32BIT)
-                .base   = SH7780_32BIT_DDR_BASE_ADDR,
-                .size   = 0x40000000,
-#else
-                .base   = SH7780_CS0_BASE_ADDR,
-                .size   = 0x20000000,
-#endif
-        },
+struct pci_errors {
+        unsigned int    mask;
+        const char      *str;
+} pci_arbiter_errors[] = {
+        { SH4_PCIAINT_MBKN,     "master broken" },
+        { SH4_PCIAINT_TBTO,     "target bus time out" },
+        { SH4_PCIAINT_MBTO,     "master bus time out" },
+        { SH4_PCIAINT_TABT,     "target abort" },
+        { SH4_PCIAINT_MABT,     "master abort" },
+        { SH4_PCIAINT_RDPE,     "read data parity error" },
+        { SH4_PCIAINT_WDPE,     "write data parity error" },
+}, pci_interrupt_errors[] = {
+        { SH4_PCIINT_MLCK,      "master lock error" },
+        { SH4_PCIINT_TABT,      "target-target abort" },
+        { SH4_PCIINT_TRET,      "target retry time out" },
+        { SH4_PCIINT_MFDE,      "master function disable erorr" },
+        { SH4_PCIINT_PRTY,      "address parity error" },
+        { SH4_PCIINT_SERR,      "SERR" },
+        { SH4_PCIINT_TWDP,      "data parity error for target write" },
+        { SH4_PCIINT_TRDP,      "PERR detected for target read" },
+        { SH4_PCIINT_MTABT,     "target abort for master" },
+        { SH4_PCIINT_MMABT,     "master abort for master" },
+        { SH4_PCIINT_MWPD,      "master write data parity error" },
+        { SH4_PCIINT_MRPD,      "master read data parity error" },
 };
 
+static irqreturn_t sh7780_pci_err_irq(int irq, void *dev_id)
+{
+        struct pci_channel *hose = dev_id;
+        unsigned long addr;
+        unsigned int status;
+        unsigned int cmd;
+        int i;
+
+        addr = __raw_readl(hose->reg_base + SH4_PCIALR);
+
+        /*
+         * Handle status errors.
+         */
+        status = __raw_readw(hose->reg_base + PCI_STATUS);
+        if (status & (PCI_STATUS_PARITY |
+                      PCI_STATUS_DETECTED_PARITY |
+                      PCI_STATUS_SIG_TARGET_ABORT |
+                      PCI_STATUS_REC_TARGET_ABORT |
+                      PCI_STATUS_REC_MASTER_ABORT)) {
+                cmd = pcibios_handle_status_errors(addr, status, hose);
+                if (likely(cmd))
+                        __raw_writew(cmd, hose->reg_base + PCI_STATUS);
+        }
+
+        /*
+         * Handle arbiter errors.
+         */
+        status = __raw_readl(hose->reg_base + SH4_PCIAINT);
+        for (i = cmd = 0; i < ARRAY_SIZE(pci_arbiter_errors); i++) {
+                if (status & pci_arbiter_errors[i].mask) {
+                        printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
+                               pci_arbiter_errors[i].str, addr);
+                        cmd |= pci_arbiter_errors[i].mask;
+                }
+        }
+        __raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
+
+        /*
+         * Handle the remaining PCI errors.
+         */
+        status = __raw_readl(hose->reg_base + SH4_PCIINT);
+        for (i = cmd = 0; i < ARRAY_SIZE(pci_interrupt_errors); i++) {
+                if (status & pci_interrupt_errors[i].mask) {
+                        printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
+                               pci_interrupt_errors[i].str, addr);
+                        cmd |= pci_interrupt_errors[i].mask;
+                }
+        }
+        __raw_writel(cmd, hose->reg_base + SH4_PCIINT);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t sh7780_pci_serr_irq(int irq, void *dev_id)
+{
+        struct pci_channel *hose = dev_id;
+
+        printk(KERN_DEBUG "PCI: system error received: ");
+        pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
+        printk("\n");
+
+        /* Deassert SERR */
+        __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
+
+        /* Back off the IRQ for awhile */
+        disable_irq_nosync(irq);
+        hose->serr_timer.expires = jiffies + HZ;
+        add_timer(&hose->serr_timer);
+
+        return IRQ_HANDLED;
+}
+
+static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
+{
+        int ret;
+
+        /* Clear out PCI arbiter IRQs */
+        __raw_writel(0, hose->reg_base + SH4_PCIAINT);
+
+        /* Clear all error conditions */
+        __raw_writew(PCI_STATUS_DETECTED_PARITY  | \
+                     PCI_STATUS_SIG_SYSTEM_ERROR | \
+                     PCI_STATUS_REC_MASTER_ABORT | \
+                     PCI_STATUS_REC_TARGET_ABORT | \
+                     PCI_STATUS_SIG_TARGET_ABORT | \
+                     PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
+
+        ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, IRQF_DISABLED,
+                          "PCI SERR interrupt", hose);
+        if (unlikely(ret)) {
+                printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n");
+                return ret;
+        }
+
+        /*
+         * The PCI ERR IRQ needs to be IRQF_SHARED since all of the power
+         * down IRQ vectors are routed through the ERR IRQ vector. We
+         * only request_irq() once as there is only a single masking
+         * source for multiple events.
+         */
+        ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
+                          "PCI ERR interrupt", hose);
+        if (unlikely(ret)) {
+                free_irq(hose->serr_irq, hose);
+                return ret;
+        }
+
+        /* Unmask all of the arbiter IRQs. */
+        __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
+                     SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
+                     SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
+
+        /* Unmask all of the PCI IRQs */
+        __raw_writel(SH4_PCIINTM_TTADIM  | SH4_PCIINTM_TMTOIM  | \
+                     SH4_PCIINTM_MDEIM   | SH4_PCIINTM_APEDIM  | \
+                     SH4_PCIINTM_SDIM    | SH4_PCIINTM_DPEITWM | \
+                     SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM  | \
+                     SH4_PCIINTM_MADIMM  | SH4_PCIINTM_MWPDIM  | \
+                     SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
+
+        return ret;
+}
+
+static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
+{
+        free_irq(hose->err_irq, hose);
+        free_irq(hose->serr_irq, hose);
+}
+
+static void __init sh7780_pci66_init(struct pci_channel *hose)
+{
+        unsigned int tmp;
+
+        if (!pci_is_66mhz_capable(hose, 0, 0))
+                return;
+
+        /* Enable register access */
+        tmp = __raw_readl(hose->reg_base + SH4_PCICR);
+        tmp |= SH4_PCICR_PREFIX;
+        __raw_writel(tmp, hose->reg_base + SH4_PCICR);
+
+        /* Enable 66MHz operation */
+        tmp = __raw_readw(hose->reg_base + PCI_STATUS);
+        tmp |= PCI_STATUS_66MHZ;
+        __raw_writew(tmp, hose->reg_base + PCI_STATUS);
+
+        /* Done */
+        tmp = __raw_readl(hose->reg_base + SH4_PCICR);
+        tmp |= SH4_PCICR_PREFIX | SH4_PCICR_CFIN;
+        __raw_writel(tmp, hose->reg_base + SH4_PCICR);
+}
+
 static int __init sh7780_pci_init(void)
 {
         struct pci_channel *chan = &sh7780_pci_controller;
+        phys_addr_t memphys;
+        size_t memsize;
         unsigned int id;
-        const char *type = NULL;
-        int ret;
-        u32 word;
+        const char *type;
+        int ret, i;
 
         printk(KERN_NOTICE "PCI: Starting intialization.\n");
 
@@ -65,17 +253,28 @@ static int __init sh7780_pci_init(void)
         /* Enable CPU access to the PCIC registers. */
         __raw_writel(PCIECR_ENBL, PCIECR);
 
-        id = __raw_readw(chan->reg_base + SH7780_PCIVID);
-        if (id != SH7780_VENDOR_ID) {
+        /* Reset */
+        __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST,
+                     chan->reg_base + SH4_PCICR);
+
+        /*
+         * Wait for it to come back up. The spec says to allow for up to
+         * 1 second after toggling the reset pin, but in practice 100ms
+         * is more than enough.
+         */
+        mdelay(100);
+
+        id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);
+        if (id != PCI_VENDOR_ID_RENESAS) {
                 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
                 return -ENODEV;
         }
 
-        id = __raw_readw(chan->reg_base + SH7780_PCIDID);
-        type = (id == SH7763_DEVICE_ID) ? "SH7763" :
-               (id == SH7780_DEVICE_ID) ? "SH7780" :
-               (id == SH7781_DEVICE_ID) ? "SH7781" :
-               (id == SH7785_DEVICE_ID) ? "SH7785" :
+        id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);
+        type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" :
+               (id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" :
+               (id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" :
+               (id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" :
                                           NULL;
         if (unlikely(!type)) {
                 printk(KERN_ERR "PCI: Found an unsupported Renesas host "
@@ -85,62 +284,119 @@ static int __init sh7780_pci_init(void)
 
         printk(KERN_NOTICE "PCI: Found a Renesas %s host "
                "controller, revision %d.\n", type,
-               __raw_readb(chan->reg_base + SH7780_PCIRID));
+               __raw_readb(chan->reg_base + PCI_REVISION_ID));
 
-        if ((ret = sh4_pci_check_direct(chan)) != 0)
+        /*
+         * Now throw it in to register initialization mode and
+         * start the real work.
+         */
+        __raw_writel(SH4_PCICR_PREFIX, chan->reg_base + SH4_PCICR);
+
+        memphys = __pa(memory_start);
+        memsize = roundup_pow_of_two(memory_end - memory_start);
+
+        /*
+         * If there's more than 512MB of memory, we need to roll over to
+         * LAR1/LSR1.
+         */
+        if (memsize > SZ_512M) {
+                __raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);
+                __raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1,
+                             chan->reg_base + SH4_PCILSR1);
+                memsize = SZ_512M;
+        } else {
+                /*
+                 * Otherwise just zero it out and disable it.
+                 */
+                __raw_writel(0, chan->reg_base + SH4_PCILAR1);
+                __raw_writel(0, chan->reg_base + SH4_PCILSR1);
+        }
+
+        /*
+         * LAR0/LSR0 covers up to the first 512MB, which is enough to
+         * cover all of lowmem on most platforms.
+         */
+        __raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
+        __raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
+                     chan->reg_base + SH4_PCILSR0);
+
+        /*
+         * Hook up the ERR and SERR IRQs.
+         */
+        ret = sh7780_pci_setup_irqs(chan);
+        if (unlikely(ret))
                 return ret;
 
         /*
-         * Set the class and sub-class codes.
+         * Disable the cache snoop controller for non-coherent DMA.
          */
-        __raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
-                     chan->reg_base + SH7780_PCIBCC);
-        __raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
-                     chan->reg_base + SH7780_PCISUB);
+        __raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
+        __raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
+        __raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
+        __raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
 
         /*
-         * Set IO and Mem windows to local address
-         * Make PCI and local address the same for easy 1 to 1 mapping
+         * Setup the memory BARs
          */
-        pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
-        /* Set the values on window 0 PCI config registers */
-        pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
-        pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
+        for (i = 1; i < chan->nr_resources; i++) {
+                struct resource *res = chan->resources + i;
+                resource_size_t size;
 
-        pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
+                if (unlikely(res->flags & IORESOURCE_IO))
+                        continue;
 
-        /* Set up standard PCI config registers */
-        __raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
-        __raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
-        __raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
-        __raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
+                /*
+                 * Make sure we're in the right physical addressing mode
+                 * for dealing with the resource.
+                 */
+                if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) {
+                        chan->nr_resources--;
+                        continue;
+                }
 
-        __raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
+                size = resource_size(res);
+
+                /*
+                 * The MBMR mask is calculated in units of 256kB, which
+                 * keeps things pretty simple.
+                 */
+                __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
+                             chan->reg_base + SH7780_PCIMBMR(i - 1));
+                __raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));
+        }
 
-        /* Apply any last-minute PCIC fixups */
-        pci_fixup_pcic(chan);
+        /*
+         * And I/O.
+         */
+        __raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
+        __raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
+        __raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
 
-        pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
-        pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
+        __raw_writew(PCI_COMMAND_SERR   | PCI_COMMAND_WAIT   | \
+                     PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
+                     PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
 
-#ifdef CONFIG_32BIT
-        pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
-        pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
-#endif
+        /*
+         * Initialization mode complete, release the control register and
+         * enable round robin mode to stop device overruns/starvation.
+         */
+        __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO,
+                     chan->reg_base + SH4_PCICR);
 
-        /* Set IOBR for windows containing area specified in pci.h */
-        pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
-                      SH7780_PCIIOBR);
-        pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
-                      SH7780_PCIIOBMR);
+        ret = register_pci_controller(chan);
+        if (unlikely(ret))
+                goto err;
 
-        /* SH7780 init done, set central function init complete */
-        /* use round robin mode to stop a device starving/overruning */
-        word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
-        pci_write_reg(chan, word, SH4_PCICR);
+        sh7780_pci66_init(chan);
 
-        register_pci_controller(chan);
+        printk(KERN_NOTICE "PCI: Running at %dMHz.\n",
+               (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ?
+               66 : 33);
 
         return 0;
+
+err:
+        sh7780_pci_teardown_irqs(chan);
+        return ret;
 }
 arch_initcall(sh7780_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 4a52478c97cf..205dcbefe275 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -12,12 +12,11 @@
 #ifndef _PCI_SH7780_H_
 #define _PCI_SH7780_H_
 
-/* Platform Specific Values */
-#define SH7780_VENDOR_ID        0x1912
-#define SH7781_DEVICE_ID        0x0001
-#define SH7780_DEVICE_ID        0x0002
-#define SH7763_DEVICE_ID        0x0004
-#define SH7785_DEVICE_ID        0x0007
+#define PCI_VENDOR_ID_RENESAS           0x1912
+#define PCI_DEVICE_ID_RENESAS_SH7781    0x0001
+#define PCI_DEVICE_ID_RENESAS_SH7780    0x0002
+#define PCI_DEVICE_ID_RENESAS_SH7763    0x0004
+#define PCI_DEVICE_ID_RENESAS_SH7785    0x0007
 
 /* SH7780 Control Registers */
 #define PCIECR                  0xFE000008
@@ -27,44 +26,9 @@
 #define SH7780_PCI_CONFIG_BASE  0xFD000000      /* Config space base addr */
 #define SH7780_PCI_CONFIG_SIZE  0x01000000      /* Config space size */
 
-#define SH7780_PCI_MEMORY_BASE  0xFD000000      /* Memory space base addr */
-#define SH7780_PCI_MEM_SIZE     0x01000000      /* Size of Memory window */
-
-#define SH7780_PCI_IO_BASE      0xFE200000      /* IO space base address */
-#define SH7780_PCI_IO_SIZE      0x00400000      /* Size of IO window */
-
 #define SH7780_PCIREG_BASE      0xFE040000      /* PCI regs base address */
 
 /* SH7780 PCI Config Registers */
-#define SH7780_PCIVID           0x000           /* Vendor ID */
-#define SH7780_PCIDID           0x002           /* Device ID */
-#define SH7780_PCICMD           0x004           /* Command */
-#define SH7780_PCISTATUS        0x006           /* Status */
-#define SH7780_PCIRID           0x008           /* Revision ID */
-#define SH7780_PCIPIF           0x009           /* Program Interface */
-#define SH7780_PCISUB           0x00a           /* Sub class code */
-#define SH7780_PCIBCC           0x00b           /* Base class code */
-#define SH7780_PCICLS           0x00c           /* Cache line size */
-#define SH7780_PCILTM           0x00d           /* latency timer */
-#define SH7780_PCIHDR           0x00e           /* Header type */
-#define SH7780_PCIBIST          0x00f           /* BIST */
-#define SH7780_PCIIBAR          0x010           /* IO Base address */
-#define SH7780_PCIMBAR0         0x014           /* Memory base address0 */
-#define SH7780_PCIMBAR1         0x018           /* Memory base address1 */
-#define SH7780_PCISVID          0x02c           /* Sub system vendor ID */
-#define SH7780_PCISID           0x02e           /* Sub system ID */
-#define SH7780_PCICP            0x034
-#define SH7780_PCIINTLINE       0x03c           /* Interrupt line */
-#define SH7780_PCIINTPIN        0x03d           /* Interrupt pin */
-#define SH7780_PCIMINGNT        0x03e           /* Minumum grand */
-#define SH7780_PCIMAXLAT        0x03f           /* Maxmum latency */
-#define SH7780_PCICID           0x040
-#define SH7780_PCINIP           0x041
-#define SH7780_PCIPMC           0x042
-#define SH7780_PCIPMCSR         0x044
-#define SH7780_PCIPMCSR_BSE     0x046
-#define SH7780_PCICDD           0x047
-
 #define SH7780_PCIIR            0x114           /* PCI Interrupt Register */
 #define SH7780_PCIIMR           0x118           /* PCI Interrupt Mask Register */
 #define SH7780_PCIAIR           0x11C           /* Error Address Register */
@@ -76,10 +40,8 @@
 #define SH7780_PCIPINT          0x1CC           /* Power Mgmnt Int. Register */
 #define SH7780_PCIPINTM         0x1D0           /* Power Mgmnt Mask Register */
 
-#define SH7780_PCIMBR0          0x1E0
-#define SH7780_PCIMBMR0         0x1E4
-#define SH7780_PCIMBR2          0x1F0
-#define SH7780_PCIMBMR2         0x1F4
+#define SH7780_PCIMBR(x)        (0x1E0 + ((x) * 8))
+#define SH7780_PCIMBMR(x)       (0x1E4 + ((x) * 8))
 #define SH7780_PCIIOBR          0x1F8
 #define SH7780_PCIIOBMR         0x1FC
 #define SH7780_PCICSCR0         0x210           /* Cache Snoop1 Cnt. Register */
@@ -87,16 +49,4 @@
 #define SH7780_PCICSAR0         0x218   /* Cache Snoop1 Addr. Register */
 #define SH7780_PCICSAR1         0x21C   /* Cache Snoop2 Addr. Register */
 
-/* General Memory Config Addresses */
-#define SH7780_CS0_BASE_ADDR    0x0
-#define SH7780_MEM_REGION_SIZE  0x04000000
-#define SH7780_CS1_BASE_ADDR    (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
-#define SH7780_CS2_BASE_ADDR    (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
-#define SH7780_CS3_BASE_ADDR    (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
-#define SH7780_CS4_BASE_ADDR    (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
-#define SH7780_CS5_BASE_ADDR    (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
-#define SH7780_CS6_BASE_ADDR    (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
-
-#define SH7780_32BIT_DDR_BASE_ADDR      0x40000000
-
 #endif /* _PCI_SH7780_H_ */
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index c481df639022..953af139e230 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -33,15 +33,22 @@ static int pci_initialized;
 static void __devinit pcibios_scanbus(struct pci_channel *hose)
 {
         static int next_busno;
+        static int need_domain_info;
         struct pci_bus *bus;
 
         bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
+        hose->bus = bus;
+
+        need_domain_info = need_domain_info || hose->index;
+        hose->need_domain_info = need_domain_info;
         if (bus) {
                 next_busno = bus->subordinate + 1;
                 /* Don't allow 8-bit bus number overflow inside the hose -
                    reserve some space for bridges. */
-                if (next_busno > 224)
+                if (next_busno > 224) {
                         next_busno = 0;
+                        need_domain_info = 1;
+                }
 
                 pci_bus_size_bridges(bus);
                 pci_bus_assign_resources(bus);
@@ -51,10 +58,21 @@ static void __devinit pcibios_scanbus(struct pci_channel *hose)
 
 static DEFINE_MUTEX(pci_scan_mutex);
 
-void __devinit register_pci_controller(struct pci_channel *hose)
+int __devinit register_pci_controller(struct pci_channel *hose)
 {
-        request_resource(&iomem_resource, hose->mem_resource);
-        request_resource(&ioport_resource, hose->io_resource);
+        int i;
+
+        for (i = 0; i < hose->nr_resources; i++) {
+                struct resource *res = hose->resources + i;
+
+                if (res->flags & IORESOURCE_IO) {
+                        if (request_resource(&ioport_resource, res) < 0)
+                                goto out;
+                } else {
+                        if (request_resource(&iomem_resource, res) < 0)
+                                goto out;
+                }
+        }
 
         *hose_tail = hose;
         hose_tail = &hose->next;
@@ -68,6 +86,11 @@ void __devinit register_pci_controller(struct pci_channel *hose)
         }
 
         /*
+         * Setup the ERR/PERR and SERR timers, if available.
+         */
+        pcibios_enable_timers(hose);
+
+        /*
          * Scan the bus if it is register after the PCI subsystem
          * initialization.
          */
@@ -76,6 +99,15 @@ void __devinit register_pci_controller(struct pci_channel *hose)
                 pcibios_scanbus(hose);
                 mutex_unlock(&pci_scan_mutex);
         }
+
+        return 0;
+
+out:
+        for (--i; i >= 0; i--)
+                release_resource(&hose->resources[i]);
+
+        printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
+        return -1;
 }
 
 static int __init pcibios_init(void)
@@ -127,11 +159,13 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
 {
         struct pci_dev *dev = bus->self;
         struct list_head *ln;
-        struct pci_channel *chan = bus->sysdata;
+        struct pci_channel *hose = bus->sysdata;
 
         if (!dev) {
-                bus->resource[0] = chan->io_resource;
-                bus->resource[1] = chan->mem_resource;
+                int i;
+
+                for (i = 0; i < hose->nr_resources; i++)
+                        bus->resource[i] = hose->resources + i;
         }
 
         for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
@@ -148,34 +182,29 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus)
  * addresses to be allocated in the 0x000-0x0ff region
  * modulo 0x400.
  */
-void pcibios_align_resource(void *data, struct resource *res,
-                            resource_size_t size, resource_size_t align)
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
-        struct pci_channel *chan = dev->sysdata;
+        struct pci_channel *hose = dev->sysdata;
         resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO) {
-                if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
-                        start = PCIBIOS_MIN_IO + chan->io_resource->start;
+                if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
+                        start = PCIBIOS_MIN_IO + hose->resources[0].start;
 
                 /*
                  * Put everything into 0x00-0xff region modulo 0x400.
                  */
-                if (start & 0x300) {
+                if (start & 0x300)
                         start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
-        } else if (res->flags & IORESOURCE_MEM) {
-                if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
-                        start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
         }
 
-        res->start = start;
+        return start;
 }
 
 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
-                         struct resource *res)
+                             struct resource *res)
 {
         struct pci_channel *hose = dev->sysdata;
         unsigned long offset = 0;
@@ -189,9 +218,8 @@ void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
         region->end = res->end - offset;
 }
 
-void __devinit
-pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                        struct pci_bus_region *region)
+void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
+                             struct pci_bus_region *region)
 {
         struct pci_channel *hose = dev->sysdata;
         unsigned long offset = 0;
@@ -274,6 +302,86 @@ char * __devinit pcibios_setup(char *str)
         return str;
 }
 
+static void __init
+pcibios_bus_report_status_early(struct pci_channel *hose,
+                                int top_bus, int current_bus,
+                                unsigned int status_mask, int warn)
+{
+        unsigned int pci_devfn;
+        u16 status;
+        int ret;
+
+        for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
+                if (PCI_FUNC(pci_devfn))
+                        continue;
+                ret = early_read_config_word(hose, top_bus, current_bus,
+                                             pci_devfn, PCI_STATUS, &status);
+                if (ret != PCIBIOS_SUCCESSFUL)
+                        continue;
+                if (status == 0xffff)
+                        continue;
+
+                early_write_config_word(hose, top_bus, current_bus,
+                                        pci_devfn, PCI_STATUS,
+                                        status & status_mask);
+                if (warn)
+                        printk("(%02x:%02x: %04X) ", current_bus,
+                               pci_devfn, status);
+        }
+}
+
+/*
+ * We can't use pci_find_device() here since we are
+ * called from interrupt context.
+ */
+static void __init_refok
+pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
+                          int warn)
+{
+        struct pci_dev *dev;
+
+        list_for_each_entry(dev, &bus->devices, bus_list) {
+                u16 status;
+
+                /*
+                 * ignore host bridge - we handle
+                 * that separately
+                 */
+                if (dev->bus->number == 0 && dev->devfn == 0)
+                        continue;
+
+                pci_read_config_word(dev, PCI_STATUS, &status);
+                if (status == 0xffff)
+                        continue;
+
+                if ((status & status_mask) == 0)
+                        continue;
+
+                /* clear the status errors */
+                pci_write_config_word(dev, PCI_STATUS, status & status_mask);
+
+                if (warn)
+                        printk("(%s: %04X) ", pci_name(dev), status);
+        }
+
+        list_for_each_entry(dev, &bus->devices, bus_list)
+                if (dev->subordinate)
+                        pcibios_bus_report_status(dev->subordinate, status_mask, warn);
+}
+
+void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
+{
+        struct pci_channel *hose;
+
+        for (hose = hose_head; hose; hose = hose->next) {
+                if (unlikely(!hose->bus))
+                        pcibios_bus_report_status_early(hose, hose_head->index,
+                                        hose->index, status_mask, warn);
+                else
+                        pcibios_bus_report_status(hose->bus, status_mask, warn);
+        }
+}
+
 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
                         enum pci_mmap_state mmap_state, int write_combine)
 {
@@ -302,9 +410,15 @@ static void __iomem *ioport_map_pci(struct pci_dev *dev,
 {
         struct pci_channel *chan = dev->sysdata;
 
-        if (!chan->io_map_base)
+        if (unlikely(!chan->io_map_base)) {
                 chan->io_map_base = generic_io_base;
 
+                if (pci_domains_supported)
+                        panic("To avoid data corruption io_map_base MUST be "
+                              "set with multiple PCI domains.");
+        }
+
+
         return (void __iomem *)(chan->io_map_base + port);
 }
 
@@ -321,20 +435,9 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
 
         if (flags & IORESOURCE_IO)
                 return ioport_map_pci(dev, start, len);
-
-        /*
-         * Presently the IORESOURCE_MEM case is a bit special, most
-         * SH7751 style PCI controllers have PCI memory at a fixed
-         * location in the address space where no remapping is desired.
-         * With the IORESOURCE_MEM case more care has to be taken
-         * to inhibit page table mapping for legacy cores, but this is
-         * punted off to __ioremap().
-         *                                      -- PFM.
-         */
         if (flags & IORESOURCE_MEM) {
                 if (flags & IORESOURCE_CACHEABLE)
                         return ioremap(start, len);
-
                 return ioremap_nocache(start, len);
         }
 
diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c
index ac37ee879bab..ae91a2dd9183 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.c
+++ b/arch/sh/drivers/pci/pcie-sh7786.c
@@ -1,7 +1,7 @@
 /*
  * Low-Level PCI Express Support for the SH7786
  *
- *  Copyright (C) 2009  Paul Mundt
+ *  Copyright (C) 2009 - 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -30,60 +30,84 @@ static struct sh7786_pcie_hwops {
         int (*port_init_hw)(struct sh7786_pcie_port *port);
 } *sh7786_pcie_hwops;
 
-static struct resource sh7786_pci_32bit_mem_resources[] = {
+static struct resource sh7786_pci0_resources[] = {
         {
-                .name   = "pci0_mem",
-                .start  = SH4A_PCIMEM_BASEA,
-                .end    = SH4A_PCIMEM_BASEA + SZ_64M - 1,
-                .flags  = IORESOURCE_MEM,
+                .name   = "PCIe0 IO",
+                .start  = 0xfd000000,
+                .end    = 0xfd000000 + SZ_8M - 1,
+                .flags  = IORESOURCE_IO,
         }, {
-                .name   = "pci1_mem",
-                .start  = SH4A_PCIMEM_BASEA1,
-                .end    = SH4A_PCIMEM_BASEA1 + SZ_64M - 1,
-                .flags  = IORESOURCE_MEM,
+                .name   = "PCIe0 MEM 0",
+                .start  = 0xc0000000,
+                .end    = 0xc0000000 + SZ_512M - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
         }, {
-                .name   = "pci2_mem",
-                .start  = SH4A_PCIMEM_BASEA2,
-                .end    = SH4A_PCIMEM_BASEA2 + SZ_64M - 1,
+                .name   = "PCIe0 MEM 1",
+                .start  = 0x10000000,
+                .end    = 0x10000000 + SZ_64M - 1,
                 .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "PCIe0 MEM 2",
+                .start  = 0xfe100000,
+                .end    = 0xfe100000 + SZ_1M - 1,
         },
 };
 
-static struct resource sh7786_pci_29bit_mem_resource = {
-        .start  = SH4A_PCIMEM_BASE,
-        .end    = SH4A_PCIMEM_BASE + SZ_64M - 1,
-        .flags  = IORESOURCE_MEM,
+static struct resource sh7786_pci1_resources[] = {
+        {
+                .name   = "PCIe1 IO",
+                .start  = 0xfd800000,
+                .end    = 0xfd800000 + SZ_8M - 1,
+                .flags  = IORESOURCE_IO,
+        }, {
+                .name   = "PCIe1 MEM 0",
+                .start  = 0xa0000000,
+                .end    = 0xa0000000 + SZ_512M - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+        }, {
+                .name   = "PCIe1 MEM 1",
+                .start  = 0x30000000,
+                .end    = 0x30000000 + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+        }, {
+                .name   = "PCIe1 MEM 2",
+                .start  = 0xfe300000,
+                .end    = 0xfe300000 + SZ_1M - 1,
+        },
 };
 
-static struct resource sh7786_pci_io_resources[] = {
+static struct resource sh7786_pci2_resources[] = {
         {
-                .name   = "pci0_io",
-                .start  = SH4A_PCIIO_BASE,
-                .end    = SH4A_PCIIO_BASE + SZ_8M - 1,
-                .flags  = IORESOURCE_IO,
+                .name   = "PCIe2 IO",
+                .start  = 0xfc800000,
+                .end    = 0xfc800000 + SZ_4M - 1,
         }, {
-                .name   = "pci1_io",
-                .start  = SH4A_PCIIO_BASE1,
-                .end    = SH4A_PCIIO_BASE1 + SZ_8M - 1,
-                .flags  = IORESOURCE_IO,
+                .name   = "PCIe2 MEM 0",
+                .start  = 0x80000000,
+                .end    = 0x80000000 + SZ_512M - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
         }, {
-                .name   = "pci2_io",
-                .start  = SH4A_PCIIO_BASE2,
-                .end    = SH4A_PCIIO_BASE2 + SZ_4M - 1,
-                .flags  = IORESOURCE_IO,
+                .name   = "PCIe2 MEM 1",
+                .start  = 0x20000000,
+                .end    = 0x20000000 + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
+        }, {
+                .name   = "PCIe2 MEM 2",
+                .start  = 0xfcd00000,
+                .end    = 0xfcd00000 + SZ_1M - 1,
         },
 };
 
 extern struct pci_ops sh7786_pci_ops;
 
-#define DEFINE_CONTROLLER(start, idx)                           \
-{                                                               \
-        .pci_ops        = &sh7786_pci_ops,                      \
-        .reg_base       = start,                                \
-        /* mem_resource filled in at probe time */              \
-        .mem_offset     = 0,                                    \
-        .io_resource    = &sh7786_pci_io_resources[idx],        \
-        .io_offset      = 0,                                    \
+#define DEFINE_CONTROLLER(start, idx)                                   \
+{                                                                       \
+        .pci_ops        = &sh7786_pci_ops,                              \
+        .resources      = sh7786_pci##idx##_resources,                  \
+        .nr_resources   = ARRAY_SIZE(sh7786_pci##idx##_resources),      \
+        .reg_base       = start,                                        \
+        .mem_offset     = 0,                                            \
+        .io_offset      = 0,                                            \
 }
 
 static struct pci_channel sh7786_pci_channels[] = {
@@ -180,7 +204,9 @@ static int pcie_init(struct sh7786_pcie_port *port)
 {
         struct pci_channel *chan = port->hose;
         unsigned int data;
-        int ret;
+        phys_addr_t memphys;
+        size_t memsize;
+        int ret, i;
 
         /* Begin initialization */
         pci_write_reg(chan, 0, SH4A_PCIETCTLR);
@@ -203,15 +229,24 @@ static int pcie_init(struct sh7786_pcie_port *port)
         data |= PCI_CAP_ID_EXP;
         pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
 
-        /* Enable x4 link width and extended sync. */
+        /* Enable data link layer active state reporting */
+        pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
+
+        /* Enable extended sync and ASPM L0s support */
         data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
-        data &= ~(PCI_EXP_LNKSTA_NLW << 16);
-        data |= (1 << 22) | PCI_EXP_LNKCTL_ES;
+        data &= ~PCI_EXP_LNKCTL_ASPMC;
+        data |= PCI_EXP_LNKCTL_ES | 1;
         pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
 
+        /* Write out the physical slot number */
+        data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
+        data &= ~PCI_EXP_SLTCAP_PSN;
+        data |= (port->index + 1) << 19;
+        pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
+
         /* Set the completion timer timeout to the maximum 32ms. */
         data = pci_read_reg(chan, SH4A_PCIETLCTLR);
-        data &= ~0xffff;
+        data &= ~0x3f00;
         data |= 0x32 << 8;
         pci_write_reg(chan, data, SH4A_PCIETLCTLR);
 
@@ -224,6 +259,33 @@ static int pcie_init(struct sh7786_pcie_port *port)
         data |= (0xff << 16);
         pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
 
+        memphys = __pa(memory_start);
+        memsize = roundup_pow_of_two(memory_end - memory_start);
+
+        /*
+         * If there's more than 512MB of memory, we need to roll over to
+         * LAR1/LAMR1.
+         */
+        if (memsize > SZ_512M) {
+                __raw_writel(memphys + SZ_512M, chan->reg_base + SH4A_PCIELAR1);
+                __raw_writel(((memsize - SZ_512M) - SZ_256) | 1,
+                             chan->reg_base + SH4A_PCIELAMR1);
+                memsize = SZ_512M;
+        } else {
+                /*
+                 * Otherwise just zero it out and disable it.
+                 */
+                __raw_writel(0, chan->reg_base + SH4A_PCIELAR1);
+                __raw_writel(0, chan->reg_base + SH4A_PCIELAMR1);
+        }
+
+        /*
+         * LAR0/LAMR0 covers up to the first 512MB, which is enough to
+         * cover all of lowmem on most platforms.
+         */
+        __raw_writel(memphys, chan->reg_base + SH4A_PCIELAR0);
+        __raw_writel((memsize - SZ_256) | 1, chan->reg_base + SH4A_PCIELAMR0);
+
         /* Finish initialization */
         data = pci_read_reg(chan, SH4A_PCIETCTLR);
         data |= 0x1;
@@ -243,10 +305,14 @@ static int pcie_init(struct sh7786_pcie_port *port)
         if (unlikely(ret != 0))
                 return -ENODEV;
 
-        pci_write_reg(chan, 0x00100007, SH4A_PCIEPCICONF1);
+        data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
+        data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
+        data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
+        pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
+
         pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
         pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
-        pci_write_reg(chan, 0x000050A0, SH4A_PCIEEXPCAP2);
 
         wmb();
 
@@ -254,15 +320,32 @@ static int pcie_init(struct sh7786_pcie_port *port)
         printk(KERN_NOTICE "PCI: PCIe#%d link width %d\n",
                port->index, (data >> 20) & 0x3f);
 
-        pci_write_reg(chan, 0x007c0000, SH4A_PCIEPAMR0);
-        pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH0);
-        pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL0);
-        pci_write_reg(chan, 0x80000100, SH4A_PCIEPTCTLR0);
 
-        pci_write_reg(chan, 0x03fc0000, SH4A_PCIEPAMR2);
-        pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH2);
-        pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL2);
-        pci_write_reg(chan, 0x80000000, SH4A_PCIEPTCTLR2);
+        for (i = 0; i < chan->nr_resources; i++) {
+                struct resource *res = chan->resources + i;
+                resource_size_t size;
+                u32 enable_mask;
+
+                pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(i));
+
+                size = resource_size(res);
+
+                /*
+                 * The PAMR mask is calculated in units of 256kB, which
+                 * keeps things pretty simple.
+                 */
+                __raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
+                             chan->reg_base + SH4A_PCIEPAMR(i));
+
+                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARH(i));
+                pci_write_reg(chan, 0x00000000, SH4A_PCIEPARL(i));
+
+                enable_mask = MASK_PARE;
+                if (res->flags & IORESOURCE_IO)
+                        enable_mask |= MASK_SPC;
+
+                pci_write_reg(chan, enable_mask, SH4A_PCIEPTCTLR(i));
+        }
 
         return 0;
 }
@@ -296,9 +379,7 @@ static int __devinit sh7786_pcie_init_hw(struct sh7786_pcie_port *port)
         if (unlikely(ret < 0))
                 return ret;
 
-        register_pci_controller(port->hose);
-
-        return 0;
+        return register_pci_controller(port->hose);
 }
 
 static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
@@ -332,17 +413,7 @@ static int __init sh7786_pcie_init(void)
 
                 port->index             = i;
                 port->hose              = sh7786_pci_channels + i;
-                port->hose->io_map_base = port->hose->io_resource->start;
-
-                /*
-                 * Check if we are booting in 29 or 32-bit mode
-                 *
-                 * 32-bit mode provides each controller with its own
-                 * memory window, while 29-bit mode uses a shared one.
-                 */
-                port->hose->mem_resource = test_mode_pin(MODE_PIN10) ?
-                        &sh7786_pci_32bit_mem_resources[i] :
-                        &sh7786_pci_29bit_mem_resource;
+                port->hose->io_map_base = port->hose->resources[0].start;
 
                 ret |= sh7786_pcie_hwops->port_init_hw(port);
         }
diff --git a/arch/sh/drivers/pci/pcie-sh7786.h b/arch/sh/drivers/pci/pcie-sh7786.h
index c655290a7750..90a6992576b0 100644
--- a/arch/sh/drivers/pci/pcie-sh7786.h
+++ b/arch/sh/drivers/pci/pcie-sh7786.h
@@ -30,47 +30,9 @@
  * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
  */
 
-/* PCI0-0: PCI I/O space */
-#define SH4A_PCIIO_BASE         0xFD000000      /* PCI I/O for controller 0 */
-#define SH4A_PCIIO_BASE1        0xFD800000      /* PCI I/O for controller 1 (Rev1.14)*/
-#define SH4A_PCIIO_BASE2        0xFC800000      /* PCI I/O for controller 2 (Rev1.171)*/
-
-#define SH4A_PCIIO_SIZE64       0x00010000      /* PLX allows only 64K */
-#define SH4A_PCIIO_SIZE         0x00800000      /* 8M */
-#define SH4A_PCIIO_SIZE2        0x00400000      /* 4M (Rev1.171)*/
-
-/* PCI0-1: PCI memory space 29-bit address */
-#define SH4A_PCIMEM_BASE        0x10000000
-#define SH4A_PCIMEM_SIZE        0x04000000      /* 64M */
-
-/* PCI0-2: PCI memory space 32-bit address */
-#define SH4A_PCIMEM_BASEA       0xC0000000      /*  for controller 0 */
-#define SH4A_PCIMEM_BASEA1      0xA0000000      /*  for controller 1 (Rev1.14)*/
-#define SH4A_PCIMEM_BASEA2      0x80000000      /*  for controller 2 (Rev1.171)*/
-#define SH4A_PCIMEM_SIZEA       0x20000000      /* 512M */
-
 /* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
 #define SH4A_PCIBMSTR_TRANSLATION       0x20000000
 
-#define SH4A_PCI_DEVICE_ID              0x0002
-#define SH4A_PCI_VENDOR_ID              0x1912
-
-// PCI compatible 000-03f
-#define PCI_CMD         0x004
-#define PCI_RID         0x008
-#define PCI_IBAR        0x010
-#define PCI_MBAR0       0x014
-#define PCI_MBAR1       0x018
-
-/* PCI power management/MSI/capablity 040-0ff */
-/* PCIE extended 100-fff */
-
-/* SH7786 device identification */      // Rev1.171
-#define SH4A_PVR                (0xFF000030)
-#define SH4A_PVR_SHX3           (0x10400000)
-#define SH4A_PRR                (0xFF000044)
-#define SH4A_PRR_SH7786         (0x00000400)    // Rev1.171
-
 /*      SPVCR0          */
 #define SH4A_PCIEVCR0           (0x000000)      /* R - 0x0000 0000 32 */
 #define         BITS_TOP_MB     (24)
@@ -350,23 +312,23 @@
 #define SH4A_PCIECSAR5          (0x0202B4)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIESTCTLR5        (0x0202B8)      /* R/W R/W 0x0000 0000 32 */
 
-/*      PCIEPARL0       */
-#define SH4A_PCIEPARL0          (0x020400)      /* R/W R/W 0x0000 0000 32 */
+/*      PCIEPARL        */
+#define SH4A_PCIEPARL(x)        (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
 #define         BITS_PAL        (18)
 #define         MASK_PAL        (0x3fff<<BITS_PAL)
 
-/*      PCIEPARH0       */
-#define SH4A_PCIEPARH0          (0x020404)      /* R/W R/W 0x0000 0000 32 */
+/*      PCIEPARH        */
+#define SH4A_PCIEPARH(x)        (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
 #define         BITS_PAH        (0)
 #define         MASK_PAH        (0xffffffff<<BITS_PAH)
 
-/*      PCIEPAMR0        */
-#define SH4A_PCIEPAMR0          (0x020408)      /* R/W R/W 0x0000 0000 32 */
+/*      PCIEPAMR         */
+#define SH4A_PCIEPAMR(x)        (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
 #define         BITS_PAM        (18)
 #define         MASK_PAM        (0x3fff<<BITS_PAM)
 
-/*      PCIEPTCTLR0     */
-#define SH4A_PCIEPTCTLR0        (0x02040C)      /* R/W R/W 0x0000 0000 32 */
+/*      PCIEPTCTLR      */
+#define SH4A_PCIEPTCTLR(x)      (0x02040C + ((x) * 0x20))
 #define         BITS_PARE       (31)
 #define         MASK_PARE       (0x1<<BITS_PARE)
 #define         BITS_TC         (20)
@@ -378,26 +340,6 @@
 #define         BITS_SPC        (8)
 #define         MASK_SPC        (0x1<<BITS_SPC)
 
-#define SH4A_PCIEPARL1          (0x020420)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH1          (0x020424)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR1          (0x020428)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR1        (0x02042C)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL2          (0x020440)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH2          (0x020444)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR2          (0x020448)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR2        (0x02044C)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL3          (0x020460)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH3          (0x020464)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR3          (0x020468)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR3        (0x02046C)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL4          (0x020480)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH4          (0x020484)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR4          (0x020488)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR4        (0x02048C)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARL5          (0x0204A0)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPARH5          (0x0204A4)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPAMR5          (0x0204A8)      /* R/W R/W 0x0000 0000 32 */
-#define SH4A_PCIEPTCTLR5        (0x0204AC)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMAOR          (0x021000)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMSAR0         (0x021100)      /* R/W R/W 0x0000 0000 32 */
 #define SH4A_PCIEDMSAHR0        (0x021104)      /* R/W R/W 0x0000 0000 32 */
diff --git a/arch/sh/drivers/superhyway/ops-sh4-202.c b/arch/sh/drivers/superhyway/ops-sh4-202.c
index 3b14bf860db6..6da62e9475c4 100644
--- a/arch/sh/drivers/superhyway/ops-sh4-202.c
+++ b/arch/sh/drivers/superhyway/ops-sh4-202.c
@@ -134,8 +134,8 @@ static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
          *
          * Do not trust the documentation, for it is evil.
          */
-        vcrh = ctrl_inl(base);
-        vcrl = ctrl_inl(base + sizeof(u32));
+        vcrh = __raw_readl(base);
+        vcrl = __raw_readl(base + sizeof(u32));
 
         tmp = ((u64)vcrh << 32) | vcrl;
         memcpy(vcr, &tmp, sizeof(u64));
@@ -147,8 +147,8 @@ static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
 {
         u64 tmp = *(u64 *)&vcr;
 
-        ctrl_outl((tmp >> 32) & 0xffffffff, base);
-        ctrl_outl(tmp & 0xffffffff, base + sizeof(u32));
+        __raw_writel((tmp >> 32) & 0xffffffff, base);
+        __raw_writel(tmp & 0xffffffff, base + sizeof(u32));
 
         return 0;
 }
diff --git a/arch/sh/include/asm/Kbuild b/arch/sh/include/asm/Kbuild
index e121c30f797d..46cb93477bcb 100644
--- a/arch/sh/include/asm/Kbuild
+++ b/arch/sh/include/asm/Kbuild
@@ -1,6 +1,8 @@
 include include/asm-generic/Kbuild.asm
 
-header-y += cachectl.h cpu-features.h
+header-y += cachectl.h
+header-y += cpu-features.h
+header-y += hw_breakpoint.h
 
 unifdef-y += unistd_32.h
 unifdef-y += unistd_64.h
diff --git a/arch/sh/include/asm/addrspace.h b/arch/sh/include/asm/addrspace.h
index 99d6b3ecbe22..446b3831c214 100644
--- a/arch/sh/include/asm/addrspace.h
+++ b/arch/sh/include/asm/addrspace.h
@@ -28,7 +28,7 @@
 /* Returns the privileged segment base of a given address  */
 #define PXSEG(a)        (((unsigned long)(a)) & 0xe0000000)
 
-#if defined(CONFIG_29BIT) || defined(CONFIG_PMB_FIXED)
+#ifdef CONFIG_29BIT
 /*
  * Map an address to a certain privileged segment
  */
@@ -40,7 +40,15 @@
         ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
 #define P4SEGADDR(a)    \
         ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
-#endif /* 29BIT || PMB_FIXED */
+#else
+/*
+ * These will never work in 32-bit, don't even bother.
+ */
+#define P1SEGADDR(a)    __futile_remapping_attempt
+#define P2SEGADDR(a)    __futile_remapping_attempt
+#define P3SEGADDR(a)    __futile_remapping_attempt
+#define P4SEGADDR(a)    __futile_remapping_attempt
+#endif
 #endif /* P1SEG */
 
 /* Check if an address can be reached in 29 bits */
@@ -57,11 +65,5 @@
 #define P3_ADDR_MAX             P4SEG
 #endif
 
-#ifndef __ASSEMBLY__
-#ifdef CONFIG_PMB
-extern int __in_29bit_mode(void);
-#endif /* CONFIG_PMB */
-#endif /* __ASSEMBLY__ */
-
 #endif /* __KERNEL__ */
 #endif /* __ASM_SH_ADDRSPACE_H */
diff --git a/arch/sh/include/asm/alignment.h b/arch/sh/include/asm/alignment.h
new file mode 100644
index 000000000000..b12efecf5294
--- /dev/null
+++ b/arch/sh/include/asm/alignment.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_ALIGNMENT_H
+#define __ASM_SH_ALIGNMENT_H
+
+#include <linux/types.h>
+
+extern void inc_unaligned_byte_access(void);
+extern void inc_unaligned_word_access(void);
+extern void inc_unaligned_dword_access(void);
+extern void inc_unaligned_multi_access(void);
+extern void inc_unaligned_user_access(void);
+extern void inc_unaligned_kernel_access(void);
+
+#define UM_WARN         (1 << 0)
+#define UM_FIXUP        (1 << 1)
+#define UM_SIGNAL       (1 << 2)
+
+extern unsigned int unaligned_user_action(void);
+
+extern void unaligned_fixups_notify(struct task_struct *, insn_size_t, struct pt_regs *);
+
+#endif /* __ASM_SH_ALIGNMENT_H */
diff --git a/arch/sh/include/asm/atomic-grb.h b/arch/sh/include/asm/atomic-grb.h
index 4c5b7dbfcedb..a273c88578fc 100644
--- a/arch/sh/include/asm/atomic-grb.h
+++ b/arch/sh/include/asm/atomic-grb.h
@@ -120,50 +120,4 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
                 : "memory" , "r0", "r1");
 }
 
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
-        int ret;
-
-        __asm__ __volatile__ (
-                "   .align 2            \n\t"
-                "   mova     1f,  r0    \n\t"
-                "   nop                 \n\t"
-                "   mov     r15,  r1    \n\t"
-                "   mov    #-8,  r15    \n\t"
-                "   mov.l   @%1,  %0    \n\t"
-                "   cmp/eq   %2,  %0    \n\t"
-                "   bf       1f         \n\t"
-                "   mov.l    %3, @%1    \n\t"
-                "1: mov      r1,  r15   \n\t"
-                : "=&r" (ret)
-                : "r" (v), "r" (old), "r" (new)
-                : "memory" , "r0", "r1" , "t");
-
-        return ret;
-}
-
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int ret;
-        unsigned long tmp;
-
-        __asm__ __volatile__ (
-                "   .align 2            \n\t"
-                "   mova    1f,   r0    \n\t"
-                "   nop                 \n\t"
-                "   mov    r15,   r1    \n\t"
-                "   mov    #-12,  r15   \n\t"
-                "   mov.l  @%2,   %1    \n\t"
-                "   mov     %1,   %0    \n\t"
-                "   cmp/eq  %4,   %0    \n\t"
-                "   bt/s    1f          \n\t"
-                "    add    %3,   %1    \n\t"
-                "   mov.l   %1,  @%2    \n\t"
-                "1: mov     r1,   r15   \n\t"
-                : "=&r" (ret), "=&r" (tmp)
-                : "r" (v), "r" (a), "r" (u)
-                : "memory" , "r0", "r1" , "t");
-
-        return ret != u;
-}
 #endif /* __ASM_SH_ATOMIC_GRB_H */
diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h
index b040e1e08610..4b00b78e3f4f 100644
--- a/arch/sh/include/asm/atomic-llsc.h
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -104,31 +104,4 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
         : "t");
 }
 
-#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int c, old;
-        c = atomic_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-
-        return c != (u);
-}
-
 #endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index b16388d71954..275a448ae8c2 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -25,58 +25,43 @@
 #endif
 
 #define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+#define atomic_dec_return(v)            atomic_sub_return(1, (v))
+#define atomic_inc_return(v)            atomic_add_return(1, (v))
+#define atomic_inc_and_test(v)          (atomic_inc_return(v) == 0)
+#define atomic_sub_and_test(i,v)        (atomic_sub_return((i), (v)) == 0)
+#define atomic_dec_and_test(v)          (atomic_sub_return(1, (v)) == 0)
+#define atomic_inc_not_zero(v)          atomic_add_unless((v), 1, 0)
 
-#define atomic_dec_return(v) atomic_sub_return(1,(v))
-#define atomic_inc_return(v) atomic_add_return(1,(v))
+#define atomic_inc(v)                   atomic_add(1, (v))
+#define atomic_dec(v)                   atomic_sub(1, (v))
 
-/*
- * atomic_inc_and_test - increment and test
+#define atomic_xchg(v, new)             (xchg(&((v)->counter), new))
+#define atomic_cmpxchg(v, o, n)         (cmpxchg(&((v)->counter), (o), (n)))
+
+/**
+ * atomic_add_unless - add unless the number is a given value
  * @v: pointer of type atomic_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
  *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
-#define atomic_inc(v) atomic_add(1,(v))
-#define atomic_dec(v) atomic_sub(1,(v))
-
-#if !defined(CONFIG_GUSA_RB) && !defined(CONFIG_CPU_SH4A)
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
-        int ret;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        ret = v->counter;
-        if (likely(ret == old))
-                v->counter = new;
-        local_irq_restore(flags);
-
-        return ret;
-}
-
 static inline int atomic_add_unless(atomic_t *v, int a, int u)
 {
-        int ret;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        ret = v->counter;
-        if (ret != u)
-                v->counter += a;
-        local_irq_restore(flags);
-
-        return ret != u;
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+
+        return c != (u);
 }
-#endif /* !CONFIG_GUSA_RB && !CONFIG_CPU_SH4A */
-
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 #define smp_mb__before_atomic_dec()     smp_mb()
 #define smp_mb__after_atomic_dec()      smp_mb()
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index dda96eb3e7c0..da3ebec921a7 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -63,6 +63,14 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
         if (boot_cpu_data.dcache.n_aliases && PageAnon(page))
                 __flush_anon_page(page, vmaddr);
 }
+static inline void flush_kernel_vmap_range(void *addr, int size)
+{
+        __flush_wback_region(addr, size);
+}
+static inline void invalidate_kernel_vmap_range(void *addr, int size)
+{
+        __flush_invalidate_region(addr, size);
+}
 
 #define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
 static inline void flush_kernel_dcache_page(struct page *page)
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 9fe7d7f8af40..11da4c5beb68 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -146,8 +146,17 @@ int sh_clk_mstp32_register(struct clk *clks, int nr);
         .flags = _flags,                                                \
 }
 
+struct clk_div4_table {
+        struct clk_div_mult_table *div_mult_table;
+        void (*kick)(struct clk *clk);
+};
+
 int sh_clk_div4_register(struct clk *clks, int nr,
-                         struct clk_div_mult_table *table);
+                         struct clk_div4_table *table);
+int sh_clk_div4_enable_register(struct clk *clks, int nr,
+                         struct clk_div4_table *table);
+int sh_clk_div4_reparent_register(struct clk *clks, int nr,
+                         struct clk_div4_table *table);
 
 #define SH_CLK_DIV6(_name, _parent, _reg, _flags)       \
 {                                                       \
diff --git a/arch/sh/include/asm/cmpxchg-grb.h b/arch/sh/include/asm/cmpxchg-grb.h
index e2681abe764f..4676bf57693a 100644
--- a/arch/sh/include/asm/cmpxchg-grb.h
+++ b/arch/sh/include/asm/cmpxchg-grb.h
@@ -57,11 +57,10 @@ static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
                 "   mov.l  @%1,   %0      \n\t" /* load  old value */
                 "   cmp/eq  %0,   %2      \n\t"
                 "   bf            1f      \n\t" /* if not equal */
-                "   mov.l   %2,   @%1     \n\t" /* store new value */
+                "   mov.l   %3,   @%1     \n\t" /* store new value */
                 "1: mov     r1,   r15     \n\t" /* LOGOUT */
-                : "=&r" (retval),
-                  "+r"  (m)
-                : "r"   (new)
+                : "=&r" (retval)
+                :  "r"  (m), "r"  (old), "r"  (new)
                 : "memory" , "r0", "r1", "t");
 
         return retval;
diff --git a/arch/sh/include/asm/dma-mapping.h b/arch/sh/include/asm/dma-mapping.h
index 87ced133a363..bea3337a426a 100644
--- a/arch/sh/include/asm/dma-mapping.h
+++ b/arch/sh/include/asm/dma-mapping.h
@@ -89,8 +89,6 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 {
         struct dma_map_ops *ops = get_dma_ops(dev);
 
-        WARN_ON(irqs_disabled());       /* for portability */
-
         if (dma_release_from_coherent(dev, get_order(size), vaddr))
                 return;
 
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index 78eed3e0bdf5..e934a2e66651 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -20,14 +20,14 @@
     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define dmaor_read_reg(n) \
-    (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
-        : ctrl_inw(SH_DMAC_BASE0 + DMAOR))
+    (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
+        : __raw_readw(SH_DMAC_BASE0 + DMAOR))
 #define dmaor_write_reg(n, data) \
-    (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
-    : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
+    (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
+    : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
 #else /* Other CPU */
-#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
-#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
+#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
+#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
 #endif
 
 static int dmte_irq_map[] __maybe_unused = {
@@ -64,8 +64,10 @@ static int dmte_irq_map[] __maybe_unused = {
 #define ACK_L   0x00010000
 #define DM_INC  0x00004000
 #define DM_DEC  0x00008000
+#define DM_FIX  0x0000c000
 #define SM_INC  0x00001000
 #define SM_DEC  0x00002000
+#define SM_FIX  0x00003000
 #define RS_IN   0x00000200
 #define RS_OUT  0x00000300
 #define TS_BLK  0x00000040
@@ -83,7 +85,7 @@ static int dmte_irq_map[] __maybe_unused = {
  * Define the default configuration for dual address memory-memory transfer.
  * The 0x400 value represents auto-request, external->external.
  */
-#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
+#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_INDEX2VAL(XMIT_SZ_32BIT))
 
 /* DMA base address */
 static u32 dma_base_addr[] __maybe_unused = {
@@ -123,10 +125,47 @@ static u32 dma_base_addr[] __maybe_unused = {
  */
 #define SHDMA_MIX_IRQ   (1 << 1)
 #define SHDMA_DMAOR1    (1 << 2)
-#define SHDMA_DMAE1             (1 << 3)
+#define SHDMA_DMAE1     (1 << 3)
+
+enum sh_dmae_slave_chan_id {
+        SHDMA_SLAVE_SCIF0_TX,
+        SHDMA_SLAVE_SCIF0_RX,
+        SHDMA_SLAVE_SCIF1_TX,
+        SHDMA_SLAVE_SCIF1_RX,
+        SHDMA_SLAVE_SCIF2_TX,
+        SHDMA_SLAVE_SCIF2_RX,
+        SHDMA_SLAVE_SCIF3_TX,
+        SHDMA_SLAVE_SCIF3_RX,
+        SHDMA_SLAVE_SCIF4_TX,
+        SHDMA_SLAVE_SCIF4_RX,
+        SHDMA_SLAVE_SCIF5_TX,
+        SHDMA_SLAVE_SCIF5_RX,
+        SHDMA_SLAVE_SIUA_TX,
+        SHDMA_SLAVE_SIUA_RX,
+        SHDMA_SLAVE_SIUB_TX,
+        SHDMA_SLAVE_SIUB_RX,
+        SHDMA_SLAVE_NUMBER,     /* Must stay last */
+};
+
+struct sh_dmae_slave_config {
+        enum sh_dmae_slave_chan_id      slave_id;
+        dma_addr_t                      addr;
+        u32                             chcr;
+        char                            mid_rid;
+};
 
 struct sh_dmae_pdata {
         unsigned int mode;
+        struct sh_dmae_slave_config *config;
+        int config_num;
+};
+
+struct device;
+
+struct sh_dmae_slave {
+        enum sh_dmae_slave_chan_id      slave_id; /* Set by the platform */
+        struct device                   *dma_dev; /* Set by the platform */
+        struct sh_dmae_slave_config     *config;  /* Set by the driver */
 };
 
 #endif /* __DMA_SH_H */
diff --git a/arch/sh/include/asm/dwarf.h b/arch/sh/include/asm/dwarf.h
index bdccbbfdc0bd..d62abd1d0c05 100644
--- a/arch/sh/include/asm/dwarf.h
+++ b/arch/sh/include/asm/dwarf.h
@@ -243,16 +243,13 @@ struct dwarf_cie {
 
         unsigned long cie_pointer;
 
-        struct list_head link;
-
         unsigned long flags;
 #define DWARF_CIE_Z_AUGMENTATION        (1 << 0)
 
-        /*
-         * 'mod' will be non-NULL if this CIE came from a module's
-         * .eh_frame section.
-         */
-        struct module *mod;
+        /* linked-list entry if this CIE is from a module */
+        struct list_head link;
+
+        struct rb_node node;
 };
 
 /**
@@ -266,13 +263,11 @@ struct dwarf_fde {
         unsigned long address_range;
         unsigned char *instructions;
         unsigned char *end;
+
+        /* linked-list entry if this FDE is from a module */
         struct list_head link;
 
-        /*
-         * 'mod' will be non-NULL if this FDE came from a module's
-         * .eh_frame section.
-         */
-        struct module *mod;
+        struct rb_node node;
 };
 
 /**
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
index 5ac1e40a511c..6e7cea453895 100644
--- a/arch/sh/include/asm/fixmap.h
+++ b/arch/sh/include/asm/fixmap.h
@@ -55,16 +55,29 @@ enum fixed_addresses {
 #define FIX_N_COLOURS 8
         FIX_CMAP_BEGIN,
         FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS) - 1,
-        FIX_UNCACHED,
+
 #ifdef CONFIG_HIGHMEM
         FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
         FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
 #endif
+
+#ifdef CONFIG_IOREMAP_FIXED
+        /*
+         * FIX_IOREMAP entries are useful for mapping physical address
+         * space before ioremap() is useable, e.g. really early in boot
+         * before kmalloc() is working.
+         */
+#define FIX_N_IOREMAPS  32
+        FIX_IOREMAP_BEGIN,
+        FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS,
+#endif
+
         __end_of_fixed_addresses
 };
 
 extern void __set_fixmap(enum fixed_addresses idx,
                          unsigned long phys, pgprot_t flags);
+extern void __clear_fixmap(enum fixed_addresses idx, pgprot_t flags);
 
 #define set_fixmap(idx, phys) \
                 __set_fixmap(idx, phys, PAGE_KERNEL)
diff --git a/arch/sh/include/asm/fpu.h b/arch/sh/include/asm/fpu.h
index fb6bbb9b1cc8..06c4281aab65 100644
--- a/arch/sh/include/asm/fpu.h
+++ b/arch/sh/include/asm/fpu.h
@@ -2,8 +2,8 @@
 #define __ASM_SH_FPU_H
 
 #ifndef __ASSEMBLY__
-#include <linux/preempt.h>
-#include <asm/ptrace.h>
+
+struct task_struct;
 
 #ifdef CONFIG_SH_FPU
 static inline void release_fpu(struct pt_regs *regs)
@@ -16,22 +16,23 @@ static inline void grab_fpu(struct pt_regs *regs)
         regs->sr &= ~SR_FD;
 }
 
-struct task_struct;
-
 extern void save_fpu(struct task_struct *__tsk);
-void fpu_state_restore(struct pt_regs *regs);
+extern void restore_fpu(struct task_struct *__tsk);
+extern void fpu_state_restore(struct pt_regs *regs);
+extern void __fpu_state_restore(void);
 #else
-
-#define save_fpu(tsk)           do { } while (0)
-#define release_fpu(regs)       do { } while (0)
-#define grab_fpu(regs)          do { } while (0)
-#define fpu_state_restore(regs) do { } while (0)
-
+#define save_fpu(tsk)                   do { } while (0)
+#define restore_fpu(tsk)                do { } while (0)
+#define release_fpu(regs)               do { } while (0)
+#define grab_fpu(regs)                  do { } while (0)
+#define fpu_state_restore(regs)         do { } while (0)
+#define __fpu_state_restore(regs)       do { } while (0)
 #endif
 
 struct user_regset;
 
 extern int do_fpu_inst(unsigned short, struct pt_regs *);
+extern int init_fpu(struct task_struct *);
 
 extern int fpregs_get(struct task_struct *target,
                       const struct user_regset *regset,
@@ -65,18 +66,6 @@ static inline void clear_fpu(struct task_struct *tsk, struct pt_regs *regs)
         preempt_enable();
 }
 
-static inline int init_fpu(struct task_struct *tsk)
-{
-        if (tsk_used_math(tsk)) {
-                if ((boot_cpu_data.flags & CPU_HAS_FPU) && tsk == current)
-                        unlazy_fpu(tsk, task_pt_regs(tsk));
-                return 0;
-        }
-
-        set_stopped_child_used_math(tsk);
-        return 0;
-}
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_SH_FPU_H */
diff --git a/arch/sh/include/asm/hw_breakpoint.h b/arch/sh/include/asm/hw_breakpoint.h
new file mode 100644
index 000000000000..965dd780d51b
--- /dev/null
+++ b/arch/sh/include/asm/hw_breakpoint.h
@@ -0,0 +1,67 @@
+#ifndef __ASM_SH_HW_BREAKPOINT_H
+#define __ASM_SH_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+#define __ARCH_HW_BREAKPOINT_H
+
+#include <linux/kdebug.h>
+#include <linux/types.h>
+
+struct arch_hw_breakpoint {
+        char            *name; /* Contains name of the symbol to set bkpt */
+        unsigned long   address;
+        u16             len;
+        u16             type;
+};
+
+enum {
+        SH_BREAKPOINT_READ      = (1 << 1),
+        SH_BREAKPOINT_WRITE     = (1 << 2),
+        SH_BREAKPOINT_RW        = SH_BREAKPOINT_READ | SH_BREAKPOINT_WRITE,
+
+        SH_BREAKPOINT_LEN_1     = (1 << 12),
+        SH_BREAKPOINT_LEN_2     = (1 << 13),
+        SH_BREAKPOINT_LEN_4     = SH_BREAKPOINT_LEN_1 | SH_BREAKPOINT_LEN_2,
+        SH_BREAKPOINT_LEN_8     = (1 << 14),
+};
+
+struct sh_ubc {
+        const char      *name;
+        unsigned int    num_events;
+        unsigned int    trap_nr;
+        void            (*enable)(struct arch_hw_breakpoint *, int);
+        void            (*disable)(struct arch_hw_breakpoint *, int);
+        void            (*enable_all)(unsigned long);
+        void            (*disable_all)(void);
+        unsigned long   (*active_mask)(void);
+        unsigned long   (*triggered_mask)(void);
+        void            (*clear_triggered_mask)(unsigned long);
+        struct clk      *clk;   /* optional interface clock / MSTP bit */
+};
+
+struct perf_event;
+struct task_struct;
+struct pmu;
+
+/* Maximum number of UBC channels */
+#define HBP_NUM         2
+
+/* arch/sh/kernel/hw_breakpoint.c */
+extern int arch_check_va_in_userspace(unsigned long va, u16 hbp_len);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp,
+                                         struct task_struct *tsk);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+                                           unsigned long val, void *data);
+
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+void hw_breakpoint_pmu_unthrottle(struct perf_event *bp);
+
+extern void arch_fill_perf_breakpoint(struct perf_event *bp);
+extern int register_sh_ubc(struct sh_ubc *);
+
+extern struct pmu perf_ops_bp;
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_SH_HW_BREAKPOINT_H */
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 026dd659a640..7dab7b23a5ec 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -22,6 +22,7 @@
  * for old compat code for I/O offseting to SuperIOs, all of which are
  * better handled through the machvec ioport mapping routines these days.
  */
+#include <linux/errno.h>
 #include <asm/cache.h>
 #include <asm/system.h>
 #include <asm/addrspace.h>
@@ -79,16 +80,51 @@
 #define writel(v,a)             ({ __raw_writel((v),(a)); mb(); })
 #define writeq(v,a)             ({ __raw_writeq((v),(a)); mb(); })
 
-/* SuperH on-chip I/O functions */
-#define ctrl_inb                __raw_readb
-#define ctrl_inw                __raw_readw
-#define ctrl_inl                __raw_readl
-#define ctrl_inq                __raw_readq
+/*
+ * Legacy SuperH on-chip I/O functions
+ *
+ * These are all deprecated, all new (and especially cross-platform) code
+ * should be using the __raw_xxx() routines directly.
+ */
+static inline u8 __deprecated ctrl_inb(unsigned long addr)
+{
+        return __raw_readb(addr);
+}
+
+static inline u16 __deprecated ctrl_inw(unsigned long addr)
+{
+        return __raw_readw(addr);
+}
+
+static inline u32 __deprecated ctrl_inl(unsigned long addr)
+{
+        return __raw_readl(addr);
+}
+
+static inline u64 __deprecated ctrl_inq(unsigned long addr)
+{
+        return __raw_readq(addr);
+}
+
+static inline void __deprecated ctrl_outb(u8 v, unsigned long addr)
+{
+        __raw_writeb(v, addr);
+}
+
+static inline void __deprecated ctrl_outw(u16 v, unsigned long addr)
+{
+        __raw_writew(v, addr);
+}
 
-#define ctrl_outb               __raw_writeb
-#define ctrl_outw               __raw_writew
-#define ctrl_outl               __raw_writel
-#define ctrl_outq               __raw_writeq
+static inline void __deprecated ctrl_outl(u32 v, unsigned long addr)
+{
+        __raw_writel(v, addr);
+}
+
+static inline void __deprecated ctrl_outq(u64 v, unsigned long addr)
+{
+        __raw_writeq(v, addr);
+}
 
 extern unsigned long generic_io_base;
 
@@ -97,6 +133,28 @@ static inline void ctrl_delay(void)
         __raw_readw(generic_io_base);
 }
 
+#define __BUILD_UNCACHED_IO(bwlq, type)                                 \
+static inline type read##bwlq##_uncached(unsigned long addr)            \
+{                                                                       \
+        type ret;                                                       \
+        jump_to_uncached();                                             \
+        ret = __raw_read##bwlq(addr);                                   \
+        back_to_cached();                                               \
+        return ret;                                                     \
+}                                                                       \
+                                                                        \
+static inline void write##bwlq##_uncached(type v, unsigned long addr)   \
+{                                                                       \
+        jump_to_uncached();                                             \
+        __raw_write##bwlq(v, addr);                                     \
+        back_to_cached();                                               \
+}
+
+__BUILD_UNCACHED_IO(b, u8)
+__BUILD_UNCACHED_IO(w, u16)
+__BUILD_UNCACHED_IO(l, u32)
+__BUILD_UNCACHED_IO(q, u64)
+
 #define __BUILD_MEMORY_STRING(bwlq, type)                               \
                                                                         \
 static inline void __raw_writes##bwlq(volatile void __iomem *mem,       \
@@ -234,28 +292,21 @@ unsigned long long poke_real_address_q(unsigned long long addr,
  */
 #ifdef CONFIG_MMU
 void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
-                               unsigned long flags, void *caller);
+                               pgprot_t prot, void *caller);
 void __iounmap(void __iomem *addr);
 
 static inline void __iomem *
-__ioremap(unsigned long offset, unsigned long size, unsigned long flags)
+__ioremap(unsigned long offset, unsigned long size, pgprot_t prot)
 {
-        return __ioremap_caller(offset, size, flags, __builtin_return_address(0));
+        return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
 }
 
 static inline void __iomem *
-__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
+__ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot)
 {
-#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED) && !defined(CONFIG_PMB)
+#ifdef CONFIG_29BIT
         unsigned long last_addr = offset + size - 1;
-#endif
-        void __iomem *ret;
 
-        ret = __ioremap_trapped(offset, size);
-        if (ret)
-                return ret;
-
-#if defined(CONFIG_SUPERH32) && !defined(CONFIG_PMB_FIXED) && !defined(CONFIG_PMB)
         /*
          * For P1 and P2 space this is trivial, as everything is already
          * mapped. Uncached access for P1 addresses are done through P2.
@@ -263,7 +314,7 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
          * mapping must be done by the PMB or by using page tables.
          */
         if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
-                if (unlikely(flags & _PAGE_CACHABLE))
+                if (unlikely(pgprot_val(prot) & _PAGE_CACHABLE))
                         return (void __iomem *)P1SEGADDR(offset);
 
                 return (void __iomem *)P2SEGADDR(offset);
@@ -274,26 +325,70 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
                 return (void __iomem *)P4SEGADDR(offset);
 #endif
 
-        return __ioremap(offset, size, flags);
+        return NULL;
+}
+
+static inline void __iomem *
+__ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot)
+{
+        void __iomem *ret;
+
+        ret = __ioremap_trapped(offset, size);
+        if (ret)
+                return ret;
+
+        ret = __ioremap_29bit(offset, size, prot);
+        if (ret)
+                return ret;
+
+        return __ioremap(offset, size, prot);
 }
 #else
-#define __ioremap(offset, size, flags)          ((void __iomem *)(offset))
-#define __ioremap_mode(offset, size, flags)     ((void __iomem *)(offset))
+#define __ioremap(offset, size, prot)           ((void __iomem *)(offset))
+#define __ioremap_mode(offset, size, prot)      ((void __iomem *)(offset))
 #define __iounmap(addr)                         do { } while (0)
 #endif /* CONFIG_MMU */
 
-#define ioremap(offset, size)                           \
-        __ioremap_mode((offset), (size), 0)
-#define ioremap_nocache(offset, size)                   \
-        __ioremap_mode((offset), (size), 0)
-#define ioremap_cache(offset, size)                     \
-        __ioremap_mode((offset), (size), _PAGE_CACHABLE)
-#define p3_ioremap(offset, size, flags)                 \
-        __ioremap((offset), (size), (flags))
-#define ioremap_prot(offset, size, flags)               \
-        __ioremap_mode((offset), (size), (flags))
-#define iounmap(addr)                                   \
-        __iounmap((addr))
+static inline void __iomem *
+ioremap(unsigned long offset, unsigned long size)
+{
+        return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
+}
+
+static inline void __iomem *
+ioremap_cache(unsigned long offset, unsigned long size)
+{
+        return __ioremap_mode(offset, size, PAGE_KERNEL);
+}
+
+#ifdef CONFIG_HAVE_IOREMAP_PROT
+static inline void __iomem *
+ioremap_prot(resource_size_t offset, unsigned long size, unsigned long flags)
+{
+        return __ioremap_mode(offset, size, __pgprot(flags));
+}
+#endif
+
+#ifdef CONFIG_IOREMAP_FIXED
+extern void __iomem *ioremap_fixed(resource_size_t, unsigned long,
+                                   unsigned long, pgprot_t);
+extern int iounmap_fixed(void __iomem *);
+extern void ioremap_fixed_init(void);
+#else
+static inline void __iomem *
+ioremap_fixed(resource_size_t phys_addr, unsigned long offset,
+              unsigned long size, pgprot_t prot)
+{
+        BUG();
+        return NULL;
+}
+
+static inline void ioremap_fixed_init(void) { }
+static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
+#endif
+
+#define ioremap_nocache ioremap
+#define iounmap         __iounmap
 
 #define maybebadio(port) \
         printk(KERN_ERR "bad PC-like io %s:%u for port 0x%lx at 0x%08x\n", \
diff --git a/arch/sh/include/asm/kdebug.h b/arch/sh/include/asm/kdebug.h
index 985219f9759e..5f6d2e9ccb7c 100644
--- a/arch/sh/include/asm/kdebug.h
+++ b/arch/sh/include/asm/kdebug.h
@@ -6,6 +6,8 @@ enum die_val {
         DIE_TRAP,
         DIE_NMI,
         DIE_OOPS,
+        DIE_BREAKPOINT,
+        DIE_SSTEP,
 };
 
 #endif /* __ASM_SH_KDEBUG_H */
diff --git a/arch/sh/include/asm/mmu.h b/arch/sh/include/asm/mmu.h
index c7426ad9926e..15a05b615ba7 100644
--- a/arch/sh/include/asm/mmu.h
+++ b/arch/sh/include/asm/mmu.h
@@ -11,7 +11,9 @@
 
 #define PMB_ADDR                0xf6100000
 #define PMB_DATA                0xf7100000
-#define PMB_ENTRY_MAX           16
+
+#define NR_PMB_ENTRIES          16
+
 #define PMB_E_MASK              0x0000000f
 #define PMB_E_SHIFT             8
 
@@ -25,11 +27,15 @@
 #define PMB_C                   0x00000008
 #define PMB_WT                  0x00000001
 #define PMB_UB                  0x00000200
+#define PMB_CACHE_MASK          (PMB_C | PMB_WT | PMB_UB)
 #define PMB_V                   0x00000100
 
 #define PMB_NO_ENTRY            (-1)
 
 #ifndef __ASSEMBLY__
+#include <linux/errno.h>
+#include <linux/threads.h>
+#include <asm/page.h>
 
 /* Default "unsigned long" context */
 typedef unsigned long mm_context_id_t[NR_CPUS];
@@ -47,29 +53,30 @@ typedef struct {
 #endif
 } mm_context_t;
 
-struct pmb_entry;
-
-struct pmb_entry {
-        unsigned long vpn;
-        unsigned long ppn;
-        unsigned long flags;
-
-        /*
-         * 0 .. NR_PMB_ENTRIES for specific entry selection, or
-         * PMB_NO_ENTRY to search for a free one
-         */
-        int entry;
-
-        struct pmb_entry *next;
-        /* Adjacent entry link for contiguous multi-entry mappings */
-        struct pmb_entry *link;
-};
-
+#ifdef CONFIG_PMB
 /* arch/sh/mm/pmb.c */
 long pmb_remap(unsigned long virt, unsigned long phys,
-               unsigned long size, unsigned long flags);
+               unsigned long size, pgprot_t prot);
 void pmb_unmap(unsigned long addr);
-int pmb_init(void);
+void pmb_init(void);
+bool __in_29bit_mode(void);
+#else
+static inline long pmb_remap(unsigned long virt, unsigned long phys,
+                             unsigned long size, pgprot_t prot)
+{
+        return -EINVAL;
+}
+
+#define pmb_unmap(addr)         do { } while (0)
+#define pmb_init(addr)          do { } while (0)
+
+#ifdef CONFIG_29BIT
+#define __in_29bit_mode()       (1)
+#else
+#define __in_29bit_mode()       (0)
+#endif
+
+#endif /* CONFIG_PMB */
 #endif /* __ASSEMBLY__ */
 
 #endif /* __MMU_H */
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
index 41080b173a7a..384c7471a374 100644
--- a/arch/sh/include/asm/mmu_context.h
+++ b/arch/sh/include/asm/mmu_context.h
@@ -158,7 +158,7 @@ static inline void enable_mmu(void)
         unsigned int cpu = smp_processor_id();
 
         /* Enable MMU */
-        ctrl_outl(MMU_CONTROL_INIT, MMUCR);
+        __raw_writel(MMU_CONTROL_INIT, MMUCR);
         ctrl_barrier();
 
         if (asid_cache(cpu) == NO_CONTEXT)
@@ -171,9 +171,9 @@ static inline void disable_mmu(void)
 {
         unsigned long cr;
 
-        cr = ctrl_inl(MMUCR);
+        cr = __raw_readl(MMUCR);
         cr &= ~MMU_CONTROL_INIT;
-        ctrl_outl(cr, MMUCR);
+        __raw_writel(cr, MMUCR);
 
         ctrl_barrier();
 }
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h
index 8ef800c549ab..10e2e17210d2 100644
--- a/arch/sh/include/asm/mmu_context_32.h
+++ b/arch/sh/include/asm/mmu_context_32.h
@@ -49,11 +49,11 @@ static inline unsigned long get_asid(void)
 /* MMU_TTB is used for optimizing the fault handling. */
 static inline void set_TTB(pgd_t *pgd)
 {
-        ctrl_outl((unsigned long)pgd, MMU_TTB);
+        __raw_writel((unsigned long)pgd, MMU_TTB);
 }
 
 static inline pgd_t *get_TTB(void)
 {
-        return (pgd_t *)ctrl_inl(MMU_TTB);
+        return (pgd_t *)__raw_readl(MMU_TTB);
 }
 #endif /* __ASM_SH_MMU_CONTEXT_32_H */
diff --git a/arch/sh/include/asm/module.h b/arch/sh/include/asm/module.h
index 068bf1659750..b7927de86f9f 100644
--- a/arch/sh/include/asm/module.h
+++ b/arch/sh/include/asm/module.h
@@ -1,7 +1,22 @@
 #ifndef _ASM_SH_MODULE_H
 #define _ASM_SH_MODULE_H
 
-#include <asm-generic/module.h>
+struct mod_arch_specific {
+#ifdef CONFIG_DWARF_UNWINDER
+        struct list_head fde_list;
+        struct list_head cie_list;
+#endif
+};
+
+#ifdef CONFIG_64BIT
+#define Elf_Shdr Elf64_Shdr
+#define Elf_Sym Elf64_Sym
+#define Elf_Ehdr Elf64_Ehdr
+#else
+#define Elf_Shdr Elf32_Shdr
+#define Elf_Sym Elf32_Sym
+#define Elf_Ehdr Elf32_Ehdr
+#endif
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 # ifdef CONFIG_CPU_SH2
diff --git a/arch/sh/include/asm/page.h b/arch/sh/include/asm/page.h
index 81bffc0d6860..d71feb359304 100644
--- a/arch/sh/include/asm/page.h
+++ b/arch/sh/include/asm/page.h
@@ -45,6 +45,7 @@
 #endif
 
 #ifndef __ASSEMBLY__
+#include <asm/uncached.h>
 
 extern unsigned long shm_align_mask;
 extern unsigned long max_low_pfn, min_low_pfn;
@@ -56,7 +57,6 @@ pages_do_alias(unsigned long addr1, unsigned long addr2)
         return (addr1 ^ addr2) & shm_align_mask;
 }
 
-
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, void *from);
 
@@ -88,7 +88,7 @@ typedef struct { unsigned long pgd; } pgd_t;
 #define __pte(x)        ((pte_t) { (x) } )
 #else
 typedef struct { unsigned long long pte_low; } pte_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long long pgprot; } pgprot_t;
 typedef struct { unsigned long pgd; } pgd_t;
 #define pte_val(x)      ((x).pte_low)
 #define __pte(x)        ((pte_t) { (x) } )
@@ -127,12 +127,7 @@ typedef struct page *pgtable_t;
  * is not visible (it is part of the PMB mapping) and so needs to be
  * added or subtracted as required.
  */
-#if defined(CONFIG_PMB_FIXED)
-/* phys = virt - PAGE_OFFSET - (__MEMORY_START & 0xe0000000) */
-#define PMB_OFFSET      (PAGE_OFFSET - PXSEG(__MEMORY_START))
-#define __pa(x) ((unsigned long)(x) - PMB_OFFSET)
-#define __va(x) ((void *)((unsigned long)(x) + PMB_OFFSET))
-#elif defined(CONFIG_32BIT)
+#ifdef CONFIG_PMB
 #define __pa(x) ((unsigned long)(x)-PAGE_OFFSET+__MEMORY_START)
 #define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET-__MEMORY_START))
 #else
@@ -140,6 +135,14 @@ typedef struct page *pgtable_t;
 #define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET))
 #endif
 
+#ifdef CONFIG_UNCACHED_MAPPING
+#define UNCAC_ADDR(addr)        ((addr) - PAGE_OFFSET + uncached_start)
+#define CAC_ADDR(addr)          ((addr) - uncached_start + PAGE_OFFSET)
+#else
+#define UNCAC_ADDR(addr)        ((addr))
+#define CAC_ADDR(addr)          ((addr))
+#endif
+
 #define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index 67f3999b544e..1042f7f0a48b 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -15,20 +15,49 @@
  */
 struct pci_channel {
         struct pci_channel      *next;
+        struct pci_bus          *bus;
 
         struct pci_ops          *pci_ops;
-        struct resource         *io_resource;
-        struct resource         *mem_resource;
+
+        struct resource         *resources;
+        unsigned int            nr_resources;
 
         unsigned long           io_offset;
         unsigned long           mem_offset;
 
         unsigned long           reg_base;
-
         unsigned long           io_map_base;
+
+        unsigned int            index;
+        unsigned int            need_domain_info;
+
+        /* Optional error handling */
+        struct timer_list       err_timer, serr_timer;
+        unsigned int            err_irq, serr_irq;
 };
 
-extern void register_pci_controller(struct pci_channel *hose);
+/* arch/sh/drivers/pci/pci.c */
+extern int register_pci_controller(struct pci_channel *hose);
+extern void pcibios_report_status(unsigned int status_mask, int warn);
+
+/* arch/sh/drivers/pci/common.c */
+extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
+                                  int bus, int devfn, int offset, u8 *value);
+extern int early_read_config_word(struct pci_channel *hose, int top_bus,
+                                  int bus, int devfn, int offset, u16 *value);
+extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
+                                   int bus, int devfn, int offset, u32 *value);
+extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
+                                   int bus, int devfn, int offset, u8 value);
+extern int early_write_config_word(struct pci_channel *hose, int top_bus,
+                                   int bus, int devfn, int offset, u16 value);
+extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
+                                    int bus, int devfn, int offset, u32 value);
+extern void pcibios_enable_timers(struct pci_channel *hose);
+extern unsigned int pcibios_handle_status_errors(unsigned long addr,
+                                 unsigned int status, struct pci_channel *hose);
+extern int pci_is_66mhz_capable(struct pci_channel *hose,
+                                int top_bus, int current_bus);
 
 extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
 
@@ -99,20 +128,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
 
-#ifdef CONFIG_SUPERH32
-/*
- * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
- * at the end of the address space in a special non-translatable area.
- */
-#define PCI_MEM_FIXED_START     0xfd000000
-#define PCI_MEM_FIXED_END       (PCI_MEM_FIXED_START + 0x01000000)
-
-#define is_pci_memory_fixed_range(s, e) \
-        ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
-#else
-#define is_pci_memory_fixed_range(s, e) (0)
-#endif
-
 /* Board-specific fixup routines. */
 int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
 
@@ -122,6 +137,14 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev,
 extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
                                     struct pci_bus_region *region);
 
+#define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
+
+static inline int pci_proc_domain(struct pci_bus *bus)
+{
+        struct pci_channel *hose = bus->sysdata;
+        return hose->need_domain_info;
+}
+
 /* Chances are this interrupt is wired PC-style ...  */
 static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
 {
diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h
index 63ca37bd9a95..8c00785c60d5 100644
--- a/arch/sh/include/asm/pgalloc.h
+++ b/arch/sh/include/asm/pgalloc.h
@@ -4,8 +4,16 @@
 #include <linux/quicklist.h>
 #include <asm/page.h>
 
-#define QUICK_PGD 0     /* We preserve special mappings over free */
-#define QUICK_PT 1      /* Other page table pages that are zero on free */
+#define QUICK_PT 0      /* Other page table pages that are zero on free */
+
+extern pgd_t *pgd_alloc(struct mm_struct *);
+extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
+
+#if PAGETABLE_LEVELS > 2
+extern void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd);
+extern pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address);
+extern void pmd_free(struct mm_struct *mm, pmd_t *pmd);
+#endif
 
 static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
                                        pte_t *pte)
@@ -20,28 +28,9 @@ static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 }
 #define pmd_pgtable(pmd) pmd_page(pmd)
 
-static inline void pgd_ctor(void *x)
-{
-        pgd_t *pgd = x;
-
-        memcpy(pgd + USER_PTRS_PER_PGD,
-               swapper_pg_dir + USER_PTRS_PER_PGD,
-               (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
-}
-
 /*
  * Allocate and free page tables.
  */
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
-        return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-        quicklist_free(QUICK_PGD, NULL, pgd);
-}
-
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                                           unsigned long address)
 {
@@ -81,7 +70,6 @@ do {							\
 
 static inline void check_pgt_cache(void)
 {
-        quicklist_trim(QUICK_PGD, NULL, 25, 16);
         quicklist_trim(QUICK_PT, NULL, 25, 16);
 }
 
diff --git a/arch/sh/include/asm/pgtable-2level.h b/arch/sh/include/asm/pgtable-2level.h
new file mode 100644
index 000000000000..19bd89db17e7
--- /dev/null
+++ b/arch/sh/include/asm/pgtable-2level.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_SH_PGTABLE_2LEVEL_H
+#define __ASM_SH_PGTABLE_2LEVEL_H
+
+#include <asm-generic/pgtable-nopmd.h>
+
+/*
+ * traditional two-level paging structure
+ */
+#define PAGETABLE_LEVELS        2
+
+/* PTE bits */
+#define PTE_MAGNITUDE           2       /* 32-bit PTEs */
+
+#define PTE_SHIFT               PAGE_SHIFT
+#define PTE_BITS                (PTE_SHIFT - PTE_MAGNITUDE)
+
+/* PGD bits */
+#define PGDIR_SHIFT             (PTE_SHIFT + PTE_BITS)
+
+#define PTRS_PER_PGD            (PAGE_SIZE / (1 << PTE_MAGNITUDE))
+#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
+
+#endif /* __ASM_SH_PGTABLE_2LEVEL_H */
diff --git a/arch/sh/include/asm/pgtable-3level.h b/arch/sh/include/asm/pgtable-3level.h
new file mode 100644
index 000000000000..249a985d9648
--- /dev/null
+++ b/arch/sh/include/asm/pgtable-3level.h
@@ -0,0 +1,56 @@
+#ifndef __ASM_SH_PGTABLE_3LEVEL_H
+#define __ASM_SH_PGTABLE_3LEVEL_H
+
+#include <asm-generic/pgtable-nopud.h>
+
+/*
+ * Some cores need a 3-level page table layout, for example when using
+ * 64-bit PTEs and 4K pages.
+ */
+#define PAGETABLE_LEVELS        3
+
+#define PTE_MAGNITUDE           3       /* 64-bit PTEs on SH-X2 TLB */
+
+/* PGD bits */
+#define PGDIR_SHIFT             30
+
+#define PTRS_PER_PGD            4
+#define USER_PTRS_PER_PGD       2
+
+/* PMD bits */
+#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT - PTE_MAGNITUDE))
+#define PMD_SIZE        (1UL << PMD_SHIFT)
+#define PMD_MASK        (~(PMD_SIZE-1))
+
+#define PTRS_PER_PMD    ((1 << PGDIR_SHIFT) / PMD_SIZE)
+
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %016llx.\n", __FILE__, __LINE__, pmd_val(e))
+
+typedef struct { unsigned long long pmd; } pmd_t;
+#define pmd_val(x)      ((x).pmd)
+#define __pmd(x)        ((pmd_t) { (x) } )
+
+static inline unsigned long pud_page_vaddr(pud_t pud)
+{
+        return pud_val(pud);
+}
+
+#define pmd_index(address)      (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
+static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
+{
+        return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(address);
+}
+
+#define pud_none(x)     (!pud_val(x))
+#define pud_present(x)  (pud_val(x))
+#define pud_clear(xp)   do { set_pud(xp, __pud(0)); } while (0)
+#define pud_bad(x)      (pud_val(x) & ~PAGE_MASK)
+
+/*
+ * (puds are folded into pgds so this doesn't get actually called,
+ * but the define is needed for a generic inline function.)
+ */
+#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
+
+#endif /* __ASM_SH_PGTABLE_3LEVEL_H */
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index ba3046e4f06f..02f77450cd8f 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -12,7 +12,11 @@
 #ifndef __ASM_SH_PGTABLE_H
 #define __ASM_SH_PGTABLE_H
 
-#include <asm-generic/pgtable-nopmd.h>
+#ifdef CONFIG_X2TLB
+#include <asm/pgtable-3level.h>
+#else
+#include <asm/pgtable-2level.h>
+#endif
 #include <asm/page.h>
 
 #ifndef __ASSEMBLY__
@@ -51,28 +55,12 @@ static inline unsigned long long neff_sign_extend(unsigned long val)
 #define NPHYS_SIGN      (1LL << (NPHYS - 1))
 #define NPHYS_MASK      (-1LL << NPHYS)
 
-/*
- * traditional two-level paging structure
- */
-/* PTE bits */
-#if defined(CONFIG_X2TLB) || defined(CONFIG_SUPERH64)
-# define PTE_MAGNITUDE  3       /* 64-bit PTEs on extended mode SH-X2 TLB */
-#else
-# define PTE_MAGNITUDE  2       /* 32-bit PTEs */
-#endif
-#define PTE_SHIFT       PAGE_SHIFT
-#define PTE_BITS        (PTE_SHIFT - PTE_MAGNITUDE)
-
-/* PGD bits */
-#define PGDIR_SHIFT     (PTE_SHIFT + PTE_BITS)
 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 
 /* Entries per level */
 #define PTRS_PER_PTE    (PAGE_SIZE / (1 << PTE_MAGNITUDE))
-#define PTRS_PER_PGD    (PAGE_SIZE / sizeof(pgd_t))
 
-#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS      0
 
 #define PHYS_ADDR_MASK29                0x1fffffff
@@ -153,9 +141,9 @@ typedef pte_t *pte_addr_t;
 #define pte_pfn(x)              ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
 
 /*
- * No page table caches to initialise
+ * Initialise the page table caches
  */
-#define pgtable_cache_init()    do { } while (0)
+extern void pgtable_cache_init(void);
 
 struct vm_area_struct;
 
@@ -165,8 +153,9 @@ extern void __update_tlb(struct vm_area_struct *vma,
                          unsigned long address, pte_t pte);
 
 static inline void
-update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
+        pte_t pte = *ptep;
         __update_cache(vma, address, pte);
         __update_tlb(vma, address, pte);
 }
diff --git a/arch/sh/include/asm/pgtable_32.h b/arch/sh/include/asm/pgtable_32.h
index 5003ee86f67b..e172d696e52b 100644
--- a/arch/sh/include/asm/pgtable_32.h
+++ b/arch/sh/include/asm/pgtable_32.h
@@ -71,6 +71,8 @@
 #define _PAGE_EXT_KERN_WRITE    0x1000  /* EPR4-bit: Kernel space writable */
 #define _PAGE_EXT_KERN_READ     0x2000  /* EPR5-bit: Kernel space readable */
 
+#define _PAGE_EXT_WIRED         0x4000  /* software: Wire TLB entry */
+
 /* Wrapper for extended mode pgprot twiddling */
 #define _PAGE_EXT(x)            ((unsigned long long)(x) << 32)
 
@@ -141,12 +143,14 @@ static inline unsigned long copy_ptea_attributes(unsigned long x)
 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
 #  define _PAGE_SZHUGE  (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
 # endif
+# define _PAGE_WIRED    (_PAGE_EXT(_PAGE_EXT_WIRED))
 #else
 # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
 #  define _PAGE_SZHUGE  (_PAGE_SZ1)
 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
 #  define _PAGE_SZHUGE  (_PAGE_SZ0 | _PAGE_SZ1)
 # endif
+# define _PAGE_WIRED    (0)
 #endif
 
 /*
diff --git a/arch/sh/include/asm/pgtable_64.h b/arch/sh/include/asm/pgtable_64.h
index 17cdbecc3adc..0ee46776dad6 100644
--- a/arch/sh/include/asm/pgtable_64.h
+++ b/arch/sh/include/asm/pgtable_64.h
@@ -43,11 +43,6 @@ static __inline__ void set_pte(pte_t *pteptr, pte_t pteval)
 }
 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
 
-static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
-{
-        pmd_val(*pmdp) = (unsigned long) ptep;
-}
-
 /*
  * PGD defines. Top level.
  */
@@ -128,8 +123,21 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
 #define _PAGE_DIRTY     0x400  /* software: page accessed in write */
 #define _PAGE_ACCESSED  0x800  /* software: page referenced */
 
+/* Wrapper for extended mode pgprot twiddling */
+#define _PAGE_EXT(x)            ((unsigned long long)(x) << 32)
+
+/*
+ * We can use the sign-extended bits in the PTEL to get 32 bits of
+ * software flags. This works for now because no implementations uses
+ * anything above the PPN field.
+ */
+#define _PAGE_WIRED     _PAGE_EXT(0x001) /* software: wire the tlb entry */
+
+#define _PAGE_CLEAR_FLAGS       (_PAGE_PRESENT | _PAGE_FILE | _PAGE_SHARED | \
+                                 _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_WIRED)
+
 /* Mask which drops software flags */
-#define _PAGE_FLAGS_HARDWARE_MASK       0xfffffffffffff3dbLL
+#define _PAGE_FLAGS_HARDWARE_MASK       (NEFF_MASK & ~(_PAGE_CLEAR_FLAGS))
 
 /*
  * HugeTLB support
@@ -203,12 +211,6 @@ static __inline__ void pmd_set(pmd_t *pmdp,pte_t *ptep)
 #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
 
 /*
- * Handling allocation failures during page table setup.
- */
-extern void __handle_bad_pmd_kernel(pmd_t * pmd);
-#define __handle_bad_pmd(x)     __handle_bad_pmd_kernel(x)
-
-/*
  * PTE level access routines.
  *
  * Note1:
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 017e0c1807b2..9605e062840f 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -98,13 +98,34 @@ extern struct sh_cpuinfo cpu_data[];
 
 /* Forward decl */
 struct seq_operations;
+struct task_struct;
 
 extern struct pt_regs fake_swapper_regs;
 
+/* arch/sh/kernel/process.c */
+extern unsigned int xstate_size;
+extern void free_thread_xstate(struct task_struct *);
+extern struct kmem_cache *task_xstate_cachep;
+
+/* arch/sh/mm/alignment.c */
+extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
+extern int set_unalign_ctl(struct task_struct *, unsigned int val);
+
+#define GET_UNALIGN_CTL(tsk, addr)      get_unalign_ctl((tsk), (addr))
+#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
+
+/* arch/sh/mm/init.c */
+extern unsigned int mem_init_done;
+
 /* arch/sh/kernel/setup.c */
 const char *get_cpu_subtype(struct sh_cpuinfo *c);
 extern const struct seq_operations cpuinfo_op;
 
+/* thread_struct flags */
+#define SH_THREAD_UAC_NOPRINT   (1 << 0)
+#define SH_THREAD_UAC_SIGBUS    (1 << 1)
+#define SH_THREAD_UAC_MASK      (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
+
 /* processor boot mode configuration */
 #define MODE_PIN0 (1 << 0)
 #define MODE_PIN1 (1 << 1)
diff --git a/arch/sh/include/asm/processor_32.h b/arch/sh/include/asm/processor_32.h
index 1f3d6fab660c..572b4eb09493 100644
--- a/arch/sh/include/asm/processor_32.h
+++ b/arch/sh/include/asm/processor_32.h
@@ -14,6 +14,7 @@
 #include <asm/page.h>
 #include <asm/types.h>
 #include <asm/ptrace.h>
+#include <asm/hw_breakpoint.h>
 
 /*
  * Default implementation of macro that returns current
@@ -90,9 +91,9 @@ struct sh_fpu_soft_struct {
         unsigned long entry_pc;
 };
 
-union sh_fpu_union {
-        struct sh_fpu_hard_struct hard;
-        struct sh_fpu_soft_struct soft;
+union thread_xstate {
+        struct sh_fpu_hard_struct hardfpu;
+        struct sh_fpu_soft_struct softfpu;
 };
 
 struct thread_struct {
@@ -100,38 +101,30 @@ struct thread_struct {
         unsigned long sp;
         unsigned long pc;
 
-        /* Hardware debugging registers */
-        unsigned long ubc_pc;
+        /* Various thread flags, see SH_THREAD_xxx */
+        unsigned long flags;
 
-        /* floating point info */
-        union sh_fpu_union fpu;
+        /* Save middle states of ptrace breakpoints */
+        struct perf_event *ptrace_bps[HBP_NUM];
 
 #ifdef CONFIG_SH_DSP
         /* Dsp status information */
         struct sh_dsp_struct dsp_status;
 #endif
-};
 
-/* Count of active tasks with UBC settings */
-extern int ubc_usercnt;
+        /* Extended processor state */
+        union thread_xstate *xstate;
+};
 
 #define INIT_THREAD  {                                          \
         .sp = sizeof(init_stack) + (long) &init_stack,          \
+        .flags = 0,                                             \
 }
 
-/*
- * Do necessary setup to start up a newly executed thread.
- */
-#define start_thread(_regs, new_pc, new_sp)      \
-        set_fs(USER_DS);                         \
-        _regs->pr = 0;                           \
-        _regs->sr = SR_FD;      /* User mode. */ \
-        _regs->pc = new_pc;                      \
-        _regs->regs[15] = new_sp
-
 /* Forward declaration, a strange C thing */
 struct task_struct;
-struct mm_struct;
+
+extern void start_thread(struct pt_regs *regs, unsigned long new_pc, unsigned long new_sp);
 
 /* Free all resources held by a thread. */
 extern void release_thread(struct task_struct *);
diff --git a/arch/sh/include/asm/processor_64.h b/arch/sh/include/asm/processor_64.h
index 5727d31b0ccf..621bc4618c6b 100644
--- a/arch/sh/include/asm/processor_64.h
+++ b/arch/sh/include/asm/processor_64.h
@@ -87,26 +87,31 @@ struct sh_fpu_hard_struct {
         /* long status; * software status information */
 };
 
-#if 0
 /* Dummy fpu emulator  */
 struct sh_fpu_soft_struct {
-        unsigned long long fp_regs[32];
+        unsigned long fp_regs[64];
         unsigned int fpscr;
         unsigned char lookahead;
         unsigned long entry_pc;
 };
-#endif
 
-union sh_fpu_union {
-        struct sh_fpu_hard_struct hard;
-        /* 'hard' itself only produces 32 bit alignment, yet we need
-           to access it using 64 bit load/store as well. */
+union thread_xstate {
+        struct sh_fpu_hard_struct hardfpu;
+        struct sh_fpu_soft_struct softfpu;
+        /*
+         * The structure definitions only produce 32 bit alignment, yet we need
+         * to access them using 64 bit load/store as well.
+         */
         unsigned long long alignment_dummy;
 };
 
 struct thread_struct {
         unsigned long sp;
         unsigned long pc;
+
+        /* Various thread flags, see SH_THREAD_xxx */
+        unsigned long flags;
+
         /* This stores the address of the pt_regs built during a context
            switch, or of the register save area built for a kernel mode
            exception.  It is used for backtracing the stack of a sleeping task
@@ -122,7 +127,7 @@ struct thread_struct {
         /* Hardware debugging registers may come here */
 
         /* floating point info */
-        union sh_fpu_union fpu;
+        union thread_xstate *xstate;
 };
 
 #define INIT_MMAP \
@@ -137,7 +142,7 @@ struct thread_struct {
         .trap_no        = 0,                    \
         .error_code     = 0,                    \
         .address        = 0,                    \
-        .fpu            = { { { 0, } }, }       \
+        .flags          = 0,                    \
 }
 
 /*
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 1dc12cb44a2d..e11b14ea2c43 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -102,13 +102,15 @@ struct pt_dspregs {
 #define PTRACE_GETDSPREGS       55      /* DSP registers */
 #define PTRACE_SETDSPREGS       56
 
-#define PT_TEXT_END_ADDR        240
-#define PT_TEXT_ADDR            244     /* &(struct user)->start_code */
-#define PT_DATA_ADDR            248     /* &(struct user)->start_data */
+#define PT_TEXT_END_ADDR        240
+#define PT_TEXT_ADDR            244     /* &(struct user)->start_code */
+#define PT_DATA_ADDR            248     /* &(struct user)->start_data */
 #define PT_TEXT_LEN             252
 
 #ifdef __KERNEL__
 #include <asm/addrspace.h>
+#include <asm/page.h>
+#include <asm/system.h>
 
 #define user_mode(regs)                 (((regs)->sr & 0x40000000)==0)
 #define instruction_pointer(regs)       ((unsigned long)(regs)->pc)
@@ -124,6 +126,12 @@ struct task_struct;
 extern void user_enable_single_step(struct task_struct *);
 extern void user_disable_single_step(struct task_struct *);
 
+struct perf_event;
+struct perf_sample_data;
+
+extern void ptrace_triggered(struct perf_event *bp, int nmi,
+                      struct perf_sample_data *data, struct pt_regs *regs);
+
 #define task_pt_regs(task) \
         ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE) - 1)
 
@@ -131,10 +139,8 @@ static inline unsigned long profile_pc(struct pt_regs *regs)
 {
         unsigned long pc = instruction_pointer(regs);
 
-#ifdef P2SEG
-        if (pc >= P2SEG && pc < P3SEG)
-                pc -= 0x20000000;
-#endif
+        if (virt_addr_uncached(pc))
+                return CAC_ADDR(pc);
 
         return pc;
 }
diff --git a/arch/sh/include/asm/reboot.h b/arch/sh/include/asm/reboot.h
new file mode 100644
index 000000000000..b3da0c63fc3d
--- /dev/null
+++ b/arch/sh/include/asm/reboot.h
@@ -0,0 +1,21 @@
+#ifndef __ASM_SH_REBOOT_H
+#define __ASM_SH_REBOOT_H
+
+#include <linux/kdebug.h>
+
+struct pt_regs;
+
+struct machine_ops {
+        void (*restart)(char *cmd);
+        void (*halt)(void);
+        void (*power_off)(void);
+        void (*shutdown)(void);
+        void (*crash_shutdown)(struct pt_regs *);
+};
+
+extern struct machine_ops machine_ops;
+
+/* arch/sh/kernel/machine_kexec.c */
+void native_machine_crash_shutdown(struct pt_regs *regs);
+
+#endif /* __ASM_SH_REBOOT_H */
diff --git a/arch/sh/include/asm/setup.h b/arch/sh/include/asm/setup.h
index ce3743599b27..4758325bb24a 100644
--- a/arch/sh/include/asm/setup.h
+++ b/arch/sh/include/asm/setup.h
@@ -18,7 +18,6 @@
 /* ... */
 #define COMMAND_LINE ((char *) (PARAM+0x100))
 
-int setup_early_printk(char *);
 void sh_mv_setup(void);
 
 #endif /* __KERNEL__ */
diff --git a/arch/sh/include/asm/sh_bios.h b/arch/sh/include/asm/sh_bios.h
index d9c96d7cf6c7..95714c28422b 100644
--- a/arch/sh/include/asm/sh_bios.h
+++ b/arch/sh/include/asm/sh_bios.h
@@ -1,18 +1,27 @@
 #ifndef __ASM_SH_BIOS_H
 #define __ASM_SH_BIOS_H
 
+#ifdef CONFIG_SH_STANDARD_BIOS
+
 /*
  * Copyright (C) 2000 Greg Banks, Mitch Davis
  * C API to interface to the standard LinuxSH BIOS
  * usually from within the early stages of kernel boot.
  */
-
-
 extern void sh_bios_console_write(const char *buf, unsigned int len);
-extern void sh_bios_char_out(char ch);
 extern void sh_bios_gdb_detach(void);
 
 extern void sh_bios_get_node_addr(unsigned char *node_addr);
 extern void sh_bios_shutdown(unsigned int how);
 
+extern void sh_bios_vbr_init(void);
+extern void sh_bios_vbr_reload(void);
+
+#else
+
+static inline void sh_bios_vbr_init(void) { }
+static inline void sh_bios_vbr_reload(void) { }
+
+#endif /* CONFIG_SH_STANDARD_BIOS */
+
 #endif /* __ASM_SH_BIOS_H */
diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h
new file mode 100644
index 000000000000..57565a3b551f
--- /dev/null
+++ b/arch/sh/include/asm/siu.h
@@ -0,0 +1,26 @@
+/*
+ * platform header for the SIU ASoC driver
+ *
+ * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_SIU_H
+#define ASM_SIU_H
+
+#include <asm/dma-sh.h>
+
+struct device;
+
+struct siu_platform {
+        struct device *dma_dev;
+        enum sh_dmae_slave_chan_id dma_slave_tx_a;
+        enum sh_dmae_slave_chan_id dma_slave_rx_a;
+        enum sh_dmae_slave_chan_id dma_slave_tx_b;
+        enum sh_dmae_slave_chan_id dma_slave_rx_b;
+};
+
+#endif /* ASM_SIU_H */
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
index fe9c2a1ad047..64eb41a063e8 100644
--- a/arch/sh/include/asm/suspend.h
+++ b/arch/sh/include/asm/suspend.h
@@ -92,5 +92,6 @@ extern unsigned long sh_mobile_sleep_supported;
 #define SUSP_SH_USTANDBY        (1 << 3) /* SH-Mobile U-standby mode */
 #define SUSP_SH_SF              (1 << 4) /* Enable self-refresh */
 #define SUSP_SH_MMU             (1 << 5) /* Save/restore MMU and cache */
+#define SUSP_SH_REGS            (1 << 6) /* Save/restore registers */
 
 #endif /* _ASM_SH_SUSPEND_H */
diff --git a/arch/sh/include/asm/syscall.h b/arch/sh/include/asm/syscall.h
index 6a381429ee9d..aa7777bdc370 100644
--- a/arch/sh/include/asm/syscall.h
+++ b/arch/sh/include/asm/syscall.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_SH_SYSCALL_H
 #define __ASM_SH_SYSCALL_H
 
+extern const unsigned long sys_call_table[];
+
 #ifdef CONFIG_SUPERH32
 # include "syscall_32.h"
 #else
diff --git a/arch/sh/include/asm/system.h b/arch/sh/include/asm/system.h
index c15415b4b169..0bd7a17d5e1a 100644
--- a/arch/sh/include/asm/system.h
+++ b/arch/sh/include/asm/system.h
@@ -10,7 +10,6 @@
 #include <linux/compiler.h>
 #include <linux/linkage.h>
 #include <asm/types.h>
-#include <asm/ptrace.h>
 
 #define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
 
@@ -32,7 +31,7 @@
 #define mb()            __asm__ __volatile__ ("synco": : :"memory")
 #define rmb()           mb()
 #define wmb()           __asm__ __volatile__ ("synco": : :"memory")
-#define ctrl_barrier()  __icbi(0xa8000000)
+#define ctrl_barrier()  __icbi(PAGE_OFFSET)
 #define read_barrier_depends()  do { } while(0)
 #else
 #define mb()            __asm__ __volatile__ ("": : :"memory")
@@ -114,6 +113,8 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
                                     (unsigned long)_n_, sizeof(*(ptr))); \
   })
 
+struct pt_regs;
+
 extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
 void free_initmem(void);
 void free_initrd_mem(unsigned long start, unsigned long end);
@@ -137,14 +138,14 @@ extern unsigned int instruction_size(unsigned int insn);
 #endif
 
 extern unsigned long cached_to_uncached;
+extern unsigned long uncached_size;
 
 extern struct dentry *sh_debugfs_root;
 
 void per_cpu_trap_init(void);
 void default_idle(void);
 void cpu_idle_wait(void);
-
-asmlinkage void break_point_trap(void);
+void stop_this_cpu(void *);
 
 #ifdef CONFIG_SUPERH32
 #define BUILD_TRAP_HANDLER(name)                                        \
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 06814f5b59c7..51296b36770e 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -2,6 +2,7 @@
 #define __ASM_SH_SYSTEM_32_H
 
 #include <linux/types.h>
+#include <asm/mmu.h>
 
 #ifdef CONFIG_SH_DSP
 
@@ -144,9 +145,6 @@ do {								\
                 __restore_dsp(prev);                            \
 } while (0)
 
-#define __uses_jump_to_uncached \
-        noinline __attribute__ ((__section__ (".uncached.text")))
-
 /*
  * Jump to uncached area.
  * When handling TLB or caches, we need to do it from an uncached area.
@@ -216,6 +214,17 @@ static inline reg_size_t register_align(void *val)
 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
                             struct mem_access *ma, int);
 
+static inline void trigger_address_error(void)
+{
+        if (__in_29bit_mode())
+                __asm__ __volatile__ (
+                        "ldc %0, sr\n\t"
+                        "mov.l @%1, %0"
+                        :
+                        : "r" (0x10000000), "r" (0x80000001)
+                );
+}
+
 asmlinkage void do_address_error(struct pt_regs *regs,
                                  unsigned long writeaccess,
                                  unsigned long address);
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
index ab1dd917ea87..36338646dfc8 100644
--- a/arch/sh/include/asm/system_64.h
+++ b/arch/sh/include/asm/system_64.h
@@ -18,6 +18,7 @@
 /*
  *      switch_to() should switch tasks to task nr n, first
  */
+struct thread_struct;
 struct task_struct *sh64_switch_to(struct task_struct *prev,
                                    struct thread_struct *prev_thread,
                                    struct task_struct *next,
@@ -33,8 +34,6 @@ do {								\
                               &next->thread);                   \
 } while (0)
 
-#define __uses_jump_to_uncached
-
 #define jump_to_uncached()      do { } while (0)
 #define back_to_cached()        do { } while (0)
 
@@ -48,6 +47,13 @@ static inline reg_size_t register_align(void *val)
         return (unsigned long long)(signed long long)(signed long)val;
 }
 
+extern void phys_stext(void);
+
+static inline void trigger_address_error(void)
+{
+        phys_stext();
+}
+
 #define SR_BL_LL        0x0000000010000000LL
 
 static inline void set_bl_bit(void)
diff --git a/arch/sh/include/asm/thread_info.h b/arch/sh/include/asm/thread_info.h
index 1f3d927e2265..55a36fef6875 100644
--- a/arch/sh/include/asm/thread_info.h
+++ b/arch/sh/include/asm/thread_info.h
@@ -93,14 +93,16 @@ static inline struct thread_info *current_thread_info(void)
 
 #define THREAD_SIZE_ORDER       (THREAD_SHIFT - PAGE_SHIFT)
 
-#else /* THREAD_SHIFT < PAGE_SHIFT */
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
+#endif
 
 extern struct thread_info *alloc_thread_info(struct task_struct *tsk);
 extern void free_thread_info(struct thread_info *ti);
+extern void arch_task_cache_init(void);
+#define arch_task_cache_init arch_task_cache_init
+extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
+extern void init_thread_xstate(void);
 
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
+#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
index da8fe7ab8728..75abb38dffd5 100644
--- a/arch/sh/include/asm/tlb.h
+++ b/arch/sh/include/asm/tlb.h
@@ -11,6 +11,7 @@
 #ifdef CONFIG_MMU
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
+#include <asm/mmu_context.h>
 
 /*
  * TLB handling.  This allows us to remove pages from the page
@@ -97,6 +98,22 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 
 #define tlb_migrate_finish(mm)          do { } while (0)
 
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SUPERH64)
+extern void tlb_wire_entry(struct vm_area_struct *, unsigned long, pte_t);
+extern void tlb_unwire_entry(void);
+#else
+static inline void tlb_wire_entry(struct vm_area_struct *vma ,
+                                  unsigned long addr, pte_t pte)
+{
+        BUG();
+}
+
+static inline void tlb_unwire_entry(void)
+{
+        BUG();
+}
+#endif
+
 #else /* CONFIG_MMU */
 
 #define tlb_start_vma(tlb, vma)                         do { } while (0)
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
deleted file mode 100644
index 9bf961684431..000000000000
--- a/arch/sh/include/asm/ubc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * include/asm-sh/ubc.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- * Copyright (C) 2002, 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_SH_UBC_H
-#define __ASM_SH_UBC_H
-#ifdef __KERNEL__
-
-#include <cpu/ubc.h>
-
-/* User Break Controller */
-#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
-#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
-#else
-#define UBC_TYPE_SH7729 0
-#endif
-
-#define BAMR_ASID               (1 << 2)
-#define BAMR_NONE               0
-#define BAMR_10                 0x1
-#define BAMR_12                 0x2
-#define BAMR_ALL                0x3
-#define BAMR_16                 0x8
-#define BAMR_20                 0x9
-
-#define BBR_INST                (1 << 4)
-#define BBR_DATA                (2 << 4)
-#define BBR_READ                (1 << 2)
-#define BBR_WRITE               (2 << 2)
-#define BBR_BYTE                0x1
-#define BBR_HALF                0x2
-#define BBR_LONG                0x3
-#define BBR_QUAD                (1 << 6)        /* SH7750 */
-#define BBR_CPU                 (1 << 6)        /* SH7709A,SH7729 */
-#define BBR_DMA                 (2 << 6)        /* SH7709A,SH7729 */
-
-#define BRCR_CMFA               (1 << 15)
-#define BRCR_CMFB               (1 << 14)
-
-#if defined CONFIG_CPU_SH2A
-#define BRCR_CMFCA              (1 << 15)
-#define BRCR_CMFCB              (1 << 14)
-#define BRCR_CMFDA              (1 << 13)
-#define BRCR_CMFDB              (1 << 12)
-#define BRCR_PCBB               (1 << 6)        /* 1: after execution */
-#define BRCR_PCBA               (1 << 5)        /* 1: after execution */
-#define BRCR_PCTE               0
-#else
-#define BRCR_PCTE               (1 << 11)
-#define BRCR_PCBA               (1 << 10)       /* 1: after execution */
-#define BRCR_DBEB               (1 << 7)
-#define BRCR_PCBB               (1 << 6)
-#define BRCR_SEQ                (1 << 3)
-#define BRCR_UBDE               (1 << 0)
-#endif
-
-#endif /* __KERNEL__ */
-#endif /* __ASM_SH_UBC_H */
diff --git a/arch/sh/include/asm/uncached.h b/arch/sh/include/asm/uncached.h
new file mode 100644
index 000000000000..e3419f96626a
--- /dev/null
+++ b/arch/sh/include/asm/uncached.h
@@ -0,0 +1,18 @@
+#ifndef __ASM_SH_UNCACHED_H
+#define __ASM_SH_UNCACHED_H
+
+#include <linux/bug.h>
+
+#ifdef CONFIG_UNCACHED_MAPPING
+extern unsigned long uncached_start, uncached_end;
+
+extern int virt_addr_uncached(unsigned long kaddr);
+extern void uncached_init(void);
+extern void uncached_resize(unsigned long size);
+#else
+#define virt_addr_uncached(kaddr)       (0)
+#define uncached_init()                 do { } while (0)
+#define uncached_resize(size)           BUG()
+#endif
+
+#endif /* __ASM_SH_UNCACHED_H */
diff --git a/arch/sh/include/asm/vmlinux.lds.h b/arch/sh/include/asm/vmlinux.lds.h
index 244ec4ad9a79..d58ad493b3a6 100644
--- a/arch/sh/include/asm/vmlinux.lds.h
+++ b/arch/sh/include/asm/vmlinux.lds.h
@@ -14,4 +14,12 @@
 #define DWARF_EH_FRAME
 #endif
 
+#ifdef CONFIG_SUPERH64
+#define EXTRA_TEXT              \
+        *(.text64)              \
+        *(.text..SHmedia32)
+#else
+#define EXTRA_TEXT
+#endif
+
 #endif /* __ASM_SH_VMLINUX_LDS_H */
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
index 19dfff5c8511..85a7aca7fb8f 100644
--- a/arch/sh/include/asm/watchdog.h
+++ b/arch/sh/include/asm/watchdog.h
@@ -70,7 +70,7 @@
  */
 static inline __u32 sh_wdt_read_cnt(void)
 {
-        return ctrl_inl(WTCNT_R);
+        return __raw_readl(WTCNT_R);
 }
 
 /**
@@ -82,7 +82,7 @@ static inline __u32 sh_wdt_read_cnt(void)
  */
 static inline void sh_wdt_write_cnt(__u32 val)
 {
-        ctrl_outl((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
+        __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
 }
 
 /**
@@ -94,7 +94,7 @@ static inline void sh_wdt_write_cnt(__u32 val)
  */
 static inline void sh_wdt_write_bst(__u32 val)
 {
-        ctrl_outl((WTBST_HIGH << 24) | (__u32)val, WTBST);
+        __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
 }
 /**
  *      sh_wdt_read_csr - Read from Control/Status Register
@@ -103,7 +103,7 @@ static inline void sh_wdt_write_bst(__u32 val)
  */
 static inline __u32 sh_wdt_read_csr(void)
 {
-        return ctrl_inl(WTCSR_R);
+        return __raw_readl(WTCSR_R);
 }
 
 /**
@@ -115,7 +115,7 @@ static inline __u32 sh_wdt_read_csr(void)
  */
 static inline void sh_wdt_write_csr(__u32 val)
 {
-        ctrl_outl((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
+        __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
 }
 #else
 /**
@@ -124,7 +124,7 @@ static inline void sh_wdt_write_csr(__u32 val)
  */
 static inline __u8 sh_wdt_read_cnt(void)
 {
-        return ctrl_inb(WTCNT_R);
+        return __raw_readb(WTCNT_R);
 }
 
 /**
@@ -136,7 +136,7 @@ static inline __u8 sh_wdt_read_cnt(void)
  */
 static inline void sh_wdt_write_cnt(__u8 val)
 {
-        ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
+        __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
 }
 
 /**
@@ -146,7 +146,7 @@ static inline void sh_wdt_write_cnt(__u8 val)
  */
 static inline __u8 sh_wdt_read_csr(void)
 {
-        return ctrl_inb(WTCSR_R);
+        return __raw_readb(WTCSR_R);
 }
 
 /**
@@ -158,7 +158,7 @@ static inline __u8 sh_wdt_read_csr(void)
  */
 static inline void sh_wdt_write_csr(__u8 val)
 {
-        ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
+        __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
 }
 #endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
 #endif /* __KERNEL__ */
diff --git a/arch/sh/include/cpu-sh2/cpu/ubc.h b/arch/sh/include/cpu-sh2/cpu/ubc.h
deleted file mode 100644
index ba0e87f19c7a..000000000000
--- a/arch/sh/include/cpu-sh2/cpu/ubc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-sh/cpu-sh2/ubc.h
- *
- * Copyright (C) 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH2_UBC_H
-#define __ASM_CPU_SH2_UBC_H
-
-#define UBC_BARA                0xffffff40
-#define UBC_BAMRA               0xffffff44
-#define UBC_BBRA                0xffffff48
-#define UBC_BARB                0xffffff60
-#define UBC_BAMRB               0xffffff64
-#define UBC_BBRB                0xffffff68
-#define UBC_BDRB                0xffffff70
-#define UBC_BDMRB               0xffffff74
-#define UBC_BRCR                0xffffff78
-
-/*
- * We don't have any ASID changes to make in the UBC on the SH-2.
- *
- * Make these purposely invalid to track misuse.
- */
-#define UBC_BASRA               0x00000000
-#define UBC_BASRB               0x00000000
-
-#endif /* __ASM_CPU_SH2_UBC_H */
-
diff --git a/arch/sh/include/cpu-sh2/cpu/watchdog.h b/arch/sh/include/cpu-sh2/cpu/watchdog.h
index 393161c9c6d0..1eab8aa63a6d 100644
--- a/arch/sh/include/cpu-sh2/cpu/watchdog.h
+++ b/arch/sh/include/cpu-sh2/cpu/watchdog.h
@@ -44,7 +44,7 @@ static inline __u8 sh_wdt_read_rstcsr(void)
         /*
          * Same read/write brain-damage as for WTCNT here..
          */
-        return ctrl_inb(RSTCSR_R);
+        return __raw_readb(RSTCSR_R);
 }
 
 /**
@@ -62,7 +62,7 @@ static inline void sh_wdt_write_rstcsr(__u8 val)
          * we can't presently touch the WOVF bit, since the upper byte
          * has to be swapped for this. So just leave it alone..
          */
-        ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
+        __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
 }
 
 #endif /* __ASM_CPU_SH2_WATCHDOG_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dac.h b/arch/sh/include/cpu-sh3/cpu/dac.h
index 05fda8316ebc..98f1d15f0ab5 100644
--- a/arch/sh/include/cpu-sh3/cpu/dac.h
+++ b/arch/sh/include/cpu-sh3/cpu/dac.h
@@ -17,25 +17,25 @@
 static __inline__ void sh_dac_enable(int channel)
 {
         unsigned char v;
-        v = ctrl_inb(DACR);
+        v = __raw_readb(DACR);
         if(channel) v |= DACR_DAOE1;
         else v |= DACR_DAOE0;
-        ctrl_outb(v,DACR);
+        __raw_writeb(v,DACR);
 }
 
 static __inline__ void sh_dac_disable(int channel)
 {
         unsigned char v;
-        v = ctrl_inb(DACR);
+        v = __raw_readb(DACR);
         if(channel) v &= ~DACR_DAOE1;
         else v &= ~DACR_DAOE0;
-        ctrl_outb(v,DACR);
+        __raw_writeb(v,DACR);
 }
 
 static __inline__ void sh_dac_output(u8 value, int channel)
 {
-        if(channel) ctrl_outb(value,DADR1);
-        else ctrl_outb(value,DADR0);
+        if(channel) __raw_writeb(value,DADR1);
+        else __raw_writeb(value,DADR0);
 }
 
 #endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 0ea15f3f2363..207811a7a650 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -20,8 +20,10 @@
 #define TS_32           0x00000010
 #define TS_128          0x00000018
 
-#define CHCR_TS_MASK    0x18
-#define CHCR_TS_SHIFT   3
+#define CHCR_TS_LOW_MASK        0x18
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
 
 #define DMAOR_INIT      DMAOR_DME
 
@@ -36,11 +38,13 @@ enum {
         XMIT_SZ_128BIT,
 };
 
-static unsigned int ts_shift[] __maybe_unused = {
-        [XMIT_SZ_8BIT]          = 0,
-        [XMIT_SZ_16BIT]         = 1,
-        [XMIT_SZ_32BIT]         = 2,
-        [XMIT_SZ_128BIT]        = 4,
-};
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_128BIT]        = 4,    \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
 
 #endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/ubc.h b/arch/sh/include/cpu-sh3/cpu/ubc.h
deleted file mode 100644
index 4e6381d5ff7a..000000000000
--- a/arch/sh/include/cpu-sh3/cpu/ubc.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * include/asm-sh/cpu-sh3/ubc.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- * Copyright (C) 2003 Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH3_UBC_H
-#define __ASM_CPU_SH3_UBC_H
-
-#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7720) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7721)
-#define UBC_BARA                0xa4ffffb0
-#define UBC_BAMRA               0xa4ffffb4
-#define UBC_BBRA                0xa4ffffb8
-#define UBC_BASRA               0xffffffe4
-#define UBC_BARB                0xa4ffffa0
-#define UBC_BAMRB               0xa4ffffa4
-#define UBC_BBRB                0xa4ffffa8
-#define UBC_BASRB               0xffffffe8
-#define UBC_BDRB                0xa4ffff90
-#define UBC_BDMRB               0xa4ffff94
-#define UBC_BRCR                0xa4ffff98
-#else
-#define UBC_BARA                0xffffffb0
-#define UBC_BAMRA               0xffffffb4
-#define UBC_BBRA                0xffffffb8
-#define UBC_BASRA               0xffffffe4
-#define UBC_BARB                0xffffffa0
-#define UBC_BAMRB               0xffffffa4
-#define UBC_BBRB                0xffffffa8
-#define UBC_BASRB               0xffffffe8
-#define UBC_BDRB                0xffffff90
-#define UBC_BDMRB               0xffffff94
-#define UBC_BRCR                0xffffff98
-#endif
-
-#endif /* __ASM_CPU_SH3_UBC_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/addrspace.h b/arch/sh/include/cpu-sh4/cpu/addrspace.h
index a3fa733c1c7d..d51da25da72c 100644
--- a/arch/sh/include/cpu-sh4/cpu/addrspace.h
+++ b/arch/sh/include/cpu-sh4/cpu/addrspace.h
@@ -28,6 +28,15 @@
 #define P4SEG_TLB_DATA  0xf7000000
 #define P4SEG_REG_BASE  0xff000000
 
+#define PA_AREA0        0x00000000
+#define PA_AREA1        0x04000000
+#define PA_AREA2        0x08000000
+#define PA_AREA3        0x0c000000
+#define PA_AREA4        0x10000000
+#define PA_AREA5        0x14000000
+#define PA_AREA6        0x18000000
+#define PA_AREA7        0x1c000000
+
 #define PA_AREA5_IO     0xb4000000      /* Area 5 IO Memory */
 #define PA_AREA6_IO     0xb8000000      /* Area 6 IO Memory */
 
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
index c4ed660c14cf..e734ea47d8a0 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -2,22 +2,38 @@
 #define __ASM_SH_CPU_SH4_DMA_SH7780_H
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
-        defined(CONFIG_CPU_SUBTYPE_SH7722) || \
         defined(CONFIG_CPU_SUBTYPE_SH7730)
 #define DMTE0_IRQ       48
 #define DMTE4_IRQ       76
 #define DMAE0_IRQ       78      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
-#define SH_DMARS_BASE   0xFE009000
+#define SH_DMARS_BASE0  0xFE009000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
+#define DMTE0_IRQ       48
+#define DMTE4_IRQ       76
+#define DMAE0_IRQ       78      /* DMA Error IRQ*/
+#define SH_DMAC_BASE0   0xFE008020
+#define SH_DMARS_BASE0  0xFE009000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0x00300000
+#define CHCR_TS_HIGH_SHIFT      20
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
         defined(CONFIG_CPU_SUBTYPE_SH7764)
 #define DMTE0_IRQ       34
 #define DMTE4_IRQ       44
 #define DMAE0_IRQ       38
 #define SH_DMAC_BASE0   0xFF608020
-#define SH_DMARS_BASE   0xFF609000
-#elif defined(CONFIG_CPU_SUBTYPE_SH7723) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define SH_DMARS_BASE0  0xFF609000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 #define DMTE0_IRQ       48      /* DMAC0A*/
 #define DMTE4_IRQ       76      /* DMAC0B */
 #define DMTE6_IRQ       40
@@ -29,7 +45,29 @@
 #define DMAE1_IRQ       74      /* DMA Error IRQ*/
 #define SH_DMAC_BASE0   0xFE008020
 #define SH_DMAC_BASE1   0xFDC08020
-#define SH_DMARS_BASE   0xFDC09000
+#define SH_DMARS_BASE0  0xFDC09000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
+#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
+#define DMTE0_IRQ       48      /* DMAC0A*/
+#define DMTE4_IRQ       76      /* DMAC0B */
+#define DMTE6_IRQ       40
+#define DMTE8_IRQ       42      /* DMAC1A */
+#define DMTE9_IRQ       43
+#define DMTE10_IRQ      72      /* DMAC1B */
+#define DMTE11_IRQ      73
+#define DMAE0_IRQ       78      /* DMA Error IRQ*/
+#define DMAE1_IRQ       74      /* DMA Error IRQ*/
+#define SH_DMAC_BASE0   0xFE008020
+#define SH_DMAC_BASE1   0xFDC08020
+#define SH_DMARS_BASE0  0xFE009000
+#define SH_DMARS_BASE1  0xFDC09000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0x00600000
+#define CHCR_TS_HIGH_SHIFT      21
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define DMTE0_IRQ       34
 #define DMTE4_IRQ       44
@@ -41,7 +79,11 @@
 #define DMAE0_IRQ       38      /* DMA Error IRQ */
 #define SH_DMAC_BASE0   0xFC808020
 #define SH_DMAC_BASE1   0xFC818020
-#define SH_DMARS_BASE   0xFC809000
+#define SH_DMARS_BASE0  0xFC809000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
 #else /* SH7785 */
 #define DMTE0_IRQ       33
 #define DMTE4_IRQ       37
@@ -54,18 +96,17 @@
 #define DMAE1_IRQ       58      /* DMA Error IRQ1 */
 #define SH_DMAC_BASE0   0xFC808020
 #define SH_DMAC_BASE1   0xFCC08020
-#define SH_DMARS_BASE   0xFC809000
+#define SH_DMARS_BASE0  0xFC809000
+#define CHCR_TS_LOW_MASK        0x00000018
+#define CHCR_TS_LOW_SHIFT       3
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
 #endif
 
-#define REQ_HE  0x000000C0
-#define REQ_H   0x00000080
-#define REQ_LE  0x00000040
-#define TM_BURST 0x0000020
-#define TS_8    0x00000000
-#define TS_16   0x00000008
-#define TS_32   0x00000010
-#define TS_16BLK        0x00000018
-#define TS_32BLK        0x00100000
+#define REQ_HE          0x000000C0
+#define REQ_H           0x00000080
+#define REQ_LE          0x00000040
+#define TM_BURST        0x00000020
 
 /*
  * The SuperH DMAC supports a number of transmit sizes, we list them here,
@@ -74,22 +115,31 @@
  * Defaults to a 64-bit transfer size.
  */
 enum {
-        XMIT_SZ_8BIT,
-        XMIT_SZ_16BIT,
-        XMIT_SZ_32BIT,
-        XMIT_SZ_128BIT,
-        XMIT_SZ_256BIT,
+        XMIT_SZ_8BIT            = 0,
+        XMIT_SZ_16BIT           = 1,
+        XMIT_SZ_32BIT           = 2,
+        XMIT_SZ_64BIT           = 7,
+        XMIT_SZ_128BIT          = 3,
+        XMIT_SZ_256BIT          = 4,
+        XMIT_SZ_128BIT_BLK      = 0xb,
+        XMIT_SZ_256BIT_BLK      = 0xc,
 };
 
 /*
  * The DMA count is defined as the number of bytes to transfer.
  */
-static unsigned int ts_shift[] __maybe_unused = {
-        [XMIT_SZ_8BIT]          = 0,
-        [XMIT_SZ_16BIT]         = 1,
-        [XMIT_SZ_32BIT]         = 2,
-        [XMIT_SZ_128BIT]        = 4,
-        [XMIT_SZ_256BIT]        = 5,
-};
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_64BIT]         = 3,    \
+        [XMIT_SZ_128BIT]        = 4,    \
+        [XMIT_SZ_256BIT]        = 5,    \
+        [XMIT_SZ_128BIT_BLK]    = 4,    \
+        [XMIT_SZ_256BIT_BLK]    = 5,    \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
+                         ((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
 
 #endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index bcb30246e85c..114a369705bc 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -6,8 +6,6 @@
 #ifdef CONFIG_CPU_SH4A
 
 #define DMAOR_INIT      (DMAOR_DME)
-#define CHCR_TS_MASK    0x18
-#define CHCR_TS_SHIFT   3
 
 #include <cpu/dma-sh4a.h>
 #else /* CONFIG_CPU_SH4A */
@@ -29,8 +27,10 @@
 #define TS_32           0x00000030
 #define TS_64           0x00000000
 
-#define CHCR_TS_MASK    0x70
-#define CHCR_TS_SHIFT   4
+#define CHCR_TS_LOW_MASK        0x70
+#define CHCR_TS_LOW_SHIFT       4
+#define CHCR_TS_HIGH_MASK       0
+#define CHCR_TS_HIGH_SHIFT      0
 
 #define DMAOR_COD       0x00000008
 
@@ -41,23 +41,26 @@
  * Defaults to a 64-bit transfer size.
  */
 enum {
-        XMIT_SZ_64BIT,
-        XMIT_SZ_8BIT,
-        XMIT_SZ_16BIT,
-        XMIT_SZ_32BIT,
-        XMIT_SZ_256BIT,
+        XMIT_SZ_8BIT    = 1,
+        XMIT_SZ_16BIT   = 2,
+        XMIT_SZ_32BIT   = 3,
+        XMIT_SZ_64BIT   = 0,
+        XMIT_SZ_256BIT  = 4,
 };
 
 /*
  * The DMA count is defined as the number of bytes to transfer.
  */
-static unsigned int ts_shift[] __maybe_unused = {
-        [XMIT_SZ_64BIT]         = 3,
-        [XMIT_SZ_8BIT]          = 0,
-        [XMIT_SZ_16BIT]         = 1,
-        [XMIT_SZ_32BIT]         = 2,
-        [XMIT_SZ_256BIT]        = 5,
-};
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_64BIT]         = 3,    \
+        [XMIT_SZ_256BIT]        = 5,    \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
+
 #endif
 
 #endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/mmu_context.h b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
index 3ce7ef6c2978..03ea75c5315d 100644
--- a/arch/sh/include/cpu-sh4/cpu/mmu_context.h
+++ b/arch/sh/include/cpu-sh4/cpu/mmu_context.h
@@ -25,6 +25,10 @@
 
 #define MMUCR_TI                (1<<2)
 
+#define MMUCR_URB               0x00FC0000
+#define MMUCR_URB_SHIFT         18
+#define MMUCR_URB_NENTRIES      64
+
 #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
 #define MMUCR_SE                (1 << 4)
 #else
diff --git a/arch/sh/include/cpu-sh4/cpu/sq.h b/arch/sh/include/cpu-sh4/cpu/sq.h
index 586d6491816a..74716ba2dc3c 100644
--- a/arch/sh/include/cpu-sh4/cpu/sq.h
+++ b/arch/sh/include/cpu-sh4/cpu/sq.h
@@ -12,6 +12,7 @@
 #define __ASM_CPU_SH4_SQ_H
 
 #include <asm/addrspace.h>
+#include <asm/page.h>
 
 /*
  * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
@@ -28,7 +29,7 @@
 
 /* arch/sh/kernel/cpu/sh4/sq.c */
 unsigned long sq_remap(unsigned long phys, unsigned int size,
-                       const char *name, unsigned long flags);
+                       const char *name, pgprot_t prot);
 void sq_unmap(unsigned long vaddr);
 void sq_flush_range(unsigned long start, unsigned int len);
 
diff --git a/arch/sh/include/cpu-sh4/cpu/ubc.h b/arch/sh/include/cpu-sh4/cpu/ubc.h
deleted file mode 100644
index c86e17050935..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/ubc.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * include/asm-sh/cpu-sh4/ubc.h
- *
- * Copyright (C) 1999 Niibe Yutaka
- * Copyright (C) 2003 Paul Mundt
- * Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_CPU_SH4_UBC_H
-#define __ASM_CPU_SH4_UBC_H
-
-#if defined(CONFIG_CPU_SH4A)
-#define UBC_CBR0                0xff200000
-#define UBC_CRR0                0xff200004
-#define UBC_CAR0                0xff200008
-#define UBC_CAMR0               0xff20000c
-#define UBC_CBR1                0xff200020
-#define UBC_CRR1                0xff200024
-#define UBC_CAR1                0xff200028
-#define UBC_CAMR1               0xff20002c
-#define UBC_CDR1                0xff200030
-#define UBC_CDMR1               0xff200034
-#define UBC_CETR1               0xff200038
-#define UBC_CCMFR               0xff200600
-#define UBC_CBCR                0xff200620
-
-/* CBR  */
-#define UBC_CBR_AIE             (0x01<<30)
-#define UBC_CBR_ID_INST         (0x01<<4)
-#define UBC_CBR_RW_READ         (0x01<<1)
-#define UBC_CBR_CE              (0x01)
-
-#define UBC_CBR_AIV_MASK        (0x00FF0000)
-#define UBC_CBR_AIV_SHIFT       (16)
-#define UBC_CBR_AIV_SET(asid)   (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
-
-#define UBC_CBR_INIT            0x20000000
-
-/* CRR  */
-#define UBC_CRR_RES             (0x01<<13)
-#define UBC_CRR_PCB             (0x01<<1)
-#define UBC_CRR_BIE             (0x01)
-
-#define UBC_CRR_INIT            0x00002000
-
-#else   /* CONFIG_CPU_SH4 */
-#define UBC_BARA                0xff200000
-#define UBC_BAMRA               0xff200004
-#define UBC_BBRA                0xff200008
-#define UBC_BASRA               0xff000014
-#define UBC_BARB                0xff20000c
-#define UBC_BAMRB               0xff200010
-#define UBC_BBRB                0xff200014
-#define UBC_BASRB               0xff000018
-#define UBC_BDRB                0xff200018
-#define UBC_BDMRB               0xff20001c
-#define UBC_BRCR                0xff200020
-#endif  /* CONFIG_CPU_SH4 */
-
-#endif /* __ASM_CPU_SH4_UBC_H */
-
diff --git a/arch/sh/include/mach-common/mach/magicpanelr2.h b/arch/sh/include/mach-common/mach/magicpanelr2.h
index c644a77ee357..183a2f744251 100644
--- a/arch/sh/include/mach-common/mach/magicpanelr2.h
+++ b/arch/sh/include/mach-common/mach/magicpanelr2.h
@@ -19,12 +19,12 @@
 #include <asm/io_generic.h>
 
 
-#define SETBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) | mask, reg)
-#define SETBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) | mask, reg)
-#define SETBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) | mask, reg)
-#define CLRBITS_OUTB(mask, reg)   ctrl_outb(ctrl_inb(reg) & ~mask, reg)
-#define CLRBITS_OUTW(mask, reg)   ctrl_outw(ctrl_inw(reg) & ~mask, reg)
-#define CLRBITS_OUTL(mask, reg)   ctrl_outl(ctrl_inl(reg) & ~mask, reg)
+#define SETBITS_OUTB(mask, reg)   __raw_writeb(__raw_readb(reg) | mask, reg)
+#define SETBITS_OUTW(mask, reg)   __raw_writew(__raw_readw(reg) | mask, reg)
+#define SETBITS_OUTL(mask, reg)   __raw_writel(__raw_readl(reg) | mask, reg)
+#define CLRBITS_OUTB(mask, reg)   __raw_writeb(__raw_readb(reg) & ~mask, reg)
+#define CLRBITS_OUTW(mask, reg)   __raw_writew(__raw_readw(reg) & ~mask, reg)
+#define CLRBITS_OUTL(mask, reg)   __raw_writel(__raw_readl(reg) & ~mask, reg)
 
 
 #define PA_LED          PORT_PADR      /* LED */
diff --git a/arch/sh/include/mach-dreamcast/mach/sysasic.h b/arch/sh/include/mach-dreamcast/mach/sysasic.h
index f33426608a87..58f710e1ebc2 100644
--- a/arch/sh/include/mach-dreamcast/mach/sysasic.h
+++ b/arch/sh/include/mach-dreamcast/mach/sysasic.h
@@ -39,5 +39,10 @@
 
 #define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
 
+/* arch/sh/boards/mach-dreamcast/irq.c */
+extern int systemasic_irq_demux(int);
+extern void systemasic_irq_init(void);
+extern void aica_time_init(void);
+
 #endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
 
diff --git a/arch/sh/include/mach-sdk7786/mach/fpga.h b/arch/sh/include/mach-sdk7786/mach/fpga.h
new file mode 100644
index 000000000000..2120d67dec70
--- /dev/null
+++ b/arch/sh/include/mach-sdk7786/mach/fpga.h
@@ -0,0 +1,114 @@
+#ifndef __MACH_SDK7786_FPGA_H
+#define __MACH_SDK7786_FPGA_H
+
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+
+#define SRSTR           0x000
+#define  SRSTR_MAGIC    0x1971  /* Fixed magical read value */
+
+#define INTASR          0x010
+#define INTAMR          0x020
+#define MODSWR          0x030
+#define INTTESTR        0x040
+#define SYSSR           0x050
+#define NRGPR           0x060
+#define NMISR           0x070
+
+#define NMIMR           0x080
+#define  NMIMR_MAN_NMIM BIT(0)  /* Manual NMI mask */
+#define  NMIMR_AUX_NMIM BIT(1)  /* Auxiliary NMI mask */
+
+#define INTBSR          0x090
+#define INTBMR          0x0a0
+#define USRLEDR         0x0b0
+#define MAPSWR          0x0c0
+#define FPGAVR          0x0d0
+#define FPGADR          0x0e0
+#define PCBRR           0x0f0
+#define RSR             0x100
+#define EXTASR          0x110
+#define SPCAR           0x120
+#define INTMSR          0x130
+#define PCIECR          0x140
+#define FAER            0x150
+#define USRGPIR         0x160
+/* 0x170 reserved */
+#define LCLASR          0x180
+
+#define SBCR            0x190
+#define  SCBR_I2CMEN    BIT(0)  /* FPGA I2C master enable */
+#define  SCBR_I2CCEN    BIT(1)  /* CPU I2C master enable */
+
+#define PWRCR           0x1a0
+#define SPCBR           0x1b0
+#define SPICR           0x1c0
+#define SPIDR           0x1d0
+#define I2CCR           0x1e0
+#define I2CDR           0x1f0
+#define FPGACR          0x200
+#define IASELR1         0x210
+#define IASELR2         0x220
+#define IASELR3         0x230
+#define IASELR4         0x240
+#define IASELR5         0x250
+#define IASELR6         0x260
+#define IASELR7         0x270
+#define IASELR8         0x280
+#define IASELR9         0x290
+#define IASELR10        0x2a0
+#define IASELR11        0x2b0
+#define IASELR12        0x2c0
+#define IASELR13        0x2d0
+#define IASELR14        0x2e0
+#define IASELR15        0x2f0
+/* 0x300 reserved */
+#define IBSELR1         0x310
+#define IBSELR2         0x320
+#define IBSELR3         0x330
+#define IBSELR4         0x340
+#define IBSELR5         0x350
+#define IBSELR6         0x360
+#define IBSELR7         0x370
+#define IBSELR8         0x380
+#define IBSELR9         0x390
+#define IBSELR10        0x3a0
+#define IBSELR11        0x3b0
+#define IBSELR12        0x3c0
+#define IBSELR13        0x3d0
+#define IBSELR14        0x3e0
+#define IBSELR15        0x3f0
+#define USRACR          0x400
+#define BEEPR           0x410
+#define USRLCDR         0x420
+#define SMBCR           0x430
+#define SMBDR           0x440
+#define USBCR           0x450
+#define AMSR            0x460
+#define ACCR            0x470
+#define SDIFCR          0x480
+
+/* arch/sh/boards/mach-sdk7786/fpga.c */
+extern void __iomem *sdk7786_fpga_base;
+extern void sdk7786_fpga_init(void);
+
+#define SDK7786_FPGA_REGADDR(reg)       (sdk7786_fpga_base + (reg))
+
+/*
+ * A convenience wrapper from register offset to internal I2C address,
+ * when the FPGA is in I2C slave mode.
+ */
+#define SDK7786_FPGA_I2CADDR(reg)       ((reg) >> 3)
+
+static inline u16 fpga_read_reg(unsigned int reg)
+{
+        return ioread16(sdk7786_fpga_base + reg);
+}
+
+static inline void fpga_write_reg(u16 val, unsigned int reg)
+{
+        iowrite16(val, sdk7786_fpga_base + reg);
+}
+
+#endif /* __MACH_SDK7786_FPGA_H */
diff --git a/arch/sh/include/mach-sdk7786/mach/irq.h b/arch/sh/include/mach-sdk7786/mach/irq.h
new file mode 100644
index 000000000000..0f584635e6e5
--- /dev/null
+++ b/arch/sh/include/mach-sdk7786/mach/irq.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_SDK7786_IRQ_H
+#define __MACH_SDK7786_IRQ_H
+
+/* arch/sh/boards/mach-sdk7786/irq.c */
+extern void sdk7786_init_irq(void);
+
+#endif /* __MACH_SDK7786_IRQ_H */
diff --git a/arch/sh/include/mach-se/mach/se7343.h b/arch/sh/include/mach-se/mach/se7343.h
index 749914b400fb..8d8170d6cc43 100644
--- a/arch/sh/include/mach-se/mach/se7343.h
+++ b/arch/sh/include/mach-se/mach/se7343.h
@@ -94,26 +94,26 @@
 
 #define PORT_DRVCR      0xA4050180
 
-#define PORT_PADR       0xA4050120
-#define PORT_PBDR       0xA4050122
-#define PORT_PCDR       0xA4050124
-#define PORT_PDDR       0xA4050126
-#define PORT_PEDR       0xA4050128
-#define PORT_PFDR       0xA405012A
-#define PORT_PGDR       0xA405012C
-#define PORT_PHDR       0xA405012E
-#define PORT_PJDR       0xA4050130
-#define PORT_PKDR       0xA4050132
-#define PORT_PLDR       0xA4050134
-#define PORT_PMDR       0xA4050136
-#define PORT_PNDR       0xA4050138
-#define PORT_PQDR       0xA405013A
-#define PORT_PRDR       0xA405013C
-#define PORT_PTDR       0xA4050160
-#define PORT_PUDR       0xA4050162
-#define PORT_PVDR       0xA4050164
-#define PORT_PWDR       0xA4050166
-#define PORT_PYDR       0xA4050168
+#define PORT_PADR       0xA4050120
+#define PORT_PBDR       0xA4050122
+#define PORT_PCDR       0xA4050124
+#define PORT_PDDR       0xA4050126
+#define PORT_PEDR       0xA4050128
+#define PORT_PFDR       0xA405012A
+#define PORT_PGDR       0xA405012C
+#define PORT_PHDR       0xA405012E
+#define PORT_PJDR       0xA4050130
+#define PORT_PKDR       0xA4050132
+#define PORT_PLDR       0xA4050134
+#define PORT_PMDR       0xA4050136
+#define PORT_PNDR       0xA4050138
+#define PORT_PQDR       0xA405013A
+#define PORT_PRDR       0xA405013C
+#define PORT_PTDR       0xA4050160
+#define PORT_PUDR       0xA4050162
+#define PORT_PVDR       0xA4050164
+#define PORT_PWDR       0xA4050166
+#define PORT_PYDR       0xA4050168
 
 #define FPGA_IN         0xb1400000
 #define FPGA_OUT        0xb1400002
@@ -133,18 +133,10 @@
 #define SE7343_FPGA_IRQ_UARTB   11
 
 #define SE7343_FPGA_IRQ_NR      12
-#define SE7343_FPGA_IRQ_BASE    120
-
-#define MRSHPC_IRQ3     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC3)
-#define MRSHPC_IRQ2     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC2)
-#define MRSHPC_IRQ1     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC1)
-#define MRSHPC_IRQ0     (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_MRSHPC0)
-#define SMC_IRQ         (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_SMC)
-#define USB_IRQ         (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_USB)
-#define UARTA_IRQ       (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_UARTA)
-#define UARTB_IRQ       (SE7343_FPGA_IRQ_BASE + SE7343_FPGA_IRQ_UARTB)
 
 /* arch/sh/boards/se/7343/irq.c */
+extern unsigned int se7343_fpga_irq[];
+
 void init_7343se_IRQ(void);
 
 #endif  /* __ASM_SH_HITACHI_SE7343_H */
diff --git a/arch/sh/kernel/Makefile b/arch/sh/kernel/Makefile
index 0d587da1ef12..02fd3ae8b0ee 100644
--- a/arch/sh/kernel/Makefile
+++ b/arch/sh/kernel/Makefile
@@ -13,8 +13,9 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 obj-y   := debugtraps.o dma-nommu.o dumpstack.o                         \
            idle.o io.o io_generic.o irq.o                               \
-           irq_$(BITS).o machvec.o nmi_debug.o process_$(BITS).o        \
-           ptrace_$(BITS).o return_address.o                            \
+           irq_$(BITS).o machvec.o nmi_debug.o process.o                \
+           process_$(BITS).o ptrace_$(BITS).o                           \
+           reboot.o return_address.o                                    \
            setup.o signal_$(BITS).o sys_sh.o sys_sh$(BITS).o            \
            syscalls_$(BITS).o time.o topology.o traps.o                 \
            traps_$(BITS).o unwinder.o
@@ -22,7 +23,7 @@ obj-y	:= debugtraps.o dma-nommu.o dumpstack.o 			\
 obj-y                           += cpu/
 obj-$(CONFIG_VSYSCALL)          += vsyscall/
 obj-$(CONFIG_SMP)               += smp.o
-obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o early_printk.o
+obj-$(CONFIG_SH_STANDARD_BIOS)  += sh_bios.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_SH_CPU_FREQ)       += cpufreq.o
 obj-$(CONFIG_MODULES)           += sh_ksyms_$(BITS).o module.o
@@ -39,6 +40,7 @@ obj-$(CONFIG_HIBERNATION)	+= swsusp.o
 obj-$(CONFIG_DWARF_UNWINDER)    += dwarf.o
 obj-$(CONFIG_PERF_EVENTS)       += perf_event.o perf_callchain.o
 
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)                += hw_breakpoint.o
 obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)     += localtimer.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index d97c803719ec..0e48bc61c272 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,5 +17,7 @@ obj-$(CONFIG_ARCH_SHMOBILE)	+= shmobile/
 
 obj-$(CONFIG_SH_ADC)            += adc.o
 obj-$(CONFIG_SH_CLK_CPG)        += clock-cpg.o
+obj-$(CONFIG_SH_FPU)            += fpu.o
+obj-$(CONFIG_SH_FPU_EMU)        += fpu.o
 
 obj-y   += irq/ init.o clock.o hwblk.o
diff --git a/arch/sh/kernel/cpu/adc.c b/arch/sh/kernel/cpu/adc.c
index da3d6877f93d..d307571d54b6 100644
--- a/arch/sh/kernel/cpu/adc.c
+++ b/arch/sh/kernel/cpu/adc.c
@@ -18,19 +18,19 @@ int adc_single(unsigned int channel)
 
         off = (channel & 0x03) << 2;
 
-        csr = ctrl_inb(ADCSR);
+        csr = __raw_readb(ADCSR);
         csr = channel | ADCSR_ADST | ADCSR_CKS;
-        ctrl_outb(csr, ADCSR);
+        __raw_writeb(csr, ADCSR);
 
         do {
-                csr = ctrl_inb(ADCSR);
+                csr = __raw_readb(ADCSR);
         } while ((csr & ADCSR_ADF) == 0);
 
         csr &= ~(ADCSR_ADF | ADCSR_ADST);
-        ctrl_outb(csr, ADCSR);
+        __raw_writeb(csr, ADCSR);
 
-        return (((ctrl_inb(ADDRAH + off) << 8) |
-                ctrl_inb(ADDRAL + off)) >> 6);
+        return (((__raw_readb(ADDRAH + off) << 8) |
+                __raw_readb(ADDRAL + off)) >> 6);
 }
 
 EXPORT_SYMBOL(adc_single);
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
index 6dfe2cced3fc..eed5eaff96ba 100644
--- a/arch/sh/kernel/cpu/clock-cpg.c
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -149,7 +149,8 @@ int __init sh_clk_div6_register(struct clk *clks, int nr)
 
 static unsigned long sh_clk_div4_recalc(struct clk *clk)
 {
-        struct clk_div_mult_table *table = clk->priv;
+        struct clk_div4_table *d4t = clk->priv;
+        struct clk_div_mult_table *table = d4t->div_mult_table;
         unsigned int idx;
 
         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
@@ -160,17 +161,90 @@ static unsigned long sh_clk_div4_recalc(struct clk *clk)
         return clk->freq_table[idx].frequency;
 }
 
+static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
+{
+        struct clk_div4_table *d4t = clk->priv;
+        struct clk_div_mult_table *table = d4t->div_mult_table;
+        u32 value;
+        int ret;
+
+        if (!strcmp("pll_clk", parent->name))
+                value = __raw_readl(clk->enable_reg) & ~(1 << 7);
+        else
+                value = __raw_readl(clk->enable_reg) | (1 << 7);
+
+        ret = clk_reparent(clk, parent);
+        if (ret < 0)
+                return ret;
+
+        __raw_writel(value, clk->enable_reg);
+
+        /* Rebiuld the frequency table */
+        clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
+                             table, &clk->arch_flags);
+
+        return 0;
+}
+
+static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
+{
+        struct clk_div4_table *d4t = clk->priv;
+        unsigned long value;
+        int idx = clk_rate_table_find(clk, clk->freq_table, rate);
+        if (idx < 0)
+                return idx;
+
+        value = __raw_readl(clk->enable_reg);
+        value &= ~(0xf << clk->enable_bit);
+        value |= (idx << clk->enable_bit);
+        __raw_writel(value, clk->enable_reg);
+
+        if (d4t->kick)
+                d4t->kick(clk);
+
+        return 0;
+}
+
+static int sh_clk_div4_enable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
+        return 0;
+}
+
+static void sh_clk_div4_disable(struct clk *clk)
+{
+        __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
+}
+
 static struct clk_ops sh_clk_div4_clk_ops = {
         .recalc         = sh_clk_div4_recalc,
+        .set_rate       = sh_clk_div4_set_rate,
         .round_rate     = sh_clk_div_round_rate,
 };
 
-int __init sh_clk_div4_register(struct clk *clks, int nr,
-                                struct clk_div_mult_table *table)
+static struct clk_ops sh_clk_div4_enable_clk_ops = {
+        .recalc         = sh_clk_div4_recalc,
+        .set_rate       = sh_clk_div4_set_rate,
+        .round_rate     = sh_clk_div_round_rate,
+        .enable         = sh_clk_div4_enable,
+        .disable        = sh_clk_div4_disable,
+};
+
+static struct clk_ops sh_clk_div4_reparent_clk_ops = {
+        .recalc         = sh_clk_div4_recalc,
+        .set_rate       = sh_clk_div4_set_rate,
+        .round_rate     = sh_clk_div_round_rate,
+        .enable         = sh_clk_div4_enable,
+        .disable        = sh_clk_div4_disable,
+        .set_parent     = sh_clk_div4_set_parent,
+};
+
+static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
+                        struct clk_div4_table *table, struct clk_ops *ops)
 {
         struct clk *clkp;
         void *freq_table;
-        int nr_divs = table->nr_divisors;
+        int nr_divs = table->div_mult_table->nr_divisors;
         int freq_table_size = sizeof(struct cpufreq_frequency_table);
         int ret = 0;
         int k;
@@ -185,7 +259,7 @@ int __init sh_clk_div4_register(struct clk *clks, int nr,
         for (k = 0; !ret && (k < nr); k++) {
                 clkp = clks + k;
 
-                clkp->ops = &sh_clk_div4_clk_ops;
+                clkp->ops = ops;
                 clkp->id = -1;
                 clkp->priv = table;
 
@@ -198,6 +272,26 @@ int __init sh_clk_div4_register(struct clk *clks, int nr,
         return ret;
 }
 
+int __init sh_clk_div4_register(struct clk *clks, int nr,
+                                struct clk_div4_table *table)
+{
+        return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
+}
+
+int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
+                                struct clk_div4_table *table)
+{
+        return sh_clk_div4_register_ops(clks, nr, table,
+                                        &sh_clk_div4_enable_clk_ops);
+}
+
+int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
+                                struct clk_div4_table *table)
+{
+        return sh_clk_div4_register_ops(clks, nr, table,
+                                        &sh_clk_div4_reparent_clk_ops);
+}
+
 #ifdef CONFIG_SH_CLK_CPG_LEGACY
 static struct clk master_clk = {
         .name           = "master_clk",
diff --git a/arch/sh/kernel/cpu/fpu.c b/arch/sh/kernel/cpu/fpu.c
new file mode 100644
index 000000000000..f059ed62cf57
--- /dev/null
+++ b/arch/sh/kernel/cpu/fpu.c
@@ -0,0 +1,84 @@
+#include <linux/sched.h>
+#include <asm/processor.h>
+#include <asm/fpu.h>
+
+int init_fpu(struct task_struct *tsk)
+{
+        if (tsk_used_math(tsk)) {
+                if ((boot_cpu_data.flags & CPU_HAS_FPU) && tsk == current)
+                        unlazy_fpu(tsk, task_pt_regs(tsk));
+                return 0;
+        }
+
+        /*
+         * Memory allocation at the first usage of the FPU and other state.
+         */
+        if (!tsk->thread.xstate) {
+                tsk->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+                                                      GFP_KERNEL);
+                if (!tsk->thread.xstate)
+                        return -ENOMEM;
+        }
+
+        if (boot_cpu_data.flags & CPU_HAS_FPU) {
+                struct sh_fpu_hard_struct *fp = &tsk->thread.xstate->hardfpu;
+                memset(fp, 0, xstate_size);
+                fp->fpscr = FPSCR_INIT;
+        } else {
+                struct sh_fpu_soft_struct *fp = &tsk->thread.xstate->softfpu;
+                memset(fp, 0, xstate_size);
+                fp->fpscr = FPSCR_INIT;
+        }
+
+        set_stopped_child_used_math(tsk);
+        return 0;
+}
+
+#ifdef CONFIG_SH_FPU
+void __fpu_state_restore(void)
+{
+        struct task_struct *tsk = current;
+
+        restore_fpu(tsk);
+
+        task_thread_info(tsk)->status |= TS_USEDFPU;
+        tsk->fpu_counter++;
+}
+
+void fpu_state_restore(struct pt_regs *regs)
+{
+        struct task_struct *tsk = current;
+
+        if (unlikely(!user_mode(regs))) {
+                printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
+                BUG();
+                return;
+        }
+
+        if (!tsk_used_math(tsk)) {
+                local_irq_enable();
+                /*
+                 * does a slab alloc which can sleep
+                 */
+                if (init_fpu(tsk)) {
+                        /*
+                         * ran out of memory!
+                         */
+                        do_group_exit(SIGKILL);
+                        return;
+                }
+                local_irq_disable();
+        }
+
+        grab_fpu(regs);
+
+        __fpu_state_restore();
+}
+
+BUILD_TRAP_HANDLER(fpu_state_restore)
+{
+        TRAP_HANDLER_DECL;
+
+        fpu_state_restore(regs);
+}
+#endif /* CONFIG_SH_FPU */
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 89b4b76c0d76..c736422344eb 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -24,22 +24,32 @@
 #include <asm/elf.h>
 #include <asm/io.h>
 #include <asm/smp.h>
-#ifdef CONFIG_SUPERH32
-#include <asm/ubc.h>
+#include <asm/sh_bios.h>
+
+#ifdef CONFIG_SH_FPU
+#define cpu_has_fpu     1
+#else
+#define cpu_has_fpu     0
+#endif
+
+#ifdef CONFIG_SH_DSP
+#define cpu_has_dsp     1
+#else
+#define cpu_has_dsp     0
 #endif
 
 /*
  * Generic wrapper for command line arguments to disable on-chip
  * peripherals (nofpu, nodsp, and so forth).
  */
-#define onchip_setup(x)                         \
-static int x##_disabled __initdata = 0;         \
-                                                \
-static int __init x##_setup(char *opts)         \
-{                                               \
-        x##_disabled = 1;                       \
-        return 1;                               \
-}                                               \
+#define onchip_setup(x)                                 \
+static int x##_disabled __initdata = !cpu_has_##x;      \
+                                                        \
+static int __init x##_setup(char *opts)                 \
+{                                                       \
+        x##_disabled = 1;                               \
+        return 1;                                       \
+}                                                       \
 __setup("no" __stringify(x), x##_setup);
 
 onchip_setup(fpu);
@@ -52,10 +62,10 @@ onchip_setup(dsp);
 static void __init speculative_execution_init(void)
 {
         /* Clear RABD */
-        ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
+        __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
 
         /* Flush the update */
-        (void)ctrl_inl(CPUOPM);
+        (void)__raw_readl(CPUOPM);
         ctrl_barrier();
 }
 #else
@@ -89,7 +99,7 @@ static void __init expmask_init(void)
 #endif
 
 /* 2nd-level cache init */
-void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
+void __attribute__ ((weak)) l2_cache_init(void)
 {
 }
 
@@ -97,12 +107,12 @@ void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
  * Generic first-level cache init
  */
 #ifdef CONFIG_SUPERH32
-static void __uses_jump_to_uncached cache_init(void)
+static void cache_init(void)
 {
         unsigned long ccr, flags;
 
         jump_to_uncached();
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
 
         /*
          * At this point we don't know whether the cache is enabled or not - a
@@ -146,7 +156,7 @@ static void __uses_jump_to_uncached cache_init(void)
                         for (addr = addrstart;
                              addr < addrstart + waysize;
                              addr += current_cpu_data.dcache.linesz)
-                                ctrl_outl(0, addr);
+                                __raw_writel(0, addr);
 
                         addrstart += current_cpu_data.dcache.way_incr;
                 } while (--ways);
@@ -179,7 +189,7 @@ static void __uses_jump_to_uncached cache_init(void)
 
         l2_cache_init();
 
-        ctrl_outl(flags, CCR);
+        __raw_writel(flags, CCR);
         back_to_cached();
 }
 #else
@@ -207,6 +217,18 @@ static void detect_cache_shape(void)
                 l2_cache_shape = -1; /* No S-cache */
 }
 
+static void __init fpu_init(void)
+{
+        /* Disable the FPU */
+        if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
+                printk("FPU Disabled\n");
+                current_cpu_data.flags &= ~CPU_HAS_FPU;
+        }
+
+        disable_fpu();
+        clear_used_math();
+}
+
 #ifdef CONFIG_SH_DSP
 static void __init release_dsp(void)
 {
@@ -244,28 +266,35 @@ static void __init dsp_init(void)
         if (sr & SR_DSP)
                 current_cpu_data.flags |= CPU_HAS_DSP;
 
+        /* Disable the DSP */
+        if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) {
+                printk("DSP Disabled\n");
+                current_cpu_data.flags &= ~CPU_HAS_DSP;
+        }
+
         /* Now that we've determined the DSP status, clear the DSP bit. */
         release_dsp();
 }
+#else
+static inline void __init dsp_init(void) { }
 #endif /* CONFIG_SH_DSP */
 
 /**
  * sh_cpu_init
  *
- * This is our initial entry point for each CPU, and is invoked on the boot
- * CPU prior to calling start_kernel(). For SMP, a combination of this and
- * start_secondary() will bring up each processor to a ready state prior
- * to hand forking the idle loop.
+ * This is our initial entry point for each CPU, and is invoked on the
+ * boot CPU prior to calling start_kernel(). For SMP, a combination of
+ * this and start_secondary() will bring up each processor to a ready
+ * state prior to hand forking the idle loop.
  *
- * We do all of the basic processor init here, including setting up the
- * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
- * hit (and subsequently platform_setup()) things like determining the
- * CPU subtype and initial configuration will all be done.
+ * We do all of the basic processor init here, including setting up
+ * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and
+ * subsequently platform_setup()) things like determining the CPU
+ * subtype and initial configuration will all be done.
  *
  * Each processor family is still responsible for doing its own probing
  * and cache configuration in detect_cpu_and_cache_system().
  */
-
 asmlinkage void __init sh_cpu_init(void)
 {
         current_thread_info()->cpu = hard_smp_processor_id();
@@ -302,18 +331,8 @@ asmlinkage void __init sh_cpu_init(void)
                 detect_cache_shape();
         }
 
-        /* Disable the FPU */
-        if (fpu_disabled) {
-                printk("FPU Disabled\n");
-                current_cpu_data.flags &= ~CPU_HAS_FPU;
-        }
-
-        /* FPU initialization */
-        disable_fpu();
-        if ((current_cpu_data.flags & CPU_HAS_FPU)) {
-                current_thread_info()->status &= ~TS_USEDFPU;
-                clear_used_math();
-        }
+        fpu_init();
+        dsp_init();
 
         /*
          * Initialize the per-CPU ASID cache very early, since the
@@ -321,18 +340,24 @@ asmlinkage void __init sh_cpu_init(void)
          */
         current_cpu_data.asid_cache = NO_CONTEXT;
 
-#ifdef CONFIG_SH_DSP
-        /* Probe for DSP */
-        dsp_init();
-
-        /* Disable the DSP */
-        if (dsp_disabled) {
-                printk("DSP Disabled\n");
-                current_cpu_data.flags &= ~CPU_HAS_DSP;
-                release_dsp();
-        }
-#endif
-
         speculative_execution_init();
         expmask_init();
+
+        /* Do the rest of the boot processor setup */
+        if (raw_smp_processor_id() == 0) {
+                /* Save off the BIOS VBR, if there is one */
+                sh_bios_vbr_init();
+
+                /*
+                 * Setup VBR for boot CPU. Secondary CPUs do this through
+                 * start_secondary().
+                 */
+                per_cpu_trap_init();
+
+                /*
+                 * Boot processor to setup the FP and extended state
+                 * context info.
+                 */
+                init_thread_xstate();
+        }
 }
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 06e7e2959b54..96a239583948 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -123,7 +123,7 @@ static void enable_intc_irq(unsigned int irq)
                 bitmask = 1 << (irq - 32);
         }
 
-        ctrl_outl(bitmask, reg);
+        __raw_writel(bitmask, reg);
 }
 
 static void disable_intc_irq(unsigned int irq)
@@ -139,7 +139,7 @@ static void disable_intc_irq(unsigned int irq)
                 bitmask = 1 << (irq - 32);
         }
 
-        ctrl_outl(bitmask, reg);
+        __raw_writel(bitmask, reg);
 }
 
 static void mask_and_ack_intc(unsigned int irq)
@@ -170,11 +170,11 @@ void __init plat_irq_setup(void)
 
 
         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
-        ctrl_outl(-1, INTC_INTDSB_0);
-        ctrl_outl(-1, INTC_INTDSB_1);
+        __raw_writel(-1, INTC_INTDSB_0);
+        __raw_writel(-1, INTC_INTDSB_1);
 
         for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
-                ctrl_outl( NO_PRIORITY, reg);
+                __raw_writel( NO_PRIORITY, reg);
 
 
 #ifdef CONFIG_SH_CAYMAN
@@ -199,7 +199,7 @@ void __init plat_irq_setup(void)
                         reg = INTC_ICR_SET;
                         i = IRQ_IRL0;
                 }
-                ctrl_outl(INTC_ICR_IRLM, reg);
+                __raw_writel(INTC_ICR_IRLM, reg);
 
                 /* Set interrupt priorities according to platform description */
                 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
@@ -207,7 +207,7 @@ void __init plat_irq_setup(void)
                                 ((i % INTC_INTPRI_PPREG) * 4);
                         if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
                                 /* Upon the 7th, set Priority Register */
-                                ctrl_outl(data, reg);
+                                __raw_writel(data, reg);
                                 data = 0;
                                 reg += 8;
                         }
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 4fe863170e31..0c9f24d7a02f 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -31,7 +31,7 @@ static const int pfc_divisors[] = {1,2,0,4};
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
+        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_master_clk_ops = {
@@ -40,7 +40,7 @@ static struct clk_ops sh7619_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -50,7 +50,7 @@ static struct clk_ops sh7619_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
+        return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
 }
 
 static struct clk_ops sh7619_bus_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 7814c76159a7..b26264dc2aef 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
 
 static void master_clk_init(struct clk *clk)
 {
-        return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7201_master_clk_ops = {
@@ -43,7 +43,7 @@ static struct clk_ops sh7201_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -53,7 +53,7 @@ static struct clk_ops sh7201_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -63,7 +63,7 @@ static struct clk_ops sh7201_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
+        int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 940986965102..7e75d8f79502 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -39,7 +39,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ;
+        clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
 }
 
 static struct clk_ops sh7203_master_clk_ops = {
@@ -48,7 +48,7 @@ static struct clk_ops sh7203_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -58,7 +58,7 @@ static struct clk_ops sh7203_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx-2];
 }
 
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index c2268bdeceeb..b27a5e2687ab 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_master_clk_ops = {
@@ -43,7 +43,7 @@ static struct clk_ops sh7206_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -53,7 +53,7 @@ static struct clk_ops sh7206_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
+        return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
 }
 
 static struct clk_ops sh7206_bus_clk_ops = {
@@ -62,7 +62,7 @@ static struct clk_ops sh7206_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FREQCR) & 0x0007);
+        int idx = (__raw_readw(FREQCR) & 0x0007);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh2a/fpu.c b/arch/sh/kernel/cpu/sh2a/fpu.c
index d395ce5740e7..488d24e0cdf0 100644
--- a/arch/sh/kernel/cpu/sh2a/fpu.c
+++ b/arch/sh/kernel/cpu/sh2a/fpu.c
@@ -26,8 +26,7 @@
 /*
  * Save FPU registers onto task structure.
  */
-void
-save_fpu(struct task_struct *tsk)
+void save_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
@@ -52,7 +51,7 @@ save_fpu(struct task_struct *tsk)
                      "fmov.s    fr0, @-%0\n\t"
                      "lds       %3, fpscr\n\t"
                      : "=r" (dummy)
-                     : "0" ((char *)(&tsk->thread.fpu.hard.status)),
+                     : "0" ((char *)(&tsk->thread.xstate->hardfpu.status)),
                        "r" (FPSCR_RCHG),
                        "r" (FPSCR_INIT)
                      : "memory");
@@ -60,8 +59,7 @@ save_fpu(struct task_struct *tsk)
         disable_fpu();
 }
 
-static void
-restore_fpu(struct task_struct *tsk)
+void restore_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
@@ -85,45 +83,12 @@ restore_fpu(struct task_struct *tsk)
                      "lds.l     @%0+, fpscr\n\t"
                      "lds.l     @%0+, fpul\n\t"
                      : "=r" (dummy)
-                     : "0" (&tsk->thread.fpu), "r" (FPSCR_RCHG)
+                     : "0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
                      : "memory");
         disable_fpu();
 }
 
 /*
- * Load the FPU with signalling NANS.  This bit pattern we're using
- * has the property that no matter wether considered as single or as
- * double precission represents signaling NANS.
- */
-
-static void
-fpu_init(void)
-{
-        enable_fpu();
-        asm volatile("lds       %0, fpul\n\t"
-                     "fsts      fpul, fr0\n\t"
-                     "fsts      fpul, fr1\n\t"
-                     "fsts      fpul, fr2\n\t"
-                     "fsts      fpul, fr3\n\t"
-                     "fsts      fpul, fr4\n\t"
-                     "fsts      fpul, fr5\n\t"
-                     "fsts      fpul, fr6\n\t"
-                     "fsts      fpul, fr7\n\t"
-                     "fsts      fpul, fr8\n\t"
-                     "fsts      fpul, fr9\n\t"
-                     "fsts      fpul, fr10\n\t"
-                     "fsts      fpul, fr11\n\t"
-                     "fsts      fpul, fr12\n\t"
-                     "fsts      fpul, fr13\n\t"
-                     "fsts      fpul, fr14\n\t"
-                     "fsts      fpul, fr15\n\t"
-                     "lds       %2, fpscr\n\t"
-                     : /* no output */
-                     : "r" (0), "r" (FPSCR_RCHG), "r" (FPSCR_INIT));
-        disable_fpu();
-}
-
-/*
  *      Emulate arithmetic ops on denormalized number for some FPU insns.
  */
 
@@ -490,9 +455,9 @@ ieee_fpe_handler (struct pt_regs *regs)
         if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
                 struct task_struct *tsk = current;
 
-                if ((tsk->thread.fpu.hard.fpscr & FPSCR_FPU_ERROR)) {
+                if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_FPU_ERROR)) {
                         /* FPU error */
-                        denormal_to_double (&tsk->thread.fpu.hard,
+                        denormal_to_double (&tsk->thread.xstate->hardfpu,
                                             (finsn >> 8) & 0xf);
                 } else
                         return 0;
@@ -507,9 +472,9 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & (1 << 19);
 
                 if ((fpscr & FPSCR_FPU_ERROR)
@@ -519,15 +484,15 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                         /* FPU error because of denormal */
                         llx = ((long long) hx << 32)
-                               | tsk->thread.fpu.hard.fp_regs[n+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[n+1];
                         lly = ((long long) hy << 32)
-                               | tsk->thread.fpu.hard.fp_regs[m+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[m+1];
                         if ((hx & 0x7fffffff) >= 0x00100000)
                                 llx = denormal_muld(lly, llx);
                         else
                                 llx = denormal_muld(llx, lly);
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_FPU_ERROR)
                      && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                    || (hy & 0x7fffffff) < 0x00800000))) {
@@ -536,7 +501,7 @@ ieee_fpe_handler (struct pt_regs *regs)
                                 hx = denormal_mulf(hy, hx);
                         else
                                 hx = denormal_mulf(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -550,9 +515,9 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & (1 << 19);
 
                 if ((fpscr & FPSCR_FPU_ERROR)
@@ -562,15 +527,15 @@ ieee_fpe_handler (struct pt_regs *regs)
 
                         /* FPU error because of denormal */
                         llx = ((long long) hx << 32)
-                               | tsk->thread.fpu.hard.fp_regs[n+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[n+1];
                         lly = ((long long) hy << 32)
-                               | tsk->thread.fpu.hard.fp_regs[m+1];
+                               | tsk->thread.xstate->hardfpu.fp_regs[m+1];
                         if ((finsn & 0xf00f) == 0xf000)
                                 llx = denormal_addd(llx, lly);
                         else
                                 llx = denormal_addd(llx, lly ^ (1LL << 63));
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n+1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n+1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_FPU_ERROR)
                      && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                    || (hy & 0x7fffffff) < 0x00800000))) {
@@ -579,7 +544,7 @@ ieee_fpe_handler (struct pt_regs *regs)
                                 hx = denormal_addf(hx, hy);
                         else
                                 hx = denormal_addf(hx, hy ^ 0x80000000);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -597,7 +562,7 @@ BUILD_TRAP_HANDLER(fpu_error)
 
         __unlazy_fpu(tsk, regs);
         if (ieee_fpe_handler(regs)) {
-                tsk->thread.fpu.hard.fpscr &=
+                tsk->thread.xstate->hardfpu.fpscr &=
                         ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
                 grab_fpu(regs);
                 restore_fpu(tsk);
@@ -607,33 +572,3 @@ BUILD_TRAP_HANDLER(fpu_error)
 
         force_sig(SIGFPE, tsk);
 }
-
-void fpu_state_restore(struct pt_regs *regs)
-{
-        struct task_struct *tsk = current;
-
-        grab_fpu(regs);
-        if (unlikely(!user_mode(regs))) {
-                printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
-                BUG();
-                return;
-        }
-
-        if (likely(used_math())) {
-                /* Using the FPU again.  */
-                restore_fpu(tsk);
-        } else  {
-                /* First time FPU user.  */
-                fpu_init();
-                set_used_math();
-        }
-        task_thread_info(tsk)->status |= TS_USEDFPU;
-        tsk->fpu_counter++;
-}
-
-BUILD_TRAP_HANDLER(fpu_state_restore)
-{
-        TRAP_HANDLER_DECL;
-
-        fpu_state_restore(regs);
-}
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index 27b8738f0b09..b78384afac09 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -28,7 +28,7 @@ static int pfc_divisors[]    = { 1, 2, 3, 4, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         clk->rate *= pfc_divisors[idx];
@@ -40,7 +40,7 @@ static struct clk_ops sh3_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         return clk->parent->rate / pfc_divisors[idx];
@@ -52,7 +52,7 @@ static struct clk_ops sh3_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
 
         return clk->parent->rate / stc_multipliers[idx];
@@ -64,7 +64,7 @@ static struct clk_ops sh3_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
         return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index 0ca8f2c3646c..0ecea1451c6f 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -32,7 +32,7 @@ static int pfc_divisors[]    = { 1, 2, 3, 4, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003];
+        clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
 }
 
 static struct clk_ops sh7705_master_clk_ops = {
@@ -41,7 +41,7 @@ static struct clk_ops sh7705_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ctrl_inw(FRQCR) & 0x0003;
+        int idx = __raw_readw(FRQCR) & 0x0003;
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -51,7 +51,7 @@ static struct clk_ops sh7705_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
+        int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;
         return clk->parent->rate / stc_multipliers[idx];
 }
 
@@ -61,7 +61,7 @@ static struct clk_ops sh7705_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
+        int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 4bf7887d310a..6f9ff8b57dd6 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -24,7 +24,7 @@ static int pfc_divisors[]    = { 1, 2, 4, 1, 3, 6, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7706_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7706_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
 
         return clk->parent->rate / stc_multipliers[idx];
@@ -60,7 +60,7 @@ static struct clk_ops sh7706_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
         return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index e8749505bd2a..f302ba09e681 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -24,7 +24,7 @@ static int pfc_divisors[]    = { 1, 2, 4, 1, 3, 6, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7709_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
 
         return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7709_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = (frqcr & 0x0080) ?
                 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
 
@@ -61,7 +61,7 @@ static struct clk_ops sh7709_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
 
         return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 030a58ba18a5..29a87d8946a4 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -26,7 +26,7 @@ static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007];
+        clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
 }
 
 static struct clk_ops sh7710_master_clk_ops = {
@@ -35,7 +35,7 @@ static struct clk_ops sh7710_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0007);
+        int idx = (__raw_readw(FRQCR) & 0x0007);
         return clk->parent->rate / md_table[idx];
 }
 
@@ -45,7 +45,7 @@ static struct clk_ops sh7710_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
+        int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;
         return clk->parent->rate / md_table[idx];
 }
 
@@ -55,7 +55,7 @@ static struct clk_ops sh7710_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
+        int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;
         return clk->parent->rate / md_table[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 6428ee6c77ed..b0d0c5203996 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -23,7 +23,7 @@ static int divisors[]    = { 1, 2, 3, 4, 6 };
 
 static void master_clk_init(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = (frqcr & 0x0300) >> 8;
 
         clk->rate *= multipliers[idx];
@@ -35,7 +35,7 @@ static struct clk_ops sh7712_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = frqcr & 0x0007;
 
         return clk->parent->rate / divisors[idx];
@@ -47,7 +47,7 @@ static struct clk_ops sh7712_module_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int frqcr = ctrl_inw(FRQCR);
+        int frqcr = __raw_readw(FRQCR);
         int idx = (frqcr & 0x0030) >> 4;
 
         return clk->parent->rate / divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/ex.S b/arch/sh/kernel/cpu/sh3/ex.S
index 46610c35c232..99b4d020179a 100644
--- a/arch/sh/kernel/cpu/sh3/ex.S
+++ b/arch/sh/kernel/cpu/sh3/ex.S
@@ -49,7 +49,7 @@ ENTRY(exception_handling_table)
         .long   exception_error ! reserved_instruction (filled by trap_init) /* 180 */
         .long   exception_error ! illegal_slot_instruction (filled by trap_init) /*1A0*/
         .long   nmi_trap_handler        /* 1C0 */       ! Allow trap to debugger
-        .long   break_point_trap        /* 1E0 */
+        .long   breakpoint_trap_handler /* 1E0 */
 
         /*
          * Pad the remainder of the table out, exceptions residing in far
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index f9c7df64eb01..295ec4c99e98 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,7 +16,7 @@
 #include <asm/cache.h>
 #include <asm/io.h>
 
-int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
+int detect_cpu_and_cache_system(void)
 {
         unsigned long addr0, addr1, data0, data1, data2, data3;
 
@@ -30,23 +30,23 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
         addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
 
         /* First, write back & invalidate */
-        data0  = ctrl_inl(addr0);
-        ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
-        data1  = ctrl_inl(addr1);
-        ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
+        data0  = __raw_readl(addr0);
+        __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
+        data1  = __raw_readl(addr1);
+        __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
 
         /* Next, check if there's shadow or not */
-        data0 = ctrl_inl(addr0);
+        data0 = __raw_readl(addr0);
         data0 ^= SH_CACHE_VALID;
-        ctrl_outl(data0, addr0);
-        data1 = ctrl_inl(addr1);
+        __raw_writel(data0, addr0);
+        data1 = __raw_readl(addr1);
         data2 = data1 ^ SH_CACHE_VALID;
-        ctrl_outl(data2, addr1);
-        data3 = ctrl_inl(addr0);
+        __raw_writel(data2, addr1);
+        data3 = __raw_readl(addr0);
 
         /* Lastly, invaliate them. */
-        ctrl_outl(data0&~SH_CACHE_VALID, addr0);
-        ctrl_outl(data2&~SH_CACHE_VALID, addr1);
+        __raw_writel(data0&~SH_CACHE_VALID, addr0);
+        __raw_writel(data2&~SH_CACHE_VALID, addr1);
 
         back_to_cached();
 
@@ -94,9 +94,9 @@ int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
                 boot_cpu_data.dcache.way_incr   = (1 << 13);
                 boot_cpu_data.dcache.entry_mask = 0x1ff0;
                 boot_cpu_data.dcache.sets       = 512;
-                ctrl_outl(CCR_CACHE_32KB, CCR3_REG);
+                __raw_writel(CCR_CACHE_32KB, CCR3_REG);
 #else
-                ctrl_outl(CCR_CACHE_16KB, CCR3_REG);
+                __raw_writel(CCR_CACHE_16KB, CCR3_REG);
 #endif
 #endif
         }
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
index c98846857855..53be70b98116 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -58,7 +58,7 @@ static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
 void __init plat_irq_setup_pins(int mode)
 {
         if (mode == IRQ_MODE_IRQ) {
-                ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
+                __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
                 register_intc_controller(&intc_desc_irq0123);
                 return;
         }
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 21421e34e7d5..6b80850294da 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -23,7 +23,7 @@ static int frqcr3_values[]   = { 0, 1, 2, 3, 4, 5, 6  };
 
 static unsigned long emi_clk_recalc(struct clk *clk)
 {
-        int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
+        int idx = __raw_readl(CPG2_FRQCR3) & 0x0007;
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
@@ -52,7 +52,7 @@ static struct clk sh4202_emi_clk = {
 
 static unsigned long femi_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
+        int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007;
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
@@ -92,7 +92,7 @@ static void shoc_clk_init(struct clk *clk)
 
 static unsigned long shoc_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
+        int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007;
         return clk->parent->rate / frqcr3_divisors[idx];
 }
 
@@ -122,10 +122,10 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
 
         tmp = frqcr3_lookup(clk, rate);
 
-        frqcr3 = ctrl_inl(CPG2_FRQCR3);
+        frqcr3 = __raw_readl(CPG2_FRQCR3);
         frqcr3 &= ~(0x0007 << 6);
         frqcr3 |= tmp << 6;
-        ctrl_outl(frqcr3, CPG2_FRQCR3);
+        __raw_writel(frqcr3, CPG2_FRQCR3);
 
         clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
 
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index 73294d9cd049..5add75c1f539 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007];
+        clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
 }
 
 static struct clk_ops sh4_master_clk_ops = {
@@ -37,7 +37,7 @@ static struct clk_ops sh4_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) & 0x0007);
+        int idx = (__raw_readw(FRQCR) & 0x0007);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -47,7 +47,7 @@ static struct clk_ops sh4_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
+        int idx = (__raw_readw(FRQCR) >> 3) & 0x0007;
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -57,7 +57,7 @@ static struct clk_ops sh4_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
+        int idx = (__raw_readw(FRQCR) >> 6) & 0x0007;
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c
index e97857aec8a0..447482d7f65e 100644
--- a/arch/sh/kernel/cpu/sh4/fpu.c
+++ b/arch/sh/kernel/cpu/sh4/fpu.c
@@ -85,14 +85,14 @@ void save_fpu(struct task_struct *tsk)
                       "fmov.s   fr1, @-%0\n\t"
                       "fmov.s   fr0, @-%0\n\t"
                       "lds      %3, fpscr\n\t":"=r" (dummy)
-                      :"0"((char *)(&tsk->thread.fpu.hard.status)),
+                      :"0"((char *)(&tsk->thread.xstate->hardfpu.status)),
                       "r"(FPSCR_RCHG), "r"(FPSCR_INIT)
                       :"memory");
 
         disable_fpu();
 }
 
-static void restore_fpu(struct task_struct *tsk)
+void restore_fpu(struct task_struct *tsk)
 {
         unsigned long dummy;
 
@@ -135,62 +135,11 @@ static void restore_fpu(struct task_struct *tsk)
                       "lds.l    @%0+, fpscr\n\t"
                       "lds.l    @%0+, fpul\n\t"
                       :"=r" (dummy)
-                      :"0"(&tsk->thread.fpu), "r"(FPSCR_RCHG)
+                      :"0" (tsk->thread.xstate), "r" (FPSCR_RCHG)
                       :"memory");
         disable_fpu();
 }
 
-/*
- * Load the FPU with signalling NANS.  This bit pattern we're using
- * has the property that no matter wether considered as single or as
- * double precision represents signaling NANS.
- */
-
-static void fpu_init(void)
-{
-        enable_fpu();
-        asm volatile (  "lds    %0, fpul\n\t"
-                        "lds    %1, fpscr\n\t"
-                        "fsts   fpul, fr0\n\t"
-                        "fsts   fpul, fr1\n\t"
-                        "fsts   fpul, fr2\n\t"
-                        "fsts   fpul, fr3\n\t"
-                        "fsts   fpul, fr4\n\t"
-                        "fsts   fpul, fr5\n\t"
-                        "fsts   fpul, fr6\n\t"
-                        "fsts   fpul, fr7\n\t"
-                        "fsts   fpul, fr8\n\t"
-                        "fsts   fpul, fr9\n\t"
-                        "fsts   fpul, fr10\n\t"
-                        "fsts   fpul, fr11\n\t"
-                        "fsts   fpul, fr12\n\t"
-                        "fsts   fpul, fr13\n\t"
-                        "fsts   fpul, fr14\n\t"
-                        "fsts   fpul, fr15\n\t"
-                        "frchg\n\t"
-                        "fsts   fpul, fr0\n\t"
-                        "fsts   fpul, fr1\n\t"
-                        "fsts   fpul, fr2\n\t"
-                        "fsts   fpul, fr3\n\t"
-                        "fsts   fpul, fr4\n\t"
-                        "fsts   fpul, fr5\n\t"
-                        "fsts   fpul, fr6\n\t"
-                        "fsts   fpul, fr7\n\t"
-                        "fsts   fpul, fr8\n\t"
-                        "fsts   fpul, fr9\n\t"
-                        "fsts   fpul, fr10\n\t"
-                        "fsts   fpul, fr11\n\t"
-                        "fsts   fpul, fr12\n\t"
-                        "fsts   fpul, fr13\n\t"
-                        "fsts   fpul, fr14\n\t"
-                        "fsts   fpul, fr15\n\t"
-                        "frchg\n\t"
-                        "lds    %2, fpscr\n\t"
-                        :       /* no output */
-                        :"r" (0), "r"(FPSCR_RCHG), "r"(FPSCR_INIT));
-        disable_fpu();
-}
-
 /**
  *      denormal_to_double - Given denormalized float number,
  *                           store double float
@@ -282,9 +231,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
                 /* fcnvsd */
                 struct task_struct *tsk = current;
 
-                if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR))
+                if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR))
                         /* FPU error */
-                        denormal_to_double(&tsk->thread.fpu.hard,
+                        denormal_to_double(&tsk->thread.xstate->hardfpu,
                                            (finsn >> 8) & 0xf);
                 else
                         return 0;
@@ -300,9 +249,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & FPSCR_DBL_PRECISION;
 
                 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -312,18 +261,18 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                         /* FPU error because of denormal (doubles) */
                         llx = ((long long)hx << 32)
-                            | tsk->thread.fpu.hard.fp_regs[n + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
                         lly = ((long long)hy << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
                         llx = float64_mul(llx, lly);
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_CAUSE_ERROR)
                            && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                          || (hy & 0x7fffffff) < 0x00800000))) {
                         /* FPU error because of denormal (floats) */
                         hx = float32_mul(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -338,9 +287,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & FPSCR_DBL_PRECISION;
 
                 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -350,15 +299,15 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                         /* FPU error because of denormal (doubles) */
                         llx = ((long long)hx << 32)
-                            | tsk->thread.fpu.hard.fp_regs[n + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
                         lly = ((long long)hy << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
                         if ((finsn & 0xf00f) == 0xf000)
                                 llx = float64_add(llx, lly);
                         else
                                 llx = float64_sub(llx, lly);
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_CAUSE_ERROR)
                            && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                          || (hy & 0x7fffffff) < 0x00800000))) {
@@ -367,7 +316,7 @@ static int ieee_fpe_handler(struct pt_regs *regs)
                                 hx = float32_add(hx, hy);
                         else
                                 hx = float32_sub(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -382,9 +331,9 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                 n = (finsn >> 8) & 0xf;
                 m = (finsn >> 4) & 0xf;
-                hx = tsk->thread.fpu.hard.fp_regs[n];
-                hy = tsk->thread.fpu.hard.fp_regs[m];
-                fpscr = tsk->thread.fpu.hard.fpscr;
+                hx = tsk->thread.xstate->hardfpu.fp_regs[n];
+                hy = tsk->thread.xstate->hardfpu.fp_regs[m];
+                fpscr = tsk->thread.xstate->hardfpu.fpscr;
                 prec = fpscr & FPSCR_DBL_PRECISION;
 
                 if ((fpscr & FPSCR_CAUSE_ERROR)
@@ -394,20 +343,20 @@ static int ieee_fpe_handler(struct pt_regs *regs)
 
                         /* FPU error because of denormal (doubles) */
                         llx = ((long long)hx << 32)
-                            | tsk->thread.fpu.hard.fp_regs[n + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[n + 1];
                         lly = ((long long)hy << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
 
                         llx = float64_div(llx, lly);
 
-                        tsk->thread.fpu.hard.fp_regs[n] = llx >> 32;
-                        tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32;
+                        tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff;
                 } else if ((fpscr & FPSCR_CAUSE_ERROR)
                            && (!prec && ((hx & 0x7fffffff) < 0x00800000
                                          || (hy & 0x7fffffff) < 0x00800000))) {
                         /* FPU error because of denormal (floats) */
                         hx = float32_div(hx, hy);
-                        tsk->thread.fpu.hard.fp_regs[n] = hx;
+                        tsk->thread.xstate->hardfpu.fp_regs[n] = hx;
                 } else
                         return 0;
 
@@ -420,17 +369,17 @@ static int ieee_fpe_handler(struct pt_regs *regs)
                 unsigned int hx;
 
                 m = (finsn >> 8) & 0x7;
-                hx = tsk->thread.fpu.hard.fp_regs[m];
+                hx = tsk->thread.xstate->hardfpu.fp_regs[m];
 
-                if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR)
+                if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR)
                         && ((hx & 0x7fffffff) < 0x00100000)) {
                         /* subnormal double to float conversion */
                         long long llx;
 
-                        llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32)
-                            | tsk->thread.fpu.hard.fp_regs[m + 1];
+                        llx = ((long long)tsk->thread.xstate->hardfpu.fp_regs[m] << 32)
+                            | tsk->thread.xstate->hardfpu.fp_regs[m + 1];
 
-                        tsk->thread.fpu.hard.fpul = float64_to_float32(llx);
+                        tsk->thread.xstate->hardfpu.fpul = float64_to_float32(llx);
                 } else
                         return 0;
 
@@ -449,7 +398,7 @@ void float_raise(unsigned int flags)
 int float_rounding_mode(void)
 {
         struct task_struct *tsk = current;
-        int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.fpu.hard.fpscr);
+        int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.xstate->hardfpu.fpscr);
         return roundingMode;
 }
 
@@ -461,16 +410,16 @@ BUILD_TRAP_HANDLER(fpu_error)
         __unlazy_fpu(tsk, regs);
         fpu_exception_flags = 0;
         if (ieee_fpe_handler(regs)) {
-                tsk->thread.fpu.hard.fpscr &=
+                tsk->thread.xstate->hardfpu.fpscr &=
                     ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
-                tsk->thread.fpu.hard.fpscr |= fpu_exception_flags;
+                tsk->thread.xstate->hardfpu.fpscr |= fpu_exception_flags;
                 /* Set the FPSCR flag as well as cause bits - simply
                  * replicate the cause */
-                tsk->thread.fpu.hard.fpscr |= (fpu_exception_flags >> 10);
+                tsk->thread.xstate->hardfpu.fpscr |= (fpu_exception_flags >> 10);
                 grab_fpu(regs);
                 restore_fpu(tsk);
                 task_thread_info(tsk)->status |= TS_USEDFPU;
-                if ((((tsk->thread.fpu.hard.fpscr & FPSCR_ENABLE_MASK) >> 7) &
+                if ((((tsk->thread.xstate->hardfpu.fpscr & FPSCR_ENABLE_MASK) >> 7) &
                      (fpu_exception_flags >> 2)) == 0) {
                         return;
                 }
@@ -478,33 +427,3 @@ BUILD_TRAP_HANDLER(fpu_error)
 
         force_sig(SIGFPE, tsk);
 }
-
-void fpu_state_restore(struct pt_regs *regs)
-{
-        struct task_struct *tsk = current;
-
-        grab_fpu(regs);
-        if (unlikely(!user_mode(regs))) {
-                printk(KERN_ERR "BUG: FPU is used in kernel mode.\n");
-                BUG();
-                return;
-        }
-
-        if (likely(used_math())) {
-                /* Using the FPU again.  */
-                restore_fpu(tsk);
-        } else {
-                /* First time FPU user.  */
-                fpu_init();
-                set_used_math();
-        }
-        task_thread_info(tsk)->status |= TS_USEDFPU;
-        tsk->fpu_counter++;
-}
-
-BUILD_TRAP_HANDLER(fpu_state_restore)
-{
-        TRAP_HANDLER_DECL;
-
-        fpu_state_restore(regs);
-}
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index d36f0c45f55f..822977a06d84 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -28,9 +28,9 @@ int __init detect_cpu_and_cache_system(void)
                 [9] = (1 << 16)
         };
 
-        pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
-        prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
-        cvr = (ctrl_inl(CCN_CVR));
+        pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
+        prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
+        cvr = (__raw_readl(CCN_CVR));
 
         /*
          * Setup some sane SH-4 defaults for the icache
@@ -71,11 +71,11 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.dcache.ways = 4;
         } else {
                 /* And some SH-4 defaults.. */
-                boot_cpu_data.flags |= CPU_HAS_PTEA;
+                boot_cpu_data.flags |= CPU_HAS_PTEA | CPU_HAS_FPU;
                 boot_cpu_data.family = CPU_FAMILY_SH4;
         }
 
-        /* FPU detection works for everyone */
+        /* FPU detection works for almost everyone */
         if ((cvr & 0x20000000))
                 boot_cpu_data.flags |= CPU_HAS_FPU;
 
@@ -124,6 +124,7 @@ int __init detect_cpu_and_cache_system(void)
                 boot_cpu_data.type = CPU_SH7785;
                 break;
         case 0x4004:
+        case 0x4005:
                 boot_cpu_data.type = CPU_SH7786;
                 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
                 break;
@@ -160,6 +161,7 @@ int __init detect_cpu_and_cache_system(void)
                 break;
         case 0x700:
                 boot_cpu_data.type = CPU_SH4_501;
+                boot_cpu_data.flags &= ~CPU_HAS_FPU;
                 boot_cpu_data.icache.ways = 2;
                 boot_cpu_data.dcache.ways = 2;
                 break;
@@ -227,7 +229,7 @@ int __init detect_cpu_and_cache_system(void)
                          * Size calculation is much more sensible
                          * than it is for the L1.
                          *
-                         * Sizes are 128KB, 258KB, 512KB, and 1MB.
+                         * Sizes are 128KB, 256KB, 512KB, and 1MB.
                          */
                         size = (cvr & 0xf) << 17;
 
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 4b733715cdb5..b9b7e10ad68f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -198,7 +198,7 @@ void __init plat_irq_setup_pins(int mode)
 {
         switch (mode) {
         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
-                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irlm);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index b2a9df1af64c..ffd79e57254f 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -442,7 +442,7 @@ void __init plat_irq_setup_pins(int mode)
 
         switch (mode) {
         case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
-                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irlm);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 5b74cc0b43da..a16eb3656f4b 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -319,7 +319,7 @@ void __init plat_irq_setup_pins(int mode)
 {
         switch (mode) {
         case IRQ_MODE_IRQ:
-                ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
+                __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
                 register_intc_controller(&intc_desc_irq);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 8a8a993f55ea..fc065f9da6e5 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -43,9 +43,9 @@ static unsigned long *sq_bitmap;
 
 #define store_queue_barrier()                   \
 do {                                            \
-        (void)ctrl_inl(P4SEG_STORE_QUE);        \
-        ctrl_outl(0, P4SEG_STORE_QUE + 0);      \
-        ctrl_outl(0, P4SEG_STORE_QUE + 8);      \
+        (void)__raw_readl(P4SEG_STORE_QUE);     \
+        __raw_writel(0, P4SEG_STORE_QUE + 0);   \
+        __raw_writel(0, P4SEG_STORE_QUE + 8);   \
 } while (0);
 
 /**
@@ -100,7 +100,7 @@ static inline void sq_mapping_list_del(struct sq_mapping *map)
         spin_unlock_irq(&sq_mapping_lock);
 }
 
-static int __sq_remap(struct sq_mapping *map, unsigned long flags)
+static int __sq_remap(struct sq_mapping *map, pgprot_t prot)
 {
 #if defined(CONFIG_MMU)
         struct vm_struct *vma;
@@ -113,7 +113,7 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
 
         if (ioremap_page_range((unsigned long)vma->addr,
                                (unsigned long)vma->addr + map->size,
-                               vma->phys_addr, __pgprot(flags))) {
+                               vma->phys_addr, prot)) {
                 vunmap(vma->addr);
                 return -EAGAIN;
         }
@@ -123,8 +123,8 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
          * straightforward, as we can just load up each queue's QACR with
          * the physical address appropriately masked.
          */
-        ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
-        ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
+        __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
+        __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
 #endif
 
         return 0;
@@ -135,14 +135,14 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
  * @phys: Physical address of mapping.
  * @size: Length of mapping.
  * @name: User invoking mapping.
- * @flags: Protection flags.
+ * @prot: Protection bits.
  *
  * Remaps the physical address @phys through the next available store queue
  * address of @size length. @name is logged at boot time as well as through
  * the sysfs interface.
  */
 unsigned long sq_remap(unsigned long phys, unsigned int size,
-                       const char *name, unsigned long flags)
+                       const char *name, pgprot_t prot)
 {
         struct sq_mapping *map;
         unsigned long end;
@@ -177,7 +177,7 @@ unsigned long sq_remap(unsigned long phys, unsigned int size,
 
         map->sq_addr = P4SEG_STORE_QUE + (page << PAGE_SHIFT);
 
-        ret = __sq_remap(map, pgprot_val(PAGE_KERNEL_NOCACHE) | flags);
+        ret = __sq_remap(map, prot);
         if (unlikely(ret != 0))
                 goto out;
 
@@ -309,8 +309,7 @@ static ssize_t mapping_store(const char *buf, size_t count)
                 return -EIO;
 
         if (likely(len)) {
-                int ret = sq_remap(base, len, "Userspace",
-                                   pgprot_val(PAGE_SHARED));
+                int ret = sq_remap(base, len, "Userspace", PAGE_SHARED);
                 if (ret < 0)
                         return ret;
         } else
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 33bab477d2e2..b144e8af89dc 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -41,7 +41,8 @@ pinmux-$(CONFIG_CPU_SUBTYPE_SH7757)	:= pinmux-sh7757.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)     := pinmux-sh7785.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)     := pinmux-sh7786.o
 
-obj-y                           += $(clock-y)
-obj-$(CONFIG_SMP)               += $(smp-y)
-obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
-obj-$(CONFIG_PERF_EVENTS)       += perf_event.o
+obj-y                                   += $(clock-y)
+obj-$(CONFIG_SMP)                       += $(smp-y)
+obj-$(CONFIG_GENERIC_GPIO)              += $(pinmux-y)
+obj-$(CONFIG_PERF_EVENTS)               += perf_event.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)        += ubc.o
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index 0ee3ee861252..2c16df37eda6 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -107,13 +107,17 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
index a95ebaba095c..91588d280cd8 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -110,13 +110,17 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
        DIV4_SIUA, DIV4_SIUB, DIV4_NR };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index ea38b554dc05..15db6d521c5c 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -110,19 +110,22 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
-       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
 
 #define DIV4(_str, _reg, _bit, _mask, _flags) \
   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
+
 struct clk div4_clks[DIV4_NR] = {
         [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
         [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
@@ -130,9 +133,19 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
+};
+
+enum { DIV4_IRDA, DIV4_ENABLE_NR };
+
+struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
+        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
+};
+
+enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
+
+struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
         [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
         [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
-        [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
 };
 
 struct clk div6_clks[] = {
@@ -189,6 +202,14 @@ int __init arch_clk_init(void)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
+                ret = sh_clk_div4_enable_register(div4_enable_clks,
+                                        DIV4_ENABLE_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div4_reparent_register(div4_reparent_clks,
+                                        DIV4_REPARENT_NR, &div4_table);
+
+        if (!ret)
                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 
         if (!ret)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
index 20a31c2255a8..50babe01fe44 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -110,15 +110,18 @@ struct clk *main_clks[] = {
 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
         .multipliers = multipliers,
         .nr_multipliers = ARRAY_SIZE(multipliers),
 };
 
-enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
-       DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 
 #define DIV4(_str, _reg, _bit, _mask, _flags) \
   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
@@ -130,11 +133,20 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
         [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
         [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
-        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
-        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
+};
+
+enum { DIV4_IRDA, DIV4_ENABLE_NR };
+
+struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
         [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
 };
 
+enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
+
+struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
+        [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
+        [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
+};
 struct clk div6_clks[] = {
         SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
 };
@@ -216,6 +228,14 @@ int __init arch_clk_init(void)
                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 
         if (!ret)
+                ret = sh_clk_div4_enable_register(div4_enable_clks,
+                                        DIV4_ENABLE_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_div4_reparent_register(div4_reparent_clks,
+                                        DIV4_REPARENT_NR, &div4_table);
+
+        if (!ret)
                 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
 
         if (!ret)
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
index 9db743802f06..6707061fbf54 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -127,13 +127,28 @@ struct clk *main_clks[] = {
         &div3_clk,
 };
 
+static void div4_kick(struct clk *clk)
+{
+        unsigned long value;
+
+        /* set KICK bit in FRQCRA to update hardware setting */
+        value = __raw_readl(FRQCRA);
+        value |= (1 << 31);
+        __raw_writel(value, FRQCRA);
+}
+
 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = divisors,
         .nr_divisors = ARRAY_SIZE(divisors),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+        .kick = div4_kick,
+};
+
 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 
 #define DIV4(_str, _reg, _bit, _mask, _flags) \
@@ -144,7 +159,7 @@ struct clk div4_clks[DIV4_NR] = {
         [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
         [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
         [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
-        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
+        [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 };
 
 struct clk div6_clks[] = {
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index ddc235ca9664..86aae60677dc 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -35,7 +35,7 @@ static struct clk_ops sh7757_master_clk_ops = {
 
 static void module_clk_recalc(struct clk *clk)
 {
-        int idx = ctrl_inl(FRQCR) & 0x0000000f;
+        int idx = __raw_readl(FRQCR) & 0x0000000f;
         clk->rate = clk->parent->rate / p1fc_divisors[idx];
 }
 
@@ -45,7 +45,7 @@ static struct clk_ops sh7757_module_clk_ops = {
 
 static void bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
+        int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f;
         clk->rate = clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -55,7 +55,7 @@ static struct clk_ops sh7757_bus_clk_ops = {
 
 static void cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
+        int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
         clk->rate = clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -78,7 +78,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static void shyway_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
+        int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
         clk->rate = clk->parent->rate / sfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 370cd47642ef..9f401163e71e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
+        clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
 }
 
 static struct clk_ops sh7763_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7763_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
         return clk->parent->rate / p0fc_divisors[idx];
 }
 
@@ -41,7 +41,7 @@ static struct clk_ops sh7763_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -68,7 +68,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
+        int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index e0b896769205..9e3354365d40 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -21,7 +21,7 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f];
+        clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
 }
 
 static struct clk_ops sh7770_master_clk_ops = {
@@ -30,7 +30,7 @@ static struct clk_ops sh7770_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
+        int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -40,7 +40,7 @@ static struct clk_ops sh7770_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) & 0x000f);
+        int idx = (__raw_readl(FRQCR) & 0x000f);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -50,7 +50,7 @@ static struct clk_ops sh7770_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
+        int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index a249d823578e..150963a6001e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003];
+        clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
 }
 
 static struct clk_ops sh7780_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7780_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQCR) & 0x0003);
+        int idx = (__raw_readl(FRQCR) & 0x0003);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -41,7 +41,7 @@ static struct clk_ops sh7780_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
+        int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -51,7 +51,7 @@ static struct clk_ops sh7780_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
+        int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -74,7 +74,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
+        int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 73abfbf2f16d..d997f0a25b10 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -57,11 +57,15 @@ static struct clk *clks[] = {
 static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
                                24, 32, 36, 48 };
 
-static struct clk_div_mult_table div4_table = {
+static struct clk_div_mult_table div4_div_mult_table = {
         .divisors = div2,
         .nr_divisors = ARRAY_SIZE(div2),
 };
 
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
         DIV4_DU, DIV4_P, DIV4_NR };
 
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index a0e8869071ac..af69fd468703 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -3,11 +3,7 @@
  *
  * SH7786 support for the clock framework
  *
- * Copyright (C) 2008, 2009  Renesas Solutions Corp.
- * Kuninori Morimoto <morimoto.kuninori@renesas.com>
- *
- * Based on SH7785
- *  Copyright (C) 2007  Paul Mundt
+ *  Copyright (C) 2010  Paul Mundt
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -15,127 +11,127 @@
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
 #include <asm/clock.h>
 #include <asm/freq.h>
-#include <asm/io.h>
-
-static int ifc_divisors[] = { 1, 2, 4, 1 };
-static int sfc_divisors[] = { 1, 1, 4, 1 };
-static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
-                             24, 32, 1, 1, 1, 1, 1, 1 };
-static int mfc_divisors[] = { 1, 1, 4, 1 };
-static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
-                              24, 32, 1, 48, 1, 1, 1, 1 };
 
-static void master_clk_init(struct clk *clk)
-{
-        clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
-}
-
-static struct clk_ops sh7786_master_clk_ops = {
-        .init           = master_clk_init,
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .name           = "extal",
+        .id             = -1,
+        .rate           = 33333333,
 };
 
-static unsigned long module_clk_recalc(struct clk *clk)
+static unsigned long pll_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inl(FRQMR1) & 0x000f);
-        return clk->parent->rate / pfc_divisors[idx];
-}
+        int multiplier;
 
-static struct clk_ops sh7786_module_clk_ops = {
-        .recalc         = module_clk_recalc,
-};
+        /*
+         * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
+         * while modes 3, 4, and 5 use an x32.
+         */
+        multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
 
-static unsigned long bus_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
-        return clk->parent->rate / bfc_divisors[idx];
+        return clk->parent->rate * multiplier;
 }
 
-static struct clk_ops sh7786_bus_clk_ops = {
-        .recalc         = bus_clk_recalc,
+static struct clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
 };
 
-static unsigned long cpu_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
-        return clk->parent->rate / ifc_divisors[idx];
-}
-
-static struct clk_ops sh7786_cpu_clk_ops = {
-        .recalc         = cpu_clk_recalc,
+static struct clk pll_clk = {
+        .name           = "pll_clk",
+        .id             = -1,
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
 };
 
-static struct clk_ops *sh7786_clk_ops[] = {
-        &sh7786_master_clk_ops,
-        &sh7786_module_clk_ops,
-        &sh7786_bus_clk_ops,
-        &sh7786_cpu_clk_ops,
+static struct clk *clks[] = {
+        &extal_clk,
+        &pll_clk,
 };
 
-void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
-{
-        if (idx < ARRAY_SIZE(sh7786_clk_ops))
-                *ops = sh7786_clk_ops[idx];
-}
+static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
+                               24, 32, 36, 48 };
 
-static unsigned long shyway_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
-        return clk->parent->rate / sfc_divisors[idx];
-}
-
-static struct clk_ops sh7786_shyway_clk_ops = {
-        .recalc         = shyway_clk_recalc,
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
 };
 
-static struct clk sh7786_shyway_clk = {
-        .name           = "shyway_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7786_shyway_clk_ops,
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
 };
 
-static unsigned long ddr_clk_recalc(struct clk *clk)
-{
-        int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
-        return clk->parent->rate / mfc_divisors[idx];
-}
+enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
 
-static struct clk_ops sh7786_ddr_clk_ops = {
-        .recalc         = ddr_clk_recalc,
-};
+#define DIV4(_str, _bit, _mask, _flags) \
+  SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
 
-static struct clk sh7786_ddr_clk = {
-        .name           = "ddr_clk",
-        .flags          = CLK_ENABLE_ON_INIT,
-        .ops            = &sh7786_ddr_clk_ops,
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
+        [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
+        [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
+        [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
+        [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
+        [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
 };
 
-/*
- * Additional SH7786-specific on-chip clocks that aren't already part of the
- * clock framework
- */
-static struct clk *sh7786_onchip_clocks[] = {
-        &sh7786_shyway_clk,
-        &sh7786_ddr_clk,
+#define MSTPCR0         0xffc40030
+#define MSTPCR1         0xffc40034
+
+static struct clk mstp_clks[] = {
+        /* MSTPCR0 */
+        SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
+        SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
+        SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
+        SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
+        SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
+        SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
+        SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
+        SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
+        SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
+        SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
+        SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
+        SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
+        SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
+        SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
+        SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
+        SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
+        SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
+        SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
+        SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
+        SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
+        SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
+
+        /* MSTPCR1 */
+        SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
+        SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
+        SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
+        SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
+        SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
+        SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
+        SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
+        SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
 };
 
 int __init arch_clk_init(void)
 {
-        struct clk *clk;
         int i, ret = 0;
 
-        cpg_clk_init();
-
-        clk = clk_get(NULL, "master_clk");
-        for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
-                struct clk *clkp = sh7786_onchip_clocks[i];
-
-                clkp->parent = clk;
-                ret |= clk_register(clkp);
-        }
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                ret |= clk_register(clks[i]);
 
-        clk_put(clk);
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
+                                           &div4_table);
+        if (!ret)
+                ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
 
         return ret;
 }
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 23c27d32d982..e75c57bdfa5e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -33,7 +33,7 @@ static int cfc_divisors[] = { 1, 1, 4, 6 };
 
 static void master_clk_init(struct clk *clk)
 {
-        clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK];
+        clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
 }
 
 static struct clk_ops shx3_master_clk_ops = {
@@ -42,7 +42,7 @@ static struct clk_ops shx3_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
         return clk->parent->rate / pfc_divisors[idx];
 }
 
@@ -52,7 +52,7 @@ static struct clk_ops shx3_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
         return clk->parent->rate / bfc_divisors[idx];
 }
 
@@ -62,7 +62,7 @@ static struct clk_ops shx3_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
         return clk->parent->rate / ifc_divisors[idx];
 }
 
@@ -85,7 +85,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
 
 static unsigned long shyway_clk_recalc(struct clk *clk)
 {
-        int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
+        int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
         return clk->parent->rate / cfc_divisors[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index cb9d07bd59f8..0688a7502f86 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -278,6 +278,7 @@ enum {
         HIZA8_LCDC, HIZA8_HIZ,
         HIZA7_LCDC, HIZA7_HIZ,
         HIZA6_LCDC, HIZA6_HIZ,
+        HIZB4_SIUA, HIZB4_HIZ,
         HIZB1_VIO, HIZB1_HIZ,
         HIZB0_VIO, HIZB0_HIZ,
         HIZC15_IRQ7, HIZC15_HIZ,
@@ -546,7 +547,7 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2,
                     HIZB0_VIO, FOE_VIO_VD2),
         PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2,
-                    HIZB1_VIO, HIZB1_VIO, FCE_VIO_HD2),
+                    HIZB1_VIO, FCE_VIO_HD2),
         PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2,
                     HIZB1_VIO, FRB_VIO_CLK2),
 
@@ -658,14 +659,14 @@ static pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(SDHICLK_MARK, SDHICLK),
 
         /* SIU - Port A */
-        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, SIUAOLR_SIOF1_SYNC),
-        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, SIUAOBT_SIOF1_SCK),
-        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, SIUAISLD_SIOF1_RXD),
-        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, SIUAILR_SIOF1_SS2),
-        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, SIUAIBT_SIOF1_SS1),
-        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, SIUAOSLD_SIOF1_TXD),
-        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, PSB1_SIUMCKA, PTK0),
-        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, PTK0),
+        PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC),
+        PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK),
+        PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD),
+        PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2),
+        PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1),
+        PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD),
+        PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0),
+        PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0),
 
         /* SIU - Port B */
         PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR),
@@ -1612,7 +1613,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
                 0, 0,
                 0, 0,
                 0, 0,
-                0, 0,
+                HIZB4_SIUA, HIZB4_HIZ,
                 0, 0,
                 0, 0,
                 HIZB1_VIO, HIZB1_HIZ,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index b5335b5e309c..ef3f97827808 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -446,6 +446,8 @@ void __init plat_early_device_setup(void)
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -461,7 +463,6 @@ enum {
         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
-        SDHI0, SDHI1, SDHI2, SDHI3,
         CMT, TSIF, SIU, TWODG,
         TMU0, TMU1, TMU2,
         IRDA, JPU, LCDC,
@@ -494,8 +495,8 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
-        INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
-        INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
+        INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
+        INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
@@ -513,7 +514,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
-        INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
@@ -535,7 +535,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
+          { DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -573,9 +573,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7722",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 772b9265d0e4..85c61f624702 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -592,14 +592,17 @@ void __init plat_early_device_setup(void)
 #define RAMCR_CACHE_L2FC        0x0002
 #define RAMCR_CACHE_L2E         0x0001
 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
-void __uses_jump_to_uncached l2_cache_init(void)
+
+void l2_cache_init(void)
 {
         /* Enable L2 cache */
-        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+        __raw_writel(L2_CACHE_ENABLE, RAMCR);
 }
 
 enum {
         UNUSED=0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -622,7 +625,6 @@ enum {
         SCIFA_SCIFA1,
         FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
         I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
-        SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
         CMT_CMTI,
         TSIF_TSIFI,
         SIU_SIUI,
@@ -630,7 +632,6 @@ enum {
         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
         IRDA_IRDAI,
         ATAPI_ATAPII,
-        SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
         VEU2H1_VEU2HI,
         LCDC_LCDCI,
         TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
@@ -701,9 +702,9 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(I2C_WAITI,0xE40),
         INTC_VECT(I2C_DTEI,0xE60),
 
-        INTC_VECT(SDHI0_SDHII0,0xE80),
-        INTC_VECT(SDHI0_SDHII1,0xEA0),
-        INTC_VECT(SDHI0_SDHII2,0xEC0),
+        INTC_VECT(SDHI0, 0xE80),
+        INTC_VECT(SDHI0, 0xEA0),
+        INTC_VECT(SDHI0, 0xEC0),
 
         INTC_VECT(CMT_CMTI,0xF00),
         INTC_VECT(TSIF_TSIFI,0xF20),
@@ -717,9 +718,9 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(IRDA_IRDAI,0x480),
         INTC_VECT(ATAPI_ATAPII,0x4A0),
 
-        INTC_VECT(SDHI1_SDHII0,0x4E0),
-        INTC_VECT(SDHI1_SDHII1,0x500),
-        INTC_VECT(SDHI1_SDHII2,0x520),
+        INTC_VECT(SDHI1, 0x4E0),
+        INTC_VECT(SDHI1, 0x500),
+        INTC_VECT(SDHI1, 0x520),
 
         INTC_VECT(VEU2H1_VEU2HI,0x560),
         INTC_VECT(LCDC_LCDCI,0x580),
@@ -738,15 +739,14 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
         INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
         INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
-        INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
         INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
         INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
-        INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
 };
 
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
-          { 0,  TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
+          { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
+            0, DISABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
@@ -763,7 +763,8 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
+          { 0, DISABLED, ENABLED, ENABLED,
+            0, 0, SCIFA_SCIFA2, SIU_SIUI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
@@ -803,9 +804,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7723",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index d32f96c1cc15..31e3451f7e3d 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -714,14 +714,17 @@ void __init plat_early_device_setup(void)
 #define RAMCR_CACHE_L2FC        0x0002
 #define RAMCR_CACHE_L2E         0x0001
 #define L2_CACHE_ENABLE         (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
-void __uses_jump_to_uncached l2_cache_init(void)
+
+void l2_cache_init(void)
 {
         /* Enable L2 cache */
-        ctrl_outl(L2_CACHE_ENABLE, RAMCR);
+        __raw_writel(L2_CACHE_ENABLE, RAMCR);
 }
 
 enum {
         UNUSED = 0,
+        ENABLED,
+        DISABLED,
 
         /* interrupt sources */
         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
@@ -750,14 +753,12 @@ enum {
         ETHI,
         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
-        SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
         CMT,
         TSIF,
         FSI,
         SCIFA5,
         TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
         IRDA,
-        SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
         JPU,
         _2DDMAC,
         MMC_MMC2I, MMC_MMC3I,
@@ -839,10 +840,10 @@ static struct intc_vect vectors[] __initdata = {
         INTC_VECT(I2C0_WAITI, 0xE40),
         INTC_VECT(I2C0_DTEI, 0xE60),
 
-        INTC_VECT(SDHI0_SDHII0, 0xE80),
-        INTC_VECT(SDHI0_SDHII1, 0xEA0),
-        INTC_VECT(SDHI0_SDHII2, 0xEC0),
-        INTC_VECT(SDHI0_SDHII3, 0xEE0),
+        INTC_VECT(SDHI0, 0xE80),
+        INTC_VECT(SDHI0, 0xEA0),
+        INTC_VECT(SDHI0, 0xEC0),
+        INTC_VECT(SDHI0, 0xEE0),
 
         INTC_VECT(CMT,    0xF00),
         INTC_VECT(TSIF,   0xF20),
@@ -855,9 +856,9 @@ static struct intc_vect vectors[] __initdata = {
 
         INTC_VECT(IRDA,    0x480),
 
-        INTC_VECT(SDHI1_SDHII0, 0x4E0),
-        INTC_VECT(SDHI1_SDHII1, 0x500),
-        INTC_VECT(SDHI1_SDHII2, 0x520),
+        INTC_VECT(SDHI1, 0x4E0),
+        INTC_VECT(SDHI1, 0x500),
+        INTC_VECT(SDHI1, 0x520),
 
         INTC_VECT(JPU, 0x560),
         INTC_VECT(_2DDMAC, 0x4A0),
@@ -883,8 +884,6 @@ static struct intc_group groups[] __initdata = {
         INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
-        INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
-        INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
         INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
         INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
 };
@@ -892,7 +891,7 @@ static struct intc_group groups[] __initdata = {
 static struct intc_mask_reg mask_registers[] __initdata = {
         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
           { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
-            0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
+            0, DISABLED, ENABLED, ENABLED } },
         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
           { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
             DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
@@ -914,7 +913,7 @@ static struct intc_mask_reg mask_registers[] __initdata = {
           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
             I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
-          { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
+          { DISABLED, DISABLED, ENABLED, ENABLED,
             0, 0, SCIFA5, FSI } },
         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
           { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
@@ -961,9 +960,13 @@ static struct intc_mask_reg ack_registers[] __initdata = {
           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 };
 
-static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
-                             mask_registers, prio_registers, sense_registers,
-                             ack_registers);
+static struct intc_desc intc_desc __initdata = {
+        .name = "sh7724",
+        .force_enable = ENABLED,
+        .force_disable = DISABLED,
+        .hw = INTC_HW_DESC(vectors, groups, mask_registers,
+                           prio_registers, sense_registers, ack_registers),
+};
 
 void __init plat_irq_setup(void)
 {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 37e32efbbaa7..e75edf58796a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -487,17 +487,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -507,32 +507,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 6aba26fec416..7f6b0a5f7f82 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -538,11 +538,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         register_intc_controller(&intc_desc);
 }
@@ -552,27 +552,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index c1643bc9590d..86d681ecf90e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -694,17 +694,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -714,27 +714,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index c310558490d5..f8f21618d785 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -461,17 +461,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ7-0 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -481,27 +481,27 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ:
                 /* select IRQ mode for IRL3-0 + IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
                 register_intc_controller(&intc_irq_desc);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl7654_desc);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_irl3210_desc);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index f685b9b21999..23448d8c6711 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -541,17 +541,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         /* disable holding function, ie enable "SH-4 Mode" */
-        ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -561,32 +561,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 71673487ace0..7e585320710a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -867,14 +867,14 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
 void __init plat_irq_setup(void)
 {
         /* disable IRQ3-0 + IRQ7-4 */
-        ctrl_outl(0xff000000, INTC_INTMSK0);
+        __raw_writel(0xff000000, INTC_INTMSK0);
 
         /* disable IRL3-0 + IRL7-4 */
-        ctrl_outl(0xc0000000, INTC_INTMSK1);
-        ctrl_outl(0xfffefffe, INTC_INTMSK2);
+        __raw_writel(0xc0000000, INTC_INTMSK1);
+        __raw_writel(0xfffefffe, INTC_INTMSK2);
 
         /* select IRL mode for IRL3-0 + IRL7-4 */
-        ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+        __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 
         register_intc_controller(&intc_desc);
 }
@@ -884,32 +884,32 @@ void __init plat_irq_setup_pins(int mode)
         switch (mode) {
         case IRQ_MODE_IRQ7654:
                 /* select IRQ mode for IRL7-4 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq4567);
                 break;
         case IRQ_MODE_IRQ3210:
                 /* select IRQ mode for IRL3-0 */
-                ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+                __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
                 register_intc_controller(&intc_desc_irq0123);
                 break;
         case IRQ_MODE_IRL7654:
                 /* enable IRL7-4 but don't provide any masking */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
-                ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL3210:
                 /* enable IRL0-3 but don't provide any masking */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
-                ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
                 break;
         case IRQ_MODE_IRL7654_MASK:
                 /* enable IRL7-4 and mask using cpu intc controller */
-                ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+                __raw_writel(0x40000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl4567);
                 break;
         case IRQ_MODE_IRL3210_MASK:
                 /* enable IRL0-3 and mask using cpu intc controller */
-                ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+                __raw_writel(0x80000000, INTC_INTMSKCLR1);
                 register_intc_controller(&intc_desc_irl0123);
                 break;
         default:
diff --git a/arch/sh/kernel/cpu/sh4a/smp-shx3.c b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
index 5863e0c4d02f..11bf4c1e25c0 100644
--- a/arch/sh/kernel/cpu/sh4a/smp-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/smp-shx3.c
@@ -78,7 +78,10 @@ void __init plat_prepare_cpus(unsigned int max_cpus)
 
 void plat_start_cpu(unsigned int cpu, unsigned long entry_point)
 {
-        __raw_writel(entry_point, RESET_REG(cpu));
+        if (__in_29bit_mode())
+                __raw_writel(entry_point, RESET_REG(cpu));
+        else
+                __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu));
 
         if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP))
                 __raw_writel(STBCR_MSTP, STBCR_REG(cpu));
diff --git a/arch/sh/kernel/cpu/sh4a/ubc.c b/arch/sh/kernel/cpu/sh4a/ubc.c
new file mode 100644
index 000000000000..efb2745bcb36
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/ubc.c
@@ -0,0 +1,133 @@
+/*
+ * arch/sh/kernel/cpu/sh4a/ubc.c
+ *
+ * On-chip UBC support for SH-4A CPUs.
+ *
+ * Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <asm/hw_breakpoint.h>
+
+#define UBC_CBR(idx)    (0xff200000 + (0x20 * idx))
+#define UBC_CRR(idx)    (0xff200004 + (0x20 * idx))
+#define UBC_CAR(idx)    (0xff200008 + (0x20 * idx))
+#define UBC_CAMR(idx)   (0xff20000c + (0x20 * idx))
+
+#define UBC_CCMFR       0xff200600
+#define UBC_CBCR        0xff200620
+
+/* CRR */
+#define UBC_CRR_PCB     (1 << 1)
+#define UBC_CRR_BIE     (1 << 0)
+
+/* CBR */
+#define UBC_CBR_CE      (1 << 0)
+
+static struct sh_ubc sh4a_ubc;
+
+static void sh4a_ubc_enable(struct arch_hw_breakpoint *info, int idx)
+{
+        __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx));
+        __raw_writel(info->address, UBC_CAR(idx));
+}
+
+static void sh4a_ubc_disable(struct arch_hw_breakpoint *info, int idx)
+{
+        __raw_writel(0, UBC_CBR(idx));
+        __raw_writel(0, UBC_CAR(idx));
+}
+
+static void sh4a_ubc_enable_all(unsigned long mask)
+{
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                if (mask & (1 << i))
+                        __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE,
+                                     UBC_CBR(i));
+}
+
+static void sh4a_ubc_disable_all(void)
+{
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE,
+                             UBC_CBR(i));
+}
+
+static unsigned long sh4a_ubc_active_mask(void)
+{
+        unsigned long active = 0;
+        int i;
+
+        for (i = 0; i < sh4a_ubc.num_events; i++)
+                if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE)
+                        active |= (1 << i);
+
+        return active;
+}
+
+static unsigned long sh4a_ubc_triggered_mask(void)
+{
+        return __raw_readl(UBC_CCMFR);
+}
+
+static void sh4a_ubc_clear_triggered_mask(unsigned long mask)
+{
+        __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR);
+}
+
+static struct sh_ubc sh4a_ubc = {
+        .name                   = "SH-4A",
+        .num_events             = 2,
+        .trap_nr                = 0x1e0,
+        .enable                 = sh4a_ubc_enable,
+        .disable                = sh4a_ubc_disable,
+        .enable_all             = sh4a_ubc_enable_all,
+        .disable_all            = sh4a_ubc_disable_all,
+        .active_mask            = sh4a_ubc_active_mask,
+        .triggered_mask         = sh4a_ubc_triggered_mask,
+        .clear_triggered_mask   = sh4a_ubc_clear_triggered_mask,
+};
+
+static int __init sh4a_ubc_init(void)
+{
+        struct clk *ubc_iclk = clk_get(NULL, "ubc0");
+        int i;
+
+        /*
+         * The UBC MSTP bit is optional, as not all platforms will have
+         * it. Just ignore it if we can't find it.
+         */
+        if (IS_ERR(ubc_iclk))
+                ubc_iclk = NULL;
+
+        clk_enable(ubc_iclk);
+
+        __raw_writel(0, UBC_CBCR);
+
+        for (i = 0; i < sh4a_ubc.num_events; i++) {
+                __raw_writel(0, UBC_CAMR(i));
+                __raw_writel(0, UBC_CBR(i));
+
+                __raw_writel(UBC_CRR_BIE | UBC_CRR_PCB, UBC_CRR(i));
+
+                /* dummy read for write posting */
+                (void)__raw_readl(UBC_CRR(i));
+        }
+
+        clk_disable(ubc_iclk);
+
+        sh4a_ubc.clk = ubc_iclk;
+
+        return register_sh_ubc(&sh4a_ubc);
+}
+arch_initcall(sh4a_ubc_init);
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 7f864ebc51d3..9cfc19b8dbe4 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -24,7 +24,7 @@ static unsigned long cprc_base;
 
 static void master_clk_init(struct clk *clk)
 {
-        int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007;
+        int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007;
         clk->rate *= ifc_table[idx];
 }
 
@@ -34,7 +34,7 @@ static struct clk_ops sh5_master_clk_ops = {
 
 static unsigned long module_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
+        int idx = (__raw_readw(cprc_base) >> 12) & 0x0007;
         return clk->parent->rate / ifc_table[idx];
 }
 
@@ -44,7 +44,7 @@ static struct clk_ops sh5_module_clk_ops = {
 
 static unsigned long bus_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
+        int idx = (__raw_readw(cprc_base) >> 3) & 0x0007;
         return clk->parent->rate / ifc_table[idx];
 }
 
@@ -54,7 +54,7 @@ static struct clk_ops sh5_bus_clk_ops = {
 
 static unsigned long cpu_clk_recalc(struct clk *clk)
 {
-        int idx = (ctrl_inw(cprc_base) & 0x0007);
+        int idx = (__raw_readw(cprc_base) & 0x0007);
         return clk->parent->rate / ifc_table[idx];
 }
 
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index 8f13f73cb2cb..6b80295dd7a4 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -187,7 +187,7 @@ trap_jtable:
         .rept 6
                 .long do_exception_error        /* 0x880 - 0x920 */
         .endr
-        .long   do_software_break_point /* 0x940 */
+        .long   breakpoint_trap_handler /* 0x940 */
         .long   do_exception_error              /* 0x960 */
         .long   do_single_step          /* 0x980 */
 
@@ -1124,7 +1124,7 @@ fpu_error_or_IRQA:
         pta     its_IRQ, tr0
         beqi/l  r4, EVENT_INTERRUPT, tr0
 #ifdef CONFIG_SH_FPU
-        movi    do_fpu_state_restore, r6
+        movi    fpu_state_restore_trap_handler, r6
 #else
         movi    do_exception_error, r6
 #endif
@@ -1135,7 +1135,7 @@ fpu_error_or_IRQB:
         pta     its_IRQ, tr0
         beqi/l  r4, EVENT_INTERRUPT, tr0
 #ifdef CONFIG_SH_FPU
-        movi    do_fpu_state_restore, r6
+        movi    fpu_state_restore_trap_handler, r6
 #else
         movi    do_exception_error, r6
 #endif
diff --git a/arch/sh/kernel/cpu/sh5/fpu.c b/arch/sh/kernel/cpu/sh5/fpu.c
index 4648ccee6c4d..4b3bb35e99f3 100644
--- a/arch/sh/kernel/cpu/sh5/fpu.c
+++ b/arch/sh/kernel/cpu/sh5/fpu.c
@@ -15,24 +15,6 @@
 #include <linux/sched.h>
 #include <linux/signal.h>
 #include <asm/processor.h>
-#include <asm/user.h>
-#include <asm/io.h>
-#include <asm/fpu.h>
-
-/*
- * Initially load the FPU with signalling NANS.  This bit pattern
- * has the property that no matter whether considered as single or as
- * double precision, it still represents a signalling NAN.
- */
-#define sNAN64          0xFFFFFFFFFFFFFFFFULL
-#define sNAN32          0xFFFFFFFFUL
-
-static union sh_fpu_union init_fpuregs = {
-        .hard = {
-                .fp_regs = { [0 ... 63] = sNAN32 },
-                .fpscr = FPSCR_INIT
-        }
-};
 
 void save_fpu(struct task_struct *tsk)
 {
@@ -72,12 +54,11 @@ void save_fpu(struct task_struct *tsk)
                      "fgetscr   fr63\n\t"
                      "fst.s     %0, (32*8), fr63\n\t"
                 : /* no output */
-                : "r" (&tsk->thread.fpu.hard)
+                : "r" (&tsk->thread.xstate->hardfpu)
                 : "memory");
 }
 
-static inline void
-fpload(struct sh_fpu_hard_struct *fpregs)
+void restore_fpu(struct task_struct *tsk)
 {
         asm volatile("fld.p     %0, (0*8), fp0\n\t"
                      "fld.p     %0, (1*8), fp2\n\t"
@@ -116,16 +97,11 @@ fpload(struct sh_fpu_hard_struct *fpregs)
 
                      "fld.p     %0, (31*8), fp62\n\t"
                 : /* no output */
-                : "r" (fpregs) );
-}
-
-void fpinit(struct sh_fpu_hard_struct *fpregs)
-{
-        *fpregs = init_fpuregs.hard;
+                : "r" (&tsk->thread.xstate->hardfpu)
+                : "memory");
 }
 
-asmlinkage void
-do_fpu_error(unsigned long ex, struct pt_regs *regs)
+asmlinkage void do_fpu_error(unsigned long ex, struct pt_regs *regs)
 {
         struct task_struct *tsk = current;
 
@@ -133,35 +109,6 @@ do_fpu_error(unsigned long ex, struct pt_regs *regs)
 
         tsk->thread.trap_no = 11;
         tsk->thread.error_code = 0;
-        force_sig(SIGFPE, tsk);
-}
-
-
-asmlinkage void
-do_fpu_state_restore(unsigned long ex, struct pt_regs *regs)
-{
-        void die(const char *str, struct pt_regs *regs, long err);
-
-        if (! user_mode(regs))
-                die("FPU used in kernel", regs, ex);
 
-        regs->sr &= ~SR_FD;
-
-        if (last_task_used_math == current)
-                return;
-
-        enable_fpu();
-        if (last_task_used_math != NULL)
-                /* Other processes fpu state, save away */
-                save_fpu(last_task_used_math);
-
-        last_task_used_math = current;
-        if (used_math()) {
-                fpload(&current->thread.fpu.hard);
-        } else {
-                /* First time FPU user.  */
-                fpload(&init_fpuregs.hard);
-                set_used_math();
-        }
-        disable_fpu();
+        force_sig(SIGFPE, tsk);
 }
diff --git a/arch/sh/kernel/cpu/shmobile/pm.c b/arch/sh/kernel/cpu/shmobile/pm.c
index ca029a44743c..e55968712706 100644
--- a/arch/sh/kernel/cpu/shmobile/pm.c
+++ b/arch/sh/kernel/cpu/shmobile/pm.c
@@ -33,7 +33,8 @@ ATOMIC_NOTIFIER_HEAD(sh_mobile_post_sleep_notifier_list);
 #define SUSP_MODE_SLEEP         (SUSP_SH_SLEEP)
 #define SUSP_MODE_SLEEP_SF      (SUSP_SH_SLEEP | SUSP_SH_SF)
 #define SUSP_MODE_STANDBY_SF    (SUSP_SH_STANDBY | SUSP_SH_SF)
-#define SUSP_MODE_RSTANDBY      (SUSP_SH_RSTANDBY | SUSP_SH_MMU | SUSP_SH_SF)
+#define SUSP_MODE_RSTANDBY_SF \
+        (SUSP_SH_RSTANDBY | SUSP_SH_MMU | SUSP_SH_REGS | SUSP_SH_SF)
  /*
   * U-standby mode is unsupported since it needs bootloader hacks
   */
diff --git a/arch/sh/kernel/cpu/shmobile/sleep.S b/arch/sh/kernel/cpu/shmobile/sleep.S
index e9dd7fa0abd2..e6aac65f5750 100644
--- a/arch/sh/kernel/cpu/shmobile/sleep.S
+++ b/arch/sh/kernel/cpu/shmobile/sleep.S
@@ -48,8 +48,48 @@ ENTRY(sh_mobile_sleep_enter_start)
         stc     sr, r0
         mov.l   r0, @(SH_SLEEP_SR, r5)
 
-        /* save sp */
+        /* save general purpose registers to stack if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_REGS, r0
+        bt      skip_regs_save
+
+        sts.l   pr, @-r15
+        mov.l   r14, @-r15
+        mov.l   r13, @-r15
+        mov.l   r12, @-r15
+        mov.l   r11, @-r15
+        mov.l   r10, @-r15
+        mov.l   r9, @-r15
+        mov.l   r8, @-r15
+
+        /* make sure bank0 is selected, save low registers */
+        mov.l   rb_bit, r9
+        not     r9, r9
+        bsr     set_sr
+         mov    #0, r10
+
+        bsr     save_low_regs
+         nop
+
+        /* switch to bank 1, save low registers */
+        mov.l   rb_bit, r10
+        bsr     set_sr
+         mov    #-1, r9
+
+        bsr     save_low_regs
+         nop
+
+        /* switch back to bank 0 */
+        mov.l   rb_bit, r9
+        not     r9, r9
+        bsr     set_sr
+         mov    #0, r10
+
+skip_regs_save:
+
+        /* save sp, also set to internal ram */
         mov.l   r15, @(SH_SLEEP_SP, r5)
+        mov     r5, r15
 
         /* save stbcr */
         bsr     save_register
@@ -60,7 +100,7 @@ ENTRY(sh_mobile_sleep_enter_start)
         tst     #SUSP_SH_MMU, r0
         bt      skip_mmu_save_disable
 
-       /* save mmu state */
+        /* save mmu state */
         bsr     save_register
          mov    #SH_SLEEP_REG_PTEH, r0
 
@@ -177,6 +217,29 @@ get_register:
         mov.l   @(r0, r5), r0
         rts
          nop
+
+set_sr:
+        stc     sr, r8
+        and     r9, r8
+        or      r10, r8
+        ldc     r8, sr
+        rts
+         nop
+
+save_low_regs:
+        mov.l   r7, @-r15
+        mov.l   r6, @-r15
+        mov.l   r5, @-r15
+        mov.l   r4, @-r15
+        mov.l   r3, @-r15
+        mov.l   r2, @-r15
+        mov.l   r1, @-r15
+        rts
+         mov.l  r0, @-r15
+
+        .balign 4
+rb_bit: .long   0x20000000 ! RB=1
+
 ENTRY(sh_mobile_sleep_enter_end)
 
         .balign 4
@@ -270,6 +333,40 @@ skip_restore_sf:
         icbi    @r0
 
 skip_restore_mmu:
+
+        /* restore general purpose registers if needed */
+        mov.l   @(SH_SLEEP_MODE, r5), r0
+        tst     #SUSP_SH_REGS, r0
+        bt      skip_restore_regs
+
+        /* switch to bank 1, restore low registers */
+        mov.l   _rb_bit, r10
+        bsr     _set_sr
+         mov    #-1, r9
+
+        bsr     restore_low_regs
+         nop
+
+        /* switch to bank0, restore low registers */
+        mov.l   _rb_bit, r9
+        not     r9, r9
+        bsr     _set_sr
+         mov    #0, r10
+
+        bsr     restore_low_regs
+         nop
+
+        /* restore the rest of the registers */
+        mov.l   @r15+, r8
+        mov.l   @r15+, r9
+        mov.l   @r15+, r10
+        mov.l   @r15+, r11
+        mov.l   @r15+, r12
+        mov.l   @r15+, r13
+        mov.l   @r15+, r14
+        lds.l   @r15+, pr
+
+skip_restore_regs:
         rte
          nop
 
@@ -283,6 +380,26 @@ restore_register:
         rts
          nop
 
+_set_sr:
+        stc     sr, r8
+        and     r9, r8
+        or      r10, r8
+        ldc     r8, sr
+        rts
+         nop
+
+restore_low_regs:
+        mov.l   @r15+, r0
+        mov.l   @r15+, r1
+        mov.l   @r15+, r2
+        mov.l   @r15+, r3
+        mov.l   @r15+, r4
+        mov.l   @r15+, r5
+        mov.l   @r15+, r6
+        rts
+         mov.l  @r15+, r7
+
         .balign 4
+_rb_bit:        .long   0x20000000 ! RB=1
 1:      .long   ~0x7ff
 ENTRY(sh_mobile_sleep_resume_end)
diff --git a/arch/sh/kernel/debugtraps.S b/arch/sh/kernel/debugtraps.S
index 591741383ee6..7a1b46fec0f4 100644
--- a/arch/sh/kernel/debugtraps.S
+++ b/arch/sh/kernel/debugtraps.S
@@ -13,7 +13,6 @@
 #include <linux/linkage.h>
 
 #if !defined(CONFIG_KGDB)
-#define breakpoint_trap_handler         debug_trap_handler
 #define singlestep_trap_handler         debug_trap_handler
 #endif
 
diff --git a/arch/sh/kernel/dwarf.c b/arch/sh/kernel/dwarf.c
index e51168064e56..bd1c497280a6 100644
--- a/arch/sh/kernel/dwarf.c
+++ b/arch/sh/kernel/dwarf.c
@@ -39,10 +39,10 @@ static mempool_t *dwarf_frame_pool;
 static struct kmem_cache *dwarf_reg_cachep;
 static mempool_t *dwarf_reg_pool;
 
-static LIST_HEAD(dwarf_cie_list);
+static struct rb_root cie_root;
 static DEFINE_SPINLOCK(dwarf_cie_lock);
 
-static LIST_HEAD(dwarf_fde_list);
+static struct rb_root fde_root;
 static DEFINE_SPINLOCK(dwarf_fde_lock);
 
 static struct dwarf_cie *cached_cie;
@@ -301,7 +301,8 @@ static inline int dwarf_entry_len(char *addr, unsigned long *len)
  */
 static struct dwarf_cie *dwarf_lookup_cie(unsigned long cie_ptr)
 {
-        struct dwarf_cie *cie;
+        struct rb_node **rb_node = &cie_root.rb_node;
+        struct dwarf_cie *cie = NULL;
         unsigned long flags;
 
         spin_lock_irqsave(&dwarf_cie_lock, flags);
@@ -315,16 +316,24 @@ static struct dwarf_cie *dwarf_lookup_cie(unsigned long cie_ptr)
                 goto out;
         }
 
-        list_for_each_entry(cie, &dwarf_cie_list, link) {
-                if (cie->cie_pointer == cie_ptr) {
-                        cached_cie = cie;
-                        break;
+        while (*rb_node) {
+                struct dwarf_cie *cie_tmp;
+
+                cie_tmp = rb_entry(*rb_node, struct dwarf_cie, node);
+                BUG_ON(!cie_tmp);
+
+                if (cie_ptr == cie_tmp->cie_pointer) {
+                        cie = cie_tmp;
+                        cached_cie = cie_tmp;
+                        goto out;
+                } else {
+                        if (cie_ptr < cie_tmp->cie_pointer)
+                                rb_node = &(*rb_node)->rb_left;
+                        else
+                                rb_node = &(*rb_node)->rb_right;
                 }
         }
 
-        /* Couldn't find the entry in the list. */
-        if (&cie->link == &dwarf_cie_list)
-                cie = NULL;
 out:
         spin_unlock_irqrestore(&dwarf_cie_lock, flags);
         return cie;
@@ -336,25 +345,34 @@ out:
  */
 struct dwarf_fde *dwarf_lookup_fde(unsigned long pc)
 {
-        struct dwarf_fde *fde;
+        struct rb_node **rb_node = &fde_root.rb_node;
+        struct dwarf_fde *fde = NULL;
         unsigned long flags;
 
         spin_lock_irqsave(&dwarf_fde_lock, flags);
 
-        list_for_each_entry(fde, &dwarf_fde_list, link) {
-                unsigned long start, end;
+        while (*rb_node) {
+                struct dwarf_fde *fde_tmp;
+                unsigned long tmp_start, tmp_end;
 
-                start = fde->initial_location;
-                end = fde->initial_location + fde->address_range;
+                fde_tmp = rb_entry(*rb_node, struct dwarf_fde, node);
+                BUG_ON(!fde_tmp);
 
-                if (pc >= start && pc < end)
-                        break;
-        }
+                tmp_start = fde_tmp->initial_location;
+                tmp_end = fde_tmp->initial_location + fde_tmp->address_range;
 
-        /* Couldn't find the entry in the list. */
-        if (&fde->link == &dwarf_fde_list)
-                fde = NULL;
+                if (pc < tmp_start) {
+                        rb_node = &(*rb_node)->rb_left;
+                } else {
+                        if (pc < tmp_end) {
+                                fde = fde_tmp;
+                                goto out;
+                        } else
+                                rb_node = &(*rb_node)->rb_right;
+                }
+        }
 
+out:
         spin_unlock_irqrestore(&dwarf_fde_lock, flags);
 
         return fde;
@@ -552,8 +570,8 @@ extern void ret_from_irq(void);
  *      on the callstack. Each of the lower (older) stack frames are
  *      linked via the "prev" member.
  */
-struct dwarf_frame * dwarf_unwind_stack(unsigned long pc,
-                                        struct dwarf_frame *prev)
+struct dwarf_frame *dwarf_unwind_stack(unsigned long pc,
+                                       struct dwarf_frame *prev)
 {
         struct dwarf_frame *frame;
         struct dwarf_cie *cie;
@@ -708,6 +726,8 @@ bail:
 static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
                            unsigned char *end, struct module *mod)
 {
+        struct rb_node **rb_node = &cie_root.rb_node;
+        struct rb_node *parent;
         struct dwarf_cie *cie;
         unsigned long flags;
         int count;
@@ -802,11 +822,30 @@ static int dwarf_parse_cie(void *entry, void *p, unsigned long len,
         cie->initial_instructions = p;
         cie->instructions_end = end;
 
-        cie->mod = mod;
-
         /* Add to list */
         spin_lock_irqsave(&dwarf_cie_lock, flags);
-        list_add_tail(&cie->link, &dwarf_cie_list);
+
+        while (*rb_node) {
+                struct dwarf_cie *cie_tmp;
+
+                cie_tmp = rb_entry(*rb_node, struct dwarf_cie, node);
+
+                parent = *rb_node;
+
+                if (cie->cie_pointer < cie_tmp->cie_pointer)
+                        rb_node = &parent->rb_left;
+                else if (cie->cie_pointer >= cie_tmp->cie_pointer)
+                        rb_node = &parent->rb_right;
+                else
+                        WARN_ON(1);
+        }
+
+        rb_link_node(&cie->node, parent, rb_node);
+        rb_insert_color(&cie->node, &cie_root);
+
+        if (mod != NULL)
+                list_add_tail(&cie->link, &mod->arch.cie_list);
+
         spin_unlock_irqrestore(&dwarf_cie_lock, flags);
 
         return 0;
@@ -816,6 +855,8 @@ static int dwarf_parse_fde(void *entry, u32 entry_type,
                            void *start, unsigned long len,
                            unsigned char *end, struct module *mod)
 {
+        struct rb_node **rb_node = &fde_root.rb_node;
+        struct rb_node *parent;
         struct dwarf_fde *fde;
         struct dwarf_cie *cie;
         unsigned long flags;
@@ -863,11 +904,38 @@ static int dwarf_parse_fde(void *entry, u32 entry_type,
         fde->instructions = p;
         fde->end = end;
 
-        fde->mod = mod;
-
         /* Add to list. */
         spin_lock_irqsave(&dwarf_fde_lock, flags);
-        list_add_tail(&fde->link, &dwarf_fde_list);
+
+        while (*rb_node) {
+                struct dwarf_fde *fde_tmp;
+                unsigned long tmp_start, tmp_end;
+                unsigned long start, end;
+
+                fde_tmp = rb_entry(*rb_node, struct dwarf_fde, node);
+
+                start = fde->initial_location;
+                end = fde->initial_location + fde->address_range;
+
+                tmp_start = fde_tmp->initial_location;
+                tmp_end = fde_tmp->initial_location + fde_tmp->address_range;
+
+                parent = *rb_node;
+
+                if (start < tmp_start)
+                        rb_node = &parent->rb_left;
+                else if (start >= tmp_end)
+                        rb_node = &parent->rb_right;
+                else
+                        WARN_ON(1);
+        }
+
+        rb_link_node(&fde->node, parent, rb_node);
+        rb_insert_color(&fde->node, &fde_root);
+
+        if (mod != NULL)
+                list_add_tail(&fde->link, &mod->arch.fde_list);
+
         spin_unlock_irqrestore(&dwarf_fde_lock, flags);
 
         return 0;
@@ -912,19 +980,29 @@ static struct unwinder dwarf_unwinder = {
 
 static void dwarf_unwinder_cleanup(void)
 {
-        struct dwarf_cie *cie, *cie_tmp;
-        struct dwarf_fde *fde, *fde_tmp;
+        struct rb_node **fde_rb_node = &fde_root.rb_node;
+        struct rb_node **cie_rb_node = &cie_root.rb_node;
 
         /*
          * Deallocate all the memory allocated for the DWARF unwinder.
          * Traverse all the FDE/CIE lists and remove and free all the
          * memory associated with those data structures.
          */
-        list_for_each_entry_safe(cie, cie_tmp, &dwarf_cie_list, link)
-                kfree(cie);
+        while (*fde_rb_node) {
+                struct dwarf_fde *fde;
 
-        list_for_each_entry_safe(fde, fde_tmp, &dwarf_fde_list, link)
+                fde = rb_entry(*fde_rb_node, struct dwarf_fde, node);
+                rb_erase(*fde_rb_node, &fde_root);
                 kfree(fde);
+        }
+
+        while (*cie_rb_node) {
+                struct dwarf_cie *cie;
+
+                cie = rb_entry(*cie_rb_node, struct dwarf_cie, node);
+                rb_erase(*cie_rb_node, &cie_root);
+                kfree(cie);
+        }
 
         kmem_cache_destroy(dwarf_reg_cachep);
         kmem_cache_destroy(dwarf_frame_cachep);
@@ -1024,6 +1102,8 @@ int module_dwarf_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
 
         /* Did we find the .eh_frame section? */
         if (i != hdr->e_shnum) {
+                INIT_LIST_HEAD(&me->arch.cie_list);
+                INIT_LIST_HEAD(&me->arch.fde_list);
                 err = dwarf_parse_section((char *)start, (char *)end, me);
                 if (err) {
                         printk(KERN_WARNING "%s: failed to parse DWARF info\n",
@@ -1044,38 +1124,26 @@ int module_dwarf_finalize(const Elf_Ehdr *hdr, const Elf_Shdr *sechdrs,
  */
 void module_dwarf_cleanup(struct module *mod)
 {
-        struct dwarf_fde *fde;
-        struct dwarf_cie *cie;
+        struct dwarf_fde *fde, *ftmp;
+        struct dwarf_cie *cie, *ctmp;
         unsigned long flags;
 
         spin_lock_irqsave(&dwarf_cie_lock, flags);
 
-again_cie:
-        list_for_each_entry(cie, &dwarf_cie_list, link) {
-                if (cie->mod == mod)
-                        break;
-        }
-
-        if (&cie->link != &dwarf_cie_list) {
+        list_for_each_entry_safe(cie, ctmp, &mod->arch.cie_list, link) {
                 list_del(&cie->link);
+                rb_erase(&cie->node, &cie_root);
                 kfree(cie);
-                goto again_cie;
         }
 
         spin_unlock_irqrestore(&dwarf_cie_lock, flags);
 
         spin_lock_irqsave(&dwarf_fde_lock, flags);
 
-again_fde:
-        list_for_each_entry(fde, &dwarf_fde_list, link) {
-                if (fde->mod == mod)
-                        break;
-        }
-
-        if (&fde->link != &dwarf_fde_list) {
+        list_for_each_entry_safe(fde, ftmp, &mod->arch.fde_list, link) {
                 list_del(&fde->link);
+                rb_erase(&fde->node, &fde_root);
                 kfree(fde);
-                goto again_fde;
         }
 
         spin_unlock_irqrestore(&dwarf_fde_lock, flags);
@@ -1094,8 +1162,6 @@ again_fde:
 static int __init dwarf_unwinder_init(void)
 {
         int err;
-        INIT_LIST_HEAD(&dwarf_cie_list);
-        INIT_LIST_HEAD(&dwarf_fde_list);
 
         dwarf_frame_cachep = kmem_cache_create("dwarf_frames",
                         sizeof(struct dwarf_frame), 0,
diff --git a/arch/sh/kernel/early_printk.c b/arch/sh/kernel/early_printk.c
deleted file mode 100644
index f8bb50c6e050..000000000000
--- a/arch/sh/kernel/early_printk.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * arch/sh/kernel/early_printk.c
- *
- *  Copyright (C) 1999, 2000  Niibe Yutaka
- *  Copyright (C) 2002  M. R. Brown
- *  Copyright (C) 2004 - 2007  Paul Mundt
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/console.h>
-#include <linux/tty.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-
-#include <asm/sh_bios.h>
-
-/*
- *      Print a string through the BIOS
- */
-static void sh_console_write(struct console *co, const char *s,
-                                 unsigned count)
-{
-        sh_bios_console_write(s, count);
-}
-
-/*
- *      Setup initial baud/bits/parity. We do two things here:
- *      - construct a cflag setting for the first rs_open()
- *      - initialize the serial port
- *      Return non-zero if we didn't find a serial port.
- */
-static int __init sh_console_setup(struct console *co, char *options)
-{
-        int     cflag = CREAD | HUPCL | CLOCAL;
-
-        /*
-         *      Now construct a cflag setting.
-         *      TODO: this is a totally bogus cflag, as we have
-         *      no idea what serial settings the BIOS is using, or
-         *      even if its using the serial port at all.
-         */
-        cflag |= B115200 | CS8 | /*no parity*/0;
-
-        co->cflag = cflag;
-
-        return 0;
-}
-
-static struct console bios_console = {
-        .name           = "bios",
-        .write          = sh_console_write,
-        .setup          = sh_console_setup,
-        .flags          = CON_PRINTBUFFER,
-        .index          = -1,
-};
-
-static struct console *early_console;
-
-static int __init setup_early_printk(char *buf)
-{
-        int keep_early = 0;
-
-        if (!buf)
-                return 0;
-
-        if (strstr(buf, "keep"))
-                keep_early = 1;
-
-        if (!strncmp(buf, "bios", 4))
-                early_console = &bios_console;
-
-        if (likely(early_console)) {
-                if (keep_early)
-                        early_console->flags &= ~CON_BOOT;
-                else
-                        early_console->flags |= CON_BOOT;
-                register_console(early_console);
-        }
-
-        return 0;
-}
-early_param("earlyprintk", setup_early_printk);
diff --git a/arch/sh/kernel/ftrace.c b/arch/sh/kernel/ftrace.c
index a48cdedc73b5..30e13196d35b 100644
--- a/arch/sh/kernel/ftrace.c
+++ b/arch/sh/kernel/ftrace.c
@@ -399,12 +399,3 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
         }
 }
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
-
-#ifdef CONFIG_FTRACE_SYSCALLS
-extern unsigned long *sys_call_table;
-
-unsigned long __init arch_syscall_addr(int nr)
-{
-        return (unsigned long)sys_call_table[nr];
-}
-#endif /* CONFIG_FTRACE_SYSCALLS */
diff --git a/arch/sh/kernel/head_32.S b/arch/sh/kernel/head_32.S
index 1151ecdffa71..fe0b743881b0 100644
--- a/arch/sh/kernel/head_32.S
+++ b/arch/sh/kernel/head_32.S
@@ -3,6 +3,7 @@
  *  arch/sh/kernel/head.S
  *
  *  Copyright (C) 1999, 2000  Niibe Yutaka & Kaz Kojima
+ *  Copyright (C) 2010  Matt Fleming
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -13,6 +14,8 @@
 #include <linux/init.h>
 #include <linux/linkage.h>
 #include <asm/thread_info.h>
+#include <asm/mmu.h>
+#include <cpu/mmu_context.h>
 
 #ifdef CONFIG_CPU_SH4A
 #define SYNCO()         synco
@@ -33,7 +36,7 @@ ENTRY(empty_zero_page)
         .long   1               /* LOADER_TYPE */
         .long   0x00000000      /* INITRD_START */
         .long   0x00000000      /* INITRD_SIZE */
-#if defined(CONFIG_32BIT) && defined(CONFIG_PMB_FIXED)
+#ifdef CONFIG_32BIT
         .long   0x53453f00 + 32 /* "SE?" = 32 bit */
 #else
         .long   0x53453f00 + 29 /* "SE?" = 29 bit */
@@ -82,6 +85,209 @@ ENTRY(_stext)
         ldc     r0, r7_bank     ! ... and initial thread_info
 #endif
 
+#ifdef CONFIG_PMB
+/*
+ * Reconfigure the initial PMB mappings setup by the hardware.
+ *
+ * When we boot in 32-bit MMU mode there are 2 PMB entries already
+ * setup for us.
+ *
+ * Entry       VPN         PPN      V   SZ      C       UB      WT
+ * ---------------------------------------------------------------
+ *   0      0x80000000 0x00000000   1  512MB    1       0       1
+ *   1      0xA0000000 0x00000000   1  512MB    0       0       0
+ *
+ * But we reprogram them here because we want complete control over
+ * our address space and the initial mappings may not map PAGE_OFFSET
+ * to __MEMORY_START (or even map all of our RAM).
+ *
+ * Once we've setup cached and uncached mappings we clear the rest of the
+ * PMB entries. This clearing also deals with the fact that PMB entries
+ * can persist across reboots. The PMB could have been left in any state
+ * when the reboot occurred, so to be safe we clear all entries and start
+ * with with a clean slate.
+ *
+ * The uncached mapping is constructed using the smallest possible
+ * mapping with a single unbufferable page. Only the kernel text needs to
+ * be covered via the uncached mapping so that certain functions can be
+ * run uncached.
+ *
+ * Drivers and the like that have previously abused the 1:1 identity
+ * mapping are unsupported in 32-bit mode and must specify their caching
+ * preference when page tables are constructed.
+ *
+ * This frees up the P2 space for more nefarious purposes.
+ *
+ * Register utilization is as follows:
+ *
+ *      r0 = PMB_DATA data field
+ *      r1 = PMB_DATA address field
+ *      r2 = PMB_ADDR data field
+ *      r3 = PMB_ADDR address field
+ *      r4 = PMB_E_SHIFT
+ *      r5 = remaining amount of RAM to map
+ *      r6 = PMB mapping size we're trying to use
+ *      r7 = cached_to_uncached
+ *      r8 = scratch register
+ *      r9 = scratch register
+ *      r10 = number of PMB entries we've setup
+ */
+
+        mov.l   .LMMUCR, r1     /* Flush the TLB */
+        mov.l   @r1, r0
+        or      #MMUCR_TI, r0
+        mov.l   r0, @r1
+
+        mov.l   .LMEMORY_SIZE, r5
+
+        mov     #PMB_E_SHIFT, r0
+        mov     #0x1, r4
+        shld    r0, r4
+
+        mov.l   .LFIRST_DATA_ENTRY, r0
+        mov.l   .LPMB_DATA, r1
+        mov.l   .LFIRST_ADDR_ENTRY, r2
+        mov.l   .LPMB_ADDR, r3
+
+        /*
+         * First we need to walk the PMB and figure out if there are any
+         * existing mappings that match the initial mappings VPN/PPN.
+         * If these have already been established by the bootloader, we
+         * don't bother setting up new entries here, and let the late PMB
+         * initialization take care of things instead.
+         *
+         * Note that we may need to coalesce and merge entries in order
+         * to reclaim more available PMB slots, which is much more than
+         * we want to do at this early stage.
+         */
+        mov     #0, r10
+        mov     #NR_PMB_ENTRIES, r9
+
+        mov     r1, r7          /* temporary PMB_DATA iter */
+
+.Lvalidate_existing_mappings:
+
+        mov.l   @r7, r8
+        and     r0, r8
+        cmp/eq  r0, r8          /* Check for valid __MEMORY_START mappings */
+        bt      .Lpmb_done
+
+        add     #1, r10         /* Increment the loop counter */
+        cmp/eq  r9, r10
+        bf/s    .Lvalidate_existing_mappings
+         add    r4, r7          /* Increment to the next PMB_DATA entry */
+
+        /*
+         * If we've fallen through, continue with setting up the initial
+         * mappings.
+         */
+
+        mov     r5, r7          /* cached_to_uncached */
+        mov     #0, r10
+
+#ifdef CONFIG_UNCACHED_MAPPING
+        /*
+         * Uncached mapping
+         */
+        mov     #(PMB_SZ_16M >> 2), r9
+        shll2   r9
+
+        mov     #(PMB_UB >> 8), r8
+        shll8   r8
+
+        or      r0, r8
+        or      r9, r8
+        mov.l   r8, @r1
+        mov     r2, r8
+        add     r7, r8
+        mov.l   r8, @r3
+
+        add     r4, r1
+        add     r4, r3
+        add     #1, r10
+#endif
+
+/*
+ * Iterate over all of the available sizes from largest to
+ * smallest for constructing the cached mapping.
+ */
+#define __PMB_ITER_BY_SIZE(size)                        \
+.L##size:                                               \
+        mov     #(size >> 4), r6;                       \
+        shll16  r6;                                     \
+        shll8   r6;                                     \
+                                                        \
+        cmp/hi  r5, r6;                                 \
+        bt      9999f;                                  \
+                                                        \
+        mov     #(PMB_SZ_##size##M >> 2), r9;           \
+        shll2   r9;                                     \
+                                                        \
+        /*                                              \
+         * Cached mapping                               \
+         */                                             \
+        mov     #PMB_C, r8;                             \
+        or      r0, r8;                                 \
+        or      r9, r8;                                 \
+        mov.l   r8, @r1;                                \
+        mov.l   r2, @r3;                                \
+                                                        \
+        /* Increment to the next PMB_DATA entry */      \
+        add     r4, r1;                                 \
+        /* Increment to the next PMB_ADDR entry */      \
+        add     r4, r3;                                 \
+        /* Increment number of PMB entries */           \
+        add     #1, r10;                                \
+                                                        \
+        sub     r6, r5;                                 \
+        add     r6, r0;                                 \
+        add     r6, r2;                                 \
+                                                        \
+        bra     .L##size;                               \
+9999:
+
+        __PMB_ITER_BY_SIZE(512)
+        __PMB_ITER_BY_SIZE(128)
+        __PMB_ITER_BY_SIZE(64)
+        __PMB_ITER_BY_SIZE(16)
+
+#ifdef CONFIG_UNCACHED_MAPPING
+        /*
+         * Now that we can access it, update cached_to_uncached and
+         * uncached_size.
+         */
+        mov.l   .Lcached_to_uncached, r0
+        mov.l   r7, @r0
+
+        mov.l   .Luncached_size, r0
+        mov     #1, r7
+        shll16  r7
+        shll8   r7
+        mov.l   r7, @r0
+#endif
+
+        /*
+         * Clear the remaining PMB entries.
+         *
+         * r3 = entry to begin clearing from
+         * r10 = number of entries we've setup so far
+         */
+        mov     #0, r1
+        mov     #NR_PMB_ENTRIES, r0
+
+.Lagain:
+        mov.l   r1, @r3         /* Clear PMB_ADDR entry */
+        add     #1, r10         /* Increment the loop counter */
+        cmp/eq  r0, r10
+        bf/s    .Lagain
+         add    r4, r3          /* Increment to the next PMB_ADDR entry */
+
+        mov.l   6f, r0
+        icbi    @r0
+
+.Lpmb_done:
+#endif /* CONFIG_PMB */
+
 #ifndef CONFIG_SH_NO_BSS_INIT
         /*
          * Don't clear BSS if running on slow platforms such as an RTL simulation,
@@ -131,3 +337,16 @@ ENTRY(stack_start)
 5:      .long   start_kernel
 6:      .long   sh_cpu_init
 7:      .long   init_thread_union
+
+#ifdef CONFIG_PMB
+.LPMB_ADDR:             .long   PMB_ADDR
+.LPMB_DATA:             .long   PMB_DATA
+.LFIRST_ADDR_ENTRY:     .long   PAGE_OFFSET | PMB_V
+.LFIRST_DATA_ENTRY:     .long   __MEMORY_START | PMB_V
+.LMMUCR:                .long   MMUCR
+.LMEMORY_SIZE:          .long   __MEMORY_SIZE
+#ifdef CONFIG_UNCACHED_MAPPING
+.Lcached_to_uncached:   .long   cached_to_uncached
+.Luncached_size:        .long   uncached_size
+#endif
+#endif
diff --git a/arch/sh/kernel/head_64.S b/arch/sh/kernel/head_64.S
index 3ea765844c74..defd851abefa 100644
--- a/arch/sh/kernel/head_64.S
+++ b/arch/sh/kernel/head_64.S
@@ -220,7 +220,6 @@ clear_DTLB:
         add.l   r22, r63, r22           /* Sign extend */
         putcfg  r21, 0, r22             /* Set MMUDR[0].PTEH */
 
-#ifdef CONFIG_EARLY_PRINTK
         /*
          * Setup a DTLB translation for SCIF phys.
          */
@@ -231,7 +230,6 @@ clear_DTLB:
         movi    0xfa03, r22     /* 0xfa030000, fixed SCIF virt */
         shori   0x0003, r22
         putcfg  r21, 0, r22     /* PTEH last */
-#endif
 
         /*
          * Set cache behaviours.
diff --git a/arch/sh/kernel/hw_breakpoint.c b/arch/sh/kernel/hw_breakpoint.c
new file mode 100644
index 000000000000..e2f1753d275c
--- /dev/null
+++ b/arch/sh/kernel/hw_breakpoint.c
@@ -0,0 +1,463 @@
+/*
+ * arch/sh/kernel/hw_breakpoint.c
+ *
+ * Unified kernel/user-space hardware breakpoint facility for the on-chip UBC.
+ *
+ * Copyright (C) 2009 - 2010  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/perf_event.h>
+#include <linux/hw_breakpoint.h>
+#include <linux/percpu.h>
+#include <linux/kallsyms.h>
+#include <linux/notifier.h>
+#include <linux/kprobes.h>
+#include <linux/kdebug.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <asm/hw_breakpoint.h>
+#include <asm/mmu_context.h>
+#include <asm/ptrace.h>
+
+/*
+ * Stores the breakpoints currently in use on each breakpoint address
+ * register for each cpus
+ */
+static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM]);
+
+/*
+ * A dummy placeholder for early accesses until the CPUs get a chance to
+ * register their UBCs later in the boot process.
+ */
+static struct sh_ubc ubc_dummy = { .num_events = 0 };
+
+static struct sh_ubc *sh_ubc __read_mostly = &ubc_dummy;
+
+/*
+ * Install a perf counter breakpoint.
+ *
+ * We seek a free UBC channel and use it for this breakpoint.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        int i;
+
+        for (i = 0; i < sh_ubc->num_events; i++) {
+                struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
+
+                if (!*slot) {
+                        *slot = bp;
+                        break;
+                }
+        }
+
+        if (WARN_ONCE(i == sh_ubc->num_events, "Can't find any breakpoint slot"))
+                return -EBUSY;
+
+        clk_enable(sh_ubc->clk);
+        sh_ubc->enable(info, i);
+
+        return 0;
+}
+
+/*
+ * Uninstall the breakpoint contained in the given counter.
+ *
+ * First we search the debug address register it uses and then we disable
+ * it.
+ *
+ * Atomic: we hold the counter->ctx->lock and we only handle variables
+ * and registers local to this cpu.
+ */
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        int i;
+
+        for (i = 0; i < sh_ubc->num_events; i++) {
+                struct perf_event **slot = &__get_cpu_var(bp_per_reg[i]);
+
+                if (*slot == bp) {
+                        *slot = NULL;
+                        break;
+                }
+        }
+
+        if (WARN_ONCE(i == sh_ubc->num_events, "Can't find any breakpoint slot"))
+                return;
+
+        sh_ubc->disable(info, i);
+        clk_disable(sh_ubc->clk);
+}
+
+static int get_hbp_len(u16 hbp_len)
+{
+        unsigned int len_in_bytes = 0;
+
+        switch (hbp_len) {
+        case SH_BREAKPOINT_LEN_1:
+                len_in_bytes = 1;
+                break;
+        case SH_BREAKPOINT_LEN_2:
+                len_in_bytes = 2;
+                break;
+        case SH_BREAKPOINT_LEN_4:
+                len_in_bytes = 4;
+                break;
+        case SH_BREAKPOINT_LEN_8:
+                len_in_bytes = 8;
+                break;
+        }
+        return len_in_bytes;
+}
+
+/*
+ * Check for virtual address in user space.
+ */
+int arch_check_va_in_userspace(unsigned long va, u16 hbp_len)
+{
+        unsigned int len;
+
+        len = get_hbp_len(hbp_len);
+
+        return (va <= TASK_SIZE - len);
+}
+
+/*
+ * Check for virtual address in kernel space.
+ */
+static int arch_check_va_in_kernelspace(unsigned long va, u8 hbp_len)
+{
+        unsigned int len;
+
+        len = get_hbp_len(hbp_len);
+
+        return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
+}
+
+/*
+ * Store a breakpoint's encoded address, length, and type.
+ */
+static int arch_store_info(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        /*
+         * User-space requests will always have the address field populated
+         * For kernel-addresses, either the address or symbol name can be
+         * specified.
+         */
+        if (info->name)
+                info->address = (unsigned long)kallsyms_lookup_name(info->name);
+        if (info->address)
+                return 0;
+
+        return -EINVAL;
+}
+
+int arch_bp_generic_fields(int sh_len, int sh_type,
+                           int *gen_len, int *gen_type)
+{
+        /* Len */
+        switch (sh_len) {
+        case SH_BREAKPOINT_LEN_1:
+                *gen_len = HW_BREAKPOINT_LEN_1;
+                break;
+        case SH_BREAKPOINT_LEN_2:
+                *gen_len = HW_BREAKPOINT_LEN_2;
+                break;
+        case SH_BREAKPOINT_LEN_4:
+                *gen_len = HW_BREAKPOINT_LEN_4;
+                break;
+        case SH_BREAKPOINT_LEN_8:
+                *gen_len = HW_BREAKPOINT_LEN_8;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Type */
+        switch (sh_type) {
+        case SH_BREAKPOINT_READ:
+                *gen_type = HW_BREAKPOINT_R;
+        case SH_BREAKPOINT_WRITE:
+                *gen_type = HW_BREAKPOINT_W;
+                break;
+        case SH_BREAKPOINT_RW:
+                *gen_type = HW_BREAKPOINT_W | HW_BREAKPOINT_R;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int arch_build_bp_info(struct perf_event *bp)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+        info->address = bp->attr.bp_addr;
+
+        /* Len */
+        switch (bp->attr.bp_len) {
+        case HW_BREAKPOINT_LEN_1:
+                info->len = SH_BREAKPOINT_LEN_1;
+                break;
+        case HW_BREAKPOINT_LEN_2:
+                info->len = SH_BREAKPOINT_LEN_2;
+                break;
+        case HW_BREAKPOINT_LEN_4:
+                info->len = SH_BREAKPOINT_LEN_4;
+                break;
+        case HW_BREAKPOINT_LEN_8:
+                info->len = SH_BREAKPOINT_LEN_8;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        /* Type */
+        switch (bp->attr.bp_type) {
+        case HW_BREAKPOINT_R:
+                info->type = SH_BREAKPOINT_READ;
+                break;
+        case HW_BREAKPOINT_W:
+                info->type = SH_BREAKPOINT_WRITE;
+                break;
+        case HW_BREAKPOINT_W | HW_BREAKPOINT_R:
+                info->type = SH_BREAKPOINT_RW;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp,
+                                  struct task_struct *tsk)
+{
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+        unsigned int align;
+        int ret;
+
+        ret = arch_build_bp_info(bp);
+        if (ret)
+                return ret;
+
+        ret = -EINVAL;
+
+        switch (info->len) {
+        case SH_BREAKPOINT_LEN_1:
+                align = 0;
+                break;
+        case SH_BREAKPOINT_LEN_2:
+                align = 1;
+                break;
+        case SH_BREAKPOINT_LEN_4:
+                align = 3;
+                break;
+        case SH_BREAKPOINT_LEN_8:
+                align = 7;
+                break;
+        default:
+                return ret;
+        }
+
+        ret = arch_store_info(bp);
+
+        if (ret < 0)
+                return ret;
+
+        /*
+         * Check that the low-order bits of the address are appropriate
+         * for the alignment implied by len.
+         */
+        if (info->address & align)
+                return -EINVAL;
+
+        /* Check that the virtual address is in the proper range */
+        if (tsk) {
+                if (!arch_check_va_in_userspace(info->address, info->len))
+                        return -EFAULT;
+        } else {
+                if (!arch_check_va_in_kernelspace(info->address, info->len))
+                        return -EFAULT;
+        }
+
+        return 0;
+}
+
+/*
+ * Release the user breakpoints used by ptrace
+ */
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+        int i;
+        struct thread_struct *t = &tsk->thread;
+
+        for (i = 0; i < sh_ubc->num_events; i++) {
+                unregister_hw_breakpoint(t->ptrace_bps[i]);
+                t->ptrace_bps[i] = NULL;
+        }
+}
+
+static int __kprobes hw_breakpoint_handler(struct die_args *args)
+{
+        int cpu, i, rc = NOTIFY_STOP;
+        struct perf_event *bp;
+        unsigned int cmf, resume_mask;
+
+        /*
+         * Do an early return if none of the channels triggered.
+         */
+        cmf = sh_ubc->triggered_mask();
+        if (unlikely(!cmf))
+                return NOTIFY_DONE;
+
+        /*
+         * By default, resume all of the active channels.
+         */
+        resume_mask = sh_ubc->active_mask();
+
+        /*
+         * Disable breakpoints during exception handling.
+         */
+        sh_ubc->disable_all();
+
+        cpu = get_cpu();
+        for (i = 0; i < sh_ubc->num_events; i++) {
+                unsigned long event_mask = (1 << i);
+
+                if (likely(!(cmf & event_mask)))
+                        continue;
+
+                /*
+                 * The counter may be concurrently released but that can only
+                 * occur from a call_rcu() path. We can then safely fetch
+                 * the breakpoint, use its callback, touch its counter
+                 * while we are in an rcu_read_lock() path.
+                 */
+                rcu_read_lock();
+
+                bp = per_cpu(bp_per_reg[i], cpu);
+                if (bp)
+                        rc = NOTIFY_DONE;
+
+                /*
+                 * Reset the condition match flag to denote completion of
+                 * exception handling.
+                 */
+                sh_ubc->clear_triggered_mask(event_mask);
+
+                /*
+                 * bp can be NULL due to concurrent perf counter
+                 * removing.
+                 */
+                if (!bp) {
+                        rcu_read_unlock();
+                        break;
+                }
+
+                /*
+                 * Don't restore the channel if the breakpoint is from
+                 * ptrace, as it always operates in one-shot mode.
+                 */
+                if (bp->overflow_handler == ptrace_triggered)
+                        resume_mask &= ~(1 << i);
+
+                perf_bp_event(bp, args->regs);
+
+                /* Deliver the signal to userspace */
+                if (arch_check_va_in_userspace(bp->attr.bp_addr,
+                                               bp->attr.bp_len)) {
+                        siginfo_t info;
+
+                        info.si_signo = args->signr;
+                        info.si_errno = notifier_to_errno(rc);
+                        info.si_code = TRAP_HWBKPT;
+
+                        force_sig_info(args->signr, &info, current);
+                }
+
+                rcu_read_unlock();
+        }
+
+        if (cmf == 0)
+                rc = NOTIFY_DONE;
+
+        sh_ubc->enable_all(resume_mask);
+
+        put_cpu();
+
+        return rc;
+}
+
+BUILD_TRAP_HANDLER(breakpoint)
+{
+        unsigned long ex = lookup_exception_vector();
+        TRAP_HANDLER_DECL;
+
+        notify_die(DIE_BREAKPOINT, "breakpoint", regs, 0, ex, SIGTRAP);
+}
+
+/*
+ * Handle debug exception notifications.
+ */
+int __kprobes hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+                                    unsigned long val, void *data)
+{
+        struct die_args *args = data;
+
+        if (val != DIE_BREAKPOINT)
+                return NOTIFY_DONE;
+
+        /*
+         * If the breakpoint hasn't been triggered by the UBC, it's
+         * probably from a debugger, so don't do anything more here.
+         *
+         * This also permits the UBC interface clock to remain off for
+         * non-UBC breakpoints, as we don't need to check the triggered
+         * or active channel masks.
+         */
+        if (args->trapnr != sh_ubc->trap_nr)
+                return NOTIFY_DONE;
+
+        return hw_breakpoint_handler(data);
+}
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+        /* TODO */
+}
+
+void hw_breakpoint_pmu_unthrottle(struct perf_event *bp)
+{
+        /* TODO */
+}
+
+int register_sh_ubc(struct sh_ubc *ubc)
+{
+        /* Bail if it's already assigned */
+        if (sh_ubc != &ubc_dummy)
+                return -EBUSY;
+        sh_ubc = ubc;
+
+        pr_info("HW Breakpoints: %s UBC support registered\n", ubc->name);
+
+        WARN_ON(ubc->num_events > HBP_NUM);
+
+        return 0;
+}
diff --git a/arch/sh/kernel/idle.c b/arch/sh/kernel/idle.c
index 6b3d706deac1..0fd7b41f0a22 100644
--- a/arch/sh/kernel/idle.c
+++ b/arch/sh/kernel/idle.c
@@ -20,10 +20,9 @@
 #include <asm/system.h>
 #include <asm/atomic.h>
 
-static int hlt_counter;
 void (*pm_idle)(void) = NULL;
-void (*pm_power_off)(void);
-EXPORT_SYMBOL(pm_power_off);
+
+static int hlt_counter;
 
 static int __init nohlt_setup(char *__unused)
 {
@@ -131,6 +130,15 @@ static void do_nothing(void *unused)
 {
 }
 
+void stop_this_cpu(void *unused)
+{
+        local_irq_disable();
+        cpu_clear(smp_processor_id(), cpu_online_map);
+
+        for (;;)
+                cpu_sleep();
+}
+
 /*
  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
  * pm_idle and update to new pm_idle value. Required while changing pm_idle
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 69be603aa2d7..4a8bb4eeb8ad 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -184,31 +184,31 @@ static unsigned long long copy_word(unsigned long src_addr, int src_len,
 
         switch (src_len) {
         case 1:
-                tmp = ctrl_inb(src_addr);
+                tmp = __raw_readb(src_addr);
                 break;
         case 2:
-                tmp = ctrl_inw(src_addr);
+                tmp = __raw_readw(src_addr);
                 break;
         case 4:
-                tmp = ctrl_inl(src_addr);
+                tmp = __raw_readl(src_addr);
                 break;
         case 8:
-                tmp = ctrl_inq(src_addr);
+                tmp = __raw_readq(src_addr);
                 break;
         }
 
         switch (dst_len) {
         case 1:
-                ctrl_outb(tmp, dst_addr);
+                __raw_writeb(tmp, dst_addr);
                 break;
         case 2:
-                ctrl_outw(tmp, dst_addr);
+                __raw_writew(tmp, dst_addr);
                 break;
         case 4:
-                ctrl_outl(tmp, dst_addr);
+                __raw_writel(tmp, dst_addr);
                 break;
         case 8:
-                ctrl_outq(tmp, dst_addr);
+                __raw_writeq(tmp, dst_addr);
                 break;
         }
 
@@ -271,6 +271,8 @@ int handle_trapped_io(struct pt_regs *regs, unsigned long address)
         insn_size_t instruction;
         int tmp;
 
+        if (trapped_io_disable)
+                return 0;
         if (!lookup_tiop(address))
                 return 0;
 
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index 3e532d0d4a5c..70c69659b846 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -1,7 +1,7 @@
 /*
  * SuperH KGDB support
  *
- * Copyright (C) 2008  Paul Mundt
+ * Copyright (C) 2008 - 2009  Paul Mundt
  *
  * Single stepping taken from the old stub by Henry Bell and Jeremy Siegel.
  *
@@ -251,24 +251,60 @@ BUILD_TRAP_HANDLER(singlestep)
         local_irq_restore(flags);
 }
 
+static int __kgdb_notify(struct die_args *args, unsigned long cmd)
+{
+        int ret;
+
+        switch (cmd) {
+        case DIE_BREAKPOINT:
+                /*
+                 * This means a user thread is single stepping
+                 * a system call which should be ignored
+                 */
+                if (test_thread_flag(TIF_SINGLESTEP))
+                        return NOTIFY_DONE;
+
+                ret = kgdb_handle_exception(args->trapnr & 0xff, args->signr,
+                                            args->err, args->regs);
+                if (ret)
+                        return NOTIFY_DONE;
+
+                break;
+        }
 
-BUILD_TRAP_HANDLER(breakpoint)
+        return NOTIFY_STOP;
+}
+
+static int
+kgdb_notify(struct notifier_block *self, unsigned long cmd, void *ptr)
 {
         unsigned long flags;
-        TRAP_HANDLER_DECL;
+        int ret;
 
         local_irq_save(flags);
-        kgdb_handle_exception(vec >> 2, SIGTRAP, 0, regs);
+        ret = __kgdb_notify(ptr, cmd);
         local_irq_restore(flags);
+
+        return ret;
 }
 
+static struct notifier_block kgdb_notifier = {
+        .notifier_call  = kgdb_notify,
+
+        /*
+         * Lowest-prio notifier priority, we want to be notified last:
+         */
+        .priority       = -INT_MAX,
+};
+
 int kgdb_arch_init(void)
 {
-        return 0;
+        return register_die_notifier(&kgdb_notifier);
 }
 
 void kgdb_arch_exit(void)
 {
+        unregister_die_notifier(&kgdb_notifier);
 }
 
 struct kgdb_arch arch_kgdb_ops = {
diff --git a/arch/sh/kernel/machine_kexec.c b/arch/sh/kernel/machine_kexec.c
index 76f280223ebd..7672141c841b 100644
--- a/arch/sh/kernel/machine_kexec.c
+++ b/arch/sh/kernel/machine_kexec.c
@@ -21,6 +21,8 @@
 #include <asm/mmu_context.h>
 #include <asm/io.h>
 #include <asm/cacheflush.h>
+#include <asm/sh_bios.h>
+#include <asm/reboot.h>
 
 typedef void (*relocate_new_kernel_t)(unsigned long indirection_page,
                                       unsigned long reboot_code_buffer,
@@ -28,15 +30,11 @@ typedef void (*relocate_new_kernel_t)(unsigned long indirection_page,
 
 extern const unsigned char relocate_new_kernel[];
 extern const unsigned int relocate_new_kernel_size;
-extern void *gdb_vbr_vector;
 extern void *vbr_base;
 
-void machine_shutdown(void)
-{
-}
-
-void machine_crash_shutdown(struct pt_regs *regs)
+void native_machine_crash_shutdown(struct pt_regs *regs)
 {
+        /* Nothing to do for UP, but definitely broken for SMP.. */
 }
 
 /*
@@ -117,11 +115,7 @@ void machine_kexec(struct kimage *image)
         kexec_info(image);
         flush_cache_all();
 
-#if defined(CONFIG_SH_STANDARD_BIOS)
-        asm volatile("ldc %0, vbr" :
-                     : "r" (((unsigned long) gdb_vbr_vector) - 0x100)
-                     : "memory");
-#endif
+        sh_bios_vbr_reload();
 
         /* now call it */
         rnk = (relocate_new_kernel_t) reboot_code_buffer;
diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c
index 24ea837eac5b..a9dd3abde28e 100644
--- a/arch/sh/kernel/perf_callchain.c
+++ b/arch/sh/kernel/perf_callchain.c
@@ -68,9 +68,6 @@ perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
 
         is_user = user_mode(regs);
 
-        if (!current || current->pid == 0)
-                return;
-
         if (is_user && current->state != TASK_RUNNING)
                 return;
 
diff --git a/arch/sh/kernel/process.c b/arch/sh/kernel/process.c
new file mode 100644
index 000000000000..81add9b9ea6e
--- /dev/null
+++ b/arch/sh/kernel/process.c
@@ -0,0 +1,100 @@
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+
+struct kmem_cache *task_xstate_cachep = NULL;
+unsigned int xstate_size;
+
+int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
+{
+        *dst = *src;
+
+        if (src->thread.xstate) {
+                dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
+                                                      GFP_KERNEL);
+                if (!dst->thread.xstate)
+                        return -ENOMEM;
+                memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
+        }
+
+        return 0;
+}
+
+void free_thread_xstate(struct task_struct *tsk)
+{
+        if (tsk->thread.xstate) {
+                kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
+                tsk->thread.xstate = NULL;
+        }
+}
+
+#if THREAD_SHIFT < PAGE_SHIFT
+static struct kmem_cache *thread_info_cache;
+
+struct thread_info *alloc_thread_info(struct task_struct *tsk)
+{
+        struct thread_info *ti;
+
+        ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL);
+        if (unlikely(ti == NULL))
+                return NULL;
+#ifdef CONFIG_DEBUG_STACK_USAGE
+        memset(ti, 0, THREAD_SIZE);
+#endif
+        return ti;
+}
+
+void free_thread_info(struct thread_info *ti)
+{
+        free_thread_xstate(ti->task);
+        kmem_cache_free(thread_info_cache, ti);
+}
+
+void thread_info_cache_init(void)
+{
+        thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
+                                              THREAD_SIZE, SLAB_PANIC, NULL);
+}
+#else
+struct thread_info *alloc_thread_info(struct task_struct *tsk)
+{
+#ifdef CONFIG_DEBUG_STACK_USAGE
+        gfp_t mask = GFP_KERNEL | __GFP_ZERO;
+#else
+        gfp_t mask = GFP_KERNEL;
+#endif
+        return (struct thread_info *)__get_free_pages(mask, THREAD_SIZE_ORDER);
+}
+
+void free_thread_info(struct thread_info *ti)
+{
+        free_thread_xstate(ti->task);
+        free_pages((unsigned long)ti, THREAD_SIZE_ORDER);
+}
+#endif /* THREAD_SHIFT < PAGE_SHIFT */
+
+void arch_task_cache_init(void)
+{
+        if (!xstate_size)
+                return;
+
+        task_xstate_cachep = kmem_cache_create("task_xstate", xstate_size,
+                                               __alignof__(union thread_xstate),
+                                               SLAB_PANIC | SLAB_NOTRACK, NULL);
+}
+
+#ifdef CONFIG_SH_FPU_EMU
+# define HAVE_SOFTFP    1
+#else
+# define HAVE_SOFTFP    0
+#endif
+
+void init_thread_xstate(void)
+{
+        if (boot_cpu_data.flags & CPU_HAS_FPU)
+                xstate_size = sizeof(struct sh_fpu_hard_struct);
+        else if (HAVE_SOFTFP)
+                xstate_size = sizeof(struct sh_fpu_soft_struct);
+        else
+                xstate_size = 0;
+}
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index d8af889366a4..3cb88f114d7a 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -16,65 +16,15 @@
 #include <linux/module.h>
 #include <linux/mm.h>
 #include <linux/elfcore.h>
-#include <linux/pm.h>
 #include <linux/kallsyms.h>
-#include <linux/kexec.h>
-#include <linux/kdebug.h>
-#include <linux/tick.h>
-#include <linux/reboot.h>
 #include <linux/fs.h>
 #include <linux/ftrace.h>
-#include <linux/preempt.h>
+#include <linux/hw_breakpoint.h>
 #include <asm/uaccess.h>
 #include <asm/mmu_context.h>
-#include <asm/pgalloc.h>
 #include <asm/system.h>
-#include <asm/ubc.h>
 #include <asm/fpu.h>
 #include <asm/syscalls.h>
-#include <asm/watchdog.h>
-
-int ubc_usercnt = 0;
-
-#ifdef CONFIG_32BIT
-static void watchdog_trigger_immediate(void)
-{
-        sh_wdt_write_cnt(0xFF);
-        sh_wdt_write_csr(0xC2);
-}
-
-void machine_restart(char * __unused)
-{
-        local_irq_disable();
-
-        /* Use watchdog timer to trigger reset */
-        watchdog_trigger_immediate();
-
-        while (1)
-                cpu_sleep();
-}
-#else
-void machine_restart(char * __unused)
-{
-        /* SR.BL=1 and invoke address error to let CPU reset (manual reset) */
-        asm volatile("ldc %0, sr\n\t"
-                     "mov.l @%1, %0" : : "r" (0x10000000), "r" (0x80000001));
-}
-#endif
-
-void machine_halt(void)
-{
-        local_irq_disable();
-
-        while (1)
-                cpu_sleep();
-}
-
-void machine_power_off(void)
-{
-        if (pm_power_off)
-                pm_power_off();
-}
 
 void show_regs(struct pt_regs * regs)
 {
@@ -91,7 +41,7 @@ void show_regs(struct pt_regs * regs)
         printk("PC  : %08lx SP  : %08lx SR  : %08lx ",
                regs->pc, regs->regs[15], regs->sr);
 #ifdef CONFIG_MMU
-        printk("TEA : %08x\n", ctrl_inl(MMU_TEA));
+        printk("TEA : %08x\n", __raw_readl(MMU_TEA));
 #else
         printk("\n");
 #endif
@@ -147,21 +97,34 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
 }
 EXPORT_SYMBOL(kernel_thread);
 
+void start_thread(struct pt_regs *regs, unsigned long new_pc,
+                  unsigned long new_sp)
+{
+        set_fs(USER_DS);
+
+        regs->pr = 0;
+        regs->sr = SR_FD;
+        regs->pc = new_pc;
+        regs->regs[15] = new_sp;
+
+        free_thread_xstate(current);
+}
+EXPORT_SYMBOL(start_thread);
+
 /*
  * Free current thread data structures etc..
  */
 void exit_thread(void)
 {
-        if (current->thread.ubc_pc) {
-                current->thread.ubc_pc = 0;
-                ubc_usercnt -= 1;
-        }
 }
 
 void flush_thread(void)
 {
-#if defined(CONFIG_SH_FPU)
         struct task_struct *tsk = current;
+
+        flush_ptrace_hw_breakpoint(tsk);
+
+#if defined(CONFIG_SH_FPU)
         /* Forget lazy FPU state */
         clear_fpu(tsk, task_pt_regs(tsk));
         clear_used_math();
@@ -209,11 +172,10 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
 {
         struct thread_info *ti = task_thread_info(p);
         struct pt_regs *childregs;
+
 #if defined(CONFIG_SH_DSP)
         struct task_struct *tsk = current;
-#endif
 
-#if defined(CONFIG_SH_DSP)
         if (is_dsp_enabled(tsk)) {
                 /* We can use the __save_dsp or just copy the struct:
                  * __save_dsp(p);
@@ -244,53 +206,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
         p->thread.sp = (unsigned long) childregs;
         p->thread.pc = (unsigned long) ret_from_fork;
 
-        p->thread.ubc_pc = 0;
+        memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
 
         return 0;
 }
 
-/* Tracing by user break controller.  */
-static void ubc_set_tracing(int asid, unsigned long pc)
-{
-#if defined(CONFIG_CPU_SH4A)
-        unsigned long val;
-
-        val = (UBC_CBR_ID_INST | UBC_CBR_RW_READ | UBC_CBR_CE);
-        val |= (UBC_CBR_AIE | UBC_CBR_AIV_SET(asid));
-
-        ctrl_outl(val, UBC_CBR0);
-        ctrl_outl(pc,  UBC_CAR0);
-        ctrl_outl(0x0, UBC_CAMR0);
-        ctrl_outl(0x0, UBC_CBCR);
-
-        val = (UBC_CRR_RES | UBC_CRR_PCB | UBC_CRR_BIE);
-        ctrl_outl(val, UBC_CRR0);
-
-        /* Read UBC register that we wrote last, for checking update */
-        val = ctrl_inl(UBC_CRR0);
-
-#else   /* CONFIG_CPU_SH4A */
-        ctrl_outl(pc, UBC_BARA);
-
-#ifdef CONFIG_MMU
-        ctrl_outb(asid, UBC_BASRA);
-#endif
-
-        ctrl_outl(0, UBC_BAMRA);
-
-        if (current_cpu_data.type == CPU_SH7729 ||
-            current_cpu_data.type == CPU_SH7710 ||
-            current_cpu_data.type == CPU_SH7712 ||
-            current_cpu_data.type == CPU_SH7203){
-                ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
-                ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
-        } else {
-                ctrl_outw(BBR_INST | BBR_READ, UBC_BBRA);
-                ctrl_outw(BRCR_PCBA, UBC_BRCR);
-        }
-#endif  /* CONFIG_CPU_SH4A */
-}
-
 /*
  *      switch_to(x,y) should switch tasks from x to y.
  *
@@ -304,7 +224,7 @@ __switch_to(struct task_struct *prev, struct task_struct *next)
 
         /* we're going to use this soon, after a few expensive things */
         if (next->fpu_counter > 5)
-                prefetch(&next_t->fpu.hard);
+                prefetch(next_t->xstate);
 
 #ifdef CONFIG_MMU
         /*
@@ -316,32 +236,13 @@ __switch_to(struct task_struct *prev, struct task_struct *next)
                      : "r" (task_thread_info(next)));
 #endif
 
-        /* If no tasks are using the UBC, we're done */
-        if (ubc_usercnt == 0)
-                /* If no tasks are using the UBC, we're done */;
-        else if (next->thread.ubc_pc && next->mm) {
-                int asid = 0;
-#ifdef CONFIG_MMU
-                asid |= cpu_asid(smp_processor_id(), next->mm);
-#endif
-                ubc_set_tracing(asid, next->thread.ubc_pc);
-        } else {
-#if defined(CONFIG_CPU_SH4A)
-                ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
-                ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
-#else
-                ctrl_outw(0, UBC_BBRA);
-                ctrl_outw(0, UBC_BBRB);
-#endif
-        }
-
         /*
          * If the task has used fpu the last 5 timeslices, just do a full
          * restore of the math state immediately to avoid the trap; the
          * chances of needing FPU soon are obviously high now
          */
         if (next->fpu_counter > 5)
-                fpu_state_restore(task_pt_regs(next));
+                __fpu_state_restore();
 
         return prev;
 }
@@ -434,20 +335,3 @@ unsigned long get_wchan(struct task_struct *p)
 
         return pc;
 }
-
-asmlinkage void break_point_trap(void)
-{
-        /* Clear tracing.  */
-#if defined(CONFIG_CPU_SH4A)
-        ctrl_outl(UBC_CBR_INIT, UBC_CBR0);
-        ctrl_outl(UBC_CRR_INIT, UBC_CRR0);
-#else
-        ctrl_outw(0, UBC_BBRA);
-        ctrl_outw(0, UBC_BBRB);
-        ctrl_outl(0, UBC_BRCR);
-#endif
-        current->thread.ubc_pc = 0;
-        ubc_usercnt -= 1;
-
-        force_sig(SIGTRAP, current);
-}
diff --git a/arch/sh/kernel/process_64.c b/arch/sh/kernel/process_64.c
index ec79faf6f021..c90957a459ac 100644
--- a/arch/sh/kernel/process_64.c
+++ b/arch/sh/kernel/process_64.c
@@ -32,30 +32,7 @@
 
 struct task_struct *last_task_used_math = NULL;
 
-void machine_restart(char * __unused)
-{
-        extern void phys_stext(void);
-
-        phys_stext();
-}
-
-void machine_halt(void)
-{
-        for (;;);
-}
-
-void machine_power_off(void)
-{
-        __asm__ __volatile__ (
-                "sleep\n\t"
-                "synci\n\t"
-                "nop;nop;nop;nop\n\t"
-        );
-
-        panic("Unexpected wakeup!\n");
-}
-
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
         unsigned long long ah, al, bh, bl, ch, cl;
 
@@ -410,7 +387,7 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *fpu)
                         regs->sr |= SR_FD;
                 }
 
-                memcpy(fpu, &tsk->thread.fpu.hard, sizeof(*fpu));
+                memcpy(fpu, &tsk->thread.xstate->hardfpu, sizeof(*fpu));
         }
 
         return fpvalid;
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index 9be35f348093..c625cdab76dd 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -2,7 +2,7 @@
  * SuperH process tracing
  *
  * Copyright (C) 1999, 2000  Kaz Kojima & Niibe Yutaka
- * Copyright (C) 2002 - 2008  Paul Mundt
+ * Copyright (C) 2002 - 2009  Paul Mundt
  *
  * Audit support by Yuichi Nakamura <ynakam@hitachisoft.jp>
  *
@@ -26,6 +26,7 @@
 #include <linux/tracehook.h>
 #include <linux/elf.h>
 #include <linux/regset.h>
+#include <linux/hw_breakpoint.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -63,33 +64,64 @@ static inline int put_stack_long(struct task_struct *task, int offset,
         return 0;
 }
 
-void user_enable_single_step(struct task_struct *child)
+void ptrace_triggered(struct perf_event *bp, int nmi,
+                      struct perf_sample_data *data, struct pt_regs *regs)
 {
-        /* Next scheduling will set up UBC */
-        if (child->thread.ubc_pc == 0)
-                ubc_usercnt += 1;
+        struct perf_event_attr attr;
+
+        /*
+         * Disable the breakpoint request here since ptrace has defined a
+         * one-shot behaviour for breakpoint exceptions.
+         */
+        attr = bp->attr;
+        attr.disabled = true;
+        modify_user_hw_breakpoint(bp, &attr);
+}
+
+static int set_single_step(struct task_struct *tsk, unsigned long addr)
+{
+        struct thread_struct *thread = &tsk->thread;
+        struct perf_event *bp;
+        struct perf_event_attr attr;
+
+        bp = thread->ptrace_bps[0];
+        if (!bp) {
+                hw_breakpoint_init(&attr);
+
+                attr.bp_addr = addr;
+                attr.bp_len = HW_BREAKPOINT_LEN_2;
+                attr.bp_type = HW_BREAKPOINT_R;
+
+                bp = register_user_hw_breakpoint(&attr, ptrace_triggered, tsk);
+                if (IS_ERR(bp))
+                        return PTR_ERR(bp);
+
+                thread->ptrace_bps[0] = bp;
+        } else {
+                int err;
+
+                attr = bp->attr;
+                attr.bp_addr = addr;
+                err = modify_user_hw_breakpoint(bp, &attr);
+                if (unlikely(err))
+                        return err;
+        }
+
+        return 0;
+}
 
-        child->thread.ubc_pc = get_stack_long(child,
-                                offsetof(struct pt_regs, pc));
+void user_enable_single_step(struct task_struct *child)
+{
+        unsigned long pc = get_stack_long(child, offsetof(struct pt_regs, pc));
 
         set_tsk_thread_flag(child, TIF_SINGLESTEP);
+
+        set_single_step(child, pc);
 }
 
 void user_disable_single_step(struct task_struct *child)
 {
         clear_tsk_thread_flag(child, TIF_SINGLESTEP);
-
-        /*
-         * Ensure the UBC is not programmed at the next context switch.
-         *
-         * Normally this is not needed but there are sequences such as
-         * singlestep, signal delivery, and continue that leave the
-         * ubc_pc non-zero leading to spurious SIGTRAPs.
-         */
-        if (child->thread.ubc_pc != 0) {
-                ubc_usercnt -= 1;
-                child->thread.ubc_pc = 0;
-        }
 }
 
 /*
@@ -163,10 +195,10 @@ int fpregs_get(struct task_struct *target,
 
         if ((boot_cpu_data.flags & CPU_HAS_FPU))
                 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-                                           &target->thread.fpu.hard, 0, -1);
+                                           &target->thread.xstate->hardfpu, 0, -1);
 
         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-                                   &target->thread.fpu.soft, 0, -1);
+                                   &target->thread.xstate->softfpu, 0, -1);
 }
 
 static int fpregs_set(struct task_struct *target,
@@ -184,10 +216,10 @@ static int fpregs_set(struct task_struct *target,
 
         if ((boot_cpu_data.flags & CPU_HAS_FPU))
                 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                          &target->thread.fpu.hard, 0, -1);
+                                          &target->thread.xstate->hardfpu, 0, -1);
 
         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                  &target->thread.fpu.soft, 0, -1);
+                                  &target->thread.xstate->softfpu, 0, -1);
 }
 
 static int fpregs_active(struct task_struct *target,
@@ -333,7 +365,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                                 else
                                         tmp = 0;
                         } else
-                                tmp = ((long *)&child->thread.fpu)
+                                tmp = ((long *)child->thread.xstate)
                                         [(addr - (long)&dummy->fpu) >> 2];
                 } else if (addr == (long) &dummy->u_fpvalid)
                         tmp = !!tsk_used_math(child);
@@ -362,7 +394,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
                 else if (addr >= (long) &dummy->fpu &&
                          addr < (long) &dummy->u_fpvalid) {
                         set_stopped_child_used_math(child);
-                        ((long *)&child->thread.fpu)
+                        ((long *)child->thread.xstate)
                                 [(addr - (long)&dummy->fpu) >> 2] = data;
                         ret = 0;
                 } else if (addr == (long) &dummy->u_fpvalid) {
diff --git a/arch/sh/kernel/ptrace_64.c b/arch/sh/kernel/ptrace_64.c
index 873ebdc4f98e..5fd644da7f02 100644
--- a/arch/sh/kernel/ptrace_64.c
+++ b/arch/sh/kernel/ptrace_64.c
@@ -88,7 +88,7 @@ get_fpu_long(struct task_struct *task, unsigned long addr)
                 regs->sr |= SR_FD;
         }
 
-        tmp = ((long *)&task->thread.fpu)[addr / sizeof(unsigned long)];
+        tmp = ((long *)task->thread.xstate)[addr / sizeof(unsigned long)];
         return tmp;
 }
 
@@ -114,8 +114,7 @@ put_fpu_long(struct task_struct *task, unsigned long addr, unsigned long data)
         regs = (struct pt_regs*)((unsigned char *)task + THREAD_SIZE) - 1;
 
         if (!tsk_used_math(task)) {
-                fpinit(&task->thread.fpu.hard);
-                set_stopped_child_used_math(task);
+                init_fpu(task);
         } else if (last_task_used_math == task) {
                 enable_fpu();
                 save_fpu(task);
@@ -124,7 +123,7 @@ put_fpu_long(struct task_struct *task, unsigned long addr, unsigned long data)
                 regs->sr |= SR_FD;
         }
 
-        ((long *)&task->thread.fpu)[addr / sizeof(unsigned long)] = data;
+        ((long *)task->thread.xstate)[addr / sizeof(unsigned long)] = data;
         return 0;
 }
 
@@ -133,6 +132,8 @@ void user_enable_single_step(struct task_struct *child)
         struct pt_regs *regs = child->thread.uregs;
 
         regs->sr |= SR_SSTEP;   /* auto-resetting upon exception */
+
+        set_tsk_thread_flag(child, TIF_SINGLESTEP);
 }
 
 void user_disable_single_step(struct task_struct *child)
@@ -140,6 +141,8 @@ void user_disable_single_step(struct task_struct *child)
         struct pt_regs *regs = child->thread.uregs;
 
         regs->sr &= ~SR_SSTEP;
+
+        clear_tsk_thread_flag(child, TIF_SINGLESTEP);
 }
 
 static int genregs_get(struct task_struct *target,
@@ -222,7 +225,7 @@ int fpregs_get(struct task_struct *target,
                 return ret;
 
         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-                                   &target->thread.fpu.hard, 0, -1);
+                                   &target->thread.xstate->hardfpu, 0, -1);
 }
 
 static int fpregs_set(struct task_struct *target,
@@ -239,7 +242,7 @@ static int fpregs_set(struct task_struct *target,
         set_stopped_child_used_math(target);
 
         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-                                  &target->thread.fpu.hard, 0, -1);
+                                  &target->thread.xstate->hardfpu, 0, -1);
 }
 
 static int fpregs_active(struct task_struct *target,
@@ -454,6 +457,8 @@ asmlinkage long long do_syscall_trace_enter(struct pt_regs *regs)
 
 asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
 {
+        int step;
+
         if (unlikely(current->audit_context))
                 audit_syscall_exit(AUDITSC_RESULT(regs->regs[9]),
                                    regs->regs[9]);
@@ -461,8 +466,9 @@ asmlinkage void do_syscall_trace_leave(struct pt_regs *regs)
         if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
                 trace_sys_exit(regs, regs->regs[9]);
 
-        if (test_thread_flag(TIF_SYSCALL_TRACE))
-                tracehook_report_syscall_exit(regs, 0);
+        step = test_thread_flag(TIF_SINGLESTEP);
+        if (step || test_thread_flag(TIF_SYSCALL_TRACE))
+                tracehook_report_syscall_exit(regs, step);
 }
 
 /* Called with interrupts disabled */
@@ -479,9 +485,10 @@ asmlinkage void do_single_step(unsigned long long vec, struct pt_regs *regs)
 }
 
 /* Called with interrupts disabled */
-asmlinkage void do_software_break_point(unsigned long long vec,
-                                        struct pt_regs *regs)
+BUILD_TRAP_HANDLER(breakpoint)
 {
+        TRAP_HANDLER_DECL;
+
         /* We need to forward step the PC, to counteract the backstep done
            in signal.c. */
         local_irq_enable();
diff --git a/arch/sh/kernel/reboot.c b/arch/sh/kernel/reboot.c
new file mode 100644
index 000000000000..b1fca66bb92e
--- /dev/null
+++ b/arch/sh/kernel/reboot.c
@@ -0,0 +1,98 @@
+#include <linux/pm.h>
+#include <linux/kexec.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/module.h>
+#ifdef CONFIG_SUPERH32
+#include <asm/watchdog.h>
+#endif
+#include <asm/addrspace.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+
+void (*pm_power_off)(void);
+EXPORT_SYMBOL(pm_power_off);
+
+#ifdef CONFIG_SUPERH32
+static void watchdog_trigger_immediate(void)
+{
+        sh_wdt_write_cnt(0xFF);
+        sh_wdt_write_csr(0xC2);
+}
+#endif
+
+static void native_machine_restart(char * __unused)
+{
+        local_irq_disable();
+
+        /* Address error with SR.BL=1 first. */
+        trigger_address_error();
+
+#ifdef CONFIG_SUPERH32
+        /* If that fails or is unsupported, go for the watchdog next. */
+        watchdog_trigger_immediate();
+#endif
+
+        /*
+         * Give up and sleep.
+         */
+        while (1)
+                cpu_sleep();
+}
+
+static void native_machine_shutdown(void)
+{
+        smp_send_stop();
+}
+
+static void native_machine_power_off(void)
+{
+        if (pm_power_off)
+                pm_power_off();
+}
+
+static void native_machine_halt(void)
+{
+        /* stop other cpus */
+        machine_shutdown();
+
+        /* stop this cpu */
+        stop_this_cpu(NULL);
+}
+
+struct machine_ops machine_ops = {
+        .power_off      = native_machine_power_off,
+        .shutdown       = native_machine_shutdown,
+        .restart        = native_machine_restart,
+        .halt           = native_machine_halt,
+#ifdef CONFIG_KEXEC
+        .crash_shutdown = native_machine_crash_shutdown,
+#endif
+};
+
+void machine_power_off(void)
+{
+        machine_ops.power_off();
+}
+
+void machine_shutdown(void)
+{
+        machine_ops.shutdown();
+}
+
+void machine_restart(char *cmd)
+{
+        machine_ops.restart(cmd);
+}
+
+void machine_halt(void)
+{
+        machine_ops.halt();
+}
+
+#ifdef CONFIG_KEXEC
+void machine_crash_shutdown(struct pt_regs *regs)
+{
+        machine_ops.crash_shutdown(regs);
+}
+#endif
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 8b0e69792cf4..3459e70eed72 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -421,6 +421,8 @@ void __init setup_arch(char **cmdline_p)
 
         parse_early_param();
 
+        uncached_init();
+
         plat_early_device_setup();
 
         /* Let earlyprintk output early console messages */
@@ -449,17 +451,15 @@ void __init setup_arch(char **cmdline_p)
 #ifdef CONFIG_DUMMY_CONSOLE
         conswitchp = &dummy_con;
 #endif
+        paging_init();
+        pmb_init();
+
+        ioremap_fixed_init();
 
         /* Perform the machine specific initialisation */
         if (likely(sh_mv.mv_setup))
                 sh_mv.mv_setup(cmdline_p);
 
-        paging_init();
-
-#ifdef CONFIG_PMB_ENABLE
-        pmb_init();
-#endif
-
 #ifdef CONFIG_SMP
         plat_smp_setup();
 #endif
diff --git a/arch/sh/kernel/sh_bios.c b/arch/sh/kernel/sh_bios.c
index c852f7805728..47475cca068a 100644
--- a/arch/sh/kernel/sh_bios.c
+++ b/arch/sh/kernel/sh_bios.c
@@ -1,19 +1,30 @@
 /*
- *  linux/arch/sh/kernel/sh_bios.c
  *  C interface for trapping into the standard LinuxSH BIOS.
  *
  *  Copyright (C) 2000 Greg Banks, Mitch Davis
+ *  Copyright (C) 1999, 2000  Niibe Yutaka
+ *  Copyright (C) 2002  M. R. Brown
+ *  Copyright (C) 2004 - 2010  Paul Mundt
  *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  */
 #include <linux/module.h>
+#include <linux/console.h>
+#include <linux/tty.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/delay.h>
 #include <asm/sh_bios.h>
 
 #define BIOS_CALL_CONSOLE_WRITE         0
 #define BIOS_CALL_ETH_NODE_ADDR         10
 #define BIOS_CALL_SHUTDOWN              11
-#define BIOS_CALL_CHAR_OUT              0x1f    /* TODO: hack */
 #define BIOS_CALL_GDB_DETACH            0xff
 
+void *gdb_vbr_vector = NULL;
+
 static inline long sh_bios_call(long func, long arg0, long arg1, long arg2,
                                     long arg3)
 {
@@ -23,6 +34,9 @@ static inline long sh_bios_call(long func, long arg0, long arg1, long arg2,
         register long r6 __asm__("r6") = arg2;
         register long r7 __asm__("r7") = arg3;
 
+        if (!gdb_vbr_vector)
+                return -ENOSYS;
+
         __asm__ __volatile__("trapa     #0x3f":"=z"(r0)
                              :"0"(r0), "r"(r4), "r"(r5), "r"(r6), "r"(r7)
                              :"memory");
@@ -34,11 +48,6 @@ void sh_bios_console_write(const char *buf, unsigned int len)
         sh_bios_call(BIOS_CALL_CONSOLE_WRITE, (long)buf, (long)len, 0, 0);
 }
 
-void sh_bios_char_out(char ch)
-{
-        sh_bios_call(BIOS_CALL_CHAR_OUT, ch, 0, 0, 0);
-}
-
 void sh_bios_gdb_detach(void)
 {
         sh_bios_call(BIOS_CALL_GDB_DETACH, 0, 0, 0, 0);
@@ -55,3 +64,109 @@ void sh_bios_shutdown(unsigned int how)
 {
         sh_bios_call(BIOS_CALL_SHUTDOWN, how, 0, 0, 0);
 }
+
+/*
+ * Read the old value of the VBR register to initialise the vector
+ * through which debug and BIOS traps are delegated by the Linux trap
+ * handler.
+ */
+void sh_bios_vbr_init(void)
+{
+        unsigned long vbr;
+
+        if (unlikely(gdb_vbr_vector))
+                return;
+
+        __asm__ __volatile__ ("stc vbr, %0" : "=r" (vbr));
+
+        if (vbr) {
+                gdb_vbr_vector = (void *)(vbr + 0x100);
+                printk(KERN_NOTICE "Setting GDB trap vector to %p\n",
+                       gdb_vbr_vector);
+        } else
+                printk(KERN_NOTICE "SH-BIOS not detected\n");
+}
+
+/**
+ * sh_bios_vbr_reload - Re-load the system VBR from the BIOS vector.
+ *
+ * This can be used by save/restore code to reinitialize the system VBR
+ * from the fixed BIOS VBR. A no-op if no BIOS VBR is known.
+ */
+void sh_bios_vbr_reload(void)
+{
+        if (gdb_vbr_vector)
+                __asm__ __volatile__ (
+                        "ldc %0, vbr"
+                        :
+                        : "r" (((unsigned long) gdb_vbr_vector) - 0x100)
+                        : "memory"
+                );
+}
+
+/*
+ *      Print a string through the BIOS
+ */
+static void sh_console_write(struct console *co, const char *s,
+                                 unsigned count)
+{
+        sh_bios_console_write(s, count);
+}
+
+/*
+ *      Setup initial baud/bits/parity. We do two things here:
+ *      - construct a cflag setting for the first rs_open()
+ *      - initialize the serial port
+ *      Return non-zero if we didn't find a serial port.
+ */
+static int __init sh_console_setup(struct console *co, char *options)
+{
+        int     cflag = CREAD | HUPCL | CLOCAL;
+
+        /*
+         *      Now construct a cflag setting.
+         *      TODO: this is a totally bogus cflag, as we have
+         *      no idea what serial settings the BIOS is using, or
+         *      even if its using the serial port at all.
+         */
+        cflag |= B115200 | CS8 | /*no parity*/0;
+
+        co->cflag = cflag;
+
+        return 0;
+}
+
+static struct console bios_console = {
+        .name           = "bios",
+        .write          = sh_console_write,
+        .setup          = sh_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+};
+
+static struct console *early_console;
+
+static int __init setup_early_printk(char *buf)
+{
+        int keep_early = 0;
+
+        if (!buf)
+                return 0;
+
+        if (strstr(buf, "keep"))
+                keep_early = 1;
+
+        if (!strncmp(buf, "bios", 4))
+                early_console = &bios_console;
+
+        if (likely(early_console)) {
+                if (keep_early)
+                        early_console->flags &= ~CON_BOOT;
+                else
+                        early_console->flags |= CON_BOOT;
+                register_console(early_console);
+        }
+
+        return 0;
+}
+early_param("earlyprintk", setup_early_printk);
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 12815ce01ecd..579cd2ca358d 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -150,7 +150,7 @@ static inline int restore_sigcontext_fpu(struct sigcontext __user *sc)
                 return 0;
 
         set_used_math();
-        return __copy_from_user(&tsk->thread.fpu.hard, &sc->sc_fpregs[0],
+        return __copy_from_user(&tsk->thread.xstate->hardfpu, &sc->sc_fpregs[0],
                                 sizeof(long)*(16*2+2));
 }
 
@@ -175,7 +175,7 @@ static inline int save_sigcontext_fpu(struct sigcontext __user *sc,
         clear_used_math();
 
         unlazy_fpu(tsk, regs);
-        return __copy_to_user(&sc->sc_fpregs[0], &tsk->thread.fpu.hard,
+        return __copy_to_user(&sc->sc_fpregs[0], &tsk->thread.xstate->hardfpu,
                               sizeof(long)*(16*2+2));
 }
 #endif /* CONFIG_SH_FPU */
@@ -528,7 +528,7 @@ handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs,
                 /* fallthrough */
                 case -ERESTARTNOINTR:
                         regs->regs[0] = save_r0;
-                        regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
+                        regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
                         break;
         }
 }
@@ -626,9 +626,9 @@ no_signal:
                     regs->regs[0] == -ERESTARTSYS ||
                     regs->regs[0] == -ERESTARTNOINTR) {
                         regs->regs[0] = save_r0;
-                        regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
+                        regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
                 } else if (regs->regs[0] == -ERESTART_RESTARTBLOCK) {
-                        regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
+                        regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
                         regs->regs[3] = __NR_restart_syscall;
                 }
         }
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index ce76dbdef294..5a9f1f10ebf4 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -118,7 +118,9 @@ static int do_signal(struct pt_regs *regs, sigset_t *oldset)
                          * clear the TS_RESTORE_SIGMASK flag.
                          */
                         current_thread_info()->status &= ~TS_RESTORE_SIGMASK;
-                        tracehook_signal_handler(signr, &info, &ka, regs, 0);
+
+                        tracehook_signal_handler(signr, &info, &ka, regs,
+                                        test_thread_flag(TIF_SINGLESTEP));
                         return 1;
                 }
         }
@@ -295,7 +297,7 @@ restore_sigcontext_fpu(struct pt_regs *regs, struct sigcontext __user *sc)
                 regs->sr |= SR_FD;
         }
 
-        err |= __copy_from_user(&current->thread.fpu.hard, &sc->sc_fpregs[0],
+        err |= __copy_from_user(&current->thread.xstate->hardfpu, &sc->sc_fpregs[0],
                                 (sizeof(long long) * 32) + (sizeof(int) * 1));
 
         return err;
@@ -320,7 +322,7 @@ setup_sigcontext_fpu(struct pt_regs *regs, struct sigcontext __user *sc)
                 regs->sr |= SR_FD;
         }
 
-        err |= __copy_to_user(&sc->sc_fpregs[0], &current->thread.fpu.hard,
+        err |= __copy_to_user(&sc->sc_fpregs[0], &current->thread.xstate->hardfpu,
                               (sizeof(long long) * 32) + (sizeof(int) * 1));
         clear_used_math();
 
diff --git a/arch/sh/kernel/smp.c b/arch/sh/kernel/smp.c
index 983e0792d5f3..e124cf7008df 100644
--- a/arch/sh/kernel/smp.c
+++ b/arch/sh/kernel/smp.c
@@ -161,15 +161,6 @@ void smp_send_reschedule(int cpu)
         plat_send_ipi(cpu, SMP_MSG_RESCHEDULE);
 }
 
-static void stop_this_cpu(void *unused)
-{
-        cpu_clear(smp_processor_id(), cpu_online_map);
-        local_irq_disable();
-
-        for (;;)
-                cpu_relax();
-}
-
 void smp_send_stop(void)
 {
         smp_call_function(stop_this_cpu, 0, 0);
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 7b036339dc92..0830c2a9f712 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -58,7 +58,7 @@ BUILD_TRAP_HANDLER(debug)
         TRAP_HANDLER_DECL;
 
         /* Rewind */
-        regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
+        regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
 
         if (notify_die(DIE_TRAP, "debug trap", regs, 0, vec & 0xff,
                        SIGTRAP) == NOTIFY_STOP)
@@ -75,7 +75,7 @@ BUILD_TRAP_HANDLER(bug)
         TRAP_HANDLER_DECL;
 
         /* Rewind */
-        regs->pc -= instruction_size(ctrl_inw(regs->pc - 4));
+        regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
 
         if (notify_die(DIE_TRAP, "bug trap", regs, 0, TRAPA_BUG_OPCODE & 0xff,
                        SIGTRAP) == NOTIFY_STOP)
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 86639beac3a2..c3d86fa71ddf 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -24,11 +24,10 @@
 #include <linux/kdebug.h>
 #include <linux/kexec.h>
 #include <linux/limits.h>
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
 #include <linux/sysfs.h>
+#include <linux/uaccess.h>
 #include <asm/system.h>
-#include <asm/uaccess.h>
+#include <asm/alignment.h>
 #include <asm/fpu.h>
 #include <asm/kprobes.h>
 
@@ -47,73 +46,6 @@
 #define TRAP_ILLEGAL_SLOT_INST  13
 #endif
 
-static unsigned long se_user;
-static unsigned long se_sys;
-static unsigned long se_half;
-static unsigned long se_word;
-static unsigned long se_dword;
-static unsigned long se_multi;
-/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
-   valid! */
-static int se_usermode = 3;
-/* 0: no warning 1: print a warning message, disabled by default */
-static int se_kernmode_warn;
-
-#ifdef CONFIG_PROC_FS
-static const char *se_usermode_action[] = {
-        "ignored",
-        "warn",
-        "fixup",
-        "fixup+warn",
-        "signal",
-        "signal+warn"
-};
-
-static int alignment_proc_show(struct seq_file *m, void *v)
-{
-        seq_printf(m, "User:\t\t%lu\n", se_user);
-        seq_printf(m, "System:\t\t%lu\n", se_sys);
-        seq_printf(m, "Half:\t\t%lu\n", se_half);
-        seq_printf(m, "Word:\t\t%lu\n", se_word);
-        seq_printf(m, "DWord:\t\t%lu\n", se_dword);
-        seq_printf(m, "Multi:\t\t%lu\n", se_multi);
-        seq_printf(m, "User faults:\t%i (%s)\n", se_usermode,
-                        se_usermode_action[se_usermode]);
-        seq_printf(m, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
-                        se_kernmode_warn ? "+warn" : "");
-        return 0;
-}
-
-static int alignment_proc_open(struct inode *inode, struct file *file)
-{
-        return single_open(file, alignment_proc_show, NULL);
-}
-
-static ssize_t alignment_proc_write(struct file *file,
-                const char __user *buffer, size_t count, loff_t *pos)
-{
-        int *data = PDE(file->f_path.dentry->d_inode)->data;
-        char mode;
-
-        if (count > 0) {
-                if (get_user(mode, buffer))
-                        return -EFAULT;
-                if (mode >= '0' && mode <= '5')
-                        *data = mode - '0';
-        }
-        return count;
-}
-
-static const struct file_operations alignment_proc_fops = {
-        .owner          = THIS_MODULE,
-        .open           = alignment_proc_open,
-        .read           = seq_read,
-        .llseek         = seq_lseek,
-        .release        = single_release,
-        .write          = alignment_proc_write,
-};
-#endif
-
 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
 {
         unsigned long p;
@@ -265,10 +197,10 @@ static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
         count = 1<<(instruction&3);
 
         switch (count) {
-        case 1: se_half  += 1; break;
-        case 2: se_word  += 1; break;
-        case 4: se_dword += 1; break;
-        case 8: se_multi += 1; break; /* ??? */
+        case 1: inc_unaligned_byte_access(); break;
+        case 2: inc_unaligned_word_access(); break;
+        case 4: inc_unaligned_dword_access(); break;
+        case 8: inc_unaligned_multi_access(); break;
         }
 
         ret = -EFAULT;
@@ -452,18 +384,8 @@ int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
         rm = regs->regs[index];
 
         /* shout about fixups */
-        if (!expected) {
-                if (user_mode(regs) && (se_usermode & 1) && printk_ratelimit())
-                        pr_notice("Fixing up unaligned userspace access "
-                                  "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
-                                  current->comm, task_pid_nr(current),
-                                  (void *)regs->pc, instruction);
-                else if (se_kernmode_warn && printk_ratelimit())
-                        pr_notice("Fixing up unaligned kernel access "
-                                  "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
-                                  current->comm, task_pid_nr(current),
-                                  (void *)regs->pc, instruction);
-        }
+        if (!expected)
+                unaligned_fixups_notify(current, instruction, regs);
 
         ret = -EFAULT;
         switch (instruction&0xF000) {
@@ -616,10 +538,10 @@ asmlinkage void do_address_error(struct pt_regs *regs,
 
         if (user_mode(regs)) {
                 int si_code = BUS_ADRERR;
+                unsigned int user_action;
 
                 local_irq_enable();
-
-                se_user += 1;
+                inc_unaligned_user_access();
 
                 set_fs(USER_DS);
                 if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1),
@@ -630,16 +552,12 @@ asmlinkage void do_address_error(struct pt_regs *regs,
                 set_fs(oldfs);
 
                 /* shout about userspace fixups */
-                if (se_usermode & 1)
-                        printk(KERN_NOTICE "Unaligned userspace access "
-                               "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
-                               current->comm, current->pid, (void *)regs->pc,
-                               instruction);
+                unaligned_fixups_notify(current, instruction, regs);
 
-                if (se_usermode & 2)
+                user_action = unaligned_user_action();
+                if (user_action & UM_FIXUP)
                         goto fixup;
-
-                if (se_usermode & 4)
+                if (user_action & UM_SIGNAL)
                         goto uspace_segv;
                 else {
                         /* ignore */
@@ -659,7 +577,7 @@ fixup:
                                               &user_mem_access, 0);
                 set_fs(oldfs);
 
-                if (tmp==0)
+                if (tmp == 0)
                         return; /* sorted */
 uspace_segv:
                 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
@@ -672,7 +590,7 @@ uspace_segv:
                 info.si_addr = (void __user *)address;
                 force_sig_info(SIGBUS, &info, current);
         } else {
-                se_sys += 1;
+                inc_unaligned_kernel_access();
 
                 if (regs->pc & 1)
                         die("unaligned program counter", regs, error_code);
@@ -687,11 +605,7 @@ uspace_segv:
                         die("insn faulting in do_address_error", regs, 0);
                 }
 
-                if (se_kernmode_warn)
-                        printk(KERN_NOTICE "Unaligned kernel access "
-                               "on behalf of \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
-                               current->comm, current->pid, (void *)regs->pc,
-                               instruction);
+                unaligned_fixups_notify(current, instruction, regs);
 
                 handle_unaligned_access(instruction, regs,
                                         &user_mem_access, 0);
@@ -876,35 +790,10 @@ asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
         die_if_kernel("exception", regs, ex);
 }
 
-#if defined(CONFIG_SH_STANDARD_BIOS)
-void *gdb_vbr_vector;
-
-static inline void __init gdb_vbr_init(void)
-{
-        register unsigned long vbr;
-
-        /*
-         * Read the old value of the VBR register to initialise
-         * the vector through which debug and BIOS traps are
-         * delegated by the Linux trap handler.
-         */
-        asm volatile("stc vbr, %0" : "=r" (vbr));
-
-        gdb_vbr_vector = (void *)(vbr + 0x100);
-        printk("Setting GDB trap vector to 0x%08lx\n",
-               (unsigned long)gdb_vbr_vector);
-}
-#endif
-
 void __cpuinit per_cpu_trap_init(void)
 {
         extern void *vbr_base;
 
-#ifdef CONFIG_SH_STANDARD_BIOS
-        if (raw_smp_processor_id() == 0)
-                gdb_vbr_init();
-#endif
-
         /* NOTE: The VBR value should be at P1
            (or P2, virtural "fixed" address space).
            It's definitely should not in physical address.  */
@@ -956,11 +845,8 @@ void __init trap_init(void)
 #endif
 
 #ifdef TRAP_UBC
-        set_exception_table_vec(TRAP_UBC, break_point_trap);
+        set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler);
 #endif
-
-        /* Setup VBR for boot cpu */
-        per_cpu_trap_init();
 }
 
 void show_stack(struct task_struct *tsk, unsigned long *sp)
@@ -985,34 +871,3 @@ void dump_stack(void)
         show_stack(NULL, NULL);
 }
 EXPORT_SYMBOL(dump_stack);
-
-#ifdef CONFIG_PROC_FS
-/*
- * This needs to be done after sysctl_init, otherwise sys/ will be
- * overwritten.  Actually, this shouldn't be in sys/ at all since
- * it isn't a sysctl, and it doesn't contain sysctl information.
- * We now locate it in /proc/cpu/alignment instead.
- */
-static int __init alignment_init(void)
-{
-        struct proc_dir_entry *dir, *res;
-
-        dir = proc_mkdir("cpu", NULL);
-        if (!dir)
-                return -ENOMEM;
-
-        res = proc_create_data("alignment", S_IWUSR | S_IRUGO, dir,
-                               &alignment_proc_fops, &se_usermode);
-        if (!res)
-                return -ENOMEM;
-
-        res = proc_create_data("kernel_alignment", S_IWUSR | S_IRUGO, dir,
-                               &alignment_proc_fops, &se_kernmode_warn);
-        if (!res)
-                return -ENOMEM;
-
-        return 0;
-}
-
-fs_initcall(alignment_init);
-#endif
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index d86f5315a0c1..e3f92eb05ffd 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -611,19 +611,19 @@ static int misaligned_fpu_load(struct pt_regs *regs,
 
                 switch (width_shift) {
                 case 2:
-                        current->thread.fpu.hard.fp_regs[destreg] = buflo;
+                        current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
                         break;
                 case 3:
                         if (do_paired_load) {
-                                current->thread.fpu.hard.fp_regs[destreg] = buflo;
-                                current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
+                                current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
+                                current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
                         } else {
 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
-                                current->thread.fpu.hard.fp_regs[destreg] = bufhi;
-                                current->thread.fpu.hard.fp_regs[destreg+1] = buflo;
+                                current->thread.xstate->hardfpu.fp_regs[destreg] = bufhi;
+                                current->thread.xstate->hardfpu.fp_regs[destreg+1] = buflo;
 #else
-                                current->thread.fpu.hard.fp_regs[destreg] = buflo;
-                                current->thread.fpu.hard.fp_regs[destreg+1] = bufhi;
+                                current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
+                                current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
 #endif
                         }
                         break;
@@ -681,19 +681,19 @@ static int misaligned_fpu_store(struct pt_regs *regs,
 
                 switch (width_shift) {
                 case 2:
-                        buflo = current->thread.fpu.hard.fp_regs[srcreg];
+                        buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
                         break;
                 case 3:
                         if (do_paired_load) {
-                                buflo = current->thread.fpu.hard.fp_regs[srcreg];
-                                bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
+                                buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
+                                bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
                         } else {
 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
-                                bufhi = current->thread.fpu.hard.fp_regs[srcreg];
-                                buflo = current->thread.fpu.hard.fp_regs[srcreg+1];
+                                bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg];
+                                buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 #else
-                                buflo = current->thread.fpu.hard.fp_regs[srcreg];
-                                bufhi = current->thread.fpu.hard.fp_regs[srcreg+1];
+                                buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
+                                bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
 #endif
                         }
                         break;
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index a1e4ec24f1f5..7f8a709c3ada 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -3,7 +3,7 @@
  * Written by Niibe Yutaka and Paul Mundt
  */
 #ifdef CONFIG_SUPERH64
-#define LOAD_OFFSET     CONFIG_PAGE_OFFSET
+#define LOAD_OFFSET     PAGE_OFFSET
 OUTPUT_ARCH(sh:sh5)
 #else
 #define LOAD_OFFSET     0
@@ -14,17 +14,16 @@ OUTPUT_ARCH(sh)
 #include <asm/cache.h>
 #include <asm/vmlinux.lds.h>
 
+#ifdef CONFIG_PMB
+ #define MEMORY_OFFSET  0
+#else
+ #define MEMORY_OFFSET  __MEMORY_START
+#endif
+
 ENTRY(_start)
 SECTIONS
 {
-#ifdef CONFIG_PMB_FIXED
-        . = CONFIG_PAGE_OFFSET + (CONFIG_MEMORY_START & 0x1fffffff) +
-            CONFIG_ZERO_PAGE_OFFSET;
-#elif defined(CONFIG_32BIT)
-        . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
-#else
-        . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET;
-#endif
+        . = PAGE_OFFSET + MEMORY_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
 
         _text = .;              /* Text and read-only data */
 
@@ -35,12 +34,7 @@ SECTIONS
         .text : AT(ADDR(.text) - LOAD_OFFSET) {
                 HEAD_TEXT
                 TEXT_TEXT
-
-#ifdef CONFIG_SUPERH64
-                *(.text64)
-                *(.text..SHmedia32)
-#endif
-
+                EXTRA_TEXT
                 SCHED_TEXT
                 LOCK_TEXT
                 KPROBES_TEXT
@@ -51,24 +45,12 @@ SECTIONS
         } = 0x0009
 
         EXCEPTION_TABLE(16)
-
         NOTES
-        RO_DATA(PAGE_SIZE)
-
-        /*
-         * Code which must be executed uncached and the associated data
-         */
-        . = ALIGN(PAGE_SIZE);
-        .uncached : AT(ADDR(.uncached) - LOAD_OFFSET) {
-                __uncached_start = .;
-                *(.uncached.text)
-                *(.uncached.data)
-                __uncached_end = .;
-        }
 
+        _sdata = .;
+        RO_DATA(PAGE_SIZE)
         RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
-
-        _edata = .;                     /* End of data section */
+        _edata = .;
 
         DWARF_EH_FRAME
 
diff --git a/arch/sh/math-emu/math.c b/arch/sh/math-emu/math.c
index d6c15cae0912..1fcdb1220975 100644
--- a/arch/sh/math-emu/math.c
+++ b/arch/sh/math-emu/math.c
@@ -471,10 +471,10 @@ static int fpu_emulate(u16 code, struct sh_fpu_soft_struct *fregs, struct pt_reg
  *      denormal_to_double - Given denormalized float number,
  *                           store double float
  *
- *      @fpu: Pointer to sh_fpu_hard structure
+ *      @fpu: Pointer to sh_fpu_soft structure
  *      @n: Index to FP register
  */
-static void denormal_to_double(struct sh_fpu_hard_struct *fpu, int n)
+static void denormal_to_double(struct sh_fpu_soft_struct *fpu, int n)
 {
         unsigned long du, dl;
         unsigned long x = fpu->fpul;
@@ -552,11 +552,11 @@ static int ieee_fpe_handler(struct pt_regs *regs)
         if ((finsn & 0xf1ff) == 0xf0ad) { /* fcnvsd */
                 struct task_struct *tsk = current;
 
-                if ((tsk->thread.fpu.hard.fpscr & (1 << 17))) {
+                if ((tsk->thread.xstate->softfpu.fpscr & (1 << 17))) {
                         /* FPU error */
-                        denormal_to_double (&tsk->thread.fpu.hard,
+                        denormal_to_double (&tsk->thread.xstate->softfpu,
                                             (finsn >> 8) & 0xf);
-                        tsk->thread.fpu.hard.fpscr &=
+                        tsk->thread.xstate->softfpu.fpscr &=
                                 ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK);
                         task_thread_info(tsk)->status |= TS_USEDFPU;
                 } else {
@@ -617,7 +617,7 @@ static void fpu_init(struct sh_fpu_soft_struct *fpu)
 int do_fpu_inst(unsigned short inst, struct pt_regs *regs)
 {
         struct task_struct *tsk = current;
-        struct sh_fpu_soft_struct *fpu = &(tsk->thread.fpu.soft);
+        struct sh_fpu_soft_struct *fpu = &(tsk->thread.xstate->softfpu);
 
         if (!(task_thread_info(tsk)->status & TS_USEDFPU)) {
                 /* initialize once. */
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 986a71b88ca3..1445ca6257df 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -75,52 +75,25 @@ config MEMORY_SIZE
 config 29BIT
         def_bool !32BIT
         depends on SUPERH32
+        select UNCACHED_MAPPING
 
 config 32BIT
         bool
         default y if CPU_SH5
 
-config PMB_ENABLE
-        bool "Support 32-bit physical addressing through PMB"
-        depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
-        help
-          If you say Y here, physical addressing will be extended to
-          32-bits through the SH-4A PMB. If this is not set, legacy
-          29-bit physical addressing will be used.
-
-choice
-        prompt "PMB handling type"
-        depends on PMB_ENABLE
-        default PMB_FIXED
-
 config PMB
-        bool "PMB"
+        bool "Support 32-bit physical addressing through PMB"
         depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
+        select 32BIT
+        select UNCACHED_MAPPING
         help
           If you say Y here, physical addressing will be extended to
           32-bits through the SH-4A PMB. If this is not set, legacy
           29-bit physical addressing will be used.
 
-config PMB_FIXED
-        bool "fixed PMB"
-        depends on MMU && EXPERIMENTAL && CPU_SH4A && !CPU_SH4AL_DSP
-        select 32BIT
-        help
-          If this option is enabled, fixed PMB mappings are inherited
-          from the boot loader, and the kernel does not attempt dynamic
-          management. This is the closest to legacy 29-bit physical mode,
-          and allows systems to support up to 512MiB of system memory.
-
-endchoice
-
 config X2TLB
-        bool "Enable extended TLB mode"
-        depends on (CPU_SHX2 || CPU_SHX3) && MMU && EXPERIMENTAL
-        help
-          Selecting this option will enable the extended mode of the SH-X2
-          TLB. For legacy SH-X behaviour and interoperability, say N. For
-          all of the fun new features and a willingless to submit bug reports,
-          say Y.
+        def_bool y
+        depends on (CPU_SHX2 || CPU_SHX3) && MMU
 
 config VSYSCALL
         bool "Support vsyscall page"
@@ -188,14 +161,19 @@ config ARCH_MEMORY_PROBE
         def_bool y
         depends on MEMORY_HOTPLUG
 
+config IOREMAP_FIXED
+       def_bool y
+       depends on X2TLB || SUPERH64
+
+config UNCACHED_MAPPING
+        bool
+
 choice
         prompt "Kernel page size"
-        default PAGE_SIZE_8KB if X2TLB
         default PAGE_SIZE_4KB
 
 config PAGE_SIZE_4KB
         bool "4kB"
-        depends on !MMU || !X2TLB
         help
           This is the default page size used by all SuperH CPUs.
 
diff --git a/arch/sh/mm/Makefile b/arch/sh/mm/Makefile
index 8a70535fa7ce..3dc8a8a63822 100644
--- a/arch/sh/mm/Makefile
+++ b/arch/sh/mm/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the Linux SuperH-specific parts of the memory manager.
 #
 
-obj-y                   := cache.o init.o consistent.o mmap.o
+obj-y                   := alignment.o cache.o init.o consistent.o mmap.o
 
 cacheops-$(CONFIG_CPU_SH2)              := cache-sh2.o
 cacheops-$(CONFIG_CPU_SH2A)             := cache-sh2a.o
@@ -15,7 +15,7 @@ obj-y			+= $(cacheops-y)
 
 mmu-y                   := nommu.o extable_32.o
 mmu-$(CONFIG_MMU)       := extable_$(BITS).o fault_$(BITS).o \
-                           ioremap_$(BITS).o kmap.o tlbflush_$(BITS).o
+                           ioremap.o kmap.o pgtable.o tlbflush_$(BITS).o
 
 obj-y                   += $(mmu-y)
 obj-$(CONFIG_DEBUG_FS)  += asids-debugfs.o
@@ -26,15 +26,17 @@ endif
 
 ifdef CONFIG_MMU
 tlb-$(CONFIG_CPU_SH3)           := tlb-sh3.o
-tlb-$(CONFIG_CPU_SH4)           := tlb-sh4.o
+tlb-$(CONFIG_CPU_SH4)           := tlb-sh4.o tlb-urb.o
 tlb-$(CONFIG_CPU_SH5)           := tlb-sh5.o
-tlb-$(CONFIG_CPU_HAS_PTEAEX)    := tlb-pteaex.o
+tlb-$(CONFIG_CPU_HAS_PTEAEX)    := tlb-pteaex.o tlb-urb.o
 obj-y                           += $(tlb-y)
 endif
 
 obj-$(CONFIG_HUGETLB_PAGE)      += hugetlbpage.o
-obj-$(CONFIG_PMB_ENABLE)        += pmb.o
+obj-$(CONFIG_PMB)               += pmb.o
 obj-$(CONFIG_NUMA)              += numa.o
+obj-$(CONFIG_IOREMAP_FIXED)     += ioremap_fixed.o
+obj-$(CONFIG_UNCACHED_MAPPING)  += uncached.o
 
 # Special flags for fault_64.o.  This puts restrictions on the number of
 # caller-save registers that the compiler can target when building this file.
diff --git a/arch/sh/mm/alignment.c b/arch/sh/mm/alignment.c
new file mode 100644
index 000000000000..b2595b8548ee
--- /dev/null
+++ b/arch/sh/mm/alignment.c
@@ -0,0 +1,189 @@
+/*
+ * Alignment access counters and corresponding user-space interfaces.
+ *
+ * Copyright (C) 2009 ST Microelectronics
+ * Copyright (C) 2009 - 2010 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/seq_file.h>
+#include <linux/proc_fs.h>
+#include <linux/uaccess.h>
+#include <asm/alignment.h>
+#include <asm/processor.h>
+
+static unsigned long se_user;
+static unsigned long se_sys;
+static unsigned long se_half;
+static unsigned long se_word;
+static unsigned long se_dword;
+static unsigned long se_multi;
+/* bitfield: 1: warn 2: fixup 4: signal -> combinations 2|4 && 1|2|4 are not
+   valid! */
+static int se_usermode = UM_WARN | UM_FIXUP;
+/* 0: no warning 1: print a warning message, disabled by default */
+static int se_kernmode_warn;
+
+core_param(alignment, se_usermode, int, 0600);
+
+void inc_unaligned_byte_access(void)
+{
+        se_half++;
+}
+
+void inc_unaligned_word_access(void)
+{
+        se_word++;
+}
+
+void inc_unaligned_dword_access(void)
+{
+        se_dword++;
+}
+
+void inc_unaligned_multi_access(void)
+{
+        se_multi++;
+}
+
+void inc_unaligned_user_access(void)
+{
+        se_user++;
+}
+
+void inc_unaligned_kernel_access(void)
+{
+        se_sys++;
+}
+
+/*
+ * This defaults to the global policy which can be set from the command
+ * line, while processes can overload their preferences via prctl().
+ */
+unsigned int unaligned_user_action(void)
+{
+        unsigned int action = se_usermode;
+
+        if (current->thread.flags & SH_THREAD_UAC_SIGBUS) {
+                action &= ~UM_FIXUP;
+                action |= UM_SIGNAL;
+        }
+
+        if (current->thread.flags & SH_THREAD_UAC_NOPRINT)
+                action &= ~UM_WARN;
+
+        return action;
+}
+
+int get_unalign_ctl(struct task_struct *tsk, unsigned long addr)
+{
+        return put_user(tsk->thread.flags & SH_THREAD_UAC_MASK,
+                        (unsigned int __user *)addr);
+}
+
+int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
+{
+        tsk->thread.flags = (tsk->thread.flags & ~SH_THREAD_UAC_MASK) |
+                            (val & SH_THREAD_UAC_MASK);
+        return 0;
+}
+
+void unaligned_fixups_notify(struct task_struct *tsk, insn_size_t insn,
+                             struct pt_regs *regs)
+{
+        if (user_mode(regs) && (se_usermode & UM_WARN) && printk_ratelimit())
+                pr_notice("Fixing up unaligned userspace access "
+                          "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                          tsk->comm, task_pid_nr(tsk),
+                          (void *)instruction_pointer(regs), insn);
+        else if (se_kernmode_warn && printk_ratelimit())
+                pr_notice("Fixing up unaligned kernel access "
+                          "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
+                          tsk->comm, task_pid_nr(tsk),
+                          (void *)instruction_pointer(regs), insn);
+}
+
+static const char *se_usermode_action[] = {
+        "ignored",
+        "warn",
+        "fixup",
+        "fixup+warn",
+        "signal",
+        "signal+warn"
+};
+
+static int alignment_proc_show(struct seq_file *m, void *v)
+{
+        seq_printf(m, "User:\t\t%lu\n", se_user);
+        seq_printf(m, "System:\t\t%lu\n", se_sys);
+        seq_printf(m, "Half:\t\t%lu\n", se_half);
+        seq_printf(m, "Word:\t\t%lu\n", se_word);
+        seq_printf(m, "DWord:\t\t%lu\n", se_dword);
+        seq_printf(m, "Multi:\t\t%lu\n", se_multi);
+        seq_printf(m, "User faults:\t%i (%s)\n", se_usermode,
+                        se_usermode_action[se_usermode]);
+        seq_printf(m, "Kernel faults:\t%i (fixup%s)\n", se_kernmode_warn,
+                        se_kernmode_warn ? "+warn" : "");
+        return 0;
+}
+
+static int alignment_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, alignment_proc_show, NULL);
+}
+
+static ssize_t alignment_proc_write(struct file *file,
+                const char __user *buffer, size_t count, loff_t *pos)
+{
+        int *data = PDE(file->f_path.dentry->d_inode)->data;
+        char mode;
+
+        if (count > 0) {
+                if (get_user(mode, buffer))
+                        return -EFAULT;
+                if (mode >= '0' && mode <= '5')
+                        *data = mode - '0';
+        }
+        return count;
+}
+
+static const struct file_operations alignment_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = alignment_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .write          = alignment_proc_write,
+};
+
+/*
+ * This needs to be done after sysctl_init, otherwise sys/ will be
+ * overwritten.  Actually, this shouldn't be in sys/ at all since
+ * it isn't a sysctl, and it doesn't contain sysctl information.
+ * We now locate it in /proc/cpu/alignment instead.
+ */
+static int __init alignment_init(void)
+{
+        struct proc_dir_entry *dir, *res;
+
+        dir = proc_mkdir("cpu", NULL);
+        if (!dir)
+                return -ENOMEM;
+
+        res = proc_create_data("alignment", S_IWUSR | S_IRUGO, dir,
+                               &alignment_proc_fops, &se_usermode);
+        if (!res)
+                return -ENOMEM;
+
+        res = proc_create_data("kernel_alignment", S_IWUSR | S_IRUGO, dir,
+                               &alignment_proc_fops, &se_kernmode_warn);
+        if (!res)
+                return -ENOMEM;
+
+        return 0;
+}
+fs_initcall(alignment_init);
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 5ba067b26591..690ed010d002 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -22,8 +22,7 @@ enum cache_type {
         CACHE_TYPE_UNIFIED,
 };
 
-static int __uses_jump_to_uncached cache_seq_show(struct seq_file *file,
-                                                  void *iter)
+static int cache_seq_show(struct seq_file *file, void *iter)
 {
         unsigned int cache_type = (unsigned int)file->private;
         struct cache_info *cache;
@@ -37,7 +36,7 @@ static int __uses_jump_to_uncached cache_seq_show(struct seq_file *file,
          */
         jump_to_uncached();
 
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
         if ((ccr & CCR_CACHE_ENABLE) == 0) {
                 back_to_cached();
 
@@ -90,7 +89,7 @@ static int __uses_jump_to_uncached cache_seq_show(struct seq_file *file,
                 for (addr = addrstart, line = 0;
                      addr < addrstart + waysize;
                      addr += cache->linesz, line++) {
-                        unsigned long data = ctrl_inl(addr);
+                        unsigned long data = __raw_readl(addr);
 
                         /* Check the V bit, ignore invalid cachelines */
                         if ((data & 1) == 0)
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 699a71f46327..defcf719f2e8 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -28,10 +28,10 @@ static void sh2__flush_wback_region(void *start, int size)
                 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
                 int way;
                 for (way = 0; way < 4; way++) {
-                        unsigned long data =  ctrl_inl(addr | (way << 12));
+                        unsigned long data =  __raw_readl(addr | (way << 12));
                         if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, addr | (way << 12));
+                                __raw_writel(data, addr | (way << 12));
                         }
                 }
         }
@@ -47,7 +47,7 @@ static void sh2__flush_purge_region(void *start, int size)
                 & ~(L1_CACHE_BYTES-1);
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES)
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 }
 
@@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region(void *start, int size)
         local_irq_save(flags);
         jump_to_uncached();
 
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
         ccr |= CCR_CACHE_INVALIDATE;
-        ctrl_outl(ccr, CCR);
+        __raw_writel(ccr, CCR);
 
         back_to_cached();
         local_irq_restore(flags);
@@ -78,7 +78,7 @@ static void sh2__flush_invalidate_region(void *start, int size)
                 & ~(L1_CACHE_BYTES-1);
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES)
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
 #endif
 }
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 975899d83564..1f51225426a2 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -32,10 +32,10 @@ static void sh2a__flush_wback_region(void *start, int size)
                 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
                 int way;
                 for (way = 0; way < 4; way++) {
-                        unsigned long data =  ctrl_inl(addr | (way << 11));
+                        unsigned long data =  __raw_readl(addr | (way << 11));
                         if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, addr | (way << 11));
+                                __raw_writel(data, addr | (way << 11));
                         }
                 }
         }
@@ -58,7 +58,7 @@ static void sh2a__flush_purge_region(void *start, int size)
         jump_to_uncached();
 
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
         }
         back_to_cached();
@@ -78,17 +78,17 @@ static void sh2a__flush_invalidate_region(void *start, int size)
         jump_to_uncached();
 
 #ifdef CONFIG_CACHE_WRITEBACK
-        ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
+        __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
         /* I-cache invalidate */
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
         }
 #else
         for (v = begin; v < end; v+=L1_CACHE_BYTES) {
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
-                ctrl_outl((v & CACHE_PHYSADDR_MASK),
+                __raw_writel((v & CACHE_PHYSADDR_MASK),
                           CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
         }
 #endif
@@ -115,14 +115,14 @@ static void sh2a_flush_icache_range(void *args)
                 int way;
                 /* O-Cache writeback */
                 for (way = 0; way < 4; way++) {
-                        unsigned long data =  ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                        unsigned long data =  __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
                         if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
+                                __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
                         }
                 }
                 /* I-Cache invalidate */
-                ctrl_outl(addr,
+                __raw_writel(addr,
                           CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
         }
 
diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c
index faef80c98134..e37523f65195 100644
--- a/arch/sh/mm/cache-sh3.c
+++ b/arch/sh/mm/cache-sh3.c
@@ -50,12 +50,12 @@ static void sh3__flush_wback_region(void *start, int size)
                         p = __pa(v);
                         addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
                         local_irq_save(flags);
-                        data = ctrl_inl(addr);
+                        data = __raw_readl(addr);
 
                         if ((data & CACHE_PHYSADDR_MASK) ==
                             (p & CACHE_PHYSADDR_MASK)) {
                                 data &= ~SH_CACHE_UPDATED;
-                                ctrl_outl(data, addr);
+                                __raw_writel(data, addr);
                                 local_irq_restore(flags);
                                 break;
                         }
@@ -86,7 +86,7 @@ static void sh3__flush_purge_region(void *start, int size)
                 data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
                 addr = CACHE_OC_ADDRESS_ARRAY |
                         (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
-                ctrl_outl(data, addr);
+                __raw_writel(data, addr);
         }
 }
 
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 560ddb6bc8a7..2cfae81914aa 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -36,7 +36,7 @@ static void __flush_cache_one(unsigned long addr, unsigned long phys,
  * Called from kernel/module.c:sys_init_module and routine for a.out format,
  * signal handler code and kprobes code
  */
-static void __uses_jump_to_uncached sh4_flush_icache_range(void *args)
+static void sh4_flush_icache_range(void *args)
 {
         struct flusher_data *data = args;
         unsigned long start, end;
@@ -109,6 +109,7 @@ static inline void flush_cache_one(unsigned long start, unsigned long phys)
 static void sh4_flush_dcache_page(void *arg)
 {
         struct page *page = arg;
+        unsigned long addr = (unsigned long)page_address(page);
 #ifndef CONFIG_SMP
         struct address_space *mapping = page_mapping(page);
 
@@ -116,22 +117,14 @@ static void sh4_flush_dcache_page(void *arg)
                 set_bit(PG_dcache_dirty, &page->flags);
         else
 #endif
-        {
-                unsigned long phys = page_to_phys(page);
-                unsigned long addr = CACHE_OC_ADDRESS_ARRAY;
-                int i, n;
-
-                /* Loop all the D-cache */
-                n = boot_cpu_data.dcache.n_aliases;
-                for (i = 0; i < n; i++, addr += PAGE_SIZE)
-                        flush_cache_one(addr, phys);
-        }
+                flush_cache_one(CACHE_OC_ADDRESS_ARRAY |
+                                (addr & shm_align_mask), page_to_phys(page));
 
         wmb();
 }
 
 /* TODO: Selective icache invalidation through IC address array.. */
-static void __uses_jump_to_uncached flush_icache_all(void)
+static void flush_icache_all(void)
 {
         unsigned long flags, ccr;
 
@@ -139,9 +132,9 @@ static void __uses_jump_to_uncached flush_icache_all(void)
         jump_to_uncached();
 
         /* Flush I-cache */
-        ccr = ctrl_inl(CCR);
+        ccr = __raw_readl(CCR);
         ccr |= CCR_CACHE_ICI;
-        ctrl_outl(ccr, CCR);
+        __raw_writel(ccr, CCR);
 
         /*
          * back_to_cached() will take care of the barrier for us, don't add
@@ -384,9 +377,9 @@ extern void __weak sh4__flush_region_init(void);
 void __init sh4_cache_init(void)
 {
         printk("PVR=%08x CVR=%08x PRR=%08x\n",
-                ctrl_inl(CCN_PVR),
-                ctrl_inl(CCN_CVR),
-                ctrl_inl(CCN_PRR));
+                __raw_readl(CCN_PVR),
+                __raw_readl(CCN_CVR),
+                __raw_readl(CCN_PRR));
 
         local_flush_icache_range        = sh4_flush_icache_range;
         local_flush_dcache_page         = sh4_flush_dcache_page;
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index f527fb70fce6..f498da1cce7a 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -48,10 +48,10 @@ static inline void cache_wback_all(void)
                         unsigned long data;
                         int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
 
-                        data = ctrl_inl(addr);
+                        data = __raw_readl(addr);
 
                         if ((data & v) == v)
-                                ctrl_outl(data & ~v, addr);
+                                __raw_writel(data & ~v, addr);
 
                 }
 
@@ -78,7 +78,7 @@ static void sh7705_flush_icache_range(void *args)
 /*
  * Writeback&Invalidate the D-cache of the page
  */
-static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys)
+static void __flush_dcache_page(unsigned long phys)
 {
         unsigned long ways, waysize, addrstart;
         unsigned long flags;
@@ -115,10 +115,10 @@ static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys)
                      addr += current_cpu_data.dcache.linesz) {
                         unsigned long data;
 
-                        data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
+                        data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
                         if (data == phys) {
                                 data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
-                                ctrl_outl(data, addr);
+                                __raw_writel(data, addr);
                         }
                 }
 
@@ -144,7 +144,7 @@ static void sh7705_flush_dcache_page(void *arg)
                 __flush_dcache_page(__pa(page_address(page)));
 }
 
-static void __uses_jump_to_uncached sh7705_flush_cache_all(void *args)
+static void sh7705_flush_cache_all(void *args)
 {
         unsigned long flags;
 
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index b8607fa7ae12..0f4095d7ac8b 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -2,7 +2,7 @@
  * arch/sh/mm/cache.c
  *
  * Copyright (C) 1999, 2000, 2002  Niibe Yutaka
- * Copyright (C) 2002 - 2009  Paul Mundt
+ * Copyright (C) 2002 - 2010  Paul Mundt
  *
  * Released under the terms of the GNU GPL v2.0.
  */
@@ -41,8 +41,17 @@ static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
                                    int wait)
 {
         preempt_disable();
-        smp_call_function(func, info, wait);
+
+        /*
+         * It's possible that this gets called early on when IRQs are
+         * still disabled due to ioremapping by the boot CPU, so don't
+         * even attempt IPIs unless there are other CPUs online.
+         */
+        if (num_online_cpus() > 1)
+                smp_call_function(func, info, wait);
+
         func(info);
+
         preempt_enable();
 }
 
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 47530104e0ad..8bf79e3b7bdd 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -53,6 +53,9 @@ static inline pmd_t *vmalloc_sync_one(pgd_t *pgd, unsigned long address)
         if (!pud_present(*pud_k))
                 return NULL;
 
+        if (!pud_present(*pud))
+            set_pud(pud, *pud_k);
+
         pmd = pmd_offset(pud, address);
         pmd_k = pmd_offset(pud_k, address);
         if (!pmd_present(*pmd_k))
@@ -371,7 +374,7 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess,
                 local_flush_tlb_one(get_asid(), address & PAGE_MASK);
 #endif
 
-        update_mmu_cache(NULL, address, entry);
+        update_mmu_cache(NULL, address, pte);
 
         return 0;
 }
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 432acd07e76a..68028e8f26ce 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -21,25 +21,13 @@
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
 #include <asm/cache.h>
+#include <asm/sizes.h>
 
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
-#ifdef CONFIG_SUPERH32
-/*
- * Handle trivial transitions between cached and uncached
- * segments, making use of the 1:1 mapping relationship in
- * 512MB lowmem.
- *
- * This is the offset of the uncached section from its cached alias.
- * Default value only valid in 29 bit mode, in 32bit mode will be
- * overridden in pmb_init.
- */
-unsigned long cached_to_uncached = P2SEG - P1SEG;
-#endif
-
 #ifdef CONFIG_MMU
-static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
+static pte_t *__get_pte_phys(unsigned long addr)
 {
         pgd_t *pgd;
         pud_t *pud;
@@ -49,22 +37,30 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
         pgd = pgd_offset_k(addr);
         if (pgd_none(*pgd)) {
                 pgd_ERROR(*pgd);
-                return;
+                return NULL;
         }
 
         pud = pud_alloc(NULL, pgd, addr);
         if (unlikely(!pud)) {
                 pud_ERROR(*pud);
-                return;
+                return NULL;
         }
 
         pmd = pmd_alloc(NULL, pud, addr);
         if (unlikely(!pmd)) {
                 pmd_ERROR(*pmd);
-                return;
+                return NULL;
         }
 
         pte = pte_offset_kernel(pmd, addr);
+        return pte;
+}
+
+static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
+{
+        pte_t *pte;
+
+        pte = __get_pte_phys(addr);
         if (!pte_none(*pte)) {
                 pte_ERROR(*pte);
                 return;
@@ -72,23 +68,24 @@ static void set_pte_phys(unsigned long addr, unsigned long phys, pgprot_t prot)
 
         set_pte(pte, pfn_pte(phys >> PAGE_SHIFT, prot));
         local_flush_tlb_one(get_asid(), addr);
+
+        if (pgprot_val(prot) & _PAGE_WIRED)
+                tlb_wire_entry(NULL, addr, *pte);
+}
+
+static void clear_pte_phys(unsigned long addr, pgprot_t prot)
+{
+        pte_t *pte;
+
+        pte = __get_pte_phys(addr);
+
+        if (pgprot_val(prot) & _PAGE_WIRED)
+                tlb_unwire_entry();
+
+        set_pte(pte, pfn_pte(0, __pgprot(0)));
+        local_flush_tlb_one(get_asid(), addr);
 }
 
-/*
- * As a performance optimization, other platforms preserve the fixmap mapping
- * across a context switch, we don't presently do this, but this could be done
- * in a similar fashion as to the wired TLB interface that sh64 uses (by way
- * of the memory mapped UTLB configuration) -- this unfortunately forces us to
- * give up a TLB entry for each mapping we want to preserve. While this may be
- * viable for a small number of fixmaps, it's not particularly useful for
- * everything and needs to be carefully evaluated. (ie, we may want this for
- * the vsyscall page).
- *
- * XXX: Perhaps add a _PAGE_WIRED flag or something similar that we can pass
- * in at __set_fixmap() time to determine the appropriate behavior to follow.
- *
- *                                       -- PFM.
- */
 void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
 {
         unsigned long address = __fix_to_virt(idx);
@@ -101,6 +98,18 @@ void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
         set_pte_phys(address, phys, prot);
 }
 
+void __clear_fixmap(enum fixed_addresses idx, pgprot_t prot)
+{
+        unsigned long address = __fix_to_virt(idx);
+
+        if (idx >= __end_of_fixed_addresses) {
+                BUG();
+                return;
+        }
+
+        clear_pte_phys(address, prot);
+}
+
 void __init page_table_range_init(unsigned long start, unsigned long end,
                                          pgd_t *pgd_base)
 {
@@ -120,7 +129,13 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
         for ( ; (i < PTRS_PER_PGD) && (vaddr != end); pgd++, i++) {
                 pud = (pud_t *)pgd;
                 for ( ; (j < PTRS_PER_PUD) && (vaddr != end); pud++, j++) {
+#ifdef __PAGETABLE_PMD_FOLDED
                         pmd = (pmd_t *)pud;
+#else
+                        pmd = (pmd_t *)alloc_bootmem_low_pages(PAGE_SIZE);
+                        pud_populate(&init_mm, pud, pmd);
+                        pmd += k;
+#endif
                         for (; (k < PTRS_PER_PMD) && (vaddr != end); pmd++, k++) {
                                 if (pmd_none(*pmd)) {
                                         pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE);
@@ -182,9 +197,6 @@ void __init paging_init(void)
         }
 
         free_area_init_nodes(max_zone_pfns);
-
-        /* Set up the uncached fixmap */
-        set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start));
 }
 
 /*
@@ -195,6 +207,8 @@ static void __init iommu_init(void)
         no_iommu_init();
 }
 
+unsigned int mem_init_done = 0;
+
 void __init mem_init(void)
 {
         int codesize, datasize, initsize;
@@ -231,6 +245,8 @@ void __init mem_init(void)
         memset(empty_zero_page, 0, PAGE_SIZE);
         __flush_wback_region(empty_zero_page, PAGE_SIZE);
 
+        vsyscall_init();
+
         codesize =  (unsigned long) &_etext - (unsigned long) &_text;
         datasize =  (unsigned long) &_edata - (unsigned long) &_etext;
         initsize =  (unsigned long) &__init_end - (unsigned long) &__init_begin;
@@ -243,8 +259,48 @@ void __init mem_init(void)
                 datasize >> 10,
                 initsize >> 10);
 
-        /* Initialize the vDSO */
-        vsyscall_init();
+        printk(KERN_INFO "virtual kernel memory layout:\n"
+                "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#ifdef CONFIG_HIGHMEM
+                "    pkmap   : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#endif
+                "    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+                "    lowmem  : 0x%08lx - 0x%08lx   (%4ld MB) (cached)\n"
+#ifdef CONFIG_UNCACHED_MAPPING
+                "            : 0x%08lx - 0x%08lx   (%4ld MB) (uncached)\n"
+#endif
+                "      .init : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+                "      .data : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+                "      .text : 0x%08lx - 0x%08lx   (%4ld kB)\n",
+                FIXADDR_START, FIXADDR_TOP,
+                (FIXADDR_TOP - FIXADDR_START) >> 10,
+
+#ifdef CONFIG_HIGHMEM
+                PKMAP_BASE, PKMAP_BASE+LAST_PKMAP*PAGE_SIZE,
+                (LAST_PKMAP*PAGE_SIZE) >> 10,
+#endif
+
+                (unsigned long)VMALLOC_START, VMALLOC_END,
+                (VMALLOC_END - VMALLOC_START) >> 20,
+
+                (unsigned long)memory_start, (unsigned long)high_memory,
+                ((unsigned long)high_memory - (unsigned long)memory_start) >> 20,
+
+#ifdef CONFIG_UNCACHED_MAPPING
+                uncached_start, uncached_end, uncached_size >> 20,
+#endif
+
+                (unsigned long)&__init_begin, (unsigned long)&__init_end,
+                ((unsigned long)&__init_end -
+                 (unsigned long)&__init_begin) >> 10,
+
+                (unsigned long)&_etext, (unsigned long)&_edata,
+                ((unsigned long)&_edata - (unsigned long)&_etext) >> 10,
+
+                (unsigned long)&_text, (unsigned long)&_etext,
+                ((unsigned long)&_etext - (unsigned long)&_text) >> 10);
+
+        mem_init_done = 1;
 }
 
 void free_initmem(void)
@@ -277,35 +333,6 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 }
 #endif
 
-#if THREAD_SHIFT < PAGE_SHIFT
-static struct kmem_cache *thread_info_cache;
-
-struct thread_info *alloc_thread_info(struct task_struct *tsk)
-{
-        struct thread_info *ti;
-
-        ti = kmem_cache_alloc(thread_info_cache, GFP_KERNEL);
-        if (unlikely(ti == NULL))
-                return NULL;
-#ifdef CONFIG_DEBUG_STACK_USAGE
-        memset(ti, 0, THREAD_SIZE);
-#endif
-        return ti;
-}
-
-void free_thread_info(struct thread_info *ti)
-{
-        kmem_cache_free(thread_info_cache, ti);
-}
-
-void thread_info_cache_init(void)
-{
-        thread_info_cache = kmem_cache_create("thread_info", THREAD_SIZE,
-                                              THREAD_SIZE, 0, NULL);
-        BUG_ON(thread_info_cache == NULL);
-}
-#endif /* THREAD_SHIFT < PAGE_SHIFT */
-
 #ifdef CONFIG_MEMORY_HOTPLUG
 int arch_add_memory(int nid, u64 start, u64 size)
 {
@@ -336,10 +363,3 @@ EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
 #endif
 
 #endif /* CONFIG_MEMORY_HOTPLUG */
-
-#ifdef CONFIG_PMB
-int __in_29bit_mode(void)
-{
-        return !(ctrl_inl(PMB_PASCR) & PASCR_SE);
-}
-#endif /* CONFIG_PMB */
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap.c
index 2141befb4f91..c68d2d7d00a9 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap.c
@@ -1,13 +1,13 @@
 /*
  * arch/sh/mm/ioremap.c
  *
+ * (C) Copyright 1995 1996 Linus Torvalds
+ * (C) Copyright 2005 - 2010  Paul Mundt
+ *
  * Re-map IO memory to kernel address space so that we can access it.
  * This is needed for high PCI addresses that aren't mapped in the
  * 640k-1MB IO memory area on PC's
  *
- * (C) Copyright 1995 1996 Linus Torvalds
- * (C) Copyright 2005, 2006 Paul Mundt
- *
  * This file is subject to the terms and conditions of the GNU General
  * Public License. See the file "COPYING" in the main directory of this
  * archive for more details.
@@ -33,12 +33,12 @@
  * have to convert them into an offset in a page-aligned mapping, but the
  * caller shouldn't need to know that small detail.
  */
-void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
-                               unsigned long flags, void *caller)
+void __iomem * __init_refok
+__ioremap_caller(unsigned long phys_addr, unsigned long size,
+                 pgprot_t pgprot, void *caller)
 {
         struct vm_struct *area;
         unsigned long offset, last_addr, addr, orig_addr;
-        pgprot_t pgprot;
 
         /* Don't allow wraparound or zero size */
         last_addr = phys_addr + size - 1;
@@ -46,18 +46,6 @@ void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
                 return NULL;
 
         /*
-         * If we're in the fixed PCI memory range, mapping through page
-         * tables is not only pointless, but also fundamentally broken.
-         * Just return the physical address instead.
-         *
-         * For boards that map a small PCI memory aperture somewhere in
-         * P1/P2 space, ioremap() will already do the right thing,
-         * and we'll never get this far.
-         */
-        if (is_pci_memory_fixed_range(phys_addr, size))
-                return (void __iomem *)phys_addr;
-
-        /*
          * Mappings have to be page-aligned
          */
         offset = phys_addr & ~PAGE_MASK;
@@ -65,6 +53,12 @@ void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
         size = PAGE_ALIGN(last_addr+1) - phys_addr;
 
         /*
+         * If we can't yet use the regular approach, go the fixmap route.
+         */
+        if (!mem_init_done)
+                return ioremap_fixed(phys_addr, offset, size, pgprot);
+
+        /*
          * Ok, go for it..
          */
         area = get_vm_area_caller(size, VM_IOREMAP, caller);
@@ -84,8 +78,9 @@ void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
          * PMB entries are all pre-faulted.
          */
         if (unlikely(phys_addr >= P1SEG)) {
-                unsigned long mapped = pmb_remap(addr, phys_addr, size, flags);
+                unsigned long mapped;
 
+                mapped = pmb_remap(addr, phys_addr, size, pgprot);
                 if (likely(mapped)) {
                         addr            += mapped;
                         phys_addr       += mapped;
@@ -94,7 +89,6 @@ void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
         }
 #endif
 
-        pgprot = __pgprot(pgprot_val(PAGE_KERNEL_NOCACHE) | flags);
         if (likely(size))
                 if (ioremap_page_range(addr, addr + size, phys_addr, pgprot)) {
                         vunmap((void *)orig_addr);
@@ -105,15 +99,38 @@ void __iomem *__ioremap_caller(unsigned long phys_addr, unsigned long size,
 }
 EXPORT_SYMBOL(__ioremap_caller);
 
+/*
+ * Simple checks for non-translatable mappings.
+ */
+static inline int iomapping_nontranslatable(unsigned long offset)
+{
+#ifdef CONFIG_29BIT
+        /*
+         * In 29-bit mode this includes the fixed P1/P2 areas, as well as
+         * parts of P3.
+         */
+        if (PXSEG(offset) < P3SEG || offset >= P3_ADDR_MAX)
+                return 1;
+#endif
+
+        return 0;
+}
+
 void __iounmap(void __iomem *addr)
 {
         unsigned long vaddr = (unsigned long __force)addr;
-        unsigned long seg = PXSEG(vaddr);
         struct vm_struct *p;
 
-        if (seg < P3SEG || vaddr >= P3_ADDR_MAX)
+        /*
+         * Nothing to do if there is no translatable mapping.
+         */
+        if (iomapping_nontranslatable(vaddr))
                 return;
-        if (is_pci_memory_fixed_range(vaddr, 0))
+
+        /*
+         * There's no VMA if it's from an early fixed mapping.
+         */
+        if (iounmap_fixed(addr) == 0)
                 return;
 
 #ifdef CONFIG_PMB
diff --git a/arch/sh/mm/ioremap_64.c b/arch/sh/mm/ioremap_64.c
deleted file mode 100644
index ef434657d428..000000000000
--- a/arch/sh/mm/ioremap_64.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * arch/sh/mm/ioremap_64.c
- *
- * Copyright (C) 2000, 2001  Paolo Alberelli
- * Copyright (C) 2003 - 2007  Paul Mundt
- *
- * Mostly derived from arch/sh/mm/ioremap.c which, in turn is mostly
- * derived from arch/i386/mm/ioremap.c .
- *
- *   (C) Copyright 1995 1996 Linus Torvalds
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/vmalloc.h>
-#include <linux/ioport.h>
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/io.h>
-#include <linux/bootmem.h>
-#include <linux/proc_fs.h>
-#include <linux/slab.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/addrspace.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <asm/mmu.h>
-
-static struct resource shmedia_iomap = {
-        .name   = "shmedia_iomap",
-        .start  = IOBASE_VADDR + PAGE_SIZE,
-        .end    = IOBASE_END - 1,
-};
-
-static void shmedia_mapioaddr(unsigned long pa, unsigned long va,
-                              unsigned long flags);
-static void shmedia_unmapioaddr(unsigned long vaddr);
-static void __iomem *shmedia_ioremap(struct resource *res, u32 pa,
-                                     int sz, unsigned long flags);
-
-/*
- * We have the same problem as the SPARC, so lets have the same comment:
- * Our mini-allocator...
- * Boy this is gross! We need it because we must map I/O for
- * timers and interrupt controller before the kmalloc is available.
- */
-
-#define XNMLN  15
-#define XNRES  10
-
-struct xresource {
-        struct resource xres;   /* Must be first */
-        int xflag;              /* 1 == used */
-        char xname[XNMLN+1];
-};
-
-static struct xresource xresv[XNRES];
-
-static struct xresource *xres_alloc(void)
-{
-        struct xresource *xrp;
-        int n;
-
-        xrp = xresv;
-        for (n = 0; n < XNRES; n++) {
-                if (xrp->xflag == 0) {
-                        xrp->xflag = 1;
-                        return xrp;
-                }
-                xrp++;
-        }
-        return NULL;
-}
-
-static void xres_free(struct xresource *xrp)
-{
-        xrp->xflag = 0;
-}
-
-static struct resource *shmedia_find_resource(struct resource *root,
-                                              unsigned long vaddr)
-{
-        struct resource *res;
-
-        for (res = root->child; res; res = res->sibling)
-                if (res->start <= vaddr && res->end >= vaddr)
-                        return res;
-
-        return NULL;
-}
-
-static void __iomem *shmedia_alloc_io(unsigned long phys, unsigned long size,
-                                      const char *name, unsigned long flags)
-{
-        struct xresource *xres;
-        struct resource *res;
-        char *tack;
-        int tlen;
-
-        if (name == NULL)
-                name = "???";
-
-        xres = xres_alloc();
-        if (xres != 0) {
-                tack = xres->xname;
-                res = &xres->xres;
-        } else {
-                printk_once(KERN_NOTICE "%s: done with statics, "
-                               "switching to kmalloc\n", __func__);
-                tlen = strlen(name);
-                tack = kmalloc(sizeof(struct resource) + tlen + 1, GFP_KERNEL);
-                if (!tack)
-                        return NULL;
-                memset(tack, 0, sizeof(struct resource));
-                res = (struct resource *) tack;
-                tack += sizeof(struct resource);
-        }
-
-        strncpy(tack, name, XNMLN);
-        tack[XNMLN] = 0;
-        res->name = tack;
-
-        return shmedia_ioremap(res, phys, size, flags);
-}
-
-static void __iomem *shmedia_ioremap(struct resource *res, u32 pa, int sz,
-                                     unsigned long flags)
-{
-        unsigned long offset = ((unsigned long) pa) & (~PAGE_MASK);
-        unsigned long round_sz = (offset + sz + PAGE_SIZE-1) & PAGE_MASK;
-        unsigned long va;
-        unsigned int psz;
-
-        if (allocate_resource(&shmedia_iomap, res, round_sz,
-                              shmedia_iomap.start, shmedia_iomap.end,
-                              PAGE_SIZE, NULL, NULL) != 0) {
-                panic("alloc_io_res(%s): cannot occupy\n",
-                      (res->name != NULL) ? res->name : "???");
-        }
-
-        va = res->start;
-        pa &= PAGE_MASK;
-
-        psz = (res->end - res->start + (PAGE_SIZE - 1)) / PAGE_SIZE;
-
-        for (psz = res->end - res->start + 1; psz != 0; psz -= PAGE_SIZE) {
-                shmedia_mapioaddr(pa, va, flags);
-                va += PAGE_SIZE;
-                pa += PAGE_SIZE;
-        }
-
-        return (void __iomem *)(unsigned long)(res->start + offset);
-}
-
-static void shmedia_free_io(struct resource *res)
-{
-        unsigned long len = res->end - res->start + 1;
-
-        BUG_ON((len & (PAGE_SIZE - 1)) != 0);
-
-        while (len) {
-                len -= PAGE_SIZE;
-                shmedia_unmapioaddr(res->start + len);
-        }
-
-        release_resource(res);
-}
-
-static __init_refok void *sh64_get_page(void)
-{
-        void *page;
-
-        if (slab_is_available())
-                page = (void *)get_zeroed_page(GFP_KERNEL);
-        else
-                page = alloc_bootmem_pages(PAGE_SIZE);
-
-        if (!page || ((unsigned long)page & ~PAGE_MASK))
-                panic("sh64_get_page: Out of memory already?\n");
-
-        return page;
-}
-
-static void shmedia_mapioaddr(unsigned long pa, unsigned long va,
-                              unsigned long flags)
-{
-        pgd_t *pgdp;
-        pud_t *pudp;
-        pmd_t *pmdp;
-        pte_t *ptep, pte;
-        pgprot_t prot;
-
-        pr_debug("shmedia_mapiopage pa %08lx va %08lx\n",  pa, va);
-
-        if (!flags)
-                flags = 1; /* 1 = CB0-1 device */
-
-        pgdp = pgd_offset_k(va);
-        if (pgd_none(*pgdp) || !pgd_present(*pgdp)) {
-                pudp = (pud_t *)sh64_get_page();
-                set_pgd(pgdp, __pgd((unsigned long)pudp | _KERNPG_TABLE));
-        }
-
-        pudp = pud_offset(pgdp, va);
-        if (pud_none(*pudp) || !pud_present(*pudp)) {
-                pmdp = (pmd_t *)sh64_get_page();
-                set_pud(pudp, __pud((unsigned long)pmdp | _KERNPG_TABLE));
-        }
-
-        pmdp = pmd_offset(pudp, va);
-        if (pmd_none(*pmdp) || !pmd_present(*pmdp)) {
-                ptep = (pte_t *)sh64_get_page();
-                set_pmd(pmdp, __pmd((unsigned long)ptep + _PAGE_TABLE));
-        }
-
-        prot = __pgprot(_PAGE_PRESENT | _PAGE_READ     | _PAGE_WRITE  |
-                        _PAGE_DIRTY   | _PAGE_ACCESSED | _PAGE_SHARED | flags);
-
-        pte = pfn_pte(pa >> PAGE_SHIFT, prot);
-        ptep = pte_offset_kernel(pmdp, va);
-
-        if (!pte_none(*ptep) &&
-            pte_val(*ptep) != pte_val(pte))
-                pte_ERROR(*ptep);
-
-        set_pte(ptep, pte);
-
-        flush_tlb_kernel_range(va, PAGE_SIZE);
-}
-
-static void shmedia_unmapioaddr(unsigned long vaddr)
-{
-        pgd_t *pgdp;
-        pud_t *pudp;
-        pmd_t *pmdp;
-        pte_t *ptep;
-
-        pgdp = pgd_offset_k(vaddr);
-        if (pgd_none(*pgdp) || pgd_bad(*pgdp))
-                return;
-
-        pudp = pud_offset(pgdp, vaddr);
-        if (pud_none(*pudp) || pud_bad(*pudp))
-                return;
-
-        pmdp = pmd_offset(pudp, vaddr);
-        if (pmd_none(*pmdp) || pmd_bad(*pmdp))
-                return;
-
-        ptep = pte_offset_kernel(pmdp, vaddr);
-
-        if (pte_none(*ptep) || !pte_present(*ptep))
-                return;
-
-        clear_page((void *)ptep);
-        pte_clear(&init_mm, vaddr, ptep);
-}
-
-void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
-                               unsigned long flags, void *caller)
-{
-        char name[14];
-
-        sprintf(name, "phys_%08x", (u32)offset);
-        return shmedia_alloc_io(offset, size, name, flags);
-}
-EXPORT_SYMBOL(__ioremap_caller);
-
-void __iounmap(void __iomem *virtual)
-{
-        unsigned long vaddr = (unsigned long)virtual & PAGE_MASK;
-        struct resource *res;
-        unsigned int psz;
-
-        res = shmedia_find_resource(&shmedia_iomap, vaddr);
-        if (!res) {
-                printk(KERN_ERR "%s: Failed to free 0x%08lx\n",
-                       __func__, vaddr);
-                return;
-        }
-
-        psz = (res->end - res->start + (PAGE_SIZE - 1)) / PAGE_SIZE;
-
-        shmedia_free_io(res);
-
-        if ((char *)res >= (char *)xresv &&
-            (char *)res <  (char *)&xresv[XNRES]) {
-                xres_free((struct xresource *)res);
-        } else {
-                kfree(res);
-        }
-}
-EXPORT_SYMBOL(__iounmap);
-
-static int
-ioremap_proc_info(char *buf, char **start, off_t fpos, int length, int *eof,
-                  void *data)
-{
-        char *p = buf, *e = buf + length;
-        struct resource *r;
-        const char *nm;
-
-        for (r = ((struct resource *)data)->child; r != NULL; r = r->sibling) {
-                if (p + 32 >= e)        /* Better than nothing */
-                        break;
-                nm = r->name;
-                if (nm == NULL)
-                        nm = "???";
-
-                p += sprintf(p, "%08lx-%08lx: %s\n",
-                             (unsigned long)r->start,
-                             (unsigned long)r->end, nm);
-        }
-
-        return p-buf;
-}
-
-static int __init register_proc_onchip(void)
-{
-        create_proc_read_entry("io_map", 0, 0, ioremap_proc_info,
-                               &shmedia_iomap);
-        return 0;
-}
-late_initcall(register_proc_onchip);
diff --git a/arch/sh/mm/ioremap_fixed.c b/arch/sh/mm/ioremap_fixed.c
new file mode 100644
index 000000000000..0b78b1e20ef1
--- /dev/null
+++ b/arch/sh/mm/ioremap_fixed.c
@@ -0,0 +1,128 @@
+/*
+ * Re-map IO memory to kernel address space so that we can access it.
+ *
+ * These functions should only be used when it is necessary to map a
+ * physical address space into the kernel address space before ioremap()
+ * can be used, e.g. early in boot before paging_init().
+ *
+ * Copyright (C) 2009  Matt Fleming
+ */
+
+#include <linux/vmalloc.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <linux/bootmem.h>
+#include <linux/proc_fs.h>
+#include <linux/slab.h>
+#include <asm/fixmap.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+#include <asm/addrspace.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/mmu.h>
+#include <asm/mmu_context.h>
+
+struct ioremap_map {
+        void __iomem *addr;
+        unsigned long size;
+        unsigned long fixmap_addr;
+};
+
+static struct ioremap_map ioremap_maps[FIX_N_IOREMAPS];
+
+void __init ioremap_fixed_init(void)
+{
+        struct ioremap_map *map;
+        int i;
+
+        for (i = 0; i < FIX_N_IOREMAPS; i++) {
+                map = &ioremap_maps[i];
+                map->fixmap_addr = __fix_to_virt(FIX_IOREMAP_BEGIN + i);
+        }
+}
+
+void __init __iomem *
+ioremap_fixed(resource_size_t phys_addr, unsigned long offset,
+              unsigned long size, pgprot_t prot)
+{
+        enum fixed_addresses idx0, idx;
+        struct ioremap_map *map;
+        unsigned int nrpages;
+        int i, slot;
+
+        slot = -1;
+        for (i = 0; i < FIX_N_IOREMAPS; i++) {
+                map = &ioremap_maps[i];
+                if (!map->addr) {
+                        map->size = size;
+                        slot = i;
+                        break;
+                }
+        }
+
+        if (slot < 0)
+                return NULL;
+
+        /*
+         * Mappings have to fit in the FIX_IOREMAP area.
+         */
+        nrpages = size >> PAGE_SHIFT;
+        if (nrpages > FIX_N_IOREMAPS)
+                return NULL;
+
+        /*
+         * Ok, go for it..
+         */
+        idx0 = FIX_IOREMAP_BEGIN + slot;
+        idx = idx0;
+        while (nrpages > 0) {
+                pgprot_val(prot) |= _PAGE_WIRED;
+                __set_fixmap(idx, phys_addr, prot);
+                phys_addr += PAGE_SIZE;
+                idx++;
+                --nrpages;
+        }
+
+        map->addr = (void __iomem *)(offset + map->fixmap_addr);
+        return map->addr;
+}
+
+int iounmap_fixed(void __iomem *addr)
+{
+        enum fixed_addresses idx;
+        struct ioremap_map *map;
+        unsigned int nrpages;
+        int i, slot;
+
+        slot = -1;
+        for (i = 0; i < FIX_N_IOREMAPS; i++) {
+                map = &ioremap_maps[i];
+                if (map->addr == addr) {
+                        slot = i;
+                        break;
+                }
+        }
+
+        /*
+         * If we don't match, it's not for us.
+         */
+        if (slot < 0)
+                return -EINVAL;
+
+        nrpages = map->size >> PAGE_SHIFT;
+
+        idx = FIX_IOREMAP_BEGIN + slot + nrpages - 1;
+        while (nrpages > 0) {
+                __clear_fixmap(idx, __pgprot(_PAGE_WIRED));
+                --idx;
+                --nrpages;
+        }
+
+        map->size = 0;
+        map->addr = NULL;
+
+        return 0;
+}
diff --git a/arch/sh/mm/nommu.c b/arch/sh/mm/nommu.c
index ac16c05917ef..7694f50c9034 100644
--- a/arch/sh/mm/nommu.c
+++ b/arch/sh/mm/nommu.c
@@ -94,3 +94,7 @@ void __init page_table_range_init(unsigned long start, unsigned long end,
 void __set_fixmap(enum fixed_addresses idx, unsigned long phys, pgprot_t prot)
 {
 }
+
+void pgtable_cache_init(void)
+{
+}
diff --git a/arch/sh/mm/pgtable.c b/arch/sh/mm/pgtable.c
new file mode 100644
index 000000000000..6f21fb1d8726
--- /dev/null
+++ b/arch/sh/mm/pgtable.c
@@ -0,0 +1,56 @@
+#include <linux/mm.h>
+
+#define PGALLOC_GFP GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO
+
+static struct kmem_cache *pgd_cachep;
+#if PAGETABLE_LEVELS > 2
+static struct kmem_cache *pmd_cachep;
+#endif
+
+void pgd_ctor(void *x)
+{
+        pgd_t *pgd = x;
+
+        memcpy(pgd + USER_PTRS_PER_PGD,
+               swapper_pg_dir + USER_PTRS_PER_PGD,
+               (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
+}
+
+void pgtable_cache_init(void)
+{
+        pgd_cachep = kmem_cache_create("pgd_cache",
+                                       PTRS_PER_PGD * (1<<PTE_MAGNITUDE),
+                                       PAGE_SIZE, SLAB_PANIC, pgd_ctor);
+#if PAGETABLE_LEVELS > 2
+        pmd_cachep = kmem_cache_create("pmd_cache",
+                                       PTRS_PER_PMD * (1<<PTE_MAGNITUDE),
+                                       PAGE_SIZE, SLAB_PANIC, NULL);
+#endif
+}
+
+pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return kmem_cache_alloc(pgd_cachep, PGALLOC_GFP);
+}
+
+void pgd_free(struct mm_struct *mm, pgd_t *pgd)
+{
+        kmem_cache_free(pgd_cachep, pgd);
+}
+
+#if PAGETABLE_LEVELS > 2
+void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        set_pud(pud, __pud((unsigned long)pmd));
+}
+
+pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+        return kmem_cache_alloc(pmd_cachep, PGALLOC_GFP);
+}
+
+void pmd_free(struct mm_struct *mm, pmd_t *pmd)
+{
+        kmem_cache_free(pmd_cachep, pmd);
+}
+#endif /* PAGETABLE_LEVELS > 2 */
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 280f6a166035..198bcff5e96f 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -3,11 +3,8 @@
  *
  * Privileged Space Mapping Buffer (PMB) Support.
  *
- * Copyright (C) 2005, 2006, 2007 Paul Mundt
- *
- * P1/P2 Section mapping definitions from map32.h, which was:
- *
- *      Copyright 2003 (c) Lineo Solutions,Inc.
+ * Copyright (C) 2005 - 2010  Paul Mundt
+ * Copyright (C) 2010  Matt Fleming
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
@@ -24,47 +21,67 @@
 #include <linux/fs.h>
 #include <linux/seq_file.h>
 #include <linux/err.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/rwlock.h>
+#include <asm/sizes.h>
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/pgtable.h>
+#include <asm/page.h>
 #include <asm/mmu.h>
-#include <asm/io.h>
 #include <asm/mmu_context.h>
 
-#define NR_PMB_ENTRIES  16
+struct pmb_entry;
+
+struct pmb_entry {
+        unsigned long vpn;
+        unsigned long ppn;
+        unsigned long flags;
+        unsigned long size;
 
-static void __pmb_unmap(struct pmb_entry *);
+        spinlock_t lock;
+
+        /*
+         * 0 .. NR_PMB_ENTRIES for specific entry selection, or
+         * PMB_NO_ENTRY to search for a free one
+         */
+        int entry;
 
+        /* Adjacent entry link for contiguous multi-entry mappings */
+        struct pmb_entry *link;
+};
+
+static void pmb_unmap_entry(struct pmb_entry *, int depth);
+
+static DEFINE_RWLOCK(pmb_rwlock);
 static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
-static unsigned long pmb_map;
+static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
 
-static inline unsigned long mk_pmb_entry(unsigned int entry)
+static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
 {
         return (entry & PMB_E_MASK) << PMB_E_SHIFT;
 }
 
-static inline unsigned long mk_pmb_addr(unsigned int entry)
+static __always_inline unsigned long mk_pmb_addr(unsigned int entry)
 {
         return mk_pmb_entry(entry) | PMB_ADDR;
 }
 
-static inline unsigned long mk_pmb_data(unsigned int entry)
+static __always_inline unsigned long mk_pmb_data(unsigned int entry)
 {
         return mk_pmb_entry(entry) | PMB_DATA;
 }
 
 static int pmb_alloc_entry(void)
 {
-        unsigned int pos;
-
-repeat:
-        pos = find_first_zero_bit(&pmb_map, NR_PMB_ENTRIES);
-
-        if (unlikely(pos > NR_PMB_ENTRIES))
-                return -ENOSPC;
+        int pos;
 
-        if (test_and_set_bit(pos, &pmb_map))
-                goto repeat;
+        pos = find_first_zero_bit(pmb_map, NR_PMB_ENTRIES);
+        if (pos >= 0 && pos < NR_PMB_ENTRIES)
+                __set_bit(pos, pmb_map);
+        else
+                pos = -ENOSPC;
 
         return pos;
 }
@@ -73,21 +90,34 @@ static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
                                    unsigned long flags, int entry)
 {
         struct pmb_entry *pmbe;
+        unsigned long irqflags;
+        void *ret = NULL;
         int pos;
 
+        write_lock_irqsave(&pmb_rwlock, irqflags);
+
         if (entry == PMB_NO_ENTRY) {
                 pos = pmb_alloc_entry();
-                if (pos < 0)
-                        return ERR_PTR(pos);
+                if (unlikely(pos < 0)) {
+                        ret = ERR_PTR(pos);
+                        goto out;
+                }
         } else {
-                if (test_bit(entry, &pmb_map))
-                        return ERR_PTR(-ENOSPC);
+                if (__test_and_set_bit(entry, pmb_map)) {
+                        ret = ERR_PTR(-ENOSPC);
+                        goto out;
+                }
+
                 pos = entry;
         }
 
+        write_unlock_irqrestore(&pmb_rwlock, irqflags);
+
         pmbe = &pmb_entry_list[pos];
-        if (!pmbe)
-                return ERR_PTR(-ENOMEM);
+
+        memset(pmbe, 0, sizeof(struct pmb_entry));
+
+        spin_lock_init(&pmbe->lock);
 
         pmbe->vpn       = vpn;
         pmbe->ppn       = ppn;
@@ -95,101 +125,113 @@ static struct pmb_entry *pmb_alloc(unsigned long vpn, unsigned long ppn,
         pmbe->entry     = pos;
 
         return pmbe;
+
+out:
+        write_unlock_irqrestore(&pmb_rwlock, irqflags);
+        return ret;
 }
 
 static void pmb_free(struct pmb_entry *pmbe)
 {
-        int pos = pmbe->entry;
-
-        pmbe->vpn       = 0;
-        pmbe->ppn       = 0;
-        pmbe->flags     = 0;
-        pmbe->entry     = 0;
+        __clear_bit(pmbe->entry, pmb_map);
 
-        clear_bit(pos, &pmb_map);
+        pmbe->entry     = PMB_NO_ENTRY;
+        pmbe->link      = NULL;
 }
 
 /*
- * Must be in P2 for __set_pmb_entry()
+ * Ensure that the PMB entries match our cache configuration.
+ *
+ * When we are in 32-bit address extended mode, CCR.CB becomes
+ * invalid, so care must be taken to manually adjust cacheable
+ * translations.
  */
-static void __set_pmb_entry(unsigned long vpn, unsigned long ppn,
-                            unsigned long flags, int pos)
+static __always_inline unsigned long pmb_cache_flags(void)
 {
-        ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos));
+        unsigned long flags = 0;
 
-#ifdef CONFIG_CACHE_WRITETHROUGH
-        /*
-         * When we are in 32-bit address extended mode, CCR.CB becomes
-         * invalid, so care must be taken to manually adjust cacheable
-         * translations.
-         */
-        if (likely(flags & PMB_C))
-                flags |= PMB_WT;
+#if defined(CONFIG_CACHE_WRITETHROUGH)
+        flags |= PMB_C | PMB_WT | PMB_UB;
+#elif defined(CONFIG_CACHE_WRITEBACK)
+        flags |= PMB_C;
 #endif
 
-        ctrl_outl(ppn | flags | PMB_V, mk_pmb_data(pos));
+        return flags;
 }
 
-static void __uses_jump_to_uncached set_pmb_entry(struct pmb_entry *pmbe)
+/*
+ * Must be run uncached.
+ */
+static void __set_pmb_entry(struct pmb_entry *pmbe)
 {
-        jump_to_uncached();
-        __set_pmb_entry(pmbe->vpn, pmbe->ppn, pmbe->flags, pmbe->entry);
-        back_to_cached();
+        writel_uncached(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
+        writel_uncached(pmbe->ppn | pmbe->flags | PMB_V,
+                        mk_pmb_data(pmbe->entry));
 }
 
-static void __uses_jump_to_uncached clear_pmb_entry(struct pmb_entry *pmbe)
+static void __clear_pmb_entry(struct pmb_entry *pmbe)
 {
-        unsigned int entry = pmbe->entry;
-        unsigned long addr;
+        unsigned long addr, data;
+        unsigned long addr_val, data_val;
 
-        if (unlikely(entry >= NR_PMB_ENTRIES))
-                return;
+        addr = mk_pmb_addr(pmbe->entry);
+        data = mk_pmb_data(pmbe->entry);
 
-        jump_to_uncached();
+        addr_val = __raw_readl(addr);
+        data_val = __raw_readl(data);
 
         /* Clear V-bit */
-        addr = mk_pmb_addr(entry);
-        ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr);
+        writel_uncached(addr_val & ~PMB_V, addr);
+        writel_uncached(data_val & ~PMB_V, data);
+}
 
-        addr = mk_pmb_data(entry);
-        ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr);
+static void set_pmb_entry(struct pmb_entry *pmbe)
+{
+        unsigned long flags;
 
-        back_to_cached();
+        spin_lock_irqsave(&pmbe->lock, flags);
+        __set_pmb_entry(pmbe);
+        spin_unlock_irqrestore(&pmbe->lock, flags);
 }
 
-
 static struct {
         unsigned long size;
         int flag;
 } pmb_sizes[] = {
-        { .size = 0x20000000, .flag = PMB_SZ_512M, },
-        { .size = 0x08000000, .flag = PMB_SZ_128M, },
-        { .size = 0x04000000, .flag = PMB_SZ_64M,  },
-        { .size = 0x01000000, .flag = PMB_SZ_16M,  },
+        { .size = SZ_512M, .flag = PMB_SZ_512M, },
+        { .size = SZ_128M, .flag = PMB_SZ_128M, },
+        { .size = SZ_64M,  .flag = PMB_SZ_64M,  },
+        { .size = SZ_16M,  .flag = PMB_SZ_16M,  },
 };
 
 long pmb_remap(unsigned long vaddr, unsigned long phys,
-               unsigned long size, unsigned long flags)
+               unsigned long size, pgprot_t prot)
 {
         struct pmb_entry *pmbp, *pmbe;
         unsigned long wanted;
         int pmb_flags, i;
         long err;
+        u64 flags;
+
+        flags = pgprot_val(prot);
+
+        pmb_flags = PMB_WT | PMB_UB;
 
         /* Convert typical pgprot value to the PMB equivalent */
         if (flags & _PAGE_CACHABLE) {
-                if (flags & _PAGE_WT)
-                        pmb_flags = PMB_WT;
-                else
-                        pmb_flags = PMB_C;
-        } else
-                pmb_flags = PMB_WT | PMB_UB;
+                pmb_flags |= PMB_C;
+
+                if ((flags & _PAGE_WT) == 0)
+                        pmb_flags &= ~(PMB_WT | PMB_UB);
+        }
 
         pmbp = NULL;
         wanted = size;
 
 again:
         for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
+                unsigned long flags;
+
                 if (size < pmb_sizes[i].size)
                         continue;
 
@@ -200,18 +242,25 @@ again:
                         goto out;
                 }
 
-                set_pmb_entry(pmbe);
+                spin_lock_irqsave(&pmbe->lock, flags);
+
+                __set_pmb_entry(pmbe);
 
                 phys    += pmb_sizes[i].size;
                 vaddr   += pmb_sizes[i].size;
                 size    -= pmb_sizes[i].size;
 
+                pmbe->size = pmb_sizes[i].size;
+
                 /*
                  * Link adjacent entries that span multiple PMB entries
                  * for easier tear-down.
                  */
-                if (likely(pmbp))
+                if (likely(pmbp)) {
+                        spin_lock(&pmbp->lock);
                         pmbp->link = pmbe;
+                        spin_unlock(&pmbp->lock);
+                }
 
                 pmbp = pmbe;
 
@@ -221,16 +270,17 @@ again:
                  * pmb_sizes[i].size again.
                  */
                 i--;
+
+                spin_unlock_irqrestore(&pmbe->lock, flags);
         }
 
-        if (size >= 0x1000000)
+        if (size >= SZ_16M)
                 goto again;
 
         return wanted - size;
 
 out:
-        if (pmbp)
-                __pmb_unmap(pmbp);
+        pmb_unmap_entry(pmbp, NR_PMB_ENTRIES);
 
         return err;
 }
@@ -240,24 +290,52 @@ void pmb_unmap(unsigned long addr)
         struct pmb_entry *pmbe = NULL;
         int i;
 
+        read_lock(&pmb_rwlock);
+
         for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
-                if (test_bit(i, &pmb_map)) {
+                if (test_bit(i, pmb_map)) {
                         pmbe = &pmb_entry_list[i];
                         if (pmbe->vpn == addr)
                                 break;
                 }
         }
 
-        if (unlikely(!pmbe))
-                return;
+        read_unlock(&pmb_rwlock);
 
-        __pmb_unmap(pmbe);
+        pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
 }
 
-static void __pmb_unmap(struct pmb_entry *pmbe)
+static bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
 {
-        BUG_ON(!test_bit(pmbe->entry, &pmb_map));
+        return (b->vpn == (a->vpn + a->size)) &&
+               (b->ppn == (a->ppn + a->size)) &&
+               (b->flags == a->flags);
+}
 
+static bool pmb_size_valid(unsigned long size)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
+                if (pmb_sizes[i].size == size)
+                        return true;
+
+        return false;
+}
+
+static int pmb_size_to_flags(unsigned long size)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
+                if (pmb_sizes[i].size == size)
+                        return pmb_sizes[i].flag;
+
+        return 0;
+}
+
+static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
+{
         do {
                 struct pmb_entry *pmblink = pmbe;
 
@@ -268,102 +346,312 @@ static void __pmb_unmap(struct pmb_entry *pmbe)
                  * this entry in pmb_alloc() (even if we haven't filled
                  * it yet).
                  *
-                 * Therefore, calling clear_pmb_entry() is safe as no
+                 * Therefore, calling __clear_pmb_entry() is safe as no
                  * other mapping can be using that slot.
                  */
-                clear_pmb_entry(pmbe);
+                __clear_pmb_entry(pmbe);
 
                 pmbe = pmblink->link;
 
                 pmb_free(pmblink);
-        } while (pmbe);
+        } while (pmbe && --depth);
+}
+
+static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
+{
+        unsigned long flags;
+
+        if (unlikely(!pmbe))
+                return;
+
+        write_lock_irqsave(&pmb_rwlock, flags);
+        __pmb_unmap_entry(pmbe, depth);
+        write_unlock_irqrestore(&pmb_rwlock, flags);
+}
+
+static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
+{
+        return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
 }
 
-#ifdef CONFIG_PMB
-int __uses_jump_to_uncached pmb_init(void)
+static void __init pmb_notify(void)
 {
-        unsigned int i;
-        long size, ret;
+        int i;
 
-        jump_to_uncached();
+        pr_info("PMB: boot mappings:\n");
+
+        read_lock(&pmb_rwlock);
+
+        for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
+                struct pmb_entry *pmbe;
+
+                if (!test_bit(i, pmb_map))
+                        continue;
+
+                pmbe = &pmb_entry_list[i];
+
+                pr_info("       0x%08lx -> 0x%08lx [ %4ldMB %2scached ]\n",
+                        pmbe->vpn >> PAGE_SHIFT, pmbe->ppn >> PAGE_SHIFT,
+                        pmbe->size >> 20, (pmbe->flags & PMB_C) ? "" : "un");
+        }
+
+        read_unlock(&pmb_rwlock);
+}
+
+/*
+ * Sync our software copy of the PMB mappings with those in hardware. The
+ * mappings in the hardware PMB were either set up by the bootloader or
+ * very early on by the kernel.
+ */
+static void __init pmb_synchronize(void)
+{
+        struct pmb_entry *pmbp = NULL;
+        int i, j;
 
         /*
-         * Insert PMB entries for the P1 and P2 areas so that, after
-         * we've switched the MMU to 32-bit mode, the semantics of P1
-         * and P2 are the same as in 29-bit mode, e.g.
+         * Run through the initial boot mappings, log the established
+         * ones, and blow away anything that falls outside of the valid
+         * PPN range. Specifically, we only care about existing mappings
+         * that impact the cached/uncached sections.
          *
-         *      P1 - provides a cached window onto physical memory
-         *      P2 - provides an uncached window onto physical memory
+         * Note that touching these can be a bit of a minefield; the boot
+         * loader can establish multi-page mappings with the same caching
+         * attributes, so we need to ensure that we aren't modifying a
+         * mapping that we're presently executing from, or may execute
+         * from in the case of straddling page boundaries.
+         *
+         * In the future we will have to tidy up after the boot loader by
+         * jumping between the cached and uncached mappings and tearing
+         * down alternating mappings while executing from the other.
          */
-        size = __MEMORY_START + __MEMORY_SIZE;
+        for (i = 0; i < NR_PMB_ENTRIES; i++) {
+                unsigned long addr, data;
+                unsigned long addr_val, data_val;
+                unsigned long ppn, vpn, flags;
+                unsigned long irqflags;
+                unsigned int size;
+                struct pmb_entry *pmbe;
 
-        ret = pmb_remap(P1SEG, 0x00000000, size, PMB_C);
-        BUG_ON(ret != size);
+                addr = mk_pmb_addr(i);
+                data = mk_pmb_data(i);
 
-        ret = pmb_remap(P2SEG, 0x00000000, size, PMB_WT | PMB_UB);
-        BUG_ON(ret != size);
+                addr_val = __raw_readl(addr);
+                data_val = __raw_readl(data);
 
-        ctrl_outl(0, PMB_IRMCR);
+                /*
+                 * Skip over any bogus entries
+                 */
+                if (!(data_val & PMB_V) || !(addr_val & PMB_V))
+                        continue;
 
-        /* PMB.SE and UB[7] */
-        ctrl_outl(PASCR_SE | (1 << 7), PMB_PASCR);
+                ppn = data_val & PMB_PFN_MASK;
+                vpn = addr_val & PMB_PFN_MASK;
 
-        /* Flush out the TLB */
-        i =  ctrl_inl(MMUCR);
-        i |= MMUCR_TI;
-        ctrl_outl(i, MMUCR);
+                /*
+                 * Only preserve in-range mappings.
+                 */
+                if (!pmb_ppn_in_range(ppn)) {
+                        /*
+                         * Invalidate anything out of bounds.
+                         */
+                        writel_uncached(addr_val & ~PMB_V, addr);
+                        writel_uncached(data_val & ~PMB_V, data);
+                        continue;
+                }
 
-        back_to_cached();
+                /*
+                 * Update the caching attributes if necessary
+                 */
+                if (data_val & PMB_C) {
+                        data_val &= ~PMB_CACHE_MASK;
+                        data_val |= pmb_cache_flags();
 
-        return 0;
+                        writel_uncached(data_val, data);
+                }
+
+                size = data_val & PMB_SZ_MASK;
+                flags = size | (data_val & PMB_CACHE_MASK);
+
+                pmbe = pmb_alloc(vpn, ppn, flags, i);
+                if (IS_ERR(pmbe)) {
+                        WARN_ON_ONCE(1);
+                        continue;
+                }
+
+                spin_lock_irqsave(&pmbe->lock, irqflags);
+
+                for (j = 0; j < ARRAY_SIZE(pmb_sizes); j++)
+                        if (pmb_sizes[j].flag == size)
+                                pmbe->size = pmb_sizes[j].size;
+
+                if (pmbp) {
+                        spin_lock(&pmbp->lock);
+
+                        /*
+                         * Compare the previous entry against the current one to
+                         * see if the entries span a contiguous mapping. If so,
+                         * setup the entry links accordingly. Compound mappings
+                         * are later coalesced.
+                         */
+                        if (pmb_can_merge(pmbp, pmbe))
+                                pmbp->link = pmbe;
+
+                        spin_unlock(&pmbp->lock);
+                }
+
+                pmbp = pmbe;
+
+                spin_unlock_irqrestore(&pmbe->lock, irqflags);
+        }
+}
+
+static void __init pmb_merge(struct pmb_entry *head)
+{
+        unsigned long span, newsize;
+        struct pmb_entry *tail;
+        int i = 1, depth = 0;
+
+        span = newsize = head->size;
+
+        tail = head->link;
+        while (tail) {
+                span += tail->size;
+
+                if (pmb_size_valid(span)) {
+                        newsize = span;
+                        depth = i;
+                }
+
+                /* This is the end of the line.. */
+                if (!tail->link)
+                        break;
+
+                tail = tail->link;
+                i++;
+        }
+
+        /*
+         * The merged page size must be valid.
+         */
+        if (!pmb_size_valid(newsize))
+                return;
+
+        head->flags &= ~PMB_SZ_MASK;
+        head->flags |= pmb_size_to_flags(newsize);
+
+        head->size = newsize;
+
+        __pmb_unmap_entry(head->link, depth);
+        __set_pmb_entry(head);
 }
-#else
-int __uses_jump_to_uncached pmb_init(void)
+
+static void __init pmb_coalesce(void)
 {
+        unsigned long flags;
         int i;
-        unsigned long addr, data;
 
-        jump_to_uncached();
+        write_lock_irqsave(&pmb_rwlock, flags);
 
-        for (i = 0; i < PMB_ENTRY_MAX; i++) {
+        for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
                 struct pmb_entry *pmbe;
-                unsigned long vpn, ppn, flags;
 
-                addr = PMB_DATA + (i << PMB_E_SHIFT);
-                data = ctrl_inl(addr);
-                if (!(data & PMB_V))
+                if (!test_bit(i, pmb_map))
                         continue;
 
-                if (data & PMB_C) {
-#if defined(CONFIG_CACHE_WRITETHROUGH)
-                        data |= PMB_WT;
-#elif defined(CONFIG_CACHE_WRITEBACK)
-                        data &= ~PMB_WT;
-#else
-                        data &= ~(PMB_C | PMB_WT);
-#endif
-                }
-                ctrl_outl(data, addr);
+                pmbe = &pmb_entry_list[i];
 
-                ppn = data & PMB_PFN_MASK;
+                /*
+                 * We're only interested in compound mappings
+                 */
+                if (!pmbe->link)
+                        continue;
 
-                flags = data & (PMB_C | PMB_WT | PMB_UB);
-                flags |= data & PMB_SZ_MASK;
+                /*
+                 * Nothing to do if it already uses the largest possible
+                 * page size.
+                 */
+                if (pmbe->size == SZ_512M)
+                        continue;
 
-                addr = PMB_ADDR + (i << PMB_E_SHIFT);
-                data = ctrl_inl(addr);
+                pmb_merge(pmbe);
+        }
 
-                vpn = data & PMB_PFN_MASK;
+        write_unlock_irqrestore(&pmb_rwlock, flags);
+}
 
-                pmbe = pmb_alloc(vpn, ppn, flags, i);
-                WARN_ON(IS_ERR(pmbe));
+#ifdef CONFIG_UNCACHED_MAPPING
+static void __init pmb_resize(void)
+{
+        int i;
+
+        /*
+         * If the uncached mapping was constructed by the kernel, it will
+         * already be a reasonable size.
+         */
+        if (uncached_size == SZ_16M)
+                return;
+
+        read_lock(&pmb_rwlock);
+
+        for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
+                struct pmb_entry *pmbe;
+                unsigned long flags;
+
+                if (!test_bit(i, pmb_map))
+                        continue;
+
+                pmbe = &pmb_entry_list[i];
+
+                if (pmbe->vpn != uncached_start)
+                        continue;
+
+                /*
+                 * Found it, now resize it.
+                 */
+                spin_lock_irqsave(&pmbe->lock, flags);
+
+                pmbe->size = SZ_16M;
+                pmbe->flags &= ~PMB_SZ_MASK;
+                pmbe->flags |= pmb_size_to_flags(pmbe->size);
+
+                uncached_resize(pmbe->size);
+
+                __set_pmb_entry(pmbe);
+
+                spin_unlock_irqrestore(&pmbe->lock, flags);
         }
 
-        back_to_cached();
+        read_lock(&pmb_rwlock);
+}
+#endif
+
+void __init pmb_init(void)
+{
+        /* Synchronize software state */
+        pmb_synchronize();
 
-        return 0;
+        /* Attempt to combine compound mappings */
+        pmb_coalesce();
+
+#ifdef CONFIG_UNCACHED_MAPPING
+        /* Resize initial mappings, if necessary */
+        pmb_resize();
+#endif
+
+        /* Log them */
+        pmb_notify();
+
+        writel_uncached(0, PMB_IRMCR);
+
+        /* Flush out the TLB */
+        __raw_writel(__raw_readl(MMUCR) | MMUCR_TI, MMUCR);
+        ctrl_barrier();
+}
+
+bool __in_29bit_mode(void)
+{
+        return (__raw_readl(PMB_PASCR) & PASCR_SE) == 0;
 }
-#endif /* CONFIG_PMB */
 
 static int pmb_seq_show(struct seq_file *file, void *iter)
 {
@@ -378,8 +666,8 @@ static int pmb_seq_show(struct seq_file *file, void *iter)
                 unsigned int size;
                 char *sz_str = NULL;
 
-                addr = ctrl_inl(mk_pmb_addr(i));
-                data = ctrl_inl(mk_pmb_data(i));
+                addr = __raw_readl(mk_pmb_addr(i));
+                data = __raw_readl(mk_pmb_data(i));
 
                 size = data & PMB_SZ_MASK;
                 sz_str = (size == PMB_SZ_16M)  ? " 16MB":
@@ -437,14 +725,21 @@ static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
         if (state.event == PM_EVENT_ON &&
             prev_state.event == PM_EVENT_FREEZE) {
                 struct pmb_entry *pmbe;
+
+                read_lock(&pmb_rwlock);
+
                 for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
-                        if (test_bit(i, &pmb_map)) {
+                        if (test_bit(i, pmb_map)) {
                                 pmbe = &pmb_entry_list[i];
                                 set_pmb_entry(pmbe);
                         }
                 }
+
+                read_unlock(&pmb_rwlock);
         }
+
         prev_state = state;
+
         return 0;
 }
 
@@ -462,6 +757,5 @@ static int __init pmb_sysdev_init(void)
 {
         return sysdev_driver_register(&cpu_sysdev_class, &pmb_sysdev_driver);
 }
-
 subsys_initcall(pmb_sysdev_init);
 #endif
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index 409b7c2b4b9d..32dc674c550c 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -68,8 +68,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
  * in extended mode, the legacy 8-bit ASID field in address array 1 has
  * undefined behaviour.
  */
-void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
-                                                 unsigned long page)
+void local_flush_tlb_one(unsigned long asid, unsigned long page)
 {
         jump_to_uncached();
         __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index ace8e6d2f59d..4f5f7cbdd508 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -41,14 +41,14 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 
         /* Set PTEH register */
         vpn = (address & MMU_VPN_MASK) | get_asid();
-        ctrl_outl(vpn, MMU_PTEH);
+        __raw_writel(vpn, MMU_PTEH);
 
         pteval = pte_val(pte);
 
         /* Set PTEL register */
         pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
         /* conveniently, we want all the software flags to be 0 anyway */
-        ctrl_outl(pteval, MMU_PTEL);
+        __raw_writel(pteval, MMU_PTEL);
 
         /* Load the TLB */
         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
@@ -75,5 +75,5 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
         }
 
         for (i = 0; i < ways; i++)
-                ctrl_outl(data, addr + (i << 8));
+                __raw_writel(data, addr + (i << 8));
 }
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 8cf550e2570f..ccac77f504a8 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -29,7 +29,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 
         /* Set PTEH register */
         vpn = (address & MMU_VPN_MASK) | get_asid();
-        ctrl_outl(vpn, MMU_PTEH);
+        __raw_writel(vpn, MMU_PTEH);
 
         pteval = pte.pte_low;
 
@@ -41,13 +41,13 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
          * the protection bits (with the exception of the compat-mode SZ
          * and PR bits, which are cleared) being written out in PTEL.
          */
-        ctrl_outl(pte.pte_high, MMU_PTEA);
+        __raw_writel(pte.pte_high, MMU_PTEA);
 #else
         if (cpu_data->flags & CPU_HAS_PTEA) {
                 /* The last 3 bits and the first one of pteval contains
                  * the PTEA timing control and space attribute bits
                  */
-                ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA);
+                __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
         }
 #endif
 
@@ -57,15 +57,14 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
         pteval |= _PAGE_WT;
 #endif
         /* conveniently, we want all the software flags to be 0 anyway */
-        ctrl_outl(pteval, MMU_PTEL);
+        __raw_writel(pteval, MMU_PTEL);
 
         /* Load the TLB */
         asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
         local_irq_restore(flags);
 }
 
-void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
-                                                 unsigned long page)
+void local_flush_tlb_one(unsigned long asid, unsigned long page)
 {
         unsigned long addr, data;
 
@@ -78,6 +77,6 @@ void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid,
         addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
         data = page | asid; /* VALID bit is off */
         jump_to_uncached();
-        ctrl_outl(data, addr);
+        __raw_writel(data, addr);
         back_to_cached();
 }
diff --git a/arch/sh/mm/tlb-sh5.c b/arch/sh/mm/tlb-sh5.c
index fdb64e41ec50..f27dbe1c1599 100644
--- a/arch/sh/mm/tlb-sh5.c
+++ b/arch/sh/mm/tlb-sh5.c
@@ -143,3 +143,42 @@ void sh64_setup_tlb_slot(unsigned long long config_addr, unsigned long eaddr,
  */
 void sh64_teardown_tlb_slot(unsigned long long config_addr)
         __attribute__ ((alias("__flush_tlb_slot")));
+
+static int dtlb_entry;
+static unsigned long long dtlb_entries[64];
+
+void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+        unsigned long long entry;
+        unsigned long paddr, flags;
+
+        BUG_ON(dtlb_entry == ARRAY_SIZE(dtlb_entries));
+
+        local_irq_save(flags);
+
+        entry = sh64_get_wired_dtlb_entry();
+        dtlb_entries[dtlb_entry++] = entry;
+
+        paddr = pte_val(pte) & _PAGE_FLAGS_HARDWARE_MASK;
+        paddr &= ~PAGE_MASK;
+
+        sh64_setup_tlb_slot(entry, addr, get_asid(), paddr);
+
+        local_irq_restore(flags);
+}
+
+void tlb_unwire_entry(void)
+{
+        unsigned long long entry;
+        unsigned long flags;
+
+        BUG_ON(!dtlb_entry);
+
+        local_irq_save(flags);
+        entry = dtlb_entries[dtlb_entry--];
+
+        sh64_teardown_tlb_slot(entry);
+        sh64_put_wired_dtlb_entry(entry);
+
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlb-urb.c b/arch/sh/mm/tlb-urb.c
new file mode 100644
index 000000000000..bb5b9098956d
--- /dev/null
+++ b/arch/sh/mm/tlb-urb.c
@@ -0,0 +1,81 @@
+/*
+ * arch/sh/mm/tlb-urb.c
+ *
+ * TLB entry wiring helpers for URB-equipped parts.
+ *
+ * Copyright (C) 2010  Matt Fleming
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/mm.h>
+#include <linux/io.h>
+#include <asm/tlb.h>
+#include <asm/mmu_context.h>
+
+/*
+ * Load the entry for 'addr' into the TLB and wire the entry.
+ */
+void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+{
+        unsigned long status, flags;
+        int urb;
+
+        local_irq_save(flags);
+
+        /* Load the entry into the TLB */
+        __update_tlb(vma, addr, pte);
+
+        /* ... and wire it up. */
+        status = __raw_readl(MMUCR);
+        urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
+        status &= ~MMUCR_URB;
+
+        /*
+         * Make sure we're not trying to wire the last TLB entry slot.
+         */
+        BUG_ON(!--urb);
+
+        urb = urb % MMUCR_URB_NENTRIES;
+
+        status |= (urb << MMUCR_URB_SHIFT);
+        __raw_writel(status, MMUCR);
+        ctrl_barrier();
+
+        local_irq_restore(flags);
+}
+
+/*
+ * Unwire the last wired TLB entry.
+ *
+ * It should also be noted that it is not possible to wire and unwire
+ * TLB entries in an arbitrary order. If you wire TLB entry N, followed
+ * by entry N+1, you must unwire entry N+1 first, then entry N. In this
+ * respect, it works like a stack or LIFO queue.
+ */
+void tlb_unwire_entry(void)
+{
+        unsigned long status, flags;
+        int urb;
+
+        local_irq_save(flags);
+
+        status = __raw_readl(MMUCR);
+        urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
+        status &= ~MMUCR_URB;
+
+        /*
+         * Make sure we're not trying to unwire a TLB entry when none
+         * have been wired.
+         */
+        BUG_ON(urb++ == MMUCR_URB_NENTRIES);
+
+        urb = urb % MMUCR_URB_NENTRIES;
+
+        status |= (urb << MMUCR_URB_SHIFT);
+        __raw_writel(status, MMUCR);
+        ctrl_barrier();
+
+        local_irq_restore(flags);
+}
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 6f45c1f8a7fe..004bb3f25b5f 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -132,9 +132,9 @@ void local_flush_tlb_all(void)
          *      It's same position, bit #2.
          */
         local_irq_save(flags);
-        status = ctrl_inl(MMUCR);
+        status = __raw_readl(MMUCR);
         status |= 0x04;
-        ctrl_outl(status, MMUCR);
+        __raw_writel(status, MMUCR);
         ctrl_barrier();
         local_irq_restore(flags);
 }
diff --git a/arch/sh/mm/tlbflush_64.c b/arch/sh/mm/tlbflush_64.c
index de0b0e881823..706da1d3a67a 100644
--- a/arch/sh/mm/tlbflush_64.c
+++ b/arch/sh/mm/tlbflush_64.c
@@ -36,7 +36,7 @@ extern void die(const char *,struct pt_regs *,long);
 
 static inline void print_prots(pgprot_t prot)
 {
-        printk("prot is 0x%08lx\n",pgprot_val(prot));
+        printk("prot is 0x%016llx\n",pgprot_val(prot));
 
         printk("%s %s %s %s %s\n",PPROT(_PAGE_SHARED),PPROT(_PAGE_READ),
                PPROT(_PAGE_EXECUTE),PPROT(_PAGE_WRITE),PPROT(_PAGE_USER));
diff --git a/arch/sh/mm/uncached.c b/arch/sh/mm/uncached.c
new file mode 100644
index 000000000000..cf20a5c5136a
--- /dev/null
+++ b/arch/sh/mm/uncached.c
@@ -0,0 +1,34 @@
+#include <linux/init.h>
+#include <asm/sizes.h>
+#include <asm/page.h>
+
+/*
+ * This is the offset of the uncached section from its cached alias.
+ *
+ * Legacy platforms handle trivial transitions between cached and
+ * uncached segments by making use of the 1:1 mapping relationship in
+ * 512MB lowmem, others via a special uncached mapping.
+ *
+ * Default value only valid in 29 bit mode, in 32bit mode this will be
+ * updated by the early PMB initialization code.
+ */
+unsigned long cached_to_uncached = SZ_512M;
+unsigned long uncached_size = SZ_512M;
+unsigned long uncached_start, uncached_end;
+
+int virt_addr_uncached(unsigned long kaddr)
+{
+        return (kaddr >= uncached_start) && (kaddr < uncached_end);
+}
+
+void __init uncached_init(void)
+{
+        uncached_start = memory_end;
+        uncached_end = uncached_start + uncached_size;
+}
+
+void __init uncached_resize(unsigned long size)
+{
+        uncached_size = size;
+        uncached_end = uncached_start + uncached_size;
+}
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 6639b25d8d57..b25aa554ee5e 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -32,6 +32,7 @@ DREAMCAST		SH_DREAMCAST
 SNAPGEAR                SH_SECUREEDGE5410
 EDOSK7705               SH_EDOSK7705
 EDOSK7760               SH_EDOSK7760
+SDK7786                 SH_SDK7786
 SH4202_MICRODEV         SH_SH4202_MICRODEV
 SH03                    SH_SH03
 LANDISK                 SH_LANDISK
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index e0cabe790ec1..77f906d8cc21 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -330,9 +330,9 @@ BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
 #define FAULT_CODE_WRITE    0x2
 #define FAULT_CODE_USER     0x4
 
-BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
+BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t *)
 
-#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
+#define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep)
 
 BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
     unsigned long, unsigned int)
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index f3cb790fa2ae..f5b5fa76c02d 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -706,7 +706,7 @@ extern unsigned long find_ecache_flush_span(unsigned long size);
 #define mmu_unlockarea(vaddr, len)              do { } while(0)
 
 struct vm_area_struct;
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 /* Encode and de-code a swap entry */
 #define __swp_type(entry)       (((entry).val >> PAGE_SHIFT) & 0xffUL)
diff --git a/arch/sparc/include/asm/stat.h b/arch/sparc/include/asm/stat.h
index 55db5eca08e2..39327d6a57eb 100644
--- a/arch/sparc/include/asm/stat.h
+++ b/arch/sparc/include/asm/stat.h
@@ -53,8 +53,8 @@ struct stat {
         ino_t           st_ino;
         mode_t          st_mode;
         short           st_nlink;
-        uid_t           st_uid;
-        gid_t           st_gid;
+        uid16_t         st_uid;
+        gid16_t         st_gid;
         unsigned short  st_rdev;
         off_t           st_size;
         time_t          st_atime;
diff --git a/arch/sparc/include/asm/syscall.h b/arch/sparc/include/asm/syscall.h
index 7486c605e23c..025a02ad2e31 100644
--- a/arch/sparc/include/asm/syscall.h
+++ b/arch/sparc/include/asm/syscall.h
@@ -5,6 +5,13 @@
 #include <linux/sched.h>
 #include <asm/ptrace.h>
 
+/*
+ * The syscall table always contains 32 bit pointers since we know that the
+ * address of the function to be called is (way) below 4GB.  So the "int"
+ * type here is what we want [need] for both 32 bit and 64 bit systems.
+ */
+extern const unsigned int sys_call_table[];
+
 /* The system call number is given by the user in %g1 */
 static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
diff --git a/arch/sparc/kernel/devices.c b/arch/sparc/kernel/devices.c
index b171ae8de90d..b062de9424a4 100644
--- a/arch/sparc/kernel/devices.c
+++ b/arch/sparc/kernel/devices.c
@@ -59,7 +59,7 @@ static int __cpu_find_by(int (*compare)(int, int, void *), void *compare_arg,
 
         cur_inst = 0;
         for_each_node_by_type(dp, "cpu") {
-                int err = check_cpu_node(dp->node, &cur_inst,
+                int err = check_cpu_node(dp->phandle, &cur_inst,
                                          compare, compare_arg,
                                          prom_node, mid);
                 if (!err) {
diff --git a/arch/sparc/kernel/ftrace.c b/arch/sparc/kernel/ftrace.c
index 29973daa9930..9103a56b39e8 100644
--- a/arch/sparc/kernel/ftrace.c
+++ b/arch/sparc/kernel/ftrace.c
@@ -91,14 +91,3 @@ int __init ftrace_dyn_arch_init(void *data)
         return 0;
 }
 #endif
-
-#ifdef CONFIG_FTRACE_SYSCALLS
-
-extern unsigned int sys_call_table[];
-
-unsigned long __init arch_syscall_addr(int nr)
-{
-        return (unsigned long)sys_call_table[nr];
-}
-
-#endif
diff --git a/arch/sparc/kernel/kstack.h b/arch/sparc/kernel/kstack.h
index 4248d969272f..5247283d1c03 100644
--- a/arch/sparc/kernel/kstack.h
+++ b/arch/sparc/kernel/kstack.h
@@ -11,6 +11,10 @@ static inline bool kstack_valid(struct thread_info *tp, unsigned long sp)
 {
         unsigned long base = (unsigned long) tp;
 
+        /* Stack pointer must be 16-byte aligned.  */
+        if (sp & (16UL - 1))
+                return false;
+
         if (sp >= (base + sizeof(struct thread_info)) &&
             sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf)))
                 return true;
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index 4c26eb59e742..da527b33ebc7 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -105,7 +105,7 @@ static unsigned long of_bus_sbus_get_flags(const u32 *addr, unsigned long flags)
 
 static int of_bus_ambapp_match(struct device_node *np)
 {
-        return !strcmp(np->name, "ambapp");
+        return !strcmp(np->type, "ambapp");
 }
 
 static void of_bus_ambapp_count_cells(struct device_node *child,
@@ -433,7 +433,7 @@ build_resources:
         if (!parent)
                 dev_set_name(&op->dev, "root");
         else
-                dev_set_name(&op->dev, "%08x", dp->node);
+                dev_set_name(&op->dev, "%08x", dp->phandle);
 
         if (of_device_register(op)) {
                 printk("%s: Could not register of device.\n",
diff --git a/arch/sparc/kernel/of_device_64.c b/arch/sparc/kernel/of_device_64.c
index 0a6f2d1798d1..b3d4cb5d21b3 100644
--- a/arch/sparc/kernel/of_device_64.c
+++ b/arch/sparc/kernel/of_device_64.c
@@ -676,7 +676,7 @@ static struct of_device * __init scan_one_device(struct device_node *dp,
         if (!parent)
                 dev_set_name(&op->dev, "root");
         else
-                dev_set_name(&op->dev, "%08x", dp->node);
+                dev_set_name(&op->dev, "%08x", dp->phandle);
 
         if (of_device_register(op)) {
                 printk("%s: Could not register of device.\n",
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 539e83f8e087..37b66c60abe3 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -247,6 +247,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
                                          struct pci_bus *bus, int devfn)
 {
         struct dev_archdata *sd;
+        struct pci_slot *slot;
         struct of_device *op;
         struct pci_dev *dev;
         const char *type;
@@ -286,6 +287,11 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
         dev->dev.bus = &pci_bus_type;
         dev->devfn = devfn;
         dev->multifunction = 0;         /* maybe a lie? */
+        set_pcie_port_type(dev);
+
+        list_for_each_entry(slot, &dev->bus->slots, list)
+                if (PCI_SLOT(dev->devfn) == slot->number)
+                        dev->slot = slot;
 
         dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
         dev->device = of_getintprop_default(node, "device-id", 0xffff);
@@ -322,6 +328,7 @@ static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
 
         dev->current_state = 4;         /* unknown power state */
         dev->error_state = pci_channel_io_normal;
+        dev->dma_mask = 0xffffffff;
 
         if (!strcmp(node->name, "pci")) {
                 /* a PCI-PCI bridge */
@@ -715,9 +722,10 @@ void pcibios_update_irq(struct pci_dev *pdev, int irq)
 {
 }
 
-void pcibios_align_resource(void *data, struct resource *res,
-                            resource_size_t size, resource_size_t align)
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
 {
+        return res->start;
 }
 
 int pcibios_enable_device(struct pci_dev *dev, int mask)
diff --git a/arch/sparc/kernel/pcic.c b/arch/sparc/kernel/pcic.c
index 4e2724ec2bb6..75e88c00bca3 100644
--- a/arch/sparc/kernel/pcic.c
+++ b/arch/sparc/kernel/pcic.c
@@ -768,9 +768,10 @@ char * __devinit pcibios_setup(char *str)
         return str;
 }
 
-void pcibios_align_resource(void *data, struct resource *res,
-                            resource_size_t size, resource_size_t align)
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
 {
+        return res->start;
 }
 
 int pcibios_enable_device(struct pci_dev *pdev, int mask)
diff --git a/arch/sparc/kernel/perf_event.c b/arch/sparc/kernel/perf_event.c
index e856456ec02f..9f2b2bac8b2b 100644
--- a/arch/sparc/kernel/perf_event.c
+++ b/arch/sparc/kernel/perf_event.c
@@ -980,10 +980,10 @@ static int collect_events(struct perf_event *group, int max_count,
         return n;
 }
 
-static void event_sched_in(struct perf_event *event, int cpu)
+static void event_sched_in(struct perf_event *event)
 {
         event->state = PERF_EVENT_STATE_ACTIVE;
-        event->oncpu = cpu;
+        event->oncpu = smp_processor_id();
         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
         if (is_software_event(event))
                 event->pmu->enable(event);
@@ -991,7 +991,7 @@ static void event_sched_in(struct perf_event *event, int cpu)
 
 int hw_perf_group_sched_in(struct perf_event *group_leader,
                            struct perf_cpu_context *cpuctx,
-                           struct perf_event_context *ctx, int cpu)
+                           struct perf_event_context *ctx)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct perf_event *sub;
@@ -1015,10 +1015,10 @@ int hw_perf_group_sched_in(struct perf_event *group_leader,
 
         cpuctx->active_oncpu += n;
         n = 1;
-        event_sched_in(group_leader, cpu);
+        event_sched_in(group_leader);
         list_for_each_entry(sub, &group_leader->sibling_list, group_entry) {
                 if (sub->state != PERF_EVENT_STATE_OFF) {
-                        event_sched_in(sub, cpu);
+                        event_sched_in(sub);
                         n++;
                 }
         }
diff --git a/arch/sparc/kernel/prom.h b/arch/sparc/kernel/prom.h
index 453397fe5e14..a8591ef2636d 100644
--- a/arch/sparc/kernel/prom.h
+++ b/arch/sparc/kernel/prom.h
@@ -4,9 +4,6 @@
 #include <linux/spinlock.h>
 #include <asm/prom.h>
 
-extern struct device_node *allnodes;    /* temporary while merging */
-extern rwlock_t devtree_lock;   /* temporary while merging */
-
 extern void * prom_early_alloc(unsigned long size);
 extern void irq_trans_init(struct device_node *dp);
 
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index d80a65d9e893..57ac9e28be0c 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -37,18 +37,6 @@ EXPORT_SYMBOL(of_console_path);
 char *of_console_options;
 EXPORT_SYMBOL(of_console_options);
 
-struct device_node *of_find_node_by_phandle(phandle handle)
-{
-        struct device_node *np;
-
-        for (np = allnodes; np; np = np->allnext)
-                if (np->node == handle)
-                        break;
-
-        return np;
-}
-EXPORT_SYMBOL(of_find_node_by_phandle);
-
 int of_getintprop_default(struct device_node *np, const char *name, int def)
 {
         struct property *prop;
@@ -89,7 +77,7 @@ int of_set_property(struct device_node *dp, const char *name, void *val, int len
                         void *old_val = prop->value;
                         int ret;
 
-                        ret = prom_setprop(dp->node, name, val, len);
+                        ret = prom_setprop(dp->phandle, name, val, len);
 
                         err = -EINVAL;
                         if (ret >= 0) {
@@ -236,7 +224,7 @@ static struct device_node * __init prom_create_node(phandle node,
 
         dp->name = get_one_property(node, "name");
         dp->type = get_one_property(node, "device_type");
-        dp->node = node;
+        dp->phandle = node;
 
         dp->properties = build_prop_list(node);
 
@@ -313,7 +301,7 @@ void __init prom_build_devicetree(void)
 
         nextp = &allnodes->allnext;
         allnodes->child = prom_build_tree(allnodes,
-                                          prom_getchild(allnodes->node),
+                                          prom_getchild(allnodes->phandle),
                                           &nextp);
         of_console_init();
 
diff --git a/arch/sparc/kernel/smp_64.c b/arch/sparc/kernel/smp_64.c
index aa36223497b9..eb14844a0021 100644
--- a/arch/sparc/kernel/smp_64.c
+++ b/arch/sparc/kernel/smp_64.c
@@ -370,7 +370,7 @@ static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
         } else {
                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 
-                prom_startcpu(dp->node, entry, cookie);
+                prom_startcpu(dp->phandle, entry, cookie);
         }
 
         for (timeout = 0; timeout < 50000; timeout++) {
diff --git a/arch/sparc/kernel/tsb.S b/arch/sparc/kernel/tsb.S
index 8c91d9b29a2f..db15d123f054 100644
--- a/arch/sparc/kernel/tsb.S
+++ b/arch/sparc/kernel/tsb.S
@@ -191,10 +191,12 @@ tsb_dtlb_load:
 
 tsb_itlb_load:
         /* Executable bit must be set.  */
-661:    andcc           %g5, _PAGE_EXEC_4U, %g0
-        .section        .sun4v_1insn_patch, "ax"
+661:    sethi           %hi(_PAGE_EXEC_4U), %g4
+        andcc           %g5, %g4, %g0
+        .section        .sun4v_2insn_patch, "ax"
         .word           661b
         andcc           %g5, _PAGE_EXEC_4V, %g0
+        nop
         .previous
 
         be,pn           %xcc, tsb_do_fault
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index a3413acb8f12..3fa09ba3845f 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -378,7 +378,7 @@ asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write,
                                unsigned long address)
 {
         extern void sun4c_update_mmu_cache(struct vm_area_struct *,
-                                           unsigned long,pte_t);
+                                           unsigned long,pte_t *);
         extern pte_t *sun4c_pte_offset_kernel(pmd_t *,unsigned long);
         struct task_struct *tsk = current;
         struct mm_struct *mm = tsk->mm;
@@ -455,7 +455,7 @@ asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write,
                  *       on the CPU and doing a shrink_mmap() on this vma.
                  */
                 sun4c_update_mmu_cache (find_vma(current->mm, address), address,
-                                        *ptep);
+                                        ptep);
         else
                 do_sparc_fault(regs, text_fault, write, address);
 }
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 1886d37d411b..9245a822a2f1 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -289,12 +289,13 @@ static void flush_dcache(unsigned long pfn)
         }
 }
 
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
         struct mm_struct *mm;
         struct tsb *tsb;
         unsigned long tag, flags;
         unsigned long tsb_index, tsb_hash_shift;
+        pte_t pte = *ptep;
 
         if (tlb_type != hypervisor) {
                 unsigned long pfn = pte_pfn(pte);
diff --git a/arch/sparc/mm/nosun4c.c b/arch/sparc/mm/nosun4c.c
index 196263f895b7..4e62c27147c4 100644
--- a/arch/sparc/mm/nosun4c.c
+++ b/arch/sparc/mm/nosun4c.c
@@ -62,7 +62,7 @@ pte_t *sun4c_pte_offset_kernel(pmd_t *dir, unsigned long address)
         return NULL;
 }
 
-void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 367321a030dd..df49b200ca4c 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -694,7 +694,7 @@ extern void tsunami_setup_blockops(void);
  * The following code is a deadwood that may be necessary when
  * we start to make precise page flushes again. --zaitcev
  */
-static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
+static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
 {
 #if 0
         static unsigned long last;
@@ -703,10 +703,10 @@ static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long ad
 
         if (address == last) {
                 val = srmmu_hwprobe(address);
-                if (val != 0 && pte_val(pte) != val) {
+                if (val != 0 && pte_val(*ptep) != val) {
                         printk("swift_update_mmu_cache: "
                             "addr %lx put %08x probed %08x from %p\n",
-                            address, pte_val(pte), val,
+                            address, pte_val(*ptep), val,
                             __builtin_return_address(0));
                         srmmu_flush_whole_tlb();
                 }
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
index a89baf0d875a..18652534b91a 100644
--- a/arch/sparc/mm/sun4c.c
+++ b/arch/sparc/mm/sun4c.c
@@ -1887,7 +1887,7 @@ static void sun4c_check_pgt_cache(int low, int high)
 /* An experiment, turn off by default for now... -DaveM */
 #define SUN4C_PRELOAD_PSEG
 
-void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
         unsigned long flags;
         int pseg;
@@ -1929,7 +1929,7 @@ void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, p
                         start += PAGE_SIZE;
                 }
 #ifndef SUN4C_PRELOAD_PSEG
-                sun4c_put_pte(address, pte_val(pte));
+                sun4c_put_pte(address, pte_val(*ptep));
 #endif
                 local_irq_restore(flags);
                 return;
@@ -1940,7 +1940,7 @@ void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, p
                 add_lru(entry);
         }
 
-        sun4c_put_pte(address, pte_val(pte));
+        sun4c_put_pte(address, pte_val(*ptep));
         local_irq_restore(flags);
 }
 
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index 5ff554677f40..c1ff6903b622 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -747,7 +747,7 @@ static int ubd_open_dev(struct ubd *ubd_dev)
         ubd_dev->fd = fd;
 
         if(ubd_dev->cow.file != NULL){
-                blk_queue_max_sectors(ubd_dev->queue, 8 * sizeof(long));
+                blk_queue_max_hw_sectors(ubd_dev->queue, 8 * sizeof(long));
 
                 err = -ENOMEM;
                 ubd_dev->cow.bitmap = vmalloc(ubd_dev->cow.bitmap_len);
@@ -849,7 +849,7 @@ static int ubd_add(int n, char **error_out)
         }
         ubd_dev->queue->queuedata = ubd_dev;
 
-        blk_queue_max_hw_segments(ubd_dev->queue, MAX_SG);
+        blk_queue_max_segments(ubd_dev->queue, MAX_SG);
         err = ubd_disk_register(UBD_MAJOR, ubd_dev->size, n, &ubd_gendisk[n]);
         if(err){
                 *error_out = "Failed to register device";
diff --git a/arch/um/include/asm/pgtable.h b/arch/um/include/asm/pgtable.h
index 9ce3f165111a..a9f7251b4a8d 100644
--- a/arch/um/include/asm/pgtable.h
+++ b/arch/um/include/asm/pgtable.h
@@ -345,7 +345,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 struct mm_struct;
 extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
 
-#define update_mmu_cache(vma,address,pte) do ; while (0)
+#define update_mmu_cache(vma,address,ptep) do ; while (0)
 
 /* Encode and de-code a swap entry */
 #define __swp_type(x)                   (((x).val >> 4) & 0x3f)
diff --git a/arch/um/sys-x86_64/Makefile b/arch/um/sys-x86_64/Makefile
index 2201e9c20e4a..c1ea9eb04466 100644
--- a/arch/um/sys-x86_64/Makefile
+++ b/arch/um/sys-x86_64/Makefile
@@ -8,7 +8,8 @@ obj-y = bug.o bugs.o delay.o fault.o ldt.o mem.o ptrace.o ptrace_user.o \
         setjmp.o signal.o stub.o stub_segv.o syscalls.o syscall_table.o \
         sysrq.o ksyms.o tls.o
 
-subarch-obj-y = lib/csum-partial_64.o lib/memcpy_64.o lib/thunk_64.o
+subarch-obj-y = lib/csum-partial_64.o lib/memcpy_64.o lib/thunk_64.o \
+                lib/rwsem_64.o
 subarch-obj-$(CONFIG_MODULES) += kernel/module.o
 
 ldt-y = ../sys-i386/ldt.o
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index eb4092568f9e..0896008f7509 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -45,6 +45,7 @@ config X86
         select HAVE_GENERIC_DMA_COHERENT if X86_32
         select HAVE_EFFICIENT_UNALIGNED_ACCESS
         select USER_STACKTRACE_SUPPORT
+        select HAVE_REGS_AND_STACK_ACCESS_API
         select HAVE_DMA_API_DEBUG
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_BZIP2
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index f20ddf84a893..a19829374e6a 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -319,7 +319,7 @@ config X86_L1_CACHE_SHIFT
 
 config X86_XADD
         def_bool y
-        depends on X86_32 && !M386
+        depends on X86_64 || !M386
 
 config X86_PPRO_FENCE
         bool "PentiumPro memory ordering errata workaround"
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 78b32be55e9e..0a43dc515e4c 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -135,9 +135,7 @@ drivers-$(CONFIG_OPROFILE) += arch/x86/oprofile/
 # suspend and hibernation support
 drivers-$(CONFIG_PM) += arch/x86/power/
 
-ifeq ($(CONFIG_X86_32),y)
 drivers-$(CONFIG_FB) += arch/x86/video/
-endif
 
 ####
 # boot loader support. Several targets are kept for legacy purposes
diff --git a/arch/x86/boot/compressed/misc.c b/arch/x86/boot/compressed/misc.c
index 3b22fe8ab91b..51e240779a44 100644
--- a/arch/x86/boot/compressed/misc.c
+++ b/arch/x86/boot/compressed/misc.c
@@ -19,11 +19,6 @@
 #define _ASM_X86_DESC_H 1
 #endif
 
-#ifdef CONFIG_X86_64
-#define _LINUX_STRING_H_ 1
-#define __LINUX_BITMAP_H 1
-#endif
-
 #include <linux/linkage.h>
 #include <linux/screen_info.h>
 #include <linux/elf.h>
@@ -131,8 +126,8 @@ static void error(char *m);
 static struct boot_params *real_mode;           /* Pointer to real-mode data */
 static int quiet;
 
-static void *memset(void *s, int c, unsigned n);
-void *memcpy(void *dest, const void *src, unsigned n);
+void *memset(void *s, int c, size_t n);
+void *memcpy(void *dest, const void *src, size_t n);
 
 static void __putstr(int, const char *);
 #define putstr(__x)  __putstr(0, __x)
@@ -185,11 +180,9 @@ static void __putstr(int error, const char *s)
                 return;
 #endif
 
-#ifdef CONFIG_X86_32
         if (real_mode->screen_info.orig_video_mode == 0 &&
             lines == 0 && cols == 0)
                 return;
-#endif
 
         x = real_mode->screen_info.orig_x;
         y = real_mode->screen_info.orig_y;
@@ -223,7 +216,7 @@ static void __putstr(int error, const char *s)
         outb(0xff & (pos >> 1), vidport+1);
 }
 
-static void *memset(void *s, int c, unsigned n)
+void *memset(void *s, int c, size_t n)
 {
         int i;
         char *ss = s;
@@ -233,7 +226,7 @@ static void *memset(void *s, int c, unsigned n)
         return s;
 }
 
-void *memcpy(void *dest, const void *src, unsigned n)
+void *memcpy(void *dest, const void *src, size_t n)
 {
         int i;
         const char *s = src;
diff --git a/arch/x86/boot/mkcpustr.c b/arch/x86/boot/mkcpustr.c
index 8ef60f20b371..919257f526f2 100644
--- a/arch/x86/boot/mkcpustr.c
+++ b/arch/x86/boot/mkcpustr.c
@@ -22,7 +22,7 @@ int main(void)
         int i, j;
         const char *str;
 
-        printf("static const char x86_cap_strs[] = \n");
+        printf("static const char x86_cap_strs[] =\n");
 
         for (i = 0; i < NCAPINTS; i++) {
                 for (j = 0; j < 32; j++) {
diff --git a/arch/x86/boot/video-vga.c b/arch/x86/boot/video-vga.c
index 819caa1f2008..ed7aeff786b2 100644
--- a/arch/x86/boot/video-vga.c
+++ b/arch/x86/boot/video-vga.c
@@ -42,22 +42,15 @@ static u8 vga_set_basic_mode(void)
 {
         struct biosregs ireg, oreg;
         u16 ax;
-        u8 rows;
         u8 mode;
 
         initregs(&ireg);
 
+        /* Query current mode */
         ax = 0x0f00;
         intcall(0x10, &ireg, &oreg);
         mode = oreg.al;
 
-        set_fs(0);
-        rows = rdfs8(0x484);    /* rows minus one */
-
-        if ((oreg.ax == 0x5003 || oreg.ax == 0x5007) &&
-            (rows == 0 || rows == 24))
-                return mode;
-
         if (mode != 3 && mode != 7)
                 mode = 3;
 
diff --git a/arch/x86/boot/video.c b/arch/x86/boot/video.c
index f767164cd5df..43eda284d27f 100644
--- a/arch/x86/boot/video.c
+++ b/arch/x86/boot/video.c
@@ -298,11 +298,18 @@ static void restore_screen(void)
         }
 
         /* Restore cursor position */
+        if (saved.curx >= xs)
+                saved.curx = xs-1;
+        if (saved.cury >= ys)
+                saved.cury = ys-1;
+
         initregs(&ireg);
         ireg.ah = 0x02;         /* Set cursor position */
         ireg.dh = saved.cury;
         ireg.dl = saved.curx;
         intcall(0x10, &ireg, NULL);
+
+        store_cursor_position();
 }
 
 void set_video(void)
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index f9f472462753..9046e4af66ce 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -297,7 +297,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
          * size limits imposed on them by creating programs with large
          * arrays in the data or bss.
          */
-        rlim = current->signal->rlim[RLIMIT_DATA].rlim_cur;
+        rlim = rlimit(RLIMIT_DATA);
         if (rlim >= RLIM_INFINITY)
                 rlim = ~0;
         if (ex.a_data + ex.a_bss > rlim)
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 69b74a7b877f..f1e253ceba4b 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -65,12 +65,17 @@ extern void alternatives_smp_module_add(struct module *mod, char *name,
                                         void *text, void *text_end);
 extern void alternatives_smp_module_del(struct module *mod);
 extern void alternatives_smp_switch(int smp);
+extern int alternatives_text_reserved(void *start, void *end);
 #else
 static inline void alternatives_smp_module_add(struct module *mod, char *name,
                                                void *locks, void *locks_end,
                                                void *text, void *text_end) {}
 static inline void alternatives_smp_module_del(struct module *mod) {}
 static inline void alternatives_smp_switch(int smp) {}
+static inline int alternatives_text_reserved(void *start, void *end)
+{
+        return 0;
+}
 #endif  /* CONFIG_SMP */
 
 /* alternative assembly primitive: */
@@ -125,11 +130,16 @@ static inline void alternatives_smp_switch(int smp) {}
         asm volatile (ALTERNATIVE(oldinstr, newinstr, feature)          \
                 : output : "i" (0), ## input)
 
+/* Like alternative_io, but for replacing a direct call with another one. */
+#define alternative_call(oldfunc, newfunc, feature, output, input...)   \
+        asm volatile (ALTERNATIVE("call %P[old]", "call %P[new]", feature) \
+                : output : [old] "i" (oldfunc), [new] "i" (newfunc), ## input)
+
 /*
  * use this macro(s) if you need more than one output parameter
  * in alternative_io
  */
-#define ASM_OUTPUT2(a, b) a, b
+#define ASM_OUTPUT2(a...) a
 
 struct paravirt_patch_site;
 #ifdef CONFIG_PARAVIRT
diff --git a/arch/x86/include/asm/atomic.h b/arch/x86/include/asm/atomic.h
index 4e1b8873c474..8f8217b9bdac 100644
--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -1,5 +1,300 @@
+#ifndef _ASM_X86_ATOMIC_H
+#define _ASM_X86_ATOMIC_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/processor.h>
+#include <asm/alternative.h>
+#include <asm/cmpxchg.h>
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ */
+
+#define ATOMIC_INIT(i)  { (i) }
+
+/**
+ * atomic_read - read atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically reads the value of @v.
+ */
+static inline int atomic_read(const atomic_t *v)
+{
+        return v->counter;
+}
+
+/**
+ * atomic_set - set atomic variable
+ * @v: pointer of type atomic_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+static inline void atomic_set(atomic_t *v, int i)
+{
+        v->counter = i;
+}
+
+/**
+ * atomic_add - add integer to atomic variable
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic_add(int i, atomic_t *v)
+{
+        asm volatile(LOCK_PREFIX "addl %1,%0"
+                     : "+m" (v->counter)
+                     : "ir" (i));
+}
+
+/**
+ * atomic_sub - subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic_sub(int i, atomic_t *v)
+{
+        asm volatile(LOCK_PREFIX "subl %1,%0"
+                     : "+m" (v->counter)
+                     : "ir" (i));
+}
+
+/**
+ * atomic_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer of type atomic_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+static inline int atomic_sub_and_test(int i, atomic_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
+                     : "+m" (v->counter), "=qm" (c)
+                     : "ir" (i) : "memory");
+        return c;
+}
+
+/**
+ * atomic_inc - increment atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1.
+ */
+static inline void atomic_inc(atomic_t *v)
+{
+        asm volatile(LOCK_PREFIX "incl %0"
+                     : "+m" (v->counter));
+}
+
+/**
+ * atomic_dec - decrement atomic variable
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1.
+ */
+static inline void atomic_dec(atomic_t *v)
+{
+        asm volatile(LOCK_PREFIX "decl %0"
+                     : "+m" (v->counter));
+}
+
+/**
+ * atomic_dec_and_test - decrement and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+static inline int atomic_dec_and_test(atomic_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "decl %0; sete %1"
+                     : "+m" (v->counter), "=qm" (c)
+                     : : "memory");
+        return c != 0;
+}
+
+/**
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+static inline int atomic_inc_and_test(atomic_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "incl %0; sete %1"
+                     : "+m" (v->counter), "=qm" (c)
+                     : : "memory");
+        return c != 0;
+}
+
+/**
+ * atomic_add_negative - add and test if negative
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+static inline int atomic_add_negative(int i, atomic_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "addl %2,%0; sets %1"
+                     : "+m" (v->counter), "=qm" (c)
+                     : "ir" (i) : "memory");
+        return c;
+}
+
+/**
+ * atomic_add_return - add integer and return
+ * @i: integer value to add
+ * @v: pointer of type atomic_t
+ *
+ * Atomically adds @i to @v and returns @i + @v
+ */
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        int __i;
+#ifdef CONFIG_M386
+        unsigned long flags;
+        if (unlikely(boot_cpu_data.x86 <= 3))
+                goto no_xadd;
+#endif
+        /* Modern 486+ processor */
+        __i = i;
+        asm volatile(LOCK_PREFIX "xaddl %0, %1"
+                     : "+r" (i), "+m" (v->counter)
+                     : : "memory");
+        return i + __i;
+
+#ifdef CONFIG_M386
+no_xadd: /* Legacy 386 processor */
+        raw_local_irq_save(flags);
+        __i = atomic_read(v);
+        atomic_set(v, i + __i);
+        raw_local_irq_restore(flags);
+        return i + __i;
+#endif
+}
+
+/**
+ * atomic_sub_return - subtract integer and return
+ * @v: pointer of type atomic_t
+ * @i: integer value to subtract
+ *
+ * Atomically subtracts @i from @v and returns @v - @i
+ */
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        return atomic_add_return(-i, v);
+}
+
+#define atomic_inc_return(v)  (atomic_add_return(1, v))
+#define atomic_dec_return(v)  (atomic_sub_return(1, v))
+
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
+{
+        return cmpxchg(&v->counter, old, new);
+}
+
+static inline int atomic_xchg(atomic_t *v, int new)
+{
+        return xchg(&v->counter, new);
+}
+
+/**
+ * atomic_add_unless - add unless the number is already a given value
+ * @v: pointer of type atomic_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as @v was not already @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+/**
+ * atomic_inc_short - increment of a short integer
+ * @v: pointer to type int
+ *
+ * Atomically adds 1 to @v
+ * Returns the new value of @u
+ */
+static inline short int atomic_inc_short(short int *v)
+{
+        asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
+        return *v;
+}
+
+#ifdef CONFIG_X86_64
+/**
+ * atomic_or_long - OR of two long integers
+ * @v1: pointer to type unsigned long
+ * @v2: pointer to type unsigned long
+ *
+ * Atomically ORs @v1 and @v2
+ * Returns the result of the OR
+ */
+static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
+{
+        asm(LOCK_PREFIX "orq %1, %0" : "+m" (*v1) : "r" (v2));
+}
+#endif
+
+/* These are x86-specific, used by some header files */
+#define atomic_clear_mask(mask, addr)                           \
+        asm volatile(LOCK_PREFIX "andl %0,%1"                   \
+                     : : "r" (~(mask)), "m" (*(addr)) : "memory")
+
+#define atomic_set_mask(mask, addr)                             \
+        asm volatile(LOCK_PREFIX "orl %0,%1"                    \
+                     : : "r" ((unsigned)(mask)), "m" (*(addr))  \
+                     : "memory")
+
+/* Atomic operations are already serializing on x86 */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
 #ifdef CONFIG_X86_32
-# include "atomic_32.h"
+# include "atomic64_32.h"
 #else
-# include "atomic_64.h"
+# include "atomic64_64.h"
 #endif
+
+#include <asm-generic/atomic-long.h>
+#endif /* _ASM_X86_ATOMIC_H */
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
new file mode 100644
index 000000000000..03027bf28de5
--- /dev/null
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -0,0 +1,160 @@
+#ifndef _ASM_X86_ATOMIC64_32_H
+#define _ASM_X86_ATOMIC64_32_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/processor.h>
+//#include <asm/cmpxchg.h>
+
+/* An 64bit atomic type */
+
+typedef struct {
+        u64 __aligned(8) counter;
+} atomic64_t;
+
+#define ATOMIC64_INIT(val)      { (val) }
+
+extern u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old_val, u64 new_val);
+
+/**
+ * atomic64_xchg - xchg atomic64 variable
+ * @ptr:      pointer to type atomic64_t
+ * @new_val:  value to assign
+ *
+ * Atomically xchgs the value of @ptr to @new_val and returns
+ * the old value.
+ */
+extern u64 atomic64_xchg(atomic64_t *ptr, u64 new_val);
+
+/**
+ * atomic64_set - set atomic64 variable
+ * @ptr:      pointer to type atomic64_t
+ * @new_val:  value to assign
+ *
+ * Atomically sets the value of @ptr to @new_val.
+ */
+extern void atomic64_set(atomic64_t *ptr, u64 new_val);
+
+/**
+ * atomic64_read - read atomic64 variable
+ * @ptr:      pointer to type atomic64_t
+ *
+ * Atomically reads the value of @ptr and returns it.
+ */
+static inline u64 atomic64_read(atomic64_t *ptr)
+{
+        u64 res;
+
+        /*
+         * Note, we inline this atomic64_t primitive because
+         * it only clobbers EAX/EDX and leaves the others
+         * untouched. We also (somewhat subtly) rely on the
+         * fact that cmpxchg8b returns the current 64-bit value
+         * of the memory location we are touching:
+         */
+        asm volatile(
+                "mov %%ebx, %%eax\n\t"
+                "mov %%ecx, %%edx\n\t"
+                LOCK_PREFIX "cmpxchg8b %1\n"
+                        : "=&A" (res)
+                        : "m" (*ptr)
+                );
+
+        return res;
+}
+
+extern u64 atomic64_read(atomic64_t *ptr);
+
+/**
+ * atomic64_add_return - add and return
+ * @delta: integer value to add
+ * @ptr:   pointer to type atomic64_t
+ *
+ * Atomically adds @delta to @ptr and returns @delta + *@ptr
+ */
+extern u64 atomic64_add_return(u64 delta, atomic64_t *ptr);
+
+/*
+ * Other variants with different arithmetic operators:
+ */
+extern u64 atomic64_sub_return(u64 delta, atomic64_t *ptr);
+extern u64 atomic64_inc_return(atomic64_t *ptr);
+extern u64 atomic64_dec_return(atomic64_t *ptr);
+
+/**
+ * atomic64_add - add integer to atomic64 variable
+ * @delta: integer value to add
+ * @ptr:   pointer to type atomic64_t
+ *
+ * Atomically adds @delta to @ptr.
+ */
+extern void atomic64_add(u64 delta, atomic64_t *ptr);
+
+/**
+ * atomic64_sub - subtract the atomic64 variable
+ * @delta: integer value to subtract
+ * @ptr:   pointer to type atomic64_t
+ *
+ * Atomically subtracts @delta from @ptr.
+ */
+extern void atomic64_sub(u64 delta, atomic64_t *ptr);
+
+/**
+ * atomic64_sub_and_test - subtract value from variable and test result
+ * @delta: integer value to subtract
+ * @ptr:   pointer to type atomic64_t
+ *
+ * Atomically subtracts @delta from @ptr and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+extern int atomic64_sub_and_test(u64 delta, atomic64_t *ptr);
+
+/**
+ * atomic64_inc - increment atomic64 variable
+ * @ptr: pointer to type atomic64_t
+ *
+ * Atomically increments @ptr by 1.
+ */
+extern void atomic64_inc(atomic64_t *ptr);
+
+/**
+ * atomic64_dec - decrement atomic64 variable
+ * @ptr: pointer to type atomic64_t
+ *
+ * Atomically decrements @ptr by 1.
+ */
+extern void atomic64_dec(atomic64_t *ptr);
+
+/**
+ * atomic64_dec_and_test - decrement and test
+ * @ptr: pointer to type atomic64_t
+ *
+ * Atomically decrements @ptr by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+extern int atomic64_dec_and_test(atomic64_t *ptr);
+
+/**
+ * atomic64_inc_and_test - increment and test
+ * @ptr: pointer to type atomic64_t
+ *
+ * Atomically increments @ptr by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+extern int atomic64_inc_and_test(atomic64_t *ptr);
+
+/**
+ * atomic64_add_negative - add and test if negative
+ * @delta: integer value to add
+ * @ptr:   pointer to type atomic64_t
+ *
+ * Atomically adds @delta to @ptr and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+extern int atomic64_add_negative(u64 delta, atomic64_t *ptr);
+
+#endif /* _ASM_X86_ATOMIC64_32_H */
diff --git a/arch/x86/include/asm/atomic64_64.h b/arch/x86/include/asm/atomic64_64.h
new file mode 100644
index 000000000000..51c5b4056929
--- /dev/null
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -0,0 +1,224 @@
+#ifndef _ASM_X86_ATOMIC64_64_H
+#define _ASM_X86_ATOMIC64_64_H
+
+#include <linux/types.h>
+#include <asm/alternative.h>
+#include <asm/cmpxchg.h>
+
+/* The 64-bit atomic type */
+
+#define ATOMIC64_INIT(i)        { (i) }
+
+/**
+ * atomic64_read - read atomic64 variable
+ * @v: pointer of type atomic64_t
+ *
+ * Atomically reads the value of @v.
+ * Doesn't imply a read memory barrier.
+ */
+static inline long atomic64_read(const atomic64_t *v)
+{
+        return v->counter;
+}
+
+/**
+ * atomic64_set - set atomic64 variable
+ * @v: pointer to type atomic64_t
+ * @i: required value
+ *
+ * Atomically sets the value of @v to @i.
+ */
+static inline void atomic64_set(atomic64_t *v, long i)
+{
+        v->counter = i;
+}
+
+/**
+ * atomic64_add - add integer to atomic64 variable
+ * @i: integer value to add
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically adds @i to @v.
+ */
+static inline void atomic64_add(long i, atomic64_t *v)
+{
+        asm volatile(LOCK_PREFIX "addq %1,%0"
+                     : "=m" (v->counter)
+                     : "er" (i), "m" (v->counter));
+}
+
+/**
+ * atomic64_sub - subtract the atomic64 variable
+ * @i: integer value to subtract
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically subtracts @i from @v.
+ */
+static inline void atomic64_sub(long i, atomic64_t *v)
+{
+        asm volatile(LOCK_PREFIX "subq %1,%0"
+                     : "=m" (v->counter)
+                     : "er" (i), "m" (v->counter));
+}
+
+/**
+ * atomic64_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically subtracts @i from @v and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+static inline int atomic64_sub_and_test(long i, atomic64_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "subq %2,%0; sete %1"
+                     : "=m" (v->counter), "=qm" (c)
+                     : "er" (i), "m" (v->counter) : "memory");
+        return c;
+}
+
+/**
+ * atomic64_inc - increment atomic64 variable
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically increments @v by 1.
+ */
+static inline void atomic64_inc(atomic64_t *v)
+{
+        asm volatile(LOCK_PREFIX "incq %0"
+                     : "=m" (v->counter)
+                     : "m" (v->counter));
+}
+
+/**
+ * atomic64_dec - decrement atomic64 variable
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically decrements @v by 1.
+ */
+static inline void atomic64_dec(atomic64_t *v)
+{
+        asm volatile(LOCK_PREFIX "decq %0"
+                     : "=m" (v->counter)
+                     : "m" (v->counter));
+}
+
+/**
+ * atomic64_dec_and_test - decrement and test
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically decrements @v by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+static inline int atomic64_dec_and_test(atomic64_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "decq %0; sete %1"
+                     : "=m" (v->counter), "=qm" (c)
+                     : "m" (v->counter) : "memory");
+        return c != 0;
+}
+
+/**
+ * atomic64_inc_and_test - increment and test
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+static inline int atomic64_inc_and_test(atomic64_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "incq %0; sete %1"
+                     : "=m" (v->counter), "=qm" (c)
+                     : "m" (v->counter) : "memory");
+        return c != 0;
+}
+
+/**
+ * atomic64_add_negative - add and test if negative
+ * @i: integer value to add
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically adds @i to @v and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+static inline int atomic64_add_negative(long i, atomic64_t *v)
+{
+        unsigned char c;
+
+        asm volatile(LOCK_PREFIX "addq %2,%0; sets %1"
+                     : "=m" (v->counter), "=qm" (c)
+                     : "er" (i), "m" (v->counter) : "memory");
+        return c;
+}
+
+/**
+ * atomic64_add_return - add and return
+ * @i: integer value to add
+ * @v: pointer to type atomic64_t
+ *
+ * Atomically adds @i to @v and returns @i + @v
+ */
+static inline long atomic64_add_return(long i, atomic64_t *v)
+{
+        long __i = i;
+        asm volatile(LOCK_PREFIX "xaddq %0, %1;"
+                     : "+r" (i), "+m" (v->counter)
+                     : : "memory");
+        return i + __i;
+}
+
+static inline long atomic64_sub_return(long i, atomic64_t *v)
+{
+        return atomic64_add_return(-i, v);
+}
+
+#define atomic64_inc_return(v)  (atomic64_add_return(1, (v)))
+#define atomic64_dec_return(v)  (atomic64_sub_return(1, (v)))
+
+static inline long atomic64_cmpxchg(atomic64_t *v, long old, long new)
+{
+        return cmpxchg(&v->counter, old, new);
+}
+
+static inline long atomic64_xchg(atomic64_t *v, long new)
+{
+        return xchg(&v->counter, new);
+}
+
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+#endif /* _ASM_X86_ATOMIC64_64_H */
diff --git a/arch/x86/include/asm/atomic_32.h b/arch/x86/include/asm/atomic_32.h
deleted file mode 100644
index dc5a667ff791..000000000000
--- a/arch/x86/include/asm/atomic_32.h
+++ /dev/null
@@ -1,415 +0,0 @@
-#ifndef _ASM_X86_ATOMIC_32_H
-#define _ASM_X86_ATOMIC_32_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <asm/processor.h>
-#include <asm/cmpxchg.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-#define ATOMIC_INIT(i)  { (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-static inline int atomic_read(const atomic_t *v)
-{
-        return v->counter;
-}
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-static inline void atomic_set(atomic_t *v, int i)
-{
-        v->counter = i;
-}
-
-/**
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic_add(int i, atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "addl %1,%0"
-                     : "+m" (v->counter)
-                     : "ir" (i));
-}
-
-/**
- * atomic_sub - subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static inline void atomic_sub(int i, atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "subl %1,%0"
-                     : "+m" (v->counter)
-                     : "ir" (i));
-}
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_sub_and_test(int i, atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
-                     : "+m" (v->counter), "=qm" (c)
-                     : "ir" (i) : "memory");
-        return c;
-}
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-static inline void atomic_inc(atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "incl %0"
-                     : "+m" (v->counter));
-}
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-static inline void atomic_dec(atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "decl %0"
-                     : "+m" (v->counter));
-}
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int atomic_dec_and_test(atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "decl %0; sete %1"
-                     : "+m" (v->counter), "=qm" (c)
-                     : : "memory");
-        return c != 0;
-}
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_inc_and_test(atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "incl %0; sete %1"
-                     : "+m" (v->counter), "=qm" (c)
-                     : : "memory");
-        return c != 0;
-}
-
-/**
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "addl %2,%0; sets %1"
-                     : "+m" (v->counter), "=qm" (c)
-                     : "ir" (i) : "memory");
-        return c;
-}
-
-/**
- * atomic_add_return - add integer and return
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-        int __i;
-#ifdef CONFIG_M386
-        unsigned long flags;
-        if (unlikely(boot_cpu_data.x86 <= 3))
-                goto no_xadd;
-#endif
-        /* Modern 486+ processor */
-        __i = i;
-        asm volatile(LOCK_PREFIX "xaddl %0, %1"
-                     : "+r" (i), "+m" (v->counter)
-                     : : "memory");
-        return i + __i;
-
-#ifdef CONFIG_M386
-no_xadd: /* Legacy 386 processor */
-        local_irq_save(flags);
-        __i = atomic_read(v);
-        atomic_set(v, i + __i);
-        local_irq_restore(flags);
-        return i + __i;
-#endif
-}
-
-/**
- * atomic_sub_return - subtract integer and return
- * @v: pointer of type atomic_t
- * @i: integer value to subtract
- *
- * Atomically subtracts @i from @v and returns @v - @i
- */
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
-        return atomic_add_return(-i, v);
-}
-
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
-        return cmpxchg(&v->counter, old, new);
-}
-
-static inline int atomic_xchg(atomic_t *v, int new)
-{
-        return xchg(&v->counter, new);
-}
-
-/**
- * atomic_add_unless - add unless the number is already a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as @v was not already @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int c, old;
-        c = atomic_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic_inc_return(v)  (atomic_add_return(1, v))
-#define atomic_dec_return(v)  (atomic_sub_return(1, v))
-
-/* These are x86-specific, used by some header files */
-#define atomic_clear_mask(mask, addr)                           \
-        asm volatile(LOCK_PREFIX "andl %0,%1"                   \
-                     : : "r" (~(mask)), "m" (*(addr)) : "memory")
-
-#define atomic_set_mask(mask, addr)                             \
-        asm volatile(LOCK_PREFIX "orl %0,%1"                            \
-                     : : "r" (mask), "m" (*(addr)) : "memory")
-
-/* Atomic operations are already serializing on x86 */
-#define smp_mb__before_atomic_dec()     barrier()
-#define smp_mb__after_atomic_dec()      barrier()
-#define smp_mb__before_atomic_inc()     barrier()
-#define smp_mb__after_atomic_inc()      barrier()
-
-/* An 64bit atomic type */
-
-typedef struct {
-        u64 __aligned(8) counter;
-} atomic64_t;
-
-#define ATOMIC64_INIT(val)      { (val) }
-
-extern u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old_val, u64 new_val);
-
-/**
- * atomic64_xchg - xchg atomic64 variable
- * @ptr:      pointer to type atomic64_t
- * @new_val:  value to assign
- *
- * Atomically xchgs the value of @ptr to @new_val and returns
- * the old value.
- */
-extern u64 atomic64_xchg(atomic64_t *ptr, u64 new_val);
-
-/**
- * atomic64_set - set atomic64 variable
- * @ptr:      pointer to type atomic64_t
- * @new_val:  value to assign
- *
- * Atomically sets the value of @ptr to @new_val.
- */
-extern void atomic64_set(atomic64_t *ptr, u64 new_val);
-
-/**
- * atomic64_read - read atomic64 variable
- * @ptr:      pointer to type atomic64_t
- *
- * Atomically reads the value of @ptr and returns it.
- */
-static inline u64 atomic64_read(atomic64_t *ptr)
-{
-        u64 res;
-
-        /*
-         * Note, we inline this atomic64_t primitive because
-         * it only clobbers EAX/EDX and leaves the others
-         * untouched. We also (somewhat subtly) rely on the
-         * fact that cmpxchg8b returns the current 64-bit value
-         * of the memory location we are touching:
-         */
-        asm volatile(
-                "mov %%ebx, %%eax\n\t"
-                "mov %%ecx, %%edx\n\t"
-                LOCK_PREFIX "cmpxchg8b %1\n"
-                        : "=&A" (res)
-                        : "m" (*ptr)
-                );
-
-        return res;
-}
-
-extern u64 atomic64_read(atomic64_t *ptr);
-
-/**
- * atomic64_add_return - add and return
- * @delta: integer value to add
- * @ptr:   pointer to type atomic64_t
- *
- * Atomically adds @delta to @ptr and returns @delta + *@ptr
- */
-extern u64 atomic64_add_return(u64 delta, atomic64_t *ptr);
-
-/*
- * Other variants with different arithmetic operators:
- */
-extern u64 atomic64_sub_return(u64 delta, atomic64_t *ptr);
-extern u64 atomic64_inc_return(atomic64_t *ptr);
-extern u64 atomic64_dec_return(atomic64_t *ptr);
-
-/**
- * atomic64_add - add integer to atomic64 variable
- * @delta: integer value to add
- * @ptr:   pointer to type atomic64_t
- *
- * Atomically adds @delta to @ptr.
- */
-extern void atomic64_add(u64 delta, atomic64_t *ptr);
-
-/**
- * atomic64_sub - subtract the atomic64 variable
- * @delta: integer value to subtract
- * @ptr:   pointer to type atomic64_t
- *
- * Atomically subtracts @delta from @ptr.
- */
-extern void atomic64_sub(u64 delta, atomic64_t *ptr);
-
-/**
- * atomic64_sub_and_test - subtract value from variable and test result
- * @delta: integer value to subtract
- * @ptr:   pointer to type atomic64_t
- *
- * Atomically subtracts @delta from @ptr and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-extern int atomic64_sub_and_test(u64 delta, atomic64_t *ptr);
-
-/**
- * atomic64_inc - increment atomic64 variable
- * @ptr: pointer to type atomic64_t
- *
- * Atomically increments @ptr by 1.
- */
-extern void atomic64_inc(atomic64_t *ptr);
-
-/**
- * atomic64_dec - decrement atomic64 variable
- * @ptr: pointer to type atomic64_t
- *
- * Atomically decrements @ptr by 1.
- */
-extern void atomic64_dec(atomic64_t *ptr);
-
-/**
- * atomic64_dec_and_test - decrement and test
- * @ptr: pointer to type atomic64_t
- *
- * Atomically decrements @ptr by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-extern int atomic64_dec_and_test(atomic64_t *ptr);
-
-/**
- * atomic64_inc_and_test - increment and test
- * @ptr: pointer to type atomic64_t
- *
- * Atomically increments @ptr by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-extern int atomic64_inc_and_test(atomic64_t *ptr);
-
-/**
- * atomic64_add_negative - add and test if negative
- * @delta: integer value to add
- * @ptr:   pointer to type atomic64_t
- *
- * Atomically adds @delta to @ptr and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-extern int atomic64_add_negative(u64 delta, atomic64_t *ptr);
-
-#include <asm-generic/atomic-long.h>
-#endif /* _ASM_X86_ATOMIC_32_H */
diff --git a/arch/x86/include/asm/atomic_64.h b/arch/x86/include/asm/atomic_64.h
deleted file mode 100644
index d605dc268e79..000000000000
--- a/arch/x86/include/asm/atomic_64.h
+++ /dev/null
@@ -1,485 +0,0 @@
-#ifndef _ASM_X86_ATOMIC_64_H
-#define _ASM_X86_ATOMIC_64_H
-
-#include <linux/types.h>
-#include <asm/alternative.h>
-#include <asm/cmpxchg.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-#define ATOMIC_INIT(i)  { (i) }
-
-/**
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-static inline int atomic_read(const atomic_t *v)
-{
-        return v->counter;
-}
-
-/**
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-static inline void atomic_set(atomic_t *v, int i)
-{
-        v->counter = i;
-}
-
-/**
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic_add(int i, atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "addl %1,%0"
-                     : "=m" (v->counter)
-                     : "ir" (i), "m" (v->counter));
-}
-
-/**
- * atomic_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static inline void atomic_sub(int i, atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "subl %1,%0"
-                     : "=m" (v->counter)
-                     : "ir" (i), "m" (v->counter));
-}
-
-/**
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_sub_and_test(int i, atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "subl %2,%0; sete %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "ir" (i), "m" (v->counter) : "memory");
-        return c;
-}
-
-/**
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-static inline void atomic_inc(atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "incl %0"
-                     : "=m" (v->counter)
-                     : "m" (v->counter));
-}
-
-/**
- * atomic_dec - decrement atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-static inline void atomic_dec(atomic_t *v)
-{
-        asm volatile(LOCK_PREFIX "decl %0"
-                     : "=m" (v->counter)
-                     : "m" (v->counter));
-}
-
-/**
- * atomic_dec_and_test - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int atomic_dec_and_test(atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "decl %0; sete %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "m" (v->counter) : "memory");
-        return c != 0;
-}
-
-/**
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic_inc_and_test(atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "incl %0; sete %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "m" (v->counter) : "memory");
-        return c != 0;
-}
-
-/**
- * atomic_add_negative - add and test if negative
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int atomic_add_negative(int i, atomic_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "addl %2,%0; sets %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "ir" (i), "m" (v->counter) : "memory");
-        return c;
-}
-
-/**
- * atomic_add_return - add and return
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-        int __i = i;
-        asm volatile(LOCK_PREFIX "xaddl %0, %1"
-                     : "+r" (i), "+m" (v->counter)
-                     : : "memory");
-        return i + __i;
-}
-
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
-        return atomic_add_return(-i, v);
-}
-
-#define atomic_inc_return(v)  (atomic_add_return(1, v))
-#define atomic_dec_return(v)  (atomic_sub_return(1, v))
-
-/* The 64-bit atomic type */
-
-#define ATOMIC64_INIT(i)        { (i) }
-
-/**
- * atomic64_read - read atomic64 variable
- * @v: pointer of type atomic64_t
- *
- * Atomically reads the value of @v.
- * Doesn't imply a read memory barrier.
- */
-static inline long atomic64_read(const atomic64_t *v)
-{
-        return v->counter;
-}
-
-/**
- * atomic64_set - set atomic64 variable
- * @v: pointer to type atomic64_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-static inline void atomic64_set(atomic64_t *v, long i)
-{
-        v->counter = i;
-}
-
-/**
- * atomic64_add - add integer to atomic64 variable
- * @i: integer value to add
- * @v: pointer to type atomic64_t
- *
- * Atomically adds @i to @v.
- */
-static inline void atomic64_add(long i, atomic64_t *v)
-{
-        asm volatile(LOCK_PREFIX "addq %1,%0"
-                     : "=m" (v->counter)
-                     : "er" (i), "m" (v->counter));
-}
-
-/**
- * atomic64_sub - subtract the atomic64 variable
- * @i: integer value to subtract
- * @v: pointer to type atomic64_t
- *
- * Atomically subtracts @i from @v.
- */
-static inline void atomic64_sub(long i, atomic64_t *v)
-{
-        asm volatile(LOCK_PREFIX "subq %1,%0"
-                     : "=m" (v->counter)
-                     : "er" (i), "m" (v->counter));
-}
-
-/**
- * atomic64_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer to type atomic64_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic64_sub_and_test(long i, atomic64_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "subq %2,%0; sete %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "er" (i), "m" (v->counter) : "memory");
-        return c;
-}
-
-/**
- * atomic64_inc - increment atomic64 variable
- * @v: pointer to type atomic64_t
- *
- * Atomically increments @v by 1.
- */
-static inline void atomic64_inc(atomic64_t *v)
-{
-        asm volatile(LOCK_PREFIX "incq %0"
-                     : "=m" (v->counter)
-                     : "m" (v->counter));
-}
-
-/**
- * atomic64_dec - decrement atomic64 variable
- * @v: pointer to type atomic64_t
- *
- * Atomically decrements @v by 1.
- */
-static inline void atomic64_dec(atomic64_t *v)
-{
-        asm volatile(LOCK_PREFIX "decq %0"
-                     : "=m" (v->counter)
-                     : "m" (v->counter));
-}
-
-/**
- * atomic64_dec_and_test - decrement and test
- * @v: pointer to type atomic64_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-static inline int atomic64_dec_and_test(atomic64_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "decq %0; sete %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "m" (v->counter) : "memory");
-        return c != 0;
-}
-
-/**
- * atomic64_inc_and_test - increment and test
- * @v: pointer to type atomic64_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-static inline int atomic64_inc_and_test(atomic64_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "incq %0; sete %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "m" (v->counter) : "memory");
-        return c != 0;
-}
-
-/**
- * atomic64_add_negative - add and test if negative
- * @i: integer value to add
- * @v: pointer to type atomic64_t
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-static inline int atomic64_add_negative(long i, atomic64_t *v)
-{
-        unsigned char c;
-
-        asm volatile(LOCK_PREFIX "addq %2,%0; sets %1"
-                     : "=m" (v->counter), "=qm" (c)
-                     : "er" (i), "m" (v->counter) : "memory");
-        return c;
-}
-
-/**
- * atomic64_add_return - add and return
- * @i: integer value to add
- * @v: pointer to type atomic64_t
- *
- * Atomically adds @i to @v and returns @i + @v
- */
-static inline long atomic64_add_return(long i, atomic64_t *v)
-{
-        long __i = i;
-        asm volatile(LOCK_PREFIX "xaddq %0, %1;"
-                     : "+r" (i), "+m" (v->counter)
-                     : : "memory");
-        return i + __i;
-}
-
-static inline long atomic64_sub_return(long i, atomic64_t *v)
-{
-        return atomic64_add_return(-i, v);
-}
-
-#define atomic64_inc_return(v)  (atomic64_add_return(1, (v)))
-#define atomic64_dec_return(v)  (atomic64_sub_return(1, (v)))
-
-static inline long atomic64_cmpxchg(atomic64_t *v, long old, long new)
-{
-        return cmpxchg(&v->counter, old, new);
-}
-
-static inline long atomic64_xchg(atomic64_t *v, long new)
-{
-        return xchg(&v->counter, new);
-}
-
-static inline long atomic_cmpxchg(atomic_t *v, int old, int new)
-{
-        return cmpxchg(&v->counter, old, new);
-}
-
-static inline long atomic_xchg(atomic_t *v, int new)
-{
-        return xchg(&v->counter, new);
-}
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int c, old;
-        c = atomic_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
-        long c, old;
-        c = atomic64_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic64_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-/**
- * atomic_inc_short - increment of a short integer
- * @v: pointer to type int
- *
- * Atomically adds 1 to @v
- * Returns the new value of @u
- */
-static inline short int atomic_inc_short(short int *v)
-{
-        asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
-        return *v;
-}
-
-/**
- * atomic_or_long - OR of two long integers
- * @v1: pointer to type unsigned long
- * @v2: pointer to type unsigned long
- *
- * Atomically ORs @v1 and @v2
- * Returns the result of the OR
- */
-static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
-{
-        asm(LOCK_PREFIX "orq %1, %0" : "+m" (*v1) : "r" (v2));
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-/* These are x86-specific, used by some header files */
-#define atomic_clear_mask(mask, addr)                                   \
-        asm volatile(LOCK_PREFIX "andl %0,%1"                           \
-                     : : "r" (~(mask)), "m" (*(addr)) : "memory")
-
-#define atomic_set_mask(mask, addr)                                     \
-        asm volatile(LOCK_PREFIX "orl %0,%1"                            \
-                     : : "r" ((unsigned)(mask)), "m" (*(addr))          \
-                     : "memory")
-
-/* Atomic operations are already serializing on x86 */
-#define smp_mb__before_atomic_dec()     barrier()
-#define smp_mb__after_atomic_dec()      barrier()
-#define smp_mb__before_atomic_inc()     barrier()
-#define smp_mb__after_atomic_inc()      barrier()
-
-#include <asm-generic/atomic-long.h>
-#endif /* _ASM_X86_ATOMIC_64_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 637e1ec963c3..0cd82d068613 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -168,6 +168,10 @@
 #define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
 #define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
 #define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
+#define X86_FEATURE_NPT         (8*32+5)  /* AMD Nested Page Table support */
+#define X86_FEATURE_LBRV        (8*32+6)  /* AMD LBR Virtualization support */
+#define X86_FEATURE_SVML        (8*32+7)  /* "svm_lock" AMD SVM locking MSR */
+#define X86_FEATURE_NRIPS       (8*32+8)  /* "nrip_save" AMD SVM next_rip save */
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 8240f76b531e..b81002f23614 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -14,6 +14,9 @@
    which debugging register was responsible for the trap.  The other bits
    are either reserved or not of interest to us. */
 
+/* Define reserved bits in DR6 which are always set to 1 */
+#define DR6_RESERVED    (0xFFFF0FF0)
+
 #define DR_TRAP0        (0x1)           /* db0 */
 #define DR_TRAP1        (0x2)           /* db1 */
 #define DR_TRAP2        (0x4)           /* db2 */
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index 1994d3f58443..f2ad2163109d 100644
--- a/arch/x86/include/asm/elf.h
+++ b/arch/x86/include/asm/elf.h
@@ -170,10 +170,7 @@ static inline void elf_common_init(struct thread_struct *t,
 }
 
 #define ELF_PLAT_INIT(_r, load_addr)                    \
-do {                                                    \
-        elf_common_init(&current->thread, _r, 0);       \
-        clear_thread_flag(TIF_IA32);                    \
-} while (0)
+        elf_common_init(&current->thread, _r, 0)
 
 #define COMPAT_ELF_PLAT_INIT(regs, load_addr)           \
         elf_common_init(&current->thread, regs, __USER_DS)
diff --git a/arch/x86/include/asm/fb.h b/arch/x86/include/asm/fb.h
index 53018464aea6..2519d0679d99 100644
--- a/arch/x86/include/asm/fb.h
+++ b/arch/x86/include/asm/fb.h
@@ -12,10 +12,6 @@ static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
                 pgprot_val(vma->vm_page_prot) |= _PAGE_PCD;
 }
 
-#ifdef CONFIG_X86_32
 extern int fb_is_primary_device(struct fb_info *info);
-#else
-static inline int fb_is_primary_device(struct fb_info *info) { return 0; }
-#endif
 
 #endif /* _ASM_X86_FB_H */
diff --git a/arch/x86/include/asm/fixmap.h b/arch/x86/include/asm/fixmap.h
index 14f9890eb495..635f03bb4995 100644
--- a/arch/x86/include/asm/fixmap.h
+++ b/arch/x86/include/asm/fixmap.h
@@ -118,14 +118,20 @@ enum fixed_addresses {
          * 256 temporary boot-time mappings, used by early_ioremap(),
          * before ioremap() is functional.
          *
-         * We round it up to the next 256 pages boundary so that we
-         * can have a single pgd entry and a single pte table:
+         * If necessary we round it up to the next 256 pages boundary so
+         * that we can have a single pgd entry and a single pte table:
          */
 #define NR_FIX_BTMAPS           64
 #define FIX_BTMAPS_SLOTS        4
-        FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 256 -
-                        (__end_of_permanent_fixed_addresses & 255),
-        FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_SLOTS - 1,
+#define TOTAL_FIX_BTMAPS        (NR_FIX_BTMAPS * FIX_BTMAPS_SLOTS)
+        FIX_BTMAP_END =
+         (__end_of_permanent_fixed_addresses ^
+          (__end_of_permanent_fixed_addresses + TOTAL_FIX_BTMAPS - 1)) &
+         -PTRS_PER_PTE
+         ? __end_of_permanent_fixed_addresses + TOTAL_FIX_BTMAPS -
+           (__end_of_permanent_fixed_addresses & (TOTAL_FIX_BTMAPS - 1))
+         : __end_of_permanent_fixed_addresses,
+        FIX_BTMAP_BEGIN = FIX_BTMAP_END + TOTAL_FIX_BTMAPS - 1,
 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
         FIX_OHCI1394_BASE,
 #endif
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index ebfb8a9e11f7..da2930924501 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -33,8 +33,16 @@ extern void init_thread_xstate(void);
 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
 
 extern user_regset_active_fn fpregs_active, xfpregs_active;
-extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
-extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
+extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
+                                xstateregs_get;
+extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
+                                 xstateregs_set;
+
+/*
+ * xstateregs_active == fpregs_active. Please refer to the comment
+ * at the definition of fpregs_active.
+ */
+#define xstateregs_active       fpregs_active
 
 extern struct _fpx_sw_bytes fx_sw_reserved;
 #ifdef CONFIG_IA32_EMULATION
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 73739322b6d0..a1dcfa3ab17d 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -1,8 +1,42 @@
 #ifndef _ASM_X86_IO_H
 #define _ASM_X86_IO_H
 
+/*
+ * This file contains the definitions for the x86 IO instructions
+ * inb/inw/inl/outb/outw/outl and the "string versions" of the same
+ * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
+ * versions of the single-IO instructions (inb_p/inw_p/..).
+ *
+ * This file is not meant to be obfuscating: it's just complicated
+ * to (a) handle it all in a way that makes gcc able to optimize it
+ * as well as possible and (b) trying to avoid writing the same thing
+ * over and over again with slight variations and possibly making a
+ * mistake somewhere.
+ */
+
+/*
+ * Thanks to James van Artsdalen for a better timing-fix than
+ * the two short jumps: using outb's to a nonexistent port seems
+ * to guarantee better timings even on fast machines.
+ *
+ * On the other hand, I'd like to be sure of a non-existent port:
+ * I feel a bit unsafe about using 0x80 (should be safe, though)
+ *
+ *              Linus
+ */
+
+ /*
+  *  Bit simplified and optimized by Jan Hubicka
+  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
+  *
+  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
+  *  isa_read[wl] and isa_write[wl] fixed
+  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
+  */
+
 #define ARCH_HAS_IOREMAP_WC
 
+#include <linux/string.h>
 #include <linux/compiler.h>
 #include <asm-generic/int-ll64.h>
 #include <asm/page.h>
@@ -173,11 +207,126 @@ static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
 extern void iounmap(volatile void __iomem *addr);
 
 
-#ifdef CONFIG_X86_32
-# include "io_32.h"
+#ifdef __KERNEL__
+
+#include <asm-generic/iomap.h>
+
+#include <linux/vmalloc.h>
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+static inline void
+memset_io(volatile void __iomem *addr, unsigned char val, size_t count)
+{
+        memset((void __force *)addr, val, count);
+}
+
+static inline void
+memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count)
+{
+        memcpy(dst, (const void __force *)src, count);
+}
+
+static inline void
+memcpy_toio(volatile void __iomem *dst, const void *src, size_t count)
+{
+        memcpy((void __force *)dst, src, count);
+}
+
+/*
+ * ISA space is 'always mapped' on a typical x86 system, no need to
+ * explicitly ioremap() it. The fact that the ISA IO space is mapped
+ * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
+ * are physical addresses. The following constant pointer can be
+ * used as the IO-area pointer (it can be iounmapped as well, so the
+ * analogy with PCI is quite large):
+ */
+#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
+
+/*
+ *      Cache management
+ *
+ *      This needed for two cases
+ *      1. Out of order aware processors
+ *      2. Accidentally out of order processors (PPro errata #51)
+ */
+
+static inline void flush_write_buffers(void)
+{
+#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
+        asm volatile("lock; addl $0,0(%%esp)": : :"memory");
+#endif
+}
+
+#endif /* __KERNEL__ */
+
+extern void native_io_delay(void);
+
+extern int io_delay_type;
+extern void io_delay_init(void);
+
+#if defined(CONFIG_PARAVIRT)
+#include <asm/paravirt.h>
 #else
-# include "io_64.h"
+
+static inline void slow_down_io(void)
+{
+        native_io_delay();
+#ifdef REALLY_SLOW_IO
+        native_io_delay();
+        native_io_delay();
+        native_io_delay();
 #endif
+}
+
+#endif
+
+#define BUILDIO(bwl, bw, type)                                          \
+static inline void out##bwl(unsigned type value, int port)              \
+{                                                                       \
+        asm volatile("out" #bwl " %" #bw "0, %w1"                       \
+                     : : "a"(value), "Nd"(port));                       \
+}                                                                       \
+                                                                        \
+static inline unsigned type in##bwl(int port)                           \
+{                                                                       \
+        unsigned type value;                                            \
+        asm volatile("in" #bwl " %w1, %" #bw "0"                        \
+                     : "=a"(value) : "Nd"(port));                       \
+        return value;                                                   \
+}                                                                       \
+                                                                        \
+static inline void out##bwl##_p(unsigned type value, int port)          \
+{                                                                       \
+        out##bwl(value, port);                                          \
+        slow_down_io();                                                 \
+}                                                                       \
+                                                                        \
+static inline unsigned type in##bwl##_p(int port)                       \
+{                                                                       \
+        unsigned type value = in##bwl(port);                            \
+        slow_down_io();                                                 \
+        return value;                                                   \
+}                                                                       \
+                                                                        \
+static inline void outs##bwl(int port, const void *addr, unsigned long count) \
+{                                                                       \
+        asm volatile("rep; outs" #bwl                                   \
+                     : "+S"(addr), "+c"(count) : "d"(port));            \
+}                                                                       \
+                                                                        \
+static inline void ins##bwl(int port, void *addr, unsigned long count)  \
+{                                                                       \
+        asm volatile("rep; ins" #bwl                                    \
+                     : "+D"(addr), "+c"(count) : "d"(port));            \
+}
+
+BUILDIO(b, b, char)
+BUILDIO(w, w, short)
+BUILDIO(l, , int)
 
 extern void *xlate_dev_mem_ptr(unsigned long phys);
 extern void unxlate_dev_mem_ptr(unsigned long phys, void *addr);
diff --git a/arch/x86/include/asm/io_32.h b/arch/x86/include/asm/io_32.h
deleted file mode 100644
index a299900f5920..000000000000
--- a/arch/x86/include/asm/io_32.h
+++ /dev/null
@@ -1,196 +0,0 @@
-#ifndef _ASM_X86_IO_32_H
-#define _ASM_X86_IO_32_H
-
-#include <linux/string.h>
-#include <linux/compiler.h>
-
-/*
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
-
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *              Linus
- */
-
- /*
-  *  Bit simplified and optimized by Jan Hubicka
-  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
-  *
-  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
-  *  isa_read[wl] and isa_write[wl] fixed
-  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
-  */
-
-#define XQUAD_PORTIO_BASE 0xfe400000
-#define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
-
-#ifdef __KERNEL__
-
-#include <asm-generic/iomap.h>
-
-#include <linux/vmalloc.h>
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-static inline void
-memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
-        memset((void __force *)addr, val, count);
-}
-
-static inline void
-memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
-{
-        __memcpy(dst, (const void __force *)src, count);
-}
-
-static inline void
-memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
-        __memcpy((void __force *)dst, src, count);
-}
-
-/*
- * ISA space is 'always mapped' on a typical x86 system, no need to
- * explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
-
-/*
- *      Cache management
- *
- *      This needed for two cases
- *      1. Out of order aware processors
- *      2. Accidentally out of order processors (PPro errata #51)
- */
-
-#if defined(CONFIG_X86_OOSTORE) || defined(CONFIG_X86_PPRO_FENCE)
-
-static inline void flush_write_buffers(void)
-{
-        asm volatile("lock; addl $0,0(%%esp)": : :"memory");
-}
-
-#else
-
-#define flush_write_buffers() do { } while (0)
-
-#endif
-
-#endif /* __KERNEL__ */
-
-extern void native_io_delay(void);
-
-extern int io_delay_type;
-extern void io_delay_init(void);
-
-#if defined(CONFIG_PARAVIRT)
-#include <asm/paravirt.h>
-#else
-
-static inline void slow_down_io(void)
-{
-        native_io_delay();
-#ifdef REALLY_SLOW_IO
-        native_io_delay();
-        native_io_delay();
-        native_io_delay();
-#endif
-}
-
-#endif
-
-#define __BUILDIO(bwl, bw, type)                                \
-static inline void out##bwl(unsigned type value, int port)      \
-{                                                               \
-        out##bwl##_local(value, port);                          \
-}                                                               \
-                                                                \
-static inline unsigned type in##bwl(int port)                   \
-{                                                               \
-        return in##bwl##_local(port);                           \
-}
-
-#define BUILDIO(bwl, bw, type)                                          \
-static inline void out##bwl##_local(unsigned type value, int port)      \
-{                                                                       \
-        asm volatile("out" #bwl " %" #bw "0, %w1"               \
-                     : : "a"(value), "Nd"(port));                       \
-}                                                                       \
-                                                                        \
-static inline unsigned type in##bwl##_local(int port)                   \
-{                                                                       \
-        unsigned type value;                                            \
-        asm volatile("in" #bwl " %w1, %" #bw "0"                \
-                     : "=a"(value) : "Nd"(port));                       \
-        return value;                                                   \
-}                                                                       \
-                                                                        \
-static inline void out##bwl##_local_p(unsigned type value, int port)    \
-{                                                                       \
-        out##bwl##_local(value, port);                                  \
-        slow_down_io();                                                 \
-}                                                                       \
-                                                                        \
-static inline unsigned type in##bwl##_local_p(int port)                 \
-{                                                                       \
-        unsigned type value = in##bwl##_local(port);                    \
-        slow_down_io();                                                 \
-        return value;                                                   \
-}                                                                       \
-                                                                        \
-__BUILDIO(bwl, bw, type)                                                \
-                                                                        \
-static inline void out##bwl##_p(unsigned type value, int port)          \
-{                                                                       \
-        out##bwl(value, port);                                          \
-        slow_down_io();                                                 \
-}                                                                       \
-                                                                        \
-static inline unsigned type in##bwl##_p(int port)                       \
-{                                                                       \
-        unsigned type value = in##bwl(port);                            \
-        slow_down_io();                                                 \
-        return value;                                                   \
-}                                                                       \
-                                                                        \
-static inline void outs##bwl(int port, const void *addr, unsigned long count) \
-{                                                                       \
-        asm volatile("rep; outs" #bwl                                   \
-                     : "+S"(addr), "+c"(count) : "d"(port));            \
-}                                                                       \
-                                                                        \
-static inline void ins##bwl(int port, void *addr, unsigned long count)  \
-{                                                                       \
-        asm volatile("rep; ins" #bwl                                    \
-                     : "+D"(addr), "+c"(count) : "d"(port));            \
-}
-
-BUILDIO(b, b, char)
-BUILDIO(w, w, short)
-BUILDIO(l, , int)
-
-#endif /* _ASM_X86_IO_32_H */
diff --git a/arch/x86/include/asm/io_64.h b/arch/x86/include/asm/io_64.h
deleted file mode 100644
index 244067893af4..000000000000
--- a/arch/x86/include/asm/io_64.h
+++ /dev/null
@@ -1,181 +0,0 @@
-#ifndef _ASM_X86_IO_64_H
-#define _ASM_X86_IO_64_H
-
-
-/*
- * This file contains the definitions for the x86 IO instructions
- * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
- *
- * This file is not meant to be obfuscating: it's just complicated
- * to (a) handle it all in a way that makes gcc able to optimize it
- * as well as possible and (b) trying to avoid writing the same thing
- * over and over again with slight variations and possibly making a
- * mistake somewhere.
- */
-
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *              Linus
- */
-
- /*
-  *  Bit simplified and optimized by Jan Hubicka
-  *  Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
-  *
-  *  isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
-  *  isa_read[wl] and isa_write[wl] fixed
-  *  - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
-  */
-
-extern void native_io_delay(void);
-
-extern int io_delay_type;
-extern void io_delay_init(void);
-
-#if defined(CONFIG_PARAVIRT)
-#include <asm/paravirt.h>
-#else
-
-static inline void slow_down_io(void)
-{
-        native_io_delay();
-#ifdef REALLY_SLOW_IO
-        native_io_delay();
-        native_io_delay();
-        native_io_delay();
-#endif
-}
-#endif
-
-/*
- * Talk about misusing macros..
- */
-#define __OUT1(s, x)                                                    \
-static inline void out##s(unsigned x value, unsigned short port) {
-
-#define __OUT2(s, s1, s2)                               \
-asm volatile ("out" #s " %" s1 "0,%" s2 "1"
-
-#ifndef REALLY_SLOW_IO
-#define REALLY_SLOW_IO
-#define UNSET_REALLY_SLOW_IO
-#endif
-
-#define __OUT(s, s1, x)                                                 \
-        __OUT1(s, x) __OUT2(s, s1, "w") : : "a" (value), "Nd" (port));  \
-        }                                                               \
-        __OUT1(s##_p, x) __OUT2(s, s1, "w") : : "a" (value), "Nd" (port)); \
-        slow_down_io();                                                 \
-}
-
-#define __IN1(s)                                                        \
-static inline RETURN_TYPE in##s(unsigned short port)                    \
-{                                                                       \
-        RETURN_TYPE _v;
-
-#define __IN2(s, s1, s2)                                                \
-        asm volatile ("in" #s " %" s2 "1,%" s1 "0"
-
-#define __IN(s, s1, i...)                                               \
-        __IN1(s) __IN2(s, s1, "w") : "=a" (_v) : "Nd" (port), ##i);     \
-        return _v;                                                      \
-        }                                                               \
-        __IN1(s##_p) __IN2(s, s1, "w") : "=a" (_v) : "Nd" (port), ##i); \
-        slow_down_io(); \
-        return _v; }
-
-#ifdef UNSET_REALLY_SLOW_IO
-#undef REALLY_SLOW_IO
-#endif
-
-#define __INS(s)                                                        \
-static inline void ins##s(unsigned short port, void *addr,              \
-                          unsigned long count)                          \
-{                                                                       \
-        asm volatile ("rep ; ins" #s                                    \
-                      : "=D" (addr), "=c" (count)                       \
-                      : "d" (port), "0" (addr), "1" (count));           \
-}
-
-#define __OUTS(s)                                                       \
-static inline void outs##s(unsigned short port, const void *addr,       \
-                           unsigned long count)                         \
-{                                                                       \
-        asm volatile ("rep ; outs" #s                                   \
-                      : "=S" (addr), "=c" (count)                       \
-                      : "d" (port), "0" (addr), "1" (count));           \
-}
-
-#define RETURN_TYPE unsigned char
-__IN(b, "")
-#undef RETURN_TYPE
-#define RETURN_TYPE unsigned short
-__IN(w, "")
-#undef RETURN_TYPE
-#define RETURN_TYPE unsigned int
-__IN(l, "")
-#undef RETURN_TYPE
-
-__OUT(b, "b", char)
-__OUT(w, "w", short)
-__OUT(l, , int)
-
-__INS(b)
-__INS(w)
-__INS(l)
-
-__OUTS(b)
-__OUTS(w)
-__OUTS(l)
-
-#if defined(__KERNEL__) && defined(__x86_64__)
-
-#include <linux/vmalloc.h>
-
-#include <asm-generic/iomap.h>
-
-void __memcpy_fromio(void *, unsigned long, unsigned);
-void __memcpy_toio(unsigned long, const void *, unsigned);
-
-static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
-                                 unsigned len)
-{
-        __memcpy_fromio(to, (unsigned long)from, len);
-}
-
-static inline void memcpy_toio(volatile void __iomem *to, const void *from,
-                               unsigned len)
-{
-        __memcpy_toio((unsigned long)to, from, len);
-}
-
-void memset_io(volatile void __iomem *a, int b, size_t c);
-
-/*
- * ISA space is 'always mapped' on a typical x86 system, no need to
- * explicitly ioremap() it. The fact that the ISA IO space is mapped
- * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
- * are physical addresses. The following constant pointer can be
- * used as the IO-area pointer (it can be iounmapped as well, so the
- * analogy with PCI is quite large):
- */
-#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
-
-#define flush_write_buffers()
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_X86_IO_64_H */
diff --git a/arch/x86/include/asm/mmzone_64.h b/arch/x86/include/asm/mmzone_64.h
index a29f48c2a322..288b96f815a6 100644
--- a/arch/x86/include/asm/mmzone_64.h
+++ b/arch/x86/include/asm/mmzone_64.h
@@ -39,11 +39,5 @@ static inline __attribute__((pure)) int phys_to_nid(unsigned long addr)
 #define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
 #define node_end_pfn(nid)       (NODE_DATA(nid)->node_start_pfn +       \
                                  NODE_DATA(nid)->node_spanned_pages)
-
-#ifdef CONFIG_NUMA_EMU
-#define FAKE_NODE_MIN_SIZE      (64 * 1024 * 1024)
-#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL))
-#endif
-
 #endif
 #endif /* _ASM_X86_MMZONE_64_H */
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index 139d4c1a33a7..93da9c3f3341 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -19,7 +19,6 @@ extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
 extern int check_nmi_watchdog(void);
 extern int nmi_watchdog_enabled;
 extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);
-extern int avail_to_resrv_perfctr_nmi(unsigned int);
 extern int reserve_perfctr_nmi(unsigned int);
 extern void release_perfctr_nmi(unsigned int);
 extern int reserve_evntsel_nmi(unsigned int);
diff --git a/arch/x86/include/asm/numa_64.h b/arch/x86/include/asm/numa_64.h
index c4ae822e415f..823e070e7c26 100644
--- a/arch/x86/include/asm/numa_64.h
+++ b/arch/x86/include/asm/numa_64.h
@@ -36,6 +36,11 @@ extern void __cpuinit numa_set_node(int cpu, int node);
 extern void __cpuinit numa_clear_node(int cpu);
 extern void __cpuinit numa_add_cpu(int cpu);
 extern void __cpuinit numa_remove_cpu(int cpu);
+
+#ifdef CONFIG_NUMA_EMU
+#define FAKE_NODE_MIN_SIZE      ((u64)64 << 20)
+#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL))
+#endif /* CONFIG_NUMA_EMU */
 #else
 static inline void init_cpu_to_node(void)               { }
 static inline void numa_set_node(int cpu, int node)     { }
diff --git a/arch/x86/include/asm/numaq.h b/arch/x86/include/asm/numaq.h
index 9f0a5f5d29ec..13370b95ea94 100644
--- a/arch/x86/include/asm/numaq.h
+++ b/arch/x86/include/asm/numaq.h
@@ -33,6 +33,10 @@ extern int get_memcfg_numaq(void);
 
 extern void *xquad_portio;
 
+#define XQUAD_PORTIO_BASE 0xfe400000
+#define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
+#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
+
 /*
  * SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
  */
diff --git a/arch/x86/include/asm/page_types.h b/arch/x86/include/asm/page_types.h
index 642fe34b36a2..a667f24c7254 100644
--- a/arch/x86/include/asm/page_types.h
+++ b/arch/x86/include/asm/page_types.h
@@ -40,7 +40,6 @@
 
 #ifndef __ASSEMBLY__
 
-extern int page_is_ram(unsigned long pagenr);
 extern int devmem_is_allowed(unsigned long pagenr);
 
 extern unsigned long max_low_pfn_mapped;
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index b4bf9a942ed0..05b58ccb2e82 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -29,6 +29,7 @@
 #define PCI_CHECK_ENABLE_AMD_MMCONF     0x20000
 #define PCI_HAS_IO_ECS          0x40000
 #define PCI_NOASSIGN_ROMS       0x80000
+#define PCI_ROOT_NO_CRS         0x100000
 
 extern unsigned int pci_probe;
 extern unsigned long pirq_table_addr;
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 1380367dabd9..befd172c82ad 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -27,7 +27,14 @@
 /*
  * Includes eventsel and unit mask as well:
  */
-#define ARCH_PERFMON_EVENT_MASK                             0xffff
+
+
+#define INTEL_ARCH_EVTSEL_MASK          0x000000FFULL
+#define INTEL_ARCH_UNIT_MASK            0x0000FF00ULL
+#define INTEL_ARCH_EDGE_MASK            0x00040000ULL
+#define INTEL_ARCH_INV_MASK             0x00800000ULL
+#define INTEL_ARCH_CNT_MASK             0xFF000000ULL
+#define INTEL_ARCH_EVENT_MASK   (INTEL_ARCH_UNIT_MASK|INTEL_ARCH_EVTSEL_MASK)
 
 /*
  * filter mask to validate fixed counter events.
@@ -38,7 +45,12 @@
  *  The other filters are supported by fixed counters.
  *  The any-thread option is supported starting with v3.
  */
-#define ARCH_PERFMON_EVENT_FILTER_MASK                  0xff840000
+#define INTEL_ARCH_FIXED_MASK \
+        (INTEL_ARCH_CNT_MASK| \
+         INTEL_ARCH_INV_MASK| \
+         INTEL_ARCH_EDGE_MASK|\
+         INTEL_ARCH_UNIT_MASK|\
+         INTEL_ARCH_EVTSEL_MASK)
 
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                 0x3c
 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h
index 0e8c2a0fd922..271de94c3810 100644
--- a/arch/x86/include/asm/pgalloc.h
+++ b/arch/x86/include/asm/pgalloc.h
@@ -23,6 +23,11 @@ static inline void paravirt_release_pud(unsigned long pfn) {}
 #endif
 
 /*
+ * Flags to use when allocating a user page table page.
+ */
+extern gfp_t __userpte_alloc_gfp;
+
+/*
  * Allocate and free page tables.
  */
 extern pgd_t *pgd_alloc(struct mm_struct *);
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index 01fd9461d323..a28668396508 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -80,7 +80,7 @@ do {						\
  * The i386 doesn't have any external MMU info: the kernel page
  * tables contain all the necessary information.
  */
-#define update_mmu_cache(vma, address, pte) do { } while (0)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index c57a30117149..181be528c612 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -129,7 +129,7 @@ static inline int pgd_large(pgd_t pgd) { return 0; }
 #define pte_unmap(pte) /* NOP */
 #define pte_unmap_nested(pte) /* NOP */
 
-#define update_mmu_cache(vma, address, pte) do { } while (0)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
 
 /* Encode and de-code a swap entry */
 #if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index fc801bab1b3b..b753ea59703a 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -450,6 +450,8 @@ struct thread_struct {
         struct perf_event       *ptrace_bps[HBP_NUM];
         /* Debug status used for traps, single steps, etc... */
         unsigned long           debugreg6;
+        /* Keep track of the exact dr7 value set by the user */
+        unsigned long           ptrace_dr7;
         /* Fault info: */
         unsigned long           cr2;
         unsigned long           trap_no;
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 9d369f680321..20102808b191 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -274,10 +274,6 @@ static inline unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
                 return 0;
 }
 
-/* Get Nth argument at function call */
-extern unsigned long regs_get_argument_nth(struct pt_regs *regs,
-                                           unsigned int n);
-
 /*
  * These are defined as per linux/ptrace.h, which see.
  */
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index ca7517d33776..606ede126972 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -41,6 +41,7 @@
 #include <linux/list.h>
 #include <linux/spinlock.h>
 #include <linux/lockdep.h>
+#include <asm/asm.h>
 
 struct rwsem_waiter;
 
@@ -55,17 +56,28 @@ extern asmregparm struct rw_semaphore *
 
 /*
  * the semaphore definition
+ *
+ * The bias values and the counter type limits the number of
+ * potential readers/writers to 32767 for 32 bits and 2147483647
+ * for 64 bits.
  */
 
-#define RWSEM_UNLOCKED_VALUE            0x00000000
-#define RWSEM_ACTIVE_BIAS               0x00000001
-#define RWSEM_ACTIVE_MASK               0x0000ffff
-#define RWSEM_WAITING_BIAS              (-0x00010000)
+#ifdef CONFIG_X86_64
+# define RWSEM_ACTIVE_MASK              0xffffffffL
+#else
+# define RWSEM_ACTIVE_MASK              0x0000ffffL
+#endif
+
+#define RWSEM_UNLOCKED_VALUE            0x00000000L
+#define RWSEM_ACTIVE_BIAS               0x00000001L
+#define RWSEM_WAITING_BIAS              (-RWSEM_ACTIVE_MASK-1)
 #define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
 
+typedef signed long rwsem_count_t;
+
 struct rw_semaphore {
-        signed long             count;
+        rwsem_count_t           count;
         spinlock_t              wait_lock;
         struct list_head        wait_list;
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
@@ -105,7 +117,7 @@ do {								\
 static inline void __down_read(struct rw_semaphore *sem)
 {
         asm volatile("# beginning down_read\n\t"
-                     LOCK_PREFIX "  incl      (%%eax)\n\t"
+                     LOCK_PREFIX _ASM_INC "(%1)\n\t"
                      /* adds 0x00000001, returns the old value */
                      "  jns        1f\n"
                      "  call call_rwsem_down_read_failed\n"
@@ -121,14 +133,14 @@ static inline void __down_read(struct rw_semaphore *sem)
  */
 static inline int __down_read_trylock(struct rw_semaphore *sem)
 {
-        __s32 result, tmp;
+        rwsem_count_t result, tmp;
         asm volatile("# beginning __down_read_trylock\n\t"
-                     "  movl      %0,%1\n\t"
+                     "  mov          %0,%1\n\t"
                      "1:\n\t"
-                     "  movl         %1,%2\n\t"
-                     "  addl      %3,%2\n\t"
+                     "  mov          %1,%2\n\t"
+                     "  add          %3,%2\n\t"
                      "  jle          2f\n\t"
-                     LOCK_PREFIX "  cmpxchgl  %2,%0\n\t"
+                     LOCK_PREFIX "  cmpxchg  %2,%0\n\t"
                      "  jnz          1b\n\t"
                      "2:\n\t"
                      "# ending __down_read_trylock\n\t"
@@ -143,13 +155,13 @@ static inline int __down_read_trylock(struct rw_semaphore *sem)
  */
 static inline void __down_write_nested(struct rw_semaphore *sem, int subclass)
 {
-        int tmp;
+        rwsem_count_t tmp;
 
         tmp = RWSEM_ACTIVE_WRITE_BIAS;
         asm volatile("# beginning down_write\n\t"
-                     LOCK_PREFIX "  xadd      %%edx,(%%eax)\n\t"
+                     LOCK_PREFIX "  xadd      %1,(%2)\n\t"
                      /* subtract 0x0000ffff, returns the old value */
-                     "  testl     %%edx,%%edx\n\t"
+                     "  test      %1,%1\n\t"
                      /* was the count 0 before? */
                      "  jz        1f\n"
                      "  call call_rwsem_down_write_failed\n"
@@ -170,9 +182,9 @@ static inline void __down_write(struct rw_semaphore *sem)
  */
 static inline int __down_write_trylock(struct rw_semaphore *sem)
 {
-        signed long ret = cmpxchg(&sem->count,
-                                  RWSEM_UNLOCKED_VALUE,
-                                  RWSEM_ACTIVE_WRITE_BIAS);
+        rwsem_count_t ret = cmpxchg(&sem->count,
+                                    RWSEM_UNLOCKED_VALUE,
+                                    RWSEM_ACTIVE_WRITE_BIAS);
         if (ret == RWSEM_UNLOCKED_VALUE)
                 return 1;
         return 0;
@@ -183,9 +195,9 @@ static inline int __down_write_trylock(struct rw_semaphore *sem)
  */
 static inline void __up_read(struct rw_semaphore *sem)
 {
-        __s32 tmp = -RWSEM_ACTIVE_READ_BIAS;
+        rwsem_count_t tmp = -RWSEM_ACTIVE_READ_BIAS;
         asm volatile("# beginning __up_read\n\t"
-                     LOCK_PREFIX "  xadd      %%edx,(%%eax)\n\t"
+                     LOCK_PREFIX "  xadd      %1,(%2)\n\t"
                      /* subtracts 1, returns the old value */
                      "  jns        1f\n\t"
                      "  call call_rwsem_wake\n"
@@ -201,18 +213,18 @@ static inline void __up_read(struct rw_semaphore *sem)
  */
 static inline void __up_write(struct rw_semaphore *sem)
 {
+        rwsem_count_t tmp;
         asm volatile("# beginning __up_write\n\t"
-                     "  movl      %2,%%edx\n\t"
-                     LOCK_PREFIX "  xaddl     %%edx,(%%eax)\n\t"
+                     LOCK_PREFIX "  xadd      %1,(%2)\n\t"
                      /* tries to transition
                         0xffff0001 -> 0x00000000 */
                      "  jz       1f\n"
                      "  call call_rwsem_wake\n"
                      "1:\n\t"
                      "# ending __up_write\n"
-                     : "+m" (sem->count)
-                     : "a" (sem), "i" (-RWSEM_ACTIVE_WRITE_BIAS)
-                     : "memory", "cc", "edx");
+                     : "+m" (sem->count), "=d" (tmp)
+                     : "a" (sem), "1" (-RWSEM_ACTIVE_WRITE_BIAS)
+                     : "memory", "cc");
 }
 
 /*
@@ -221,33 +233,38 @@ static inline void __up_write(struct rw_semaphore *sem)
 static inline void __downgrade_write(struct rw_semaphore *sem)
 {
         asm volatile("# beginning __downgrade_write\n\t"
-                     LOCK_PREFIX "  addl      %2,(%%eax)\n\t"
-                     /* transitions 0xZZZZ0001 -> 0xYYYY0001 */
+                     LOCK_PREFIX _ASM_ADD "%2,(%1)\n\t"
+                     /*
+                      * transitions 0xZZZZ0001 -> 0xYYYY0001 (i386)
+                      *     0xZZZZZZZZ00000001 -> 0xYYYYYYYY00000001 (x86_64)
+                      */
                      "  jns       1f\n\t"
                      "  call call_rwsem_downgrade_wake\n"
                      "1:\n\t"
                      "# ending __downgrade_write\n"
                      : "+m" (sem->count)
-                     : "a" (sem), "i" (-RWSEM_WAITING_BIAS)
+                     : "a" (sem), "er" (-RWSEM_WAITING_BIAS)
                      : "memory", "cc");
 }
 
 /*
  * implement atomic add functionality
  */
-static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
+static inline void rwsem_atomic_add(rwsem_count_t delta,
+                                    struct rw_semaphore *sem)
 {
-        asm volatile(LOCK_PREFIX "addl %1,%0"
+        asm volatile(LOCK_PREFIX _ASM_ADD "%1,%0"
                      : "+m" (sem->count)
-                     : "ir" (delta));
+                     : "er" (delta));
 }
 
 /*
  * implement exchange and add functionality
  */
-static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
+static inline rwsem_count_t rwsem_atomic_update(rwsem_count_t delta,
+                                                struct rw_semaphore *sem)
 {
-        int tmp = delta;
+        rwsem_count_t tmp = delta;
 
         asm volatile(LOCK_PREFIX "xadd %0,%1"
                      : "+r" (tmp), "+m" (sem->count)
diff --git a/arch/x86/include/asm/smp.h b/arch/x86/include/asm/smp.h
index 1e796782cd7b..4cfc90824068 100644
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -135,6 +135,8 @@ int native_cpu_disable(void);
 void native_cpu_die(unsigned int cpu);
 void native_play_dead(void);
 void play_dead_common(void);
+void wbinvd_on_cpu(int cpu);
+int wbinvd_on_all_cpus(void);
 
 void native_send_call_func_ipi(const struct cpumask *mask);
 void native_send_call_func_single_ipi(int cpu);
@@ -147,6 +149,13 @@ static inline int num_booting_cpus(void)
 {
         return cpumask_weight(cpu_callout_mask);
 }
+#else /* !CONFIG_SMP */
+#define wbinvd_on_cpu(cpu)     wbinvd()
+static inline int wbinvd_on_all_cpus(void)
+{
+        wbinvd();
+        return 0;
+}
 #endif /* CONFIG_SMP */
 
 extern unsigned disabled_cpus __cpuinitdata;
diff --git a/arch/x86/include/asm/stacktrace.h b/arch/x86/include/asm/stacktrace.h
index 35e89122a42f..4dab78edbad9 100644
--- a/arch/x86/include/asm/stacktrace.h
+++ b/arch/x86/include/asm/stacktrace.h
@@ -3,8 +3,6 @@
 
 extern int kstack_depth_to_print;
 
-int x86_is_stack_id(int id, char *name);
-
 struct thread_info;
 struct stacktrace_ops;
 
diff --git a/arch/x86/include/asm/syscall.h b/arch/x86/include/asm/syscall.h
index 8d33bc5462d1..c4a348f7bd43 100644
--- a/arch/x86/include/asm/syscall.h
+++ b/arch/x86/include/asm/syscall.h
@@ -16,6 +16,8 @@
 #include <linux/sched.h>
 #include <linux/err.h>
 
+extern const unsigned long sys_call_table[];
+
 /*
  * Only the low 32 bits of orig_ax are meaningful, so we return int.
  * This importantly ignores the high bits on 64-bit, so comparisons
diff --git a/arch/x86/include/asm/uaccess_64.h b/arch/x86/include/asm/uaccess_64.h
index 535e421498f6..316708d5af92 100644
--- a/arch/x86/include/asm/uaccess_64.h
+++ b/arch/x86/include/asm/uaccess_64.h
@@ -8,6 +8,8 @@
 #include <linux/errno.h>
 #include <linux/prefetch.h>
 #include <linux/lockdep.h>
+#include <asm/alternative.h>
+#include <asm/cpufeature.h>
 #include <asm/page.h>
 
 /*
@@ -16,7 +18,24 @@
 
 /* Handles exceptions in both to and from, but doesn't do access_ok */
 __must_check unsigned long
-copy_user_generic(void *to, const void *from, unsigned len);
+copy_user_generic_string(void *to, const void *from, unsigned len);
+__must_check unsigned long
+copy_user_generic_unrolled(void *to, const void *from, unsigned len);
+
+static __always_inline __must_check unsigned long
+copy_user_generic(void *to, const void *from, unsigned len)
+{
+        unsigned ret;
+
+        alternative_call(copy_user_generic_unrolled,
+                         copy_user_generic_string,
+                         X86_FEATURE_REP_GOOD,
+                         ASM_OUTPUT2("=a" (ret), "=D" (to), "=S" (from),
+                                     "=d" (len)),
+                         "1" (to), "2" (from), "3" (len)
+                         : "memory", "rcx", "r8", "r9", "r10", "r11");
+        return ret;
+}
 
 __must_check unsigned long
 _copy_to_user(void __user *to, const void *from, unsigned len);
diff --git a/arch/x86/include/asm/user.h b/arch/x86/include/asm/user.h
index 999873b22e7f..24532c7da3d6 100644
--- a/arch/x86/include/asm/user.h
+++ b/arch/x86/include/asm/user.h
@@ -1,5 +1,63 @@
+#ifndef _ASM_X86_USER_H
+#define _ASM_X86_USER_H
+
 #ifdef CONFIG_X86_32
 # include "user_32.h"
 #else
 # include "user_64.h"
 #endif
+
+#include <asm/types.h>
+
+struct user_ymmh_regs {
+        /* 16 * 16 bytes for each YMMH-reg */
+        __u32 ymmh_space[64];
+};
+
+struct user_xsave_hdr {
+        __u64 xstate_bv;
+        __u64 reserved1[2];
+        __u64 reserved2[5];
+};
+
+/*
+ * The structure layout of user_xstateregs, used for exporting the
+ * extended register state through ptrace and core-dump (NT_X86_XSTATE note)
+ * interfaces will be same as the memory layout of xsave used by the processor
+ * (except for the bytes 464..511, which can be used by the software) and hence
+ * the size of this structure varies depending on the features supported by the
+ * processor and OS. The size of the structure that users need to use can be
+ * obtained by doing:
+ *     cpuid_count(0xd, 0, &eax, &ptrace_xstateregs_struct_size, &ecx, &edx);
+ * i.e., cpuid.(eax=0xd,ecx=0).ebx will be the size that user (debuggers, etc.)
+ * need to use.
+ *
+ * For now, only the first 8 bytes of the software usable bytes[464..471] will
+ * be used and will be set to OS enabled xstate mask (which is same as the
+ * 64bit mask returned by the xgetbv's xCR0).  Users (analyzing core dump
+ * remotely, etc.) can use this mask as well as the mask saved in the
+ * xstate_hdr bytes and interpret what states the processor/OS supports
+ * and what states are in modified/initialized conditions for the
+ * particular process/thread.
+ *
+ * Also when the user modifies certain state FP/SSE/etc through the
+ * ptrace interface, they must ensure that the xsave_hdr.xstate_bv
+ * bytes[512..519] of the memory layout are updated correspondingly.
+ * i.e., for example when FP state is modified to a non-init state,
+ * xsave_hdr.xstate_bv's bit 0 must be set to '1', when SSE is modified to
+ * non-init state, xsave_hdr.xstate_bv's bit 1 must to be set to '1', etc.
+ */
+#define USER_XSTATE_FX_SW_WORDS 6
+#define USER_XSTATE_XCR0_WORD   0
+
+struct user_xstateregs {
+        struct {
+                __u64 fpx_space[58];
+                __u64 xstate_fx_sw[USER_XSTATE_FX_SW_WORDS];
+        } i387;
+        struct user_xsave_hdr xsave_hdr;
+        struct user_ymmh_regs ymmh;
+        /* further processor state extensions go here */
+};
+
+#endif /* _ASM_X86_USER_H */
diff --git a/arch/x86/include/asm/uv/bios.h b/arch/x86/include/asm/uv/bios.h
index 2751f3075d8b..71605c7d5c5c 100644
--- a/arch/x86/include/asm/uv/bios.h
+++ b/arch/x86/include/asm/uv/bios.h
@@ -18,8 +18,8 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  *
- *  Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
- *  Copyright (c) Russ Anderson
+ *  Copyright (c) 2008-2009 Silicon Graphics, Inc.  All Rights Reserved.
+ *  Copyright (c) Russ Anderson <rja@sgi.com>
  */
 
 #include <linux/rtc.h>
@@ -36,7 +36,8 @@ enum uv_bios_cmd {
         UV_BIOS_WATCHLIST_ALLOC,
         UV_BIOS_WATCHLIST_FREE,
         UV_BIOS_MEMPROTECT,
-        UV_BIOS_GET_PARTITION_ADDR
+        UV_BIOS_GET_PARTITION_ADDR,
+        UV_BIOS_SET_LEGACY_VGA_TARGET
 };
 
 /*
@@ -89,13 +90,14 @@ extern s64 uv_bios_call(enum uv_bios_cmd, u64, u64, u64, u64, u64);
 extern s64 uv_bios_call_irqsave(enum uv_bios_cmd, u64, u64, u64, u64, u64);
 extern s64 uv_bios_call_reentrant(enum uv_bios_cmd, u64, u64, u64, u64, u64);
 
-extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *);
+extern s64 uv_bios_get_sn_info(int, int *, long *, long *, long *, long *);
 extern s64 uv_bios_freq_base(u64, u64 *);
 extern int uv_bios_mq_watchlist_alloc(unsigned long, unsigned int,
                                         unsigned long *);
 extern int uv_bios_mq_watchlist_free(int, int);
 extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect);
 extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *);
+extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus);
 
 extern void uv_bios_init(void);
 
@@ -104,6 +106,7 @@ extern int uv_type;
 extern long sn_partition_id;
 extern long sn_coherency_id;
 extern long sn_region_size;
+extern long system_serial_number;
 #define partition_coherence_id()        (sn_coherency_id)
 
 extern struct kobject *sgi_uv_kobj;     /* /sys/firmware/sgi_uv */
diff --git a/arch/x86/include/asm/uv/uv.h b/arch/x86/include/asm/uv/uv.h
index c0a01b5d985b..3bb9491b7659 100644
--- a/arch/x86/include/asm/uv/uv.h
+++ b/arch/x86/include/asm/uv/uv.h
@@ -11,6 +11,7 @@ struct mm_struct;
 extern enum uv_system_type get_uv_system_type(void);
 extern int is_uv_system(void);
 extern void uv_cpu_init(void);
+extern void uv_nmi_init(void);
 extern void uv_system_init(void);
 extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
                                                  struct mm_struct *mm,
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 40be813fefb1..14cc74ba5d23 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -329,7 +329,8 @@ static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset
  */
 static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
 {
-        return UV_GLOBAL_GRU_MMR_BASE | offset | (pnode << uv_hub_info->m_val);
+        return UV_GLOBAL_GRU_MMR_BASE | offset |
+                ((unsigned long)pnode << uv_hub_info->m_val);
 }
 
 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index ea0e8ea15e15..60cc35269083 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -126,6 +126,7 @@ struct x86_cpuinit_ops {
  * @get_wallclock:              get time from HW clock like RTC etc.
  * @set_wallclock:              set time back to HW clock
  * @is_untracked_pat_range      exclude from PAT logic
+ * @nmi_init                    enable NMI on cpus
  */
 struct x86_platform_ops {
         unsigned long (*calibrate_tsc)(void);
@@ -133,6 +134,7 @@ struct x86_platform_ops {
         int (*set_wallclock)(unsigned long nowtime);
         void (*iommu_shutdown)(void);
         bool (*is_untracked_pat_range)(u64 start, u64 end);
+        void (*nmi_init)(void);
 };
 
 extern struct x86_init_ops x86_init;
diff --git a/arch/x86/include/asm/xsave.h b/arch/x86/include/asm/xsave.h
index 727acc152344..ddc04ccad03b 100644
--- a/arch/x86/include/asm/xsave.h
+++ b/arch/x86/include/asm/xsave.h
@@ -27,9 +27,11 @@
 extern unsigned int xstate_size;
 extern u64 pcntxt_mask;
 extern struct xsave_struct *init_xstate_buf;
+extern u64 xstate_fx_sw_bytes[USER_XSTATE_FX_SW_WORDS];
 
 extern void xsave_cntxt_init(void);
 extern void xsave_init(void);
+extern void update_regset_xstate_info(unsigned int size, u64 xstate_mask);
 extern int init_fpu(struct task_struct *child);
 extern int check_for_xstate(struct i387_fxsave_struct __user *buf,
                             void __user *fpstate,
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 0acbcdfa5ca4..f95703098f8d 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -49,6 +49,7 @@ EXPORT_SYMBOL(acpi_disabled);
 
 #ifdef  CONFIG_X86_64
 # include <asm/proto.h>
+# include <asm/numa_64.h>
 #endif                          /* X86 */
 
 #define BAD_MADT_ENTRY(entry, end) (                                        \
@@ -482,6 +483,25 @@ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
  */
 #ifdef CONFIG_ACPI_HOTPLUG_CPU
 
+static void acpi_map_cpu2node(acpi_handle handle, int cpu, int physid)
+{
+#ifdef CONFIG_ACPI_NUMA
+        int nid;
+
+        nid = acpi_get_node(handle);
+        if (nid == -1 || !node_online(nid))
+                return;
+#ifdef CONFIG_X86_64
+        apicid_to_node[physid] = nid;
+        numa_set_node(cpu, nid);
+#else /* CONFIG_X86_32 */
+        apicid_2_node[physid] = nid;
+        cpu_to_node_map[cpu] = nid;
+#endif
+
+#endif
+}
+
 static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu)
 {
         struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
@@ -540,6 +560,7 @@ static int __cpuinit _acpi_map_lsapic(acpi_handle handle, int *pcpu)
         }
 
         cpu = cpumask_first(new_map);
+        acpi_map_cpu2node(handle, cpu, physid);
 
         *pcpu = cpu;
         retval = 0;
@@ -1344,14 +1365,6 @@ static struct dmi_system_id __initdata acpi_dmi_table[] = {
          },
         {
          .callback = force_acpi_ht,
-         .ident = "ASUS P2B-DS",
-         .matches = {
-                     DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
-                     DMI_MATCH(DMI_BOARD_NAME, "P2B-DS"),
-                     },
-         },
-        {
-         .callback = force_acpi_ht,
          .ident = "ASUS CUR-DLS",
          .matches = {
                      DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index de7353c0ce9c..e6ea0342c8f8 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -205,7 +205,7 @@ void __init_or_module apply_alternatives(struct alt_instr *start,
                                          struct alt_instr *end)
 {
         struct alt_instr *a;
-        char insnbuf[MAX_PATCH_LEN];
+        u8 insnbuf[MAX_PATCH_LEN];
 
         DPRINTK("%s: alt table %p -> %p\n", __func__, start, end);
         for (a = start; a < end; a++) {
@@ -223,6 +223,8 @@ void __init_or_module apply_alternatives(struct alt_instr *start,
                 }
 #endif
                 memcpy(insnbuf, a->replacement, a->replacementlen);
+                if (*insnbuf == 0xe8 && a->replacementlen == 5)
+                    *(s32 *)(insnbuf + 1) += a->replacement - a->instr;
                 add_nops(insnbuf + a->replacementlen,
                          a->instrlen - a->replacementlen);
                 text_poke_early(instr, insnbuf, a->instrlen);
@@ -390,6 +392,24 @@ void alternatives_smp_switch(int smp)
         mutex_unlock(&smp_alt);
 }
 
+/* Return 1 if the address range is reserved for smp-alternatives */
+int alternatives_text_reserved(void *start, void *end)
+{
+        struct smp_alt_module *mod;
+        u8 **ptr;
+        u8 *text_start = start;
+        u8 *text_end = end;
+
+        list_for_each_entry(mod, &smp_alt_modules, next) {
+                if (mod->text > text_end || mod->text_end < text_start)
+                        continue;
+                for (ptr = mod->locks; ptr < mod->locks_end; ptr++)
+                        if (text_start <= *ptr && text_end >= *ptr)
+                                return 1;
+        }
+
+        return 0;
+}
 #endif
 
 #ifdef CONFIG_PARAVIRT
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index dfca210f6a10..6e29b2a77aa8 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -581,7 +581,7 @@ calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
                 res = (((u64)(*deltatsc)) * pm_100ms);
                 do_div(res, deltapm);
                 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
-                                          "PM-Timer: %lu (%ld) \n",
+                                          "PM-Timer: %lu (%ld)\n",
                                         (unsigned long)res, *deltatsc);
                 *deltatsc = (long)res;
         }
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 53243ca7816d..6bdd2c7ead75 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1647,7 +1647,7 @@ __apicdebuginit(void) print_IO_APIC(void)
         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 
         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
-                          " Stat Dmod Deli Vect:   \n");
+                          " Stat Dmod Deli Vect:\n");
 
         for (i = 0; i <= reg_01.bits.entries; i++) {
                 struct IO_APIC_route_entry entry;
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
index 98c4665f251c..47dd856708e5 100644
--- a/arch/x86/kernel/apic/numaq_32.c
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -225,7 +225,7 @@ static void __init smp_read_mpc_oem(struct mpc_table *mpc)
 
         mpc_record = 0;
         printk(KERN_INFO
-                "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
+                "Found an OEM MPC table at %8p - parsing it...\n", oemtable);
 
         if (memcmp(oemtable->signature, MPC_OEM_SIGNATURE, 4)) {
                 printk(KERN_WARNING
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 21db3cbea7dc..3740c8a4eae7 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -5,7 +5,7 @@
  *
  * SGI UV APIC functions (note: not an Intel compatible APIC)
  *
- * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2009 Silicon Graphics, Inc. All rights reserved.
  */
 #include <linux/cpumask.h>
 #include <linux/hardirq.h>
@@ -20,6 +20,8 @@
 #include <linux/cpu.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/pci.h>
+#include <linux/kdebug.h>
 
 #include <asm/uv/uv_mmrs.h>
 #include <asm/uv/uv_hub.h>
@@ -34,10 +36,13 @@
 
 DEFINE_PER_CPU(int, x2apic_extra_bits);
 
+#define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
+
 static enum uv_system_type uv_system_type;
 static u64 gru_start_paddr, gru_end_paddr;
 int uv_min_hub_revision_id;
 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
+static DEFINE_SPINLOCK(uv_nmi_lock);
 
 static inline bool is_GRU_range(u64 start, u64 end)
 {
@@ -71,6 +76,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
         if (!strcmp(oem_id, "SGI")) {
                 nodeid = early_get_nodeid();
                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
+                x86_platform.nmi_init = uv_nmi_init;
                 if (!strcmp(oem_table_id, "UVL"))
                         uv_system_type = UV_LEGACY_APIC;
                 else if (!strcmp(oem_table_id, "UVX"))
@@ -482,7 +488,7 @@ static void uv_heartbeat(unsigned long ignored)
 
 static void __cpuinit uv_heartbeat_enable(int cpu)
 {
-        if (!uv_cpu_hub_info(cpu)->scir.enabled) {
+        while (!uv_cpu_hub_info(cpu)->scir.enabled) {
                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 
                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
@@ -490,11 +496,10 @@ static void __cpuinit uv_heartbeat_enable(int cpu)
                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
                 add_timer_on(timer, cpu);
                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
-        }
 
-        /* check boot cpu */
-        if (!uv_cpu_hub_info(0)->scir.enabled)
-                uv_heartbeat_enable(0);
+                /* also ensure that boot cpu is enabled */
+                cpu = 0;
+        }
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
@@ -553,6 +558,30 @@ late_initcall(uv_init_heartbeat);
 
 #endif /* !CONFIG_HOTPLUG_CPU */
 
+/* Direct Legacy VGA I/O traffic to designated IOH */
+int uv_set_vga_state(struct pci_dev *pdev, bool decode,
+                      unsigned int command_bits, bool change_bridge)
+{
+        int domain, bus, rc;
+
+        PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
+                        pdev->devfn, decode, command_bits, change_bridge);
+
+        if (!change_bridge)
+                return 0;
+
+        if ((command_bits & PCI_COMMAND_IO) == 0)
+                return 0;
+
+        domain = pci_domain_nr(pdev->bus);
+        bus = pdev->bus->number;
+
+        rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
+        PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
+
+        return rc;
+}
+
 /*
  * Called on each cpu to initialize the per_cpu UV data area.
  * FIXME: hotplug not supported yet
@@ -569,6 +598,46 @@ void __cpuinit uv_cpu_init(void)
                 set_x2apic_extra_bits(uv_hub_info->pnode);
 }
 
+/*
+ * When NMI is received, print a stack trace.
+ */
+int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
+{
+        if (reason != DIE_NMI_IPI)
+                return NOTIFY_OK;
+        /*
+         * Use a lock so only one cpu prints at a time
+         * to prevent intermixed output.
+         */
+        spin_lock(&uv_nmi_lock);
+        pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
+        dump_stack();
+        spin_unlock(&uv_nmi_lock);
+
+        return NOTIFY_STOP;
+}
+
+static struct notifier_block uv_dump_stack_nmi_nb = {
+        .notifier_call  = uv_handle_nmi
+};
+
+void uv_register_nmi_notifier(void)
+{
+        if (register_die_notifier(&uv_dump_stack_nmi_nb))
+                printk(KERN_WARNING "UV NMI handler failed to register\n");
+}
+
+void uv_nmi_init(void)
+{
+        unsigned int value;
+
+        /*
+         * Unmask NMI on all cpus
+         */
+        value = apic_read(APIC_LVT1) | APIC_DM_NMI;
+        value &= ~APIC_LVT_MASKED;
+        apic_write(APIC_LVT1, value);
+}
 
 void __init uv_system_init(void)
 {
@@ -634,8 +703,8 @@ void __init uv_system_init(void)
         }
 
         uv_bios_init();
-        uv_bios_get_sn_info(0, &uv_type, &sn_partition_id,
-                            &sn_coherency_id, &sn_region_size);
+        uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
+                            &sn_region_size, &system_serial_number);
         uv_rtc_init();
 
         for_each_present_cpu(cpu) {
@@ -690,5 +759,9 @@ void __init uv_system_init(void)
 
         uv_cpu_init();
         uv_scir_register_cpu_notifier();
+        uv_register_nmi_notifier();
         proc_mkdir("sgi_uv", NULL);
+
+        /* register Legacy VGA I/O redirection handler */
+        pci_register_set_vga_state(uv_set_vga_state);
 }
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index b5b6b23bce53..031aa887b0eb 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -1992,8 +1992,8 @@ static int __init apm_is_horked_d850md(const struct dmi_system_id *d)
                 apm_info.disabled = 1;
                 printk(KERN_INFO "%s machine detected. "
                        "Disabling APM.\n", d->ident);
-                printk(KERN_INFO "This bug is fixed in bios P15 which is available for \n");
-                printk(KERN_INFO "download from support.intel.com \n");
+                printk(KERN_INFO "This bug is fixed in bios P15 which is available for\n");
+                printk(KERN_INFO "download from support.intel.com\n");
         }
         return 0;
 }
diff --git a/arch/x86/kernel/bios_uv.c b/arch/x86/kernel/bios_uv.c
index b0206a211b09..8bc57baaa9ad 100644
--- a/arch/x86/kernel/bios_uv.c
+++ b/arch/x86/kernel/bios_uv.c
@@ -15,8 +15,8 @@
  *  along with this program; if not, write to the Free Software
  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  *
- *  Copyright (c) 2008 Silicon Graphics, Inc.  All Rights Reserved.
- *  Copyright (c) Russ Anderson
+ *  Copyright (c) 2008-2009 Silicon Graphics, Inc.  All Rights Reserved.
+ *  Copyright (c) Russ Anderson <rja@sgi.com>
  */
 
 #include <linux/efi.h>
@@ -30,6 +30,7 @@ static struct uv_systab uv_systab;
 s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
 {
         struct uv_systab *tab = &uv_systab;
+        s64 ret;
 
         if (!tab->function)
                 /*
@@ -37,9 +38,11 @@ s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
                  */
                 return BIOS_STATUS_UNIMPLEMENTED;
 
-        return efi_call6((void *)__va(tab->function),
-                                        (u64)which, a1, a2, a3, a4, a5);
+        ret = efi_call6((void *)__va(tab->function), (u64)which,
+                        a1, a2, a3, a4, a5);
+        return ret;
 }
+EXPORT_SYMBOL_GPL(uv_bios_call);
 
 s64 uv_bios_call_irqsave(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3,
                                         u64 a4, u64 a5)
@@ -73,11 +76,14 @@ long sn_coherency_id;
 EXPORT_SYMBOL_GPL(sn_coherency_id);
 long sn_region_size;
 EXPORT_SYMBOL_GPL(sn_region_size);
+long system_serial_number;
+EXPORT_SYMBOL_GPL(system_serial_number);
 int uv_type;
+EXPORT_SYMBOL_GPL(uv_type);
 
 
 s64 uv_bios_get_sn_info(int fc, int *uvtype, long *partid, long *coher,
-                long *region)
+                long *region, long *ssn)
 {
         s64 ret;
         u64 v0, v1;
@@ -97,8 +103,11 @@ s64 uv_bios_get_sn_info(int fc, int *uvtype, long *partid, long *coher,
                 *coher = part.coherence_id;
         if (region)
                 *region = part.region_size;
+        if (ssn)
+                *ssn = v1;
         return ret;
 }
+EXPORT_SYMBOL_GPL(uv_bios_get_sn_info);
 
 int
 uv_bios_mq_watchlist_alloc(unsigned long addr, unsigned int mq_size,
@@ -154,6 +163,25 @@ s64 uv_bios_freq_base(u64 clock_type, u64 *ticks_per_second)
 }
 EXPORT_SYMBOL_GPL(uv_bios_freq_base);
 
+/*
+ * uv_bios_set_legacy_vga_target - Set Legacy VGA I/O Target
+ * @decode: true to enable target, false to disable target
+ * @domain: PCI domain number
+ * @bus: PCI bus number
+ *
+ * Returns:
+ *    0: Success
+ *    -EINVAL: Invalid domain or bus number
+ *    -ENOSYS: Capability not available
+ *    -EBUSY: Legacy VGA I/O cannot be retargeted at this time
+ */
+int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus)
+{
+        return uv_bios_call(UV_BIOS_SET_LEGACY_VGA_TARGET,
+                                (u64)decode, (u64)domain, (u64)bus, 0, 0);
+}
+EXPORT_SYMBOL_GPL(uv_bios_set_legacy_vga_target);
+
 
 #ifdef CONFIG_EFI
 void uv_bios_init(void)
@@ -185,4 +213,3 @@ void uv_bios_init(void)
 
 void uv_bios_init(void) { }
 #endif
-
diff --git a/arch/x86/kernel/cpu/addon_cpuid_features.c b/arch/x86/kernel/cpu/addon_cpuid_features.c
index 468489b57aae..97ad79cdf688 100644
--- a/arch/x86/kernel/cpu/addon_cpuid_features.c
+++ b/arch/x86/kernel/cpu/addon_cpuid_features.c
@@ -32,6 +32,10 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
         static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
                 { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
                 { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 },
+                { X86_FEATURE_NPT,   CR_EDX, 0, 0x8000000a },
+                { X86_FEATURE_LBRV,  CR_EDX, 1, 0x8000000a },
+                { X86_FEATURE_SVML,  CR_EDX, 2, 0x8000000a },
+                { X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a },
                 { 0, 0, 0, 0 }
         };
 
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index fc6c8ef92dcc..eddb1bdd1b8f 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -18,6 +18,7 @@
 #include <asm/processor.h>
 #include <linux/smp.h>
 #include <asm/k8.h>
+#include <asm/smp.h>
 
 #define LVL_1_INST      1
 #define LVL_1_DATA      2
@@ -31,6 +32,8 @@ struct _cache_table {
         short size;
 };
 
+#define MB(x)   ((x) * 1024)
+
 /* All the cache descriptor types we care about (no TLB or
    trace cache entries) */
 
@@ -44,9 +47,9 @@ static const struct _cache_table __cpuinitconst cache_table[] =
         { 0x0d, LVL_1_DATA, 16 },       /* 4-way set assoc, 64 byte line size */
         { 0x21, LVL_2,      256 },      /* 8-way set assoc, 64 byte line size */
         { 0x22, LVL_3,      512 },      /* 4-way set assoc, sectored cache, 64 byte line size */
-        { 0x23, LVL_3,      1024 },     /* 8-way set assoc, sectored cache, 64 byte line size */
-        { 0x25, LVL_3,      2048 },     /* 8-way set assoc, sectored cache, 64 byte line size */
-        { 0x29, LVL_3,      4096 },     /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x23, LVL_3,      MB(1) },    /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x25, LVL_3,      MB(2) },    /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x29, LVL_3,      MB(4) },    /* 8-way set assoc, sectored cache, 64 byte line size */
         { 0x2c, LVL_1_DATA, 32 },       /* 8-way set assoc, 64 byte line size */
         { 0x30, LVL_1_INST, 32 },       /* 8-way set assoc, 64 byte line size */
         { 0x39, LVL_2,      128 },      /* 4-way set assoc, sectored cache, 64 byte line size */
@@ -59,16 +62,16 @@ static const struct _cache_table __cpuinitconst cache_table[] =
         { 0x41, LVL_2,      128 },      /* 4-way set assoc, 32 byte line size */
         { 0x42, LVL_2,      256 },      /* 4-way set assoc, 32 byte line size */
         { 0x43, LVL_2,      512 },      /* 4-way set assoc, 32 byte line size */
-        { 0x44, LVL_2,      1024 },     /* 4-way set assoc, 32 byte line size */
-        { 0x45, LVL_2,      2048 },     /* 4-way set assoc, 32 byte line size */
-        { 0x46, LVL_3,      4096 },     /* 4-way set assoc, 64 byte line size */
-        { 0x47, LVL_3,      8192 },     /* 8-way set assoc, 64 byte line size */
-        { 0x49, LVL_3,      4096 },     /* 16-way set assoc, 64 byte line size */
-        { 0x4a, LVL_3,      6144 },     /* 12-way set assoc, 64 byte line size */
-        { 0x4b, LVL_3,      8192 },     /* 16-way set assoc, 64 byte line size */
-        { 0x4c, LVL_3,     12288 },     /* 12-way set assoc, 64 byte line size */
-        { 0x4d, LVL_3,     16384 },     /* 16-way set assoc, 64 byte line size */
-        { 0x4e, LVL_2,      6144 },     /* 24-way set assoc, 64 byte line size */
+        { 0x44, LVL_2,      MB(1) },    /* 4-way set assoc, 32 byte line size */
+        { 0x45, LVL_2,      MB(2) },    /* 4-way set assoc, 32 byte line size */
+        { 0x46, LVL_3,      MB(4) },    /* 4-way set assoc, 64 byte line size */
+        { 0x47, LVL_3,      MB(8) },    /* 8-way set assoc, 64 byte line size */
+        { 0x49, LVL_3,      MB(4) },    /* 16-way set assoc, 64 byte line size */
+        { 0x4a, LVL_3,      MB(6) },    /* 12-way set assoc, 64 byte line size */
+        { 0x4b, LVL_3,      MB(8) },    /* 16-way set assoc, 64 byte line size */
+        { 0x4c, LVL_3,      MB(12) },   /* 12-way set assoc, 64 byte line size */
+        { 0x4d, LVL_3,      MB(16) },   /* 16-way set assoc, 64 byte line size */
+        { 0x4e, LVL_2,      MB(6) },    /* 24-way set assoc, 64 byte line size */
         { 0x60, LVL_1_DATA, 16 },       /* 8-way set assoc, sectored cache, 64 byte line size */
         { 0x66, LVL_1_DATA, 8 },        /* 4-way set assoc, sectored cache, 64 byte line size */
         { 0x67, LVL_1_DATA, 16 },       /* 4-way set assoc, sectored cache, 64 byte line size */
@@ -77,34 +80,34 @@ static const struct _cache_table __cpuinitconst cache_table[] =
         { 0x71, LVL_TRACE,  16 },       /* 8-way set assoc */
         { 0x72, LVL_TRACE,  32 },       /* 8-way set assoc */
         { 0x73, LVL_TRACE,  64 },       /* 8-way set assoc */
-        { 0x78, LVL_2,    1024 },       /* 4-way set assoc, 64 byte line size */
-        { 0x79, LVL_2,     128 },       /* 8-way set assoc, sectored cache, 64 byte line size */
-        { 0x7a, LVL_2,     256 },       /* 8-way set assoc, sectored cache, 64 byte line size */
-        { 0x7b, LVL_2,     512 },       /* 8-way set assoc, sectored cache, 64 byte line size */
-        { 0x7c, LVL_2,    1024 },       /* 8-way set assoc, sectored cache, 64 byte line size */
-        { 0x7d, LVL_2,    2048 },       /* 8-way set assoc, 64 byte line size */
-        { 0x7f, LVL_2,     512 },       /* 2-way set assoc, 64 byte line size */
-        { 0x82, LVL_2,     256 },       /* 8-way set assoc, 32 byte line size */
-        { 0x83, LVL_2,     512 },       /* 8-way set assoc, 32 byte line size */
-        { 0x84, LVL_2,    1024 },       /* 8-way set assoc, 32 byte line size */
-        { 0x85, LVL_2,    2048 },       /* 8-way set assoc, 32 byte line size */
-        { 0x86, LVL_2,     512 },       /* 4-way set assoc, 64 byte line size */
-        { 0x87, LVL_2,    1024 },       /* 8-way set assoc, 64 byte line size */
-        { 0xd0, LVL_3,     512 },       /* 4-way set assoc, 64 byte line size */
-        { 0xd1, LVL_3,    1024 },       /* 4-way set assoc, 64 byte line size */
-        { 0xd2, LVL_3,    2048 },       /* 4-way set assoc, 64 byte line size */
-        { 0xd6, LVL_3,    1024 },       /* 8-way set assoc, 64 byte line size */
-        { 0xd7, LVL_3,    2048 },       /* 8-way set assoc, 64 byte line size */
-        { 0xd8, LVL_3,    4096 },       /* 12-way set assoc, 64 byte line size */
-        { 0xdc, LVL_3,    2048 },       /* 12-way set assoc, 64 byte line size */
-        { 0xdd, LVL_3,    4096 },       /* 12-way set assoc, 64 byte line size */
-        { 0xde, LVL_3,    8192 },       /* 12-way set assoc, 64 byte line size */
-        { 0xe2, LVL_3,    2048 },       /* 16-way set assoc, 64 byte line size */
-        { 0xe3, LVL_3,    4096 },       /* 16-way set assoc, 64 byte line size */
-        { 0xe4, LVL_3,    8192 },       /* 16-way set assoc, 64 byte line size */
-        { 0xea, LVL_3,    12288 },      /* 24-way set assoc, 64 byte line size */
-        { 0xeb, LVL_3,    18432 },      /* 24-way set assoc, 64 byte line size */
-        { 0xec, LVL_3,    24576 },      /* 24-way set assoc, 64 byte line size */
+        { 0x78, LVL_2,      MB(1) },    /* 4-way set assoc, 64 byte line size */
+        { 0x79, LVL_2,      128 },      /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x7a, LVL_2,      256 },      /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x7b, LVL_2,      512 },      /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x7c, LVL_2,      MB(1) },    /* 8-way set assoc, sectored cache, 64 byte line size */
+        { 0x7d, LVL_2,      MB(2) },    /* 8-way set assoc, 64 byte line size */
+        { 0x7f, LVL_2,      512 },      /* 2-way set assoc, 64 byte line size */
+        { 0x82, LVL_2,      256 },      /* 8-way set assoc, 32 byte line size */
+        { 0x83, LVL_2,      512 },      /* 8-way set assoc, 32 byte line size */
+        { 0x84, LVL_2,      MB(1) },    /* 8-way set assoc, 32 byte line size */
+        { 0x85, LVL_2,      MB(2) },    /* 8-way set assoc, 32 byte line size */
+        { 0x86, LVL_2,      512 },      /* 4-way set assoc, 64 byte line size */
+        { 0x87, LVL_2,      MB(1) },    /* 8-way set assoc, 64 byte line size */
+        { 0xd0, LVL_3,      512 },      /* 4-way set assoc, 64 byte line size */
+        { 0xd1, LVL_3,      MB(1) },    /* 4-way set assoc, 64 byte line size */
+        { 0xd2, LVL_3,      MB(2) },    /* 4-way set assoc, 64 byte line size */
+        { 0xd6, LVL_3,      MB(1) },    /* 8-way set assoc, 64 byte line size */
+        { 0xd7, LVL_3,      MB(2) },    /* 8-way set assoc, 64 byte line size */
+        { 0xd8, LVL_3,      MB(4) },    /* 12-way set assoc, 64 byte line size */
+        { 0xdc, LVL_3,      MB(2) },    /* 12-way set assoc, 64 byte line size */
+        { 0xdd, LVL_3,      MB(4) },    /* 12-way set assoc, 64 byte line size */
+        { 0xde, LVL_3,      MB(8) },    /* 12-way set assoc, 64 byte line size */
+        { 0xe2, LVL_3,      MB(2) },    /* 16-way set assoc, 64 byte line size */
+        { 0xe3, LVL_3,      MB(4) },    /* 16-way set assoc, 64 byte line size */
+        { 0xe4, LVL_3,      MB(8) },    /* 16-way set assoc, 64 byte line size */
+        { 0xea, LVL_3,      MB(12) },   /* 24-way set assoc, 64 byte line size */
+        { 0xeb, LVL_3,      MB(18) },   /* 24-way set assoc, 64 byte line size */
+        { 0xec, LVL_3,      MB(24) },   /* 24-way set assoc, 64 byte line size */
         { 0x00, 0, 0}
 };
 
@@ -150,7 +153,8 @@ struct _cpuid4_info {
         union _cpuid4_leaf_ebx ebx;
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
-        unsigned long can_disable;
+        bool can_disable;
+        unsigned int l3_indices;
         DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
 };
 
@@ -160,7 +164,8 @@ struct _cpuid4_info_regs {
         union _cpuid4_leaf_ebx ebx;
         union _cpuid4_leaf_ecx ecx;
         unsigned long size;
-        unsigned long can_disable;
+        bool can_disable;
+        unsigned int l3_indices;
 };
 
 unsigned short                  num_cache_leaves;
@@ -290,6 +295,36 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
                 (ebx->split.ways_of_associativity + 1) - 1;
 }
 
+struct _cache_attr {
+        struct attribute attr;
+        ssize_t (*show)(struct _cpuid4_info *, char *);
+        ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
+};
+
+#ifdef CONFIG_CPU_SUP_AMD
+static unsigned int __cpuinit amd_calc_l3_indices(void)
+{
+        /*
+         * We're called over smp_call_function_single() and therefore
+         * are on the correct cpu.
+         */
+        int cpu = smp_processor_id();
+        int node = cpu_to_node(cpu);
+        struct pci_dev *dev = node_to_k8_nb_misc(node);
+        unsigned int sc0, sc1, sc2, sc3;
+        u32 val = 0;
+
+        pci_read_config_dword(dev, 0x1C4, &val);
+
+        /* calculate subcache sizes */
+        sc0 = !(val & BIT(0));
+        sc1 = !(val & BIT(4));
+        sc2 = !(val & BIT(8))  + !(val & BIT(9));
+        sc3 = !(val & BIT(12)) + !(val & BIT(13));
+
+        return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
+}
+
 static void __cpuinit
 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
 {
@@ -299,12 +334,103 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
         if (boot_cpu_data.x86 == 0x11)
                 return;
 
-        /* see erratum #382 */
-        if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
+        /* see errata #382 and #388 */
+        if ((boot_cpu_data.x86 == 0x10) &&
+            ((boot_cpu_data.x86_model < 0x8) ||
+             (boot_cpu_data.x86_mask  < 0x1)))
                 return;
 
-        this_leaf->can_disable = 1;
+        this_leaf->can_disable = true;
+        this_leaf->l3_indices  = amd_calc_l3_indices();
+}
+
+static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
+                                  unsigned int index)
+{
+        int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+        int node = amd_get_nb_id(cpu);
+        struct pci_dev *dev = node_to_k8_nb_misc(node);
+        unsigned int reg = 0;
+
+        if (!this_leaf->can_disable)
+                return -EINVAL;
+
+        if (!dev)
+                return -EINVAL;
+
+        pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
+        return sprintf(buf, "0x%08x\n", reg);
+}
+
+#define SHOW_CACHE_DISABLE(index)                                       \
+static ssize_t                                                          \
+show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)   \
+{                                                                       \
+        return show_cache_disable(this_leaf, buf, index);               \
 }
+SHOW_CACHE_DISABLE(0)
+SHOW_CACHE_DISABLE(1)
+
+static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
+        const char *buf, size_t count, unsigned int index)
+{
+        int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
+        int node = amd_get_nb_id(cpu);
+        struct pci_dev *dev = node_to_k8_nb_misc(node);
+        unsigned long val = 0;
+
+#define SUBCACHE_MASK   (3UL << 20)
+#define SUBCACHE_INDEX  0xfff
+
+        if (!this_leaf->can_disable)
+                return -EINVAL;
+
+        if (!capable(CAP_SYS_ADMIN))
+                return -EPERM;
+
+        if (!dev)
+                return -EINVAL;
+
+        if (strict_strtoul(buf, 10, &val) < 0)
+                return -EINVAL;
+
+        /* do not allow writes outside of allowed bits */
+        if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
+            ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
+                return -EINVAL;
+
+        val |= BIT(30);
+        pci_write_config_dword(dev, 0x1BC + index * 4, val);
+        /*
+         * We need to WBINVD on a core on the node containing the L3 cache which
+         * indices we disable therefore a simple wbinvd() is not sufficient.
+         */
+        wbinvd_on_cpu(cpu);
+        pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
+        return count;
+}
+
+#define STORE_CACHE_DISABLE(index)                                      \
+static ssize_t                                                          \
+store_cache_disable_##index(struct _cpuid4_info *this_leaf,             \
+                            const char *buf, size_t count)              \
+{                                                                       \
+        return store_cache_disable(this_leaf, buf, count, index);       \
+}
+STORE_CACHE_DISABLE(0)
+STORE_CACHE_DISABLE(1)
+
+static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
+                show_cache_disable_0, store_cache_disable_0);
+static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
+                show_cache_disable_1, store_cache_disable_1);
+
+#else   /* CONFIG_CPU_SUP_AMD */
+static void __cpuinit
+amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
+{
+};
+#endif /* CONFIG_CPU_SUP_AMD */
 
 static int
 __cpuinit cpuid4_cache_lookup_regs(int index,
@@ -711,82 +837,6 @@ static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
 #define to_object(k)    container_of(k, struct _index_kobject, kobj)
 #define to_attr(a)      container_of(a, struct _cache_attr, attr)
 
-static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
-                                  unsigned int index)
-{
-        int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-        int node = cpu_to_node(cpu);
-        struct pci_dev *dev = node_to_k8_nb_misc(node);
-        unsigned int reg = 0;
-
-        if (!this_leaf->can_disable)
-                return -EINVAL;
-
-        if (!dev)
-                return -EINVAL;
-
-        pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
-        return sprintf(buf, "%x\n", reg);
-}
-
-#define SHOW_CACHE_DISABLE(index)                                       \
-static ssize_t                                                          \
-show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf)   \
-{                                                                       \
-        return show_cache_disable(this_leaf, buf, index);               \
-}
-SHOW_CACHE_DISABLE(0)
-SHOW_CACHE_DISABLE(1)
-
-static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
-        const char *buf, size_t count, unsigned int index)
-{
-        int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
-        int node = cpu_to_node(cpu);
-        struct pci_dev *dev = node_to_k8_nb_misc(node);
-        unsigned long val = 0;
-        unsigned int scrubber = 0;
-
-        if (!this_leaf->can_disable)
-                return -EINVAL;
-
-        if (!capable(CAP_SYS_ADMIN))
-                return -EPERM;
-
-        if (!dev)
-                return -EINVAL;
-
-        if (strict_strtoul(buf, 10, &val) < 0)
-                return -EINVAL;
-
-        val |= 0xc0000000;
-
-        pci_read_config_dword(dev, 0x58, &scrubber);
-        scrubber &= ~0x1f000000;
-        pci_write_config_dword(dev, 0x58, scrubber);
-
-        pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
-        wbinvd();
-        pci_write_config_dword(dev, 0x1BC + index * 4, val);
-        return count;
-}
-
-#define STORE_CACHE_DISABLE(index)                                      \
-static ssize_t                                                          \
-store_cache_disable_##index(struct _cpuid4_info *this_leaf,             \
-                            const char *buf, size_t count)              \
-{                                                                       \
-        return store_cache_disable(this_leaf, buf, count, index);       \
-}
-STORE_CACHE_DISABLE(0)
-STORE_CACHE_DISABLE(1)
-
-struct _cache_attr {
-        struct attribute attr;
-        ssize_t (*show)(struct _cpuid4_info *, char *);
-        ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
-};
-
 #define define_one_ro(_name) \
 static struct _cache_attr _name = \
         __ATTR(_name, 0444, show_##_name, NULL)
@@ -801,23 +851,28 @@ define_one_ro(size);
 define_one_ro(shared_cpu_map);
 define_one_ro(shared_cpu_list);
 
-static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
-                show_cache_disable_0, store_cache_disable_0);
-static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
-                show_cache_disable_1, store_cache_disable_1);
+#define DEFAULT_SYSFS_CACHE_ATTRS       \
+        &type.attr,                     \
+        &level.attr,                    \
+        &coherency_line_size.attr,      \
+        &physical_line_partition.attr,  \
+        &ways_of_associativity.attr,    \
+        &number_of_sets.attr,           \
+        &size.attr,                     \
+        &shared_cpu_map.attr,           \
+        &shared_cpu_list.attr
 
 static struct attribute *default_attrs[] = {
-        &type.attr,
-        &level.attr,
-        &coherency_line_size.attr,
-        &physical_line_partition.attr,
-        &ways_of_associativity.attr,
-        &number_of_sets.attr,
-        &size.attr,
-        &shared_cpu_map.attr,
-        &shared_cpu_list.attr,
+        DEFAULT_SYSFS_CACHE_ATTRS,
+        NULL
+};
+
+static struct attribute *default_l3_attrs[] = {
+        DEFAULT_SYSFS_CACHE_ATTRS,
+#ifdef CONFIG_CPU_SUP_AMD
         &cache_disable_0.attr,
         &cache_disable_1.attr,
+#endif
         NULL
 };
 
@@ -908,6 +963,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
         unsigned int cpu = sys_dev->id;
         unsigned long i, j;
         struct _index_kobject *this_object;
+        struct _cpuid4_info   *this_leaf;
         int retval;
 
         retval = cpuid4_cache_sysfs_init(cpu);
@@ -926,6 +982,14 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
                 this_object = INDEX_KOBJECT_PTR(cpu, i);
                 this_object->cpu = cpu;
                 this_object->index = i;
+
+                this_leaf = CPUID4_INFO_IDX(cpu, i);
+
+                if (this_leaf->can_disable)
+                        ktype_cache.default_attrs = default_l3_attrs;
+                else
+                        ktype_cache.default_attrs = default_attrs;
+
                 retval = kobject_init_and_add(&(this_object->kobj),
                                               &ktype_cache,
                                               per_cpu(ici_cache_kobject, cpu),
diff --git a/arch/x86/kernel/cpu/mtrr/Makefile b/arch/x86/kernel/cpu/mtrr/Makefile
index f4361b56f8e9..ad9e5ed81181 100644
--- a/arch/x86/kernel/cpu/mtrr/Makefile
+++ b/arch/x86/kernel/cpu/mtrr/Makefile
@@ -1,3 +1,3 @@
-obj-y           := main.o if.o generic.o state.o cleanup.o
+obj-y           := main.o if.o generic.o cleanup.o
 obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o
 
diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c
index 33af14110dfd..92ba9cd31c9a 100644
--- a/arch/x86/kernel/cpu/mtrr/amd.c
+++ b/arch/x86/kernel/cpu/mtrr/amd.c
@@ -108,7 +108,7 @@ amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
         return 0;
 }
 
-static struct mtrr_ops amd_mtrr_ops = {
+static const struct mtrr_ops amd_mtrr_ops = {
         .vendor            = X86_VENDOR_AMD,
         .set               = amd_set_mtrr,
         .get               = amd_get_mtrr,
diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c
index de89f14eff3a..316fe3e60a97 100644
--- a/arch/x86/kernel/cpu/mtrr/centaur.c
+++ b/arch/x86/kernel/cpu/mtrr/centaur.c
@@ -110,7 +110,7 @@ centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int t
         return 0;
 }
 
-static struct mtrr_ops centaur_mtrr_ops = {
+static const struct mtrr_ops centaur_mtrr_ops = {
         .vendor            = X86_VENDOR_CENTAUR,
         .set               = centaur_set_mcr,
         .get               = centaur_get_mcr,
diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c
index 228d982ce09c..68a3343e5798 100644
--- a/arch/x86/kernel/cpu/mtrr/cyrix.c
+++ b/arch/x86/kernel/cpu/mtrr/cyrix.c
@@ -265,7 +265,7 @@ static void cyrix_set_all(void)
         post_set();
 }
 
-static struct mtrr_ops cyrix_mtrr_ops = {
+static const struct mtrr_ops cyrix_mtrr_ops = {
         .vendor            = X86_VENDOR_CYRIX,
         .set_all           = cyrix_set_all,
         .set               = cyrix_set_arr,
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 55da0c5f68dd..9aa5dc76ff4a 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -464,7 +464,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
                 tmp |= ~((1<<(hi - 1)) - 1);
 
                 if (tmp != mask_lo) {
-                        WARN_ONCE(1, KERN_INFO "mtrr: your BIOS has set up an incorrect mask, fixing it up.\n");
+                        printk(KERN_WARNING "mtrr: your BIOS has configured an incorrect mask, fixing it.\n");
                         mask_lo = tmp;
                 }
         }
@@ -570,7 +570,7 @@ static unsigned long set_mtrr_state(void)
 
 
 static unsigned long cr4;
-static DEFINE_SPINLOCK(set_atomicity_lock);
+static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
 
 /*
  * Since we are disabling the cache don't allow any interrupts,
@@ -590,7 +590,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
          * changes to the way the kernel boots
          */
 
-        spin_lock(&set_atomicity_lock);
+        raw_spin_lock(&set_atomicity_lock);
 
         /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
         cr0 = read_cr0() | X86_CR0_CD;
@@ -627,7 +627,7 @@ static void post_set(void) __releases(set_atomicity_lock)
         /* Restore value of CR4 */
         if (cpu_has_pge)
                 write_cr4(cr4);
-        spin_unlock(&set_atomicity_lock);
+        raw_spin_unlock(&set_atomicity_lock);
 }
 
 static void generic_set_all(void)
@@ -752,7 +752,7 @@ int positive_have_wrcomb(void)
 /*
  * Generic structure...
  */
-struct mtrr_ops generic_mtrr_ops = {
+const struct mtrr_ops generic_mtrr_ops = {
         .use_intel_if           = 1,
         .set_all                = generic_set_all,
         .get                    = generic_get_mtrr,
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 84e83de54575..fe4622e8c837 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -60,14 +60,14 @@ static DEFINE_MUTEX(mtrr_mutex);
 u64 size_or_mask, size_and_mask;
 static bool mtrr_aps_delayed_init;
 
-static struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
+static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
 
-struct mtrr_ops *mtrr_if;
+const struct mtrr_ops *mtrr_if;
 
 static void set_mtrr(unsigned int reg, unsigned long base,
                      unsigned long size, mtrr_type type);
 
-void set_mtrr_ops(struct mtrr_ops *ops)
+void set_mtrr_ops(const struct mtrr_ops *ops)
 {
         if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
                 mtrr_ops[ops->vendor] = ops;
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h
index a501dee9a87a..df5e41f31a27 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.h
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.h
@@ -32,7 +32,7 @@ extern int generic_get_free_region(unsigned long base, unsigned long size,
 extern int generic_validate_add_page(unsigned long base, unsigned long size,
                                      unsigned int type);
 
-extern struct mtrr_ops generic_mtrr_ops;
+extern const struct mtrr_ops generic_mtrr_ops;
 
 extern int positive_have_wrcomb(void);
 
@@ -53,10 +53,10 @@ void fill_mtrr_var_range(unsigned int index,
                 u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
 void get_mtrr_state(void);
 
-extern void set_mtrr_ops(struct mtrr_ops *ops);
+extern void set_mtrr_ops(const struct mtrr_ops *ops);
 
 extern u64 size_or_mask, size_and_mask;
-extern struct mtrr_ops *mtrr_if;
+extern const struct mtrr_ops *mtrr_if;
 
 #define is_cpu(vnd)     (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
 #define use_intel()     (mtrr_if && mtrr_if->use_intel_if == 1)
diff --git a/arch/x86/kernel/cpu/mtrr/state.c b/arch/x86/kernel/cpu/mtrr/state.c
deleted file mode 100644
index dfc80b4e6b0d..000000000000
--- a/arch/x86/kernel/cpu/mtrr/state.c
+++ /dev/null
@@ -1,94 +0,0 @@
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/mm.h>
-
-#include <asm/processor-cyrix.h>
-#include <asm/processor-flags.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-
-#include "mtrr.h"
-
-/* Put the processor into a state where MTRRs can be safely set */
-void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
-{
-        unsigned int cr0;
-
-        /* Disable interrupts locally */
-        local_irq_save(ctxt->flags);
-
-        if (use_intel() || is_cpu(CYRIX)) {
-
-                /* Save value of CR4 and clear Page Global Enable (bit 7) */
-                if (cpu_has_pge) {
-                        ctxt->cr4val = read_cr4();
-                        write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
-                }
-
-                /*
-                 * Disable and flush caches. Note that wbinvd flushes the TLBs
-                 * as a side-effect
-                 */
-                cr0 = read_cr0() | X86_CR0_CD;
-                wbinvd();
-                write_cr0(cr0);
-                wbinvd();
-
-                if (use_intel()) {
-                        /* Save MTRR state */
-                        rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
-                } else {
-                        /*
-                         * Cyrix ARRs -
-                         * everything else were excluded at the top
-                         */
-                        ctxt->ccr3 = getCx86(CX86_CCR3);
-                }
-        }
-}
-
-void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
-{
-        if (use_intel()) {
-                /* Disable MTRRs, and set the default type to uncached */
-                mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,
-                      ctxt->deftype_hi);
-        } else {
-                if (is_cpu(CYRIX)) {
-                        /* Cyrix ARRs - everything else were excluded at the top */
-                        setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
-                }
-        }
-}
-
-/* Restore the processor after a set_mtrr_prepare */
-void set_mtrr_done(struct set_mtrr_context *ctxt)
-{
-        if (use_intel() || is_cpu(CYRIX)) {
-
-                /* Flush caches and TLBs */
-                wbinvd();
-
-                /* Restore MTRRdefType */
-                if (use_intel()) {
-                        /* Intel (P6) standard MTRRs */
-                        mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo,
-                                   ctxt->deftype_hi);
-                } else {
-                        /*
-                         * Cyrix ARRs -
-                         * everything else was excluded at the top
-                         */
-                        setCx86(CX86_CCR3, ctxt->ccr3);
-                }
-
-                /* Enable caches */
-                write_cr0(read_cr0() & 0xbfffffff);
-
-                /* Restore value of CR4 */
-                if (cpu_has_pge)
-                        write_cr4(ctxt->cr4val);
-        }
-        /* Re-enable interrupts locally (if enabled previously) */
-        local_irq_restore(ctxt->flags);
-}
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index 8c1c07073ccc..641ccb9dddbc 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -7,6 +7,7 @@
  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
+ *  Copyright (C) 2009 Google, Inc., Stephane Eranian
  *
  *  For licencing details see kernel-base/COPYING
  */
@@ -22,6 +23,7 @@
 #include <linux/uaccess.h>
 #include <linux/highmem.h>
 #include <linux/cpu.h>
+#include <linux/bitops.h>
 
 #include <asm/apic.h>
 #include <asm/stacktrace.h>
@@ -68,26 +70,59 @@ struct debug_store {
         u64     pebs_event_reset[MAX_PEBS_EVENTS];
 };
 
+struct event_constraint {
+        union {
+                unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+                u64             idxmsk64[1];
+        };
+        int     code;
+        int     cmask;
+        int     weight;
+};
+
+struct amd_nb {
+        int nb_id;  /* NorthBridge id */
+        int refcnt; /* reference count */
+        struct perf_event *owners[X86_PMC_IDX_MAX];
+        struct event_constraint event_constraints[X86_PMC_IDX_MAX];
+};
+
 struct cpu_hw_events {
-        struct perf_event       *events[X86_PMC_IDX_MAX];
-        unsigned long           used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+        struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
         unsigned long           interrupts;
         int                     enabled;
         struct debug_store      *ds;
-};
 
-struct event_constraint {
-        unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
-        int             code;
+        int                     n_events;
+        int                     n_added;
+        int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
+        u64                     tags[X86_PMC_IDX_MAX];
+        struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
+        struct amd_nb           *amd_nb;
 };
 
-#define EVENT_CONSTRAINT(c, m) { .code = (c), .idxmsk[0] = (m) }
-#define EVENT_CONSTRAINT_END  { .code = 0, .idxmsk[0] = 0 }
+#define __EVENT_CONSTRAINT(c, n, m, w) {\
+        { .idxmsk64[0] = (n) },         \
+        .code = (c),                    \
+        .cmask = (m),                   \
+        .weight = (w),                  \
+}
+
+#define EVENT_CONSTRAINT(c, n, m)       \
+        __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
 
-#define for_each_event_constraint(e, c) \
-        for ((e) = (c); (e)->idxmsk[0]; (e)++)
+#define INTEL_EVENT_CONSTRAINT(c, n)    \
+        EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
 
+#define FIXED_EVENT_CONSTRAINT(c, n)    \
+        EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK)
+
+#define EVENT_CONSTRAINT_END            \
+        EVENT_CONSTRAINT(0, 0, 0)
+
+#define for_each_event_constraint(e, c) \
+        for ((e) = (c); (e)->cmask; (e)++)
 
 /*
  * struct x86_pmu - generic x86 pmu
@@ -114,8 +149,14 @@ struct x86_pmu {
         u64             intel_ctrl;
         void            (*enable_bts)(u64 config);
         void            (*disable_bts)(void);
-        int             (*get_event_idx)(struct cpu_hw_events *cpuc,
-                                         struct hw_perf_event *hwc);
+
+        struct event_constraint *
+                        (*get_event_constraints)(struct cpu_hw_events *cpuc,
+                                                 struct perf_event *event);
+
+        void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
+                                                 struct perf_event *event);
+        struct event_constraint *event_constraints;
 };
 
 static struct x86_pmu x86_pmu __read_mostly;
@@ -124,111 +165,8 @@ static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
         .enabled = 1,
 };
 
-static const struct event_constraint *event_constraints;
-
-/*
- * Not sure about some of these
- */
-static const u64 p6_perfmon_event_map[] =
-{
-  [PERF_COUNT_HW_CPU_CYCLES]            = 0x0079,
-  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
-  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0f2e,
-  [PERF_COUNT_HW_CACHE_MISSES]          = 0x012e,
-  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
-  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
-  [PERF_COUNT_HW_BUS_CYCLES]            = 0x0062,
-};
-
-static u64 p6_pmu_event_map(int hw_event)
-{
-        return p6_perfmon_event_map[hw_event];
-}
-
-/*
- * Event setting that is specified not to count anything.
- * We use this to effectively disable a counter.
- *
- * L2_RQSTS with 0 MESI unit mask.
- */
-#define P6_NOP_EVENT                    0x0000002EULL
-
-static u64 p6_pmu_raw_event(u64 hw_event)
-{
-#define P6_EVNTSEL_EVENT_MASK           0x000000FFULL
-#define P6_EVNTSEL_UNIT_MASK            0x0000FF00ULL
-#define P6_EVNTSEL_EDGE_MASK            0x00040000ULL
-#define P6_EVNTSEL_INV_MASK             0x00800000ULL
-#define P6_EVNTSEL_REG_MASK             0xFF000000ULL
-
-#define P6_EVNTSEL_MASK                 \
-        (P6_EVNTSEL_EVENT_MASK |        \
-         P6_EVNTSEL_UNIT_MASK  |        \
-         P6_EVNTSEL_EDGE_MASK  |        \
-         P6_EVNTSEL_INV_MASK   |        \
-         P6_EVNTSEL_REG_MASK)
-
-        return hw_event & P6_EVNTSEL_MASK;
-}
-
-static const struct event_constraint intel_p6_event_constraints[] =
-{
-        EVENT_CONSTRAINT(0xc1, 0x1),    /* FLOPS */
-        EVENT_CONSTRAINT(0x10, 0x1),    /* FP_COMP_OPS_EXE */
-        EVENT_CONSTRAINT(0x11, 0x1),    /* FP_ASSIST */
-        EVENT_CONSTRAINT(0x12, 0x2),    /* MUL */
-        EVENT_CONSTRAINT(0x13, 0x2),    /* DIV */
-        EVENT_CONSTRAINT(0x14, 0x1),    /* CYCLES_DIV_BUSY */
-        EVENT_CONSTRAINT_END
-};
-
-/*
- * Intel PerfMon v3. Used on Core2 and later.
- */
-static const u64 intel_perfmon_event_map[] =
-{
-  [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
-  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
-  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
-  [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
-  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
-  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
-  [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
-};
-
-static const struct event_constraint intel_core_event_constraints[] =
-{
-        EVENT_CONSTRAINT(0x10, 0x1),    /* FP_COMP_OPS_EXE */
-        EVENT_CONSTRAINT(0x11, 0x2),    /* FP_ASSIST */
-        EVENT_CONSTRAINT(0x12, 0x2),    /* MUL */
-        EVENT_CONSTRAINT(0x13, 0x2),    /* DIV */
-        EVENT_CONSTRAINT(0x14, 0x1),    /* CYCLES_DIV_BUSY */
-        EVENT_CONSTRAINT(0x18, 0x1),    /* IDLE_DURING_DIV */
-        EVENT_CONSTRAINT(0x19, 0x2),    /* DELAYED_BYPASS */
-        EVENT_CONSTRAINT(0xa1, 0x1),    /* RS_UOPS_DISPATCH_CYCLES */
-        EVENT_CONSTRAINT(0xcb, 0x1),    /* MEM_LOAD_RETIRED */
-        EVENT_CONSTRAINT_END
-};
-
-static const struct event_constraint intel_nehalem_event_constraints[] =
-{
-        EVENT_CONSTRAINT(0x40, 0x3),    /* L1D_CACHE_LD */
-        EVENT_CONSTRAINT(0x41, 0x3),    /* L1D_CACHE_ST */
-        EVENT_CONSTRAINT(0x42, 0x3),    /* L1D_CACHE_LOCK */
-        EVENT_CONSTRAINT(0x43, 0x3),    /* L1D_ALL_REF */
-        EVENT_CONSTRAINT(0x4e, 0x3),    /* L1D_PREFETCH */
-        EVENT_CONSTRAINT(0x4c, 0x3),    /* LOAD_HIT_PRE */
-        EVENT_CONSTRAINT(0x51, 0x3),    /* L1D */
-        EVENT_CONSTRAINT(0x52, 0x3),    /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
-        EVENT_CONSTRAINT(0x53, 0x3),    /* L1D_CACHE_LOCK_FB_HIT */
-        EVENT_CONSTRAINT(0xc5, 0x3),    /* CACHE_LOCK_CYCLES */
-        EVENT_CONSTRAINT_END
-};
-
-static u64 intel_pmu_event_map(int hw_event)
-{
-        return intel_perfmon_event_map[hw_event];
-}
+static int x86_perf_event_set_period(struct perf_event *event,
+                             struct hw_perf_event *hwc, int idx);
 
 /*
  * Generalized hw caching related hw_event table, filled
@@ -245,424 +183,6 @@ static u64 __read_mostly hw_cache_event_ids
                                 [PERF_COUNT_HW_CACHE_OP_MAX]
                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 
-static __initconst u64 nehalem_hw_cache_event_ids
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(L1D) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
-                [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
-                [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
-                [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
-        },
- },
- [ C(L1I ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
-                [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
-                [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
-                [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
-                [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
-        },
- },
- [ C(DTLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
-                [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
-                [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0x0,
-        },
- },
- [ C(ITLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
-                [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
- [ C(BPU ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
-                [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
-};
-
-static __initconst u64 core2_hw_cache_event_ids
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(L1D) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
-                [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
-                [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(L1I ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
-                [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
-                [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
-                [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(DTLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
-                [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
-                [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(ITLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
-                [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
- [ C(BPU ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
-                [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
-};
-
-static __initconst u64 atom_hw_cache_event_ids
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(L1D) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
-                [ C(RESULT_MISS)   ] = 0,
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
-                [ C(RESULT_MISS)   ] = 0,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(L1I ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
-                [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
-                [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
-                [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(DTLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
-                [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
-                [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(ITLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
-                [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
- [ C(BPU ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
-                [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
-};
-
-static u64 intel_pmu_raw_event(u64 hw_event)
-{
-#define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
-#define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
-#define CORE_EVNTSEL_EDGE_MASK          0x00040000ULL
-#define CORE_EVNTSEL_INV_MASK           0x00800000ULL
-#define CORE_EVNTSEL_REG_MASK           0xFF000000ULL
-
-#define CORE_EVNTSEL_MASK               \
-        (CORE_EVNTSEL_EVENT_MASK |      \
-         CORE_EVNTSEL_UNIT_MASK  |      \
-         CORE_EVNTSEL_EDGE_MASK  |      \
-         CORE_EVNTSEL_INV_MASK  |       \
-         CORE_EVNTSEL_REG_MASK)
-
-        return hw_event & CORE_EVNTSEL_MASK;
-}
-
-static __initconst u64 amd_hw_cache_event_ids
-                                [PERF_COUNT_HW_CACHE_MAX]
-                                [PERF_COUNT_HW_CACHE_OP_MAX]
-                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
-{
- [ C(L1D) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
-                [ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
-                [ C(RESULT_MISS)   ] = 0,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
-                [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
-        },
- },
- [ C(L1I ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
-                [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(LL  ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
-                [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
-                [ C(RESULT_MISS)   ] = 0,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(DTLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
-                [ C(RESULT_MISS)   ] = 0x0046, /* L1 DTLB and L2 DLTB Miss   */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = 0,
-                [ C(RESULT_MISS)   ] = 0,
-        },
- },
- [ C(ITLB) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
-                [ C(RESULT_MISS)   ] = 0x0085, /* Instr. fetch ITLB misses   */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
- [ C(BPU ) ] = {
-        [ C(OP_READ) ] = {
-                [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
-                [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
-        },
-        [ C(OP_WRITE) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
-        [ C(OP_PREFETCH) ] = {
-                [ C(RESULT_ACCESS) ] = -1,
-                [ C(RESULT_MISS)   ] = -1,
-        },
- },
-};
-
-/*
- * AMD Performance Monitor K7 and later.
- */
-static const u64 amd_perfmon_event_map[] =
-{
-  [PERF_COUNT_HW_CPU_CYCLES]            = 0x0076,
-  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
-  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0080,
-  [PERF_COUNT_HW_CACHE_MISSES]          = 0x0081,
-  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
-  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
-};
-
-static u64 amd_pmu_event_map(int hw_event)
-{
-        return amd_perfmon_event_map[hw_event];
-}
-
-static u64 amd_pmu_raw_event(u64 hw_event)
-{
-#define K7_EVNTSEL_EVENT_MASK   0x7000000FFULL
-#define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
-#define K7_EVNTSEL_EDGE_MASK    0x000040000ULL
-#define K7_EVNTSEL_INV_MASK     0x000800000ULL
-#define K7_EVNTSEL_REG_MASK     0x0FF000000ULL
-
-#define K7_EVNTSEL_MASK                 \
-        (K7_EVNTSEL_EVENT_MASK |        \
-         K7_EVNTSEL_UNIT_MASK  |        \
-         K7_EVNTSEL_EDGE_MASK  |        \
-         K7_EVNTSEL_INV_MASK   |        \
-         K7_EVNTSEL_REG_MASK)
-
-        return hw_event & K7_EVNTSEL_MASK;
-}
-
 /*
  * Propagate event elapsed time into the generic event.
  * Can only be executed on the CPU where the event is active.
@@ -914,42 +434,6 @@ set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
         return 0;
 }
 
-static void intel_pmu_enable_bts(u64 config)
-{
-        unsigned long debugctlmsr;
-
-        debugctlmsr = get_debugctlmsr();
-
-        debugctlmsr |= X86_DEBUGCTL_TR;
-        debugctlmsr |= X86_DEBUGCTL_BTS;
-        debugctlmsr |= X86_DEBUGCTL_BTINT;
-
-        if (!(config & ARCH_PERFMON_EVENTSEL_OS))
-                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
-
-        if (!(config & ARCH_PERFMON_EVENTSEL_USR))
-                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
-
-        update_debugctlmsr(debugctlmsr);
-}
-
-static void intel_pmu_disable_bts(void)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        unsigned long debugctlmsr;
-
-        if (!cpuc->ds)
-                return;
-
-        debugctlmsr = get_debugctlmsr();
-
-        debugctlmsr &=
-                ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
-                  X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
-
-        update_debugctlmsr(debugctlmsr);
-}
-
 /*
  * Setup the hardware configuration for a given attr_type
  */
@@ -988,6 +472,8 @@ static int __hw_perf_event_init(struct perf_event *event)
         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
 
         hwc->idx = -1;
+        hwc->last_cpu = -1;
+        hwc->last_tag = ~0ULL;
 
         /*
          * Count user and OS events unless requested not to.
@@ -1056,216 +542,323 @@ static int __hw_perf_event_init(struct perf_event *event)
         return 0;
 }
 
-static void p6_pmu_disable_all(void)
+static void x86_pmu_disable_all(void)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        u64 val;
-
-        if (!cpuc->enabled)
-                return;
+        int idx;
 
-        cpuc->enabled = 0;
-        barrier();
+        for (idx = 0; idx < x86_pmu.num_events; idx++) {
+                u64 val;
 
-        /* p6 only has one enable register */
-        rdmsrl(MSR_P6_EVNTSEL0, val);
-        val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
-        wrmsrl(MSR_P6_EVNTSEL0, val);
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+                rdmsrl(x86_pmu.eventsel + idx, val);
+                if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
+                        continue;
+                val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
+                wrmsrl(x86_pmu.eventsel + idx, val);
+        }
 }
 
-static void intel_pmu_disable_all(void)
+void hw_perf_disable(void)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 
+        if (!x86_pmu_initialized())
+                return;
+
         if (!cpuc->enabled)
                 return;
 
+        cpuc->n_added = 0;
         cpuc->enabled = 0;
         barrier();
 
-        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
-
-        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
-                intel_pmu_disable_bts();
+        x86_pmu.disable_all();
 }
 
-static void amd_pmu_disable_all(void)
+static void x86_pmu_enable_all(void)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         int idx;
 
-        if (!cpuc->enabled)
-                return;
-
-        cpuc->enabled = 0;
-        /*
-         * ensure we write the disable before we start disabling the
-         * events proper, so that amd_pmu_enable_event() does the
-         * right thing.
-         */
-        barrier();
-
         for (idx = 0; idx < x86_pmu.num_events; idx++) {
+                struct perf_event *event = cpuc->events[idx];
                 u64 val;
 
                 if (!test_bit(idx, cpuc->active_mask))
                         continue;
-                rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
-                if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
-                        continue;
-                val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
-                wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
+
+                val = event->hw.config;
+                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+                wrmsrl(x86_pmu.eventsel + idx, val);
         }
 }
 
-void hw_perf_disable(void)
+static const struct pmu pmu;
+
+static inline int is_x86_event(struct perf_event *event)
 {
-        if (!x86_pmu_initialized())
-                return;
-        return x86_pmu.disable_all();
+        return event->pmu == &pmu;
 }
 
-static void p6_pmu_enable_all(void)
+static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        unsigned long val;
+        struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
+        unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
+        int i, j, w, wmax, num = 0;
+        struct hw_perf_event *hwc;
 
-        if (cpuc->enabled)
-                return;
+        bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 
-        cpuc->enabled = 1;
-        barrier();
+        for (i = 0; i < n; i++) {
+                constraints[i] =
+                  x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
+        }
 
-        /* p6 only has one enable register */
-        rdmsrl(MSR_P6_EVNTSEL0, val);
-        val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-        wrmsrl(MSR_P6_EVNTSEL0, val);
-}
+        /*
+         * fastpath, try to reuse previous register
+         */
+        for (i = 0; i < n; i++) {
+                hwc = &cpuc->event_list[i]->hw;
+                c = constraints[i];
 
-static void intel_pmu_enable_all(void)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+                /* never assigned */
+                if (hwc->idx == -1)
+                        break;
 
-        if (cpuc->enabled)
-                return;
+                /* constraint still honored */
+                if (!test_bit(hwc->idx, c->idxmsk))
+                        break;
 
-        cpuc->enabled = 1;
-        barrier();
+                /* not already used */
+                if (test_bit(hwc->idx, used_mask))
+                        break;
+
+                set_bit(hwc->idx, used_mask);
+                if (assign)
+                        assign[i] = hwc->idx;
+        }
+        if (i == n)
+                goto done;
+
+        /*
+         * begin slow path
+         */
+
+        bitmap_zero(used_mask, X86_PMC_IDX_MAX);
+
+        /*
+         * weight = number of possible counters
+         *
+         * 1    = most constrained, only works on one counter
+         * wmax = least constrained, works on any counter
+         *
+         * assign events to counters starting with most
+         * constrained events.
+         */
+        wmax = x86_pmu.num_events;
+
+        /*
+         * when fixed event counters are present,
+         * wmax is incremented by 1 to account
+         * for one more choice
+         */
+        if (x86_pmu.num_events_fixed)
+                wmax++;
 
-        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
+        for (w = 1, num = n; num && w <= wmax; w++) {
+                /* for each event */
+                for (i = 0; num && i < n; i++) {
+                        c = constraints[i];
+                        hwc = &cpuc->event_list[i]->hw;
 
-        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
-                struct perf_event *event =
-                        cpuc->events[X86_PMC_IDX_FIXED_BTS];
+                        if (c->weight != w)
+                                continue;
 
-                if (WARN_ON_ONCE(!event))
-                        return;
+                        for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
+                                if (!test_bit(j, used_mask))
+                                        break;
+                        }
+
+                        if (j == X86_PMC_IDX_MAX)
+                                break;
+
+                        set_bit(j, used_mask);
 
-                intel_pmu_enable_bts(event->hw.config);
+                        if (assign)
+                                assign[i] = j;
+                        num--;
+                }
+        }
+done:
+        /*
+         * scheduling failed or is just a simulation,
+         * free resources if necessary
+         */
+        if (!assign || num) {
+                for (i = 0; i < n; i++) {
+                        if (x86_pmu.put_event_constraints)
+                                x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
+                }
         }
+        return num ? -ENOSPC : 0;
 }
 
-static void amd_pmu_enable_all(void)
+/*
+ * dogrp: true if must collect siblings events (group)
+ * returns total number of events and error code
+ */
+static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        int idx;
+        struct perf_event *event;
+        int n, max_count;
 
-        if (cpuc->enabled)
-                return;
+        max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
 
-        cpuc->enabled = 1;
-        barrier();
+        /* current number of events already accepted */
+        n = cpuc->n_events;
 
-        for (idx = 0; idx < x86_pmu.num_events; idx++) {
-                struct perf_event *event = cpuc->events[idx];
-                u64 val;
+        if (is_x86_event(leader)) {
+                if (n >= max_count)
+                        return -ENOSPC;
+                cpuc->event_list[n] = leader;
+                n++;
+        }
+        if (!dogrp)
+                return n;
 
-                if (!test_bit(idx, cpuc->active_mask))
+        list_for_each_entry(event, &leader->sibling_list, group_entry) {
+                if (!is_x86_event(event) ||
+                    event->state <= PERF_EVENT_STATE_OFF)
                         continue;
 
-                val = event->hw.config;
-                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-                wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
-        }
-}
+                if (n >= max_count)
+                        return -ENOSPC;
 
-void hw_perf_enable(void)
-{
-        if (!x86_pmu_initialized())
-                return;
-        x86_pmu.enable_all();
+                cpuc->event_list[n] = event;
+                n++;
+        }
+        return n;
 }
 
-static inline u64 intel_pmu_get_status(void)
+static inline void x86_assign_hw_event(struct perf_event *event,
+                                struct cpu_hw_events *cpuc, int i)
 {
-        u64 status;
+        struct hw_perf_event *hwc = &event->hw;
 
-        rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
+        hwc->idx = cpuc->assign[i];
+        hwc->last_cpu = smp_processor_id();
+        hwc->last_tag = ++cpuc->tags[i];
 
-        return status;
+        if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
+                hwc->config_base = 0;
+                hwc->event_base = 0;
+        } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
+                hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
+                /*
+                 * We set it so that event_base + idx in wrmsr/rdmsr maps to
+                 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
+                 */
+                hwc->event_base =
+                        MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
+        } else {
+                hwc->config_base = x86_pmu.eventsel;
+                hwc->event_base  = x86_pmu.perfctr;
+        }
 }
 
-static inline void intel_pmu_ack_status(u64 ack)
+static inline int match_prev_assignment(struct hw_perf_event *hwc,
+                                        struct cpu_hw_events *cpuc,
+                                        int i)
 {
-        wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
+        return hwc->idx == cpuc->assign[i] &&
+                hwc->last_cpu == smp_processor_id() &&
+                hwc->last_tag == cpuc->tags[i];
 }
 
-static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        (void)checking_wrmsrl(hwc->config_base + idx,
-                              hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
-}
+static void x86_pmu_stop(struct perf_event *event);
 
-static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
+void hw_perf_enable(void)
 {
-        (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
-}
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct perf_event *event;
+        struct hw_perf_event *hwc;
+        int i;
 
-static inline void
-intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
-{
-        int idx = __idx - X86_PMC_IDX_FIXED;
-        u64 ctrl_val, mask;
+        if (!x86_pmu_initialized())
+                return;
 
-        mask = 0xfULL << (idx * 4);
+        if (cpuc->enabled)
+                return;
 
-        rdmsrl(hwc->config_base, ctrl_val);
-        ctrl_val &= ~mask;
-        (void)checking_wrmsrl(hwc->config_base, ctrl_val);
-}
+        if (cpuc->n_added) {
+                /*
+                 * apply assignment obtained either from
+                 * hw_perf_group_sched_in() or x86_pmu_enable()
+                 *
+                 * step1: save events moving to new counters
+                 * step2: reprogram moved events into new counters
+                 */
+                for (i = 0; i < cpuc->n_events; i++) {
 
-static inline void
-p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        u64 val = P6_NOP_EVENT;
+                        event = cpuc->event_list[i];
+                        hwc = &event->hw;
 
-        if (cpuc->enabled)
-                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+                        /*
+                         * we can avoid reprogramming counter if:
+                         * - assigned same counter as last time
+                         * - running on same CPU as last time
+                         * - no other event has used the counter since
+                         */
+                        if (hwc->idx == -1 ||
+                            match_prev_assignment(hwc, cpuc, i))
+                                continue;
 
-        (void)checking_wrmsrl(hwc->config_base + idx, val);
-}
+                        x86_pmu_stop(event);
 
-static inline void
-intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
-                intel_pmu_disable_bts();
-                return;
-        }
+                        hwc->idx = -1;
+                }
 
-        if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
-                intel_pmu_disable_fixed(hwc, idx);
-                return;
+                for (i = 0; i < cpuc->n_events; i++) {
+
+                        event = cpuc->event_list[i];
+                        hwc = &event->hw;
+
+                        if (hwc->idx == -1) {
+                                x86_assign_hw_event(event, cpuc, i);
+                                x86_perf_event_set_period(event, hwc, hwc->idx);
+                        }
+                        /*
+                         * need to mark as active because x86_pmu_disable()
+                         * clear active_mask and events[] yet it preserves
+                         * idx
+                         */
+                        set_bit(hwc->idx, cpuc->active_mask);
+                        cpuc->events[hwc->idx] = event;
+
+                        x86_pmu.enable(hwc, hwc->idx);
+                        perf_event_update_userpage(event);
+                }
+                cpuc->n_added = 0;
+                perf_events_lapic_init();
         }
 
-        x86_pmu_disable_event(hwc, idx);
+        cpuc->enabled = 1;
+        barrier();
+
+        x86_pmu.enable_all();
+}
+
+static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        (void)checking_wrmsrl(hwc->config_base + idx,
+                              hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
 }
 
-static inline void
-amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
+static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
 {
-        x86_pmu_disable_event(hwc, idx);
+        (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
 }
 
 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
@@ -1326,220 +919,60 @@ x86_perf_event_set_period(struct perf_event *event,
         return ret;
 }
 
-static inline void
-intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
-{
-        int idx = __idx - X86_PMC_IDX_FIXED;
-        u64 ctrl_val, bits, mask;
-        int err;
-
-        /*
-         * Enable IRQ generation (0x8),
-         * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
-         * if requested:
-         */
-        bits = 0x8ULL;
-        if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
-                bits |= 0x2;
-        if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
-                bits |= 0x1;
-
-        /*
-         * ANY bit is supported in v3 and up
-         */
-        if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
-                bits |= 0x4;
-
-        bits <<= (idx * 4);
-        mask = 0xfULL << (idx * 4);
-
-        rdmsrl(hwc->config_base, ctrl_val);
-        ctrl_val &= ~mask;
-        ctrl_val |= bits;
-        err = checking_wrmsrl(hwc->config_base, ctrl_val);
-}
-
-static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+static void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
-        u64 val;
-
-        val = hwc->config;
         if (cpuc->enabled)
-                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-
-        (void)checking_wrmsrl(hwc->config_base + idx, val);
+                __x86_pmu_enable_event(hwc, idx);
 }
 
-
-static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
-                if (!__get_cpu_var(cpu_hw_events).enabled)
-                        return;
-
-                intel_pmu_enable_bts(hwc->config);
-                return;
-        }
-
-        if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
-                intel_pmu_enable_fixed(hwc, idx);
-                return;
-        }
-
-        x86_pmu_enable_event(hwc, idx);
-}
-
-static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+/*
+ * activate a single event
+ *
+ * The event is added to the group of enabled events
+ * but only if it can be scehduled with existing events.
+ *
+ * Called with PMU disabled. If successful and return value 1,
+ * then guaranteed to call perf_enable() and hw_perf_enable()
+ */
+static int x86_pmu_enable(struct perf_event *event)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc;
+        int assign[X86_PMC_IDX_MAX];
+        int n, n0, ret;
 
-        if (cpuc->enabled)
-                x86_pmu_enable_event(hwc, idx);
-}
-
-static int fixed_mode_idx(struct hw_perf_event *hwc)
-{
-        unsigned int hw_event;
-
-        hw_event = hwc->config & ARCH_PERFMON_EVENT_MASK;
-
-        if (unlikely((hw_event ==
-                      x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
-                     (hwc->sample_period == 1)))
-                return X86_PMC_IDX_FIXED_BTS;
+        hwc = &event->hw;
 
-        if (!x86_pmu.num_events_fixed)
-                return -1;
+        n0 = cpuc->n_events;
+        n = collect_events(cpuc, event, false);
+        if (n < 0)
+                return n;
 
+        ret = x86_schedule_events(cpuc, n, assign);
+        if (ret)
+                return ret;
         /*
-         * fixed counters do not take all possible filters
+         * copy new assignment, now we know it is possible
+         * will be used by hw_perf_enable()
          */
-        if (hwc->config & ARCH_PERFMON_EVENT_FILTER_MASK)
-                return -1;
+        memcpy(cpuc->assign, assign, n*sizeof(int));
 
-        if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
-                return X86_PMC_IDX_FIXED_INSTRUCTIONS;
-        if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
-                return X86_PMC_IDX_FIXED_CPU_CYCLES;
-        if (unlikely(hw_event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
-                return X86_PMC_IDX_FIXED_BUS_CYCLES;
+        cpuc->n_events = n;
+        cpuc->n_added  = n - n0;
 
-        return -1;
-}
-
-/*
- * generic counter allocator: get next free counter
- */
-static int
-gen_get_event_idx(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
-{
-        int idx;
-
-        idx = find_first_zero_bit(cpuc->used_mask, x86_pmu.num_events);
-        return idx == x86_pmu.num_events ? -1 : idx;
-}
-
-/*
- * intel-specific counter allocator: check event constraints
- */
-static int
-intel_get_event_idx(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
-{
-        const struct event_constraint *event_constraint;
-        int i, code;
-
-        if (!event_constraints)
-                goto skip;
-
-        code = hwc->config & CORE_EVNTSEL_EVENT_MASK;
-
-        for_each_event_constraint(event_constraint, event_constraints) {
-                if (code == event_constraint->code) {
-                        for_each_bit(i, event_constraint->idxmsk, X86_PMC_IDX_MAX) {
-                                if (!test_and_set_bit(i, cpuc->used_mask))
-                                        return i;
-                        }
-                        return -1;
-                }
-        }
-skip:
-        return gen_get_event_idx(cpuc, hwc);
-}
-
-static int
-x86_schedule_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc)
-{
-        int idx;
-
-        idx = fixed_mode_idx(hwc);
-        if (idx == X86_PMC_IDX_FIXED_BTS) {
-                /* BTS is already occupied. */
-                if (test_and_set_bit(idx, cpuc->used_mask))
-                        return -EAGAIN;
-
-                hwc->config_base        = 0;
-                hwc->event_base         = 0;
-                hwc->idx                = idx;
-        } else if (idx >= 0) {
-                /*
-                 * Try to get the fixed event, if that is already taken
-                 * then try to get a generic event:
-                 */
-                if (test_and_set_bit(idx, cpuc->used_mask))
-                        goto try_generic;
-
-                hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
-                /*
-                 * We set it so that event_base + idx in wrmsr/rdmsr maps to
-                 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
-                 */
-                hwc->event_base =
-                        MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
-                hwc->idx = idx;
-        } else {
-                idx = hwc->idx;
-                /* Try to get the previous generic event again */
-                if (idx == -1 || test_and_set_bit(idx, cpuc->used_mask)) {
-try_generic:
-                        idx = x86_pmu.get_event_idx(cpuc, hwc);
-                        if (idx == -1)
-                                return -EAGAIN;
-
-                        set_bit(idx, cpuc->used_mask);
-                        hwc->idx = idx;
-                }
-                hwc->config_base = x86_pmu.eventsel;
-                hwc->event_base  = x86_pmu.perfctr;
-        }
-
-        return idx;
+        return 0;
 }
 
-/*
- * Find a PMC slot for the freshly enabled / scheduled in event:
- */
-static int x86_pmu_enable(struct perf_event *event)
+static int x86_pmu_start(struct perf_event *event)
 {
-        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
-        int idx;
-
-        idx = x86_schedule_event(cpuc, hwc);
-        if (idx < 0)
-                return idx;
 
-        perf_events_lapic_init();
-
-        x86_pmu.disable(hwc, idx);
+        if (hwc->idx == -1)
+                return -EAGAIN;
 
-        cpuc->events[idx] = event;
-        set_bit(idx, cpuc->active_mask);
-
-        x86_perf_event_set_period(event, hwc, idx);
-        x86_pmu.enable(hwc, idx);
-
-        perf_event_update_userpage(event);
+        x86_perf_event_set_period(event, hwc, hwc->idx);
+        x86_pmu.enable(hwc, hwc->idx);
 
         return 0;
 }
@@ -1583,7 +1016,7 @@ void perf_event_print_debug(void)
                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
         }
-        pr_info("CPU#%d: used:       %016llx\n", cpu, *(u64 *)cpuc->used_mask);
+        pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
 
         for (idx = 0; idx < x86_pmu.num_events; idx++) {
                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
@@ -1607,67 +1040,7 @@ void perf_event_print_debug(void)
         local_irq_restore(flags);
 }
 
-static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
-{
-        struct debug_store *ds = cpuc->ds;
-        struct bts_record {
-                u64     from;
-                u64     to;
-                u64     flags;
-        };
-        struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
-        struct bts_record *at, *top;
-        struct perf_output_handle handle;
-        struct perf_event_header header;
-        struct perf_sample_data data;
-        struct pt_regs regs;
-
-        if (!event)
-                return;
-
-        if (!ds)
-                return;
-
-        at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
-        top = (struct bts_record *)(unsigned long)ds->bts_index;
-
-        if (top <= at)
-                return;
-
-        ds->bts_index = ds->bts_buffer_base;
-
-
-        data.period     = event->hw.last_period;
-        data.addr       = 0;
-        data.raw        = NULL;
-        regs.ip         = 0;
-
-        /*
-         * Prepare a generic sample, i.e. fill in the invariant fields.
-         * We will overwrite the from and to address before we output
-         * the sample.
-         */
-        perf_prepare_sample(&header, &data, event, &regs);
-
-        if (perf_output_begin(&handle, event,
-                              header.size * (top - at), 1, 1))
-                return;
-
-        for (; at < top; at++) {
-                data.ip         = at->from;
-                data.addr       = at->to;
-
-                perf_output_sample(&handle, &header, &data, event);
-        }
-
-        perf_output_end(&handle);
-
-        /* There's new data available. */
-        event->hw.interrupts++;
-        event->pending_kill = POLL_IN;
-}
-
-static void x86_pmu_disable(struct perf_event *event)
+static void x86_pmu_stop(struct perf_event *event)
 {
         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
         struct hw_perf_event *hwc = &event->hw;
@@ -1681,183 +1054,38 @@ static void x86_pmu_disable(struct perf_event *event)
         x86_pmu.disable(hwc, idx);
 
         /*
-         * Make sure the cleared pointer becomes visible before we
-         * (potentially) free the event:
-         */
-        barrier();
-
-        /*
          * Drain the remaining delta count out of a event
          * that we are disabling:
          */
         x86_perf_event_update(event, hwc, idx);
 
-        /* Drain the remaining BTS records. */
-        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
-                intel_pmu_drain_bts_buffer(cpuc);
-
         cpuc->events[idx] = NULL;
-        clear_bit(idx, cpuc->used_mask);
-
-        perf_event_update_userpage(event);
-}
-
-/*
- * Save and restart an expired event. Called by NMI contexts,
- * so it has to be careful about preempting normal event ops:
- */
-static int intel_pmu_save_and_restart(struct perf_event *event)
-{
-        struct hw_perf_event *hwc = &event->hw;
-        int idx = hwc->idx;
-        int ret;
-
-        x86_perf_event_update(event, hwc, idx);
-        ret = x86_perf_event_set_period(event, hwc, idx);
-
-        if (event->state == PERF_EVENT_STATE_ACTIVE)
-                intel_pmu_enable_event(hwc, idx);
-
-        return ret;
 }
 
-static void intel_pmu_reset(void)
-{
-        struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
-        unsigned long flags;
-        int idx;
-
-        if (!x86_pmu.num_events)
-                return;
-
-        local_irq_save(flags);
-
-        printk("clearing PMU state on CPU#%d\n", smp_processor_id());
-
-        for (idx = 0; idx < x86_pmu.num_events; idx++) {
-                checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
-                checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
-        }
-        for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
-                checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
-        }
-        if (ds)
-                ds->bts_index = ds->bts_buffer_base;
-
-        local_irq_restore(flags);
-}
-
-static int p6_pmu_handle_irq(struct pt_regs *regs)
-{
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct perf_event *event;
-        struct hw_perf_event *hwc;
-        int idx, handled = 0;
-        u64 val;
-
-        data.addr = 0;
-        data.raw = NULL;
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-
-        for (idx = 0; idx < x86_pmu.num_events; idx++) {
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                event = cpuc->events[idx];
-                hwc = &event->hw;
-
-                val = x86_perf_event_update(event, hwc, idx);
-                if (val & (1ULL << (x86_pmu.event_bits - 1)))
-                        continue;
-
-                /*
-                 * event overflow
-                 */
-                handled         = 1;
-                data.period     = event->hw.last_period;
-
-                if (!x86_perf_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 1, &data, regs))
-                        p6_pmu_disable_event(hwc, idx);
-        }
-
-        if (handled)
-                inc_irq_stat(apic_perf_irqs);
-
-        return handled;
-}
-
-/*
- * This handler is triggered by the local APIC, so the APIC IRQ handling
- * rules apply:
- */
-static int intel_pmu_handle_irq(struct pt_regs *regs)
+static void x86_pmu_disable(struct perf_event *event)
 {
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        int bit, loops;
-        u64 ack, status;
-
-        data.addr = 0;
-        data.raw = NULL;
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-
-        perf_disable();
-        intel_pmu_drain_bts_buffer(cpuc);
-        status = intel_pmu_get_status();
-        if (!status) {
-                perf_enable();
-                return 0;
-        }
-
-        loops = 0;
-again:
-        if (++loops > 100) {
-                WARN_ONCE(1, "perfevents: irq loop stuck!\n");
-                perf_event_print_debug();
-                intel_pmu_reset();
-                perf_enable();
-                return 1;
-        }
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        int i;
 
-        inc_irq_stat(apic_perf_irqs);
-        ack = status;
-        for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
-                struct perf_event *event = cpuc->events[bit];
+        x86_pmu_stop(event);
 
-                clear_bit(bit, (unsigned long *) &status);
-                if (!test_bit(bit, cpuc->active_mask))
-                        continue;
+        for (i = 0; i < cpuc->n_events; i++) {
+                if (event == cpuc->event_list[i]) {
 
-                if (!intel_pmu_save_and_restart(event))
-                        continue;
+                        if (x86_pmu.put_event_constraints)
+                                x86_pmu.put_event_constraints(cpuc, event);
 
-                data.period = event->hw.last_period;
+                        while (++i < cpuc->n_events)
+                                cpuc->event_list[i-1] = cpuc->event_list[i];
 
-                if (perf_event_overflow(event, 1, &data, regs))
-                        intel_pmu_disable_event(&event->hw, bit);
+                        --cpuc->n_events;
+                        break;
+                }
         }
-
-        intel_pmu_ack_status(ack);
-
-        /*
-         * Repeat if there is more work to be done:
-         */
-        status = intel_pmu_get_status();
-        if (status)
-                goto again;
-
-        perf_enable();
-
-        return 1;
+        perf_event_update_userpage(event);
 }
 
-static int amd_pmu_handle_irq(struct pt_regs *regs)
+static int x86_pmu_handle_irq(struct pt_regs *regs)
 {
         struct perf_sample_data data;
         struct cpu_hw_events *cpuc;
@@ -1892,7 +1120,7 @@ static int amd_pmu_handle_irq(struct pt_regs *regs)
                         continue;
 
                 if (perf_event_overflow(event, 1, &data, regs))
-                        amd_pmu_disable_event(hwc, idx);
+                        x86_pmu.disable(hwc, idx);
         }
 
         if (handled)
@@ -1975,194 +1203,137 @@ static __read_mostly struct notifier_block perf_event_nmi_notifier = {
         .priority               = 1
 };
 
-static __initconst struct x86_pmu p6_pmu = {
-        .name                   = "p6",
-        .handle_irq             = p6_pmu_handle_irq,
-        .disable_all            = p6_pmu_disable_all,
-        .enable_all             = p6_pmu_enable_all,
-        .enable                 = p6_pmu_enable_event,
-        .disable                = p6_pmu_disable_event,
-        .eventsel               = MSR_P6_EVNTSEL0,
-        .perfctr                = MSR_P6_PERFCTR0,
-        .event_map              = p6_pmu_event_map,
-        .raw_event              = p6_pmu_raw_event,
-        .max_events             = ARRAY_SIZE(p6_perfmon_event_map),
-        .apic                   = 1,
-        .max_period             = (1ULL << 31) - 1,
-        .version                = 0,
-        .num_events             = 2,
-        /*
-         * Events have 40 bits implemented. However they are designed such
-         * that bits [32-39] are sign extensions of bit 31. As such the
-         * effective width of a event for P6-like PMU is 32 bits only.
-         *
-         * See IA-32 Intel Architecture Software developer manual Vol 3B
-         */
-        .event_bits             = 32,
-        .event_mask             = (1ULL << 32) - 1,
-        .get_event_idx          = intel_get_event_idx,
-};
+static struct event_constraint unconstrained;
+static struct event_constraint emptyconstraint;
 
-static __initconst struct x86_pmu intel_pmu = {
-        .name                   = "Intel",
-        .handle_irq             = intel_pmu_handle_irq,
-        .disable_all            = intel_pmu_disable_all,
-        .enable_all             = intel_pmu_enable_all,
-        .enable                 = intel_pmu_enable_event,
-        .disable                = intel_pmu_disable_event,
-        .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
-        .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
-        .event_map              = intel_pmu_event_map,
-        .raw_event              = intel_pmu_raw_event,
-        .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
-        .apic                   = 1,
-        /*
-         * Intel PMCs cannot be accessed sanely above 32 bit width,
-         * so we install an artificial 1<<31 period regardless of
-         * the generic event period:
-         */
-        .max_period             = (1ULL << 31) - 1,
-        .enable_bts             = intel_pmu_enable_bts,
-        .disable_bts            = intel_pmu_disable_bts,
-        .get_event_idx          = intel_get_event_idx,
-};
+static struct event_constraint *
+x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+{
+        struct event_constraint *c;
 
-static __initconst struct x86_pmu amd_pmu = {
-        .name                   = "AMD",
-        .handle_irq             = amd_pmu_handle_irq,
-        .disable_all            = amd_pmu_disable_all,
-        .enable_all             = amd_pmu_enable_all,
-        .enable                 = amd_pmu_enable_event,
-        .disable                = amd_pmu_disable_event,
-        .eventsel               = MSR_K7_EVNTSEL0,
-        .perfctr                = MSR_K7_PERFCTR0,
-        .event_map              = amd_pmu_event_map,
-        .raw_event              = amd_pmu_raw_event,
-        .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
-        .num_events             = 4,
-        .event_bits             = 48,
-        .event_mask             = (1ULL << 48) - 1,
-        .apic                   = 1,
-        /* use highest bit to detect overflow */
-        .max_period             = (1ULL << 47) - 1,
-        .get_event_idx          = gen_get_event_idx,
-};
+        if (x86_pmu.event_constraints) {
+                for_each_event_constraint(c, x86_pmu.event_constraints) {
+                        if ((event->hw.config & c->cmask) == c->code)
+                                return c;
+                }
+        }
+
+        return &unconstrained;
+}
 
-static __init int p6_pmu_init(void)
+static int x86_event_sched_in(struct perf_event *event,
+                          struct perf_cpu_context *cpuctx)
 {
-        switch (boot_cpu_data.x86_model) {
-        case 1:
-        case 3:  /* Pentium Pro */
-        case 5:
-        case 6:  /* Pentium II */
-        case 7:
-        case 8:
-        case 11: /* Pentium III */
-                event_constraints = intel_p6_event_constraints;
-                break;
-        case 9:
-        case 13:
-                /* Pentium M */
-                event_constraints = intel_p6_event_constraints;
-                break;
-        default:
-                pr_cont("unsupported p6 CPU model %d ",
-                        boot_cpu_data.x86_model);
-                return -ENODEV;
-        }
+        int ret = 0;
 
-        x86_pmu = p6_pmu;
+        event->state = PERF_EVENT_STATE_ACTIVE;
+        event->oncpu = smp_processor_id();
+        event->tstamp_running += event->ctx->time - event->tstamp_stopped;
 
-        return 0;
+        if (!is_x86_event(event))
+                ret = event->pmu->enable(event);
+
+        if (!ret && !is_software_event(event))
+                cpuctx->active_oncpu++;
+
+        if (!ret && event->attr.exclusive)
+                cpuctx->exclusive = 1;
+
+        return ret;
 }
 
-static __init int intel_pmu_init(void)
+static void x86_event_sched_out(struct perf_event *event,
+                            struct perf_cpu_context *cpuctx)
 {
-        union cpuid10_edx edx;
-        union cpuid10_eax eax;
-        unsigned int unused;
-        unsigned int ebx;
-        int version;
-
-        if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
-                /* check for P6 processor family */
-           if (boot_cpu_data.x86 == 6) {
-                return p6_pmu_init();
-           } else {
-                return -ENODEV;
-           }
-        }
+        event->state = PERF_EVENT_STATE_INACTIVE;
+        event->oncpu = -1;
 
-        /*
-         * Check whether the Architectural PerfMon supports
-         * Branch Misses Retired hw_event or not.
-         */
-        cpuid(10, &eax.full, &ebx, &unused, &edx.full);
-        if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
-                return -ENODEV;
+        if (!is_x86_event(event))
+                event->pmu->disable(event);
 
-        version = eax.split.version_id;
-        if (version < 2)
-                return -ENODEV;
+        event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
 
-        x86_pmu                         = intel_pmu;
-        x86_pmu.version                 = version;
-        x86_pmu.num_events              = eax.split.num_events;
-        x86_pmu.event_bits              = eax.split.bit_width;
-        x86_pmu.event_mask              = (1ULL << eax.split.bit_width) - 1;
+        if (!is_software_event(event))
+                cpuctx->active_oncpu--;
 
-        /*
-         * Quirk: v2 perfmon does not report fixed-purpose events, so
-         * assume at least 3 events:
-         */
-        x86_pmu.num_events_fixed        = max((int)edx.split.num_events_fixed, 3);
+        if (event->attr.exclusive || !cpuctx->active_oncpu)
+                cpuctx->exclusive = 0;
+}
 
+/*
+ * Called to enable a whole group of events.
+ * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
+ * Assumes the caller has disabled interrupts and has
+ * frozen the PMU with hw_perf_save_disable.
+ *
+ * called with PMU disabled. If successful and return value 1,
+ * then guaranteed to call perf_enable() and hw_perf_enable()
+ */
+int hw_perf_group_sched_in(struct perf_event *leader,
+               struct perf_cpu_context *cpuctx,
+               struct perf_event_context *ctx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct perf_event *sub;
+        int assign[X86_PMC_IDX_MAX];
+        int n0, n1, ret;
+
+        /* n0 = total number of events */
+        n0 = collect_events(cpuc, leader, true);
+        if (n0 < 0)
+                return n0;
+
+        ret = x86_schedule_events(cpuc, n0, assign);
+        if (ret)
+                return ret;
+
+        ret = x86_event_sched_in(leader, cpuctx);
+        if (ret)
+                return ret;
+
+        n1 = 1;
+        list_for_each_entry(sub, &leader->sibling_list, group_entry) {
+                if (sub->state > PERF_EVENT_STATE_OFF) {
+                        ret = x86_event_sched_in(sub, cpuctx);
+                        if (ret)
+                                goto undo;
+                        ++n1;
+                }
+        }
         /*
-         * Install the hw-cache-events table:
+         * copy new assignment, now we know it is possible
+         * will be used by hw_perf_enable()
          */
-        switch (boot_cpu_data.x86_model) {
-        case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
-        case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
-        case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
-        case 29: /* six-core 45 nm xeon "Dunnington" */
-                memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
-                       sizeof(hw_cache_event_ids));
-
-                pr_cont("Core2 events, ");
-                event_constraints = intel_core_event_constraints;
-                break;
-        default:
-        case 26:
-                memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
-                       sizeof(hw_cache_event_ids));
+        memcpy(cpuc->assign, assign, n0*sizeof(int));
 
-                event_constraints = intel_nehalem_event_constraints;
-                pr_cont("Nehalem/Corei7 events, ");
-                break;
-        case 28:
-                memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
-                       sizeof(hw_cache_event_ids));
+        cpuc->n_events  = n0;
+        cpuc->n_added   = n1;
+        ctx->nr_active += n1;
 
-                pr_cont("Atom events, ");
-                break;
+        /*
+         * 1 means successful and events are active
+         * This is not quite true because we defer
+         * actual activation until hw_perf_enable() but
+         * this way we* ensure caller won't try to enable
+         * individual events
+         */
+        return 1;
+undo:
+        x86_event_sched_out(leader, cpuctx);
+        n0  = 1;
+        list_for_each_entry(sub, &leader->sibling_list, group_entry) {
+                if (sub->state == PERF_EVENT_STATE_ACTIVE) {
+                        x86_event_sched_out(sub, cpuctx);
+                        if (++n0 == n1)
+                                break;
+                }
         }
-        return 0;
+        return ret;
 }
 
-static __init int amd_pmu_init(void)
-{
-        /* Performance-monitoring supported from K7 and later: */
-        if (boot_cpu_data.x86 < 6)
-                return -ENODEV;
-
-        x86_pmu = amd_pmu;
-
-        /* Events are common for all AMDs */
-        memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
-               sizeof(hw_cache_event_ids));
-
-        return 0;
-}
+#include "perf_event_amd.c"
+#include "perf_event_p6.c"
+#include "perf_event_intel.c"
 
 static void __init pmu_check_apic(void)
 {
@@ -2220,6 +1391,10 @@ void __init init_hw_perf_events(void)
         perf_events_lapic_init();
         register_die_notifier(&perf_event_nmi_notifier);
 
+        unconstrained = (struct event_constraint)
+                __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
+                                   0, x86_pmu.num_events);
+
         pr_info("... version:                %d\n",     x86_pmu.version);
         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
@@ -2237,50 +1412,79 @@ static inline void x86_pmu_read(struct perf_event *event)
 static const struct pmu pmu = {
         .enable         = x86_pmu_enable,
         .disable        = x86_pmu_disable,
+        .start          = x86_pmu_start,
+        .stop           = x86_pmu_stop,
         .read           = x86_pmu_read,
         .unthrottle     = x86_pmu_unthrottle,
 };
 
-static int
-validate_event(struct cpu_hw_events *cpuc, struct perf_event *event)
-{
-        struct hw_perf_event fake_event = event->hw;
-
-        if (event->pmu && event->pmu != &pmu)
-                return 0;
-
-        return x86_schedule_event(cpuc, &fake_event) >= 0;
-}
-
+/*
+ * validate a single event group
+ *
+ * validation include:
+ *      - check events are compatible which each other
+ *      - events do not compete for the same counter
+ *      - number of events <= number of counters
+ *
+ * validation ensures the group can be loaded onto the
+ * PMU if it was the only group available.
+ */
 static int validate_group(struct perf_event *event)
 {
-        struct perf_event *sibling, *leader = event->group_leader;
-        struct cpu_hw_events fake_pmu;
+        struct perf_event *leader = event->group_leader;
+        struct cpu_hw_events *fake_cpuc;
+        int ret, n;
 
-        memset(&fake_pmu, 0, sizeof(fake_pmu));
+        ret = -ENOMEM;
+        fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
+        if (!fake_cpuc)
+                goto out;
+
+        /*
+         * the event is not yet connected with its
+         * siblings therefore we must first collect
+         * existing siblings, then add the new event
+         * before we can simulate the scheduling
+         */
+        ret = -ENOSPC;
+        n = collect_events(fake_cpuc, leader, true);
+        if (n < 0)
+                goto out_free;
 
-        if (!validate_event(&fake_pmu, leader))
-                return -ENOSPC;
+        fake_cpuc->n_events = n;
+        n = collect_events(fake_cpuc, event, false);
+        if (n < 0)
+                goto out_free;
 
-        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
-                if (!validate_event(&fake_pmu, sibling))
-                        return -ENOSPC;
-        }
+        fake_cpuc->n_events = n;
 
-        if (!validate_event(&fake_pmu, event))
-                return -ENOSPC;
+        ret = x86_schedule_events(fake_cpuc, n, NULL);
 
-        return 0;
+out_free:
+        kfree(fake_cpuc);
+out:
+        return ret;
 }
 
 const struct pmu *hw_perf_event_init(struct perf_event *event)
 {
+        const struct pmu *tmp;
         int err;
 
         err = __hw_perf_event_init(event);
         if (!err) {
+                /*
+                 * we temporarily connect event to its pmu
+                 * such that validate_group() can classify
+                 * it as an x86 event using is_x86_event()
+                 */
+                tmp = event->pmu;
+                event->pmu = &pmu;
+
                 if (event->group_leader != event)
                         err = validate_group(event);
+
+                event->pmu = tmp;
         }
         if (err) {
                 if (event->destroy)
@@ -2304,7 +1508,6 @@ void callchain_store(struct perf_callchain_entry *entry, u64 ip)
 
 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
-static DEFINE_PER_CPU(int, in_ignored_frame);
 
 
 static void
@@ -2320,10 +1523,6 @@ static void backtrace_warning(void *data, char *msg)
 
 static int backtrace_stack(void *data, char *name)
 {
-        per_cpu(in_ignored_frame, smp_processor_id()) =
-                        x86_is_stack_id(NMI_STACK, name) ||
-                        x86_is_stack_id(DEBUG_STACK, name);
-
         return 0;
 }
 
@@ -2331,9 +1530,6 @@ static void backtrace_address(void *data, unsigned long addr, int reliable)
 {
         struct perf_callchain_entry *entry = data;
 
-        if (per_cpu(in_ignored_frame, smp_processor_id()))
-                return;
-
         if (reliable)
                 callchain_store(entry, addr);
 }
@@ -2440,9 +1636,6 @@ perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
 
         is_user = user_mode(regs);
 
-        if (!current || current->pid == 0)
-                return;
-
         if (is_user && current->state != TASK_RUNNING)
                 return;
 
@@ -2472,4 +1665,25 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
 void hw_perf_event_setup_online(int cpu)
 {
         init_debug_store_on_cpu(cpu);
+
+        switch (boot_cpu_data.x86_vendor) {
+        case X86_VENDOR_AMD:
+                amd_pmu_cpu_online(cpu);
+                break;
+        default:
+                return;
+        }
+}
+
+void hw_perf_event_setup_offline(int cpu)
+{
+        init_debug_store_on_cpu(cpu);
+
+        switch (boot_cpu_data.x86_vendor) {
+        case X86_VENDOR_AMD:
+                amd_pmu_cpu_offline(cpu);
+                break;
+        default:
+                return;
+        }
 }
diff --git a/arch/x86/kernel/cpu/perf_event_amd.c b/arch/x86/kernel/cpu/perf_event_amd.c
new file mode 100644
index 000000000000..8f3dbfda3c4f
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_amd.c
@@ -0,0 +1,416 @@
+#ifdef CONFIG_CPU_SUP_AMD
+
+static DEFINE_RAW_SPINLOCK(amd_nb_lock);
+
+static __initconst u64 amd_hw_cache_event_ids
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
+                [ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
+                [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
+        },
+ },
+ [ C(L1I ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
+                [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
+                [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(DTLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
+                [ C(RESULT_MISS)   ] = 0x0046, /* L1 DTLB and L2 DLTB Miss   */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(ITLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
+                [ C(RESULT_MISS)   ] = 0x0085, /* Instr. fetch ITLB misses   */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+ [ C(BPU ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
+                [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+};
+
+/*
+ * AMD Performance Monitor K7 and later.
+ */
+static const u64 amd_perfmon_event_map[] =
+{
+  [PERF_COUNT_HW_CPU_CYCLES]            = 0x0076,
+  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
+  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0080,
+  [PERF_COUNT_HW_CACHE_MISSES]          = 0x0081,
+  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
+  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
+};
+
+static u64 amd_pmu_event_map(int hw_event)
+{
+        return amd_perfmon_event_map[hw_event];
+}
+
+static u64 amd_pmu_raw_event(u64 hw_event)
+{
+#define K7_EVNTSEL_EVENT_MASK   0xF000000FFULL
+#define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
+#define K7_EVNTSEL_EDGE_MASK    0x000040000ULL
+#define K7_EVNTSEL_INV_MASK     0x000800000ULL
+#define K7_EVNTSEL_REG_MASK     0x0FF000000ULL
+
+#define K7_EVNTSEL_MASK                 \
+        (K7_EVNTSEL_EVENT_MASK |        \
+         K7_EVNTSEL_UNIT_MASK  |        \
+         K7_EVNTSEL_EDGE_MASK  |        \
+         K7_EVNTSEL_INV_MASK   |        \
+         K7_EVNTSEL_REG_MASK)
+
+        return hw_event & K7_EVNTSEL_MASK;
+}
+
+/*
+ * AMD64 events are detected based on their event codes.
+ */
+static inline int amd_is_nb_event(struct hw_perf_event *hwc)
+{
+        return (hwc->config & 0xe0) == 0xe0;
+}
+
+static void amd_put_event_constraints(struct cpu_hw_events *cpuc,
+                                      struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct amd_nb *nb = cpuc->amd_nb;
+        int i;
+
+        /*
+         * only care about NB events
+         */
+        if (!(nb && amd_is_nb_event(hwc)))
+                return;
+
+        /*
+         * need to scan whole list because event may not have
+         * been assigned during scheduling
+         *
+         * no race condition possible because event can only
+         * be removed on one CPU at a time AND PMU is disabled
+         * when we come here
+         */
+        for (i = 0; i < x86_pmu.num_events; i++) {
+                if (nb->owners[i] == event) {
+                        cmpxchg(nb->owners+i, event, NULL);
+                        break;
+                }
+        }
+}
+
+ /*
+  * AMD64 NorthBridge events need special treatment because
+  * counter access needs to be synchronized across all cores
+  * of a package. Refer to BKDG section 3.12
+  *
+  * NB events are events measuring L3 cache, Hypertransport
+  * traffic. They are identified by an event code >= 0xe00.
+  * They measure events on the NorthBride which is shared
+  * by all cores on a package. NB events are counted on a
+  * shared set of counters. When a NB event is programmed
+  * in a counter, the data actually comes from a shared
+  * counter. Thus, access to those counters needs to be
+  * synchronized.
+  *
+  * We implement the synchronization such that no two cores
+  * can be measuring NB events using the same counters. Thus,
+  * we maintain a per-NB allocation table. The available slot
+  * is propagated using the event_constraint structure.
+  *
+  * We provide only one choice for each NB event based on
+  * the fact that only NB events have restrictions. Consequently,
+  * if a counter is available, there is a guarantee the NB event
+  * will be assigned to it. If no slot is available, an empty
+  * constraint is returned and scheduling will eventually fail
+  * for this event.
+  *
+  * Note that all cores attached the same NB compete for the same
+  * counters to host NB events, this is why we use atomic ops. Some
+  * multi-chip CPUs may have more than one NB.
+  *
+  * Given that resources are allocated (cmpxchg), they must be
+  * eventually freed for others to use. This is accomplished by
+  * calling amd_put_event_constraints().
+  *
+  * Non NB events are not impacted by this restriction.
+  */
+static struct event_constraint *
+amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        struct amd_nb *nb = cpuc->amd_nb;
+        struct perf_event *old = NULL;
+        int max = x86_pmu.num_events;
+        int i, j, k = -1;
+
+        /*
+         * if not NB event or no NB, then no constraints
+         */
+        if (!(nb && amd_is_nb_event(hwc)))
+                return &unconstrained;
+
+        /*
+         * detect if already present, if so reuse
+         *
+         * cannot merge with actual allocation
+         * because of possible holes
+         *
+         * event can already be present yet not assigned (in hwc->idx)
+         * because of successive calls to x86_schedule_events() from
+         * hw_perf_group_sched_in() without hw_perf_enable()
+         */
+        for (i = 0; i < max; i++) {
+                /*
+                 * keep track of first free slot
+                 */
+                if (k == -1 && !nb->owners[i])
+                        k = i;
+
+                /* already present, reuse */
+                if (nb->owners[i] == event)
+                        goto done;
+        }
+        /*
+         * not present, so grab a new slot
+         * starting either at:
+         */
+        if (hwc->idx != -1) {
+                /* previous assignment */
+                i = hwc->idx;
+        } else if (k != -1) {
+                /* start from free slot found */
+                i = k;
+        } else {
+                /*
+                 * event not found, no slot found in
+                 * first pass, try again from the
+                 * beginning
+                 */
+                i = 0;
+        }
+        j = i;
+        do {
+                old = cmpxchg(nb->owners+i, NULL, event);
+                if (!old)
+                        break;
+                if (++i == max)
+                        i = 0;
+        } while (i != j);
+done:
+        if (!old)
+                return &nb->event_constraints[i];
+
+        return &emptyconstraint;
+}
+
+static __initconst struct x86_pmu amd_pmu = {
+        .name                   = "AMD",
+        .handle_irq             = x86_pmu_handle_irq,
+        .disable_all            = x86_pmu_disable_all,
+        .enable_all             = x86_pmu_enable_all,
+        .enable                 = x86_pmu_enable_event,
+        .disable                = x86_pmu_disable_event,
+        .eventsel               = MSR_K7_EVNTSEL0,
+        .perfctr                = MSR_K7_PERFCTR0,
+        .event_map              = amd_pmu_event_map,
+        .raw_event              = amd_pmu_raw_event,
+        .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
+        .num_events             = 4,
+        .event_bits             = 48,
+        .event_mask             = (1ULL << 48) - 1,
+        .apic                   = 1,
+        /* use highest bit to detect overflow */
+        .max_period             = (1ULL << 47) - 1,
+        .get_event_constraints  = amd_get_event_constraints,
+        .put_event_constraints  = amd_put_event_constraints
+};
+
+static struct amd_nb *amd_alloc_nb(int cpu, int nb_id)
+{
+        struct amd_nb *nb;
+        int i;
+
+        nb = kmalloc(sizeof(struct amd_nb), GFP_KERNEL);
+        if (!nb)
+                return NULL;
+
+        memset(nb, 0, sizeof(*nb));
+        nb->nb_id = nb_id;
+
+        /*
+         * initialize all possible NB constraints
+         */
+        for (i = 0; i < x86_pmu.num_events; i++) {
+                set_bit(i, nb->event_constraints[i].idxmsk);
+                nb->event_constraints[i].weight = 1;
+        }
+        return nb;
+}
+
+static void amd_pmu_cpu_online(int cpu)
+{
+        struct cpu_hw_events *cpu1, *cpu2;
+        struct amd_nb *nb = NULL;
+        int i, nb_id;
+
+        if (boot_cpu_data.x86_max_cores < 2)
+                return;
+
+        /*
+         * function may be called too early in the
+         * boot process, in which case nb_id is bogus
+         */
+        nb_id = amd_get_nb_id(cpu);
+        if (nb_id == BAD_APICID)
+                return;
+
+        cpu1 = &per_cpu(cpu_hw_events, cpu);
+        cpu1->amd_nb = NULL;
+
+        raw_spin_lock(&amd_nb_lock);
+
+        for_each_online_cpu(i) {
+                cpu2 = &per_cpu(cpu_hw_events, i);
+                nb = cpu2->amd_nb;
+                if (!nb)
+                        continue;
+                if (nb->nb_id == nb_id)
+                        goto found;
+        }
+
+        nb = amd_alloc_nb(cpu, nb_id);
+        if (!nb) {
+                pr_err("perf_events: failed NB allocation for CPU%d\n", cpu);
+                raw_spin_unlock(&amd_nb_lock);
+                return;
+        }
+found:
+        nb->refcnt++;
+        cpu1->amd_nb = nb;
+
+        raw_spin_unlock(&amd_nb_lock);
+}
+
+static void amd_pmu_cpu_offline(int cpu)
+{
+        struct cpu_hw_events *cpuhw;
+
+        if (boot_cpu_data.x86_max_cores < 2)
+                return;
+
+        cpuhw = &per_cpu(cpu_hw_events, cpu);
+
+        raw_spin_lock(&amd_nb_lock);
+
+        if (--cpuhw->amd_nb->refcnt == 0)
+                kfree(cpuhw->amd_nb);
+
+        cpuhw->amd_nb = NULL;
+
+        raw_spin_unlock(&amd_nb_lock);
+}
+
+static __init int amd_pmu_init(void)
+{
+        /* Performance-monitoring supported from K7 and later: */
+        if (boot_cpu_data.x86 < 6)
+                return -ENODEV;
+
+        x86_pmu = amd_pmu;
+
+        /* Events are common for all AMDs */
+        memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
+               sizeof(hw_cache_event_ids));
+
+        /*
+         * explicitly initialize the boot cpu, other cpus will get
+         * the cpu hotplug callbacks from smp_init()
+         */
+        amd_pmu_cpu_online(smp_processor_id());
+        return 0;
+}
+
+#else /* CONFIG_CPU_SUP_AMD */
+
+static int amd_pmu_init(void)
+{
+        return 0;
+}
+
+static void amd_pmu_cpu_online(int cpu)
+{
+}
+
+static void amd_pmu_cpu_offline(int cpu)
+{
+}
+
+#endif
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
new file mode 100644
index 000000000000..cf6590cf4a5f
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -0,0 +1,971 @@
+#ifdef CONFIG_CPU_SUP_INTEL
+
+/*
+ * Intel PerfMon v3. Used on Core2 and later.
+ */
+static const u64 intel_perfmon_event_map[] =
+{
+  [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
+  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
+  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
+  [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
+  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
+  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
+  [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
+};
+
+static struct event_constraint intel_core_event_constraints[] =
+{
+        INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
+        INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
+        INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
+        INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
+        INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
+        INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
+        EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_core2_event_constraints[] =
+{
+        FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
+        FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
+        INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
+        INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
+        INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
+        INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
+        INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
+        INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
+        INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
+        INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
+        INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
+        EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_nehalem_event_constraints[] =
+{
+        FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
+        FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
+        INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
+        INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
+        INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
+        INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
+        INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
+        INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
+        INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
+        INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
+        EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_westmere_event_constraints[] =
+{
+        FIXED_EVENT_CONSTRAINT(0xc0, (0xf|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
+        FIXED_EVENT_CONSTRAINT(0x3c, (0xf|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
+        INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
+        INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
+        INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
+        EVENT_CONSTRAINT_END
+};
+
+static struct event_constraint intel_gen_event_constraints[] =
+{
+        FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
+        FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
+        EVENT_CONSTRAINT_END
+};
+
+static u64 intel_pmu_event_map(int hw_event)
+{
+        return intel_perfmon_event_map[hw_event];
+}
+
+static __initconst u64 westmere_hw_cache_event_ids
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
+                [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
+                [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
+                [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
+        },
+ },
+ [ C(L1I ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
+                [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0x0,
+        },
+ },
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
+                [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
+                [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
+                [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
+        },
+ },
+ [ C(DTLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
+                [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
+                [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0x0,
+        },
+ },
+ [ C(ITLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
+                [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+ [ C(BPU ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
+                [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+};
+
+static __initconst u64 nehalem_hw_cache_event_ids
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
+                [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
+                [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
+                [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
+        },
+ },
+ [ C(L1I ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
+                [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0x0,
+        },
+ },
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
+                [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
+                [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
+                [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
+        },
+ },
+ [ C(DTLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
+                [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
+                [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0x0,
+        },
+ },
+ [ C(ITLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
+                [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+ [ C(BPU ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
+                [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+};
+
+static __initconst u64 core2_hw_cache_event_ids
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
+                [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
+                [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(L1I ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
+                [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
+                [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
+                [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(DTLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
+                [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
+                [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(ITLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
+                [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+ [ C(BPU ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
+                [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+};
+
+static __initconst u64 atom_hw_cache_event_ids
+                                [PERF_COUNT_HW_CACHE_MAX]
+                                [PERF_COUNT_HW_CACHE_OP_MAX]
+                                [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(L1D) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
+                [ C(RESULT_MISS)   ] = 0,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(L1I ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
+                [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(LL  ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
+                [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
+                [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(DTLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
+                [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
+                [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = 0,
+                [ C(RESULT_MISS)   ] = 0,
+        },
+ },
+ [ C(ITLB) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
+                [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+ [ C(BPU ) ] = {
+        [ C(OP_READ) ] = {
+                [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
+                [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
+        },
+        [ C(OP_WRITE) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+        [ C(OP_PREFETCH) ] = {
+                [ C(RESULT_ACCESS) ] = -1,
+                [ C(RESULT_MISS)   ] = -1,
+        },
+ },
+};
+
+static u64 intel_pmu_raw_event(u64 hw_event)
+{
+#define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
+#define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
+#define CORE_EVNTSEL_EDGE_MASK          0x00040000ULL
+#define CORE_EVNTSEL_INV_MASK           0x00800000ULL
+#define CORE_EVNTSEL_REG_MASK           0xFF000000ULL
+
+#define CORE_EVNTSEL_MASK               \
+        (INTEL_ARCH_EVTSEL_MASK |       \
+         INTEL_ARCH_UNIT_MASK   |       \
+         INTEL_ARCH_EDGE_MASK   |       \
+         INTEL_ARCH_INV_MASK    |       \
+         INTEL_ARCH_CNT_MASK)
+
+        return hw_event & CORE_EVNTSEL_MASK;
+}
+
+static void intel_pmu_enable_bts(u64 config)
+{
+        unsigned long debugctlmsr;
+
+        debugctlmsr = get_debugctlmsr();
+
+        debugctlmsr |= X86_DEBUGCTL_TR;
+        debugctlmsr |= X86_DEBUGCTL_BTS;
+        debugctlmsr |= X86_DEBUGCTL_BTINT;
+
+        if (!(config & ARCH_PERFMON_EVENTSEL_OS))
+                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
+
+        if (!(config & ARCH_PERFMON_EVENTSEL_USR))
+                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
+
+        update_debugctlmsr(debugctlmsr);
+}
+
+static void intel_pmu_disable_bts(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        unsigned long debugctlmsr;
+
+        if (!cpuc->ds)
+                return;
+
+        debugctlmsr = get_debugctlmsr();
+
+        debugctlmsr &=
+                ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
+                  X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
+
+        update_debugctlmsr(debugctlmsr);
+}
+
+static void intel_pmu_disable_all(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+
+        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
+                intel_pmu_disable_bts();
+}
+
+static void intel_pmu_enable_all(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
+
+        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
+                struct perf_event *event =
+                        cpuc->events[X86_PMC_IDX_FIXED_BTS];
+
+                if (WARN_ON_ONCE(!event))
+                        return;
+
+                intel_pmu_enable_bts(event->hw.config);
+        }
+}
+
+static inline u64 intel_pmu_get_status(void)
+{
+        u64 status;
+
+        rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
+
+        return status;
+}
+
+static inline void intel_pmu_ack_status(u64 ack)
+{
+        wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
+}
+
+static inline void
+intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
+{
+        int idx = __idx - X86_PMC_IDX_FIXED;
+        u64 ctrl_val, mask;
+
+        mask = 0xfULL << (idx * 4);
+
+        rdmsrl(hwc->config_base, ctrl_val);
+        ctrl_val &= ~mask;
+        (void)checking_wrmsrl(hwc->config_base, ctrl_val);
+}
+
+static void intel_pmu_drain_bts_buffer(void)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct debug_store *ds = cpuc->ds;
+        struct bts_record {
+                u64     from;
+                u64     to;
+                u64     flags;
+        };
+        struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
+        struct bts_record *at, *top;
+        struct perf_output_handle handle;
+        struct perf_event_header header;
+        struct perf_sample_data data;
+        struct pt_regs regs;
+
+        if (!event)
+                return;
+
+        if (!ds)
+                return;
+
+        at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
+        top = (struct bts_record *)(unsigned long)ds->bts_index;
+
+        if (top <= at)
+                return;
+
+        ds->bts_index = ds->bts_buffer_base;
+
+
+        data.period     = event->hw.last_period;
+        data.addr       = 0;
+        data.raw        = NULL;
+        regs.ip         = 0;
+
+        /*
+         * Prepare a generic sample, i.e. fill in the invariant fields.
+         * We will overwrite the from and to address before we output
+         * the sample.
+         */
+        perf_prepare_sample(&header, &data, event, &regs);
+
+        if (perf_output_begin(&handle, event,
+                              header.size * (top - at), 1, 1))
+                return;
+
+        for (; at < top; at++) {
+                data.ip         = at->from;
+                data.addr       = at->to;
+
+                perf_output_sample(&handle, &header, &data, event);
+        }
+
+        perf_output_end(&handle);
+
+        /* There's new data available. */
+        event->hw.interrupts++;
+        event->pending_kill = POLL_IN;
+}
+
+static inline void
+intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
+                intel_pmu_disable_bts();
+                intel_pmu_drain_bts_buffer();
+                return;
+        }
+
+        if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
+                intel_pmu_disable_fixed(hwc, idx);
+                return;
+        }
+
+        x86_pmu_disable_event(hwc, idx);
+}
+
+static inline void
+intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
+{
+        int idx = __idx - X86_PMC_IDX_FIXED;
+        u64 ctrl_val, bits, mask;
+        int err;
+
+        /*
+         * Enable IRQ generation (0x8),
+         * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
+         * if requested:
+         */
+        bits = 0x8ULL;
+        if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
+                bits |= 0x2;
+        if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
+                bits |= 0x1;
+
+        /*
+         * ANY bit is supported in v3 and up
+         */
+        if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
+                bits |= 0x4;
+
+        bits <<= (idx * 4);
+        mask = 0xfULL << (idx * 4);
+
+        rdmsrl(hwc->config_base, ctrl_val);
+        ctrl_val &= ~mask;
+        ctrl_val |= bits;
+        err = checking_wrmsrl(hwc->config_base, ctrl_val);
+}
+
+static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
+                if (!__get_cpu_var(cpu_hw_events).enabled)
+                        return;
+
+                intel_pmu_enable_bts(hwc->config);
+                return;
+        }
+
+        if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
+                intel_pmu_enable_fixed(hwc, idx);
+                return;
+        }
+
+        __x86_pmu_enable_event(hwc, idx);
+}
+
+/*
+ * Save and restart an expired event. Called by NMI contexts,
+ * so it has to be careful about preempting normal event ops:
+ */
+static int intel_pmu_save_and_restart(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        int ret;
+
+        x86_perf_event_update(event, hwc, idx);
+        ret = x86_perf_event_set_period(event, hwc, idx);
+
+        return ret;
+}
+
+static void intel_pmu_reset(void)
+{
+        struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
+        unsigned long flags;
+        int idx;
+
+        if (!x86_pmu.num_events)
+                return;
+
+        local_irq_save(flags);
+
+        printk("clearing PMU state on CPU#%d\n", smp_processor_id());
+
+        for (idx = 0; idx < x86_pmu.num_events; idx++) {
+                checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
+                checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
+        }
+        for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
+                checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
+        }
+        if (ds)
+                ds->bts_index = ds->bts_buffer_base;
+
+        local_irq_restore(flags);
+}
+
+/*
+ * This handler is triggered by the local APIC, so the APIC IRQ handling
+ * rules apply:
+ */
+static int intel_pmu_handle_irq(struct pt_regs *regs)
+{
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        int bit, loops;
+        u64 ack, status;
+
+        data.addr = 0;
+        data.raw = NULL;
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+
+        perf_disable();
+        intel_pmu_drain_bts_buffer();
+        status = intel_pmu_get_status();
+        if (!status) {
+                perf_enable();
+                return 0;
+        }
+
+        loops = 0;
+again:
+        if (++loops > 100) {
+                WARN_ONCE(1, "perfevents: irq loop stuck!\n");
+                perf_event_print_debug();
+                intel_pmu_reset();
+                perf_enable();
+                return 1;
+        }
+
+        inc_irq_stat(apic_perf_irqs);
+        ack = status;
+        for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
+                struct perf_event *event = cpuc->events[bit];
+
+                clear_bit(bit, (unsigned long *) &status);
+                if (!test_bit(bit, cpuc->active_mask))
+                        continue;
+
+                if (!intel_pmu_save_and_restart(event))
+                        continue;
+
+                data.period = event->hw.last_period;
+
+                if (perf_event_overflow(event, 1, &data, regs))
+                        intel_pmu_disable_event(&event->hw, bit);
+        }
+
+        intel_pmu_ack_status(ack);
+
+        /*
+         * Repeat if there is more work to be done:
+         */
+        status = intel_pmu_get_status();
+        if (status)
+                goto again;
+
+        perf_enable();
+
+        return 1;
+}
+
+static struct event_constraint bts_constraint =
+        EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
+
+static struct event_constraint *
+intel_special_constraints(struct perf_event *event)
+{
+        unsigned int hw_event;
+
+        hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK;
+
+        if (unlikely((hw_event ==
+                      x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
+                     (event->hw.sample_period == 1))) {
+
+                return &bts_constraint;
+        }
+        return NULL;
+}
+
+static struct event_constraint *
+intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
+{
+        struct event_constraint *c;
+
+        c = intel_special_constraints(event);
+        if (c)
+                return c;
+
+        return x86_get_event_constraints(cpuc, event);
+}
+
+static __initconst struct x86_pmu core_pmu = {
+        .name                   = "core",
+        .handle_irq             = x86_pmu_handle_irq,
+        .disable_all            = x86_pmu_disable_all,
+        .enable_all             = x86_pmu_enable_all,
+        .enable                 = x86_pmu_enable_event,
+        .disable                = x86_pmu_disable_event,
+        .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
+        .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
+        .event_map              = intel_pmu_event_map,
+        .raw_event              = intel_pmu_raw_event,
+        .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
+        .apic                   = 1,
+        /*
+         * Intel PMCs cannot be accessed sanely above 32 bit width,
+         * so we install an artificial 1<<31 period regardless of
+         * the generic event period:
+         */
+        .max_period             = (1ULL << 31) - 1,
+        .get_event_constraints  = intel_get_event_constraints,
+        .event_constraints      = intel_core_event_constraints,
+};
+
+static __initconst struct x86_pmu intel_pmu = {
+        .name                   = "Intel",
+        .handle_irq             = intel_pmu_handle_irq,
+        .disable_all            = intel_pmu_disable_all,
+        .enable_all             = intel_pmu_enable_all,
+        .enable                 = intel_pmu_enable_event,
+        .disable                = intel_pmu_disable_event,
+        .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
+        .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
+        .event_map              = intel_pmu_event_map,
+        .raw_event              = intel_pmu_raw_event,
+        .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
+        .apic                   = 1,
+        /*
+         * Intel PMCs cannot be accessed sanely above 32 bit width,
+         * so we install an artificial 1<<31 period regardless of
+         * the generic event period:
+         */
+        .max_period             = (1ULL << 31) - 1,
+        .enable_bts             = intel_pmu_enable_bts,
+        .disable_bts            = intel_pmu_disable_bts,
+        .get_event_constraints  = intel_get_event_constraints
+};
+
+static __init int intel_pmu_init(void)
+{
+        union cpuid10_edx edx;
+        union cpuid10_eax eax;
+        unsigned int unused;
+        unsigned int ebx;
+        int version;
+
+        if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
+                /* check for P6 processor family */
+           if (boot_cpu_data.x86 == 6) {
+                return p6_pmu_init();
+           } else {
+                return -ENODEV;
+           }
+        }
+
+        /*
+         * Check whether the Architectural PerfMon supports
+         * Branch Misses Retired hw_event or not.
+         */
+        cpuid(10, &eax.full, &ebx, &unused, &edx.full);
+        if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
+                return -ENODEV;
+
+        version = eax.split.version_id;
+        if (version < 2)
+                x86_pmu = core_pmu;
+        else
+                x86_pmu = intel_pmu;
+
+        x86_pmu.version                 = version;
+        x86_pmu.num_events              = eax.split.num_events;
+        x86_pmu.event_bits              = eax.split.bit_width;
+        x86_pmu.event_mask              = (1ULL << eax.split.bit_width) - 1;
+
+        /*
+         * Quirk: v2 perfmon does not report fixed-purpose events, so
+         * assume at least 3 events:
+         */
+        if (version > 1)
+                x86_pmu.num_events_fixed = max((int)edx.split.num_events_fixed, 3);
+
+        /*
+         * Install the hw-cache-events table:
+         */
+        switch (boot_cpu_data.x86_model) {
+        case 14: /* 65 nm core solo/duo, "Yonah" */
+                pr_cont("Core events, ");
+                break;
+
+        case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
+        case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
+        case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
+        case 29: /* six-core 45 nm xeon "Dunnington" */
+                memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
+                       sizeof(hw_cache_event_ids));
+
+                x86_pmu.event_constraints = intel_core2_event_constraints;
+                pr_cont("Core2 events, ");
+                break;
+
+        case 26: /* 45 nm nehalem, "Bloomfield" */
+        case 30: /* 45 nm nehalem, "Lynnfield" */
+                memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
+                       sizeof(hw_cache_event_ids));
+
+                x86_pmu.event_constraints = intel_nehalem_event_constraints;
+                pr_cont("Nehalem/Corei7 events, ");
+                break;
+        case 28:
+                memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
+                       sizeof(hw_cache_event_ids));
+
+                x86_pmu.event_constraints = intel_gen_event_constraints;
+                pr_cont("Atom events, ");
+                break;
+
+        case 37: /* 32 nm nehalem, "Clarkdale" */
+        case 44: /* 32 nm nehalem, "Gulftown" */
+                memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
+                       sizeof(hw_cache_event_ids));
+
+                x86_pmu.event_constraints = intel_westmere_event_constraints;
+                pr_cont("Westmere events, ");
+                break;
+        default:
+                /*
+                 * default constraints for v2 and up
+                 */
+                x86_pmu.event_constraints = intel_gen_event_constraints;
+                pr_cont("generic architected perfmon, ");
+        }
+        return 0;
+}
+
+#else /* CONFIG_CPU_SUP_INTEL */
+
+static int intel_pmu_init(void)
+{
+        return 0;
+}
+
+#endif /* CONFIG_CPU_SUP_INTEL */
diff --git a/arch/x86/kernel/cpu/perf_event_p6.c b/arch/x86/kernel/cpu/perf_event_p6.c
new file mode 100644
index 000000000000..1ca5ba078afd
--- /dev/null
+++ b/arch/x86/kernel/cpu/perf_event_p6.c
@@ -0,0 +1,157 @@
+#ifdef CONFIG_CPU_SUP_INTEL
+
+/*
+ * Not sure about some of these
+ */
+static const u64 p6_perfmon_event_map[] =
+{
+  [PERF_COUNT_HW_CPU_CYCLES]            = 0x0079,
+  [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
+  [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0f2e,
+  [PERF_COUNT_HW_CACHE_MISSES]          = 0x012e,
+  [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
+  [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
+  [PERF_COUNT_HW_BUS_CYCLES]            = 0x0062,
+};
+
+static u64 p6_pmu_event_map(int hw_event)
+{
+        return p6_perfmon_event_map[hw_event];
+}
+
+/*
+ * Event setting that is specified not to count anything.
+ * We use this to effectively disable a counter.
+ *
+ * L2_RQSTS with 0 MESI unit mask.
+ */
+#define P6_NOP_EVENT                    0x0000002EULL
+
+static u64 p6_pmu_raw_event(u64 hw_event)
+{
+#define P6_EVNTSEL_EVENT_MASK           0x000000FFULL
+#define P6_EVNTSEL_UNIT_MASK            0x0000FF00ULL
+#define P6_EVNTSEL_EDGE_MASK            0x00040000ULL
+#define P6_EVNTSEL_INV_MASK             0x00800000ULL
+#define P6_EVNTSEL_REG_MASK             0xFF000000ULL
+
+#define P6_EVNTSEL_MASK                 \
+        (P6_EVNTSEL_EVENT_MASK |        \
+         P6_EVNTSEL_UNIT_MASK  |        \
+         P6_EVNTSEL_EDGE_MASK  |        \
+         P6_EVNTSEL_INV_MASK   |        \
+         P6_EVNTSEL_REG_MASK)
+
+        return hw_event & P6_EVNTSEL_MASK;
+}
+
+static struct event_constraint p6_event_constraints[] =
+{
+        INTEL_EVENT_CONSTRAINT(0xc1, 0x1),      /* FLOPS */
+        INTEL_EVENT_CONSTRAINT(0x10, 0x1),      /* FP_COMP_OPS_EXE */
+        INTEL_EVENT_CONSTRAINT(0x11, 0x1),      /* FP_ASSIST */
+        INTEL_EVENT_CONSTRAINT(0x12, 0x2),      /* MUL */
+        INTEL_EVENT_CONSTRAINT(0x13, 0x2),      /* DIV */
+        INTEL_EVENT_CONSTRAINT(0x14, 0x1),      /* CYCLES_DIV_BUSY */
+        EVENT_CONSTRAINT_END
+};
+
+static void p6_pmu_disable_all(void)
+{
+        u64 val;
+
+        /* p6 only has one enable register */
+        rdmsrl(MSR_P6_EVNTSEL0, val);
+        val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
+        wrmsrl(MSR_P6_EVNTSEL0, val);
+}
+
+static void p6_pmu_enable_all(void)
+{
+        unsigned long val;
+
+        /* p6 only has one enable register */
+        rdmsrl(MSR_P6_EVNTSEL0, val);
+        val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+        wrmsrl(MSR_P6_EVNTSEL0, val);
+}
+
+static inline void
+p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        u64 val = P6_NOP_EVENT;
+
+        if (cpuc->enabled)
+                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+
+        (void)checking_wrmsrl(hwc->config_base + idx, val);
+}
+
+static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        u64 val;
+
+        val = hwc->config;
+        if (cpuc->enabled)
+                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
+
+        (void)checking_wrmsrl(hwc->config_base + idx, val);
+}
+
+static __initconst struct x86_pmu p6_pmu = {
+        .name                   = "p6",
+        .handle_irq             = x86_pmu_handle_irq,
+        .disable_all            = p6_pmu_disable_all,
+        .enable_all             = p6_pmu_enable_all,
+        .enable                 = p6_pmu_enable_event,
+        .disable                = p6_pmu_disable_event,
+        .eventsel               = MSR_P6_EVNTSEL0,
+        .perfctr                = MSR_P6_PERFCTR0,
+        .event_map              = p6_pmu_event_map,
+        .raw_event              = p6_pmu_raw_event,
+        .max_events             = ARRAY_SIZE(p6_perfmon_event_map),
+        .apic                   = 1,
+        .max_period             = (1ULL << 31) - 1,
+        .version                = 0,
+        .num_events             = 2,
+        /*
+         * Events have 40 bits implemented. However they are designed such
+         * that bits [32-39] are sign extensions of bit 31. As such the
+         * effective width of a event for P6-like PMU is 32 bits only.
+         *
+         * See IA-32 Intel Architecture Software developer manual Vol 3B
+         */
+        .event_bits             = 32,
+        .event_mask             = (1ULL << 32) - 1,
+        .get_event_constraints  = x86_get_event_constraints,
+        .event_constraints      = p6_event_constraints,
+};
+
+static __init int p6_pmu_init(void)
+{
+        switch (boot_cpu_data.x86_model) {
+        case 1:
+        case 3:  /* Pentium Pro */
+        case 5:
+        case 6:  /* Pentium II */
+        case 7:
+        case 8:
+        case 11: /* Pentium III */
+        case 9:
+        case 13:
+                /* Pentium M */
+                break;
+        default:
+                pr_cont("unsupported p6 CPU model %d ",
+                        boot_cpu_data.x86_model);
+                return -ENODEV;
+        }
+
+        x86_pmu = p6_pmu;
+
+        return 0;
+}
+
+#endif /* CONFIG_CPU_SUP_INTEL */
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 898df9719afb..74f4e85a5727 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -115,17 +115,6 @@ int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 
         return !test_bit(counter, perfctr_nmi_owner);
 }
-
-/* checks the an msr for availability */
-int avail_to_resrv_perfctr_nmi(unsigned int msr)
-{
-        unsigned int counter;
-
-        counter = nmi_perfctr_msr_to_bit(msr);
-        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
-
-        return !test_bit(counter, perfctr_nmi_owner);
-}
 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 
 int reserve_perfctr_nmi(unsigned int msr)
diff --git a/arch/x86/kernel/dumpstack_32.c b/arch/x86/kernel/dumpstack_32.c
index ae775ca47b25..11540a189d93 100644
--- a/arch/x86/kernel/dumpstack_32.c
+++ b/arch/x86/kernel/dumpstack_32.c
@@ -18,11 +18,6 @@
 
 #include "dumpstack.h"
 
-/* Just a stub for now */
-int x86_is_stack_id(int id, char *name)
-{
-        return 0;
-}
 
 void dump_trace(struct task_struct *task, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp,
diff --git a/arch/x86/kernel/dumpstack_64.c b/arch/x86/kernel/dumpstack_64.c
index 0ad9597073f5..dce99abb4496 100644
--- a/arch/x86/kernel/dumpstack_64.c
+++ b/arch/x86/kernel/dumpstack_64.c
@@ -33,11 +33,6 @@ static char x86_stack_ids[][8] = {
 #endif
 };
 
-int x86_is_stack_id(int id, char *name)
-{
-        return x86_stack_ids[id - 1] == name;
-}
-
 static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
                                          unsigned *usedp, char **idp)
 {
@@ -291,6 +286,7 @@ void show_registers(struct pt_regs *regs)
 
         sp = regs->sp;
         printk("CPU %d ", cpu);
+        print_modules();
         __show_regs(regs, 1);
         printk("Process %s (pid: %d, threadinfo %p, task %p)\n",
                 cur->comm, cur->pid, task_thread_info(cur), cur);
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index a1a7876cadcb..a966b753e496 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -517,11 +517,19 @@ u64 __init e820_remove_range(u64 start, u64 size, unsigned old_type,
                              int checktype)
 {
         int i;
+        u64 end;
         u64 real_removed_size = 0;
 
         if (size > (ULLONG_MAX - start))
                 size = ULLONG_MAX - start;
 
+        end = start + size;
+        printk(KERN_DEBUG "e820 remove range: %016Lx - %016Lx ",
+                       (unsigned long long) start,
+                       (unsigned long long) end);
+        e820_print_type(old_type);
+        printk(KERN_CONT "\n");
+
         for (i = 0; i < e820.nr_map; i++) {
                 struct e820entry *ei = &e820.map[i];
                 u64 final_start, final_end;
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index cdcfb122f256..c2fa9b8b497e 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -362,7 +362,7 @@ void __init efi_init(void)
                 printk(KERN_ERR PFX "Could not map the firmware vendor!\n");
         early_iounmap(tmp, 2);
 
-        printk(KERN_INFO "EFI v%u.%.02u by %s \n",
+        printk(KERN_INFO "EFI v%u.%.02u by %s\n",
                efi.systab->hdr.revision >> 16,
                efi.systab->hdr.revision & 0xffff, vendor);
 
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index 309689245431..cd37469b54ee 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -30,14 +30,32 @@
 
 #ifdef CONFIG_DYNAMIC_FTRACE
 
+/*
+ * modifying_code is set to notify NMIs that they need to use
+ * memory barriers when entering or exiting. But we don't want
+ * to burden NMIs with unnecessary memory barriers when code
+ * modification is not being done (which is most of the time).
+ *
+ * A mutex is already held when ftrace_arch_code_modify_prepare
+ * and post_process are called. No locks need to be taken here.
+ *
+ * Stop machine will make sure currently running NMIs are done
+ * and new NMIs will see the updated variable before we need
+ * to worry about NMIs doing memory barriers.
+ */
+static int modifying_code __read_mostly;
+static DEFINE_PER_CPU(int, save_modifying_code);
+
 int ftrace_arch_code_modify_prepare(void)
 {
         set_kernel_text_rw();
+        modifying_code = 1;
         return 0;
 }
 
 int ftrace_arch_code_modify_post_process(void)
 {
+        modifying_code = 0;
         set_kernel_text_ro();
         return 0;
 }
@@ -149,6 +167,11 @@ static void ftrace_mod_code(void)
 
 void ftrace_nmi_enter(void)
 {
+        __get_cpu_var(save_modifying_code) = modifying_code;
+
+        if (!__get_cpu_var(save_modifying_code))
+                return;
+
         if (atomic_inc_return(&nmi_running) & MOD_CODE_WRITE_FLAG) {
                 smp_rmb();
                 ftrace_mod_code();
@@ -160,6 +183,9 @@ void ftrace_nmi_enter(void)
 
 void ftrace_nmi_exit(void)
 {
+        if (!__get_cpu_var(save_modifying_code))
+                return;
+
         /* Finish all executions before clearing nmi_running */
         smp_mb();
         atomic_dec(&nmi_running);
@@ -484,13 +510,3 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
         }
 }
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
-
-#ifdef CONFIG_FTRACE_SYSCALLS
-
-extern unsigned long *sys_call_table;
-
-unsigned long __init arch_syscall_addr(int nr)
-{
-        return (unsigned long)(&sys_call_table)[nr];
-}
-#endif
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index ad80a1c718c6..ee4fa1bfcb33 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -266,7 +266,7 @@ static void hpet_resume_device(void)
         force_hpet_resume();
 }
 
-static void hpet_resume_counter(void)
+static void hpet_resume_counter(struct clocksource *cs)
 {
         hpet_resume_device();
         hpet_restart_counter();
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 05d5fec64a94..dca2802c666f 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c
@@ -212,25 +212,6 @@ static int arch_check_va_in_kernelspace(unsigned long va, u8 hbp_len)
         return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
 }
 
-/*
- * Store a breakpoint's encoded address, length, and type.
- */
-static int arch_store_info(struct perf_event *bp)
-{
-        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
-        /*
-         * For kernel-addresses, either the address or symbol name can be
-         * specified.
-         */
-        if (info->name)
-                info->address = (unsigned long)
-                                kallsyms_lookup_name(info->name);
-        if (info->address)
-                return 0;
-
-        return -EINVAL;
-}
-
 int arch_bp_generic_fields(int x86_len, int x86_type,
                            int *gen_len, int *gen_type)
 {
@@ -362,10 +343,13 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp,
                 return ret;
         }
 
-        ret = arch_store_info(bp);
-
-        if (ret < 0)
-                return ret;
+        /*
+         * For kernel-addresses, either the address or symbol name can be
+         * specified.
+         */
+        if (info->name)
+                info->address = (unsigned long)
+                                kallsyms_lookup_name(info->name);
         /*
          * Check that the low-order bits of the address are appropriate
          * for the alignment implied by len.
@@ -502,8 +486,6 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
                 rcu_read_lock();
 
                 bp = per_cpu(bp_per_reg[i], cpu);
-                if (bp)
-                        rc = NOTIFY_DONE;
                 /*
                  * Reset the 'i'th TRAP bit in dr6 to denote completion of
                  * exception handling
@@ -522,7 +504,13 @@ static int __kprobes hw_breakpoint_handler(struct die_args *args)
 
                 rcu_read_unlock();
         }
-        if (dr6 & (~DR_TRAP_BITS))
+        /*
+         * Further processing in do_debug() is needed for a) user-space
+         * breakpoints (to generate signals) and b) when the system has
+         * taken exception due to multiple causes
+         */
+        if ((current->thread.debugreg6 & DR_TRAP_BITS) ||
+            (dr6 & (~DR_TRAP_BITS)))
                 rc = NOTIFY_DONE;
 
         set_debugreg(dr7, 7);
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index f2f8540a7f3d..c01a2b846d47 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -164,6 +164,11 @@ int init_fpu(struct task_struct *tsk)
         return 0;
 }
 
+/*
+ * The xstateregs_active() routine is the same as the fpregs_active() routine,
+ * as the "regset->n" for the xstate regset will be updated based on the feature
+ * capabilites supported by the xsave.
+ */
 int fpregs_active(struct task_struct *target, const struct user_regset *regset)
 {
         return tsk_used_math(target) ? regset->n : 0;
@@ -204,8 +209,6 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
         if (ret)
                 return ret;
 
-        set_stopped_child_used_math(target);
-
         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
                                  &target->thread.xstate->fxsave, 0, -1);
 
@@ -224,6 +227,68 @@ int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
         return ret;
 }
 
+int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
+                unsigned int pos, unsigned int count,
+                void *kbuf, void __user *ubuf)
+{
+        int ret;
+
+        if (!cpu_has_xsave)
+                return -ENODEV;
+
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
+
+        /*
+         * Copy the 48bytes defined by the software first into the xstate
+         * memory layout in the thread struct, so that we can copy the entire
+         * xstateregs to the user using one user_regset_copyout().
+         */
+        memcpy(&target->thread.xstate->fxsave.sw_reserved,
+               xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
+
+        /*
+         * Copy the xstate memory layout.
+         */
+        ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+                                  &target->thread.xstate->xsave, 0, -1);
+        return ret;
+}
+
+int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
+                  unsigned int pos, unsigned int count,
+                  const void *kbuf, const void __user *ubuf)
+{
+        int ret;
+        struct xsave_hdr_struct *xsave_hdr;
+
+        if (!cpu_has_xsave)
+                return -ENODEV;
+
+        ret = init_fpu(target);
+        if (ret)
+                return ret;
+
+        ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+                                 &target->thread.xstate->xsave, 0, -1);
+
+        /*
+         * mxcsr reserved bits must be masked to zero for security reasons.
+         */
+        target->thread.xstate->fxsave.mxcsr &= mxcsr_feature_mask;
+
+        xsave_hdr = &target->thread.xstate->xsave.xsave_hdr;
+
+        xsave_hdr->xstate_bv &= pcntxt_mask;
+        /*
+         * These bits must be zero.
+         */
+        xsave_hdr->reserved1[0] = xsave_hdr->reserved1[1] = 0;
+
+        return ret;
+}
+
 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
 
 /*
@@ -404,8 +469,6 @@ int fpregs_set(struct task_struct *target, const struct user_regset *regset,
         if (ret)
                 return ret;
 
-        set_stopped_child_used_math(target);
-
         if (!HAVE_HWFP)
                 return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
 
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c
index 5b8c7505b3bc..5de9f4a9c3fd 100644
--- a/arch/x86/kernel/kprobes.c
+++ b/arch/x86/kernel/kprobes.c
@@ -337,6 +337,9 @@ static void __kprobes arch_copy_kprobe(struct kprobe *p)
 
 int __kprobes arch_prepare_kprobe(struct kprobe *p)
 {
+        if (alternatives_text_reserved(p->addr, p->addr))
+                return -EINVAL;
+
         if (!can_probe((unsigned long)p->addr))
                 return -EILSEQ;
         /* insn: must be on special executable page on x86. */
@@ -429,7 +432,7 @@ void __kprobes arch_prepare_kretprobe(struct kretprobe_instance *ri,
 static void __kprobes setup_singlestep(struct kprobe *p, struct pt_regs *regs,
                                        struct kprobe_ctlblk *kcb)
 {
-#if !defined(CONFIG_PREEMPT) || defined(CONFIG_FREEZER)
+#if !defined(CONFIG_PREEMPT)
         if (p->ainsn.boostable == 1 && !p->post_handler) {
                 /* Boost up -- we can execute copied instructions directly */
                 reset_current_kprobe();
diff --git a/arch/x86/kernel/microcode_intel.c b/arch/x86/kernel/microcode_intel.c
index ebd193e476ca..85a343e28937 100644
--- a/arch/x86/kernel/microcode_intel.c
+++ b/arch/x86/kernel/microcode_intel.c
@@ -328,7 +328,7 @@ static int apply_microcode(int cpu)
                        cpu_num, mc_intel->hdr.rev);
                 return -1;
         }
-        pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x \n",
+        pr_info("CPU%d updated to revision 0x%x, date = %04x-%02x-%02x\n",
                 cpu_num, val[1],
                 mc_intel->hdr.date & 0xffff,
                 mc_intel->hdr.date >> 24,
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index c9b3522b6b46..02d678065d7d 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -92,6 +92,13 @@ void exit_thread(void)
         }
 }
 
+void show_regs(struct pt_regs *regs)
+{
+        show_registers(regs);
+        show_trace(NULL, regs, (unsigned long *)kernel_stack_pointer(regs),
+                   regs->bp);
+}
+
 void show_regs_common(void)
 {
         const char *board, *product;
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 37ad1e046aae..f6c62667e30c 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -174,12 +174,6 @@ void __show_regs(struct pt_regs *regs, int all)
                         d6, d7);
 }
 
-void show_regs(struct pt_regs *regs)
-{
-        show_registers(regs);
-        show_trace(NULL, regs, &regs->sp, regs->bp);
-}
-
 void release_thread(struct task_struct *dead_task)
 {
         BUG_ON(dead_task->mm);
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 41a26a82470a..dc9690b4c4cc 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -211,12 +211,6 @@ void __show_regs(struct pt_regs *regs, int all)
         printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", d3, d6, d7);
 }
 
-void show_regs(struct pt_regs *regs)
-{
-        show_registers(regs);
-        show_trace(NULL, regs, (void *)(regs + 1), regs->bp);
-}
-
 void release_thread(struct task_struct *dead_task)
 {
         if (dead_task->mm) {
@@ -527,6 +521,7 @@ void set_personality_ia32(void)
 
         /* Make sure to be in 32bit mode */
         set_thread_flag(TIF_IA32);
+        current->personality |= force_personality32;
 
         /* Prepare the first "return" to user space */
         current_thread_info()->status |= TS_COMPAT;
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 017d937639fe..2d96aab82a48 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -48,6 +48,7 @@ enum x86_regset {
         REGSET_FP,
         REGSET_XFP,
         REGSET_IOPERM64 = REGSET_XFP,
+        REGSET_XSTATE,
         REGSET_TLS,
         REGSET_IOPERM32,
 };
@@ -140,30 +141,6 @@ static const int arg_offs_table[] = {
 #endif
 };
 
-/**
- * regs_get_argument_nth() - get Nth argument at function call
- * @regs:       pt_regs which contains registers at function entry.
- * @n:          argument number.
- *
- * regs_get_argument_nth() returns @n th argument of a function call.
- * Since usually the kernel stack will be changed right after function entry,
- * you must use this at function entry. If the @n th entry is NOT in the
- * kernel stack or pt_regs, this returns 0.
- */
-unsigned long regs_get_argument_nth(struct pt_regs *regs, unsigned int n)
-{
-        if (n < ARRAY_SIZE(arg_offs_table))
-                return *(unsigned long *)((char *)regs + arg_offs_table[n]);
-        else {
-                /*
-                 * The typical case: arg n is on the stack.
-                 * (Note: stack[0] = return address, so skip it)
-                 */
-                n -= ARRAY_SIZE(arg_offs_table);
-                return regs_get_kernel_stack_nth(regs, 1 + n);
-        }
-}
-
 /*
  * does not yet catch signals sent when the child dies.
  * in exit.c or in signal.c.
@@ -702,7 +679,7 @@ static unsigned long ptrace_get_debugreg(struct task_struct *tsk, int n)
         } else if (n == 6) {
                 val = thread->debugreg6;
          } else if (n == 7) {
-                val = ptrace_get_dr7(thread->ptrace_bps);
+                val = thread->ptrace_dr7;
         }
         return val;
 }
@@ -778,8 +755,11 @@ int ptrace_set_debugreg(struct task_struct *tsk, int n, unsigned long val)
                         return rc;
         }
         /* All that's left is DR7 */
-        if (n == 7)
+        if (n == 7) {
                 rc = ptrace_write_dr7(tsk, val);
+                if (!rc)
+                        thread->ptrace_dr7 = val;
+        }
 
 ret_path:
         return rc;
@@ -1584,7 +1564,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
 
 #ifdef CONFIG_X86_64
 
-static const struct user_regset x86_64_regsets[] = {
+static struct user_regset x86_64_regsets[] __read_mostly = {
         [REGSET_GENERAL] = {
                 .core_note_type = NT_PRSTATUS,
                 .n = sizeof(struct user_regs_struct) / sizeof(long),
@@ -1597,6 +1577,12 @@ static const struct user_regset x86_64_regsets[] = {
                 .size = sizeof(long), .align = sizeof(long),
                 .active = xfpregs_active, .get = xfpregs_get, .set = xfpregs_set
         },
+        [REGSET_XSTATE] = {
+                .core_note_type = NT_X86_XSTATE,
+                .size = sizeof(u64), .align = sizeof(u64),
+                .active = xstateregs_active, .get = xstateregs_get,
+                .set = xstateregs_set
+        },
         [REGSET_IOPERM64] = {
                 .core_note_type = NT_386_IOPERM,
                 .n = IO_BITMAP_LONGS,
@@ -1622,7 +1608,7 @@ static const struct user_regset_view user_x86_64_view = {
 #endif  /* CONFIG_X86_64 */
 
 #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
-static const struct user_regset x86_32_regsets[] = {
+static struct user_regset x86_32_regsets[] __read_mostly = {
         [REGSET_GENERAL] = {
                 .core_note_type = NT_PRSTATUS,
                 .n = sizeof(struct user_regs_struct32) / sizeof(u32),
@@ -1641,6 +1627,12 @@ static const struct user_regset x86_32_regsets[] = {
                 .size = sizeof(u32), .align = sizeof(u32),
                 .active = xfpregs_active, .get = xfpregs_get, .set = xfpregs_set
         },
+        [REGSET_XSTATE] = {
+                .core_note_type = NT_X86_XSTATE,
+                .size = sizeof(u64), .align = sizeof(u64),
+                .active = xstateregs_active, .get = xstateregs_get,
+                .set = xstateregs_set
+        },
         [REGSET_TLS] = {
                 .core_note_type = NT_386_TLS,
                 .n = GDT_ENTRY_TLS_ENTRIES, .bias = GDT_ENTRY_TLS_MIN,
@@ -1663,6 +1655,23 @@ static const struct user_regset_view user_x86_32_view = {
 };
 #endif
 
+/*
+ * This represents bytes 464..511 in the memory layout exported through
+ * the REGSET_XSTATE interface.
+ */
+u64 xstate_fx_sw_bytes[USER_XSTATE_FX_SW_WORDS];
+
+void update_regset_xstate_info(unsigned int size, u64 xstate_mask)
+{
+#ifdef CONFIG_X86_64
+        x86_64_regsets[REGSET_XSTATE].n = size / sizeof(u64);
+#endif
+#if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
+        x86_32_regsets[REGSET_XSTATE].n = size / sizeof(u64);
+#endif
+        xstate_fx_sw_bytes[USER_XSTATE_XCR0_WORD] = xstate_mask;
+}
+
 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
 {
 #ifdef CONFIG_IA32_EMULATION
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 5d9e40c58628..cb42109a55b4 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -121,7 +121,9 @@
 unsigned long max_low_pfn_mapped;
 unsigned long max_pfn_mapped;
 
+#ifdef CONFIG_DMI
 RESERVE_BRK(dmi_alloc, 65536);
+#endif
 
 unsigned int boot_cpu_id __read_mostly;
 
@@ -667,6 +669,23 @@ static struct dmi_system_id __initdata bad_bios_dmi_table[] = {
         {}
 };
 
+static void __init trim_bios_range(void)
+{
+        /*
+         * A special case is the first 4Kb of memory;
+         * This is a BIOS owned area, not kernel ram, but generally
+         * not listed as such in the E820 table.
+         */
+        e820_update_range(0, PAGE_SIZE, E820_RAM, E820_RESERVED);
+        /*
+         * special case: Some BIOSen report the PC BIOS
+         * area (640->1Mb) as ram even though it is not.
+         * take them out.
+         */
+        e820_remove_range(BIOS_BEGIN, BIOS_END - BIOS_BEGIN, E820_RAM, 1);
+        sanitize_e820_map(e820.map, ARRAY_SIZE(e820.map), &e820.nr_map);
+}
+
 /*
  * Determine if we were loaded by an EFI loader.  If so, then we have also been
  * passed the efi memmap, systab, etc., so we should use these data structures
@@ -830,7 +849,7 @@ void __init setup_arch(char **cmdline_p)
         insert_resource(&iomem_resource, &data_resource);
         insert_resource(&iomem_resource, &bss_resource);
 
-
+        trim_bios_range();
 #ifdef CONFIG_X86_32
         if (ppro_with_ram_bug()) {
                 e820_update_range(0x70000000ULL, 0x40000ULL, E820_RAM,
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index b4e870cbdc60..9b4401115ea1 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -320,6 +320,7 @@ notrace static void __cpuinit start_secondary(void *unused)
         unlock_vector_lock();
         ipi_call_unlock();
         per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
+        x86_platform.nmi_init();
 
         /* enable local interrupts */
         local_irq_enable();
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 33399176512a..1168e4454188 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -534,6 +534,9 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
 
         get_debugreg(dr6, 6);
 
+        /* Filter out all the reserved bits which are preset to 1 */
+        dr6 &= ~DR6_RESERVED;
+
         /* Catch kmemcheck conditions first of all! */
         if ((dr6 & DR_STEP) && kmemcheck_trap(regs))
                 return;
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 597683aa5ba0..208a857c679f 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -740,7 +740,7 @@ static cycle_t __vsyscall_fn vread_tsc(void)
 }
 #endif
 
-static void resume_tsc(void)
+static void resume_tsc(struct clocksource *cs)
 {
         clocksource_tsc.cycle_last = 0;
 }
@@ -806,7 +806,7 @@ static void __init check_system_tsc_reliable(void)
         unsigned long res_low, res_high;
 
         rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
-        /* Geode_LX - the OLPC CPU has a possibly a very reliable TSC */
+        /* Geode_LX - the OLPC CPU has a very reliable TSC */
         if (res_low & RTSC_SUSP)
                 tsc_clocksource_reliable = 1;
 #endif
diff --git a/arch/x86/kernel/uv_sysfs.c b/arch/x86/kernel/uv_sysfs.c
index 36afb98675a4..309c70fb7759 100644
--- a/arch/x86/kernel/uv_sysfs.c
+++ b/arch/x86/kernel/uv_sysfs.c
@@ -54,19 +54,19 @@ static int __init sgi_uv_sysfs_init(void)
         if (!sgi_uv_kobj)
                 sgi_uv_kobj = kobject_create_and_add("sgi_uv", firmware_kobj);
         if (!sgi_uv_kobj) {
-                printk(KERN_WARNING "kobject_create_and_add sgi_uv failed \n");
+                printk(KERN_WARNING "kobject_create_and_add sgi_uv failed\n");
                 return -EINVAL;
         }
 
         ret = sysfs_create_file(sgi_uv_kobj, &partition_id_attr.attr);
         if (ret) {
-                printk(KERN_WARNING "sysfs_create_file partition_id failed \n");
+                printk(KERN_WARNING "sysfs_create_file partition_id failed\n");
                 return ret;
         }
 
         ret = sysfs_create_file(sgi_uv_kobj, &coherence_id_attr.attr);
         if (ret) {
-                printk(KERN_WARNING "sysfs_create_file coherence_id failed \n");
+                printk(KERN_WARNING "sysfs_create_file coherence_id failed\n");
                 return ret;
         }
 
diff --git a/arch/x86/kernel/x8664_ksyms_64.c b/arch/x86/kernel/x8664_ksyms_64.c
index 619f7f88b8cc..693920b22496 100644
--- a/arch/x86/kernel/x8664_ksyms_64.c
+++ b/arch/x86/kernel/x8664_ksyms_64.c
@@ -26,7 +26,8 @@ EXPORT_SYMBOL(__put_user_2);
 EXPORT_SYMBOL(__put_user_4);
 EXPORT_SYMBOL(__put_user_8);
 
-EXPORT_SYMBOL(copy_user_generic);
+EXPORT_SYMBOL(copy_user_generic_string);
+EXPORT_SYMBOL(copy_user_generic_unrolled);
 EXPORT_SYMBOL(__copy_user_nocache);
 EXPORT_SYMBOL(_copy_from_user);
 EXPORT_SYMBOL(_copy_to_user);
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index ccd179dec36e..ee5746c94628 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -76,10 +76,13 @@ struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
         .setup_percpu_clockev           = setup_secondary_APIC_clock,
 };
 
+static void default_nmi_init(void) { };
+
 struct x86_platform_ops x86_platform = {
         .calibrate_tsc                  = native_calibrate_tsc,
         .get_wallclock                  = mach_get_cmos_time,
         .set_wallclock                  = mach_set_rtc_mmss,
         .iommu_shutdown                 = iommu_shutdown_noop,
         .is_untracked_pat_range         = is_ISA_range,
+        .nmi_init                       = default_nmi_init
 };
diff --git a/arch/x86/kernel/xsave.c b/arch/x86/kernel/xsave.c
index c5ee17e8c6d9..782c3a362ec6 100644
--- a/arch/x86/kernel/xsave.c
+++ b/arch/x86/kernel/xsave.c
@@ -337,6 +337,7 @@ void __ref xsave_cntxt_init(void)
         cpuid_count(0xd, 0, &eax, &ebx, &ecx, &edx);
         xstate_size = ebx;
 
+        update_regset_xstate_info(xstate_size, pcntxt_mask);
         prepare_fx_sw_frame();
 
         setup_xstate_init();
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index cffd754f3039..419386c24b82 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -14,7 +14,7 @@ $(obj)/inat.o: $(obj)/inat-tables.c
 
 clean-files := inat-tables.c
 
-obj-$(CONFIG_SMP) += msr-smp.o
+obj-$(CONFIG_SMP) += msr-smp.o cache-smp.o
 
 lib-y := delay.o
 lib-y += thunk_$(BITS).o
@@ -34,9 +34,10 @@ ifneq ($(CONFIG_X86_CMPXCHG64),y)
 endif
         lib-$(CONFIG_X86_USE_3DNOW) += mmx_32.o
 else
-        obj-y += io_64.o iomap_copy_64.o
+        obj-y += iomap_copy_64.o
         lib-y += csum-partial_64.o csum-copy_64.o csum-wrappers_64.o
         lib-y += thunk_64.o clear_page_64.o copy_page_64.o
         lib-y += memmove_64.o memset_64.o
         lib-y += copy_user_64.o rwlock_64.o copy_user_nocache_64.o
+        lib-$(CONFIG_RWSEM_XCHGADD_ALGORITHM) += rwsem_64.o
 endif
diff --git a/arch/x86/lib/cache-smp.c b/arch/x86/lib/cache-smp.c
new file mode 100644
index 000000000000..a3c668875038
--- /dev/null
+++ b/arch/x86/lib/cache-smp.c
@@ -0,0 +1,19 @@
+#include <linux/smp.h>
+#include <linux/module.h>
+
+static void __wbinvd(void *dummy)
+{
+        wbinvd();
+}
+
+void wbinvd_on_cpu(int cpu)
+{
+        smp_call_function_single(cpu, __wbinvd, NULL, 1);
+}
+EXPORT_SYMBOL(wbinvd_on_cpu);
+
+int wbinvd_on_all_cpus(void)
+{
+        return on_each_cpu(__wbinvd, NULL, 1);
+}
+EXPORT_SYMBOL(wbinvd_on_all_cpus);
diff --git a/arch/x86/lib/copy_user_64.S b/arch/x86/lib/copy_user_64.S
index cf889d4e076a..71100c98e337 100644
--- a/arch/x86/lib/copy_user_64.S
+++ b/arch/x86/lib/copy_user_64.S
@@ -90,12 +90,6 @@ ENTRY(_copy_from_user)
         CFI_ENDPROC
 ENDPROC(_copy_from_user)
 
-ENTRY(copy_user_generic)
-        CFI_STARTPROC
-        ALTERNATIVE_JUMP X86_FEATURE_REP_GOOD,copy_user_generic_unrolled,copy_user_generic_string
-        CFI_ENDPROC
-ENDPROC(copy_user_generic)
-
         .section .fixup,"ax"
         /* must zero dest */
 ENTRY(bad_from_user)
diff --git a/arch/x86/lib/io_64.c b/arch/x86/lib/io_64.c
deleted file mode 100644
index 3f1eb59b5f08..000000000000
--- a/arch/x86/lib/io_64.c
+++ /dev/null
@@ -1,25 +0,0 @@
-#include <linux/string.h>
-#include <linux/module.h>
-#include <asm/io.h>
-
-void __memcpy_toio(unsigned long dst, const void *src, unsigned len)
-{
-        __inline_memcpy((void *)dst, src, len);
-}
-EXPORT_SYMBOL(__memcpy_toio);
-
-void __memcpy_fromio(void *dst, unsigned long src, unsigned len)
-{
-        __inline_memcpy(dst, (const void *)src, len);
-}
-EXPORT_SYMBOL(__memcpy_fromio);
-
-void memset_io(volatile void __iomem *a, int b, size_t c)
-{
-        /*
-         * TODO: memset can mangle the IO patterns quite a bit.
-         * perhaps it would be better to use a dumb one:
-         */
-        memset((void *)a, b, c);
-}
-EXPORT_SYMBOL(memset_io);
diff --git a/arch/x86/lib/memcpy_64.S b/arch/x86/lib/memcpy_64.S
index ad5441ed1b57..f82e884928af 100644
--- a/arch/x86/lib/memcpy_64.S
+++ b/arch/x86/lib/memcpy_64.S
@@ -20,12 +20,11 @@
 /*
  * memcpy_c() - fast string ops (REP MOVSQ) based variant.
  *
- * Calls to this get patched into the kernel image via the
+ * This gets patched over the unrolled variant (below) via the
  * alternative instructions framework:
  */
-        ALIGN
-memcpy_c:
-        CFI_STARTPROC
+        .section .altinstr_replacement, "ax", @progbits
+.Lmemcpy_c:
         movq %rdi, %rax
 
         movl %edx, %ecx
@@ -35,8 +34,8 @@ memcpy_c:
         movl %edx, %ecx
         rep movsb
         ret
-        CFI_ENDPROC
-ENDPROC(memcpy_c)
+.Lmemcpy_e:
+        .previous
 
 ENTRY(__memcpy)
 ENTRY(memcpy)
@@ -128,16 +127,10 @@ ENDPROC(__memcpy)
          * It is also a lot simpler. Use this when possible:
          */
 
-        .section .altinstr_replacement, "ax"
-1:      .byte 0xeb                              /* jmp <disp8> */
-        .byte (memcpy_c - memcpy) - (2f - 1b)   /* offset */
-2:
-        .previous
-
         .section .altinstructions, "a"
         .align 8
         .quad memcpy
-        .quad 1b
+        .quad .Lmemcpy_c
         .byte X86_FEATURE_REP_GOOD
 
         /*
@@ -145,6 +138,6 @@ ENDPROC(__memcpy)
          * so it is silly to overwrite itself with nops - reboot is the
          * only outcome...
          */
-        .byte 2b - 1b
-        .byte 2b - 1b
+        .byte .Lmemcpy_e - .Lmemcpy_c
+        .byte .Lmemcpy_e - .Lmemcpy_c
         .previous
diff --git a/arch/x86/lib/memset_64.S b/arch/x86/lib/memset_64.S
index 2c5948116bd2..e88d3b81644a 100644
--- a/arch/x86/lib/memset_64.S
+++ b/arch/x86/lib/memset_64.S
@@ -12,9 +12,8 @@
  * 
  * rax   original destination
  */     
-        ALIGN
-memset_c:
-        CFI_STARTPROC
+        .section .altinstr_replacement, "ax", @progbits
+.Lmemset_c:
         movq %rdi,%r9
         movl %edx,%r8d
         andl $7,%r8d
@@ -29,8 +28,8 @@ memset_c:
         rep stosb
         movq %r9,%rax
         ret
-        CFI_ENDPROC
-ENDPROC(memset_c)
+.Lmemset_e:
+        .previous
 
 ENTRY(memset)
 ENTRY(__memset)
@@ -118,16 +117,11 @@ ENDPROC(__memset)
 
 #include <asm/cpufeature.h>
 
-        .section .altinstr_replacement,"ax"
-1:      .byte 0xeb                              /* jmp <disp8> */
-        .byte (memset_c - memset) - (2f - 1b)   /* offset */
-2:
-        .previous
         .section .altinstructions,"a"
         .align 8
         .quad memset
-        .quad 1b
+        .quad .Lmemset_c
         .byte X86_FEATURE_REP_GOOD
         .byte .Lfinal - memset
-        .byte 2b - 1b
+        .byte .Lmemset_e - .Lmemset_c
         .previous
diff --git a/arch/x86/lib/rwsem_64.S b/arch/x86/lib/rwsem_64.S
new file mode 100644
index 000000000000..15acecf0d7aa
--- /dev/null
+++ b/arch/x86/lib/rwsem_64.S
@@ -0,0 +1,81 @@
+/*
+ * x86-64 rwsem wrappers
+ *
+ * This interfaces the inline asm code to the slow-path
+ * C routines. We need to save the call-clobbered regs
+ * that the asm does not mark as clobbered, and move the
+ * argument from %rax to %rdi.
+ *
+ * NOTE! We don't need to save %rax, because the functions
+ * will always return the semaphore pointer in %rax (which
+ * is also the input argument to these helpers)
+ *
+ * The following can clobber %rdx because the asm clobbers it:
+ *   call_rwsem_down_write_failed
+ *   call_rwsem_wake
+ * but %rdi, %rsi, %rcx, %r8-r11 always need saving.
+ */
+
+#include <linux/linkage.h>
+#include <asm/rwlock.h>
+#include <asm/alternative-asm.h>
+#include <asm/frame.h>
+#include <asm/dwarf2.h>
+
+#define save_common_regs \
+        pushq %rdi; \
+        pushq %rsi; \
+        pushq %rcx; \
+        pushq %r8; \
+        pushq %r9; \
+        pushq %r10; \
+        pushq %r11
+
+#define restore_common_regs \
+        popq %r11; \
+        popq %r10; \
+        popq %r9; \
+        popq %r8; \
+        popq %rcx; \
+        popq %rsi; \
+        popq %rdi
+
+/* Fix up special calling conventions */
+ENTRY(call_rwsem_down_read_failed)
+        save_common_regs
+        pushq %rdx
+        movq %rax,%rdi
+        call rwsem_down_read_failed
+        popq %rdx
+        restore_common_regs
+        ret
+        ENDPROC(call_rwsem_down_read_failed)
+
+ENTRY(call_rwsem_down_write_failed)
+        save_common_regs
+        movq %rax,%rdi
+        call rwsem_down_write_failed
+        restore_common_regs
+        ret
+        ENDPROC(call_rwsem_down_write_failed)
+
+ENTRY(call_rwsem_wake)
+        decw %dx    /* do nothing if still outstanding active readers */
+        jnz 1f
+        save_common_regs
+        movq %rax,%rdi
+        call rwsem_wake
+        restore_common_regs
+1:      ret
+        ENDPROC(call_rwsem_wake)
+
+/* Fix up special calling conventions */
+ENTRY(call_rwsem_downgrade_wake)
+        save_common_regs
+        pushq %rdx
+        movq %rax,%rdi
+        call rwsem_downgrade_wake
+        popq %rdx
+        restore_common_regs
+        ret
+        ENDPROC(call_rwsem_downgrade_wake)
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index d406c5239019..e71c5cbc8f35 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -266,16 +266,9 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
         if (!after_bootmem)
                 find_early_table_space(end, use_pse, use_gbpages);
 
-#ifdef CONFIG_X86_32
-        for (i = 0; i < nr_range; i++)
-                kernel_physical_mapping_init(mr[i].start, mr[i].end,
-                                             mr[i].page_size_mask);
-        ret = end;
-#else /* CONFIG_X86_64 */
         for (i = 0; i < nr_range; i++)
                 ret = kernel_physical_mapping_init(mr[i].start, mr[i].end,
                                                    mr[i].page_size_mask);
-#endif
 
 #ifdef CONFIG_X86_32
         early_ioremap_page_table_range_init();
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 9a0c258a86be..2226f2c70ea3 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -241,6 +241,7 @@ kernel_physical_mapping_init(unsigned long start,
                              unsigned long page_size_mask)
 {
         int use_pse = page_size_mask == (1<<PG_LEVEL_2M);
+        unsigned long last_map_addr = end;
         unsigned long start_pfn, end_pfn;
         pgd_t *pgd_base = swapper_pg_dir;
         int pgd_idx, pmd_idx, pte_ofs;
@@ -341,9 +342,10 @@ repeat:
                                         prot = PAGE_KERNEL_EXEC;
 
                                 pages_4k++;
-                                if (mapping_iter == 1)
+                                if (mapping_iter == 1) {
                                         set_pte(pte, pfn_pte(pfn, init_prot));
-                                else
+                                        last_map_addr = (pfn << PAGE_SHIFT) + PAGE_SIZE;
+                                } else
                                         set_pte(pte, pfn_pte(pfn, prot));
                         }
                 }
@@ -368,7 +370,7 @@ repeat:
                 mapping_iter = 2;
                 goto repeat;
         }
-        return 0;
+        return last_map_addr;
 }
 
 pte_t *kmap_pte;
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index c246d259822d..5eb1ba74a3a9 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -24,43 +24,6 @@
 
 #include "physaddr.h"
 
-int page_is_ram(unsigned long pagenr)
-{
-        resource_size_t addr, end;
-        int i;
-
-        /*
-         * A special case is the first 4Kb of memory;
-         * This is a BIOS owned area, not kernel ram, but generally
-         * not listed as such in the E820 table.
-         */
-        if (pagenr == 0)
-                return 0;
-
-        /*
-         * Second special case: Some BIOSen report the PC BIOS
-         * area (640->1Mb) as ram even though it is not.
-         */
-        if (pagenr >= (BIOS_BEGIN >> PAGE_SHIFT) &&
-                    pagenr < (BIOS_END >> PAGE_SHIFT))
-                return 0;
-
-        for (i = 0; i < e820.nr_map; i++) {
-                /*
-                 * Not usable memory:
-                 */
-                if (e820.map[i].type != E820_RAM)
-                        continue;
-                addr = (e820.map[i].addr + PAGE_SIZE-1) >> PAGE_SHIFT;
-                end = (e820.map[i].addr + e820.map[i].size) >> PAGE_SHIFT;
-
-
-                if ((pagenr >= addr) && (pagenr < end))
-                        return 1;
-        }
-        return 0;
-}
-
 /*
  * Fix up the linear direct mapping of the kernel to avoid cache attribute
  * conflicts.
@@ -422,6 +385,10 @@ void __init early_ioremap_init(void)
          * The boot-ioremap range spans multiple pmds, for which
          * we are not prepared:
          */
+#define __FIXADDR_TOP (-PAGE_SIZE)
+        BUILD_BUG_ON((__fix_to_virt(FIX_BTMAP_BEGIN) >> PMD_SHIFT)
+                     != (__fix_to_virt(FIX_BTMAP_END) >> PMD_SHIFT));
+#undef __FIXADDR_TOP
         if (pmd != early_ioremap_pmd(fix_to_virt(FIX_BTMAP_END))) {
                 WARN_ON(1);
                 printk(KERN_WARNING "pmd %p != %p\n",
diff --git a/arch/x86/mm/kmemcheck/kmemcheck.c b/arch/x86/mm/kmemcheck/kmemcheck.c
index 8cc183344140..b3b531a4f8e5 100644
--- a/arch/x86/mm/kmemcheck/kmemcheck.c
+++ b/arch/x86/mm/kmemcheck/kmemcheck.c
@@ -337,7 +337,7 @@ bool kmemcheck_is_obj_initialized(unsigned long addr, size_t size)
         if (!shadow)
                 return true;
 
-        status = kmemcheck_shadow_test(shadow, size);
+        status = kmemcheck_shadow_test_all(shadow, size);
 
         return status == KMEMCHECK_SHADOW_INITIALIZED;
 }
diff --git a/arch/x86/mm/kmemcheck/shadow.c b/arch/x86/mm/kmemcheck/shadow.c
index 3f66b82076a3..aec124214d97 100644
--- a/arch/x86/mm/kmemcheck/shadow.c
+++ b/arch/x86/mm/kmemcheck/shadow.c
@@ -125,12 +125,12 @@ void kmemcheck_mark_initialized_pages(struct page *p, unsigned int n)
 
 enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size)
 {
+#ifdef CONFIG_KMEMCHECK_PARTIAL_OK
         uint8_t *x;
         unsigned int i;
 
         x = shadow;
 
-#ifdef CONFIG_KMEMCHECK_PARTIAL_OK
         /*
          * Make sure _some_ bytes are initialized. Gcc frequently generates
          * code to access neighboring bytes.
@@ -139,13 +139,25 @@ enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size)
                 if (x[i] == KMEMCHECK_SHADOW_INITIALIZED)
                         return x[i];
         }
+
+        return x[0];
 #else
+        return kmemcheck_shadow_test_all(shadow, size);
+#endif
+}
+
+enum kmemcheck_shadow kmemcheck_shadow_test_all(void *shadow, unsigned int size)
+{
+        uint8_t *x;
+        unsigned int i;
+
+        x = shadow;
+
         /* All bytes must be initialized. */
         for (i = 0; i < size; ++i) {
                 if (x[i] != KMEMCHECK_SHADOW_INITIALIZED)
                         return x[i];
         }
-#endif
 
         return x[0];
 }
diff --git a/arch/x86/mm/kmemcheck/shadow.h b/arch/x86/mm/kmemcheck/shadow.h
index af46d9ab9d86..ff0b2f70fbcb 100644
--- a/arch/x86/mm/kmemcheck/shadow.h
+++ b/arch/x86/mm/kmemcheck/shadow.h
@@ -11,6 +11,8 @@ enum kmemcheck_shadow {
 void *kmemcheck_shadow_lookup(unsigned long address);
 
 enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size);
+enum kmemcheck_shadow kmemcheck_shadow_test_all(void *shadow,
+                                                unsigned int size);
 void kmemcheck_shadow_set(void *shadow, unsigned int size);
 
 #endif
diff --git a/arch/x86/mm/mmap.c b/arch/x86/mm/mmap.c
index c8191defc38a..1dab5194fd9d 100644
--- a/arch/x86/mm/mmap.c
+++ b/arch/x86/mm/mmap.c
@@ -71,7 +71,7 @@ static int mmap_is_legacy(void)
         if (current->personality & ADDR_COMPAT_LAYOUT)
                 return 1;
 
-        if (current->signal->rlim[RLIMIT_STACK].rlim_cur == RLIM_INFINITY)
+        if (rlimit(RLIMIT_STACK) == RLIM_INFINITY)
                 return 1;
 
         return sysctl_legacy_va_layout;
@@ -96,7 +96,7 @@ static unsigned long mmap_rnd(void)
 
 static unsigned long mmap_base(void)
 {
-        unsigned long gap = current->signal->rlim[RLIMIT_STACK].rlim_cur;
+        unsigned long gap = rlimit(RLIMIT_STACK);
 
         if (gap < MIN_GAP)
                 gap = MIN_GAP;
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index 83bbc70d11bb..3307ea8bd43a 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -427,7 +427,7 @@ static int __init split_nodes_interleave(u64 addr, u64 max_addr,
          * Calculate the number of big nodes that can be allocated as a result
          * of consolidating the remainder.
          */
-        big = ((size & ~FAKE_NODE_MIN_HASH_MASK) & nr_nodes) /
+        big = ((size & ~FAKE_NODE_MIN_HASH_MASK) * nr_nodes) /
                 FAKE_NODE_MIN_SIZE;
 
         size &= FAKE_NODE_MIN_HASH_MASK;
@@ -502,77 +502,99 @@ static int __init split_nodes_interleave(u64 addr, u64 max_addr,
 }
 
 /*
- * Splits num_nodes nodes up equally starting at node_start.  The return value
- * is the number of nodes split up and addr is adjusted to be at the end of the
- * last node allocated.
+ * Returns the end address of a node so that there is at least `size' amount of
+ * non-reserved memory or `max_addr' is reached.
  */
-static int __init split_nodes_equally(u64 *addr, u64 max_addr, int node_start,
-                                      int num_nodes)
+static u64 __init find_end_of_node(u64 start, u64 max_addr, u64 size)
 {
-        unsigned int big;
-        u64 size;
-        int i;
-
-        if (num_nodes <= 0)
-                return -1;
-        if (num_nodes > MAX_NUMNODES)
-                num_nodes = MAX_NUMNODES;
-        size = (max_addr - *addr - e820_hole_size(*addr, max_addr)) /
-               num_nodes;
-        /*
-         * Calculate the number of big nodes that can be allocated as a result
-         * of consolidating the leftovers.
-         */
-        big = ((size & ~FAKE_NODE_MIN_HASH_MASK) * num_nodes) /
-              FAKE_NODE_MIN_SIZE;
-
-        /* Round down to nearest FAKE_NODE_MIN_SIZE. */
-        size &= FAKE_NODE_MIN_HASH_MASK;
-        if (!size) {
-                printk(KERN_ERR "Not enough memory for each node.  "
-                       "NUMA emulation disabled.\n");
-                return -1;
-        }
-
-        for (i = node_start; i < num_nodes + node_start; i++) {
-                u64 end = *addr + size;
+        u64 end = start + size;
 
-                if (i < big)
-                        end += FAKE_NODE_MIN_SIZE;
-                /*
-                 * The final node can have the remaining system RAM.  Other
-                 * nodes receive roughly the same amount of available pages.
-                 */
-                if (i == num_nodes + node_start - 1)
+        while (end - start - e820_hole_size(start, end) < size) {
+                end += FAKE_NODE_MIN_SIZE;
+                if (end > max_addr) {
                         end = max_addr;
-                else
-                        while (end - *addr - e820_hole_size(*addr, end) <
-                               size) {
-                                end += FAKE_NODE_MIN_SIZE;
-                                if (end > max_addr) {
-                                        end = max_addr;
-                                        break;
-                                }
-                        }
-                if (setup_node_range(i, addr, end - *addr, max_addr) < 0)
                         break;
+                }
         }
-        return i - node_start + 1;
+        return end;
 }
 
 /*
- * Splits the remaining system RAM into chunks of size.  The remaining memory is
- * always assigned to a final node and can be asymmetric.  Returns the number of
- * nodes split.
+ * Sets up fake nodes of `size' interleaved over physical nodes ranging from
+ * `addr' to `max_addr'.  The return value is the number of nodes allocated.
  */
-static int __init split_nodes_by_size(u64 *addr, u64 max_addr, int node_start,
-                                      u64 size)
+static int __init split_nodes_size_interleave(u64 addr, u64 max_addr, u64 size)
 {
-        int i = node_start;
-        size = (size << 20) & FAKE_NODE_MIN_HASH_MASK;
-        while (!setup_node_range(i++, addr, size, max_addr))
-                ;
-        return i - node_start;
+        nodemask_t physnode_mask = NODE_MASK_NONE;
+        u64 min_size;
+        int ret = 0;
+        int i;
+
+        if (!size)
+                return -1;
+        /*
+         * The limit on emulated nodes is MAX_NUMNODES, so the size per node is
+         * increased accordingly if the requested size is too small.  This
+         * creates a uniform distribution of node sizes across the entire
+         * machine (but not necessarily over physical nodes).
+         */
+        min_size = (max_addr - addr - e820_hole_size(addr, max_addr)) /
+                                                MAX_NUMNODES;
+        min_size = max(min_size, FAKE_NODE_MIN_SIZE);
+        if ((min_size & FAKE_NODE_MIN_HASH_MASK) < min_size)
+                min_size = (min_size + FAKE_NODE_MIN_SIZE) &
+                                                FAKE_NODE_MIN_HASH_MASK;
+        if (size < min_size) {
+                pr_err("Fake node size %LuMB too small, increasing to %LuMB\n",
+                        size >> 20, min_size >> 20);
+                size = min_size;
+        }
+        size &= FAKE_NODE_MIN_HASH_MASK;
+
+        for (i = 0; i < MAX_NUMNODES; i++)
+                if (physnodes[i].start != physnodes[i].end)
+                        node_set(i, physnode_mask);
+        /*
+         * Fill physical nodes with fake nodes of size until there is no memory
+         * left on any of them.
+         */
+        while (nodes_weight(physnode_mask)) {
+                for_each_node_mask(i, physnode_mask) {
+                        u64 dma32_end = MAX_DMA32_PFN << PAGE_SHIFT;
+                        u64 end;
+
+                        end = find_end_of_node(physnodes[i].start,
+                                                physnodes[i].end, size);
+                        /*
+                         * If there won't be at least FAKE_NODE_MIN_SIZE of
+                         * non-reserved memory in ZONE_DMA32 for the next node,
+                         * this one must extend to the boundary.
+                         */
+                        if (end < dma32_end && dma32_end - end -
+                            e820_hole_size(end, dma32_end) < FAKE_NODE_MIN_SIZE)
+                                end = dma32_end;
+
+                        /*
+                         * If there won't be enough non-reserved memory for the
+                         * next node, this one must extend to the end of the
+                         * physical node.
+                         */
+                        if (physnodes[i].end - end -
+                            e820_hole_size(end, physnodes[i].end) < size)
+                                end = physnodes[i].end;
+
+                        /*
+                         * Setup the fake node that will be allocated as bootmem
+                         * later.  If setup_node_range() returns non-zero, there
+                         * is no more memory available on this physical node.
+                         */
+                        if (setup_node_range(ret++, &physnodes[i].start,
+                                                end - physnodes[i].start,
+                                                physnodes[i].end) < 0)
+                                node_clear(i, physnode_mask);
+                }
+        }
+        return ret;
 }
 
 /*
@@ -582,87 +604,32 @@ static int __init split_nodes_by_size(u64 *addr, u64 max_addr, int node_start,
 static int __init numa_emulation(unsigned long start_pfn,
                         unsigned long last_pfn, int acpi, int k8)
 {
-        u64 size, addr = start_pfn << PAGE_SHIFT;
+        u64 addr = start_pfn << PAGE_SHIFT;
         u64 max_addr = last_pfn << PAGE_SHIFT;
-        int num_nodes = 0, num = 0, coeff_flag, coeff = -1, i;
         int num_phys_nodes;
+        int num_nodes;
+        int i;
 
         num_phys_nodes = setup_physnodes(addr, max_addr, acpi, k8);
         /*
-         * If the numa=fake command-line is just a single number N, split the
-         * system RAM into N fake nodes.
+         * If the numa=fake command-line contains a 'M' or 'G', it represents
+         * the fixed node size.  Otherwise, if it is just a single number N,
+         * split the system RAM into N fake nodes.
          */
-        if (!strchr(cmdline, '*') && !strchr(cmdline, ',')) {
-                long n = simple_strtol(cmdline, NULL, 0);
-
-                num_nodes = split_nodes_interleave(addr, max_addr,
-                                                        num_phys_nodes, n);
-                if (num_nodes < 0)
-                        return num_nodes;
-                goto out;
-        }
+        if (strchr(cmdline, 'M') || strchr(cmdline, 'G')) {
+                u64 size;
 
-        /* Parse the command line. */
-        for (coeff_flag = 0; ; cmdline++) {
-                if (*cmdline && isdigit(*cmdline)) {
-                        num = num * 10 + *cmdline - '0';
-                        continue;
-                }
-                if (*cmdline == '*') {
-                        if (num > 0)
-                                coeff = num;
-                        coeff_flag = 1;
-                }
-                if (!*cmdline || *cmdline == ',') {
-                        if (!coeff_flag)
-                                coeff = 1;
-                        /*
-                         * Round down to the nearest FAKE_NODE_MIN_SIZE.
-                         * Command-line coefficients are in megabytes.
-                         */
-                        size = ((u64)num << 20) & FAKE_NODE_MIN_HASH_MASK;
-                        if (size)
-                                for (i = 0; i < coeff; i++, num_nodes++)
-                                        if (setup_node_range(num_nodes, &addr,
-                                                size, max_addr) < 0)
-                                                goto done;
-                        if (!*cmdline)
-                                break;
-                        coeff_flag = 0;
-                        coeff = -1;
-                }
-                num = 0;
-        }
-done:
-        if (!num_nodes)
-                return -1;
-        /* Fill remainder of system RAM, if appropriate. */
-        if (addr < max_addr) {
-                if (coeff_flag && coeff < 0) {
-                        /* Split remaining nodes into num-sized chunks */
-                        num_nodes += split_nodes_by_size(&addr, max_addr,
-                                                         num_nodes, num);
-                        goto out;
-                }
-                switch (*(cmdline - 1)) {
-                case '*':
-                        /* Split remaining nodes into coeff chunks */
-                        if (coeff <= 0)
-                                break;
-                        num_nodes += split_nodes_equally(&addr, max_addr,
-                                                         num_nodes, coeff);
-                        break;
-                case ',':
-                        /* Do not allocate remaining system RAM */
-                        break;
-                default:
-                        /* Give one final node */
-                        setup_node_range(num_nodes, &addr, max_addr - addr,
-                                         max_addr);
-                        num_nodes++;
-                }
+                size = memparse(cmdline, &cmdline);
+                num_nodes = split_nodes_size_interleave(addr, max_addr, size);
+        } else {
+                unsigned long n;
+
+                n = simple_strtoul(cmdline, NULL, 0);
+                num_nodes = split_nodes_interleave(addr, max_addr, num_phys_nodes, n);
         }
-out:
+
+        if (num_nodes < 0)
+                return num_nodes;
         memnode_shift = compute_hash_shift(nodes, num_nodes, NULL);
         if (memnode_shift < 0) {
                 memnode_shift = 0;
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index ed34f5e35999..c9ba9deafe83 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -6,6 +6,14 @@
 
 #define PGALLOC_GFP GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO
 
+#ifdef CONFIG_HIGHPTE
+#define PGALLOC_USER_GFP __GFP_HIGHMEM
+#else
+#define PGALLOC_USER_GFP 0
+#endif
+
+gfp_t __userpte_alloc_gfp = PGALLOC_GFP | PGALLOC_USER_GFP;
+
 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 {
         return (pte_t *)__get_free_page(PGALLOC_GFP);
@@ -15,16 +23,29 @@ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
 {
         struct page *pte;
 
-#ifdef CONFIG_HIGHPTE
-        pte = alloc_pages(PGALLOC_GFP | __GFP_HIGHMEM, 0);
-#else
-        pte = alloc_pages(PGALLOC_GFP, 0);
-#endif
+        pte = alloc_pages(__userpte_alloc_gfp, 0);
         if (pte)
                 pgtable_page_ctor(pte);
         return pte;
 }
 
+static int __init setup_userpte(char *arg)
+{
+        if (!arg)
+                return -EINVAL;
+
+        /*
+         * "userpte=nohigh" disables allocation of user pagetables in
+         * high memory.
+         */
+        if (strcmp(arg, "nohigh") == 0)
+                __userpte_alloc_gfp &= ~__GFP_HIGHMEM;
+        else
+                return -EINVAL;
+        return 0;
+}
+early_param("userpte", setup_userpte);
+
 void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte)
 {
         pgtable_page_dtor(pte);
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 65b58e4b0b8b..426f3a1a64d3 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -41,7 +41,7 @@ union smp_flush_state {
         struct {
                 struct mm_struct *flush_mm;
                 unsigned long flush_va;
-                spinlock_t tlbstate_lock;
+                raw_spinlock_t tlbstate_lock;
                 DECLARE_BITMAP(flush_cpumask, NR_CPUS);
         };
         char pad[INTERNODE_CACHE_BYTES];
@@ -181,7 +181,7 @@ static void flush_tlb_others_ipi(const struct cpumask *cpumask,
          * num_online_cpus() <= NUM_INVALIDATE_TLB_VECTORS, but it is
          * probably not worth checking this for a cache-hot lock.
          */
-        spin_lock(&f->tlbstate_lock);
+        raw_spin_lock(&f->tlbstate_lock);
 
         f->flush_mm = mm;
         f->flush_va = va;
@@ -199,7 +199,7 @@ static void flush_tlb_others_ipi(const struct cpumask *cpumask,
 
         f->flush_mm = NULL;
         f->flush_va = 0;
-        spin_unlock(&f->tlbstate_lock);
+        raw_spin_unlock(&f->tlbstate_lock);
 }
 
 void native_flush_tlb_others(const struct cpumask *cpumask,
@@ -223,7 +223,7 @@ static int __cpuinit init_smp_flush(void)
         int i;
 
         for (i = 0; i < ARRAY_SIZE(flush_state); i++)
-                spin_lock_init(&flush_state[i].tlbstate_lock);
+                raw_spin_lock_init(&flush_state[i].tlbstate_lock);
 
         return 0;
 }
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 3347f696edc7..2c505ee71014 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -159,7 +159,7 @@ static int nmi_setup_mux(void)
 
         for_each_possible_cpu(i) {
                 per_cpu(cpu_msrs, i).multiplex =
-                        kmalloc(multiplex_size, GFP_KERNEL);
+                        kzalloc(multiplex_size, GFP_KERNEL);
                 if (!per_cpu(cpu_msrs, i).multiplex)
                         return 0;
         }
@@ -179,7 +179,6 @@ static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
                 if (counter_config[i].enabled) {
                         multiplex[i].saved = -(u64)counter_config[i].count;
                 } else {
-                        multiplex[i].addr  = 0;
                         multiplex[i].saved = 0;
                 }
         }
@@ -189,25 +188,27 @@ static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 
 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 {
+        struct op_msr *counters = msrs->counters;
         struct op_msr *multiplex = msrs->multiplex;
         int i;
 
         for (i = 0; i < model->num_counters; ++i) {
                 int virt = op_x86_phys_to_virt(i);
-                if (multiplex[virt].addr)
-                        rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
+                if (counters[i].addr)
+                        rdmsrl(counters[i].addr, multiplex[virt].saved);
         }
 }
 
 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 {
+        struct op_msr *counters = msrs->counters;
         struct op_msr *multiplex = msrs->multiplex;
         int i;
 
         for (i = 0; i < model->num_counters; ++i) {
                 int virt = op_x86_phys_to_virt(i);
-                if (multiplex[virt].addr)
-                        wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
+                if (counters[i].addr)
+                        wrmsrl(counters[i].addr, multiplex[virt].saved);
         }
 }
 
@@ -303,11 +304,11 @@ static int allocate_msrs(void)
 
         int i;
         for_each_possible_cpu(i) {
-                per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
+                per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
                                                         GFP_KERNEL);
                 if (!per_cpu(cpu_msrs, i).counters)
                         return 0;
-                per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
+                per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
                                                         GFP_KERNEL);
                 if (!per_cpu(cpu_msrs, i).controls)
                         return 0;
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 39686c29f03a..6a58256dce9f 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -22,6 +22,9 @@
 #include <asm/ptrace.h>
 #include <asm/msr.h>
 #include <asm/nmi.h>
+#include <asm/apic.h>
+#include <asm/processor.h>
+#include <asm/cpufeature.h>
 
 #include "op_x86_model.h"
 #include "op_counter.h"
@@ -43,15 +46,13 @@
 
 static unsigned long reset_value[NUM_VIRT_COUNTERS];
 
-#ifdef CONFIG_OPROFILE_IBS
-
 /* IbsFetchCtl bits/masks */
 #define IBS_FETCH_RAND_EN               (1ULL<<57)
 #define IBS_FETCH_VAL                   (1ULL<<49)
 #define IBS_FETCH_ENABLE                (1ULL<<48)
 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
 
-/*IbsOpCtl bits */
+/* IbsOpCtl bits */
 #define IBS_OP_CNT_CTL                  (1ULL<<19)
 #define IBS_OP_VAL                      (1ULL<<18)
 #define IBS_OP_ENABLE                   (1ULL<<17)
@@ -59,7 +60,7 @@ static unsigned long reset_value[NUM_VIRT_COUNTERS];
 #define IBS_FETCH_SIZE                  6
 #define IBS_OP_SIZE                     12
 
-static int has_ibs;     /* AMD Family10h and later */
+static u32 ibs_caps;
 
 struct op_ibs_config {
         unsigned long op_enabled;
@@ -71,24 +72,52 @@ struct op_ibs_config {
 };
 
 static struct op_ibs_config ibs_config;
+static u64 ibs_op_ctl;
 
-#endif
+/*
+ * IBS cpuid feature detection
+ */
 
-#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+#define IBS_CPUID_FEATURES      0x8000001b
+
+/*
+ * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
+ * bit 0 is used to indicate the existence of IBS.
+ */
+#define IBS_CAPS_AVAIL                  (1LL<<0)
+#define IBS_CAPS_RDWROPCNT              (1LL<<3)
+#define IBS_CAPS_OPCNT                  (1LL<<4)
+
+/*
+ * IBS randomization macros
+ */
+#define IBS_RANDOM_BITS                 12
+#define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
+#define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
 
-static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
+static u32 get_ibs_caps(void)
 {
-        int i;
+        u32 ibs_caps;
+        unsigned int max_level;
 
-        for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
-                int hw_counter = op_x86_virt_to_phys(i);
-                if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
-                        msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
-                else
-                        msrs->multiplex[i].addr = 0;
-        }
+        if (!boot_cpu_has(X86_FEATURE_IBS))
+                return 0;
+
+        /* check IBS cpuid feature flags */
+        max_level = cpuid_eax(0x80000000);
+        if (max_level < IBS_CPUID_FEATURES)
+                return IBS_CAPS_AVAIL;
+
+        ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
+        if (!(ibs_caps & IBS_CAPS_AVAIL))
+                /* cpuid flags not valid */
+                return IBS_CAPS_AVAIL;
+
+        return ibs_caps;
 }
 
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+
 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
                                struct op_msrs const * const msrs)
 {
@@ -98,7 +127,7 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
         /* enable active counters */
         for (i = 0; i < NUM_COUNTERS; ++i) {
                 int virt = op_x86_phys_to_virt(i);
-                if (!counter_config[virt].enabled)
+                if (!reset_value[virt])
                         continue;
                 rdmsrl(msrs->controls[i].addr, val);
                 val &= model->reserved;
@@ -107,10 +136,6 @@ static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
         }
 }
 
-#else
-
-static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
-
 #endif
 
 /* functions for op_amd_spec */
@@ -122,18 +147,12 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
         for (i = 0; i < NUM_COUNTERS; i++) {
                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
-                else
-                        msrs->counters[i].addr = 0;
         }
 
         for (i = 0; i < NUM_CONTROLS; i++) {
                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
-                else
-                        msrs->controls[i].addr = 0;
         }
-
-        op_mux_fill_in_addresses(msrs);
 }
 
 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
@@ -144,7 +163,8 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 
         /* setup reset_value */
         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
-                if (counter_config[i].enabled)
+                if (counter_config[i].enabled
+                    && msrs->counters[op_x86_virt_to_phys(i)].addr)
                         reset_value[i] = counter_config[i].count;
                 else
                         reset_value[i] = 0;
@@ -152,9 +172,18 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
 
         /* clear all counters */
         for (i = 0; i < NUM_CONTROLS; ++i) {
-                if (unlikely(!msrs->controls[i].addr))
+                if (unlikely(!msrs->controls[i].addr)) {
+                        if (counter_config[i].enabled && !smp_processor_id())
+                                /*
+                                 * counter is reserved, this is on all
+                                 * cpus, so report only for cpu #0
+                                 */
+                                op_x86_warn_reserved(i);
                         continue;
+                }
                 rdmsrl(msrs->controls[i].addr, val);
+                if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
+                        op_x86_warn_in_use(i);
                 val &= model->reserved;
                 wrmsrl(msrs->controls[i].addr, val);
         }
@@ -169,9 +198,7 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
         /* enable active counters */
         for (i = 0; i < NUM_COUNTERS; ++i) {
                 int virt = op_x86_phys_to_virt(i);
-                if (!counter_config[virt].enabled)
-                        continue;
-                if (!msrs->counters[i].addr)
+                if (!reset_value[virt])
                         continue;
 
                 /* setup counter registers */
@@ -185,7 +212,60 @@ static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
         }
 }
 
-#ifdef CONFIG_OPROFILE_IBS
+/*
+ * 16-bit Linear Feedback Shift Register (LFSR)
+ *
+ *                       16   14   13    11
+ * Feedback polynomial = X  + X  + X  +  X  + 1
+ */
+static unsigned int lfsr_random(void)
+{
+        static unsigned int lfsr_value = 0xF00D;
+        unsigned int bit;
+
+        /* Compute next bit to shift in */
+        bit = ((lfsr_value >> 0) ^
+               (lfsr_value >> 2) ^
+               (lfsr_value >> 3) ^
+               (lfsr_value >> 5)) & 0x0001;
+
+        /* Advance to next register value */
+        lfsr_value = (lfsr_value >> 1) | (bit << 15);
+
+        return lfsr_value;
+}
+
+/*
+ * IBS software randomization
+ *
+ * The IBS periodic op counter is randomized in software. The lower 12
+ * bits of the 20 bit counter are randomized. IbsOpCurCnt is
+ * initialized with a 12 bit random value.
+ */
+static inline u64 op_amd_randomize_ibs_op(u64 val)
+{
+        unsigned int random = lfsr_random();
+
+        if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
+                /*
+                 * Work around if the hw can not write to IbsOpCurCnt
+                 *
+                 * Randomize the lower 8 bits of the 16 bit
+                 * IbsOpMaxCnt [15:0] value in the range of -128 to
+                 * +127 by adding/subtracting an offset to the
+                 * maximum count (IbsOpMaxCnt).
+                 *
+                 * To avoid over or underflows and protect upper bits
+                 * starting at bit 16, the initial value for
+                 * IbsOpMaxCnt must fit in the range from 0x0081 to
+                 * 0xff80.
+                 */
+                val += (s8)(random >> 4);
+        else
+                val |= (u64)(random & IBS_RANDOM_MASK) << 32;
+
+        return val;
+}
 
 static inline void
 op_amd_handle_ibs(struct pt_regs * const regs,
@@ -194,7 +274,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
         u64 val, ctl;
         struct op_entry entry;
 
-        if (!has_ibs)
+        if (!ibs_caps)
                 return;
 
         if (ibs_config.fetch_enabled) {
@@ -236,8 +316,7 @@ op_amd_handle_ibs(struct pt_regs * const regs,
                         oprofile_write_commit(&entry);
 
                         /* reenable the IRQ */
-                        ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
-                        ctl |= IBS_OP_ENABLE;
+                        ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
                 }
         }
@@ -246,41 +325,57 @@ op_amd_handle_ibs(struct pt_regs * const regs,
 static inline void op_amd_start_ibs(void)
 {
         u64 val;
-        if (has_ibs && ibs_config.fetch_enabled) {
+
+        if (!ibs_caps)
+                return;
+
+        if (ibs_config.fetch_enabled) {
                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
                 val |= IBS_FETCH_ENABLE;
                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
         }
 
-        if (has_ibs && ibs_config.op_enabled) {
-                val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
-                val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
-                val |= IBS_OP_ENABLE;
+        if (ibs_config.op_enabled) {
+                ibs_op_ctl = ibs_config.max_cnt_op >> 4;
+                if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
+                        /*
+                         * IbsOpCurCnt not supported.  See
+                         * op_amd_randomize_ibs_op() for details.
+                         */
+                        ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
+                } else {
+                        /*
+                         * The start value is randomized with a
+                         * positive offset, we need to compensate it
+                         * with the half of the randomized range. Also
+                         * avoid underflows.
+                         */
+                        ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
+                                         0xFFFFULL);
+                }
+                if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
+                        ibs_op_ctl |= IBS_OP_CNT_CTL;
+                ibs_op_ctl |= IBS_OP_ENABLE;
+                val = op_amd_randomize_ibs_op(ibs_op_ctl);
                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
         }
 }
 
 static void op_amd_stop_ibs(void)
 {
-        if (has_ibs && ibs_config.fetch_enabled)
+        if (!ibs_caps)
+                return;
+
+        if (ibs_config.fetch_enabled)
                 /* clear max count and enable */
                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
 
-        if (has_ibs && ibs_config.op_enabled)
+        if (ibs_config.op_enabled)
                 /* clear max count and enable */
                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 }
 
-#else
-
-static inline void op_amd_handle_ibs(struct pt_regs * const regs,
-                                    struct op_msrs const * const msrs) { }
-static inline void op_amd_start_ibs(void) { }
-static inline void op_amd_stop_ibs(void) { }
-
-#endif
-
 static int op_amd_check_ctrs(struct pt_regs * const regs,
                              struct op_msrs const * const msrs)
 {
@@ -355,8 +450,6 @@ static void op_amd_shutdown(struct op_msrs const * const msrs)
         }
 }
 
-#ifdef CONFIG_OPROFILE_IBS
-
 static u8 ibs_eilvt_off;
 
 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
@@ -405,45 +498,36 @@ static int init_ibs_nmi(void)
                 return 1;
         }
 
-#ifdef CONFIG_NUMA
-        /* Sanity check */
-        /* Works only for 64bit with proper numa implementation. */
-        if (nodes != num_possible_nodes()) {
-                printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
-                        "found: %d, expected %d",
-                        nodes, num_possible_nodes());
-                return 1;
-        }
-#endif
         return 0;
 }
 
 /* uninitialize the APIC for the IBS interrupts if needed */
 static void clear_ibs_nmi(void)
 {
-        if (has_ibs)
+        if (ibs_caps)
                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
 }
 
 /* initialize the APIC for the IBS interrupts if available */
 static void ibs_init(void)
 {
-        has_ibs = boot_cpu_has(X86_FEATURE_IBS);
+        ibs_caps = get_ibs_caps();
 
-        if (!has_ibs)
+        if (!ibs_caps)
                 return;
 
         if (init_ibs_nmi()) {
-                has_ibs = 0;
+                ibs_caps = 0;
                 return;
         }
 
-        printk(KERN_INFO "oprofile: AMD IBS detected\n");
+        printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
+               (unsigned)ibs_caps);
 }
 
 static void ibs_exit(void)
 {
-        if (!has_ibs)
+        if (!ibs_caps)
                 return;
 
         clear_ibs_nmi();
@@ -463,7 +547,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
         if (ret)
                 return ret;
 
-        if (!has_ibs)
+        if (!ibs_caps)
                 return ret;
 
         /* model specific files */
@@ -473,7 +557,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
         ibs_config.fetch_enabled = 0;
         ibs_config.max_cnt_op = 250000;
         ibs_config.op_enabled = 0;
-        ibs_config.dispatched_ops = 1;
+        ibs_config.dispatched_ops = 0;
 
         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
         oprofilefs_create_ulong(sb, dir, "enable",
@@ -488,8 +572,9 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root)
                                 &ibs_config.op_enabled);
         oprofilefs_create_ulong(sb, dir, "max_count",
                                 &ibs_config.max_cnt_op);
-        oprofilefs_create_ulong(sb, dir, "dispatched_ops",
-                                &ibs_config.dispatched_ops);
+        if (ibs_caps & IBS_CAPS_OPCNT)
+                oprofilefs_create_ulong(sb, dir, "dispatched_ops",
+                                        &ibs_config.dispatched_ops);
 
         return 0;
 }
@@ -507,19 +592,6 @@ static void op_amd_exit(void)
         ibs_exit();
 }
 
-#else
-
-/* no IBS support */
-
-static int op_amd_init(struct oprofile_operations *ops)
-{
-        return 0;
-}
-
-static void op_amd_exit(void) {}
-
-#endif /* CONFIG_OPROFILE_IBS */
-
 struct op_x86_model_spec op_amd_spec = {
         .num_counters           = NUM_COUNTERS,
         .num_controls           = NUM_CONTROLS,
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index ac6b354becdf..e6a160a4684a 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -394,12 +394,6 @@ static void p4_fill_in_addresses(struct op_msrs * const msrs)
         setup_num_counters();
         stag = get_stagger();
 
-        /* initialize some registers */
-        for (i = 0; i < num_counters; ++i)
-                msrs->counters[i].addr = 0;
-        for (i = 0; i < num_controls; ++i)
-                msrs->controls[i].addr = 0;
-
         /* the counter & cccr registers we pay attention to */
         for (i = 0; i < num_counters; ++i) {
                 addr = p4_counters[VIRT_CTR(stag, i)].counter_address;
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 8eb05878554c..5d1727ba409e 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -37,15 +37,11 @@ static void ppro_fill_in_addresses(struct op_msrs * const msrs)
         for (i = 0; i < num_counters; i++) {
                 if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
                         msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
-                else
-                        msrs->counters[i].addr = 0;
         }
 
         for (i = 0; i < num_counters; i++) {
                 if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
                         msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
-                else
-                        msrs->controls[i].addr = 0;
         }
 }
 
@@ -57,7 +53,7 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
         int i;
 
         if (!reset_value) {
-                reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
+                reset_value = kzalloc(sizeof(reset_value[0]) * num_counters,
                                         GFP_ATOMIC);
                 if (!reset_value)
                         return;
@@ -82,9 +78,18 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
 
         /* clear all counters */
         for (i = 0; i < num_counters; ++i) {
-                if (unlikely(!msrs->controls[i].addr))
+                if (unlikely(!msrs->controls[i].addr)) {
+                        if (counter_config[i].enabled && !smp_processor_id())
+                                /*
+                                 * counter is reserved, this is on all
+                                 * cpus, so report only for cpu #0
+                                 */
+                                op_x86_warn_reserved(i);
                         continue;
+                }
                 rdmsrl(msrs->controls[i].addr, val);
+                if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
+                        op_x86_warn_in_use(i);
                 val &= model->reserved;
                 wrmsrl(msrs->controls[i].addr, val);
         }
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index 7b8e75d16081..ff82a755edd4 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -57,6 +57,26 @@ struct op_x86_model_spec {
 
 struct op_counter_config;
 
+static inline void op_x86_warn_in_use(int counter)
+{
+        /*
+         * The warning indicates an already running counter. If
+         * oprofile doesn't collect data, then try using a different
+         * performance counter on your platform to monitor the desired
+         * event. Delete counter #%d from the desired event by editing
+         * the /usr/share/oprofile/%s/<cpu>/events file. If the event
+         * cannot be monitored by any other counter, contact your
+         * hardware or BIOS vendor.
+         */
+        pr_warning("oprofile: counter #%d on cpu #%d may already be used\n",
+                   counter, smp_processor_id());
+}
+
+static inline void op_x86_warn_reserved(int counter)
+{
+        pr_warning("oprofile: counter #%d is already reserved\n", counter);
+}
+
 extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
                            struct op_counter_config *counter_config);
 extern int op_x86_phys_to_virt(int phys);
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 959e548a7039..5f11ff6f5389 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -15,6 +15,51 @@ struct pci_root_info {
         int busnum;
 };
 
+static bool pci_use_crs = true;
+
+static int __init set_use_crs(const struct dmi_system_id *id)
+{
+        pci_use_crs = true;
+        return 0;
+}
+
+static const struct dmi_system_id pci_use_crs_table[] __initconst = {
+        /* http://bugzilla.kernel.org/show_bug.cgi?id=14183 */
+        {
+                .callback = set_use_crs,
+                .ident = "IBM System x3800",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "x3800"),
+                },
+        },
+        {}
+};
+
+void __init pci_acpi_crs_quirks(void)
+{
+        int year;
+
+        if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && year < 2008)
+                pci_use_crs = false;
+
+        dmi_check_system(pci_use_crs_table);
+
+        /*
+         * If the user specifies "pci=use_crs" or "pci=nocrs" explicitly, that
+         * takes precedence over anything we figured out above.
+         */
+        if (pci_probe & PCI_ROOT_NO_CRS)
+                pci_use_crs = false;
+        else if (pci_probe & PCI_USE__CRS)
+                pci_use_crs = true;
+
+        printk(KERN_INFO "PCI: %s host bridge windows from ACPI; "
+               "if necessary, use \"pci=%s\" and report a bug\n",
+               pci_use_crs ? "Using" : "Ignoring",
+               pci_use_crs ? "nocrs" : "use_crs");
+}
+
 static acpi_status
 resource_to_addr(struct acpi_resource *resource,
                         struct acpi_resource_address64 *addr)
@@ -45,20 +90,6 @@ count_resource(struct acpi_resource *acpi_res, void *data)
         return AE_OK;
 }
 
-static int
-bus_has_transparent_bridge(struct pci_bus *bus)
-{
-        struct pci_dev *dev;
-
-        list_for_each_entry(dev, &bus->devices, bus_list) {
-                u16 class = dev->class >> 8;
-
-                if (class == PCI_CLASS_BRIDGE_PCI && dev->transparent)
-                        return true;
-        }
-        return false;
-}
-
 static void
 align_resource(struct acpi_device *bridge, struct resource *res)
 {
@@ -92,12 +123,8 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         acpi_status status;
         unsigned long flags;
         struct resource *root;
-        int max_root_bus_resources = PCI_BUS_NUM_RESOURCES;
         u64 start, end;
 
-        if (bus_has_transparent_bridge(info->bus))
-                max_root_bus_resources -= 3;
-
         status = resource_to_addr(acpi_res, &addr);
         if (!ACPI_SUCCESS(status))
                 return AE_OK;
@@ -115,15 +142,6 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
 
         start = addr.minimum + addr.translation_offset;
         end = start + addr.address_length - 1;
-        if (info->res_num >= max_root_bus_resources) {
-                if (pci_probe & PCI_USE__CRS)
-                        printk(KERN_WARNING "PCI: Failed to allocate "
-                               "0x%lx-0x%lx from %s for %s due to _CRS "
-                               "returning more than %d resource descriptors\n",
-                               (unsigned long) start, (unsigned long) end,
-                               root->name, info->name, max_root_bus_resources);
-                return AE_OK;
-        }
 
         res = &info->res[info->res_num];
         res->name = info->name;
@@ -133,7 +151,7 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
         res->child = NULL;
         align_resource(info->bridge, res);
 
-        if (!(pci_probe & PCI_USE__CRS)) {
+        if (!pci_use_crs) {
                 dev_printk(KERN_DEBUG, &info->bridge->dev,
                            "host bridge window %pR (ignored)\n", res);
                 return AE_OK;
@@ -143,7 +161,7 @@ setup_resource(struct acpi_resource *acpi_res, void *data)
                 dev_err(&info->bridge->dev,
                         "can't allocate host bridge window %pR\n", res);
         } else {
-                info->bus->resource[info->res_num] = res;
+                pci_bus_add_resource(info->bus, res, 0);
                 info->res_num++;
                 if (addr.translation_offset)
                         dev_info(&info->bridge->dev, "host bridge window %pR "
@@ -164,10 +182,8 @@ get_current_resources(struct acpi_device *device, int busnum,
         struct pci_root_info info;
         size_t size;
 
-        if (!(pci_probe & PCI_USE__CRS))
-                dev_info(&device->dev,
-                         "ignoring host bridge windows from ACPI; "
-                         "boot with \"pci=use_crs\" to use them\n");
+        if (pci_use_crs)
+                pci_bus_remove_resources(bus);
 
         info.bridge = device;
         info.bus = bus;
diff --git a/arch/x86/pci/bus_numa.c b/arch/x86/pci/bus_numa.c
index f939d603adfa..12d54ff3654d 100644
--- a/arch/x86/pci/bus_numa.c
+++ b/arch/x86/pci/bus_numa.c
@@ -36,13 +36,14 @@ void x86_pci_root_bus_res_quirks(struct pci_bus *b)
         printk(KERN_DEBUG "PCI: peer root bus %02x res updated from pci conf\n",
                         b->number);
 
+        pci_bus_remove_resources(b);
         info = &pci_root_info[i];
         for (j = 0; j < info->res_num; j++) {
                 struct resource *res;
                 struct resource *root;
 
                 res = &info->res[j];
-                b->resource[j] = res;
+                pci_bus_add_resource(b, res, 0);
                 if (res->flags & IORESOURCE_IO)
                         root = &ioport_resource;
                 else
diff --git a/arch/x86/pci/bus_numa.h b/arch/x86/pci/bus_numa.h
index adbc23fe82ac..731b64ee8d84 100644
--- a/arch/x86/pci/bus_numa.h
+++ b/arch/x86/pci/bus_numa.h
@@ -2,8 +2,7 @@
 
 /*
  * sub bus (transparent) will use entres from 3 to store extra from
- * root, so need to make sure we have enough slot there, Should we
- * increase PCI_BUS_NUM_RESOURCES?
+ * root, so need to make sure we have enough slot there.
  */
 #define RES_NUM 16
 struct pci_root_info {
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index d2552c68e94d..3736176acaab 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -520,6 +520,9 @@ char * __devinit  pcibios_setup(char *str)
         } else if (!strcmp(str, "use_crs")) {
                 pci_probe |= PCI_USE__CRS;
                 return NULL;
+        } else if (!strcmp(str, "nocrs")) {
+                pci_probe |= PCI_ROOT_NO_CRS;
+                return NULL;
         } else if (!strcmp(str, "earlydump")) {
                 pci_early_dump_regs = 1;
                 return NULL;
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c
index 5dc9e8c63fcd..5a8fbf8d4cac 100644
--- a/arch/x86/pci/i386.c
+++ b/arch/x86/pci/i386.c
@@ -60,22 +60,20 @@ skip_isa_ioresource_align(struct pci_dev *dev) {
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-void
-pcibios_align_resource(void *data, struct resource *res,
+resource_size_t
+pcibios_align_resource(void *data, const struct resource *res,
                         resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
+        resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO) {
-                resource_size_t start = res->start;
-
                 if (skip_isa_ioresource_align(dev))
-                        return;
-                if (start & 0x300) {
+                        return start;
+                if (start & 0x300)
                         start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
         }
+        return start;
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 0696d506c4ad..b02f6d8ac922 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -590,6 +590,8 @@ static __init int intel_router_probe(struct irq_router *r, struct pci_dev *route
         case PCI_DEVICE_ID_INTEL_ICH10_1:
         case PCI_DEVICE_ID_INTEL_ICH10_2:
         case PCI_DEVICE_ID_INTEL_ICH10_3:
+        case PCI_DEVICE_ID_INTEL_CPT_LPC1:
+        case PCI_DEVICE_ID_INTEL_CPT_LPC2:
                 r->name = "PIIX/ICH";
                 r->get = pirq_piix_get;
                 r->set = pirq_piix_set;
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index b19d1e54201e..8f3f9a50b1e0 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -303,22 +303,17 @@ static void __init pci_mmcfg_check_end_bus_number(void)
 {
         struct pci_mmcfg_region *cfg, *cfgx;
 
-        /* last one*/
-        cfg = list_entry(pci_mmcfg_list.prev, typeof(*cfg), list);
-        if (cfg)
-                if (cfg->end_bus < cfg->start_bus)
-                        cfg->end_bus = 255;
-
-        if (list_is_singular(&pci_mmcfg_list))
-                return;
-
-        /* don't overlap please */
+        /* Fixup overlaps */
         list_for_each_entry(cfg, &pci_mmcfg_list, list) {
                 if (cfg->end_bus < cfg->start_bus)
                         cfg->end_bus = 255;
 
+                /* Don't access the list head ! */
+                if (cfg->list.next == &pci_mmcfg_list)
+                        break;
+
                 cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
-                if (cfg != cfgx && cfg->end_bus >= cfgx->start_bus)
+                if (cfg->end_bus >= cfgx->start_bus)
                         cfg->end_bus = cfgx->start_bus - 1;
         }
 }
diff --git a/arch/x86/pci/numaq_32.c b/arch/x86/pci/numaq_32.c
index 8eb295e116f6..8884a1c1ada6 100644
--- a/arch/x86/pci/numaq_32.c
+++ b/arch/x86/pci/numaq_32.c
@@ -8,9 +8,7 @@
 #include <asm/apic.h>
 #include <asm/mpspec.h>
 #include <asm/pci_x86.h>
-
-#define XQUAD_PORTIO_BASE 0xfe400000
-#define XQUAD_PORTIO_QUAD 0x40000  /* 256k per quad. */
+#include <asm/numaq.h>
 
 #define BUS2QUAD(global) (mp_bus_id_to_node[global])
 
@@ -18,8 +16,6 @@
 
 #define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
 
-#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
-
 #define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
         (0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
 
diff --git a/arch/x86/tools/test_get_len.c b/arch/x86/tools/test_get_len.c
index bee8d6ac2691..13403fc95a96 100644
--- a/arch/x86/tools/test_get_len.c
+++ b/arch/x86/tools/test_get_len.c
@@ -43,7 +43,7 @@ static int x86_64;
 static void usage(void)
 {
         fprintf(stderr, "Usage: objdump -d a.out | awk -f distill.awk |"
-                " %s [-y|-n] [-v] \n", prog);
+                " %s [-y|-n] [-v]\n", prog);
         fprintf(stderr, "\t-y   64bit mode\n");
         fprintf(stderr, "\t-n   32bit mode\n");
         fprintf(stderr, "\t-v   verbose mode\n");
@@ -69,7 +69,7 @@ static void dump_field(FILE *fp, const char *name, const char *indent,
 
 static void dump_insn(FILE *fp, struct insn *insn)
 {
-        fprintf(fp, "Instruction = { \n");
+        fprintf(fp, "Instruction = {\n");
         dump_field(fp, "prefixes", "\t",        &insn->prefixes);
         dump_field(fp, "rex_prefix", "\t",      &insn->rex_prefix);
         dump_field(fp, "vex_prefix", "\t",      &insn->vex_prefix);
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index a138770c358e..76bf35554117 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -394,7 +394,7 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 #define kern_addr_valid(addr)   (1)
 
 extern  void update_mmu_cache(struct vm_area_struct * vma,
-                              unsigned long address, pte_t pte);
+                              unsigned long address, pte_t *ptep);
 
 /*
  * remap a physical page `pfn' of size `size' with page protection `prot'
diff --git a/arch/xtensa/kernel/pci.c b/arch/xtensa/kernel/pci.c
index b7c073484e01..cd1026931203 100644
--- a/arch/xtensa/kernel/pci.c
+++ b/arch/xtensa/kernel/pci.c
@@ -69,26 +69,25 @@ static int pci_bus_count;
  * but we want to try to avoid allocating at 0x2900-0x2bff
  * which might have be mirrored at 0x0100-0x03ff..
  */
-void
-pcibios_align_resource(void *data, struct resource *res, resource_size_t size,
-                       resource_size_t align)
+resource_size_t
+pcibios_align_resource(void *data, const struct resource *res,
+                       resource_size_t size, resource_size_t align)
 {
         struct pci_dev *dev = data;
+        resource_size_t start = res->start;
 
         if (res->flags & IORESOURCE_IO) {
-                resource_size_t start = res->start;
-
                 if (size > 0x100) {
                         printk(KERN_ERR "PCI: I/O Region %s/%d too large"
                                " (%ld bytes)\n", pci_name(dev),
                                dev->resource - res, size);
                 }
 
-                if (start & 0x300) {
+                if (start & 0x300)
                         start = (start + 0x3ff) & ~0x3ff;
-                        res->start = start;
-                }
         }
+
+        return start;
 }
 
 int
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 3ba990c67676..85df4655d326 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -147,9 +147,9 @@ void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
 #endif
 
 void
-update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte)
+update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
 {
-        unsigned long pfn = pte_pfn(pte);
+        unsigned long pfn = pte_pfn(*ptep);
         struct page *page;
 
         if (!pfn_valid(pfn))