diff options
author | Paul Mundt <lethal@linux-sh.org> | 2008-07-29 09:46:55 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-29 09:46:55 -0400 |
commit | 93dc544cf4892b9188d7d0d4946b0394020b4551 (patch) | |
tree | 5b518ad829e53e23304cc463e8013b66f1c087a0 /arch | |
parent | 1795cf48b322b4d19230a40dbe7181acedd34a94 (diff) |
sh: Provide common CPU headers, prune the SH-2 and SH-2A directories.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sh/Makefile | 26 | ||||
-rw-r--r-- | arch/sh/include/cpu-common/cpu/addrspace.h (renamed from arch/sh/include/cpu-sh2/cpu/addrspace.h) | 0 | ||||
-rw-r--r-- | arch/sh/include/cpu-common/cpu/cacheflush.h (renamed from arch/sh/include/cpu-sh2a/cpu/cacheflush.h) | 4 | ||||
-rw-r--r-- | arch/sh/include/cpu-common/cpu/mmu_context.h (renamed from arch/sh/include/cpu-sh2/cpu/mmu_context.h) | 0 | ||||
-rw-r--r-- | arch/sh/include/cpu-common/cpu/sigcontext.h (renamed from arch/sh/include/cpu-sh2/cpu/sigcontext.h) | 0 | ||||
-rw-r--r-- | arch/sh/include/cpu-common/cpu/timer.h (renamed from arch/sh/include/cpu-sh2/cpu/timer.h) | 0 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2/cpu/cacheflush.h | 44 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/addrspace.h | 10 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/dma.h | 24 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/mmu_context.h | 16 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/timer.h | 6 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/ubc.h | 33 | ||||
-rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/watchdog.h | 70 |
13 files changed, 23 insertions, 210 deletions
diff --git a/arch/sh/Makefile b/arch/sh/Makefile index fb3b65ed2910..fafc01236f6a 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile | |||
@@ -91,7 +91,6 @@ LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64+4' | |||
91 | LDFLAGS += -EB | 91 | LDFLAGS += -EB |
92 | endif | 92 | endif |
93 | 93 | ||
94 | |||
95 | head-y := arch/sh/kernel/init_task.o | 94 | head-y := arch/sh/kernel/init_task.o |
96 | head-$(CONFIG_SUPERH32) += arch/sh/kernel/head_32.o | 95 | head-$(CONFIG_SUPERH32) += arch/sh/kernel/head_32.o |
97 | head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o | 96 | head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o |
@@ -134,11 +133,22 @@ endif | |||
134 | # Companion chips | 133 | # Companion chips |
135 | core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/ | 134 | core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/ |
136 | 135 | ||
137 | cpuincdir-$(CONFIG_CPU_SH2) := cpu-sh2 | 136 | # |
138 | cpuincdir-$(CONFIG_CPU_SH2A) := cpu-sh2a | 137 | # CPU header paths |
139 | cpuincdir-$(CONFIG_CPU_SH3) := cpu-sh3 | 138 | # |
140 | cpuincdir-$(CONFIG_CPU_SH4) := cpu-sh4 | 139 | # These are ordered by optimization level. A CPU family that is a subset |
141 | cpuincdir-$(CONFIG_CPU_SH5) := cpu-sh5 | 140 | # of another (ie, SH-2A / SH-2), is picked up first, with increasing |
141 | # levels of genericness if nothing more suitable is situated in the | ||
142 | # hierarchy. | ||
143 | # | ||
144 | # As an example, in order of preference, SH-2A > SH-2 > common definitions. | ||
145 | # | ||
146 | cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a | ||
147 | cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2 | ||
148 | cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3 | ||
149 | cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4 | ||
150 | cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5 | ||
151 | cpuincdir-y += cpu-common # Must be last | ||
142 | 152 | ||
143 | libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y) | 153 | libs-$(CONFIG_SUPERH32) := arch/sh/lib/ $(libs-y) |
144 | libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y) | 154 | libs-$(CONFIG_SUPERH64) := arch/sh/lib64/ $(libs-y) |
@@ -149,8 +159,8 @@ drivers-$(CONFIG_OPROFILE) += arch/sh/oprofile/ | |||
149 | 159 | ||
150 | boot := arch/sh/boot | 160 | boot := arch/sh/boot |
151 | 161 | ||
152 | cflags-y += -Iarch/sh/include/$(cpuincdir-y) | 162 | cflags-y += $(foreach d, $(cpuincdir-y), -Iarch/sh/include/$(d)) \ |
153 | cflags-y += $(foreach d, $(machdir-y), -Iarch/sh/include/$(d)) | 163 | $(foreach d, $(machdir-y), -Iarch/sh/include/$(d)) |
154 | 164 | ||
155 | KBUILD_CFLAGS += -pipe $(cflags-y) | 165 | KBUILD_CFLAGS += -pipe $(cflags-y) |
156 | KBUILD_CPPFLAGS += $(cflags-y) | 166 | KBUILD_CPPFLAGS += $(cflags-y) |
diff --git a/arch/sh/include/cpu-sh2/cpu/addrspace.h b/arch/sh/include/cpu-common/cpu/addrspace.h index 2b9ab93efa4e..2b9ab93efa4e 100644 --- a/arch/sh/include/cpu-sh2/cpu/addrspace.h +++ b/arch/sh/include/cpu-common/cpu/addrspace.h | |||
diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-common/cpu/cacheflush.h index 2979efb26de3..c3db00b73605 100644 --- a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h +++ b/arch/sh/include/cpu-common/cpu/cacheflush.h | |||
@@ -10,7 +10,7 @@ | |||
10 | #ifndef __ASM_CPU_SH2_CACHEFLUSH_H | 10 | #ifndef __ASM_CPU_SH2_CACHEFLUSH_H |
11 | #define __ASM_CPU_SH2_CACHEFLUSH_H | 11 | #define __ASM_CPU_SH2_CACHEFLUSH_H |
12 | 12 | ||
13 | /* | 13 | /* |
14 | * Cache flushing: | 14 | * Cache flushing: |
15 | * | 15 | * |
16 | * - flush_cache_all() flushes entire cache | 16 | * - flush_cache_all() flushes entire cache |
@@ -40,5 +40,5 @@ | |||
40 | #define flush_cache_sigtramp(vaddr) do { } while (0) | 40 | #define flush_cache_sigtramp(vaddr) do { } while (0) |
41 | 41 | ||
42 | #define p3_cache_init() do { } while (0) | 42 | #define p3_cache_init() do { } while (0) |
43 | #endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ | ||
44 | 43 | ||
44 | #endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ | ||
diff --git a/arch/sh/include/cpu-sh2/cpu/mmu_context.h b/arch/sh/include/cpu-common/cpu/mmu_context.h index beeb299e01ec..beeb299e01ec 100644 --- a/arch/sh/include/cpu-sh2/cpu/mmu_context.h +++ b/arch/sh/include/cpu-common/cpu/mmu_context.h | |||
diff --git a/arch/sh/include/cpu-sh2/cpu/sigcontext.h b/arch/sh/include/cpu-common/cpu/sigcontext.h index fe5c15dd6e87..fe5c15dd6e87 100644 --- a/arch/sh/include/cpu-sh2/cpu/sigcontext.h +++ b/arch/sh/include/cpu-common/cpu/sigcontext.h | |||
diff --git a/arch/sh/include/cpu-sh2/cpu/timer.h b/arch/sh/include/cpu-common/cpu/timer.h index a39c241e8195..a39c241e8195 100644 --- a/arch/sh/include/cpu-sh2/cpu/timer.h +++ b/arch/sh/include/cpu-common/cpu/timer.h | |||
diff --git a/arch/sh/include/cpu-sh2/cpu/cacheflush.h b/arch/sh/include/cpu-sh2/cpu/cacheflush.h deleted file mode 100644 index 2979efb26de3..000000000000 --- a/arch/sh/include/cpu-sh2/cpu/cacheflush.h +++ /dev/null | |||
@@ -1,44 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-sh/cpu-sh2/cacheflush.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #ifndef __ASM_CPU_SH2_CACHEFLUSH_H | ||
11 | #define __ASM_CPU_SH2_CACHEFLUSH_H | ||
12 | |||
13 | /* | ||
14 | * Cache flushing: | ||
15 | * | ||
16 | * - flush_cache_all() flushes entire cache | ||
17 | * - flush_cache_mm(mm) flushes the specified mm context's cache lines | ||
18 | * - flush_cache_dup mm(mm) handles cache flushing when forking | ||
19 | * - flush_cache_page(mm, vmaddr, pfn) flushes a single page | ||
20 | * - flush_cache_range(vma, start, end) flushes a range of pages | ||
21 | * | ||
22 | * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache | ||
23 | * - flush_icache_range(start, end) flushes(invalidates) a range for icache | ||
24 | * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache | ||
25 | * | ||
26 | * Caches are indexed (effectively) by physical address on SH-2, so | ||
27 | * we don't need them. | ||
28 | */ | ||
29 | #define flush_cache_all() do { } while (0) | ||
30 | #define flush_cache_mm(mm) do { } while (0) | ||
31 | #define flush_cache_dup_mm(mm) do { } while (0) | ||
32 | #define flush_cache_range(vma, start, end) do { } while (0) | ||
33 | #define flush_cache_page(vma, vmaddr, pfn) do { } while (0) | ||
34 | #define flush_dcache_page(page) do { } while (0) | ||
35 | #define flush_dcache_mmap_lock(mapping) do { } while (0) | ||
36 | #define flush_dcache_mmap_unlock(mapping) do { } while (0) | ||
37 | #define flush_icache_range(start, end) do { } while (0) | ||
38 | #define flush_icache_page(vma,pg) do { } while (0) | ||
39 | #define flush_icache_user_range(vma,pg,adr,len) do { } while (0) | ||
40 | #define flush_cache_sigtramp(vaddr) do { } while (0) | ||
41 | |||
42 | #define p3_cache_init() do { } while (0) | ||
43 | #endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ | ||
44 | |||
diff --git a/arch/sh/include/cpu-sh2a/cpu/addrspace.h b/arch/sh/include/cpu-sh2a/cpu/addrspace.h deleted file mode 100644 index 795ddd6856a3..000000000000 --- a/arch/sh/include/cpu-sh2a/cpu/addrspace.h +++ /dev/null | |||
@@ -1,10 +0,0 @@ | |||
1 | #ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H | ||
2 | #define __ASM_SH_CPU_SH2A_ADDRSPACE_H | ||
3 | |||
4 | #define P0SEG 0x00000000 | ||
5 | #define P1SEG 0x00000000 | ||
6 | #define P2SEG 0x20000000 | ||
7 | #define P3SEG 0x00000000 | ||
8 | #define P4SEG 0x80000000 | ||
9 | |||
10 | #endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */ | ||
diff --git a/arch/sh/include/cpu-sh2a/cpu/dma.h b/arch/sh/include/cpu-sh2a/cpu/dma.h index d66b43cdc637..27a13ef4fdfc 100644 --- a/arch/sh/include/cpu-sh2a/cpu/dma.h +++ b/arch/sh/include/cpu-sh2a/cpu/dma.h | |||
@@ -1,23 +1 @@ | |||
1 | /* | #include <cpu-sh2/cpu/dma.h> | |
2 | * Definitions for the SH-2 DMAC. | ||
3 | * | ||
4 | * Copyright (C) 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #ifndef __ASM_CPU_SH2_DMA_H | ||
11 | #define __ASM_CPU_SH2_DMA_H | ||
12 | |||
13 | #define SH_MAX_DMA_CHANNELS 2 | ||
14 | |||
15 | #define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 }) | ||
16 | #define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 }) | ||
17 | #define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 }) | ||
18 | #define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c }) | ||
19 | |||
20 | #define DMAOR 0xffffffb0 | ||
21 | |||
22 | #endif /* __ASM_CPU_SH2_DMA_H */ | ||
23 | |||
diff --git a/arch/sh/include/cpu-sh2a/cpu/mmu_context.h b/arch/sh/include/cpu-sh2a/cpu/mmu_context.h deleted file mode 100644 index beeb299e01ec..000000000000 --- a/arch/sh/include/cpu-sh2a/cpu/mmu_context.h +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | /* | ||
2 | * include/asm-sh/cpu-sh2/mmu_context.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #ifndef __ASM_CPU_SH2_MMU_CONTEXT_H | ||
11 | #define __ASM_CPU_SH2_MMU_CONTEXT_H | ||
12 | |||
13 | /* No MMU */ | ||
14 | |||
15 | #endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */ | ||
16 | |||
diff --git a/arch/sh/include/cpu-sh2a/cpu/timer.h b/arch/sh/include/cpu-sh2a/cpu/timer.h deleted file mode 100644 index a39c241e8195..000000000000 --- a/arch/sh/include/cpu-sh2a/cpu/timer.h +++ /dev/null | |||
@@ -1,6 +0,0 @@ | |||
1 | #ifndef __ASM_CPU_SH2_TIMER_H | ||
2 | #define __ASM_CPU_SH2_TIMER_H | ||
3 | |||
4 | /* Nothing needed yet */ | ||
5 | |||
6 | #endif /* __ASM_CPU_SH2_TIMER_H */ | ||
diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h index ba0e87f19c7a..8ce2fc1cf625 100644 --- a/arch/sh/include/cpu-sh2a/cpu/ubc.h +++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h | |||
@@ -1,32 +1 @@ | |||
1 | /* | #include <cpu-sh2/cpu/ubc.h> | |
2 | * include/asm-sh/cpu-sh2/ubc.h | ||
3 | * | ||
4 | * Copyright (C) 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #ifndef __ASM_CPU_SH2_UBC_H | ||
11 | #define __ASM_CPU_SH2_UBC_H | ||
12 | |||
13 | #define UBC_BARA 0xffffff40 | ||
14 | #define UBC_BAMRA 0xffffff44 | ||
15 | #define UBC_BBRA 0xffffff48 | ||
16 | #define UBC_BARB 0xffffff60 | ||
17 | #define UBC_BAMRB 0xffffff64 | ||
18 | #define UBC_BBRB 0xffffff68 | ||
19 | #define UBC_BDRB 0xffffff70 | ||
20 | #define UBC_BDMRB 0xffffff74 | ||
21 | #define UBC_BRCR 0xffffff78 | ||
22 | |||
23 | /* | ||
24 | * We don't have any ASID changes to make in the UBC on the SH-2. | ||
25 | * | ||
26 | * Make these purposely invalid to track misuse. | ||
27 | */ | ||
28 | #define UBC_BASRA 0x00000000 | ||
29 | #define UBC_BASRB 0x00000000 | ||
30 | |||
31 | #endif /* __ASM_CPU_SH2_UBC_H */ | ||
32 | |||
diff --git a/arch/sh/include/cpu-sh2a/cpu/watchdog.h b/arch/sh/include/cpu-sh2a/cpu/watchdog.h index 393161c9c6d0..e7e8259e468c 100644 --- a/arch/sh/include/cpu-sh2a/cpu/watchdog.h +++ b/arch/sh/include/cpu-sh2a/cpu/watchdog.h | |||
@@ -1,69 +1 @@ | |||
1 | /* | #include <cpu-sh2/cpu/watchdog.h> | |
2 | * include/asm-sh/cpu-sh2/watchdog.h | ||
3 | * | ||
4 | * Copyright (C) 2002, 2003 Paul Mundt | ||
5 | * | ||
6 | * This file is subject to the terms and conditions of the GNU General Public | ||
7 | * License. See the file "COPYING" in the main directory of this archive | ||
8 | * for more details. | ||
9 | */ | ||
10 | #ifndef __ASM_CPU_SH2_WATCHDOG_H | ||
11 | #define __ASM_CPU_SH2_WATCHDOG_H | ||
12 | |||
13 | /* | ||
14 | * More SH-2 brilliance .. its not good enough that we can't read | ||
15 | * and write the same sizes to WTCNT, now we have to read and write | ||
16 | * with different sizes at different addresses for WTCNT _and_ RSTCSR. | ||
17 | * | ||
18 | * At least on the bright side no one has managed to screw over WTCSR | ||
19 | * in this fashion .. yet. | ||
20 | */ | ||
21 | /* Register definitions */ | ||
22 | #define WTCNT 0xfffffe80 | ||
23 | #define WTCSR 0xfffffe80 | ||
24 | #define RSTCSR 0xfffffe82 | ||
25 | |||
26 | #define WTCNT_R (WTCNT + 1) | ||
27 | #define RSTCSR_R (RSTCSR + 1) | ||
28 | |||
29 | /* Bit definitions */ | ||
30 | #define WTCSR_IOVF 0x80 | ||
31 | #define WTCSR_WT 0x40 | ||
32 | #define WTCSR_TME 0x20 | ||
33 | #define WTCSR_RSTS 0x00 | ||
34 | |||
35 | #define RSTCSR_RSTS 0x20 | ||
36 | |||
37 | /** | ||
38 | * sh_wdt_read_rstcsr - Read from Reset Control/Status Register | ||
39 | * | ||
40 | * Reads back the RSTCSR value. | ||
41 | */ | ||
42 | static inline __u8 sh_wdt_read_rstcsr(void) | ||
43 | { | ||
44 | /* | ||
45 | * Same read/write brain-damage as for WTCNT here.. | ||
46 | */ | ||
47 | return ctrl_inb(RSTCSR_R); | ||
48 | } | ||
49 | |||
50 | /** | ||
51 | * sh_wdt_write_csr - Write to Reset Control/Status Register | ||
52 | * | ||
53 | * @val: Value to write | ||
54 | * | ||
55 | * Writes the given value @val to the lower byte of the control/status | ||
56 | * register. The upper byte is set manually on each write. | ||
57 | */ | ||
58 | static inline void sh_wdt_write_rstcsr(__u8 val) | ||
59 | { | ||
60 | /* | ||
61 | * Note: Due to the brain-damaged nature of this register, | ||
62 | * we can't presently touch the WOVF bit, since the upper byte | ||
63 | * has to be swapped for this. So just leave it alone.. | ||
64 | */ | ||
65 | ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); | ||
66 | } | ||
67 | |||
68 | #endif /* __ASM_CPU_SH2_WATCHDOG_H */ | ||
69 | |||