[MIPS] time: Move R4000 clockevent device code to separate configurable file

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

8 files changed, 318 insertions, 241 deletions

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 235d4514e0a9..cb027580cd1d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -21,6 +21,7 @@ config MACH_ALCHEMY
 
 config BASLER_EXCITE
         bool "Basler eXcite smart camera"
+        select CEVT_R4K
         select DMA_COHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -47,6 +48,7 @@ config BASLER_EXCITE_PROTOTYPE
 
 config BCM47XX
         bool "BCM47XX based boards"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -63,6 +65,7 @@ config BCM47XX
 
 config MIPS_COBALT
         bool "Cobalt Server"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select I8253
@@ -80,6 +83,7 @@ config MIPS_COBALT
 config MACH_DECSTATION
         bool "DECstations"
         select BOOT_ELF32
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select NO_IOPORT
         select IRQ_CPU
@@ -111,6 +115,7 @@ config MACH_JAZZ
         select ARC
         select ARC32
         select ARCH_MAY_HAVE_PC_FDC
+        select CEVT_R4K
         select GENERIC_ISA_DMA
         select IRQ_CPU
         select I8253
@@ -130,6 +135,7 @@ config MACH_JAZZ
 
 config LASAT
         bool "LASAT Networks platforms"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select SYS_HAS_EARLY_PRINTK
         select HW_HAS_PCI
@@ -146,6 +152,7 @@ config LASAT
 config LEMOTE_FULONG
         bool "Lemote Fulong mini-PC"
         select ARCH_SPARSEMEM_ENABLE
+        select CEVT_R4K
         select SYS_HAS_CPU_LOONGSON2
         select DMA_NONCOHERENT
         select BOOT_ELF32
@@ -170,6 +177,7 @@ config LEMOTE_FULONG
 config MIPS_ATLAS
         bool "MIPS Atlas board"
         select BOOT_ELF32
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select SYS_HAS_EARLY_PRINTK
         select IRQ_CPU
@@ -200,6 +208,7 @@ config MIPS_MALTA
         bool "MIPS Malta board"
         select ARCH_MAY_HAVE_PC_FDC
         select BOOT_ELF32
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA
         select IRQ_CPU
@@ -230,6 +239,7 @@ config MIPS_MALTA
 
 config MIPS_SEAD
         bool "MIPS SEAD board"
+        select CEVT_R4K
         select IRQ_CPU
         select DMA_NONCOHERENT
         select SYS_HAS_EARLY_PRINTK
@@ -248,6 +258,7 @@ config MIPS_SEAD
 
 config MIPS_SIM
         bool 'MIPS simulator (MIPSsim)'
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select SYS_HAS_EARLY_PRINTK
         select IRQ_CPU
@@ -265,6 +276,7 @@ config MIPS_SIM
 
 config MARKEINS
         bool "NEC EMMA2RH Mark-eins"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -279,6 +291,7 @@ config MARKEINS
 
 config MACH_VR41XX
         bool "NEC VR4100 series based machines"
+        select CEVT_R4K
         select SYS_HAS_CPU_VR41XX
         select GENERIC_HARDIRQS_NO__DO_IRQ
 
@@ -315,6 +328,7 @@ config PMC_MSP
 
 config PMC_YOSEMITE
         bool "PMC-Sierra Yosemite eval board"
+        select CEVT_R4K
         select DMA_COHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -335,6 +349,7 @@ config PMC_YOSEMITE
 
 config QEMU
         bool "Qemu"
+        select CEVT_R4K
         select DMA_COHERENT
         select GENERIC_ISA_DMA
         select HAVE_STD_PC_SERIAL_PORT
@@ -365,6 +380,7 @@ config SGI_IP22
         select ARC
         select ARC32
         select BOOT_ELF32
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HW_HAS_EISA
         select I8253
@@ -409,6 +425,7 @@ config SGI_IP32
         select ARC
         select ARC32
         select BOOT_ELF32
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HW_HAS_PCI
         select IRQ_CPU
@@ -536,6 +553,7 @@ config SNI_RM
         select ARC32 if CPU_LITTLE_ENDIAN
         select ARCH_MAY_HAVE_PC_FDC
         select BOOT_ELF32
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select GENERIC_ISA_DMA
         select HW_HAS_EISA
@@ -577,6 +595,7 @@ config TOSHIBA_JMR3927
 
 config TOSHIBA_RBTX4927
         bool "Toshiba RBTX49[23]7 board"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
@@ -597,6 +616,7 @@ config TOSHIBA_RBTX4927
 
 config TOSHIBA_RBTX4938
         bool "Toshiba RBTX4938 board"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select HAS_TXX9_SERIAL
         select HW_HAS_PCI
@@ -616,6 +636,7 @@ config TOSHIBA_RBTX4938
 
 config WR_PPMC
         bool "Wind River PPMC board"
+        select CEVT_R4K
         select IRQ_CPU
         select BOOT_ELF32
         select DMA_NONCOHERENT
@@ -708,6 +729,9 @@ config ARCH_MAY_HAVE_PC_FDC
 config BOOT_RAW
         bool
 
+config CEVT_R4K
+        bool
+
 config CFE
         bool
 
diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig
index a23d4154da01..b36cec58a9a8 100644
--- a/arch/mips/au1000/Kconfig
+++ b/arch/mips/au1000/Kconfig
@@ -137,6 +137,7 @@ config SOC_AU1200
 config SOC_AU1X00
         bool
         select 64BIT_PHYS_ADDR
+        select CEVT_R4K
         select IRQ_CPU
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_SUPPORTS_32BIT_KERNEL
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 95a356ef3910..a3afa39faae5 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -8,6 +8,8 @@ obj-y		+= cpu-probe.o branch.o entry.o genex.o irq.o process.o \
                    ptrace.o reset.o semaphore.o setup.o signal.o syscall.o \
                    time.o topology.o traps.o unaligned.o
 
+obj-$(CONFIG_CEVT_R4K)          += cevt-r4k.o
+
 binfmt_irix-objs        := irixelf.o irixinv.o irixioctl.o irixsig.o    \
                            irix5sys.o sysirix.o
 
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
new file mode 100644
index 000000000000..08b84d476c87
--- /dev/null
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -0,0 +1,272 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 MIPS Technologies, Inc.
+ * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
+ */
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/percpu.h>
+
+#include <asm/time.h>
+
+static int mips_next_event(unsigned long delta,
+                           struct clock_event_device *evt)
+{
+        unsigned int cnt;
+        int res;
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        {
+        unsigned long flags, vpflags;
+        local_irq_save(flags);
+        vpflags = dvpe();
+#endif
+        cnt = read_c0_count();
+        cnt += delta;
+        write_c0_compare(cnt);
+        res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
+#ifdef CONFIG_MIPS_MT_SMTC
+        evpe(vpflags);
+        local_irq_restore(flags);
+        }
+#endif
+        return res;
+}
+
+static void mips_set_mode(enum clock_event_mode mode,
+                          struct clock_event_device *evt)
+{
+        /* Nothing to do ...  */
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+static int cp0_timer_irq_installed;
+
+/*
+ * Timer ack for an R4k-compatible timer of a known frequency.
+ */
+static void c0_timer_ack(void)
+{
+        write_c0_compare(read_c0_compare());
+}
+
+/*
+ * Possibly handle a performance counter interrupt.
+ * Return true if the timer interrupt should not be checked
+ */
+static inline int handle_perf_irq(int r2)
+{
+        /*
+         * The performance counter overflow interrupt may be shared with the
+         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
+         * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
+         * and we can't reliably determine if a counter interrupt has also
+         * happened (!r2) then don't check for a timer interrupt.
+         */
+        return (cp0_perfcount_irq < 0) &&
+                perf_irq() == IRQ_HANDLED &&
+                !r2;
+}
+
+static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
+{
+        const int r2 = cpu_has_mips_r2;
+        struct clock_event_device *cd;
+        int cpu = smp_processor_id();
+
+        /*
+         * Suckage alert:
+         * Before R2 of the architecture there was no way to see if a
+         * performance counter interrupt was pending, so we have to run
+         * the performance counter interrupt handler anyway.
+         */
+        if (handle_perf_irq(r2))
+                goto out;
+
+        /*
+         * The same applies to performance counter interrupts.  But with the
+         * above we now know that the reason we got here must be a timer
+         * interrupt.  Being the paranoiacs we are we check anyway.
+         */
+        if (!r2 || (read_c0_cause() & (1 << 30))) {
+                c0_timer_ack();
+#ifdef CONFIG_MIPS_MT_SMTC
+                if (cpu_data[cpu].vpe_id)
+                        goto out;
+                cpu = 0;
+#endif
+                cd = &per_cpu(mips_clockevent_device, cpu);
+                cd->event_handler(cd);
+        }
+
+out:
+        return IRQ_HANDLED;
+}
+
+static struct irqaction c0_compare_irqaction = {
+        .handler = c0_compare_interrupt,
+#ifdef CONFIG_MIPS_MT_SMTC
+        .flags = IRQF_DISABLED,
+#else
+        .flags = IRQF_DISABLED | IRQF_PERCPU,
+#endif
+        .name = "timer",
+};
+
+#ifdef CONFIG_MIPS_MT_SMTC
+DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
+
+static void smtc_set_mode(enum clock_event_mode mode,
+                          struct clock_event_device *evt)
+{
+}
+
+static void mips_broadcast(cpumask_t mask)
+{
+        unsigned int cpu;
+
+        for_each_cpu_mask(cpu, mask)
+                smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
+}
+
+static void setup_smtc_dummy_clockevent_device(void)
+{
+        //uint64_t mips_freq = mips_hpt_^frequency;
+        unsigned int cpu = smp_processor_id();
+        struct clock_event_device *cd;
+
+        cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
+
+        cd->name                = "SMTC";
+        cd->features            = CLOCK_EVT_FEAT_DUMMY;
+
+        /* Calculate the min / max delta */
+        cd->mult        = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
+        cd->shift               = 0; //32;
+        cd->max_delta_ns        = 0; //clockevent_delta2ns(0x7fffffff, cd);
+        cd->min_delta_ns        = 0; //clockevent_delta2ns(0x30, cd);
+
+        cd->rating              = 200;
+        cd->irq                 = 17; //-1;
+//      if (cpu)
+//              cd->cpumask     = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
+//      else
+                cd->cpumask     = cpumask_of_cpu(cpu);
+
+        cd->set_mode            = smtc_set_mode;
+
+        cd->broadcast           = mips_broadcast;
+
+        clockevents_register_device(cd);
+}
+#endif
+
+static void mips_event_handler(struct clock_event_device *dev)
+{
+}
+
+/*
+ * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
+ */
+static int c0_compare_int_pending(void)
+{
+        return (read_c0_cause() >> cp0_compare_irq) & 0x100;
+}
+
+static int c0_compare_int_usable(void)
+{
+        const unsigned int delta = 0x300000;
+        unsigned int cnt;
+
+        /*
+         * IP7 already pending?  Try to clear it by acking the timer.
+         */
+        if (c0_compare_int_pending()) {
+                write_c0_compare(read_c0_compare());
+                irq_disable_hazard();
+                if (c0_compare_int_pending())
+                        return 0;
+        }
+
+        cnt = read_c0_count();
+        cnt += delta;
+        write_c0_compare(cnt);
+
+        while ((long)(read_c0_count() - cnt) <= 0)
+                ;       /* Wait for expiry  */
+
+        if (!c0_compare_int_pending())
+                return 0;
+
+        write_c0_compare(read_c0_compare());
+        irq_disable_hazard();
+        if (c0_compare_int_pending())
+                return 0;
+
+        /*
+         * Feels like a real count / compare timer.
+         */
+        return 1;
+}
+
+void __cpuinit mips_clockevent_init(void)
+{
+        uint64_t mips_freq = mips_hpt_frequency;
+        unsigned int cpu = smp_processor_id();
+        struct clock_event_device *cd;
+        unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
+
+        if (!cpu_has_counter)
+                return;
+
+#ifdef CONFIG_MIPS_MT_SMTC
+        setup_smtc_dummy_clockevent_device();
+
+        /*
+         * On SMTC we only register VPE0's compare interrupt as clockevent
+         * device.
+         */
+        if (cpu)
+                return;
+#endif
+
+        if (!c0_compare_int_usable())
+                return;
+
+        cd = &per_cpu(mips_clockevent_device, cpu);
+
+        cd->name                = "MIPS";
+        cd->features            = CLOCK_EVT_FEAT_ONESHOT;
+
+        /* Calculate the min / max delta */
+        cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
+        cd->shift               = 32;
+        cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
+        cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
+
+        cd->rating              = 300;
+        cd->irq                 = irq;
+#ifdef CONFIG_MIPS_MT_SMTC
+        cd->cpumask             = CPU_MASK_ALL;
+#else
+        cd->cpumask             = cpumask_of_cpu(cpu);
+#endif
+        cd->set_next_event      = mips_next_event;
+        cd->set_mode            = mips_set_mode;
+        cd->event_handler       = mips_event_handler;
+
+        clockevents_register_device(cd);
+
+        if (!cp0_timer_irq_installed) {
+#ifdef CONFIG_MIPS_MT_SMTC
+#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
+                setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
+#else
+                setup_irq(irq, &c0_compare_irqaction);
+#endif /* CONFIG_MIPS_MT_SMTC */
+                cp0_timer_irq_installed = 1;
+        }
+}
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index abadb8cb77c0..ea7cfe766a8e 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -81,14 +81,6 @@ static cycle_t null_hpt_read(void)
 }
 
 /*
- * Timer ack for an R4k-compatible timer of a known frequency.
- */
-static void c0_timer_ack(void)
-{
-        write_c0_compare(read_c0_compare());
-}
-
-/*
  * High precision timer functions for a R4k-compatible timer.
  */
 static cycle_t c0_hpt_read(void)
@@ -126,35 +118,6 @@ int (*perf_irq)(void) = null_perf_irq;
 EXPORT_SYMBOL(perf_irq);
 
 /*
- * Timer interrupt
- */
-int cp0_compare_irq;
-
-/*
- * Performance counter IRQ or -1 if shared with timer
- */
-int cp0_perfcount_irq;
-EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
-
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq(int r2)
-{
-        /*
-         * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-         * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-         * and we can't reliably determine if a counter interrupt has also
-         * happened (!r2) then don't check for a timer interrupt.
-         */
-        return (cp0_perfcount_irq < 0) &&
-                perf_irq() == IRQ_HANDLED &&
-                !r2;
-}
-
-/*
  * time_init() - it does the following things.
  *
  * 1) plat_time_init() -
@@ -219,84 +182,6 @@ struct clocksource clocksource_mips = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-static int mips_next_event(unsigned long delta,
-                           struct clock_event_device *evt)
-{
-        unsigned int cnt;
-        int res;
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        {
-        unsigned long flags, vpflags;
-        local_irq_save(flags);
-        vpflags = dvpe();
-#endif
-        cnt = read_c0_count();
-        cnt += delta;
-        write_c0_compare(cnt);
-        res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
-#ifdef CONFIG_MIPS_MT_SMTC
-        evpe(vpflags);
-        local_irq_restore(flags);
-        }
-#endif
-        return res;
-}
-
-static void mips_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
-{
-        /* Nothing to do ...  */
-}
-
-static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
-static int cp0_timer_irq_installed;
-
-static irqreturn_t timer_interrupt(int irq, void *dev_id)
-{
-        const int r2 = cpu_has_mips_r2;
-        struct clock_event_device *cd;
-        int cpu = smp_processor_id();
-
-        /*
-         * Suckage alert:
-         * Before R2 of the architecture there was no way to see if a
-         * performance counter interrupt was pending, so we have to run
-         * the performance counter interrupt handler anyway.
-         */
-        if (handle_perf_irq(r2))
-                goto out;
-
-        /*
-         * The same applies to performance counter interrupts.  But with the
-         * above we now know that the reason we got here must be a timer
-         * interrupt.  Being the paranoiacs we are we check anyway.
-         */
-        if (!r2 || (read_c0_cause() & (1 << 30))) {
-                c0_timer_ack();
-#ifdef CONFIG_MIPS_MT_SMTC
-                if (cpu_data[cpu].vpe_id)
-                        goto out;
-                cpu = 0;
-#endif
-                cd = &per_cpu(mips_clockevent_device, cpu);
-                cd->event_handler(cd);
-        }
-
-out:
-        return IRQ_HANDLED;
-}
-
-static struct irqaction timer_irqaction = {
-        .handler = timer_interrupt,
-#ifdef CONFIG_MIPS_MT_SMTC
-        .flags = IRQF_DISABLED,
-#else
-        .flags = IRQF_DISABLED | IRQF_PERCPU,
-#endif
-        .name = "timer",
-};
-
 static void __init init_mips_clocksource(void)
 {
         u64 temp;
@@ -336,8 +221,6 @@ static void smtc_set_mode(enum clock_event_mode mode,
 {
 }
 
-int dummycnt[NR_CPUS];
-
 static void mips_broadcast(cpumask_t mask)
 {
         unsigned int cpu;
@@ -378,113 +261,6 @@ static void setup_smtc_dummy_clockevent_device(void)
 }
 #endif
 
-static void mips_event_handler(struct clock_event_device *dev)
-{
-}
-
-/*
- * FIXME: This doesn't hold for the relocated E9000 compare interrupt.
- */
-static int c0_compare_int_pending(void)
-{
-        return (read_c0_cause() >> cp0_compare_irq) & 0x100;
-}
-
-static int c0_compare_int_usable(void)
-{
-        const unsigned int delta = 0x300000;
-        unsigned int cnt;
-
-        /*
-         * IP7 already pending?  Try to clear it by acking the timer.
-         */
-        if (c0_compare_int_pending()) {
-                write_c0_compare(read_c0_compare());
-                irq_disable_hazard();
-                if (c0_compare_int_pending())
-                        return 0;
-        }
-
-        cnt = read_c0_count();
-        cnt += delta;
-        write_c0_compare(cnt);
-
-        while ((long)(read_c0_count() - cnt) <= 0)
-                ;       /* Wait for expiry  */
-
-        if (!c0_compare_int_pending())
-                return 0;
-
-        write_c0_compare(read_c0_compare());
-        irq_disable_hazard();
-        if (c0_compare_int_pending())
-                return 0;
-
-        /*
-         * Feels like a real count / compare timer.
-         */
-        return 1;
-}
-
-void __cpuinit mips_clockevent_init(void)
-{
-        uint64_t mips_freq = mips_hpt_frequency;
-        unsigned int cpu = smp_processor_id();
-        struct clock_event_device *cd;
-        unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
-
-        if (!cpu_has_counter)
-                return;
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        setup_smtc_dummy_clockevent_device();
-
-        /*
-         * On SMTC we only register VPE0's compare interrupt as clockevent
-         * device.
-         */
-        if (cpu)
-                return;
-#endif
-
-        if (!c0_compare_int_usable())
-                return;
-
-        cd = &per_cpu(mips_clockevent_device, cpu);
-
-        cd->name                = "MIPS";
-        cd->features            = CLOCK_EVT_FEAT_ONESHOT;
-
-        /* Calculate the min / max delta */
-        cd->mult        = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
-        cd->shift               = 32;
-        cd->max_delta_ns        = clockevent_delta2ns(0x7fffffff, cd);
-        cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
-
-        cd->rating              = 300;
-        cd->irq                 = irq;
-#ifdef CONFIG_MIPS_MT_SMTC
-        cd->cpumask             = CPU_MASK_ALL;
-#else
-        cd->cpumask             = cpumask_of_cpu(cpu);
-#endif
-        cd->set_next_event      = mips_next_event;
-        cd->set_mode            = mips_set_mode;
-        cd->event_handler       = mips_event_handler;
-
-        clockevents_register_device(cd);
-
-        if (!cp0_timer_irq_installed) {
-#ifdef CONFIG_MIPS_MT_SMTC
-#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
-                setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
-#else
-                setup_irq(irq, &timer_irqaction);
-#endif /* CONFIG_MIPS_MT_SMTC */
-                cp0_timer_irq_installed = 1;
-        }
-}
-
 void __init time_init(void)
 {
         plat_time_init();
@@ -511,25 +287,8 @@ void __init time_init(void)
                 printk("Using %u.%03u MHz high precision timer.\n",
                        ((mips_hpt_frequency + 500) / 1000) / 1000,
                        ((mips_hpt_frequency + 500) / 1000) % 1000);
-
-#ifdef CONFIG_IRQ_CPU
-                setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
-#endif
         }
 
-        /*
-         * Call board specific timer interrupt setup.
-         *
-         * this pointer must be setup in machine setup routine.
-         *
-         * Even if a machine chooses to use a low-level timer interrupt,
-         * it still needs to setup the timer_irqaction.
-         * In that case, it might be better to set timer_irqaction.handler
-         * to be NULL function so that we are sure the high-level code
-         * is not invoked accidentally.
-         */
-        plat_timer_setup(&timer_irqaction);
-
         init_mips_clocksource();
         mips_clockevent_init();
 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index bbf01b81a4ff..7b78d137259f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1336,6 +1336,17 @@ extern void cpu_cache_init(void);
 extern void tlb_init(void);
 extern void flush_tlb_handlers(void);
 
+/*
+ * Timer interrupt
+ */
+int cp0_compare_irq;
+
+/*
+ * Performance counter IRQ or -1 if shared with timer
+ */
+int cp0_perfcount_irq;
+EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
+
 void __init per_cpu_trap_init(void)
 {
         unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/pmc-sierra/Kconfig b/arch/mips/pmc-sierra/Kconfig
index abbd0bbfabd7..6b293ce0935f 100644
--- a/arch/mips/pmc-sierra/Kconfig
+++ b/arch/mips/pmc-sierra/Kconfig
@@ -4,11 +4,13 @@ choice
 
 config PMC_MSP4200_EVAL
         bool "PMC-Sierra MSP4200 Eval Board"
+        select CEVT_R4K
         select IRQ_MSP_SLP
         select HW_HAS_PCI
 
 config PMC_MSP4200_GW
         bool "PMC-Sierra MSP4200 VoIP Gateway"
+        select CEVT_R4K
         select IRQ_MSP_SLP
         select HW_HAS_PCI
 
diff --git a/arch/mips/vr41xx/Kconfig b/arch/mips/vr41xx/Kconfig
index 8f4d3e74c230..eeb089f20c0d 100644
--- a/arch/mips/vr41xx/Kconfig
+++ b/arch/mips/vr41xx/Kconfig
@@ -5,6 +5,7 @@ choice
 
 config CASIO_E55
         bool "CASIO CASSIOPEIA E-10/15/55/65"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
         select ISA
@@ -13,6 +14,7 @@ config CASIO_E55
 
 config IBM_WORKPAD
         bool "IBM WorkPad z50"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
         select ISA
@@ -21,6 +23,7 @@ config IBM_WORKPAD
 
 config NEC_CMBVR4133
         bool "NEC CMB-VR4133"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
         select HW_HAS_PCI
@@ -29,6 +32,7 @@ config NEC_CMBVR4133
 
 config TANBAC_TB022X
         bool "TANBAC VR4131 multichip module and TANBAC VR4131DIMM"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
         select HW_HAS_PCI
@@ -43,6 +47,7 @@ config TANBAC_TB022X
 
 config VICTOR_MPC30X
         bool "Victor MP-C303/304"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
         select HW_HAS_PCI
@@ -52,6 +57,7 @@ config VICTOR_MPC30X
 
 config ZAO_CAPCELLA
         bool "ZAO Networks Capcella"
+        select CEVT_R4K
         select DMA_NONCOHERENT
         select IRQ_CPU
         select HW_HAS_PCI