diff options
author | Jean Pihet <j-pihet@ti.com> | 2011-05-09 06:02:13 -0400 |
---|---|---|
committer | Kevin Hilman <khilman@ti.com> | 2011-05-20 11:15:53 -0400 |
commit | 866ba0ef967c693dae952afafcb1582a390a82a0 (patch) | |
tree | c74c93907a3b2903e45a6628df342e6826e2de19 /arch | |
parent | 90d231f7673e20acc4f8b5c3effb5c12098179a7 (diff) |
OMAP3: clean-up mach specific cpuidle data structures
- sleep_latency and wake_latency are not used, replace them by
exit_latency which is used by cpuidle. exit_latency simply is
the sum of sleep_latency and wake_latency,
- replace threshold by target_residency,
- changed the OMAP3 specific cpuidle code accordingly,
- changed the OMAP3 board code accordingly.
Signed-off-by: Jean Pihet <j-pihet@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/board-rx51.c | 18 | ||||
-rw-r--r-- | arch/arm/mach-omap2/cpuidle34xx.c | 103 | ||||
-rw-r--r-- | arch/arm/mach-omap2/pm.h | 13 |
3 files changed, 63 insertions, 71 deletions
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c index f8ba20a14e62..fec4cac8fa0a 100644 --- a/arch/arm/mach-omap2/board-rx51.c +++ b/arch/arm/mach-omap2/board-rx51.c | |||
@@ -58,21 +58,25 @@ static struct platform_device leds_gpio = { | |||
58 | }, | 58 | }, |
59 | }; | 59 | }; |
60 | 60 | ||
61 | /* | ||
62 | * cpuidle C-states definition override from the default values. | ||
63 | * The 'exit_latency' field is the sum of sleep and wake-up latencies. | ||
64 | */ | ||
61 | static struct cpuidle_params rx51_cpuidle_params[] = { | 65 | static struct cpuidle_params rx51_cpuidle_params[] = { |
62 | /* C1 */ | 66 | /* C1 */ |
63 | {1, 110, 162, 5}, | 67 | {110 + 162, 5 , 1}, |
64 | /* C2 */ | 68 | /* C2 */ |
65 | {1, 106, 180, 309}, | 69 | {106 + 180, 309, 1}, |
66 | /* C3 */ | 70 | /* C3 */ |
67 | {0, 107, 410, 46057}, | 71 | {107 + 410, 46057, 0}, |
68 | /* C4 */ | 72 | /* C4 */ |
69 | {0, 121, 3374, 46057}, | 73 | {121 + 3374, 46057, 0}, |
70 | /* C5 */ | 74 | /* C5 */ |
71 | {1, 855, 1146, 46057}, | 75 | {855 + 1146, 46057, 1}, |
72 | /* C6 */ | 76 | /* C6 */ |
73 | {0, 7580, 4134, 484329}, | 77 | {7580 + 4134, 484329, 0}, |
74 | /* C7 */ | 78 | /* C7 */ |
75 | {1, 7505, 15274, 484329}, | 79 | {7505 + 15274, 484329, 1}, |
76 | }; | 80 | }; |
77 | 81 | ||
78 | static struct omap_lcd_config rx51_lcd_config = { | 82 | static struct omap_lcd_config rx51_lcd_config = { |
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 1c240eff3918..d7bc31a2b3af 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c | |||
@@ -52,11 +52,10 @@ | |||
52 | struct omap3_processor_cx { | 52 | struct omap3_processor_cx { |
53 | u8 valid; | 53 | u8 valid; |
54 | u8 type; | 54 | u8 type; |
55 | u32 sleep_latency; | 55 | u32 exit_latency; |
56 | u32 wakeup_latency; | ||
57 | u32 mpu_state; | 56 | u32 mpu_state; |
58 | u32 core_state; | 57 | u32 core_state; |
59 | u32 threshold; | 58 | u32 target_residency; |
60 | u32 flags; | 59 | u32 flags; |
61 | const char *desc; | 60 | const char *desc; |
62 | }; | 61 | }; |
@@ -75,19 +74,19 @@ struct powerdomain *cam_pd; | |||
75 | */ | 74 | */ |
76 | static struct cpuidle_params cpuidle_params_table[] = { | 75 | static struct cpuidle_params cpuidle_params_table[] = { |
77 | /* C1 */ | 76 | /* C1 */ |
78 | {1, 2, 2, 5}, | 77 | {2 + 2, 5, 1}, |
79 | /* C2 */ | 78 | /* C2 */ |
80 | {1, 10, 10, 30}, | 79 | {10 + 10, 30, 1}, |
81 | /* C3 */ | 80 | /* C3 */ |
82 | {1, 50, 50, 300}, | 81 | {50 + 50, 300, 1}, |
83 | /* C4 */ | 82 | /* C4 */ |
84 | {1, 1500, 1800, 4000}, | 83 | {1500 + 1800, 4000, 1}, |
85 | /* C5 */ | 84 | /* C5 */ |
86 | {1, 2500, 7500, 12000}, | 85 | {2500 + 7500, 12000, 1}, |
87 | /* C6 */ | 86 | /* C6 */ |
88 | {1, 3000, 8500, 15000}, | 87 | {3000 + 8500, 15000, 1}, |
89 | /* C7 */ | 88 | /* C7 */ |
90 | {1, 10000, 30000, 300000}, | 89 | {10000 + 30000, 300000, 1}, |
91 | }; | 90 | }; |
92 | 91 | ||
93 | static int omap3_idle_bm_check(void) | 92 | static int omap3_idle_bm_check(void) |
@@ -330,12 +329,10 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params) | |||
330 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { | 329 | for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) { |
331 | cpuidle_params_table[i].valid = | 330 | cpuidle_params_table[i].valid = |
332 | cpuidle_board_params[i].valid; | 331 | cpuidle_board_params[i].valid; |
333 | cpuidle_params_table[i].sleep_latency = | 332 | cpuidle_params_table[i].exit_latency = |
334 | cpuidle_board_params[i].sleep_latency; | 333 | cpuidle_board_params[i].exit_latency; |
335 | cpuidle_params_table[i].wake_latency = | 334 | cpuidle_params_table[i].target_residency = |
336 | cpuidle_board_params[i].wake_latency; | 335 | cpuidle_board_params[i].target_residency; |
337 | cpuidle_params_table[i].threshold = | ||
338 | cpuidle_board_params[i].threshold; | ||
339 | } | 336 | } |
340 | return; | 337 | return; |
341 | } | 338 | } |
@@ -357,12 +354,10 @@ void omap_init_power_states(void) | |||
357 | omap3_power_states[OMAP3_STATE_C1].valid = | 354 | omap3_power_states[OMAP3_STATE_C1].valid = |
358 | cpuidle_params_table[OMAP3_STATE_C1].valid; | 355 | cpuidle_params_table[OMAP3_STATE_C1].valid; |
359 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; | 356 | omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1; |
360 | omap3_power_states[OMAP3_STATE_C1].sleep_latency = | 357 | omap3_power_states[OMAP3_STATE_C1].exit_latency = |
361 | cpuidle_params_table[OMAP3_STATE_C1].sleep_latency; | 358 | cpuidle_params_table[OMAP3_STATE_C1].exit_latency; |
362 | omap3_power_states[OMAP3_STATE_C1].wakeup_latency = | 359 | omap3_power_states[OMAP3_STATE_C1].target_residency = |
363 | cpuidle_params_table[OMAP3_STATE_C1].wake_latency; | 360 | cpuidle_params_table[OMAP3_STATE_C1].target_residency; |
364 | omap3_power_states[OMAP3_STATE_C1].threshold = | ||
365 | cpuidle_params_table[OMAP3_STATE_C1].threshold; | ||
366 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; | 361 | omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON; |
367 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; | 362 | omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON; |
368 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; | 363 | omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID; |
@@ -372,12 +367,10 @@ void omap_init_power_states(void) | |||
372 | omap3_power_states[OMAP3_STATE_C2].valid = | 367 | omap3_power_states[OMAP3_STATE_C2].valid = |
373 | cpuidle_params_table[OMAP3_STATE_C2].valid; | 368 | cpuidle_params_table[OMAP3_STATE_C2].valid; |
374 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; | 369 | omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2; |
375 | omap3_power_states[OMAP3_STATE_C2].sleep_latency = | 370 | omap3_power_states[OMAP3_STATE_C2].exit_latency = |
376 | cpuidle_params_table[OMAP3_STATE_C2].sleep_latency; | 371 | cpuidle_params_table[OMAP3_STATE_C2].exit_latency; |
377 | omap3_power_states[OMAP3_STATE_C2].wakeup_latency = | 372 | omap3_power_states[OMAP3_STATE_C2].target_residency = |
378 | cpuidle_params_table[OMAP3_STATE_C2].wake_latency; | 373 | cpuidle_params_table[OMAP3_STATE_C2].target_residency; |
379 | omap3_power_states[OMAP3_STATE_C2].threshold = | ||
380 | cpuidle_params_table[OMAP3_STATE_C2].threshold; | ||
381 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; | 374 | omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON; |
382 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; | 375 | omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON; |
383 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | | 376 | omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID | |
@@ -388,12 +381,10 @@ void omap_init_power_states(void) | |||
388 | omap3_power_states[OMAP3_STATE_C3].valid = | 381 | omap3_power_states[OMAP3_STATE_C3].valid = |
389 | cpuidle_params_table[OMAP3_STATE_C3].valid; | 382 | cpuidle_params_table[OMAP3_STATE_C3].valid; |
390 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; | 383 | omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3; |
391 | omap3_power_states[OMAP3_STATE_C3].sleep_latency = | 384 | omap3_power_states[OMAP3_STATE_C3].exit_latency = |
392 | cpuidle_params_table[OMAP3_STATE_C3].sleep_latency; | 385 | cpuidle_params_table[OMAP3_STATE_C3].exit_latency; |
393 | omap3_power_states[OMAP3_STATE_C3].wakeup_latency = | 386 | omap3_power_states[OMAP3_STATE_C3].target_residency = |
394 | cpuidle_params_table[OMAP3_STATE_C3].wake_latency; | 387 | cpuidle_params_table[OMAP3_STATE_C3].target_residency; |
395 | omap3_power_states[OMAP3_STATE_C3].threshold = | ||
396 | cpuidle_params_table[OMAP3_STATE_C3].threshold; | ||
397 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; | 388 | omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET; |
398 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; | 389 | omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON; |
399 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | | 390 | omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID | |
@@ -404,12 +395,10 @@ void omap_init_power_states(void) | |||
404 | omap3_power_states[OMAP3_STATE_C4].valid = | 395 | omap3_power_states[OMAP3_STATE_C4].valid = |
405 | cpuidle_params_table[OMAP3_STATE_C4].valid; | 396 | cpuidle_params_table[OMAP3_STATE_C4].valid; |
406 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; | 397 | omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4; |
407 | omap3_power_states[OMAP3_STATE_C4].sleep_latency = | 398 | omap3_power_states[OMAP3_STATE_C4].exit_latency = |
408 | cpuidle_params_table[OMAP3_STATE_C4].sleep_latency; | 399 | cpuidle_params_table[OMAP3_STATE_C4].exit_latency; |
409 | omap3_power_states[OMAP3_STATE_C4].wakeup_latency = | 400 | omap3_power_states[OMAP3_STATE_C4].target_residency = |
410 | cpuidle_params_table[OMAP3_STATE_C4].wake_latency; | 401 | cpuidle_params_table[OMAP3_STATE_C4].target_residency; |
411 | omap3_power_states[OMAP3_STATE_C4].threshold = | ||
412 | cpuidle_params_table[OMAP3_STATE_C4].threshold; | ||
413 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; | 402 | omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF; |
414 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; | 403 | omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON; |
415 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | | 404 | omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID | |
@@ -420,12 +409,10 @@ void omap_init_power_states(void) | |||
420 | omap3_power_states[OMAP3_STATE_C5].valid = | 409 | omap3_power_states[OMAP3_STATE_C5].valid = |
421 | cpuidle_params_table[OMAP3_STATE_C5].valid; | 410 | cpuidle_params_table[OMAP3_STATE_C5].valid; |
422 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; | 411 | omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5; |
423 | omap3_power_states[OMAP3_STATE_C5].sleep_latency = | 412 | omap3_power_states[OMAP3_STATE_C5].exit_latency = |
424 | cpuidle_params_table[OMAP3_STATE_C5].sleep_latency; | 413 | cpuidle_params_table[OMAP3_STATE_C5].exit_latency; |
425 | omap3_power_states[OMAP3_STATE_C5].wakeup_latency = | 414 | omap3_power_states[OMAP3_STATE_C5].target_residency = |
426 | cpuidle_params_table[OMAP3_STATE_C5].wake_latency; | 415 | cpuidle_params_table[OMAP3_STATE_C5].target_residency; |
427 | omap3_power_states[OMAP3_STATE_C5].threshold = | ||
428 | cpuidle_params_table[OMAP3_STATE_C5].threshold; | ||
429 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; | 416 | omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET; |
430 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; | 417 | omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET; |
431 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | | 418 | omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID | |
@@ -436,12 +423,10 @@ void omap_init_power_states(void) | |||
436 | omap3_power_states[OMAP3_STATE_C6].valid = | 423 | omap3_power_states[OMAP3_STATE_C6].valid = |
437 | cpuidle_params_table[OMAP3_STATE_C6].valid; | 424 | cpuidle_params_table[OMAP3_STATE_C6].valid; |
438 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; | 425 | omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6; |
439 | omap3_power_states[OMAP3_STATE_C6].sleep_latency = | 426 | omap3_power_states[OMAP3_STATE_C6].exit_latency = |
440 | cpuidle_params_table[OMAP3_STATE_C6].sleep_latency; | 427 | cpuidle_params_table[OMAP3_STATE_C6].exit_latency; |
441 | omap3_power_states[OMAP3_STATE_C6].wakeup_latency = | 428 | omap3_power_states[OMAP3_STATE_C6].target_residency = |
442 | cpuidle_params_table[OMAP3_STATE_C6].wake_latency; | 429 | cpuidle_params_table[OMAP3_STATE_C6].target_residency; |
443 | omap3_power_states[OMAP3_STATE_C6].threshold = | ||
444 | cpuidle_params_table[OMAP3_STATE_C6].threshold; | ||
445 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; | 430 | omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF; |
446 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; | 431 | omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET; |
447 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | | 432 | omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID | |
@@ -452,12 +437,10 @@ void omap_init_power_states(void) | |||
452 | omap3_power_states[OMAP3_STATE_C7].valid = | 437 | omap3_power_states[OMAP3_STATE_C7].valid = |
453 | cpuidle_params_table[OMAP3_STATE_C7].valid; | 438 | cpuidle_params_table[OMAP3_STATE_C7].valid; |
454 | omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; | 439 | omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7; |
455 | omap3_power_states[OMAP3_STATE_C7].sleep_latency = | 440 | omap3_power_states[OMAP3_STATE_C7].exit_latency = |
456 | cpuidle_params_table[OMAP3_STATE_C7].sleep_latency; | 441 | cpuidle_params_table[OMAP3_STATE_C7].exit_latency; |
457 | omap3_power_states[OMAP3_STATE_C7].wakeup_latency = | 442 | omap3_power_states[OMAP3_STATE_C7].target_residency = |
458 | cpuidle_params_table[OMAP3_STATE_C7].wake_latency; | 443 | cpuidle_params_table[OMAP3_STATE_C7].target_residency; |
459 | omap3_power_states[OMAP3_STATE_C7].threshold = | ||
460 | cpuidle_params_table[OMAP3_STATE_C7].threshold; | ||
461 | omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; | 444 | omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF; |
462 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; | 445 | omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF; |
463 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | | 446 | omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID | |
@@ -512,8 +495,8 @@ int __init omap3_idle_init(void) | |||
512 | if (!cx->valid) | 495 | if (!cx->valid) |
513 | continue; | 496 | continue; |
514 | cpuidle_set_statedata(state, cx); | 497 | cpuidle_set_statedata(state, cx); |
515 | state->exit_latency = cx->sleep_latency + cx->wakeup_latency; | 498 | state->exit_latency = cx->exit_latency; |
516 | state->target_residency = cx->threshold; | 499 | state->target_residency = cx->target_residency; |
517 | state->flags = cx->flags; | 500 | state->flags = cx->flags; |
518 | state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? | 501 | state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ? |
519 | omap3_enter_idle_bm : omap3_enter_idle; | 502 | omap3_enter_idle_bm : omap3_enter_idle; |
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 797bfd12b643..32dbc1311efd 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h | |||
@@ -36,11 +36,16 @@ static inline int omap4_opp_init(void) | |||
36 | } | 36 | } |
37 | #endif | 37 | #endif |
38 | 38 | ||
39 | /* | ||
40 | * cpuidle mach specific parameters | ||
41 | * | ||
42 | * The board code can override the default C-states definition using | ||
43 | * omap3_pm_init_cpuidle | ||
44 | */ | ||
39 | struct cpuidle_params { | 45 | struct cpuidle_params { |
40 | u8 valid; | 46 | u32 exit_latency; /* exit_latency = sleep + wake-up latencies */ |
41 | u32 sleep_latency; | 47 | u32 target_residency; |
42 | u32 wake_latency; | 48 | u8 valid; /* validates the C-state */ |
43 | u32 threshold; | ||
44 | }; | 49 | }; |
45 | 50 | ||
46 | #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE) | 51 | #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE) |