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authorSrinivas KANDAGATLA <srinivas.kandagatla@st.com>2011-06-02 06:30:44 -0400
committerPaul Mundt <lethal@linux-sh.org>2011-06-05 23:30:02 -0400
commit298c48a811673ba5e292359545f3af6d1a6c9764 (patch)
tree3f81630f55a7b3c3f49d0567c4e88e99e1737ba5 /arch
parent0792644d22852f40c8ad16c4ba1fefd76aba5643 (diff)
sh: fix wrong icache/dcache address-array start addr in cache-debugfs.
This patch fixes a icache/dcache address-array start address while dumping its entires in debugfs. Perviously the code was attempting to remember the address in static variable, which is no more required for debugfs, as the function can be executed in one pass. Without this patch the start address ends up in wrong place and the /sys/kernel/debug/sh/icache or dcache debugfs contents may not be correct. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Cc: Stuart Menefy <stuart.menefy@st.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/mm/cache-debugfs.c25
1 files changed, 5 insertions, 20 deletions
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 52411462c409..115725198038 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -26,9 +26,9 @@ static int cache_seq_show(struct seq_file *file, void *iter)
26{ 26{
27 unsigned int cache_type = (unsigned int)file->private; 27 unsigned int cache_type = (unsigned int)file->private;
28 struct cache_info *cache; 28 struct cache_info *cache;
29 unsigned int waysize, way, cache_size; 29 unsigned int waysize, way;
30 unsigned long ccr, base; 30 unsigned long ccr;
31 static unsigned long addrstart = 0; 31 unsigned long addrstart = 0;
32 32
33 /* 33 /*
34 * Go uncached immediately so we don't skew the results any 34 * Go uncached immediately so we don't skew the results any
@@ -45,28 +45,13 @@ static int cache_seq_show(struct seq_file *file, void *iter)
45 } 45 }
46 46
47 if (cache_type == CACHE_TYPE_DCACHE) { 47 if (cache_type == CACHE_TYPE_DCACHE) {
48 base = CACHE_OC_ADDRESS_ARRAY; 48 addrstart = CACHE_OC_ADDRESS_ARRAY;
49 cache = &current_cpu_data.dcache; 49 cache = &current_cpu_data.dcache;
50 } else { 50 } else {
51 base = CACHE_IC_ADDRESS_ARRAY; 51 addrstart = CACHE_IC_ADDRESS_ARRAY;
52 cache = &current_cpu_data.icache; 52 cache = &current_cpu_data.icache;
53 } 53 }
54 54
55 /*
56 * Due to the amount of data written out (depending on the cache size),
57 * we may be iterated over multiple times. In this case, keep track of
58 * the entry position in addrstart, and rewind it when we've hit the
59 * end of the cache.
60 *
61 * Likewise, the same code is used for multiple caches, so care must
62 * be taken for bouncing addrstart back and forth so the appropriate
63 * cache is hit.
64 */
65 cache_size = cache->ways * cache->sets * cache->linesz;
66 if (((addrstart & 0xff000000) != base) ||
67 (addrstart & 0x00ffffff) > cache_size)
68 addrstart = base;
69
70 waysize = cache->sets; 55 waysize = cache->sets;
71 56
72 /* 57 /*