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authorBecky Bruce <beckyb@kernel.crashing.org>2009-08-24 02:15:36 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-08-28 00:24:12 -0400
commite3e1d15855206c85f4c9ed82746e81acfe13e5aa (patch)
treea44794ac7c0e2ed11b805c61be0ff86c1d60b40c /arch
parent948c28fe3001f2c9d852dff2a0b2c69fe7cec91b (diff)
powerpc: Name xpn & x fields in HW Hash PTE format
Previously, the 36-bit code was using these bits, but they had never been named in the pte format definition. This patch just gives those fields their proper names and adds a comment that they are only present on some processors. There is no functional code change. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/mmu-hash32.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/powerpc/include/asm/mmu-hash32.h b/arch/powerpc/include/asm/mmu-hash32.h
index 382fc689f204..16f513e5cbd7 100644
--- a/arch/powerpc/include/asm/mmu-hash32.h
+++ b/arch/powerpc/include/asm/mmu-hash32.h
@@ -55,21 +55,25 @@ struct ppc_bat {
55 55
56#ifndef __ASSEMBLY__ 56#ifndef __ASSEMBLY__
57 57
58/* Hardware Page Table Entry */ 58/*
59 * Hardware Page Table Entry
60 * Note that the xpn and x bitfields are used only by processors that
61 * support extended addressing; otherwise, those bits are reserved.
62 */
59struct hash_pte { 63struct hash_pte {
60 unsigned long v:1; /* Entry is valid */ 64 unsigned long v:1; /* Entry is valid */
61 unsigned long vsid:24; /* Virtual segment identifier */ 65 unsigned long vsid:24; /* Virtual segment identifier */
62 unsigned long h:1; /* Hash algorithm indicator */ 66 unsigned long h:1; /* Hash algorithm indicator */
63 unsigned long api:6; /* Abbreviated page index */ 67 unsigned long api:6; /* Abbreviated page index */
64 unsigned long rpn:20; /* Real (physical) page number */ 68 unsigned long rpn:20; /* Real (physical) page number */
65 unsigned long :3; /* Unused */ 69 unsigned long xpn:3; /* Real page number bits 0-2, optional */
66 unsigned long r:1; /* Referenced */ 70 unsigned long r:1; /* Referenced */
67 unsigned long c:1; /* Changed */ 71 unsigned long c:1; /* Changed */
68 unsigned long w:1; /* Write-thru cache mode */ 72 unsigned long w:1; /* Write-thru cache mode */
69 unsigned long i:1; /* Cache inhibited */ 73 unsigned long i:1; /* Cache inhibited */
70 unsigned long m:1; /* Memory coherence */ 74 unsigned long m:1; /* Memory coherence */
71 unsigned long g:1; /* Guarded */ 75 unsigned long g:1; /* Guarded */
72 unsigned long :1; /* Unused */ 76 unsigned long x:1; /* Real page number bit 3, optional */
73 unsigned long pp:2; /* Page protection */ 77 unsigned long pp:2; /* Page protection */
74}; 78};
75 79