diff options
author | Ingo Molnar <mingo@elte.hu> | 2008-02-26 02:52:33 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2008-04-17 11:40:51 -0400 |
commit | d0e95ebdc5cf5fe6fa29f2e0a5c6a0fe5c5aa50f (patch) | |
tree | c07b4afb14fb557920bb6f2994e967c5fd6dab9e /arch | |
parent | 1d007cd5aeea2c9283e01433dbce4c9f91dd7823 (diff) |
x86: clean up cpu capabilities in arch/x86/kernel/cpu/intel.c
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/kernel/cpu/intel.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index c9ecf378cc41..fe9224c51d37 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c | |||
@@ -143,12 +143,12 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) | |||
143 | unsigned eax = cpuid_eax(10); | 143 | unsigned eax = cpuid_eax(10); |
144 | /* Check for version and the number of counters */ | 144 | /* Check for version and the number of counters */ |
145 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) | 145 | if ((eax & 0xff) && (((eax>>8) & 0xff) > 1)) |
146 | set_bit(X86_FEATURE_ARCH_PERFMON, c->x86_capability); | 146 | set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON); |
147 | } | 147 | } |
148 | 148 | ||
149 | /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */ | 149 | /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */ |
150 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) | 150 | if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633) |
151 | clear_bit(X86_FEATURE_SEP, c->x86_capability); | 151 | clear_cpu_cap(c, X86_FEATURE_SEP); |
152 | 152 | ||
153 | /* | 153 | /* |
154 | * Names for the Pentium II/Celeron processors | 154 | * Names for the Pentium II/Celeron processors |
@@ -209,19 +209,19 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) | |||
209 | #endif | 209 | #endif |
210 | 210 | ||
211 | if (cpu_has_xmm2) | 211 | if (cpu_has_xmm2) |
212 | set_bit(X86_FEATURE_LFENCE_RDTSC, c->x86_capability); | 212 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); |
213 | if (c->x86 == 15) { | 213 | if (c->x86 == 15) { |
214 | set_bit(X86_FEATURE_P4, c->x86_capability); | 214 | set_cpu_cap(c, X86_FEATURE_P4); |
215 | } | 215 | } |
216 | if (c->x86 == 6) | 216 | if (c->x86 == 6) |
217 | set_bit(X86_FEATURE_P3, c->x86_capability); | 217 | set_cpu_cap(c, X86_FEATURE_P3); |
218 | if (cpu_has_ds) { | 218 | if (cpu_has_ds) { |
219 | unsigned int l1; | 219 | unsigned int l1; |
220 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); | 220 | rdmsr(MSR_IA32_MISC_ENABLE, l1, l2); |
221 | if (!(l1 & (1<<11))) | 221 | if (!(l1 & (1<<11))) |
222 | set_bit(X86_FEATURE_BTS, c->x86_capability); | 222 | set_cpu_cap(c, X86_FEATURE_BTS); |
223 | if (!(l1 & (1<<12))) | 223 | if (!(l1 & (1<<12))) |
224 | set_bit(X86_FEATURE_PEBS, c->x86_capability); | 224 | set_cpu_cap(c, X86_FEATURE_PEBS); |
225 | } | 225 | } |
226 | 226 | ||
227 | if (cpu_has_bts) | 227 | if (cpu_has_bts) |