Merge branch 'tip/perf/core' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-2.6-trace into perf/core

120 files changed, 869 insertions, 962 deletions

diff --git a/arch/alpha/include/asm/cache.h b/arch/alpha/include/asm/cache.h
index f199e69a5d0b..ad368a93a46a 100644
--- a/arch/alpha/include/asm/cache.h
+++ b/arch/alpha/include/asm/cache.h
@@ -17,7 +17,6 @@
 # define L1_CACHE_SHIFT     5
 #endif
 
-#define L1_CACHE_ALIGN(x)  (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
 #define SMP_CACHE_BYTES    L1_CACHE_BYTES
 
 #endif
diff --git a/arch/alpha/kernel/err_marvel.c b/arch/alpha/kernel/err_marvel.c
index 52a79dfc13c6..5c905aaaeccd 100644
--- a/arch/alpha/kernel/err_marvel.c
+++ b/arch/alpha/kernel/err_marvel.c
@@ -109,7 +109,7 @@ marvel_print_err_cyc(u64 err_cyc)
 #define IO7__ERR_CYC__CYCLE__M  (0x7)
 
         printk("%s        Packet In Error: %s\n"
-               "%s        Error in %s, cycle %ld%s%s\n",
+               "%s        Error in %s, cycle %lld%s%s\n",
                err_print_prefix, 
                packet_desc[EXTRACT(err_cyc, IO7__ERR_CYC__PACKET)],
                err_print_prefix,
@@ -313,7 +313,7 @@ marvel_print_po7_ugbge_sym(u64 ugbge_sym)
         }
 
         printk("%s      Up Hose Garbage Symptom:\n"
-               "%s        Source Port: %ld - Dest PID: %ld - OpCode: %s\n", 
+               "%s        Source Port: %lld - Dest PID: %lld - OpCode: %s\n",
                err_print_prefix,
                err_print_prefix, 
                EXTRACT(ugbge_sym, IO7__PO7_UGBGE_SYM__UPH_SRC_PORT),
@@ -552,7 +552,7 @@ marvel_print_pox_spl_cmplt(u64 spl_cmplt)
 #define IO7__POX_SPLCMPLT__REM_BYTE_COUNT__M    (0xfff)
 
         printk("%s      Split Completion Error:\n"      
-               "%s         Source (Bus:Dev:Func): %ld:%ld:%ld\n",
+               "%s         Source (Bus:Dev:Func): %lld:%lld:%lld\n",
                err_print_prefix,
                err_print_prefix,
                EXTRACT(spl_cmplt, IO7__POX_SPLCMPLT__SOURCE_BUS),
diff --git a/arch/alpha/kernel/osf_sys.c b/arch/alpha/kernel/osf_sys.c
index fb58150a7e8f..5d1e6d6ce684 100644
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@@ -252,7 +252,7 @@ SYSCALL_DEFINE3(osf_statfs, const char __user *, pathname,
 
         retval = user_path(pathname, &path);
         if (!retval) {
-                retval = do_osf_statfs(&path buffer, bufsiz);
+                retval = do_osf_statfs(&path, buffer, bufsiz);
                 path_put(&path);
         }
         return retval;
diff --git a/arch/alpha/kernel/perf_event.c b/arch/alpha/kernel/perf_event.c
index 9bb8c024080c..a25fe9eb4739 100644
--- a/arch/alpha/kernel/perf_event.c
+++ b/arch/alpha/kernel/perf_event.c
@@ -241,20 +241,20 @@ static inline unsigned long alpha_read_pmc(int idx)
 static int alpha_perf_event_set_period(struct perf_event *event,
                                 struct hw_perf_event *hwc, int idx)
 {
-        long left = atomic64_read(&hwc->period_left);
+        long left = local64_read(&hwc->period_left);
         long period = hwc->sample_period;
         int ret = 0;
 
         if (unlikely(left <= -period)) {
                 left = period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
 
         if (unlikely(left <= 0)) {
                 left += period;
-                atomic64_set(&hwc->period_left, left);
+                local64_set(&hwc->period_left, left);
                 hwc->last_period = period;
                 ret = 1;
         }
@@ -269,7 +269,7 @@ static int alpha_perf_event_set_period(struct perf_event *event,
         if (left > (long)alpha_pmu->pmc_max_period[idx])
                 left = alpha_pmu->pmc_max_period[idx];
 
-        atomic64_set(&hwc->prev_count, (unsigned long)(-left));
+        local64_set(&hwc->prev_count, (unsigned long)(-left));
 
         alpha_write_pmc(idx, (unsigned long)(-left));
 
@@ -300,10 +300,10 @@ static unsigned long alpha_perf_event_update(struct perf_event *event,
         long delta;
 
 again:
-        prev_raw_count = atomic64_read(&hwc->prev_count);
+        prev_raw_count = local64_read(&hwc->prev_count);
         new_raw_count = alpha_read_pmc(idx);
 
-        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
                              new_raw_count) != prev_raw_count)
                 goto again;
 
@@ -316,8 +316,8 @@ again:
                 delta += alpha_pmu->pmc_max_period[idx] + 1;
         }
 
-        atomic64_add(delta, &event->count);
-        atomic64_sub(delta, &hwc->period_left);
+        local64_add(delta, &event->count);
+        local64_sub(delta, &hwc->period_left);
 
         return new_raw_count;
 }
@@ -670,7 +670,7 @@ static int __hw_perf_event_init(struct perf_event *event)
         if (!hwc->sample_period) {
                 hwc->sample_period = alpha_pmu->pmc_max_period[0];
                 hwc->last_period = hwc->sample_period;
-                atomic64_set(&hwc->period_left, hwc->sample_period);
+                local64_set(&hwc->period_left, hwc->sample_period);
         }
 
         return 0;
diff --git a/arch/alpha/kernel/proto.h b/arch/alpha/kernel/proto.h
index 3d2627ec9860..d3e52d3fd592 100644
--- a/arch/alpha/kernel/proto.h
+++ b/arch/alpha/kernel/proto.h
@@ -156,9 +156,6 @@ extern void SMC669_Init(int);
 /* es1888.c */
 extern void es1888_init(void);
 
-/* ns87312.c */
-extern void ns87312_enable_ide(long ide_base);
-
 /* ../lib/fpreg.c */
 extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
 extern unsigned long alpha_read_fp_reg (unsigned long reg);
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
index affd0f3f25df..14c8898d19ec 100644
--- a/arch/alpha/kernel/sys_cabriolet.c
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -33,7 +33,7 @@
 #include "irq_impl.h"
 #include "pci_impl.h"
 #include "machvec_impl.h"
-
+#include "pc873xx.h"
 
 /* Note mask bit is true for DISABLED irqs.  */
 static unsigned long cached_irq_mask = ~0UL;
@@ -236,17 +236,30 @@ cabriolet_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 static inline void __init
+cabriolet_enable_ide(void)
+{
+        if (pc873xx_probe() == -1) {
+                printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
+         } else {
+                printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
+                        pc873xx_get_model(), pc873xx_get_base());
+
+                pc873xx_enable_ide();
+        }
+}
+
+static inline void __init
 cabriolet_init_pci(void)
 {
         common_init_pci();
-        ns87312_enable_ide(0x398);
+        cabriolet_enable_ide();
 }
 
 static inline void __init
 cia_cab_init_pci(void)
 {
         cia_init_pci();
-        ns87312_enable_ide(0x398);
+        cabriolet_enable_ide();
 }
 
 /*
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index 230464885b5c..4da596b6adbb 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -29,7 +29,7 @@
 #include "irq_impl.h"
 #include "pci_impl.h"
 #include "machvec_impl.h"
-
+#include "pc873xx.h"
 
 /* Note mask bit is true for DISABLED irqs.  */
 static unsigned long cached_irq_mask[2] = { -1, -1 };
@@ -264,7 +264,14 @@ takara_init_pci(void)
                 alpha_mv.pci_map_irq = takara_map_irq_srm;
 
         cia_init_pci();
-        ns87312_enable_ide(0x26e);
+
+        if (pc873xx_probe() == -1) {
+                printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
+        } else {
+                printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
+                        pc873xx_get_model(), pc873xx_get_base());
+                pc873xx_enable_ide();
+        }
 }
 
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92951103255a..553b7cf17bfb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1576,95 +1576,6 @@ config AUTO_ZRELADDR
           0xf8000000. This assumes the zImage being placed in the first 128MB
           from start of memory.
 
-config ZRELADDR
-        hex "Physical address of the decompressed kernel image"
-        depends on !AUTO_ZRELADDR
-        default 0x00008000 if ARCH_BCMRING ||\
-                ARCH_CNS3XXX ||\
-                ARCH_DOVE ||\
-                ARCH_EBSA110 ||\
-                ARCH_FOOTBRIDGE ||\
-                ARCH_INTEGRATOR ||\
-                ARCH_IOP13XX ||\
-                ARCH_IOP33X ||\
-                ARCH_IXP2000 ||\
-                ARCH_IXP23XX ||\
-                ARCH_IXP4XX ||\
-                ARCH_KIRKWOOD ||\
-                ARCH_KS8695 ||\
-                ARCH_LOKI ||\
-                ARCH_MMP ||\
-                ARCH_MV78XX0 ||\
-                ARCH_NOMADIK ||\
-                ARCH_NUC93X ||\
-                ARCH_NS9XXX ||\
-                ARCH_ORION5X ||\
-                ARCH_SPEAR3XX ||\
-                ARCH_SPEAR6XX ||\
-                ARCH_U8500 ||\
-                ARCH_VERSATILE ||\
-                ARCH_W90X900
-        default 0x08008000 if ARCH_MX1 ||\
-                ARCH_SHARK
-        default 0x10008000 if ARCH_MSM ||\
-                ARCH_OMAP1 ||\
-                ARCH_RPC
-        default 0x20008000 if ARCH_S5P6440 ||\
-                ARCH_S5P6442 ||\
-                ARCH_S5PC100 ||\
-                ARCH_S5PV210
-        default 0x30008000 if ARCH_S3C2410 ||\
-                ARCH_S3C2400 ||\
-                ARCH_S3C2412 ||\
-                ARCH_S3C2416 ||\
-                ARCH_S3C2440 ||\
-                ARCH_S3C2443
-        default 0x40008000 if ARCH_STMP378X ||\
-                ARCH_STMP37XX ||\
-                ARCH_SH7372 ||\
-                ARCH_SH7377
-        default 0x50008000 if ARCH_S3C64XX ||\
-                ARCH_SH7367
-        default 0x60008000 if ARCH_VEXPRESS
-        default 0x80008000 if ARCH_MX25 ||\
-                ARCH_MX3 ||\
-                ARCH_NETX ||\
-                ARCH_OMAP2PLUS ||\
-                ARCH_PNX4008
-        default 0x90008000 if ARCH_MX5 ||\
-                ARCH_MX91231
-        default 0xa0008000 if ARCH_IOP32X ||\
-                ARCH_PXA ||\
-                MACH_MX27
-        default 0xc0008000 if ARCH_LH7A40X ||\
-                MACH_MX21
-        default 0xf0008000 if ARCH_AAEC2000 ||\
-                ARCH_L7200
-        default 0xc0028000 if ARCH_CLPS711X
-        default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
-        default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
-        default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
-        default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
-        default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
-        default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
-        default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
-        default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
-        default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
-        default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
-        default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
-        default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
-        default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
-        default 0xc0208000 if ARCH_SA1100 && SA1111
-        default 0xc0008000 if ARCH_SA1100 && !SA1111
-        default 0x30108000 if ARCH_S3C2410 && PM_H1940
-        default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
-        default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
-        help
-          ZRELADDR is the physical address where the decompressed kernel
-          image will be placed. ZRELADDR has to be specified when the
-          assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
-          selected.
-
 endmenu
 
 menu "CPU Power Management"
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index f705213caa88..4a590f4113e2 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -14,16 +14,18 @@
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
 ifneq ($(MACHINE),)
--include $(srctree)/$(MACHINE)/Makefile.boot
+include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
 # Note: the following conditions must always be true:
+#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
+ZRELADDR    := $(zreladdr-y)
 PARAMS_PHYS := $(params_phys-y)
 INITRD_PHYS := $(initrd_phys-y)
 
-export INITRD_PHYS PARAMS_PHYS
+export ZRELADDR INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
@@ -65,7 +67,7 @@ quiet_cmd_uimage = UIMAGE  $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
-$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
+$(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 68775e33476c..b23f6bc46cfa 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -79,6 +79,10 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
+# Supply ZRELADDR to the decompressor via a linker symbol.
+ifneq ($(CONFIG_AUTO_ZRELADDR),y)
+LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
+endif
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 6af9907c3b5c..6825c34646d4 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -177,7 +177,7 @@ not_angel:
                 and     r4, pc, #0xf8000000
                 add     r4, r4, #TEXT_OFFSET
 #else
-                ldr     r4, =CONFIG_ZRELADDR
+                ldr     r4, =zreladdr
 #endif
                 subs    r0, r0, r1              @ calculate the delta offset
 
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 6c0913562455..7974baacafce 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -263,6 +263,14 @@ static int it8152_pci_platform_notify_remove(struct device *dev)
         return 0;
 }
 
+int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
+{
+        dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
+                __func__, dma_addr, size);
+        return (dev->bus == &pci_bus_type) &&
+                ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
+}
+
 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 {
         it8152_io.start = IT8152_IO_BASE + 0x12000;
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 63e0c2d50f32..14c1e18c648f 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -13,6 +13,9 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_OMAP=y
 CONFIG_ARCH_OMAP4=y
+# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set
+# CONFIG_ARCH_OMAP2 is not set
+# CONFIG_ARCH_OMAP3 is not set
 # CONFIG_OMAP_MUX is not set
 CONFIG_OMAP_32K_TIMER=y
 CONFIG_OMAP_DM_TIMER=y
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index c226fe10553e..c568da7dcae4 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -288,15 +288,7 @@ extern void dmabounce_unregister_dev(struct device *);
  * DMA access and 1 if the buffer needs to be bounced.
  *
  */
-#ifdef CONFIG_SA1111
 extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
-#else
-static inline int dma_needs_bounce(struct device *dev, dma_addr_t addr,
-                                   size_t size)
-{
-        return 0;
-}
-#endif
 
 /*
  * The DMA API, implemented by dmabounce.c.  See below for descriptions.
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 48837e6d8887..b5799a3b7117 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -17,7 +17,7 @@
  * counter interrupts are regular interrupts and not an NMI. This
  * means that when we receive the interrupt we can call
  * perf_event_do_pending() that handles all of the work with
- * interrupts enabled.
+ * interrupts disabled.
  */
 static inline void
 set_perf_event_pending(void)
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index d02cfb683487..c891eb76c0e3 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -393,6 +393,9 @@
 #define __NR_perf_event_open            (__NR_SYSCALL_BASE+364)
 #define __NR_recvmmsg                   (__NR_SYSCALL_BASE+365)
 #define __NR_accept4                    (__NR_SYSCALL_BASE+366)
+#define __NR_fanotify_init              (__NR_SYSCALL_BASE+367)
+#define __NR_fanotify_mark              (__NR_SYSCALL_BASE+368)
+#define __NR_prlimit64                  (__NR_SYSCALL_BASE+369)
 
 /*
  * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index afeb71fa72cb..5c26eccef998 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -376,6 +376,9 @@
                 CALL(sys_perf_event_open)
 /* 365 */       CALL(sys_recvmmsg)
                 CALL(sys_accept4)
+                CALL(sys_fanotify_init)
+                CALL(sys_fanotify_mark)
+                CALL(sys_prlimit64)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/etm.c b/arch/arm/kernel/etm.c
index 56418f98cd01..33c7077174db 100644
--- a/arch/arm/kernel/etm.c
+++ b/arch/arm/kernel/etm.c
@@ -230,7 +230,7 @@ static void etm_dump(void)
         etb_lock(t);
 }
 
-static void sysrq_etm_dump(int key, struct tty_struct *tty)
+static void sysrq_etm_dump(int key)
 {
         dev_dbg(tracer.dev, "Dumping ETB buffer\n");
         etm_dump();
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 45d6a35217c1..ad19c276b10f 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -342,8 +342,8 @@ validate_event(struct cpu_hw_events *cpuc,
 {
         struct hw_perf_event fake_event = event->hw;
 
-        if (event->pmu && event->pmu != &pmu)
-                return 0;
+        if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
+                return 1;
 
         return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
 }
@@ -1082,8 +1082,8 @@ armv6pmu_handle_irq(int irq_num,
         /*
          * Handle the pending perf events.
          *
-         * Note: this call *must* be run with interrupts enabled. For
-         * platforms that can have the PMU interrupts raised as a PMI, this
+         * Note: this call *must* be run with interrupts disabled. For
+         * platforms that can have the PMU interrupts raised as an NMI, this
          * will not work.
          */
         perf_event_do_pending();
@@ -2058,8 +2058,8 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
         /*
          * Handle the pending perf events.
          *
-         * Note: this call *must* be run with interrupts enabled. For
-         * platforms that can have the PMU interrupts raised as a PMI, this
+         * Note: this call *must* be run with interrupts disabled. For
+         * platforms that can have the PMU interrupts raised as an NMI, this
          * will not work.
          */
         perf_event_do_pending();
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 753c0d31a3d3..c67b47f1c0fd 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -121,8 +121,8 @@ static struct clk ssc1_clk = {
         .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
         .type           = CLK_TYPE_PERIPHERAL,
 };
-static struct clk tcb_clk = {
-        .name           = "tcb_clk",
+static struct clk tcb0_clk = {
+        .name           = "tcb0_clk",
         .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
         .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -192,6 +192,14 @@ static struct clk ohci_clk = {
         .parent         = &uhphs_clk,
 };
 
+/* One additional fake clock for second TC block */
+static struct clk tcb1_clk = {
+        .name           = "tcb1_clk",
+        .pmc_mask       = 0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .parent         = &tcb0_clk,
+};
+
 static struct clk *periph_clocks[] __initdata = {
         &pioA_clk,
         &pioB_clk,
@@ -208,7 +216,7 @@ static struct clk *periph_clocks[] __initdata = {
         &spi1_clk,
         &ssc0_clk,
         &ssc1_clk,
-        &tcb_clk,
+        &tcb0_clk,
         &pwm_clk,
         &tsc_clk,
         &dma_clk,
@@ -221,6 +229,7 @@ static struct clk *periph_clocks[] __initdata = {
         &mmc1_clk,
         // irq0
         &ohci_clk,
+        &tcb1_clk,
 };
 
 /*
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 809114d5a5a6..5e71ccd5e7d3 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -46,7 +46,7 @@ static struct resource hdmac_resources[] = {
                 .end    = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
                 .flags  = IORESOURCE_MEM,
         },
-        [2] = {
+        [1] = {
                 .start  = AT91SAM9G45_ID_DMA,
                 .end    = AT91SAM9G45_ID_DMA,
                 .flags  = IORESOURCE_IRQ,
@@ -835,9 +835,9 @@ static struct platform_device at91sam9g45_tcb1_device = {
 static void __init at91_add_device_tc(void)
 {
         /* this chip has one clock and irq for all six TC channels */
-        at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
+        at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
         platform_device_register(&at91sam9g45_tcb0_device);
-        at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
+        at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
         platform_device_register(&at91sam9g45_tcb1_device);
 }
 #else
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index c4c8865d52d7..65eb0943194f 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -93,11 +93,12 @@ static struct resource dm9000_resource[] = {
                 .start  = AT91_PIN_PC11,
                 .end    = AT91_PIN_PC11,
                 .flags  = IORESOURCE_IRQ
+                        | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
         }
 };
 
 static struct dm9000_plat_data dm9000_platdata = {
-        .flags          = DM9000_PLATF_16BITONLY,
+        .flags          = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM,
 };
 
 static struct platform_device dm9000_device = {
@@ -168,17 +169,6 @@ static struct at91_udc_data __initdata ek_udc_data = {
 
 
 /*
- * MCI (SD/MMC)
- */
-static struct at91_mmc_data __initdata ek_mmc_data = {
-        .wire4          = 1,
-//      .det_pin        = ... not connected
-//      .wp_pin         = ... not connected
-//      .vcc_pin        = ... not connected
-};
-
-
-/*
  * NAND flash
  */
 static struct mtd_partition __initdata ek_nand_partition[] = {
@@ -246,6 +236,10 @@ static void __init ek_add_device_nand(void)
         at91_add_device_nand(&ek_nand_data);
 }
 
+/*
+ * SPI related devices
+ */
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
 
 /*
  * ADS7846 Touchscreen
@@ -356,6 +350,19 @@ static struct spi_board_info ek_spi_devices[] = {
 #endif
 };
 
+#else /* CONFIG_SPI_ATMEL_* */
+/* spi0 and mmc/sd share the same PIO pins: cannot be used at the same time */
+
+/*
+ * MCI (SD/MMC)
+ * det_pin, wp_pin and vcc_pin are not connected
+ */
+static struct at91_mmc_data __initdata ek_mmc_data = {
+        .wire4          = 1,
+};
+
+#endif /* CONFIG_SPI_ATMEL_* */
+
 
 /*
  * LCD Controller
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7f7da439341f..7525cee3983f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -501,7 +501,8 @@ postcore_initcall(at91_clk_debugfs_init);
 int __init clk_register(struct clk *clk)
 {
         if (clk_is_peripheral(clk)) {
-                clk->parent = &mck;
+                if (!clk->parent)
+                        clk->parent = &mck;
                 clk->mode = pmc_periph_mode;
                 list_add_tail(&clk->node, &clocks);
         }
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 8bf3cec98cfa..4566bd1c8660 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -560,4 +560,4 @@ static int __init ep93xx_clock_init(void)
         clkdev_add_table(clocks, ARRAY_SIZE(clocks));
         return 0;
 }
-arch_initcall(ep93xx_clock_init);
+postcore_initcall(ep93xx_clock_init);
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
index 91931dcb0689..4aaadc753d3e 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -215,7 +215,7 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
  * Add platform devices present on this baseboard and init
  * them from CPU side as far as required to use them later on
  */
-void __init eukrea_mbimxsd_baseboard_init(void)
+void __init eukrea_mbimxsd25_baseboard_init(void)
 {
         if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
                         ARRAY_SIZE(eukrea_mbimxsd_pads)))
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index a5f0174290b4..e064bb3d6919 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -147,8 +147,8 @@ static void __init eukrea_cpuimx25_init(void)
         if (!otg_mode_host)
                 mxc_register_device(&otg_udc_device, &otg_device_pdata);
 
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
-        eukrea_mbimxsd_baseboard_init();
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
+        eukrea_mbimxsd25_baseboard_init();
 #endif
 }
 
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index d3af0fdf8475..7a62e744a8b0 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -155,7 +155,7 @@ static unsigned long get_rate_arm(void)
 
         aad = &clk_consumer[(pdr0 >> 16) & 0xf];
         if (aad->sel)
-                fref = fref * 2 / 3;
+                fref = fref * 3 / 4;
 
         return fref / aad->arm;
 }
@@ -164,7 +164,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
 {
         unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
         struct arm_ahb_div *aad;
-        unsigned long fref = get_rate_mpll();
+        unsigned long fref = get_rate_arm();
 
         aad = &clk_consumer[(pdr0 >> 16) & 0xf];
 
@@ -176,16 +176,11 @@ static unsigned long get_rate_ipg(struct clk *clk)
         return get_rate_ahb(NULL) >> 1;
 }
 
-static unsigned long get_3_3_div(unsigned long in)
-{
-        return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
-}
-
 static unsigned long get_rate_uart(struct clk *clk)
 {
         unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
         unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
-        unsigned long div = get_3_3_div(pdr4 >> 10);
+        unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
 
         if (pdr3 & (1 << 14))
                 return get_rate_arm() / div;
@@ -216,7 +211,7 @@ static unsigned long get_rate_sdhc(struct clk *clk)
                 break;
         }
 
-        return rate / get_3_3_div(div);
+        return rate / (div + 1);
 }
 
 static unsigned long get_rate_mshc(struct clk *clk)
@@ -270,7 +265,7 @@ static unsigned long get_rate_csi(struct clk *clk)
         else
                 rate = get_rate_ppll();
 
-        return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
+        return rate / (((pdr2 >> 16) & 0x3f) + 1);
 }
 
 static unsigned long get_rate_otg(struct clk *clk)
@@ -283,25 +278,51 @@ static unsigned long get_rate_otg(struct clk *clk)
         else
                 rate = get_rate_ppll();
 
-        return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
+        return rate / (((pdr4 >> 22) & 0x3f) + 1);
 }
 
 static unsigned long get_rate_ipg_per(struct clk *clk)
 {
         unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
         unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
-        unsigned long div1, div2;
+        unsigned long div;
 
         if (pdr0 & (1 << 26)) {
-                div1 = (pdr4 >> 19) & 0x7;
-                div2 = (pdr4 >> 16) & 0x7;
-                return get_rate_arm() / ((div1 + 1) * (div2 + 1));
+                div = (pdr4 >> 16) & 0x3f;
+                return get_rate_arm() / (div + 1);
         } else {
-                div1 = (pdr0 >> 12) & 0x7;
-                return get_rate_ahb(NULL) / div1;
+                div = (pdr0 >> 12) & 0x7;
+                return get_rate_ahb(NULL) / (div + 1);
         }
 }
 
+static unsigned long get_rate_hsp(struct clk *clk)
+{
+        unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+        unsigned long fref = get_rate_mpll();
+
+        if (fref > 400 * 1000 * 1000) {
+                switch (hsp_podf) {
+                case 0:
+                        return fref >> 2;
+                case 1:
+                        return fref >> 3;
+                case 2:
+                        return fref / 3;
+                }
+        } else {
+                switch (hsp_podf) {
+                case 0:
+                case 2:
+                        return fref / 3;
+                case 1:
+                        return fref / 6;
+                }
+        }
+
+        return 0;
+}
+
 static int clk_cgr_enable(struct clk *clk)
 {
         u32 reg;
@@ -359,7 +380,7 @@ DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_ahb, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_hsp, NULL);
 DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
 DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
 DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
@@ -485,10 +506,10 @@ static struct clk_lookup lookups[] = {
 
 int __init mx35_clocks_init()
 {
-        unsigned int ll = 0;
+        unsigned int cgr2 = 3 << 26, cgr3 = 0;
 
 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
-        ll = (3 << 16);
+        cgr2 |= 3 << 16;
 #endif
 
         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
@@ -499,8 +520,20 @@ int __init mx35_clocks_init()
         __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
         __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
                         CCM_BASE + CCM_CGR1);
-        __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
-        __raw_writel(0, CCM_BASE + CCM_CGR3);
+
+        /*
+         * Check if we came up in internal boot mode. If yes, we need some
+         * extra clocks turned on, otherwise the MX35 boot ROM code will
+         * hang after a watchdog reset.
+         */
+        if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
+                /* Additionally turn on UART1, SCC, and IIM clocks */
+                cgr2 |= 3 << 16 | 3 << 4;
+                cgr3 |= 3 << 2;
+        }
+
+        __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
+        __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
 
         mxc_timer_init(&gpt_clk,
                         MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 1dc5004df866..f8f15e3ac7a0 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -216,7 +216,7 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
  * Add platform devices present on this baseboard and init
  * them from CPU side as far as required to use them later on
  */
-void __init eukrea_mbimxsd_baseboard_init(void)
+void __init eukrea_mbimxsd35_baseboard_init(void)
 {
         if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
                         ARRAY_SIZE(eukrea_mbimxsd_pads)))
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 9770a6a973be..2a4f8b781ba4 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -201,8 +201,8 @@ static void __init mxc_board_init(void)
         if (!otg_mode_host)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
-        eukrea_mbimxsd_baseboard_init();
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
+        eukrea_mbimxsd35_baseboard_init();
 #endif
 }
 
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 6af69def357f..57c10a9926cc 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -56,7 +56,7 @@ static void _clk_ccgr_disable(struct clk *clk)
 {
         u32 reg;
         reg = __raw_readl(clk->enable_reg);
-        reg &= ~(MXC_CCM_CCGRx_MOD_OFF << clk->enable_shift);
+        reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
         __raw_writel(reg, clk->enable_reg);
 
 }
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 63b2d8859c3c..88d3a1e920f5 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_LOCAL_TIMERS)		+= timer-mpu.o
 obj-$(CONFIG_HOTPLUG_CPU)               += omap-hotplug.o
 obj-$(CONFIG_ARCH_OMAP4)                += omap44xx-smc.o omap4-common.o
 
+AFLAGS_omap-headsmp.o                   :=-Wa,-march=armv7-a
 AFLAGS_omap44xx-smc.o                   :=-Wa,-march=armv7-a
 
 # Functions loaded to SRAM
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 138646deac89..dfdce2d82779 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3417,7 +3417,13 @@ int __init omap3xxx_clk_init(void)
         struct omap_clk *c;
         u32 cpu_clkflg = CK_3XXX;
 
-        if (cpu_is_omap34xx()) {
+        if (cpu_is_omap3517()) {
+                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
+                cpu_clkflg |= CK_3517;
+        } else if (cpu_is_omap3505()) {
+                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
+                cpu_clkflg |= CK_3505;
+        } else if (cpu_is_omap34xx()) {
                 cpu_mask = RATE_IN_3XXX;
                 cpu_clkflg |= CK_343X;
 
@@ -3432,12 +3438,6 @@ int __init omap3xxx_clk_init(void)
                         cpu_mask |= RATE_IN_3430ES2PLUS;
                         cpu_clkflg |= CK_3430ES2;
                 }
-        } else if (cpu_is_omap3517()) {
-                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
-                cpu_clkflg |= CK_3517;
-        } else if (cpu_is_omap3505()) {
-                cpu_mask = RATE_IN_3XXX | RATE_IN_3430ES2PLUS;
-                cpu_clkflg |= CK_3505;
         }
 
         if (omap3_has_192mhz_clk())
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index e8256a2ed8e7..9a879f959509 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -284,8 +284,8 @@ static void __init omap3_check_revision(void)
                 default:
                         omap_revision =  OMAP3630_REV_ES1_2;
                         omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
-                        break;
                 }
+                break;
         default:
                 /* Unknown default to latest silicon rev as default*/
                 omap_revision =  OMAP3630_REV_ES1_2;
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 50fd74916643..06e64e1fc28a 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -177,7 +177,10 @@ omap_irq_base:	.word	0
                 cmpne   \irqnr, \tmp
                 cmpcs   \irqnr, \irqnr
                 .endm
+#endif
+#endif  /* MULTI_OMAP2 */
 
+#ifdef CONFIG_SMP
                 /* We assume that irqstat (the raw value of the IRQ acknowledge
                  * register) is preserved from the macro above.
                  * If there is an IPI, we immediately signal end of interrupt
@@ -205,8 +208,7 @@ omap_irq_base:	.word	0
                 streq   \irqstat, [\base, #GIC_CPU_EOI]
                 cmp     \tmp, #0
                 .endm
-#endif
-#endif  /* MULTI_OMAP2 */
+#endif  /* CONFIG_SMP */
 
                 .macro  irq_prio_table
                 .endm
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index af3c20c8d3f9..9e9f70e18e3c 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -102,8 +102,7 @@ static void __init wakeup_secondary(void)
          * Send a 'sev' to wake the secondary core from WFE.
          * Drain the outstanding writes to memory
          */
-        dsb();
-        set_event();
+        dsb_sev();
         mb();
 }
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index fb4994ad622e..7b03426c72a3 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -480,7 +480,9 @@ void omap_sram_idle(void)
         }
 
         /* Disable IO-PAD and IO-CHAIN wakeup */
-        if (omap3_has_io_wakeup() && core_next_state < PWRDM_POWER_ON) {
+        if (omap3_has_io_wakeup() &&
+            (per_next_state < PWRDM_POWER_ON ||
+             core_next_state < PWRDM_POWER_ON)) {
                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
                 omap3_disable_io_chain();
         }
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 268a9bc6be8a..50d5939a78f1 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -398,7 +398,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
         return 0;
 }
 
-static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
+static int pxa_cpufreq_init(struct cpufreq_policy *policy)
 {
         int i;
         unsigned int freq;
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
index 27fa329d9a8b..0a0d0fe99220 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c
@@ -204,7 +204,7 @@ static int pxa3xx_cpufreq_set(struct cpufreq_policy *policy,
         return 0;
 }
 
-static __init int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
+static int pxa3xx_cpufreq_init(struct cpufreq_policy *policy)
 {
         int ret = -EINVAL;
 
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
index 7139e0dc26d1..4e1287070d21 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h
@@ -71,10 +71,10 @@
 #define GPIO46_CI_DD_7          MFP_CFG_DRV(GPIO46, AF0, DS04X)
 #define GPIO47_CI_DD_8          MFP_CFG_DRV(GPIO47, AF1, DS04X)
 #define GPIO48_CI_DD_9          MFP_CFG_DRV(GPIO48, AF1, DS04X)
-#define GPIO52_CI_HSYNC         MFP_CFG_DRV(GPIO52, AF0, DS04X)
-#define GPIO51_CI_VSYNC         MFP_CFG_DRV(GPIO51, AF0, DS04X)
 #define GPIO49_CI_MCLK          MFP_CFG_DRV(GPIO49, AF0, DS04X)
 #define GPIO50_CI_PCLK          MFP_CFG_DRV(GPIO50, AF0, DS04X)
+#define GPIO51_CI_HSYNC         MFP_CFG_DRV(GPIO51, AF0, DS04X)
+#define GPIO52_CI_VSYNC         MFP_CFG_DRV(GPIO52, AF0, DS04X)
 
 /* KEYPAD */
 #define GPIO3_KP_DKIN_6         MFP_CFG_LPM(GPIO3,   AF2, FLOAT)
diff --git a/arch/arm/mach-s3c2410/include/mach/vmalloc.h b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
index 315b0078a34d..54297eb0bf5e 100644
--- a/arch/arm/mach-s3c2410/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c2410/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END     0xE0000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
index 7411ef3711a6..bc0e91389864 100644
--- a/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c64xx/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END     0xE0000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6440/include/mach/vmalloc.h b/arch/arm/mach-s5p6440/include/mach/vmalloc.h
index 16df257b1dce..e3f0eebf5205 100644
--- a/arch/arm/mach-s5p6440/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p6440/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END     0xE0000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
index be3333688c20..f5c83f02c18e 100644
--- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END     0xE0000000UL
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/vmalloc.h b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
index 58f515e0747e..df9a28808323 100644
--- a/arch/arm/mach-s5pv210/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv210/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H __FILE__
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END     (0xE0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
index 77f2b4d85e6b..26a0f03df8ea 100644
--- a/arch/arm/mach-s5pv310/clock.c
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -30,6 +30,16 @@ static struct clk clk_sclk_hdmi27m = {
         .rate           = 27000000,
 };
 
+static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
+}
+
 /* Core list of CMU_CPU side */
 
 static struct clksrc_clk clk_mout_apll = {
@@ -39,6 +49,14 @@ static struct clksrc_clk clk_mout_apll = {
         },
         .sources        = &clk_src_apll,
         .reg_src        = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_apll = {
+        .clk    = {
+                .name           = "sclk_apll",
+                .id             = -1,
+                .parent         = &clk_mout_apll.clk,
+        },
         .reg_div        = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
 };
 
@@ -61,7 +79,7 @@ static struct clksrc_clk clk_mout_mpll = {
 };
 
 static struct clk *clkset_moutcore_list[] = {
-        [0] = &clk_mout_apll.clk,
+        [0] = &clk_sclk_apll.clk,
         [1] = &clk_mout_mpll.clk,
 };
 
@@ -154,7 +172,7 @@ static struct clksrc_clk clk_pclk_dbg = {
 
 static struct clk *clkset_corebus_list[] = {
         [0] = &clk_mout_mpll.clk,
-        [1] = &clk_mout_apll.clk,
+        [1] = &clk_sclk_apll.clk,
 };
 
 static struct clksrc_sources clkset_mout_corebus = {
@@ -220,7 +238,7 @@ static struct clksrc_clk clk_pclk_acp = {
 
 static struct clk *clkset_aclk_top_list[] = {
         [0] = &clk_mout_mpll.clk,
-        [1] = &clk_mout_apll.clk,
+        [1] = &clk_sclk_apll.clk,
 };
 
 static struct clksrc_sources clkset_aclk_200 = {
@@ -321,11 +339,6 @@ static struct clksrc_clk clk_sclk_vpll = {
         .reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
 };
 
-static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
-}
-
 static struct clk init_clocks_disable[] = {
         {
                 .name           = "timers",
@@ -337,7 +350,37 @@ static struct clk init_clocks_disable[] = {
 };
 
 static struct clk init_clocks[] = {
-        /* Nothing here yet */
+        {
+                .name           = "uart",
+                .id             = 0,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 0),
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 1),
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 2),
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 3),
+        }, {
+                .name           = "uart",
+                .id             = 4,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 4),
+        }, {
+                .name           = "uart",
+                .id             = 5,
+                .enable         = s5pv310_clk_ip_peril_ctrl,
+                .ctrlbit        = (1 << 5),
+        }
 };
 
 static struct clk *clkset_group_list[] = {
@@ -359,8 +402,8 @@ static struct clksrc_clk clksrcs[] = {
                 .clk    = {
                         .name           = "uclk1",
                         .id             = 0,
+                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 0),
-                        .enable         = s5pv310_clk_ip_peril_ctrl,
                 },
                 .sources = &clkset_group,
                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
@@ -369,8 +412,8 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "uclk1",
                         .id             = 1,
-                        .enable         = s5pv310_clk_ip_peril_ctrl,
-                        .ctrlbit        = (1 << 1),
+                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .ctrlbit        = (1 << 4),
                 },
                 .sources = &clkset_group,
                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
@@ -379,8 +422,8 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "uclk1",
                         .id             = 2,
-                        .enable         = s5pv310_clk_ip_peril_ctrl,
-                        .ctrlbit        = (1 << 2),
+                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .ctrlbit        = (1 << 8),
                 },
                 .sources = &clkset_group,
                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
@@ -389,8 +432,8 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "uclk1",
                         .id             = 3,
-                        .enable         = s5pv310_clk_ip_peril_ctrl,
-                        .ctrlbit        = (1 << 3),
+                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
+                        .ctrlbit        = (1 << 12),
                 },
                 .sources = &clkset_group,
                 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
@@ -399,7 +442,7 @@ static struct clksrc_clk clksrcs[] = {
                 .clk            = {
                         .name           = "sclk_pwm",
                         .id             = -1,
-                        .enable         = s5pv310_clk_ip_peril_ctrl,
+                        .enable         = s5pv310_clksrc_mask_peril0_ctrl,
                         .ctrlbit        = (1 << 24),
                 },
                 .sources = &clkset_group,
@@ -411,6 +454,7 @@ static struct clksrc_clk clksrcs[] = {
 /* Clock initialization code */
 static struct clksrc_clk *sysclks[] = {
         &clk_mout_apll,
+        &clk_sclk_apll,
         &clk_mout_epll,
         &clk_mout_mpll,
         &clk_moutcore,
@@ -470,11 +514,11 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
-                                __raw_readl(S5P_EPLL_CON1), pll_4500);
+                                __raw_readl(S5P_EPLL_CON1), pll_4600);
 
         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
         vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
-                                __raw_readl(S5P_VPLL_CON1), pll_4502);
+                                __raw_readl(S5P_VPLL_CON1), pll_4650);
 
         clk_fout_apll.rate = apll;
         clk_fout_mpll.rate = mpll;
diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
index 196c9f12ed85..e5b261a99ab2 100644
--- a/arch/arm/mach-s5pv310/cpu.c
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -45,6 +45,16 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
                 .pfn            = __phys_to_pfn(S5PV310_PA_L2CC),
                 .length         = SZ_4K,
                 .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_SYSRAM,
+                .pfn            = __phys_to_pfn(S5PV310_PA_SYSRAM),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5P_VA_CMU,
+                .pfn            = __phys_to_pfn(S5PV310_PA_CMU),
+                .length         = SZ_128K,
+                .type           = MT_DEVICE,
         },
 };
 
diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
index 56885ca3773c..4cdedda6e652 100644
--- a/arch/arm/mach-s5pv310/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -15,12 +15,14 @@
 
 #include <plat/irqs.h>
 
-/* Private Peripheral Interrupt */
+/* PPI: Private Peripheral Interrupt */
+
 #define IRQ_PPI(x)              S5P_IRQ(x+16)
 
 #define IRQ_LOCALTIMER          IRQ_PPI(13)
 
-/* Shared Peripheral Interrupt */
+/* SPI: Shared Peripheral Interrupt */
+
 #define IRQ_SPI(x)              S5P_IRQ(x+32)
 
 #define IRQ_EINT0               IRQ_SPI(40)
@@ -36,7 +38,7 @@
 #define IRQ_PCIE                IRQ_SPI(50)
 #define IRQ_SYSTEM_TIMER        IRQ_SPI(51)
 #define IRQ_MFC                 IRQ_SPI(52)
-#define IRQ_WTD                 IRQ_SPI(53)
+#define IRQ_WDT                 IRQ_SPI(53)
 #define IRQ_AUDIO_SS            IRQ_SPI(54)
 #define IRQ_AC97                IRQ_SPI(55)
 #define IRQ_SPDIF               IRQ_SPI(56)
@@ -67,8 +69,9 @@
 #define IRQ_IIC                 COMBINER_IRQ(27, 0)
 
 /* Set the default NR_IRQS */
+
 #define NR_IRQS                 COMBINER_IRQ(MAX_COMBINER_NR, 0)
 
 #define MAX_COMBINER_NR         39
 
-#endif /* ASM_ARCH_IRQS_H */
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 87697c9fca5b..213e1101a3b3 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -23,12 +23,16 @@
 
 #include <plat/map-s5p.h>
 
+#define S5PV310_PA_SYSRAM               (0x02025000)
+
 #define S5PV310_PA_CHIPID               (0x10000000)
 #define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
 
 #define S5PV310_PA_SYSCON               (0x10020000)
 #define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
 
+#define S5PV310_PA_CMU                  (0x10030000)
+
 #define S5PV310_PA_WATCHDOG             (0x10060000)
 
 #define S5PV310_PA_COMBINER             (0x10448000)
@@ -39,8 +43,12 @@
 #define S5PV310_PA_GIC_DIST             (0x10501000)
 #define S5PV310_PA_L2CC                 (0x10502000)
 
-#define S5PV310_PA_GPIO                 (0x11000000)
-#define S5P_PA_GPIO                     S5PV310_PA_GPIO
+#define S5PV310_PA_GPIO1                (0x11400000)
+#define S5PV310_PA_GPIO2                (0x11000000)
+#define S5PV310_PA_GPIO3                (0x03860000)
+#define S5P_PA_GPIO                     S5PV310_PA_GPIO1
+
+#define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
 
 #define S5PV310_PA_UART                 (0x13800000)
 
@@ -63,6 +71,10 @@
 
 /* compatibiltiy defines. */
 #define S3C_PA_UART                     S5PV310_PA_UART
+#define S3C_PA_HSMMC0                   S5PV310_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                   S5PV310_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                   S5PV310_PA_HSMMC(2)
+#define S3C_PA_HSMMC3                   S5PV310_PA_HSMMC(3)
 #define S3C_PA_IIC                      S5PV310_PA_IIC0
 #define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
 
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
index 59e3a7e94d80..4013553cd9be 100644
--- a/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -15,48 +15,49 @@
 
 #include <mach/map.h>
 
-#define S5P_CLKREG(x)                   (S3C_VA_SYS + (x))
+#define S5P_CLKREG(x)                   (S5P_VA_CMU + (x))
 
 #define S5P_INFORM0                     S5P_CLKREG(0x800)
 
-#define S5P_EPLL_CON0                   S5P_CLKREG(0x1C110)
-#define S5P_EPLL_CON1                   S5P_CLKREG(0x1C114)
-#define S5P_VPLL_CON0                   S5P_CLKREG(0x1C120)
-#define S5P_VPLL_CON1                   S5P_CLKREG(0x1C124)
+#define S5P_EPLL_CON0                   S5P_CLKREG(0x0C110)
+#define S5P_EPLL_CON1                   S5P_CLKREG(0x0C114)
+#define S5P_VPLL_CON0                   S5P_CLKREG(0x0C120)
+#define S5P_VPLL_CON1                   S5P_CLKREG(0x0C124)
 
-#define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x1C210)
-#define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x1C214)
+#define S5P_CLKSRC_TOP0                 S5P_CLKREG(0x0C210)
+#define S5P_CLKSRC_TOP1                 S5P_CLKREG(0x0C214)
 
-#define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x1C250)
+#define S5P_CLKSRC_PERIL0               S5P_CLKREG(0x0C250)
 
-#define S5P_CLKDIV_TOP                  S5P_CLKREG(0x1C510)
+#define S5P_CLKDIV_TOP                  S5P_CLKREG(0x0C510)
 
-#define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x1C550)
-#define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x1C554)
-#define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x1C558)
-#define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x1C55C)
-#define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x1C560)
-#define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x1C564)
+#define S5P_CLKDIV_PERIL0               S5P_CLKREG(0x0C550)
+#define S5P_CLKDIV_PERIL1               S5P_CLKREG(0x0C554)
+#define S5P_CLKDIV_PERIL2               S5P_CLKREG(0x0C558)
+#define S5P_CLKDIV_PERIL3               S5P_CLKREG(0x0C55C)
+#define S5P_CLKDIV_PERIL4               S5P_CLKREG(0x0C560)
+#define S5P_CLKDIV_PERIL5               S5P_CLKREG(0x0C564)
 
-#define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x1C950)
+#define S5P_CLKSRC_MASK_PERIL0          S5P_CLKREG(0x0C350)
 
-#define S5P_CLKSRC_CORE                 S5P_CLKREG(0x20200)
+#define S5P_CLKGATE_IP_PERIL            S5P_CLKREG(0x0C950)
 
-#define S5P_CLKDIV_CORE0                S5P_CLKREG(0x20500)
+#define S5P_CLKSRC_CORE                 S5P_CLKREG(0x10200)
+#define S5P_CLKDIV_CORE0                S5P_CLKREG(0x10500)
 
-#define S5P_APLL_LOCK                   S5P_CLKREG(0x24000)
-#define S5P_MPLL_LOCK                   S5P_CLKREG(0x24004)
-#define S5P_APLL_CON0                   S5P_CLKREG(0x24100)
-#define S5P_APLL_CON1                   S5P_CLKREG(0x24104)
-#define S5P_MPLL_CON0                   S5P_CLKREG(0x24108)
-#define S5P_MPLL_CON1                   S5P_CLKREG(0x2410C)
+#define S5P_APLL_LOCK                   S5P_CLKREG(0x14000)
+#define S5P_MPLL_LOCK                   S5P_CLKREG(0x14004)
+#define S5P_APLL_CON0                   S5P_CLKREG(0x14100)
+#define S5P_APLL_CON1                   S5P_CLKREG(0x14104)
+#define S5P_MPLL_CON0                   S5P_CLKREG(0x14108)
+#define S5P_MPLL_CON1                   S5P_CLKREG(0x1410C)
 
-#define S5P_CLKSRC_CPU                  S5P_CLKREG(0x24200)
-#define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x24400)
+#define S5P_CLKSRC_CPU                  S5P_CLKREG(0x14200)
+#define S5P_CLKMUX_STATCPU              S5P_CLKREG(0x14400)
 
-#define S5P_CLKDIV_CPU                  S5P_CLKREG(0x24500)
-#define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x24600)
+#define S5P_CLKDIV_CPU                  S5P_CLKREG(0x14500)
+#define S5P_CLKDIV_STATCPU              S5P_CLKREG(0x14600)
 
-#define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x24800)
+#define S5P_CLKGATE_SCLKCPU             S5P_CLKREG(0x14800)
 
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
index 3f565ebb7daa..256f221edf3a 100644
--- a/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
@@ -17,6 +17,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H __FILE__
 
-#define VMALLOC_END       (0xF0000000)
+#define VMALLOC_END     (0xF0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
index fe9469abd006..d357c198edee 100644
--- a/arch/arm/mach-s5pv310/platsmp.c
+++ b/arch/arm/mach-s5pv310/platsmp.c
@@ -187,6 +187,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
                  * until it receives a soft interrupt, and then the
                  * secondary CPU branches to this address.
                  */
-        __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0);
+        __raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
         }
 }
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 5e16b4c69222..ae416fe7daf2 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common objects
-obj-y                           := timer.o console.o clock.o
+obj-y                           := timer.o console.o clock.o pm_runtime.o
 
 # CPU objects
 obj-$(CONFIG_ARCH_SH7367)       += setup-sh7367.o clock-sh7367.o intc-sh7367.o
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 23d472f9525e..95935c83c306 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -25,6 +25,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <linux/mmc/host.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
@@ -39,6 +40,7 @@
 #include <linux/sh_clk.h>
 #include <linux/gpio.h>
 #include <linux/input.h>
+#include <linux/leds.h>
 #include <linux/input/sh_keysc.h>
 #include <linux/usb/r8a66597.h>
 
@@ -307,6 +309,7 @@ static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
         .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
         .tmio_ocr_mask  = MMC_VDD_165_195,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
 };
 
 static struct resource sdhi1_resources[] = {
@@ -558,7 +561,7 @@ static struct resource fsi_resources[] = {
 
 static struct platform_device fsi_device = {
         .name           = "sh_fsi2",
-        .id             = 0,
+        .id             = -1,
         .num_resources  = ARRAY_SIZE(fsi_resources),
         .resource       = fsi_resources,
         .dev    = {
@@ -650,7 +653,44 @@ static struct platform_device hdmi_device = {
         },
 };
 
+static struct gpio_led ap4evb_leds[] = {
+        {
+                .name                   = "led4",
+                .gpio                   = GPIO_PORT185,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name                   = "led2",
+                .gpio                   = GPIO_PORT186,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name                   = "led3",
+                .gpio                   = GPIO_PORT187,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        },
+        {
+                .name                   = "led1",
+                .gpio                   = GPIO_PORT188,
+                .default_state  = LEDS_GPIO_DEFSTATE_ON,
+        }
+};
+
+static struct gpio_led_platform_data ap4evb_leds_pdata = {
+        .num_leds = ARRAY_SIZE(ap4evb_leds),
+        .leds = ap4evb_leds,
+};
+
+static struct platform_device leds_device = {
+        .name = "leds-gpio",
+        .id = 0,
+        .dev = {
+                .platform_data  = &ap4evb_leds_pdata,
+        },
+};
+
 static struct platform_device *ap4evb_devices[] __initdata = {
+        &leds_device,
         &nor_flash_device,
         &smc911x_device,
         &sdhi0_device,
@@ -840,20 +880,6 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_CS5A,      NULL);
         gpio_request(GPIO_FN_IRQ6_39,   NULL);
 
-        /* enable LED 1 - 4 */
-        gpio_request(GPIO_PORT185, NULL);
-        gpio_request(GPIO_PORT186, NULL);
-        gpio_request(GPIO_PORT187, NULL);
-        gpio_request(GPIO_PORT188, NULL);
-        gpio_direction_output(GPIO_PORT185, 1);
-        gpio_direction_output(GPIO_PORT186, 1);
-        gpio_direction_output(GPIO_PORT187, 1);
-        gpio_direction_output(GPIO_PORT188, 1);
-        gpio_export(GPIO_PORT185, 0);
-        gpio_export(GPIO_PORT186, 0);
-        gpio_export(GPIO_PORT187, 0);
-        gpio_export(GPIO_PORT188, 0);
-
         /* enable Debug switch (S6) */
         gpio_request(GPIO_PORT32, NULL);
         gpio_request(GPIO_PORT33, NULL);
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index fb4e9b1d788e..759468992ad2 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -286,7 +286,6 @@ static struct clk_ops pllc2_clk_ops = {
 
 struct clk pllc2_clk = {
         .ops            = &pllc2_clk_ops,
-        .flags          = CLK_ENABLE_ON_INIT,
         .parent         = &extal1_div2_clk,
         .freq_table     = pllc2_freq_table,
         .parent_table   = pllc2_parent,
@@ -395,7 +394,7 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
 
 enum { MSTP001,
        MSTP131, MSTP130,
-       MSTP129, MSTP128,
+       MSTP129, MSTP128, MSTP127, MSTP126,
        MSTP118, MSTP117, MSTP116,
        MSTP106, MSTP101, MSTP100,
        MSTP223,
@@ -413,6 +412,8 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
         [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
         [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
+        [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
+        [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
         [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
         [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
@@ -428,7 +429,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
         [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
-        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, CLK_ENABLE_ON_INIT), /* FSIA */
+        [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */
         [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
         [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
         [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -498,6 +499,8 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
         CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
         CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
+        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
+        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
         CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index b7c705a213a2..6b7c7c42bc8f 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -1,8 +1,10 @@
 /*
- * SH-Mobile Timer
+ * SH-Mobile Clock Framework
  *
  * Copyright (C) 2010  Magnus Damm
  *
+ * Used together with arch/arm/common/clkdev.c and drivers/sh/clk.c.
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; version 2 of the License.
diff --git a/arch/arm/mach-shmobile/pm_runtime.c b/arch/arm/mach-shmobile/pm_runtime.c
new file mode 100644
index 000000000000..94912d3944d3
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm_runtime.c
@@ -0,0 +1,169 @@
+/*
+ * arch/arm/mach-shmobile/pm_runtime.c
+ *
+ * Runtime PM support code for SuperH Mobile ARM
+ *
+ *  Copyright (C) 2009-2010 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/sh_clk.h>
+#include <linux/bitmap.h>
+
+#ifdef CONFIG_PM_RUNTIME
+#define BIT_ONCE 0
+#define BIT_ACTIVE 1
+#define BIT_CLK_ENABLED 2
+
+struct pm_runtime_data {
+        unsigned long flags;
+        struct clk *clk;
+};
+
+static void __devres_release(struct device *dev, void *res)
+{
+        struct pm_runtime_data *prd = res;
+
+        dev_dbg(dev, "__devres_release()\n");
+
+        if (test_bit(BIT_CLK_ENABLED, &prd->flags))
+                clk_disable(prd->clk);
+
+        if (test_bit(BIT_ACTIVE, &prd->flags))
+                clk_put(prd->clk);
+}
+
+static struct pm_runtime_data *__to_prd(struct device *dev)
+{
+        return devres_find(dev, __devres_release, NULL, NULL);
+}
+
+static void platform_pm_runtime_init(struct device *dev,
+                                     struct pm_runtime_data *prd)
+{
+        if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags)) {
+                prd->clk = clk_get(dev, NULL);
+                if (!IS_ERR(prd->clk)) {
+                        set_bit(BIT_ACTIVE, &prd->flags);
+                        dev_info(dev, "clocks managed by runtime pm\n");
+                }
+        }
+}
+
+static void platform_pm_runtime_bug(struct device *dev,
+                                    struct pm_runtime_data *prd)
+{
+        if (prd && !test_and_set_bit(BIT_ONCE, &prd->flags))
+                dev_err(dev, "runtime pm suspend before resume\n");
+}
+
+int platform_pm_runtime_suspend(struct device *dev)
+{
+        struct pm_runtime_data *prd = __to_prd(dev);
+
+        dev_dbg(dev, "platform_pm_runtime_suspend()\n");
+
+        platform_pm_runtime_bug(dev, prd);
+
+        if (prd && test_bit(BIT_ACTIVE, &prd->flags)) {
+                clk_disable(prd->clk);
+                clear_bit(BIT_CLK_ENABLED, &prd->flags);
+        }
+
+        return 0;
+}
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+        struct pm_runtime_data *prd = __to_prd(dev);
+
+        dev_dbg(dev, "platform_pm_runtime_resume()\n");
+
+        platform_pm_runtime_init(dev, prd);
+
+        if (prd && test_bit(BIT_ACTIVE, &prd->flags)) {
+                clk_enable(prd->clk);
+                set_bit(BIT_CLK_ENABLED, &prd->flags);
+        }
+
+        return 0;
+}
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+        /* suspend synchronously to disable clocks immediately */
+        return pm_runtime_suspend(dev);
+}
+
+static int platform_bus_notify(struct notifier_block *nb,
+                               unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct pm_runtime_data *prd;
+
+        dev_dbg(dev, "platform_bus_notify() %ld !\n", action);
+
+        if (action == BUS_NOTIFY_BIND_DRIVER) {
+                prd = devres_alloc(__devres_release, sizeof(*prd), GFP_KERNEL);
+                if (prd)
+                        devres_add(dev, prd);
+                else
+                        dev_err(dev, "unable to alloc memory for runtime pm\n");
+        }
+
+        return 0;
+}
+
+#else /* CONFIG_PM_RUNTIME */
+
+static int platform_bus_notify(struct notifier_block *nb,
+                               unsigned long action, void *data)
+{
+        struct device *dev = data;
+        struct clk *clk;
+
+        dev_dbg(dev, "platform_bus_notify() %ld !\n", action);
+
+        switch (action) {
+        case BUS_NOTIFY_BIND_DRIVER:
+                clk = clk_get(dev, NULL);
+                if (!IS_ERR(clk)) {
+                        clk_enable(clk);
+                        clk_put(clk);
+                        dev_info(dev, "runtime pm disabled, clock forced on\n");
+                }
+                break;
+        case BUS_NOTIFY_UNBOUND_DRIVER:
+                clk = clk_get(dev, NULL);
+                if (!IS_ERR(clk)) {
+                        clk_disable(clk);
+                        clk_put(clk);
+                        dev_info(dev, "runtime pm disabled, clock forced off\n");
+                }
+                break;
+        }
+
+        return 0;
+}
+
+#endif /* CONFIG_PM_RUNTIME */
+
+static struct notifier_block platform_bus_notifier = {
+        .notifier_call = platform_bus_notify
+};
+
+static int __init sh_pm_runtime_init(void)
+{
+        bus_register_notifier(&platform_bus_type, &platform_bus_notifier);
+        return 0;
+}
+core_initcall(sh_pm_runtime_init);
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 05e78dd9b50c..9e305de56be9 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -91,10 +91,8 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc,
 {
         mi->nr_banks = 2;
         mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
         mi->bank[0].size = 448 * SZ_1M;
         mi->bank[1].start = SZ_512M;
-        mi->bank[1].node = PHYS_TO_NID(SZ_512M);
         mi->bank[1].size = SZ_512M;
 }
 
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
index 267a141730d9..fd6aa65b2dc6 100644
--- a/arch/arm/mach-tegra/include/mach/vmalloc.h
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -23,6 +23,6 @@
 
 #include <asm/sizes.h>
 
-#define VMALLOC_END        0xFE000000
+#define VMALLOC_END        0xFE000000UL
 
 #endif
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 33c3f570aaa0..a0a2928ae4dd 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -398,7 +398,7 @@ config CPU_V6
 # ARMv6k
 config CPU_32v6K
         bool "Support ARM V6K processor extensions" if !SMP
-        depends on CPU_V6
+        depends on CPU_V6 || CPU_V7
         default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)
         help
           Say Y here if your ARMv6 processor supports the 'K' extension.
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index c704eed63c5d..4bc43e535d3b 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -229,6 +229,8 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
                         }
                 } while (size -= PAGE_SIZE);
 
+                dsb();
+
                 return (void *)c->vm_start;
         }
         return NULL;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 0527e65318f4..6785db4179b8 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -43,6 +43,7 @@ config ARCH_MXC91231
 config ARCH_MX5
         bool "MX5-based"
         select CPU_V7
+        select ARM_L1_CACHE_SHIFT_6
         help
           This enables support for systems based on the Freescale i.MX51 family
 
diff --git a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index 634e3f4c454d..656acb45d434 100644
--- a/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -37,9 +37,9 @@
  * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
  */
 
-extern void eukrea_mbimx25_baseboard_init(void);
+extern void eukrea_mbimxsd25_baseboard_init(void);
 extern void eukrea_mbimx27_baseboard_init(void);
-extern void eukrea_mbimx35_baseboard_init(void);
+extern void eukrea_mbimxsd35_baseboard_init(void);
 extern void eukrea_mbimx51_baseboard_init(void);
 
 #endif
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index b3da9aad4295..3703ab28257f 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -164,8 +164,9 @@ int tzic_enable_wake(int is_idle)
                 return -EAGAIN;
 
         for (i = 0; i < 4; i++) {
-                v = is_idle ? __raw_readl(TZIC_ENSET0(i)) : wakeup_intr[i];
-                __raw_writel(v, TZIC_WAKEUP0(i));
+                v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
+                        wakeup_intr[i];
+                __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
         }
 
         return 0;
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
index 6a3ff65c0303..5177a9c5a25a 100644
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ b/arch/arm/plat-omap/include/plat/smp.h
@@ -19,13 +19,6 @@
 
 #include <asm/hardware/gic.h>
 
-/*
- * set_event() is used to wake up secondary core from wfe using sev. ROM
- * code puts the second core into wfe(standby).
- *
- */
-#define set_event()     __asm__ __volatile__ ("sev" : : : "memory")
-
 /* Needed for secondary core boot */
 extern void omap_secondary_startup(void);
 extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
diff --git a/arch/arm/plat-pxa/pwm.c b/arch/arm/plat-pxa/pwm.c
index 0732c6c8d511..ef32686feef9 100644
--- a/arch/arm/plat-pxa/pwm.c
+++ b/arch/arm/plat-pxa/pwm.c
@@ -176,7 +176,7 @@ static inline void __add_pwm(struct pwm_device *pwm)
 
 static int __devinit pwm_probe(struct platform_device *pdev)
 {
-        struct platform_device_id *id = platform_get_device_id(pdev);
+        const struct platform_device_id *id = platform_get_device_id(pdev);
         struct pwm_device *pwm, *secondary = NULL;
         struct resource *r;
         int ret = 0;
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index 54e9fb9d315e..c4ff88bf6477 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -17,6 +17,7 @@
 #define S5P_VA_GPIO             S3C_ADDR(0x00500000)
 #define S5P_VA_SYSTIMER         S3C_ADDR(0x01200000)
 #define S5P_VA_SROMC            S3C_ADDR(0x01100000)
+#define S5P_VA_SYSRAM           S3C_ADDR(0x01180000)
 
 #define S5P_VA_COMBINER_BASE    S3C_ADDR(0x00600000)
 #define S5P_VA_COMBINER(x)      (S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
@@ -29,6 +30,7 @@
 #define S5P_VA_GIC_DIST         S5P_VA_COREPERI(0x1000)
 
 #define S5P_VA_L2CC             S3C_ADDR(0x00900000)
+#define S5P_VA_CMU              S3C_ADDR(0x00920000)
 
 #define S5P_VA_UART(x)          (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 #define S5P_VA_UART0            S5P_VA_UART(0)
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 48cbdcb6bbd4..55590a4d87c9 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Mon Jul 12 21:10:14 2010
+# Last update: Thu Sep 9 22:43:01 2010
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2622,7 +2622,7 @@ kraken			MACH_KRAKEN		KRAKEN			2634
 gw2388                  MACH_GW2388             GW2388                  2635
 jadecpu                 MACH_JADECPU            JADECPU                 2636
 carlisle                MACH_CARLISLE           CARLISLE                2637
-lux_sf9                 MACH_LUX_SFT9           LUX_SFT9                2638
+lux_sf9                 MACH_LUX_SF9            LUX_SF9                 2638
 nemid_tb                MACH_NEMID_TB           NEMID_TB                2639
 terrier                 MACH_TERRIER            TERRIER                 2640
 turbot                  MACH_TURBOT             TURBOT                  2641
@@ -2950,3 +2950,97 @@ davinci_dm365_dvr	MACH_DAVINCI_DM365_DVR	DAVINCI_DM365_DVR	2963
 netviz                  MACH_NETVIZ             NETVIZ                  2964
 flexibity               MACH_FLEXIBITY          FLEXIBITY               2965
 wlan_computer           MACH_WLAN_COMPUTER      WLAN_COMPUTER           2966
+lpc24xx                 MACH_LPC24XX            LPC24XX                 2967
+spica                   MACH_SPICA              SPICA                   2968
+gpsdisplay              MACH_GPSDISPLAY         GPSDISPLAY              2969
+bipnet                  MACH_BIPNET             BIPNET                  2970
+overo_ctu_inertial      MACH_OVERO_CTU_INERTIAL OVERO_CTU_INERTIAL      2971
+davinci_dm355_mmm       MACH_DAVINCI_DM355_MMM  DAVINCI_DM355_MMM       2972
+pc9260_v2               MACH_PC9260_V2          PC9260_V2               2973
+ptx7545                 MACH_PTX7545            PTX7545                 2974
+tm_efdc                 MACH_TM_EFDC            TM_EFDC                 2975
+omap3_waldo1            MACH_OMAP3_WALDO1       OMAP3_WALDO1            2977
+flyer                   MACH_FLYER              FLYER                   2978
+tornado3240             MACH_TORNADO3240        TORNADO3240             2979
+soli_01                 MACH_SOLI_01            SOLI_01                 2980
+omapl138_europalc       MACH_OMAPL138_EUROPALC  OMAPL138_EUROPALC       2981
+helios_v1               MACH_HELIOS_V1          HELIOS_V1               2982
+netspace_lite_v2        MACH_NETSPACE_LITE_V2   NETSPACE_LITE_V2        2983
+ssc                     MACH_SSC                SSC                     2984
+premierwave_en          MACH_PREMIERWAVE_EN     PREMIERWAVE_EN          2985
+wasabi                  MACH_WASABI             WASABI                  2986
+vivow                   MACH_VIVOW              VIVOW                   2987
+mx50_rdp                MACH_MX50_RDP           MX50_RDP                2988
+universal               MACH_UNIVERSAL          UNIVERSAL               2989
+real6410                MACH_REAL6410           REAL6410                2990
+spx_sakura              MACH_SPX_SAKURA         SPX_SAKURA              2991
+ij3k_2440               MACH_IJ3K_2440          IJ3K_2440               2992
+omap3_bc10              MACH_OMAP3_BC10         OMAP3_BC10              2993
+thebe                   MACH_THEBE              THEBE                   2994
+rv082                   MACH_RV082              RV082                   2995
+armlguest               MACH_ARMLGUEST          ARMLGUEST               2996
+tjinc1000               MACH_TJINC1000          TJINC1000               2997
+dockstar                MACH_DOCKSTAR           DOCKSTAR                2998
+ax8008                  MACH_AX8008             AX8008                  2999
+gnet_sgce               MACH_GNET_SGCE          GNET_SGCE               3000
+pxwnas_500_1000         MACH_PXWNAS_500_1000    PXWNAS_500_1000         3001
+ea20                    MACH_EA20               EA20                    3002
+awm2                    MACH_AWM2               AWM2                    3003
+ti8148evm               MACH_TI8148EVM          TI8148EVM               3004
+tegra_seaboard          MACH_TEGRA_SEABOARD     TEGRA_SEABOARD          3005
+linkstation_chlv2       MACH_LINKSTATION_CHLV2  LINKSTATION_CHLV2       3006
+tera_pro2_rack          MACH_TERA_PRO2_RACK     TERA_PRO2_RACK          3007
+rubys                   MACH_RUBYS              RUBYS                   3008
+aquarius                MACH_AQUARIUS           AQUARIUS                3009
+mx53_ard                MACH_MX53_ARD           MX53_ARD                3010
+mx53_smd                MACH_MX53_SMD           MX53_SMD                3011
+lswxl                   MACH_LSWXL              LSWXL                   3012
+dove_avng_v3            MACH_DOVE_AVNG_V3       DOVE_AVNG_V3            3013
+sdi_ess_9263            MACH_SDI_ESS_9263       SDI_ESS_9263            3014
+jocpu550                MACH_JOCPU550           JOCPU550                3015
+msm8x60_rumi3           MACH_MSM8X60_RUMI3      MSM8X60_RUMI3           3016
+msm8x60_ffa             MACH_MSM8X60_FFA        MSM8X60_FFA             3017
+yanomami                MACH_YANOMAMI           YANOMAMI                3018
+gta04                   MACH_GTA04              GTA04                   3019
+cm_a510                 MACH_CM_A510            CM_A510                 3020
+omap3_rfs200            MACH_OMAP3_RFS200       OMAP3_RFS200            3021
+kx33xx                  MACH_KX33XX             KX33XX                  3022
+ptx7510                 MACH_PTX7510            PTX7510                 3023
+top9000                 MACH_TOP9000            TOP9000                 3024
+teenote                 MACH_TEENOTE            TEENOTE                 3025
+ts3                     MACH_TS3                TS3                     3026
+a0                      MACH_A0                 A0                      3027
+fsm9xxx_surf            MACH_FSM9XXX_SURF       FSM9XXX_SURF            3028
+fsm9xxx_ffa             MACH_FSM9XXX_FFA        FSM9XXX_FFA             3029
+frrhwcdma60w            MACH_FRRHWCDMA60W       FRRHWCDMA60W            3030
+remus                   MACH_REMUS              REMUS                   3031
+at91cap7xdk             MACH_AT91CAP7XDK        AT91CAP7XDK             3032
+at91cap7stk             MACH_AT91CAP7STK        AT91CAP7STK             3033
+kt_sbc_sam9_1           MACH_KT_SBC_SAM9_1      KT_SBC_SAM9_1           3034
+oratisrouter            MACH_ORATISROUTER       ORATISROUTER            3035
+armada_xp_db            MACH_ARMADA_XP_DB       ARMADA_XP_DB            3036
+spdm                    MACH_SPDM               SPDM                    3037
+gtib                    MACH_GTIB               GTIB                    3038
+dgm3240                 MACH_DGM3240            DGM3240                 3039
+atlas_i_lpe             MACH_ATLAS_I_LPE        ATLAS_I_LPE             3040
+htcmega                 MACH_HTCMEGA            HTCMEGA                 3041
+tricorder               MACH_TRICORDER          TRICORDER               3042
+tx28                    MACH_TX28               TX28                    3043
+bstbrd                  MACH_BSTBRD             BSTBRD                  3044
+pwb3090                 MACH_PWB3090            PWB3090                 3045
+idea6410                MACH_IDEA6410           IDEA6410                3046
+qbc9263                 MACH_QBC9263            QBC9263                 3047
+borabora                MACH_BORABORA           BORABORA                3048
+valdez                  MACH_VALDEZ             VALDEZ                  3049
+ls9g20                  MACH_LS9G20             LS9G20                  3050
+mios_v1                 MACH_MIOS_V1            MIOS_V1                 3051
+s5pc110_crespo          MACH_S5PC110_CRESPO     S5PC110_CRESPO          3052
+controltek9g20          MACH_CONTROLTEK9G20     CONTROLTEK9G20          3053
+tin307                  MACH_TIN307             TIN307                  3054
+tin510                  MACH_TIN510             TIN510                  3055
+bluecheese              MACH_BLUECHEESE         BLUECHEESE              3057
+tem3x30                 MACH_TEM3X30            TEM3X30                 3058
+harvest_desoto          MACH_HARVEST_DESOTO     HARVEST_DESOTO          3059
+msm8x60_qrdc            MACH_MSM8X60_QRDC       MSM8X60_QRDC            3060
+spear900                MACH_SPEAR900           SPEAR900                3061
+pcontrol_g20            MACH_PCONTROL_G20       PCONTROL_G20            3062
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index 9626cf7e4251..d27600c262c2 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -115,12 +115,6 @@ struct sport_register {
 
 #endif
 
-/* Workaround defBF*.h SPORT MMRs till they get cleansed */
-#undef DTYPE_NORM
-#undef SLEN
-#undef SP_WOFF
-#undef SP_WSIZE
-
 /* SPORT_TCR1 Masks */
 #define TSPEN           0x0001  /* TX enable */
 #define ITCLK           0x0002  /* Internal TX Clock Select */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 2bc8f4f98011..037a51fd8e93 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -913,88 +913,6 @@
 #define PH6             0x0040
 #define PH7             0x0080
 
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001          /* Transmit Enable                                                              */
-#define ITCLK           0x0002          /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010          /* Transmit Bit Order                                                   */
-#define ITFS            0x0200          /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400          /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800          /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000          /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000          /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100          /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200          /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001          /* Receive Enable                                                               */
-#define IRCLK           0x0002          /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010          /* Receive Bit Order                                                    */
-#define IRFS            0x0200          /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400          /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000          /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000          /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100          /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200          /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400          /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001          /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002          /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004          /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008          /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010          /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020          /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040          /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)      ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004          /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008          /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010          /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080          /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                    */
 #define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index f392af641657..645ba5c8077b 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -145,7 +145,6 @@ static struct mtd_partition partition_info[] = {
 };
 
 static struct bf5xx_nand_platform bf5xx_nand_platform = {
-        .page_size = NFC_PG_SIZE_256,
         .data_width = NFC_NWIDTH_8,
         .partitions = partition_info,
         .nr_partitions = ARRAY_SIZE(partition_info),
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 606eb36b9d6e..c975fe88eba3 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -149,7 +149,6 @@ static struct mtd_partition partition_info[] = {
 };
 
 static struct bf5xx_nand_platform bf5xx_nand_platform = {
-        .page_size = NFC_PG_SIZE_256,
         .data_width = NFC_NWIDTH_8,
         .partitions = partition_info,
         .nr_partitions = ARRAY_SIZE(partition_info),
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index a05c967a24cf..87b41e994ba3 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -234,7 +234,6 @@ static struct mtd_partition partition_info[] = {
 };
 
 static struct bf5xx_nand_platform bf5xx_nand_platform = {
-        .page_size = NFC_PG_SIZE_256,
         .data_width = NFC_NWIDTH_8,
         .partitions = partition_info,
         .nr_partitions = ARRAY_SIZE(partition_info),
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 5f97f01fcda6..3e000756aacd 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -922,88 +922,6 @@
 #define PH14    0x4000
 #define PH15    0x8000
 
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001          /* Transmit Enable                                                              */
-#define ITCLK           0x0002          /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010          /* Transmit Bit Order                                                   */
-#define ITFS            0x0200          /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400          /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800          /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000          /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000          /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100          /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200          /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001          /* Receive Enable                                                               */
-#define IRCLK           0x0002          /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010          /* Receive Bit Order                                                    */
-#define IRFS            0x0200          /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400          /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000          /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000          /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100          /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200          /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400          /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001          /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002          /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004          /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008          /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010          /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020          /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040          /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)      ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004          /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008          /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010          /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080          /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                    */
 #define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index e9ff491c0953..04acf1ed10f9 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -509,98 +509,6 @@
 #define IREN_P  0x01
 #define UCEN_P  0x00
 
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001         /* TX enable  */
-#define ITCLK    0x0002         /* Internal TX Clock Select  */
-#define TDTYPE   0x000C         /* TX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT   0x0010         /* TX Bit Order */
-#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400         /* TX Frame Sync Required Select  */
-#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000         /* Low TX Frame Sync Select  */
-#define LATFS    0x2000         /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
-    defined(__ADSPBF533__)
-# define SLEN       0x001F      /*TX Word Length  */
-#else
-# define SLEN(x)                ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#endif
-#define TXSE        0x0100      /*TX Secondary Enable */
-#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400      /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001         /* RX enable  */
-#define IRCLK    0x0002         /* Internal RX Clock Select  */
-#define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* no companding                                                        */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT   0x0010         /* RX Bit Order */
-#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400         /* RX Frame Sync Required Select  */
-#define LRFS     0x1000         /* Low RX Frame Sync Select  */
-#define LARFS    0x2000         /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE        0x0100      /*RX Secondary Enable */
-#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400      /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001  /*RX FIFO Not Empty Status */
-#define RUVF            0x0002  /*RX Underflow Status */
-#define ROVF            0x0004  /*RX Overflow Status */
-#define TXF             0x0008  /*TX FIFO Full Status */
-#define TUVF            0x0010  /*TX Underflow Status */
-#define TOVF            0x0020  /*TX Overflow Status */
-#define TXHRE           0x0040  /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
-#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SET_SP_WOFF(x)  ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits                                                */
-#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
 /*  PPI_CONTROL Masks         */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index aad61b887373..6f56907a18c0 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1241,86 +1241,6 @@
 #define PH14    0x4000
 #define PH15    0x8000
 
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001  /* Transmit Enable                                                              */
-#define ITCLK           0x0002  /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010  /* Transmit Bit Order                                                   */
-#define ITFS            0x0200  /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400  /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800  /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000  /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000  /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000  /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100  /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200  /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400  /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001  /* Receive Enable                                                               */
-#define IRCLK           0x0002  /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010  /* Receive Bit Order                                                    */
-#define IRFS            0x0200  /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400  /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000  /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000  /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000  /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100  /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200  /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400  /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001  /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002  /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004  /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008  /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010  /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020  /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040  /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)              ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010  /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000  /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000  /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000  /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000  /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000  /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000  /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000  /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000  /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000  /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000  /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000  /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000  /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000  /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000  /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000  /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000  /* Multichannel Frame Delay = 15                                */
-
 /* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
 /* EBIU_AMGCTL Masks                                                                                                                                    */
 #define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index b674a1c4aef1..fe43062b4975 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1610,113 +1610,6 @@
 #define UCEN_P          0x00
 
 
-/* **********  SERIAL PORT MASKS  ********************** */
-/* SPORTx_TCR1 Masks */
-#define TSPEN           0x0001  /* TX enable  */
-#define ITCLK           0x0002  /* Internal TX Clock Select  */
-#define TDTYPE          0x000C  /* TX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* Data Format Normal */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law */
-#define TLSBIT          0x0010  /* TX Bit Order */
-#define ITFS            0x0200  /* Internal TX Frame Sync Select  */
-#define TFSR            0x0400  /* TX Frame Sync Required Select  */
-#define DITFS           0x0800  /* Data Independent TX Frame Sync Select  */
-#define LTFS            0x1000  /* Low TX Frame Sync Select  */
-#define LATFS           0x2000  /* Late TX Frame Sync Select  */
-#define TCKFE           0x4000  /* TX Clock Falling Edge Select */
-/* SPORTx_RCR1 Deprecated Masks                                                          */
-#define TULAW           DTYPE_ULAW              /* Compand Using u-Law */
-#define TALAW           DTYPE_ALAW                      /* Compand Using A-Law */
-
-/* SPORTx_TCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)         ((x)&0x1Fu)     /* SPORT TX Word Length (2 - 31) */
-#else
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31) */
-#endif /* _MISRA_RULES */
-#define TXSE            0x0100  /*TX Secondary Enable */
-#define TSFSE           0x0200  /*TX Stereo Frame Sync Enable */
-#define TRFST           0x0400  /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN           0x0001  /* RX enable  */
-#define IRCLK           0x0002  /* Internal RX Clock Select  */
-#define RDTYPE          0x000C  /* RX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* no companding */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law */
-#define RLSBIT          0x0010  /* RX Bit Order */
-#define IRFS            0x0200  /* Internal RX Frame Sync Select  */
-#define RFSR            0x0400  /* RX Frame Sync Required Select  */
-#define LRFS            0x1000  /* Low RX Frame Sync Select  */
-#define LARFS           0x2000  /* Late RX Frame Sync Select  */
-#define RCKFE           0x4000  /* RX Clock Falling Edge Select */
-/* SPORTx_RCR1 Deprecated Masks                                                          */
-#define RULAW           DTYPE_ULAW              /* Compand Using u-Law */
-#define RALAW           DTYPE_ALAW                      /* Compand Using A-Law */
-
-/* SPORTx_RCR2 Masks */
-#ifdef _MISRA_RULES
-#define SLEN(x)         ((x)&0x1Fu)     /* SPORT RX Word Length (2 - 31) */
-#else
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31) */
-#endif /* _MISRA_RULES */
-#define RXSE            0x0100  /*RX Secondary Enable */
-#define RSFSE           0x0200  /*RX Stereo Frame Sync Enable */
-#define RRFST           0x0400  /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001          /*RX FIFO Not Empty Status */
-#define RUVF            0x0002          /*RX Underflow Status */
-#define ROVF            0x0004          /*RX Overflow Status */
-#define TXF                     0x0008          /*TX FIFO Full Status */
-#define TUVF            0x0010          /*TX Underflow Status */
-#define TOVF            0x0020          /*TX Overflow Status */
-#define TXHRE           0x0040          /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define WOFF                    0x000003FF      /*Multichannel Window Offset Field */
-/* SPORTx_MCMC1 Macros                                                           */
-#ifdef _MISRA_RULES
-#define SET_WOFF(x)             ((x) & 0x3FFu)  /* Multichannel Window Offset Field */
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
-#define SET_WSIZE(x)    (((((x)>>0x3)-1u)&0xFu) << 0xC) /* Multichannel Window Size = (x/8)-1 */
-#else
-#define SET_WOFF(x)             ((x) & 0x3FF)   /* Multichannel Window Offset Field */
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
-#define SET_WSIZE(x)    (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1 */
-#endif /* _MISRA_RULES */
-
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x0003  /*Multichannel Clock Recovery Mode */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery) */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock */
-#define MCDTXPE         0x0004  /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x0008  /*Multichannel DMA Receive Packing */
-#define MCMEN           0x0010  /*Multichannel Frame Mode Enable */
-#define FSDR            0x0080  /*Multichannel Frame Sync to Data Relationship */
-#define MFD                     0xF000  /*Multichannel Frame Delay    */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10 */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11 */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12 */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13 */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14 */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15 */
-
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 /*  PPI_CONTROL Masks         */
 #define PORT_EN         0x0001  /* PPI Port Enable  */
diff --git a/arch/blackfin/mach-bf548/boards/cm_bf548.c b/arch/blackfin/mach-bf548/boards/cm_bf548.c
index dbb6b1d83f6d..0c38eec9ade1 100644
--- a/arch/blackfin/mach-bf548/boards/cm_bf548.c
+++ b/arch/blackfin/mach-bf548/boards/cm_bf548.c
@@ -706,7 +706,6 @@ static struct mtd_partition partition_info[] = {
 };
 
 static struct bf5xx_nand_platform bf5xx_nand_platform = {
-        .page_size = NFC_PG_SIZE_256,
         .data_width = NFC_NWIDTH_8,
         .partitions = partition_info,
         .nr_partitions = ARRAY_SIZE(partition_info),
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 6fcfb9187c35..56682a36e42d 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -849,7 +849,6 @@ static struct mtd_partition partition_info[] = {
 };
 
 static struct bf5xx_nand_platform bf5xx_nand_platform = {
-        .page_size = NFC_PG_SIZE_256,
         .data_width = NFC_NWIDTH_8,
         .partitions = partition_info,
         .nr_partitions = ARRAY_SIZE(partition_info),
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 95ff44601fd1..7866197f5485 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2221,73 +2221,6 @@
 
 #define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
 
-/* Bit masks for SPORTx_TCR1 */
-
-#define                     TCKFE  0x4000     /* Clock Falling Edge Select */
-#define                     LATFS  0x2000     /* Late Transmit Frame Sync */
-#define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
-#define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
-#define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
-#define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
-#define                    TLSBIT  0x10       /* Transmit Bit Order */
-#define                    TDTYPE  0xc        /* Data Formatting Type Select */
-#define                     ITCLK  0x2        /* Internal Transmit Clock Select */
-#define                     TSPEN  0x1        /* Transmit Enable */
-
-/* Bit masks for SPORTx_TCR2 */
-
-#define                     TRFST  0x400      /* Left/Right Order */
-#define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
-#define                      TXSE  0x100      /* TxSEC Enable */
-#define                    SLEN_T  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_RCR1 */
-
-#define                     RCKFE  0x4000     /* Clock Falling Edge Select */
-#define                     LARFS  0x2000     /* Late Receive Frame Sync */
-#define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
-#define                      RFSR  0x400      /* Receive Frame Sync Required Select */
-#define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
-#define                    RLSBIT  0x10       /* Receive Bit Order */
-#define                    RDTYPE  0xc        /* Data Formatting Type Select */
-#define                     IRCLK  0x2        /* Internal Receive Clock Select */
-#define                     RSPEN  0x1        /* Receive Enable */
-
-/* Bit masks for SPORTx_RCR2 */
-
-#define                     RRFST  0x400      /* Left/Right Order */
-#define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
-#define                      RXSE  0x100      /* RxSEC Enable */
-#define                    SLEN_R  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_STAT */
-
-#define                     TXHRE  0x40       /* Transmit Hold Register Empty */
-#define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
-#define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
-#define                       TXF  0x8        /* Transmit FIFO Full Status */
-#define                      ROVF  0x4        /* Sticky Receive Overflow Status */
-#define                      RUVF  0x2        /* Sticky Receive Underflow Status */
-#define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
-
-/* Bit masks for SPORTx_MCMC1 */
-
-#define                  SP_WSIZE  0xf000     /* Window Size */
-#define                   SP_WOFF  0x3ff      /* Windows Offset */
-
-/* Bit masks for SPORTx_MCMC2 */
-
-#define                       MFD  0xf000     /* Multi channel Frame Delay */
-#define                      FSDR  0x80       /* Frame Sync to Data Relationship */
-#define                  MCMEN  0x10       /* Multi channel Frame Mode Enable */
-#define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
-#define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
-#define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
-
-/* Bit masks for SPORTx_CHNL */
-
-#define                  CUR_CHNL  0x3ff      /* Current Channel Indicator */
-
 /* Bit masks for UARTx_LCR */
 
 #if 0
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 4c8e36b7fb33..2674f0097576 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1007,66 +1007,6 @@
 #define IREN_P  0x01
 #define UCEN_P  0x00
 
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001         /* TX enable  */
-#define ITCLK    0x0002         /* Internal TX Clock Select  */
-#define TDTYPE   0x000C         /* TX Data Formatting Select */
-#define TLSBIT   0x0010         /* TX Bit Order */
-#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400         /* TX Frame Sync Required Select  */
-#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000         /* Low TX Frame Sync Select  */
-#define LATFS    0x2000         /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN        0x001F      /*TX Word Length  */
-#define TXSE        0x0100      /*TX Secondary Enable */
-#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400      /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001         /* RX enable  */
-#define IRCLK    0x0002         /* Internal RX Clock Select  */
-#define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define RULAW    0x0008         /* u-Law enable  */
-#define RALAW    0x000C         /* A-Law enable  */
-#define RLSBIT   0x0010         /* RX Bit Order */
-#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400         /* RX Frame Sync Required Select  */
-#define LRFS     0x1000         /* Low RX Frame Sync Select  */
-#define LARFS    0x2000         /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN        0x001F      /*RX Word Length  */
-#define RXSE        0x0100      /*RX Secondary Enable */
-#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400      /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001  /*RX FIFO Not Empty Status */
-#define RUVF            0x0002  /*RX Underflow Status */
-#define ROVF            0x0004  /*RX Overflow Status */
-#define TXF             0x0008  /*TX FIFO Full Status */
-#define TUVF            0x0010  /*TX Underflow Status */
-#define TOVF            0x0020  /*TX Overflow Status */
-#define TXHRE           0x0040  /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
-#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
-
 /*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
 
 /*  PPI_CONTROL Masks         */
diff --git a/arch/h8300/include/asm/atomic.h b/arch/h8300/include/asm/atomic.h
index e936804b7508..984221abb66d 100644
--- a/arch/h8300/include/asm/atomic.h
+++ b/arch/h8300/include/asm/atomic.h
@@ -18,7 +18,8 @@
 
 static __inline__ int atomic_add_return(int i, atomic_t *v)
 {
-        int ret,flags;
+        unsigned long flags;
+        int ret;
         local_irq_save(flags);
         ret = v->counter += i;
         local_irq_restore(flags);
@@ -30,7 +31,8 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
 
 static __inline__ int atomic_sub_return(int i, atomic_t *v)
 {
-        int ret,flags;
+        unsigned long flags;
+        int ret;
         local_irq_save(flags);
         ret = v->counter -= i;
         local_irq_restore(flags);
@@ -42,7 +44,8 @@ static __inline__ int atomic_sub_return(int i, atomic_t *v)
 
 static __inline__ int atomic_inc_return(atomic_t *v)
 {
-        int ret,flags;
+        unsigned long flags;
+        int ret;
         local_irq_save(flags);
         v->counter++;
         ret = v->counter;
@@ -64,7 +67,8 @@ static __inline__ int atomic_inc_return(atomic_t *v)
 
 static __inline__ int atomic_dec_return(atomic_t *v)
 {
-        int ret,flags;
+        unsigned long flags;
+        int ret;
         local_irq_save(flags);
         --v->counter;
         ret = v->counter;
@@ -76,7 +80,8 @@ static __inline__ int atomic_dec_return(atomic_t *v)
 
 static __inline__ int atomic_dec_and_test(atomic_t *v)
 {
-        int ret,flags;
+        unsigned long flags;
+        int ret;
         local_irq_save(flags);
         --v->counter;
         ret = v->counter;
diff --git a/arch/h8300/include/asm/system.h b/arch/h8300/include/asm/system.h
index d98d97685f06..16bf1560ff68 100644
--- a/arch/h8300/include/asm/system.h
+++ b/arch/h8300/include/asm/system.h
@@ -3,6 +3,8 @@
 
 #include <linux/linkage.h>
 
+struct pt_regs;
+
 /*
  * switch_to(n) should switch tasks to task ptr, first checking that
  * ptr isn't the current task, in which case it does nothing.  This
@@ -155,6 +157,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 #define arch_align_stack(x) (x)
 
-void die(char *str, struct pt_regs *fp, unsigned long err);
+extern void die(const char *str, struct pt_regs *fp, unsigned long err);
 
 #endif /* _H8300_SYSTEM_H */
diff --git a/arch/h8300/kernel/sys_h8300.c b/arch/h8300/kernel/sys_h8300.c
index dc1ac0243b78..aaf5e5a48f93 100644
--- a/arch/h8300/kernel/sys_h8300.c
+++ b/arch/h8300/kernel/sys_h8300.c
@@ -56,8 +56,8 @@ int kernel_execve(const char *filename,
                   const char *const envp[])
 {
         register long res __asm__("er0");
-        register char *const *_c __asm__("er3") = envp;
-        register char *const *_b __asm__("er2") = argv;
+        register const char *const *_c __asm__("er3") = envp;
+        register const char *const *_b __asm__("er2") = argv;
         register const char * _a __asm__("er1") = filename;
         __asm__ __volatile__ ("mov.l %1,er0\n\t"
                         "trapa  #0\n\t"
diff --git a/arch/h8300/kernel/traps.c b/arch/h8300/kernel/traps.c
index 3c0b66bc669e..dfa05bd908b6 100644
--- a/arch/h8300/kernel/traps.c
+++ b/arch/h8300/kernel/traps.c
@@ -96,7 +96,7 @@ static void dump(struct pt_regs *fp)
         printk("\n\n");
 }
 
-void die(char *str, struct pt_regs *fp, unsigned long err)
+void die(const char *str, struct pt_regs *fp, unsigned long err)
 {
         static int diecount;
 
diff --git a/arch/ia64/hp/sim/simserial.c b/arch/ia64/hp/sim/simserial.c
index 2bef5261d96d..1e8d71ad93ef 100644
--- a/arch/ia64/hp/sim/simserial.c
+++ b/arch/ia64/hp/sim/simserial.c
@@ -149,7 +149,7 @@ static  void receive_chars(struct tty_struct *tty)
                                                 ch = ia64_ssc(0, 0, 0, 0,
                                                               SSC_GETCHAR);
                                         while (!ch);
-                                        handle_sysrq(ch, NULL);
+                                        handle_sysrq(ch);
                                 }
 #endif
                                 seen_esc = 0;
diff --git a/arch/ia64/kernel/fsys.S b/arch/ia64/kernel/fsys.S
index 3567d54f8cee..471a1e783aca 100644
--- a/arch/ia64/kernel/fsys.S
+++ b/arch/ia64/kernel/fsys.S
@@ -424,14 +424,26 @@ EX(.fail_efault, ld8 r14=[r33])			// r14 <- *set
         andcm r14=r14,r17                       // filter out SIGKILL & SIGSTOP
 
 #ifdef CONFIG_SMP
-        mov r17=1
-        ;;
-        cmpxchg4.acq r18=[r31],r17,ar.ccv       // try to acquire the lock
+        // __ticket_spin_trylock(r31)
+        ld4 r17=[r31]
         mov r8=EINVAL                   // default to EINVAL
         ;;
+        extr r9=r17,17,15
+        ;;
+        xor r18=r17,r9
+        adds r19=1,r17
+        ;;
+        extr.u r18=r18,0,15
+        ;;
+        cmp.eq p0,p7=0,r18
+(p7)    br.cond.spnt.many .lock_contention
+        mov.m ar.ccv=r17
+        ;;
+        cmpxchg4.acq r9=[r31],r19,ar.ccv
+        ;;
+        cmp4.eq p0,p7=r9,r17
+(p7)    br.cond.spnt.many .lock_contention
         ld8 r3=[r2]                     // re-read current->blocked now that we hold the lock
-        cmp4.ne p6,p0=r18,r0
-(p6)    br.cond.spnt.many .lock_contention
         ;;
 #else
         ld8 r3=[r2]                     // re-read current->blocked now that we hold the lock
@@ -490,7 +502,17 @@ EX(.fail_efault, ld8 r14=[r33])			// r14 <- *set
 (p6)    br.cond.spnt.few 1b                     // yes -> retry
 
 #ifdef CONFIG_SMP
-        st4.rel [r31]=r0                        // release the lock
+        // __ticket_spin_unlock(r31)
+        adds r31=2,r31
+        ;;
+        ld2.bias r2=[r31]
+        mov r3=65534
+        ;;
+        adds r2=2,r2
+        ;;
+        and r3=r3,r2
+        ;;
+        st2.rel [r31]=r3
 #endif
         SSM_PSR_I(p0, p9, r31)
         ;;
@@ -512,7 +534,17 @@ EX(.fail_efault, (p15) st8 [r34]=r3)
 
 .sig_pending:
 #ifdef CONFIG_SMP
-        st4.rel [r31]=r0                        // release the lock
+        // __ticket_spin_unlock(r31)
+        adds r31=2,r31
+        ;;
+        ld2.bias r2=[r31]
+        mov r3=65534
+        ;;
+        adds r2=2,r2
+        ;;
+        and r3=r3,r2
+        ;;
+        st2.rel [r31]=r3
 #endif
         SSM_PSR_I(p0, p9, r17)
         ;;
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index 60b15d0aa072..b43b36beafe3 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -340,10 +340,13 @@
 #define __NR_set_thread_area    334
 #define __NR_atomic_cmpxchg_32  335
 #define __NR_atomic_barrier     336
+#define __NR_fanotify_init      337
+#define __NR_fanotify_mark      338
+#define __NR_prlimit64          339
 
 #ifdef __KERNEL__
 
-#define NR_syscalls             337
+#define NR_syscalls             340
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index 2391bdff0996..6360c437dcf5 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -765,4 +765,7 @@ sys_call_table:
         .long sys_set_thread_area
         .long sys_atomic_cmpxchg_32     /* 335 */
         .long sys_atomic_barrier
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
 
diff --git a/arch/m68knommu/kernel/syscalltable.S b/arch/m68knommu/kernel/syscalltable.S
index b30b3eb197a5..79b1ed198c07 100644
--- a/arch/m68knommu/kernel/syscalltable.S
+++ b/arch/m68knommu/kernel/syscalltable.S
@@ -355,6 +355,9 @@ ENTRY(sys_call_table)
         .long sys_set_thread_area
         .long sys_atomic_cmpxchg_32     /* 335 */
         .long sys_atomic_barrier
+        .long sys_fanotify_init
+        .long sys_fanotify_mark
+        .long sys_prlimit64
 
         .rept NR_syscalls-(.-sys_call_table)/4
                 .long sys_ni_syscall
diff --git a/arch/m68knommu/kernel/vmlinux.lds.S b/arch/m68knommu/kernel/vmlinux.lds.S
index a91b2713451d..ef332136f96d 100644
--- a/arch/m68knommu/kernel/vmlinux.lds.S
+++ b/arch/m68knommu/kernel/vmlinux.lds.S
@@ -150,6 +150,8 @@ SECTIONS {
                 _sdata = . ;
                 DATA_DATA
                 CACHELINE_ALIGNED_DATA(32)
+                PAGE_ALIGNED_DATA(PAGE_SIZE)
+                *(.data..shared_aligned)
                 INIT_TASK_DATA(THREAD_SIZE)
                 _edata = . ;
         } > DATA
diff --git a/arch/powerpc/include/asm/fsldma.h b/arch/powerpc/include/asm/fsldma.h
index a67aeed17d40..debc5ed96d6e 100644
--- a/arch/powerpc/include/asm/fsldma.h
+++ b/arch/powerpc/include/asm/fsldma.h
@@ -11,6 +11,7 @@
 #ifndef __ARCH_POWERPC_ASM_FSLDMA_H__
 #define __ARCH_POWERPC_ASM_FSLDMA_H__
 
+#include <linux/slab.h>
 #include <linux/dmaengine.h>
 
 /*
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 4d6681dce816..c571cd3c1453 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -575,13 +575,19 @@ __secondary_start:
         /* Initialize the kernel stack.  Just a repeat for iSeries.      */
         LOAD_REG_ADDR(r3, current_set)
         sldi    r28,r24,3               /* get current_set[cpu#]         */
-        ldx     r1,r3,r28
-        addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
-        std     r1,PACAKSAVE(r13)
+        ldx     r14,r3,r28
+        addi    r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
+        std     r14,PACAKSAVE(r13)
 
         /* Do early setup for that CPU (stab, slb, hash table pointer) */
         bl      .early_setup_secondary
 
+        /*
+         * setup the new stack pointer, but *don't* use this until
+         * translation is on.
+         */
+        mr      r1, r14
+
         /* Clear backchain so we get nice backtraces */
         li      r7,0
         mtlr    r7
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 6bbd7a604d24..a7a570dcdd57 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -810,6 +810,9 @@ relocate_new_kernel:
         isync
         sync
 
+        mfspr   r3, SPRN_PIR /* current core we are running on */
+        mr      r4, r5 /* load physical address of chunk called */
+
         /* jump to the entry point, usually the setup routine */
         mtlr    r5
         blrl
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index ce53dfa7130d..8533b3b83f5d 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -577,20 +577,11 @@ void timer_interrupt(struct pt_regs * regs)
          * some CPUs will continuue to take decrementer exceptions */
         set_dec(DECREMENTER_MAX);
 
-#ifdef CONFIG_PPC32
+#if defined(CONFIG_PPC32) && defined(CONFIG_PMAC)
         if (atomic_read(&ppc_n_lost_interrupts) != 0)
                 do_IRQ(regs);
 #endif
 
-        now = get_tb_or_rtc();
-        if (now < decrementer->next_tb) {
-                /* not time for this event yet */
-                now = decrementer->next_tb - now;
-                if (now <= DECREMENTER_MAX)
-                        set_dec((int)now);
-                trace_timer_interrupt_exit(regs);
-                return;
-        }
         old_regs = set_irq_regs(regs);
         irq_enter();
 
@@ -606,8 +597,16 @@ void timer_interrupt(struct pt_regs * regs)
                 get_lppaca()->int_dword.fields.decr_int = 0;
 #endif
 
-        if (evt->event_handler)
-                evt->event_handler(evt);
+        now = get_tb_or_rtc();
+        if (now >= decrementer->next_tb) {
+                decrementer->next_tb = ~(u64)0;
+                if (evt->event_handler)
+                        evt->event_handler(evt);
+        } else {
+                now = decrementer->next_tb - now;
+                if (now <= DECREMENTER_MAX)
+                        set_dec((int)now);
+        }
 
 #ifdef CONFIG_PPC_ISERIES
         if (firmware_has_feature(FW_FEATURE_ISERIES) && hvlpevent_is_pending())
diff --git a/arch/powerpc/platforms/83xx/mpc837x_mds.c b/arch/powerpc/platforms/83xx/mpc837x_mds.c
index f9751c8905be..83068322abd1 100644
--- a/arch/powerpc/platforms/83xx/mpc837x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc837x_mds.c
@@ -48,8 +48,10 @@ static int mpc837xmds_usb_cfg(void)
                 return -1;
 
         np = of_find_node_by_name(NULL, "usb");
-        if (!np)
-                return -ENODEV;
+        if (!np) {
+                ret = -ENODEV;
+                goto out;
+        }
         phy_type = of_get_property(np, "phy_type", NULL);
         if (phy_type && !strcmp(phy_type, "ulpi")) {
                 clrbits8(bcsr_regs + 12, BCSR12_USB_SER_PIN);
@@ -65,8 +67,9 @@ static int mpc837xmds_usb_cfg(void)
         }
 
         of_node_put(np);
+out:
         iounmap(bcsr_regs);
-        return 0;
+        return ret;
 }
 
 /* ************************************************************************
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index da64be19d099..aa34cac4eb5c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -357,6 +357,7 @@ static void __init mpc85xx_mds_setup_arch(void)
 {
 #ifdef CONFIG_PCI
         struct pci_controller *hose;
+        struct device_node *np;
 #endif
         dma_addr_t max = 0xffffffff;
 
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index e1467c937450..34e00902ce86 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -19,7 +19,7 @@
 
 #include <linux/pci.h>
 #include <linux/of_platform.h>
-#include <linux/lmb.h>
+#include <linux/memblock.h>
 
 #include <asm/mpic.h>
 #include <asm/swiotlb.h>
@@ -97,7 +97,7 @@ static void __init p1022_ds_setup_arch(void)
 #endif
 
 #ifdef CONFIG_SWIOTLB
-        if (lmb_end_of_DRAM() > max) {
+        if (memblock_end_of_DRAM() > max) {
                 ppc_swiotlb_enable = 1;
                 set_pci_dma_ops(&swiotlb_dma_ops);
                 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
diff --git a/arch/powerpc/platforms/pseries/dlpar.c b/arch/powerpc/platforms/pseries/dlpar.c
index 227c1c3d585e..72d8054fa739 100644
--- a/arch/powerpc/platforms/pseries/dlpar.c
+++ b/arch/powerpc/platforms/pseries/dlpar.c
@@ -129,20 +129,35 @@ struct device_node *dlpar_configure_connector(u32 drc_index)
         struct property *property;
         struct property *last_property = NULL;
         struct cc_workarea *ccwa;
+        char *data_buf;
         int cc_token;
-        int rc;
+        int rc = -1;
 
         cc_token = rtas_token("ibm,configure-connector");
         if (cc_token == RTAS_UNKNOWN_SERVICE)
                 return NULL;
 
-        spin_lock(&rtas_data_buf_lock);
-        ccwa = (struct cc_workarea *)&rtas_data_buf[0];
+        data_buf = kzalloc(RTAS_DATA_BUF_SIZE, GFP_KERNEL);
+        if (!data_buf)
+                return NULL;
+
+        ccwa = (struct cc_workarea *)&data_buf[0];
         ccwa->drc_index = drc_index;
         ccwa->zero = 0;
 
-        rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL);
-        while (rc) {
+        do {
+                /* Since we release the rtas_data_buf lock between configure
+                 * connector calls we want to re-populate the rtas_data_buffer
+                 * with the contents of the previous call.
+                 */
+                spin_lock(&rtas_data_buf_lock);
+
+                memcpy(rtas_data_buf, data_buf, RTAS_DATA_BUF_SIZE);
+                rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL);
+                memcpy(data_buf, rtas_data_buf, RTAS_DATA_BUF_SIZE);
+
+                spin_unlock(&rtas_data_buf_lock);
+
                 switch (rc) {
                 case NEXT_SIBLING:
                         dn = dlpar_parse_cc_node(ccwa);
@@ -197,18 +212,19 @@ struct device_node *dlpar_configure_connector(u32 drc_index)
                                "returned from configure-connector\n", rc);
                         goto cc_error;
                 }
+        } while (rc);
 
-                rc = rtas_call(cc_token, 2, 1, NULL, rtas_data_buf, NULL);
+cc_error:
+        kfree(data_buf);
+
+        if (rc) {
+                if (first_dn)
+                        dlpar_free_cc_nodes(first_dn);
+
+                return NULL;
         }
 
-        spin_unlock(&rtas_data_buf_lock);
         return first_dn;
-
-cc_error:
-        if (first_dn)
-                dlpar_free_cc_nodes(first_dn);
-        spin_unlock(&rtas_data_buf_lock);
-        return NULL;
 }
 
 static struct device_node *derive_parent(const char *path)
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 209384b6e039..4ae933225251 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -399,6 +399,8 @@ DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021E, quirk_fsl_pcie_header);
+DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1021, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 6425abe5b7db..3017532319c8 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -240,12 +240,13 @@ struct rio_priv {
 
 static void __iomem *rio_regs_win;
 
+#ifdef CONFIG_E500
 static int (*saved_mcheck_exception)(struct pt_regs *regs);
 
 static int fsl_rio_mcheck_exception(struct pt_regs *regs)
 {
         const struct exception_table_entry *entry = NULL;
-        unsigned long reason = (mfspr(SPRN_MCSR) & MCSR_MASK);
+        unsigned long reason = mfspr(SPRN_MCSR);
 
         if (reason & MCSR_BUS_RBERR) {
                 reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
@@ -269,6 +270,7 @@ static int fsl_rio_mcheck_exception(struct pt_regs *regs)
         else
                 return cur_cpu_spec->machine_check(regs);
 }
+#endif
 
 /**
  * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
@@ -1517,8 +1519,10 @@ int fsl_rio_setup(struct platform_device *dev)
         fsl_rio_doorbell_init(port);
         fsl_rio_port_write_init(port);
 
+#ifdef CONFIG_E500
         saved_mcheck_exception = ppc_md.machine_check_exception;
         ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
+#endif
         /* Ensure that RFXE is set */
         mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
 
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 3da8014931c9..90020de4dcf2 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -640,6 +640,7 @@ unsigned int qe_get_num_of_snums(void)
                 if ((num_of_snums < 28) || (num_of_snums > QE_NUM_OF_SNUM)) {
                         /* No QE ever has fewer than 28 SNUMs */
                         pr_err("QE: number of snum is invalid\n");
+                        of_node_put(qe);
                         return -EINVAL;
                 }
         }
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index 0554445200bf..d17d04cfb2cd 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -2880,15 +2880,14 @@ static void xmon_init(int enable)
 }
 
 #ifdef CONFIG_MAGIC_SYSRQ
-static void sysrq_handle_xmon(int key, struct tty_struct *tty) 
+static void sysrq_handle_xmon(int key)
 {
         /* ensure xmon is enabled */
         xmon_init(1);
         debugger(get_irq_regs());
 }
 
-static struct sysrq_key_op sysrq_xmon_op = 
-{
+static struct sysrq_key_op sysrq_xmon_op = {
         .handler =      sysrq_handle_xmon,
         .help_msg =     "Xmon",
         .action_msg =   "Entering xmon",
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index 485f54748384..c158a95ec664 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -303,7 +303,7 @@ void arch_trigger_all_cpu_backtrace(void)
 
 #ifdef CONFIG_MAGIC_SYSRQ
 
-static void sysrq_handle_globreg(int key, struct tty_struct *tty)
+static void sysrq_handle_globreg(int key)
 {
         arch_trigger_all_cpu_backtrace();
 }
diff --git a/arch/sparc/kernel/sys_sparc_32.c b/arch/sparc/kernel/sys_sparc_32.c
index 50794137d710..675c9e11ada5 100644
--- a/arch/sparc/kernel/sys_sparc_32.c
+++ b/arch/sparc/kernel/sys_sparc_32.c
@@ -166,7 +166,6 @@ sparc_breakpoint (struct pt_regs *regs)
 {
         siginfo_t info;
 
-        lock_kernel();
 #ifdef DEBUG_SPARC_BREAKPOINT
         printk ("TRAP: Entering kernel PC=%x, nPC=%x\n", regs->pc, regs->npc);
 #endif
@@ -180,7 +179,6 @@ sparc_breakpoint (struct pt_regs *regs)
 #ifdef DEBUG_SPARC_BREAKPOINT
         printk ("TRAP: Returning to space: PC=%x nPC=%x\n", regs->pc, regs->npc);
 #endif
-        unlock_kernel();
 }
 
 asmlinkage int
diff --git a/arch/sparc/kernel/unaligned_32.c b/arch/sparc/kernel/unaligned_32.c
index f8514e291e15..12b9f352595f 100644
--- a/arch/sparc/kernel/unaligned_32.c
+++ b/arch/sparc/kernel/unaligned_32.c
@@ -323,7 +323,6 @@ asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn)
 {
         enum direction dir;
 
-        lock_kernel();
         if(!(current->thread.flags & SPARC_FLAG_UNALIGNED) ||
            (((insn >> 30) & 3) != 3))
                 goto kill_user;
@@ -377,5 +376,5 @@ asmlinkage void user_unaligned_trap(struct pt_regs *regs, unsigned int insn)
 kill_user:
         user_mna_trap_fault(regs, insn);
 out:
-        unlock_kernel();
+        ;
 }
diff --git a/arch/sparc/kernel/windows.c b/arch/sparc/kernel/windows.c
index f24d298bda29..b351770cbdd6 100644
--- a/arch/sparc/kernel/windows.c
+++ b/arch/sparc/kernel/windows.c
@@ -112,7 +112,6 @@ void try_to_clear_window_buffer(struct pt_regs *regs, int who)
         struct thread_info *tp = current_thread_info();
         int window;
 
-        lock_kernel();
         flush_user_windows();
         for(window = 0; window < tp->w_saved; window++) {
                 unsigned long sp = tp->rwbuf_stkptrs[window];
@@ -123,5 +122,4 @@ void try_to_clear_window_buffer(struct pt_regs *regs, int who)
                         do_exit(SIGILL);
         }
         tp->w_saved = 0;
-        unlock_kernel();
 }
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index de317d0c3294..ebc680717e59 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -690,7 +690,7 @@ static void with_console(struct mc_request *req, void (*proc)(void *),
 static void sysrq_proc(void *arg)
 {
         char *op = arg;
-        handle_sysrq(*op, NULL);
+        handle_sysrq(*op);
 }
 
 void mconsole_sysrq(struct mc_request *req)
diff --git a/arch/x86/include/asm/iomap.h b/arch/x86/include/asm/iomap.h
index f35eb45d6576..c4191b3b7056 100644
--- a/arch/x86/include/asm/iomap.h
+++ b/arch/x86/include/asm/iomap.h
@@ -26,11 +26,11 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 
-void *
+void __iomem *
 iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot);
 
 void
-iounmap_atomic(void *kvaddr, enum km_type type);
+iounmap_atomic(void __iomem *kvaddr, enum km_type type);
 
 int
 iomap_create_wc(resource_size_t base, unsigned long size, pgprot_t *prot);
diff --git a/arch/x86/include/asm/kvm_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index 51cfd730ac5d..1f99ecfc48e1 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -152,9 +152,14 @@ struct x86_emulate_ops {
 struct operand {
         enum { OP_REG, OP_MEM, OP_IMM, OP_NONE } type;
         unsigned int bytes;
-        unsigned long orig_val, *ptr;
+        union {
+                unsigned long orig_val;
+                u64 orig_val64;
+        };
+        unsigned long *ptr;
         union {
                 unsigned long val;
+                u64 val64;
                 char valptr[sizeof(unsigned long) + 2];
         };
 };
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 404a880ea325..d395540ff894 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -27,6 +27,9 @@ extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
                                             int node);
 extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
 
+#ifdef CONFIG_PCI
+
+#ifdef CONFIG_PCI_DOMAINS
 static inline int pci_domain_nr(struct pci_bus *bus)
 {
         struct pci_sysdata *sd = bus->sysdata;
@@ -37,13 +40,12 @@ static inline int pci_proc_domain(struct pci_bus *bus)
 {
         return pci_domain_nr(bus);
 }
-
+#endif
 
 /* Can be used to override the logic in pci_scan_bus for skipping
    already-configured bus numbers - to be used for buggy BIOSes
    or architectures with incomplete PCI setup by the loader */
 
-#ifdef CONFIG_PCI
 extern unsigned int pcibios_assign_all_busses(void);
 extern int pci_legacy_init(void);
 # ifdef CONFIG_ACPI
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index c0427295e8f5..1ca132fc0d03 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -59,5 +59,7 @@ extern void check_tsc_sync_source(int cpu);
 extern void check_tsc_sync_target(void);
 
 extern int notsc_setup(char *);
+extern void save_sched_clock_state(void);
+extern void restore_sched_clock_state(void);
 
 #endif /* _ASM_X86_TSC_H */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 224392d8fe8c..5e975298fa81 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -530,7 +530,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                 err = -ENOMEM;
                 goto out;
         }
-        if (!alloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
+        if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
                 kfree(b);
                 err = -ENOMEM;
                 goto out;
@@ -543,7 +543,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 #ifndef CONFIG_SMP
         cpumask_setall(b->cpus);
 #else
-        cpumask_copy(b->cpus, c->llc_shared_map);
+        cpumask_set_cpu(cpu, b->cpus);
 #endif
 
         per_cpu(threshold_banks, cpu)[bank] = b;
diff --git a/arch/x86/kernel/cpu/mcheck/therm_throt.c b/arch/x86/kernel/cpu/mcheck/therm_throt.c
index c2a8b26d4fea..d9368eeda309 100644
--- a/arch/x86/kernel/cpu/mcheck/therm_throt.c
+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c
@@ -202,10 +202,11 @@ static int therm_throt_process(bool new_event, int event, int level)
 
 #ifdef CONFIG_SYSFS
 /* Add/Remove thermal_throttle interface for CPU device: */
-static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev)
+static __cpuinit int thermal_throttle_add_dev(struct sys_device *sys_dev,
+                                unsigned int cpu)
 {
         int err;
-        struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
+        struct cpuinfo_x86 *c = &cpu_data(cpu);
 
         err = sysfs_create_group(&sys_dev->kobj, &thermal_attr_group);
         if (err)
@@ -251,7 +252,7 @@ thermal_throttle_cpu_callback(struct notifier_block *nfb,
         case CPU_UP_PREPARE:
         case CPU_UP_PREPARE_FROZEN:
                 mutex_lock(&therm_cpu_lock);
-                err = thermal_throttle_add_dev(sys_dev);
+                err = thermal_throttle_add_dev(sys_dev, cpu);
                 mutex_unlock(&therm_cpu_lock);
                 WARN_ON(err);
                 break;
@@ -287,7 +288,7 @@ static __init int thermal_throttle_init_device(void)
 #endif
         /* connect live CPUs to sysfs */
         for_each_online_cpu(cpu) {
-                err = thermal_throttle_add_dev(get_cpu_sysdev(cpu));
+                err = thermal_throttle_add_dev(get_cpu_sysdev(cpu), cpu);
                 WARN_ON(err);
         }
 #ifdef CONFIG_HOTPLUG_CPU
diff --git a/arch/x86/kernel/trampoline.c b/arch/x86/kernel/trampoline.c
index a874495b3673..e2a595257390 100644
--- a/arch/x86/kernel/trampoline.c
+++ b/arch/x86/kernel/trampoline.c
@@ -45,8 +45,7 @@ void __init setup_trampoline_page_table(void)
         /* Copy kernel address range */
         clone_pgd_range(trampoline_pg_dir + KERNEL_PGD_BOUNDARY,
                         swapper_pg_dir + KERNEL_PGD_BOUNDARY,
-                        min_t(unsigned long, KERNEL_PGD_PTRS,
-                              KERNEL_PGD_BOUNDARY));
+                        KERNEL_PGD_PTRS);
 
         /* Initialize low mappings */
         clone_pgd_range(trampoline_pg_dir,
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index ce8e50239332..26a863a9c2a8 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -626,6 +626,44 @@ static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
         local_irq_restore(flags);
 }
 
+static unsigned long long cyc2ns_suspend;
+
+void save_sched_clock_state(void)
+{
+        if (!sched_clock_stable)
+                return;
+
+        cyc2ns_suspend = sched_clock();
+}
+
+/*
+ * Even on processors with invariant TSC, TSC gets reset in some the
+ * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
+ * arbitrary value (still sync'd across cpu's) during resume from such sleep
+ * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
+ * that sched_clock() continues from the point where it was left off during
+ * suspend.
+ */
+void restore_sched_clock_state(void)
+{
+        unsigned long long offset;
+        unsigned long flags;
+        int cpu;
+
+        if (!sched_clock_stable)
+                return;
+
+        local_irq_save(flags);
+
+        __get_cpu_var(cyc2ns_offset) = 0;
+        offset = cyc2ns_suspend - sched_clock();
+
+        for_each_possible_cpu(cpu)
+                per_cpu(cyc2ns_offset, cpu) = offset;
+
+        local_irq_restore(flags);
+}
+
 #ifdef CONFIG_CPU_FREQ
 
 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index b38bd8b92aa6..66ca98aafdd6 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -1870,17 +1870,16 @@ static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
                                struct x86_emulate_ops *ops)
 {
         struct decode_cache *c = &ctxt->decode;
-        u64 old = c->dst.orig_val;
+        u64 old = c->dst.orig_val64;
 
         if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
             ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
-
                 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
                 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
                 ctxt->eflags &= ~EFLG_ZF;
         } else {
-                c->dst.val = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
-                       (u32) c->regs[VCPU_REGS_RBX];
+                c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
+                        (u32) c->regs[VCPU_REGS_RBX];
 
                 ctxt->eflags |= EFLG_ZF;
         }
@@ -2616,7 +2615,7 @@ x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
                                         c->src.valptr, c->src.bytes);
                 if (rc != X86EMUL_CONTINUE)
                         goto done;
-                c->src.orig_val = c->src.val;
+                c->src.orig_val64 = c->src.val64;
         }
 
         if (c->src2.type == OP_MEM) {
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index 8d10c063d7f2..4b7b73ce2098 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -64,6 +64,9 @@ static void pic_unlock(struct kvm_pic *s)
                 if (!found)
                         found = s->kvm->bsp_vcpu;
 
+                if (!found)
+                        return;
+
                 kvm_vcpu_kick(found);
         }
 }
diff --git a/arch/x86/kvm/irq.h b/arch/x86/kvm/irq.h
index ffed06871c5c..63c314502993 100644
--- a/arch/x86/kvm/irq.h
+++ b/arch/x86/kvm/irq.h
@@ -43,7 +43,6 @@ struct kvm_kpic_state {
         u8 irr;         /* interrupt request register */
         u8 imr;         /* interrupt mask register */
         u8 isr;         /* interrupt service register */
-        u8 isr_ack;     /* interrupt ack detection */
         u8 priority_add;        /* highest irq priority */
         u8 irq_base;
         u8 read_reg_select;
@@ -56,6 +55,7 @@ struct kvm_kpic_state {
         u8 init4;               /* true if 4 byte init */
         u8 elcr;                /* PIIX edge/trigger selection */
         u8 elcr_mask;
+        u8 isr_ack;     /* interrupt ack detection */
         struct kvm_pic *pics_state;
 };
 
diff --git a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c
index 84e236ce76ba..72fc70cf6184 100644
--- a/arch/x86/mm/iomap_32.c
+++ b/arch/x86/mm/iomap_32.c
@@ -74,7 +74,7 @@ void *kmap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
 /*
  * Map 'pfn' using fixed map 'type' and protections 'prot'
  */
-void *
+void __iomem *
 iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
 {
         /*
@@ -86,12 +86,12 @@ iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot)
         if (!pat_enabled && pgprot_val(prot) == pgprot_val(PAGE_KERNEL_WC))
                 prot = PAGE_KERNEL_UC_MINUS;
 
-        return kmap_atomic_prot_pfn(pfn, type, prot);
+        return (void __force __iomem *) kmap_atomic_prot_pfn(pfn, type, prot);
 }
 EXPORT_SYMBOL_GPL(iomap_atomic_prot_pfn);
 
 void
-iounmap_atomic(void *kvaddr, enum km_type type)
+iounmap_atomic(void __iomem *kvaddr, enum km_type type)
 {
         unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
         enum fixed_addresses idx = type + KM_TYPE_NR*smp_processor_id();
diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index e7e8c5f54956..87bb35e34ef1 100644
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -113,6 +113,7 @@ static void __save_processor_state(struct saved_context *ctxt)
 void save_processor_state(void)
 {
         __save_processor_state(&saved_context);
+        save_sched_clock_state();
 }
 #ifdef CONFIG_X86_32
 EXPORT_SYMBOL(save_processor_state);
@@ -229,6 +230,7 @@ static void __restore_processor_state(struct saved_context *ctxt)
 void restore_processor_state(void)
 {
         __restore_processor_state(&saved_context);
+        restore_sched_clock_state();
 }
 #ifdef CONFIG_X86_32
 EXPORT_SYMBOL(restore_processor_state);