[MIPS] SB1250: Interrupt handler fixes

Mask cp0.status against cp0.cause.  Additionally, spurious interrupts are
not recorded.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 5 insertions, 2 deletions

diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index a451b4c7732d..f9bd9f074517 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -442,7 +442,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
          * blasting the high 32 bits.
          */
 
-        pending = read_c0_cause();
+        pending = read_c0_cause() & read_c0_status();
 
 #ifdef CONFIG_SIBYTE_SB1250_PROF
         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
@@ -476,5 +476,8 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
                                               R_IMR_INTERRUPT_STATUS_BASE)));
                 if (mask)
                         do_IRQ(fls64(mask) - 1, regs);
-        }
+                else
+                        spurious_interrupt(regs);
+        } else
+                spurious_interrupt(regs);
 }