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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-30 22:02:59 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-30 22:02:59 -0400 |
commit | 55bcab46955644d5a8149a9b3cc9752a336e02f8 (patch) | |
tree | a45593603de9265cb0624043ab36f4e0f98823fc /arch | |
parent | 58580c86450bc09ff101f0d23fd8a162c146bc64 (diff) | |
parent | 7bec7a9134c25cecb0d7029199b59f7b1bef35b8 (diff) |
Merge branch 'perfcounters-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'perfcounters-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (47 commits)
perf report: Add --symbols parameter
perf report: Add --comms parameter
perf report: Add --dsos parameter
perf_counter tools: Adjust only prelinked symbol's addresses
perf_counter: Provide a way to enable counters on exec
perf_counter tools: Reduce perf stat measurement overhead/skew
perf stat: Use percentages for scaling output
perf_counter, x86: Update x86_pmu after WARN()
perf stat: Micro-optimize the code: memcpy is only required if no event is selected and !null_run
perf stat: Improve output
perf stat: Fix multi-run stats
perf stat: Add -n/--null option to run without counters
perf_counter tools: Remove dead code
perf_counter: Complete counter swap
perf report: Print sorted callchains per histogram entries
perf_counter tools: Prepare a small callchain framework
perf record: Fix unhandled io return value
perf_counter tools: Add alias for 'l1d' and 'l1i'
perf-report: Add bare minimum PERF_EVENT_READ parsing
perf-report: Add modes for inherited stats and no-samples
...
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/include/asm/perf_counter.h | 2 | ||||
-rw-r--r-- | arch/x86/include/asm/perf_counter.h | 3 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/perf_counter.c | 22 |
3 files changed, 15 insertions, 12 deletions
diff --git a/arch/powerpc/include/asm/perf_counter.h b/arch/powerpc/include/asm/perf_counter.h index 8ccd4e155768..0ea0639fcf75 100644 --- a/arch/powerpc/include/asm/perf_counter.h +++ b/arch/powerpc/include/asm/perf_counter.h | |||
@@ -61,6 +61,8 @@ struct pt_regs; | |||
61 | extern unsigned long perf_misc_flags(struct pt_regs *regs); | 61 | extern unsigned long perf_misc_flags(struct pt_regs *regs); |
62 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); | 62 | extern unsigned long perf_instruction_pointer(struct pt_regs *regs); |
63 | 63 | ||
64 | #define PERF_COUNTER_INDEX_OFFSET 1 | ||
65 | |||
64 | /* | 66 | /* |
65 | * Only override the default definitions in include/linux/perf_counter.h | 67 | * Only override the default definitions in include/linux/perf_counter.h |
66 | * if we have hardware PMU support. | 68 | * if we have hardware PMU support. |
diff --git a/arch/x86/include/asm/perf_counter.h b/arch/x86/include/asm/perf_counter.h index 5fb33e160ea0..fa64e401589d 100644 --- a/arch/x86/include/asm/perf_counter.h +++ b/arch/x86/include/asm/perf_counter.h | |||
@@ -87,6 +87,9 @@ union cpuid10_edx { | |||
87 | #ifdef CONFIG_PERF_COUNTERS | 87 | #ifdef CONFIG_PERF_COUNTERS |
88 | extern void init_hw_perf_counters(void); | 88 | extern void init_hw_perf_counters(void); |
89 | extern void perf_counters_lapic_init(void); | 89 | extern void perf_counters_lapic_init(void); |
90 | |||
91 | #define PERF_COUNTER_INDEX_OFFSET 0 | ||
92 | |||
90 | #else | 93 | #else |
91 | static inline void init_hw_perf_counters(void) { } | 94 | static inline void init_hw_perf_counters(void) { } |
92 | static inline void perf_counters_lapic_init(void) { } | 95 | static inline void perf_counters_lapic_init(void) { } |
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c index 76dfef23f789..d4cf4ce19aac 100644 --- a/arch/x86/kernel/cpu/perf_counter.c +++ b/arch/x86/kernel/cpu/perf_counter.c | |||
@@ -401,7 +401,7 @@ static const u64 amd_hw_cache_event_ids | |||
401 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ | 401 | [ C(RESULT_MISS) ] = 0x0041, /* Data Cache Misses */ |
402 | }, | 402 | }, |
403 | [ C(OP_WRITE) ] = { | 403 | [ C(OP_WRITE) ] = { |
404 | [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */ | 404 | [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */ |
405 | [ C(RESULT_MISS) ] = 0, | 405 | [ C(RESULT_MISS) ] = 0, |
406 | }, | 406 | }, |
407 | [ C(OP_PREFETCH) ] = { | 407 | [ C(OP_PREFETCH) ] = { |
@@ -912,6 +912,8 @@ x86_perf_counter_set_period(struct perf_counter *counter, | |||
912 | err = checking_wrmsrl(hwc->counter_base + idx, | 912 | err = checking_wrmsrl(hwc->counter_base + idx, |
913 | (u64)(-left) & x86_pmu.counter_mask); | 913 | (u64)(-left) & x86_pmu.counter_mask); |
914 | 914 | ||
915 | perf_counter_update_userpage(counter); | ||
916 | |||
915 | return ret; | 917 | return ret; |
916 | } | 918 | } |
917 | 919 | ||
@@ -969,13 +971,6 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc) | |||
969 | if (!x86_pmu.num_counters_fixed) | 971 | if (!x86_pmu.num_counters_fixed) |
970 | return -1; | 972 | return -1; |
971 | 973 | ||
972 | /* | ||
973 | * Quirk, IA32_FIXED_CTRs do not work on current Atom processors: | ||
974 | */ | ||
975 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | ||
976 | boot_cpu_data.x86_model == 28) | ||
977 | return -1; | ||
978 | |||
979 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; | 974 | event = hwc->config & ARCH_PERFMON_EVENT_MASK; |
980 | 975 | ||
981 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) | 976 | if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS))) |
@@ -1041,6 +1036,8 @@ try_generic: | |||
1041 | x86_perf_counter_set_period(counter, hwc, idx); | 1036 | x86_perf_counter_set_period(counter, hwc, idx); |
1042 | x86_pmu.enable(hwc, idx); | 1037 | x86_pmu.enable(hwc, idx); |
1043 | 1038 | ||
1039 | perf_counter_update_userpage(counter); | ||
1040 | |||
1044 | return 0; | 1041 | return 0; |
1045 | } | 1042 | } |
1046 | 1043 | ||
@@ -1133,6 +1130,8 @@ static void x86_pmu_disable(struct perf_counter *counter) | |||
1133 | x86_perf_counter_update(counter, hwc, idx); | 1130 | x86_perf_counter_update(counter, hwc, idx); |
1134 | cpuc->counters[idx] = NULL; | 1131 | cpuc->counters[idx] = NULL; |
1135 | clear_bit(idx, cpuc->used_mask); | 1132 | clear_bit(idx, cpuc->used_mask); |
1133 | |||
1134 | perf_counter_update_userpage(counter); | ||
1136 | } | 1135 | } |
1137 | 1136 | ||
1138 | /* | 1137 | /* |
@@ -1428,8 +1427,6 @@ static int intel_pmu_init(void) | |||
1428 | */ | 1427 | */ |
1429 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); | 1428 | x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); |
1430 | 1429 | ||
1431 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl); | ||
1432 | |||
1433 | /* | 1430 | /* |
1434 | * Install the hw-cache-events table: | 1431 | * Install the hw-cache-events table: |
1435 | */ | 1432 | */ |
@@ -1499,21 +1496,22 @@ void __init init_hw_perf_counters(void) | |||
1499 | pr_cont("%s PMU driver.\n", x86_pmu.name); | 1496 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
1500 | 1497 | ||
1501 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { | 1498 | if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) { |
1502 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | ||
1503 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", | 1499 | WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!", |
1504 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); | 1500 | x86_pmu.num_counters, X86_PMC_MAX_GENERIC); |
1501 | x86_pmu.num_counters = X86_PMC_MAX_GENERIC; | ||
1505 | } | 1502 | } |
1506 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; | 1503 | perf_counter_mask = (1 << x86_pmu.num_counters) - 1; |
1507 | perf_max_counters = x86_pmu.num_counters; | 1504 | perf_max_counters = x86_pmu.num_counters; |
1508 | 1505 | ||
1509 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { | 1506 | if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) { |
1510 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | ||
1511 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", | 1507 | WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!", |
1512 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); | 1508 | x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED); |
1509 | x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED; | ||
1513 | } | 1510 | } |
1514 | 1511 | ||
1515 | perf_counter_mask |= | 1512 | perf_counter_mask |= |
1516 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; | 1513 | ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED; |
1514 | x86_pmu.intel_ctrl = perf_counter_mask; | ||
1517 | 1515 | ||
1518 | perf_counters_lapic_init(); | 1516 | perf_counters_lapic_init(); |
1519 | register_die_notifier(&perf_counter_nmi_notifier); | 1517 | register_die_notifier(&perf_counter_nmi_notifier); |