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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-06-17 21:16:55 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-06-17 21:16:55 -0400
commit4b337c5f245b6587ba844ac7bb13c313a2912f7b (patch)
tree999c6a6580b76a083c8efb9dabff709d1c49fcd0 /arch
parent492b057c426e4aa747484958e18e9da29003985d (diff)
parent3fe0344faf7fdcb158bd5c1a9aec960a8d70c8e8 (diff)
Merge commit 'origin/master' into next
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/include/asm/8253pit.h7
-rw-r--r--arch/alpha/include/asm/kmap_types.h24
-rw-r--r--arch/alpha/kernel/init_task.c3
-rw-r--r--arch/alpha/kernel/irq_alpha.c2
-rw-r--r--arch/alpha/kernel/irq_i8259.c2
-rw-r--r--arch/alpha/kernel/irq_impl.h2
-rw-r--r--arch/alpha/kernel/irq_pyxis.c2
-rw-r--r--arch/alpha/kernel/irq_srm.c2
-rw-r--r--arch/alpha/kernel/setup.c6
-rw-r--r--arch/alpha/kernel/sys_alcor.c2
-rw-r--r--arch/alpha/kernel/sys_cabriolet.c2
-rw-r--r--arch/alpha/kernel/sys_dp264.c6
-rw-r--r--arch/alpha/kernel/sys_eb64p.c2
-rw-r--r--arch/alpha/kernel/sys_eiger.c2
-rw-r--r--arch/alpha/kernel/sys_jensen.c2
-rw-r--r--arch/alpha/kernel/sys_marvel.c10
-rw-r--r--arch/alpha/kernel/sys_mikasa.c2
-rw-r--r--arch/alpha/kernel/sys_noritake.c2
-rw-r--r--arch/alpha/kernel/sys_rawhide.c2
-rw-r--r--arch/alpha/kernel/sys_ruffian.c1
-rw-r--r--arch/alpha/kernel/sys_rx164.c2
-rw-r--r--arch/alpha/kernel/sys_sable.c2
-rw-r--r--arch/alpha/kernel/sys_takara.c2
-rw-r--r--arch/alpha/kernel/sys_titan.c4
-rw-r--r--arch/alpha/kernel/sys_wildfire.c2
-rw-r--r--arch/alpha/mm/numa.c6
-rw-r--r--arch/arm/kernel/init_task.c4
-rw-r--r--arch/arm/mach-pxa/pcm990-baseboard.c23
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h50
-rw-r--r--arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h377
-rw-r--r--arch/avr32/kernel/init_task.c4
-rw-r--r--arch/blackfin/include/asm/kmap_types.h17
-rw-r--r--arch/blackfin/kernel/init_task.c4
-rw-r--r--arch/cris/include/asm/kmap_types.h17
-rw-r--r--arch/cris/kernel/process.c4
-rw-r--r--arch/frv/kernel/init_task.c4
-rw-r--r--arch/h8300/include/asm/kmap_types.h17
-rw-r--r--arch/h8300/kernel/init_task.c4
-rw-r--r--arch/ia64/hp/common/sba_iommu.c2
-rw-r--r--arch/ia64/include/asm/kmap_types.h24
-rw-r--r--arch/ia64/kernel/init_task.c4
-rw-r--r--arch/ia64/kernel/mca.c3
-rw-r--r--arch/ia64/kernel/perfmon.c2
-rw-r--r--arch/ia64/kernel/uncached.c3
-rw-r--r--arch/ia64/sn/pci/pci_dma.c3
-rw-r--r--arch/m32r/include/asm/kmap_types.h23
-rw-r--r--arch/m32r/kernel/init_task.c4
-rw-r--r--arch/m32r/mm/discontig.c6
-rw-r--r--arch/m32r/platforms/m32104ut/setup.c2
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c8
-rw-r--r--arch/m32r/platforms/mappi/setup.c2
-rw-r--r--arch/m32r/platforms/mappi2/setup.c2
-rw-r--r--arch/m32r/platforms/mappi3/setup.c2
-rw-r--r--arch/m32r/platforms/oaks32r/setup.c2
-rw-r--r--arch/m32r/platforms/opsput/setup.c8
-rw-r--r--arch/m32r/platforms/usrv/setup.c4
-rw-r--r--arch/m68k/include/asm/kmap_types.h17
-rw-r--r--arch/m68k/kernel/process.c4
-rw-r--r--arch/m68knommu/kernel/init_task.c4
-rw-r--r--arch/microblaze/include/asm/kmap_types.h25
-rw-r--r--arch/mips/Kconfig17
-rw-r--r--arch/mips/Makefile9
-rw-r--r--arch/mips/alchemy/Kconfig19
-rw-r--r--arch/mips/alchemy/common/Makefile9
-rw-r--r--arch/mips/alchemy/common/gpio.c201
-rw-r--r--arch/mips/alchemy/common/gpiolib-au1000.c130
-rw-r--r--arch/mips/alchemy/common/reset.c5
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c12
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c10
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c3
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c10
-rw-r--r--arch/mips/alchemy/devboards/pm.c3
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c24
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c21
-rw-r--r--arch/mips/cavium-octeon/Makefile4
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c311
-rw-r--r--arch/mips/cavium-octeon/executive/Makefile1
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-bootmem.c104
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-errata.c73
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c144
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-sysinfo.c2
-rw-r--r--arch/mips/cavium-octeon/msi.c288
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c2
-rw-r--r--arch/mips/cavium-octeon/pci-common.c137
-rw-r--r--arch/mips/cavium-octeon/pci-common.h39
-rw-r--r--arch/mips/cavium-octeon/pci.c568
-rw-r--r--arch/mips/cavium-octeon/pcie.c1370
-rw-r--r--arch/mips/include/asm/cpu-features.h8
-rw-r--r--arch/mips/include/asm/delay.h2
-rw-r--r--arch/mips/include/asm/hugetlb.h114
-rw-r--r--arch/mips/include/asm/i8253.h2
-rw-r--r--arch/mips/include/asm/ioctl.h85
-rw-r--r--arch/mips/include/asm/kmap_types.h24
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000_gpio.h56
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio-au1000.h604
-rw-r--r--arch/mips/include/asm/mach-au1x00/gpio.h35
-rw-r--r--arch/mips/include/asm/mach-bcm47xx/gpio.h3
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h2
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-lemote/dma-coherence.h6
-rw-r--r--arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h5
-rw-r--r--arch/mips/include/asm/mipsregs.h16
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h13
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h85
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-errata.h33
-rw-r--r--arch/mips/include/asm/octeon/cvmx-helper-jtag.h43
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npei-defs.h2560
-rw-r--r--arch/mips/include/asm/octeon/cvmx-npi-defs.h1735
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pci-defs.h1645
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcieep-defs.h1365
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pciercx-defs.h1397
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pescx-defs.h410
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pexp-defs.h229
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h12
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h27
-rw-r--r--arch/mips/include/asm/octeon/octeon.h2
-rw-r--r--arch/mips/include/asm/page.h5
-rw-r--r--arch/mips/include/asm/pgtable-bits.h1
-rw-r--r--arch/mips/include/asm/pgtable.h10
-rw-r--r--arch/mips/include/asm/r4kcache.h1
-rw-r--r--arch/mips/include/asm/suspend.h9
-rw-r--r--arch/mips/include/asm/txx9/dmac.h51
-rw-r--r--arch/mips/include/asm/txx9/generic.h6
-rw-r--r--arch/mips/include/asm/txx9/tx4927.h4
-rw-r--r--arch/mips/include/asm/txx9/tx4938.h3
-rw-r--r--arch/mips/include/asm/txx9/tx4939.h6
-rw-r--r--arch/mips/kernel/asm-offsets.c13
-rw-r--r--arch/mips/kernel/cevt-txx9.c67
-rw-r--r--arch/mips/kernel/init_task.c4
-rw-r--r--arch/mips/kernel/smtc.c1
-rw-r--r--arch/mips/kernel/traps.c6
-rw-r--r--arch/mips/lib/delay.c4
-rw-r--r--arch/mips/mm/Makefile1
-rw-r--r--arch/mips/mm/c-r4k.c12
-rw-r--r--arch/mips/mm/dma-default.c23
-rw-r--r--arch/mips/mm/hugetlbpage.c101
-rw-r--r--arch/mips/mm/tlb-r4k.c43
-rw-r--r--arch/mips/mm/tlbex.c282
-rw-r--r--arch/mips/power/Makefile1
-rw-r--r--arch/mips/power/cpu.c43
-rw-r--r--arch/mips/power/hibernate.S70
-rw-r--r--arch/mips/rb532/irq.c5
-rw-r--r--arch/mips/sibyte/Kconfig31
-rw-r--r--arch/mips/sibyte/cfe/Makefile2
-rw-r--r--arch/mips/sibyte/common/Makefile4
-rw-r--r--arch/mips/sibyte/common/cfe.c (renamed from arch/mips/sibyte/cfe/setup.c)0
-rw-r--r--arch/mips/sibyte/common/cfe_console.c (renamed from arch/mips/sibyte/cfe/console.c)0
-rw-r--r--arch/mips/sibyte/sb1250/Makefile1
-rw-r--r--arch/mips/sibyte/sb1250/irq.c5
-rw-r--r--arch/mips/sibyte/sb1250/prom.c96
-rw-r--r--arch/mips/sibyte/swarm/setup.c14
-rw-r--r--arch/mips/sni/eisa.c2
-rw-r--r--arch/mips/txx9/Kconfig3
-rw-r--r--arch/mips/txx9/generic/setup.c175
-rw-r--r--arch/mips/txx9/generic/setup_tx4927.c55
-rw-r--r--arch/mips/txx9/generic/setup_tx4938.c38
-rw-r--r--arch/mips/txx9/generic/setup_tx4939.c53
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c8
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c4
-rw-r--r--arch/mips/txx9/rbtx4939/setup.c5
-rw-r--r--arch/mn10300/include/asm/kmap_types.h27
-rw-r--r--arch/mn10300/kernel/init_task.c3
-rw-r--r--arch/parisc/include/asm/kmap_types.h24
-rw-r--r--arch/parisc/kernel/init_task.c4
-rw-r--r--arch/powerpc/include/asm/8253pit.h7
-rw-r--r--arch/powerpc/kernel/init_task.c4
-rw-r--r--arch/powerpc/kernel/prom_init.c3
-rw-r--r--arch/powerpc/platforms/cell/ras.c4
-rw-r--r--arch/powerpc/platforms/cell/spu_base.c11
-rw-r--r--arch/s390/include/asm/kmap_types.h17
-rw-r--r--arch/s390/kernel/init_task.c4
-rw-r--r--arch/sh/include/asm/kmap_types.h24
-rw-r--r--arch/sh/kernel/init_task.c3
-rw-r--r--arch/sparc/include/asm/kmap_types.h17
-rw-r--r--arch/sparc/kernel/init_task.c3
-rw-r--r--arch/um/drivers/net_kern.c4
-rw-r--r--arch/um/drivers/ubd_kern.c4
-rw-r--r--arch/um/include/shared/init.h2
-rw-r--r--arch/um/include/shared/net_user.h2
-rw-r--r--arch/um/kernel/init_task.c3
-rw-r--r--arch/um/kernel/irq.c6
-rw-r--r--arch/um/sys-i386/stub.S2
-rw-r--r--arch/um/sys-x86_64/asm/elf.h44
-rw-r--r--arch/um/sys-x86_64/stub.S2
-rw-r--r--arch/x86/Kconfig1
-rw-r--r--arch/x86/Makefile5
-rw-r--r--arch/x86/include/asm/dma-mapping.h7
-rw-r--r--arch/x86/include/asm/kmap_types.h23
-rw-r--r--arch/x86/include/asm/kmemcheck.h42
-rw-r--r--arch/x86/include/asm/pgtable.h5
-rw-r--r--arch/x86/include/asm/pgtable_types.h9
-rw-r--r--arch/x86/include/asm/string_32.h8
-rw-r--r--arch/x86/include/asm/string_64.h8
-rw-r--r--arch/x86/include/asm/thread_info.h4
-rw-r--r--arch/x86/include/asm/timex.h4
-rw-r--r--arch/x86/include/asm/xor.h5
-rw-r--r--arch/x86/kernel/cpu/common.c11
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.c191
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.h11
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c60
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-ich.c93
-rw-r--r--arch/x86/kernel/cpu/cpufreq/speedstep-lib.c1
-rw-r--r--arch/x86/kernel/cpu/intel.c23
-rw-r--r--arch/x86/kernel/cpuid.c6
-rw-r--r--arch/x86/kernel/i8253.c1
-rw-r--r--arch/x86/kernel/init_task.c1
-rw-r--r--arch/x86/kernel/microcode_core.c1
-rw-r--r--arch/x86/kernel/msr.c6
-rw-r--r--arch/x86/kernel/process.c2
-rw-r--r--arch/x86/kernel/stacktrace.c7
-rw-r--r--arch/x86/kernel/traps.c5
-rw-r--r--arch/x86/kernel/tsc.c9
-rw-r--r--arch/x86/kvm/vmx.c2
-rw-r--r--arch/x86/mm/Makefile2
-rw-r--r--arch/x86/mm/fault.c18
-rw-r--r--arch/x86/mm/init.c2
-rw-r--r--arch/x86/mm/init_32.c2
-rw-r--r--arch/x86/mm/init_64.c4
-rw-r--r--arch/x86/mm/kmemcheck/Makefile1
-rw-r--r--arch/x86/mm/kmemcheck/error.c228
-rw-r--r--arch/x86/mm/kmemcheck/error.h15
-rw-r--r--arch/x86/mm/kmemcheck/kmemcheck.c640
-rw-r--r--arch/x86/mm/kmemcheck/opcode.c106
-rw-r--r--arch/x86/mm/kmemcheck/opcode.h9
-rw-r--r--arch/x86/mm/kmemcheck/pte.c22
-rw-r--r--arch/x86/mm/kmemcheck/pte.h10
-rw-r--r--arch/x86/mm/kmemcheck/selftest.c69
-rw-r--r--arch/x86/mm/kmemcheck/selftest.h6
-rw-r--r--arch/x86/mm/kmemcheck/shadow.c162
-rw-r--r--arch/x86/mm/kmemcheck/shadow.h16
-rw-r--r--arch/x86/mm/pageattr.c2
-rw-r--r--arch/x86/mm/pgtable.c12
-rw-r--r--arch/xtensa/include/asm/kmap_types.h27
-rw-r--r--arch/xtensa/kernel/init_task.c4
238 files changed, 16827 insertions, 1417 deletions
diff --git a/arch/alpha/include/asm/8253pit.h b/arch/alpha/include/asm/8253pit.h
index fef5c1450e47..a71c9c1455a7 100644
--- a/arch/alpha/include/asm/8253pit.h
+++ b/arch/alpha/include/asm/8253pit.h
@@ -1,10 +1,3 @@
1/* 1/*
2 * 8253/8254 Programmable Interval Timer 2 * 8253/8254 Programmable Interval Timer
3 */ 3 */
4
5#ifndef _8253PIT_H
6#define _8253PIT_H
7
8#define PIT_TICK_RATE 1193180UL
9
10#endif
diff --git a/arch/alpha/include/asm/kmap_types.h b/arch/alpha/include/asm/kmap_types.h
index 3e6735a34c57..a8d4ec8ea4b6 100644
--- a/arch/alpha/include/asm/kmap_types.h
+++ b/arch/alpha/include/asm/kmap_types.h
@@ -3,30 +3,12 @@
3 3
4/* Dummy header just to define km_type. */ 4/* Dummy header just to define km_type. */
5 5
6
7#ifdef CONFIG_DEBUG_HIGHMEM 6#ifdef CONFIG_DEBUG_HIGHMEM
8# define D(n) __KM_FENCE_##n , 7#define __WITH_KM_FENCE
9#else
10# define D(n)
11#endif 8#endif
12 9
13enum km_type { 10#include <asm-generic/kmap_types.h>
14D(0) KM_BOUNCE_READ,
15D(1) KM_SKB_SUNRPC_DATA,
16D(2) KM_SKB_DATA_SOFTIRQ,
17D(3) KM_USER0,
18D(4) KM_USER1,
19D(5) KM_BIO_SRC_IRQ,
20D(6) KM_BIO_DST_IRQ,
21D(7) KM_PTE0,
22D(8) KM_PTE1,
23D(9) KM_IRQ0,
24D(10) KM_IRQ1,
25D(11) KM_SOFTIRQ0,
26D(12) KM_SOFTIRQ1,
27D(13) KM_TYPE_NR
28};
29 11
30#undef D 12#undef __WITH_KM_FENCE
31 13
32#endif 14#endif
diff --git a/arch/alpha/kernel/init_task.c b/arch/alpha/kernel/init_task.c
index c2938e574a40..19b86328ffd7 100644
--- a/arch/alpha/kernel/init_task.c
+++ b/arch/alpha/kernel/init_task.c
@@ -10,10 +10,7 @@
10 10
11static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 11static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
12static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 12static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
13struct mm_struct init_mm = INIT_MM(init_mm);
14struct task_struct init_task = INIT_TASK(init_task); 13struct task_struct init_task = INIT_TASK(init_task);
15
16EXPORT_SYMBOL(init_mm);
17EXPORT_SYMBOL(init_task); 14EXPORT_SYMBOL(init_task);
18 15
19union thread_union init_thread_union 16union thread_union init_thread_union
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 67c19f8a9944..38c805dfc544 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -227,7 +227,7 @@ struct irqaction timer_irqaction = {
227 .name = "timer", 227 .name = "timer",
228}; 228};
229 229
230static struct hw_interrupt_type rtc_irq_type = { 230static struct irq_chip rtc_irq_type = {
231 .typename = "RTC", 231 .typename = "RTC",
232 .startup = rtc_startup, 232 .startup = rtc_startup,
233 .shutdown = rtc_enable_disable, 233 .shutdown = rtc_enable_disable,
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
index 9405bee9894e..50bfec9b588f 100644
--- a/arch/alpha/kernel/irq_i8259.c
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -83,7 +83,7 @@ i8259a_end_irq(unsigned int irq)
83 i8259a_enable_irq(irq); 83 i8259a_enable_irq(irq);
84} 84}
85 85
86struct hw_interrupt_type i8259a_irq_type = { 86struct irq_chip i8259a_irq_type = {
87 .typename = "XT-PIC", 87 .typename = "XT-PIC",
88 .startup = i8259a_startup_irq, 88 .startup = i8259a_startup_irq,
89 .shutdown = i8259a_disable_irq, 89 .shutdown = i8259a_disable_irq,
diff --git a/arch/alpha/kernel/irq_impl.h b/arch/alpha/kernel/irq_impl.h
index cc9a8a7aa279..b63ccd7386f1 100644
--- a/arch/alpha/kernel/irq_impl.h
+++ b/arch/alpha/kernel/irq_impl.h
@@ -36,7 +36,7 @@ extern void i8259a_disable_irq(unsigned int);
36extern void i8259a_mask_and_ack_irq(unsigned int); 36extern void i8259a_mask_and_ack_irq(unsigned int);
37extern unsigned int i8259a_startup_irq(unsigned int); 37extern unsigned int i8259a_startup_irq(unsigned int);
38extern void i8259a_end_irq(unsigned int); 38extern void i8259a_end_irq(unsigned int);
39extern struct hw_interrupt_type i8259a_irq_type; 39extern struct irq_chip i8259a_irq_type;
40extern void init_i8259a_irqs(void); 40extern void init_i8259a_irqs(void);
41 41
42extern void handle_irq(int irq); 42extern void handle_irq(int irq);
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c
index d53edbccbfe5..69199a76ec4a 100644
--- a/arch/alpha/kernel/irq_pyxis.c
+++ b/arch/alpha/kernel/irq_pyxis.c
@@ -70,7 +70,7 @@ pyxis_mask_and_ack_irq(unsigned int irq)
70 *(vulp)PYXIS_INT_MASK; 70 *(vulp)PYXIS_INT_MASK;
71} 71}
72 72
73static struct hw_interrupt_type pyxis_irq_type = { 73static struct irq_chip pyxis_irq_type = {
74 .typename = "PYXIS", 74 .typename = "PYXIS",
75 .startup = pyxis_startup_irq, 75 .startup = pyxis_startup_irq,
76 .shutdown = pyxis_disable_irq, 76 .shutdown = pyxis_disable_irq,
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c
index a03fbca4940e..85229369a1f8 100644
--- a/arch/alpha/kernel/irq_srm.c
+++ b/arch/alpha/kernel/irq_srm.c
@@ -48,7 +48,7 @@ srm_end_irq(unsigned int irq)
48} 48}
49 49
50/* Handle interrupts from the SRM, assuming no additional weirdness. */ 50/* Handle interrupts from the SRM, assuming no additional weirdness. */
51static struct hw_interrupt_type srm_irq_type = { 51static struct irq_chip srm_irq_type = {
52 .typename = "SRM", 52 .typename = "SRM",
53 .startup = srm_startup_irq, 53 .startup = srm_startup_irq,
54 .shutdown = srm_disable_irq, 54 .shutdown = srm_disable_irq,
diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c
index 80df86cd746b..d2634e4476b4 100644
--- a/arch/alpha/kernel/setup.c
+++ b/arch/alpha/kernel/setup.c
@@ -252,9 +252,9 @@ reserve_std_resources(void)
252} 252}
253 253
254#define PFN_MAX PFN_DOWN(0x80000000) 254#define PFN_MAX PFN_DOWN(0x80000000)
255#define for_each_mem_cluster(memdesc, cluster, i) \ 255#define for_each_mem_cluster(memdesc, _cluster, i) \
256 for ((cluster) = (memdesc)->cluster, (i) = 0; \ 256 for ((_cluster) = (memdesc)->cluster, (i) = 0; \
257 (i) < (memdesc)->numclusters; (i)++, (cluster)++) 257 (i) < (memdesc)->numclusters; (i)++, (_cluster)++)
258 258
259static unsigned long __init 259static unsigned long __init
260get_mem_size_limit(char *s) 260get_mem_size_limit(char *s)
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c
index e53a1e1c2f21..382035ef7394 100644
--- a/arch/alpha/kernel/sys_alcor.c
+++ b/arch/alpha/kernel/sys_alcor.c
@@ -89,7 +89,7 @@ alcor_end_irq(unsigned int irq)
89 alcor_enable_irq(irq); 89 alcor_enable_irq(irq);
90} 90}
91 91
92static struct hw_interrupt_type alcor_irq_type = { 92static struct irq_chip alcor_irq_type = {
93 .typename = "ALCOR", 93 .typename = "ALCOR",
94 .startup = alcor_startup_irq, 94 .startup = alcor_startup_irq,
95 .shutdown = alcor_disable_irq, 95 .shutdown = alcor_disable_irq,
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
index ace475c124f6..ed349436732b 100644
--- a/arch/alpha/kernel/sys_cabriolet.c
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -71,7 +71,7 @@ cabriolet_end_irq(unsigned int irq)
71 cabriolet_enable_irq(irq); 71 cabriolet_enable_irq(irq);
72} 72}
73 73
74static struct hw_interrupt_type cabriolet_irq_type = { 74static struct irq_chip cabriolet_irq_type = {
75 .typename = "CABRIOLET", 75 .typename = "CABRIOLET",
76 .startup = cabriolet_startup_irq, 76 .startup = cabriolet_startup_irq,
77 .shutdown = cabriolet_disable_irq, 77 .shutdown = cabriolet_disable_irq,
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index 5bd5259324b7..46e70ece5176 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -198,7 +198,7 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
198 return 0; 198 return 0;
199} 199}
200 200
201static struct hw_interrupt_type dp264_irq_type = { 201static struct irq_chip dp264_irq_type = {
202 .typename = "DP264", 202 .typename = "DP264",
203 .startup = dp264_startup_irq, 203 .startup = dp264_startup_irq,
204 .shutdown = dp264_disable_irq, 204 .shutdown = dp264_disable_irq,
@@ -209,7 +209,7 @@ static struct hw_interrupt_type dp264_irq_type = {
209 .set_affinity = dp264_set_affinity, 209 .set_affinity = dp264_set_affinity,
210}; 210};
211 211
212static struct hw_interrupt_type clipper_irq_type = { 212static struct irq_chip clipper_irq_type = {
213 .typename = "CLIPPER", 213 .typename = "CLIPPER",
214 .startup = clipper_startup_irq, 214 .startup = clipper_startup_irq,
215 .shutdown = clipper_disable_irq, 215 .shutdown = clipper_disable_irq,
@@ -298,7 +298,7 @@ clipper_srm_device_interrupt(unsigned long vector)
298} 298}
299 299
300static void __init 300static void __init
301init_tsunami_irqs(struct hw_interrupt_type * ops, int imin, int imax) 301init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
302{ 302{
303 long i; 303 long i;
304 for (i = imin; i <= imax; ++i) { 304 for (i = imin; i <= imax; ++i) {
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c
index 9c5a306dc0ee..660c23ef661f 100644
--- a/arch/alpha/kernel/sys_eb64p.c
+++ b/arch/alpha/kernel/sys_eb64p.c
@@ -69,7 +69,7 @@ eb64p_end_irq(unsigned int irq)
69 eb64p_enable_irq(irq); 69 eb64p_enable_irq(irq);
70} 70}
71 71
72static struct hw_interrupt_type eb64p_irq_type = { 72static struct irq_chip eb64p_irq_type = {
73 .typename = "EB64P", 73 .typename = "EB64P",
74 .startup = eb64p_startup_irq, 74 .startup = eb64p_startup_irq,
75 .shutdown = eb64p_disable_irq, 75 .shutdown = eb64p_disable_irq,
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c
index baf60f36cbd7..b99ea488d844 100644
--- a/arch/alpha/kernel/sys_eiger.c
+++ b/arch/alpha/kernel/sys_eiger.c
@@ -80,7 +80,7 @@ eiger_end_irq(unsigned int irq)
80 eiger_enable_irq(irq); 80 eiger_enable_irq(irq);
81} 81}
82 82
83static struct hw_interrupt_type eiger_irq_type = { 83static struct irq_chip eiger_irq_type = {
84 .typename = "EIGER", 84 .typename = "EIGER",
85 .startup = eiger_startup_irq, 85 .startup = eiger_startup_irq,
86 .shutdown = eiger_disable_irq, 86 .shutdown = eiger_disable_irq,
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c
index 2b5caf3d9b15..ef0b83a070ac 100644
--- a/arch/alpha/kernel/sys_jensen.c
+++ b/arch/alpha/kernel/sys_jensen.c
@@ -118,7 +118,7 @@ jensen_local_end(unsigned int irq)
118 i8259a_end_irq(1); 118 i8259a_end_irq(1);
119} 119}
120 120
121static struct hw_interrupt_type jensen_local_irq_type = { 121static struct irq_chip jensen_local_irq_type = {
122 .typename = "LOCAL", 122 .typename = "LOCAL",
123 .startup = jensen_local_startup, 123 .startup = jensen_local_startup,
124 .shutdown = jensen_local_shutdown, 124 .shutdown = jensen_local_shutdown,
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index c5a1a2438c67..bbfc4f20ca72 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -169,7 +169,7 @@ marvel_irq_noop_return(unsigned int irq)
169 return 0; 169 return 0;
170} 170}
171 171
172static struct hw_interrupt_type marvel_legacy_irq_type = { 172static struct irq_chip marvel_legacy_irq_type = {
173 .typename = "LEGACY", 173 .typename = "LEGACY",
174 .startup = marvel_irq_noop_return, 174 .startup = marvel_irq_noop_return,
175 .shutdown = marvel_irq_noop, 175 .shutdown = marvel_irq_noop,
@@ -179,7 +179,7 @@ static struct hw_interrupt_type marvel_legacy_irq_type = {
179 .end = marvel_irq_noop, 179 .end = marvel_irq_noop,
180}; 180};
181 181
182static struct hw_interrupt_type io7_lsi_irq_type = { 182static struct irq_chip io7_lsi_irq_type = {
183 .typename = "LSI", 183 .typename = "LSI",
184 .startup = io7_startup_irq, 184 .startup = io7_startup_irq,
185 .shutdown = io7_disable_irq, 185 .shutdown = io7_disable_irq,
@@ -189,7 +189,7 @@ static struct hw_interrupt_type io7_lsi_irq_type = {
189 .end = io7_end_irq, 189 .end = io7_end_irq,
190}; 190};
191 191
192static struct hw_interrupt_type io7_msi_irq_type = { 192static struct irq_chip io7_msi_irq_type = {
193 .typename = "MSI", 193 .typename = "MSI",
194 .startup = io7_startup_irq, 194 .startup = io7_startup_irq,
195 .shutdown = io7_disable_irq, 195 .shutdown = io7_disable_irq,
@@ -273,8 +273,8 @@ init_one_io7_msi(struct io7 *io7, unsigned int which, unsigned int where)
273 273
274static void __init 274static void __init
275init_io7_irqs(struct io7 *io7, 275init_io7_irqs(struct io7 *io7,
276 struct hw_interrupt_type *lsi_ops, 276 struct irq_chip *lsi_ops,
277 struct hw_interrupt_type *msi_ops) 277 struct irq_chip *msi_ops)
278{ 278{
279 long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16; 279 long base = (io7->pe << MARVEL_IRQ_VEC_PE_SHIFT) + 16;
280 long i; 280 long i;
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c
index 8d3e9429c5ee..4e366641a08e 100644
--- a/arch/alpha/kernel/sys_mikasa.c
+++ b/arch/alpha/kernel/sys_mikasa.c
@@ -68,7 +68,7 @@ mikasa_end_irq(unsigned int irq)
68 mikasa_enable_irq(irq); 68 mikasa_enable_irq(irq);
69} 69}
70 70
71static struct hw_interrupt_type mikasa_irq_type = { 71static struct irq_chip mikasa_irq_type = {
72 .typename = "MIKASA", 72 .typename = "MIKASA",
73 .startup = mikasa_startup_irq, 73 .startup = mikasa_startup_irq,
74 .shutdown = mikasa_disable_irq, 74 .shutdown = mikasa_disable_irq,
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c
index 538876b62449..35753a173bac 100644
--- a/arch/alpha/kernel/sys_noritake.c
+++ b/arch/alpha/kernel/sys_noritake.c
@@ -73,7 +73,7 @@ noritake_end_irq(unsigned int irq)
73 noritake_enable_irq(irq); 73 noritake_enable_irq(irq);
74} 74}
75 75
76static struct hw_interrupt_type noritake_irq_type = { 76static struct irq_chip noritake_irq_type = {
77 .typename = "NORITAKE", 77 .typename = "NORITAKE",
78 .startup = noritake_startup_irq, 78 .startup = noritake_startup_irq,
79 .shutdown = noritake_disable_irq, 79 .shutdown = noritake_disable_irq,
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c
index 672cb2df53df..f3aec7e085c8 100644
--- a/arch/alpha/kernel/sys_rawhide.c
+++ b/arch/alpha/kernel/sys_rawhide.c
@@ -135,7 +135,7 @@ rawhide_end_irq(unsigned int irq)
135 rawhide_enable_irq(irq); 135 rawhide_enable_irq(irq);
136} 136}
137 137
138static struct hw_interrupt_type rawhide_irq_type = { 138static struct irq_chip rawhide_irq_type = {
139 .typename = "RAWHIDE", 139 .typename = "RAWHIDE",
140 .startup = rawhide_startup_irq, 140 .startup = rawhide_startup_irq,
141 .shutdown = rawhide_disable_irq, 141 .shutdown = rawhide_disable_irq,
diff --git a/arch/alpha/kernel/sys_ruffian.c b/arch/alpha/kernel/sys_ruffian.c
index f15a329b6011..d9f9cfeb9931 100644
--- a/arch/alpha/kernel/sys_ruffian.c
+++ b/arch/alpha/kernel/sys_ruffian.c
@@ -14,6 +14,7 @@
14#include <linux/sched.h> 14#include <linux/sched.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/timex.h>
17#include <linux/init.h> 18#include <linux/init.h>
18 19
19#include <asm/ptrace.h> 20#include <asm/ptrace.h>
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c
index ce1faa6f1df1..fc9246373452 100644
--- a/arch/alpha/kernel/sys_rx164.c
+++ b/arch/alpha/kernel/sys_rx164.c
@@ -72,7 +72,7 @@ rx164_end_irq(unsigned int irq)
72 rx164_enable_irq(irq); 72 rx164_enable_irq(irq);
73} 73}
74 74
75static struct hw_interrupt_type rx164_irq_type = { 75static struct irq_chip rx164_irq_type = {
76 .typename = "RX164", 76 .typename = "RX164",
77 .startup = rx164_startup_irq, 77 .startup = rx164_startup_irq,
78 .shutdown = rx164_disable_irq, 78 .shutdown = rx164_disable_irq,
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c
index 9e263256a42d..426eb6906d01 100644
--- a/arch/alpha/kernel/sys_sable.c
+++ b/arch/alpha/kernel/sys_sable.c
@@ -501,7 +501,7 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
501 spin_unlock(&sable_lynx_irq_lock); 501 spin_unlock(&sable_lynx_irq_lock);
502} 502}
503 503
504static struct hw_interrupt_type sable_lynx_irq_type = { 504static struct irq_chip sable_lynx_irq_type = {
505 .typename = "SABLE/LYNX", 505 .typename = "SABLE/LYNX",
506 .startup = sable_lynx_startup_irq, 506 .startup = sable_lynx_startup_irq,
507 .shutdown = sable_lynx_disable_irq, 507 .shutdown = sable_lynx_disable_irq,
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index 9bd9a31450c6..830318c21661 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -74,7 +74,7 @@ takara_end_irq(unsigned int irq)
74 takara_enable_irq(irq); 74 takara_enable_irq(irq);
75} 75}
76 76
77static struct hw_interrupt_type takara_irq_type = { 77static struct irq_chip takara_irq_type = {
78 .typename = "TAKARA", 78 .typename = "TAKARA",
79 .startup = takara_startup_irq, 79 .startup = takara_startup_irq,
80 .shutdown = takara_disable_irq, 80 .shutdown = takara_disable_irq,
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 8dd239ebdb9e..88978fc60f83 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -185,7 +185,7 @@ titan_srm_device_interrupt(unsigned long vector)
185 185
186 186
187static void __init 187static void __init
188init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax) 188init_titan_irqs(struct irq_chip * ops, int imin, int imax)
189{ 189{
190 long i; 190 long i;
191 for (i = imin; i <= imax; ++i) { 191 for (i = imin; i <= imax; ++i) {
@@ -194,7 +194,7 @@ init_titan_irqs(struct hw_interrupt_type * ops, int imin, int imax)
194 } 194 }
195} 195}
196 196
197static struct hw_interrupt_type titan_irq_type = { 197static struct irq_chip titan_irq_type = {
198 .typename = "TITAN", 198 .typename = "TITAN",
199 .startup = titan_startup_irq, 199 .startup = titan_startup_irq,
200 .shutdown = titan_disable_irq, 200 .shutdown = titan_disable_irq,
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c
index 42c3eede4d09..e91b4c3838a8 100644
--- a/arch/alpha/kernel/sys_wildfire.c
+++ b/arch/alpha/kernel/sys_wildfire.c
@@ -157,7 +157,7 @@ wildfire_end_irq(unsigned int irq)
157 wildfire_enable_irq(irq); 157 wildfire_enable_irq(irq);
158} 158}
159 159
160static struct hw_interrupt_type wildfire_irq_type = { 160static struct irq_chip wildfire_irq_type = {
161 .typename = "WILDFIRE", 161 .typename = "WILDFIRE",
162 .startup = wildfire_startup_irq, 162 .startup = wildfire_startup_irq,
163 .shutdown = wildfire_disable_irq, 163 .shutdown = wildfire_disable_irq,
diff --git a/arch/alpha/mm/numa.c b/arch/alpha/mm/numa.c
index a13de49d1265..0eab55749423 100644
--- a/arch/alpha/mm/numa.c
+++ b/arch/alpha/mm/numa.c
@@ -28,9 +28,9 @@ EXPORT_SYMBOL(node_data);
28#define DBGDCONT(args...) 28#define DBGDCONT(args...)
29#endif 29#endif
30 30
31#define for_each_mem_cluster(memdesc, cluster, i) \ 31#define for_each_mem_cluster(memdesc, _cluster, i) \
32 for ((cluster) = (memdesc)->cluster, (i) = 0; \ 32 for ((_cluster) = (memdesc)->cluster, (i) = 0; \
33 (i) < (memdesc)->numclusters; (i)++, (cluster)++) 33 (i) < (memdesc)->numclusters; (i)++, (_cluster)++)
34 34
35static void __init show_mem_layout(void) 35static void __init show_mem_layout(void)
36{ 36{
diff --git a/arch/arm/kernel/init_task.c b/arch/arm/kernel/init_task.c
index e859af349467..3f470866bb89 100644
--- a/arch/arm/kernel/init_task.c
+++ b/arch/arm/kernel/init_task.c
@@ -14,10 +14,6 @@
14 14
15static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 15static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
17struct mm_struct init_mm = INIT_MM(init_mm);
18
19EXPORT_SYMBOL(init_mm);
20
21/* 17/*
22 * Initial thread structure. 18 * Initial thread structure.
23 * 19 *
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 095521e9ee24..01791d74e08e 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -380,12 +380,12 @@ static struct pca953x_platform_data pca9536_data = {
380 .gpio_base = NR_BUILTIN_GPIO, 380 .gpio_base = NR_BUILTIN_GPIO,
381}; 381};
382 382
383static int gpio_bus_switch; 383static int gpio_bus_switch = -EINVAL;
384 384
385static int pcm990_camera_set_bus_param(struct soc_camera_link *link, 385static int pcm990_camera_set_bus_param(struct soc_camera_link *link,
386 unsigned long flags) 386 unsigned long flags)
387{ 387{
388 if (gpio_bus_switch <= 0) { 388 if (gpio_bus_switch < 0) {
389 if (flags == SOCAM_DATAWIDTH_10) 389 if (flags == SOCAM_DATAWIDTH_10)
390 return 0; 390 return 0;
391 else 391 else
@@ -404,25 +404,34 @@ static unsigned long pcm990_camera_query_bus_param(struct soc_camera_link *link)
404{ 404{
405 int ret; 405 int ret;
406 406
407 if (!gpio_bus_switch) { 407 if (gpio_bus_switch < 0) {
408 ret = gpio_request(NR_BUILTIN_GPIO, "camera"); 408 ret = gpio_request(NR_BUILTIN_GPIO, "camera");
409 if (!ret) { 409 if (!ret) {
410 gpio_bus_switch = NR_BUILTIN_GPIO; 410 gpio_bus_switch = NR_BUILTIN_GPIO;
411 gpio_direction_output(gpio_bus_switch, 0); 411 gpio_direction_output(gpio_bus_switch, 0);
412 } else 412 }
413 gpio_bus_switch = -EINVAL;
414 } 413 }
415 414
416 if (gpio_bus_switch > 0) 415 if (gpio_bus_switch >= 0)
417 return SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_10; 416 return SOCAM_DATAWIDTH_8 | SOCAM_DATAWIDTH_10;
418 else 417 else
419 return SOCAM_DATAWIDTH_10; 418 return SOCAM_DATAWIDTH_10;
420} 419}
421 420
421static void pcm990_camera_free_bus(struct soc_camera_link *link)
422{
423 if (gpio_bus_switch < 0)
424 return;
425
426 gpio_free(gpio_bus_switch);
427 gpio_bus_switch = -EINVAL;
428}
429
422static struct soc_camera_link iclink = { 430static struct soc_camera_link iclink = {
423 .bus_id = 0, /* Must match with the camera ID above */ 431 .bus_id = 0, /* Must match with the camera ID above */
424 .query_bus_param = pcm990_camera_query_bus_param, 432 .query_bus_param = pcm990_camera_query_bus_param,
425 .set_bus_param = pcm990_camera_set_bus_param, 433 .set_bus_param = pcm990_camera_set_bus_param,
434 .free_bus = pcm990_camera_free_bus,
426}; 435};
427 436
428/* Board I2C devices. */ 437/* Board I2C devices. */
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
new file mode 100644
index 000000000000..36a85f5000c8
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
@@ -0,0 +1,50 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg-phy.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device PHY registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/* Note, this is a seperate header file as some of the clock framework
16 * needs to touch this if the clk_48m is used as the USB OHCI or other
17 * peripheral source.
18*/
19
20#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H
21#define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__
22
23/* S3C64XX_PA_USB_HSPHY */
24
25#define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
26
27#define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00)
28#define SRC_PHYPWR_OTG_DISABLE (1 << 4)
29#define SRC_PHYPWR_ANALOG_POWERDOWN (1 << 3)
30#define SRC_PHYPWR_FORCE_SUSPEND (1 << 1)
31
32#define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04)
33#define S3C_PHYCLK_MODE_USB11 (1 << 6)
34#define S3C_PHYCLK_EXT_OSC (1 << 5)
35#define S3C_PHYCLK_CLK_FORCE (1 << 4)
36#define S3C_PHYCLK_ID_PULL (1 << 2)
37#define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0)
38#define S3C_PHYCLK_CLKSEL_SHIFT (0)
39#define S3C_PHYCLK_CLKSEL_48M (0x0 << 0)
40#define S3C_PHYCLK_CLKSEL_12M (0x2 << 0)
41#define S3C_PHYCLK_CLKSEL_24M (0x3 << 0)
42
43#define S3C_RSTCON S3C_HSOTG_PHYREG(0x08)
44#define S3C_RSTCON_PHYCLK (1 << 2)
45#define S3C_RSTCON_HCLK (1 << 2)
46#define S3C_RSTCON_PHY (1 << 0)
47
48#define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
49
50#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
new file mode 100644
index 000000000000..8d18d9d4d148
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
@@ -0,0 +1,377 @@
1/* arch/arm/plat-s3c/include/plat/regs-usb-hsotg.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * S3C - USB2.0 Highspeed/OtG device block registers
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_H
16#define __PLAT_S3C64XX_REGS_USB_HSOTG_H __FILE__
17
18#define S3C_HSOTG_REG(x) (x)
19
20#define S3C_GOTGCTL S3C_HSOTG_REG(0x000)
21#define S3C_GOTGCTL_BSESVLD (1 << 19)
22#define S3C_GOTGCTL_ASESVLD (1 << 18)
23#define S3C_GOTGCTL_DBNC_SHORT (1 << 17)
24#define S3C_GOTGCTL_CONID_B (1 << 16)
25#define S3C_GOTGCTL_DEVHNPEN (1 << 11)
26#define S3C_GOTGCTL_HSSETHNPEN (1 << 10)
27#define S3C_GOTGCTL_HNPREQ (1 << 9)
28#define S3C_GOTGCTL_HSTNEGSCS (1 << 8)
29#define S3C_GOTGCTL_SESREQ (1 << 1)
30#define S3C_GOTGCTL_SESREQSCS (1 << 0)
31
32#define S3C_GOTGINT S3C_HSOTG_REG(0x004)
33#define S3C_GOTGINT_DbnceDone (1 << 19)
34#define S3C_GOTGINT_ADevTOUTChg (1 << 18)
35#define S3C_GOTGINT_HstNegDet (1 << 17)
36#define S3C_GOTGINT_HstnegSucStsChng (1 << 9)
37#define S3C_GOTGINT_SesReqSucStsChng (1 << 8)
38#define S3C_GOTGINT_SesEndDet (1 << 2)
39
40#define S3C_GAHBCFG S3C_HSOTG_REG(0x008)
41#define S3C_GAHBCFG_PTxFEmpLvl (1 << 8)
42#define S3C_GAHBCFG_NPTxFEmpLvl (1 << 7)
43#define S3C_GAHBCFG_DMAEn (1 << 5)
44#define S3C_GAHBCFG_HBstLen_MASK (0xf << 1)
45#define S3C_GAHBCFG_HBstLen_SHIFT (1)
46#define S3C_GAHBCFG_HBstLen_Single (0x0 << 1)
47#define S3C_GAHBCFG_HBstLen_Incr (0x1 << 1)
48#define S3C_GAHBCFG_HBstLen_Incr4 (0x3 << 1)
49#define S3C_GAHBCFG_HBstLen_Incr8 (0x5 << 1)
50#define S3C_GAHBCFG_HBstLen_Incr16 (0x7 << 1)
51#define S3C_GAHBCFG_GlblIntrEn (1 << 0)
52
53#define S3C_GUSBCFG S3C_HSOTG_REG(0x00C)
54#define S3C_GUSBCFG_PHYLPClkSel (1 << 15)
55#define S3C_GUSBCFG_HNPCap (1 << 9)
56#define S3C_GUSBCFG_SRPCap (1 << 8)
57#define S3C_GUSBCFG_PHYIf16 (1 << 3)
58#define S3C_GUSBCFG_TOutCal_MASK (0x7 << 0)
59#define S3C_GUSBCFG_TOutCal_SHIFT (0)
60#define S3C_GUSBCFG_TOutCal_LIMIT (0x7)
61#define S3C_GUSBCFG_TOutCal(_x) ((_x) << 0)
62
63#define S3C_GRSTCTL S3C_HSOTG_REG(0x010)
64
65#define S3C_GRSTCTL_AHBIdle (1 << 31)
66#define S3C_GRSTCTL_DMAReq (1 << 30)
67#define S3C_GRSTCTL_TxFNum_MASK (0x1f << 6)
68#define S3C_GRSTCTL_TxFNum_SHIFT (6)
69#define S3C_GRSTCTL_TxFNum_LIMIT (0x1f)
70#define S3C_GRSTCTL_TxFNum(_x) ((_x) << 6)
71#define S3C_GRSTCTL_TxFFlsh (1 << 5)
72#define S3C_GRSTCTL_RxFFlsh (1 << 4)
73#define S3C_GRSTCTL_INTknQFlsh (1 << 3)
74#define S3C_GRSTCTL_FrmCntrRst (1 << 2)
75#define S3C_GRSTCTL_HSftRst (1 << 1)
76#define S3C_GRSTCTL_CSftRst (1 << 0)
77
78#define S3C_GINTSTS S3C_HSOTG_REG(0x014)
79#define S3C_GINTMSK S3C_HSOTG_REG(0x018)
80
81#define S3C_GINTSTS_WkUpInt (1 << 31)
82#define S3C_GINTSTS_SessReqInt (1 << 30)
83#define S3C_GINTSTS_DisconnInt (1 << 29)
84#define S3C_GINTSTS_ConIDStsChng (1 << 28)
85#define S3C_GINTSTS_PTxFEmp (1 << 26)
86#define S3C_GINTSTS_HChInt (1 << 25)
87#define S3C_GINTSTS_PrtInt (1 << 24)
88#define S3C_GINTSTS_FetSusp (1 << 22)
89#define S3C_GINTSTS_incompIP (1 << 21)
90#define S3C_GINTSTS_IncomplSOIN (1 << 20)
91#define S3C_GINTSTS_OEPInt (1 << 19)
92#define S3C_GINTSTS_IEPInt (1 << 18)
93#define S3C_GINTSTS_EPMis (1 << 17)
94#define S3C_GINTSTS_EOPF (1 << 15)
95#define S3C_GINTSTS_ISOutDrop (1 << 14)
96#define S3C_GINTSTS_EnumDone (1 << 13)
97#define S3C_GINTSTS_USBRst (1 << 12)
98#define S3C_GINTSTS_USBSusp (1 << 11)
99#define S3C_GINTSTS_ErlySusp (1 << 10)
100#define S3C_GINTSTS_GOUTNakEff (1 << 7)
101#define S3C_GINTSTS_GINNakEff (1 << 6)
102#define S3C_GINTSTS_NPTxFEmp (1 << 5)
103#define S3C_GINTSTS_RxFLvl (1 << 4)
104#define S3C_GINTSTS_SOF (1 << 3)
105#define S3C_GINTSTS_OTGInt (1 << 2)
106#define S3C_GINTSTS_ModeMis (1 << 1)
107#define S3C_GINTSTS_CurMod_Host (1 << 0)
108
109#define S3C_GRXSTSR S3C_HSOTG_REG(0x01C)
110#define S3C_GRXSTSP S3C_HSOTG_REG(0x020)
111
112#define S3C_GRXSTS_FN_MASK (0x7f << 25)
113#define S3C_GRXSTS_FN_SHIFT (25)
114
115#define S3C_GRXSTS_PktSts_MASK (0xf << 17)
116#define S3C_GRXSTS_PktSts_SHIFT (17)
117#define S3C_GRXSTS_PktSts_GlobalOutNAK (0x1 << 17)
118#define S3C_GRXSTS_PktSts_OutRX (0x2 << 17)
119#define S3C_GRXSTS_PktSts_OutDone (0x3 << 17)
120#define S3C_GRXSTS_PktSts_SetupDone (0x4 << 17)
121#define S3C_GRXSTS_PktSts_SetupRX (0x6 << 17)
122
123#define S3C_GRXSTS_DPID_MASK (0x3 << 15)
124#define S3C_GRXSTS_DPID_SHIFT (15)
125#define S3C_GRXSTS_ByteCnt_MASK (0x7ff << 4)
126#define S3C_GRXSTS_ByteCnt_SHIFT (4)
127#define S3C_GRXSTS_EPNum_MASK (0xf << 0)
128#define S3C_GRXSTS_EPNum_SHIFT (0)
129
130#define S3C_GRXFSIZ S3C_HSOTG_REG(0x024)
131
132#define S3C_GNPTXFSIZ S3C_HSOTG_REG(0x028)
133
134#define S3C_GNPTXFSIZ_NPTxFDep_MASK (0xffff << 16)
135#define S3C_GNPTXFSIZ_NPTxFDep_SHIFT (16)
136#define S3C_GNPTXFSIZ_NPTxFDep_LIMIT (0xffff)
137#define S3C_GNPTXFSIZ_NPTxFDep(_x) ((_x) << 16)
138#define S3C_GNPTXFSIZ_NPTxFStAddr_MASK (0xffff << 0)
139#define S3C_GNPTXFSIZ_NPTxFStAddr_SHIFT (0)
140#define S3C_GNPTXFSIZ_NPTxFStAddr_LIMIT (0xffff)
141#define S3C_GNPTXFSIZ_NPTxFStAddr(_x) ((_x) << 0)
142
143#define S3C_GNPTXSTS S3C_HSOTG_REG(0x02C)
144
145#define S3C_GNPTXSTS_NPtxQTop_MASK (0x7f << 24)
146#define S3C_GNPTXSTS_NPtxQTop_SHIFT (24)
147
148#define S3C_GNPTXSTS_NPTxQSpcAvail_MASK (0xff << 16)
149#define S3C_GNPTXSTS_NPTxQSpcAvail_SHIFT (16)
150#define S3C_GNPTXSTS_NPTxQSpcAvail_GET(_v) (((_v) >> 16) & 0xff)
151
152#define S3C_GNPTXSTS_NPTxFSpcAvail_MASK (0xffff << 0)
153#define S3C_GNPTXSTS_NPTxFSpcAvail_SHIFT (0)
154#define S3C_GNPTXSTS_NPTxFSpcAvail_GET(_v) (((_v) >> 0) & 0xffff)
155
156
157#define S3C_HPTXFSIZ S3C_HSOTG_REG(0x100)
158
159#define S3C_DPTXFSIZn(_a) S3C_HSOTG_REG(0x104 + (((_a) - 1) * 4))
160
161#define S3C_DPTXFSIZn_DPTxFSize_MASK (0xffff << 16)
162#define S3C_DPTXFSIZn_DPTxFSize_SHIFT (16)
163#define S3C_DPTXFSIZn_DPTxFSize_GET(_v) (((_v) >> 16) & 0xffff)
164#define S3C_DPTXFSIZn_DPTxFSize_LIMIT (0xffff)
165#define S3C_DPTXFSIZn_DPTxFSize(_x) ((_x) << 16)
166
167#define S3C_DPTXFSIZn_DPTxFStAddr_MASK (0xffff << 0)
168#define S3C_DPTXFSIZn_DPTxFStAddr_SHIFT (0)
169
170/* Device mode registers */
171#define S3C_DCFG S3C_HSOTG_REG(0x800)
172
173#define S3C_DCFG_EPMisCnt_MASK (0x1f << 18)
174#define S3C_DCFG_EPMisCnt_SHIFT (18)
175#define S3C_DCFG_EPMisCnt_LIMIT (0x1f)
176#define S3C_DCFG_EPMisCnt(_x) ((_x) << 18)
177
178#define S3C_DCFG_PerFrInt_MASK (0x3 << 11)
179#define S3C_DCFG_PerFrInt_SHIFT (11)
180#define S3C_DCFG_PerFrInt_LIMIT (0x3)
181#define S3C_DCFG_PerFrInt(_x) ((_x) << 11)
182
183#define S3C_DCFG_DevAddr_MASK (0x7f << 4)
184#define S3C_DCFG_DevAddr_SHIFT (4)
185#define S3C_DCFG_DevAddr_LIMIT (0x7f)
186#define S3C_DCFG_DevAddr(_x) ((_x) << 4)
187
188#define S3C_DCFG_NZStsOUTHShk (1 << 2)
189
190#define S3C_DCFG_DevSpd_MASK (0x3 << 0)
191#define S3C_DCFG_DevSpd_SHIFT (0)
192#define S3C_DCFG_DevSpd_HS (0x0 << 0)
193#define S3C_DCFG_DevSpd_FS (0x1 << 0)
194#define S3C_DCFG_DevSpd_LS (0x2 << 0)
195#define S3C_DCFG_DevSpd_FS48 (0x3 << 0)
196
197#define S3C_DCTL S3C_HSOTG_REG(0x804)
198
199#define S3C_DCTL_PWROnPrgDone (1 << 11)
200#define S3C_DCTL_CGOUTNak (1 << 10)
201#define S3C_DCTL_SGOUTNak (1 << 9)
202#define S3C_DCTL_CGNPInNAK (1 << 8)
203#define S3C_DCTL_SGNPInNAK (1 << 7)
204#define S3C_DCTL_TstCtl_MASK (0x7 << 4)
205#define S3C_DCTL_TstCtl_SHIFT (4)
206#define S3C_DCTL_GOUTNakSts (1 << 3)
207#define S3C_DCTL_GNPINNakSts (1 << 2)
208#define S3C_DCTL_SftDiscon (1 << 1)
209#define S3C_DCTL_RmtWkUpSig (1 << 0)
210
211#define S3C_DSTS S3C_HSOTG_REG(0x808)
212
213#define S3C_DSTS_SOFFN_MASK (0x3fff << 8)
214#define S3C_DSTS_SOFFN_SHIFT (8)
215#define S3C_DSTS_SOFFN_LIMIT (0x3fff)
216#define S3C_DSTS_SOFFN(_x) ((_x) << 8)
217#define S3C_DSTS_ErraticErr (1 << 3)
218#define S3C_DSTS_EnumSpd_MASK (0x3 << 1)
219#define S3C_DSTS_EnumSpd_SHIFT (1)
220#define S3C_DSTS_EnumSpd_HS (0x0 << 1)
221#define S3C_DSTS_EnumSpd_FS (0x1 << 1)
222#define S3C_DSTS_EnumSpd_LS (0x2 << 1)
223#define S3C_DSTS_EnumSpd_FS48 (0x3 << 1)
224
225#define S3C_DSTS_SuspSts (1 << 0)
226
227#define S3C_DIEPMSK S3C_HSOTG_REG(0x810)
228
229#define S3C_DIEPMSK_INEPNakEffMsk (1 << 6)
230#define S3C_DIEPMSK_INTknEPMisMsk (1 << 5)
231#define S3C_DIEPMSK_INTknTXFEmpMsk (1 << 4)
232#define S3C_DIEPMSK_TimeOUTMsk (1 << 3)
233#define S3C_DIEPMSK_AHBErrMsk (1 << 2)
234#define S3C_DIEPMSK_EPDisbldMsk (1 << 1)
235#define S3C_DIEPMSK_XferComplMsk (1 << 0)
236
237#define S3C_DOEPMSK S3C_HSOTG_REG(0x814)
238
239#define S3C_DOEPMSK_Back2BackSetup (1 << 6)
240#define S3C_DOEPMSK_OUTTknEPdisMsk (1 << 4)
241#define S3C_DOEPMSK_SetupMsk (1 << 3)
242#define S3C_DOEPMSK_AHBErrMsk (1 << 2)
243#define S3C_DOEPMSK_EPDisbldMsk (1 << 1)
244#define S3C_DOEPMSK_XferComplMsk (1 << 0)
245
246#define S3C_DAINT S3C_HSOTG_REG(0x818)
247#define S3C_DAINTMSK S3C_HSOTG_REG(0x81C)
248
249#define S3C_DAINT_OutEP_SHIFT (16)
250#define S3C_DAINT_OutEP(x) (1 << ((x) + 16))
251#define S3C_DAINT_InEP(x) (1 << (x))
252
253#define S3C_DTKNQR1 S3C_HSOTG_REG(0x820)
254#define S3C_DTKNQR2 S3C_HSOTG_REG(0x824)
255#define S3C_DTKNQR3 S3C_HSOTG_REG(0x830)
256#define S3C_DTKNQR4 S3C_HSOTG_REG(0x834)
257
258#define S3C_DVBUSDIS S3C_HSOTG_REG(0x828)
259#define S3C_DVBUSPULSE S3C_HSOTG_REG(0x82C)
260
261#define S3C_DIEPCTL0 S3C_HSOTG_REG(0x900)
262#define S3C_DOEPCTL0 S3C_HSOTG_REG(0xB00)
263#define S3C_DIEPCTL(_a) S3C_HSOTG_REG(0x900 + ((_a) * 0x20))
264#define S3C_DOEPCTL(_a) S3C_HSOTG_REG(0xB00 + ((_a) * 0x20))
265
266/* EP0 specialness:
267 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
268 * bits[25..22] - should always be zero, this isn't a periodic endpoint
269 * bits[10..0] - MPS setting differenct for EP0
270*/
271#define S3C_D0EPCTL_MPS_MASK (0x3 << 0)
272#define S3C_D0EPCTL_MPS_SHIFT (0)
273#define S3C_D0EPCTL_MPS_64 (0x0 << 0)
274#define S3C_D0EPCTL_MPS_32 (0x1 << 0)
275#define S3C_D0EPCTL_MPS_16 (0x2 << 0)
276#define S3C_D0EPCTL_MPS_8 (0x3 << 0)
277
278#define S3C_DxEPCTL_EPEna (1 << 31)
279#define S3C_DxEPCTL_EPDis (1 << 30)
280#define S3C_DxEPCTL_SetD1PID (1 << 29)
281#define S3C_DxEPCTL_SetOddFr (1 << 29)
282#define S3C_DxEPCTL_SetD0PID (1 << 28)
283#define S3C_DxEPCTL_SetEvenFr (1 << 28)
284#define S3C_DxEPCTL_SNAK (1 << 27)
285#define S3C_DxEPCTL_CNAK (1 << 26)
286#define S3C_DxEPCTL_TxFNum_MASK (0xf << 22)
287#define S3C_DxEPCTL_TxFNum_SHIFT (22)
288#define S3C_DxEPCTL_TxFNum_LIMIT (0xf)
289#define S3C_DxEPCTL_TxFNum(_x) ((_x) << 22)
290
291#define S3C_DxEPCTL_Stall (1 << 21)
292#define S3C_DxEPCTL_Snp (1 << 20)
293#define S3C_DxEPCTL_EPType_MASK (0x3 << 18)
294#define S3C_DxEPCTL_EPType_SHIFT (18)
295#define S3C_DxEPCTL_EPType_Control (0x0 << 18)
296#define S3C_DxEPCTL_EPType_Iso (0x1 << 18)
297#define S3C_DxEPCTL_EPType_Bulk (0x2 << 18)
298#define S3C_DxEPCTL_EPType_Intterupt (0x3 << 18)
299
300#define S3C_DxEPCTL_NAKsts (1 << 17)
301#define S3C_DxEPCTL_DPID (1 << 16)
302#define S3C_DxEPCTL_EOFrNum (1 << 16)
303#define S3C_DxEPCTL_USBActEp (1 << 15)
304#define S3C_DxEPCTL_NextEp_MASK (0xf << 11)
305#define S3C_DxEPCTL_NextEp_SHIFT (11)
306#define S3C_DxEPCTL_NextEp_LIMIT (0xf)
307#define S3C_DxEPCTL_NextEp(_x) ((_x) << 11)
308
309#define S3C_DxEPCTL_MPS_MASK (0x7ff << 0)
310#define S3C_DxEPCTL_MPS_SHIFT (0)
311#define S3C_DxEPCTL_MPS_LIMIT (0x7ff)
312#define S3C_DxEPCTL_MPS(_x) ((_x) << 0)
313
314#define S3C_DIEPINT(_a) S3C_HSOTG_REG(0x908 + ((_a) * 0x20))
315#define S3C_DOEPINT(_a) S3C_HSOTG_REG(0xB08 + ((_a) * 0x20))
316
317#define S3C_DxEPINT_INEPNakEff (1 << 6)
318#define S3C_DxEPINT_Back2BackSetup (1 << 6)
319#define S3C_DxEPINT_INTknEPMis (1 << 5)
320#define S3C_DxEPINT_INTknTXFEmp (1 << 4)
321#define S3C_DxEPINT_OUTTknEPdis (1 << 4)
322#define S3C_DxEPINT_Timeout (1 << 3)
323#define S3C_DxEPINT_Setup (1 << 3)
324#define S3C_DxEPINT_AHBErr (1 << 2)
325#define S3C_DxEPINT_EPDisbld (1 << 1)
326#define S3C_DxEPINT_XferCompl (1 << 0)
327
328#define S3C_DIEPTSIZ0 S3C_HSOTG_REG(0x910)
329
330#define S3C_DIEPTSIZ0_PktCnt_MASK (0x3 << 19)
331#define S3C_DIEPTSIZ0_PktCnt_SHIFT (19)
332#define S3C_DIEPTSIZ0_PktCnt_LIMIT (0x3)
333#define S3C_DIEPTSIZ0_PktCnt(_x) ((_x) << 19)
334
335#define S3C_DIEPTSIZ0_XferSize_MASK (0x7f << 0)
336#define S3C_DIEPTSIZ0_XferSize_SHIFT (0)
337#define S3C_DIEPTSIZ0_XferSize_LIMIT (0x7f)
338#define S3C_DIEPTSIZ0_XferSize(_x) ((_x) << 0)
339
340
341#define DOEPTSIZ0 S3C_HSOTG_REG(0xB10)
342#define S3C_DOEPTSIZ0_SUPCnt_MASK (0x3 << 29)
343#define S3C_DOEPTSIZ0_SUPCnt_SHIFT (29)
344#define S3C_DOEPTSIZ0_SUPCnt_LIMIT (0x3)
345#define S3C_DOEPTSIZ0_SUPCnt(_x) ((_x) << 29)
346
347#define S3C_DOEPTSIZ0_PktCnt (1 << 19)
348#define S3C_DOEPTSIZ0_XferSize_MASK (0x7f << 0)
349#define S3C_DOEPTSIZ0_XferSize_SHIFT (0)
350
351#define S3C_DIEPTSIZ(_a) S3C_HSOTG_REG(0x910 + ((_a) * 0x20))
352#define S3C_DOEPTSIZ(_a) S3C_HSOTG_REG(0xB10 + ((_a) * 0x20))
353
354#define S3C_DxEPTSIZ_MC_MASK (0x3 << 29)
355#define S3C_DxEPTSIZ_MC_SHIFT (29)
356#define S3C_DxEPTSIZ_MC_LIMIT (0x3)
357#define S3C_DxEPTSIZ_MC(_x) ((_x) << 29)
358
359#define S3C_DxEPTSIZ_PktCnt_MASK (0x3ff << 19)
360#define S3C_DxEPTSIZ_PktCnt_SHIFT (19)
361#define S3C_DxEPTSIZ_PktCnt_GET(_v) (((_v) >> 19) & 0x3ff)
362#define S3C_DxEPTSIZ_PktCnt_LIMIT (0x3ff)
363#define S3C_DxEPTSIZ_PktCnt(_x) ((_x) << 19)
364
365#define S3C_DxEPTSIZ_XferSize_MASK (0x7ffff << 0)
366#define S3C_DxEPTSIZ_XferSize_SHIFT (0)
367#define S3C_DxEPTSIZ_XferSize_GET(_v) (((_v) >> 0) & 0x7ffff)
368#define S3C_DxEPTSIZ_XferSize_LIMIT (0x7ffff)
369#define S3C_DxEPTSIZ_XferSize(_x) ((_x) << 0)
370
371
372#define S3C_DIEPDMA(_a) S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
373#define S3C_DOEPDMA(_a) S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
374
375#define S3C_EPFIFO(_a) S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
376
377#endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_H */
diff --git a/arch/avr32/kernel/init_task.c b/arch/avr32/kernel/init_task.c
index 993d56ee3cf3..57ec9f2dcd95 100644
--- a/arch/avr32/kernel/init_task.c
+++ b/arch/avr32/kernel/init_task.c
@@ -15,10 +15,6 @@
15 15
16static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 16static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
17static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 17static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
18struct mm_struct init_mm = INIT_MM(init_mm);
19
20EXPORT_SYMBOL(init_mm);
21
22/* 18/*
23 * Initial thread structure. Must be aligned on an 8192-byte boundary. 19 * Initial thread structure. Must be aligned on an 8192-byte boundary.
24 */ 20 */
diff --git a/arch/blackfin/include/asm/kmap_types.h b/arch/blackfin/include/asm/kmap_types.h
index e215f7104974..0a88622339ee 100644
--- a/arch/blackfin/include/asm/kmap_types.h
+++ b/arch/blackfin/include/asm/kmap_types.h
@@ -1,21 +1,6 @@
1#ifndef _ASM_KMAP_TYPES_H 1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H 2#define _ASM_KMAP_TYPES_H
3 3
4enum km_type { 4#include <asm-generic/kmap_types.h>
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20 5
21#endif 6#endif
diff --git a/arch/blackfin/kernel/init_task.c b/arch/blackfin/kernel/init_task.c
index 2c228c020978..c26c34de9f3c 100644
--- a/arch/blackfin/kernel/init_task.c
+++ b/arch/blackfin/kernel/init_task.c
@@ -35,10 +35,6 @@
35 35
36static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 36static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
37static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 37static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
38
39struct mm_struct init_mm = INIT_MM(init_mm);
40EXPORT_SYMBOL(init_mm);
41
42/* 38/*
43 * Initial task structure. 39 * Initial task structure.
44 * 40 *
diff --git a/arch/cris/include/asm/kmap_types.h b/arch/cris/include/asm/kmap_types.h
index 492988cb9077..d2d643c4ea59 100644
--- a/arch/cris/include/asm/kmap_types.h
+++ b/arch/cris/include/asm/kmap_types.h
@@ -5,21 +5,6 @@
5 * is actually used on cris. 5 * is actually used on cris.
6 */ 6 */
7 7
8enum km_type { 8#include <asm-generic/kmap_types.h>
9 KM_BOUNCE_READ,
10 KM_SKB_SUNRPC_DATA,
11 KM_SKB_DATA_SOFTIRQ,
12 KM_USER0,
13 KM_USER1,
14 KM_BIO_SRC_IRQ,
15 KM_BIO_DST_IRQ,
16 KM_PTE0,
17 KM_PTE1,
18 KM_IRQ0,
19 KM_IRQ1,
20 KM_SOFTIRQ0,
21 KM_SOFTIRQ1,
22 KM_TYPE_NR
23};
24 9
25#endif 10#endif
diff --git a/arch/cris/kernel/process.c b/arch/cris/kernel/process.c
index 4df0b320d524..51dcd04d2777 100644
--- a/arch/cris/kernel/process.c
+++ b/arch/cris/kernel/process.c
@@ -38,10 +38,6 @@
38 38
39static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 39static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
40static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 40static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
41struct mm_struct init_mm = INIT_MM(init_mm);
42
43EXPORT_SYMBOL(init_mm);
44
45/* 41/*
46 * Initial thread structure. 42 * Initial thread structure.
47 * 43 *
diff --git a/arch/frv/kernel/init_task.c b/arch/frv/kernel/init_task.c
index 29429a8b7f6a..1d3df1d9495c 100644
--- a/arch/frv/kernel/init_task.c
+++ b/arch/frv/kernel/init_task.c
@@ -12,10 +12,6 @@
12 12
13static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 13static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
14static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 14static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
15struct mm_struct init_mm = INIT_MM(init_mm);
16
17EXPORT_SYMBOL(init_mm);
18
19/* 15/*
20 * Initial thread structure. 16 * Initial thread structure.
21 * 17 *
diff --git a/arch/h8300/include/asm/kmap_types.h b/arch/h8300/include/asm/kmap_types.h
index 1ec8a3427120..be12a7160116 100644
--- a/arch/h8300/include/asm/kmap_types.h
+++ b/arch/h8300/include/asm/kmap_types.h
@@ -1,21 +1,6 @@
1#ifndef _ASM_H8300_KMAP_TYPES_H 1#ifndef _ASM_H8300_KMAP_TYPES_H
2#define _ASM_H8300_KMAP_TYPES_H 2#define _ASM_H8300_KMAP_TYPES_H
3 3
4enum km_type { 4#include <asm-generic/kmap_types.h>
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20 5
21#endif 6#endif
diff --git a/arch/h8300/kernel/init_task.c b/arch/h8300/kernel/init_task.c
index cb5dc552da97..089c65ed6eb3 100644
--- a/arch/h8300/kernel/init_task.c
+++ b/arch/h8300/kernel/init_task.c
@@ -14,10 +14,6 @@
14 14
15static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 15static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
17struct mm_struct init_mm = INIT_MM(init_mm);
18
19EXPORT_SYMBOL(init_mm);
20
21/* 17/*
22 * Initial task structure. 18 * Initial task structure.
23 * 19 *
diff --git a/arch/ia64/hp/common/sba_iommu.c b/arch/ia64/hp/common/sba_iommu.c
index 56ceb68eb99d..fe63b2dc9d07 100644
--- a/arch/ia64/hp/common/sba_iommu.c
+++ b/arch/ia64/hp/common/sba_iommu.c
@@ -1131,7 +1131,7 @@ sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp
1131#ifdef CONFIG_NUMA 1131#ifdef CONFIG_NUMA
1132 { 1132 {
1133 struct page *page; 1133 struct page *page;
1134 page = alloc_pages_node(ioc->node == MAX_NUMNODES ? 1134 page = alloc_pages_exact_node(ioc->node == MAX_NUMNODES ?
1135 numa_node_id() : ioc->node, flags, 1135 numa_node_id() : ioc->node, flags,
1136 get_order(size)); 1136 get_order(size));
1137 1137
diff --git a/arch/ia64/include/asm/kmap_types.h b/arch/ia64/include/asm/kmap_types.h
index 5d1658aa2b3b..05d5f9996105 100644
--- a/arch/ia64/include/asm/kmap_types.h
+++ b/arch/ia64/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
1#ifndef _ASM_IA64_KMAP_TYPES_H 1#ifndef _ASM_IA64_KMAP_TYPES_H
2#define _ASM_IA64_KMAP_TYPES_H 2#define _ASM_IA64_KMAP_TYPES_H
3 3
4
5#ifdef CONFIG_DEBUG_HIGHMEM 4#ifdef CONFIG_DEBUG_HIGHMEM
6# define D(n) __KM_FENCE_##n , 5#define __WITH_KM_FENCE
7#else
8# define D(n)
9#endif 6#endif
10 7
11enum km_type { 8#include <asm-generic/kmap_types.h>
12D(0) KM_BOUNCE_READ,
13D(1) KM_SKB_SUNRPC_DATA,
14D(2) KM_SKB_DATA_SOFTIRQ,
15D(3) KM_USER0,
16D(4) KM_USER1,
17D(5) KM_BIO_SRC_IRQ,
18D(6) KM_BIO_DST_IRQ,
19D(7) KM_PTE0,
20D(8) KM_PTE1,
21D(9) KM_IRQ0,
22D(10) KM_IRQ1,
23D(11) KM_SOFTIRQ0,
24D(12) KM_SOFTIRQ1,
25D(13) KM_TYPE_NR
26};
27 9
28#undef D 10#undef __WITH_KM_FENCE
29 11
30#endif /* _ASM_IA64_KMAP_TYPES_H */ 12#endif /* _ASM_IA64_KMAP_TYPES_H */
diff --git a/arch/ia64/kernel/init_task.c b/arch/ia64/kernel/init_task.c
index 5b0e830c6f33..c475fc281be7 100644
--- a/arch/ia64/kernel/init_task.c
+++ b/arch/ia64/kernel/init_task.c
@@ -19,10 +19,6 @@
19 19
20static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 20static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
21static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 21static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
22struct mm_struct init_mm = INIT_MM(init_mm);
23
24EXPORT_SYMBOL(init_mm);
25
26/* 22/*
27 * Initial task structure. 23 * Initial task structure.
28 * 24 *
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 8f33a8840422..5b17bd402275 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -1829,8 +1829,7 @@ ia64_mca_cpu_init(void *cpu_data)
1829 data = mca_bootmem(); 1829 data = mca_bootmem();
1830 first_time = 0; 1830 first_time = 0;
1831 } else 1831 } else
1832 data = page_address(alloc_pages_node(numa_node_id(), 1832 data = __get_free_pages(GFP_KERNEL, get_order(sz));
1833 GFP_KERNEL, get_order(sz)));
1834 if (!data) 1833 if (!data)
1835 panic("Could not allocate MCA memory for cpu %d\n", 1834 panic("Could not allocate MCA memory for cpu %d\n",
1836 cpu); 1835 cpu);
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 8a06dc480594..bdc176cb5e85 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -5595,7 +5595,7 @@ pfm_interrupt_handler(int irq, void *arg)
5595 (*pfm_alt_intr_handler->handler)(irq, arg, regs); 5595 (*pfm_alt_intr_handler->handler)(irq, arg, regs);
5596 } 5596 }
5597 5597
5598 put_cpu_no_resched(); 5598 put_cpu();
5599 return IRQ_HANDLED; 5599 return IRQ_HANDLED;
5600} 5600}
5601 5601
diff --git a/arch/ia64/kernel/uncached.c b/arch/ia64/kernel/uncached.c
index 8eff8c1d40a6..6ba72ab42fcc 100644
--- a/arch/ia64/kernel/uncached.c
+++ b/arch/ia64/kernel/uncached.c
@@ -98,7 +98,8 @@ static int uncached_add_chunk(struct uncached_pool *uc_pool, int nid)
98 98
99 /* attempt to allocate a granule's worth of cached memory pages */ 99 /* attempt to allocate a granule's worth of cached memory pages */
100 100
101 page = alloc_pages_node(nid, GFP_KERNEL | __GFP_ZERO | GFP_THISNODE, 101 page = alloc_pages_exact_node(nid,
102 GFP_KERNEL | __GFP_ZERO | GFP_THISNODE,
102 IA64_GRANULE_SHIFT-PAGE_SHIFT); 103 IA64_GRANULE_SHIFT-PAGE_SHIFT);
103 if (!page) { 104 if (!page) {
104 mutex_unlock(&uc_pool->add_chunk_mutex); 105 mutex_unlock(&uc_pool->add_chunk_mutex);
diff --git a/arch/ia64/sn/pci/pci_dma.c b/arch/ia64/sn/pci/pci_dma.c
index d876423e4e75..98b684928e12 100644
--- a/arch/ia64/sn/pci/pci_dma.c
+++ b/arch/ia64/sn/pci/pci_dma.c
@@ -90,7 +90,8 @@ static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
90 */ 90 */
91 node = pcibus_to_node(pdev->bus); 91 node = pcibus_to_node(pdev->bus);
92 if (likely(node >=0)) { 92 if (likely(node >=0)) {
93 struct page *p = alloc_pages_node(node, flags, get_order(size)); 93 struct page *p = alloc_pages_exact_node(node,
94 flags, get_order(size));
94 95
95 if (likely(p)) 96 if (likely(p))
96 cpuaddr = page_address(p); 97 cpuaddr = page_address(p);
diff --git a/arch/m32r/include/asm/kmap_types.h b/arch/m32r/include/asm/kmap_types.h
index fa94dc6410ea..4cdb5e3a06bf 100644
--- a/arch/m32r/include/asm/kmap_types.h
+++ b/arch/m32r/include/asm/kmap_types.h
@@ -2,28 +2,11 @@
2#define __M32R_KMAP_TYPES_H 2#define __M32R_KMAP_TYPES_H
3 3
4#ifdef CONFIG_DEBUG_HIGHMEM 4#ifdef CONFIG_DEBUG_HIGHMEM
5# define D(n) __KM_FENCE_##n , 5#define __WITH_KM_FENCE
6#else
7# define D(n)
8#endif 6#endif
9 7
10enum km_type { 8#include <asm-generic/kmap_types.h>
11D(0) KM_BOUNCE_READ,
12D(1) KM_SKB_SUNRPC_DATA,
13D(2) KM_SKB_DATA_SOFTIRQ,
14D(3) KM_USER0,
15D(4) KM_USER1,
16D(5) KM_BIO_SRC_IRQ,
17D(6) KM_BIO_DST_IRQ,
18D(7) KM_PTE0,
19D(8) KM_PTE1,
20D(9) KM_IRQ0,
21D(10) KM_IRQ1,
22D(11) KM_SOFTIRQ0,
23D(12) KM_SOFTIRQ1,
24D(13) KM_TYPE_NR
25};
26 9
27#undef D 10#undef __WITH_KM_FENCE
28 11
29#endif /* __M32R_KMAP_TYPES_H */ 12#endif /* __M32R_KMAP_TYPES_H */
diff --git a/arch/m32r/kernel/init_task.c b/arch/m32r/kernel/init_task.c
index 016885c6f260..fce57e5d3f91 100644
--- a/arch/m32r/kernel/init_task.c
+++ b/arch/m32r/kernel/init_task.c
@@ -13,10 +13,6 @@
13 13
14static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 14static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
15static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 15static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
16struct mm_struct init_mm = INIT_MM(init_mm);
17
18EXPORT_SYMBOL(init_mm);
19
20/* 16/*
21 * Initial thread structure. 17 * Initial thread structure.
22 * 18 *
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index 7daf897292cf..b7a78ad429b7 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -154,9 +154,9 @@ unsigned long __init zone_sizes_init(void)
154 * Use all area of internal RAM. 154 * Use all area of internal RAM.
155 * see __alloc_pages() 155 * see __alloc_pages()
156 */ 156 */
157 NODE_DATA(1)->node_zones->pages_min = 0; 157 NODE_DATA(1)->node_zones->watermark[WMARK_MIN] = 0;
158 NODE_DATA(1)->node_zones->pages_low = 0; 158 NODE_DATA(1)->node_zones->watermark[WMARK_LOW] = 0;
159 NODE_DATA(1)->node_zones->pages_high = 0; 159 NODE_DATA(1)->node_zones->watermark[WMARK_HIGH] = 0;
160 160
161 return holes; 161 return holes;
162} 162}
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 98138b4e9220..922fdfdadeaa 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -63,7 +63,7 @@ static void shutdown_m32104ut_irq(unsigned int irq)
63 outl(M32R_ICUCR_ILEVEL7, port); 63 outl(M32R_ICUCR_ILEVEL7, port);
64} 64}
65 65
66static struct hw_interrupt_type m32104ut_irq_type = 66static struct irq_chip m32104ut_irq_type =
67{ 67{
68 .typename = "M32104UT-IRQ", 68 .typename = "M32104UT-IRQ",
69 .startup = startup_m32104ut_irq, 69 .startup = startup_m32104ut_irq,
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 77b0ae9379e9..9c1bc7487c1e 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -69,7 +69,7 @@ static void shutdown_m32700ut_irq(unsigned int irq)
69 outl(M32R_ICUCR_ILEVEL7, port); 69 outl(M32R_ICUCR_ILEVEL7, port);
70} 70}
71 71
72static struct hw_interrupt_type m32700ut_irq_type = 72static struct irq_chip m32700ut_irq_type =
73{ 73{
74 .typename = "M32700UT-IRQ", 74 .typename = "M32700UT-IRQ",
75 .startup = startup_m32700ut_irq, 75 .startup = startup_m32700ut_irq,
@@ -146,7 +146,7 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq)
146 outw(PLD_ICUCR_ILEVEL7, port); 146 outw(PLD_ICUCR_ILEVEL7, port);
147} 147}
148 148
149static struct hw_interrupt_type m32700ut_pld_irq_type = 149static struct irq_chip m32700ut_pld_irq_type =
150{ 150{
151 .typename = "M32700UT-PLD-IRQ", 151 .typename = "M32700UT-PLD-IRQ",
152 .startup = startup_m32700ut_pld_irq, 152 .startup = startup_m32700ut_pld_irq,
@@ -215,7 +215,7 @@ static void shutdown_m32700ut_lanpld_irq(unsigned int irq)
215 outw(PLD_ICUCR_ILEVEL7, port); 215 outw(PLD_ICUCR_ILEVEL7, port);
216} 216}
217 217
218static struct hw_interrupt_type m32700ut_lanpld_irq_type = 218static struct irq_chip m32700ut_lanpld_irq_type =
219{ 219{
220 .typename = "M32700UT-PLD-LAN-IRQ", 220 .typename = "M32700UT-PLD-LAN-IRQ",
221 .startup = startup_m32700ut_lanpld_irq, 221 .startup = startup_m32700ut_lanpld_irq,
@@ -284,7 +284,7 @@ static void shutdown_m32700ut_lcdpld_irq(unsigned int irq)
284 outw(PLD_ICUCR_ILEVEL7, port); 284 outw(PLD_ICUCR_ILEVEL7, port);
285} 285}
286 286
287static struct hw_interrupt_type m32700ut_lcdpld_irq_type = 287static struct irq_chip m32700ut_lcdpld_irq_type =
288{ 288{
289 .typename = "M32700UT-PLD-LCD-IRQ", 289 .typename = "M32700UT-PLD-LCD-IRQ",
290 .startup = startup_m32700ut_lcdpld_irq, 290 .startup = startup_m32700ut_lcdpld_irq,
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index 3ec087ff2214..fb4b17799b66 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -63,7 +63,7 @@ static void shutdown_mappi_irq(unsigned int irq)
63 outl(M32R_ICUCR_ILEVEL7, port); 63 outl(M32R_ICUCR_ILEVEL7, port);
64} 64}
65 65
66static struct hw_interrupt_type mappi_irq_type = 66static struct irq_chip mappi_irq_type =
67{ 67{
68 .typename = "MAPPI-IRQ", 68 .typename = "MAPPI-IRQ",
69 .startup = startup_mappi_irq, 69 .startup = startup_mappi_irq,
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index d87969c6356e..6a65eda0a056 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -70,7 +70,7 @@ static void shutdown_mappi2_irq(unsigned int irq)
70 outl(M32R_ICUCR_ILEVEL7, port); 70 outl(M32R_ICUCR_ILEVEL7, port);
71} 71}
72 72
73static struct hw_interrupt_type mappi2_irq_type = 73static struct irq_chip mappi2_irq_type =
74{ 74{
75 .typename = "MAPPI2-IRQ", 75 .typename = "MAPPI2-IRQ",
76 .startup = startup_mappi2_irq, 76 .startup = startup_mappi2_irq,
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index 785b4bd6d9fd..9c337aeac94b 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -70,7 +70,7 @@ static void shutdown_mappi3_irq(unsigned int irq)
70 outl(M32R_ICUCR_ILEVEL7, port); 70 outl(M32R_ICUCR_ILEVEL7, port);
71} 71}
72 72
73static struct hw_interrupt_type mappi3_irq_type = 73static struct irq_chip mappi3_irq_type =
74{ 74{
75 .typename = "MAPPI3-IRQ", 75 .typename = "MAPPI3-IRQ",
76 .startup = startup_mappi3_irq, 76 .startup = startup_mappi3_irq,
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index 6faa5db68e95..ed865741c38d 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -61,7 +61,7 @@ static void shutdown_oaks32r_irq(unsigned int irq)
61 outl(M32R_ICUCR_ILEVEL7, port); 61 outl(M32R_ICUCR_ILEVEL7, port);
62} 62}
63 63
64static struct hw_interrupt_type oaks32r_irq_type = 64static struct irq_chip oaks32r_irq_type =
65{ 65{
66 .typename = "OAKS32R-IRQ", 66 .typename = "OAKS32R-IRQ",
67 .startup = startup_oaks32r_irq, 67 .startup = startup_oaks32r_irq,
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index fab13fd85422..80d680657019 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -70,7 +70,7 @@ static void shutdown_opsput_irq(unsigned int irq)
70 outl(M32R_ICUCR_ILEVEL7, port); 70 outl(M32R_ICUCR_ILEVEL7, port);
71} 71}
72 72
73static struct hw_interrupt_type opsput_irq_type = 73static struct irq_chip opsput_irq_type =
74{ 74{
75 .typename = "OPSPUT-IRQ", 75 .typename = "OPSPUT-IRQ",
76 .startup = startup_opsput_irq, 76 .startup = startup_opsput_irq,
@@ -147,7 +147,7 @@ static void shutdown_opsput_pld_irq(unsigned int irq)
147 outw(PLD_ICUCR_ILEVEL7, port); 147 outw(PLD_ICUCR_ILEVEL7, port);
148} 148}
149 149
150static struct hw_interrupt_type opsput_pld_irq_type = 150static struct irq_chip opsput_pld_irq_type =
151{ 151{
152 .typename = "OPSPUT-PLD-IRQ", 152 .typename = "OPSPUT-PLD-IRQ",
153 .startup = startup_opsput_pld_irq, 153 .startup = startup_opsput_pld_irq,
@@ -216,7 +216,7 @@ static void shutdown_opsput_lanpld_irq(unsigned int irq)
216 outw(PLD_ICUCR_ILEVEL7, port); 216 outw(PLD_ICUCR_ILEVEL7, port);
217} 217}
218 218
219static struct hw_interrupt_type opsput_lanpld_irq_type = 219static struct irq_chip opsput_lanpld_irq_type =
220{ 220{
221 .typename = "OPSPUT-PLD-LAN-IRQ", 221 .typename = "OPSPUT-PLD-LAN-IRQ",
222 .startup = startup_opsput_lanpld_irq, 222 .startup = startup_opsput_lanpld_irq,
@@ -285,7 +285,7 @@ static void shutdown_opsput_lcdpld_irq(unsigned int irq)
285 outw(PLD_ICUCR_ILEVEL7, port); 285 outw(PLD_ICUCR_ILEVEL7, port);
286} 286}
287 287
288static struct hw_interrupt_type opsput_lcdpld_irq_type = 288static struct irq_chip opsput_lcdpld_irq_type =
289{ 289{
290 "OPSPUT-PLD-LCD-IRQ", 290 "OPSPUT-PLD-LCD-IRQ",
291 startup_opsput_lcdpld_irq, 291 startup_opsput_lcdpld_irq,
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index 89588d649eb7..757302660af8 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -61,7 +61,7 @@ static void shutdown_mappi_irq(unsigned int irq)
61 outl(M32R_ICUCR_ILEVEL7, port); 61 outl(M32R_ICUCR_ILEVEL7, port);
62} 62}
63 63
64static struct hw_interrupt_type mappi_irq_type = 64static struct irq_chip mappi_irq_type =
65{ 65{
66 .typename = "M32700-IRQ", 66 .typename = "M32700-IRQ",
67 .startup = startup_mappi_irq, 67 .startup = startup_mappi_irq,
@@ -134,7 +134,7 @@ static void shutdown_m32700ut_pld_irq(unsigned int irq)
134 outw(PLD_ICUCR_ILEVEL7, port); 134 outw(PLD_ICUCR_ILEVEL7, port);
135} 135}
136 136
137static struct hw_interrupt_type m32700ut_pld_irq_type = 137static struct irq_chip m32700ut_pld_irq_type =
138{ 138{
139 .typename = "USRV-PLD-IRQ", 139 .typename = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq, 140 .startup = startup_m32700ut_pld_irq,
diff --git a/arch/m68k/include/asm/kmap_types.h b/arch/m68k/include/asm/kmap_types.h
index c843c63d3801..3413cc1390ec 100644
--- a/arch/m68k/include/asm/kmap_types.h
+++ b/arch/m68k/include/asm/kmap_types.h
@@ -1,21 +1,6 @@
1#ifndef __ASM_M68K_KMAP_TYPES_H 1#ifndef __ASM_M68K_KMAP_TYPES_H
2#define __ASM_M68K_KMAP_TYPES_H 2#define __ASM_M68K_KMAP_TYPES_H
3 3
4enum km_type { 4#include <asm-generic/kmap_types.h>
5 KM_BOUNCE_READ,
6 KM_SKB_SUNRPC_DATA,
7 KM_SKB_DATA_SOFTIRQ,
8 KM_USER0,
9 KM_USER1,
10 KM_BIO_SRC_IRQ,
11 KM_BIO_DST_IRQ,
12 KM_PTE0,
13 KM_PTE1,
14 KM_IRQ0,
15 KM_IRQ1,
16 KM_SOFTIRQ0,
17 KM_SOFTIRQ1,
18 KM_TYPE_NR
19};
20 5
21#endif /* __ASM_M68K_KMAP_TYPES_H */ 6#endif /* __ASM_M68K_KMAP_TYPES_H */
diff --git a/arch/m68k/kernel/process.c b/arch/m68k/kernel/process.c
index ec37fb56c127..72bad65dba3a 100644
--- a/arch/m68k/kernel/process.c
+++ b/arch/m68k/kernel/process.c
@@ -42,10 +42,6 @@
42 */ 42 */
43static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 43static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
44static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 44static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
45struct mm_struct init_mm = INIT_MM(init_mm);
46
47EXPORT_SYMBOL(init_mm);
48
49union thread_union init_thread_union 45union thread_union init_thread_union
50__attribute__((section(".data.init_task"), aligned(THREAD_SIZE))) 46__attribute__((section(".data.init_task"), aligned(THREAD_SIZE)))
51 = { INIT_THREAD_INFO(init_task) }; 47 = { INIT_THREAD_INFO(init_task) };
diff --git a/arch/m68knommu/kernel/init_task.c b/arch/m68knommu/kernel/init_task.c
index fe282de1d596..45e97a207fed 100644
--- a/arch/m68knommu/kernel/init_task.c
+++ b/arch/m68knommu/kernel/init_task.c
@@ -14,10 +14,6 @@
14 14
15static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 15static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 16static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
17struct mm_struct init_mm = INIT_MM(init_mm);
18
19EXPORT_SYMBOL(init_mm);
20
21/* 17/*
22 * Initial task structure. 18 * Initial task structure.
23 * 19 *
diff --git a/arch/microblaze/include/asm/kmap_types.h b/arch/microblaze/include/asm/kmap_types.h
index 4d7e222f5dd7..25975252d83d 100644
--- a/arch/microblaze/include/asm/kmap_types.h
+++ b/arch/microblaze/include/asm/kmap_types.h
@@ -1,29 +1,6 @@
1/*
2 * Copyright (C) 2006 Atmark Techno, Inc.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8
9#ifndef _ASM_MICROBLAZE_KMAP_TYPES_H 1#ifndef _ASM_MICROBLAZE_KMAP_TYPES_H
10#define _ASM_MICROBLAZE_KMAP_TYPES_H 2#define _ASM_MICROBLAZE_KMAP_TYPES_H
11 3
12enum km_type { 4#include <asm-generic/kmap_types.h>
13 KM_BOUNCE_READ,
14 KM_SKB_SUNRPC_DATA,
15 KM_SKB_DATA_SOFTIRQ,
16 KM_USER0,
17 KM_USER1,
18 KM_BIO_SRC_IRQ,
19 KM_BIO_DST_IRQ,
20 KM_PTE0,
21 KM_PTE1,
22 KM_IRQ0,
23 KM_IRQ1,
24 KM_SOFTIRQ0,
25 KM_SOFTIRQ1,
26 KM_TYPE_NR,
27};
28 5
29#endif /* _ASM_MICROBLAZE_KMAP_TYPES_H */ 6#endif /* _ASM_MICROBLAZE_KMAP_TYPES_H */
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 25f3b0a11ca8..b29f0280d712 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -618,6 +618,8 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
618 select SYS_HAS_EARLY_PRINTK 618 select SYS_HAS_EARLY_PRINTK
619 select SYS_HAS_CPU_CAVIUM_OCTEON 619 select SYS_HAS_CPU_CAVIUM_OCTEON
620 select SWAP_IO_SPACE 620 select SWAP_IO_SPACE
621 select HW_HAS_PCI
622 select ARCH_SUPPORTS_MSI
621 help 623 help
622 This option supports all of the Octeon reference boards from Cavium 624 This option supports all of the Octeon reference boards from Cavium
623 Networks. It builds a kernel that dynamically determines the Octeon 625 Networks. It builds a kernel that dynamically determines the Octeon
@@ -851,6 +853,11 @@ config SYS_SUPPORTS_BIG_ENDIAN
851config SYS_SUPPORTS_LITTLE_ENDIAN 853config SYS_SUPPORTS_LITTLE_ENDIAN
852 bool 854 bool
853 855
856config SYS_SUPPORTS_HUGETLBFS
857 bool
858 depends on CPU_SUPPORTS_HUGEPAGES && 64BIT
859 default y
860
854config IRQ_CPU 861config IRQ_CPU
855 bool 862 bool
856 863
@@ -1055,6 +1062,7 @@ config CPU_MIPS64_R1
1055 select CPU_SUPPORTS_32BIT_KERNEL 1062 select CPU_SUPPORTS_32BIT_KERNEL
1056 select CPU_SUPPORTS_64BIT_KERNEL 1063 select CPU_SUPPORTS_64BIT_KERNEL
1057 select CPU_SUPPORTS_HIGHMEM 1064 select CPU_SUPPORTS_HIGHMEM
1065 select CPU_SUPPORTS_HUGEPAGES
1058 help 1066 help
1059 Choose this option to build a kernel for release 1 or later of the 1067 Choose this option to build a kernel for release 1 or later of the
1060 MIPS64 architecture. Many modern embedded systems with a 64-bit 1068 MIPS64 architecture. Many modern embedded systems with a 64-bit
@@ -1074,6 +1082,7 @@ config CPU_MIPS64_R2
1074 select CPU_SUPPORTS_32BIT_KERNEL 1082 select CPU_SUPPORTS_32BIT_KERNEL
1075 select CPU_SUPPORTS_64BIT_KERNEL 1083 select CPU_SUPPORTS_64BIT_KERNEL
1076 select CPU_SUPPORTS_HIGHMEM 1084 select CPU_SUPPORTS_HIGHMEM
1085 select CPU_SUPPORTS_HUGEPAGES
1077 help 1086 help
1078 Choose this option to build a kernel for release 2 or later of the 1087 Choose this option to build a kernel for release 2 or later of the
1079 MIPS64 architecture. Many modern embedded systems with a 64-bit 1088 MIPS64 architecture. Many modern embedded systems with a 64-bit
@@ -1160,6 +1169,7 @@ config CPU_R5500
1160 select CPU_HAS_LLSC 1169 select CPU_HAS_LLSC
1161 select CPU_SUPPORTS_32BIT_KERNEL 1170 select CPU_SUPPORTS_32BIT_KERNEL
1162 select CPU_SUPPORTS_64BIT_KERNEL 1171 select CPU_SUPPORTS_64BIT_KERNEL
1172 select CPU_SUPPORTS_HUGEPAGES
1163 help 1173 help
1164 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV 1174 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1165 instruction set. 1175 instruction set.
@@ -1245,6 +1255,7 @@ config CPU_CAVIUM_OCTEON
1245 select WEAK_ORDERING 1255 select WEAK_ORDERING
1246 select WEAK_REORDERING_BEYOND_LLSC 1256 select WEAK_REORDERING_BEYOND_LLSC
1247 select CPU_SUPPORTS_HIGHMEM 1257 select CPU_SUPPORTS_HIGHMEM
1258 select CPU_SUPPORTS_HUGEPAGES
1248 help 1259 help
1249 The Cavium Octeon processor is a highly integrated chip containing 1260 The Cavium Octeon processor is a highly integrated chip containing
1250 many ethernet hardware widgets for networking tasks. The processor 1261 many ethernet hardware widgets for networking tasks. The processor
@@ -1364,6 +1375,8 @@ config CPU_SUPPORTS_32BIT_KERNEL
1364 bool 1375 bool
1365config CPU_SUPPORTS_64BIT_KERNEL 1376config CPU_SUPPORTS_64BIT_KERNEL
1366 bool 1377 bool
1378config CPU_SUPPORTS_HUGEPAGES
1379 bool
1367 1380
1368# 1381#
1369# Set to y for ptrace access to watch registers. 1382# Set to y for ptrace access to watch registers.
@@ -2121,6 +2134,10 @@ endmenu
2121 2134
2122menu "Power management options" 2135menu "Power management options"
2123 2136
2137config ARCH_HIBERNATION_POSSIBLE
2138 def_bool y
2139 depends on !SMP
2140
2124config ARCH_SUSPEND_POSSIBLE 2141config ARCH_SUSPEND_POSSIBLE
2125 def_bool y 2142 def_bool y
2126 depends on !SMP 2143 depends on !SMP
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index c4cae9e6b802..807572a6a4d2 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -167,7 +167,6 @@ libs-$(CONFIG_ARC) += arch/mips/fw/arc/
167libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ 167libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
168libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ 168libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/
169libs-y += arch/mips/fw/lib/ 169libs-y += arch/mips/fw/lib/
170libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
171 170
172# 171#
173# Board-dependent options and extra files 172# Board-dependent options and extra files
@@ -184,7 +183,6 @@ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000
184# Common Alchemy Au1x00 stuff 183# Common Alchemy Au1x00 stuff
185# 184#
186core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/ 185core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/
187cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
188 186
189# 187#
190# AMD Alchemy Pb1000 eval board 188# AMD Alchemy Pb1000 eval board
@@ -282,6 +280,10 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000
282libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/ 280libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/
283load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 281load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
284 282
283# must be last for Alchemy systems for GPIO to work properly
284cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
285
286
285# 287#
286# Cobalt Server 288# Cobalt Server
287# 289#
@@ -675,6 +677,9 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
675 677
676drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 678drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
677 679
680# suspend and hibernation support
681drivers-$(CONFIG_PM) += arch/mips/power/
682
678ifdef CONFIG_LASAT 683ifdef CONFIG_LASAT
679rom.bin rom.sw: vmlinux 684rom.bin rom.sw: vmlinux
680 $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ 685 $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index 8128aebfb155..00b498e97c83 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -1,3 +1,14 @@
1# au1000-style gpio
2config ALCHEMY_GPIO_AU1000
3 bool
4
5# select this in your board config if you don't want to use the gpio
6# namespace as documented in the manuals. In this case however you need
7# to create the necessary gpio_* functions in your board code/headers!
8# see arch/mips/include/asm/mach-au1x00/gpio.h for more information.
9config ALCHEMY_GPIO_INDIRECT
10 def_bool n
11
1choice 12choice
2 prompt "Machine type" 13 prompt "Machine type"
3 depends on MACH_ALCHEMY 14 depends on MACH_ALCHEMY
@@ -108,22 +119,27 @@ endchoice
108config SOC_AU1000 119config SOC_AU1000
109 bool 120 bool
110 select SOC_AU1X00 121 select SOC_AU1X00
122 select ALCHEMY_GPIO_AU1000
111 123
112config SOC_AU1100 124config SOC_AU1100
113 bool 125 bool
114 select SOC_AU1X00 126 select SOC_AU1X00
127 select ALCHEMY_GPIO_AU1000
115 128
116config SOC_AU1500 129config SOC_AU1500
117 bool 130 bool
118 select SOC_AU1X00 131 select SOC_AU1X00
132 select ALCHEMY_GPIO_AU1000
119 133
120config SOC_AU1550 134config SOC_AU1550
121 bool 135 bool
122 select SOC_AU1X00 136 select SOC_AU1X00
137 select ALCHEMY_GPIO_AU1000
123 138
124config SOC_AU1200 139config SOC_AU1200
125 bool 140 bool
126 select SOC_AU1X00 141 select SOC_AU1X00
142 select ALCHEMY_GPIO_AU1000
127 143
128config SOC_AU1X00 144config SOC_AU1X00
129 bool 145 bool
@@ -134,4 +150,5 @@ config SOC_AU1X00
134 select SYS_HAS_CPU_MIPS32_R1 150 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 151 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 152 select SYS_SUPPORTS_APM_EMULATION
137 select ARCH_REQUIRE_GPIOLIB 153 select GENERIC_GPIO
154 select ARCH_WANT_OPTIONAL_GPIOLIB
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index d50d4764eafe..b67fb512529d 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -7,7 +7,14 @@
7 7
8obj-y += prom.o irq.o puts.o time.o reset.o \ 8obj-y += prom.o irq.o puts.o time.o reset.o \
9 clocks.o platform.o power.o setup.o \ 9 clocks.o platform.o power.o setup.o \
10 sleeper.o dma.o dbdma.o gpio.o 10 sleeper.o dma.o dbdma.o
11
12# optional gpiolib support
13ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
14 ifeq ($(CONFIG_GPIOLIB),y)
15 obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o
16 endif
17endif
11 18
12obj-$(CONFIG_PCI) += pci.o 19obj-$(CONFIG_PCI) += pci.o
13 20
diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c
deleted file mode 100644
index 91a9c4436c39..000000000000
--- a/arch/mips/alchemy/common/gpio.c
+++ /dev/null
@@ -1,201 +0,0 @@
1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * Architecture specific GPIO support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO line : GPIO1
27 * others have a second one : GPIO2
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
35
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/gpio.h>
38
39struct au1000_gpio_chip {
40 struct gpio_chip chip;
41 void __iomem *regbase;
42};
43
44#if !defined(CONFIG_SOC_AU1000)
45static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
46{
47 u32 mask = 1 << offset;
48 struct au1000_gpio_chip *gpch;
49
50 gpch = container_of(chip, struct au1000_gpio_chip, chip);
51 return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
52}
53
54static void au1000_gpio2_set(struct gpio_chip *chip,
55 unsigned offset, int value)
56{
57 u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
58 struct au1000_gpio_chip *gpch;
59 unsigned long flags;
60
61 gpch = container_of(chip, struct au1000_gpio_chip, chip);
62
63 local_irq_save(flags);
64 writel(mask, gpch->regbase + AU1000_GPIO2_OUT);
65 local_irq_restore(flags);
66}
67
68static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
69{
70 u32 mask = 1 << offset;
71 u32 tmp;
72 struct au1000_gpio_chip *gpch;
73 unsigned long flags;
74
75 gpch = container_of(chip, struct au1000_gpio_chip, chip);
76
77 local_irq_save(flags);
78 tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
79 tmp &= ~mask;
80 writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
81 local_irq_restore(flags);
82
83 return 0;
84}
85
86static int au1000_gpio2_direction_output(struct gpio_chip *chip,
87 unsigned offset, int value)
88{
89 u32 mask = 1 << offset;
90 u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset));
91 u32 tmp;
92 struct au1000_gpio_chip *gpch;
93 unsigned long flags;
94
95 gpch = container_of(chip, struct au1000_gpio_chip, chip);
96
97 local_irq_save(flags);
98 tmp = readl(gpch->regbase + AU1000_GPIO2_DIR);
99 tmp |= mask;
100 writel(tmp, gpch->regbase + AU1000_GPIO2_DIR);
101 writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT);
102 local_irq_restore(flags);
103
104 return 0;
105}
106#endif /* !defined(CONFIG_SOC_AU1000) */
107
108static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
109{
110 u32 mask = 1 << offset;
111 struct au1000_gpio_chip *gpch;
112
113 gpch = container_of(chip, struct au1000_gpio_chip, chip);
114 return readl(gpch->regbase + AU1000_GPIO1_ST) & mask;
115}
116
117static void au1000_gpio1_set(struct gpio_chip *chip,
118 unsigned offset, int value)
119{
120 u32 mask = 1 << offset;
121 u32 reg_offset;
122 struct au1000_gpio_chip *gpch;
123 unsigned long flags;
124
125 gpch = container_of(chip, struct au1000_gpio_chip, chip);
126
127 if (value)
128 reg_offset = AU1000_GPIO1_OUT;
129 else
130 reg_offset = AU1000_GPIO1_CLR;
131
132 local_irq_save(flags);
133 writel(mask, gpch->regbase + reg_offset);
134 local_irq_restore(flags);
135}
136
137static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
138{
139 u32 mask = 1 << offset;
140 struct au1000_gpio_chip *gpch;
141
142 gpch = container_of(chip, struct au1000_gpio_chip, chip);
143 writel(mask, gpch->regbase + AU1000_GPIO1_ST);
144
145 return 0;
146}
147
148static int au1000_gpio1_direction_output(struct gpio_chip *chip,
149 unsigned offset, int value)
150{
151 u32 mask = 1 << offset;
152 struct au1000_gpio_chip *gpch;
153
154 gpch = container_of(chip, struct au1000_gpio_chip, chip);
155
156 writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT);
157 au1000_gpio1_set(chip, offset, value);
158
159 return 0;
160}
161
162struct au1000_gpio_chip au1000_gpio_chip[] = {
163 [0] = {
164 .regbase = (void __iomem *)SYS_BASE,
165 .chip = {
166 .label = "au1000-gpio1",
167 .direction_input = au1000_gpio1_direction_input,
168 .direction_output = au1000_gpio1_direction_output,
169 .get = au1000_gpio1_get,
170 .set = au1000_gpio1_set,
171 .base = 0,
172 .ngpio = 32,
173 },
174 },
175#if !defined(CONFIG_SOC_AU1000)
176 [1] = {
177 .regbase = (void __iomem *)GPIO2_BASE,
178 .chip = {
179 .label = "au1000-gpio2",
180 .direction_input = au1000_gpio2_direction_input,
181 .direction_output = au1000_gpio2_direction_output,
182 .get = au1000_gpio2_get,
183 .set = au1000_gpio2_set,
184 .base = AU1XXX_GPIO_BASE,
185 .ngpio = 32,
186 },
187 },
188#endif
189};
190
191static int __init au1000_gpio_init(void)
192{
193 gpiochip_add(&au1000_gpio_chip[0].chip);
194#if !defined(CONFIG_SOC_AU1000)
195 gpiochip_add(&au1000_gpio_chip[1].chip);
196#endif
197
198 return 0;
199}
200arch_initcall(au1000_gpio_init);
201
diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
new file mode 100644
index 000000000000..1bfa91f939f4
--- /dev/null
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -0,0 +1,130 @@
1/*
2 * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
3 * GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Notes :
26 * au1000 SoC have only one GPIO block : GPIO1
27 * Au1100, Au15x0, Au12x0 have a second one : GPIO2
28 */
29
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/platform_device.h>
34#include <linux/gpio.h>
35
36#include <asm/mach-au1x00/au1000.h>
37#include <asm/mach-au1x00/gpio.h>
38
39#if !defined(CONFIG_SOC_AU1000)
40static int gpio2_get(struct gpio_chip *chip, unsigned offset)
41{
42 return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
43}
44
45static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
46{
47 alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
48}
49
50static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
51{
52 return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
53}
54
55static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
56 int value)
57{
58 return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
59 value);
60}
61
62static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
63{
64 return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
65}
66#endif /* !defined(CONFIG_SOC_AU1000) */
67
68static int gpio1_get(struct gpio_chip *chip, unsigned offset)
69{
70 return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
71}
72
73static void gpio1_set(struct gpio_chip *chip,
74 unsigned offset, int value)
75{
76 alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
77}
78
79static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
80{
81 return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
82}
83
84static int gpio1_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
86{
87 return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
88 value);
89}
90
91static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
92{
93 return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
94}
95
96struct gpio_chip alchemy_gpio_chip[] = {
97 [0] = {
98 .label = "alchemy-gpio1",
99 .direction_input = gpio1_direction_input,
100 .direction_output = gpio1_direction_output,
101 .get = gpio1_get,
102 .set = gpio1_set,
103 .to_irq = gpio1_to_irq,
104 .base = ALCHEMY_GPIO1_BASE,
105 .ngpio = ALCHEMY_GPIO1_NUM,
106 },
107#if !defined(CONFIG_SOC_AU1000)
108 [1] = {
109 .label = "alchemy-gpio2",
110 .direction_input = gpio2_direction_input,
111 .direction_output = gpio2_direction_output,
112 .get = gpio2_get,
113 .set = gpio2_set,
114 .to_irq = gpio2_to_irq,
115 .base = ALCHEMY_GPIO2_BASE,
116 .ngpio = ALCHEMY_GPIO2_NUM,
117 },
118#endif
119};
120
121static int __init alchemy_gpiolib_init(void)
122{
123 gpiochip_add(&alchemy_gpio_chip[0]);
124#if !defined(CONFIG_SOC_AU1000)
125 gpiochip_add(&alchemy_gpio_chip[1]);
126#endif
127
128 return 0;
129}
130arch_initcall(alchemy_gpiolib_init);
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
index 0191c936cb5e..4791011e8f92 100644
--- a/arch/mips/alchemy/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
@@ -27,8 +27,9 @@
27 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */ 28 */
29 29
30#include <asm/cacheflush.h> 30#include <linux/gpio.h>
31 31
32#include <asm/cacheflush.h>
32#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
33 34
34void au1000_restart(char *command) 35void au1000_restart(char *command)
@@ -161,7 +162,7 @@ void au1000_halt(void)
161#else 162#else
162 printk(KERN_NOTICE "\n** You can safely turn off the power\n"); 163 printk(KERN_NOTICE "\n** You can safely turn off the power\n");
163#ifdef CONFIG_MIPS_MIRAGE 164#ifdef CONFIG_MIPS_MIRAGE
164 au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); 165 gpio_direction_output(210, 1);
165#endif 166#endif
166#ifdef CONFIG_MIPS_DB1200 167#ifdef CONFIG_MIPS_DB1200
167 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); 168 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index a75ffbf99f25..de30d8ea7176 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -27,6 +27,7 @@
27 * 675 Mass Ave, Cambridge, MA 02139, USA. 27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */ 28 */
29 29
30#include <linux/gpio.h>
30#include <linux/init.h> 31#include <linux/init.h>
31 32
32#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
@@ -94,12 +95,12 @@ void __init board_setup(void)
94#endif 95#endif
95 bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ 96 bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */
96 97
97#ifdef CONFIG_MIPS_MIRAGE
98 /* Enable GPIO[31:0] inputs */ 98 /* Enable GPIO[31:0] inputs */
99 au_writel(0, SYS_PININPUTEN); 99 alchemy_gpio1_input_enable();
100 100
101 /* GPIO[20] is output, tristate the other input primary GPIOs */ 101#ifdef CONFIG_MIPS_MIRAGE
102 au_writel(~(1 << 20), SYS_TRIOUTCLR); 102 /* GPIO[20] is output */
103 alchemy_gpio_direction_output(20, 0);
103 104
104 /* Set GPIO[210:208] instead of SSI_0 */ 105 /* Set GPIO[210:208] instead of SSI_0 */
105 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; 106 pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
@@ -118,8 +119,7 @@ void __init board_setup(void)
118 * Enable speaker amplifier. This should 119 * Enable speaker amplifier. This should
119 * be part of the audio driver. 120 * be part of the audio driver.
120 */ 121 */
121 au_writel(au_readl(GPIO2_DIR) | 0x200, GPIO2_DIR); 122 alchemy_gpio_direction_output(209, 1);
122 au_writel(0x02000200, GPIO2_OUTPUT);
123#endif 123#endif
124 124
125 au_sync(); 125 au_sync();
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index aed2fdecc709..cd273545e810 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -24,6 +24,7 @@
24 */ 24 */
25 25
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/gpio.h>
27#include <linux/init.h> 28#include <linux/init.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <asm/mach-au1x00/au1000.h> 30#include <asm/mach-au1x00/au1000.h>
@@ -130,8 +131,11 @@ void __init board_setup(void)
130 pin_func |= SYS_PF_USB; 131 pin_func |= SYS_PF_USB;
131 132
132 au_writel(pin_func, SYS_PINFUNC); 133 au_writel(pin_func, SYS_PINFUNC);
133 au_writel(0x2800, SYS_TRIOUTCLR); 134
134 au_writel(0x0030, SYS_OUTPUTCLR); 135 alchemy_gpio_direction_input(11);
136 alchemy_gpio_direction_input(13);
137 alchemy_gpio_direction_output(4, 0);
138 alchemy_gpio_direction_output(5, 0);
135#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 139#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
136 140
137 /* Make GPIO 15 an input (for interrupt line) */ 141 /* Make GPIO 15 an input (for interrupt line) */
@@ -140,7 +144,7 @@ void __init board_setup(void)
140 pin_func |= SYS_PF_I2S; 144 pin_func |= SYS_PF_I2S;
141 au_writel(pin_func, SYS_PINFUNC); 145 au_writel(pin_func, SYS_PINFUNC);
142 146
143 au_writel(0x8000, SYS_TRIOUTCLR); 147 alchemy_gpio_direction_input(15);
144 148
145 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00; 149 static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
146 au_writel(static_cfg0, MEM_STCFG0); 150 au_writel(static_cfg0, MEM_STCFG0);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 4df57fae15d4..61263081ef58 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -23,6 +23,7 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/gpio.h>
26#include <linux/init.h> 27#include <linux/init.h>
27#include <linux/delay.h> 28#include <linux/delay.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
@@ -88,7 +89,7 @@ void __init board_setup(void)
88 89
89 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 90 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
90 au_writel(8, SYS_AUXPLL); 91 au_writel(8, SYS_AUXPLL);
91 au_writel(0, SYS_PININPUTEN); 92 alchemy_gpio1_input_enable();
92 udelay(100); 93 udelay(100);
93 94
94#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 95#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index fed3b093156a..d7a56569e7ed 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -23,8 +23,9 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/init.h>
27#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/gpio.h>
28#include <linux/init.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29 30
30#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
@@ -90,11 +91,12 @@ void __init board_setup(void)
90 au_writel(0, SYS_PINSTATERD); 91 au_writel(0, SYS_PINSTATERD);
91 udelay(100); 92 udelay(100);
92 93
93#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
94
95 /* GPIO201 is input for PCMCIA card detect */ 94 /* GPIO201 is input for PCMCIA card detect */
96 /* GPIO203 is input for PCMCIA interrupt request */ 95 /* GPIO203 is input for PCMCIA interrupt request */
97 au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR); 96 alchemy_gpio_direction_input(201);
97 alchemy_gpio_direction_input(203);
98
99#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
98 100
99 /* Zero and disable FREQ2 */ 101 /* Zero and disable FREQ2 */
100 sys_freqctrl = au_readl(SYS_FREQCTRL0); 102 sys_freqctrl = au_readl(SYS_FREQCTRL0);
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index d5eb9c325ed0..632f9862a0fb 100644
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -9,6 +9,7 @@
9#include <linux/suspend.h> 9#include <linux/suspend.h>
10#include <linux/sysfs.h> 10#include <linux/sysfs.h>
11#include <asm/mach-au1x00/au1000.h> 11#include <asm/mach-au1x00/au1000.h>
12#include <asm/mach-au1x00/gpio.h>
12 13
13/* 14/*
14 * Generic suspend userspace interface for Alchemy development boards. 15 * Generic suspend userspace interface for Alchemy development boards.
@@ -26,7 +27,7 @@ static unsigned long db1x_pm_last_wakesrc;
26static int db1x_pm_enter(suspend_state_t state) 27static int db1x_pm_enter(suspend_state_t state)
27{ 28{
28 /* enable GPIO based wakeup */ 29 /* enable GPIO based wakeup */
29 au_writel(1, SYS_PININPUTEN); 30 alchemy_gpio1_input_enable();
30 31
31 /* clear and setup wake cause and source */ 32 /* clear and setup wake cause and source */
32 au_writel(0, SYS_WAKEMSK); 33 au_writel(0, SYS_WAKEMSK);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 8ed1ae12bc55..cc32c69a74ad 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -28,6 +28,7 @@
28 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */ 29 */
30 30
31#include <linux/gpio.h>
31#include <linux/init.h> 32#include <linux/init.h>
32 33
33#include <asm/mach-au1x00/au1000.h> 34#include <asm/mach-au1x00/au1000.h>
@@ -55,10 +56,11 @@ void __init board_setup(void)
55 } 56 }
56#endif 57#endif
57 58
59 alchemy_gpio2_enable();
60
58#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 61#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
59 /* Enable USB power switch */ 62 /* Enable USB power switch */
60 au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); 63 alchemy_gpio_direction_output(204, 0);
61 au_writel(0x100000, GPIO2_OUTPUT);
62#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 64#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
63 65
64#ifdef CONFIG_PCI 66#ifdef CONFIG_PCI
@@ -74,14 +76,14 @@ void __init board_setup(void)
74 76
75 /* Initialize GPIO */ 77 /* Initialize GPIO */
76 au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); 78 au_writel(0xFFFFFFFF, SYS_TRIOUTCLR);
77 au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */ 79 alchemy_gpio_direction_output(0, 0); /* Disable M66EN (PCI 66MHz) */
78 au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */ 80 alchemy_gpio_direction_output(3, 1); /* Disable PCI CLKRUN# */
79 au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ 81 alchemy_gpio_direction_output(1, 1); /* Enable EXT_IO3 */
80 au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */ 82 alchemy_gpio_direction_output(5, 0); /* Disable eth PHY TX_ER */
81 83
82 /* Enable LED and set it to green */ 84 /* Enable LED and set it to green */
83 au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR); 85 alchemy_gpio_direction_output(211, 1); /* green on */
84 au_writel(0x18000800, GPIO2_OUTPUT); 86 alchemy_gpio_direction_output(212, 0); /* red off */
85 87
86 board_pci_idsel = mtx1_pci_idsel; 88 board_pci_idsel = mtx1_pci_idsel;
87 89
@@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
101 103
102 if (assert && devsel != 0) 104 if (assert && devsel != 0)
103 /* Suppress signal to Cardbus */ 105 /* Suppress signal to Cardbus */
104 au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ 106 gpio_set_value(1, 0); /* set EXT_IO3 OFF */
105 else 107 else
106 au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ 108 gpio_set_value(1, 1); /* set EXT_IO3 ON */
109
107 au_sync_udelay(1); 110 au_sync_udelay(1);
108 return 1; 111 return 1;
109} 112}
110
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index a2634fabc50d..4de2d48caed8 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -23,6 +23,7 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/gpio.h>
26#include <linux/init.h> 27#include <linux/init.h>
27#include <linux/delay.h> 28#include <linux/delay.h>
28 29
@@ -50,6 +51,9 @@ void __init board_setup(void)
50 } 51 }
51#endif 52#endif
52 53
54 alchemy_gpio1_input_enable();
55 alchemy_gpio2_enable();
56
53 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ 57 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
54 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; 58 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
55 pin_func |= SYS_PF_UR3; 59 pin_func |= SYS_PF_UR3;
@@ -65,20 +69,19 @@ void __init board_setup(void)
65 au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */ 69 au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */
66 70
67#ifdef CONFIG_PCMCIA_XXS1500 71#ifdef CONFIG_PCMCIA_XXS1500
68 /* Setup PCMCIA signals */
69 au_writel(0, SYS_PININPUTEN);
70
71 /* GPIO 0, 1, and 4 are inputs */ 72 /* GPIO 0, 1, and 4 are inputs */
72 au_writel(1 | (1 << 1) | (1 << 4), SYS_TRIOUTCLR); 73 alchemy_gpio_direction_input(0);
74 alchemy_gpio_direction_input(1);
75 alchemy_gpio_direction_input(4);
73 76
74 /* Enable GPIO2 if not already enabled */
75 au_writel(1, GPIO2_ENABLE);
76 /* GPIO2 208/9/10/11 are inputs */ 77 /* GPIO2 208/9/10/11 are inputs */
77 au_writel((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11), GPIO2_DIR); 78 alchemy_gpio_direction_input(208);
79 alchemy_gpio_direction_input(209);
80 alchemy_gpio_direction_input(210);
81 alchemy_gpio_direction_input(211);
78 82
79 /* Turn off power */ 83 /* Turn off power */
80 au_writel((au_readl(GPIO2_PINSTATE) & ~(1 << 14)) | (1 << 30), 84 alchemy_gpio_direction_output(214, 0);
81 GPIO2_OUTPUT);
82#endif 85#endif
83 86
84#ifdef CONFIG_PCI 87#ifdef CONFIG_PCI
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index d6903c3f3d51..7c0528b0e34c 100644
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -14,5 +14,9 @@ obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o 14obj-y += octeon-memcpy.o
15 15
16obj-$(CONFIG_SMP) += smp.o 16obj-$(CONFIG_SMP) += smp.o
17obj-$(CONFIG_PCI) += pci-common.o
18obj-$(CONFIG_PCI) += pci.o
19obj-$(CONFIG_PCI) += pcie.o
20obj-$(CONFIG_PCI_MSI) += msi.o
17 21
18EXTRA_CFLAGS += -Werror 22EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
index 01b1ef94b361..627c162a6159 100644
--- a/arch/mips/cavium-octeon/dma-octeon.c
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -13,20 +13,327 @@
13 */ 13 */
14#include <linux/types.h> 14#include <linux/types.h>
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/module.h>
17#include <linux/string.h>
18#include <linux/dma-mapping.h>
19#include <linux/platform_device.h>
20#include <linux/scatterlist.h>
21
22#include <linux/cache.h>
23#include <linux/io.h>
24
25#include <asm/octeon/octeon.h>
26#include <asm/octeon/cvmx-npi-defs.h>
27#include <asm/octeon/cvmx-pci-defs.h>
16 28
17#include <dma-coherence.h> 29#include <dma-coherence.h>
18 30
31#ifdef CONFIG_PCI
32#include "pci-common.h"
33#endif
34
35#define BAR2_PCI_ADDRESS 0x8000000000ul
36
37struct bar1_index_state {
38 int16_t ref_count; /* Number of PCI mappings using this index */
39 uint16_t address_bits; /* Upper bits of physical address. This is
40 shifted 22 bits */
41};
42
43#ifdef CONFIG_PCI
44static DEFINE_SPINLOCK(bar1_lock);
45static struct bar1_index_state bar1_state[32];
46#endif
47
19dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) 48dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
20{ 49{
50#ifndef CONFIG_PCI
21 /* Without PCI/PCIe this function can be called for Octeon internal 51 /* Without PCI/PCIe this function can be called for Octeon internal
22 devices such as USB. These devices all support 64bit addressing */ 52 devices such as USB. These devices all support 64bit addressing */
23 mb(); 53 mb();
24 return virt_to_phys(ptr); 54 return virt_to_phys(ptr);
55#else
56 unsigned long flags;
57 uint64_t dma_mask;
58 int64_t start_index;
59 dma_addr_t result = -1;
60 uint64_t physical = virt_to_phys(ptr);
61 int64_t index;
62
63 mb();
64 /*
65 * Use the DMA masks to determine the allowed memory
66 * region. For us it doesn't limit the actual memory, just the
67 * address visible over PCI. Devices with limits need to use
68 * lower indexed Bar1 entries.
69 */
70 if (dev) {
71 dma_mask = dev->coherent_dma_mask;
72 if (dev->dma_mask)
73 dma_mask = *dev->dma_mask;
74 } else {
75 dma_mask = 0xfffffffful;
76 }
77
78 /*
79 * Platform devices, such as the internal USB, skip all
80 * translation and use Octeon physical addresses directly.
81 */
82 if (!dev || dev->bus == &platform_bus_type)
83 return physical;
84
85 switch (octeon_dma_bar_type) {
86 case OCTEON_DMA_BAR_TYPE_PCIE:
87 if (unlikely(physical < (16ul << 10)))
88 panic("dma_map_single: Not allowed to map first 16KB."
89 " It interferes with BAR0 special area\n");
90 else if ((physical + size >= (256ul << 20)) &&
91 (physical < (512ul << 20)))
92 panic("dma_map_single: Not allowed to map bootbus\n");
93 else if ((physical + size >= 0x400000000ull) &&
94 physical < 0x410000000ull)
95 panic("dma_map_single: "
96 "Attempt to map illegal memory address 0x%llx\n",
97 physical);
98 else if (physical >= 0x420000000ull)
99 panic("dma_map_single: "
100 "Attempt to map illegal memory address 0x%llx\n",
101 physical);
102 else if ((physical + size >=
103 (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
104 && physical < (4ull<<30))
105 pr_warning("dma_map_single: Warning: "
106 "Mapping memory address that might "
107 "conflict with devices 0x%llx-0x%llx\n",
108 physical, physical+size-1);
109 /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
110 if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
111 result = physical - 0x400000000ull;
112 else
113 result = physical;
114 if (((result+size-1) & dma_mask) != result+size-1)
115 panic("dma_map_single: Attempt to map address "
116 "0x%llx-0x%llx, which can't be accessed "
117 "according to the dma mask 0x%llx\n",
118 physical, physical+size-1, dma_mask);
119 goto done;
120
121 case OCTEON_DMA_BAR_TYPE_BIG:
122#ifdef CONFIG_64BIT
123 /* If the device supports 64bit addressing, then use BAR2 */
124 if (dma_mask > BAR2_PCI_ADDRESS) {
125 result = physical + BAR2_PCI_ADDRESS;
126 goto done;
127 }
128#endif
129 if (unlikely(physical < (4ul << 10))) {
130 panic("dma_map_single: Not allowed to map first 4KB. "
131 "It interferes with BAR0 special area\n");
132 } else if (physical < (256ul << 20)) {
133 if (unlikely(physical + size > (256ul << 20)))
134 panic("dma_map_single: Requested memory spans "
135 "Bar0 0:256MB and bootbus\n");
136 result = physical;
137 goto done;
138 } else if (unlikely(physical < (512ul << 20))) {
139 panic("dma_map_single: Not allowed to map bootbus\n");
140 } else if (physical < (2ul << 30)) {
141 if (unlikely(physical + size > (2ul << 30)))
142 panic("dma_map_single: Requested memory spans "
143 "Bar0 512MB:2GB and BAR1\n");
144 result = physical;
145 goto done;
146 } else if (physical < (2ul << 30) + (128 << 20)) {
147 /* Fall through */
148 } else if (physical <
149 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
150 if (unlikely
151 (physical + size >
152 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
153 panic("dma_map_single: Requested memory "
154 "extends past Bar1 (4GB-%luMB)\n",
155 OCTEON_PCI_BAR1_HOLE_SIZE);
156 result = physical;
157 goto done;
158 } else if ((physical >= 0x410000000ull) &&
159 (physical < 0x420000000ull)) {
160 if (unlikely(physical + size > 0x420000000ull))
161 panic("dma_map_single: Requested memory spans "
162 "non existant memory\n");
163 /* BAR0 fixed mapping 256MB:512MB ->
164 * 16GB+256MB:16GB+512MB */
165 result = physical - 0x400000000ull;
166 goto done;
167 } else {
168 /* Continued below switch statement */
169 }
170 break;
171
172 case OCTEON_DMA_BAR_TYPE_SMALL:
173#ifdef CONFIG_64BIT
174 /* If the device supports 64bit addressing, then use BAR2 */
175 if (dma_mask > BAR2_PCI_ADDRESS) {
176 result = physical + BAR2_PCI_ADDRESS;
177 goto done;
178 }
179#endif
180 /* Continued below switch statement */
181 break;
182
183 default:
184 panic("dma_map_single: Invalid octeon_dma_bar_type\n");
185 }
186
187 /* Don't allow mapping to span multiple Bar entries. The hardware guys
188 won't guarantee that DMA across boards work */
189 if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
190 panic("dma_map_single: "
191 "Requested memory spans more than one Bar1 entry\n");
192
193 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
194 start_index = 31;
195 else if (unlikely(dma_mask < (1ul << 27)))
196 start_index = (dma_mask >> 22);
197 else
198 start_index = 31;
199
200 /* Only one processor can access the Bar register at once */
201 spin_lock_irqsave(&bar1_lock, flags);
202
203 /* Look through Bar1 for existing mapping that will work */
204 for (index = start_index; index >= 0; index--) {
205 if ((bar1_state[index].address_bits == physical >> 22) &&
206 (bar1_state[index].ref_count)) {
207 /* An existing mapping will work, use it */
208 bar1_state[index].ref_count++;
209 if (unlikely(bar1_state[index].ref_count < 0))
210 panic("dma_map_single: "
211 "Bar1[%d] reference count overflowed\n",
212 (int) index);
213 result = (index << 22) | (physical & ((1 << 22) - 1));
214 /* Large BAR1 is offset at 2GB */
215 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
216 result += 2ul << 30;
217 goto done_unlock;
218 }
219 }
220
221 /* No existing mappings, look for a free entry */
222 for (index = start_index; index >= 0; index--) {
223 if (unlikely(bar1_state[index].ref_count == 0)) {
224 union cvmx_pci_bar1_indexx bar1_index;
225 /* We have a free entry, use it */
226 bar1_state[index].ref_count = 1;
227 bar1_state[index].address_bits = physical >> 22;
228 bar1_index.u32 = 0;
229 /* Address bits[35:22] sent to L2C */
230 bar1_index.s.addr_idx = physical >> 22;
231 /* Don't put PCI accesses in L2. */
232 bar1_index.s.ca = 1;
233 /* Endian Swap Mode */
234 bar1_index.s.end_swp = 1;
235 /* Set '1' when the selected address range is valid. */
236 bar1_index.s.addr_v = 1;
237 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
238 bar1_index.u32);
239 /* An existing mapping will work, use it */
240 result = (index << 22) | (physical & ((1 << 22) - 1));
241 /* Large BAR1 is offset at 2GB */
242 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
243 result += 2ul << 30;
244 goto done_unlock;
245 }
246 }
247
248 pr_err("dma_map_single: "
249 "Can't find empty BAR1 index for physical mapping 0x%llx\n",
250 (unsigned long long) physical);
251
252done_unlock:
253 spin_unlock_irqrestore(&bar1_lock, flags);
254done:
255 pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result);
256 return result;
257#endif
25} 258}
26 259
27void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 260void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
28{ 261{
29 /* Without PCI/PCIe this function can be called for Octeon internal 262#ifndef CONFIG_PCI
30 * devices such as USB. These devices all support 64bit addressing */ 263 /*
264 * Without PCI/PCIe this function can be called for Octeon internal
265 * devices such as USB. These devices all support 64bit addressing.
266 */
267 return;
268#else
269 unsigned long flags;
270 uint64_t index;
271
272 /*
273 * Platform devices, such as the internal USB, skip all
274 * translation and use Octeon physical addresses directly.
275 */
276 if (dev->bus == &platform_bus_type)
277 return;
278
279 switch (octeon_dma_bar_type) {
280 case OCTEON_DMA_BAR_TYPE_PCIE:
281 /* Nothing to do, all mappings are static */
282 goto done;
283
284 case OCTEON_DMA_BAR_TYPE_BIG:
285#ifdef CONFIG_64BIT
286 /* Nothing to do for addresses using BAR2 */
287 if (dma_addr >= BAR2_PCI_ADDRESS)
288 goto done;
289#endif
290 if (unlikely(dma_addr < (4ul << 10)))
291 panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
292 dma_addr);
293 else if (dma_addr < (2ul << 30))
294 /* Nothing to do for addresses using BAR0 */
295 goto done;
296 else if (dma_addr < (2ul << 30) + (128ul << 20))
297 /* Need to unmap, fall through */
298 index = (dma_addr - (2ul << 30)) >> 22;
299 else if (dma_addr <
300 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
301 goto done; /* Nothing to do for the rest of BAR1 */
302 else
303 panic("dma_unmap_single: Unexpect DMA address 0x%llx\n",
304 dma_addr);
305 /* Continued below switch statement */
306 break;
307
308 case OCTEON_DMA_BAR_TYPE_SMALL:
309#ifdef CONFIG_64BIT
310 /* Nothing to do for addresses using BAR2 */
311 if (dma_addr >= BAR2_PCI_ADDRESS)
312 goto done;
313#endif
314 index = dma_addr >> 22;
315 /* Continued below switch statement */
316 break;
317
318 default:
319 panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
320 }
321
322 if (unlikely(index > 31))
323 panic("dma_unmap_single: "
324 "Attempt to unmap an invalid address (0x%llx)\n",
325 dma_addr);
326
327 spin_lock_irqsave(&bar1_lock, flags);
328 bar1_state[index].ref_count--;
329 if (bar1_state[index].ref_count == 0)
330 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
331 else if (unlikely(bar1_state[index].ref_count < 0))
332 panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
333 (int) index);
334 spin_unlock_irqrestore(&bar1_lock, flags);
335done:
336 pr_debug("dma_unmap_single 0x%llx\n", dma_addr);
31 return; 337 return;
338#endif
32} 339}
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
index 80d6cb26766b..2fd66db6939e 100644
--- a/arch/mips/cavium-octeon/executive/Makefile
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -11,3 +11,4 @@
11 11
12obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o 12obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
13 13
14obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-jtag.o
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 4f5a08b37ccd..25666da17b22 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -31,6 +31,7 @@
31 */ 31 */
32 32
33#include <linux/kernel.h> 33#include <linux/kernel.h>
34#include <linux/module.h>
34 35
35#include <asm/octeon/cvmx.h> 36#include <asm/octeon/cvmx.h>
36#include <asm/octeon/cvmx-spinlock.h> 37#include <asm/octeon/cvmx-spinlock.h>
@@ -97,6 +98,33 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
97 return cvmx_bootmem_alloc_range(size, alignment, 0, 0); 98 return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
98} 99}
99 100
101void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
102 uint64_t max_addr, uint64_t align,
103 char *name)
104{
105 int64_t addr;
106
107 addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr,
108 align, name, 0);
109 if (addr >= 0)
110 return cvmx_phys_to_ptr(addr);
111 else
112 return NULL;
113}
114
115void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
116 char *name)
117{
118 return cvmx_bootmem_alloc_named_range(size, address, address + size,
119 0, name);
120}
121
122void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name)
123{
124 return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name);
125}
126EXPORT_SYMBOL(cvmx_bootmem_alloc_named);
127
100int cvmx_bootmem_free_named(char *name) 128int cvmx_bootmem_free_named(char *name)
101{ 129{
102 return cvmx_bootmem_phy_named_block_free(name, 0); 130 return cvmx_bootmem_phy_named_block_free(name, 0);
@@ -106,6 +134,7 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name)
106{ 134{
107 return cvmx_bootmem_phy_named_block_find(name, 0); 135 return cvmx_bootmem_phy_named_block_find(name, 0);
108} 136}
137EXPORT_SYMBOL(cvmx_bootmem_find_named_block);
109 138
110void cvmx_bootmem_lock(void) 139void cvmx_bootmem_lock(void)
111{ 140{
@@ -584,3 +613,78 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
584 cvmx_bootmem_unlock(); 613 cvmx_bootmem_unlock();
585 return named_block_ptr != NULL; /* 0 on failure, 1 on success */ 614 return named_block_ptr != NULL; /* 0 on failure, 1 on success */
586} 615}
616
617int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
618 uint64_t max_addr,
619 uint64_t alignment,
620 char *name,
621 uint32_t flags)
622{
623 int64_t addr_allocated;
624 struct cvmx_bootmem_named_block_desc *named_block_desc_ptr;
625
626#ifdef DEBUG
627 cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: "
628 "0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n",
629 (unsigned long long)size,
630 (unsigned long long)min_addr,
631 (unsigned long long)max_addr,
632 (unsigned long long)alignment,
633 name);
634#endif
635 if (cvmx_bootmem_desc->major_version != 3) {
636 cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
637 "%d.%d at addr: %p\n",
638 (int)cvmx_bootmem_desc->major_version,
639 (int)cvmx_bootmem_desc->minor_version,
640 cvmx_bootmem_desc);
641 return -1;
642 }
643
644 /*
645 * Take lock here, as name lookup/block alloc/name add need to
646 * be atomic.
647 */
648 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
649 cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
650
651 /* Get pointer to first available named block descriptor */
652 named_block_desc_ptr =
653 cvmx_bootmem_phy_named_block_find(NULL,
654 flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
655
656 /*
657 * Check to see if name already in use, return error if name
658 * not available or no more room for blocks.
659 */
660 if (cvmx_bootmem_phy_named_block_find(name,
661 flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr) {
662 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
663 cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
664 return -1;
665 }
666
667
668 /*
669 * Round size up to mult of minimum alignment bytes We need
670 * the actual size allocated to allow for blocks to be
671 * coallesced when they are freed. The alloc routine does the
672 * same rounding up on all allocations.
673 */
674 size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1));
675
676 addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr,
677 alignment,
678 flags | CVMX_BOOTMEM_FLAG_NO_LOCKING);
679 if (addr_allocated >= 0) {
680 named_block_desc_ptr->base_addr = addr_allocated;
681 named_block_desc_ptr->size = size;
682 strncpy(named_block_desc_ptr->name, name,
683 cvmx_bootmem_desc->named_block_name_len);
684 named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0;
685 }
686
687 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
688 cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock));
689 return addr_allocated;
690}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
new file mode 100644
index 000000000000..868659e64d4a
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
@@ -0,0 +1,73 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Fixes and workaround for Octeon chip errata. This file
31 * contains functions called by cvmx-helper to workaround known
32 * chip errata. For the most part, code doesn't need to call
33 * these functions directly.
34 *
35 */
36#include <linux/module.h>
37
38#include <asm/octeon/octeon.h>
39
40#include <asm/octeon/cvmx-helper-jtag.h>
41
42/**
43 * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
44 * 1 doesn't work properly. The following code disables 2nd order
45 * CDR for the specified QLM.
46 *
47 * @qlm: QLM to disable 2nd order CDR for.
48 */
49void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
50{
51 int lane;
52 cvmx_helper_qlm_jtag_init();
53 /* We need to load all four lanes of the QLM, a total of 1072 bits */
54 for (lane = 0; lane < 4; lane++) {
55 /*
56 * Each lane has 268 bits. We need to set
57 * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
58 * 1. All other bits are zero. Bits go in LSB first,
59 * so start off with the zeros for bits <63:0>.
60 */
61 cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
62 /* cfg_cdr_incx<67:64>=3 */
63 cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
64 /* Zeros for bits <76:68> */
65 cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
66 /* cfg_cdr_secord<77>=1 */
67 cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
68 /* Zeros for bits <267:78> */
69 cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
70 }
71 cvmx_helper_qlm_jtag_update(qlm);
72}
73EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr);
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
new file mode 100644
index 000000000000..c1c54890bae0
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -0,0 +1,144 @@
1
2/***********************license start***************
3 * Author: Cavium Networks
4 *
5 * Contact: support@caviumnetworks.com
6 * This file is part of the OCTEON SDK
7 *
8 * Copyright (c) 2003-2008 Cavium Networks
9 *
10 * This file is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, Version 2, as
12 * published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful, but
15 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
17 * NONINFRINGEMENT. See the GNU General Public License for more
18 * details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this file; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 * or visit http://www.gnu.org/licenses/.
24 *
25 * This file may also be available under a different license from Cavium.
26 * Contact Cavium Networks for more information
27 ***********************license end**************************************/
28
29/**
30 *
31 * Helper utilities for qlm_jtag.
32 *
33 */
34
35#include <asm/octeon/octeon.h>
36#include <asm/octeon/cvmx-helper-jtag.h>
37
38
39/**
40 * Initialize the internal QLM JTAG logic to allow programming
41 * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
42 * These functions should only be used at the direction of Cavium
43 * Networks. Programming incorrect values into the JTAG chain
44 * can cause chip damage.
45 */
46void cvmx_helper_qlm_jtag_init(void)
47{
48 union cvmx_ciu_qlm_jtgc jtgc;
49 uint32_t clock_div = 0;
50 uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
51 divisor = (divisor - 1) >> 2;
52 /* Convert the divisor into a power of 2 shift */
53 while (divisor) {
54 clock_div++;
55 divisor = divisor >> 1;
56 }
57
58 /*
59 * Clock divider for QLM JTAG operations. eclk is divided by
60 * 2^(CLK_DIV + 2)
61 */
62 jtgc.u64 = 0;
63 jtgc.s.clk_div = clock_div;
64 jtgc.s.mux_sel = 0;
65 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
66 jtgc.s.bypass = 0x3;
67 else
68 jtgc.s.bypass = 0xf;
69 cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
70 cvmx_read_csr(CVMX_CIU_QLM_JTGC);
71}
72
73/**
74 * Write up to 32bits into the QLM jtag chain. Bits are shifted
75 * into the MSB and out the LSB, so you should shift in the low
76 * order bits followed by the high order bits. The JTAG chain is
77 * 4 * 268 bits long, or 1072.
78 *
79 * @qlm: QLM to shift value into
80 * @bits: Number of bits to shift in (1-32).
81 * @data: Data to shift in. Bit 0 enters the chain first, followed by
82 * bit 1, etc.
83 *
84 * Returns The low order bits of the JTAG chain that shifted out of the
85 * circle.
86 */
87uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
88{
89 union cvmx_ciu_qlm_jtgd jtgd;
90 jtgd.u64 = 0;
91 jtgd.s.shift = 1;
92 jtgd.s.shft_cnt = bits - 1;
93 jtgd.s.shft_reg = data;
94 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
95 jtgd.s.select = 1 << qlm;
96 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
97 do {
98 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
99 } while (jtgd.s.shift);
100 return jtgd.s.shft_reg >> (32 - bits);
101}
102
103/**
104 * Shift long sequences of zeros into the QLM JTAG chain. It is
105 * common to need to shift more than 32 bits of zeros into the
106 * chain. This function is a convience wrapper around
107 * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
108 * zeros at a time.
109 *
110 * @qlm: QLM to shift zeros into
111 * @bits:
112 */
113void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
114{
115 while (bits > 0) {
116 int n = bits;
117 if (n > 32)
118 n = 32;
119 cvmx_helper_qlm_jtag_shift(qlm, n, 0);
120 bits -= n;
121 }
122}
123
124/**
125 * Program the QLM JTAG chain into all lanes of the QLM. You must
126 * have already shifted in 268*4, or 1072 bits into the JTAG
127 * chain. Updating invalid values can possibly cause chip damage.
128 *
129 * @qlm: QLM to program
130 */
131void cvmx_helper_qlm_jtag_update(int qlm)
132{
133 union cvmx_ciu_qlm_jtgd jtgd;
134
135 /* Update the new data */
136 jtgd.u64 = 0;
137 jtgd.s.update = 1;
138 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
139 jtgd.s.select = 1 << qlm;
140 cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
141 do {
142 jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
143 } while (jtgd.s.update);
144}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
index 4812370706a1..e5838890cba5 100644
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -29,6 +29,7 @@
29 * This module provides system/board/application information obtained 29 * This module provides system/board/application information obtained
30 * by the bootloader. 30 * by the bootloader.
31 */ 31 */
32#include <linux/module.h>
32 33
33#include <asm/octeon/cvmx.h> 34#include <asm/octeon/cvmx.h>
34#include <asm/octeon/cvmx-spinlock.h> 35#include <asm/octeon/cvmx-spinlock.h>
@@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void)
69{ 70{
70 return &(state.sysinfo); 71 return &(state.sysinfo);
71} 72}
73EXPORT_SYMBOL(cvmx_sysinfo_get);
72 74
73/** 75/**
74 * This function is used in non-simple executive environments (such as 76 * This function is used in non-simple executive environments (such as
diff --git a/arch/mips/cavium-octeon/msi.c b/arch/mips/cavium-octeon/msi.c
new file mode 100644
index 000000000000..964b03b75a8f
--- /dev/null
+++ b/arch/mips/cavium-octeon/msi.c
@@ -0,0 +1,288 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/msi.h>
11#include <linux/spinlock.h>
12#include <linux/interrupt.h>
13
14#include <asm/octeon/octeon.h>
15#include <asm/octeon/cvmx-npi-defs.h>
16#include <asm/octeon/cvmx-pci-defs.h>
17#include <asm/octeon/cvmx-npei-defs.h>
18#include <asm/octeon/cvmx-pexp-defs.h>
19
20#include "pci-common.h"
21
22/*
23 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
24 * in use.
25 */
26static uint64_t msi_free_irq_bitmask;
27
28/*
29 * Each bit in msi_multiple_irq_bitmask tells that the device using
30 * this bit in msi_free_irq_bitmask is also using the next bit. This
31 * is used so we can disable all of the MSI interrupts when a device
32 * uses multiple.
33 */
34static uint64_t msi_multiple_irq_bitmask;
35
36/*
37 * This lock controls updates to msi_free_irq_bitmask and
38 * msi_multiple_irq_bitmask.
39 */
40static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
41
42
43/**
44 * Called when a driver request MSI interrupts instead of the
45 * legacy INT A-D. This routine will allocate multiple interrupts
46 * for MSI devices that support them. A device can override this by
47 * programming the MSI control bits [6:4] before calling
48 * pci_enable_msi().
49 *
50 * @param dev Device requesting MSI interrupts
51 * @param desc MSI descriptor
52 *
53 * Returns 0 on success.
54 */
55int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
56{
57 struct msi_msg msg;
58 uint16_t control;
59 int configured_private_bits;
60 int request_private_bits;
61 int irq;
62 int irq_step;
63 uint64_t search_mask;
64
65 /*
66 * Read the MSI config to figure out how many IRQs this device
67 * wants. Most devices only want 1, which will give
68 * configured_private_bits and request_private_bits equal 0.
69 */
70 pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
71 &control);
72
73 /*
74 * If the number of private bits has been configured then use
75 * that value instead of the requested number. This gives the
76 * driver the chance to override the number of interrupts
77 * before calling pci_enable_msi().
78 */
79 configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
80 if (configured_private_bits == 0) {
81 /* Nothing is configured, so use the hardware requested size */
82 request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
83 } else {
84 /*
85 * Use the number of configured bits, assuming the
86 * driver wanted to override the hardware request
87 * value.
88 */
89 request_private_bits = configured_private_bits;
90 }
91
92 /*
93 * The PCI 2.3 spec mandates that there are at most 32
94 * interrupts. If this device asks for more, only give it one.
95 */
96 if (request_private_bits > 5)
97 request_private_bits = 0;
98
99try_only_one:
100 /*
101 * The IRQs have to be aligned on a power of two based on the
102 * number being requested.
103 */
104 irq_step = 1 << request_private_bits;
105
106 /* Mask with one bit for each IRQ */
107 search_mask = (1 << irq_step) - 1;
108
109 /*
110 * We're going to search msi_free_irq_bitmask_lock for zero
111 * bits. This represents an MSI interrupt number that isn't in
112 * use.
113 */
114 spin_lock(&msi_free_irq_bitmask_lock);
115 for (irq = 0; irq < 64; irq += irq_step) {
116 if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
117 msi_free_irq_bitmask |= search_mask << irq;
118 msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
119 break;
120 }
121 }
122 spin_unlock(&msi_free_irq_bitmask_lock);
123
124 /* Make sure the search for available interrupts didn't fail */
125 if (irq >= 64) {
126 if (request_private_bits) {
127 pr_err("arch_setup_msi_irq: Unable to find %d free "
128 "interrupts, trying just one",
129 1 << request_private_bits);
130 request_private_bits = 0;
131 goto try_only_one;
132 } else
133 panic("arch_setup_msi_irq: Unable to find a free MSI "
134 "interrupt");
135 }
136
137 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
138 irq += OCTEON_IRQ_MSI_BIT0;
139
140 switch (octeon_dma_bar_type) {
141 case OCTEON_DMA_BAR_TYPE_SMALL:
142 /* When not using big bar, Bar 0 is based at 128MB */
143 msg.address_lo =
144 ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
145 msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
146 case OCTEON_DMA_BAR_TYPE_BIG:
147 /* When using big bar, Bar 0 is based at 0 */
148 msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
149 msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
150 break;
151 case OCTEON_DMA_BAR_TYPE_PCIE:
152 /* When using PCIe, Bar 0 is based at 0 */
153 /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
154 msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
155 msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
156 break;
157 default:
158 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
159 }
160 msg.data = irq - OCTEON_IRQ_MSI_BIT0;
161
162 /* Update the number of IRQs the device has available to it */
163 control &= ~PCI_MSI_FLAGS_QSIZE;
164 control |= request_private_bits << 4;
165 pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
166 control);
167
168 set_irq_msi(irq, desc);
169 write_msi_msg(irq, &msg);
170 return 0;
171}
172
173
174/**
175 * Called when a device no longer needs its MSI interrupts. All
176 * MSI interrupts for the device are freed.
177 *
178 * @irq: The devices first irq number. There may be multple in sequence.
179 */
180void arch_teardown_msi_irq(unsigned int irq)
181{
182 int number_irqs;
183 uint64_t bitmask;
184
185 if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
186 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
187 "MSI interrupt (%d)", irq);
188 irq -= OCTEON_IRQ_MSI_BIT0;
189
190 /*
191 * Count the number of IRQs we need to free by looking at the
192 * msi_multiple_irq_bitmask. Each bit set means that the next
193 * IRQ is also owned by this device.
194 */
195 number_irqs = 0;
196 while ((irq+number_irqs < 64) &&
197 (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
198 number_irqs++;
199 number_irqs++;
200 /* Mask with one bit for each IRQ */
201 bitmask = (1 << number_irqs) - 1;
202 /* Shift the mask to the correct bit location */
203 bitmask <<= irq;
204 if ((msi_free_irq_bitmask & bitmask) != bitmask)
205 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
206 "interrupt (%d) not in use", irq);
207
208 /* Checks are done, update the in use bitmask */
209 spin_lock(&msi_free_irq_bitmask_lock);
210 msi_free_irq_bitmask &= ~bitmask;
211 msi_multiple_irq_bitmask &= ~bitmask;
212 spin_unlock(&msi_free_irq_bitmask_lock);
213}
214
215
216/**
217 * Called by the interrupt handling code when an MSI interrupt
218 * occurs.
219 *
220 * @param cpl
221 * @param dev_id
222 *
223 * @return
224 */
225static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
226{
227 uint64_t msi_bits;
228 int irq;
229
230 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
231 msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
232 else
233 msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
234 irq = fls64(msi_bits);
235 if (irq) {
236 irq += OCTEON_IRQ_MSI_BIT0 - 1;
237 if (irq_desc[irq].action) {
238 do_IRQ(irq);
239 return IRQ_HANDLED;
240 } else {
241 pr_err("Spurious MSI interrupt %d\n", irq);
242 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
243 /* These chips have PCIe */
244 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
245 1ull << (irq -
246 OCTEON_IRQ_MSI_BIT0));
247 } else {
248 /* These chips have PCI */
249 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
250 1ull << (irq -
251 OCTEON_IRQ_MSI_BIT0));
252 }
253 }
254 }
255 return IRQ_NONE;
256}
257
258
259/**
260 * Initializes the MSI interrupt handling code
261 *
262 * @return
263 */
264int octeon_msi_initialize(void)
265{
266 int r;
267 if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
268 r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
269 IRQF_SHARED,
270 "MSI[0:63]", octeon_msi_interrupt);
271 } else if (octeon_is_pci_host()) {
272 r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
273 IRQF_SHARED,
274 "MSI[0:15]", octeon_msi_interrupt);
275 r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
276 IRQF_SHARED,
277 "MSI[16:31]", octeon_msi_interrupt);
278 r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
279 IRQF_SHARED,
280 "MSI[32:47]", octeon_msi_interrupt);
281 r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
282 IRQF_SHARED,
283 "MSI[48:63]", octeon_msi_interrupt);
284 }
285 return 0;
286}
287
288subsys_initcall(octeon_msi_initialize);
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index d3a0c8154bec..8dfa009e0070 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -10,6 +10,8 @@
10#include <linux/hardirq.h> 10#include <linux/hardirq.h>
11 11
12#include <asm/octeon/octeon.h> 12#include <asm/octeon/octeon.h>
13#include <asm/octeon/cvmx-pexp-defs.h>
14#include <asm/octeon/cvmx-npi-defs.h>
13 15
14DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); 16DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
15DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); 17DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
diff --git a/arch/mips/cavium-octeon/pci-common.c b/arch/mips/cavium-octeon/pci-common.c
new file mode 100644
index 000000000000..cd029f88da7f
--- /dev/null
+++ b/arch/mips/cavium-octeon/pci-common.c
@@ -0,0 +1,137 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14#include "pci-common.h"
15
16typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
17enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
18
19/**
20 * Map a PCI device to the appropriate interrupt line
21 *
22 * @param dev The Linux PCI device structure for the device to map
23 * @param slot The slot number for this device on __BUS 0__. Linux
24 * enumerates through all the bridges and figures out the
25 * slot on Bus 0 where this device eventually hooks to.
26 * @param pin The PCI interrupt pin read from the device, then swizzled
27 * as it goes through each bridge.
28 * @return Interrupt number for the device
29 */
30int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
31{
32 if (octeon_pcibios_map_irq)
33 return octeon_pcibios_map_irq(dev, slot, pin);
34 else
35 panic("octeon_pcibios_map_irq doesn't point to a "
36 "pcibios_map_irq() function");
37}
38
39
40/**
41 * Called to perform platform specific PCI setup
42 *
43 * @param dev
44 * @return
45 */
46int pcibios_plat_dev_init(struct pci_dev *dev)
47{
48 uint16_t config;
49 uint32_t dconfig;
50 int pos;
51 /*
52 * Force the Cache line setting to 64 bytes. The standard
53 * Linux bus scan doesn't seem to set it. Octeon really has
54 * 128 byte lines, but Intel bridges get really upset if you
55 * try and set values above 64 bytes. Value is specified in
56 * 32bit words.
57 */
58 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
59 /* Set latency timers for all devices */
60 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
61
62 /* Enable reporting System errors and parity errors on all devices */
63 /* Enable parity checking and error reporting */
64 pci_read_config_word(dev, PCI_COMMAND, &config);
65 config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
66 pci_write_config_word(dev, PCI_COMMAND, config);
67
68 if (dev->subordinate) {
69 /* Set latency timers on sub bridges */
70 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
71 /* More bridge error detection */
72 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
73 config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
74 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
75 }
76
77 /* Enable the PCIe normal error reporting */
78 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
79 if (pos) {
80 /* Update Device Control */
81 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
82 /* Correctable Error Reporting */
83 config |= PCI_EXP_DEVCTL_CERE;
84 /* Non-Fatal Error Reporting */
85 config |= PCI_EXP_DEVCTL_NFERE;
86 /* Fatal Error Reporting */
87 config |= PCI_EXP_DEVCTL_FERE;
88 /* Unsupported Request */
89 config |= PCI_EXP_DEVCTL_URRE;
90 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
91 }
92
93 /* Find the Advanced Error Reporting capability */
94 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
95 if (pos) {
96 /* Clear Uncorrectable Error Status */
97 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
98 &dconfig);
99 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
100 dconfig);
101 /* Enable reporting of all uncorrectable errors */
102 /* Uncorrectable Error Mask - turned on bits disable errors */
103 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
104 /*
105 * Leave severity at HW default. This only controls if
106 * errors are reported as uncorrectable or
107 * correctable, not if the error is reported.
108 */
109 /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
110 /* Clear Correctable Error Status */
111 pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
112 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
113 /* Enable reporting of all correctable errors */
114 /* Correctable Error Mask - turned on bits disable errors */
115 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
116 /* Advanced Error Capabilities */
117 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
118 /* ECRC Generation Enable */
119 if (config & PCI_ERR_CAP_ECRC_GENC)
120 config |= PCI_ERR_CAP_ECRC_GENE;
121 /* ECRC Check Enable */
122 if (config & PCI_ERR_CAP_ECRC_CHKC)
123 config |= PCI_ERR_CAP_ECRC_CHKE;
124 pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
125 /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
126 /* Report all errors to the root complex */
127 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
128 PCI_ERR_ROOT_CMD_COR_EN |
129 PCI_ERR_ROOT_CMD_NONFATAL_EN |
130 PCI_ERR_ROOT_CMD_FATAL_EN);
131 /* Clear the Root status register */
132 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
133 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
134 }
135
136 return 0;
137}
diff --git a/arch/mips/cavium-octeon/pci-common.h b/arch/mips/cavium-octeon/pci-common.h
new file mode 100644
index 000000000000..74ae79991e45
--- /dev/null
+++ b/arch/mips/cavium-octeon/pci-common.h
@@ -0,0 +1,39 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#ifndef __OCTEON_PCI_COMMON_H__
9#define __OCTEON_PCI_COMMON_H__
10
11#include <linux/pci.h>
12
13/* Some PCI cards require delays when accessing config space. */
14#define PCI_CONFIG_SPACE_DELAY 10000
15
16/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
17 Octeon specific version pointed to by this variable. This function needs to
18 change for PCI or PCIe based hosts */
19extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
20
21/* The following defines are only used when octeon_dma_bar_type =
22 OCTEON_DMA_BAR_TYPE_BIG */
23#define OCTEON_PCI_BAR1_HOLE_BITS 5
24#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
25
26enum octeon_dma_bar_type {
27 OCTEON_DMA_BAR_TYPE_INVALID,
28 OCTEON_DMA_BAR_TYPE_SMALL,
29 OCTEON_DMA_BAR_TYPE_BIG,
30 OCTEON_DMA_BAR_TYPE_PCIE
31};
32
33/**
34 * This is a variable to tell the DMA mapping system in dma-octeon.c
35 * how to map PCI DMA addresses.
36 */
37extern enum octeon_dma_bar_type octeon_dma_bar_type;
38
39#endif
diff --git a/arch/mips/cavium-octeon/pci.c b/arch/mips/cavium-octeon/pci.c
new file mode 100644
index 000000000000..67c0ff5e92f1
--- /dev/null
+++ b/arch/mips/cavium-octeon/pci.c
@@ -0,0 +1,568 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/time.h>
16
17#include <asm/octeon/octeon.h>
18#include <asm/octeon/cvmx-npi-defs.h>
19#include <asm/octeon/cvmx-pci-defs.h>
20
21#include "pci-common.h"
22
23#define USE_OCTEON_INTERNAL_ARBITER
24
25/*
26 * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
27 * addresses. Use PCI endian swapping 1 so no address swapping is
28 * necessary. The Linux io routines will endian swap the data.
29 */
30#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
31#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
32
33/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
34#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
35
36/**
37 * This is the bit decoding used for the Octeon PCI controller addresses
38 */
39union octeon_pci_address {
40 uint64_t u64;
41 struct {
42 uint64_t upper:2;
43 uint64_t reserved:13;
44 uint64_t io:1;
45 uint64_t did:5;
46 uint64_t subdid:3;
47 uint64_t reserved2:4;
48 uint64_t endian_swap:2;
49 uint64_t reserved3:10;
50 uint64_t bus:8;
51 uint64_t dev:5;
52 uint64_t func:3;
53 uint64_t reg:8;
54 } s;
55};
56
57/**
58 * Return the mapping of PCI device number to IRQ line. Each
59 * character in the return string represents the interrupt
60 * line for the device at that position. Device 1 maps to the
61 * first character, etc. The characters A-D are used for PCI
62 * interrupts.
63 *
64 * Returns PCI interrupt mapping
65 */
66const char *octeon_get_pci_interrupts(void)
67{
68 /*
69 * Returning an empty string causes the interrupts to be
70 * routed based on the PCI specification. From the PCI spec:
71 *
72 * INTA# of Device Number 0 is connected to IRQW on the system
73 * board. (Device Number has no significance regarding being
74 * located on the system board or in a connector.) INTA# of
75 * Device Number 1 is connected to IRQX on the system
76 * board. INTA# of Device Number 2 is connected to IRQY on the
77 * system board. INTA# of Device Number 3 is connected to IRQZ
78 * on the system board. The table below describes how each
79 * agent's INTx# lines are connected to the system board
80 * interrupt lines. The following equation can be used to
81 * determine to which INTx# signal on the system board a given
82 * device's INTx# line(s) is connected.
83 *
84 * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
85 * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
86 * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
87 * INTD# = 3)
88 */
89 switch (octeon_bootinfo->board_type) {
90 case CVMX_BOARD_TYPE_NAO38:
91 /* This is really the NAC38 */
92 return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
93 case CVMX_BOARD_TYPE_THUNDER:
94 return "";
95 case CVMX_BOARD_TYPE_EBH3000:
96 return "";
97 case CVMX_BOARD_TYPE_EBH3100:
98 case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
99 case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
100 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
101 case CVMX_BOARD_TYPE_BBGW_REF:
102 return "AABCD";
103 default:
104 return "";
105 }
106}
107
108/**
109 * Map a PCI device to the appropriate interrupt line
110 *
111 * @dev: The Linux PCI device structure for the device to map
112 * @slot: The slot number for this device on __BUS 0__. Linux
113 * enumerates through all the bridges and figures out the
114 * slot on Bus 0 where this device eventually hooks to.
115 * @pin: The PCI interrupt pin read from the device, then swizzled
116 * as it goes through each bridge.
117 * Returns Interrupt number for the device
118 */
119int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
120 u8 slot, u8 pin)
121{
122 int irq_num;
123 const char *interrupts;
124 int dev_num;
125
126 /* Get the board specific interrupt mapping */
127 interrupts = octeon_get_pci_interrupts();
128
129 dev_num = dev->devfn >> 3;
130 if (dev_num < strlen(interrupts))
131 irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
132 OCTEON_IRQ_PCI_INT0;
133 else
134 irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
135 return irq_num;
136}
137
138
139/**
140 * Read a value from configuration space
141 *
142 */
143static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
144 int reg, int size, u32 *val)
145{
146 union octeon_pci_address pci_addr;
147
148 pci_addr.u64 = 0;
149 pci_addr.s.upper = 2;
150 pci_addr.s.io = 1;
151 pci_addr.s.did = 3;
152 pci_addr.s.subdid = 1;
153 pci_addr.s.endian_swap = 1;
154 pci_addr.s.bus = bus->number;
155 pci_addr.s.dev = devfn >> 3;
156 pci_addr.s.func = devfn & 0x7;
157 pci_addr.s.reg = reg;
158
159#if PCI_CONFIG_SPACE_DELAY
160 udelay(PCI_CONFIG_SPACE_DELAY);
161#endif
162 switch (size) {
163 case 4:
164 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
165 return PCIBIOS_SUCCESSFUL;
166 case 2:
167 *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
168 return PCIBIOS_SUCCESSFUL;
169 case 1:
170 *val = cvmx_read64_uint8(pci_addr.u64);
171 return PCIBIOS_SUCCESSFUL;
172 }
173 return PCIBIOS_FUNC_NOT_SUPPORTED;
174}
175
176
177/**
178 * Write a value to PCI configuration space
179 *
180 * @bus:
181 * @devfn:
182 * @reg:
183 * @size:
184 * @val:
185 * Returns
186 */
187static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
188 int reg, int size, u32 val)
189{
190 union octeon_pci_address pci_addr;
191
192 pci_addr.u64 = 0;
193 pci_addr.s.upper = 2;
194 pci_addr.s.io = 1;
195 pci_addr.s.did = 3;
196 pci_addr.s.subdid = 1;
197 pci_addr.s.endian_swap = 1;
198 pci_addr.s.bus = bus->number;
199 pci_addr.s.dev = devfn >> 3;
200 pci_addr.s.func = devfn & 0x7;
201 pci_addr.s.reg = reg;
202
203#if PCI_CONFIG_SPACE_DELAY
204 udelay(PCI_CONFIG_SPACE_DELAY);
205#endif
206 switch (size) {
207 case 4:
208 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
209 return PCIBIOS_SUCCESSFUL;
210 case 2:
211 cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
212 return PCIBIOS_SUCCESSFUL;
213 case 1:
214 cvmx_write64_uint8(pci_addr.u64, val);
215 return PCIBIOS_SUCCESSFUL;
216 }
217 return PCIBIOS_FUNC_NOT_SUPPORTED;
218}
219
220
221static struct pci_ops octeon_pci_ops = {
222 octeon_read_config,
223 octeon_write_config,
224};
225
226static struct resource octeon_pci_mem_resource = {
227 .start = 0,
228 .end = 0,
229 .name = "Octeon PCI MEM",
230 .flags = IORESOURCE_MEM,
231};
232
233/*
234 * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
235 * bridge
236 */
237static struct resource octeon_pci_io_resource = {
238 .start = 0x4000,
239 .end = OCTEON_PCI_IOSPACE_SIZE - 1,
240 .name = "Octeon PCI IO",
241 .flags = IORESOURCE_IO,
242};
243
244static struct pci_controller octeon_pci_controller = {
245 .pci_ops = &octeon_pci_ops,
246 .mem_resource = &octeon_pci_mem_resource,
247 .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
248 .io_resource = &octeon_pci_io_resource,
249 .io_offset = 0,
250 .io_map_base = OCTEON_PCI_IOSPACE_BASE,
251};
252
253
254/**
255 * Low level initialize the Octeon PCI controller
256 *
257 * Returns
258 */
259static void octeon_pci_initialize(void)
260{
261 union cvmx_pci_cfg01 cfg01;
262 union cvmx_npi_ctl_status ctl_status;
263 union cvmx_pci_ctl_status_2 ctl_status_2;
264 union cvmx_pci_cfg19 cfg19;
265 union cvmx_pci_cfg16 cfg16;
266 union cvmx_pci_cfg22 cfg22;
267 union cvmx_pci_cfg56 cfg56;
268
269 /* Reset the PCI Bus */
270 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
271 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
272
273 udelay(2000); /* Hold PCI reset for 2 ms */
274
275 ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
276 ctl_status.s.max_word = 1;
277 ctl_status.s.timer = 1;
278 cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
279
280 /* Deassert PCI reset and advertize PCX Host Mode Device Capability
281 (64b) */
282 cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
283 cvmx_read_csr(CVMX_CIU_SOFT_PRST);
284
285 udelay(2000); /* Wait 2 ms after deasserting PCI reset */
286
287 ctl_status_2.u32 = 0;
288 ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
289 before any PCI reads. */
290 ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
291 ctl_status_2.s.bar2_enb = 1;
292 ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
293 ctl_status_2.s.bar2_esx = 1;
294 ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
295 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
296 /* BAR1 hole */
297 ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
298 ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
299 ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
300 ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
301 ctl_status_2.s.bb1 = 1; /* BAR1 is big */
302 ctl_status_2.s.bb0 = 1; /* BAR0 is big */
303 }
304
305 octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
306 udelay(2000); /* Wait 2 ms before doing PCI reads */
307
308 ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
309 pr_notice("PCI Status: %s %s-bit\n",
310 ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
311 ctl_status_2.s.ap_64ad ? "64" : "32");
312
313 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
314 union cvmx_pci_cnt_reg cnt_reg_start;
315 union cvmx_pci_cnt_reg cnt_reg_end;
316 unsigned long cycles, pci_clock;
317
318 cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
319 cycles = read_c0_cvmcount();
320 udelay(1000);
321 cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
322 cycles = read_c0_cvmcount() - cycles;
323 pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
324 (cycles / (mips_hpt_frequency / 1000000));
325 pr_notice("PCI Clock: %lu MHz\n", pci_clock);
326 }
327
328 /*
329 * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
330 * in PCI-X mode to allow four oustanding splits. Otherwise,
331 * should not change from its reset value. Don't write PCI_CFG19
332 * in PCI mode (0x82000001 reset value), write it to 0x82000004
333 * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
334 * MRBCM -> must be one.
335 */
336 if (ctl_status_2.s.ap_pcix) {
337 cfg19.u32 = 0;
338 /*
339 * Target Delayed/Split request outstanding maximum
340 * count. [1..31] and 0=32. NOTE: If the user
341 * programs these bits beyond the Designed Maximum
342 * outstanding count, then the designed maximum table
343 * depth will be used instead. No additional
344 * Deferred/Split transactions will be accepted if
345 * this outstanding maximum count is
346 * reached. Furthermore, no additional deferred/split
347 * transactions will be accepted if the I/O delay/ I/O
348 * Split Request outstanding maximum is reached.
349 */
350 cfg19.s.tdomc = 4;
351 /*
352 * Master Deferred Read Request Outstanding Max Count
353 * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
354 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
355 * 5 2 110 6 3 111 7 3 For example, if these bits are
356 * programmed to 100, the core can support 2 DAC
357 * cycles, 4 SAC cycles or a combination of 1 DAC and
358 * 2 SAC cycles. NOTE: For the PCI-X maximum
359 * outstanding split transactions, refer to
360 * CRE0[22:20].
361 */
362 cfg19.s.mdrrmc = 2;
363 /*
364 * Master Request (Memory Read) Byte Count/Byte Enable
365 * select. 0 = Byte Enables valid. In PCI mode, a
366 * burst transaction cannot be performed using Memory
367 * Read command=4?h6. 1 = DWORD Byte Count valid
368 * (default). In PCI Mode, the memory read byte
369 * enables are automatically generated by the
370 * core. Note: N3 Master Request transaction sizes are
371 * always determined through the
372 * am_attr[<35:32>|<7:0>] field.
373 */
374 cfg19.s.mrbcm = 1;
375 octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
376 }
377
378
379 cfg01.u32 = 0;
380 cfg01.s.msae = 1; /* Memory Space Access Enable */
381 cfg01.s.me = 1; /* Master Enable */
382 cfg01.s.pee = 1; /* PERR# Enable */
383 cfg01.s.see = 1; /* System Error Enable */
384 cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
385
386 octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
387
388#ifdef USE_OCTEON_INTERNAL_ARBITER
389 /*
390 * When OCTEON is a PCI host, most systems will use OCTEON's
391 * internal arbiter, so must enable it before any PCI/PCI-X
392 * traffic can occur.
393 */
394 {
395 union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
396
397 pci_int_arb_cfg.u64 = 0;
398 pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
399 cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
400 }
401#endif /* USE_OCTEON_INTERNAL_ARBITER */
402
403 /*
404 * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
405 * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
406 * 1..7.
407 */
408 cfg16.u32 = 0;
409 cfg16.s.mltd = 1; /* Master Latency Timer Disable */
410 octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
411
412 /*
413 * Should be written to 0x4ff00. MTTV -> must be zero.
414 * FLUSH -> must be 1. MRV -> should be 0xFF.
415 */
416 cfg22.u32 = 0;
417 /* Master Retry Value [1..255] and 0=infinite */
418 cfg22.s.mrv = 0xff;
419 /*
420 * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
421 * N3K operation.
422 */
423 cfg22.s.flush = 1;
424 octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
425
426 /*
427 * MOST Indicates the maximum number of outstanding splits (in -1
428 * notation) when OCTEON is in PCI-X mode. PCI-X performance is
429 * affected by the MOST selection. Should generally be written
430 * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
431 * depending on the desired MOST of 3, 2, 1, or 0, respectively.
432 */
433 cfg56.u32 = 0;
434 cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
435 cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
436 cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
437 cfg56.s.roe = 1; /* Relaxed Ordering Enable */
438 cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
439 [0=512B,1=1024B,2=2048B,3=4096B] */
440 cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
441 .. 7=32] */
442
443 octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
444
445 /*
446 * Affects PCI performance when OCTEON services reads to its
447 * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
448 * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
449 * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
450 * these values need to be changed so they won't possibly prefetch off
451 * of the end of memory if PCI is DMAing a buffer at the end of
452 * memory. Note that these values differ from their reset values.
453 */
454 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
455 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
456 octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
457}
458
459
460/**
461 * Initialize the Octeon PCI controller
462 *
463 * Returns
464 */
465static int __init octeon_pci_setup(void)
466{
467 union cvmx_npi_mem_access_subidx mem_access;
468 int index;
469
470 /* Only these chips have PCI */
471 if (octeon_has_feature(OCTEON_FEATURE_PCIE))
472 return 0;
473
474 /* Point pcibios_map_irq() to the PCI version of it */
475 octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
476
477 /* Only use the big bars on chips that support it */
478 if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
479 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
480 OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
481 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
482 else
483 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
484
485 /* PCI I/O and PCI MEM values */
486 set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
487 ioport_resource.start = 0;
488 ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
489 if (!octeon_is_pci_host()) {
490 pr_notice("Not in host mode, PCI Controller not initialized\n");
491 return 0;
492 }
493
494 pr_notice("%s Octeon big bar support\n",
495 (octeon_dma_bar_type ==
496 OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
497
498 octeon_pci_initialize();
499
500 mem_access.u64 = 0;
501 mem_access.s.esr = 1; /* Endian-Swap on read. */
502 mem_access.s.esw = 1; /* Endian-Swap on write. */
503 mem_access.s.nsr = 0; /* No-Snoop on read. */
504 mem_access.s.nsw = 0; /* No-Snoop on write. */
505 mem_access.s.ror = 0; /* Relax Read on read. */
506 mem_access.s.row = 0; /* Relax Order on write. */
507 mem_access.s.ba = 0; /* PCI Address bits [63:36]. */
508 cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
509
510 /*
511 * Remap the Octeon BAR 2 above all 32 bit devices
512 * (0x8000000000ul). This is done here so it is remapped
513 * before the readl()'s below. We don't want BAR2 overlapping
514 * with BAR0/BAR1 during these reads.
515 */
516 octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
517 octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
518
519 /* Disable the BAR1 movable mappings */
520 for (index = 0; index < 32; index++)
521 octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
522
523 if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
524 /* Remap the Octeon BAR 0 to 0-2GB */
525 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
526 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
527
528 /*
529 * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
530 * BAR 1 hole).
531 */
532 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
533 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
534
535 /* Devices go after BAR1 */
536 octeon_pci_mem_resource.start =
537 OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
538 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
539 octeon_pci_mem_resource.end =
540 octeon_pci_mem_resource.start + (1ul << 30);
541 } else {
542 /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
543 octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
544 octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
545
546 /* Remap the Octeon BAR 1 to map 0-128MB */
547 octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
548 octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
549
550 /* Devices go after BAR0 */
551 octeon_pci_mem_resource.start =
552 OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
553 (4ul << 10);
554 octeon_pci_mem_resource.end =
555 octeon_pci_mem_resource.start + (1ul << 30);
556 }
557
558 register_pci_controller(&octeon_pci_controller);
559
560 /*
561 * Clear any errors that might be pending from before the bus
562 * was setup properly.
563 */
564 cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
565 return 0;
566}
567
568arch_initcall(octeon_pci_setup);
diff --git a/arch/mips/cavium-octeon/pcie.c b/arch/mips/cavium-octeon/pcie.c
new file mode 100644
index 000000000000..49d14081b3b5
--- /dev/null
+++ b/arch/mips/cavium-octeon/pcie.c
@@ -0,0 +1,1370 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007, 2008 Cavium Networks
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/interrupt.h>
12#include <linux/time.h>
13#include <linux/delay.h>
14
15#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-npei-defs.h>
17#include <asm/octeon/cvmx-pciercx-defs.h>
18#include <asm/octeon/cvmx-pescx-defs.h>
19#include <asm/octeon/cvmx-pexp-defs.h>
20#include <asm/octeon/cvmx-helper-errata.h>
21
22#include "pci-common.h"
23
24union cvmx_pcie_address {
25 uint64_t u64;
26 struct {
27 uint64_t upper:2; /* Normally 2 for XKPHYS */
28 uint64_t reserved_49_61:13; /* Must be zero */
29 uint64_t io:1; /* 1 for IO space access */
30 uint64_t did:5; /* PCIe DID = 3 */
31 uint64_t subdid:3; /* PCIe SubDID = 1 */
32 uint64_t reserved_36_39:4; /* Must be zero */
33 uint64_t es:2; /* Endian swap = 1 */
34 uint64_t port:2; /* PCIe port 0,1 */
35 uint64_t reserved_29_31:3; /* Must be zero */
36 /*
37 * Selects the type of the configuration request (0 = type 0,
38 * 1 = type 1).
39 */
40 uint64_t ty:1;
41 /* Target bus number sent in the ID in the request. */
42 uint64_t bus:8;
43 /*
44 * Target device number sent in the ID in the
45 * request. Note that Dev must be zero for type 0
46 * configuration requests.
47 */
48 uint64_t dev:5;
49 /* Target function number sent in the ID in the request. */
50 uint64_t func:3;
51 /*
52 * Selects a register in the configuration space of
53 * the target.
54 */
55 uint64_t reg:12;
56 } config;
57 struct {
58 uint64_t upper:2; /* Normally 2 for XKPHYS */
59 uint64_t reserved_49_61:13; /* Must be zero */
60 uint64_t io:1; /* 1 for IO space access */
61 uint64_t did:5; /* PCIe DID = 3 */
62 uint64_t subdid:3; /* PCIe SubDID = 2 */
63 uint64_t reserved_36_39:4; /* Must be zero */
64 uint64_t es:2; /* Endian swap = 1 */
65 uint64_t port:2; /* PCIe port 0,1 */
66 uint64_t address:32; /* PCIe IO address */
67 } io;
68 struct {
69 uint64_t upper:2; /* Normally 2 for XKPHYS */
70 uint64_t reserved_49_61:13; /* Must be zero */
71 uint64_t io:1; /* 1 for IO space access */
72 uint64_t did:5; /* PCIe DID = 3 */
73 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
74 uint64_t reserved_36_39:4; /* Must be zero */
75 uint64_t address:36; /* PCIe Mem address */
76 } mem;
77};
78
79/**
80 * Return the Core virtual base address for PCIe IO access. IOs are
81 * read/written as an offset from this address.
82 *
83 * @pcie_port: PCIe port the IO is for
84 *
85 * Returns 64bit Octeon IO base address for read/write
86 */
87static inline uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
88{
89 union cvmx_pcie_address pcie_addr;
90 pcie_addr.u64 = 0;
91 pcie_addr.io.upper = 0;
92 pcie_addr.io.io = 1;
93 pcie_addr.io.did = 3;
94 pcie_addr.io.subdid = 2;
95 pcie_addr.io.es = 1;
96 pcie_addr.io.port = pcie_port;
97 return pcie_addr.u64;
98}
99
100/**
101 * Size of the IO address region returned at address
102 * cvmx_pcie_get_io_base_address()
103 *
104 * @pcie_port: PCIe port the IO is for
105 *
106 * Returns Size of the IO window
107 */
108static inline uint64_t cvmx_pcie_get_io_size(int pcie_port)
109{
110 return 1ull << 32;
111}
112
113/**
114 * Return the Core virtual base address for PCIe MEM access. Memory is
115 * read/written as an offset from this address.
116 *
117 * @pcie_port: PCIe port the IO is for
118 *
119 * Returns 64bit Octeon IO base address for read/write
120 */
121static inline uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
122{
123 union cvmx_pcie_address pcie_addr;
124 pcie_addr.u64 = 0;
125 pcie_addr.mem.upper = 0;
126 pcie_addr.mem.io = 1;
127 pcie_addr.mem.did = 3;
128 pcie_addr.mem.subdid = 3 + pcie_port;
129 return pcie_addr.u64;
130}
131
132/**
133 * Size of the Mem address region returned at address
134 * cvmx_pcie_get_mem_base_address()
135 *
136 * @pcie_port: PCIe port the IO is for
137 *
138 * Returns Size of the Mem window
139 */
140static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
141{
142 return 1ull << 36;
143}
144
145/**
146 * Read a PCIe config space register indirectly. This is used for
147 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
148 *
149 * @pcie_port: PCIe port to read from
150 * @cfg_offset: Address to read
151 *
152 * Returns Value read
153 */
154static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
155{
156 union cvmx_pescx_cfg_rd pescx_cfg_rd;
157 pescx_cfg_rd.u64 = 0;
158 pescx_cfg_rd.s.addr = cfg_offset;
159 cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
160 pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
161 return pescx_cfg_rd.s.data;
162}
163
164/**
165 * Write a PCIe config space register indirectly. This is used for
166 * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
167 *
168 * @pcie_port: PCIe port to write to
169 * @cfg_offset: Address to write
170 * @val: Value to write
171 */
172static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
173 uint32_t val)
174{
175 union cvmx_pescx_cfg_wr pescx_cfg_wr;
176 pescx_cfg_wr.u64 = 0;
177 pescx_cfg_wr.s.addr = cfg_offset;
178 pescx_cfg_wr.s.data = val;
179 cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
180}
181
182/**
183 * Build a PCIe config space request address for a device
184 *
185 * @pcie_port: PCIe port to access
186 * @bus: Sub bus
187 * @dev: Device ID
188 * @fn: Device sub function
189 * @reg: Register to access
190 *
191 * Returns 64bit Octeon IO address
192 */
193static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
194 int dev, int fn, int reg)
195{
196 union cvmx_pcie_address pcie_addr;
197 union cvmx_pciercx_cfg006 pciercx_cfg006;
198
199 pciercx_cfg006.u32 =
200 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
201 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
202 return 0;
203
204 pcie_addr.u64 = 0;
205 pcie_addr.config.upper = 2;
206 pcie_addr.config.io = 1;
207 pcie_addr.config.did = 3;
208 pcie_addr.config.subdid = 1;
209 pcie_addr.config.es = 1;
210 pcie_addr.config.port = pcie_port;
211 pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
212 pcie_addr.config.bus = bus;
213 pcie_addr.config.dev = dev;
214 pcie_addr.config.func = fn;
215 pcie_addr.config.reg = reg;
216 return pcie_addr.u64;
217}
218
219/**
220 * Read 8bits from a Device's config space
221 *
222 * @pcie_port: PCIe port the device is on
223 * @bus: Sub bus
224 * @dev: Device ID
225 * @fn: Device sub function
226 * @reg: Register to access
227 *
228 * Returns Result of the read
229 */
230static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
231 int fn, int reg)
232{
233 uint64_t address =
234 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
235 if (address)
236 return cvmx_read64_uint8(address);
237 else
238 return 0xff;
239}
240
241/**
242 * Read 16bits from a Device's config space
243 *
244 * @pcie_port: PCIe port the device is on
245 * @bus: Sub bus
246 * @dev: Device ID
247 * @fn: Device sub function
248 * @reg: Register to access
249 *
250 * Returns Result of the read
251 */
252static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
253 int fn, int reg)
254{
255 uint64_t address =
256 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
257 if (address)
258 return le16_to_cpu(cvmx_read64_uint16(address));
259 else
260 return 0xffff;
261}
262
263/**
264 * Read 32bits from a Device's config space
265 *
266 * @pcie_port: PCIe port the device is on
267 * @bus: Sub bus
268 * @dev: Device ID
269 * @fn: Device sub function
270 * @reg: Register to access
271 *
272 * Returns Result of the read
273 */
274static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
275 int fn, int reg)
276{
277 uint64_t address =
278 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
279 if (address)
280 return le32_to_cpu(cvmx_read64_uint32(address));
281 else
282 return 0xffffffff;
283}
284
285/**
286 * Write 8bits to a Device's config space
287 *
288 * @pcie_port: PCIe port the device is on
289 * @bus: Sub bus
290 * @dev: Device ID
291 * @fn: Device sub function
292 * @reg: Register to access
293 * @val: Value to write
294 */
295static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
296 int reg, uint8_t val)
297{
298 uint64_t address =
299 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
300 if (address)
301 cvmx_write64_uint8(address, val);
302}
303
304/**
305 * Write 16bits to a Device's config space
306 *
307 * @pcie_port: PCIe port the device is on
308 * @bus: Sub bus
309 * @dev: Device ID
310 * @fn: Device sub function
311 * @reg: Register to access
312 * @val: Value to write
313 */
314static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
315 int reg, uint16_t val)
316{
317 uint64_t address =
318 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
319 if (address)
320 cvmx_write64_uint16(address, cpu_to_le16(val));
321}
322
323/**
324 * Write 32bits to a Device's config space
325 *
326 * @pcie_port: PCIe port the device is on
327 * @bus: Sub bus
328 * @dev: Device ID
329 * @fn: Device sub function
330 * @reg: Register to access
331 * @val: Value to write
332 */
333static void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
334 int reg, uint32_t val)
335{
336 uint64_t address =
337 __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
338 if (address)
339 cvmx_write64_uint32(address, cpu_to_le32(val));
340}
341
342/**
343 * Initialize the RC config space CSRs
344 *
345 * @pcie_port: PCIe port to initialize
346 */
347static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
348{
349 union cvmx_pciercx_cfg030 pciercx_cfg030;
350 union cvmx_npei_ctl_status2 npei_ctl_status2;
351 union cvmx_pciercx_cfg070 pciercx_cfg070;
352 union cvmx_pciercx_cfg001 pciercx_cfg001;
353 union cvmx_pciercx_cfg032 pciercx_cfg032;
354 union cvmx_pciercx_cfg006 pciercx_cfg006;
355 union cvmx_pciercx_cfg008 pciercx_cfg008;
356 union cvmx_pciercx_cfg009 pciercx_cfg009;
357 union cvmx_pciercx_cfg010 pciercx_cfg010;
358 union cvmx_pciercx_cfg011 pciercx_cfg011;
359 union cvmx_pciercx_cfg035 pciercx_cfg035;
360 union cvmx_pciercx_cfg075 pciercx_cfg075;
361 union cvmx_pciercx_cfg034 pciercx_cfg034;
362
363 /* Max Payload Size (PCIE*_CFG030[MPS]) */
364 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
365 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
366 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
367 pciercx_cfg030.u32 =
368 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
369 /*
370 * Max payload size = 128 bytes for best Octeon DMA
371 * performance.
372 */
373 pciercx_cfg030.s.mps = 0;
374 /*
375 * Max read request size = 128 bytes for best Octeon DMA
376 * performance.
377 */
378 pciercx_cfg030.s.mrrs = 0;
379 /* Enable relaxed ordering. */
380 pciercx_cfg030.s.ro_en = 1;
381 /* Enable no snoop. */
382 pciercx_cfg030.s.ns_en = 1;
383 /* Correctable error reporting enable. */
384 pciercx_cfg030.s.ce_en = 1;
385 /* Non-fatal error reporting enable. */
386 pciercx_cfg030.s.nfe_en = 1;
387 /* Fatal error reporting enable. */
388 pciercx_cfg030.s.fe_en = 1;
389 /* Unsupported request reporting enable. */
390 pciercx_cfg030.s.ur_en = 1;
391 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
392 pciercx_cfg030.u32);
393
394 /*
395 * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
396 * PCIE*_CFG030[MPS]
397 *
398 * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
399 * exceed PCIE*_CFG030[MRRS].
400 */
401 npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
402 /* Max payload size = 128 bytes for best Octeon DMA performance */
403 npei_ctl_status2.s.mps = 0;
404 /* Max read request size = 128 bytes for best Octeon DMA performance */
405 npei_ctl_status2.s.mrrs = 0;
406 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
407
408 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
409 pciercx_cfg070.u32 =
410 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
411 pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
412 pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
413 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
414 pciercx_cfg070.u32);
415
416 /*
417 * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
418 * always be set.
419 *
420 * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
421 * Message Enable (PCIE*_CFG001[SEE])
422 */
423 pciercx_cfg001.u32 =
424 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
425 pciercx_cfg001.s.msae = 1; /* Memory space enable. */
426 pciercx_cfg001.s.me = 1; /* Bus master enable. */
427 pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
428 pciercx_cfg001.s.see = 1; /* SERR# enable */
429 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
430 pciercx_cfg001.u32);
431
432 /* Advanced Error Recovery Message Enables */
433 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
434 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
435 /* Use CVMX_PCIERCX_CFG067 hardware default */
436 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
437
438 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
439 pciercx_cfg032.u32 =
440 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
441 pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
442 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
443 pciercx_cfg032.u32);
444
445 /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
446
447 /*
448 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
449 * cvmx_pcie_rc_initialize_link()
450 *
451 * Primary Bus Number (PCIERCn_CFG006[PBNUM])
452 *
453 * We set the primary bus number to 1 so IDT bridges are
454 * happy. They don't like zero.
455 */
456 pciercx_cfg006.u32 = 0;
457 pciercx_cfg006.s.pbnum = 1;
458 pciercx_cfg006.s.sbnum = 1;
459 pciercx_cfg006.s.subbnum = 1;
460 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
461 pciercx_cfg006.u32);
462
463 /*
464 * Memory-mapped I/O BAR (PCIERCn_CFG008)
465 * Most applications should disable the memory-mapped I/O BAR by
466 * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
467 */
468 pciercx_cfg008.u32 = 0;
469 pciercx_cfg008.s.mb_addr = 0x100;
470 pciercx_cfg008.s.ml_addr = 0;
471 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
472 pciercx_cfg008.u32);
473
474 /*
475 * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
476 * Most applications should disable the prefetchable BAR by setting
477 * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
478 * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
479 */
480 pciercx_cfg009.u32 =
481 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
482 pciercx_cfg010.u32 =
483 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
484 pciercx_cfg011.u32 =
485 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
486 pciercx_cfg009.s.lmem_base = 0x100;
487 pciercx_cfg009.s.lmem_limit = 0;
488 pciercx_cfg010.s.umem_base = 0x100;
489 pciercx_cfg011.s.umem_limit = 0;
490 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
491 pciercx_cfg009.u32);
492 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
493 pciercx_cfg010.u32);
494 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
495 pciercx_cfg011.u32);
496
497 /*
498 * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
499 * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
500 */
501 pciercx_cfg035.u32 =
502 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
503 /* System error on correctable error enable. */
504 pciercx_cfg035.s.secee = 1;
505 /* System error on fatal error enable. */
506 pciercx_cfg035.s.sefee = 1;
507 /* System error on non-fatal error enable. */
508 pciercx_cfg035.s.senfee = 1;
509 /* PME interrupt enable. */
510 pciercx_cfg035.s.pmeie = 1;
511 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
512 pciercx_cfg035.u32);
513
514 /*
515 * Advanced Error Recovery Interrupt Enables
516 * (PCIERCn_CFG075[CERE,NFERE,FERE])
517 */
518 pciercx_cfg075.u32 =
519 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
520 /* Correctable error reporting enable. */
521 pciercx_cfg075.s.cere = 1;
522 /* Non-fatal error reporting enable. */
523 pciercx_cfg075.s.nfere = 1;
524 /* Fatal error reporting enable. */
525 pciercx_cfg075.s.fere = 1;
526 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
527 pciercx_cfg075.u32);
528
529 /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
530 * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
531 */
532 pciercx_cfg034.u32 =
533 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
534 /* Hot-plug interrupt enable. */
535 pciercx_cfg034.s.hpint_en = 1;
536 /* Data Link Layer state changed enable */
537 pciercx_cfg034.s.dlls_en = 1;
538 /* Command completed interrupt enable. */
539 pciercx_cfg034.s.ccint_en = 1;
540 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
541 pciercx_cfg034.u32);
542}
543
544/**
545 * Initialize a host mode PCIe link. This function takes a PCIe
546 * port from reset to a link up state. Software can then begin
547 * configuring the rest of the link.
548 *
549 * @pcie_port: PCIe port to initialize
550 *
551 * Returns Zero on success
552 */
553static int __cvmx_pcie_rc_initialize_link(int pcie_port)
554{
555 uint64_t start_cycle;
556 union cvmx_pescx_ctl_status pescx_ctl_status;
557 union cvmx_pciercx_cfg452 pciercx_cfg452;
558 union cvmx_pciercx_cfg032 pciercx_cfg032;
559 union cvmx_pciercx_cfg448 pciercx_cfg448;
560
561 /* Set the lane width */
562 pciercx_cfg452.u32 =
563 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
564 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
565 if (pescx_ctl_status.s.qlm_cfg == 0) {
566 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
567 pciercx_cfg452.s.lme = 0xf;
568 } else {
569 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
570 pciercx_cfg452.s.lme = 0x7;
571 }
572 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
573 pciercx_cfg452.u32);
574
575 /*
576 * CN52XX pass 1.x has an errata where length mismatches on UR
577 * responses can cause bus errors on 64bit memory
578 * reads. Turning off length error checking fixes this.
579 */
580 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
581 union cvmx_pciercx_cfg455 pciercx_cfg455;
582 pciercx_cfg455.u32 =
583 cvmx_pcie_cfgx_read(pcie_port,
584 CVMX_PCIERCX_CFG455(pcie_port));
585 pciercx_cfg455.s.m_cpl_len_err = 1;
586 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
587 pciercx_cfg455.u32);
588 }
589
590 /* Lane swap needs to be manually enabled for CN52XX */
591 if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
592 pescx_ctl_status.s.lane_swp = 1;
593 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
594 pescx_ctl_status.u64);
595 }
596
597 /* Bring up the link */
598 pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
599 pescx_ctl_status.s.lnk_enb = 1;
600 cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
601
602 /*
603 * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
604 * be disabled.
605 */
606 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
607 __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
608
609 /* Wait for the link to come up */
610 cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
611 start_cycle = cvmx_get_cycle();
612 do {
613 if (cvmx_get_cycle() - start_cycle >
614 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
615 cvmx_dprintf("PCIe: Port %d link timeout\n",
616 pcie_port);
617 return -1;
618 }
619 cvmx_wait(10000);
620 pciercx_cfg032.u32 =
621 cvmx_pcie_cfgx_read(pcie_port,
622 CVMX_PCIERCX_CFG032(pcie_port));
623 } while (pciercx_cfg032.s.dlla == 0);
624
625 /* Display the link status */
626 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
627 pciercx_cfg032.s.nlw);
628
629 /*
630 * Update the Replay Time Limit. Empirically, some PCIe
631 * devices take a little longer to respond than expected under
632 * load. As a workaround for this we configure the Replay Time
633 * Limit to the value expected for a 512 byte MPS instead of
634 * our actual 256 byte MPS. The numbers below are directly
635 * from the PCIe spec table 3-4.
636 */
637 pciercx_cfg448.u32 =
638 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
639 switch (pciercx_cfg032.s.nlw) {
640 case 1: /* 1 lane */
641 pciercx_cfg448.s.rtl = 1677;
642 break;
643 case 2: /* 2 lanes */
644 pciercx_cfg448.s.rtl = 867;
645 break;
646 case 4: /* 4 lanes */
647 pciercx_cfg448.s.rtl = 462;
648 break;
649 case 8: /* 8 lanes */
650 pciercx_cfg448.s.rtl = 258;
651 break;
652 }
653 cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
654 pciercx_cfg448.u32);
655
656 return 0;
657}
658
659/**
660 * Initialize a PCIe port for use in host(RC) mode. It doesn't
661 * enumerate the bus.
662 *
663 * @pcie_port: PCIe port to initialize
664 *
665 * Returns Zero on success
666 */
667static int cvmx_pcie_rc_initialize(int pcie_port)
668{
669 int i;
670 union cvmx_ciu_soft_prst ciu_soft_prst;
671 union cvmx_pescx_bist_status pescx_bist_status;
672 union cvmx_pescx_bist_status2 pescx_bist_status2;
673 union cvmx_npei_ctl_status npei_ctl_status;
674 union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
675 union cvmx_npei_mem_access_subidx mem_access_subid;
676 union cvmx_npei_dbg_data npei_dbg_data;
677 union cvmx_pescx_ctl_status2 pescx_ctl_status2;
678
679 /*
680 * Make sure we aren't trying to setup a target mode interface
681 * in host mode.
682 */
683 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
684 if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
685 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
686 "on port0, but port0 is not in host mode\n");
687 return -1;
688 }
689
690 /*
691 * Make sure a CN52XX isn't trying to bring up port 1 when it
692 * is disabled.
693 */
694 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
695 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
696 if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
697 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
698 "called on port1, but port1 is "
699 "disabled\n");
700 return -1;
701 }
702 }
703
704 /*
705 * PCIe switch arbitration mode. '0' == fixed priority NPEI,
706 * PCIe0, then PCIe1. '1' == round robin.
707 */
708 npei_ctl_status.s.arb = 1;
709 /* Allow up to 0x20 config retries */
710 npei_ctl_status.s.cfg_rtry = 0x20;
711 /*
712 * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
713 * don't reset.
714 */
715 if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
716 npei_ctl_status.s.p0_ntags = 0x20;
717 npei_ctl_status.s.p1_ntags = 0x20;
718 }
719 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
720
721 /* Bring the PCIe out of reset */
722 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
723 /*
724 * The EBH5200 board swapped the PCIe reset lines on
725 * the board. As a workaround for this bug, we bring
726 * both PCIe ports out of reset at the same time
727 * instead of on separate calls. So for port 0, we
728 * bring both out of reset and do nothing on port 1.
729 */
730 if (pcie_port == 0) {
731 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
732 /*
733 * After a chip reset the PCIe will also be in
734 * reset. If it isn't, most likely someone is
735 * trying to init it again without a proper
736 * PCIe reset.
737 */
738 if (ciu_soft_prst.s.soft_prst == 0) {
739 /* Reset the ports */
740 ciu_soft_prst.s.soft_prst = 1;
741 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
742 ciu_soft_prst.u64);
743 ciu_soft_prst.u64 =
744 cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
745 ciu_soft_prst.s.soft_prst = 1;
746 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
747 ciu_soft_prst.u64);
748 /* Wait until pcie resets the ports. */
749 udelay(2000);
750 }
751 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
752 ciu_soft_prst.s.soft_prst = 0;
753 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
754 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
755 ciu_soft_prst.s.soft_prst = 0;
756 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
757 }
758 } else {
759 /*
760 * The normal case: The PCIe ports are completely
761 * separate and can be brought out of reset
762 * independently.
763 */
764 if (pcie_port)
765 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
766 else
767 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
768 /*
769 * After a chip reset the PCIe will also be in
770 * reset. If it isn't, most likely someone is trying
771 * to init it again without a proper PCIe reset.
772 */
773 if (ciu_soft_prst.s.soft_prst == 0) {
774 /* Reset the port */
775 ciu_soft_prst.s.soft_prst = 1;
776 if (pcie_port)
777 cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
778 ciu_soft_prst.u64);
779 else
780 cvmx_write_csr(CVMX_CIU_SOFT_PRST,
781 ciu_soft_prst.u64);
782 /* Wait until pcie resets the ports. */
783 udelay(2000);
784 }
785 if (pcie_port) {
786 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
787 ciu_soft_prst.s.soft_prst = 0;
788 cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
789 } else {
790 ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
791 ciu_soft_prst.s.soft_prst = 0;
792 cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
793 }
794 }
795
796 /*
797 * Wait for PCIe reset to complete. Due to errata PCIE-700, we
798 * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
799 * fixed number of cycles.
800 */
801 cvmx_wait(400000);
802
803 /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
804 CN52XX, so we only probe it on newer chips */
805 if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
806 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
807 /* Clear PCLK_RUN so we can check if the clock is running */
808 pescx_ctl_status2.u64 =
809 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
810 pescx_ctl_status2.s.pclk_run = 1;
811 cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
812 pescx_ctl_status2.u64);
813 /*
814 * Now that we cleared PCLK_RUN, wait for it to be set
815 * again telling us the clock is running.
816 */
817 if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
818 union cvmx_pescx_ctl_status2,
819 pclk_run, ==, 1, 10000)) {
820 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
821 pcie_port);
822 return -1;
823 }
824 }
825
826 /*
827 * Check and make sure PCIe came out of reset. If it doesn't
828 * the board probably hasn't wired the clocks up and the
829 * interface should be skipped.
830 */
831 pescx_ctl_status2.u64 =
832 cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
833 if (pescx_ctl_status2.s.pcierst) {
834 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
835 pcie_port);
836 return -1;
837 }
838
839 /*
840 * Check BIST2 status. If any bits are set skip this interface. This
841 * is an attempt to catch PCIE-813 on pass 1 parts.
842 */
843 pescx_bist_status2.u64 =
844 cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
845 if (pescx_bist_status2.u64) {
846 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
847 "port isn't hooked up, skipping.\n",
848 pcie_port);
849 return -1;
850 }
851
852 /* Check BIST status */
853 pescx_bist_status.u64 =
854 cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
855 if (pescx_bist_status.u64)
856 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
857 pcie_port, CAST64(pescx_bist_status.u64));
858
859 /* Initialize the config space CSRs */
860 __cvmx_pcie_rc_initialize_config_space(pcie_port);
861
862 /* Bring the link up */
863 if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
864 cvmx_dprintf
865 ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
866 return -1;
867 }
868
869 /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
870 npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
871 /* Allow 16 words to combine */
872 npei_mem_access_ctl.s.max_word = 0;
873 /* Wait up to 127 cycles for more data */
874 npei_mem_access_ctl.s.timer = 127;
875 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
876
877 /* Setup Mem access SubDIDs */
878 mem_access_subid.u64 = 0;
879 /* Port the request is sent to. */
880 mem_access_subid.s.port = pcie_port;
881 /* Due to an errata on pass 1 chips, no merging is allowed. */
882 mem_access_subid.s.nmerge = 1;
883 /* Endian-swap for Reads. */
884 mem_access_subid.s.esr = 1;
885 /* Endian-swap for Writes. */
886 mem_access_subid.s.esw = 1;
887 /* No Snoop for Reads. */
888 mem_access_subid.s.nsr = 1;
889 /* No Snoop for Writes. */
890 mem_access_subid.s.nsw = 1;
891 /* Disable Relaxed Ordering for Reads. */
892 mem_access_subid.s.ror = 0;
893 /* Disable Relaxed Ordering for Writes. */
894 mem_access_subid.s.row = 0;
895 /* PCIe Adddress Bits <63:34>. */
896 mem_access_subid.s.ba = 0;
897
898 /*
899 * Setup mem access 12-15 for port 0, 16-19 for port 1,
900 * supplying 36 bits of address space.
901 */
902 for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
903 cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
904 mem_access_subid.u64);
905 /* Set each SUBID to extend the addressable range */
906 mem_access_subid.s.ba += 1;
907 }
908
909 /*
910 * Disable the peer to peer forwarding register. This must be
911 * setup by the OS after it enumerates the bus and assigns
912 * addresses to the PCIe busses.
913 */
914 for (i = 0; i < 4; i++) {
915 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
916 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
917 }
918
919 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
920 cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
921
922 /*
923 * Disable Octeon's BAR1. It isn't needed in RC mode since
924 * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
925 * the 2nd 256MB of memory.
926 */
927 cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
928
929 /*
930 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
931 * precedence where they overlap. It also overlaps with the
932 * device addresses, so make sure the peer to peer forwarding
933 * is set right.
934 */
935 cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
936
937 /*
938 * Setup BAR2 attributes
939 *
940 * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
941 * - PTLP_RO,CTLP_RO should normally be set (except for debug).
942 * - WAIT_COM=0 will likely work for all applications.
943 *
944 * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
945 */
946 if (pcie_port) {
947 union cvmx_npei_ctl_port1 npei_ctl_port;
948 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
949 npei_ctl_port.s.bar2_enb = 1;
950 npei_ctl_port.s.bar2_esx = 1;
951 npei_ctl_port.s.bar2_cax = 0;
952 npei_ctl_port.s.ptlp_ro = 1;
953 npei_ctl_port.s.ctlp_ro = 1;
954 npei_ctl_port.s.wait_com = 0;
955 npei_ctl_port.s.waitl_com = 0;
956 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
957 } else {
958 union cvmx_npei_ctl_port0 npei_ctl_port;
959 npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
960 npei_ctl_port.s.bar2_enb = 1;
961 npei_ctl_port.s.bar2_esx = 1;
962 npei_ctl_port.s.bar2_cax = 0;
963 npei_ctl_port.s.ptlp_ro = 1;
964 npei_ctl_port.s.ctlp_ro = 1;
965 npei_ctl_port.s.wait_com = 0;
966 npei_ctl_port.s.waitl_com = 0;
967 cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
968 }
969 return 0;
970}
971
972
973/* Above was cvmx-pcie.c, below original pcie.c */
974
975
976/**
977 * Map a PCI device to the appropriate interrupt line
978 *
979 * @param dev The Linux PCI device structure for the device to map
980 * @param slot The slot number for this device on __BUS 0__. Linux
981 * enumerates through all the bridges and figures out the
982 * slot on Bus 0 where this device eventually hooks to.
983 * @param pin The PCI interrupt pin read from the device, then swizzled
984 * as it goes through each bridge.
985 * @return Interrupt number for the device
986 */
987int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
988 u8 slot, u8 pin)
989{
990 /*
991 * The EBH5600 board with the PCI to PCIe bridge mistakenly
992 * wires the first slot for both device id 2 and interrupt
993 * A. According to the PCI spec, device id 2 should be C. The
994 * following kludge attempts to fix this.
995 */
996 if (strstr(octeon_board_type_string(), "EBH5600") &&
997 dev->bus && dev->bus->parent) {
998 /*
999 * Iterate all the way up the device chain and find
1000 * the root bus.
1001 */
1002 while (dev->bus && dev->bus->parent)
1003 dev = to_pci_dev(dev->bus->bridge);
1004 /* If the root bus is number 0 and the PEX 8114 is the
1005 * root, assume we are behind the miswired bus. We
1006 * need to correct the swizzle level by two. Yuck.
1007 */
1008 if ((dev->bus->number == 0) &&
1009 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
1010 /*
1011 * The pin field is one based, not zero. We
1012 * need to swizzle it by minus two.
1013 */
1014 pin = ((pin - 3) & 3) + 1;
1015 }
1016 }
1017 /*
1018 * The -1 is because pin starts with one, not zero. It might
1019 * be that this equation needs to include the slot number, but
1020 * I don't have hardware to check that against.
1021 */
1022 return pin - 1 + OCTEON_IRQ_PCI_INT0;
1023}
1024
1025/**
1026 * Read a value from configuration space
1027 *
1028 * @param bus
1029 * @param devfn
1030 * @param reg
1031 * @param size
1032 * @param val
1033 * @return
1034 */
1035static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
1036 unsigned int devfn, int reg, int size,
1037 u32 *val)
1038{
1039 union octeon_cvmemctl cvmmemctl;
1040 union octeon_cvmemctl cvmmemctl_save;
1041 int bus_number = bus->number;
1042
1043 /*
1044 * We need to force the bus number to be zero on the root
1045 * bus. Linux numbers the 2nd root bus to start after all
1046 * buses on root 0.
1047 */
1048 if (bus->parent == NULL)
1049 bus_number = 0;
1050
1051 /*
1052 * PCIe only has a single device connected to Octeon. It is
1053 * always device ID 0. Don't bother doing reads for other
1054 * device IDs on the first segment.
1055 */
1056 if ((bus_number == 0) && (devfn >> 3 != 0))
1057 return PCIBIOS_FUNC_NOT_SUPPORTED;
1058
1059 /*
1060 * The following is a workaround for the CN57XX, CN56XX,
1061 * CN55XX, and CN54XX errata with PCIe config reads from non
1062 * existent devices. These chips will hang the PCIe link if a
1063 * config read is performed that causes a UR response.
1064 */
1065 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1066 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
1067 /*
1068 * For our EBH5600 board, port 0 has a bridge with two
1069 * PCI-X slots. We need a new special checks to make
1070 * sure we only probe valid stuff. The PCIe->PCI-X
1071 * bridge only respondes to device ID 0, function
1072 * 0-1
1073 */
1074 if ((bus_number == 0) && (devfn >= 2))
1075 return PCIBIOS_FUNC_NOT_SUPPORTED;
1076 /*
1077 * The PCI-X slots are device ID 2,3. Choose one of
1078 * the below "if" blocks based on what is plugged into
1079 * the board.
1080 */
1081#if 1
1082 /* Use this option if you aren't using either slot */
1083 if (bus_number == 1)
1084 return PCIBIOS_FUNC_NOT_SUPPORTED;
1085#elif 0
1086 /*
1087 * Use this option if you are using the first slot but
1088 * not the second.
1089 */
1090 if ((bus_number == 1) && (devfn >> 3 != 2))
1091 return PCIBIOS_FUNC_NOT_SUPPORTED;
1092#elif 0
1093 /*
1094 * Use this option if you are using the second slot
1095 * but not the first.
1096 */
1097 if ((bus_number == 1) && (devfn >> 3 != 3))
1098 return PCIBIOS_FUNC_NOT_SUPPORTED;
1099#elif 0
1100 /* Use this opion if you are using both slots */
1101 if ((bus_number == 1) &&
1102 !((devfn == (2 << 3)) || (devfn == (3 << 3))))
1103 return PCIBIOS_FUNC_NOT_SUPPORTED;
1104#endif
1105
1106 /*
1107 * Shorten the DID timeout so bus errors for PCIe
1108 * config reads from non existent devices happen
1109 * faster. This allows us to continue booting even if
1110 * the above "if" checks are wrong. Once one of these
1111 * errors happens, the PCIe port is dead.
1112 */
1113 cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
1114 cvmmemctl.u64 = cvmmemctl_save.u64;
1115 cvmmemctl.s.didtto = 2;
1116 __write_64bit_c0_register($11, 7, cvmmemctl.u64);
1117 }
1118
1119 switch (size) {
1120 case 4:
1121 *val = cvmx_pcie_config_read32(pcie_port, bus_number,
1122 devfn >> 3, devfn & 0x7, reg);
1123 break;
1124 case 2:
1125 *val = cvmx_pcie_config_read16(pcie_port, bus_number,
1126 devfn >> 3, devfn & 0x7, reg);
1127 break;
1128 case 1:
1129 *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
1130 devfn & 0x7, reg);
1131 break;
1132 default:
1133 return PCIBIOS_FUNC_NOT_SUPPORTED;
1134 }
1135
1136 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
1137 OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
1138 __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
1139 return PCIBIOS_SUCCESSFUL;
1140}
1141
1142static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
1143 int reg, int size, u32 *val)
1144{
1145 return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
1146}
1147
1148static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
1149 int reg, int size, u32 *val)
1150{
1151 return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
1152}
1153
1154
1155
1156/**
1157 * Write a value to PCI configuration space
1158 *
1159 * @param bus
1160 * @param devfn
1161 * @param reg
1162 * @param size
1163 * @param val
1164 * @return
1165 */
1166static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
1167 unsigned int devfn, int reg,
1168 int size, u32 val)
1169{
1170 int bus_number = bus->number;
1171 /*
1172 * We need to force the bus number to be zero on the root
1173 * bus. Linux numbers the 2nd root bus to start after all
1174 * busses on root 0.
1175 */
1176 if (bus->parent == NULL)
1177 bus_number = 0;
1178
1179 switch (size) {
1180 case 4:
1181 cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
1182 devfn & 0x7, reg, val);
1183 return PCIBIOS_SUCCESSFUL;
1184 case 2:
1185 cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
1186 devfn & 0x7, reg, val);
1187 return PCIBIOS_SUCCESSFUL;
1188 case 1:
1189 cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
1190 devfn & 0x7, reg, val);
1191 return PCIBIOS_SUCCESSFUL;
1192 }
1193#if PCI_CONFIG_SPACE_DELAY
1194 udelay(PCI_CONFIG_SPACE_DELAY);
1195#endif
1196 return PCIBIOS_FUNC_NOT_SUPPORTED;
1197}
1198
1199static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
1200 int reg, int size, u32 val)
1201{
1202 return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
1203}
1204
1205static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
1206 int reg, int size, u32 val)
1207{
1208 return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
1209}
1210
1211static struct pci_ops octeon_pcie0_ops = {
1212 octeon_pcie0_read_config,
1213 octeon_pcie0_write_config,
1214};
1215
1216static struct resource octeon_pcie0_mem_resource = {
1217 .name = "Octeon PCIe0 MEM",
1218 .flags = IORESOURCE_MEM,
1219};
1220
1221static struct resource octeon_pcie0_io_resource = {
1222 .name = "Octeon PCIe0 IO",
1223 .flags = IORESOURCE_IO,
1224};
1225
1226static struct pci_controller octeon_pcie0_controller = {
1227 .pci_ops = &octeon_pcie0_ops,
1228 .mem_resource = &octeon_pcie0_mem_resource,
1229 .io_resource = &octeon_pcie0_io_resource,
1230};
1231
1232static struct pci_ops octeon_pcie1_ops = {
1233 octeon_pcie1_read_config,
1234 octeon_pcie1_write_config,
1235};
1236
1237static struct resource octeon_pcie1_mem_resource = {
1238 .name = "Octeon PCIe1 MEM",
1239 .flags = IORESOURCE_MEM,
1240};
1241
1242static struct resource octeon_pcie1_io_resource = {
1243 .name = "Octeon PCIe1 IO",
1244 .flags = IORESOURCE_IO,
1245};
1246
1247static struct pci_controller octeon_pcie1_controller = {
1248 .pci_ops = &octeon_pcie1_ops,
1249 .mem_resource = &octeon_pcie1_mem_resource,
1250 .io_resource = &octeon_pcie1_io_resource,
1251};
1252
1253
1254/**
1255 * Initialize the Octeon PCIe controllers
1256 *
1257 * @return
1258 */
1259static int __init octeon_pcie_setup(void)
1260{
1261 union cvmx_npei_ctl_status npei_ctl_status;
1262 int result;
1263
1264 /* These chips don't have PCIe */
1265 if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
1266 return 0;
1267
1268 /* Point pcibios_map_irq() to the PCIe version of it */
1269 octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
1270
1271 /* Use the PCIe based DMA mappings */
1272 octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
1273
1274 /*
1275 * PCIe I/O range. It is based on port 0 but includes up until
1276 * port 1's end.
1277 */
1278 set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
1279 ioport_resource.start = 0;
1280 ioport_resource.end =
1281 cvmx_pcie_get_io_base_address(1) -
1282 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
1283
1284 npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1285 if (npei_ctl_status.s.host_mode) {
1286 pr_notice("PCIe: Initializing port 0\n");
1287 result = cvmx_pcie_rc_initialize(0);
1288 if (result == 0) {
1289 /* Memory offsets are physical addresses */
1290 octeon_pcie0_controller.mem_offset =
1291 cvmx_pcie_get_mem_base_address(0);
1292 /* IO offsets are Mips virtual addresses */
1293 octeon_pcie0_controller.io_map_base =
1294 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
1295 (0));
1296 octeon_pcie0_controller.io_offset = 0;
1297 /*
1298 * To keep things similar to PCI, we start
1299 * device addresses at the same place as PCI
1300 * uisng big bar support. This normally
1301 * translates to 4GB-256MB, which is the same
1302 * as most x86 PCs.
1303 */
1304 octeon_pcie0_controller.mem_resource->start =
1305 cvmx_pcie_get_mem_base_address(0) +
1306 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1307 octeon_pcie0_controller.mem_resource->end =
1308 cvmx_pcie_get_mem_base_address(0) +
1309 cvmx_pcie_get_mem_size(0) - 1;
1310 /*
1311 * Ports must be above 16KB for the ISA bus
1312 * filtering in the PCI-X to PCI bridge.
1313 */
1314 octeon_pcie0_controller.io_resource->start = 4 << 10;
1315 octeon_pcie0_controller.io_resource->end =
1316 cvmx_pcie_get_io_size(0) - 1;
1317 register_pci_controller(&octeon_pcie0_controller);
1318 }
1319 } else {
1320 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
1321 }
1322
1323 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
1324 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1325 union cvmx_npei_dbg_data npei_dbg_data;
1326 npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1327 if (npei_dbg_data.cn52xx.qlm0_link_width)
1328 return 0;
1329 }
1330
1331 pr_notice("PCIe: Initializing port 1\n");
1332 result = cvmx_pcie_rc_initialize(1);
1333 if (result == 0) {
1334 /* Memory offsets are physical addresses */
1335 octeon_pcie1_controller.mem_offset =
1336 cvmx_pcie_get_mem_base_address(1);
1337 /* IO offsets are Mips virtual addresses */
1338 octeon_pcie1_controller.io_map_base =
1339 CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
1340 octeon_pcie1_controller.io_offset =
1341 cvmx_pcie_get_io_base_address(1) -
1342 cvmx_pcie_get_io_base_address(0);
1343 /*
1344 * To keep things similar to PCI, we start device
1345 * addresses at the same place as PCI uisng big bar
1346 * support. This normally translates to 4GB-256MB,
1347 * which is the same as most x86 PCs.
1348 */
1349 octeon_pcie1_controller.mem_resource->start =
1350 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
1351 (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
1352 octeon_pcie1_controller.mem_resource->end =
1353 cvmx_pcie_get_mem_base_address(1) +
1354 cvmx_pcie_get_mem_size(1) - 1;
1355 /*
1356 * Ports must be above 16KB for the ISA bus filtering
1357 * in the PCI-X to PCI bridge.
1358 */
1359 octeon_pcie1_controller.io_resource->start =
1360 cvmx_pcie_get_io_base_address(1) -
1361 cvmx_pcie_get_io_base_address(0);
1362 octeon_pcie1_controller.io_resource->end =
1363 octeon_pcie1_controller.io_resource->start +
1364 cvmx_pcie_get_io_size(1) - 1;
1365 register_pci_controller(&octeon_pcie1_controller);
1366 }
1367 return 0;
1368}
1369
1370arch_initcall(octeon_pcie_setup);
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0047f861337..8ab1d12ba7f4 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,10 @@
147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 147#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
148 cpu_has_mips64r1 | cpu_has_mips64r2) 148 cpu_has_mips64r1 | cpu_has_mips64r2)
149 149
150#ifndef cpu_has_mips_r2_exec_hazard
151#define cpu_has_mips_r2_exec_hazard cpu_has_mips_r2
152#endif
153
150/* 154/*
151 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 155 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
152 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels 156 * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
@@ -230,4 +234,8 @@
230#define cpu_scache_line_size() cpu_data[0].scache.linesz 234#define cpu_scache_line_size() cpu_data[0].scache.linesz
231#endif 235#endif
232 236
237#ifndef cpu_hwrena_impl_bits
238#define cpu_hwrena_impl_bits 0
239#endif
240
233#endif /* __ASM_CPU_FEATURES_H */ 241#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
index a07e51b2be13..d2d8949be6b7 100644
--- a/arch/mips/include/asm/delay.h
+++ b/arch/mips/include/asm/delay.h
@@ -15,7 +15,7 @@ extern void __delay(unsigned int loops);
15extern void __ndelay(unsigned int ns); 15extern void __ndelay(unsigned int ns);
16extern void __udelay(unsigned int us); 16extern void __udelay(unsigned int us);
17 17
18#define ndelay(ns) __udelay(ns) 18#define ndelay(ns) __ndelay(ns)
19#define udelay(us) __udelay(us) 19#define udelay(us) __udelay(us)
20 20
21/* make sure "usecs *= ..." in udelay do not overflow. */ 21/* make sure "usecs *= ..." in udelay do not overflow. */
diff --git a/arch/mips/include/asm/hugetlb.h b/arch/mips/include/asm/hugetlb.h
new file mode 100644
index 000000000000..f5e856015329
--- /dev/null
+++ b/arch/mips/include/asm/hugetlb.h
@@ -0,0 +1,114 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
7 */
8
9#ifndef __ASM_HUGETLB_H
10#define __ASM_HUGETLB_H
11
12#include <asm/page.h>
13
14
15static inline int is_hugepage_only_range(struct mm_struct *mm,
16 unsigned long addr,
17 unsigned long len)
18{
19 return 0;
20}
21
22static inline int prepare_hugepage_range(struct file *file,
23 unsigned long addr,
24 unsigned long len)
25{
26 unsigned long task_size = STACK_TOP;
27 struct hstate *h = hstate_file(file);
28
29 if (len & ~huge_page_mask(h))
30 return -EINVAL;
31 if (addr & ~huge_page_mask(h))
32 return -EINVAL;
33 if (len > task_size)
34 return -ENOMEM;
35 if (task_size - len < addr)
36 return -EINVAL;
37 return 0;
38}
39
40static inline void hugetlb_prefault_arch_hook(struct mm_struct *mm)
41{
42}
43
44static inline void hugetlb_free_pgd_range(struct mmu_gather *tlb,
45 unsigned long addr,
46 unsigned long end,
47 unsigned long floor,
48 unsigned long ceiling)
49{
50 free_pgd_range(tlb, addr, end, floor, ceiling);
51}
52
53static inline void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
54 pte_t *ptep, pte_t pte)
55{
56 set_pte_at(mm, addr, ptep, pte);
57}
58
59static inline pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
60 unsigned long addr, pte_t *ptep)
61{
62 pte_t clear;
63 pte_t pte = *ptep;
64
65 pte_val(clear) = (unsigned long)invalid_pte_table;
66 set_pte_at(mm, addr, ptep, clear);
67 return pte;
68}
69
70static inline void huge_ptep_clear_flush(struct vm_area_struct *vma,
71 unsigned long addr, pte_t *ptep)
72{
73}
74
75static inline int huge_pte_none(pte_t pte)
76{
77 unsigned long val = pte_val(pte) & ~_PAGE_GLOBAL;
78 return !val || (val == (unsigned long)invalid_pte_table);
79}
80
81static inline pte_t huge_pte_wrprotect(pte_t pte)
82{
83 return pte_wrprotect(pte);
84}
85
86static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
87 unsigned long addr, pte_t *ptep)
88{
89 ptep_set_wrprotect(mm, addr, ptep);
90}
91
92static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
93 unsigned long addr,
94 pte_t *ptep, pte_t pte,
95 int dirty)
96{
97 return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
98}
99
100static inline pte_t huge_ptep_get(pte_t *ptep)
101{
102 return *ptep;
103}
104
105static inline int arch_prepare_hugepage(struct page *page)
106{
107 return 0;
108}
109
110static inline void arch_release_hugepage(struct page *page)
111{
112}
113
114#endif /* __ASM_HUGETLB_H */
diff --git a/arch/mips/include/asm/i8253.h b/arch/mips/include/asm/i8253.h
index 5dabc870b322..032ca73f181b 100644
--- a/arch/mips/include/asm/i8253.h
+++ b/arch/mips/include/asm/i8253.h
@@ -12,8 +12,6 @@
12#define PIT_CH0 0x40 12#define PIT_CH0 0x40
13#define PIT_CH2 0x42 13#define PIT_CH2 0x42
14 14
15#define PIT_TICK_RATE 1193182UL
16
17extern spinlock_t i8253_lock; 15extern spinlock_t i8253_lock;
18 16
19extern void setup_pit_timer(void); 17extern void setup_pit_timer(void);
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
index 916163401b2c..c515a1a4c47c 100644
--- a/arch/mips/include/asm/ioctl.h
+++ b/arch/mips/include/asm/ioctl.h
@@ -3,40 +3,16 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle 6 * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2009 Wind River Systems
8 * Written by Ralf Baechle <ralf@linux-mips.org>
7 */ 9 */
8#ifndef _ASM_IOCTL_H 10#ifndef __ASM_IOCTL_H
9#define _ASM_IOCTL_H 11#define __ASM_IOCTL_H
10 12
11/*
12 * The original linux ioctl numbering scheme was just a general
13 * "anything goes" setup, where more or less random numbers were
14 * assigned. Sorry, I was clueless when I started out on this.
15 *
16 * On the alpha, we'll try to clean it up a bit, using a more sane
17 * ioctl numbering, and also trying to be compatible with OSF/1 in
18 * the process. I'd like to clean it up for the i386 as well, but
19 * it's so painful recognizing both the new and the old numbers..
20 *
21 * The same applies for for the MIPS ABI; in fact even the macros
22 * from Linux/Alpha fit almost perfectly.
23 */
24
25#define _IOC_NRBITS 8
26#define _IOC_TYPEBITS 8
27#define _IOC_SIZEBITS 13 13#define _IOC_SIZEBITS 13
28#define _IOC_DIRBITS 3 14#define _IOC_DIRBITS 3
29 15
30#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
31#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
32#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
33#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
34
35#define _IOC_NRSHIFT 0
36#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
37#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
38#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
39
40/* 16/*
41 * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit. 17 * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
42 * And this turns out useful to catch old ioctl numbers in header 18 * And this turns out useful to catch old ioctl numbers in header
@@ -46,53 +22,6 @@
46#define _IOC_READ 2U 22#define _IOC_READ 2U
47#define _IOC_WRITE 4U 23#define _IOC_WRITE 4U
48 24
49/* 25#include <asm-generic/ioctl.h>
50 * The following are included for compatibility
51 */
52#define _IOC_VOID 0x20000000
53#define _IOC_OUT 0x40000000
54#define _IOC_IN 0x80000000
55#define _IOC_INOUT (IOC_IN|IOC_OUT)
56
57#define _IOC(dir, type, nr, size) \
58 (((dir) << _IOC_DIRSHIFT) | \
59 ((type) << _IOC_TYPESHIFT) | \
60 ((nr) << _IOC_NRSHIFT) | \
61 ((size) << _IOC_SIZESHIFT))
62
63#ifdef __KERNEL__
64/* provoke compile error for invalid uses of size argument */
65extern unsigned int __invalid_size_argument_for_IOC;
66#define _IOC_TYPECHECK(t) \
67 ((sizeof(t) == sizeof(t[1]) && \
68 sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
69 sizeof(t) : __invalid_size_argument_for_IOC)
70#else
71#define _IOC_TYPECHECK(t) (sizeof(t))
72#endif
73
74/* used to create numbers */
75#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
76#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
77#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
78#define _IOWR(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
79#define _IOR_BAD(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof(size))
80#define _IOW_BAD(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
81#define _IOWR_BAD(type, nr, size) _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
82
83
84/* used to decode them.. */
85#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
86#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
87#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
88#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
89
90/* ...and for the drivers/sound files... */
91
92#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
93#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
94#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
95#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
96#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
97 26
98#endif /* _ASM_IOCTL_H */ 27#endif /* __ASM_IOCTL_H */
diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h
index 806aae3c5338..58e91ed0388f 100644
--- a/arch/mips/include/asm/kmap_types.h
+++ b/arch/mips/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
1#ifndef _ASM_KMAP_TYPES_H 1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H 2#define _ASM_KMAP_TYPES_H
3 3
4
5#ifdef CONFIG_DEBUG_HIGHMEM 4#ifdef CONFIG_DEBUG_HIGHMEM
6# define D(n) __KM_FENCE_##n , 5#define __WITH_KM_FENCE
7#else
8# define D(n)
9#endif 6#endif
10 7
11enum km_type { 8#include <asm-generic/kmap_types.h>
12D(0) KM_BOUNCE_READ,
13D(1) KM_SKB_SUNRPC_DATA,
14D(2) KM_SKB_DATA_SOFTIRQ,
15D(3) KM_USER0,
16D(4) KM_USER1,
17D(5) KM_BIO_SRC_IRQ,
18D(6) KM_BIO_DST_IRQ,
19D(7) KM_PTE0,
20D(8) KM_PTE1,
21D(9) KM_IRQ0,
22D(10) KM_IRQ1,
23D(11) KM_SOFTIRQ0,
24D(12) KM_SOFTIRQ1,
25D(13) KM_TYPE_NR
26};
27 9
28#undef D 10#undef __WITH_KM_FENCE
29 11
30#endif 12#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
deleted file mode 100644
index d8c96fda5549..000000000000
--- a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * FILE NAME au1000_gpio.h
3 *
4 * BRIEF MODULE DESCRIPTION
5 * API to Alchemy Au1xx0 GPIO device.
6 *
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * Steve Longerbeam
9 *
10 * Copyright 2001, 2008 MontaVista Software Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __AU1000_GPIO_H
34#define __AU1000_GPIO_H
35
36#include <linux/ioctl.h>
37
38#define AU1000GPIO_IOC_MAGIC 'A'
39
40#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
41#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
42#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
43#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
44#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
45#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
46
47#ifdef __KERNEL__
48extern u32 get_au1000_avail_gpio_mask(void);
49extern int au1000gpio_tristate(u32 data);
50extern int au1000gpio_in(u32 *data);
51extern int au1000gpio_set(u32 data);
52extern int au1000gpio_clear(u32 data);
53extern int au1000gpio_out(u32 data);
54#endif
55
56#endif
diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
new file mode 100644
index 000000000000..127d4ed9f073
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -0,0 +1,604 @@
1/*
2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
3 *
4 * Copyright (c) 2009 Manuel Lauss.
5 *
6 * Licensed under the terms outlined in the file COPYING.
7 */
8
9#ifndef _ALCHEMY_GPIO_AU1000_H_
10#define _ALCHEMY_GPIO_AU1000_H_
11
12#include <asm/mach-au1x00/au1000.h>
13
14/* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
16 */
17#define ALCHEMY_GPIO1_BASE 0
18#define ALCHEMY_GPIO2_BASE 200
19
20#define ALCHEMY_GPIO1_NUM 32
21#define ALCHEMY_GPIO2_NUM 16
22#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
24
25#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off))
26
27
28static inline int au1000_gpio1_to_irq(int gpio)
29{
30 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
31}
32
33static inline int au1000_gpio2_to_irq(int gpio)
34{
35 return -ENXIO;
36}
37
38#ifdef CONFIG_SOC_AU1000
39static inline int au1000_irq_to_gpio(int irq)
40{
41 if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31))
42 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
43
44 return -ENXIO;
45}
46#endif
47
48static inline int au1500_gpio1_to_irq(int gpio)
49{
50 gpio -= ALCHEMY_GPIO1_BASE;
51
52 switch (gpio) {
53 case 0 ... 15:
54 case 20:
55 case 23 ... 28: return MAKE_IRQ(1, gpio);
56 }
57
58 return -ENXIO;
59}
60
61static inline int au1500_gpio2_to_irq(int gpio)
62{
63 gpio -= ALCHEMY_GPIO2_BASE;
64
65 switch (gpio) {
66 case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0);
67 case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4);
68 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
69 }
70
71 return -ENXIO;
72}
73
74#ifdef CONFIG_SOC_AU1500
75static inline int au1500_irq_to_gpio(int irq)
76{
77 switch (irq) {
78 case AU1000_GPIO_0 ... AU1000_GPIO_15:
79 case AU1500_GPIO_20:
80 case AU1500_GPIO_23 ... AU1500_GPIO_28:
81 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
82 case AU1500_GPIO_200 ... AU1500_GPIO_203:
83 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0;
84 case AU1500_GPIO_204 ... AU1500_GPIO_205:
85 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4;
86 case AU1500_GPIO_206 ... AU1500_GPIO_207:
87 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
88 case AU1500_GPIO_208_215:
89 return ALCHEMY_GPIO2_BASE + 8;
90 }
91
92 return -ENXIO;
93}
94#endif
95
96static inline int au1100_gpio1_to_irq(int gpio)
97{
98 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
99}
100
101static inline int au1100_gpio2_to_irq(int gpio)
102{
103 gpio -= ALCHEMY_GPIO2_BASE;
104
105 if ((gpio >= 8) && (gpio <= 15))
106 return MAKE_IRQ(0, 29); /* shared GPIO208_215 */
107}
108
109#ifdef CONFIG_SOC_AU1100
110static inline int au1100_irq_to_gpio(int irq)
111{
112 switch (irq) {
113 case AU1000_GPIO_0 ... AU1000_GPIO_31:
114 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
115 case AU1100_GPIO_208_215:
116 return ALCHEMY_GPIO2_BASE + 8;
117 }
118
119 return -ENXIO;
120}
121#endif
122
123static inline int au1550_gpio1_to_irq(int gpio)
124{
125 gpio -= ALCHEMY_GPIO1_BASE;
126
127 switch (gpio) {
128 case 0 ... 15:
129 case 20 ... 28: return MAKE_IRQ(1, gpio);
130 case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
131 }
132
133 return -ENXIO;
134}
135
136static inline int au1550_gpio2_to_irq(int gpio)
137{
138 gpio -= ALCHEMY_GPIO2_BASE;
139
140 switch (gpio) {
141 case 0: return MAKE_IRQ(1, 16);
142 case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
143 case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6);
144 case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
145 }
146
147 return -ENXIO;
148}
149
150#ifdef CONFIG_SOC_AU1550
151static inline int au1550_irq_to_gpio(int irq)
152{
153 switch (irq) {
154 case AU1000_GPIO_0 ... AU1000_GPIO_15:
155 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
156 case AU1550_GPIO_200:
157 case AU1500_GPIO_201_205:
158 return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0;
159 case AU1500_GPIO_16 ... AU1500_GPIO_28:
160 return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16;
161 case AU1500_GPIO_206 ... AU1500_GPIO_208_218:
162 return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6;
163 }
164
165 return -ENXIO;
166}
167#endif
168
169static inline int au1200_gpio1_to_irq(int gpio)
170{
171 return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE);
172}
173
174static inline int au1200_gpio2_to_irq(int gpio)
175{
176 gpio -= ALCHEMY_GPIO2_BASE;
177
178 switch (gpio) {
179 case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0);
180 case 3: return MAKE_IRQ(0, 22);
181 case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4);
182 case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
183 }
184
185 return -ENXIO;
186}
187
188#ifdef CONFIG_SOC_AU1200
189static inline int au1200_irq_to_gpio(int irq)
190{
191 switch (irq) {
192 case AU1000_GPIO_0 ... AU1000_GPIO_31:
193 return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0;
194 case AU1200_GPIO_200 ... AU1200_GPIO_202:
195 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0;
196 case AU1200_GPIO_203:
197 return ALCHEMY_GPIO2_BASE + 3;
198 case AU1200_GPIO_204 ... AU1200_GPIO_208_215:
199 return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4;
200 }
201
202 return -ENXIO;
203}
204#endif
205
206/*
207 * GPIO1 block macros for common linux gpio functions.
208 */
209static inline void alchemy_gpio1_set_value(int gpio, int v)
210{
211 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
212 unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR;
213 au_writel(mask, r);
214 au_sync();
215}
216
217static inline int alchemy_gpio1_get_value(int gpio)
218{
219 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
220 return au_readl(SYS_PINSTATERD) & mask;
221}
222
223static inline int alchemy_gpio1_direction_input(int gpio)
224{
225 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE);
226 au_writel(mask, SYS_TRIOUTCLR);
227 au_sync();
228 return 0;
229}
230
231static inline int alchemy_gpio1_direction_output(int gpio, int v)
232{
233 /* hardware switches to "output" mode when one of the two
234 * "set_value" registers is accessed.
235 */
236 alchemy_gpio1_set_value(gpio, v);
237 return 0;
238}
239
240static inline int alchemy_gpio1_is_valid(int gpio)
241{
242 return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX));
243}
244
245static inline int alchemy_gpio1_to_irq(int gpio)
246{
247#if defined(CONFIG_SOC_AU1000)
248 return au1000_gpio1_to_irq(gpio);
249#elif defined(CONFIG_SOC_AU1100)
250 return au1100_gpio1_to_irq(gpio);
251#elif defined(CONFIG_SOC_AU1500)
252 return au1500_gpio1_to_irq(gpio);
253#elif defined(CONFIG_SOC_AU1550)
254 return au1550_gpio1_to_irq(gpio);
255#elif defined(CONFIG_SOC_AU1200)
256 return au1200_gpio1_to_irq(gpio);
257#else
258 return -ENXIO;
259#endif
260}
261
262/*
263 * GPIO2 block macros for common linux GPIO functions. The 'gpio'
264 * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX.
265 */
266static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out)
267{
268 unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE);
269 unsigned long d = au_readl(GPIO2_DIR);
270 if (to_out)
271 d |= mask;
272 else
273 d &= ~mask;
274 au_writel(d, GPIO2_DIR);
275 au_sync();
276}
277
278static inline void alchemy_gpio2_set_value(int gpio, int v)
279{
280 unsigned long mask;
281 mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE);
282 au_writel(mask, GPIO2_OUTPUT);
283 au_sync();
284}
285
286static inline int alchemy_gpio2_get_value(int gpio)
287{
288 return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE));
289}
290
291static inline int alchemy_gpio2_direction_input(int gpio)
292{
293 unsigned long flags;
294 local_irq_save(flags);
295 __alchemy_gpio2_mod_dir(gpio, 0);
296 local_irq_restore(flags);
297 return 0;
298}
299
300static inline int alchemy_gpio2_direction_output(int gpio, int v)
301{
302 unsigned long flags;
303 alchemy_gpio2_set_value(gpio, v);
304 local_irq_save(flags);
305 __alchemy_gpio2_mod_dir(gpio, 1);
306 local_irq_restore(flags);
307 return 0;
308}
309
310static inline int alchemy_gpio2_is_valid(int gpio)
311{
312 return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX));
313}
314
315static inline int alchemy_gpio2_to_irq(int gpio)
316{
317#if defined(CONFIG_SOC_AU1000)
318 return au1000_gpio2_to_irq(gpio);
319#elif defined(CONFIG_SOC_AU1100)
320 return au1100_gpio2_to_irq(gpio);
321#elif defined(CONFIG_SOC_AU1500)
322 return au1500_gpio2_to_irq(gpio);
323#elif defined(CONFIG_SOC_AU1550)
324 return au1550_gpio2_to_irq(gpio);
325#elif defined(CONFIG_SOC_AU1200)
326 return au1200_gpio2_to_irq(gpio);
327#else
328 return -ENXIO;
329#endif
330}
331
332/**********************************************************************/
333
334/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before
335 * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this
336 * register enables use of GPIOs as wake source.
337 */
338static inline void alchemy_gpio1_input_enable(void)
339{
340 au_writel(0, SYS_PININPUTEN); /* the write op is key */
341 au_sync();
342}
343
344/* GPIO2 shared interrupts and control */
345
346static inline void __alchemy_gpio2_mod_int(int gpio2, int en)
347{
348 unsigned long r = au_readl(GPIO2_INTENABLE);
349 if (en)
350 r |= 1 << gpio2;
351 else
352 r &= ~(1 << gpio2);
353 au_writel(r, GPIO2_INTENABLE);
354 au_sync();
355}
356
357/**
358 * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution.
359 * @gpio2: The GPIO2 pin to activate (200...215).
360 *
361 * GPIO208-215 have one shared interrupt line to the INTC. They are
362 * and'ed with a per-pin enable bit and finally or'ed together to form
363 * a single irq request (useful for active-high sources).
364 * With this function, a pins' individual contribution to the int request
365 * can be enabled. As with all other GPIO-based interrupts, the INTC
366 * must be programmed to accept the GPIO208_215 interrupt as well.
367 *
368 * NOTE: Calling this macro is only necessary for GPIO208-215; all other
369 * GPIO2-based interrupts have their own request to the INTC. Please
370 * consult your Alchemy databook for more information!
371 *
372 * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request
373 * line to the INTC, GPIO201_205. This function can be used for those
374 * as well.
375 *
376 * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace
377 * (200-215 by default). No sanity checks are made,
378 */
379static inline void alchemy_gpio2_enable_int(int gpio2)
380{
381 unsigned long flags;
382
383 gpio2 -= ALCHEMY_GPIO2_BASE;
384
385#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
386 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
387 gpio2 -= 8;
388#endif
389 local_irq_save(flags);
390 __alchemy_gpio2_mod_int(gpio2, 1);
391 local_irq_restore(flags);
392}
393
394/**
395 * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution.
396 * @gpio2: The GPIO2 pin to activate (200...215).
397 *
398 * see function alchemy_gpio2_enable_int() for more information.
399 */
400static inline void alchemy_gpio2_disable_int(int gpio2)
401{
402 unsigned long flags;
403
404 gpio2 -= ALCHEMY_GPIO2_BASE;
405
406#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
407 /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */
408 gpio2 -= 8;
409#endif
410 local_irq_save(flags);
411 __alchemy_gpio2_mod_int(gpio2, 0);
412 local_irq_restore(flags);
413}
414
415/**
416 * alchemy_gpio2_enable - Activate GPIO2 block.
417 *
418 * The GPIO2 block must be enabled excplicitly to work. On systems
419 * where this isn't done by the bootloader, this macro can be used.
420 */
421static inline void alchemy_gpio2_enable(void)
422{
423 au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */
424 au_sync();
425 au_writel(1, GPIO2_ENABLE); /* clock enabled */
426 au_sync();
427}
428
429/**
430 * alchemy_gpio2_disable - disable GPIO2 block.
431 *
432 * Disable and put GPIO2 block in low-power mode.
433 */
434static inline void alchemy_gpio2_disable(void)
435{
436 au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */
437 au_sync();
438}
439
440/**********************************************************************/
441
442/* wrappers for on-chip gpios; can be used before gpio chips have been
443 * registered with gpiolib.
444 */
445static inline int alchemy_gpio_direction_input(int gpio)
446{
447 return (gpio >= ALCHEMY_GPIO2_BASE) ?
448 alchemy_gpio2_direction_input(gpio) :
449 alchemy_gpio1_direction_input(gpio);
450}
451
452static inline int alchemy_gpio_direction_output(int gpio, int v)
453{
454 return (gpio >= ALCHEMY_GPIO2_BASE) ?
455 alchemy_gpio2_direction_output(gpio, v) :
456 alchemy_gpio1_direction_output(gpio, v);
457}
458
459static inline int alchemy_gpio_get_value(int gpio)
460{
461 return (gpio >= ALCHEMY_GPIO2_BASE) ?
462 alchemy_gpio2_get_value(gpio) :
463 alchemy_gpio1_get_value(gpio);
464}
465
466static inline void alchemy_gpio_set_value(int gpio, int v)
467{
468 if (gpio >= ALCHEMY_GPIO2_BASE)
469 alchemy_gpio2_set_value(gpio, v);
470 else
471 alchemy_gpio1_set_value(gpio, v);
472}
473
474static inline int alchemy_gpio_is_valid(int gpio)
475{
476 return (gpio >= ALCHEMY_GPIO2_BASE) ?
477 alchemy_gpio2_is_valid(gpio) :
478 alchemy_gpio1_is_valid(gpio);
479}
480
481static inline int alchemy_gpio_cansleep(int gpio)
482{
483 return 0; /* Alchemy never gets tired */
484}
485
486static inline int alchemy_gpio_to_irq(int gpio)
487{
488 return (gpio >= ALCHEMY_GPIO2_BASE) ?
489 alchemy_gpio2_to_irq(gpio) :
490 alchemy_gpio1_to_irq(gpio);
491}
492
493static inline int alchemy_irq_to_gpio(int irq)
494{
495#if defined(CONFIG_SOC_AU1000)
496 return au1000_irq_to_gpio(irq);
497#elif defined(CONFIG_SOC_AU1100)
498 return au1100_irq_to_gpio(irq);
499#elif defined(CONFIG_SOC_AU1500)
500 return au1500_irq_to_gpio(irq);
501#elif defined(CONFIG_SOC_AU1550)
502 return au1550_irq_to_gpio(irq);
503#elif defined(CONFIG_SOC_AU1200)
504 return au1200_irq_to_gpio(irq);
505#else
506 return -ENXIO;
507#endif
508}
509
510/**********************************************************************/
511
512/* Linux gpio framework integration.
513 *
514 * 4 use cases of Au1000-Au1200 GPIOS:
515 *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y:
516 * Board must register gpiochips.
517 *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n:
518 * 2 (1 for Au1000) gpio_chips are registered.
519 *
520 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
521 * the boards' gpio.h must provide the linux gpio wrapper functions,
522 *
523 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
524 * inlinable gpio functions are provided which enable access to the
525 * Au1000 gpios only by using the numbers straight out of the data-
526 * sheets.
527
528 * Cases 1 and 3 are intended for boards which want to provide their own
529 * GPIO namespace and -operations (i.e. for example you have 8 GPIOs
530 * which are in part provided by spare Au1000 GPIO pins and in part by
531 * an external FPGA but you still want them to be accssible in linux
532 * as gpio0-7. The board can of course use the alchemy_gpioX_* functions
533 * as required).
534 */
535
536#ifndef CONFIG_GPIOLIB
537
538
539#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */
540
541static inline int gpio_direction_input(int gpio)
542{
543 return alchemy_gpio_direction_input(gpio);
544}
545
546static inline int gpio_direction_output(int gpio, int v)
547{
548 return alchemy_gpio_direction_output(gpio, v);
549}
550
551static inline int gpio_get_value(int gpio)
552{
553 return alchemy_gpio_get_value(gpio);
554}
555
556static inline void gpio_set_value(int gpio, int v)
557{
558 alchemy_gpio_set_value(gpio, v);
559}
560
561static inline int gpio_is_valid(int gpio)
562{
563 return alchemy_gpio_is_valid(gpio);
564}
565
566static inline int gpio_cansleep(int gpio)
567{
568 return alchemy_gpio_cansleep(gpio);
569}
570
571static inline int gpio_to_irq(int gpio)
572{
573 return alchemy_gpio_to_irq(gpio);
574}
575
576static inline int irq_to_gpio(int irq)
577{
578 return alchemy_irq_to_gpio(irq);
579}
580
581#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
582
583
584#else /* CONFIG GPIOLIB */
585
586
587 /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */
588#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */
589
590/* get everything through gpiolib */
591#define gpio_to_irq __gpio_to_irq
592#define gpio_get_value __gpio_get_value
593#define gpio_set_value __gpio_set_value
594#define gpio_cansleep __gpio_cansleep
595#define irq_to_gpio alchemy_irq_to_gpio
596
597#include <asm-generic/gpio.h>
598
599#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */
600
601
602#endif /* !CONFIG_GPIOLIB */
603
604#endif /* _ALCHEMY_GPIO_AU1000_H_ */
diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h
index 34d9b7279024..f9b7d41c659a 100644
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,33 +1,10 @@
1#ifndef _AU1XXX_GPIO_H_ 1#ifndef _ALCHEMY_GPIO_H_
2#define _AU1XXX_GPIO_H_ 2#define _ALCHEMY_GPIO_H_
3 3
4#include <linux/types.h> 4#if defined(CONFIG_ALCHEMY_GPIO_AU1000)
5 5
6#define AU1XXX_GPIO_BASE 200 6#include <asm/mach-au1x00/gpio-au1000.h>
7 7
8/* GPIO bank 1 offsets */ 8#endif
9#define AU1000_GPIO1_TRI_OUT 0x0100
10#define AU1000_GPIO1_OUT 0x0108
11#define AU1000_GPIO1_ST 0x0110
12#define AU1000_GPIO1_CLR 0x010C
13 9
14/* GPIO bank 2 offsets */ 10#endif /* _ALCHEMY_GPIO_H_ */
15#define AU1000_GPIO2_DIR 0x00
16#define AU1000_GPIO2_RSVD 0x04
17#define AU1000_GPIO2_OUT 0x08
18#define AU1000_GPIO2_ST 0x0C
19#define AU1000_GPIO2_INT 0x10
20#define AU1000_GPIO2_EN 0x14
21
22#define GPIO2_OUT_EN_MASK 0x00010000
23
24#define gpio_to_irq(gpio) NULL
25
26#define gpio_get_value __gpio_get_value
27#define gpio_set_value __gpio_set_value
28
29#define gpio_cansleep __gpio_cansleep
30
31#include <asm-generic/gpio.h>
32
33#endif /* _AU1XXX_GPIO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm47xx/gpio.h b/arch/mips/include/asm/mach-bcm47xx/gpio.h
index 1784fde2e28f..98504142124e 100644
--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
@@ -37,6 +37,9 @@ static inline int gpio_direction_input(unsigned gpio)
37 37
38static inline int gpio_direction_output(unsigned gpio, int value) 38static inline int gpio_direction_output(unsigned gpio, int value)
39{ 39{
40 /* first set the gpio out value */
41 ssb_gpio_out(&ssb_bcm47xx, 1 << gpio, value ? 1 << gpio : 0);
42 /* then set the gpio mode */
40 ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio); 43 ssb_gpio_outen(&ssb_bcm47xx, 1 << gpio, 1 << gpio);
41 return 0; 44 return 0;
42} 45}
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 04ce6e6569da..3d830756b13a 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -47,11 +47,13 @@
47#define cpu_has_mips32r2 0 47#define cpu_has_mips32r2 0
48#define cpu_has_mips64r1 0 48#define cpu_has_mips64r1 0
49#define cpu_has_mips64r2 1 49#define cpu_has_mips64r2 1
50#define cpu_has_mips_r2_exec_hazard 0
50#define cpu_has_dsp 0 51#define cpu_has_dsp 0
51#define cpu_has_mipsmt 0 52#define cpu_has_mipsmt 0
52#define cpu_has_userlocal 0 53#define cpu_has_userlocal 0
53#define cpu_has_vint 0 54#define cpu_has_vint 0
54#define cpu_has_veic 0 55#define cpu_has_veic 0
56#define cpu_hwrena_impl_bits 0xc0000000
55#define ARCH_HAS_READ_CURRENT_TIMER 1 57#define ARCH_HAS_READ_CURRENT_TIMER 1
56#define ARCH_HAS_IRQ_PER_CPU 1 58#define ARCH_HAS_IRQ_PER_CPU 1
57#define ARCH_HAS_SPINLOCK_PREFETCH 1 59#define ARCH_HAS_SPINLOCK_PREFETCH 1
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
index f30fce92aabb..17d579471ec4 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -30,12 +30,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); 30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
31} 31}
32 32
33static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 33static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
34 dma_addr_t dma_addr)
34{ 35{
35 return dma_addr; 36 return dma_addr;
36} 37}
37 38
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 39static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
40 size_t size, enum dma_data_direction direction)
39{ 41{
40 octeon_unmap_dma_mem(dev, dma_addr); 42 octeon_unmap_dma_mem(dev, dma_addr);
41} 43}
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 36c611b6c597..8da98073e952 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -23,12 +23,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
23 return page_to_phys(page); 23 return page_to_phys(page);
24} 24}
25 25
26static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 26static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
27 dma_addr_t dma_addr)
27{ 28{
28 return dma_addr; 29 return dma_addr;
29} 30}
30 31
31static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 32static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
33 size_t size, enum dma_data_direction direction)
32{ 34{
33} 35}
34 36
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index 4c21bfca10c3..d3d04018a858 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -33,12 +33,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
33 return pa; 33 return pa;
34} 34}
35 35
36static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 36static unsigned long plat_dma_addr_to_phys(struct device *dev,
37 dma_addr_t dma_addr)
37{ 38{
38 return dma_addr & ~(0xffUL << 56); 39 return dma_addr & ~(0xffUL << 56);
39} 40}
40 41
41static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 42static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
43 size_t size, enum dma_data_direction direction)
42{ 44{
43} 45}
44 46
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index 7ae40f4b1c80..37855955b313 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -50,7 +50,8 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
50} 50}
51 51
52/* This is almost certainly wrong but it's what dma-ip32.c used to use */ 52/* This is almost certainly wrong but it's what dma-ip32.c used to use */
53static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 53static unsigned long plat_dma_addr_to_phys(struct device *dev,
54 dma_addr_t dma_addr)
54{ 55{
55 unsigned long addr = dma_addr & RAM_OFFSET_MASK; 56 unsigned long addr = dma_addr & RAM_OFFSET_MASK;
56 57
@@ -60,7 +61,8 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
60 return addr; 61 return addr;
61} 62}
62 63
63static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 64static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
65 size_t size, enum dma_data_direction direction)
64{ 66{
65} 67}
66 68
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index 1c7cd27efa7b..f93aee59454a 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -22,12 +22,14 @@ static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
22 return vdma_alloc(page_to_phys(page), PAGE_SIZE); 22 return vdma_alloc(page_to_phys(page), PAGE_SIZE);
23} 23}
24 24
25static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 25static unsigned long plat_dma_addr_to_phys(struct device *dev,
26 dma_addr_t dma_addr)
26{ 27{
27 return vdma_log2phys(dma_addr); 28 return vdma_log2phys(dma_addr);
28} 29}
29 30
30static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 31static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
32 size_t size, enum dma_data_direction direction)
31{ 33{
32 vdma_free(dma_addr); 34 vdma_free(dma_addr);
33} 35}
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 38fad7dfe7da..c8de5e750777 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -25,12 +25,14 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
25 return page_to_phys(page) | 0x80000000; 25 return page_to_phys(page) | 0x80000000;
26} 26}
27 27
28static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) 28static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
29 dma_addr_t dma_addr)
29{ 30{
30 return dma_addr & 0x7fffffff; 31 return dma_addr & 0x7fffffff;
31} 32}
32 33
33static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) 34static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
35 size_t size, enum dma_data_direction direction)
34{ 36{
35} 37}
36 38
diff --git a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
index f3bc7efa2608..c3e4d3a4c95d 100644
--- a/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-rc32434/cpu-feature-overrides.h
@@ -53,11 +53,6 @@
53#define cpu_has_smartmips 0 53#define cpu_has_smartmips 0
54 54
55#define cpu_has_vtag_icache 0 55#define cpu_has_vtag_icache 0
56/* #define cpu_has_dc_aliases ? */
57/* #define cpu_has_ic_fills_f_dc ? */
58/* #define cpu_has_pindexed_dcache ? */
59
60/* #define cpu_icache_snoops_remote_store ? */
61 56
62#define cpu_has_mips32r1 1 57#define cpu_has_mips32r1 1
63#define cpu_has_mips32r2 0 58#define cpu_has_mips32r2 0
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 32ef8bec5c85..a581d60cbcc2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -220,6 +220,22 @@
220#error Bad page size configuration! 220#error Bad page size configuration!
221#endif 221#endif
222 222
223/*
224 * Default huge tlb size for a given kernel configuration
225 */
226#ifdef CONFIG_PAGE_SIZE_4KB
227#define PM_HUGE_MASK PM_1M
228#elif defined(CONFIG_PAGE_SIZE_8KB)
229#define PM_HUGE_MASK PM_4M
230#elif defined(CONFIG_PAGE_SIZE_16KB)
231#define PM_HUGE_MASK PM_16M
232#elif defined(CONFIG_PAGE_SIZE_32KB)
233#define PM_HUGE_MASK PM_64M
234#elif defined(CONFIG_PAGE_SIZE_64KB)
235#define PM_HUGE_MASK PM_256M
236#elif defined(CONFIG_HUGETLB_PAGE)
237#error Bad page size configuration for hugetlbfs!
238#endif
223 239
224/* 240/*
225 * Values used for computation of new tlb entries 241 * Values used for computation of new tlb entries
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 692989acd8a9..f3c23a43f845 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -157,6 +157,13 @@ enum cvmx_board_types_enum {
157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21, 157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
158 CVMX_BOARD_TYPE_EBT5600 = 22, 158 CVMX_BOARD_TYPE_EBT5600 = 22,
159 CVMX_BOARD_TYPE_EBH5201 = 23, 159 CVMX_BOARD_TYPE_EBH5201 = 23,
160 CVMX_BOARD_TYPE_EBT5200 = 24,
161 CVMX_BOARD_TYPE_CB5600 = 25,
162 CVMX_BOARD_TYPE_CB5601 = 26,
163 CVMX_BOARD_TYPE_CB5200 = 27,
164 /* Special 'generic' board type, supports many boards */
165 CVMX_BOARD_TYPE_GENERIC = 28,
166 CVMX_BOARD_TYPE_EBH5610 = 29,
160 CVMX_BOARD_TYPE_MAX, 167 CVMX_BOARD_TYPE_MAX,
161 168
162 /* 169 /*
@@ -228,6 +235,12 @@ static inline const char *cvmx_board_type_to_string(enum
228 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) 235 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
229 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) 236 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
230 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) 237 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
238 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200)
239 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600)
240 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601)
241 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200)
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610)
231 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) 244 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
232 245
233 /* Customer boards listed here */ 246 /* Customer boards listed here */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 1cbe4b55889d..8e708bdb43f7 100644
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
183 * Returns 0 on failure, 183 * Returns 0 on failure,
184 * !0 on success 184 * !0 on success
185 */ 185 */
186
187
188/**
189 * Allocate a block of memory from the free list that was passed
190 * to the application by the bootloader, and assign it a name in the
191 * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
192 * Named blocks can later be freed.
193 *
194 * @size: Size in bytes of block to allocate
195 * @alignment: Alignment required - must be power of 2
196 * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
197 *
198 * Returns a pointer to block of memory, NULL on error
199 */
200extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
201 char *name);
202
203
204
205/**
206 * Allocate a block of memory from the free list that was passed
207 * to the application by the bootloader, and assign it a name in the
208 * global named block table. (part of the cvmx_bootmem_descriptor_t structure)
209 * Named blocks can later be freed.
210 *
211 * @size: Size in bytes of block to allocate
212 * @address: Physical address to allocate memory at. If this
213 * memory is not available, the allocation fails.
214 * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN
215 * bytes
216 *
217 * Returns a pointer to block of memory, NULL on error
218 */
219extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address,
220 char *name);
221
222
223
224/**
225 * Allocate a block of memory from a specific range of the free list
226 * that was passed to the application by the bootloader, and assign it
227 * a name in the global named block table. (part of the
228 * cvmx_bootmem_descriptor_t structure) Named blocks can later be
229 * freed. If request cannot be satisfied within the address range
230 * specified, NULL is returned
231 *
232 * @size: Size in bytes of block to allocate
233 * @min_addr: minimum address of range
234 * @max_addr: maximum address of range
235 * @align: Alignment of memory to be allocated. (must be a power of 2)
236 * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes
237 *
238 * Returns a pointer to block of memory, NULL on error
239 */
240extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
241 uint64_t max_addr, uint64_t align,
242 char *name);
243
186extern int cvmx_bootmem_free_named(char *name); 244extern int cvmx_bootmem_free_named(char *name);
187 245
188/** 246/**
@@ -224,6 +282,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
224 uint32_t flags); 282 uint32_t flags);
225 283
226/** 284/**
285 * Allocates a named block of physical memory from the free list, at
286 * (optional) requested address and alignment.
287 *
288 * @param size size of region to allocate. All requests are rounded
289 * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
290 * bytes size
291 * @param min_addr Minimum address that block can occupy.
292 * @param max_addr Specifies the maximum address_min (inclusive) that
293 * the allocation can use.
294 * @param alignment Requested alignment of the block. If this
295 * alignment cannot be met, the allocation fails.
296 * This must be a power of 2. (Note: Alignment of
297 * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
298 * internally enforced. Requested alignments of less
299 * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
300 * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
301 * @param name name to assign to named block
302 * @param flags Flags to control options for the allocation.
303 *
304 * @return physical address of block allocated, or -1 on failure
305 */
306int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
307 uint64_t max_addr,
308 uint64_t alignment,
309 char *name, uint32_t flags);
310
311/**
227 * Finds a named memory block by name. 312 * Finds a named memory block by name.
228 * Also used for finding an unused entry in the named block table. 313 * Also used for finding an unused entry in the named block table.
229 * 314 *
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-errata.h b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
new file mode 100644
index 000000000000..5fc99189ff58
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
@@ -0,0 +1,33 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_HELPER_ERRATA_H__
29#define __CVMX_HELPER_ERRATA_H__
30
31extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
32
33#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-helper-jtag.h b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
new file mode 100644
index 000000000000..29f016ddb895
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-helper-jtag.h
@@ -0,0 +1,43 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * @file
30 *
31 * Helper utilities for qlm_jtag.
32 *
33 */
34
35#ifndef __CVMX_HELPER_JTAG_H__
36#define __CVMX_HELPER_JTAG_H__
37
38extern void cvmx_helper_qlm_jtag_init(void);
39extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
40extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
41extern void cvmx_helper_qlm_jtag_update(int qlm);
42
43#endif /* __CVMX_HELPER_JTAG_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-npei-defs.h b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
new file mode 100644
index 000000000000..4b347bb8ce80
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npei-defs.h
@@ -0,0 +1,2560 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_NPEI_DEFS_H__
29#define __CVMX_NPEI_DEFS_H__
30
31#define CVMX_NPEI_BAR1_INDEXX(offset) \
32 (0x0000000000000000ull + (((offset) & 31) * 16))
33#define CVMX_NPEI_BIST_STATUS \
34 (0x0000000000000580ull)
35#define CVMX_NPEI_BIST_STATUS2 \
36 (0x0000000000000680ull)
37#define CVMX_NPEI_CTL_PORT0 \
38 (0x0000000000000250ull)
39#define CVMX_NPEI_CTL_PORT1 \
40 (0x0000000000000260ull)
41#define CVMX_NPEI_CTL_STATUS \
42 (0x0000000000000570ull)
43#define CVMX_NPEI_CTL_STATUS2 \
44 (0x0000000000003C00ull)
45#define CVMX_NPEI_DATA_OUT_CNT \
46 (0x00000000000005F0ull)
47#define CVMX_NPEI_DBG_DATA \
48 (0x0000000000000510ull)
49#define CVMX_NPEI_DBG_SELECT \
50 (0x0000000000000500ull)
51#define CVMX_NPEI_DMA0_INT_LEVEL \
52 (0x00000000000005C0ull)
53#define CVMX_NPEI_DMA1_INT_LEVEL \
54 (0x00000000000005D0ull)
55#define CVMX_NPEI_DMAX_COUNTS(offset) \
56 (0x0000000000000450ull + (((offset) & 7) * 16))
57#define CVMX_NPEI_DMAX_DBELL(offset) \
58 (0x00000000000003B0ull + (((offset) & 7) * 16))
59#define CVMX_NPEI_DMAX_IBUFF_SADDR(offset) \
60 (0x0000000000000400ull + (((offset) & 7) * 16))
61#define CVMX_NPEI_DMAX_NADDR(offset) \
62 (0x00000000000004A0ull + (((offset) & 7) * 16))
63#define CVMX_NPEI_DMA_CNTS \
64 (0x00000000000005E0ull)
65#define CVMX_NPEI_DMA_CONTROL \
66 (0x00000000000003A0ull)
67#define CVMX_NPEI_INT_A_ENB \
68 (0x0000000000000560ull)
69#define CVMX_NPEI_INT_A_ENB2 \
70 (0x0000000000003CE0ull)
71#define CVMX_NPEI_INT_A_SUM \
72 (0x0000000000000550ull)
73#define CVMX_NPEI_INT_ENB \
74 (0x0000000000000540ull)
75#define CVMX_NPEI_INT_ENB2 \
76 (0x0000000000003CD0ull)
77#define CVMX_NPEI_INT_INFO \
78 (0x0000000000000590ull)
79#define CVMX_NPEI_INT_SUM \
80 (0x0000000000000530ull)
81#define CVMX_NPEI_INT_SUM2 \
82 (0x0000000000003CC0ull)
83#define CVMX_NPEI_LAST_WIN_RDATA0 \
84 (0x0000000000000600ull)
85#define CVMX_NPEI_LAST_WIN_RDATA1 \
86 (0x0000000000000610ull)
87#define CVMX_NPEI_MEM_ACCESS_CTL \
88 (0x00000000000004F0ull)
89#define CVMX_NPEI_MEM_ACCESS_SUBIDX(offset) \
90 (0x0000000000000340ull + (((offset) & 31) * 16) - 16 * 12)
91#define CVMX_NPEI_MSI_ENB0 \
92 (0x0000000000003C50ull)
93#define CVMX_NPEI_MSI_ENB1 \
94 (0x0000000000003C60ull)
95#define CVMX_NPEI_MSI_ENB2 \
96 (0x0000000000003C70ull)
97#define CVMX_NPEI_MSI_ENB3 \
98 (0x0000000000003C80ull)
99#define CVMX_NPEI_MSI_RCV0 \
100 (0x0000000000003C10ull)
101#define CVMX_NPEI_MSI_RCV1 \
102 (0x0000000000003C20ull)
103#define CVMX_NPEI_MSI_RCV2 \
104 (0x0000000000003C30ull)
105#define CVMX_NPEI_MSI_RCV3 \
106 (0x0000000000003C40ull)
107#define CVMX_NPEI_MSI_RD_MAP \
108 (0x0000000000003CA0ull)
109#define CVMX_NPEI_MSI_W1C_ENB0 \
110 (0x0000000000003CF0ull)
111#define CVMX_NPEI_MSI_W1C_ENB1 \
112 (0x0000000000003D00ull)
113#define CVMX_NPEI_MSI_W1C_ENB2 \
114 (0x0000000000003D10ull)
115#define CVMX_NPEI_MSI_W1C_ENB3 \
116 (0x0000000000003D20ull)
117#define CVMX_NPEI_MSI_W1S_ENB0 \
118 (0x0000000000003D30ull)
119#define CVMX_NPEI_MSI_W1S_ENB1 \
120 (0x0000000000003D40ull)
121#define CVMX_NPEI_MSI_W1S_ENB2 \
122 (0x0000000000003D50ull)
123#define CVMX_NPEI_MSI_W1S_ENB3 \
124 (0x0000000000003D60ull)
125#define CVMX_NPEI_MSI_WR_MAP \
126 (0x0000000000003C90ull)
127#define CVMX_NPEI_PCIE_CREDIT_CNT \
128 (0x0000000000003D70ull)
129#define CVMX_NPEI_PCIE_MSI_RCV \
130 (0x0000000000003CB0ull)
131#define CVMX_NPEI_PCIE_MSI_RCV_B1 \
132 (0x0000000000000650ull)
133#define CVMX_NPEI_PCIE_MSI_RCV_B2 \
134 (0x0000000000000660ull)
135#define CVMX_NPEI_PCIE_MSI_RCV_B3 \
136 (0x0000000000000670ull)
137#define CVMX_NPEI_PKTX_CNTS(offset) \
138 (0x0000000000002400ull + (((offset) & 31) * 16))
139#define CVMX_NPEI_PKTX_INSTR_BADDR(offset) \
140 (0x0000000000002800ull + (((offset) & 31) * 16))
141#define CVMX_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
142 (0x0000000000002C00ull + (((offset) & 31) * 16))
143#define CVMX_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
144 (0x0000000000003000ull + (((offset) & 31) * 16))
145#define CVMX_NPEI_PKTX_INSTR_HEADER(offset) \
146 (0x0000000000003400ull + (((offset) & 31) * 16))
147#define CVMX_NPEI_PKTX_IN_BP(offset) \
148 (0x0000000000003800ull + (((offset) & 31) * 16))
149#define CVMX_NPEI_PKTX_SLIST_BADDR(offset) \
150 (0x0000000000001400ull + (((offset) & 31) * 16))
151#define CVMX_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
152 (0x0000000000001800ull + (((offset) & 31) * 16))
153#define CVMX_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
154 (0x0000000000001C00ull + (((offset) & 31) * 16))
155#define CVMX_NPEI_PKT_CNT_INT \
156 (0x0000000000001110ull)
157#define CVMX_NPEI_PKT_CNT_INT_ENB \
158 (0x0000000000001130ull)
159#define CVMX_NPEI_PKT_DATA_OUT_ES \
160 (0x00000000000010B0ull)
161#define CVMX_NPEI_PKT_DATA_OUT_NS \
162 (0x00000000000010A0ull)
163#define CVMX_NPEI_PKT_DATA_OUT_ROR \
164 (0x0000000000001090ull)
165#define CVMX_NPEI_PKT_DPADDR \
166 (0x0000000000001080ull)
167#define CVMX_NPEI_PKT_INPUT_CONTROL \
168 (0x0000000000001150ull)
169#define CVMX_NPEI_PKT_INSTR_ENB \
170 (0x0000000000001000ull)
171#define CVMX_NPEI_PKT_INSTR_RD_SIZE \
172 (0x0000000000001190ull)
173#define CVMX_NPEI_PKT_INSTR_SIZE \
174 (0x0000000000001020ull)
175#define CVMX_NPEI_PKT_INT_LEVELS \
176 (0x0000000000001100ull)
177#define CVMX_NPEI_PKT_IN_BP \
178 (0x00000000000006B0ull)
179#define CVMX_NPEI_PKT_IN_DONEX_CNTS(offset) \
180 (0x0000000000002000ull + (((offset) & 31) * 16))
181#define CVMX_NPEI_PKT_IN_INSTR_COUNTS \
182 (0x00000000000006A0ull)
183#define CVMX_NPEI_PKT_IN_PCIE_PORT \
184 (0x00000000000011A0ull)
185#define CVMX_NPEI_PKT_IPTR \
186 (0x0000000000001070ull)
187#define CVMX_NPEI_PKT_OUTPUT_WMARK \
188 (0x0000000000001160ull)
189#define CVMX_NPEI_PKT_OUT_BMODE \
190 (0x00000000000010D0ull)
191#define CVMX_NPEI_PKT_OUT_ENB \
192 (0x0000000000001010ull)
193#define CVMX_NPEI_PKT_PCIE_PORT \
194 (0x00000000000010E0ull)
195#define CVMX_NPEI_PKT_PORT_IN_RST \
196 (0x0000000000000690ull)
197#define CVMX_NPEI_PKT_SLIST_ES \
198 (0x0000000000001050ull)
199#define CVMX_NPEI_PKT_SLIST_ID_SIZE \
200 (0x0000000000001180ull)
201#define CVMX_NPEI_PKT_SLIST_NS \
202 (0x0000000000001040ull)
203#define CVMX_NPEI_PKT_SLIST_ROR \
204 (0x0000000000001030ull)
205#define CVMX_NPEI_PKT_TIME_INT \
206 (0x0000000000001120ull)
207#define CVMX_NPEI_PKT_TIME_INT_ENB \
208 (0x0000000000001140ull)
209#define CVMX_NPEI_RSL_INT_BLOCKS \
210 (0x0000000000000520ull)
211#define CVMX_NPEI_SCRATCH_1 \
212 (0x0000000000000270ull)
213#define CVMX_NPEI_STATE1 \
214 (0x0000000000000620ull)
215#define CVMX_NPEI_STATE2 \
216 (0x0000000000000630ull)
217#define CVMX_NPEI_STATE3 \
218 (0x0000000000000640ull)
219#define CVMX_NPEI_WINDOW_CTL \
220 (0x0000000000000380ull)
221#define CVMX_NPEI_WIN_RD_ADDR \
222 (0x0000000000000210ull)
223#define CVMX_NPEI_WIN_RD_DATA \
224 (0x0000000000000240ull)
225#define CVMX_NPEI_WIN_WR_ADDR \
226 (0x0000000000000200ull)
227#define CVMX_NPEI_WIN_WR_DATA \
228 (0x0000000000000220ull)
229#define CVMX_NPEI_WIN_WR_MASK \
230 (0x0000000000000230ull)
231
232union cvmx_npei_bar1_indexx {
233 uint32_t u32;
234 struct cvmx_npei_bar1_indexx_s {
235 uint32_t reserved_18_31:14;
236 uint32_t addr_idx:14;
237 uint32_t ca:1;
238 uint32_t end_swp:2;
239 uint32_t addr_v:1;
240 } s;
241 struct cvmx_npei_bar1_indexx_s cn52xx;
242 struct cvmx_npei_bar1_indexx_s cn52xxp1;
243 struct cvmx_npei_bar1_indexx_s cn56xx;
244 struct cvmx_npei_bar1_indexx_s cn56xxp1;
245};
246
247union cvmx_npei_bist_status {
248 uint64_t u64;
249 struct cvmx_npei_bist_status_s {
250 uint64_t pkt_rdf:1;
251 uint64_t pkt_pmem:1;
252 uint64_t pkt_p1:1;
253 uint64_t reserved_60_60:1;
254 uint64_t pcr_gim:1;
255 uint64_t pkt_pif:1;
256 uint64_t pcsr_int:1;
257 uint64_t pcsr_im:1;
258 uint64_t pcsr_cnt:1;
259 uint64_t pcsr_id:1;
260 uint64_t pcsr_sl:1;
261 uint64_t reserved_50_52:3;
262 uint64_t pkt_ind:1;
263 uint64_t pkt_slm:1;
264 uint64_t reserved_36_47:12;
265 uint64_t d0_pst:1;
266 uint64_t d1_pst:1;
267 uint64_t d2_pst:1;
268 uint64_t d3_pst:1;
269 uint64_t reserved_31_31:1;
270 uint64_t n2p0_c:1;
271 uint64_t n2p0_o:1;
272 uint64_t n2p1_c:1;
273 uint64_t n2p1_o:1;
274 uint64_t cpl_p0:1;
275 uint64_t cpl_p1:1;
276 uint64_t p2n1_po:1;
277 uint64_t p2n1_no:1;
278 uint64_t p2n1_co:1;
279 uint64_t p2n0_po:1;
280 uint64_t p2n0_no:1;
281 uint64_t p2n0_co:1;
282 uint64_t p2n0_c0:1;
283 uint64_t p2n0_c1:1;
284 uint64_t p2n0_n:1;
285 uint64_t p2n0_p0:1;
286 uint64_t p2n0_p1:1;
287 uint64_t p2n1_c0:1;
288 uint64_t p2n1_c1:1;
289 uint64_t p2n1_n:1;
290 uint64_t p2n1_p0:1;
291 uint64_t p2n1_p1:1;
292 uint64_t csm0:1;
293 uint64_t csm1:1;
294 uint64_t dif0:1;
295 uint64_t dif1:1;
296 uint64_t dif2:1;
297 uint64_t dif3:1;
298 uint64_t reserved_2_2:1;
299 uint64_t msi:1;
300 uint64_t ncb_cmd:1;
301 } s;
302 struct cvmx_npei_bist_status_cn52xx {
303 uint64_t pkt_rdf:1;
304 uint64_t pkt_pmem:1;
305 uint64_t pkt_p1:1;
306 uint64_t reserved_60_60:1;
307 uint64_t pcr_gim:1;
308 uint64_t pkt_pif:1;
309 uint64_t pcsr_int:1;
310 uint64_t pcsr_im:1;
311 uint64_t pcsr_cnt:1;
312 uint64_t pcsr_id:1;
313 uint64_t pcsr_sl:1;
314 uint64_t pkt_imem:1;
315 uint64_t pkt_pfm:1;
316 uint64_t pkt_pof:1;
317 uint64_t reserved_48_49:2;
318 uint64_t pkt_pop0:1;
319 uint64_t pkt_pop1:1;
320 uint64_t d0_mem:1;
321 uint64_t d1_mem:1;
322 uint64_t d2_mem:1;
323 uint64_t d3_mem:1;
324 uint64_t d4_mem:1;
325 uint64_t ds_mem:1;
326 uint64_t reserved_36_39:4;
327 uint64_t d0_pst:1;
328 uint64_t d1_pst:1;
329 uint64_t d2_pst:1;
330 uint64_t d3_pst:1;
331 uint64_t d4_pst:1;
332 uint64_t n2p0_c:1;
333 uint64_t n2p0_o:1;
334 uint64_t n2p1_c:1;
335 uint64_t n2p1_o:1;
336 uint64_t cpl_p0:1;
337 uint64_t cpl_p1:1;
338 uint64_t p2n1_po:1;
339 uint64_t p2n1_no:1;
340 uint64_t p2n1_co:1;
341 uint64_t p2n0_po:1;
342 uint64_t p2n0_no:1;
343 uint64_t p2n0_co:1;
344 uint64_t p2n0_c0:1;
345 uint64_t p2n0_c1:1;
346 uint64_t p2n0_n:1;
347 uint64_t p2n0_p0:1;
348 uint64_t p2n0_p1:1;
349 uint64_t p2n1_c0:1;
350 uint64_t p2n1_c1:1;
351 uint64_t p2n1_n:1;
352 uint64_t p2n1_p0:1;
353 uint64_t p2n1_p1:1;
354 uint64_t csm0:1;
355 uint64_t csm1:1;
356 uint64_t dif0:1;
357 uint64_t dif1:1;
358 uint64_t dif2:1;
359 uint64_t dif3:1;
360 uint64_t dif4:1;
361 uint64_t msi:1;
362 uint64_t ncb_cmd:1;
363 } cn52xx;
364 struct cvmx_npei_bist_status_cn52xxp1 {
365 uint64_t reserved_46_63:18;
366 uint64_t d0_mem0:1;
367 uint64_t d1_mem1:1;
368 uint64_t d2_mem2:1;
369 uint64_t d3_mem3:1;
370 uint64_t dr0_mem:1;
371 uint64_t d0_mem:1;
372 uint64_t d1_mem:1;
373 uint64_t d2_mem:1;
374 uint64_t d3_mem:1;
375 uint64_t dr1_mem:1;
376 uint64_t d0_pst:1;
377 uint64_t d1_pst:1;
378 uint64_t d2_pst:1;
379 uint64_t d3_pst:1;
380 uint64_t dr2_mem:1;
381 uint64_t n2p0_c:1;
382 uint64_t n2p0_o:1;
383 uint64_t n2p1_c:1;
384 uint64_t n2p1_o:1;
385 uint64_t cpl_p0:1;
386 uint64_t cpl_p1:1;
387 uint64_t p2n1_po:1;
388 uint64_t p2n1_no:1;
389 uint64_t p2n1_co:1;
390 uint64_t p2n0_po:1;
391 uint64_t p2n0_no:1;
392 uint64_t p2n0_co:1;
393 uint64_t p2n0_c0:1;
394 uint64_t p2n0_c1:1;
395 uint64_t p2n0_n:1;
396 uint64_t p2n0_p0:1;
397 uint64_t p2n0_p1:1;
398 uint64_t p2n1_c0:1;
399 uint64_t p2n1_c1:1;
400 uint64_t p2n1_n:1;
401 uint64_t p2n1_p0:1;
402 uint64_t p2n1_p1:1;
403 uint64_t csm0:1;
404 uint64_t csm1:1;
405 uint64_t dif0:1;
406 uint64_t dif1:1;
407 uint64_t dif2:1;
408 uint64_t dif3:1;
409 uint64_t dr3_mem:1;
410 uint64_t msi:1;
411 uint64_t ncb_cmd:1;
412 } cn52xxp1;
413 struct cvmx_npei_bist_status_cn56xx {
414 uint64_t pkt_rdf:1;
415 uint64_t reserved_60_62:3;
416 uint64_t pcr_gim:1;
417 uint64_t pkt_pif:1;
418 uint64_t pcsr_int:1;
419 uint64_t pcsr_im:1;
420 uint64_t pcsr_cnt:1;
421 uint64_t pcsr_id:1;
422 uint64_t pcsr_sl:1;
423 uint64_t pkt_imem:1;
424 uint64_t pkt_pfm:1;
425 uint64_t pkt_pof:1;
426 uint64_t reserved_48_49:2;
427 uint64_t pkt_pop0:1;
428 uint64_t pkt_pop1:1;
429 uint64_t d0_mem:1;
430 uint64_t d1_mem:1;
431 uint64_t d2_mem:1;
432 uint64_t d3_mem:1;
433 uint64_t d4_mem:1;
434 uint64_t ds_mem:1;
435 uint64_t reserved_36_39:4;
436 uint64_t d0_pst:1;
437 uint64_t d1_pst:1;
438 uint64_t d2_pst:1;
439 uint64_t d3_pst:1;
440 uint64_t d4_pst:1;
441 uint64_t n2p0_c:1;
442 uint64_t n2p0_o:1;
443 uint64_t n2p1_c:1;
444 uint64_t n2p1_o:1;
445 uint64_t cpl_p0:1;
446 uint64_t cpl_p1:1;
447 uint64_t p2n1_po:1;
448 uint64_t p2n1_no:1;
449 uint64_t p2n1_co:1;
450 uint64_t p2n0_po:1;
451 uint64_t p2n0_no:1;
452 uint64_t p2n0_co:1;
453 uint64_t p2n0_c0:1;
454 uint64_t p2n0_c1:1;
455 uint64_t p2n0_n:1;
456 uint64_t p2n0_p0:1;
457 uint64_t p2n0_p1:1;
458 uint64_t p2n1_c0:1;
459 uint64_t p2n1_c1:1;
460 uint64_t p2n1_n:1;
461 uint64_t p2n1_p0:1;
462 uint64_t p2n1_p1:1;
463 uint64_t csm0:1;
464 uint64_t csm1:1;
465 uint64_t dif0:1;
466 uint64_t dif1:1;
467 uint64_t dif2:1;
468 uint64_t dif3:1;
469 uint64_t dif4:1;
470 uint64_t msi:1;
471 uint64_t ncb_cmd:1;
472 } cn56xx;
473 struct cvmx_npei_bist_status_cn56xxp1 {
474 uint64_t reserved_58_63:6;
475 uint64_t pcsr_int:1;
476 uint64_t pcsr_im:1;
477 uint64_t pcsr_cnt:1;
478 uint64_t pcsr_id:1;
479 uint64_t pcsr_sl:1;
480 uint64_t pkt_pout:1;
481 uint64_t pkt_imem:1;
482 uint64_t pkt_cntm:1;
483 uint64_t pkt_ind:1;
484 uint64_t pkt_slm:1;
485 uint64_t pkt_odf:1;
486 uint64_t pkt_oif:1;
487 uint64_t pkt_out:1;
488 uint64_t pkt_i0:1;
489 uint64_t pkt_i1:1;
490 uint64_t pkt_s0:1;
491 uint64_t pkt_s1:1;
492 uint64_t d0_mem:1;
493 uint64_t d1_mem:1;
494 uint64_t d2_mem:1;
495 uint64_t d3_mem:1;
496 uint64_t d4_mem:1;
497 uint64_t d0_pst:1;
498 uint64_t d1_pst:1;
499 uint64_t d2_pst:1;
500 uint64_t d3_pst:1;
501 uint64_t d4_pst:1;
502 uint64_t n2p0_c:1;
503 uint64_t n2p0_o:1;
504 uint64_t n2p1_c:1;
505 uint64_t n2p1_o:1;
506 uint64_t cpl_p0:1;
507 uint64_t cpl_p1:1;
508 uint64_t p2n1_po:1;
509 uint64_t p2n1_no:1;
510 uint64_t p2n1_co:1;
511 uint64_t p2n0_po:1;
512 uint64_t p2n0_no:1;
513 uint64_t p2n0_co:1;
514 uint64_t p2n0_c0:1;
515 uint64_t p2n0_c1:1;
516 uint64_t p2n0_n:1;
517 uint64_t p2n0_p0:1;
518 uint64_t p2n0_p1:1;
519 uint64_t p2n1_c0:1;
520 uint64_t p2n1_c1:1;
521 uint64_t p2n1_n:1;
522 uint64_t p2n1_p0:1;
523 uint64_t p2n1_p1:1;
524 uint64_t csm0:1;
525 uint64_t csm1:1;
526 uint64_t dif0:1;
527 uint64_t dif1:1;
528 uint64_t dif2:1;
529 uint64_t dif3:1;
530 uint64_t dif4:1;
531 uint64_t msi:1;
532 uint64_t ncb_cmd:1;
533 } cn56xxp1;
534};
535
536union cvmx_npei_bist_status2 {
537 uint64_t u64;
538 struct cvmx_npei_bist_status2_s {
539 uint64_t reserved_5_63:59;
540 uint64_t psc_p0:1;
541 uint64_t psc_p1:1;
542 uint64_t pkt_gd:1;
543 uint64_t pkt_gl:1;
544 uint64_t pkt_blk:1;
545 } s;
546 struct cvmx_npei_bist_status2_s cn52xx;
547 struct cvmx_npei_bist_status2_s cn56xx;
548};
549
550union cvmx_npei_ctl_port0 {
551 uint64_t u64;
552 struct cvmx_npei_ctl_port0_s {
553 uint64_t reserved_21_63:43;
554 uint64_t waitl_com:1;
555 uint64_t intd:1;
556 uint64_t intc:1;
557 uint64_t intb:1;
558 uint64_t inta:1;
559 uint64_t intd_map:2;
560 uint64_t intc_map:2;
561 uint64_t intb_map:2;
562 uint64_t inta_map:2;
563 uint64_t ctlp_ro:1;
564 uint64_t reserved_6_6:1;
565 uint64_t ptlp_ro:1;
566 uint64_t bar2_enb:1;
567 uint64_t bar2_esx:2;
568 uint64_t bar2_cax:1;
569 uint64_t wait_com:1;
570 } s;
571 struct cvmx_npei_ctl_port0_s cn52xx;
572 struct cvmx_npei_ctl_port0_s cn52xxp1;
573 struct cvmx_npei_ctl_port0_s cn56xx;
574 struct cvmx_npei_ctl_port0_s cn56xxp1;
575};
576
577union cvmx_npei_ctl_port1 {
578 uint64_t u64;
579 struct cvmx_npei_ctl_port1_s {
580 uint64_t reserved_21_63:43;
581 uint64_t waitl_com:1;
582 uint64_t intd:1;
583 uint64_t intc:1;
584 uint64_t intb:1;
585 uint64_t inta:1;
586 uint64_t intd_map:2;
587 uint64_t intc_map:2;
588 uint64_t intb_map:2;
589 uint64_t inta_map:2;
590 uint64_t ctlp_ro:1;
591 uint64_t reserved_6_6:1;
592 uint64_t ptlp_ro:1;
593 uint64_t bar2_enb:1;
594 uint64_t bar2_esx:2;
595 uint64_t bar2_cax:1;
596 uint64_t wait_com:1;
597 } s;
598 struct cvmx_npei_ctl_port1_s cn52xx;
599 struct cvmx_npei_ctl_port1_s cn52xxp1;
600 struct cvmx_npei_ctl_port1_s cn56xx;
601 struct cvmx_npei_ctl_port1_s cn56xxp1;
602};
603
604union cvmx_npei_ctl_status {
605 uint64_t u64;
606 struct cvmx_npei_ctl_status_s {
607 uint64_t reserved_44_63:20;
608 uint64_t p1_ntags:6;
609 uint64_t p0_ntags:6;
610 uint64_t cfg_rtry:16;
611 uint64_t ring_en:1;
612 uint64_t lnk_rst:1;
613 uint64_t arb:1;
614 uint64_t pkt_bp:4;
615 uint64_t host_mode:1;
616 uint64_t chip_rev:8;
617 } s;
618 struct cvmx_npei_ctl_status_s cn52xx;
619 struct cvmx_npei_ctl_status_cn52xxp1 {
620 uint64_t reserved_44_63:20;
621 uint64_t p1_ntags:6;
622 uint64_t p0_ntags:6;
623 uint64_t cfg_rtry:16;
624 uint64_t reserved_15_15:1;
625 uint64_t lnk_rst:1;
626 uint64_t arb:1;
627 uint64_t reserved_9_12:4;
628 uint64_t host_mode:1;
629 uint64_t chip_rev:8;
630 } cn52xxp1;
631 struct cvmx_npei_ctl_status_s cn56xx;
632 struct cvmx_npei_ctl_status_cn56xxp1 {
633 uint64_t reserved_16_63:48;
634 uint64_t ring_en:1;
635 uint64_t lnk_rst:1;
636 uint64_t arb:1;
637 uint64_t pkt_bp:4;
638 uint64_t host_mode:1;
639 uint64_t chip_rev:8;
640 } cn56xxp1;
641};
642
643union cvmx_npei_ctl_status2 {
644 uint64_t u64;
645 struct cvmx_npei_ctl_status2_s {
646 uint64_t reserved_16_63:48;
647 uint64_t mps:1;
648 uint64_t mrrs:3;
649 uint64_t c1_w_flt:1;
650 uint64_t c0_w_flt:1;
651 uint64_t c1_b1_s:3;
652 uint64_t c0_b1_s:3;
653 uint64_t c1_wi_d:1;
654 uint64_t c1_b0_d:1;
655 uint64_t c0_wi_d:1;
656 uint64_t c0_b0_d:1;
657 } s;
658 struct cvmx_npei_ctl_status2_s cn52xx;
659 struct cvmx_npei_ctl_status2_s cn52xxp1;
660 struct cvmx_npei_ctl_status2_s cn56xx;
661 struct cvmx_npei_ctl_status2_s cn56xxp1;
662};
663
664union cvmx_npei_data_out_cnt {
665 uint64_t u64;
666 struct cvmx_npei_data_out_cnt_s {
667 uint64_t reserved_44_63:20;
668 uint64_t p1_ucnt:16;
669 uint64_t p1_fcnt:6;
670 uint64_t p0_ucnt:16;
671 uint64_t p0_fcnt:6;
672 } s;
673 struct cvmx_npei_data_out_cnt_s cn52xx;
674 struct cvmx_npei_data_out_cnt_s cn52xxp1;
675 struct cvmx_npei_data_out_cnt_s cn56xx;
676 struct cvmx_npei_data_out_cnt_s cn56xxp1;
677};
678
679union cvmx_npei_dbg_data {
680 uint64_t u64;
681 struct cvmx_npei_dbg_data_s {
682 uint64_t reserved_28_63:36;
683 uint64_t qlm0_rev_lanes:1;
684 uint64_t reserved_25_26:2;
685 uint64_t qlm1_spd:2;
686 uint64_t c_mul:5;
687 uint64_t dsel_ext:1;
688 uint64_t data:17;
689 } s;
690 struct cvmx_npei_dbg_data_cn52xx {
691 uint64_t reserved_29_63:35;
692 uint64_t qlm0_link_width:1;
693 uint64_t qlm0_rev_lanes:1;
694 uint64_t qlm1_mode:2;
695 uint64_t qlm1_spd:2;
696 uint64_t c_mul:5;
697 uint64_t dsel_ext:1;
698 uint64_t data:17;
699 } cn52xx;
700 struct cvmx_npei_dbg_data_cn52xx cn52xxp1;
701 struct cvmx_npei_dbg_data_cn56xx {
702 uint64_t reserved_29_63:35;
703 uint64_t qlm2_rev_lanes:1;
704 uint64_t qlm0_rev_lanes:1;
705 uint64_t qlm3_spd:2;
706 uint64_t qlm1_spd:2;
707 uint64_t c_mul:5;
708 uint64_t dsel_ext:1;
709 uint64_t data:17;
710 } cn56xx;
711 struct cvmx_npei_dbg_data_cn56xx cn56xxp1;
712};
713
714union cvmx_npei_dbg_select {
715 uint64_t u64;
716 struct cvmx_npei_dbg_select_s {
717 uint64_t reserved_16_63:48;
718 uint64_t dbg_sel:16;
719 } s;
720 struct cvmx_npei_dbg_select_s cn52xx;
721 struct cvmx_npei_dbg_select_s cn52xxp1;
722 struct cvmx_npei_dbg_select_s cn56xx;
723 struct cvmx_npei_dbg_select_s cn56xxp1;
724};
725
726union cvmx_npei_dmax_counts {
727 uint64_t u64;
728 struct cvmx_npei_dmax_counts_s {
729 uint64_t reserved_39_63:25;
730 uint64_t fcnt:7;
731 uint64_t dbell:32;
732 } s;
733 struct cvmx_npei_dmax_counts_s cn52xx;
734 struct cvmx_npei_dmax_counts_s cn52xxp1;
735 struct cvmx_npei_dmax_counts_s cn56xx;
736 struct cvmx_npei_dmax_counts_s cn56xxp1;
737};
738
739union cvmx_npei_dmax_dbell {
740 uint32_t u32;
741 struct cvmx_npei_dmax_dbell_s {
742 uint32_t reserved_16_31:16;
743 uint32_t dbell:16;
744 } s;
745 struct cvmx_npei_dmax_dbell_s cn52xx;
746 struct cvmx_npei_dmax_dbell_s cn52xxp1;
747 struct cvmx_npei_dmax_dbell_s cn56xx;
748 struct cvmx_npei_dmax_dbell_s cn56xxp1;
749};
750
751union cvmx_npei_dmax_ibuff_saddr {
752 uint64_t u64;
753 struct cvmx_npei_dmax_ibuff_saddr_s {
754 uint64_t reserved_37_63:27;
755 uint64_t idle:1;
756 uint64_t saddr:29;
757 uint64_t reserved_0_6:7;
758 } s;
759 struct cvmx_npei_dmax_ibuff_saddr_cn52xx {
760 uint64_t reserved_36_63:28;
761 uint64_t saddr:29;
762 uint64_t reserved_0_6:7;
763 } cn52xx;
764 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn52xxp1;
765 struct cvmx_npei_dmax_ibuff_saddr_s cn56xx;
766 struct cvmx_npei_dmax_ibuff_saddr_cn52xx cn56xxp1;
767};
768
769union cvmx_npei_dmax_naddr {
770 uint64_t u64;
771 struct cvmx_npei_dmax_naddr_s {
772 uint64_t reserved_36_63:28;
773 uint64_t addr:36;
774 } s;
775 struct cvmx_npei_dmax_naddr_s cn52xx;
776 struct cvmx_npei_dmax_naddr_s cn52xxp1;
777 struct cvmx_npei_dmax_naddr_s cn56xx;
778 struct cvmx_npei_dmax_naddr_s cn56xxp1;
779};
780
781union cvmx_npei_dma0_int_level {
782 uint64_t u64;
783 struct cvmx_npei_dma0_int_level_s {
784 uint64_t time:32;
785 uint64_t cnt:32;
786 } s;
787 struct cvmx_npei_dma0_int_level_s cn52xx;
788 struct cvmx_npei_dma0_int_level_s cn52xxp1;
789 struct cvmx_npei_dma0_int_level_s cn56xx;
790 struct cvmx_npei_dma0_int_level_s cn56xxp1;
791};
792
793union cvmx_npei_dma1_int_level {
794 uint64_t u64;
795 struct cvmx_npei_dma1_int_level_s {
796 uint64_t time:32;
797 uint64_t cnt:32;
798 } s;
799 struct cvmx_npei_dma1_int_level_s cn52xx;
800 struct cvmx_npei_dma1_int_level_s cn52xxp1;
801 struct cvmx_npei_dma1_int_level_s cn56xx;
802 struct cvmx_npei_dma1_int_level_s cn56xxp1;
803};
804
805union cvmx_npei_dma_cnts {
806 uint64_t u64;
807 struct cvmx_npei_dma_cnts_s {
808 uint64_t dma1:32;
809 uint64_t dma0:32;
810 } s;
811 struct cvmx_npei_dma_cnts_s cn52xx;
812 struct cvmx_npei_dma_cnts_s cn52xxp1;
813 struct cvmx_npei_dma_cnts_s cn56xx;
814 struct cvmx_npei_dma_cnts_s cn56xxp1;
815};
816
817union cvmx_npei_dma_control {
818 uint64_t u64;
819 struct cvmx_npei_dma_control_s {
820 uint64_t reserved_39_63:25;
821 uint64_t dma4_enb:1;
822 uint64_t dma3_enb:1;
823 uint64_t dma2_enb:1;
824 uint64_t dma1_enb:1;
825 uint64_t dma0_enb:1;
826 uint64_t b0_lend:1;
827 uint64_t dwb_denb:1;
828 uint64_t dwb_ichk:9;
829 uint64_t fpa_que:3;
830 uint64_t o_add1:1;
831 uint64_t o_ro:1;
832 uint64_t o_ns:1;
833 uint64_t o_es:2;
834 uint64_t o_mode:1;
835 uint64_t csize:14;
836 } s;
837 struct cvmx_npei_dma_control_s cn52xx;
838 struct cvmx_npei_dma_control_cn52xxp1 {
839 uint64_t reserved_38_63:26;
840 uint64_t dma3_enb:1;
841 uint64_t dma2_enb:1;
842 uint64_t dma1_enb:1;
843 uint64_t dma0_enb:1;
844 uint64_t b0_lend:1;
845 uint64_t dwb_denb:1;
846 uint64_t dwb_ichk:9;
847 uint64_t fpa_que:3;
848 uint64_t o_add1:1;
849 uint64_t o_ro:1;
850 uint64_t o_ns:1;
851 uint64_t o_es:2;
852 uint64_t o_mode:1;
853 uint64_t csize:14;
854 } cn52xxp1;
855 struct cvmx_npei_dma_control_s cn56xx;
856 struct cvmx_npei_dma_control_s cn56xxp1;
857};
858
859union cvmx_npei_int_a_enb {
860 uint64_t u64;
861 struct cvmx_npei_int_a_enb_s {
862 uint64_t reserved_10_63:54;
863 uint64_t pout_err:1;
864 uint64_t pin_bp:1;
865 uint64_t p1_rdlk:1;
866 uint64_t p0_rdlk:1;
867 uint64_t pgl_err:1;
868 uint64_t pdi_err:1;
869 uint64_t pop_err:1;
870 uint64_t pins_err:1;
871 uint64_t dma1_cpl:1;
872 uint64_t dma0_cpl:1;
873 } s;
874 struct cvmx_npei_int_a_enb_cn52xx {
875 uint64_t reserved_8_63:56;
876 uint64_t p1_rdlk:1;
877 uint64_t p0_rdlk:1;
878 uint64_t pgl_err:1;
879 uint64_t pdi_err:1;
880 uint64_t pop_err:1;
881 uint64_t pins_err:1;
882 uint64_t dma1_cpl:1;
883 uint64_t dma0_cpl:1;
884 } cn52xx;
885 struct cvmx_npei_int_a_enb_cn52xxp1 {
886 uint64_t reserved_2_63:62;
887 uint64_t dma1_cpl:1;
888 uint64_t dma0_cpl:1;
889 } cn52xxp1;
890 struct cvmx_npei_int_a_enb_s cn56xx;
891};
892
893union cvmx_npei_int_a_enb2 {
894 uint64_t u64;
895 struct cvmx_npei_int_a_enb2_s {
896 uint64_t reserved_10_63:54;
897 uint64_t pout_err:1;
898 uint64_t pin_bp:1;
899 uint64_t p1_rdlk:1;
900 uint64_t p0_rdlk:1;
901 uint64_t pgl_err:1;
902 uint64_t pdi_err:1;
903 uint64_t pop_err:1;
904 uint64_t pins_err:1;
905 uint64_t dma1_cpl:1;
906 uint64_t dma0_cpl:1;
907 } s;
908 struct cvmx_npei_int_a_enb2_cn52xx {
909 uint64_t reserved_8_63:56;
910 uint64_t p1_rdlk:1;
911 uint64_t p0_rdlk:1;
912 uint64_t pgl_err:1;
913 uint64_t pdi_err:1;
914 uint64_t pop_err:1;
915 uint64_t pins_err:1;
916 uint64_t reserved_0_1:2;
917 } cn52xx;
918 struct cvmx_npei_int_a_enb2_cn52xxp1 {
919 uint64_t reserved_2_63:62;
920 uint64_t dma1_cpl:1;
921 uint64_t dma0_cpl:1;
922 } cn52xxp1;
923 struct cvmx_npei_int_a_enb2_s cn56xx;
924};
925
926union cvmx_npei_int_a_sum {
927 uint64_t u64;
928 struct cvmx_npei_int_a_sum_s {
929 uint64_t reserved_10_63:54;
930 uint64_t pout_err:1;
931 uint64_t pin_bp:1;
932 uint64_t p1_rdlk:1;
933 uint64_t p0_rdlk:1;
934 uint64_t pgl_err:1;
935 uint64_t pdi_err:1;
936 uint64_t pop_err:1;
937 uint64_t pins_err:1;
938 uint64_t dma1_cpl:1;
939 uint64_t dma0_cpl:1;
940 } s;
941 struct cvmx_npei_int_a_sum_cn52xx {
942 uint64_t reserved_8_63:56;
943 uint64_t p1_rdlk:1;
944 uint64_t p0_rdlk:1;
945 uint64_t pgl_err:1;
946 uint64_t pdi_err:1;
947 uint64_t pop_err:1;
948 uint64_t pins_err:1;
949 uint64_t dma1_cpl:1;
950 uint64_t dma0_cpl:1;
951 } cn52xx;
952 struct cvmx_npei_int_a_sum_cn52xxp1 {
953 uint64_t reserved_2_63:62;
954 uint64_t dma1_cpl:1;
955 uint64_t dma0_cpl:1;
956 } cn52xxp1;
957 struct cvmx_npei_int_a_sum_s cn56xx;
958};
959
960union cvmx_npei_int_enb {
961 uint64_t u64;
962 struct cvmx_npei_int_enb_s {
963 uint64_t mio_inta:1;
964 uint64_t reserved_62_62:1;
965 uint64_t int_a:1;
966 uint64_t c1_ldwn:1;
967 uint64_t c0_ldwn:1;
968 uint64_t c1_exc:1;
969 uint64_t c0_exc:1;
970 uint64_t c1_up_wf:1;
971 uint64_t c0_up_wf:1;
972 uint64_t c1_un_wf:1;
973 uint64_t c0_un_wf:1;
974 uint64_t c1_un_bx:1;
975 uint64_t c1_un_wi:1;
976 uint64_t c1_un_b2:1;
977 uint64_t c1_un_b1:1;
978 uint64_t c1_un_b0:1;
979 uint64_t c1_up_bx:1;
980 uint64_t c1_up_wi:1;
981 uint64_t c1_up_b2:1;
982 uint64_t c1_up_b1:1;
983 uint64_t c1_up_b0:1;
984 uint64_t c0_un_bx:1;
985 uint64_t c0_un_wi:1;
986 uint64_t c0_un_b2:1;
987 uint64_t c0_un_b1:1;
988 uint64_t c0_un_b0:1;
989 uint64_t c0_up_bx:1;
990 uint64_t c0_up_wi:1;
991 uint64_t c0_up_b2:1;
992 uint64_t c0_up_b1:1;
993 uint64_t c0_up_b0:1;
994 uint64_t c1_hpint:1;
995 uint64_t c1_pmei:1;
996 uint64_t c1_wake:1;
997 uint64_t crs1_dr:1;
998 uint64_t c1_se:1;
999 uint64_t crs1_er:1;
1000 uint64_t c1_aeri:1;
1001 uint64_t c0_hpint:1;
1002 uint64_t c0_pmei:1;
1003 uint64_t c0_wake:1;
1004 uint64_t crs0_dr:1;
1005 uint64_t c0_se:1;
1006 uint64_t crs0_er:1;
1007 uint64_t c0_aeri:1;
1008 uint64_t ptime:1;
1009 uint64_t pcnt:1;
1010 uint64_t pidbof:1;
1011 uint64_t psldbof:1;
1012 uint64_t dtime1:1;
1013 uint64_t dtime0:1;
1014 uint64_t dcnt1:1;
1015 uint64_t dcnt0:1;
1016 uint64_t dma1fi:1;
1017 uint64_t dma0fi:1;
1018 uint64_t dma4dbo:1;
1019 uint64_t dma3dbo:1;
1020 uint64_t dma2dbo:1;
1021 uint64_t dma1dbo:1;
1022 uint64_t dma0dbo:1;
1023 uint64_t iob2big:1;
1024 uint64_t bar0_to:1;
1025 uint64_t rml_wto:1;
1026 uint64_t rml_rto:1;
1027 } s;
1028 struct cvmx_npei_int_enb_s cn52xx;
1029 struct cvmx_npei_int_enb_cn52xxp1 {
1030 uint64_t mio_inta:1;
1031 uint64_t reserved_62_62:1;
1032 uint64_t int_a:1;
1033 uint64_t c1_ldwn:1;
1034 uint64_t c0_ldwn:1;
1035 uint64_t c1_exc:1;
1036 uint64_t c0_exc:1;
1037 uint64_t c1_up_wf:1;
1038 uint64_t c0_up_wf:1;
1039 uint64_t c1_un_wf:1;
1040 uint64_t c0_un_wf:1;
1041 uint64_t c1_un_bx:1;
1042 uint64_t c1_un_wi:1;
1043 uint64_t c1_un_b2:1;
1044 uint64_t c1_un_b1:1;
1045 uint64_t c1_un_b0:1;
1046 uint64_t c1_up_bx:1;
1047 uint64_t c1_up_wi:1;
1048 uint64_t c1_up_b2:1;
1049 uint64_t c1_up_b1:1;
1050 uint64_t c1_up_b0:1;
1051 uint64_t c0_un_bx:1;
1052 uint64_t c0_un_wi:1;
1053 uint64_t c0_un_b2:1;
1054 uint64_t c0_un_b1:1;
1055 uint64_t c0_un_b0:1;
1056 uint64_t c0_up_bx:1;
1057 uint64_t c0_up_wi:1;
1058 uint64_t c0_up_b2:1;
1059 uint64_t c0_up_b1:1;
1060 uint64_t c0_up_b0:1;
1061 uint64_t c1_hpint:1;
1062 uint64_t c1_pmei:1;
1063 uint64_t c1_wake:1;
1064 uint64_t crs1_dr:1;
1065 uint64_t c1_se:1;
1066 uint64_t crs1_er:1;
1067 uint64_t c1_aeri:1;
1068 uint64_t c0_hpint:1;
1069 uint64_t c0_pmei:1;
1070 uint64_t c0_wake:1;
1071 uint64_t crs0_dr:1;
1072 uint64_t c0_se:1;
1073 uint64_t crs0_er:1;
1074 uint64_t c0_aeri:1;
1075 uint64_t ptime:1;
1076 uint64_t pcnt:1;
1077 uint64_t pidbof:1;
1078 uint64_t psldbof:1;
1079 uint64_t dtime1:1;
1080 uint64_t dtime0:1;
1081 uint64_t dcnt1:1;
1082 uint64_t dcnt0:1;
1083 uint64_t dma1fi:1;
1084 uint64_t dma0fi:1;
1085 uint64_t reserved_8_8:1;
1086 uint64_t dma3dbo:1;
1087 uint64_t dma2dbo:1;
1088 uint64_t dma1dbo:1;
1089 uint64_t dma0dbo:1;
1090 uint64_t iob2big:1;
1091 uint64_t bar0_to:1;
1092 uint64_t rml_wto:1;
1093 uint64_t rml_rto:1;
1094 } cn52xxp1;
1095 struct cvmx_npei_int_enb_s cn56xx;
1096 struct cvmx_npei_int_enb_cn56xxp1 {
1097 uint64_t mio_inta:1;
1098 uint64_t reserved_61_62:2;
1099 uint64_t c1_ldwn:1;
1100 uint64_t c0_ldwn:1;
1101 uint64_t c1_exc:1;
1102 uint64_t c0_exc:1;
1103 uint64_t c1_up_wf:1;
1104 uint64_t c0_up_wf:1;
1105 uint64_t c1_un_wf:1;
1106 uint64_t c0_un_wf:1;
1107 uint64_t c1_un_bx:1;
1108 uint64_t c1_un_wi:1;
1109 uint64_t c1_un_b2:1;
1110 uint64_t c1_un_b1:1;
1111 uint64_t c1_un_b0:1;
1112 uint64_t c1_up_bx:1;
1113 uint64_t c1_up_wi:1;
1114 uint64_t c1_up_b2:1;
1115 uint64_t c1_up_b1:1;
1116 uint64_t c1_up_b0:1;
1117 uint64_t c0_un_bx:1;
1118 uint64_t c0_un_wi:1;
1119 uint64_t c0_un_b2:1;
1120 uint64_t c0_un_b1:1;
1121 uint64_t c0_un_b0:1;
1122 uint64_t c0_up_bx:1;
1123 uint64_t c0_up_wi:1;
1124 uint64_t c0_up_b2:1;
1125 uint64_t c0_up_b1:1;
1126 uint64_t c0_up_b0:1;
1127 uint64_t c1_hpint:1;
1128 uint64_t c1_pmei:1;
1129 uint64_t c1_wake:1;
1130 uint64_t reserved_29_29:1;
1131 uint64_t c1_se:1;
1132 uint64_t reserved_27_27:1;
1133 uint64_t c1_aeri:1;
1134 uint64_t c0_hpint:1;
1135 uint64_t c0_pmei:1;
1136 uint64_t c0_wake:1;
1137 uint64_t reserved_22_22:1;
1138 uint64_t c0_se:1;
1139 uint64_t reserved_20_20:1;
1140 uint64_t c0_aeri:1;
1141 uint64_t ptime:1;
1142 uint64_t pcnt:1;
1143 uint64_t pidbof:1;
1144 uint64_t psldbof:1;
1145 uint64_t dtime1:1;
1146 uint64_t dtime0:1;
1147 uint64_t dcnt1:1;
1148 uint64_t dcnt0:1;
1149 uint64_t dma1fi:1;
1150 uint64_t dma0fi:1;
1151 uint64_t dma4dbo:1;
1152 uint64_t dma3dbo:1;
1153 uint64_t dma2dbo:1;
1154 uint64_t dma1dbo:1;
1155 uint64_t dma0dbo:1;
1156 uint64_t iob2big:1;
1157 uint64_t bar0_to:1;
1158 uint64_t rml_wto:1;
1159 uint64_t rml_rto:1;
1160 } cn56xxp1;
1161};
1162
1163union cvmx_npei_int_enb2 {
1164 uint64_t u64;
1165 struct cvmx_npei_int_enb2_s {
1166 uint64_t reserved_62_63:2;
1167 uint64_t int_a:1;
1168 uint64_t c1_ldwn:1;
1169 uint64_t c0_ldwn:1;
1170 uint64_t c1_exc:1;
1171 uint64_t c0_exc:1;
1172 uint64_t c1_up_wf:1;
1173 uint64_t c0_up_wf:1;
1174 uint64_t c1_un_wf:1;
1175 uint64_t c0_un_wf:1;
1176 uint64_t c1_un_bx:1;
1177 uint64_t c1_un_wi:1;
1178 uint64_t c1_un_b2:1;
1179 uint64_t c1_un_b1:1;
1180 uint64_t c1_un_b0:1;
1181 uint64_t c1_up_bx:1;
1182 uint64_t c1_up_wi:1;
1183 uint64_t c1_up_b2:1;
1184 uint64_t c1_up_b1:1;
1185 uint64_t c1_up_b0:1;
1186 uint64_t c0_un_bx:1;
1187 uint64_t c0_un_wi:1;
1188 uint64_t c0_un_b2:1;
1189 uint64_t c0_un_b1:1;
1190 uint64_t c0_un_b0:1;
1191 uint64_t c0_up_bx:1;
1192 uint64_t c0_up_wi:1;
1193 uint64_t c0_up_b2:1;
1194 uint64_t c0_up_b1:1;
1195 uint64_t c0_up_b0:1;
1196 uint64_t c1_hpint:1;
1197 uint64_t c1_pmei:1;
1198 uint64_t c1_wake:1;
1199 uint64_t crs1_dr:1;
1200 uint64_t c1_se:1;
1201 uint64_t crs1_er:1;
1202 uint64_t c1_aeri:1;
1203 uint64_t c0_hpint:1;
1204 uint64_t c0_pmei:1;
1205 uint64_t c0_wake:1;
1206 uint64_t crs0_dr:1;
1207 uint64_t c0_se:1;
1208 uint64_t crs0_er:1;
1209 uint64_t c0_aeri:1;
1210 uint64_t ptime:1;
1211 uint64_t pcnt:1;
1212 uint64_t pidbof:1;
1213 uint64_t psldbof:1;
1214 uint64_t dtime1:1;
1215 uint64_t dtime0:1;
1216 uint64_t dcnt1:1;
1217 uint64_t dcnt0:1;
1218 uint64_t dma1fi:1;
1219 uint64_t dma0fi:1;
1220 uint64_t dma4dbo:1;
1221 uint64_t dma3dbo:1;
1222 uint64_t dma2dbo:1;
1223 uint64_t dma1dbo:1;
1224 uint64_t dma0dbo:1;
1225 uint64_t iob2big:1;
1226 uint64_t bar0_to:1;
1227 uint64_t rml_wto:1;
1228 uint64_t rml_rto:1;
1229 } s;
1230 struct cvmx_npei_int_enb2_s cn52xx;
1231 struct cvmx_npei_int_enb2_cn52xxp1 {
1232 uint64_t reserved_62_63:2;
1233 uint64_t int_a:1;
1234 uint64_t c1_ldwn:1;
1235 uint64_t c0_ldwn:1;
1236 uint64_t c1_exc:1;
1237 uint64_t c0_exc:1;
1238 uint64_t c1_up_wf:1;
1239 uint64_t c0_up_wf:1;
1240 uint64_t c1_un_wf:1;
1241 uint64_t c0_un_wf:1;
1242 uint64_t c1_un_bx:1;
1243 uint64_t c1_un_wi:1;
1244 uint64_t c1_un_b2:1;
1245 uint64_t c1_un_b1:1;
1246 uint64_t c1_un_b0:1;
1247 uint64_t c1_up_bx:1;
1248 uint64_t c1_up_wi:1;
1249 uint64_t c1_up_b2:1;
1250 uint64_t c1_up_b1:1;
1251 uint64_t c1_up_b0:1;
1252 uint64_t c0_un_bx:1;
1253 uint64_t c0_un_wi:1;
1254 uint64_t c0_un_b2:1;
1255 uint64_t c0_un_b1:1;
1256 uint64_t c0_un_b0:1;
1257 uint64_t c0_up_bx:1;
1258 uint64_t c0_up_wi:1;
1259 uint64_t c0_up_b2:1;
1260 uint64_t c0_up_b1:1;
1261 uint64_t c0_up_b0:1;
1262 uint64_t c1_hpint:1;
1263 uint64_t c1_pmei:1;
1264 uint64_t c1_wake:1;
1265 uint64_t crs1_dr:1;
1266 uint64_t c1_se:1;
1267 uint64_t crs1_er:1;
1268 uint64_t c1_aeri:1;
1269 uint64_t c0_hpint:1;
1270 uint64_t c0_pmei:1;
1271 uint64_t c0_wake:1;
1272 uint64_t crs0_dr:1;
1273 uint64_t c0_se:1;
1274 uint64_t crs0_er:1;
1275 uint64_t c0_aeri:1;
1276 uint64_t ptime:1;
1277 uint64_t pcnt:1;
1278 uint64_t pidbof:1;
1279 uint64_t psldbof:1;
1280 uint64_t dtime1:1;
1281 uint64_t dtime0:1;
1282 uint64_t dcnt1:1;
1283 uint64_t dcnt0:1;
1284 uint64_t dma1fi:1;
1285 uint64_t dma0fi:1;
1286 uint64_t reserved_8_8:1;
1287 uint64_t dma3dbo:1;
1288 uint64_t dma2dbo:1;
1289 uint64_t dma1dbo:1;
1290 uint64_t dma0dbo:1;
1291 uint64_t iob2big:1;
1292 uint64_t bar0_to:1;
1293 uint64_t rml_wto:1;
1294 uint64_t rml_rto:1;
1295 } cn52xxp1;
1296 struct cvmx_npei_int_enb2_s cn56xx;
1297 struct cvmx_npei_int_enb2_cn56xxp1 {
1298 uint64_t reserved_61_63:3;
1299 uint64_t c1_ldwn:1;
1300 uint64_t c0_ldwn:1;
1301 uint64_t c1_exc:1;
1302 uint64_t c0_exc:1;
1303 uint64_t c1_up_wf:1;
1304 uint64_t c0_up_wf:1;
1305 uint64_t c1_un_wf:1;
1306 uint64_t c0_un_wf:1;
1307 uint64_t c1_un_bx:1;
1308 uint64_t c1_un_wi:1;
1309 uint64_t c1_un_b2:1;
1310 uint64_t c1_un_b1:1;
1311 uint64_t c1_un_b0:1;
1312 uint64_t c1_up_bx:1;
1313 uint64_t c1_up_wi:1;
1314 uint64_t c1_up_b2:1;
1315 uint64_t c1_up_b1:1;
1316 uint64_t c1_up_b0:1;
1317 uint64_t c0_un_bx:1;
1318 uint64_t c0_un_wi:1;
1319 uint64_t c0_un_b2:1;
1320 uint64_t c0_un_b1:1;
1321 uint64_t c0_un_b0:1;
1322 uint64_t c0_up_bx:1;
1323 uint64_t c0_up_wi:1;
1324 uint64_t c0_up_b2:1;
1325 uint64_t c0_up_b1:1;
1326 uint64_t c0_up_b0:1;
1327 uint64_t c1_hpint:1;
1328 uint64_t c1_pmei:1;
1329 uint64_t c1_wake:1;
1330 uint64_t reserved_29_29:1;
1331 uint64_t c1_se:1;
1332 uint64_t reserved_27_27:1;
1333 uint64_t c1_aeri:1;
1334 uint64_t c0_hpint:1;
1335 uint64_t c0_pmei:1;
1336 uint64_t c0_wake:1;
1337 uint64_t reserved_22_22:1;
1338 uint64_t c0_se:1;
1339 uint64_t reserved_20_20:1;
1340 uint64_t c0_aeri:1;
1341 uint64_t ptime:1;
1342 uint64_t pcnt:1;
1343 uint64_t pidbof:1;
1344 uint64_t psldbof:1;
1345 uint64_t dtime1:1;
1346 uint64_t dtime0:1;
1347 uint64_t dcnt1:1;
1348 uint64_t dcnt0:1;
1349 uint64_t dma1fi:1;
1350 uint64_t dma0fi:1;
1351 uint64_t dma4dbo:1;
1352 uint64_t dma3dbo:1;
1353 uint64_t dma2dbo:1;
1354 uint64_t dma1dbo:1;
1355 uint64_t dma0dbo:1;
1356 uint64_t iob2big:1;
1357 uint64_t bar0_to:1;
1358 uint64_t rml_wto:1;
1359 uint64_t rml_rto:1;
1360 } cn56xxp1;
1361};
1362
1363union cvmx_npei_int_info {
1364 uint64_t u64;
1365 struct cvmx_npei_int_info_s {
1366 uint64_t reserved_12_63:52;
1367 uint64_t pidbof:6;
1368 uint64_t psldbof:6;
1369 } s;
1370 struct cvmx_npei_int_info_s cn52xx;
1371 struct cvmx_npei_int_info_s cn56xx;
1372 struct cvmx_npei_int_info_s cn56xxp1;
1373};
1374
1375union cvmx_npei_int_sum {
1376 uint64_t u64;
1377 struct cvmx_npei_int_sum_s {
1378 uint64_t mio_inta:1;
1379 uint64_t reserved_62_62:1;
1380 uint64_t int_a:1;
1381 uint64_t c1_ldwn:1;
1382 uint64_t c0_ldwn:1;
1383 uint64_t c1_exc:1;
1384 uint64_t c0_exc:1;
1385 uint64_t c1_up_wf:1;
1386 uint64_t c0_up_wf:1;
1387 uint64_t c1_un_wf:1;
1388 uint64_t c0_un_wf:1;
1389 uint64_t c1_un_bx:1;
1390 uint64_t c1_un_wi:1;
1391 uint64_t c1_un_b2:1;
1392 uint64_t c1_un_b1:1;
1393 uint64_t c1_un_b0:1;
1394 uint64_t c1_up_bx:1;
1395 uint64_t c1_up_wi:1;
1396 uint64_t c1_up_b2:1;
1397 uint64_t c1_up_b1:1;
1398 uint64_t c1_up_b0:1;
1399 uint64_t c0_un_bx:1;
1400 uint64_t c0_un_wi:1;
1401 uint64_t c0_un_b2:1;
1402 uint64_t c0_un_b1:1;
1403 uint64_t c0_un_b0:1;
1404 uint64_t c0_up_bx:1;
1405 uint64_t c0_up_wi:1;
1406 uint64_t c0_up_b2:1;
1407 uint64_t c0_up_b1:1;
1408 uint64_t c0_up_b0:1;
1409 uint64_t c1_hpint:1;
1410 uint64_t c1_pmei:1;
1411 uint64_t c1_wake:1;
1412 uint64_t crs1_dr:1;
1413 uint64_t c1_se:1;
1414 uint64_t crs1_er:1;
1415 uint64_t c1_aeri:1;
1416 uint64_t c0_hpint:1;
1417 uint64_t c0_pmei:1;
1418 uint64_t c0_wake:1;
1419 uint64_t crs0_dr:1;
1420 uint64_t c0_se:1;
1421 uint64_t crs0_er:1;
1422 uint64_t c0_aeri:1;
1423 uint64_t ptime:1;
1424 uint64_t pcnt:1;
1425 uint64_t pidbof:1;
1426 uint64_t psldbof:1;
1427 uint64_t dtime1:1;
1428 uint64_t dtime0:1;
1429 uint64_t dcnt1:1;
1430 uint64_t dcnt0:1;
1431 uint64_t dma1fi:1;
1432 uint64_t dma0fi:1;
1433 uint64_t dma4dbo:1;
1434 uint64_t dma3dbo:1;
1435 uint64_t dma2dbo:1;
1436 uint64_t dma1dbo:1;
1437 uint64_t dma0dbo:1;
1438 uint64_t iob2big:1;
1439 uint64_t bar0_to:1;
1440 uint64_t rml_wto:1;
1441 uint64_t rml_rto:1;
1442 } s;
1443 struct cvmx_npei_int_sum_s cn52xx;
1444 struct cvmx_npei_int_sum_cn52xxp1 {
1445 uint64_t mio_inta:1;
1446 uint64_t reserved_62_62:1;
1447 uint64_t int_a:1;
1448 uint64_t c1_ldwn:1;
1449 uint64_t c0_ldwn:1;
1450 uint64_t c1_exc:1;
1451 uint64_t c0_exc:1;
1452 uint64_t c1_up_wf:1;
1453 uint64_t c0_up_wf:1;
1454 uint64_t c1_un_wf:1;
1455 uint64_t c0_un_wf:1;
1456 uint64_t c1_un_bx:1;
1457 uint64_t c1_un_wi:1;
1458 uint64_t c1_un_b2:1;
1459 uint64_t c1_un_b1:1;
1460 uint64_t c1_un_b0:1;
1461 uint64_t c1_up_bx:1;
1462 uint64_t c1_up_wi:1;
1463 uint64_t c1_up_b2:1;
1464 uint64_t c1_up_b1:1;
1465 uint64_t c1_up_b0:1;
1466 uint64_t c0_un_bx:1;
1467 uint64_t c0_un_wi:1;
1468 uint64_t c0_un_b2:1;
1469 uint64_t c0_un_b1:1;
1470 uint64_t c0_un_b0:1;
1471 uint64_t c0_up_bx:1;
1472 uint64_t c0_up_wi:1;
1473 uint64_t c0_up_b2:1;
1474 uint64_t c0_up_b1:1;
1475 uint64_t c0_up_b0:1;
1476 uint64_t c1_hpint:1;
1477 uint64_t c1_pmei:1;
1478 uint64_t c1_wake:1;
1479 uint64_t crs1_dr:1;
1480 uint64_t c1_se:1;
1481 uint64_t crs1_er:1;
1482 uint64_t c1_aeri:1;
1483 uint64_t c0_hpint:1;
1484 uint64_t c0_pmei:1;
1485 uint64_t c0_wake:1;
1486 uint64_t crs0_dr:1;
1487 uint64_t c0_se:1;
1488 uint64_t crs0_er:1;
1489 uint64_t c0_aeri:1;
1490 uint64_t reserved_15_18:4;
1491 uint64_t dtime1:1;
1492 uint64_t dtime0:1;
1493 uint64_t dcnt1:1;
1494 uint64_t dcnt0:1;
1495 uint64_t dma1fi:1;
1496 uint64_t dma0fi:1;
1497 uint64_t reserved_8_8:1;
1498 uint64_t dma3dbo:1;
1499 uint64_t dma2dbo:1;
1500 uint64_t dma1dbo:1;
1501 uint64_t dma0dbo:1;
1502 uint64_t iob2big:1;
1503 uint64_t bar0_to:1;
1504 uint64_t rml_wto:1;
1505 uint64_t rml_rto:1;
1506 } cn52xxp1;
1507 struct cvmx_npei_int_sum_s cn56xx;
1508 struct cvmx_npei_int_sum_cn56xxp1 {
1509 uint64_t mio_inta:1;
1510 uint64_t reserved_61_62:2;
1511 uint64_t c1_ldwn:1;
1512 uint64_t c0_ldwn:1;
1513 uint64_t c1_exc:1;
1514 uint64_t c0_exc:1;
1515 uint64_t c1_up_wf:1;
1516 uint64_t c0_up_wf:1;
1517 uint64_t c1_un_wf:1;
1518 uint64_t c0_un_wf:1;
1519 uint64_t c1_un_bx:1;
1520 uint64_t c1_un_wi:1;
1521 uint64_t c1_un_b2:1;
1522 uint64_t c1_un_b1:1;
1523 uint64_t c1_un_b0:1;
1524 uint64_t c1_up_bx:1;
1525 uint64_t c1_up_wi:1;
1526 uint64_t c1_up_b2:1;
1527 uint64_t c1_up_b1:1;
1528 uint64_t c1_up_b0:1;
1529 uint64_t c0_un_bx:1;
1530 uint64_t c0_un_wi:1;
1531 uint64_t c0_un_b2:1;
1532 uint64_t c0_un_b1:1;
1533 uint64_t c0_un_b0:1;
1534 uint64_t c0_up_bx:1;
1535 uint64_t c0_up_wi:1;
1536 uint64_t c0_up_b2:1;
1537 uint64_t c0_up_b1:1;
1538 uint64_t c0_up_b0:1;
1539 uint64_t c1_hpint:1;
1540 uint64_t c1_pmei:1;
1541 uint64_t c1_wake:1;
1542 uint64_t reserved_29_29:1;
1543 uint64_t c1_se:1;
1544 uint64_t reserved_27_27:1;
1545 uint64_t c1_aeri:1;
1546 uint64_t c0_hpint:1;
1547 uint64_t c0_pmei:1;
1548 uint64_t c0_wake:1;
1549 uint64_t reserved_22_22:1;
1550 uint64_t c0_se:1;
1551 uint64_t reserved_20_20:1;
1552 uint64_t c0_aeri:1;
1553 uint64_t ptime:1;
1554 uint64_t pcnt:1;
1555 uint64_t pidbof:1;
1556 uint64_t psldbof:1;
1557 uint64_t dtime1:1;
1558 uint64_t dtime0:1;
1559 uint64_t dcnt1:1;
1560 uint64_t dcnt0:1;
1561 uint64_t dma1fi:1;
1562 uint64_t dma0fi:1;
1563 uint64_t dma4dbo:1;
1564 uint64_t dma3dbo:1;
1565 uint64_t dma2dbo:1;
1566 uint64_t dma1dbo:1;
1567 uint64_t dma0dbo:1;
1568 uint64_t iob2big:1;
1569 uint64_t bar0_to:1;
1570 uint64_t rml_wto:1;
1571 uint64_t rml_rto:1;
1572 } cn56xxp1;
1573};
1574
1575union cvmx_npei_int_sum2 {
1576 uint64_t u64;
1577 struct cvmx_npei_int_sum2_s {
1578 uint64_t mio_inta:1;
1579 uint64_t reserved_62_62:1;
1580 uint64_t int_a:1;
1581 uint64_t c1_ldwn:1;
1582 uint64_t c0_ldwn:1;
1583 uint64_t c1_exc:1;
1584 uint64_t c0_exc:1;
1585 uint64_t c1_up_wf:1;
1586 uint64_t c0_up_wf:1;
1587 uint64_t c1_un_wf:1;
1588 uint64_t c0_un_wf:1;
1589 uint64_t c1_un_bx:1;
1590 uint64_t c1_un_wi:1;
1591 uint64_t c1_un_b2:1;
1592 uint64_t c1_un_b1:1;
1593 uint64_t c1_un_b0:1;
1594 uint64_t c1_up_bx:1;
1595 uint64_t c1_up_wi:1;
1596 uint64_t c1_up_b2:1;
1597 uint64_t c1_up_b1:1;
1598 uint64_t c1_up_b0:1;
1599 uint64_t c0_un_bx:1;
1600 uint64_t c0_un_wi:1;
1601 uint64_t c0_un_b2:1;
1602 uint64_t c0_un_b1:1;
1603 uint64_t c0_un_b0:1;
1604 uint64_t c0_up_bx:1;
1605 uint64_t c0_up_wi:1;
1606 uint64_t c0_up_b2:1;
1607 uint64_t c0_up_b1:1;
1608 uint64_t c0_up_b0:1;
1609 uint64_t c1_hpint:1;
1610 uint64_t c1_pmei:1;
1611 uint64_t c1_wake:1;
1612 uint64_t crs1_dr:1;
1613 uint64_t c1_se:1;
1614 uint64_t crs1_er:1;
1615 uint64_t c1_aeri:1;
1616 uint64_t c0_hpint:1;
1617 uint64_t c0_pmei:1;
1618 uint64_t c0_wake:1;
1619 uint64_t crs0_dr:1;
1620 uint64_t c0_se:1;
1621 uint64_t crs0_er:1;
1622 uint64_t c0_aeri:1;
1623 uint64_t reserved_15_18:4;
1624 uint64_t dtime1:1;
1625 uint64_t dtime0:1;
1626 uint64_t dcnt1:1;
1627 uint64_t dcnt0:1;
1628 uint64_t dma1fi:1;
1629 uint64_t dma0fi:1;
1630 uint64_t reserved_8_8:1;
1631 uint64_t dma3dbo:1;
1632 uint64_t dma2dbo:1;
1633 uint64_t dma1dbo:1;
1634 uint64_t dma0dbo:1;
1635 uint64_t iob2big:1;
1636 uint64_t bar0_to:1;
1637 uint64_t rml_wto:1;
1638 uint64_t rml_rto:1;
1639 } s;
1640 struct cvmx_npei_int_sum2_s cn52xx;
1641 struct cvmx_npei_int_sum2_s cn52xxp1;
1642 struct cvmx_npei_int_sum2_s cn56xx;
1643};
1644
1645union cvmx_npei_last_win_rdata0 {
1646 uint64_t u64;
1647 struct cvmx_npei_last_win_rdata0_s {
1648 uint64_t data:64;
1649 } s;
1650 struct cvmx_npei_last_win_rdata0_s cn52xx;
1651 struct cvmx_npei_last_win_rdata0_s cn52xxp1;
1652 struct cvmx_npei_last_win_rdata0_s cn56xx;
1653 struct cvmx_npei_last_win_rdata0_s cn56xxp1;
1654};
1655
1656union cvmx_npei_last_win_rdata1 {
1657 uint64_t u64;
1658 struct cvmx_npei_last_win_rdata1_s {
1659 uint64_t data:64;
1660 } s;
1661 struct cvmx_npei_last_win_rdata1_s cn52xx;
1662 struct cvmx_npei_last_win_rdata1_s cn52xxp1;
1663 struct cvmx_npei_last_win_rdata1_s cn56xx;
1664 struct cvmx_npei_last_win_rdata1_s cn56xxp1;
1665};
1666
1667union cvmx_npei_mem_access_ctl {
1668 uint64_t u64;
1669 struct cvmx_npei_mem_access_ctl_s {
1670 uint64_t reserved_14_63:50;
1671 uint64_t max_word:4;
1672 uint64_t timer:10;
1673 } s;
1674 struct cvmx_npei_mem_access_ctl_s cn52xx;
1675 struct cvmx_npei_mem_access_ctl_s cn52xxp1;
1676 struct cvmx_npei_mem_access_ctl_s cn56xx;
1677 struct cvmx_npei_mem_access_ctl_s cn56xxp1;
1678};
1679
1680union cvmx_npei_mem_access_subidx {
1681 uint64_t u64;
1682 struct cvmx_npei_mem_access_subidx_s {
1683 uint64_t reserved_42_63:22;
1684 uint64_t zero:1;
1685 uint64_t port:2;
1686 uint64_t nmerge:1;
1687 uint64_t esr:2;
1688 uint64_t esw:2;
1689 uint64_t nsr:1;
1690 uint64_t nsw:1;
1691 uint64_t ror:1;
1692 uint64_t row:1;
1693 uint64_t ba:30;
1694 } s;
1695 struct cvmx_npei_mem_access_subidx_s cn52xx;
1696 struct cvmx_npei_mem_access_subidx_s cn52xxp1;
1697 struct cvmx_npei_mem_access_subidx_s cn56xx;
1698 struct cvmx_npei_mem_access_subidx_s cn56xxp1;
1699};
1700
1701union cvmx_npei_msi_enb0 {
1702 uint64_t u64;
1703 struct cvmx_npei_msi_enb0_s {
1704 uint64_t enb:64;
1705 } s;
1706 struct cvmx_npei_msi_enb0_s cn52xx;
1707 struct cvmx_npei_msi_enb0_s cn52xxp1;
1708 struct cvmx_npei_msi_enb0_s cn56xx;
1709 struct cvmx_npei_msi_enb0_s cn56xxp1;
1710};
1711
1712union cvmx_npei_msi_enb1 {
1713 uint64_t u64;
1714 struct cvmx_npei_msi_enb1_s {
1715 uint64_t enb:64;
1716 } s;
1717 struct cvmx_npei_msi_enb1_s cn52xx;
1718 struct cvmx_npei_msi_enb1_s cn52xxp1;
1719 struct cvmx_npei_msi_enb1_s cn56xx;
1720 struct cvmx_npei_msi_enb1_s cn56xxp1;
1721};
1722
1723union cvmx_npei_msi_enb2 {
1724 uint64_t u64;
1725 struct cvmx_npei_msi_enb2_s {
1726 uint64_t enb:64;
1727 } s;
1728 struct cvmx_npei_msi_enb2_s cn52xx;
1729 struct cvmx_npei_msi_enb2_s cn52xxp1;
1730 struct cvmx_npei_msi_enb2_s cn56xx;
1731 struct cvmx_npei_msi_enb2_s cn56xxp1;
1732};
1733
1734union cvmx_npei_msi_enb3 {
1735 uint64_t u64;
1736 struct cvmx_npei_msi_enb3_s {
1737 uint64_t enb:64;
1738 } s;
1739 struct cvmx_npei_msi_enb3_s cn52xx;
1740 struct cvmx_npei_msi_enb3_s cn52xxp1;
1741 struct cvmx_npei_msi_enb3_s cn56xx;
1742 struct cvmx_npei_msi_enb3_s cn56xxp1;
1743};
1744
1745union cvmx_npei_msi_rcv0 {
1746 uint64_t u64;
1747 struct cvmx_npei_msi_rcv0_s {
1748 uint64_t intr:64;
1749 } s;
1750 struct cvmx_npei_msi_rcv0_s cn52xx;
1751 struct cvmx_npei_msi_rcv0_s cn52xxp1;
1752 struct cvmx_npei_msi_rcv0_s cn56xx;
1753 struct cvmx_npei_msi_rcv0_s cn56xxp1;
1754};
1755
1756union cvmx_npei_msi_rcv1 {
1757 uint64_t u64;
1758 struct cvmx_npei_msi_rcv1_s {
1759 uint64_t intr:64;
1760 } s;
1761 struct cvmx_npei_msi_rcv1_s cn52xx;
1762 struct cvmx_npei_msi_rcv1_s cn52xxp1;
1763 struct cvmx_npei_msi_rcv1_s cn56xx;
1764 struct cvmx_npei_msi_rcv1_s cn56xxp1;
1765};
1766
1767union cvmx_npei_msi_rcv2 {
1768 uint64_t u64;
1769 struct cvmx_npei_msi_rcv2_s {
1770 uint64_t intr:64;
1771 } s;
1772 struct cvmx_npei_msi_rcv2_s cn52xx;
1773 struct cvmx_npei_msi_rcv2_s cn52xxp1;
1774 struct cvmx_npei_msi_rcv2_s cn56xx;
1775 struct cvmx_npei_msi_rcv2_s cn56xxp1;
1776};
1777
1778union cvmx_npei_msi_rcv3 {
1779 uint64_t u64;
1780 struct cvmx_npei_msi_rcv3_s {
1781 uint64_t intr:64;
1782 } s;
1783 struct cvmx_npei_msi_rcv3_s cn52xx;
1784 struct cvmx_npei_msi_rcv3_s cn52xxp1;
1785 struct cvmx_npei_msi_rcv3_s cn56xx;
1786 struct cvmx_npei_msi_rcv3_s cn56xxp1;
1787};
1788
1789union cvmx_npei_msi_rd_map {
1790 uint64_t u64;
1791 struct cvmx_npei_msi_rd_map_s {
1792 uint64_t reserved_16_63:48;
1793 uint64_t rd_int:8;
1794 uint64_t msi_int:8;
1795 } s;
1796 struct cvmx_npei_msi_rd_map_s cn52xx;
1797 struct cvmx_npei_msi_rd_map_s cn52xxp1;
1798 struct cvmx_npei_msi_rd_map_s cn56xx;
1799 struct cvmx_npei_msi_rd_map_s cn56xxp1;
1800};
1801
1802union cvmx_npei_msi_w1c_enb0 {
1803 uint64_t u64;
1804 struct cvmx_npei_msi_w1c_enb0_s {
1805 uint64_t clr:64;
1806 } s;
1807 struct cvmx_npei_msi_w1c_enb0_s cn52xx;
1808 struct cvmx_npei_msi_w1c_enb0_s cn56xx;
1809};
1810
1811union cvmx_npei_msi_w1c_enb1 {
1812 uint64_t u64;
1813 struct cvmx_npei_msi_w1c_enb1_s {
1814 uint64_t clr:64;
1815 } s;
1816 struct cvmx_npei_msi_w1c_enb1_s cn52xx;
1817 struct cvmx_npei_msi_w1c_enb1_s cn56xx;
1818};
1819
1820union cvmx_npei_msi_w1c_enb2 {
1821 uint64_t u64;
1822 struct cvmx_npei_msi_w1c_enb2_s {
1823 uint64_t clr:64;
1824 } s;
1825 struct cvmx_npei_msi_w1c_enb2_s cn52xx;
1826 struct cvmx_npei_msi_w1c_enb2_s cn56xx;
1827};
1828
1829union cvmx_npei_msi_w1c_enb3 {
1830 uint64_t u64;
1831 struct cvmx_npei_msi_w1c_enb3_s {
1832 uint64_t clr:64;
1833 } s;
1834 struct cvmx_npei_msi_w1c_enb3_s cn52xx;
1835 struct cvmx_npei_msi_w1c_enb3_s cn56xx;
1836};
1837
1838union cvmx_npei_msi_w1s_enb0 {
1839 uint64_t u64;
1840 struct cvmx_npei_msi_w1s_enb0_s {
1841 uint64_t set:64;
1842 } s;
1843 struct cvmx_npei_msi_w1s_enb0_s cn52xx;
1844 struct cvmx_npei_msi_w1s_enb0_s cn56xx;
1845};
1846
1847union cvmx_npei_msi_w1s_enb1 {
1848 uint64_t u64;
1849 struct cvmx_npei_msi_w1s_enb1_s {
1850 uint64_t set:64;
1851 } s;
1852 struct cvmx_npei_msi_w1s_enb1_s cn52xx;
1853 struct cvmx_npei_msi_w1s_enb1_s cn56xx;
1854};
1855
1856union cvmx_npei_msi_w1s_enb2 {
1857 uint64_t u64;
1858 struct cvmx_npei_msi_w1s_enb2_s {
1859 uint64_t set:64;
1860 } s;
1861 struct cvmx_npei_msi_w1s_enb2_s cn52xx;
1862 struct cvmx_npei_msi_w1s_enb2_s cn56xx;
1863};
1864
1865union cvmx_npei_msi_w1s_enb3 {
1866 uint64_t u64;
1867 struct cvmx_npei_msi_w1s_enb3_s {
1868 uint64_t set:64;
1869 } s;
1870 struct cvmx_npei_msi_w1s_enb3_s cn52xx;
1871 struct cvmx_npei_msi_w1s_enb3_s cn56xx;
1872};
1873
1874union cvmx_npei_msi_wr_map {
1875 uint64_t u64;
1876 struct cvmx_npei_msi_wr_map_s {
1877 uint64_t reserved_16_63:48;
1878 uint64_t ciu_int:8;
1879 uint64_t msi_int:8;
1880 } s;
1881 struct cvmx_npei_msi_wr_map_s cn52xx;
1882 struct cvmx_npei_msi_wr_map_s cn52xxp1;
1883 struct cvmx_npei_msi_wr_map_s cn56xx;
1884 struct cvmx_npei_msi_wr_map_s cn56xxp1;
1885};
1886
1887union cvmx_npei_pcie_credit_cnt {
1888 uint64_t u64;
1889 struct cvmx_npei_pcie_credit_cnt_s {
1890 uint64_t reserved_48_63:16;
1891 uint64_t p1_ccnt:8;
1892 uint64_t p1_ncnt:8;
1893 uint64_t p1_pcnt:8;
1894 uint64_t p0_ccnt:8;
1895 uint64_t p0_ncnt:8;
1896 uint64_t p0_pcnt:8;
1897 } s;
1898 struct cvmx_npei_pcie_credit_cnt_s cn52xx;
1899 struct cvmx_npei_pcie_credit_cnt_s cn56xx;
1900};
1901
1902union cvmx_npei_pcie_msi_rcv {
1903 uint64_t u64;
1904 struct cvmx_npei_pcie_msi_rcv_s {
1905 uint64_t reserved_8_63:56;
1906 uint64_t intr:8;
1907 } s;
1908 struct cvmx_npei_pcie_msi_rcv_s cn52xx;
1909 struct cvmx_npei_pcie_msi_rcv_s cn52xxp1;
1910 struct cvmx_npei_pcie_msi_rcv_s cn56xx;
1911 struct cvmx_npei_pcie_msi_rcv_s cn56xxp1;
1912};
1913
1914union cvmx_npei_pcie_msi_rcv_b1 {
1915 uint64_t u64;
1916 struct cvmx_npei_pcie_msi_rcv_b1_s {
1917 uint64_t reserved_16_63:48;
1918 uint64_t intr:8;
1919 uint64_t reserved_0_7:8;
1920 } s;
1921 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xx;
1922 struct cvmx_npei_pcie_msi_rcv_b1_s cn52xxp1;
1923 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xx;
1924 struct cvmx_npei_pcie_msi_rcv_b1_s cn56xxp1;
1925};
1926
1927union cvmx_npei_pcie_msi_rcv_b2 {
1928 uint64_t u64;
1929 struct cvmx_npei_pcie_msi_rcv_b2_s {
1930 uint64_t reserved_24_63:40;
1931 uint64_t intr:8;
1932 uint64_t reserved_0_15:16;
1933 } s;
1934 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xx;
1935 struct cvmx_npei_pcie_msi_rcv_b2_s cn52xxp1;
1936 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xx;
1937 struct cvmx_npei_pcie_msi_rcv_b2_s cn56xxp1;
1938};
1939
1940union cvmx_npei_pcie_msi_rcv_b3 {
1941 uint64_t u64;
1942 struct cvmx_npei_pcie_msi_rcv_b3_s {
1943 uint64_t reserved_32_63:32;
1944 uint64_t intr:8;
1945 uint64_t reserved_0_23:24;
1946 } s;
1947 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xx;
1948 struct cvmx_npei_pcie_msi_rcv_b3_s cn52xxp1;
1949 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xx;
1950 struct cvmx_npei_pcie_msi_rcv_b3_s cn56xxp1;
1951};
1952
1953union cvmx_npei_pktx_cnts {
1954 uint64_t u64;
1955 struct cvmx_npei_pktx_cnts_s {
1956 uint64_t reserved_54_63:10;
1957 uint64_t timer:22;
1958 uint64_t cnt:32;
1959 } s;
1960 struct cvmx_npei_pktx_cnts_s cn52xx;
1961 struct cvmx_npei_pktx_cnts_s cn56xx;
1962 struct cvmx_npei_pktx_cnts_s cn56xxp1;
1963};
1964
1965union cvmx_npei_pktx_in_bp {
1966 uint64_t u64;
1967 struct cvmx_npei_pktx_in_bp_s {
1968 uint64_t wmark:32;
1969 uint64_t cnt:32;
1970 } s;
1971 struct cvmx_npei_pktx_in_bp_s cn52xx;
1972 struct cvmx_npei_pktx_in_bp_s cn56xx;
1973 struct cvmx_npei_pktx_in_bp_s cn56xxp1;
1974};
1975
1976union cvmx_npei_pktx_instr_baddr {
1977 uint64_t u64;
1978 struct cvmx_npei_pktx_instr_baddr_s {
1979 uint64_t addr:61;
1980 uint64_t reserved_0_2:3;
1981 } s;
1982 struct cvmx_npei_pktx_instr_baddr_s cn52xx;
1983 struct cvmx_npei_pktx_instr_baddr_s cn56xx;
1984 struct cvmx_npei_pktx_instr_baddr_s cn56xxp1;
1985};
1986
1987union cvmx_npei_pktx_instr_baoff_dbell {
1988 uint64_t u64;
1989 struct cvmx_npei_pktx_instr_baoff_dbell_s {
1990 uint64_t aoff:32;
1991 uint64_t dbell:32;
1992 } s;
1993 struct cvmx_npei_pktx_instr_baoff_dbell_s cn52xx;
1994 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xx;
1995 struct cvmx_npei_pktx_instr_baoff_dbell_s cn56xxp1;
1996};
1997
1998union cvmx_npei_pktx_instr_fifo_rsize {
1999 uint64_t u64;
2000 struct cvmx_npei_pktx_instr_fifo_rsize_s {
2001 uint64_t max:9;
2002 uint64_t rrp:9;
2003 uint64_t wrp:9;
2004 uint64_t fcnt:5;
2005 uint64_t rsize:32;
2006 } s;
2007 struct cvmx_npei_pktx_instr_fifo_rsize_s cn52xx;
2008 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xx;
2009 struct cvmx_npei_pktx_instr_fifo_rsize_s cn56xxp1;
2010};
2011
2012union cvmx_npei_pktx_instr_header {
2013 uint64_t u64;
2014 struct cvmx_npei_pktx_instr_header_s {
2015 uint64_t reserved_44_63:20;
2016 uint64_t pbp:1;
2017 uint64_t rsv_f:5;
2018 uint64_t rparmode:2;
2019 uint64_t rsv_e:1;
2020 uint64_t rskp_len:7;
2021 uint64_t rsv_d:6;
2022 uint64_t use_ihdr:1;
2023 uint64_t rsv_c:5;
2024 uint64_t par_mode:2;
2025 uint64_t rsv_b:1;
2026 uint64_t skp_len:7;
2027 uint64_t rsv_a:6;
2028 } s;
2029 struct cvmx_npei_pktx_instr_header_s cn52xx;
2030 struct cvmx_npei_pktx_instr_header_s cn56xx;
2031 struct cvmx_npei_pktx_instr_header_s cn56xxp1;
2032};
2033
2034union cvmx_npei_pktx_slist_baddr {
2035 uint64_t u64;
2036 struct cvmx_npei_pktx_slist_baddr_s {
2037 uint64_t addr:60;
2038 uint64_t reserved_0_3:4;
2039 } s;
2040 struct cvmx_npei_pktx_slist_baddr_s cn52xx;
2041 struct cvmx_npei_pktx_slist_baddr_s cn56xx;
2042 struct cvmx_npei_pktx_slist_baddr_s cn56xxp1;
2043};
2044
2045union cvmx_npei_pktx_slist_baoff_dbell {
2046 uint64_t u64;
2047 struct cvmx_npei_pktx_slist_baoff_dbell_s {
2048 uint64_t aoff:32;
2049 uint64_t dbell:32;
2050 } s;
2051 struct cvmx_npei_pktx_slist_baoff_dbell_s cn52xx;
2052 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xx;
2053 struct cvmx_npei_pktx_slist_baoff_dbell_s cn56xxp1;
2054};
2055
2056union cvmx_npei_pktx_slist_fifo_rsize {
2057 uint64_t u64;
2058 struct cvmx_npei_pktx_slist_fifo_rsize_s {
2059 uint64_t reserved_32_63:32;
2060 uint64_t rsize:32;
2061 } s;
2062 struct cvmx_npei_pktx_slist_fifo_rsize_s cn52xx;
2063 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xx;
2064 struct cvmx_npei_pktx_slist_fifo_rsize_s cn56xxp1;
2065};
2066
2067union cvmx_npei_pkt_cnt_int {
2068 uint64_t u64;
2069 struct cvmx_npei_pkt_cnt_int_s {
2070 uint64_t reserved_32_63:32;
2071 uint64_t port:32;
2072 } s;
2073 struct cvmx_npei_pkt_cnt_int_s cn52xx;
2074 struct cvmx_npei_pkt_cnt_int_s cn56xx;
2075 struct cvmx_npei_pkt_cnt_int_s cn56xxp1;
2076};
2077
2078union cvmx_npei_pkt_cnt_int_enb {
2079 uint64_t u64;
2080 struct cvmx_npei_pkt_cnt_int_enb_s {
2081 uint64_t reserved_32_63:32;
2082 uint64_t port:32;
2083 } s;
2084 struct cvmx_npei_pkt_cnt_int_enb_s cn52xx;
2085 struct cvmx_npei_pkt_cnt_int_enb_s cn56xx;
2086 struct cvmx_npei_pkt_cnt_int_enb_s cn56xxp1;
2087};
2088
2089union cvmx_npei_pkt_data_out_es {
2090 uint64_t u64;
2091 struct cvmx_npei_pkt_data_out_es_s {
2092 uint64_t es:64;
2093 } s;
2094 struct cvmx_npei_pkt_data_out_es_s cn52xx;
2095 struct cvmx_npei_pkt_data_out_es_s cn56xx;
2096 struct cvmx_npei_pkt_data_out_es_s cn56xxp1;
2097};
2098
2099union cvmx_npei_pkt_data_out_ns {
2100 uint64_t u64;
2101 struct cvmx_npei_pkt_data_out_ns_s {
2102 uint64_t reserved_32_63:32;
2103 uint64_t nsr:32;
2104 } s;
2105 struct cvmx_npei_pkt_data_out_ns_s cn52xx;
2106 struct cvmx_npei_pkt_data_out_ns_s cn56xx;
2107 struct cvmx_npei_pkt_data_out_ns_s cn56xxp1;
2108};
2109
2110union cvmx_npei_pkt_data_out_ror {
2111 uint64_t u64;
2112 struct cvmx_npei_pkt_data_out_ror_s {
2113 uint64_t reserved_32_63:32;
2114 uint64_t ror:32;
2115 } s;
2116 struct cvmx_npei_pkt_data_out_ror_s cn52xx;
2117 struct cvmx_npei_pkt_data_out_ror_s cn56xx;
2118 struct cvmx_npei_pkt_data_out_ror_s cn56xxp1;
2119};
2120
2121union cvmx_npei_pkt_dpaddr {
2122 uint64_t u64;
2123 struct cvmx_npei_pkt_dpaddr_s {
2124 uint64_t reserved_32_63:32;
2125 uint64_t dptr:32;
2126 } s;
2127 struct cvmx_npei_pkt_dpaddr_s cn52xx;
2128 struct cvmx_npei_pkt_dpaddr_s cn56xx;
2129 struct cvmx_npei_pkt_dpaddr_s cn56xxp1;
2130};
2131
2132union cvmx_npei_pkt_in_bp {
2133 uint64_t u64;
2134 struct cvmx_npei_pkt_in_bp_s {
2135 uint64_t reserved_32_63:32;
2136 uint64_t bp:32;
2137 } s;
2138 struct cvmx_npei_pkt_in_bp_s cn56xx;
2139};
2140
2141union cvmx_npei_pkt_in_donex_cnts {
2142 uint64_t u64;
2143 struct cvmx_npei_pkt_in_donex_cnts_s {
2144 uint64_t reserved_32_63:32;
2145 uint64_t cnt:32;
2146 } s;
2147 struct cvmx_npei_pkt_in_donex_cnts_s cn52xx;
2148 struct cvmx_npei_pkt_in_donex_cnts_s cn56xx;
2149 struct cvmx_npei_pkt_in_donex_cnts_s cn56xxp1;
2150};
2151
2152union cvmx_npei_pkt_in_instr_counts {
2153 uint64_t u64;
2154 struct cvmx_npei_pkt_in_instr_counts_s {
2155 uint64_t wr_cnt:32;
2156 uint64_t rd_cnt:32;
2157 } s;
2158 struct cvmx_npei_pkt_in_instr_counts_s cn52xx;
2159 struct cvmx_npei_pkt_in_instr_counts_s cn56xx;
2160};
2161
2162union cvmx_npei_pkt_in_pcie_port {
2163 uint64_t u64;
2164 struct cvmx_npei_pkt_in_pcie_port_s {
2165 uint64_t pp:64;
2166 } s;
2167 struct cvmx_npei_pkt_in_pcie_port_s cn52xx;
2168 struct cvmx_npei_pkt_in_pcie_port_s cn56xx;
2169};
2170
2171union cvmx_npei_pkt_input_control {
2172 uint64_t u64;
2173 struct cvmx_npei_pkt_input_control_s {
2174 uint64_t reserved_23_63:41;
2175 uint64_t pkt_rr:1;
2176 uint64_t pbp_dhi:13;
2177 uint64_t d_nsr:1;
2178 uint64_t d_esr:2;
2179 uint64_t d_ror:1;
2180 uint64_t use_csr:1;
2181 uint64_t nsr:1;
2182 uint64_t esr:2;
2183 uint64_t ror:1;
2184 } s;
2185 struct cvmx_npei_pkt_input_control_s cn52xx;
2186 struct cvmx_npei_pkt_input_control_s cn56xx;
2187 struct cvmx_npei_pkt_input_control_s cn56xxp1;
2188};
2189
2190union cvmx_npei_pkt_instr_enb {
2191 uint64_t u64;
2192 struct cvmx_npei_pkt_instr_enb_s {
2193 uint64_t reserved_32_63:32;
2194 uint64_t enb:32;
2195 } s;
2196 struct cvmx_npei_pkt_instr_enb_s cn52xx;
2197 struct cvmx_npei_pkt_instr_enb_s cn56xx;
2198 struct cvmx_npei_pkt_instr_enb_s cn56xxp1;
2199};
2200
2201union cvmx_npei_pkt_instr_rd_size {
2202 uint64_t u64;
2203 struct cvmx_npei_pkt_instr_rd_size_s {
2204 uint64_t rdsize:64;
2205 } s;
2206 struct cvmx_npei_pkt_instr_rd_size_s cn52xx;
2207 struct cvmx_npei_pkt_instr_rd_size_s cn56xx;
2208};
2209
2210union cvmx_npei_pkt_instr_size {
2211 uint64_t u64;
2212 struct cvmx_npei_pkt_instr_size_s {
2213 uint64_t reserved_32_63:32;
2214 uint64_t is_64b:32;
2215 } s;
2216 struct cvmx_npei_pkt_instr_size_s cn52xx;
2217 struct cvmx_npei_pkt_instr_size_s cn56xx;
2218 struct cvmx_npei_pkt_instr_size_s cn56xxp1;
2219};
2220
2221union cvmx_npei_pkt_int_levels {
2222 uint64_t u64;
2223 struct cvmx_npei_pkt_int_levels_s {
2224 uint64_t reserved_54_63:10;
2225 uint64_t time:22;
2226 uint64_t cnt:32;
2227 } s;
2228 struct cvmx_npei_pkt_int_levels_s cn52xx;
2229 struct cvmx_npei_pkt_int_levels_s cn56xx;
2230 struct cvmx_npei_pkt_int_levels_s cn56xxp1;
2231};
2232
2233union cvmx_npei_pkt_iptr {
2234 uint64_t u64;
2235 struct cvmx_npei_pkt_iptr_s {
2236 uint64_t reserved_32_63:32;
2237 uint64_t iptr:32;
2238 } s;
2239 struct cvmx_npei_pkt_iptr_s cn52xx;
2240 struct cvmx_npei_pkt_iptr_s cn56xx;
2241 struct cvmx_npei_pkt_iptr_s cn56xxp1;
2242};
2243
2244union cvmx_npei_pkt_out_bmode {
2245 uint64_t u64;
2246 struct cvmx_npei_pkt_out_bmode_s {
2247 uint64_t reserved_32_63:32;
2248 uint64_t bmode:32;
2249 } s;
2250 struct cvmx_npei_pkt_out_bmode_s cn52xx;
2251 struct cvmx_npei_pkt_out_bmode_s cn56xx;
2252 struct cvmx_npei_pkt_out_bmode_s cn56xxp1;
2253};
2254
2255union cvmx_npei_pkt_out_enb {
2256 uint64_t u64;
2257 struct cvmx_npei_pkt_out_enb_s {
2258 uint64_t reserved_32_63:32;
2259 uint64_t enb:32;
2260 } s;
2261 struct cvmx_npei_pkt_out_enb_s cn52xx;
2262 struct cvmx_npei_pkt_out_enb_s cn56xx;
2263 struct cvmx_npei_pkt_out_enb_s cn56xxp1;
2264};
2265
2266union cvmx_npei_pkt_output_wmark {
2267 uint64_t u64;
2268 struct cvmx_npei_pkt_output_wmark_s {
2269 uint64_t reserved_32_63:32;
2270 uint64_t wmark:32;
2271 } s;
2272 struct cvmx_npei_pkt_output_wmark_s cn52xx;
2273 struct cvmx_npei_pkt_output_wmark_s cn56xx;
2274};
2275
2276union cvmx_npei_pkt_pcie_port {
2277 uint64_t u64;
2278 struct cvmx_npei_pkt_pcie_port_s {
2279 uint64_t pp:64;
2280 } s;
2281 struct cvmx_npei_pkt_pcie_port_s cn52xx;
2282 struct cvmx_npei_pkt_pcie_port_s cn56xx;
2283 struct cvmx_npei_pkt_pcie_port_s cn56xxp1;
2284};
2285
2286union cvmx_npei_pkt_port_in_rst {
2287 uint64_t u64;
2288 struct cvmx_npei_pkt_port_in_rst_s {
2289 uint64_t in_rst:32;
2290 uint64_t out_rst:32;
2291 } s;
2292 struct cvmx_npei_pkt_port_in_rst_s cn52xx;
2293 struct cvmx_npei_pkt_port_in_rst_s cn56xx;
2294};
2295
2296union cvmx_npei_pkt_slist_es {
2297 uint64_t u64;
2298 struct cvmx_npei_pkt_slist_es_s {
2299 uint64_t es:64;
2300 } s;
2301 struct cvmx_npei_pkt_slist_es_s cn52xx;
2302 struct cvmx_npei_pkt_slist_es_s cn56xx;
2303 struct cvmx_npei_pkt_slist_es_s cn56xxp1;
2304};
2305
2306union cvmx_npei_pkt_slist_id_size {
2307 uint64_t u64;
2308 struct cvmx_npei_pkt_slist_id_size_s {
2309 uint64_t reserved_23_63:41;
2310 uint64_t isize:7;
2311 uint64_t bsize:16;
2312 } s;
2313 struct cvmx_npei_pkt_slist_id_size_s cn52xx;
2314 struct cvmx_npei_pkt_slist_id_size_s cn56xx;
2315 struct cvmx_npei_pkt_slist_id_size_s cn56xxp1;
2316};
2317
2318union cvmx_npei_pkt_slist_ns {
2319 uint64_t u64;
2320 struct cvmx_npei_pkt_slist_ns_s {
2321 uint64_t reserved_32_63:32;
2322 uint64_t nsr:32;
2323 } s;
2324 struct cvmx_npei_pkt_slist_ns_s cn52xx;
2325 struct cvmx_npei_pkt_slist_ns_s cn56xx;
2326 struct cvmx_npei_pkt_slist_ns_s cn56xxp1;
2327};
2328
2329union cvmx_npei_pkt_slist_ror {
2330 uint64_t u64;
2331 struct cvmx_npei_pkt_slist_ror_s {
2332 uint64_t reserved_32_63:32;
2333 uint64_t ror:32;
2334 } s;
2335 struct cvmx_npei_pkt_slist_ror_s cn52xx;
2336 struct cvmx_npei_pkt_slist_ror_s cn56xx;
2337 struct cvmx_npei_pkt_slist_ror_s cn56xxp1;
2338};
2339
2340union cvmx_npei_pkt_time_int {
2341 uint64_t u64;
2342 struct cvmx_npei_pkt_time_int_s {
2343 uint64_t reserved_32_63:32;
2344 uint64_t port:32;
2345 } s;
2346 struct cvmx_npei_pkt_time_int_s cn52xx;
2347 struct cvmx_npei_pkt_time_int_s cn56xx;
2348 struct cvmx_npei_pkt_time_int_s cn56xxp1;
2349};
2350
2351union cvmx_npei_pkt_time_int_enb {
2352 uint64_t u64;
2353 struct cvmx_npei_pkt_time_int_enb_s {
2354 uint64_t reserved_32_63:32;
2355 uint64_t port:32;
2356 } s;
2357 struct cvmx_npei_pkt_time_int_enb_s cn52xx;
2358 struct cvmx_npei_pkt_time_int_enb_s cn56xx;
2359 struct cvmx_npei_pkt_time_int_enb_s cn56xxp1;
2360};
2361
2362union cvmx_npei_rsl_int_blocks {
2363 uint64_t u64;
2364 struct cvmx_npei_rsl_int_blocks_s {
2365 uint64_t reserved_31_63:33;
2366 uint64_t iob:1;
2367 uint64_t lmc1:1;
2368 uint64_t agl:1;
2369 uint64_t reserved_24_27:4;
2370 uint64_t asxpcs1:1;
2371 uint64_t asxpcs0:1;
2372 uint64_t reserved_21_21:1;
2373 uint64_t pip:1;
2374 uint64_t reserved_18_19:2;
2375 uint64_t lmc0:1;
2376 uint64_t l2c:1;
2377 uint64_t usb1:1;
2378 uint64_t rad:1;
2379 uint64_t usb:1;
2380 uint64_t pow:1;
2381 uint64_t tim:1;
2382 uint64_t pko:1;
2383 uint64_t ipd:1;
2384 uint64_t reserved_8_8:1;
2385 uint64_t zip:1;
2386 uint64_t reserved_6_6:1;
2387 uint64_t fpa:1;
2388 uint64_t key:1;
2389 uint64_t npei:1;
2390 uint64_t gmx1:1;
2391 uint64_t gmx0:1;
2392 uint64_t mio:1;
2393 } s;
2394 struct cvmx_npei_rsl_int_blocks_s cn52xx;
2395 struct cvmx_npei_rsl_int_blocks_s cn52xxp1;
2396 struct cvmx_npei_rsl_int_blocks_cn56xx {
2397 uint64_t reserved_31_63:33;
2398 uint64_t iob:1;
2399 uint64_t lmc1:1;
2400 uint64_t agl:1;
2401 uint64_t reserved_24_27:4;
2402 uint64_t asxpcs1:1;
2403 uint64_t asxpcs0:1;
2404 uint64_t reserved_21_21:1;
2405 uint64_t pip:1;
2406 uint64_t reserved_18_19:2;
2407 uint64_t lmc0:1;
2408 uint64_t l2c:1;
2409 uint64_t reserved_15_15:1;
2410 uint64_t rad:1;
2411 uint64_t usb:1;
2412 uint64_t pow:1;
2413 uint64_t tim:1;
2414 uint64_t pko:1;
2415 uint64_t ipd:1;
2416 uint64_t reserved_8_8:1;
2417 uint64_t zip:1;
2418 uint64_t reserved_6_6:1;
2419 uint64_t fpa:1;
2420 uint64_t key:1;
2421 uint64_t npei:1;
2422 uint64_t gmx1:1;
2423 uint64_t gmx0:1;
2424 uint64_t mio:1;
2425 } cn56xx;
2426 struct cvmx_npei_rsl_int_blocks_cn56xx cn56xxp1;
2427};
2428
2429union cvmx_npei_scratch_1 {
2430 uint64_t u64;
2431 struct cvmx_npei_scratch_1_s {
2432 uint64_t data:64;
2433 } s;
2434 struct cvmx_npei_scratch_1_s cn52xx;
2435 struct cvmx_npei_scratch_1_s cn52xxp1;
2436 struct cvmx_npei_scratch_1_s cn56xx;
2437 struct cvmx_npei_scratch_1_s cn56xxp1;
2438};
2439
2440union cvmx_npei_state1 {
2441 uint64_t u64;
2442 struct cvmx_npei_state1_s {
2443 uint64_t cpl1:12;
2444 uint64_t cpl0:12;
2445 uint64_t arb:1;
2446 uint64_t csr:39;
2447 } s;
2448 struct cvmx_npei_state1_s cn52xx;
2449 struct cvmx_npei_state1_s cn52xxp1;
2450 struct cvmx_npei_state1_s cn56xx;
2451 struct cvmx_npei_state1_s cn56xxp1;
2452};
2453
2454union cvmx_npei_state2 {
2455 uint64_t u64;
2456 struct cvmx_npei_state2_s {
2457 uint64_t reserved_48_63:16;
2458 uint64_t npei:1;
2459 uint64_t rac:1;
2460 uint64_t csm1:15;
2461 uint64_t csm0:15;
2462 uint64_t nnp0:8;
2463 uint64_t nnd:8;
2464 } s;
2465 struct cvmx_npei_state2_s cn52xx;
2466 struct cvmx_npei_state2_s cn52xxp1;
2467 struct cvmx_npei_state2_s cn56xx;
2468 struct cvmx_npei_state2_s cn56xxp1;
2469};
2470
2471union cvmx_npei_state3 {
2472 uint64_t u64;
2473 struct cvmx_npei_state3_s {
2474 uint64_t reserved_56_63:8;
2475 uint64_t psm1:15;
2476 uint64_t psm0:15;
2477 uint64_t nsm1:13;
2478 uint64_t nsm0:13;
2479 } s;
2480 struct cvmx_npei_state3_s cn52xx;
2481 struct cvmx_npei_state3_s cn52xxp1;
2482 struct cvmx_npei_state3_s cn56xx;
2483 struct cvmx_npei_state3_s cn56xxp1;
2484};
2485
2486union cvmx_npei_win_rd_addr {
2487 uint64_t u64;
2488 struct cvmx_npei_win_rd_addr_s {
2489 uint64_t reserved_51_63:13;
2490 uint64_t ld_cmd:2;
2491 uint64_t iobit:1;
2492 uint64_t rd_addr:48;
2493 } s;
2494 struct cvmx_npei_win_rd_addr_s cn52xx;
2495 struct cvmx_npei_win_rd_addr_s cn52xxp1;
2496 struct cvmx_npei_win_rd_addr_s cn56xx;
2497 struct cvmx_npei_win_rd_addr_s cn56xxp1;
2498};
2499
2500union cvmx_npei_win_rd_data {
2501 uint64_t u64;
2502 struct cvmx_npei_win_rd_data_s {
2503 uint64_t rd_data:64;
2504 } s;
2505 struct cvmx_npei_win_rd_data_s cn52xx;
2506 struct cvmx_npei_win_rd_data_s cn52xxp1;
2507 struct cvmx_npei_win_rd_data_s cn56xx;
2508 struct cvmx_npei_win_rd_data_s cn56xxp1;
2509};
2510
2511union cvmx_npei_win_wr_addr {
2512 uint64_t u64;
2513 struct cvmx_npei_win_wr_addr_s {
2514 uint64_t reserved_49_63:15;
2515 uint64_t iobit:1;
2516 uint64_t wr_addr:46;
2517 uint64_t reserved_0_1:2;
2518 } s;
2519 struct cvmx_npei_win_wr_addr_s cn52xx;
2520 struct cvmx_npei_win_wr_addr_s cn52xxp1;
2521 struct cvmx_npei_win_wr_addr_s cn56xx;
2522 struct cvmx_npei_win_wr_addr_s cn56xxp1;
2523};
2524
2525union cvmx_npei_win_wr_data {
2526 uint64_t u64;
2527 struct cvmx_npei_win_wr_data_s {
2528 uint64_t wr_data:64;
2529 } s;
2530 struct cvmx_npei_win_wr_data_s cn52xx;
2531 struct cvmx_npei_win_wr_data_s cn52xxp1;
2532 struct cvmx_npei_win_wr_data_s cn56xx;
2533 struct cvmx_npei_win_wr_data_s cn56xxp1;
2534};
2535
2536union cvmx_npei_win_wr_mask {
2537 uint64_t u64;
2538 struct cvmx_npei_win_wr_mask_s {
2539 uint64_t reserved_8_63:56;
2540 uint64_t wr_mask:8;
2541 } s;
2542 struct cvmx_npei_win_wr_mask_s cn52xx;
2543 struct cvmx_npei_win_wr_mask_s cn52xxp1;
2544 struct cvmx_npei_win_wr_mask_s cn56xx;
2545 struct cvmx_npei_win_wr_mask_s cn56xxp1;
2546};
2547
2548union cvmx_npei_window_ctl {
2549 uint64_t u64;
2550 struct cvmx_npei_window_ctl_s {
2551 uint64_t reserved_32_63:32;
2552 uint64_t time:32;
2553 } s;
2554 struct cvmx_npei_window_ctl_s cn52xx;
2555 struct cvmx_npei_window_ctl_s cn52xxp1;
2556 struct cvmx_npei_window_ctl_s cn56xx;
2557 struct cvmx_npei_window_ctl_s cn56xxp1;
2558};
2559
2560#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-npi-defs.h b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
new file mode 100644
index 000000000000..4e03cd8561e3
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-npi-defs.h
@@ -0,0 +1,1735 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_NPI_DEFS_H__
29#define __CVMX_NPI_DEFS_H__
30
31#define CVMX_NPI_BASE_ADDR_INPUT0 \
32 CVMX_ADD_IO_SEG(0x00011F0000000070ull)
33#define CVMX_NPI_BASE_ADDR_INPUT1 \
34 CVMX_ADD_IO_SEG(0x00011F0000000080ull)
35#define CVMX_NPI_BASE_ADDR_INPUT2 \
36 CVMX_ADD_IO_SEG(0x00011F0000000090ull)
37#define CVMX_NPI_BASE_ADDR_INPUT3 \
38 CVMX_ADD_IO_SEG(0x00011F00000000A0ull)
39#define CVMX_NPI_BASE_ADDR_INPUTX(offset) \
40 CVMX_ADD_IO_SEG(0x00011F0000000070ull + (((offset) & 3) * 16))
41#define CVMX_NPI_BASE_ADDR_OUTPUT0 \
42 CVMX_ADD_IO_SEG(0x00011F00000000B8ull)
43#define CVMX_NPI_BASE_ADDR_OUTPUT1 \
44 CVMX_ADD_IO_SEG(0x00011F00000000C0ull)
45#define CVMX_NPI_BASE_ADDR_OUTPUT2 \
46 CVMX_ADD_IO_SEG(0x00011F00000000C8ull)
47#define CVMX_NPI_BASE_ADDR_OUTPUT3 \
48 CVMX_ADD_IO_SEG(0x00011F00000000D0ull)
49#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) \
50 CVMX_ADD_IO_SEG(0x00011F00000000B8ull + (((offset) & 3) * 8))
51#define CVMX_NPI_BIST_STATUS \
52 CVMX_ADD_IO_SEG(0x00011F00000003F8ull)
53#define CVMX_NPI_BUFF_SIZE_OUTPUT0 \
54 CVMX_ADD_IO_SEG(0x00011F00000000E0ull)
55#define CVMX_NPI_BUFF_SIZE_OUTPUT1 \
56 CVMX_ADD_IO_SEG(0x00011F00000000E8ull)
57#define CVMX_NPI_BUFF_SIZE_OUTPUT2 \
58 CVMX_ADD_IO_SEG(0x00011F00000000F0ull)
59#define CVMX_NPI_BUFF_SIZE_OUTPUT3 \
60 CVMX_ADD_IO_SEG(0x00011F00000000F8ull)
61#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) \
62 CVMX_ADD_IO_SEG(0x00011F00000000E0ull + (((offset) & 3) * 8))
63#define CVMX_NPI_COMP_CTL \
64 CVMX_ADD_IO_SEG(0x00011F0000000218ull)
65#define CVMX_NPI_CTL_STATUS \
66 CVMX_ADD_IO_SEG(0x00011F0000000010ull)
67#define CVMX_NPI_DBG_SELECT \
68 CVMX_ADD_IO_SEG(0x00011F0000000008ull)
69#define CVMX_NPI_DMA_CONTROL \
70 CVMX_ADD_IO_SEG(0x00011F0000000128ull)
71#define CVMX_NPI_DMA_HIGHP_COUNTS \
72 CVMX_ADD_IO_SEG(0x00011F0000000148ull)
73#define CVMX_NPI_DMA_HIGHP_NADDR \
74 CVMX_ADD_IO_SEG(0x00011F0000000158ull)
75#define CVMX_NPI_DMA_LOWP_COUNTS \
76 CVMX_ADD_IO_SEG(0x00011F0000000140ull)
77#define CVMX_NPI_DMA_LOWP_NADDR \
78 CVMX_ADD_IO_SEG(0x00011F0000000150ull)
79#define CVMX_NPI_HIGHP_DBELL \
80 CVMX_ADD_IO_SEG(0x00011F0000000120ull)
81#define CVMX_NPI_HIGHP_IBUFF_SADDR \
82 CVMX_ADD_IO_SEG(0x00011F0000000110ull)
83#define CVMX_NPI_INPUT_CONTROL \
84 CVMX_ADD_IO_SEG(0x00011F0000000138ull)
85#define CVMX_NPI_INT_ENB \
86 CVMX_ADD_IO_SEG(0x00011F0000000020ull)
87#define CVMX_NPI_INT_SUM \
88 CVMX_ADD_IO_SEG(0x00011F0000000018ull)
89#define CVMX_NPI_LOWP_DBELL \
90 CVMX_ADD_IO_SEG(0x00011F0000000118ull)
91#define CVMX_NPI_LOWP_IBUFF_SADDR \
92 CVMX_ADD_IO_SEG(0x00011F0000000108ull)
93#define CVMX_NPI_MEM_ACCESS_SUBID3 \
94 CVMX_ADD_IO_SEG(0x00011F0000000028ull)
95#define CVMX_NPI_MEM_ACCESS_SUBID4 \
96 CVMX_ADD_IO_SEG(0x00011F0000000030ull)
97#define CVMX_NPI_MEM_ACCESS_SUBID5 \
98 CVMX_ADD_IO_SEG(0x00011F0000000038ull)
99#define CVMX_NPI_MEM_ACCESS_SUBID6 \
100 CVMX_ADD_IO_SEG(0x00011F0000000040ull)
101#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) \
102 CVMX_ADD_IO_SEG(0x00011F0000000028ull + (((offset) & 7) * 8) - 8 * 3)
103#define CVMX_NPI_MSI_RCV \
104 (0x0000000000000190ull)
105#define CVMX_NPI_NPI_MSI_RCV \
106 CVMX_ADD_IO_SEG(0x00011F0000001190ull)
107#define CVMX_NPI_NUM_DESC_OUTPUT0 \
108 CVMX_ADD_IO_SEG(0x00011F0000000050ull)
109#define CVMX_NPI_NUM_DESC_OUTPUT1 \
110 CVMX_ADD_IO_SEG(0x00011F0000000058ull)
111#define CVMX_NPI_NUM_DESC_OUTPUT2 \
112 CVMX_ADD_IO_SEG(0x00011F0000000060ull)
113#define CVMX_NPI_NUM_DESC_OUTPUT3 \
114 CVMX_ADD_IO_SEG(0x00011F0000000068ull)
115#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) \
116 CVMX_ADD_IO_SEG(0x00011F0000000050ull + (((offset) & 3) * 8))
117#define CVMX_NPI_OUTPUT_CONTROL \
118 CVMX_ADD_IO_SEG(0x00011F0000000100ull)
119#define CVMX_NPI_P0_DBPAIR_ADDR \
120 CVMX_ADD_IO_SEG(0x00011F0000000180ull)
121#define CVMX_NPI_P0_INSTR_ADDR \
122 CVMX_ADD_IO_SEG(0x00011F00000001C0ull)
123#define CVMX_NPI_P0_INSTR_CNTS \
124 CVMX_ADD_IO_SEG(0x00011F00000001A0ull)
125#define CVMX_NPI_P0_PAIR_CNTS \
126 CVMX_ADD_IO_SEG(0x00011F0000000160ull)
127#define CVMX_NPI_P1_DBPAIR_ADDR \
128 CVMX_ADD_IO_SEG(0x00011F0000000188ull)
129#define CVMX_NPI_P1_INSTR_ADDR \
130 CVMX_ADD_IO_SEG(0x00011F00000001C8ull)
131#define CVMX_NPI_P1_INSTR_CNTS \
132 CVMX_ADD_IO_SEG(0x00011F00000001A8ull)
133#define CVMX_NPI_P1_PAIR_CNTS \
134 CVMX_ADD_IO_SEG(0x00011F0000000168ull)
135#define CVMX_NPI_P2_DBPAIR_ADDR \
136 CVMX_ADD_IO_SEG(0x00011F0000000190ull)
137#define CVMX_NPI_P2_INSTR_ADDR \
138 CVMX_ADD_IO_SEG(0x00011F00000001D0ull)
139#define CVMX_NPI_P2_INSTR_CNTS \
140 CVMX_ADD_IO_SEG(0x00011F00000001B0ull)
141#define CVMX_NPI_P2_PAIR_CNTS \
142 CVMX_ADD_IO_SEG(0x00011F0000000170ull)
143#define CVMX_NPI_P3_DBPAIR_ADDR \
144 CVMX_ADD_IO_SEG(0x00011F0000000198ull)
145#define CVMX_NPI_P3_INSTR_ADDR \
146 CVMX_ADD_IO_SEG(0x00011F00000001D8ull)
147#define CVMX_NPI_P3_INSTR_CNTS \
148 CVMX_ADD_IO_SEG(0x00011F00000001B8ull)
149#define CVMX_NPI_P3_PAIR_CNTS \
150 CVMX_ADD_IO_SEG(0x00011F0000000178ull)
151#define CVMX_NPI_PCI_BAR1_INDEXX(offset) \
152 CVMX_ADD_IO_SEG(0x00011F0000001100ull + (((offset) & 31) * 4))
153#define CVMX_NPI_PCI_BIST_REG \
154 CVMX_ADD_IO_SEG(0x00011F00000011C0ull)
155#define CVMX_NPI_PCI_BURST_SIZE \
156 CVMX_ADD_IO_SEG(0x00011F00000000D8ull)
157#define CVMX_NPI_PCI_CFG00 \
158 CVMX_ADD_IO_SEG(0x00011F0000001800ull)
159#define CVMX_NPI_PCI_CFG01 \
160 CVMX_ADD_IO_SEG(0x00011F0000001804ull)
161#define CVMX_NPI_PCI_CFG02 \
162 CVMX_ADD_IO_SEG(0x00011F0000001808ull)
163#define CVMX_NPI_PCI_CFG03 \
164 CVMX_ADD_IO_SEG(0x00011F000000180Cull)
165#define CVMX_NPI_PCI_CFG04 \
166 CVMX_ADD_IO_SEG(0x00011F0000001810ull)
167#define CVMX_NPI_PCI_CFG05 \
168 CVMX_ADD_IO_SEG(0x00011F0000001814ull)
169#define CVMX_NPI_PCI_CFG06 \
170 CVMX_ADD_IO_SEG(0x00011F0000001818ull)
171#define CVMX_NPI_PCI_CFG07 \
172 CVMX_ADD_IO_SEG(0x00011F000000181Cull)
173#define CVMX_NPI_PCI_CFG08 \
174 CVMX_ADD_IO_SEG(0x00011F0000001820ull)
175#define CVMX_NPI_PCI_CFG09 \
176 CVMX_ADD_IO_SEG(0x00011F0000001824ull)
177#define CVMX_NPI_PCI_CFG10 \
178 CVMX_ADD_IO_SEG(0x00011F0000001828ull)
179#define CVMX_NPI_PCI_CFG11 \
180 CVMX_ADD_IO_SEG(0x00011F000000182Cull)
181#define CVMX_NPI_PCI_CFG12 \
182 CVMX_ADD_IO_SEG(0x00011F0000001830ull)
183#define CVMX_NPI_PCI_CFG13 \
184 CVMX_ADD_IO_SEG(0x00011F0000001834ull)
185#define CVMX_NPI_PCI_CFG15 \
186 CVMX_ADD_IO_SEG(0x00011F000000183Cull)
187#define CVMX_NPI_PCI_CFG16 \
188 CVMX_ADD_IO_SEG(0x00011F0000001840ull)
189#define CVMX_NPI_PCI_CFG17 \
190 CVMX_ADD_IO_SEG(0x00011F0000001844ull)
191#define CVMX_NPI_PCI_CFG18 \
192 CVMX_ADD_IO_SEG(0x00011F0000001848ull)
193#define CVMX_NPI_PCI_CFG19 \
194 CVMX_ADD_IO_SEG(0x00011F000000184Cull)
195#define CVMX_NPI_PCI_CFG20 \
196 CVMX_ADD_IO_SEG(0x00011F0000001850ull)
197#define CVMX_NPI_PCI_CFG21 \
198 CVMX_ADD_IO_SEG(0x00011F0000001854ull)
199#define CVMX_NPI_PCI_CFG22 \
200 CVMX_ADD_IO_SEG(0x00011F0000001858ull)
201#define CVMX_NPI_PCI_CFG56 \
202 CVMX_ADD_IO_SEG(0x00011F00000018E0ull)
203#define CVMX_NPI_PCI_CFG57 \
204 CVMX_ADD_IO_SEG(0x00011F00000018E4ull)
205#define CVMX_NPI_PCI_CFG58 \
206 CVMX_ADD_IO_SEG(0x00011F00000018E8ull)
207#define CVMX_NPI_PCI_CFG59 \
208 CVMX_ADD_IO_SEG(0x00011F00000018ECull)
209#define CVMX_NPI_PCI_CFG60 \
210 CVMX_ADD_IO_SEG(0x00011F00000018F0ull)
211#define CVMX_NPI_PCI_CFG61 \
212 CVMX_ADD_IO_SEG(0x00011F00000018F4ull)
213#define CVMX_NPI_PCI_CFG62 \
214 CVMX_ADD_IO_SEG(0x00011F00000018F8ull)
215#define CVMX_NPI_PCI_CFG63 \
216 CVMX_ADD_IO_SEG(0x00011F00000018FCull)
217#define CVMX_NPI_PCI_CNT_REG \
218 CVMX_ADD_IO_SEG(0x00011F00000011B8ull)
219#define CVMX_NPI_PCI_CTL_STATUS_2 \
220 CVMX_ADD_IO_SEG(0x00011F000000118Cull)
221#define CVMX_NPI_PCI_INT_ARB_CFG \
222 CVMX_ADD_IO_SEG(0x00011F0000000130ull)
223#define CVMX_NPI_PCI_INT_ENB2 \
224 CVMX_ADD_IO_SEG(0x00011F00000011A0ull)
225#define CVMX_NPI_PCI_INT_SUM2 \
226 CVMX_ADD_IO_SEG(0x00011F0000001198ull)
227#define CVMX_NPI_PCI_READ_CMD \
228 CVMX_ADD_IO_SEG(0x00011F0000000048ull)
229#define CVMX_NPI_PCI_READ_CMD_6 \
230 CVMX_ADD_IO_SEG(0x00011F0000001180ull)
231#define CVMX_NPI_PCI_READ_CMD_C \
232 CVMX_ADD_IO_SEG(0x00011F0000001184ull)
233#define CVMX_NPI_PCI_READ_CMD_E \
234 CVMX_ADD_IO_SEG(0x00011F0000001188ull)
235#define CVMX_NPI_PCI_SCM_REG \
236 CVMX_ADD_IO_SEG(0x00011F00000011A8ull)
237#define CVMX_NPI_PCI_TSR_REG \
238 CVMX_ADD_IO_SEG(0x00011F00000011B0ull)
239#define CVMX_NPI_PORT32_INSTR_HDR \
240 CVMX_ADD_IO_SEG(0x00011F00000001F8ull)
241#define CVMX_NPI_PORT33_INSTR_HDR \
242 CVMX_ADD_IO_SEG(0x00011F0000000200ull)
243#define CVMX_NPI_PORT34_INSTR_HDR \
244 CVMX_ADD_IO_SEG(0x00011F0000000208ull)
245#define CVMX_NPI_PORT35_INSTR_HDR \
246 CVMX_ADD_IO_SEG(0x00011F0000000210ull)
247#define CVMX_NPI_PORT_BP_CONTROL \
248 CVMX_ADD_IO_SEG(0x00011F00000001F0ull)
249#define CVMX_NPI_PX_DBPAIR_ADDR(offset) \
250 CVMX_ADD_IO_SEG(0x00011F0000000180ull + (((offset) & 3) * 8))
251#define CVMX_NPI_PX_INSTR_ADDR(offset) \
252 CVMX_ADD_IO_SEG(0x00011F00000001C0ull + (((offset) & 3) * 8))
253#define CVMX_NPI_PX_INSTR_CNTS(offset) \
254 CVMX_ADD_IO_SEG(0x00011F00000001A0ull + (((offset) & 3) * 8))
255#define CVMX_NPI_PX_PAIR_CNTS(offset) \
256 CVMX_ADD_IO_SEG(0x00011F0000000160ull + (((offset) & 3) * 8))
257#define CVMX_NPI_RSL_INT_BLOCKS \
258 CVMX_ADD_IO_SEG(0x00011F0000000000ull)
259#define CVMX_NPI_SIZE_INPUT0 \
260 CVMX_ADD_IO_SEG(0x00011F0000000078ull)
261#define CVMX_NPI_SIZE_INPUT1 \
262 CVMX_ADD_IO_SEG(0x00011F0000000088ull)
263#define CVMX_NPI_SIZE_INPUT2 \
264 CVMX_ADD_IO_SEG(0x00011F0000000098ull)
265#define CVMX_NPI_SIZE_INPUT3 \
266 CVMX_ADD_IO_SEG(0x00011F00000000A8ull)
267#define CVMX_NPI_SIZE_INPUTX(offset) \
268 CVMX_ADD_IO_SEG(0x00011F0000000078ull + (((offset) & 3) * 16))
269#define CVMX_NPI_WIN_READ_TO \
270 CVMX_ADD_IO_SEG(0x00011F00000001E0ull)
271
272union cvmx_npi_base_addr_inputx {
273 uint64_t u64;
274 struct cvmx_npi_base_addr_inputx_s {
275 uint64_t baddr:61;
276 uint64_t reserved_0_2:3;
277 } s;
278 struct cvmx_npi_base_addr_inputx_s cn30xx;
279 struct cvmx_npi_base_addr_inputx_s cn31xx;
280 struct cvmx_npi_base_addr_inputx_s cn38xx;
281 struct cvmx_npi_base_addr_inputx_s cn38xxp2;
282 struct cvmx_npi_base_addr_inputx_s cn50xx;
283 struct cvmx_npi_base_addr_inputx_s cn58xx;
284 struct cvmx_npi_base_addr_inputx_s cn58xxp1;
285};
286
287union cvmx_npi_base_addr_outputx {
288 uint64_t u64;
289 struct cvmx_npi_base_addr_outputx_s {
290 uint64_t baddr:61;
291 uint64_t reserved_0_2:3;
292 } s;
293 struct cvmx_npi_base_addr_outputx_s cn30xx;
294 struct cvmx_npi_base_addr_outputx_s cn31xx;
295 struct cvmx_npi_base_addr_outputx_s cn38xx;
296 struct cvmx_npi_base_addr_outputx_s cn38xxp2;
297 struct cvmx_npi_base_addr_outputx_s cn50xx;
298 struct cvmx_npi_base_addr_outputx_s cn58xx;
299 struct cvmx_npi_base_addr_outputx_s cn58xxp1;
300};
301
302union cvmx_npi_bist_status {
303 uint64_t u64;
304 struct cvmx_npi_bist_status_s {
305 uint64_t reserved_20_63:44;
306 uint64_t csr_bs:1;
307 uint64_t dif_bs:1;
308 uint64_t rdp_bs:1;
309 uint64_t pcnc_bs:1;
310 uint64_t pcn_bs:1;
311 uint64_t rdn_bs:1;
312 uint64_t pcac_bs:1;
313 uint64_t pcad_bs:1;
314 uint64_t rdnl_bs:1;
315 uint64_t pgf_bs:1;
316 uint64_t pig_bs:1;
317 uint64_t pof0_bs:1;
318 uint64_t pof1_bs:1;
319 uint64_t pof2_bs:1;
320 uint64_t pof3_bs:1;
321 uint64_t pos_bs:1;
322 uint64_t nus_bs:1;
323 uint64_t dob_bs:1;
324 uint64_t pdf_bs:1;
325 uint64_t dpi_bs:1;
326 } s;
327 struct cvmx_npi_bist_status_cn30xx {
328 uint64_t reserved_20_63:44;
329 uint64_t csr_bs:1;
330 uint64_t dif_bs:1;
331 uint64_t rdp_bs:1;
332 uint64_t pcnc_bs:1;
333 uint64_t pcn_bs:1;
334 uint64_t rdn_bs:1;
335 uint64_t pcac_bs:1;
336 uint64_t pcad_bs:1;
337 uint64_t rdnl_bs:1;
338 uint64_t pgf_bs:1;
339 uint64_t pig_bs:1;
340 uint64_t pof0_bs:1;
341 uint64_t reserved_5_7:3;
342 uint64_t pos_bs:1;
343 uint64_t nus_bs:1;
344 uint64_t dob_bs:1;
345 uint64_t pdf_bs:1;
346 uint64_t dpi_bs:1;
347 } cn30xx;
348 struct cvmx_npi_bist_status_s cn31xx;
349 struct cvmx_npi_bist_status_s cn38xx;
350 struct cvmx_npi_bist_status_s cn38xxp2;
351 struct cvmx_npi_bist_status_cn50xx {
352 uint64_t reserved_20_63:44;
353 uint64_t csr_bs:1;
354 uint64_t dif_bs:1;
355 uint64_t rdp_bs:1;
356 uint64_t pcnc_bs:1;
357 uint64_t pcn_bs:1;
358 uint64_t rdn_bs:1;
359 uint64_t pcac_bs:1;
360 uint64_t pcad_bs:1;
361 uint64_t rdnl_bs:1;
362 uint64_t pgf_bs:1;
363 uint64_t pig_bs:1;
364 uint64_t pof0_bs:1;
365 uint64_t pof1_bs:1;
366 uint64_t reserved_5_6:2;
367 uint64_t pos_bs:1;
368 uint64_t nus_bs:1;
369 uint64_t dob_bs:1;
370 uint64_t pdf_bs:1;
371 uint64_t dpi_bs:1;
372 } cn50xx;
373 struct cvmx_npi_bist_status_s cn58xx;
374 struct cvmx_npi_bist_status_s cn58xxp1;
375};
376
377union cvmx_npi_buff_size_outputx {
378 uint64_t u64;
379 struct cvmx_npi_buff_size_outputx_s {
380 uint64_t reserved_23_63:41;
381 uint64_t isize:7;
382 uint64_t bsize:16;
383 } s;
384 struct cvmx_npi_buff_size_outputx_s cn30xx;
385 struct cvmx_npi_buff_size_outputx_s cn31xx;
386 struct cvmx_npi_buff_size_outputx_s cn38xx;
387 struct cvmx_npi_buff_size_outputx_s cn38xxp2;
388 struct cvmx_npi_buff_size_outputx_s cn50xx;
389 struct cvmx_npi_buff_size_outputx_s cn58xx;
390 struct cvmx_npi_buff_size_outputx_s cn58xxp1;
391};
392
393union cvmx_npi_comp_ctl {
394 uint64_t u64;
395 struct cvmx_npi_comp_ctl_s {
396 uint64_t reserved_10_63:54;
397 uint64_t pctl:5;
398 uint64_t nctl:5;
399 } s;
400 struct cvmx_npi_comp_ctl_s cn50xx;
401 struct cvmx_npi_comp_ctl_s cn58xx;
402 struct cvmx_npi_comp_ctl_s cn58xxp1;
403};
404
405union cvmx_npi_ctl_status {
406 uint64_t u64;
407 struct cvmx_npi_ctl_status_s {
408 uint64_t reserved_63_63:1;
409 uint64_t chip_rev:8;
410 uint64_t dis_pniw:1;
411 uint64_t out3_enb:1;
412 uint64_t out2_enb:1;
413 uint64_t out1_enb:1;
414 uint64_t out0_enb:1;
415 uint64_t ins3_enb:1;
416 uint64_t ins2_enb:1;
417 uint64_t ins1_enb:1;
418 uint64_t ins0_enb:1;
419 uint64_t ins3_64b:1;
420 uint64_t ins2_64b:1;
421 uint64_t ins1_64b:1;
422 uint64_t ins0_64b:1;
423 uint64_t pci_wdis:1;
424 uint64_t wait_com:1;
425 uint64_t reserved_37_39:3;
426 uint64_t max_word:5;
427 uint64_t reserved_10_31:22;
428 uint64_t timer:10;
429 } s;
430 struct cvmx_npi_ctl_status_cn30xx {
431 uint64_t reserved_63_63:1;
432 uint64_t chip_rev:8;
433 uint64_t dis_pniw:1;
434 uint64_t reserved_51_53:3;
435 uint64_t out0_enb:1;
436 uint64_t reserved_47_49:3;
437 uint64_t ins0_enb:1;
438 uint64_t reserved_43_45:3;
439 uint64_t ins0_64b:1;
440 uint64_t pci_wdis:1;
441 uint64_t wait_com:1;
442 uint64_t reserved_37_39:3;
443 uint64_t max_word:5;
444 uint64_t reserved_10_31:22;
445 uint64_t timer:10;
446 } cn30xx;
447 struct cvmx_npi_ctl_status_cn31xx {
448 uint64_t reserved_63_63:1;
449 uint64_t chip_rev:8;
450 uint64_t dis_pniw:1;
451 uint64_t reserved_52_53:2;
452 uint64_t out1_enb:1;
453 uint64_t out0_enb:1;
454 uint64_t reserved_48_49:2;
455 uint64_t ins1_enb:1;
456 uint64_t ins0_enb:1;
457 uint64_t reserved_44_45:2;
458 uint64_t ins1_64b:1;
459 uint64_t ins0_64b:1;
460 uint64_t pci_wdis:1;
461 uint64_t wait_com:1;
462 uint64_t reserved_37_39:3;
463 uint64_t max_word:5;
464 uint64_t reserved_10_31:22;
465 uint64_t timer:10;
466 } cn31xx;
467 struct cvmx_npi_ctl_status_s cn38xx;
468 struct cvmx_npi_ctl_status_s cn38xxp2;
469 struct cvmx_npi_ctl_status_cn31xx cn50xx;
470 struct cvmx_npi_ctl_status_s cn58xx;
471 struct cvmx_npi_ctl_status_s cn58xxp1;
472};
473
474union cvmx_npi_dbg_select {
475 uint64_t u64;
476 struct cvmx_npi_dbg_select_s {
477 uint64_t reserved_16_63:48;
478 uint64_t dbg_sel:16;
479 } s;
480 struct cvmx_npi_dbg_select_s cn30xx;
481 struct cvmx_npi_dbg_select_s cn31xx;
482 struct cvmx_npi_dbg_select_s cn38xx;
483 struct cvmx_npi_dbg_select_s cn38xxp2;
484 struct cvmx_npi_dbg_select_s cn50xx;
485 struct cvmx_npi_dbg_select_s cn58xx;
486 struct cvmx_npi_dbg_select_s cn58xxp1;
487};
488
489union cvmx_npi_dma_control {
490 uint64_t u64;
491 struct cvmx_npi_dma_control_s {
492 uint64_t reserved_36_63:28;
493 uint64_t b0_lend:1;
494 uint64_t dwb_denb:1;
495 uint64_t dwb_ichk:9;
496 uint64_t fpa_que:3;
497 uint64_t o_add1:1;
498 uint64_t o_ro:1;
499 uint64_t o_ns:1;
500 uint64_t o_es:2;
501 uint64_t o_mode:1;
502 uint64_t hp_enb:1;
503 uint64_t lp_enb:1;
504 uint64_t csize:14;
505 } s;
506 struct cvmx_npi_dma_control_s cn30xx;
507 struct cvmx_npi_dma_control_s cn31xx;
508 struct cvmx_npi_dma_control_s cn38xx;
509 struct cvmx_npi_dma_control_s cn38xxp2;
510 struct cvmx_npi_dma_control_s cn50xx;
511 struct cvmx_npi_dma_control_s cn58xx;
512 struct cvmx_npi_dma_control_s cn58xxp1;
513};
514
515union cvmx_npi_dma_highp_counts {
516 uint64_t u64;
517 struct cvmx_npi_dma_highp_counts_s {
518 uint64_t reserved_39_63:25;
519 uint64_t fcnt:7;
520 uint64_t dbell:32;
521 } s;
522 struct cvmx_npi_dma_highp_counts_s cn30xx;
523 struct cvmx_npi_dma_highp_counts_s cn31xx;
524 struct cvmx_npi_dma_highp_counts_s cn38xx;
525 struct cvmx_npi_dma_highp_counts_s cn38xxp2;
526 struct cvmx_npi_dma_highp_counts_s cn50xx;
527 struct cvmx_npi_dma_highp_counts_s cn58xx;
528 struct cvmx_npi_dma_highp_counts_s cn58xxp1;
529};
530
531union cvmx_npi_dma_highp_naddr {
532 uint64_t u64;
533 struct cvmx_npi_dma_highp_naddr_s {
534 uint64_t reserved_40_63:24;
535 uint64_t state:4;
536 uint64_t addr:36;
537 } s;
538 struct cvmx_npi_dma_highp_naddr_s cn30xx;
539 struct cvmx_npi_dma_highp_naddr_s cn31xx;
540 struct cvmx_npi_dma_highp_naddr_s cn38xx;
541 struct cvmx_npi_dma_highp_naddr_s cn38xxp2;
542 struct cvmx_npi_dma_highp_naddr_s cn50xx;
543 struct cvmx_npi_dma_highp_naddr_s cn58xx;
544 struct cvmx_npi_dma_highp_naddr_s cn58xxp1;
545};
546
547union cvmx_npi_dma_lowp_counts {
548 uint64_t u64;
549 struct cvmx_npi_dma_lowp_counts_s {
550 uint64_t reserved_39_63:25;
551 uint64_t fcnt:7;
552 uint64_t dbell:32;
553 } s;
554 struct cvmx_npi_dma_lowp_counts_s cn30xx;
555 struct cvmx_npi_dma_lowp_counts_s cn31xx;
556 struct cvmx_npi_dma_lowp_counts_s cn38xx;
557 struct cvmx_npi_dma_lowp_counts_s cn38xxp2;
558 struct cvmx_npi_dma_lowp_counts_s cn50xx;
559 struct cvmx_npi_dma_lowp_counts_s cn58xx;
560 struct cvmx_npi_dma_lowp_counts_s cn58xxp1;
561};
562
563union cvmx_npi_dma_lowp_naddr {
564 uint64_t u64;
565 struct cvmx_npi_dma_lowp_naddr_s {
566 uint64_t reserved_40_63:24;
567 uint64_t state:4;
568 uint64_t addr:36;
569 } s;
570 struct cvmx_npi_dma_lowp_naddr_s cn30xx;
571 struct cvmx_npi_dma_lowp_naddr_s cn31xx;
572 struct cvmx_npi_dma_lowp_naddr_s cn38xx;
573 struct cvmx_npi_dma_lowp_naddr_s cn38xxp2;
574 struct cvmx_npi_dma_lowp_naddr_s cn50xx;
575 struct cvmx_npi_dma_lowp_naddr_s cn58xx;
576 struct cvmx_npi_dma_lowp_naddr_s cn58xxp1;
577};
578
579union cvmx_npi_highp_dbell {
580 uint64_t u64;
581 struct cvmx_npi_highp_dbell_s {
582 uint64_t reserved_16_63:48;
583 uint64_t dbell:16;
584 } s;
585 struct cvmx_npi_highp_dbell_s cn30xx;
586 struct cvmx_npi_highp_dbell_s cn31xx;
587 struct cvmx_npi_highp_dbell_s cn38xx;
588 struct cvmx_npi_highp_dbell_s cn38xxp2;
589 struct cvmx_npi_highp_dbell_s cn50xx;
590 struct cvmx_npi_highp_dbell_s cn58xx;
591 struct cvmx_npi_highp_dbell_s cn58xxp1;
592};
593
594union cvmx_npi_highp_ibuff_saddr {
595 uint64_t u64;
596 struct cvmx_npi_highp_ibuff_saddr_s {
597 uint64_t reserved_36_63:28;
598 uint64_t saddr:36;
599 } s;
600 struct cvmx_npi_highp_ibuff_saddr_s cn30xx;
601 struct cvmx_npi_highp_ibuff_saddr_s cn31xx;
602 struct cvmx_npi_highp_ibuff_saddr_s cn38xx;
603 struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2;
604 struct cvmx_npi_highp_ibuff_saddr_s cn50xx;
605 struct cvmx_npi_highp_ibuff_saddr_s cn58xx;
606 struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1;
607};
608
609union cvmx_npi_input_control {
610 uint64_t u64;
611 struct cvmx_npi_input_control_s {
612 uint64_t reserved_23_63:41;
613 uint64_t pkt_rr:1;
614 uint64_t pbp_dhi:13;
615 uint64_t d_nsr:1;
616 uint64_t d_esr:2;
617 uint64_t d_ror:1;
618 uint64_t use_csr:1;
619 uint64_t nsr:1;
620 uint64_t esr:2;
621 uint64_t ror:1;
622 } s;
623 struct cvmx_npi_input_control_cn30xx {
624 uint64_t reserved_22_63:42;
625 uint64_t pbp_dhi:13;
626 uint64_t d_nsr:1;
627 uint64_t d_esr:2;
628 uint64_t d_ror:1;
629 uint64_t use_csr:1;
630 uint64_t nsr:1;
631 uint64_t esr:2;
632 uint64_t ror:1;
633 } cn30xx;
634 struct cvmx_npi_input_control_cn30xx cn31xx;
635 struct cvmx_npi_input_control_s cn38xx;
636 struct cvmx_npi_input_control_cn30xx cn38xxp2;
637 struct cvmx_npi_input_control_s cn50xx;
638 struct cvmx_npi_input_control_s cn58xx;
639 struct cvmx_npi_input_control_s cn58xxp1;
640};
641
642union cvmx_npi_int_enb {
643 uint64_t u64;
644 struct cvmx_npi_int_enb_s {
645 uint64_t reserved_62_63:2;
646 uint64_t q1_a_f:1;
647 uint64_t q1_s_e:1;
648 uint64_t pdf_p_f:1;
649 uint64_t pdf_p_e:1;
650 uint64_t pcf_p_f:1;
651 uint64_t pcf_p_e:1;
652 uint64_t rdx_s_e:1;
653 uint64_t rwx_s_e:1;
654 uint64_t pnc_a_f:1;
655 uint64_t pnc_s_e:1;
656 uint64_t com_a_f:1;
657 uint64_t com_s_e:1;
658 uint64_t q3_a_f:1;
659 uint64_t q3_s_e:1;
660 uint64_t q2_a_f:1;
661 uint64_t q2_s_e:1;
662 uint64_t pcr_a_f:1;
663 uint64_t pcr_s_e:1;
664 uint64_t fcr_a_f:1;
665 uint64_t fcr_s_e:1;
666 uint64_t iobdma:1;
667 uint64_t p_dperr:1;
668 uint64_t win_rto:1;
669 uint64_t i3_pperr:1;
670 uint64_t i2_pperr:1;
671 uint64_t i1_pperr:1;
672 uint64_t i0_pperr:1;
673 uint64_t p3_ptout:1;
674 uint64_t p2_ptout:1;
675 uint64_t p1_ptout:1;
676 uint64_t p0_ptout:1;
677 uint64_t p3_pperr:1;
678 uint64_t p2_pperr:1;
679 uint64_t p1_pperr:1;
680 uint64_t p0_pperr:1;
681 uint64_t g3_rtout:1;
682 uint64_t g2_rtout:1;
683 uint64_t g1_rtout:1;
684 uint64_t g0_rtout:1;
685 uint64_t p3_perr:1;
686 uint64_t p2_perr:1;
687 uint64_t p1_perr:1;
688 uint64_t p0_perr:1;
689 uint64_t p3_rtout:1;
690 uint64_t p2_rtout:1;
691 uint64_t p1_rtout:1;
692 uint64_t p0_rtout:1;
693 uint64_t i3_overf:1;
694 uint64_t i2_overf:1;
695 uint64_t i1_overf:1;
696 uint64_t i0_overf:1;
697 uint64_t i3_rtout:1;
698 uint64_t i2_rtout:1;
699 uint64_t i1_rtout:1;
700 uint64_t i0_rtout:1;
701 uint64_t po3_2sml:1;
702 uint64_t po2_2sml:1;
703 uint64_t po1_2sml:1;
704 uint64_t po0_2sml:1;
705 uint64_t pci_rsl:1;
706 uint64_t rml_wto:1;
707 uint64_t rml_rto:1;
708 } s;
709 struct cvmx_npi_int_enb_cn30xx {
710 uint64_t reserved_62_63:2;
711 uint64_t q1_a_f:1;
712 uint64_t q1_s_e:1;
713 uint64_t pdf_p_f:1;
714 uint64_t pdf_p_e:1;
715 uint64_t pcf_p_f:1;
716 uint64_t pcf_p_e:1;
717 uint64_t rdx_s_e:1;
718 uint64_t rwx_s_e:1;
719 uint64_t pnc_a_f:1;
720 uint64_t pnc_s_e:1;
721 uint64_t com_a_f:1;
722 uint64_t com_s_e:1;
723 uint64_t q3_a_f:1;
724 uint64_t q3_s_e:1;
725 uint64_t q2_a_f:1;
726 uint64_t q2_s_e:1;
727 uint64_t pcr_a_f:1;
728 uint64_t pcr_s_e:1;
729 uint64_t fcr_a_f:1;
730 uint64_t fcr_s_e:1;
731 uint64_t iobdma:1;
732 uint64_t p_dperr:1;
733 uint64_t win_rto:1;
734 uint64_t reserved_36_38:3;
735 uint64_t i0_pperr:1;
736 uint64_t reserved_32_34:3;
737 uint64_t p0_ptout:1;
738 uint64_t reserved_28_30:3;
739 uint64_t p0_pperr:1;
740 uint64_t reserved_24_26:3;
741 uint64_t g0_rtout:1;
742 uint64_t reserved_20_22:3;
743 uint64_t p0_perr:1;
744 uint64_t reserved_16_18:3;
745 uint64_t p0_rtout:1;
746 uint64_t reserved_12_14:3;
747 uint64_t i0_overf:1;
748 uint64_t reserved_8_10:3;
749 uint64_t i0_rtout:1;
750 uint64_t reserved_4_6:3;
751 uint64_t po0_2sml:1;
752 uint64_t pci_rsl:1;
753 uint64_t rml_wto:1;
754 uint64_t rml_rto:1;
755 } cn30xx;
756 struct cvmx_npi_int_enb_cn31xx {
757 uint64_t reserved_62_63:2;
758 uint64_t q1_a_f:1;
759 uint64_t q1_s_e:1;
760 uint64_t pdf_p_f:1;
761 uint64_t pdf_p_e:1;
762 uint64_t pcf_p_f:1;
763 uint64_t pcf_p_e:1;
764 uint64_t rdx_s_e:1;
765 uint64_t rwx_s_e:1;
766 uint64_t pnc_a_f:1;
767 uint64_t pnc_s_e:1;
768 uint64_t com_a_f:1;
769 uint64_t com_s_e:1;
770 uint64_t q3_a_f:1;
771 uint64_t q3_s_e:1;
772 uint64_t q2_a_f:1;
773 uint64_t q2_s_e:1;
774 uint64_t pcr_a_f:1;
775 uint64_t pcr_s_e:1;
776 uint64_t fcr_a_f:1;
777 uint64_t fcr_s_e:1;
778 uint64_t iobdma:1;
779 uint64_t p_dperr:1;
780 uint64_t win_rto:1;
781 uint64_t reserved_37_38:2;
782 uint64_t i1_pperr:1;
783 uint64_t i0_pperr:1;
784 uint64_t reserved_33_34:2;
785 uint64_t p1_ptout:1;
786 uint64_t p0_ptout:1;
787 uint64_t reserved_29_30:2;
788 uint64_t p1_pperr:1;
789 uint64_t p0_pperr:1;
790 uint64_t reserved_25_26:2;
791 uint64_t g1_rtout:1;
792 uint64_t g0_rtout:1;
793 uint64_t reserved_21_22:2;
794 uint64_t p1_perr:1;
795 uint64_t p0_perr:1;
796 uint64_t reserved_17_18:2;
797 uint64_t p1_rtout:1;
798 uint64_t p0_rtout:1;
799 uint64_t reserved_13_14:2;
800 uint64_t i1_overf:1;
801 uint64_t i0_overf:1;
802 uint64_t reserved_9_10:2;
803 uint64_t i1_rtout:1;
804 uint64_t i0_rtout:1;
805 uint64_t reserved_5_6:2;
806 uint64_t po1_2sml:1;
807 uint64_t po0_2sml:1;
808 uint64_t pci_rsl:1;
809 uint64_t rml_wto:1;
810 uint64_t rml_rto:1;
811 } cn31xx;
812 struct cvmx_npi_int_enb_s cn38xx;
813 struct cvmx_npi_int_enb_cn38xxp2 {
814 uint64_t reserved_42_63:22;
815 uint64_t iobdma:1;
816 uint64_t p_dperr:1;
817 uint64_t win_rto:1;
818 uint64_t i3_pperr:1;
819 uint64_t i2_pperr:1;
820 uint64_t i1_pperr:1;
821 uint64_t i0_pperr:1;
822 uint64_t p3_ptout:1;
823 uint64_t p2_ptout:1;
824 uint64_t p1_ptout:1;
825 uint64_t p0_ptout:1;
826 uint64_t p3_pperr:1;
827 uint64_t p2_pperr:1;
828 uint64_t p1_pperr:1;
829 uint64_t p0_pperr:1;
830 uint64_t g3_rtout:1;
831 uint64_t g2_rtout:1;
832 uint64_t g1_rtout:1;
833 uint64_t g0_rtout:1;
834 uint64_t p3_perr:1;
835 uint64_t p2_perr:1;
836 uint64_t p1_perr:1;
837 uint64_t p0_perr:1;
838 uint64_t p3_rtout:1;
839 uint64_t p2_rtout:1;
840 uint64_t p1_rtout:1;
841 uint64_t p0_rtout:1;
842 uint64_t i3_overf:1;
843 uint64_t i2_overf:1;
844 uint64_t i1_overf:1;
845 uint64_t i0_overf:1;
846 uint64_t i3_rtout:1;
847 uint64_t i2_rtout:1;
848 uint64_t i1_rtout:1;
849 uint64_t i0_rtout:1;
850 uint64_t po3_2sml:1;
851 uint64_t po2_2sml:1;
852 uint64_t po1_2sml:1;
853 uint64_t po0_2sml:1;
854 uint64_t pci_rsl:1;
855 uint64_t rml_wto:1;
856 uint64_t rml_rto:1;
857 } cn38xxp2;
858 struct cvmx_npi_int_enb_cn31xx cn50xx;
859 struct cvmx_npi_int_enb_s cn58xx;
860 struct cvmx_npi_int_enb_s cn58xxp1;
861};
862
863union cvmx_npi_int_sum {
864 uint64_t u64;
865 struct cvmx_npi_int_sum_s {
866 uint64_t reserved_62_63:2;
867 uint64_t q1_a_f:1;
868 uint64_t q1_s_e:1;
869 uint64_t pdf_p_f:1;
870 uint64_t pdf_p_e:1;
871 uint64_t pcf_p_f:1;
872 uint64_t pcf_p_e:1;
873 uint64_t rdx_s_e:1;
874 uint64_t rwx_s_e:1;
875 uint64_t pnc_a_f:1;
876 uint64_t pnc_s_e:1;
877 uint64_t com_a_f:1;
878 uint64_t com_s_e:1;
879 uint64_t q3_a_f:1;
880 uint64_t q3_s_e:1;
881 uint64_t q2_a_f:1;
882 uint64_t q2_s_e:1;
883 uint64_t pcr_a_f:1;
884 uint64_t pcr_s_e:1;
885 uint64_t fcr_a_f:1;
886 uint64_t fcr_s_e:1;
887 uint64_t iobdma:1;
888 uint64_t p_dperr:1;
889 uint64_t win_rto:1;
890 uint64_t i3_pperr:1;
891 uint64_t i2_pperr:1;
892 uint64_t i1_pperr:1;
893 uint64_t i0_pperr:1;
894 uint64_t p3_ptout:1;
895 uint64_t p2_ptout:1;
896 uint64_t p1_ptout:1;
897 uint64_t p0_ptout:1;
898 uint64_t p3_pperr:1;
899 uint64_t p2_pperr:1;
900 uint64_t p1_pperr:1;
901 uint64_t p0_pperr:1;
902 uint64_t g3_rtout:1;
903 uint64_t g2_rtout:1;
904 uint64_t g1_rtout:1;
905 uint64_t g0_rtout:1;
906 uint64_t p3_perr:1;
907 uint64_t p2_perr:1;
908 uint64_t p1_perr:1;
909 uint64_t p0_perr:1;
910 uint64_t p3_rtout:1;
911 uint64_t p2_rtout:1;
912 uint64_t p1_rtout:1;
913 uint64_t p0_rtout:1;
914 uint64_t i3_overf:1;
915 uint64_t i2_overf:1;
916 uint64_t i1_overf:1;
917 uint64_t i0_overf:1;
918 uint64_t i3_rtout:1;
919 uint64_t i2_rtout:1;
920 uint64_t i1_rtout:1;
921 uint64_t i0_rtout:1;
922 uint64_t po3_2sml:1;
923 uint64_t po2_2sml:1;
924 uint64_t po1_2sml:1;
925 uint64_t po0_2sml:1;
926 uint64_t pci_rsl:1;
927 uint64_t rml_wto:1;
928 uint64_t rml_rto:1;
929 } s;
930 struct cvmx_npi_int_sum_cn30xx {
931 uint64_t reserved_62_63:2;
932 uint64_t q1_a_f:1;
933 uint64_t q1_s_e:1;
934 uint64_t pdf_p_f:1;
935 uint64_t pdf_p_e:1;
936 uint64_t pcf_p_f:1;
937 uint64_t pcf_p_e:1;
938 uint64_t rdx_s_e:1;
939 uint64_t rwx_s_e:1;
940 uint64_t pnc_a_f:1;
941 uint64_t pnc_s_e:1;
942 uint64_t com_a_f:1;
943 uint64_t com_s_e:1;
944 uint64_t q3_a_f:1;
945 uint64_t q3_s_e:1;
946 uint64_t q2_a_f:1;
947 uint64_t q2_s_e:1;
948 uint64_t pcr_a_f:1;
949 uint64_t pcr_s_e:1;
950 uint64_t fcr_a_f:1;
951 uint64_t fcr_s_e:1;
952 uint64_t iobdma:1;
953 uint64_t p_dperr:1;
954 uint64_t win_rto:1;
955 uint64_t reserved_36_38:3;
956 uint64_t i0_pperr:1;
957 uint64_t reserved_32_34:3;
958 uint64_t p0_ptout:1;
959 uint64_t reserved_28_30:3;
960 uint64_t p0_pperr:1;
961 uint64_t reserved_24_26:3;
962 uint64_t g0_rtout:1;
963 uint64_t reserved_20_22:3;
964 uint64_t p0_perr:1;
965 uint64_t reserved_16_18:3;
966 uint64_t p0_rtout:1;
967 uint64_t reserved_12_14:3;
968 uint64_t i0_overf:1;
969 uint64_t reserved_8_10:3;
970 uint64_t i0_rtout:1;
971 uint64_t reserved_4_6:3;
972 uint64_t po0_2sml:1;
973 uint64_t pci_rsl:1;
974 uint64_t rml_wto:1;
975 uint64_t rml_rto:1;
976 } cn30xx;
977 struct cvmx_npi_int_sum_cn31xx {
978 uint64_t reserved_62_63:2;
979 uint64_t q1_a_f:1;
980 uint64_t q1_s_e:1;
981 uint64_t pdf_p_f:1;
982 uint64_t pdf_p_e:1;
983 uint64_t pcf_p_f:1;
984 uint64_t pcf_p_e:1;
985 uint64_t rdx_s_e:1;
986 uint64_t rwx_s_e:1;
987 uint64_t pnc_a_f:1;
988 uint64_t pnc_s_e:1;
989 uint64_t com_a_f:1;
990 uint64_t com_s_e:1;
991 uint64_t q3_a_f:1;
992 uint64_t q3_s_e:1;
993 uint64_t q2_a_f:1;
994 uint64_t q2_s_e:1;
995 uint64_t pcr_a_f:1;
996 uint64_t pcr_s_e:1;
997 uint64_t fcr_a_f:1;
998 uint64_t fcr_s_e:1;
999 uint64_t iobdma:1;
1000 uint64_t p_dperr:1;
1001 uint64_t win_rto:1;
1002 uint64_t reserved_37_38:2;
1003 uint64_t i1_pperr:1;
1004 uint64_t i0_pperr:1;
1005 uint64_t reserved_33_34:2;
1006 uint64_t p1_ptout:1;
1007 uint64_t p0_ptout:1;
1008 uint64_t reserved_29_30:2;
1009 uint64_t p1_pperr:1;
1010 uint64_t p0_pperr:1;
1011 uint64_t reserved_25_26:2;
1012 uint64_t g1_rtout:1;
1013 uint64_t g0_rtout:1;
1014 uint64_t reserved_21_22:2;
1015 uint64_t p1_perr:1;
1016 uint64_t p0_perr:1;
1017 uint64_t reserved_17_18:2;
1018 uint64_t p1_rtout:1;
1019 uint64_t p0_rtout:1;
1020 uint64_t reserved_13_14:2;
1021 uint64_t i1_overf:1;
1022 uint64_t i0_overf:1;
1023 uint64_t reserved_9_10:2;
1024 uint64_t i1_rtout:1;
1025 uint64_t i0_rtout:1;
1026 uint64_t reserved_5_6:2;
1027 uint64_t po1_2sml:1;
1028 uint64_t po0_2sml:1;
1029 uint64_t pci_rsl:1;
1030 uint64_t rml_wto:1;
1031 uint64_t rml_rto:1;
1032 } cn31xx;
1033 struct cvmx_npi_int_sum_s cn38xx;
1034 struct cvmx_npi_int_sum_cn38xxp2 {
1035 uint64_t reserved_42_63:22;
1036 uint64_t iobdma:1;
1037 uint64_t p_dperr:1;
1038 uint64_t win_rto:1;
1039 uint64_t i3_pperr:1;
1040 uint64_t i2_pperr:1;
1041 uint64_t i1_pperr:1;
1042 uint64_t i0_pperr:1;
1043 uint64_t p3_ptout:1;
1044 uint64_t p2_ptout:1;
1045 uint64_t p1_ptout:1;
1046 uint64_t p0_ptout:1;
1047 uint64_t p3_pperr:1;
1048 uint64_t p2_pperr:1;
1049 uint64_t p1_pperr:1;
1050 uint64_t p0_pperr:1;
1051 uint64_t g3_rtout:1;
1052 uint64_t g2_rtout:1;
1053 uint64_t g1_rtout:1;
1054 uint64_t g0_rtout:1;
1055 uint64_t p3_perr:1;
1056 uint64_t p2_perr:1;
1057 uint64_t p1_perr:1;
1058 uint64_t p0_perr:1;
1059 uint64_t p3_rtout:1;
1060 uint64_t p2_rtout:1;
1061 uint64_t p1_rtout:1;
1062 uint64_t p0_rtout:1;
1063 uint64_t i3_overf:1;
1064 uint64_t i2_overf:1;
1065 uint64_t i1_overf:1;
1066 uint64_t i0_overf:1;
1067 uint64_t i3_rtout:1;
1068 uint64_t i2_rtout:1;
1069 uint64_t i1_rtout:1;
1070 uint64_t i0_rtout:1;
1071 uint64_t po3_2sml:1;
1072 uint64_t po2_2sml:1;
1073 uint64_t po1_2sml:1;
1074 uint64_t po0_2sml:1;
1075 uint64_t pci_rsl:1;
1076 uint64_t rml_wto:1;
1077 uint64_t rml_rto:1;
1078 } cn38xxp2;
1079 struct cvmx_npi_int_sum_cn31xx cn50xx;
1080 struct cvmx_npi_int_sum_s cn58xx;
1081 struct cvmx_npi_int_sum_s cn58xxp1;
1082};
1083
1084union cvmx_npi_lowp_dbell {
1085 uint64_t u64;
1086 struct cvmx_npi_lowp_dbell_s {
1087 uint64_t reserved_16_63:48;
1088 uint64_t dbell:16;
1089 } s;
1090 struct cvmx_npi_lowp_dbell_s cn30xx;
1091 struct cvmx_npi_lowp_dbell_s cn31xx;
1092 struct cvmx_npi_lowp_dbell_s cn38xx;
1093 struct cvmx_npi_lowp_dbell_s cn38xxp2;
1094 struct cvmx_npi_lowp_dbell_s cn50xx;
1095 struct cvmx_npi_lowp_dbell_s cn58xx;
1096 struct cvmx_npi_lowp_dbell_s cn58xxp1;
1097};
1098
1099union cvmx_npi_lowp_ibuff_saddr {
1100 uint64_t u64;
1101 struct cvmx_npi_lowp_ibuff_saddr_s {
1102 uint64_t reserved_36_63:28;
1103 uint64_t saddr:36;
1104 } s;
1105 struct cvmx_npi_lowp_ibuff_saddr_s cn30xx;
1106 struct cvmx_npi_lowp_ibuff_saddr_s cn31xx;
1107 struct cvmx_npi_lowp_ibuff_saddr_s cn38xx;
1108 struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2;
1109 struct cvmx_npi_lowp_ibuff_saddr_s cn50xx;
1110 struct cvmx_npi_lowp_ibuff_saddr_s cn58xx;
1111 struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1;
1112};
1113
1114union cvmx_npi_mem_access_subidx {
1115 uint64_t u64;
1116 struct cvmx_npi_mem_access_subidx_s {
1117 uint64_t reserved_38_63:26;
1118 uint64_t shortl:1;
1119 uint64_t nmerge:1;
1120 uint64_t esr:2;
1121 uint64_t esw:2;
1122 uint64_t nsr:1;
1123 uint64_t nsw:1;
1124 uint64_t ror:1;
1125 uint64_t row:1;
1126 uint64_t ba:28;
1127 } s;
1128 struct cvmx_npi_mem_access_subidx_s cn30xx;
1129 struct cvmx_npi_mem_access_subidx_cn31xx {
1130 uint64_t reserved_36_63:28;
1131 uint64_t esr:2;
1132 uint64_t esw:2;
1133 uint64_t nsr:1;
1134 uint64_t nsw:1;
1135 uint64_t ror:1;
1136 uint64_t row:1;
1137 uint64_t ba:28;
1138 } cn31xx;
1139 struct cvmx_npi_mem_access_subidx_s cn38xx;
1140 struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2;
1141 struct cvmx_npi_mem_access_subidx_s cn50xx;
1142 struct cvmx_npi_mem_access_subidx_s cn58xx;
1143 struct cvmx_npi_mem_access_subidx_s cn58xxp1;
1144};
1145
1146union cvmx_npi_msi_rcv {
1147 uint64_t u64;
1148 struct cvmx_npi_msi_rcv_s {
1149 uint64_t int_vec:64;
1150 } s;
1151 struct cvmx_npi_msi_rcv_s cn30xx;
1152 struct cvmx_npi_msi_rcv_s cn31xx;
1153 struct cvmx_npi_msi_rcv_s cn38xx;
1154 struct cvmx_npi_msi_rcv_s cn38xxp2;
1155 struct cvmx_npi_msi_rcv_s cn50xx;
1156 struct cvmx_npi_msi_rcv_s cn58xx;
1157 struct cvmx_npi_msi_rcv_s cn58xxp1;
1158};
1159
1160union cvmx_npi_num_desc_outputx {
1161 uint64_t u64;
1162 struct cvmx_npi_num_desc_outputx_s {
1163 uint64_t reserved_32_63:32;
1164 uint64_t size:32;
1165 } s;
1166 struct cvmx_npi_num_desc_outputx_s cn30xx;
1167 struct cvmx_npi_num_desc_outputx_s cn31xx;
1168 struct cvmx_npi_num_desc_outputx_s cn38xx;
1169 struct cvmx_npi_num_desc_outputx_s cn38xxp2;
1170 struct cvmx_npi_num_desc_outputx_s cn50xx;
1171 struct cvmx_npi_num_desc_outputx_s cn58xx;
1172 struct cvmx_npi_num_desc_outputx_s cn58xxp1;
1173};
1174
1175union cvmx_npi_output_control {
1176 uint64_t u64;
1177 struct cvmx_npi_output_control_s {
1178 uint64_t reserved_49_63:15;
1179 uint64_t pkt_rr:1;
1180 uint64_t p3_bmode:1;
1181 uint64_t p2_bmode:1;
1182 uint64_t p1_bmode:1;
1183 uint64_t p0_bmode:1;
1184 uint64_t o3_es:2;
1185 uint64_t o3_ns:1;
1186 uint64_t o3_ro:1;
1187 uint64_t o2_es:2;
1188 uint64_t o2_ns:1;
1189 uint64_t o2_ro:1;
1190 uint64_t o1_es:2;
1191 uint64_t o1_ns:1;
1192 uint64_t o1_ro:1;
1193 uint64_t o0_es:2;
1194 uint64_t o0_ns:1;
1195 uint64_t o0_ro:1;
1196 uint64_t o3_csrm:1;
1197 uint64_t o2_csrm:1;
1198 uint64_t o1_csrm:1;
1199 uint64_t o0_csrm:1;
1200 uint64_t reserved_20_23:4;
1201 uint64_t iptr_o3:1;
1202 uint64_t iptr_o2:1;
1203 uint64_t iptr_o1:1;
1204 uint64_t iptr_o0:1;
1205 uint64_t esr_sl3:2;
1206 uint64_t nsr_sl3:1;
1207 uint64_t ror_sl3:1;
1208 uint64_t esr_sl2:2;
1209 uint64_t nsr_sl2:1;
1210 uint64_t ror_sl2:1;
1211 uint64_t esr_sl1:2;
1212 uint64_t nsr_sl1:1;
1213 uint64_t ror_sl1:1;
1214 uint64_t esr_sl0:2;
1215 uint64_t nsr_sl0:1;
1216 uint64_t ror_sl0:1;
1217 } s;
1218 struct cvmx_npi_output_control_cn30xx {
1219 uint64_t reserved_45_63:19;
1220 uint64_t p0_bmode:1;
1221 uint64_t reserved_32_43:12;
1222 uint64_t o0_es:2;
1223 uint64_t o0_ns:1;
1224 uint64_t o0_ro:1;
1225 uint64_t reserved_25_27:3;
1226 uint64_t o0_csrm:1;
1227 uint64_t reserved_17_23:7;
1228 uint64_t iptr_o0:1;
1229 uint64_t reserved_4_15:12;
1230 uint64_t esr_sl0:2;
1231 uint64_t nsr_sl0:1;
1232 uint64_t ror_sl0:1;
1233 } cn30xx;
1234 struct cvmx_npi_output_control_cn31xx {
1235 uint64_t reserved_46_63:18;
1236 uint64_t p1_bmode:1;
1237 uint64_t p0_bmode:1;
1238 uint64_t reserved_36_43:8;
1239 uint64_t o1_es:2;
1240 uint64_t o1_ns:1;
1241 uint64_t o1_ro:1;
1242 uint64_t o0_es:2;
1243 uint64_t o0_ns:1;
1244 uint64_t o0_ro:1;
1245 uint64_t reserved_26_27:2;
1246 uint64_t o1_csrm:1;
1247 uint64_t o0_csrm:1;
1248 uint64_t reserved_18_23:6;
1249 uint64_t iptr_o1:1;
1250 uint64_t iptr_o0:1;
1251 uint64_t reserved_8_15:8;
1252 uint64_t esr_sl1:2;
1253 uint64_t nsr_sl1:1;
1254 uint64_t ror_sl1:1;
1255 uint64_t esr_sl0:2;
1256 uint64_t nsr_sl0:1;
1257 uint64_t ror_sl0:1;
1258 } cn31xx;
1259 struct cvmx_npi_output_control_s cn38xx;
1260 struct cvmx_npi_output_control_cn38xxp2 {
1261 uint64_t reserved_48_63:16;
1262 uint64_t p3_bmode:1;
1263 uint64_t p2_bmode:1;
1264 uint64_t p1_bmode:1;
1265 uint64_t p0_bmode:1;
1266 uint64_t o3_es:2;
1267 uint64_t o3_ns:1;
1268 uint64_t o3_ro:1;
1269 uint64_t o2_es:2;
1270 uint64_t o2_ns:1;
1271 uint64_t o2_ro:1;
1272 uint64_t o1_es:2;
1273 uint64_t o1_ns:1;
1274 uint64_t o1_ro:1;
1275 uint64_t o0_es:2;
1276 uint64_t o0_ns:1;
1277 uint64_t o0_ro:1;
1278 uint64_t o3_csrm:1;
1279 uint64_t o2_csrm:1;
1280 uint64_t o1_csrm:1;
1281 uint64_t o0_csrm:1;
1282 uint64_t reserved_20_23:4;
1283 uint64_t iptr_o3:1;
1284 uint64_t iptr_o2:1;
1285 uint64_t iptr_o1:1;
1286 uint64_t iptr_o0:1;
1287 uint64_t esr_sl3:2;
1288 uint64_t nsr_sl3:1;
1289 uint64_t ror_sl3:1;
1290 uint64_t esr_sl2:2;
1291 uint64_t nsr_sl2:1;
1292 uint64_t ror_sl2:1;
1293 uint64_t esr_sl1:2;
1294 uint64_t nsr_sl1:1;
1295 uint64_t ror_sl1:1;
1296 uint64_t esr_sl0:2;
1297 uint64_t nsr_sl0:1;
1298 uint64_t ror_sl0:1;
1299 } cn38xxp2;
1300 struct cvmx_npi_output_control_cn50xx {
1301 uint64_t reserved_49_63:15;
1302 uint64_t pkt_rr:1;
1303 uint64_t reserved_46_47:2;
1304 uint64_t p1_bmode:1;
1305 uint64_t p0_bmode:1;
1306 uint64_t reserved_36_43:8;
1307 uint64_t o1_es:2;
1308 uint64_t o1_ns:1;
1309 uint64_t o1_ro:1;
1310 uint64_t o0_es:2;
1311 uint64_t o0_ns:1;
1312 uint64_t o0_ro:1;
1313 uint64_t reserved_26_27:2;
1314 uint64_t o1_csrm:1;
1315 uint64_t o0_csrm:1;
1316 uint64_t reserved_18_23:6;
1317 uint64_t iptr_o1:1;
1318 uint64_t iptr_o0:1;
1319 uint64_t reserved_8_15:8;
1320 uint64_t esr_sl1:2;
1321 uint64_t nsr_sl1:1;
1322 uint64_t ror_sl1:1;
1323 uint64_t esr_sl0:2;
1324 uint64_t nsr_sl0:1;
1325 uint64_t ror_sl0:1;
1326 } cn50xx;
1327 struct cvmx_npi_output_control_s cn58xx;
1328 struct cvmx_npi_output_control_s cn58xxp1;
1329};
1330
1331union cvmx_npi_px_dbpair_addr {
1332 uint64_t u64;
1333 struct cvmx_npi_px_dbpair_addr_s {
1334 uint64_t reserved_63_63:1;
1335 uint64_t state:2;
1336 uint64_t naddr:61;
1337 } s;
1338 struct cvmx_npi_px_dbpair_addr_s cn30xx;
1339 struct cvmx_npi_px_dbpair_addr_s cn31xx;
1340 struct cvmx_npi_px_dbpair_addr_s cn38xx;
1341 struct cvmx_npi_px_dbpair_addr_s cn38xxp2;
1342 struct cvmx_npi_px_dbpair_addr_s cn50xx;
1343 struct cvmx_npi_px_dbpair_addr_s cn58xx;
1344 struct cvmx_npi_px_dbpair_addr_s cn58xxp1;
1345};
1346
1347union cvmx_npi_px_instr_addr {
1348 uint64_t u64;
1349 struct cvmx_npi_px_instr_addr_s {
1350 uint64_t state:3;
1351 uint64_t naddr:61;
1352 } s;
1353 struct cvmx_npi_px_instr_addr_s cn30xx;
1354 struct cvmx_npi_px_instr_addr_s cn31xx;
1355 struct cvmx_npi_px_instr_addr_s cn38xx;
1356 struct cvmx_npi_px_instr_addr_s cn38xxp2;
1357 struct cvmx_npi_px_instr_addr_s cn50xx;
1358 struct cvmx_npi_px_instr_addr_s cn58xx;
1359 struct cvmx_npi_px_instr_addr_s cn58xxp1;
1360};
1361
1362union cvmx_npi_px_instr_cnts {
1363 uint64_t u64;
1364 struct cvmx_npi_px_instr_cnts_s {
1365 uint64_t reserved_38_63:26;
1366 uint64_t fcnt:6;
1367 uint64_t avail:32;
1368 } s;
1369 struct cvmx_npi_px_instr_cnts_s cn30xx;
1370 struct cvmx_npi_px_instr_cnts_s cn31xx;
1371 struct cvmx_npi_px_instr_cnts_s cn38xx;
1372 struct cvmx_npi_px_instr_cnts_s cn38xxp2;
1373 struct cvmx_npi_px_instr_cnts_s cn50xx;
1374 struct cvmx_npi_px_instr_cnts_s cn58xx;
1375 struct cvmx_npi_px_instr_cnts_s cn58xxp1;
1376};
1377
1378union cvmx_npi_px_pair_cnts {
1379 uint64_t u64;
1380 struct cvmx_npi_px_pair_cnts_s {
1381 uint64_t reserved_37_63:27;
1382 uint64_t fcnt:5;
1383 uint64_t avail:32;
1384 } s;
1385 struct cvmx_npi_px_pair_cnts_s cn30xx;
1386 struct cvmx_npi_px_pair_cnts_s cn31xx;
1387 struct cvmx_npi_px_pair_cnts_s cn38xx;
1388 struct cvmx_npi_px_pair_cnts_s cn38xxp2;
1389 struct cvmx_npi_px_pair_cnts_s cn50xx;
1390 struct cvmx_npi_px_pair_cnts_s cn58xx;
1391 struct cvmx_npi_px_pair_cnts_s cn58xxp1;
1392};
1393
1394union cvmx_npi_pci_burst_size {
1395 uint64_t u64;
1396 struct cvmx_npi_pci_burst_size_s {
1397 uint64_t reserved_14_63:50;
1398 uint64_t wr_brst:7;
1399 uint64_t rd_brst:7;
1400 } s;
1401 struct cvmx_npi_pci_burst_size_s cn30xx;
1402 struct cvmx_npi_pci_burst_size_s cn31xx;
1403 struct cvmx_npi_pci_burst_size_s cn38xx;
1404 struct cvmx_npi_pci_burst_size_s cn38xxp2;
1405 struct cvmx_npi_pci_burst_size_s cn50xx;
1406 struct cvmx_npi_pci_burst_size_s cn58xx;
1407 struct cvmx_npi_pci_burst_size_s cn58xxp1;
1408};
1409
1410union cvmx_npi_pci_int_arb_cfg {
1411 uint64_t u64;
1412 struct cvmx_npi_pci_int_arb_cfg_s {
1413 uint64_t reserved_13_63:51;
1414 uint64_t hostmode:1;
1415 uint64_t pci_ovr:4;
1416 uint64_t reserved_5_7:3;
1417 uint64_t en:1;
1418 uint64_t park_mod:1;
1419 uint64_t park_dev:3;
1420 } s;
1421 struct cvmx_npi_pci_int_arb_cfg_cn30xx {
1422 uint64_t reserved_5_63:59;
1423 uint64_t en:1;
1424 uint64_t park_mod:1;
1425 uint64_t park_dev:3;
1426 } cn30xx;
1427 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx;
1428 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx;
1429 struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2;
1430 struct cvmx_npi_pci_int_arb_cfg_s cn50xx;
1431 struct cvmx_npi_pci_int_arb_cfg_s cn58xx;
1432 struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1;
1433};
1434
1435union cvmx_npi_pci_read_cmd {
1436 uint64_t u64;
1437 struct cvmx_npi_pci_read_cmd_s {
1438 uint64_t reserved_11_63:53;
1439 uint64_t cmd_size:11;
1440 } s;
1441 struct cvmx_npi_pci_read_cmd_s cn30xx;
1442 struct cvmx_npi_pci_read_cmd_s cn31xx;
1443 struct cvmx_npi_pci_read_cmd_s cn38xx;
1444 struct cvmx_npi_pci_read_cmd_s cn38xxp2;
1445 struct cvmx_npi_pci_read_cmd_s cn50xx;
1446 struct cvmx_npi_pci_read_cmd_s cn58xx;
1447 struct cvmx_npi_pci_read_cmd_s cn58xxp1;
1448};
1449
1450union cvmx_npi_port32_instr_hdr {
1451 uint64_t u64;
1452 struct cvmx_npi_port32_instr_hdr_s {
1453 uint64_t reserved_44_63:20;
1454 uint64_t pbp:1;
1455 uint64_t rsv_f:5;
1456 uint64_t rparmode:2;
1457 uint64_t rsv_e:1;
1458 uint64_t rskp_len:7;
1459 uint64_t rsv_d:6;
1460 uint64_t use_ihdr:1;
1461 uint64_t rsv_c:5;
1462 uint64_t par_mode:2;
1463 uint64_t rsv_b:1;
1464 uint64_t skp_len:7;
1465 uint64_t rsv_a:6;
1466 } s;
1467 struct cvmx_npi_port32_instr_hdr_s cn30xx;
1468 struct cvmx_npi_port32_instr_hdr_s cn31xx;
1469 struct cvmx_npi_port32_instr_hdr_s cn38xx;
1470 struct cvmx_npi_port32_instr_hdr_s cn38xxp2;
1471 struct cvmx_npi_port32_instr_hdr_s cn50xx;
1472 struct cvmx_npi_port32_instr_hdr_s cn58xx;
1473 struct cvmx_npi_port32_instr_hdr_s cn58xxp1;
1474};
1475
1476union cvmx_npi_port33_instr_hdr {
1477 uint64_t u64;
1478 struct cvmx_npi_port33_instr_hdr_s {
1479 uint64_t reserved_44_63:20;
1480 uint64_t pbp:1;
1481 uint64_t rsv_f:5;
1482 uint64_t rparmode:2;
1483 uint64_t rsv_e:1;
1484 uint64_t rskp_len:7;
1485 uint64_t rsv_d:6;
1486 uint64_t use_ihdr:1;
1487 uint64_t rsv_c:5;
1488 uint64_t par_mode:2;
1489 uint64_t rsv_b:1;
1490 uint64_t skp_len:7;
1491 uint64_t rsv_a:6;
1492 } s;
1493 struct cvmx_npi_port33_instr_hdr_s cn31xx;
1494 struct cvmx_npi_port33_instr_hdr_s cn38xx;
1495 struct cvmx_npi_port33_instr_hdr_s cn38xxp2;
1496 struct cvmx_npi_port33_instr_hdr_s cn50xx;
1497 struct cvmx_npi_port33_instr_hdr_s cn58xx;
1498 struct cvmx_npi_port33_instr_hdr_s cn58xxp1;
1499};
1500
1501union cvmx_npi_port34_instr_hdr {
1502 uint64_t u64;
1503 struct cvmx_npi_port34_instr_hdr_s {
1504 uint64_t reserved_44_63:20;
1505 uint64_t pbp:1;
1506 uint64_t rsv_f:5;
1507 uint64_t rparmode:2;
1508 uint64_t rsv_e:1;
1509 uint64_t rskp_len:7;
1510 uint64_t rsv_d:6;
1511 uint64_t use_ihdr:1;
1512 uint64_t rsv_c:5;
1513 uint64_t par_mode:2;
1514 uint64_t rsv_b:1;
1515 uint64_t skp_len:7;
1516 uint64_t rsv_a:6;
1517 } s;
1518 struct cvmx_npi_port34_instr_hdr_s cn38xx;
1519 struct cvmx_npi_port34_instr_hdr_s cn38xxp2;
1520 struct cvmx_npi_port34_instr_hdr_s cn58xx;
1521 struct cvmx_npi_port34_instr_hdr_s cn58xxp1;
1522};
1523
1524union cvmx_npi_port35_instr_hdr {
1525 uint64_t u64;
1526 struct cvmx_npi_port35_instr_hdr_s {
1527 uint64_t reserved_44_63:20;
1528 uint64_t pbp:1;
1529 uint64_t rsv_f:5;
1530 uint64_t rparmode:2;
1531 uint64_t rsv_e:1;
1532 uint64_t rskp_len:7;
1533 uint64_t rsv_d:6;
1534 uint64_t use_ihdr:1;
1535 uint64_t rsv_c:5;
1536 uint64_t par_mode:2;
1537 uint64_t rsv_b:1;
1538 uint64_t skp_len:7;
1539 uint64_t rsv_a:6;
1540 } s;
1541 struct cvmx_npi_port35_instr_hdr_s cn38xx;
1542 struct cvmx_npi_port35_instr_hdr_s cn38xxp2;
1543 struct cvmx_npi_port35_instr_hdr_s cn58xx;
1544 struct cvmx_npi_port35_instr_hdr_s cn58xxp1;
1545};
1546
1547union cvmx_npi_port_bp_control {
1548 uint64_t u64;
1549 struct cvmx_npi_port_bp_control_s {
1550 uint64_t reserved_8_63:56;
1551 uint64_t bp_on:4;
1552 uint64_t enb:4;
1553 } s;
1554 struct cvmx_npi_port_bp_control_s cn30xx;
1555 struct cvmx_npi_port_bp_control_s cn31xx;
1556 struct cvmx_npi_port_bp_control_s cn38xx;
1557 struct cvmx_npi_port_bp_control_s cn38xxp2;
1558 struct cvmx_npi_port_bp_control_s cn50xx;
1559 struct cvmx_npi_port_bp_control_s cn58xx;
1560 struct cvmx_npi_port_bp_control_s cn58xxp1;
1561};
1562
1563union cvmx_npi_rsl_int_blocks {
1564 uint64_t u64;
1565 struct cvmx_npi_rsl_int_blocks_s {
1566 uint64_t reserved_32_63:32;
1567 uint64_t rint_31:1;
1568 uint64_t iob:1;
1569 uint64_t reserved_28_29:2;
1570 uint64_t rint_27:1;
1571 uint64_t rint_26:1;
1572 uint64_t rint_25:1;
1573 uint64_t rint_24:1;
1574 uint64_t asx1:1;
1575 uint64_t asx0:1;
1576 uint64_t rint_21:1;
1577 uint64_t pip:1;
1578 uint64_t spx1:1;
1579 uint64_t spx0:1;
1580 uint64_t lmc:1;
1581 uint64_t l2c:1;
1582 uint64_t rint_15:1;
1583 uint64_t reserved_13_14:2;
1584 uint64_t pow:1;
1585 uint64_t tim:1;
1586 uint64_t pko:1;
1587 uint64_t ipd:1;
1588 uint64_t rint_8:1;
1589 uint64_t zip:1;
1590 uint64_t dfa:1;
1591 uint64_t fpa:1;
1592 uint64_t key:1;
1593 uint64_t npi:1;
1594 uint64_t gmx1:1;
1595 uint64_t gmx0:1;
1596 uint64_t mio:1;
1597 } s;
1598 struct cvmx_npi_rsl_int_blocks_cn30xx {
1599 uint64_t reserved_32_63:32;
1600 uint64_t rint_31:1;
1601 uint64_t iob:1;
1602 uint64_t rint_29:1;
1603 uint64_t rint_28:1;
1604 uint64_t rint_27:1;
1605 uint64_t rint_26:1;
1606 uint64_t rint_25:1;
1607 uint64_t rint_24:1;
1608 uint64_t asx1:1;
1609 uint64_t asx0:1;
1610 uint64_t rint_21:1;
1611 uint64_t pip:1;
1612 uint64_t spx1:1;
1613 uint64_t spx0:1;
1614 uint64_t lmc:1;
1615 uint64_t l2c:1;
1616 uint64_t rint_15:1;
1617 uint64_t rint_14:1;
1618 uint64_t usb:1;
1619 uint64_t pow:1;
1620 uint64_t tim:1;
1621 uint64_t pko:1;
1622 uint64_t ipd:1;
1623 uint64_t rint_8:1;
1624 uint64_t zip:1;
1625 uint64_t dfa:1;
1626 uint64_t fpa:1;
1627 uint64_t key:1;
1628 uint64_t npi:1;
1629 uint64_t gmx1:1;
1630 uint64_t gmx0:1;
1631 uint64_t mio:1;
1632 } cn30xx;
1633 struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx;
1634 struct cvmx_npi_rsl_int_blocks_cn38xx {
1635 uint64_t reserved_32_63:32;
1636 uint64_t rint_31:1;
1637 uint64_t iob:1;
1638 uint64_t rint_29:1;
1639 uint64_t rint_28:1;
1640 uint64_t rint_27:1;
1641 uint64_t rint_26:1;
1642 uint64_t rint_25:1;
1643 uint64_t rint_24:1;
1644 uint64_t asx1:1;
1645 uint64_t asx0:1;
1646 uint64_t rint_21:1;
1647 uint64_t pip:1;
1648 uint64_t spx1:1;
1649 uint64_t spx0:1;
1650 uint64_t lmc:1;
1651 uint64_t l2c:1;
1652 uint64_t rint_15:1;
1653 uint64_t rint_14:1;
1654 uint64_t rint_13:1;
1655 uint64_t pow:1;
1656 uint64_t tim:1;
1657 uint64_t pko:1;
1658 uint64_t ipd:1;
1659 uint64_t rint_8:1;
1660 uint64_t zip:1;
1661 uint64_t dfa:1;
1662 uint64_t fpa:1;
1663 uint64_t key:1;
1664 uint64_t npi:1;
1665 uint64_t gmx1:1;
1666 uint64_t gmx0:1;
1667 uint64_t mio:1;
1668 } cn38xx;
1669 struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2;
1670 struct cvmx_npi_rsl_int_blocks_cn50xx {
1671 uint64_t reserved_31_63:33;
1672 uint64_t iob:1;
1673 uint64_t lmc1:1;
1674 uint64_t agl:1;
1675 uint64_t reserved_24_27:4;
1676 uint64_t asx1:1;
1677 uint64_t asx0:1;
1678 uint64_t reserved_21_21:1;
1679 uint64_t pip:1;
1680 uint64_t spx1:1;
1681 uint64_t spx0:1;
1682 uint64_t lmc:1;
1683 uint64_t l2c:1;
1684 uint64_t reserved_15_15:1;
1685 uint64_t rad:1;
1686 uint64_t usb:1;
1687 uint64_t pow:1;
1688 uint64_t tim:1;
1689 uint64_t pko:1;
1690 uint64_t ipd:1;
1691 uint64_t reserved_8_8:1;
1692 uint64_t zip:1;
1693 uint64_t dfa:1;
1694 uint64_t fpa:1;
1695 uint64_t key:1;
1696 uint64_t npi:1;
1697 uint64_t gmx1:1;
1698 uint64_t gmx0:1;
1699 uint64_t mio:1;
1700 } cn50xx;
1701 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx;
1702 struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1;
1703};
1704
1705union cvmx_npi_size_inputx {
1706 uint64_t u64;
1707 struct cvmx_npi_size_inputx_s {
1708 uint64_t reserved_32_63:32;
1709 uint64_t size:32;
1710 } s;
1711 struct cvmx_npi_size_inputx_s cn30xx;
1712 struct cvmx_npi_size_inputx_s cn31xx;
1713 struct cvmx_npi_size_inputx_s cn38xx;
1714 struct cvmx_npi_size_inputx_s cn38xxp2;
1715 struct cvmx_npi_size_inputx_s cn50xx;
1716 struct cvmx_npi_size_inputx_s cn58xx;
1717 struct cvmx_npi_size_inputx_s cn58xxp1;
1718};
1719
1720union cvmx_npi_win_read_to {
1721 uint64_t u64;
1722 struct cvmx_npi_win_read_to_s {
1723 uint64_t reserved_32_63:32;
1724 uint64_t time:32;
1725 } s;
1726 struct cvmx_npi_win_read_to_s cn30xx;
1727 struct cvmx_npi_win_read_to_s cn31xx;
1728 struct cvmx_npi_win_read_to_s cn38xx;
1729 struct cvmx_npi_win_read_to_s cn38xxp2;
1730 struct cvmx_npi_win_read_to_s cn50xx;
1731 struct cvmx_npi_win_read_to_s cn58xx;
1732 struct cvmx_npi_win_read_to_s cn58xxp1;
1733};
1734
1735#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pci-defs.h b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
new file mode 100644
index 000000000000..90f8d6535753
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pci-defs.h
@@ -0,0 +1,1645 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCI_DEFS_H__
29#define __CVMX_PCI_DEFS_H__
30
31#define CVMX_PCI_BAR1_INDEXX(offset) \
32 (0x0000000000000100ull + (((offset) & 31) * 4))
33#define CVMX_PCI_BIST_REG \
34 (0x00000000000001C0ull)
35#define CVMX_PCI_CFG00 \
36 (0x0000000000000000ull)
37#define CVMX_PCI_CFG01 \
38 (0x0000000000000004ull)
39#define CVMX_PCI_CFG02 \
40 (0x0000000000000008ull)
41#define CVMX_PCI_CFG03 \
42 (0x000000000000000Cull)
43#define CVMX_PCI_CFG04 \
44 (0x0000000000000010ull)
45#define CVMX_PCI_CFG05 \
46 (0x0000000000000014ull)
47#define CVMX_PCI_CFG06 \
48 (0x0000000000000018ull)
49#define CVMX_PCI_CFG07 \
50 (0x000000000000001Cull)
51#define CVMX_PCI_CFG08 \
52 (0x0000000000000020ull)
53#define CVMX_PCI_CFG09 \
54 (0x0000000000000024ull)
55#define CVMX_PCI_CFG10 \
56 (0x0000000000000028ull)
57#define CVMX_PCI_CFG11 \
58 (0x000000000000002Cull)
59#define CVMX_PCI_CFG12 \
60 (0x0000000000000030ull)
61#define CVMX_PCI_CFG13 \
62 (0x0000000000000034ull)
63#define CVMX_PCI_CFG15 \
64 (0x000000000000003Cull)
65#define CVMX_PCI_CFG16 \
66 (0x0000000000000040ull)
67#define CVMX_PCI_CFG17 \
68 (0x0000000000000044ull)
69#define CVMX_PCI_CFG18 \
70 (0x0000000000000048ull)
71#define CVMX_PCI_CFG19 \
72 (0x000000000000004Cull)
73#define CVMX_PCI_CFG20 \
74 (0x0000000000000050ull)
75#define CVMX_PCI_CFG21 \
76 (0x0000000000000054ull)
77#define CVMX_PCI_CFG22 \
78 (0x0000000000000058ull)
79#define CVMX_PCI_CFG56 \
80 (0x00000000000000E0ull)
81#define CVMX_PCI_CFG57 \
82 (0x00000000000000E4ull)
83#define CVMX_PCI_CFG58 \
84 (0x00000000000000E8ull)
85#define CVMX_PCI_CFG59 \
86 (0x00000000000000ECull)
87#define CVMX_PCI_CFG60 \
88 (0x00000000000000F0ull)
89#define CVMX_PCI_CFG61 \
90 (0x00000000000000F4ull)
91#define CVMX_PCI_CFG62 \
92 (0x00000000000000F8ull)
93#define CVMX_PCI_CFG63 \
94 (0x00000000000000FCull)
95#define CVMX_PCI_CNT_REG \
96 (0x00000000000001B8ull)
97#define CVMX_PCI_CTL_STATUS_2 \
98 (0x000000000000018Cull)
99#define CVMX_PCI_DBELL_0 \
100 (0x0000000000000080ull)
101#define CVMX_PCI_DBELL_1 \
102 (0x0000000000000088ull)
103#define CVMX_PCI_DBELL_2 \
104 (0x0000000000000090ull)
105#define CVMX_PCI_DBELL_3 \
106 (0x0000000000000098ull)
107#define CVMX_PCI_DBELL_X(offset) \
108 (0x0000000000000080ull + (((offset) & 3) * 8))
109#define CVMX_PCI_DMA_CNT0 \
110 (0x00000000000000A0ull)
111#define CVMX_PCI_DMA_CNT1 \
112 (0x00000000000000A8ull)
113#define CVMX_PCI_DMA_CNTX(offset) \
114 (0x00000000000000A0ull + (((offset) & 1) * 8))
115#define CVMX_PCI_DMA_INT_LEV0 \
116 (0x00000000000000A4ull)
117#define CVMX_PCI_DMA_INT_LEV1 \
118 (0x00000000000000ACull)
119#define CVMX_PCI_DMA_INT_LEVX(offset) \
120 (0x00000000000000A4ull + (((offset) & 1) * 8))
121#define CVMX_PCI_DMA_TIME0 \
122 (0x00000000000000B0ull)
123#define CVMX_PCI_DMA_TIME1 \
124 (0x00000000000000B4ull)
125#define CVMX_PCI_DMA_TIMEX(offset) \
126 (0x00000000000000B0ull + (((offset) & 1) * 4))
127#define CVMX_PCI_INSTR_COUNT0 \
128 (0x0000000000000084ull)
129#define CVMX_PCI_INSTR_COUNT1 \
130 (0x000000000000008Cull)
131#define CVMX_PCI_INSTR_COUNT2 \
132 (0x0000000000000094ull)
133#define CVMX_PCI_INSTR_COUNT3 \
134 (0x000000000000009Cull)
135#define CVMX_PCI_INSTR_COUNTX(offset) \
136 (0x0000000000000084ull + (((offset) & 3) * 8))
137#define CVMX_PCI_INT_ENB \
138 (0x0000000000000038ull)
139#define CVMX_PCI_INT_ENB2 \
140 (0x00000000000001A0ull)
141#define CVMX_PCI_INT_SUM \
142 (0x0000000000000030ull)
143#define CVMX_PCI_INT_SUM2 \
144 (0x0000000000000198ull)
145#define CVMX_PCI_MSI_RCV \
146 (0x00000000000000F0ull)
147#define CVMX_PCI_PKTS_SENT0 \
148 (0x0000000000000040ull)
149#define CVMX_PCI_PKTS_SENT1 \
150 (0x0000000000000050ull)
151#define CVMX_PCI_PKTS_SENT2 \
152 (0x0000000000000060ull)
153#define CVMX_PCI_PKTS_SENT3 \
154 (0x0000000000000070ull)
155#define CVMX_PCI_PKTS_SENTX(offset) \
156 (0x0000000000000040ull + (((offset) & 3) * 16))
157#define CVMX_PCI_PKTS_SENT_INT_LEV0 \
158 (0x0000000000000048ull)
159#define CVMX_PCI_PKTS_SENT_INT_LEV1 \
160 (0x0000000000000058ull)
161#define CVMX_PCI_PKTS_SENT_INT_LEV2 \
162 (0x0000000000000068ull)
163#define CVMX_PCI_PKTS_SENT_INT_LEV3 \
164 (0x0000000000000078ull)
165#define CVMX_PCI_PKTS_SENT_INT_LEVX(offset) \
166 (0x0000000000000048ull + (((offset) & 3) * 16))
167#define CVMX_PCI_PKTS_SENT_TIME0 \
168 (0x000000000000004Cull)
169#define CVMX_PCI_PKTS_SENT_TIME1 \
170 (0x000000000000005Cull)
171#define CVMX_PCI_PKTS_SENT_TIME2 \
172 (0x000000000000006Cull)
173#define CVMX_PCI_PKTS_SENT_TIME3 \
174 (0x000000000000007Cull)
175#define CVMX_PCI_PKTS_SENT_TIMEX(offset) \
176 (0x000000000000004Cull + (((offset) & 3) * 16))
177#define CVMX_PCI_PKT_CREDITS0 \
178 (0x0000000000000044ull)
179#define CVMX_PCI_PKT_CREDITS1 \
180 (0x0000000000000054ull)
181#define CVMX_PCI_PKT_CREDITS2 \
182 (0x0000000000000064ull)
183#define CVMX_PCI_PKT_CREDITS3 \
184 (0x0000000000000074ull)
185#define CVMX_PCI_PKT_CREDITSX(offset) \
186 (0x0000000000000044ull + (((offset) & 3) * 16))
187#define CVMX_PCI_READ_CMD_6 \
188 (0x0000000000000180ull)
189#define CVMX_PCI_READ_CMD_C \
190 (0x0000000000000184ull)
191#define CVMX_PCI_READ_CMD_E \
192 (0x0000000000000188ull)
193#define CVMX_PCI_READ_TIMEOUT \
194 CVMX_ADD_IO_SEG(0x00011F00000000B0ull)
195#define CVMX_PCI_SCM_REG \
196 (0x00000000000001A8ull)
197#define CVMX_PCI_TSR_REG \
198 (0x00000000000001B0ull)
199#define CVMX_PCI_WIN_RD_ADDR \
200 (0x0000000000000008ull)
201#define CVMX_PCI_WIN_RD_DATA \
202 (0x0000000000000020ull)
203#define CVMX_PCI_WIN_WR_ADDR \
204 (0x0000000000000000ull)
205#define CVMX_PCI_WIN_WR_DATA \
206 (0x0000000000000010ull)
207#define CVMX_PCI_WIN_WR_MASK \
208 (0x0000000000000018ull)
209
210union cvmx_pci_bar1_indexx {
211 uint32_t u32;
212 struct cvmx_pci_bar1_indexx_s {
213 uint32_t reserved_18_31:14;
214 uint32_t addr_idx:14;
215 uint32_t ca:1;
216 uint32_t end_swp:2;
217 uint32_t addr_v:1;
218 } s;
219 struct cvmx_pci_bar1_indexx_s cn30xx;
220 struct cvmx_pci_bar1_indexx_s cn31xx;
221 struct cvmx_pci_bar1_indexx_s cn38xx;
222 struct cvmx_pci_bar1_indexx_s cn38xxp2;
223 struct cvmx_pci_bar1_indexx_s cn50xx;
224 struct cvmx_pci_bar1_indexx_s cn58xx;
225 struct cvmx_pci_bar1_indexx_s cn58xxp1;
226};
227
228union cvmx_pci_bist_reg {
229 uint64_t u64;
230 struct cvmx_pci_bist_reg_s {
231 uint64_t reserved_10_63:54;
232 uint64_t rsp_bs:1;
233 uint64_t dma0_bs:1;
234 uint64_t cmd0_bs:1;
235 uint64_t cmd_bs:1;
236 uint64_t csr2p_bs:1;
237 uint64_t csrr_bs:1;
238 uint64_t rsp2p_bs:1;
239 uint64_t csr2n_bs:1;
240 uint64_t dat2n_bs:1;
241 uint64_t dbg2n_bs:1;
242 } s;
243 struct cvmx_pci_bist_reg_s cn50xx;
244};
245
246union cvmx_pci_cfg00 {
247 uint32_t u32;
248 struct cvmx_pci_cfg00_s {
249 uint32_t devid:16;
250 uint32_t vendid:16;
251 } s;
252 struct cvmx_pci_cfg00_s cn30xx;
253 struct cvmx_pci_cfg00_s cn31xx;
254 struct cvmx_pci_cfg00_s cn38xx;
255 struct cvmx_pci_cfg00_s cn38xxp2;
256 struct cvmx_pci_cfg00_s cn50xx;
257 struct cvmx_pci_cfg00_s cn58xx;
258 struct cvmx_pci_cfg00_s cn58xxp1;
259};
260
261union cvmx_pci_cfg01 {
262 uint32_t u32;
263 struct cvmx_pci_cfg01_s {
264 uint32_t dpe:1;
265 uint32_t sse:1;
266 uint32_t rma:1;
267 uint32_t rta:1;
268 uint32_t sta:1;
269 uint32_t devt:2;
270 uint32_t mdpe:1;
271 uint32_t fbb:1;
272 uint32_t reserved_22_22:1;
273 uint32_t m66:1;
274 uint32_t cle:1;
275 uint32_t i_stat:1;
276 uint32_t reserved_11_18:8;
277 uint32_t i_dis:1;
278 uint32_t fbbe:1;
279 uint32_t see:1;
280 uint32_t ads:1;
281 uint32_t pee:1;
282 uint32_t vps:1;
283 uint32_t mwice:1;
284 uint32_t scse:1;
285 uint32_t me:1;
286 uint32_t msae:1;
287 uint32_t isae:1;
288 } s;
289 struct cvmx_pci_cfg01_s cn30xx;
290 struct cvmx_pci_cfg01_s cn31xx;
291 struct cvmx_pci_cfg01_s cn38xx;
292 struct cvmx_pci_cfg01_s cn38xxp2;
293 struct cvmx_pci_cfg01_s cn50xx;
294 struct cvmx_pci_cfg01_s cn58xx;
295 struct cvmx_pci_cfg01_s cn58xxp1;
296};
297
298union cvmx_pci_cfg02 {
299 uint32_t u32;
300 struct cvmx_pci_cfg02_s {
301 uint32_t cc:24;
302 uint32_t rid:8;
303 } s;
304 struct cvmx_pci_cfg02_s cn30xx;
305 struct cvmx_pci_cfg02_s cn31xx;
306 struct cvmx_pci_cfg02_s cn38xx;
307 struct cvmx_pci_cfg02_s cn38xxp2;
308 struct cvmx_pci_cfg02_s cn50xx;
309 struct cvmx_pci_cfg02_s cn58xx;
310 struct cvmx_pci_cfg02_s cn58xxp1;
311};
312
313union cvmx_pci_cfg03 {
314 uint32_t u32;
315 struct cvmx_pci_cfg03_s {
316 uint32_t bcap:1;
317 uint32_t brb:1;
318 uint32_t reserved_28_29:2;
319 uint32_t bcod:4;
320 uint32_t ht:8;
321 uint32_t lt:8;
322 uint32_t cls:8;
323 } s;
324 struct cvmx_pci_cfg03_s cn30xx;
325 struct cvmx_pci_cfg03_s cn31xx;
326 struct cvmx_pci_cfg03_s cn38xx;
327 struct cvmx_pci_cfg03_s cn38xxp2;
328 struct cvmx_pci_cfg03_s cn50xx;
329 struct cvmx_pci_cfg03_s cn58xx;
330 struct cvmx_pci_cfg03_s cn58xxp1;
331};
332
333union cvmx_pci_cfg04 {
334 uint32_t u32;
335 struct cvmx_pci_cfg04_s {
336 uint32_t lbase:20;
337 uint32_t lbasez:8;
338 uint32_t pf:1;
339 uint32_t typ:2;
340 uint32_t mspc:1;
341 } s;
342 struct cvmx_pci_cfg04_s cn30xx;
343 struct cvmx_pci_cfg04_s cn31xx;
344 struct cvmx_pci_cfg04_s cn38xx;
345 struct cvmx_pci_cfg04_s cn38xxp2;
346 struct cvmx_pci_cfg04_s cn50xx;
347 struct cvmx_pci_cfg04_s cn58xx;
348 struct cvmx_pci_cfg04_s cn58xxp1;
349};
350
351union cvmx_pci_cfg05 {
352 uint32_t u32;
353 struct cvmx_pci_cfg05_s {
354 uint32_t hbase:32;
355 } s;
356 struct cvmx_pci_cfg05_s cn30xx;
357 struct cvmx_pci_cfg05_s cn31xx;
358 struct cvmx_pci_cfg05_s cn38xx;
359 struct cvmx_pci_cfg05_s cn38xxp2;
360 struct cvmx_pci_cfg05_s cn50xx;
361 struct cvmx_pci_cfg05_s cn58xx;
362 struct cvmx_pci_cfg05_s cn58xxp1;
363};
364
365union cvmx_pci_cfg06 {
366 uint32_t u32;
367 struct cvmx_pci_cfg06_s {
368 uint32_t lbase:5;
369 uint32_t lbasez:23;
370 uint32_t pf:1;
371 uint32_t typ:2;
372 uint32_t mspc:1;
373 } s;
374 struct cvmx_pci_cfg06_s cn30xx;
375 struct cvmx_pci_cfg06_s cn31xx;
376 struct cvmx_pci_cfg06_s cn38xx;
377 struct cvmx_pci_cfg06_s cn38xxp2;
378 struct cvmx_pci_cfg06_s cn50xx;
379 struct cvmx_pci_cfg06_s cn58xx;
380 struct cvmx_pci_cfg06_s cn58xxp1;
381};
382
383union cvmx_pci_cfg07 {
384 uint32_t u32;
385 struct cvmx_pci_cfg07_s {
386 uint32_t hbase:32;
387 } s;
388 struct cvmx_pci_cfg07_s cn30xx;
389 struct cvmx_pci_cfg07_s cn31xx;
390 struct cvmx_pci_cfg07_s cn38xx;
391 struct cvmx_pci_cfg07_s cn38xxp2;
392 struct cvmx_pci_cfg07_s cn50xx;
393 struct cvmx_pci_cfg07_s cn58xx;
394 struct cvmx_pci_cfg07_s cn58xxp1;
395};
396
397union cvmx_pci_cfg08 {
398 uint32_t u32;
399 struct cvmx_pci_cfg08_s {
400 uint32_t lbasez:28;
401 uint32_t pf:1;
402 uint32_t typ:2;
403 uint32_t mspc:1;
404 } s;
405 struct cvmx_pci_cfg08_s cn30xx;
406 struct cvmx_pci_cfg08_s cn31xx;
407 struct cvmx_pci_cfg08_s cn38xx;
408 struct cvmx_pci_cfg08_s cn38xxp2;
409 struct cvmx_pci_cfg08_s cn50xx;
410 struct cvmx_pci_cfg08_s cn58xx;
411 struct cvmx_pci_cfg08_s cn58xxp1;
412};
413
414union cvmx_pci_cfg09 {
415 uint32_t u32;
416 struct cvmx_pci_cfg09_s {
417 uint32_t hbase:25;
418 uint32_t hbasez:7;
419 } s;
420 struct cvmx_pci_cfg09_s cn30xx;
421 struct cvmx_pci_cfg09_s cn31xx;
422 struct cvmx_pci_cfg09_s cn38xx;
423 struct cvmx_pci_cfg09_s cn38xxp2;
424 struct cvmx_pci_cfg09_s cn50xx;
425 struct cvmx_pci_cfg09_s cn58xx;
426 struct cvmx_pci_cfg09_s cn58xxp1;
427};
428
429union cvmx_pci_cfg10 {
430 uint32_t u32;
431 struct cvmx_pci_cfg10_s {
432 uint32_t cisp:32;
433 } s;
434 struct cvmx_pci_cfg10_s cn30xx;
435 struct cvmx_pci_cfg10_s cn31xx;
436 struct cvmx_pci_cfg10_s cn38xx;
437 struct cvmx_pci_cfg10_s cn38xxp2;
438 struct cvmx_pci_cfg10_s cn50xx;
439 struct cvmx_pci_cfg10_s cn58xx;
440 struct cvmx_pci_cfg10_s cn58xxp1;
441};
442
443union cvmx_pci_cfg11 {
444 uint32_t u32;
445 struct cvmx_pci_cfg11_s {
446 uint32_t ssid:16;
447 uint32_t ssvid:16;
448 } s;
449 struct cvmx_pci_cfg11_s cn30xx;
450 struct cvmx_pci_cfg11_s cn31xx;
451 struct cvmx_pci_cfg11_s cn38xx;
452 struct cvmx_pci_cfg11_s cn38xxp2;
453 struct cvmx_pci_cfg11_s cn50xx;
454 struct cvmx_pci_cfg11_s cn58xx;
455 struct cvmx_pci_cfg11_s cn58xxp1;
456};
457
458union cvmx_pci_cfg12 {
459 uint32_t u32;
460 struct cvmx_pci_cfg12_s {
461 uint32_t erbar:16;
462 uint32_t erbarz:5;
463 uint32_t reserved_1_10:10;
464 uint32_t erbar_en:1;
465 } s;
466 struct cvmx_pci_cfg12_s cn30xx;
467 struct cvmx_pci_cfg12_s cn31xx;
468 struct cvmx_pci_cfg12_s cn38xx;
469 struct cvmx_pci_cfg12_s cn38xxp2;
470 struct cvmx_pci_cfg12_s cn50xx;
471 struct cvmx_pci_cfg12_s cn58xx;
472 struct cvmx_pci_cfg12_s cn58xxp1;
473};
474
475union cvmx_pci_cfg13 {
476 uint32_t u32;
477 struct cvmx_pci_cfg13_s {
478 uint32_t reserved_8_31:24;
479 uint32_t cp:8;
480 } s;
481 struct cvmx_pci_cfg13_s cn30xx;
482 struct cvmx_pci_cfg13_s cn31xx;
483 struct cvmx_pci_cfg13_s cn38xx;
484 struct cvmx_pci_cfg13_s cn38xxp2;
485 struct cvmx_pci_cfg13_s cn50xx;
486 struct cvmx_pci_cfg13_s cn58xx;
487 struct cvmx_pci_cfg13_s cn58xxp1;
488};
489
490union cvmx_pci_cfg15 {
491 uint32_t u32;
492 struct cvmx_pci_cfg15_s {
493 uint32_t ml:8;
494 uint32_t mg:8;
495 uint32_t inta:8;
496 uint32_t il:8;
497 } s;
498 struct cvmx_pci_cfg15_s cn30xx;
499 struct cvmx_pci_cfg15_s cn31xx;
500 struct cvmx_pci_cfg15_s cn38xx;
501 struct cvmx_pci_cfg15_s cn38xxp2;
502 struct cvmx_pci_cfg15_s cn50xx;
503 struct cvmx_pci_cfg15_s cn58xx;
504 struct cvmx_pci_cfg15_s cn58xxp1;
505};
506
507union cvmx_pci_cfg16 {
508 uint32_t u32;
509 struct cvmx_pci_cfg16_s {
510 uint32_t trdnpr:1;
511 uint32_t trdard:1;
512 uint32_t rdsati:1;
513 uint32_t trdrs:1;
514 uint32_t trtae:1;
515 uint32_t twsei:1;
516 uint32_t twsen:1;
517 uint32_t twtae:1;
518 uint32_t tmae:1;
519 uint32_t tslte:3;
520 uint32_t tilt:4;
521 uint32_t pbe:12;
522 uint32_t dppmr:1;
523 uint32_t reserved_2_2:1;
524 uint32_t tswc:1;
525 uint32_t mltd:1;
526 } s;
527 struct cvmx_pci_cfg16_s cn30xx;
528 struct cvmx_pci_cfg16_s cn31xx;
529 struct cvmx_pci_cfg16_s cn38xx;
530 struct cvmx_pci_cfg16_s cn38xxp2;
531 struct cvmx_pci_cfg16_s cn50xx;
532 struct cvmx_pci_cfg16_s cn58xx;
533 struct cvmx_pci_cfg16_s cn58xxp1;
534};
535
536union cvmx_pci_cfg17 {
537 uint32_t u32;
538 struct cvmx_pci_cfg17_s {
539 uint32_t tscme:32;
540 } s;
541 struct cvmx_pci_cfg17_s cn30xx;
542 struct cvmx_pci_cfg17_s cn31xx;
543 struct cvmx_pci_cfg17_s cn38xx;
544 struct cvmx_pci_cfg17_s cn38xxp2;
545 struct cvmx_pci_cfg17_s cn50xx;
546 struct cvmx_pci_cfg17_s cn58xx;
547 struct cvmx_pci_cfg17_s cn58xxp1;
548};
549
550union cvmx_pci_cfg18 {
551 uint32_t u32;
552 struct cvmx_pci_cfg18_s {
553 uint32_t tdsrps:32;
554 } s;
555 struct cvmx_pci_cfg18_s cn30xx;
556 struct cvmx_pci_cfg18_s cn31xx;
557 struct cvmx_pci_cfg18_s cn38xx;
558 struct cvmx_pci_cfg18_s cn38xxp2;
559 struct cvmx_pci_cfg18_s cn50xx;
560 struct cvmx_pci_cfg18_s cn58xx;
561 struct cvmx_pci_cfg18_s cn58xxp1;
562};
563
564union cvmx_pci_cfg19 {
565 uint32_t u32;
566 struct cvmx_pci_cfg19_s {
567 uint32_t mrbcm:1;
568 uint32_t mrbci:1;
569 uint32_t mdwe:1;
570 uint32_t mdre:1;
571 uint32_t mdrimc:1;
572 uint32_t mdrrmc:3;
573 uint32_t tmes:8;
574 uint32_t teci:1;
575 uint32_t tmei:1;
576 uint32_t tmse:1;
577 uint32_t tmdpes:1;
578 uint32_t tmapes:1;
579 uint32_t reserved_9_10:2;
580 uint32_t tibcd:1;
581 uint32_t tibde:1;
582 uint32_t reserved_6_6:1;
583 uint32_t tidomc:1;
584 uint32_t tdomc:5;
585 } s;
586 struct cvmx_pci_cfg19_s cn30xx;
587 struct cvmx_pci_cfg19_s cn31xx;
588 struct cvmx_pci_cfg19_s cn38xx;
589 struct cvmx_pci_cfg19_s cn38xxp2;
590 struct cvmx_pci_cfg19_s cn50xx;
591 struct cvmx_pci_cfg19_s cn58xx;
592 struct cvmx_pci_cfg19_s cn58xxp1;
593};
594
595union cvmx_pci_cfg20 {
596 uint32_t u32;
597 struct cvmx_pci_cfg20_s {
598 uint32_t mdsp:32;
599 } s;
600 struct cvmx_pci_cfg20_s cn30xx;
601 struct cvmx_pci_cfg20_s cn31xx;
602 struct cvmx_pci_cfg20_s cn38xx;
603 struct cvmx_pci_cfg20_s cn38xxp2;
604 struct cvmx_pci_cfg20_s cn50xx;
605 struct cvmx_pci_cfg20_s cn58xx;
606 struct cvmx_pci_cfg20_s cn58xxp1;
607};
608
609union cvmx_pci_cfg21 {
610 uint32_t u32;
611 struct cvmx_pci_cfg21_s {
612 uint32_t scmre:32;
613 } s;
614 struct cvmx_pci_cfg21_s cn30xx;
615 struct cvmx_pci_cfg21_s cn31xx;
616 struct cvmx_pci_cfg21_s cn38xx;
617 struct cvmx_pci_cfg21_s cn38xxp2;
618 struct cvmx_pci_cfg21_s cn50xx;
619 struct cvmx_pci_cfg21_s cn58xx;
620 struct cvmx_pci_cfg21_s cn58xxp1;
621};
622
623union cvmx_pci_cfg22 {
624 uint32_t u32;
625 struct cvmx_pci_cfg22_s {
626 uint32_t mac:7;
627 uint32_t reserved_19_24:6;
628 uint32_t flush:1;
629 uint32_t mra:1;
630 uint32_t mtta:1;
631 uint32_t mrv:8;
632 uint32_t mttv:8;
633 } s;
634 struct cvmx_pci_cfg22_s cn30xx;
635 struct cvmx_pci_cfg22_s cn31xx;
636 struct cvmx_pci_cfg22_s cn38xx;
637 struct cvmx_pci_cfg22_s cn38xxp2;
638 struct cvmx_pci_cfg22_s cn50xx;
639 struct cvmx_pci_cfg22_s cn58xx;
640 struct cvmx_pci_cfg22_s cn58xxp1;
641};
642
643union cvmx_pci_cfg56 {
644 uint32_t u32;
645 struct cvmx_pci_cfg56_s {
646 uint32_t reserved_23_31:9;
647 uint32_t most:3;
648 uint32_t mmbc:2;
649 uint32_t roe:1;
650 uint32_t dpere:1;
651 uint32_t ncp:8;
652 uint32_t pxcid:8;
653 } s;
654 struct cvmx_pci_cfg56_s cn30xx;
655 struct cvmx_pci_cfg56_s cn31xx;
656 struct cvmx_pci_cfg56_s cn38xx;
657 struct cvmx_pci_cfg56_s cn38xxp2;
658 struct cvmx_pci_cfg56_s cn50xx;
659 struct cvmx_pci_cfg56_s cn58xx;
660 struct cvmx_pci_cfg56_s cn58xxp1;
661};
662
663union cvmx_pci_cfg57 {
664 uint32_t u32;
665 struct cvmx_pci_cfg57_s {
666 uint32_t reserved_30_31:2;
667 uint32_t scemr:1;
668 uint32_t mcrsd:3;
669 uint32_t mostd:3;
670 uint32_t mmrbcd:2;
671 uint32_t dc:1;
672 uint32_t usc:1;
673 uint32_t scd:1;
674 uint32_t m133:1;
675 uint32_t w64:1;
676 uint32_t bn:8;
677 uint32_t dn:5;
678 uint32_t fn:3;
679 } s;
680 struct cvmx_pci_cfg57_s cn30xx;
681 struct cvmx_pci_cfg57_s cn31xx;
682 struct cvmx_pci_cfg57_s cn38xx;
683 struct cvmx_pci_cfg57_s cn38xxp2;
684 struct cvmx_pci_cfg57_s cn50xx;
685 struct cvmx_pci_cfg57_s cn58xx;
686 struct cvmx_pci_cfg57_s cn58xxp1;
687};
688
689union cvmx_pci_cfg58 {
690 uint32_t u32;
691 struct cvmx_pci_cfg58_s {
692 uint32_t pmes:5;
693 uint32_t d2s:1;
694 uint32_t d1s:1;
695 uint32_t auxc:3;
696 uint32_t dsi:1;
697 uint32_t reserved_20_20:1;
698 uint32_t pmec:1;
699 uint32_t pcimiv:3;
700 uint32_t ncp:8;
701 uint32_t pmcid:8;
702 } s;
703 struct cvmx_pci_cfg58_s cn30xx;
704 struct cvmx_pci_cfg58_s cn31xx;
705 struct cvmx_pci_cfg58_s cn38xx;
706 struct cvmx_pci_cfg58_s cn38xxp2;
707 struct cvmx_pci_cfg58_s cn50xx;
708 struct cvmx_pci_cfg58_s cn58xx;
709 struct cvmx_pci_cfg58_s cn58xxp1;
710};
711
712union cvmx_pci_cfg59 {
713 uint32_t u32;
714 struct cvmx_pci_cfg59_s {
715 uint32_t pmdia:8;
716 uint32_t bpccen:1;
717 uint32_t bd3h:1;
718 uint32_t reserved_16_21:6;
719 uint32_t pmess:1;
720 uint32_t pmedsia:2;
721 uint32_t pmds:4;
722 uint32_t pmeens:1;
723 uint32_t reserved_2_7:6;
724 uint32_t ps:2;
725 } s;
726 struct cvmx_pci_cfg59_s cn30xx;
727 struct cvmx_pci_cfg59_s cn31xx;
728 struct cvmx_pci_cfg59_s cn38xx;
729 struct cvmx_pci_cfg59_s cn38xxp2;
730 struct cvmx_pci_cfg59_s cn50xx;
731 struct cvmx_pci_cfg59_s cn58xx;
732 struct cvmx_pci_cfg59_s cn58xxp1;
733};
734
735union cvmx_pci_cfg60 {
736 uint32_t u32;
737 struct cvmx_pci_cfg60_s {
738 uint32_t reserved_24_31:8;
739 uint32_t m64:1;
740 uint32_t mme:3;
741 uint32_t mmc:3;
742 uint32_t msien:1;
743 uint32_t ncp:8;
744 uint32_t msicid:8;
745 } s;
746 struct cvmx_pci_cfg60_s cn30xx;
747 struct cvmx_pci_cfg60_s cn31xx;
748 struct cvmx_pci_cfg60_s cn38xx;
749 struct cvmx_pci_cfg60_s cn38xxp2;
750 struct cvmx_pci_cfg60_s cn50xx;
751 struct cvmx_pci_cfg60_s cn58xx;
752 struct cvmx_pci_cfg60_s cn58xxp1;
753};
754
755union cvmx_pci_cfg61 {
756 uint32_t u32;
757 struct cvmx_pci_cfg61_s {
758 uint32_t msi31t2:30;
759 uint32_t reserved_0_1:2;
760 } s;
761 struct cvmx_pci_cfg61_s cn30xx;
762 struct cvmx_pci_cfg61_s cn31xx;
763 struct cvmx_pci_cfg61_s cn38xx;
764 struct cvmx_pci_cfg61_s cn38xxp2;
765 struct cvmx_pci_cfg61_s cn50xx;
766 struct cvmx_pci_cfg61_s cn58xx;
767 struct cvmx_pci_cfg61_s cn58xxp1;
768};
769
770union cvmx_pci_cfg62 {
771 uint32_t u32;
772 struct cvmx_pci_cfg62_s {
773 uint32_t msi:32;
774 } s;
775 struct cvmx_pci_cfg62_s cn30xx;
776 struct cvmx_pci_cfg62_s cn31xx;
777 struct cvmx_pci_cfg62_s cn38xx;
778 struct cvmx_pci_cfg62_s cn38xxp2;
779 struct cvmx_pci_cfg62_s cn50xx;
780 struct cvmx_pci_cfg62_s cn58xx;
781 struct cvmx_pci_cfg62_s cn58xxp1;
782};
783
784union cvmx_pci_cfg63 {
785 uint32_t u32;
786 struct cvmx_pci_cfg63_s {
787 uint32_t reserved_16_31:16;
788 uint32_t msimd:16;
789 } s;
790 struct cvmx_pci_cfg63_s cn30xx;
791 struct cvmx_pci_cfg63_s cn31xx;
792 struct cvmx_pci_cfg63_s cn38xx;
793 struct cvmx_pci_cfg63_s cn38xxp2;
794 struct cvmx_pci_cfg63_s cn50xx;
795 struct cvmx_pci_cfg63_s cn58xx;
796 struct cvmx_pci_cfg63_s cn58xxp1;
797};
798
799union cvmx_pci_cnt_reg {
800 uint64_t u64;
801 struct cvmx_pci_cnt_reg_s {
802 uint64_t reserved_38_63:26;
803 uint64_t hm_pcix:1;
804 uint64_t hm_speed:2;
805 uint64_t ap_pcix:1;
806 uint64_t ap_speed:2;
807 uint64_t pcicnt:32;
808 } s;
809 struct cvmx_pci_cnt_reg_s cn50xx;
810 struct cvmx_pci_cnt_reg_s cn58xx;
811 struct cvmx_pci_cnt_reg_s cn58xxp1;
812};
813
814union cvmx_pci_ctl_status_2 {
815 uint32_t u32;
816 struct cvmx_pci_ctl_status_2_s {
817 uint32_t reserved_29_31:3;
818 uint32_t bb1_hole:3;
819 uint32_t bb1_siz:1;
820 uint32_t bb_ca:1;
821 uint32_t bb_es:2;
822 uint32_t bb1:1;
823 uint32_t bb0:1;
824 uint32_t erst_n:1;
825 uint32_t bar2pres:1;
826 uint32_t scmtyp:1;
827 uint32_t scm:1;
828 uint32_t en_wfilt:1;
829 uint32_t reserved_14_14:1;
830 uint32_t ap_pcix:1;
831 uint32_t ap_64ad:1;
832 uint32_t b12_bist:1;
833 uint32_t pmo_amod:1;
834 uint32_t pmo_fpc:3;
835 uint32_t tsr_hwm:3;
836 uint32_t bar2_enb:1;
837 uint32_t bar2_esx:2;
838 uint32_t bar2_cax:1;
839 } s;
840 struct cvmx_pci_ctl_status_2_s cn30xx;
841 struct cvmx_pci_ctl_status_2_cn31xx {
842 uint32_t reserved_20_31:12;
843 uint32_t erst_n:1;
844 uint32_t bar2pres:1;
845 uint32_t scmtyp:1;
846 uint32_t scm:1;
847 uint32_t en_wfilt:1;
848 uint32_t reserved_14_14:1;
849 uint32_t ap_pcix:1;
850 uint32_t ap_64ad:1;
851 uint32_t b12_bist:1;
852 uint32_t pmo_amod:1;
853 uint32_t pmo_fpc:3;
854 uint32_t tsr_hwm:3;
855 uint32_t bar2_enb:1;
856 uint32_t bar2_esx:2;
857 uint32_t bar2_cax:1;
858 } cn31xx;
859 struct cvmx_pci_ctl_status_2_s cn38xx;
860 struct cvmx_pci_ctl_status_2_cn31xx cn38xxp2;
861 struct cvmx_pci_ctl_status_2_s cn50xx;
862 struct cvmx_pci_ctl_status_2_s cn58xx;
863 struct cvmx_pci_ctl_status_2_s cn58xxp1;
864};
865
866union cvmx_pci_dbellx {
867 uint32_t u32;
868 struct cvmx_pci_dbellx_s {
869 uint32_t reserved_16_31:16;
870 uint32_t inc_val:16;
871 } s;
872 struct cvmx_pci_dbellx_s cn30xx;
873 struct cvmx_pci_dbellx_s cn31xx;
874 struct cvmx_pci_dbellx_s cn38xx;
875 struct cvmx_pci_dbellx_s cn38xxp2;
876 struct cvmx_pci_dbellx_s cn50xx;
877 struct cvmx_pci_dbellx_s cn58xx;
878 struct cvmx_pci_dbellx_s cn58xxp1;
879};
880
881union cvmx_pci_dma_cntx {
882 uint32_t u32;
883 struct cvmx_pci_dma_cntx_s {
884 uint32_t dma_cnt:32;
885 } s;
886 struct cvmx_pci_dma_cntx_s cn30xx;
887 struct cvmx_pci_dma_cntx_s cn31xx;
888 struct cvmx_pci_dma_cntx_s cn38xx;
889 struct cvmx_pci_dma_cntx_s cn38xxp2;
890 struct cvmx_pci_dma_cntx_s cn50xx;
891 struct cvmx_pci_dma_cntx_s cn58xx;
892 struct cvmx_pci_dma_cntx_s cn58xxp1;
893};
894
895union cvmx_pci_dma_int_levx {
896 uint32_t u32;
897 struct cvmx_pci_dma_int_levx_s {
898 uint32_t pkt_cnt:32;
899 } s;
900 struct cvmx_pci_dma_int_levx_s cn30xx;
901 struct cvmx_pci_dma_int_levx_s cn31xx;
902 struct cvmx_pci_dma_int_levx_s cn38xx;
903 struct cvmx_pci_dma_int_levx_s cn38xxp2;
904 struct cvmx_pci_dma_int_levx_s cn50xx;
905 struct cvmx_pci_dma_int_levx_s cn58xx;
906 struct cvmx_pci_dma_int_levx_s cn58xxp1;
907};
908
909union cvmx_pci_dma_timex {
910 uint32_t u32;
911 struct cvmx_pci_dma_timex_s {
912 uint32_t dma_time:32;
913 } s;
914 struct cvmx_pci_dma_timex_s cn30xx;
915 struct cvmx_pci_dma_timex_s cn31xx;
916 struct cvmx_pci_dma_timex_s cn38xx;
917 struct cvmx_pci_dma_timex_s cn38xxp2;
918 struct cvmx_pci_dma_timex_s cn50xx;
919 struct cvmx_pci_dma_timex_s cn58xx;
920 struct cvmx_pci_dma_timex_s cn58xxp1;
921};
922
923union cvmx_pci_instr_countx {
924 uint32_t u32;
925 struct cvmx_pci_instr_countx_s {
926 uint32_t icnt:32;
927 } s;
928 struct cvmx_pci_instr_countx_s cn30xx;
929 struct cvmx_pci_instr_countx_s cn31xx;
930 struct cvmx_pci_instr_countx_s cn38xx;
931 struct cvmx_pci_instr_countx_s cn38xxp2;
932 struct cvmx_pci_instr_countx_s cn50xx;
933 struct cvmx_pci_instr_countx_s cn58xx;
934 struct cvmx_pci_instr_countx_s cn58xxp1;
935};
936
937union cvmx_pci_int_enb {
938 uint64_t u64;
939 struct cvmx_pci_int_enb_s {
940 uint64_t reserved_34_63:30;
941 uint64_t ill_rd:1;
942 uint64_t ill_wr:1;
943 uint64_t win_wr:1;
944 uint64_t dma1_fi:1;
945 uint64_t dma0_fi:1;
946 uint64_t idtime1:1;
947 uint64_t idtime0:1;
948 uint64_t idcnt1:1;
949 uint64_t idcnt0:1;
950 uint64_t iptime3:1;
951 uint64_t iptime2:1;
952 uint64_t iptime1:1;
953 uint64_t iptime0:1;
954 uint64_t ipcnt3:1;
955 uint64_t ipcnt2:1;
956 uint64_t ipcnt1:1;
957 uint64_t ipcnt0:1;
958 uint64_t irsl_int:1;
959 uint64_t ill_rrd:1;
960 uint64_t ill_rwr:1;
961 uint64_t idperr:1;
962 uint64_t iaperr:1;
963 uint64_t iserr:1;
964 uint64_t itsr_abt:1;
965 uint64_t imsc_msg:1;
966 uint64_t imsi_mabt:1;
967 uint64_t imsi_tabt:1;
968 uint64_t imsi_per:1;
969 uint64_t imr_tto:1;
970 uint64_t imr_abt:1;
971 uint64_t itr_abt:1;
972 uint64_t imr_wtto:1;
973 uint64_t imr_wabt:1;
974 uint64_t itr_wabt:1;
975 } s;
976 struct cvmx_pci_int_enb_cn30xx {
977 uint64_t reserved_34_63:30;
978 uint64_t ill_rd:1;
979 uint64_t ill_wr:1;
980 uint64_t win_wr:1;
981 uint64_t dma1_fi:1;
982 uint64_t dma0_fi:1;
983 uint64_t idtime1:1;
984 uint64_t idtime0:1;
985 uint64_t idcnt1:1;
986 uint64_t idcnt0:1;
987 uint64_t reserved_22_24:3;
988 uint64_t iptime0:1;
989 uint64_t reserved_18_20:3;
990 uint64_t ipcnt0:1;
991 uint64_t irsl_int:1;
992 uint64_t ill_rrd:1;
993 uint64_t ill_rwr:1;
994 uint64_t idperr:1;
995 uint64_t iaperr:1;
996 uint64_t iserr:1;
997 uint64_t itsr_abt:1;
998 uint64_t imsc_msg:1;
999 uint64_t imsi_mabt:1;
1000 uint64_t imsi_tabt:1;
1001 uint64_t imsi_per:1;
1002 uint64_t imr_tto:1;
1003 uint64_t imr_abt:1;
1004 uint64_t itr_abt:1;
1005 uint64_t imr_wtto:1;
1006 uint64_t imr_wabt:1;
1007 uint64_t itr_wabt:1;
1008 } cn30xx;
1009 struct cvmx_pci_int_enb_cn31xx {
1010 uint64_t reserved_34_63:30;
1011 uint64_t ill_rd:1;
1012 uint64_t ill_wr:1;
1013 uint64_t win_wr:1;
1014 uint64_t dma1_fi:1;
1015 uint64_t dma0_fi:1;
1016 uint64_t idtime1:1;
1017 uint64_t idtime0:1;
1018 uint64_t idcnt1:1;
1019 uint64_t idcnt0:1;
1020 uint64_t reserved_23_24:2;
1021 uint64_t iptime1:1;
1022 uint64_t iptime0:1;
1023 uint64_t reserved_19_20:2;
1024 uint64_t ipcnt1:1;
1025 uint64_t ipcnt0:1;
1026 uint64_t irsl_int:1;
1027 uint64_t ill_rrd:1;
1028 uint64_t ill_rwr:1;
1029 uint64_t idperr:1;
1030 uint64_t iaperr:1;
1031 uint64_t iserr:1;
1032 uint64_t itsr_abt:1;
1033 uint64_t imsc_msg:1;
1034 uint64_t imsi_mabt:1;
1035 uint64_t imsi_tabt:1;
1036 uint64_t imsi_per:1;
1037 uint64_t imr_tto:1;
1038 uint64_t imr_abt:1;
1039 uint64_t itr_abt:1;
1040 uint64_t imr_wtto:1;
1041 uint64_t imr_wabt:1;
1042 uint64_t itr_wabt:1;
1043 } cn31xx;
1044 struct cvmx_pci_int_enb_s cn38xx;
1045 struct cvmx_pci_int_enb_s cn38xxp2;
1046 struct cvmx_pci_int_enb_cn31xx cn50xx;
1047 struct cvmx_pci_int_enb_s cn58xx;
1048 struct cvmx_pci_int_enb_s cn58xxp1;
1049};
1050
1051union cvmx_pci_int_enb2 {
1052 uint64_t u64;
1053 struct cvmx_pci_int_enb2_s {
1054 uint64_t reserved_34_63:30;
1055 uint64_t ill_rd:1;
1056 uint64_t ill_wr:1;
1057 uint64_t win_wr:1;
1058 uint64_t dma1_fi:1;
1059 uint64_t dma0_fi:1;
1060 uint64_t rdtime1:1;
1061 uint64_t rdtime0:1;
1062 uint64_t rdcnt1:1;
1063 uint64_t rdcnt0:1;
1064 uint64_t rptime3:1;
1065 uint64_t rptime2:1;
1066 uint64_t rptime1:1;
1067 uint64_t rptime0:1;
1068 uint64_t rpcnt3:1;
1069 uint64_t rpcnt2:1;
1070 uint64_t rpcnt1:1;
1071 uint64_t rpcnt0:1;
1072 uint64_t rrsl_int:1;
1073 uint64_t ill_rrd:1;
1074 uint64_t ill_rwr:1;
1075 uint64_t rdperr:1;
1076 uint64_t raperr:1;
1077 uint64_t rserr:1;
1078 uint64_t rtsr_abt:1;
1079 uint64_t rmsc_msg:1;
1080 uint64_t rmsi_mabt:1;
1081 uint64_t rmsi_tabt:1;
1082 uint64_t rmsi_per:1;
1083 uint64_t rmr_tto:1;
1084 uint64_t rmr_abt:1;
1085 uint64_t rtr_abt:1;
1086 uint64_t rmr_wtto:1;
1087 uint64_t rmr_wabt:1;
1088 uint64_t rtr_wabt:1;
1089 } s;
1090 struct cvmx_pci_int_enb2_cn30xx {
1091 uint64_t reserved_34_63:30;
1092 uint64_t ill_rd:1;
1093 uint64_t ill_wr:1;
1094 uint64_t win_wr:1;
1095 uint64_t dma1_fi:1;
1096 uint64_t dma0_fi:1;
1097 uint64_t rdtime1:1;
1098 uint64_t rdtime0:1;
1099 uint64_t rdcnt1:1;
1100 uint64_t rdcnt0:1;
1101 uint64_t reserved_22_24:3;
1102 uint64_t rptime0:1;
1103 uint64_t reserved_18_20:3;
1104 uint64_t rpcnt0:1;
1105 uint64_t rrsl_int:1;
1106 uint64_t ill_rrd:1;
1107 uint64_t ill_rwr:1;
1108 uint64_t rdperr:1;
1109 uint64_t raperr:1;
1110 uint64_t rserr:1;
1111 uint64_t rtsr_abt:1;
1112 uint64_t rmsc_msg:1;
1113 uint64_t rmsi_mabt:1;
1114 uint64_t rmsi_tabt:1;
1115 uint64_t rmsi_per:1;
1116 uint64_t rmr_tto:1;
1117 uint64_t rmr_abt:1;
1118 uint64_t rtr_abt:1;
1119 uint64_t rmr_wtto:1;
1120 uint64_t rmr_wabt:1;
1121 uint64_t rtr_wabt:1;
1122 } cn30xx;
1123 struct cvmx_pci_int_enb2_cn31xx {
1124 uint64_t reserved_34_63:30;
1125 uint64_t ill_rd:1;
1126 uint64_t ill_wr:1;
1127 uint64_t win_wr:1;
1128 uint64_t dma1_fi:1;
1129 uint64_t dma0_fi:1;
1130 uint64_t rdtime1:1;
1131 uint64_t rdtime0:1;
1132 uint64_t rdcnt1:1;
1133 uint64_t rdcnt0:1;
1134 uint64_t reserved_23_24:2;
1135 uint64_t rptime1:1;
1136 uint64_t rptime0:1;
1137 uint64_t reserved_19_20:2;
1138 uint64_t rpcnt1:1;
1139 uint64_t rpcnt0:1;
1140 uint64_t rrsl_int:1;
1141 uint64_t ill_rrd:1;
1142 uint64_t ill_rwr:1;
1143 uint64_t rdperr:1;
1144 uint64_t raperr:1;
1145 uint64_t rserr:1;
1146 uint64_t rtsr_abt:1;
1147 uint64_t rmsc_msg:1;
1148 uint64_t rmsi_mabt:1;
1149 uint64_t rmsi_tabt:1;
1150 uint64_t rmsi_per:1;
1151 uint64_t rmr_tto:1;
1152 uint64_t rmr_abt:1;
1153 uint64_t rtr_abt:1;
1154 uint64_t rmr_wtto:1;
1155 uint64_t rmr_wabt:1;
1156 uint64_t rtr_wabt:1;
1157 } cn31xx;
1158 struct cvmx_pci_int_enb2_s cn38xx;
1159 struct cvmx_pci_int_enb2_s cn38xxp2;
1160 struct cvmx_pci_int_enb2_cn31xx cn50xx;
1161 struct cvmx_pci_int_enb2_s cn58xx;
1162 struct cvmx_pci_int_enb2_s cn58xxp1;
1163};
1164
1165union cvmx_pci_int_sum {
1166 uint64_t u64;
1167 struct cvmx_pci_int_sum_s {
1168 uint64_t reserved_34_63:30;
1169 uint64_t ill_rd:1;
1170 uint64_t ill_wr:1;
1171 uint64_t win_wr:1;
1172 uint64_t dma1_fi:1;
1173 uint64_t dma0_fi:1;
1174 uint64_t dtime1:1;
1175 uint64_t dtime0:1;
1176 uint64_t dcnt1:1;
1177 uint64_t dcnt0:1;
1178 uint64_t ptime3:1;
1179 uint64_t ptime2:1;
1180 uint64_t ptime1:1;
1181 uint64_t ptime0:1;
1182 uint64_t pcnt3:1;
1183 uint64_t pcnt2:1;
1184 uint64_t pcnt1:1;
1185 uint64_t pcnt0:1;
1186 uint64_t rsl_int:1;
1187 uint64_t ill_rrd:1;
1188 uint64_t ill_rwr:1;
1189 uint64_t dperr:1;
1190 uint64_t aperr:1;
1191 uint64_t serr:1;
1192 uint64_t tsr_abt:1;
1193 uint64_t msc_msg:1;
1194 uint64_t msi_mabt:1;
1195 uint64_t msi_tabt:1;
1196 uint64_t msi_per:1;
1197 uint64_t mr_tto:1;
1198 uint64_t mr_abt:1;
1199 uint64_t tr_abt:1;
1200 uint64_t mr_wtto:1;
1201 uint64_t mr_wabt:1;
1202 uint64_t tr_wabt:1;
1203 } s;
1204 struct cvmx_pci_int_sum_cn30xx {
1205 uint64_t reserved_34_63:30;
1206 uint64_t ill_rd:1;
1207 uint64_t ill_wr:1;
1208 uint64_t win_wr:1;
1209 uint64_t dma1_fi:1;
1210 uint64_t dma0_fi:1;
1211 uint64_t dtime1:1;
1212 uint64_t dtime0:1;
1213 uint64_t dcnt1:1;
1214 uint64_t dcnt0:1;
1215 uint64_t reserved_22_24:3;
1216 uint64_t ptime0:1;
1217 uint64_t reserved_18_20:3;
1218 uint64_t pcnt0:1;
1219 uint64_t rsl_int:1;
1220 uint64_t ill_rrd:1;
1221 uint64_t ill_rwr:1;
1222 uint64_t dperr:1;
1223 uint64_t aperr:1;
1224 uint64_t serr:1;
1225 uint64_t tsr_abt:1;
1226 uint64_t msc_msg:1;
1227 uint64_t msi_mabt:1;
1228 uint64_t msi_tabt:1;
1229 uint64_t msi_per:1;
1230 uint64_t mr_tto:1;
1231 uint64_t mr_abt:1;
1232 uint64_t tr_abt:1;
1233 uint64_t mr_wtto:1;
1234 uint64_t mr_wabt:1;
1235 uint64_t tr_wabt:1;
1236 } cn30xx;
1237 struct cvmx_pci_int_sum_cn31xx {
1238 uint64_t reserved_34_63:30;
1239 uint64_t ill_rd:1;
1240 uint64_t ill_wr:1;
1241 uint64_t win_wr:1;
1242 uint64_t dma1_fi:1;
1243 uint64_t dma0_fi:1;
1244 uint64_t dtime1:1;
1245 uint64_t dtime0:1;
1246 uint64_t dcnt1:1;
1247 uint64_t dcnt0:1;
1248 uint64_t reserved_23_24:2;
1249 uint64_t ptime1:1;
1250 uint64_t ptime0:1;
1251 uint64_t reserved_19_20:2;
1252 uint64_t pcnt1:1;
1253 uint64_t pcnt0:1;
1254 uint64_t rsl_int:1;
1255 uint64_t ill_rrd:1;
1256 uint64_t ill_rwr:1;
1257 uint64_t dperr:1;
1258 uint64_t aperr:1;
1259 uint64_t serr:1;
1260 uint64_t tsr_abt:1;
1261 uint64_t msc_msg:1;
1262 uint64_t msi_mabt:1;
1263 uint64_t msi_tabt:1;
1264 uint64_t msi_per:1;
1265 uint64_t mr_tto:1;
1266 uint64_t mr_abt:1;
1267 uint64_t tr_abt:1;
1268 uint64_t mr_wtto:1;
1269 uint64_t mr_wabt:1;
1270 uint64_t tr_wabt:1;
1271 } cn31xx;
1272 struct cvmx_pci_int_sum_s cn38xx;
1273 struct cvmx_pci_int_sum_s cn38xxp2;
1274 struct cvmx_pci_int_sum_cn31xx cn50xx;
1275 struct cvmx_pci_int_sum_s cn58xx;
1276 struct cvmx_pci_int_sum_s cn58xxp1;
1277};
1278
1279union cvmx_pci_int_sum2 {
1280 uint64_t u64;
1281 struct cvmx_pci_int_sum2_s {
1282 uint64_t reserved_34_63:30;
1283 uint64_t ill_rd:1;
1284 uint64_t ill_wr:1;
1285 uint64_t win_wr:1;
1286 uint64_t dma1_fi:1;
1287 uint64_t dma0_fi:1;
1288 uint64_t dtime1:1;
1289 uint64_t dtime0:1;
1290 uint64_t dcnt1:1;
1291 uint64_t dcnt0:1;
1292 uint64_t ptime3:1;
1293 uint64_t ptime2:1;
1294 uint64_t ptime1:1;
1295 uint64_t ptime0:1;
1296 uint64_t pcnt3:1;
1297 uint64_t pcnt2:1;
1298 uint64_t pcnt1:1;
1299 uint64_t pcnt0:1;
1300 uint64_t rsl_int:1;
1301 uint64_t ill_rrd:1;
1302 uint64_t ill_rwr:1;
1303 uint64_t dperr:1;
1304 uint64_t aperr:1;
1305 uint64_t serr:1;
1306 uint64_t tsr_abt:1;
1307 uint64_t msc_msg:1;
1308 uint64_t msi_mabt:1;
1309 uint64_t msi_tabt:1;
1310 uint64_t msi_per:1;
1311 uint64_t mr_tto:1;
1312 uint64_t mr_abt:1;
1313 uint64_t tr_abt:1;
1314 uint64_t mr_wtto:1;
1315 uint64_t mr_wabt:1;
1316 uint64_t tr_wabt:1;
1317 } s;
1318 struct cvmx_pci_int_sum2_cn30xx {
1319 uint64_t reserved_34_63:30;
1320 uint64_t ill_rd:1;
1321 uint64_t ill_wr:1;
1322 uint64_t win_wr:1;
1323 uint64_t dma1_fi:1;
1324 uint64_t dma0_fi:1;
1325 uint64_t dtime1:1;
1326 uint64_t dtime0:1;
1327 uint64_t dcnt1:1;
1328 uint64_t dcnt0:1;
1329 uint64_t reserved_22_24:3;
1330 uint64_t ptime0:1;
1331 uint64_t reserved_18_20:3;
1332 uint64_t pcnt0:1;
1333 uint64_t rsl_int:1;
1334 uint64_t ill_rrd:1;
1335 uint64_t ill_rwr:1;
1336 uint64_t dperr:1;
1337 uint64_t aperr:1;
1338 uint64_t serr:1;
1339 uint64_t tsr_abt:1;
1340 uint64_t msc_msg:1;
1341 uint64_t msi_mabt:1;
1342 uint64_t msi_tabt:1;
1343 uint64_t msi_per:1;
1344 uint64_t mr_tto:1;
1345 uint64_t mr_abt:1;
1346 uint64_t tr_abt:1;
1347 uint64_t mr_wtto:1;
1348 uint64_t mr_wabt:1;
1349 uint64_t tr_wabt:1;
1350 } cn30xx;
1351 struct cvmx_pci_int_sum2_cn31xx {
1352 uint64_t reserved_34_63:30;
1353 uint64_t ill_rd:1;
1354 uint64_t ill_wr:1;
1355 uint64_t win_wr:1;
1356 uint64_t dma1_fi:1;
1357 uint64_t dma0_fi:1;
1358 uint64_t dtime1:1;
1359 uint64_t dtime0:1;
1360 uint64_t dcnt1:1;
1361 uint64_t dcnt0:1;
1362 uint64_t reserved_23_24:2;
1363 uint64_t ptime1:1;
1364 uint64_t ptime0:1;
1365 uint64_t reserved_19_20:2;
1366 uint64_t pcnt1:1;
1367 uint64_t pcnt0:1;
1368 uint64_t rsl_int:1;
1369 uint64_t ill_rrd:1;
1370 uint64_t ill_rwr:1;
1371 uint64_t dperr:1;
1372 uint64_t aperr:1;
1373 uint64_t serr:1;
1374 uint64_t tsr_abt:1;
1375 uint64_t msc_msg:1;
1376 uint64_t msi_mabt:1;
1377 uint64_t msi_tabt:1;
1378 uint64_t msi_per:1;
1379 uint64_t mr_tto:1;
1380 uint64_t mr_abt:1;
1381 uint64_t tr_abt:1;
1382 uint64_t mr_wtto:1;
1383 uint64_t mr_wabt:1;
1384 uint64_t tr_wabt:1;
1385 } cn31xx;
1386 struct cvmx_pci_int_sum2_s cn38xx;
1387 struct cvmx_pci_int_sum2_s cn38xxp2;
1388 struct cvmx_pci_int_sum2_cn31xx cn50xx;
1389 struct cvmx_pci_int_sum2_s cn58xx;
1390 struct cvmx_pci_int_sum2_s cn58xxp1;
1391};
1392
1393union cvmx_pci_msi_rcv {
1394 uint32_t u32;
1395 struct cvmx_pci_msi_rcv_s {
1396 uint32_t reserved_6_31:26;
1397 uint32_t intr:6;
1398 } s;
1399 struct cvmx_pci_msi_rcv_s cn30xx;
1400 struct cvmx_pci_msi_rcv_s cn31xx;
1401 struct cvmx_pci_msi_rcv_s cn38xx;
1402 struct cvmx_pci_msi_rcv_s cn38xxp2;
1403 struct cvmx_pci_msi_rcv_s cn50xx;
1404 struct cvmx_pci_msi_rcv_s cn58xx;
1405 struct cvmx_pci_msi_rcv_s cn58xxp1;
1406};
1407
1408union cvmx_pci_pkt_creditsx {
1409 uint32_t u32;
1410 struct cvmx_pci_pkt_creditsx_s {
1411 uint32_t pkt_cnt:16;
1412 uint32_t ptr_cnt:16;
1413 } s;
1414 struct cvmx_pci_pkt_creditsx_s cn30xx;
1415 struct cvmx_pci_pkt_creditsx_s cn31xx;
1416 struct cvmx_pci_pkt_creditsx_s cn38xx;
1417 struct cvmx_pci_pkt_creditsx_s cn38xxp2;
1418 struct cvmx_pci_pkt_creditsx_s cn50xx;
1419 struct cvmx_pci_pkt_creditsx_s cn58xx;
1420 struct cvmx_pci_pkt_creditsx_s cn58xxp1;
1421};
1422
1423union cvmx_pci_pkts_sentx {
1424 uint32_t u32;
1425 struct cvmx_pci_pkts_sentx_s {
1426 uint32_t pkt_cnt:32;
1427 } s;
1428 struct cvmx_pci_pkts_sentx_s cn30xx;
1429 struct cvmx_pci_pkts_sentx_s cn31xx;
1430 struct cvmx_pci_pkts_sentx_s cn38xx;
1431 struct cvmx_pci_pkts_sentx_s cn38xxp2;
1432 struct cvmx_pci_pkts_sentx_s cn50xx;
1433 struct cvmx_pci_pkts_sentx_s cn58xx;
1434 struct cvmx_pci_pkts_sentx_s cn58xxp1;
1435};
1436
1437union cvmx_pci_pkts_sent_int_levx {
1438 uint32_t u32;
1439 struct cvmx_pci_pkts_sent_int_levx_s {
1440 uint32_t pkt_cnt:32;
1441 } s;
1442 struct cvmx_pci_pkts_sent_int_levx_s cn30xx;
1443 struct cvmx_pci_pkts_sent_int_levx_s cn31xx;
1444 struct cvmx_pci_pkts_sent_int_levx_s cn38xx;
1445 struct cvmx_pci_pkts_sent_int_levx_s cn38xxp2;
1446 struct cvmx_pci_pkts_sent_int_levx_s cn50xx;
1447 struct cvmx_pci_pkts_sent_int_levx_s cn58xx;
1448 struct cvmx_pci_pkts_sent_int_levx_s cn58xxp1;
1449};
1450
1451union cvmx_pci_pkts_sent_timex {
1452 uint32_t u32;
1453 struct cvmx_pci_pkts_sent_timex_s {
1454 uint32_t pkt_time:32;
1455 } s;
1456 struct cvmx_pci_pkts_sent_timex_s cn30xx;
1457 struct cvmx_pci_pkts_sent_timex_s cn31xx;
1458 struct cvmx_pci_pkts_sent_timex_s cn38xx;
1459 struct cvmx_pci_pkts_sent_timex_s cn38xxp2;
1460 struct cvmx_pci_pkts_sent_timex_s cn50xx;
1461 struct cvmx_pci_pkts_sent_timex_s cn58xx;
1462 struct cvmx_pci_pkts_sent_timex_s cn58xxp1;
1463};
1464
1465union cvmx_pci_read_cmd_6 {
1466 uint32_t u32;
1467 struct cvmx_pci_read_cmd_6_s {
1468 uint32_t reserved_9_31:23;
1469 uint32_t min_data:6;
1470 uint32_t prefetch:3;
1471 } s;
1472 struct cvmx_pci_read_cmd_6_s cn30xx;
1473 struct cvmx_pci_read_cmd_6_s cn31xx;
1474 struct cvmx_pci_read_cmd_6_s cn38xx;
1475 struct cvmx_pci_read_cmd_6_s cn38xxp2;
1476 struct cvmx_pci_read_cmd_6_s cn50xx;
1477 struct cvmx_pci_read_cmd_6_s cn58xx;
1478 struct cvmx_pci_read_cmd_6_s cn58xxp1;
1479};
1480
1481union cvmx_pci_read_cmd_c {
1482 uint32_t u32;
1483 struct cvmx_pci_read_cmd_c_s {
1484 uint32_t reserved_9_31:23;
1485 uint32_t min_data:6;
1486 uint32_t prefetch:3;
1487 } s;
1488 struct cvmx_pci_read_cmd_c_s cn30xx;
1489 struct cvmx_pci_read_cmd_c_s cn31xx;
1490 struct cvmx_pci_read_cmd_c_s cn38xx;
1491 struct cvmx_pci_read_cmd_c_s cn38xxp2;
1492 struct cvmx_pci_read_cmd_c_s cn50xx;
1493 struct cvmx_pci_read_cmd_c_s cn58xx;
1494 struct cvmx_pci_read_cmd_c_s cn58xxp1;
1495};
1496
1497union cvmx_pci_read_cmd_e {
1498 uint32_t u32;
1499 struct cvmx_pci_read_cmd_e_s {
1500 uint32_t reserved_9_31:23;
1501 uint32_t min_data:6;
1502 uint32_t prefetch:3;
1503 } s;
1504 struct cvmx_pci_read_cmd_e_s cn30xx;
1505 struct cvmx_pci_read_cmd_e_s cn31xx;
1506 struct cvmx_pci_read_cmd_e_s cn38xx;
1507 struct cvmx_pci_read_cmd_e_s cn38xxp2;
1508 struct cvmx_pci_read_cmd_e_s cn50xx;
1509 struct cvmx_pci_read_cmd_e_s cn58xx;
1510 struct cvmx_pci_read_cmd_e_s cn58xxp1;
1511};
1512
1513union cvmx_pci_read_timeout {
1514 uint64_t u64;
1515 struct cvmx_pci_read_timeout_s {
1516 uint64_t reserved_32_63:32;
1517 uint64_t enb:1;
1518 uint64_t cnt:31;
1519 } s;
1520 struct cvmx_pci_read_timeout_s cn30xx;
1521 struct cvmx_pci_read_timeout_s cn31xx;
1522 struct cvmx_pci_read_timeout_s cn38xx;
1523 struct cvmx_pci_read_timeout_s cn38xxp2;
1524 struct cvmx_pci_read_timeout_s cn50xx;
1525 struct cvmx_pci_read_timeout_s cn58xx;
1526 struct cvmx_pci_read_timeout_s cn58xxp1;
1527};
1528
1529union cvmx_pci_scm_reg {
1530 uint64_t u64;
1531 struct cvmx_pci_scm_reg_s {
1532 uint64_t reserved_32_63:32;
1533 uint64_t scm:32;
1534 } s;
1535 struct cvmx_pci_scm_reg_s cn30xx;
1536 struct cvmx_pci_scm_reg_s cn31xx;
1537 struct cvmx_pci_scm_reg_s cn38xx;
1538 struct cvmx_pci_scm_reg_s cn38xxp2;
1539 struct cvmx_pci_scm_reg_s cn50xx;
1540 struct cvmx_pci_scm_reg_s cn58xx;
1541 struct cvmx_pci_scm_reg_s cn58xxp1;
1542};
1543
1544union cvmx_pci_tsr_reg {
1545 uint64_t u64;
1546 struct cvmx_pci_tsr_reg_s {
1547 uint64_t reserved_36_63:28;
1548 uint64_t tsr:36;
1549 } s;
1550 struct cvmx_pci_tsr_reg_s cn30xx;
1551 struct cvmx_pci_tsr_reg_s cn31xx;
1552 struct cvmx_pci_tsr_reg_s cn38xx;
1553 struct cvmx_pci_tsr_reg_s cn38xxp2;
1554 struct cvmx_pci_tsr_reg_s cn50xx;
1555 struct cvmx_pci_tsr_reg_s cn58xx;
1556 struct cvmx_pci_tsr_reg_s cn58xxp1;
1557};
1558
1559union cvmx_pci_win_rd_addr {
1560 uint64_t u64;
1561 struct cvmx_pci_win_rd_addr_s {
1562 uint64_t reserved_49_63:15;
1563 uint64_t iobit:1;
1564 uint64_t reserved_0_47:48;
1565 } s;
1566 struct cvmx_pci_win_rd_addr_cn30xx {
1567 uint64_t reserved_49_63:15;
1568 uint64_t iobit:1;
1569 uint64_t rd_addr:46;
1570 uint64_t reserved_0_1:2;
1571 } cn30xx;
1572 struct cvmx_pci_win_rd_addr_cn30xx cn31xx;
1573 struct cvmx_pci_win_rd_addr_cn38xx {
1574 uint64_t reserved_49_63:15;
1575 uint64_t iobit:1;
1576 uint64_t rd_addr:45;
1577 uint64_t reserved_0_2:3;
1578 } cn38xx;
1579 struct cvmx_pci_win_rd_addr_cn38xx cn38xxp2;
1580 struct cvmx_pci_win_rd_addr_cn30xx cn50xx;
1581 struct cvmx_pci_win_rd_addr_cn38xx cn58xx;
1582 struct cvmx_pci_win_rd_addr_cn38xx cn58xxp1;
1583};
1584
1585union cvmx_pci_win_rd_data {
1586 uint64_t u64;
1587 struct cvmx_pci_win_rd_data_s {
1588 uint64_t rd_data:64;
1589 } s;
1590 struct cvmx_pci_win_rd_data_s cn30xx;
1591 struct cvmx_pci_win_rd_data_s cn31xx;
1592 struct cvmx_pci_win_rd_data_s cn38xx;
1593 struct cvmx_pci_win_rd_data_s cn38xxp2;
1594 struct cvmx_pci_win_rd_data_s cn50xx;
1595 struct cvmx_pci_win_rd_data_s cn58xx;
1596 struct cvmx_pci_win_rd_data_s cn58xxp1;
1597};
1598
1599union cvmx_pci_win_wr_addr {
1600 uint64_t u64;
1601 struct cvmx_pci_win_wr_addr_s {
1602 uint64_t reserved_49_63:15;
1603 uint64_t iobit:1;
1604 uint64_t wr_addr:45;
1605 uint64_t reserved_0_2:3;
1606 } s;
1607 struct cvmx_pci_win_wr_addr_s cn30xx;
1608 struct cvmx_pci_win_wr_addr_s cn31xx;
1609 struct cvmx_pci_win_wr_addr_s cn38xx;
1610 struct cvmx_pci_win_wr_addr_s cn38xxp2;
1611 struct cvmx_pci_win_wr_addr_s cn50xx;
1612 struct cvmx_pci_win_wr_addr_s cn58xx;
1613 struct cvmx_pci_win_wr_addr_s cn58xxp1;
1614};
1615
1616union cvmx_pci_win_wr_data {
1617 uint64_t u64;
1618 struct cvmx_pci_win_wr_data_s {
1619 uint64_t wr_data:64;
1620 } s;
1621 struct cvmx_pci_win_wr_data_s cn30xx;
1622 struct cvmx_pci_win_wr_data_s cn31xx;
1623 struct cvmx_pci_win_wr_data_s cn38xx;
1624 struct cvmx_pci_win_wr_data_s cn38xxp2;
1625 struct cvmx_pci_win_wr_data_s cn50xx;
1626 struct cvmx_pci_win_wr_data_s cn58xx;
1627 struct cvmx_pci_win_wr_data_s cn58xxp1;
1628};
1629
1630union cvmx_pci_win_wr_mask {
1631 uint64_t u64;
1632 struct cvmx_pci_win_wr_mask_s {
1633 uint64_t reserved_8_63:56;
1634 uint64_t wr_mask:8;
1635 } s;
1636 struct cvmx_pci_win_wr_mask_s cn30xx;
1637 struct cvmx_pci_win_wr_mask_s cn31xx;
1638 struct cvmx_pci_win_wr_mask_s cn38xx;
1639 struct cvmx_pci_win_wr_mask_s cn38xxp2;
1640 struct cvmx_pci_win_wr_mask_s cn50xx;
1641 struct cvmx_pci_win_wr_mask_s cn58xx;
1642 struct cvmx_pci_win_wr_mask_s cn58xxp1;
1643};
1644
1645#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
new file mode 100644
index 000000000000..d553f8e88df6
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
@@ -0,0 +1,1365 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCIEEP_DEFS_H__
29#define __CVMX_PCIEEP_DEFS_H__
30
31#define CVMX_PCIEEP_CFG000 \
32 (0x0000000000000000ull)
33#define CVMX_PCIEEP_CFG001 \
34 (0x0000000000000004ull)
35#define CVMX_PCIEEP_CFG002 \
36 (0x0000000000000008ull)
37#define CVMX_PCIEEP_CFG003 \
38 (0x000000000000000Cull)
39#define CVMX_PCIEEP_CFG004 \
40 (0x0000000000000010ull)
41#define CVMX_PCIEEP_CFG004_MASK \
42 (0x0000000080000010ull)
43#define CVMX_PCIEEP_CFG005 \
44 (0x0000000000000014ull)
45#define CVMX_PCIEEP_CFG005_MASK \
46 (0x0000000080000014ull)
47#define CVMX_PCIEEP_CFG006 \
48 (0x0000000000000018ull)
49#define CVMX_PCIEEP_CFG006_MASK \
50 (0x0000000080000018ull)
51#define CVMX_PCIEEP_CFG007 \
52 (0x000000000000001Cull)
53#define CVMX_PCIEEP_CFG007_MASK \
54 (0x000000008000001Cull)
55#define CVMX_PCIEEP_CFG008 \
56 (0x0000000000000020ull)
57#define CVMX_PCIEEP_CFG008_MASK \
58 (0x0000000080000020ull)
59#define CVMX_PCIEEP_CFG009 \
60 (0x0000000000000024ull)
61#define CVMX_PCIEEP_CFG009_MASK \
62 (0x0000000080000024ull)
63#define CVMX_PCIEEP_CFG010 \
64 (0x0000000000000028ull)
65#define CVMX_PCIEEP_CFG011 \
66 (0x000000000000002Cull)
67#define CVMX_PCIEEP_CFG012 \
68 (0x0000000000000030ull)
69#define CVMX_PCIEEP_CFG012_MASK \
70 (0x0000000080000030ull)
71#define CVMX_PCIEEP_CFG013 \
72 (0x0000000000000034ull)
73#define CVMX_PCIEEP_CFG015 \
74 (0x000000000000003Cull)
75#define CVMX_PCIEEP_CFG016 \
76 (0x0000000000000040ull)
77#define CVMX_PCIEEP_CFG017 \
78 (0x0000000000000044ull)
79#define CVMX_PCIEEP_CFG020 \
80 (0x0000000000000050ull)
81#define CVMX_PCIEEP_CFG021 \
82 (0x0000000000000054ull)
83#define CVMX_PCIEEP_CFG022 \
84 (0x0000000000000058ull)
85#define CVMX_PCIEEP_CFG023 \
86 (0x000000000000005Cull)
87#define CVMX_PCIEEP_CFG028 \
88 (0x0000000000000070ull)
89#define CVMX_PCIEEP_CFG029 \
90 (0x0000000000000074ull)
91#define CVMX_PCIEEP_CFG030 \
92 (0x0000000000000078ull)
93#define CVMX_PCIEEP_CFG031 \
94 (0x000000000000007Cull)
95#define CVMX_PCIEEP_CFG032 \
96 (0x0000000000000080ull)
97#define CVMX_PCIEEP_CFG033 \
98 (0x0000000000000084ull)
99#define CVMX_PCIEEP_CFG034 \
100 (0x0000000000000088ull)
101#define CVMX_PCIEEP_CFG037 \
102 (0x0000000000000094ull)
103#define CVMX_PCIEEP_CFG038 \
104 (0x0000000000000098ull)
105#define CVMX_PCIEEP_CFG039 \
106 (0x000000000000009Cull)
107#define CVMX_PCIEEP_CFG040 \
108 (0x00000000000000A0ull)
109#define CVMX_PCIEEP_CFG041 \
110 (0x00000000000000A4ull)
111#define CVMX_PCIEEP_CFG042 \
112 (0x00000000000000A8ull)
113#define CVMX_PCIEEP_CFG064 \
114 (0x0000000000000100ull)
115#define CVMX_PCIEEP_CFG065 \
116 (0x0000000000000104ull)
117#define CVMX_PCIEEP_CFG066 \
118 (0x0000000000000108ull)
119#define CVMX_PCIEEP_CFG067 \
120 (0x000000000000010Cull)
121#define CVMX_PCIEEP_CFG068 \
122 (0x0000000000000110ull)
123#define CVMX_PCIEEP_CFG069 \
124 (0x0000000000000114ull)
125#define CVMX_PCIEEP_CFG070 \
126 (0x0000000000000118ull)
127#define CVMX_PCIEEP_CFG071 \
128 (0x000000000000011Cull)
129#define CVMX_PCIEEP_CFG072 \
130 (0x0000000000000120ull)
131#define CVMX_PCIEEP_CFG073 \
132 (0x0000000000000124ull)
133#define CVMX_PCIEEP_CFG074 \
134 (0x0000000000000128ull)
135#define CVMX_PCIEEP_CFG448 \
136 (0x0000000000000700ull)
137#define CVMX_PCIEEP_CFG449 \
138 (0x0000000000000704ull)
139#define CVMX_PCIEEP_CFG450 \
140 (0x0000000000000708ull)
141#define CVMX_PCIEEP_CFG451 \
142 (0x000000000000070Cull)
143#define CVMX_PCIEEP_CFG452 \
144 (0x0000000000000710ull)
145#define CVMX_PCIEEP_CFG453 \
146 (0x0000000000000714ull)
147#define CVMX_PCIEEP_CFG454 \
148 (0x0000000000000718ull)
149#define CVMX_PCIEEP_CFG455 \
150 (0x000000000000071Cull)
151#define CVMX_PCIEEP_CFG456 \
152 (0x0000000000000720ull)
153#define CVMX_PCIEEP_CFG458 \
154 (0x0000000000000728ull)
155#define CVMX_PCIEEP_CFG459 \
156 (0x000000000000072Cull)
157#define CVMX_PCIEEP_CFG460 \
158 (0x0000000000000730ull)
159#define CVMX_PCIEEP_CFG461 \
160 (0x0000000000000734ull)
161#define CVMX_PCIEEP_CFG462 \
162 (0x0000000000000738ull)
163#define CVMX_PCIEEP_CFG463 \
164 (0x000000000000073Cull)
165#define CVMX_PCIEEP_CFG464 \
166 (0x0000000000000740ull)
167#define CVMX_PCIEEP_CFG465 \
168 (0x0000000000000744ull)
169#define CVMX_PCIEEP_CFG466 \
170 (0x0000000000000748ull)
171#define CVMX_PCIEEP_CFG467 \
172 (0x000000000000074Cull)
173#define CVMX_PCIEEP_CFG468 \
174 (0x0000000000000750ull)
175#define CVMX_PCIEEP_CFG490 \
176 (0x00000000000007A8ull)
177#define CVMX_PCIEEP_CFG491 \
178 (0x00000000000007ACull)
179#define CVMX_PCIEEP_CFG492 \
180 (0x00000000000007B0ull)
181#define CVMX_PCIEEP_CFG516 \
182 (0x0000000000000810ull)
183#define CVMX_PCIEEP_CFG517 \
184 (0x0000000000000814ull)
185
186union cvmx_pcieep_cfg000 {
187 uint32_t u32;
188 struct cvmx_pcieep_cfg000_s {
189 uint32_t devid:16;
190 uint32_t vendid:16;
191 } s;
192 struct cvmx_pcieep_cfg000_s cn52xx;
193 struct cvmx_pcieep_cfg000_s cn52xxp1;
194 struct cvmx_pcieep_cfg000_s cn56xx;
195 struct cvmx_pcieep_cfg000_s cn56xxp1;
196};
197
198union cvmx_pcieep_cfg001 {
199 uint32_t u32;
200 struct cvmx_pcieep_cfg001_s {
201 uint32_t dpe:1;
202 uint32_t sse:1;
203 uint32_t rma:1;
204 uint32_t rta:1;
205 uint32_t sta:1;
206 uint32_t devt:2;
207 uint32_t mdpe:1;
208 uint32_t fbb:1;
209 uint32_t reserved_22_22:1;
210 uint32_t m66:1;
211 uint32_t cl:1;
212 uint32_t i_stat:1;
213 uint32_t reserved_11_18:8;
214 uint32_t i_dis:1;
215 uint32_t fbbe:1;
216 uint32_t see:1;
217 uint32_t ids_wcc:1;
218 uint32_t per:1;
219 uint32_t vps:1;
220 uint32_t mwice:1;
221 uint32_t scse:1;
222 uint32_t me:1;
223 uint32_t msae:1;
224 uint32_t isae:1;
225 } s;
226 struct cvmx_pcieep_cfg001_s cn52xx;
227 struct cvmx_pcieep_cfg001_s cn52xxp1;
228 struct cvmx_pcieep_cfg001_s cn56xx;
229 struct cvmx_pcieep_cfg001_s cn56xxp1;
230};
231
232union cvmx_pcieep_cfg002 {
233 uint32_t u32;
234 struct cvmx_pcieep_cfg002_s {
235 uint32_t bcc:8;
236 uint32_t sc:8;
237 uint32_t pi:8;
238 uint32_t rid:8;
239 } s;
240 struct cvmx_pcieep_cfg002_s cn52xx;
241 struct cvmx_pcieep_cfg002_s cn52xxp1;
242 struct cvmx_pcieep_cfg002_s cn56xx;
243 struct cvmx_pcieep_cfg002_s cn56xxp1;
244};
245
246union cvmx_pcieep_cfg003 {
247 uint32_t u32;
248 struct cvmx_pcieep_cfg003_s {
249 uint32_t bist:8;
250 uint32_t mfd:1;
251 uint32_t chf:7;
252 uint32_t lt:8;
253 uint32_t cls:8;
254 } s;
255 struct cvmx_pcieep_cfg003_s cn52xx;
256 struct cvmx_pcieep_cfg003_s cn52xxp1;
257 struct cvmx_pcieep_cfg003_s cn56xx;
258 struct cvmx_pcieep_cfg003_s cn56xxp1;
259};
260
261union cvmx_pcieep_cfg004 {
262 uint32_t u32;
263 struct cvmx_pcieep_cfg004_s {
264 uint32_t lbab:18;
265 uint32_t reserved_4_13:10;
266 uint32_t pf:1;
267 uint32_t typ:2;
268 uint32_t mspc:1;
269 } s;
270 struct cvmx_pcieep_cfg004_s cn52xx;
271 struct cvmx_pcieep_cfg004_s cn52xxp1;
272 struct cvmx_pcieep_cfg004_s cn56xx;
273 struct cvmx_pcieep_cfg004_s cn56xxp1;
274};
275
276union cvmx_pcieep_cfg004_mask {
277 uint32_t u32;
278 struct cvmx_pcieep_cfg004_mask_s {
279 uint32_t lmask:31;
280 uint32_t enb:1;
281 } s;
282 struct cvmx_pcieep_cfg004_mask_s cn52xx;
283 struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
284 struct cvmx_pcieep_cfg004_mask_s cn56xx;
285 struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
286};
287
288union cvmx_pcieep_cfg005 {
289 uint32_t u32;
290 struct cvmx_pcieep_cfg005_s {
291 uint32_t ubab:32;
292 } s;
293 struct cvmx_pcieep_cfg005_s cn52xx;
294 struct cvmx_pcieep_cfg005_s cn52xxp1;
295 struct cvmx_pcieep_cfg005_s cn56xx;
296 struct cvmx_pcieep_cfg005_s cn56xxp1;
297};
298
299union cvmx_pcieep_cfg005_mask {
300 uint32_t u32;
301 struct cvmx_pcieep_cfg005_mask_s {
302 uint32_t umask:32;
303 } s;
304 struct cvmx_pcieep_cfg005_mask_s cn52xx;
305 struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
306 struct cvmx_pcieep_cfg005_mask_s cn56xx;
307 struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
308};
309
310union cvmx_pcieep_cfg006 {
311 uint32_t u32;
312 struct cvmx_pcieep_cfg006_s {
313 uint32_t lbab:6;
314 uint32_t reserved_4_25:22;
315 uint32_t pf:1;
316 uint32_t typ:2;
317 uint32_t mspc:1;
318 } s;
319 struct cvmx_pcieep_cfg006_s cn52xx;
320 struct cvmx_pcieep_cfg006_s cn52xxp1;
321 struct cvmx_pcieep_cfg006_s cn56xx;
322 struct cvmx_pcieep_cfg006_s cn56xxp1;
323};
324
325union cvmx_pcieep_cfg006_mask {
326 uint32_t u32;
327 struct cvmx_pcieep_cfg006_mask_s {
328 uint32_t lmask:31;
329 uint32_t enb:1;
330 } s;
331 struct cvmx_pcieep_cfg006_mask_s cn52xx;
332 struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
333 struct cvmx_pcieep_cfg006_mask_s cn56xx;
334 struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
335};
336
337union cvmx_pcieep_cfg007 {
338 uint32_t u32;
339 struct cvmx_pcieep_cfg007_s {
340 uint32_t ubab:32;
341 } s;
342 struct cvmx_pcieep_cfg007_s cn52xx;
343 struct cvmx_pcieep_cfg007_s cn52xxp1;
344 struct cvmx_pcieep_cfg007_s cn56xx;
345 struct cvmx_pcieep_cfg007_s cn56xxp1;
346};
347
348union cvmx_pcieep_cfg007_mask {
349 uint32_t u32;
350 struct cvmx_pcieep_cfg007_mask_s {
351 uint32_t umask:32;
352 } s;
353 struct cvmx_pcieep_cfg007_mask_s cn52xx;
354 struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
355 struct cvmx_pcieep_cfg007_mask_s cn56xx;
356 struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
357};
358
359union cvmx_pcieep_cfg008 {
360 uint32_t u32;
361 struct cvmx_pcieep_cfg008_s {
362 uint32_t reserved_4_31:28;
363 uint32_t pf:1;
364 uint32_t typ:2;
365 uint32_t mspc:1;
366 } s;
367 struct cvmx_pcieep_cfg008_s cn52xx;
368 struct cvmx_pcieep_cfg008_s cn52xxp1;
369 struct cvmx_pcieep_cfg008_s cn56xx;
370 struct cvmx_pcieep_cfg008_s cn56xxp1;
371};
372
373union cvmx_pcieep_cfg008_mask {
374 uint32_t u32;
375 struct cvmx_pcieep_cfg008_mask_s {
376 uint32_t lmask:31;
377 uint32_t enb:1;
378 } s;
379 struct cvmx_pcieep_cfg008_mask_s cn52xx;
380 struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
381 struct cvmx_pcieep_cfg008_mask_s cn56xx;
382 struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
383};
384
385union cvmx_pcieep_cfg009 {
386 uint32_t u32;
387 struct cvmx_pcieep_cfg009_s {
388 uint32_t ubab:25;
389 uint32_t reserved_0_6:7;
390 } s;
391 struct cvmx_pcieep_cfg009_s cn52xx;
392 struct cvmx_pcieep_cfg009_s cn52xxp1;
393 struct cvmx_pcieep_cfg009_s cn56xx;
394 struct cvmx_pcieep_cfg009_s cn56xxp1;
395};
396
397union cvmx_pcieep_cfg009_mask {
398 uint32_t u32;
399 struct cvmx_pcieep_cfg009_mask_s {
400 uint32_t umask:32;
401 } s;
402 struct cvmx_pcieep_cfg009_mask_s cn52xx;
403 struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
404 struct cvmx_pcieep_cfg009_mask_s cn56xx;
405 struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
406};
407
408union cvmx_pcieep_cfg010 {
409 uint32_t u32;
410 struct cvmx_pcieep_cfg010_s {
411 uint32_t cisp:32;
412 } s;
413 struct cvmx_pcieep_cfg010_s cn52xx;
414 struct cvmx_pcieep_cfg010_s cn52xxp1;
415 struct cvmx_pcieep_cfg010_s cn56xx;
416 struct cvmx_pcieep_cfg010_s cn56xxp1;
417};
418
419union cvmx_pcieep_cfg011 {
420 uint32_t u32;
421 struct cvmx_pcieep_cfg011_s {
422 uint32_t ssid:16;
423 uint32_t ssvid:16;
424 } s;
425 struct cvmx_pcieep_cfg011_s cn52xx;
426 struct cvmx_pcieep_cfg011_s cn52xxp1;
427 struct cvmx_pcieep_cfg011_s cn56xx;
428 struct cvmx_pcieep_cfg011_s cn56xxp1;
429};
430
431union cvmx_pcieep_cfg012 {
432 uint32_t u32;
433 struct cvmx_pcieep_cfg012_s {
434 uint32_t eraddr:16;
435 uint32_t reserved_1_15:15;
436 uint32_t er_en:1;
437 } s;
438 struct cvmx_pcieep_cfg012_s cn52xx;
439 struct cvmx_pcieep_cfg012_s cn52xxp1;
440 struct cvmx_pcieep_cfg012_s cn56xx;
441 struct cvmx_pcieep_cfg012_s cn56xxp1;
442};
443
444union cvmx_pcieep_cfg012_mask {
445 uint32_t u32;
446 struct cvmx_pcieep_cfg012_mask_s {
447 uint32_t mask:31;
448 uint32_t enb:1;
449 } s;
450 struct cvmx_pcieep_cfg012_mask_s cn52xx;
451 struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
452 struct cvmx_pcieep_cfg012_mask_s cn56xx;
453 struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
454};
455
456union cvmx_pcieep_cfg013 {
457 uint32_t u32;
458 struct cvmx_pcieep_cfg013_s {
459 uint32_t reserved_8_31:24;
460 uint32_t cp:8;
461 } s;
462 struct cvmx_pcieep_cfg013_s cn52xx;
463 struct cvmx_pcieep_cfg013_s cn52xxp1;
464 struct cvmx_pcieep_cfg013_s cn56xx;
465 struct cvmx_pcieep_cfg013_s cn56xxp1;
466};
467
468union cvmx_pcieep_cfg015 {
469 uint32_t u32;
470 struct cvmx_pcieep_cfg015_s {
471 uint32_t ml:8;
472 uint32_t mg:8;
473 uint32_t inta:8;
474 uint32_t il:8;
475 } s;
476 struct cvmx_pcieep_cfg015_s cn52xx;
477 struct cvmx_pcieep_cfg015_s cn52xxp1;
478 struct cvmx_pcieep_cfg015_s cn56xx;
479 struct cvmx_pcieep_cfg015_s cn56xxp1;
480};
481
482union cvmx_pcieep_cfg016 {
483 uint32_t u32;
484 struct cvmx_pcieep_cfg016_s {
485 uint32_t pmes:5;
486 uint32_t d2s:1;
487 uint32_t d1s:1;
488 uint32_t auxc:3;
489 uint32_t dsi:1;
490 uint32_t reserved_20_20:1;
491 uint32_t pme_clock:1;
492 uint32_t pmsv:3;
493 uint32_t ncp:8;
494 uint32_t pmcid:8;
495 } s;
496 struct cvmx_pcieep_cfg016_s cn52xx;
497 struct cvmx_pcieep_cfg016_s cn52xxp1;
498 struct cvmx_pcieep_cfg016_s cn56xx;
499 struct cvmx_pcieep_cfg016_s cn56xxp1;
500};
501
502union cvmx_pcieep_cfg017 {
503 uint32_t u32;
504 struct cvmx_pcieep_cfg017_s {
505 uint32_t pmdia:8;
506 uint32_t bpccee:1;
507 uint32_t bd3h:1;
508 uint32_t reserved_16_21:6;
509 uint32_t pmess:1;
510 uint32_t pmedsia:2;
511 uint32_t pmds:4;
512 uint32_t pmeens:1;
513 uint32_t reserved_4_7:4;
514 uint32_t nsr:1;
515 uint32_t reserved_2_2:1;
516 uint32_t ps:2;
517 } s;
518 struct cvmx_pcieep_cfg017_s cn52xx;
519 struct cvmx_pcieep_cfg017_s cn52xxp1;
520 struct cvmx_pcieep_cfg017_s cn56xx;
521 struct cvmx_pcieep_cfg017_s cn56xxp1;
522};
523
524union cvmx_pcieep_cfg020 {
525 uint32_t u32;
526 struct cvmx_pcieep_cfg020_s {
527 uint32_t reserved_24_31:8;
528 uint32_t m64:1;
529 uint32_t mme:3;
530 uint32_t mmc:3;
531 uint32_t msien:1;
532 uint32_t ncp:8;
533 uint32_t msicid:8;
534 } s;
535 struct cvmx_pcieep_cfg020_s cn52xx;
536 struct cvmx_pcieep_cfg020_s cn52xxp1;
537 struct cvmx_pcieep_cfg020_s cn56xx;
538 struct cvmx_pcieep_cfg020_s cn56xxp1;
539};
540
541union cvmx_pcieep_cfg021 {
542 uint32_t u32;
543 struct cvmx_pcieep_cfg021_s {
544 uint32_t lmsi:30;
545 uint32_t reserved_0_1:2;
546 } s;
547 struct cvmx_pcieep_cfg021_s cn52xx;
548 struct cvmx_pcieep_cfg021_s cn52xxp1;
549 struct cvmx_pcieep_cfg021_s cn56xx;
550 struct cvmx_pcieep_cfg021_s cn56xxp1;
551};
552
553union cvmx_pcieep_cfg022 {
554 uint32_t u32;
555 struct cvmx_pcieep_cfg022_s {
556 uint32_t umsi:32;
557 } s;
558 struct cvmx_pcieep_cfg022_s cn52xx;
559 struct cvmx_pcieep_cfg022_s cn52xxp1;
560 struct cvmx_pcieep_cfg022_s cn56xx;
561 struct cvmx_pcieep_cfg022_s cn56xxp1;
562};
563
564union cvmx_pcieep_cfg023 {
565 uint32_t u32;
566 struct cvmx_pcieep_cfg023_s {
567 uint32_t reserved_16_31:16;
568 uint32_t msimd:16;
569 } s;
570 struct cvmx_pcieep_cfg023_s cn52xx;
571 struct cvmx_pcieep_cfg023_s cn52xxp1;
572 struct cvmx_pcieep_cfg023_s cn56xx;
573 struct cvmx_pcieep_cfg023_s cn56xxp1;
574};
575
576union cvmx_pcieep_cfg028 {
577 uint32_t u32;
578 struct cvmx_pcieep_cfg028_s {
579 uint32_t reserved_30_31:2;
580 uint32_t imn:5;
581 uint32_t si:1;
582 uint32_t dpt:4;
583 uint32_t pciecv:4;
584 uint32_t ncp:8;
585 uint32_t pcieid:8;
586 } s;
587 struct cvmx_pcieep_cfg028_s cn52xx;
588 struct cvmx_pcieep_cfg028_s cn52xxp1;
589 struct cvmx_pcieep_cfg028_s cn56xx;
590 struct cvmx_pcieep_cfg028_s cn56xxp1;
591};
592
593union cvmx_pcieep_cfg029 {
594 uint32_t u32;
595 struct cvmx_pcieep_cfg029_s {
596 uint32_t reserved_28_31:4;
597 uint32_t cspls:2;
598 uint32_t csplv:8;
599 uint32_t reserved_16_17:2;
600 uint32_t rber:1;
601 uint32_t reserved_12_14:3;
602 uint32_t el1al:3;
603 uint32_t el0al:3;
604 uint32_t etfs:1;
605 uint32_t pfs:2;
606 uint32_t mpss:3;
607 } s;
608 struct cvmx_pcieep_cfg029_s cn52xx;
609 struct cvmx_pcieep_cfg029_s cn52xxp1;
610 struct cvmx_pcieep_cfg029_s cn56xx;
611 struct cvmx_pcieep_cfg029_s cn56xxp1;
612};
613
614union cvmx_pcieep_cfg030 {
615 uint32_t u32;
616 struct cvmx_pcieep_cfg030_s {
617 uint32_t reserved_22_31:10;
618 uint32_t tp:1;
619 uint32_t ap_d:1;
620 uint32_t ur_d:1;
621 uint32_t fe_d:1;
622 uint32_t nfe_d:1;
623 uint32_t ce_d:1;
624 uint32_t reserved_15_15:1;
625 uint32_t mrrs:3;
626 uint32_t ns_en:1;
627 uint32_t ap_en:1;
628 uint32_t pf_en:1;
629 uint32_t etf_en:1;
630 uint32_t mps:3;
631 uint32_t ro_en:1;
632 uint32_t ur_en:1;
633 uint32_t fe_en:1;
634 uint32_t nfe_en:1;
635 uint32_t ce_en:1;
636 } s;
637 struct cvmx_pcieep_cfg030_s cn52xx;
638 struct cvmx_pcieep_cfg030_s cn52xxp1;
639 struct cvmx_pcieep_cfg030_s cn56xx;
640 struct cvmx_pcieep_cfg030_s cn56xxp1;
641};
642
643union cvmx_pcieep_cfg031 {
644 uint32_t u32;
645 struct cvmx_pcieep_cfg031_s {
646 uint32_t pnum:8;
647 uint32_t reserved_22_23:2;
648 uint32_t lbnc:1;
649 uint32_t dllarc:1;
650 uint32_t sderc:1;
651 uint32_t cpm:1;
652 uint32_t l1el:3;
653 uint32_t l0el:3;
654 uint32_t aslpms:2;
655 uint32_t mlw:6;
656 uint32_t mls:4;
657 } s;
658 struct cvmx_pcieep_cfg031_s cn52xx;
659 struct cvmx_pcieep_cfg031_s cn52xxp1;
660 struct cvmx_pcieep_cfg031_s cn56xx;
661 struct cvmx_pcieep_cfg031_s cn56xxp1;
662};
663
664union cvmx_pcieep_cfg032 {
665 uint32_t u32;
666 struct cvmx_pcieep_cfg032_s {
667 uint32_t reserved_30_31:2;
668 uint32_t dlla:1;
669 uint32_t scc:1;
670 uint32_t lt:1;
671 uint32_t reserved_26_26:1;
672 uint32_t nlw:6;
673 uint32_t ls:4;
674 uint32_t reserved_10_15:6;
675 uint32_t hawd:1;
676 uint32_t ecpm:1;
677 uint32_t es:1;
678 uint32_t ccc:1;
679 uint32_t rl:1;
680 uint32_t ld:1;
681 uint32_t rcb:1;
682 uint32_t reserved_2_2:1;
683 uint32_t aslpc:2;
684 } s;
685 struct cvmx_pcieep_cfg032_s cn52xx;
686 struct cvmx_pcieep_cfg032_s cn52xxp1;
687 struct cvmx_pcieep_cfg032_s cn56xx;
688 struct cvmx_pcieep_cfg032_s cn56xxp1;
689};
690
691union cvmx_pcieep_cfg033 {
692 uint32_t u32;
693 struct cvmx_pcieep_cfg033_s {
694 uint32_t ps_num:13;
695 uint32_t nccs:1;
696 uint32_t emip:1;
697 uint32_t sp_ls:2;
698 uint32_t sp_lv:8;
699 uint32_t hp_c:1;
700 uint32_t hp_s:1;
701 uint32_t pip:1;
702 uint32_t aip:1;
703 uint32_t mrlsp:1;
704 uint32_t pcp:1;
705 uint32_t abp:1;
706 } s;
707 struct cvmx_pcieep_cfg033_s cn52xx;
708 struct cvmx_pcieep_cfg033_s cn52xxp1;
709 struct cvmx_pcieep_cfg033_s cn56xx;
710 struct cvmx_pcieep_cfg033_s cn56xxp1;
711};
712
713union cvmx_pcieep_cfg034 {
714 uint32_t u32;
715 struct cvmx_pcieep_cfg034_s {
716 uint32_t reserved_25_31:7;
717 uint32_t dlls_c:1;
718 uint32_t emis:1;
719 uint32_t pds:1;
720 uint32_t mrlss:1;
721 uint32_t ccint_d:1;
722 uint32_t pd_c:1;
723 uint32_t mrls_c:1;
724 uint32_t pf_d:1;
725 uint32_t abp_d:1;
726 uint32_t reserved_13_15:3;
727 uint32_t dlls_en:1;
728 uint32_t emic:1;
729 uint32_t pcc:1;
730 uint32_t pic:2;
731 uint32_t aic:2;
732 uint32_t hpint_en:1;
733 uint32_t ccint_en:1;
734 uint32_t pd_en:1;
735 uint32_t mrls_en:1;
736 uint32_t pf_en:1;
737 uint32_t abp_en:1;
738 } s;
739 struct cvmx_pcieep_cfg034_s cn52xx;
740 struct cvmx_pcieep_cfg034_s cn52xxp1;
741 struct cvmx_pcieep_cfg034_s cn56xx;
742 struct cvmx_pcieep_cfg034_s cn56xxp1;
743};
744
745union cvmx_pcieep_cfg037 {
746 uint32_t u32;
747 struct cvmx_pcieep_cfg037_s {
748 uint32_t reserved_5_31:27;
749 uint32_t ctds:1;
750 uint32_t ctrs:4;
751 } s;
752 struct cvmx_pcieep_cfg037_s cn52xx;
753 struct cvmx_pcieep_cfg037_s cn52xxp1;
754 struct cvmx_pcieep_cfg037_s cn56xx;
755 struct cvmx_pcieep_cfg037_s cn56xxp1;
756};
757
758union cvmx_pcieep_cfg038 {
759 uint32_t u32;
760 struct cvmx_pcieep_cfg038_s {
761 uint32_t reserved_5_31:27;
762 uint32_t ctd:1;
763 uint32_t ctv:4;
764 } s;
765 struct cvmx_pcieep_cfg038_s cn52xx;
766 struct cvmx_pcieep_cfg038_s cn52xxp1;
767 struct cvmx_pcieep_cfg038_s cn56xx;
768 struct cvmx_pcieep_cfg038_s cn56xxp1;
769};
770
771union cvmx_pcieep_cfg039 {
772 uint32_t u32;
773 struct cvmx_pcieep_cfg039_s {
774 uint32_t reserved_0_31:32;
775 } s;
776 struct cvmx_pcieep_cfg039_s cn52xx;
777 struct cvmx_pcieep_cfg039_s cn52xxp1;
778 struct cvmx_pcieep_cfg039_s cn56xx;
779 struct cvmx_pcieep_cfg039_s cn56xxp1;
780};
781
782union cvmx_pcieep_cfg040 {
783 uint32_t u32;
784 struct cvmx_pcieep_cfg040_s {
785 uint32_t reserved_0_31:32;
786 } s;
787 struct cvmx_pcieep_cfg040_s cn52xx;
788 struct cvmx_pcieep_cfg040_s cn52xxp1;
789 struct cvmx_pcieep_cfg040_s cn56xx;
790 struct cvmx_pcieep_cfg040_s cn56xxp1;
791};
792
793union cvmx_pcieep_cfg041 {
794 uint32_t u32;
795 struct cvmx_pcieep_cfg041_s {
796 uint32_t reserved_0_31:32;
797 } s;
798 struct cvmx_pcieep_cfg041_s cn52xx;
799 struct cvmx_pcieep_cfg041_s cn52xxp1;
800 struct cvmx_pcieep_cfg041_s cn56xx;
801 struct cvmx_pcieep_cfg041_s cn56xxp1;
802};
803
804union cvmx_pcieep_cfg042 {
805 uint32_t u32;
806 struct cvmx_pcieep_cfg042_s {
807 uint32_t reserved_0_31:32;
808 } s;
809 struct cvmx_pcieep_cfg042_s cn52xx;
810 struct cvmx_pcieep_cfg042_s cn52xxp1;
811 struct cvmx_pcieep_cfg042_s cn56xx;
812 struct cvmx_pcieep_cfg042_s cn56xxp1;
813};
814
815union cvmx_pcieep_cfg064 {
816 uint32_t u32;
817 struct cvmx_pcieep_cfg064_s {
818 uint32_t nco:12;
819 uint32_t cv:4;
820 uint32_t pcieec:16;
821 } s;
822 struct cvmx_pcieep_cfg064_s cn52xx;
823 struct cvmx_pcieep_cfg064_s cn52xxp1;
824 struct cvmx_pcieep_cfg064_s cn56xx;
825 struct cvmx_pcieep_cfg064_s cn56xxp1;
826};
827
828union cvmx_pcieep_cfg065 {
829 uint32_t u32;
830 struct cvmx_pcieep_cfg065_s {
831 uint32_t reserved_21_31:11;
832 uint32_t ures:1;
833 uint32_t ecrces:1;
834 uint32_t mtlps:1;
835 uint32_t ros:1;
836 uint32_t ucs:1;
837 uint32_t cas:1;
838 uint32_t cts:1;
839 uint32_t fcpes:1;
840 uint32_t ptlps:1;
841 uint32_t reserved_6_11:6;
842 uint32_t sdes:1;
843 uint32_t dlpes:1;
844 uint32_t reserved_0_3:4;
845 } s;
846 struct cvmx_pcieep_cfg065_s cn52xx;
847 struct cvmx_pcieep_cfg065_s cn52xxp1;
848 struct cvmx_pcieep_cfg065_s cn56xx;
849 struct cvmx_pcieep_cfg065_s cn56xxp1;
850};
851
852union cvmx_pcieep_cfg066 {
853 uint32_t u32;
854 struct cvmx_pcieep_cfg066_s {
855 uint32_t reserved_21_31:11;
856 uint32_t urem:1;
857 uint32_t ecrcem:1;
858 uint32_t mtlpm:1;
859 uint32_t rom:1;
860 uint32_t ucm:1;
861 uint32_t cam:1;
862 uint32_t ctm:1;
863 uint32_t fcpem:1;
864 uint32_t ptlpm:1;
865 uint32_t reserved_6_11:6;
866 uint32_t sdem:1;
867 uint32_t dlpem:1;
868 uint32_t reserved_0_3:4;
869 } s;
870 struct cvmx_pcieep_cfg066_s cn52xx;
871 struct cvmx_pcieep_cfg066_s cn52xxp1;
872 struct cvmx_pcieep_cfg066_s cn56xx;
873 struct cvmx_pcieep_cfg066_s cn56xxp1;
874};
875
876union cvmx_pcieep_cfg067 {
877 uint32_t u32;
878 struct cvmx_pcieep_cfg067_s {
879 uint32_t reserved_21_31:11;
880 uint32_t ures:1;
881 uint32_t ecrces:1;
882 uint32_t mtlps:1;
883 uint32_t ros:1;
884 uint32_t ucs:1;
885 uint32_t cas:1;
886 uint32_t cts:1;
887 uint32_t fcpes:1;
888 uint32_t ptlps:1;
889 uint32_t reserved_6_11:6;
890 uint32_t sdes:1;
891 uint32_t dlpes:1;
892 uint32_t reserved_0_3:4;
893 } s;
894 struct cvmx_pcieep_cfg067_s cn52xx;
895 struct cvmx_pcieep_cfg067_s cn52xxp1;
896 struct cvmx_pcieep_cfg067_s cn56xx;
897 struct cvmx_pcieep_cfg067_s cn56xxp1;
898};
899
900union cvmx_pcieep_cfg068 {
901 uint32_t u32;
902 struct cvmx_pcieep_cfg068_s {
903 uint32_t reserved_14_31:18;
904 uint32_t anfes:1;
905 uint32_t rtts:1;
906 uint32_t reserved_9_11:3;
907 uint32_t rnrs:1;
908 uint32_t bdllps:1;
909 uint32_t btlps:1;
910 uint32_t reserved_1_5:5;
911 uint32_t res:1;
912 } s;
913 struct cvmx_pcieep_cfg068_s cn52xx;
914 struct cvmx_pcieep_cfg068_s cn52xxp1;
915 struct cvmx_pcieep_cfg068_s cn56xx;
916 struct cvmx_pcieep_cfg068_s cn56xxp1;
917};
918
919union cvmx_pcieep_cfg069 {
920 uint32_t u32;
921 struct cvmx_pcieep_cfg069_s {
922 uint32_t reserved_14_31:18;
923 uint32_t anfem:1;
924 uint32_t rttm:1;
925 uint32_t reserved_9_11:3;
926 uint32_t rnrm:1;
927 uint32_t bdllpm:1;
928 uint32_t btlpm:1;
929 uint32_t reserved_1_5:5;
930 uint32_t rem:1;
931 } s;
932 struct cvmx_pcieep_cfg069_s cn52xx;
933 struct cvmx_pcieep_cfg069_s cn52xxp1;
934 struct cvmx_pcieep_cfg069_s cn56xx;
935 struct cvmx_pcieep_cfg069_s cn56xxp1;
936};
937
938union cvmx_pcieep_cfg070 {
939 uint32_t u32;
940 struct cvmx_pcieep_cfg070_s {
941 uint32_t reserved_9_31:23;
942 uint32_t ce:1;
943 uint32_t cc:1;
944 uint32_t ge:1;
945 uint32_t gc:1;
946 uint32_t fep:5;
947 } s;
948 struct cvmx_pcieep_cfg070_s cn52xx;
949 struct cvmx_pcieep_cfg070_s cn52xxp1;
950 struct cvmx_pcieep_cfg070_s cn56xx;
951 struct cvmx_pcieep_cfg070_s cn56xxp1;
952};
953
954union cvmx_pcieep_cfg071 {
955 uint32_t u32;
956 struct cvmx_pcieep_cfg071_s {
957 uint32_t dword1:32;
958 } s;
959 struct cvmx_pcieep_cfg071_s cn52xx;
960 struct cvmx_pcieep_cfg071_s cn52xxp1;
961 struct cvmx_pcieep_cfg071_s cn56xx;
962 struct cvmx_pcieep_cfg071_s cn56xxp1;
963};
964
965union cvmx_pcieep_cfg072 {
966 uint32_t u32;
967 struct cvmx_pcieep_cfg072_s {
968 uint32_t dword2:32;
969 } s;
970 struct cvmx_pcieep_cfg072_s cn52xx;
971 struct cvmx_pcieep_cfg072_s cn52xxp1;
972 struct cvmx_pcieep_cfg072_s cn56xx;
973 struct cvmx_pcieep_cfg072_s cn56xxp1;
974};
975
976union cvmx_pcieep_cfg073 {
977 uint32_t u32;
978 struct cvmx_pcieep_cfg073_s {
979 uint32_t dword3:32;
980 } s;
981 struct cvmx_pcieep_cfg073_s cn52xx;
982 struct cvmx_pcieep_cfg073_s cn52xxp1;
983 struct cvmx_pcieep_cfg073_s cn56xx;
984 struct cvmx_pcieep_cfg073_s cn56xxp1;
985};
986
987union cvmx_pcieep_cfg074 {
988 uint32_t u32;
989 struct cvmx_pcieep_cfg074_s {
990 uint32_t dword4:32;
991 } s;
992 struct cvmx_pcieep_cfg074_s cn52xx;
993 struct cvmx_pcieep_cfg074_s cn52xxp1;
994 struct cvmx_pcieep_cfg074_s cn56xx;
995 struct cvmx_pcieep_cfg074_s cn56xxp1;
996};
997
998union cvmx_pcieep_cfg448 {
999 uint32_t u32;
1000 struct cvmx_pcieep_cfg448_s {
1001 uint32_t rtl:16;
1002 uint32_t rtltl:16;
1003 } s;
1004 struct cvmx_pcieep_cfg448_s cn52xx;
1005 struct cvmx_pcieep_cfg448_s cn52xxp1;
1006 struct cvmx_pcieep_cfg448_s cn56xx;
1007 struct cvmx_pcieep_cfg448_s cn56xxp1;
1008};
1009
1010union cvmx_pcieep_cfg449 {
1011 uint32_t u32;
1012 struct cvmx_pcieep_cfg449_s {
1013 uint32_t omr:32;
1014 } s;
1015 struct cvmx_pcieep_cfg449_s cn52xx;
1016 struct cvmx_pcieep_cfg449_s cn52xxp1;
1017 struct cvmx_pcieep_cfg449_s cn56xx;
1018 struct cvmx_pcieep_cfg449_s cn56xxp1;
1019};
1020
1021union cvmx_pcieep_cfg450 {
1022 uint32_t u32;
1023 struct cvmx_pcieep_cfg450_s {
1024 uint32_t lpec:8;
1025 uint32_t reserved_22_23:2;
1026 uint32_t link_state:6;
1027 uint32_t force_link:1;
1028 uint32_t reserved_8_14:7;
1029 uint32_t link_num:8;
1030 } s;
1031 struct cvmx_pcieep_cfg450_s cn52xx;
1032 struct cvmx_pcieep_cfg450_s cn52xxp1;
1033 struct cvmx_pcieep_cfg450_s cn56xx;
1034 struct cvmx_pcieep_cfg450_s cn56xxp1;
1035};
1036
1037union cvmx_pcieep_cfg451 {
1038 uint32_t u32;
1039 struct cvmx_pcieep_cfg451_s {
1040 uint32_t reserved_30_31:2;
1041 uint32_t l1el:3;
1042 uint32_t l0el:3;
1043 uint32_t n_fts_cc:8;
1044 uint32_t n_fts:8;
1045 uint32_t ack_freq:8;
1046 } s;
1047 struct cvmx_pcieep_cfg451_s cn52xx;
1048 struct cvmx_pcieep_cfg451_s cn52xxp1;
1049 struct cvmx_pcieep_cfg451_s cn56xx;
1050 struct cvmx_pcieep_cfg451_s cn56xxp1;
1051};
1052
1053union cvmx_pcieep_cfg452 {
1054 uint32_t u32;
1055 struct cvmx_pcieep_cfg452_s {
1056 uint32_t reserved_26_31:6;
1057 uint32_t eccrc:1;
1058 uint32_t reserved_22_24:3;
1059 uint32_t lme:6;
1060 uint32_t reserved_8_15:8;
1061 uint32_t flm:1;
1062 uint32_t reserved_6_6:1;
1063 uint32_t dllle:1;
1064 uint32_t reserved_4_4:1;
1065 uint32_t ra:1;
1066 uint32_t le:1;
1067 uint32_t sd:1;
1068 uint32_t omr:1;
1069 } s;
1070 struct cvmx_pcieep_cfg452_s cn52xx;
1071 struct cvmx_pcieep_cfg452_s cn52xxp1;
1072 struct cvmx_pcieep_cfg452_s cn56xx;
1073 struct cvmx_pcieep_cfg452_s cn56xxp1;
1074};
1075
1076union cvmx_pcieep_cfg453 {
1077 uint32_t u32;
1078 struct cvmx_pcieep_cfg453_s {
1079 uint32_t dlld:1;
1080 uint32_t reserved_26_30:5;
1081 uint32_t ack_nak:1;
1082 uint32_t fcd:1;
1083 uint32_t ilst:24;
1084 } s;
1085 struct cvmx_pcieep_cfg453_s cn52xx;
1086 struct cvmx_pcieep_cfg453_s cn52xxp1;
1087 struct cvmx_pcieep_cfg453_s cn56xx;
1088 struct cvmx_pcieep_cfg453_s cn56xxp1;
1089};
1090
1091union cvmx_pcieep_cfg454 {
1092 uint32_t u32;
1093 struct cvmx_pcieep_cfg454_s {
1094 uint32_t reserved_29_31:3;
1095 uint32_t tmfcwt:5;
1096 uint32_t tmanlt:5;
1097 uint32_t tmrt:5;
1098 uint32_t reserved_11_13:3;
1099 uint32_t nskps:3;
1100 uint32_t reserved_4_7:4;
1101 uint32_t ntss:4;
1102 } s;
1103 struct cvmx_pcieep_cfg454_s cn52xx;
1104 struct cvmx_pcieep_cfg454_s cn52xxp1;
1105 struct cvmx_pcieep_cfg454_s cn56xx;
1106 struct cvmx_pcieep_cfg454_s cn56xxp1;
1107};
1108
1109union cvmx_pcieep_cfg455 {
1110 uint32_t u32;
1111 struct cvmx_pcieep_cfg455_s {
1112 uint32_t m_cfg0_filt:1;
1113 uint32_t m_io_filt:1;
1114 uint32_t msg_ctrl:1;
1115 uint32_t m_cpl_ecrc_filt:1;
1116 uint32_t m_ecrc_filt:1;
1117 uint32_t m_cpl_len_err:1;
1118 uint32_t m_cpl_attr_err:1;
1119 uint32_t m_cpl_tc_err:1;
1120 uint32_t m_cpl_fun_err:1;
1121 uint32_t m_cpl_rid_err:1;
1122 uint32_t m_cpl_tag_err:1;
1123 uint32_t m_lk_filt:1;
1124 uint32_t m_cfg1_filt:1;
1125 uint32_t m_bar_match:1;
1126 uint32_t m_pois_filt:1;
1127 uint32_t m_fun:1;
1128 uint32_t dfcwt:1;
1129 uint32_t reserved_11_14:4;
1130 uint32_t skpiv:11;
1131 } s;
1132 struct cvmx_pcieep_cfg455_s cn52xx;
1133 struct cvmx_pcieep_cfg455_s cn52xxp1;
1134 struct cvmx_pcieep_cfg455_s cn56xx;
1135 struct cvmx_pcieep_cfg455_s cn56xxp1;
1136};
1137
1138union cvmx_pcieep_cfg456 {
1139 uint32_t u32;
1140 struct cvmx_pcieep_cfg456_s {
1141 uint32_t reserved_2_31:30;
1142 uint32_t m_vend1_drp:1;
1143 uint32_t m_vend0_drp:1;
1144 } s;
1145 struct cvmx_pcieep_cfg456_s cn52xx;
1146 struct cvmx_pcieep_cfg456_s cn52xxp1;
1147 struct cvmx_pcieep_cfg456_s cn56xx;
1148 struct cvmx_pcieep_cfg456_s cn56xxp1;
1149};
1150
1151union cvmx_pcieep_cfg458 {
1152 uint32_t u32;
1153 struct cvmx_pcieep_cfg458_s {
1154 uint32_t dbg_info_l32:32;
1155 } s;
1156 struct cvmx_pcieep_cfg458_s cn52xx;
1157 struct cvmx_pcieep_cfg458_s cn52xxp1;
1158 struct cvmx_pcieep_cfg458_s cn56xx;
1159 struct cvmx_pcieep_cfg458_s cn56xxp1;
1160};
1161
1162union cvmx_pcieep_cfg459 {
1163 uint32_t u32;
1164 struct cvmx_pcieep_cfg459_s {
1165 uint32_t dbg_info_u32:32;
1166 } s;
1167 struct cvmx_pcieep_cfg459_s cn52xx;
1168 struct cvmx_pcieep_cfg459_s cn52xxp1;
1169 struct cvmx_pcieep_cfg459_s cn56xx;
1170 struct cvmx_pcieep_cfg459_s cn56xxp1;
1171};
1172
1173union cvmx_pcieep_cfg460 {
1174 uint32_t u32;
1175 struct cvmx_pcieep_cfg460_s {
1176 uint32_t reserved_20_31:12;
1177 uint32_t tphfcc:8;
1178 uint32_t tpdfcc:12;
1179 } s;
1180 struct cvmx_pcieep_cfg460_s cn52xx;
1181 struct cvmx_pcieep_cfg460_s cn52xxp1;
1182 struct cvmx_pcieep_cfg460_s cn56xx;
1183 struct cvmx_pcieep_cfg460_s cn56xxp1;
1184};
1185
1186union cvmx_pcieep_cfg461 {
1187 uint32_t u32;
1188 struct cvmx_pcieep_cfg461_s {
1189 uint32_t reserved_20_31:12;
1190 uint32_t tchfcc:8;
1191 uint32_t tcdfcc:12;
1192 } s;
1193 struct cvmx_pcieep_cfg461_s cn52xx;
1194 struct cvmx_pcieep_cfg461_s cn52xxp1;
1195 struct cvmx_pcieep_cfg461_s cn56xx;
1196 struct cvmx_pcieep_cfg461_s cn56xxp1;
1197};
1198
1199union cvmx_pcieep_cfg462 {
1200 uint32_t u32;
1201 struct cvmx_pcieep_cfg462_s {
1202 uint32_t reserved_20_31:12;
1203 uint32_t tchfcc:8;
1204 uint32_t tcdfcc:12;
1205 } s;
1206 struct cvmx_pcieep_cfg462_s cn52xx;
1207 struct cvmx_pcieep_cfg462_s cn52xxp1;
1208 struct cvmx_pcieep_cfg462_s cn56xx;
1209 struct cvmx_pcieep_cfg462_s cn56xxp1;
1210};
1211
1212union cvmx_pcieep_cfg463 {
1213 uint32_t u32;
1214 struct cvmx_pcieep_cfg463_s {
1215 uint32_t reserved_3_31:29;
1216 uint32_t rqne:1;
1217 uint32_t trbne:1;
1218 uint32_t rtlpfccnr:1;
1219 } s;
1220 struct cvmx_pcieep_cfg463_s cn52xx;
1221 struct cvmx_pcieep_cfg463_s cn52xxp1;
1222 struct cvmx_pcieep_cfg463_s cn56xx;
1223 struct cvmx_pcieep_cfg463_s cn56xxp1;
1224};
1225
1226union cvmx_pcieep_cfg464 {
1227 uint32_t u32;
1228 struct cvmx_pcieep_cfg464_s {
1229 uint32_t wrr_vc3:8;
1230 uint32_t wrr_vc2:8;
1231 uint32_t wrr_vc1:8;
1232 uint32_t wrr_vc0:8;
1233 } s;
1234 struct cvmx_pcieep_cfg464_s cn52xx;
1235 struct cvmx_pcieep_cfg464_s cn52xxp1;
1236 struct cvmx_pcieep_cfg464_s cn56xx;
1237 struct cvmx_pcieep_cfg464_s cn56xxp1;
1238};
1239
1240union cvmx_pcieep_cfg465 {
1241 uint32_t u32;
1242 struct cvmx_pcieep_cfg465_s {
1243 uint32_t wrr_vc7:8;
1244 uint32_t wrr_vc6:8;
1245 uint32_t wrr_vc5:8;
1246 uint32_t wrr_vc4:8;
1247 } s;
1248 struct cvmx_pcieep_cfg465_s cn52xx;
1249 struct cvmx_pcieep_cfg465_s cn52xxp1;
1250 struct cvmx_pcieep_cfg465_s cn56xx;
1251 struct cvmx_pcieep_cfg465_s cn56xxp1;
1252};
1253
1254union cvmx_pcieep_cfg466 {
1255 uint32_t u32;
1256 struct cvmx_pcieep_cfg466_s {
1257 uint32_t rx_queue_order:1;
1258 uint32_t type_ordering:1;
1259 uint32_t reserved_24_29:6;
1260 uint32_t queue_mode:3;
1261 uint32_t reserved_20_20:1;
1262 uint32_t header_credits:8;
1263 uint32_t data_credits:12;
1264 } s;
1265 struct cvmx_pcieep_cfg466_s cn52xx;
1266 struct cvmx_pcieep_cfg466_s cn52xxp1;
1267 struct cvmx_pcieep_cfg466_s cn56xx;
1268 struct cvmx_pcieep_cfg466_s cn56xxp1;
1269};
1270
1271union cvmx_pcieep_cfg467 {
1272 uint32_t u32;
1273 struct cvmx_pcieep_cfg467_s {
1274 uint32_t reserved_24_31:8;
1275 uint32_t queue_mode:3;
1276 uint32_t reserved_20_20:1;
1277 uint32_t header_credits:8;
1278 uint32_t data_credits:12;
1279 } s;
1280 struct cvmx_pcieep_cfg467_s cn52xx;
1281 struct cvmx_pcieep_cfg467_s cn52xxp1;
1282 struct cvmx_pcieep_cfg467_s cn56xx;
1283 struct cvmx_pcieep_cfg467_s cn56xxp1;
1284};
1285
1286union cvmx_pcieep_cfg468 {
1287 uint32_t u32;
1288 struct cvmx_pcieep_cfg468_s {
1289 uint32_t reserved_24_31:8;
1290 uint32_t queue_mode:3;
1291 uint32_t reserved_20_20:1;
1292 uint32_t header_credits:8;
1293 uint32_t data_credits:12;
1294 } s;
1295 struct cvmx_pcieep_cfg468_s cn52xx;
1296 struct cvmx_pcieep_cfg468_s cn52xxp1;
1297 struct cvmx_pcieep_cfg468_s cn56xx;
1298 struct cvmx_pcieep_cfg468_s cn56xxp1;
1299};
1300
1301union cvmx_pcieep_cfg490 {
1302 uint32_t u32;
1303 struct cvmx_pcieep_cfg490_s {
1304 uint32_t reserved_26_31:6;
1305 uint32_t header_depth:10;
1306 uint32_t reserved_14_15:2;
1307 uint32_t data_depth:14;
1308 } s;
1309 struct cvmx_pcieep_cfg490_s cn52xx;
1310 struct cvmx_pcieep_cfg490_s cn52xxp1;
1311 struct cvmx_pcieep_cfg490_s cn56xx;
1312 struct cvmx_pcieep_cfg490_s cn56xxp1;
1313};
1314
1315union cvmx_pcieep_cfg491 {
1316 uint32_t u32;
1317 struct cvmx_pcieep_cfg491_s {
1318 uint32_t reserved_26_31:6;
1319 uint32_t header_depth:10;
1320 uint32_t reserved_14_15:2;
1321 uint32_t data_depth:14;
1322 } s;
1323 struct cvmx_pcieep_cfg491_s cn52xx;
1324 struct cvmx_pcieep_cfg491_s cn52xxp1;
1325 struct cvmx_pcieep_cfg491_s cn56xx;
1326 struct cvmx_pcieep_cfg491_s cn56xxp1;
1327};
1328
1329union cvmx_pcieep_cfg492 {
1330 uint32_t u32;
1331 struct cvmx_pcieep_cfg492_s {
1332 uint32_t reserved_26_31:6;
1333 uint32_t header_depth:10;
1334 uint32_t reserved_14_15:2;
1335 uint32_t data_depth:14;
1336 } s;
1337 struct cvmx_pcieep_cfg492_s cn52xx;
1338 struct cvmx_pcieep_cfg492_s cn52xxp1;
1339 struct cvmx_pcieep_cfg492_s cn56xx;
1340 struct cvmx_pcieep_cfg492_s cn56xxp1;
1341};
1342
1343union cvmx_pcieep_cfg516 {
1344 uint32_t u32;
1345 struct cvmx_pcieep_cfg516_s {
1346 uint32_t phy_stat:32;
1347 } s;
1348 struct cvmx_pcieep_cfg516_s cn52xx;
1349 struct cvmx_pcieep_cfg516_s cn52xxp1;
1350 struct cvmx_pcieep_cfg516_s cn56xx;
1351 struct cvmx_pcieep_cfg516_s cn56xxp1;
1352};
1353
1354union cvmx_pcieep_cfg517 {
1355 uint32_t u32;
1356 struct cvmx_pcieep_cfg517_s {
1357 uint32_t phy_ctrl:32;
1358 } s;
1359 struct cvmx_pcieep_cfg517_s cn52xx;
1360 struct cvmx_pcieep_cfg517_s cn52xxp1;
1361 struct cvmx_pcieep_cfg517_s cn56xx;
1362 struct cvmx_pcieep_cfg517_s cn56xxp1;
1363};
1364
1365#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
new file mode 100644
index 000000000000..75574c918942
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pciercx-defs.h
@@ -0,0 +1,1397 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCIERCX_DEFS_H__
29#define __CVMX_PCIERCX_DEFS_H__
30
31#define CVMX_PCIERCX_CFG000(offset) \
32 (0x0000000000000000ull + (((offset) & 1) * 0))
33#define CVMX_PCIERCX_CFG001(offset) \
34 (0x0000000000000004ull + (((offset) & 1) * 0))
35#define CVMX_PCIERCX_CFG002(offset) \
36 (0x0000000000000008ull + (((offset) & 1) * 0))
37#define CVMX_PCIERCX_CFG003(offset) \
38 (0x000000000000000Cull + (((offset) & 1) * 0))
39#define CVMX_PCIERCX_CFG004(offset) \
40 (0x0000000000000010ull + (((offset) & 1) * 0))
41#define CVMX_PCIERCX_CFG005(offset) \
42 (0x0000000000000014ull + (((offset) & 1) * 0))
43#define CVMX_PCIERCX_CFG006(offset) \
44 (0x0000000000000018ull + (((offset) & 1) * 0))
45#define CVMX_PCIERCX_CFG007(offset) \
46 (0x000000000000001Cull + (((offset) & 1) * 0))
47#define CVMX_PCIERCX_CFG008(offset) \
48 (0x0000000000000020ull + (((offset) & 1) * 0))
49#define CVMX_PCIERCX_CFG009(offset) \
50 (0x0000000000000024ull + (((offset) & 1) * 0))
51#define CVMX_PCIERCX_CFG010(offset) \
52 (0x0000000000000028ull + (((offset) & 1) * 0))
53#define CVMX_PCIERCX_CFG011(offset) \
54 (0x000000000000002Cull + (((offset) & 1) * 0))
55#define CVMX_PCIERCX_CFG012(offset) \
56 (0x0000000000000030ull + (((offset) & 1) * 0))
57#define CVMX_PCIERCX_CFG013(offset) \
58 (0x0000000000000034ull + (((offset) & 1) * 0))
59#define CVMX_PCIERCX_CFG014(offset) \
60 (0x0000000000000038ull + (((offset) & 1) * 0))
61#define CVMX_PCIERCX_CFG015(offset) \
62 (0x000000000000003Cull + (((offset) & 1) * 0))
63#define CVMX_PCIERCX_CFG016(offset) \
64 (0x0000000000000040ull + (((offset) & 1) * 0))
65#define CVMX_PCIERCX_CFG017(offset) \
66 (0x0000000000000044ull + (((offset) & 1) * 0))
67#define CVMX_PCIERCX_CFG020(offset) \
68 (0x0000000000000050ull + (((offset) & 1) * 0))
69#define CVMX_PCIERCX_CFG021(offset) \
70 (0x0000000000000054ull + (((offset) & 1) * 0))
71#define CVMX_PCIERCX_CFG022(offset) \
72 (0x0000000000000058ull + (((offset) & 1) * 0))
73#define CVMX_PCIERCX_CFG023(offset) \
74 (0x000000000000005Cull + (((offset) & 1) * 0))
75#define CVMX_PCIERCX_CFG028(offset) \
76 (0x0000000000000070ull + (((offset) & 1) * 0))
77#define CVMX_PCIERCX_CFG029(offset) \
78 (0x0000000000000074ull + (((offset) & 1) * 0))
79#define CVMX_PCIERCX_CFG030(offset) \
80 (0x0000000000000078ull + (((offset) & 1) * 0))
81#define CVMX_PCIERCX_CFG031(offset) \
82 (0x000000000000007Cull + (((offset) & 1) * 0))
83#define CVMX_PCIERCX_CFG032(offset) \
84 (0x0000000000000080ull + (((offset) & 1) * 0))
85#define CVMX_PCIERCX_CFG033(offset) \
86 (0x0000000000000084ull + (((offset) & 1) * 0))
87#define CVMX_PCIERCX_CFG034(offset) \
88 (0x0000000000000088ull + (((offset) & 1) * 0))
89#define CVMX_PCIERCX_CFG035(offset) \
90 (0x000000000000008Cull + (((offset) & 1) * 0))
91#define CVMX_PCIERCX_CFG036(offset) \
92 (0x0000000000000090ull + (((offset) & 1) * 0))
93#define CVMX_PCIERCX_CFG037(offset) \
94 (0x0000000000000094ull + (((offset) & 1) * 0))
95#define CVMX_PCIERCX_CFG038(offset) \
96 (0x0000000000000098ull + (((offset) & 1) * 0))
97#define CVMX_PCIERCX_CFG039(offset) \
98 (0x000000000000009Cull + (((offset) & 1) * 0))
99#define CVMX_PCIERCX_CFG040(offset) \
100 (0x00000000000000A0ull + (((offset) & 1) * 0))
101#define CVMX_PCIERCX_CFG041(offset) \
102 (0x00000000000000A4ull + (((offset) & 1) * 0))
103#define CVMX_PCIERCX_CFG042(offset) \
104 (0x00000000000000A8ull + (((offset) & 1) * 0))
105#define CVMX_PCIERCX_CFG064(offset) \
106 (0x0000000000000100ull + (((offset) & 1) * 0))
107#define CVMX_PCIERCX_CFG065(offset) \
108 (0x0000000000000104ull + (((offset) & 1) * 0))
109#define CVMX_PCIERCX_CFG066(offset) \
110 (0x0000000000000108ull + (((offset) & 1) * 0))
111#define CVMX_PCIERCX_CFG067(offset) \
112 (0x000000000000010Cull + (((offset) & 1) * 0))
113#define CVMX_PCIERCX_CFG068(offset) \
114 (0x0000000000000110ull + (((offset) & 1) * 0))
115#define CVMX_PCIERCX_CFG069(offset) \
116 (0x0000000000000114ull + (((offset) & 1) * 0))
117#define CVMX_PCIERCX_CFG070(offset) \
118 (0x0000000000000118ull + (((offset) & 1) * 0))
119#define CVMX_PCIERCX_CFG071(offset) \
120 (0x000000000000011Cull + (((offset) & 1) * 0))
121#define CVMX_PCIERCX_CFG072(offset) \
122 (0x0000000000000120ull + (((offset) & 1) * 0))
123#define CVMX_PCIERCX_CFG073(offset) \
124 (0x0000000000000124ull + (((offset) & 1) * 0))
125#define CVMX_PCIERCX_CFG074(offset) \
126 (0x0000000000000128ull + (((offset) & 1) * 0))
127#define CVMX_PCIERCX_CFG075(offset) \
128 (0x000000000000012Cull + (((offset) & 1) * 0))
129#define CVMX_PCIERCX_CFG076(offset) \
130 (0x0000000000000130ull + (((offset) & 1) * 0))
131#define CVMX_PCIERCX_CFG077(offset) \
132 (0x0000000000000134ull + (((offset) & 1) * 0))
133#define CVMX_PCIERCX_CFG448(offset) \
134 (0x0000000000000700ull + (((offset) & 1) * 0))
135#define CVMX_PCIERCX_CFG449(offset) \
136 (0x0000000000000704ull + (((offset) & 1) * 0))
137#define CVMX_PCIERCX_CFG450(offset) \
138 (0x0000000000000708ull + (((offset) & 1) * 0))
139#define CVMX_PCIERCX_CFG451(offset) \
140 (0x000000000000070Cull + (((offset) & 1) * 0))
141#define CVMX_PCIERCX_CFG452(offset) \
142 (0x0000000000000710ull + (((offset) & 1) * 0))
143#define CVMX_PCIERCX_CFG453(offset) \
144 (0x0000000000000714ull + (((offset) & 1) * 0))
145#define CVMX_PCIERCX_CFG454(offset) \
146 (0x0000000000000718ull + (((offset) & 1) * 0))
147#define CVMX_PCIERCX_CFG455(offset) \
148 (0x000000000000071Cull + (((offset) & 1) * 0))
149#define CVMX_PCIERCX_CFG456(offset) \
150 (0x0000000000000720ull + (((offset) & 1) * 0))
151#define CVMX_PCIERCX_CFG458(offset) \
152 (0x0000000000000728ull + (((offset) & 1) * 0))
153#define CVMX_PCIERCX_CFG459(offset) \
154 (0x000000000000072Cull + (((offset) & 1) * 0))
155#define CVMX_PCIERCX_CFG460(offset) \
156 (0x0000000000000730ull + (((offset) & 1) * 0))
157#define CVMX_PCIERCX_CFG461(offset) \
158 (0x0000000000000734ull + (((offset) & 1) * 0))
159#define CVMX_PCIERCX_CFG462(offset) \
160 (0x0000000000000738ull + (((offset) & 1) * 0))
161#define CVMX_PCIERCX_CFG463(offset) \
162 (0x000000000000073Cull + (((offset) & 1) * 0))
163#define CVMX_PCIERCX_CFG464(offset) \
164 (0x0000000000000740ull + (((offset) & 1) * 0))
165#define CVMX_PCIERCX_CFG465(offset) \
166 (0x0000000000000744ull + (((offset) & 1) * 0))
167#define CVMX_PCIERCX_CFG466(offset) \
168 (0x0000000000000748ull + (((offset) & 1) * 0))
169#define CVMX_PCIERCX_CFG467(offset) \
170 (0x000000000000074Cull + (((offset) & 1) * 0))
171#define CVMX_PCIERCX_CFG468(offset) \
172 (0x0000000000000750ull + (((offset) & 1) * 0))
173#define CVMX_PCIERCX_CFG490(offset) \
174 (0x00000000000007A8ull + (((offset) & 1) * 0))
175#define CVMX_PCIERCX_CFG491(offset) \
176 (0x00000000000007ACull + (((offset) & 1) * 0))
177#define CVMX_PCIERCX_CFG492(offset) \
178 (0x00000000000007B0ull + (((offset) & 1) * 0))
179#define CVMX_PCIERCX_CFG516(offset) \
180 (0x0000000000000810ull + (((offset) & 1) * 0))
181#define CVMX_PCIERCX_CFG517(offset) \
182 (0x0000000000000814ull + (((offset) & 1) * 0))
183
184union cvmx_pciercx_cfg000 {
185 uint32_t u32;
186 struct cvmx_pciercx_cfg000_s {
187 uint32_t devid:16;
188 uint32_t vendid:16;
189 } s;
190 struct cvmx_pciercx_cfg000_s cn52xx;
191 struct cvmx_pciercx_cfg000_s cn52xxp1;
192 struct cvmx_pciercx_cfg000_s cn56xx;
193 struct cvmx_pciercx_cfg000_s cn56xxp1;
194};
195
196union cvmx_pciercx_cfg001 {
197 uint32_t u32;
198 struct cvmx_pciercx_cfg001_s {
199 uint32_t dpe:1;
200 uint32_t sse:1;
201 uint32_t rma:1;
202 uint32_t rta:1;
203 uint32_t sta:1;
204 uint32_t devt:2;
205 uint32_t mdpe:1;
206 uint32_t fbb:1;
207 uint32_t reserved_22_22:1;
208 uint32_t m66:1;
209 uint32_t cl:1;
210 uint32_t i_stat:1;
211 uint32_t reserved_11_18:8;
212 uint32_t i_dis:1;
213 uint32_t fbbe:1;
214 uint32_t see:1;
215 uint32_t ids_wcc:1;
216 uint32_t per:1;
217 uint32_t vps:1;
218 uint32_t mwice:1;
219 uint32_t scse:1;
220 uint32_t me:1;
221 uint32_t msae:1;
222 uint32_t isae:1;
223 } s;
224 struct cvmx_pciercx_cfg001_s cn52xx;
225 struct cvmx_pciercx_cfg001_s cn52xxp1;
226 struct cvmx_pciercx_cfg001_s cn56xx;
227 struct cvmx_pciercx_cfg001_s cn56xxp1;
228};
229
230union cvmx_pciercx_cfg002 {
231 uint32_t u32;
232 struct cvmx_pciercx_cfg002_s {
233 uint32_t bcc:8;
234 uint32_t sc:8;
235 uint32_t pi:8;
236 uint32_t rid:8;
237 } s;
238 struct cvmx_pciercx_cfg002_s cn52xx;
239 struct cvmx_pciercx_cfg002_s cn52xxp1;
240 struct cvmx_pciercx_cfg002_s cn56xx;
241 struct cvmx_pciercx_cfg002_s cn56xxp1;
242};
243
244union cvmx_pciercx_cfg003 {
245 uint32_t u32;
246 struct cvmx_pciercx_cfg003_s {
247 uint32_t bist:8;
248 uint32_t mfd:1;
249 uint32_t chf:7;
250 uint32_t lt:8;
251 uint32_t cls:8;
252 } s;
253 struct cvmx_pciercx_cfg003_s cn52xx;
254 struct cvmx_pciercx_cfg003_s cn52xxp1;
255 struct cvmx_pciercx_cfg003_s cn56xx;
256 struct cvmx_pciercx_cfg003_s cn56xxp1;
257};
258
259union cvmx_pciercx_cfg004 {
260 uint32_t u32;
261 struct cvmx_pciercx_cfg004_s {
262 uint32_t reserved_0_31:32;
263 } s;
264 struct cvmx_pciercx_cfg004_s cn52xx;
265 struct cvmx_pciercx_cfg004_s cn52xxp1;
266 struct cvmx_pciercx_cfg004_s cn56xx;
267 struct cvmx_pciercx_cfg004_s cn56xxp1;
268};
269
270union cvmx_pciercx_cfg005 {
271 uint32_t u32;
272 struct cvmx_pciercx_cfg005_s {
273 uint32_t reserved_0_31:32;
274 } s;
275 struct cvmx_pciercx_cfg005_s cn52xx;
276 struct cvmx_pciercx_cfg005_s cn52xxp1;
277 struct cvmx_pciercx_cfg005_s cn56xx;
278 struct cvmx_pciercx_cfg005_s cn56xxp1;
279};
280
281union cvmx_pciercx_cfg006 {
282 uint32_t u32;
283 struct cvmx_pciercx_cfg006_s {
284 uint32_t slt:8;
285 uint32_t subbnum:8;
286 uint32_t sbnum:8;
287 uint32_t pbnum:8;
288 } s;
289 struct cvmx_pciercx_cfg006_s cn52xx;
290 struct cvmx_pciercx_cfg006_s cn52xxp1;
291 struct cvmx_pciercx_cfg006_s cn56xx;
292 struct cvmx_pciercx_cfg006_s cn56xxp1;
293};
294
295union cvmx_pciercx_cfg007 {
296 uint32_t u32;
297 struct cvmx_pciercx_cfg007_s {
298 uint32_t dpe:1;
299 uint32_t sse:1;
300 uint32_t rma:1;
301 uint32_t rta:1;
302 uint32_t sta:1;
303 uint32_t devt:2;
304 uint32_t mdpe:1;
305 uint32_t fbb:1;
306 uint32_t reserved_22_22:1;
307 uint32_t m66:1;
308 uint32_t reserved_16_20:5;
309 uint32_t lio_limi:4;
310 uint32_t reserved_9_11:3;
311 uint32_t io32b:1;
312 uint32_t lio_base:4;
313 uint32_t reserved_1_3:3;
314 uint32_t io32a:1;
315 } s;
316 struct cvmx_pciercx_cfg007_s cn52xx;
317 struct cvmx_pciercx_cfg007_s cn52xxp1;
318 struct cvmx_pciercx_cfg007_s cn56xx;
319 struct cvmx_pciercx_cfg007_s cn56xxp1;
320};
321
322union cvmx_pciercx_cfg008 {
323 uint32_t u32;
324 struct cvmx_pciercx_cfg008_s {
325 uint32_t ml_addr:12;
326 uint32_t reserved_16_19:4;
327 uint32_t mb_addr:12;
328 uint32_t reserved_0_3:4;
329 } s;
330 struct cvmx_pciercx_cfg008_s cn52xx;
331 struct cvmx_pciercx_cfg008_s cn52xxp1;
332 struct cvmx_pciercx_cfg008_s cn56xx;
333 struct cvmx_pciercx_cfg008_s cn56xxp1;
334};
335
336union cvmx_pciercx_cfg009 {
337 uint32_t u32;
338 struct cvmx_pciercx_cfg009_s {
339 uint32_t lmem_limit:12;
340 uint32_t reserved_17_19:3;
341 uint32_t mem64b:1;
342 uint32_t lmem_base:12;
343 uint32_t reserved_1_3:3;
344 uint32_t mem64a:1;
345 } s;
346 struct cvmx_pciercx_cfg009_s cn52xx;
347 struct cvmx_pciercx_cfg009_s cn52xxp1;
348 struct cvmx_pciercx_cfg009_s cn56xx;
349 struct cvmx_pciercx_cfg009_s cn56xxp1;
350};
351
352union cvmx_pciercx_cfg010 {
353 uint32_t u32;
354 struct cvmx_pciercx_cfg010_s {
355 uint32_t umem_base:32;
356 } s;
357 struct cvmx_pciercx_cfg010_s cn52xx;
358 struct cvmx_pciercx_cfg010_s cn52xxp1;
359 struct cvmx_pciercx_cfg010_s cn56xx;
360 struct cvmx_pciercx_cfg010_s cn56xxp1;
361};
362
363union cvmx_pciercx_cfg011 {
364 uint32_t u32;
365 struct cvmx_pciercx_cfg011_s {
366 uint32_t umem_limit:32;
367 } s;
368 struct cvmx_pciercx_cfg011_s cn52xx;
369 struct cvmx_pciercx_cfg011_s cn52xxp1;
370 struct cvmx_pciercx_cfg011_s cn56xx;
371 struct cvmx_pciercx_cfg011_s cn56xxp1;
372};
373
374union cvmx_pciercx_cfg012 {
375 uint32_t u32;
376 struct cvmx_pciercx_cfg012_s {
377 uint32_t uio_limit:16;
378 uint32_t uio_base:16;
379 } s;
380 struct cvmx_pciercx_cfg012_s cn52xx;
381 struct cvmx_pciercx_cfg012_s cn52xxp1;
382 struct cvmx_pciercx_cfg012_s cn56xx;
383 struct cvmx_pciercx_cfg012_s cn56xxp1;
384};
385
386union cvmx_pciercx_cfg013 {
387 uint32_t u32;
388 struct cvmx_pciercx_cfg013_s {
389 uint32_t reserved_8_31:24;
390 uint32_t cp:8;
391 } s;
392 struct cvmx_pciercx_cfg013_s cn52xx;
393 struct cvmx_pciercx_cfg013_s cn52xxp1;
394 struct cvmx_pciercx_cfg013_s cn56xx;
395 struct cvmx_pciercx_cfg013_s cn56xxp1;
396};
397
398union cvmx_pciercx_cfg014 {
399 uint32_t u32;
400 struct cvmx_pciercx_cfg014_s {
401 uint32_t reserved_0_31:32;
402 } s;
403 struct cvmx_pciercx_cfg014_s cn52xx;
404 struct cvmx_pciercx_cfg014_s cn52xxp1;
405 struct cvmx_pciercx_cfg014_s cn56xx;
406 struct cvmx_pciercx_cfg014_s cn56xxp1;
407};
408
409union cvmx_pciercx_cfg015 {
410 uint32_t u32;
411 struct cvmx_pciercx_cfg015_s {
412 uint32_t reserved_28_31:4;
413 uint32_t dtsees:1;
414 uint32_t dts:1;
415 uint32_t sdt:1;
416 uint32_t pdt:1;
417 uint32_t fbbe:1;
418 uint32_t sbrst:1;
419 uint32_t mam:1;
420 uint32_t vga16d:1;
421 uint32_t vgae:1;
422 uint32_t isae:1;
423 uint32_t see:1;
424 uint32_t pere:1;
425 uint32_t inta:8;
426 uint32_t il:8;
427 } s;
428 struct cvmx_pciercx_cfg015_s cn52xx;
429 struct cvmx_pciercx_cfg015_s cn52xxp1;
430 struct cvmx_pciercx_cfg015_s cn56xx;
431 struct cvmx_pciercx_cfg015_s cn56xxp1;
432};
433
434union cvmx_pciercx_cfg016 {
435 uint32_t u32;
436 struct cvmx_pciercx_cfg016_s {
437 uint32_t pmes:5;
438 uint32_t d2s:1;
439 uint32_t d1s:1;
440 uint32_t auxc:3;
441 uint32_t dsi:1;
442 uint32_t reserved_20_20:1;
443 uint32_t pme_clock:1;
444 uint32_t pmsv:3;
445 uint32_t ncp:8;
446 uint32_t pmcid:8;
447 } s;
448 struct cvmx_pciercx_cfg016_s cn52xx;
449 struct cvmx_pciercx_cfg016_s cn52xxp1;
450 struct cvmx_pciercx_cfg016_s cn56xx;
451 struct cvmx_pciercx_cfg016_s cn56xxp1;
452};
453
454union cvmx_pciercx_cfg017 {
455 uint32_t u32;
456 struct cvmx_pciercx_cfg017_s {
457 uint32_t pmdia:8;
458 uint32_t bpccee:1;
459 uint32_t bd3h:1;
460 uint32_t reserved_16_21:6;
461 uint32_t pmess:1;
462 uint32_t pmedsia:2;
463 uint32_t pmds:4;
464 uint32_t pmeens:1;
465 uint32_t reserved_4_7:4;
466 uint32_t nsr:1;
467 uint32_t reserved_2_2:1;
468 uint32_t ps:2;
469 } s;
470 struct cvmx_pciercx_cfg017_s cn52xx;
471 struct cvmx_pciercx_cfg017_s cn52xxp1;
472 struct cvmx_pciercx_cfg017_s cn56xx;
473 struct cvmx_pciercx_cfg017_s cn56xxp1;
474};
475
476union cvmx_pciercx_cfg020 {
477 uint32_t u32;
478 struct cvmx_pciercx_cfg020_s {
479 uint32_t reserved_24_31:8;
480 uint32_t m64:1;
481 uint32_t mme:3;
482 uint32_t mmc:3;
483 uint32_t msien:1;
484 uint32_t ncp:8;
485 uint32_t msicid:8;
486 } s;
487 struct cvmx_pciercx_cfg020_s cn52xx;
488 struct cvmx_pciercx_cfg020_s cn52xxp1;
489 struct cvmx_pciercx_cfg020_s cn56xx;
490 struct cvmx_pciercx_cfg020_s cn56xxp1;
491};
492
493union cvmx_pciercx_cfg021 {
494 uint32_t u32;
495 struct cvmx_pciercx_cfg021_s {
496 uint32_t lmsi:30;
497 uint32_t reserved_0_1:2;
498 } s;
499 struct cvmx_pciercx_cfg021_s cn52xx;
500 struct cvmx_pciercx_cfg021_s cn52xxp1;
501 struct cvmx_pciercx_cfg021_s cn56xx;
502 struct cvmx_pciercx_cfg021_s cn56xxp1;
503};
504
505union cvmx_pciercx_cfg022 {
506 uint32_t u32;
507 struct cvmx_pciercx_cfg022_s {
508 uint32_t umsi:32;
509 } s;
510 struct cvmx_pciercx_cfg022_s cn52xx;
511 struct cvmx_pciercx_cfg022_s cn52xxp1;
512 struct cvmx_pciercx_cfg022_s cn56xx;
513 struct cvmx_pciercx_cfg022_s cn56xxp1;
514};
515
516union cvmx_pciercx_cfg023 {
517 uint32_t u32;
518 struct cvmx_pciercx_cfg023_s {
519 uint32_t reserved_16_31:16;
520 uint32_t msimd:16;
521 } s;
522 struct cvmx_pciercx_cfg023_s cn52xx;
523 struct cvmx_pciercx_cfg023_s cn52xxp1;
524 struct cvmx_pciercx_cfg023_s cn56xx;
525 struct cvmx_pciercx_cfg023_s cn56xxp1;
526};
527
528union cvmx_pciercx_cfg028 {
529 uint32_t u32;
530 struct cvmx_pciercx_cfg028_s {
531 uint32_t reserved_30_31:2;
532 uint32_t imn:5;
533 uint32_t si:1;
534 uint32_t dpt:4;
535 uint32_t pciecv:4;
536 uint32_t ncp:8;
537 uint32_t pcieid:8;
538 } s;
539 struct cvmx_pciercx_cfg028_s cn52xx;
540 struct cvmx_pciercx_cfg028_s cn52xxp1;
541 struct cvmx_pciercx_cfg028_s cn56xx;
542 struct cvmx_pciercx_cfg028_s cn56xxp1;
543};
544
545union cvmx_pciercx_cfg029 {
546 uint32_t u32;
547 struct cvmx_pciercx_cfg029_s {
548 uint32_t reserved_28_31:4;
549 uint32_t cspls:2;
550 uint32_t csplv:8;
551 uint32_t reserved_16_17:2;
552 uint32_t rber:1;
553 uint32_t reserved_12_14:3;
554 uint32_t el1al:3;
555 uint32_t el0al:3;
556 uint32_t etfs:1;
557 uint32_t pfs:2;
558 uint32_t mpss:3;
559 } s;
560 struct cvmx_pciercx_cfg029_s cn52xx;
561 struct cvmx_pciercx_cfg029_s cn52xxp1;
562 struct cvmx_pciercx_cfg029_s cn56xx;
563 struct cvmx_pciercx_cfg029_s cn56xxp1;
564};
565
566union cvmx_pciercx_cfg030 {
567 uint32_t u32;
568 struct cvmx_pciercx_cfg030_s {
569 uint32_t reserved_22_31:10;
570 uint32_t tp:1;
571 uint32_t ap_d:1;
572 uint32_t ur_d:1;
573 uint32_t fe_d:1;
574 uint32_t nfe_d:1;
575 uint32_t ce_d:1;
576 uint32_t reserved_15_15:1;
577 uint32_t mrrs:3;
578 uint32_t ns_en:1;
579 uint32_t ap_en:1;
580 uint32_t pf_en:1;
581 uint32_t etf_en:1;
582 uint32_t mps:3;
583 uint32_t ro_en:1;
584 uint32_t ur_en:1;
585 uint32_t fe_en:1;
586 uint32_t nfe_en:1;
587 uint32_t ce_en:1;
588 } s;
589 struct cvmx_pciercx_cfg030_s cn52xx;
590 struct cvmx_pciercx_cfg030_s cn52xxp1;
591 struct cvmx_pciercx_cfg030_s cn56xx;
592 struct cvmx_pciercx_cfg030_s cn56xxp1;
593};
594
595union cvmx_pciercx_cfg031 {
596 uint32_t u32;
597 struct cvmx_pciercx_cfg031_s {
598 uint32_t pnum:8;
599 uint32_t reserved_22_23:2;
600 uint32_t lbnc:1;
601 uint32_t dllarc:1;
602 uint32_t sderc:1;
603 uint32_t cpm:1;
604 uint32_t l1el:3;
605 uint32_t l0el:3;
606 uint32_t aslpms:2;
607 uint32_t mlw:6;
608 uint32_t mls:4;
609 } s;
610 struct cvmx_pciercx_cfg031_s cn52xx;
611 struct cvmx_pciercx_cfg031_s cn52xxp1;
612 struct cvmx_pciercx_cfg031_s cn56xx;
613 struct cvmx_pciercx_cfg031_s cn56xxp1;
614};
615
616union cvmx_pciercx_cfg032 {
617 uint32_t u32;
618 struct cvmx_pciercx_cfg032_s {
619 uint32_t lab:1;
620 uint32_t lbm:1;
621 uint32_t dlla:1;
622 uint32_t scc:1;
623 uint32_t lt:1;
624 uint32_t reserved_26_26:1;
625 uint32_t nlw:6;
626 uint32_t ls:4;
627 uint32_t reserved_12_15:4;
628 uint32_t lab_int_enb:1;
629 uint32_t lbm_int_enb:1;
630 uint32_t hawd:1;
631 uint32_t ecpm:1;
632 uint32_t es:1;
633 uint32_t ccc:1;
634 uint32_t rl:1;
635 uint32_t ld:1;
636 uint32_t rcb:1;
637 uint32_t reserved_2_2:1;
638 uint32_t aslpc:2;
639 } s;
640 struct cvmx_pciercx_cfg032_s cn52xx;
641 struct cvmx_pciercx_cfg032_s cn52xxp1;
642 struct cvmx_pciercx_cfg032_s cn56xx;
643 struct cvmx_pciercx_cfg032_s cn56xxp1;
644};
645
646union cvmx_pciercx_cfg033 {
647 uint32_t u32;
648 struct cvmx_pciercx_cfg033_s {
649 uint32_t ps_num:13;
650 uint32_t nccs:1;
651 uint32_t emip:1;
652 uint32_t sp_ls:2;
653 uint32_t sp_lv:8;
654 uint32_t hp_c:1;
655 uint32_t hp_s:1;
656 uint32_t pip:1;
657 uint32_t aip:1;
658 uint32_t mrlsp:1;
659 uint32_t pcp:1;
660 uint32_t abp:1;
661 } s;
662 struct cvmx_pciercx_cfg033_s cn52xx;
663 struct cvmx_pciercx_cfg033_s cn52xxp1;
664 struct cvmx_pciercx_cfg033_s cn56xx;
665 struct cvmx_pciercx_cfg033_s cn56xxp1;
666};
667
668union cvmx_pciercx_cfg034 {
669 uint32_t u32;
670 struct cvmx_pciercx_cfg034_s {
671 uint32_t reserved_25_31:7;
672 uint32_t dlls_c:1;
673 uint32_t emis:1;
674 uint32_t pds:1;
675 uint32_t mrlss:1;
676 uint32_t ccint_d:1;
677 uint32_t pd_c:1;
678 uint32_t mrls_c:1;
679 uint32_t pf_d:1;
680 uint32_t abp_d:1;
681 uint32_t reserved_13_15:3;
682 uint32_t dlls_en:1;
683 uint32_t emic:1;
684 uint32_t pcc:1;
685 uint32_t pic:2;
686 uint32_t aic:2;
687 uint32_t hpint_en:1;
688 uint32_t ccint_en:1;
689 uint32_t pd_en:1;
690 uint32_t mrls_en:1;
691 uint32_t pf_en:1;
692 uint32_t abp_en:1;
693 } s;
694 struct cvmx_pciercx_cfg034_s cn52xx;
695 struct cvmx_pciercx_cfg034_s cn52xxp1;
696 struct cvmx_pciercx_cfg034_s cn56xx;
697 struct cvmx_pciercx_cfg034_s cn56xxp1;
698};
699
700union cvmx_pciercx_cfg035 {
701 uint32_t u32;
702 struct cvmx_pciercx_cfg035_s {
703 uint32_t reserved_17_31:15;
704 uint32_t crssv:1;
705 uint32_t reserved_5_15:11;
706 uint32_t crssve:1;
707 uint32_t pmeie:1;
708 uint32_t sefee:1;
709 uint32_t senfee:1;
710 uint32_t secee:1;
711 } s;
712 struct cvmx_pciercx_cfg035_s cn52xx;
713 struct cvmx_pciercx_cfg035_s cn52xxp1;
714 struct cvmx_pciercx_cfg035_s cn56xx;
715 struct cvmx_pciercx_cfg035_s cn56xxp1;
716};
717
718union cvmx_pciercx_cfg036 {
719 uint32_t u32;
720 struct cvmx_pciercx_cfg036_s {
721 uint32_t reserved_18_31:14;
722 uint32_t pme_pend:1;
723 uint32_t pme_stat:1;
724 uint32_t pme_rid:16;
725 } s;
726 struct cvmx_pciercx_cfg036_s cn52xx;
727 struct cvmx_pciercx_cfg036_s cn52xxp1;
728 struct cvmx_pciercx_cfg036_s cn56xx;
729 struct cvmx_pciercx_cfg036_s cn56xxp1;
730};
731
732union cvmx_pciercx_cfg037 {
733 uint32_t u32;
734 struct cvmx_pciercx_cfg037_s {
735 uint32_t reserved_5_31:27;
736 uint32_t ctds:1;
737 uint32_t ctrs:4;
738 } s;
739 struct cvmx_pciercx_cfg037_s cn52xx;
740 struct cvmx_pciercx_cfg037_s cn52xxp1;
741 struct cvmx_pciercx_cfg037_s cn56xx;
742 struct cvmx_pciercx_cfg037_s cn56xxp1;
743};
744
745union cvmx_pciercx_cfg038 {
746 uint32_t u32;
747 struct cvmx_pciercx_cfg038_s {
748 uint32_t reserved_5_31:27;
749 uint32_t ctd:1;
750 uint32_t ctv:4;
751 } s;
752 struct cvmx_pciercx_cfg038_s cn52xx;
753 struct cvmx_pciercx_cfg038_s cn52xxp1;
754 struct cvmx_pciercx_cfg038_s cn56xx;
755 struct cvmx_pciercx_cfg038_s cn56xxp1;
756};
757
758union cvmx_pciercx_cfg039 {
759 uint32_t u32;
760 struct cvmx_pciercx_cfg039_s {
761 uint32_t reserved_0_31:32;
762 } s;
763 struct cvmx_pciercx_cfg039_s cn52xx;
764 struct cvmx_pciercx_cfg039_s cn52xxp1;
765 struct cvmx_pciercx_cfg039_s cn56xx;
766 struct cvmx_pciercx_cfg039_s cn56xxp1;
767};
768
769union cvmx_pciercx_cfg040 {
770 uint32_t u32;
771 struct cvmx_pciercx_cfg040_s {
772 uint32_t reserved_0_31:32;
773 } s;
774 struct cvmx_pciercx_cfg040_s cn52xx;
775 struct cvmx_pciercx_cfg040_s cn52xxp1;
776 struct cvmx_pciercx_cfg040_s cn56xx;
777 struct cvmx_pciercx_cfg040_s cn56xxp1;
778};
779
780union cvmx_pciercx_cfg041 {
781 uint32_t u32;
782 struct cvmx_pciercx_cfg041_s {
783 uint32_t reserved_0_31:32;
784 } s;
785 struct cvmx_pciercx_cfg041_s cn52xx;
786 struct cvmx_pciercx_cfg041_s cn52xxp1;
787 struct cvmx_pciercx_cfg041_s cn56xx;
788 struct cvmx_pciercx_cfg041_s cn56xxp1;
789};
790
791union cvmx_pciercx_cfg042 {
792 uint32_t u32;
793 struct cvmx_pciercx_cfg042_s {
794 uint32_t reserved_0_31:32;
795 } s;
796 struct cvmx_pciercx_cfg042_s cn52xx;
797 struct cvmx_pciercx_cfg042_s cn52xxp1;
798 struct cvmx_pciercx_cfg042_s cn56xx;
799 struct cvmx_pciercx_cfg042_s cn56xxp1;
800};
801
802union cvmx_pciercx_cfg064 {
803 uint32_t u32;
804 struct cvmx_pciercx_cfg064_s {
805 uint32_t nco:12;
806 uint32_t cv:4;
807 uint32_t pcieec:16;
808 } s;
809 struct cvmx_pciercx_cfg064_s cn52xx;
810 struct cvmx_pciercx_cfg064_s cn52xxp1;
811 struct cvmx_pciercx_cfg064_s cn56xx;
812 struct cvmx_pciercx_cfg064_s cn56xxp1;
813};
814
815union cvmx_pciercx_cfg065 {
816 uint32_t u32;
817 struct cvmx_pciercx_cfg065_s {
818 uint32_t reserved_21_31:11;
819 uint32_t ures:1;
820 uint32_t ecrces:1;
821 uint32_t mtlps:1;
822 uint32_t ros:1;
823 uint32_t ucs:1;
824 uint32_t cas:1;
825 uint32_t cts:1;
826 uint32_t fcpes:1;
827 uint32_t ptlps:1;
828 uint32_t reserved_6_11:6;
829 uint32_t sdes:1;
830 uint32_t dlpes:1;
831 uint32_t reserved_0_3:4;
832 } s;
833 struct cvmx_pciercx_cfg065_s cn52xx;
834 struct cvmx_pciercx_cfg065_s cn52xxp1;
835 struct cvmx_pciercx_cfg065_s cn56xx;
836 struct cvmx_pciercx_cfg065_s cn56xxp1;
837};
838
839union cvmx_pciercx_cfg066 {
840 uint32_t u32;
841 struct cvmx_pciercx_cfg066_s {
842 uint32_t reserved_21_31:11;
843 uint32_t urem:1;
844 uint32_t ecrcem:1;
845 uint32_t mtlpm:1;
846 uint32_t rom:1;
847 uint32_t ucm:1;
848 uint32_t cam:1;
849 uint32_t ctm:1;
850 uint32_t fcpem:1;
851 uint32_t ptlpm:1;
852 uint32_t reserved_6_11:6;
853 uint32_t sdem:1;
854 uint32_t dlpem:1;
855 uint32_t reserved_0_3:4;
856 } s;
857 struct cvmx_pciercx_cfg066_s cn52xx;
858 struct cvmx_pciercx_cfg066_s cn52xxp1;
859 struct cvmx_pciercx_cfg066_s cn56xx;
860 struct cvmx_pciercx_cfg066_s cn56xxp1;
861};
862
863union cvmx_pciercx_cfg067 {
864 uint32_t u32;
865 struct cvmx_pciercx_cfg067_s {
866 uint32_t reserved_21_31:11;
867 uint32_t ures:1;
868 uint32_t ecrces:1;
869 uint32_t mtlps:1;
870 uint32_t ros:1;
871 uint32_t ucs:1;
872 uint32_t cas:1;
873 uint32_t cts:1;
874 uint32_t fcpes:1;
875 uint32_t ptlps:1;
876 uint32_t reserved_6_11:6;
877 uint32_t sdes:1;
878 uint32_t dlpes:1;
879 uint32_t reserved_0_3:4;
880 } s;
881 struct cvmx_pciercx_cfg067_s cn52xx;
882 struct cvmx_pciercx_cfg067_s cn52xxp1;
883 struct cvmx_pciercx_cfg067_s cn56xx;
884 struct cvmx_pciercx_cfg067_s cn56xxp1;
885};
886
887union cvmx_pciercx_cfg068 {
888 uint32_t u32;
889 struct cvmx_pciercx_cfg068_s {
890 uint32_t reserved_14_31:18;
891 uint32_t anfes:1;
892 uint32_t rtts:1;
893 uint32_t reserved_9_11:3;
894 uint32_t rnrs:1;
895 uint32_t bdllps:1;
896 uint32_t btlps:1;
897 uint32_t reserved_1_5:5;
898 uint32_t res:1;
899 } s;
900 struct cvmx_pciercx_cfg068_s cn52xx;
901 struct cvmx_pciercx_cfg068_s cn52xxp1;
902 struct cvmx_pciercx_cfg068_s cn56xx;
903 struct cvmx_pciercx_cfg068_s cn56xxp1;
904};
905
906union cvmx_pciercx_cfg069 {
907 uint32_t u32;
908 struct cvmx_pciercx_cfg069_s {
909 uint32_t reserved_14_31:18;
910 uint32_t anfem:1;
911 uint32_t rttm:1;
912 uint32_t reserved_9_11:3;
913 uint32_t rnrm:1;
914 uint32_t bdllpm:1;
915 uint32_t btlpm:1;
916 uint32_t reserved_1_5:5;
917 uint32_t rem:1;
918 } s;
919 struct cvmx_pciercx_cfg069_s cn52xx;
920 struct cvmx_pciercx_cfg069_s cn52xxp1;
921 struct cvmx_pciercx_cfg069_s cn56xx;
922 struct cvmx_pciercx_cfg069_s cn56xxp1;
923};
924
925union cvmx_pciercx_cfg070 {
926 uint32_t u32;
927 struct cvmx_pciercx_cfg070_s {
928 uint32_t reserved_9_31:23;
929 uint32_t ce:1;
930 uint32_t cc:1;
931 uint32_t ge:1;
932 uint32_t gc:1;
933 uint32_t fep:5;
934 } s;
935 struct cvmx_pciercx_cfg070_s cn52xx;
936 struct cvmx_pciercx_cfg070_s cn52xxp1;
937 struct cvmx_pciercx_cfg070_s cn56xx;
938 struct cvmx_pciercx_cfg070_s cn56xxp1;
939};
940
941union cvmx_pciercx_cfg071 {
942 uint32_t u32;
943 struct cvmx_pciercx_cfg071_s {
944 uint32_t dword1:32;
945 } s;
946 struct cvmx_pciercx_cfg071_s cn52xx;
947 struct cvmx_pciercx_cfg071_s cn52xxp1;
948 struct cvmx_pciercx_cfg071_s cn56xx;
949 struct cvmx_pciercx_cfg071_s cn56xxp1;
950};
951
952union cvmx_pciercx_cfg072 {
953 uint32_t u32;
954 struct cvmx_pciercx_cfg072_s {
955 uint32_t dword2:32;
956 } s;
957 struct cvmx_pciercx_cfg072_s cn52xx;
958 struct cvmx_pciercx_cfg072_s cn52xxp1;
959 struct cvmx_pciercx_cfg072_s cn56xx;
960 struct cvmx_pciercx_cfg072_s cn56xxp1;
961};
962
963union cvmx_pciercx_cfg073 {
964 uint32_t u32;
965 struct cvmx_pciercx_cfg073_s {
966 uint32_t dword3:32;
967 } s;
968 struct cvmx_pciercx_cfg073_s cn52xx;
969 struct cvmx_pciercx_cfg073_s cn52xxp1;
970 struct cvmx_pciercx_cfg073_s cn56xx;
971 struct cvmx_pciercx_cfg073_s cn56xxp1;
972};
973
974union cvmx_pciercx_cfg074 {
975 uint32_t u32;
976 struct cvmx_pciercx_cfg074_s {
977 uint32_t dword4:32;
978 } s;
979 struct cvmx_pciercx_cfg074_s cn52xx;
980 struct cvmx_pciercx_cfg074_s cn52xxp1;
981 struct cvmx_pciercx_cfg074_s cn56xx;
982 struct cvmx_pciercx_cfg074_s cn56xxp1;
983};
984
985union cvmx_pciercx_cfg075 {
986 uint32_t u32;
987 struct cvmx_pciercx_cfg075_s {
988 uint32_t reserved_3_31:29;
989 uint32_t fere:1;
990 uint32_t nfere:1;
991 uint32_t cere:1;
992 } s;
993 struct cvmx_pciercx_cfg075_s cn52xx;
994 struct cvmx_pciercx_cfg075_s cn52xxp1;
995 struct cvmx_pciercx_cfg075_s cn56xx;
996 struct cvmx_pciercx_cfg075_s cn56xxp1;
997};
998
999union cvmx_pciercx_cfg076 {
1000 uint32_t u32;
1001 struct cvmx_pciercx_cfg076_s {
1002 uint32_t aeimn:5;
1003 uint32_t reserved_7_26:20;
1004 uint32_t femr:1;
1005 uint32_t nfemr:1;
1006 uint32_t fuf:1;
1007 uint32_t multi_efnfr:1;
1008 uint32_t efnfr:1;
1009 uint32_t multi_ecr:1;
1010 uint32_t ecr:1;
1011 } s;
1012 struct cvmx_pciercx_cfg076_s cn52xx;
1013 struct cvmx_pciercx_cfg076_s cn52xxp1;
1014 struct cvmx_pciercx_cfg076_s cn56xx;
1015 struct cvmx_pciercx_cfg076_s cn56xxp1;
1016};
1017
1018union cvmx_pciercx_cfg077 {
1019 uint32_t u32;
1020 struct cvmx_pciercx_cfg077_s {
1021 uint32_t efnfsi:16;
1022 uint32_t ecsi:16;
1023 } s;
1024 struct cvmx_pciercx_cfg077_s cn52xx;
1025 struct cvmx_pciercx_cfg077_s cn52xxp1;
1026 struct cvmx_pciercx_cfg077_s cn56xx;
1027 struct cvmx_pciercx_cfg077_s cn56xxp1;
1028};
1029
1030union cvmx_pciercx_cfg448 {
1031 uint32_t u32;
1032 struct cvmx_pciercx_cfg448_s {
1033 uint32_t rtl:16;
1034 uint32_t rtltl:16;
1035 } s;
1036 struct cvmx_pciercx_cfg448_s cn52xx;
1037 struct cvmx_pciercx_cfg448_s cn52xxp1;
1038 struct cvmx_pciercx_cfg448_s cn56xx;
1039 struct cvmx_pciercx_cfg448_s cn56xxp1;
1040};
1041
1042union cvmx_pciercx_cfg449 {
1043 uint32_t u32;
1044 struct cvmx_pciercx_cfg449_s {
1045 uint32_t omr:32;
1046 } s;
1047 struct cvmx_pciercx_cfg449_s cn52xx;
1048 struct cvmx_pciercx_cfg449_s cn52xxp1;
1049 struct cvmx_pciercx_cfg449_s cn56xx;
1050 struct cvmx_pciercx_cfg449_s cn56xxp1;
1051};
1052
1053union cvmx_pciercx_cfg450 {
1054 uint32_t u32;
1055 struct cvmx_pciercx_cfg450_s {
1056 uint32_t lpec:8;
1057 uint32_t reserved_22_23:2;
1058 uint32_t link_state:6;
1059 uint32_t force_link:1;
1060 uint32_t reserved_8_14:7;
1061 uint32_t link_num:8;
1062 } s;
1063 struct cvmx_pciercx_cfg450_s cn52xx;
1064 struct cvmx_pciercx_cfg450_s cn52xxp1;
1065 struct cvmx_pciercx_cfg450_s cn56xx;
1066 struct cvmx_pciercx_cfg450_s cn56xxp1;
1067};
1068
1069union cvmx_pciercx_cfg451 {
1070 uint32_t u32;
1071 struct cvmx_pciercx_cfg451_s {
1072 uint32_t reserved_30_31:2;
1073 uint32_t l1el:3;
1074 uint32_t l0el:3;
1075 uint32_t n_fts_cc:8;
1076 uint32_t n_fts:8;
1077 uint32_t ack_freq:8;
1078 } s;
1079 struct cvmx_pciercx_cfg451_s cn52xx;
1080 struct cvmx_pciercx_cfg451_s cn52xxp1;
1081 struct cvmx_pciercx_cfg451_s cn56xx;
1082 struct cvmx_pciercx_cfg451_s cn56xxp1;
1083};
1084
1085union cvmx_pciercx_cfg452 {
1086 uint32_t u32;
1087 struct cvmx_pciercx_cfg452_s {
1088 uint32_t reserved_26_31:6;
1089 uint32_t eccrc:1;
1090 uint32_t reserved_22_24:3;
1091 uint32_t lme:6;
1092 uint32_t reserved_8_15:8;
1093 uint32_t flm:1;
1094 uint32_t reserved_6_6:1;
1095 uint32_t dllle:1;
1096 uint32_t reserved_4_4:1;
1097 uint32_t ra:1;
1098 uint32_t le:1;
1099 uint32_t sd:1;
1100 uint32_t omr:1;
1101 } s;
1102 struct cvmx_pciercx_cfg452_s cn52xx;
1103 struct cvmx_pciercx_cfg452_s cn52xxp1;
1104 struct cvmx_pciercx_cfg452_s cn56xx;
1105 struct cvmx_pciercx_cfg452_s cn56xxp1;
1106};
1107
1108union cvmx_pciercx_cfg453 {
1109 uint32_t u32;
1110 struct cvmx_pciercx_cfg453_s {
1111 uint32_t dlld:1;
1112 uint32_t reserved_26_30:5;
1113 uint32_t ack_nak:1;
1114 uint32_t fcd:1;
1115 uint32_t ilst:24;
1116 } s;
1117 struct cvmx_pciercx_cfg453_s cn52xx;
1118 struct cvmx_pciercx_cfg453_s cn52xxp1;
1119 struct cvmx_pciercx_cfg453_s cn56xx;
1120 struct cvmx_pciercx_cfg453_s cn56xxp1;
1121};
1122
1123union cvmx_pciercx_cfg454 {
1124 uint32_t u32;
1125 struct cvmx_pciercx_cfg454_s {
1126 uint32_t reserved_29_31:3;
1127 uint32_t tmfcwt:5;
1128 uint32_t tmanlt:5;
1129 uint32_t tmrt:5;
1130 uint32_t reserved_11_13:3;
1131 uint32_t nskps:3;
1132 uint32_t reserved_4_7:4;
1133 uint32_t ntss:4;
1134 } s;
1135 struct cvmx_pciercx_cfg454_s cn52xx;
1136 struct cvmx_pciercx_cfg454_s cn52xxp1;
1137 struct cvmx_pciercx_cfg454_s cn56xx;
1138 struct cvmx_pciercx_cfg454_s cn56xxp1;
1139};
1140
1141union cvmx_pciercx_cfg455 {
1142 uint32_t u32;
1143 struct cvmx_pciercx_cfg455_s {
1144 uint32_t m_cfg0_filt:1;
1145 uint32_t m_io_filt:1;
1146 uint32_t msg_ctrl:1;
1147 uint32_t m_cpl_ecrc_filt:1;
1148 uint32_t m_ecrc_filt:1;
1149 uint32_t m_cpl_len_err:1;
1150 uint32_t m_cpl_attr_err:1;
1151 uint32_t m_cpl_tc_err:1;
1152 uint32_t m_cpl_fun_err:1;
1153 uint32_t m_cpl_rid_err:1;
1154 uint32_t m_cpl_tag_err:1;
1155 uint32_t m_lk_filt:1;
1156 uint32_t m_cfg1_filt:1;
1157 uint32_t m_bar_match:1;
1158 uint32_t m_pois_filt:1;
1159 uint32_t m_fun:1;
1160 uint32_t dfcwt:1;
1161 uint32_t reserved_11_14:4;
1162 uint32_t skpiv:11;
1163 } s;
1164 struct cvmx_pciercx_cfg455_s cn52xx;
1165 struct cvmx_pciercx_cfg455_s cn52xxp1;
1166 struct cvmx_pciercx_cfg455_s cn56xx;
1167 struct cvmx_pciercx_cfg455_s cn56xxp1;
1168};
1169
1170union cvmx_pciercx_cfg456 {
1171 uint32_t u32;
1172 struct cvmx_pciercx_cfg456_s {
1173 uint32_t reserved_2_31:30;
1174 uint32_t m_vend1_drp:1;
1175 uint32_t m_vend0_drp:1;
1176 } s;
1177 struct cvmx_pciercx_cfg456_s cn52xx;
1178 struct cvmx_pciercx_cfg456_s cn52xxp1;
1179 struct cvmx_pciercx_cfg456_s cn56xx;
1180 struct cvmx_pciercx_cfg456_s cn56xxp1;
1181};
1182
1183union cvmx_pciercx_cfg458 {
1184 uint32_t u32;
1185 struct cvmx_pciercx_cfg458_s {
1186 uint32_t dbg_info_l32:32;
1187 } s;
1188 struct cvmx_pciercx_cfg458_s cn52xx;
1189 struct cvmx_pciercx_cfg458_s cn52xxp1;
1190 struct cvmx_pciercx_cfg458_s cn56xx;
1191 struct cvmx_pciercx_cfg458_s cn56xxp1;
1192};
1193
1194union cvmx_pciercx_cfg459 {
1195 uint32_t u32;
1196 struct cvmx_pciercx_cfg459_s {
1197 uint32_t dbg_info_u32:32;
1198 } s;
1199 struct cvmx_pciercx_cfg459_s cn52xx;
1200 struct cvmx_pciercx_cfg459_s cn52xxp1;
1201 struct cvmx_pciercx_cfg459_s cn56xx;
1202 struct cvmx_pciercx_cfg459_s cn56xxp1;
1203};
1204
1205union cvmx_pciercx_cfg460 {
1206 uint32_t u32;
1207 struct cvmx_pciercx_cfg460_s {
1208 uint32_t reserved_20_31:12;
1209 uint32_t tphfcc:8;
1210 uint32_t tpdfcc:12;
1211 } s;
1212 struct cvmx_pciercx_cfg460_s cn52xx;
1213 struct cvmx_pciercx_cfg460_s cn52xxp1;
1214 struct cvmx_pciercx_cfg460_s cn56xx;
1215 struct cvmx_pciercx_cfg460_s cn56xxp1;
1216};
1217
1218union cvmx_pciercx_cfg461 {
1219 uint32_t u32;
1220 struct cvmx_pciercx_cfg461_s {
1221 uint32_t reserved_20_31:12;
1222 uint32_t tchfcc:8;
1223 uint32_t tcdfcc:12;
1224 } s;
1225 struct cvmx_pciercx_cfg461_s cn52xx;
1226 struct cvmx_pciercx_cfg461_s cn52xxp1;
1227 struct cvmx_pciercx_cfg461_s cn56xx;
1228 struct cvmx_pciercx_cfg461_s cn56xxp1;
1229};
1230
1231union cvmx_pciercx_cfg462 {
1232 uint32_t u32;
1233 struct cvmx_pciercx_cfg462_s {
1234 uint32_t reserved_20_31:12;
1235 uint32_t tchfcc:8;
1236 uint32_t tcdfcc:12;
1237 } s;
1238 struct cvmx_pciercx_cfg462_s cn52xx;
1239 struct cvmx_pciercx_cfg462_s cn52xxp1;
1240 struct cvmx_pciercx_cfg462_s cn56xx;
1241 struct cvmx_pciercx_cfg462_s cn56xxp1;
1242};
1243
1244union cvmx_pciercx_cfg463 {
1245 uint32_t u32;
1246 struct cvmx_pciercx_cfg463_s {
1247 uint32_t reserved_3_31:29;
1248 uint32_t rqne:1;
1249 uint32_t trbne:1;
1250 uint32_t rtlpfccnr:1;
1251 } s;
1252 struct cvmx_pciercx_cfg463_s cn52xx;
1253 struct cvmx_pciercx_cfg463_s cn52xxp1;
1254 struct cvmx_pciercx_cfg463_s cn56xx;
1255 struct cvmx_pciercx_cfg463_s cn56xxp1;
1256};
1257
1258union cvmx_pciercx_cfg464 {
1259 uint32_t u32;
1260 struct cvmx_pciercx_cfg464_s {
1261 uint32_t wrr_vc3:8;
1262 uint32_t wrr_vc2:8;
1263 uint32_t wrr_vc1:8;
1264 uint32_t wrr_vc0:8;
1265 } s;
1266 struct cvmx_pciercx_cfg464_s cn52xx;
1267 struct cvmx_pciercx_cfg464_s cn52xxp1;
1268 struct cvmx_pciercx_cfg464_s cn56xx;
1269 struct cvmx_pciercx_cfg464_s cn56xxp1;
1270};
1271
1272union cvmx_pciercx_cfg465 {
1273 uint32_t u32;
1274 struct cvmx_pciercx_cfg465_s {
1275 uint32_t wrr_vc7:8;
1276 uint32_t wrr_vc6:8;
1277 uint32_t wrr_vc5:8;
1278 uint32_t wrr_vc4:8;
1279 } s;
1280 struct cvmx_pciercx_cfg465_s cn52xx;
1281 struct cvmx_pciercx_cfg465_s cn52xxp1;
1282 struct cvmx_pciercx_cfg465_s cn56xx;
1283 struct cvmx_pciercx_cfg465_s cn56xxp1;
1284};
1285
1286union cvmx_pciercx_cfg466 {
1287 uint32_t u32;
1288 struct cvmx_pciercx_cfg466_s {
1289 uint32_t rx_queue_order:1;
1290 uint32_t type_ordering:1;
1291 uint32_t reserved_24_29:6;
1292 uint32_t queue_mode:3;
1293 uint32_t reserved_20_20:1;
1294 uint32_t header_credits:8;
1295 uint32_t data_credits:12;
1296 } s;
1297 struct cvmx_pciercx_cfg466_s cn52xx;
1298 struct cvmx_pciercx_cfg466_s cn52xxp1;
1299 struct cvmx_pciercx_cfg466_s cn56xx;
1300 struct cvmx_pciercx_cfg466_s cn56xxp1;
1301};
1302
1303union cvmx_pciercx_cfg467 {
1304 uint32_t u32;
1305 struct cvmx_pciercx_cfg467_s {
1306 uint32_t reserved_24_31:8;
1307 uint32_t queue_mode:3;
1308 uint32_t reserved_20_20:1;
1309 uint32_t header_credits:8;
1310 uint32_t data_credits:12;
1311 } s;
1312 struct cvmx_pciercx_cfg467_s cn52xx;
1313 struct cvmx_pciercx_cfg467_s cn52xxp1;
1314 struct cvmx_pciercx_cfg467_s cn56xx;
1315 struct cvmx_pciercx_cfg467_s cn56xxp1;
1316};
1317
1318union cvmx_pciercx_cfg468 {
1319 uint32_t u32;
1320 struct cvmx_pciercx_cfg468_s {
1321 uint32_t reserved_24_31:8;
1322 uint32_t queue_mode:3;
1323 uint32_t reserved_20_20:1;
1324 uint32_t header_credits:8;
1325 uint32_t data_credits:12;
1326 } s;
1327 struct cvmx_pciercx_cfg468_s cn52xx;
1328 struct cvmx_pciercx_cfg468_s cn52xxp1;
1329 struct cvmx_pciercx_cfg468_s cn56xx;
1330 struct cvmx_pciercx_cfg468_s cn56xxp1;
1331};
1332
1333union cvmx_pciercx_cfg490 {
1334 uint32_t u32;
1335 struct cvmx_pciercx_cfg490_s {
1336 uint32_t reserved_26_31:6;
1337 uint32_t header_depth:10;
1338 uint32_t reserved_14_15:2;
1339 uint32_t data_depth:14;
1340 } s;
1341 struct cvmx_pciercx_cfg490_s cn52xx;
1342 struct cvmx_pciercx_cfg490_s cn52xxp1;
1343 struct cvmx_pciercx_cfg490_s cn56xx;
1344 struct cvmx_pciercx_cfg490_s cn56xxp1;
1345};
1346
1347union cvmx_pciercx_cfg491 {
1348 uint32_t u32;
1349 struct cvmx_pciercx_cfg491_s {
1350 uint32_t reserved_26_31:6;
1351 uint32_t header_depth:10;
1352 uint32_t reserved_14_15:2;
1353 uint32_t data_depth:14;
1354 } s;
1355 struct cvmx_pciercx_cfg491_s cn52xx;
1356 struct cvmx_pciercx_cfg491_s cn52xxp1;
1357 struct cvmx_pciercx_cfg491_s cn56xx;
1358 struct cvmx_pciercx_cfg491_s cn56xxp1;
1359};
1360
1361union cvmx_pciercx_cfg492 {
1362 uint32_t u32;
1363 struct cvmx_pciercx_cfg492_s {
1364 uint32_t reserved_26_31:6;
1365 uint32_t header_depth:10;
1366 uint32_t reserved_14_15:2;
1367 uint32_t data_depth:14;
1368 } s;
1369 struct cvmx_pciercx_cfg492_s cn52xx;
1370 struct cvmx_pciercx_cfg492_s cn52xxp1;
1371 struct cvmx_pciercx_cfg492_s cn56xx;
1372 struct cvmx_pciercx_cfg492_s cn56xxp1;
1373};
1374
1375union cvmx_pciercx_cfg516 {
1376 uint32_t u32;
1377 struct cvmx_pciercx_cfg516_s {
1378 uint32_t phy_stat:32;
1379 } s;
1380 struct cvmx_pciercx_cfg516_s cn52xx;
1381 struct cvmx_pciercx_cfg516_s cn52xxp1;
1382 struct cvmx_pciercx_cfg516_s cn56xx;
1383 struct cvmx_pciercx_cfg516_s cn56xxp1;
1384};
1385
1386union cvmx_pciercx_cfg517 {
1387 uint32_t u32;
1388 struct cvmx_pciercx_cfg517_s {
1389 uint32_t phy_ctrl:32;
1390 } s;
1391 struct cvmx_pciercx_cfg517_s cn52xx;
1392 struct cvmx_pciercx_cfg517_s cn52xxp1;
1393 struct cvmx_pciercx_cfg517_s cn56xx;
1394 struct cvmx_pciercx_cfg517_s cn56xxp1;
1395};
1396
1397#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pescx-defs.h b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
new file mode 100644
index 000000000000..f40cfaf84454
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pescx-defs.h
@@ -0,0 +1,410 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PESCX_DEFS_H__
29#define __CVMX_PESCX_DEFS_H__
30
31#define CVMX_PESCX_BIST_STATUS(block_id) \
32 CVMX_ADD_IO_SEG(0x00011800C8000018ull + (((block_id) & 1) * 0x8000000ull))
33#define CVMX_PESCX_BIST_STATUS2(block_id) \
34 CVMX_ADD_IO_SEG(0x00011800C8000418ull + (((block_id) & 1) * 0x8000000ull))
35#define CVMX_PESCX_CFG_RD(block_id) \
36 CVMX_ADD_IO_SEG(0x00011800C8000030ull + (((block_id) & 1) * 0x8000000ull))
37#define CVMX_PESCX_CFG_WR(block_id) \
38 CVMX_ADD_IO_SEG(0x00011800C8000028ull + (((block_id) & 1) * 0x8000000ull))
39#define CVMX_PESCX_CPL_LUT_VALID(block_id) \
40 CVMX_ADD_IO_SEG(0x00011800C8000098ull + (((block_id) & 1) * 0x8000000ull))
41#define CVMX_PESCX_CTL_STATUS(block_id) \
42 CVMX_ADD_IO_SEG(0x00011800C8000000ull + (((block_id) & 1) * 0x8000000ull))
43#define CVMX_PESCX_CTL_STATUS2(block_id) \
44 CVMX_ADD_IO_SEG(0x00011800C8000400ull + (((block_id) & 1) * 0x8000000ull))
45#define CVMX_PESCX_DBG_INFO(block_id) \
46 CVMX_ADD_IO_SEG(0x00011800C8000008ull + (((block_id) & 1) * 0x8000000ull))
47#define CVMX_PESCX_DBG_INFO_EN(block_id) \
48 CVMX_ADD_IO_SEG(0x00011800C80000A0ull + (((block_id) & 1) * 0x8000000ull))
49#define CVMX_PESCX_DIAG_STATUS(block_id) \
50 CVMX_ADD_IO_SEG(0x00011800C8000020ull + (((block_id) & 1) * 0x8000000ull))
51#define CVMX_PESCX_P2N_BAR0_START(block_id) \
52 CVMX_ADD_IO_SEG(0x00011800C8000080ull + (((block_id) & 1) * 0x8000000ull))
53#define CVMX_PESCX_P2N_BAR1_START(block_id) \
54 CVMX_ADD_IO_SEG(0x00011800C8000088ull + (((block_id) & 1) * 0x8000000ull))
55#define CVMX_PESCX_P2N_BAR2_START(block_id) \
56 CVMX_ADD_IO_SEG(0x00011800C8000090ull + (((block_id) & 1) * 0x8000000ull))
57#define CVMX_PESCX_P2P_BARX_END(offset, block_id) \
58 CVMX_ADD_IO_SEG(0x00011800C8000048ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
59#define CVMX_PESCX_P2P_BARX_START(offset, block_id) \
60 CVMX_ADD_IO_SEG(0x00011800C8000040ull + (((offset) & 3) * 16) + (((block_id) & 1) * 0x8000000ull))
61#define CVMX_PESCX_TLP_CREDITS(block_id) \
62 CVMX_ADD_IO_SEG(0x00011800C8000038ull + (((block_id) & 1) * 0x8000000ull))
63
64union cvmx_pescx_bist_status {
65 uint64_t u64;
66 struct cvmx_pescx_bist_status_s {
67 uint64_t reserved_13_63:51;
68 uint64_t rqdata5:1;
69 uint64_t ctlp_or:1;
70 uint64_t ntlp_or:1;
71 uint64_t ptlp_or:1;
72 uint64_t retry:1;
73 uint64_t rqdata0:1;
74 uint64_t rqdata1:1;
75 uint64_t rqdata2:1;
76 uint64_t rqdata3:1;
77 uint64_t rqdata4:1;
78 uint64_t rqhdr1:1;
79 uint64_t rqhdr0:1;
80 uint64_t sot:1;
81 } s;
82 struct cvmx_pescx_bist_status_s cn52xx;
83 struct cvmx_pescx_bist_status_cn52xxp1 {
84 uint64_t reserved_12_63:52;
85 uint64_t ctlp_or:1;
86 uint64_t ntlp_or:1;
87 uint64_t ptlp_or:1;
88 uint64_t retry:1;
89 uint64_t rqdata0:1;
90 uint64_t rqdata1:1;
91 uint64_t rqdata2:1;
92 uint64_t rqdata3:1;
93 uint64_t rqdata4:1;
94 uint64_t rqhdr1:1;
95 uint64_t rqhdr0:1;
96 uint64_t sot:1;
97 } cn52xxp1;
98 struct cvmx_pescx_bist_status_s cn56xx;
99 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1;
100};
101
102union cvmx_pescx_bist_status2 {
103 uint64_t u64;
104 struct cvmx_pescx_bist_status2_s {
105 uint64_t reserved_14_63:50;
106 uint64_t cto_p2e:1;
107 uint64_t e2p_cpl:1;
108 uint64_t e2p_n:1;
109 uint64_t e2p_p:1;
110 uint64_t e2p_rsl:1;
111 uint64_t dbg_p2e:1;
112 uint64_t peai_p2e:1;
113 uint64_t rsl_p2e:1;
114 uint64_t pef_tpf1:1;
115 uint64_t pef_tpf0:1;
116 uint64_t pef_tnf:1;
117 uint64_t pef_tcf1:1;
118 uint64_t pef_tc0:1;
119 uint64_t ppf:1;
120 } s;
121 struct cvmx_pescx_bist_status2_s cn52xx;
122 struct cvmx_pescx_bist_status2_s cn52xxp1;
123 struct cvmx_pescx_bist_status2_s cn56xx;
124 struct cvmx_pescx_bist_status2_s cn56xxp1;
125};
126
127union cvmx_pescx_cfg_rd {
128 uint64_t u64;
129 struct cvmx_pescx_cfg_rd_s {
130 uint64_t data:32;
131 uint64_t addr:32;
132 } s;
133 struct cvmx_pescx_cfg_rd_s cn52xx;
134 struct cvmx_pescx_cfg_rd_s cn52xxp1;
135 struct cvmx_pescx_cfg_rd_s cn56xx;
136 struct cvmx_pescx_cfg_rd_s cn56xxp1;
137};
138
139union cvmx_pescx_cfg_wr {
140 uint64_t u64;
141 struct cvmx_pescx_cfg_wr_s {
142 uint64_t data:32;
143 uint64_t addr:32;
144 } s;
145 struct cvmx_pescx_cfg_wr_s cn52xx;
146 struct cvmx_pescx_cfg_wr_s cn52xxp1;
147 struct cvmx_pescx_cfg_wr_s cn56xx;
148 struct cvmx_pescx_cfg_wr_s cn56xxp1;
149};
150
151union cvmx_pescx_cpl_lut_valid {
152 uint64_t u64;
153 struct cvmx_pescx_cpl_lut_valid_s {
154 uint64_t reserved_32_63:32;
155 uint64_t tag:32;
156 } s;
157 struct cvmx_pescx_cpl_lut_valid_s cn52xx;
158 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1;
159 struct cvmx_pescx_cpl_lut_valid_s cn56xx;
160 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1;
161};
162
163union cvmx_pescx_ctl_status {
164 uint64_t u64;
165 struct cvmx_pescx_ctl_status_s {
166 uint64_t reserved_28_63:36;
167 uint64_t dnum:5;
168 uint64_t pbus:8;
169 uint64_t qlm_cfg:2;
170 uint64_t lane_swp:1;
171 uint64_t pm_xtoff:1;
172 uint64_t pm_xpme:1;
173 uint64_t ob_p_cmd:1;
174 uint64_t reserved_7_8:2;
175 uint64_t nf_ecrc:1;
176 uint64_t dly_one:1;
177 uint64_t lnk_enb:1;
178 uint64_t ro_ctlp:1;
179 uint64_t reserved_2_2:1;
180 uint64_t inv_ecrc:1;
181 uint64_t inv_lcrc:1;
182 } s;
183 struct cvmx_pescx_ctl_status_s cn52xx;
184 struct cvmx_pescx_ctl_status_s cn52xxp1;
185 struct cvmx_pescx_ctl_status_cn56xx {
186 uint64_t reserved_28_63:36;
187 uint64_t dnum:5;
188 uint64_t pbus:8;
189 uint64_t qlm_cfg:2;
190 uint64_t reserved_12_12:1;
191 uint64_t pm_xtoff:1;
192 uint64_t pm_xpme:1;
193 uint64_t ob_p_cmd:1;
194 uint64_t reserved_7_8:2;
195 uint64_t nf_ecrc:1;
196 uint64_t dly_one:1;
197 uint64_t lnk_enb:1;
198 uint64_t ro_ctlp:1;
199 uint64_t reserved_2_2:1;
200 uint64_t inv_ecrc:1;
201 uint64_t inv_lcrc:1;
202 } cn56xx;
203 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1;
204};
205
206union cvmx_pescx_ctl_status2 {
207 uint64_t u64;
208 struct cvmx_pescx_ctl_status2_s {
209 uint64_t reserved_2_63:62;
210 uint64_t pclk_run:1;
211 uint64_t pcierst:1;
212 } s;
213 struct cvmx_pescx_ctl_status2_s cn52xx;
214 struct cvmx_pescx_ctl_status2_cn52xxp1 {
215 uint64_t reserved_1_63:63;
216 uint64_t pcierst:1;
217 } cn52xxp1;
218 struct cvmx_pescx_ctl_status2_s cn56xx;
219 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1;
220};
221
222union cvmx_pescx_dbg_info {
223 uint64_t u64;
224 struct cvmx_pescx_dbg_info_s {
225 uint64_t reserved_31_63:33;
226 uint64_t ecrc_e:1;
227 uint64_t rawwpp:1;
228 uint64_t racpp:1;
229 uint64_t ramtlp:1;
230 uint64_t rarwdns:1;
231 uint64_t caar:1;
232 uint64_t racca:1;
233 uint64_t racur:1;
234 uint64_t rauc:1;
235 uint64_t rqo:1;
236 uint64_t fcuv:1;
237 uint64_t rpe:1;
238 uint64_t fcpvwt:1;
239 uint64_t dpeoosd:1;
240 uint64_t rtwdle:1;
241 uint64_t rdwdle:1;
242 uint64_t mre:1;
243 uint64_t rte:1;
244 uint64_t acto:1;
245 uint64_t rvdm:1;
246 uint64_t rumep:1;
247 uint64_t rptamrc:1;
248 uint64_t rpmerc:1;
249 uint64_t rfemrc:1;
250 uint64_t rnfemrc:1;
251 uint64_t rcemrc:1;
252 uint64_t rpoison:1;
253 uint64_t recrce:1;
254 uint64_t rtlplle:1;
255 uint64_t rtlpmal:1;
256 uint64_t spoison:1;
257 } s;
258 struct cvmx_pescx_dbg_info_s cn52xx;
259 struct cvmx_pescx_dbg_info_s cn52xxp1;
260 struct cvmx_pescx_dbg_info_s cn56xx;
261 struct cvmx_pescx_dbg_info_s cn56xxp1;
262};
263
264union cvmx_pescx_dbg_info_en {
265 uint64_t u64;
266 struct cvmx_pescx_dbg_info_en_s {
267 uint64_t reserved_31_63:33;
268 uint64_t ecrc_e:1;
269 uint64_t rawwpp:1;
270 uint64_t racpp:1;
271 uint64_t ramtlp:1;
272 uint64_t rarwdns:1;
273 uint64_t caar:1;
274 uint64_t racca:1;
275 uint64_t racur:1;
276 uint64_t rauc:1;
277 uint64_t rqo:1;
278 uint64_t fcuv:1;
279 uint64_t rpe:1;
280 uint64_t fcpvwt:1;
281 uint64_t dpeoosd:1;
282 uint64_t rtwdle:1;
283 uint64_t rdwdle:1;
284 uint64_t mre:1;
285 uint64_t rte:1;
286 uint64_t acto:1;
287 uint64_t rvdm:1;
288 uint64_t rumep:1;
289 uint64_t rptamrc:1;
290 uint64_t rpmerc:1;
291 uint64_t rfemrc:1;
292 uint64_t rnfemrc:1;
293 uint64_t rcemrc:1;
294 uint64_t rpoison:1;
295 uint64_t recrce:1;
296 uint64_t rtlplle:1;
297 uint64_t rtlpmal:1;
298 uint64_t spoison:1;
299 } s;
300 struct cvmx_pescx_dbg_info_en_s cn52xx;
301 struct cvmx_pescx_dbg_info_en_s cn52xxp1;
302 struct cvmx_pescx_dbg_info_en_s cn56xx;
303 struct cvmx_pescx_dbg_info_en_s cn56xxp1;
304};
305
306union cvmx_pescx_diag_status {
307 uint64_t u64;
308 struct cvmx_pescx_diag_status_s {
309 uint64_t reserved_4_63:60;
310 uint64_t pm_dst:1;
311 uint64_t pm_stat:1;
312 uint64_t pm_en:1;
313 uint64_t aux_en:1;
314 } s;
315 struct cvmx_pescx_diag_status_s cn52xx;
316 struct cvmx_pescx_diag_status_s cn52xxp1;
317 struct cvmx_pescx_diag_status_s cn56xx;
318 struct cvmx_pescx_diag_status_s cn56xxp1;
319};
320
321union cvmx_pescx_p2n_bar0_start {
322 uint64_t u64;
323 struct cvmx_pescx_p2n_bar0_start_s {
324 uint64_t addr:50;
325 uint64_t reserved_0_13:14;
326 } s;
327 struct cvmx_pescx_p2n_bar0_start_s cn52xx;
328 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1;
329 struct cvmx_pescx_p2n_bar0_start_s cn56xx;
330 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1;
331};
332
333union cvmx_pescx_p2n_bar1_start {
334 uint64_t u64;
335 struct cvmx_pescx_p2n_bar1_start_s {
336 uint64_t addr:38;
337 uint64_t reserved_0_25:26;
338 } s;
339 struct cvmx_pescx_p2n_bar1_start_s cn52xx;
340 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1;
341 struct cvmx_pescx_p2n_bar1_start_s cn56xx;
342 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1;
343};
344
345union cvmx_pescx_p2n_bar2_start {
346 uint64_t u64;
347 struct cvmx_pescx_p2n_bar2_start_s {
348 uint64_t addr:25;
349 uint64_t reserved_0_38:39;
350 } s;
351 struct cvmx_pescx_p2n_bar2_start_s cn52xx;
352 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1;
353 struct cvmx_pescx_p2n_bar2_start_s cn56xx;
354 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1;
355};
356
357union cvmx_pescx_p2p_barx_end {
358 uint64_t u64;
359 struct cvmx_pescx_p2p_barx_end_s {
360 uint64_t addr:52;
361 uint64_t reserved_0_11:12;
362 } s;
363 struct cvmx_pescx_p2p_barx_end_s cn52xx;
364 struct cvmx_pescx_p2p_barx_end_s cn52xxp1;
365 struct cvmx_pescx_p2p_barx_end_s cn56xx;
366 struct cvmx_pescx_p2p_barx_end_s cn56xxp1;
367};
368
369union cvmx_pescx_p2p_barx_start {
370 uint64_t u64;
371 struct cvmx_pescx_p2p_barx_start_s {
372 uint64_t addr:52;
373 uint64_t reserved_0_11:12;
374 } s;
375 struct cvmx_pescx_p2p_barx_start_s cn52xx;
376 struct cvmx_pescx_p2p_barx_start_s cn52xxp1;
377 struct cvmx_pescx_p2p_barx_start_s cn56xx;
378 struct cvmx_pescx_p2p_barx_start_s cn56xxp1;
379};
380
381union cvmx_pescx_tlp_credits {
382 uint64_t u64;
383 struct cvmx_pescx_tlp_credits_s {
384 uint64_t reserved_0_63:64;
385 } s;
386 struct cvmx_pescx_tlp_credits_cn52xx {
387 uint64_t reserved_56_63:8;
388 uint64_t peai_ppf:8;
389 uint64_t pesc_cpl:8;
390 uint64_t pesc_np:8;
391 uint64_t pesc_p:8;
392 uint64_t npei_cpl:8;
393 uint64_t npei_np:8;
394 uint64_t npei_p:8;
395 } cn52xx;
396 struct cvmx_pescx_tlp_credits_cn52xxp1 {
397 uint64_t reserved_38_63:26;
398 uint64_t peai_ppf:8;
399 uint64_t pesc_cpl:5;
400 uint64_t pesc_np:5;
401 uint64_t pesc_p:5;
402 uint64_t npei_cpl:5;
403 uint64_t npei_np:5;
404 uint64_t npei_p:5;
405 } cn52xxp1;
406 struct cvmx_pescx_tlp_credits_cn52xx cn56xx;
407 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1;
408};
409
410#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-pexp-defs.h b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
new file mode 100644
index 000000000000..5ea5dc571b54
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pexp-defs.h
@@ -0,0 +1,229 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * cvmx-pexp-defs.h
30 *
31 * Configuration and status register (CSR) definitions for
32 * OCTEON PEXP.
33 *
34 */
35#ifndef __CVMX_PEXP_DEFS_H__
36#define __CVMX_PEXP_DEFS_H__
37
38#define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) \
39 CVMX_ADD_IO_SEG(0x00011F0000008000ull + (((offset) & 31) * 16))
40#define CVMX_PEXP_NPEI_BIST_STATUS \
41 CVMX_ADD_IO_SEG(0x00011F0000008580ull)
42#define CVMX_PEXP_NPEI_BIST_STATUS2 \
43 CVMX_ADD_IO_SEG(0x00011F0000008680ull)
44#define CVMX_PEXP_NPEI_CTL_PORT0 \
45 CVMX_ADD_IO_SEG(0x00011F0000008250ull)
46#define CVMX_PEXP_NPEI_CTL_PORT1 \
47 CVMX_ADD_IO_SEG(0x00011F0000008260ull)
48#define CVMX_PEXP_NPEI_CTL_STATUS \
49 CVMX_ADD_IO_SEG(0x00011F0000008570ull)
50#define CVMX_PEXP_NPEI_CTL_STATUS2 \
51 CVMX_ADD_IO_SEG(0x00011F000000BC00ull)
52#define CVMX_PEXP_NPEI_DATA_OUT_CNT \
53 CVMX_ADD_IO_SEG(0x00011F00000085F0ull)
54#define CVMX_PEXP_NPEI_DBG_DATA \
55 CVMX_ADD_IO_SEG(0x00011F0000008510ull)
56#define CVMX_PEXP_NPEI_DBG_SELECT \
57 CVMX_ADD_IO_SEG(0x00011F0000008500ull)
58#define CVMX_PEXP_NPEI_DMA0_INT_LEVEL \
59 CVMX_ADD_IO_SEG(0x00011F00000085C0ull)
60#define CVMX_PEXP_NPEI_DMA1_INT_LEVEL \
61 CVMX_ADD_IO_SEG(0x00011F00000085D0ull)
62#define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) \
63 CVMX_ADD_IO_SEG(0x00011F0000008450ull + (((offset) & 7) * 16))
64#define CVMX_PEXP_NPEI_DMAX_DBELL(offset) \
65 CVMX_ADD_IO_SEG(0x00011F00000083B0ull + (((offset) & 7) * 16))
66#define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) \
67 CVMX_ADD_IO_SEG(0x00011F0000008400ull + (((offset) & 7) * 16))
68#define CVMX_PEXP_NPEI_DMAX_NADDR(offset) \
69 CVMX_ADD_IO_SEG(0x00011F00000084A0ull + (((offset) & 7) * 16))
70#define CVMX_PEXP_NPEI_DMA_CNTS \
71 CVMX_ADD_IO_SEG(0x00011F00000085E0ull)
72#define CVMX_PEXP_NPEI_DMA_CONTROL \
73 CVMX_ADD_IO_SEG(0x00011F00000083A0ull)
74#define CVMX_PEXP_NPEI_INT_A_ENB \
75 CVMX_ADD_IO_SEG(0x00011F0000008560ull)
76#define CVMX_PEXP_NPEI_INT_A_ENB2 \
77 CVMX_ADD_IO_SEG(0x00011F000000BCE0ull)
78#define CVMX_PEXP_NPEI_INT_A_SUM \
79 CVMX_ADD_IO_SEG(0x00011F0000008550ull)
80#define CVMX_PEXP_NPEI_INT_ENB \
81 CVMX_ADD_IO_SEG(0x00011F0000008540ull)
82#define CVMX_PEXP_NPEI_INT_ENB2 \
83 CVMX_ADD_IO_SEG(0x00011F000000BCD0ull)
84#define CVMX_PEXP_NPEI_INT_INFO \
85 CVMX_ADD_IO_SEG(0x00011F0000008590ull)
86#define CVMX_PEXP_NPEI_INT_SUM \
87 CVMX_ADD_IO_SEG(0x00011F0000008530ull)
88#define CVMX_PEXP_NPEI_INT_SUM2 \
89 CVMX_ADD_IO_SEG(0x00011F000000BCC0ull)
90#define CVMX_PEXP_NPEI_LAST_WIN_RDATA0 \
91 CVMX_ADD_IO_SEG(0x00011F0000008600ull)
92#define CVMX_PEXP_NPEI_LAST_WIN_RDATA1 \
93 CVMX_ADD_IO_SEG(0x00011F0000008610ull)
94#define CVMX_PEXP_NPEI_MEM_ACCESS_CTL \
95 CVMX_ADD_IO_SEG(0x00011F00000084F0ull)
96#define CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(offset) \
97 CVMX_ADD_IO_SEG(0x00011F0000008280ull + (((offset) & 31) * 16) - 16 * 12)
98#define CVMX_PEXP_NPEI_MSI_ENB0 \
99 CVMX_ADD_IO_SEG(0x00011F000000BC50ull)
100#define CVMX_PEXP_NPEI_MSI_ENB1 \
101 CVMX_ADD_IO_SEG(0x00011F000000BC60ull)
102#define CVMX_PEXP_NPEI_MSI_ENB2 \
103 CVMX_ADD_IO_SEG(0x00011F000000BC70ull)
104#define CVMX_PEXP_NPEI_MSI_ENB3 \
105 CVMX_ADD_IO_SEG(0x00011F000000BC80ull)
106#define CVMX_PEXP_NPEI_MSI_RCV0 \
107 CVMX_ADD_IO_SEG(0x00011F000000BC10ull)
108#define CVMX_PEXP_NPEI_MSI_RCV1 \
109 CVMX_ADD_IO_SEG(0x00011F000000BC20ull)
110#define CVMX_PEXP_NPEI_MSI_RCV2 \
111 CVMX_ADD_IO_SEG(0x00011F000000BC30ull)
112#define CVMX_PEXP_NPEI_MSI_RCV3 \
113 CVMX_ADD_IO_SEG(0x00011F000000BC40ull)
114#define CVMX_PEXP_NPEI_MSI_RD_MAP \
115 CVMX_ADD_IO_SEG(0x00011F000000BCA0ull)
116#define CVMX_PEXP_NPEI_MSI_W1C_ENB0 \
117 CVMX_ADD_IO_SEG(0x00011F000000BCF0ull)
118#define CVMX_PEXP_NPEI_MSI_W1C_ENB1 \
119 CVMX_ADD_IO_SEG(0x00011F000000BD00ull)
120#define CVMX_PEXP_NPEI_MSI_W1C_ENB2 \
121 CVMX_ADD_IO_SEG(0x00011F000000BD10ull)
122#define CVMX_PEXP_NPEI_MSI_W1C_ENB3 \
123 CVMX_ADD_IO_SEG(0x00011F000000BD20ull)
124#define CVMX_PEXP_NPEI_MSI_W1S_ENB0 \
125 CVMX_ADD_IO_SEG(0x00011F000000BD30ull)
126#define CVMX_PEXP_NPEI_MSI_W1S_ENB1 \
127 CVMX_ADD_IO_SEG(0x00011F000000BD40ull)
128#define CVMX_PEXP_NPEI_MSI_W1S_ENB2 \
129 CVMX_ADD_IO_SEG(0x00011F000000BD50ull)
130#define CVMX_PEXP_NPEI_MSI_W1S_ENB3 \
131 CVMX_ADD_IO_SEG(0x00011F000000BD60ull)
132#define CVMX_PEXP_NPEI_MSI_WR_MAP \
133 CVMX_ADD_IO_SEG(0x00011F000000BC90ull)
134#define CVMX_PEXP_NPEI_PCIE_CREDIT_CNT \
135 CVMX_ADD_IO_SEG(0x00011F000000BD70ull)
136#define CVMX_PEXP_NPEI_PCIE_MSI_RCV \
137 CVMX_ADD_IO_SEG(0x00011F000000BCB0ull)
138#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B1 \
139 CVMX_ADD_IO_SEG(0x00011F0000008650ull)
140#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B2 \
141 CVMX_ADD_IO_SEG(0x00011F0000008660ull)
142#define CVMX_PEXP_NPEI_PCIE_MSI_RCV_B3 \
143 CVMX_ADD_IO_SEG(0x00011F0000008670ull)
144#define CVMX_PEXP_NPEI_PKTX_CNTS(offset) \
145 CVMX_ADD_IO_SEG(0x00011F000000A400ull + (((offset) & 31) * 16))
146#define CVMX_PEXP_NPEI_PKTX_INSTR_BADDR(offset) \
147 CVMX_ADD_IO_SEG(0x00011F000000A800ull + (((offset) & 31) * 16))
148#define CVMX_PEXP_NPEI_PKTX_INSTR_BAOFF_DBELL(offset) \
149 CVMX_ADD_IO_SEG(0x00011F000000AC00ull + (((offset) & 31) * 16))
150#define CVMX_PEXP_NPEI_PKTX_INSTR_FIFO_RSIZE(offset) \
151 CVMX_ADD_IO_SEG(0x00011F000000B000ull + (((offset) & 31) * 16))
152#define CVMX_PEXP_NPEI_PKTX_INSTR_HEADER(offset) \
153 CVMX_ADD_IO_SEG(0x00011F000000B400ull + (((offset) & 31) * 16))
154#define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) \
155 CVMX_ADD_IO_SEG(0x00011F000000B800ull + (((offset) & 31) * 16))
156#define CVMX_PEXP_NPEI_PKTX_SLIST_BADDR(offset) \
157 CVMX_ADD_IO_SEG(0x00011F0000009400ull + (((offset) & 31) * 16))
158#define CVMX_PEXP_NPEI_PKTX_SLIST_BAOFF_DBELL(offset) \
159 CVMX_ADD_IO_SEG(0x00011F0000009800ull + (((offset) & 31) * 16))
160#define CVMX_PEXP_NPEI_PKTX_SLIST_FIFO_RSIZE(offset) \
161 CVMX_ADD_IO_SEG(0x00011F0000009C00ull + (((offset) & 31) * 16))
162#define CVMX_PEXP_NPEI_PKT_CNT_INT \
163 CVMX_ADD_IO_SEG(0x00011F0000009110ull)
164#define CVMX_PEXP_NPEI_PKT_CNT_INT_ENB \
165 CVMX_ADD_IO_SEG(0x00011F0000009130ull)
166#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ES \
167 CVMX_ADD_IO_SEG(0x00011F00000090B0ull)
168#define CVMX_PEXP_NPEI_PKT_DATA_OUT_NS \
169 CVMX_ADD_IO_SEG(0x00011F00000090A0ull)
170#define CVMX_PEXP_NPEI_PKT_DATA_OUT_ROR \
171 CVMX_ADD_IO_SEG(0x00011F0000009090ull)
172#define CVMX_PEXP_NPEI_PKT_DPADDR \
173 CVMX_ADD_IO_SEG(0x00011F0000009080ull)
174#define CVMX_PEXP_NPEI_PKT_INPUT_CONTROL \
175 CVMX_ADD_IO_SEG(0x00011F0000009150ull)
176#define CVMX_PEXP_NPEI_PKT_INSTR_ENB \
177 CVMX_ADD_IO_SEG(0x00011F0000009000ull)
178#define CVMX_PEXP_NPEI_PKT_INSTR_RD_SIZE \
179 CVMX_ADD_IO_SEG(0x00011F0000009190ull)
180#define CVMX_PEXP_NPEI_PKT_INSTR_SIZE \
181 CVMX_ADD_IO_SEG(0x00011F0000009020ull)
182#define CVMX_PEXP_NPEI_PKT_INT_LEVELS \
183 CVMX_ADD_IO_SEG(0x00011F0000009100ull)
184#define CVMX_PEXP_NPEI_PKT_IN_BP \
185 CVMX_ADD_IO_SEG(0x00011F00000086B0ull)
186#define CVMX_PEXP_NPEI_PKT_IN_DONEX_CNTS(offset) \
187 CVMX_ADD_IO_SEG(0x00011F000000A000ull + (((offset) & 31) * 16))
188#define CVMX_PEXP_NPEI_PKT_IN_INSTR_COUNTS \
189 CVMX_ADD_IO_SEG(0x00011F00000086A0ull)
190#define CVMX_PEXP_NPEI_PKT_IN_PCIE_PORT \
191 CVMX_ADD_IO_SEG(0x00011F00000091A0ull)
192#define CVMX_PEXP_NPEI_PKT_IPTR \
193 CVMX_ADD_IO_SEG(0x00011F0000009070ull)
194#define CVMX_PEXP_NPEI_PKT_OUTPUT_WMARK \
195 CVMX_ADD_IO_SEG(0x00011F0000009160ull)
196#define CVMX_PEXP_NPEI_PKT_OUT_BMODE \
197 CVMX_ADD_IO_SEG(0x00011F00000090D0ull)
198#define CVMX_PEXP_NPEI_PKT_OUT_ENB \
199 CVMX_ADD_IO_SEG(0x00011F0000009010ull)
200#define CVMX_PEXP_NPEI_PKT_PCIE_PORT \
201 CVMX_ADD_IO_SEG(0x00011F00000090E0ull)
202#define CVMX_PEXP_NPEI_PKT_PORT_IN_RST \
203 CVMX_ADD_IO_SEG(0x00011F0000008690ull)
204#define CVMX_PEXP_NPEI_PKT_SLIST_ES \
205 CVMX_ADD_IO_SEG(0x00011F0000009050ull)
206#define CVMX_PEXP_NPEI_PKT_SLIST_ID_SIZE \
207 CVMX_ADD_IO_SEG(0x00011F0000009180ull)
208#define CVMX_PEXP_NPEI_PKT_SLIST_NS \
209 CVMX_ADD_IO_SEG(0x00011F0000009040ull)
210#define CVMX_PEXP_NPEI_PKT_SLIST_ROR \
211 CVMX_ADD_IO_SEG(0x00011F0000009030ull)
212#define CVMX_PEXP_NPEI_PKT_TIME_INT \
213 CVMX_ADD_IO_SEG(0x00011F0000009120ull)
214#define CVMX_PEXP_NPEI_PKT_TIME_INT_ENB \
215 CVMX_ADD_IO_SEG(0x00011F0000009140ull)
216#define CVMX_PEXP_NPEI_RSL_INT_BLOCKS \
217 CVMX_ADD_IO_SEG(0x00011F0000008520ull)
218#define CVMX_PEXP_NPEI_SCRATCH_1 \
219 CVMX_ADD_IO_SEG(0x00011F0000008270ull)
220#define CVMX_PEXP_NPEI_STATE1 \
221 CVMX_ADD_IO_SEG(0x00011F0000008620ull)
222#define CVMX_PEXP_NPEI_STATE2 \
223 CVMX_ADD_IO_SEG(0x00011F0000008630ull)
224#define CVMX_PEXP_NPEI_STATE3 \
225 CVMX_ADD_IO_SEG(0x00011F0000008640ull)
226#define CVMX_PEXP_NPEI_WINDOW_CTL \
227 CVMX_ADD_IO_SEG(0x00011F0000008380ull)
228
229#endif
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index 03fddfa3e928..e31e3fe14f8a 100644
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -376,6 +376,18 @@ static inline uint64_t cvmx_get_cycle(void)
376} 376}
377 377
378/** 378/**
379 * Wait for the specified number of cycle
380 *
381 */
382static inline void cvmx_wait(uint64_t cycles)
383{
384 uint64_t done = cvmx_get_cycle() + cycles;
385
386 while (cvmx_get_cycle() < done)
387 ; /* Spin */
388}
389
390/**
379 * Reads a chip global cycle counter. This counts CPU cycles since 391 * Reads a chip global cycle counter. This counts CPU cycles since
380 * chip reset. The counter is 64 bit. 392 * chip reset. The counter is 64 bit.
381 * This register does not exist on CN38XX pass 1 silicion 393 * This register does not exist on CN38XX pass 1 silicion
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index 04fac684069c..ef24a7b4ea57 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -57,6 +57,13 @@ enum octeon_feature {
57 OCTEON_FEATURE_RAID, 57 OCTEON_FEATURE_RAID,
58 /* Octeon has a builtin USB */ 58 /* Octeon has a builtin USB */
59 OCTEON_FEATURE_USB, 59 OCTEON_FEATURE_USB,
60 /* Octeon IPD can run without using work queue entries */
61 OCTEON_FEATURE_NO_WPTR,
62 /* Octeon has DFA state machines */
63 OCTEON_FEATURE_DFA,
64 /* Octeon MDIO block supports clause 45 transactions for 10
65 * Gig support */
66 OCTEON_FEATURE_MDIO_CLAUSE_45,
60}; 67};
61 68
62static inline int cvmx_fuse_read(int fuse); 69static inline int cvmx_fuse_read(int fuse);
@@ -112,6 +119,26 @@ static inline int octeon_has_feature(enum octeon_feature feature)
112 case OCTEON_FEATURE_USB: 119 case OCTEON_FEATURE_USB:
113 return !(OCTEON_IS_MODEL(OCTEON_CN38XX) 120 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
114 || OCTEON_IS_MODEL(OCTEON_CN58XX)); 121 || OCTEON_IS_MODEL(OCTEON_CN58XX));
122 case OCTEON_FEATURE_NO_WPTR:
123 return (OCTEON_IS_MODEL(OCTEON_CN56XX)
124 || OCTEON_IS_MODEL(OCTEON_CN52XX))
125 && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
126 && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X);
127 case OCTEON_FEATURE_DFA:
128 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
129 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
130 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
131 return 0;
132 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
133 return 0;
134 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
135 return 1;
136 else
137 return !cvmx_fuse_read(120);
138 case OCTEON_FEATURE_MDIO_CLAUSE_45:
139 return !(OCTEON_IS_MODEL(OCTEON_CN3XXX)
140 || OCTEON_IS_MODEL(OCTEON_CN58XX)
141 || OCTEON_IS_MODEL(OCTEON_CN50XX));
115 } 142 }
116 return 0; 143 return 0;
117} 144}
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index edc676084cda..cac9b1a206fc 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -245,4 +245,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
245 return cvmx_read64_uint32(address ^ 4); 245 return cvmx_read64_uint32(address ^ 4);
246} 246}
247 247
248extern struct cvmx_bootinfo *octeon_bootinfo;
249
248#endif /* __ASM_OCTEON_OCTEON_H */ 250#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 72c80d2034c2..dc0eaa731281 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -32,6 +32,11 @@
32#define PAGE_SIZE (1UL << PAGE_SHIFT) 32#define PAGE_SIZE (1UL << PAGE_SHIFT)
33#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1)) 33#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
34 34
35#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
36#define HPAGE_SIZE ((1UL) << HPAGE_SHIFT)
37#define HPAGE_MASK (~(HPAGE_SIZE - 1))
38#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
39
35#ifndef __ASSEMBLY__ 40#ifndef __ASSEMBLY__
36 41
37#include <linux/pfn.h> 42#include <linux/pfn.h>
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 51b34a48c84a..1073e6df8621 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -72,6 +72,7 @@
72#else 72#else
73 73
74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ 74#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
75#define _PAGE_HUGE (1<<5) /* huge tlb page */
75#define _PAGE_GLOBAL (1<<6) 76#define _PAGE_GLOBAL (1<<6)
76#define _PAGE_VALID (1<<7) 77#define _PAGE_VALID (1<<7)
77#define _PAGE_SILENT_READ (1<<7) /* synonym */ 78#define _PAGE_SILENT_READ (1<<7) /* synonym */
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 6a0edf72ffbc..1a9f9b257551 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -292,6 +292,16 @@ static inline pte_t pte_mkyoung(pte_t pte)
292 pte_val(pte) |= _PAGE_SILENT_READ; 292 pte_val(pte) |= _PAGE_SILENT_READ;
293 return pte; 293 return pte;
294} 294}
295
296#ifdef _PAGE_HUGE
297static inline int pte_huge(pte_t pte) { return pte_val(pte) & _PAGE_HUGE; }
298
299static inline pte_t pte_mkhuge(pte_t pte)
300{
301 pte_val(pte) |= _PAGE_HUGE;
302 return pte;
303}
304#endif /* _PAGE_HUGE */
295#endif 305#endif
296static inline int pte_special(pte_t pte) { return 0; } 306static inline int pte_special(pte_t pte) { return 0; }
297static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 307static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 4c140db36786..387bf59f1e37 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -399,6 +399,7 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
399__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) 399__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
400__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) 400__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
401__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32) 401__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
402__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
402__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) 403__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
403__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64) 404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
404__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128) 405__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
new file mode 100644
index 000000000000..294cdb66c5fc
--- /dev/null
+++ b/arch/mips/include/asm/suspend.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_SUSPEND_H
2#define __ASM_SUSPEND_H
3
4static inline int arch_prepare_suspend(void) { return 0; }
5
6/* References to section boundaries */
7extern const void __nosave_begin, __nosave_end;
8
9#endif /* __ASM_SUSPEND_H */
diff --git a/arch/mips/include/asm/txx9/dmac.h b/arch/mips/include/asm/txx9/dmac.h
new file mode 100644
index 000000000000..5e9151fccbb4
--- /dev/null
+++ b/arch/mips/include/asm/txx9/dmac.h
@@ -0,0 +1,51 @@
1/*
2 * TXx9 SoC DMA Controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_TXX9_DMAC_H
10#define __ASM_TXX9_DMAC_H
11
12#include <linux/dmaengine.h>
13
14#define TXX9_DMA_MAX_NR_CHANNELS 4
15
16/**
17 * struct txx9dmac_platform_data - Controller configuration parameters
18 * @memcpy_chan: Channel used for DMA_MEMCPY
19 * @have_64bit_regs: DMAC have 64 bit registers
20 */
21struct txx9dmac_platform_data {
22 int memcpy_chan;
23 bool have_64bit_regs;
24};
25
26/**
27 * struct txx9dmac_chan_platform_data - Channel configuration parameters
28 * @dmac_dev: A platform device for DMAC
29 */
30struct txx9dmac_chan_platform_data {
31 struct platform_device *dmac_dev;
32};
33
34/**
35 * struct txx9dmac_slave - Controller-specific information about a slave
36 * @tx_reg: physical address of data register used for
37 * memory-to-peripheral transfers
38 * @rx_reg: physical address of data register used for
39 * peripheral-to-memory transfers
40 * @reg_width: peripheral register width
41 */
42struct txx9dmac_slave {
43 u64 tx_reg;
44 u64 rx_reg;
45 unsigned int reg_width;
46};
47
48void txx9_dmac_init(int id, unsigned long baseaddr, int irq,
49 const struct txx9dmac_platform_data *pdata);
50
51#endif /* __ASM_TXX9_DMAC_H */
diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h
index 9cde0090cbf6..827dc22be2ea 100644
--- a/arch/mips/include/asm/txx9/generic.h
+++ b/arch/mips/include/asm/txx9/generic.h
@@ -91,4 +91,10 @@ void txx9_7segled_init(unsigned int num,
91 void (*putc)(unsigned int pos, unsigned char val)); 91 void (*putc)(unsigned int pos, unsigned char val));
92int txx9_7segled_putc(unsigned int pos, char c); 92int txx9_7segled_putc(unsigned int pos, char c);
93 93
94void __init txx9_aclc_init(unsigned long baseaddr, int irq,
95 unsigned int dmac_id,
96 unsigned int dma_chan_out,
97 unsigned int dma_chan_in);
98void __init txx9_sramc_init(struct resource *r);
99
94#endif /* __ASM_TXX9_GENERIC_H */ 100#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
index 7d813f1cb98d..18c98c52afdb 100644
--- a/arch/mips/include/asm/txx9/tx4927.h
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -41,6 +41,7 @@
41 41
42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000) 42#define TX4927_SDRAMC_REG (TX4927_REG_BASE + 0x8000)
43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000) 43#define TX4927_EBUSC_REG (TX4927_REG_BASE + 0x9000)
44#define TX4927_DMA_REG (TX4927_REG_BASE + 0xb000)
44#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000) 45#define TX4927_PCIC_REG (TX4927_REG_BASE + 0xd000)
45#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000) 46#define TX4927_CCFG_REG (TX4927_REG_BASE + 0xe000)
46#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600) 47#define TX4927_IRC_REG (TX4927_REG_BASE + 0xf600)
@@ -49,6 +50,7 @@
49#define TX4927_NR_SIO 2 50#define TX4927_NR_SIO 2
50#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100) 51#define TX4927_SIO_REG(ch) (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
51#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500) 52#define TX4927_PIO_REG (TX4927_REG_BASE + 0xf500)
53#define TX4927_ACLC_REG (TX4927_REG_BASE + 0xf700)
52 54
53#define TX4927_IR_ECCERR 0 55#define TX4927_IR_ECCERR 0
54#define TX4927_IR_WTOERR 1 56#define TX4927_IR_WTOERR 1
@@ -265,5 +267,7 @@ int tx4927_pciclk66_setup(void);
265void tx4927_setup_pcierr_irq(void); 267void tx4927_setup_pcierr_irq(void);
266void tx4927_irq_init(void); 268void tx4927_irq_init(void);
267void tx4927_mtd_init(int ch); 269void tx4927_mtd_init(int ch);
270void tx4927_dmac_init(int memcpy_chan);
271void tx4927_aclc_init(unsigned int dma_chan_out, unsigned int dma_chan_in);
268 272
269#endif /* __ASM_TXX9_TX4927_H */ 273#endif /* __ASM_TXX9_TX4927_H */
diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index cd8bc2021755..8a178f186f7d 100644
--- a/arch/mips/include/asm/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -305,5 +305,8 @@ struct tx4938ide_platform_info {
305}; 305};
306 306
307void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune); 307void tx4938_ata_init(unsigned int irq, unsigned int shift, int tune);
308void tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1);
309void tx4938_aclc_init(void);
310void tx4938_sramc_init(void);
308 311
309#endif 312#endif
diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index f02c50b3abfb..d4f342cd5939 100644
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -45,6 +45,8 @@
45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00) 45#define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00)
46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00) 46#define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00)
47 47
48#define TX4939_RNG_REG (TX4939_CRYPTO_REG + 0xb0)
49
48struct tx4939_le_reg { 50struct tx4939_le_reg {
49 __u32 r; 51 __u32 r;
50 __u32 unused; 52 __u32 unused;
@@ -544,5 +546,9 @@ void tx4939_ata_init(void);
544void tx4939_rtc_init(void); 546void tx4939_rtc_init(void);
545void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, 547void tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
546 unsigned char ch_mask, unsigned char wide_mask); 548 unsigned char ch_mask, unsigned char wide_mask);
549void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1);
550void tx4939_aclc_init(void);
551void tx4939_sramc_init(void);
552void tx4939_rng_init(void);
547 553
548#endif /* __ASM_TXX9_TX4939_H */ 554#endif /* __ASM_TXX9_TX4939_H */
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index c901c22d7ad0..8d006ec65677 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -14,6 +14,7 @@
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/kbuild.h> 16#include <linux/kbuild.h>
17#include <linux/suspend.h>
17#include <asm/ptrace.h> 18#include <asm/ptrace.h>
18#include <asm/processor.h> 19#include <asm/processor.h>
19 20
@@ -326,3 +327,15 @@ void output_octeon_cop2_state_defines(void)
326 BLANK(); 327 BLANK();
327} 328}
328#endif 329#endif
330
331#ifdef CONFIG_HIBERNATION
332void output_pbe_defines(void)
333{
334 COMMENT(" Linux struct pbe offsets. ");
335 OFFSET(PBE_ADDRESS, pbe, address);
336 OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address);
337 OFFSET(PBE_NEXT, pbe, next);
338 DEFINE(PBE_SIZE, sizeof(struct pbe));
339 BLANK();
340}
341#endif
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index 2e911e3da8d3..0037f21baf0d 100644
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -20,22 +20,29 @@
20#define TIMER_CCD 0 /* 1/2 */ 20#define TIMER_CCD 0 /* 1/2 */
21#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD)) 21#define TIMER_CLK(imclk) ((imclk) / (2 << TIMER_CCD))
22 22
23static struct txx9_tmr_reg __iomem *txx9_cs_tmrptr; 23struct txx9_clocksource {
24 struct clocksource cs;
25 struct txx9_tmr_reg __iomem *tmrptr;
26};
24 27
25static cycle_t txx9_cs_read(struct clocksource *cs) 28static cycle_t txx9_cs_read(struct clocksource *cs)
26{ 29{
27 return __raw_readl(&txx9_cs_tmrptr->trr); 30 struct txx9_clocksource *txx9_cs =
31 container_of(cs, struct txx9_clocksource, cs);
32 return __raw_readl(&txx9_cs->tmrptr->trr);
28} 33}
29 34
30/* Use 1 bit smaller width to use full bits in that width */ 35/* Use 1 bit smaller width to use full bits in that width */
31#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1) 36#define TXX9_CLOCKSOURCE_BITS (TXX9_TIMER_BITS - 1)
32 37
33static struct clocksource txx9_clocksource = { 38static struct txx9_clocksource txx9_clocksource = {
34 .name = "TXx9", 39 .cs = {
35 .rating = 200, 40 .name = "TXx9",
36 .read = txx9_cs_read, 41 .rating = 200,
37 .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS), 42 .read = txx9_cs_read,
38 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 43 .mask = CLOCKSOURCE_MASK(TXX9_CLOCKSOURCE_BITS),
44 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
45 },
39}; 46};
40 47
41void __init txx9_clocksource_init(unsigned long baseaddr, 48void __init txx9_clocksource_init(unsigned long baseaddr,
@@ -43,8 +50,8 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
43{ 50{
44 struct txx9_tmr_reg __iomem *tmrptr; 51 struct txx9_tmr_reg __iomem *tmrptr;
45 52
46 clocksource_set_clock(&txx9_clocksource, TIMER_CLK(imbusclk)); 53 clocksource_set_clock(&txx9_clocksource.cs, TIMER_CLK(imbusclk));
47 clocksource_register(&txx9_clocksource); 54 clocksource_register(&txx9_clocksource.cs);
48 55
49 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 56 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
50 __raw_writel(TCR_BASE, &tmrptr->tcr); 57 __raw_writel(TCR_BASE, &tmrptr->tcr);
@@ -53,10 +60,13 @@ void __init txx9_clocksource_init(unsigned long baseaddr,
53 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); 60 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);
54 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); 61 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);
55 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); 62 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);
56 txx9_cs_tmrptr = tmrptr; 63 txx9_clocksource.tmrptr = tmrptr;
57} 64}
58 65
59static struct txx9_tmr_reg __iomem *txx9_tmrptr; 66struct txx9_clock_event_device {
67 struct clock_event_device cd;
68 struct txx9_tmr_reg __iomem *tmrptr;
69};
60 70
61static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr) 71static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
62{ 72{
@@ -69,7 +79,9 @@ static void txx9tmr_stop_and_clear(struct txx9_tmr_reg __iomem *tmrptr)
69static void txx9tmr_set_mode(enum clock_event_mode mode, 79static void txx9tmr_set_mode(enum clock_event_mode mode,
70 struct clock_event_device *evt) 80 struct clock_event_device *evt)
71{ 81{
72 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr; 82 struct txx9_clock_event_device *txx9_cd =
83 container_of(evt, struct txx9_clock_event_device, cd);
84 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
73 85
74 txx9tmr_stop_and_clear(tmrptr); 86 txx9tmr_stop_and_clear(tmrptr);
75 switch (mode) { 87 switch (mode) {
@@ -99,7 +111,9 @@ static void txx9tmr_set_mode(enum clock_event_mode mode,
99static int txx9tmr_set_next_event(unsigned long delta, 111static int txx9tmr_set_next_event(unsigned long delta,
100 struct clock_event_device *evt) 112 struct clock_event_device *evt)
101{ 113{
102 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr; 114 struct txx9_clock_event_device *txx9_cd =
115 container_of(evt, struct txx9_clock_event_device, cd);
116 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
103 117
104 txx9tmr_stop_and_clear(tmrptr); 118 txx9tmr_stop_and_clear(tmrptr);
105 /* start timer */ 119 /* start timer */
@@ -108,18 +122,22 @@ static int txx9tmr_set_next_event(unsigned long delta,
108 return 0; 122 return 0;
109} 123}
110 124
111static struct clock_event_device txx9tmr_clock_event_device = { 125static struct txx9_clock_event_device txx9_clock_event_device = {
112 .name = "TXx9", 126 .cd = {
113 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 127 .name = "TXx9",
114 .rating = 200, 128 .features = CLOCK_EVT_FEAT_PERIODIC |
115 .set_mode = txx9tmr_set_mode, 129 CLOCK_EVT_FEAT_ONESHOT,
116 .set_next_event = txx9tmr_set_next_event, 130 .rating = 200,
131 .set_mode = txx9tmr_set_mode,
132 .set_next_event = txx9tmr_set_next_event,
133 },
117}; 134};
118 135
119static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) 136static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
120{ 137{
121 struct clock_event_device *cd = &txx9tmr_clock_event_device; 138 struct txx9_clock_event_device *txx9_cd = dev_id;
122 struct txx9_tmr_reg __iomem *tmrptr = txx9_tmrptr; 139 struct clock_event_device *cd = &txx9_cd->cd;
140 struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
123 141
124 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */ 142 __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
125 cd->event_handler(cd); 143 cd->event_handler(cd);
@@ -130,19 +148,20 @@ static struct irqaction txx9tmr_irq = {
130 .handler = txx9tmr_interrupt, 148 .handler = txx9tmr_interrupt,
131 .flags = IRQF_DISABLED | IRQF_PERCPU, 149 .flags = IRQF_DISABLED | IRQF_PERCPU,
132 .name = "txx9tmr", 150 .name = "txx9tmr",
151 .dev_id = &txx9_clock_event_device,
133}; 152};
134 153
135void __init txx9_clockevent_init(unsigned long baseaddr, int irq, 154void __init txx9_clockevent_init(unsigned long baseaddr, int irq,
136 unsigned int imbusclk) 155 unsigned int imbusclk)
137{ 156{
138 struct clock_event_device *cd = &txx9tmr_clock_event_device; 157 struct clock_event_device *cd = &txx9_clock_event_device.cd;
139 struct txx9_tmr_reg __iomem *tmrptr; 158 struct txx9_tmr_reg __iomem *tmrptr;
140 159
141 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); 160 tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg));
142 txx9tmr_stop_and_clear(tmrptr); 161 txx9tmr_stop_and_clear(tmrptr);
143 __raw_writel(TIMER_CCD, &tmrptr->ccdr); 162 __raw_writel(TIMER_CCD, &tmrptr->ccdr);
144 __raw_writel(0, &tmrptr->itmr); 163 __raw_writel(0, &tmrptr->itmr);
145 txx9_tmrptr = tmrptr; 164 txx9_clock_event_device.tmrptr = tmrptr;
146 165
147 clockevent_set_clock(cd, TIMER_CLK(imbusclk)); 166 clockevent_set_clock(cd, TIMER_CLK(imbusclk));
148 cd->max_delta_ns = 167 cd->max_delta_ns =
diff --git a/arch/mips/kernel/init_task.c b/arch/mips/kernel/init_task.c
index 149cd914526e..5b457a40c784 100644
--- a/arch/mips/kernel/init_task.c
+++ b/arch/mips/kernel/init_task.c
@@ -11,10 +11,6 @@
11 11
12static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 12static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
13static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 13static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
14struct mm_struct init_mm = INIT_MM(init_mm);
15
16EXPORT_SYMBOL(init_mm);
17
18/* 14/*
19 * Initial thread structure. 15 * Initial thread structure.
20 * 16 *
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 5f5af7d4c890..37d51cd124e9 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -924,6 +924,7 @@ void ipi_decode(struct smtc_ipi *pipi)
924 int irq = MIPS_CPU_IRQ_BASE + 1; 924 int irq = MIPS_CPU_IRQ_BASE + 1;
925 925
926 smtc_ipi_nq(&freeIPIq, pipi); 926 smtc_ipi_nq(&freeIPIq, pipi);
927
927 switch (type_copy) { 928 switch (type_copy) {
928 case SMTC_CLOCK_TICK: 929 case SMTC_CLOCK_TICK:
929 irq_enter(); 930 irq_enter();
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e83da174b533..08f1edf355e8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1502,7 +1502,7 @@ void __cpuinit per_cpu_trap_init(void)
1502 status_set); 1502 status_set);
1503 1503
1504 if (cpu_has_mips_r2) { 1504 if (cpu_has_mips_r2) {
1505 unsigned int enable = 0x0000000f; 1505 unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits;
1506 1506
1507 if (!noulri && cpu_has_userlocal) 1507 if (!noulri && cpu_has_userlocal)
1508 enable |= (1 << 29); 1508 enable |= (1 << 29);
@@ -1510,10 +1510,6 @@ void __cpuinit per_cpu_trap_init(void)
1510 write_c0_hwrena(enable); 1510 write_c0_hwrena(enable);
1511 } 1511 }
1512 1512
1513#ifdef CONFIG_CPU_CAVIUM_OCTEON
1514 write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
1515#endif
1516
1517#ifdef CONFIG_MIPS_MT_SMTC 1513#ifdef CONFIG_MIPS_MT_SMTC
1518 if (!secondaryTC) { 1514 if (!secondaryTC) {
1519#endif /* CONFIG_MIPS_MT_SMTC */ 1515#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index f69c6b569eb3..6b3b1de9dcae 100644
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -43,7 +43,7 @@ void __udelay(unsigned long us)
43{ 43{
44 unsigned int lpj = current_cpu_data.udelay_val; 44 unsigned int lpj = current_cpu_data.udelay_val;
45 45
46 __delay((us * 0x000010c7 * HZ * lpj) >> 32); 46 __delay((us * 0x000010c7ull * HZ * lpj) >> 32);
47} 47}
48EXPORT_SYMBOL(__udelay); 48EXPORT_SYMBOL(__udelay);
49 49
@@ -51,6 +51,6 @@ void __ndelay(unsigned long ns)
51{ 51{
52 unsigned int lpj = current_cpu_data.udelay_val; 52 unsigned int lpj = current_cpu_data.udelay_val;
53 53
54 __delay((us * 0x00000005 * HZ * lpj) >> 32); 54 __delay((ns * 0x00000005ull * HZ * lpj) >> 32);
55} 55}
56EXPORT_SYMBOL(__ndelay); 56EXPORT_SYMBOL(__ndelay);
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index d7ec95522292..f0e435599707 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -8,6 +8,7 @@ obj-y += cache.o dma-default.o extable.o fault.o \
8obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o 8obj-$(CONFIG_32BIT) += ioremap.o pgtable-32.o
9obj-$(CONFIG_64BIT) += pgtable-64.o 9obj-$(CONFIG_64BIT) += pgtable-64.o
10obj-$(CONFIG_HIGHMEM) += highmem.o 10obj-$(CONFIG_HIGHMEM) += highmem.o
11obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
11 12
12obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o 13obj-$(CONFIG_CPU_LOONGSON2) += c-r4k.o cex-gen.o tlb-r4k.o
13obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o 14obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o tlb-r4k.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 171951d2305b..71fe4cb778cd 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -100,6 +100,12 @@ static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
100 blast_dcache32_page(addr); 100 blast_dcache32_page(addr);
101} 101}
102 102
103static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
104{
105 R4600_HIT_CACHEOP_WAR_IMPL;
106 blast_dcache64_page(addr);
107}
108
103static void __cpuinit r4k_blast_dcache_page_setup(void) 109static void __cpuinit r4k_blast_dcache_page_setup(void)
104{ 110{
105 unsigned long dc_lsize = cpu_dcache_line_size(); 111 unsigned long dc_lsize = cpu_dcache_line_size();
@@ -110,6 +116,8 @@ static void __cpuinit r4k_blast_dcache_page_setup(void)
110 r4k_blast_dcache_page = blast_dcache16_page; 116 r4k_blast_dcache_page = blast_dcache16_page;
111 else if (dc_lsize == 32) 117 else if (dc_lsize == 32)
112 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32; 118 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
119 else if (dc_lsize == 64)
120 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
113} 121}
114 122
115static void (* r4k_blast_dcache_page_indexed)(unsigned long addr); 123static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
@@ -124,6 +132,8 @@ static void __cpuinit r4k_blast_dcache_page_indexed_setup(void)
124 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed; 132 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
125 else if (dc_lsize == 32) 133 else if (dc_lsize == 32)
126 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed; 134 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
135 else if (dc_lsize == 64)
136 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
127} 137}
128 138
129static void (* r4k_blast_dcache)(void); 139static void (* r4k_blast_dcache)(void);
@@ -138,6 +148,8 @@ static void __cpuinit r4k_blast_dcache_setup(void)
138 r4k_blast_dcache = blast_dcache16; 148 r4k_blast_dcache = blast_dcache16;
139 else if (dc_lsize == 32) 149 else if (dc_lsize == 32)
140 r4k_blast_dcache = blast_dcache32; 150 r4k_blast_dcache = blast_dcache32;
151 else if (dc_lsize == 64)
152 r4k_blast_dcache = blast_dcache64;
141} 153}
142 154
143/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */ 155/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 4fdb7f5216b9..7e48e76148aa 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -20,9 +20,10 @@
20 20
21#include <dma-coherence.h> 21#include <dma-coherence.h>
22 22
23static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr) 23static inline unsigned long dma_addr_to_virt(struct device *dev,
24 dma_addr_t dma_addr)
24{ 25{
25 unsigned long addr = plat_dma_addr_to_phys(dma_addr); 26 unsigned long addr = plat_dma_addr_to_phys(dev, dma_addr);
26 27
27 return (unsigned long)phys_to_virt(addr); 28 return (unsigned long)phys_to_virt(addr);
28} 29}
@@ -111,7 +112,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
111void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, 112void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
112 dma_addr_t dma_handle) 113 dma_addr_t dma_handle)
113{ 114{
114 plat_unmap_dma_mem(dev, dma_handle); 115 plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
115 free_pages((unsigned long) vaddr, get_order(size)); 116 free_pages((unsigned long) vaddr, get_order(size));
116} 117}
117 118
@@ -122,7 +123,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
122{ 123{
123 unsigned long addr = (unsigned long) vaddr; 124 unsigned long addr = (unsigned long) vaddr;
124 125
125 plat_unmap_dma_mem(dev, dma_handle); 126 plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
126 127
127 if (!plat_device_is_coherent(dev)) 128 if (!plat_device_is_coherent(dev))
128 addr = CAC_ADDR(addr); 129 addr = CAC_ADDR(addr);
@@ -170,10 +171,10 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
170 enum dma_data_direction direction) 171 enum dma_data_direction direction)
171{ 172{
172 if (cpu_is_noncoherent_r10000(dev)) 173 if (cpu_is_noncoherent_r10000(dev))
173 __dma_sync(dma_addr_to_virt(dma_addr), size, 174 __dma_sync(dma_addr_to_virt(dev, dma_addr), size,
174 direction); 175 direction);
175 176
176 plat_unmap_dma_mem(dev, dma_addr); 177 plat_unmap_dma_mem(dev, dma_addr, size, direction);
177} 178}
178 179
179EXPORT_SYMBOL(dma_unmap_single); 180EXPORT_SYMBOL(dma_unmap_single);
@@ -232,7 +233,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
232 if (addr) 233 if (addr)
233 __dma_sync(addr, sg->length, direction); 234 __dma_sync(addr, sg->length, direction);
234 } 235 }
235 plat_unmap_dma_mem(dev, sg->dma_address); 236 plat_unmap_dma_mem(dev, sg->dma_address, sg->length, direction);
236 } 237 }
237} 238}
238 239
@@ -246,7 +247,7 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
246 if (cpu_is_noncoherent_r10000(dev)) { 247 if (cpu_is_noncoherent_r10000(dev)) {
247 unsigned long addr; 248 unsigned long addr;
248 249
249 addr = dma_addr_to_virt(dma_handle); 250 addr = dma_addr_to_virt(dev, dma_handle);
250 __dma_sync(addr, size, direction); 251 __dma_sync(addr, size, direction);
251 } 252 }
252} 253}
@@ -262,7 +263,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
262 if (!plat_device_is_coherent(dev)) { 263 if (!plat_device_is_coherent(dev)) {
263 unsigned long addr; 264 unsigned long addr;
264 265
265 addr = dma_addr_to_virt(dma_handle); 266 addr = dma_addr_to_virt(dev, dma_handle);
266 __dma_sync(addr, size, direction); 267 __dma_sync(addr, size, direction);
267 } 268 }
268} 269}
@@ -277,7 +278,7 @@ void dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
277 if (cpu_is_noncoherent_r10000(dev)) { 278 if (cpu_is_noncoherent_r10000(dev)) {
278 unsigned long addr; 279 unsigned long addr;
279 280
280 addr = dma_addr_to_virt(dma_handle); 281 addr = dma_addr_to_virt(dev, dma_handle);
281 __dma_sync(addr + offset, size, direction); 282 __dma_sync(addr + offset, size, direction);
282 } 283 }
283} 284}
@@ -293,7 +294,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
293 if (!plat_device_is_coherent(dev)) { 294 if (!plat_device_is_coherent(dev)) {
294 unsigned long addr; 295 unsigned long addr;
295 296
296 addr = dma_addr_to_virt(dma_handle); 297 addr = dma_addr_to_virt(dev, dma_handle);
297 __dma_sync(addr + offset, size, direction); 298 __dma_sync(addr + offset, size, direction);
298 } 299 }
299} 300}
diff --git a/arch/mips/mm/hugetlbpage.c b/arch/mips/mm/hugetlbpage.c
new file mode 100644
index 000000000000..471c09aa1614
--- /dev/null
+++ b/arch/mips/mm/hugetlbpage.c
@@ -0,0 +1,101 @@
1/*
2 * MIPS Huge TLB Page Support for Kernel.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2002, Rohit Seth <rohit.seth@intel.com>
9 * Copyright 2005, Embedded Alley Solutions, Inc.
10 * Matt Porter <mporter@embeddedalley.com>
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
12 */
13
14#include <linux/init.h>
15#include <linux/fs.h>
16#include <linux/mm.h>
17#include <linux/hugetlb.h>
18#include <linux/pagemap.h>
19#include <linux/smp_lock.h>
20#include <linux/slab.h>
21#include <linux/err.h>
22#include <linux/sysctl.h>
23#include <asm/mman.h>
24#include <asm/tlb.h>
25#include <asm/tlbflush.h>
26
27pte_t *huge_pte_alloc(struct mm_struct *mm, unsigned long addr,
28 unsigned long sz)
29{
30 pgd_t *pgd;
31 pud_t *pud;
32 pte_t *pte = NULL;
33
34 pgd = pgd_offset(mm, addr);
35 pud = pud_alloc(mm, pgd, addr);
36 if (pud)
37 pte = (pte_t *)pmd_alloc(mm, pud, addr);
38
39 return pte;
40}
41
42pte_t *huge_pte_offset(struct mm_struct *mm, unsigned long addr)
43{
44 pgd_t *pgd;
45 pud_t *pud;
46 pmd_t *pmd = NULL;
47
48 pgd = pgd_offset(mm, addr);
49 if (pgd_present(*pgd)) {
50 pud = pud_offset(pgd, addr);
51 if (pud_present(*pud))
52 pmd = pmd_offset(pud, addr);
53 }
54 return (pte_t *) pmd;
55}
56
57int huge_pmd_unshare(struct mm_struct *mm, unsigned long *addr, pte_t *ptep)
58{
59 return 0;
60}
61
62/*
63 * This function checks for proper alignment of input addr and len parameters.
64 */
65int is_aligned_hugepage_range(unsigned long addr, unsigned long len)
66{
67 if (len & ~HPAGE_MASK)
68 return -EINVAL;
69 if (addr & ~HPAGE_MASK)
70 return -EINVAL;
71 return 0;
72}
73
74struct page *
75follow_huge_addr(struct mm_struct *mm, unsigned long address, int write)
76{
77 return ERR_PTR(-EINVAL);
78}
79
80int pmd_huge(pmd_t pmd)
81{
82 return (pmd_val(pmd) & _PAGE_HUGE) != 0;
83}
84
85int pud_huge(pud_t pud)
86{
87 return (pud_val(pud) & _PAGE_HUGE) != 0;
88}
89
90struct page *
91follow_huge_pmd(struct mm_struct *mm, unsigned long address,
92 pmd_t *pmd, int write)
93{
94 struct page *page;
95
96 page = pte_page(*(pte_t *)pmd);
97 if (page)
98 page += ((address & ~HPAGE_MASK) >> PAGE_SHIFT);
99 return page;
100}
101
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 892be426787c..f60fe513eb60 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/sched.h> 12#include <linux/sched.h>
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/hugetlb.h>
14 15
15#include <asm/cpu.h> 16#include <asm/cpu.h>
16#include <asm/bootinfo.h> 17#include <asm/bootinfo.h>
@@ -295,21 +296,41 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
295 pudp = pud_offset(pgdp, address); 296 pudp = pud_offset(pgdp, address);
296 pmdp = pmd_offset(pudp, address); 297 pmdp = pmd_offset(pudp, address);
297 idx = read_c0_index(); 298 idx = read_c0_index();
298 ptep = pte_offset_map(pmdp, address); 299#ifdef CONFIG_HUGETLB_PAGE
300 /* this could be a huge page */
301 if (pmd_huge(*pmdp)) {
302 unsigned long lo;
303 write_c0_pagemask(PM_HUGE_MASK);
304 ptep = (pte_t *)pmdp;
305 lo = pte_val(*ptep) >> 6;
306 write_c0_entrylo0(lo);
307 write_c0_entrylo1(lo + (HPAGE_SIZE >> 7));
308
309 mtc0_tlbw_hazard();
310 if (idx < 0)
311 tlb_write_random();
312 else
313 tlb_write_indexed();
314 write_c0_pagemask(PM_DEFAULT_MASK);
315 } else
316#endif
317 {
318 ptep = pte_offset_map(pmdp, address);
299 319
300#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) 320#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
301 write_c0_entrylo0(ptep->pte_high); 321 write_c0_entrylo0(ptep->pte_high);
302 ptep++; 322 ptep++;
303 write_c0_entrylo1(ptep->pte_high); 323 write_c0_entrylo1(ptep->pte_high);
304#else 324#else
305 write_c0_entrylo0(pte_val(*ptep++) >> 6); 325 write_c0_entrylo0(pte_val(*ptep++) >> 6);
306 write_c0_entrylo1(pte_val(*ptep) >> 6); 326 write_c0_entrylo1(pte_val(*ptep) >> 6);
307#endif 327#endif
308 mtc0_tlbw_hazard(); 328 mtc0_tlbw_hazard();
309 if (idx < 0) 329 if (idx < 0)
310 tlb_write_random(); 330 tlb_write_random();
311 else 331 else
312 tlb_write_indexed(); 332 tlb_write_indexed();
333 }
313 tlbw_use_hazard(); 334 tlbw_use_hazard();
314 FLUSH_ITLB_VM(vma); 335 FLUSH_ITLB_VM(vma);
315 EXIT_CRITICAL(flags); 336 EXIT_CRITICAL(flags);
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0615b62efd6d..8f606ead826e 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -6,8 +6,9 @@
6 * Synthesize TLB refill handlers at runtime. 6 * Synthesize TLB refill handlers at runtime.
7 * 7 *
8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer 8 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
9 * Copyright (C) 2005, 2007 Maciej W. Rozycki 9 * Copyright (C) 2005, 2007, 2008, 2009 Maciej W. Rozycki
10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org) 10 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
11 * Copyright (C) 2008, 2009 Cavium Networks, Inc.
11 * 12 *
12 * ... and the days got worse and worse and now you see 13 * ... and the days got worse and worse and now you see
13 * I've gone completly out of my mind. 14 * I've gone completly out of my mind.
@@ -19,6 +20,7 @@
19 * (Condolences to Napoleon XIV) 20 * (Condolences to Napoleon XIV)
20 */ 21 */
21 22
23#include <linux/bug.h>
22#include <linux/kernel.h> 24#include <linux/kernel.h>
23#include <linux/types.h> 25#include <linux/types.h>
24#include <linux/string.h> 26#include <linux/string.h>
@@ -82,6 +84,9 @@ enum label_id {
82 label_nopage_tlbm, 84 label_nopage_tlbm,
83 label_smp_pgtable_change, 85 label_smp_pgtable_change,
84 label_r3000_write_probe_fail, 86 label_r3000_write_probe_fail,
87#ifdef CONFIG_HUGETLB_PAGE
88 label_tlb_huge_update,
89#endif
85}; 90};
86 91
87UASM_L_LA(_second_part) 92UASM_L_LA(_second_part)
@@ -98,6 +103,9 @@ UASM_L_LA(_nopage_tlbs)
98UASM_L_LA(_nopage_tlbm) 103UASM_L_LA(_nopage_tlbm)
99UASM_L_LA(_smp_pgtable_change) 104UASM_L_LA(_smp_pgtable_change)
100UASM_L_LA(_r3000_write_probe_fail) 105UASM_L_LA(_r3000_write_probe_fail)
106#ifdef CONFIG_HUGETLB_PAGE
107UASM_L_LA(_tlb_huge_update)
108#endif
101 109
102/* 110/*
103 * For debug purposes. 111 * For debug purposes.
@@ -125,6 +133,7 @@ static inline void dump_handler(const u32 *handler, int count)
125#define C0_TCBIND 2, 2 133#define C0_TCBIND 2, 2
126#define C0_ENTRYLO1 3, 0 134#define C0_ENTRYLO1 3, 0
127#define C0_CONTEXT 4, 0 135#define C0_CONTEXT 4, 0
136#define C0_PAGEMASK 5, 0
128#define C0_BADVADDR 8, 0 137#define C0_BADVADDR 8, 0
129#define C0_ENTRYHI 10, 0 138#define C0_ENTRYHI 10, 0
130#define C0_EPC 14, 0 139#define C0_EPC 14, 0
@@ -258,7 +267,8 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
258 } 267 }
259 268
260 if (cpu_has_mips_r2) { 269 if (cpu_has_mips_r2) {
261 uasm_i_ehb(p); 270 if (cpu_has_mips_r2_exec_hazard)
271 uasm_i_ehb(p);
262 tlbw(p); 272 tlbw(p);
263 return; 273 return;
264 } 274 }
@@ -310,7 +320,6 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
310 case CPU_BCM3302: 320 case CPU_BCM3302:
311 case CPU_BCM4710: 321 case CPU_BCM4710:
312 case CPU_LOONGSON2: 322 case CPU_LOONGSON2:
313 case CPU_CAVIUM_OCTEON:
314 case CPU_R5500: 323 case CPU_R5500:
315 if (m4kc_tlbp_war()) 324 if (m4kc_tlbp_war())
316 uasm_i_nop(p); 325 uasm_i_nop(p);
@@ -382,6 +391,98 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
382 } 391 }
383} 392}
384 393
394#ifdef CONFIG_HUGETLB_PAGE
395static __cpuinit void build_huge_tlb_write_entry(u32 **p,
396 struct uasm_label **l,
397 struct uasm_reloc **r,
398 unsigned int tmp,
399 enum tlb_write_entry wmode)
400{
401 /* Set huge page tlb entry size */
402 uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16);
403 uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff);
404 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
405
406 build_tlb_write_entry(p, l, r, wmode);
407
408 /* Reset default page size */
409 if (PM_DEFAULT_MASK >> 16) {
410 uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16);
411 uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff);
412 uasm_il_b(p, r, label_leave);
413 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
414 } else if (PM_DEFAULT_MASK) {
415 uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK);
416 uasm_il_b(p, r, label_leave);
417 uasm_i_mtc0(p, tmp, C0_PAGEMASK);
418 } else {
419 uasm_il_b(p, r, label_leave);
420 uasm_i_mtc0(p, 0, C0_PAGEMASK);
421 }
422}
423
424/*
425 * Check if Huge PTE is present, if so then jump to LABEL.
426 */
427static void __cpuinit
428build_is_huge_pte(u32 **p, struct uasm_reloc **r, unsigned int tmp,
429 unsigned int pmd, int lid)
430{
431 UASM_i_LW(p, tmp, 0, pmd);
432 uasm_i_andi(p, tmp, tmp, _PAGE_HUGE);
433 uasm_il_bnez(p, r, tmp, lid);
434}
435
436static __cpuinit void build_huge_update_entries(u32 **p,
437 unsigned int pte,
438 unsigned int tmp)
439{
440 int small_sequence;
441
442 /*
443 * A huge PTE describes an area the size of the
444 * configured huge page size. This is twice the
445 * of the large TLB entry size we intend to use.
446 * A TLB entry half the size of the configured
447 * huge page size is configured into entrylo0
448 * and entrylo1 to cover the contiguous huge PTE
449 * address space.
450 */
451 small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
452
453 /* We can clobber tmp. It isn't used after this.*/
454 if (!small_sequence)
455 uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
456
457 UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */
458 uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */
459 /* convert to entrylo1 */
460 if (small_sequence)
461 UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7);
462 else
463 UASM_i_ADDU(p, pte, pte, tmp);
464
465 uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */
466}
467
468static __cpuinit void build_huge_handler_tail(u32 **p,
469 struct uasm_reloc **r,
470 struct uasm_label **l,
471 unsigned int pte,
472 unsigned int ptr)
473{
474#ifdef CONFIG_SMP
475 UASM_i_SC(p, pte, 0, ptr);
476 uasm_il_beqz(p, r, pte, label_tlb_huge_update);
477 UASM_i_LW(p, pte, 0, ptr); /* Needed because SC killed our PTE */
478#else
479 UASM_i_SW(p, pte, 0, ptr);
480#endif
481 build_huge_update_entries(p, pte, ptr);
482 build_huge_tlb_write_entry(p, l, r, pte, tlb_indexed);
483}
484#endif /* CONFIG_HUGETLB_PAGE */
485
385#ifdef CONFIG_64BIT 486#ifdef CONFIG_64BIT
386/* 487/*
387 * TMP and PTR are scratch. 488 * TMP and PTR are scratch.
@@ -649,6 +750,14 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp,
649#endif 750#endif
650} 751}
651 752
753/*
754 * For a 64-bit kernel, we are using the 64-bit XTLB refill exception
755 * because EXL == 0. If we wrap, we can also use the 32 instruction
756 * slots before the XTLB refill exception handler which belong to the
757 * unused TLB refill exception.
758 */
759#define MIPS64_REFILL_INSNS 32
760
652static void __cpuinit build_r4000_tlb_refill_handler(void) 761static void __cpuinit build_r4000_tlb_refill_handler(void)
653{ 762{
654 u32 *p = tlb_handler; 763 u32 *p = tlb_handler;
@@ -680,12 +789,23 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
680 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */ 789 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
681#endif 790#endif
682 791
792#ifdef CONFIG_HUGETLB_PAGE
793 build_is_huge_pte(&p, &r, K0, K1, label_tlb_huge_update);
794#endif
795
683 build_get_ptep(&p, K0, K1); 796 build_get_ptep(&p, K0, K1);
684 build_update_entries(&p, K0, K1); 797 build_update_entries(&p, K0, K1);
685 build_tlb_write_entry(&p, &l, &r, tlb_random); 798 build_tlb_write_entry(&p, &l, &r, tlb_random);
686 uasm_l_leave(&l, p); 799 uasm_l_leave(&l, p);
687 uasm_i_eret(&p); /* return from trap */ 800 uasm_i_eret(&p); /* return from trap */
688 801
802#ifdef CONFIG_HUGETLB_PAGE
803 uasm_l_tlb_huge_update(&l, p);
804 UASM_i_LW(&p, K0, 0, K1);
805 build_huge_update_entries(&p, K0, K1);
806 build_huge_tlb_write_entry(&p, &l, &r, K0, tlb_random);
807#endif
808
689#ifdef CONFIG_64BIT 809#ifdef CONFIG_64BIT
690 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1); 810 build_get_pgd_vmalloc64(&p, &l, &r, K0, K1);
691#endif 811#endif
@@ -702,9 +822,10 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
702 if ((p - tlb_handler) > 64) 822 if ((p - tlb_handler) > 64)
703 panic("TLB refill handler space exceeded"); 823 panic("TLB refill handler space exceeded");
704#else 824#else
705 if (((p - tlb_handler) > 63) 825 if (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 1)
706 || (((p - tlb_handler) > 61) 826 || (((p - tlb_handler) > (MIPS64_REFILL_INSNS * 2) - 3)
707 && uasm_insn_has_bdelay(relocs, tlb_handler + 29))) 827 && uasm_insn_has_bdelay(relocs,
828 tlb_handler + MIPS64_REFILL_INSNS - 3)))
708 panic("TLB refill handler space exceeded"); 829 panic("TLB refill handler space exceeded");
709#endif 830#endif
710 831
@@ -717,39 +838,74 @@ static void __cpuinit build_r4000_tlb_refill_handler(void)
717 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 838 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
718 final_len = p - tlb_handler; 839 final_len = p - tlb_handler;
719#else /* CONFIG_64BIT */ 840#else /* CONFIG_64BIT */
720 f = final_handler + 32; 841 f = final_handler + MIPS64_REFILL_INSNS;
721 if ((p - tlb_handler) <= 32) { 842 if ((p - tlb_handler) <= MIPS64_REFILL_INSNS) {
722 /* Just copy the handler. */ 843 /* Just copy the handler. */
723 uasm_copy_handler(relocs, labels, tlb_handler, p, f); 844 uasm_copy_handler(relocs, labels, tlb_handler, p, f);
724 final_len = p - tlb_handler; 845 final_len = p - tlb_handler;
725 } else { 846 } else {
726 u32 *split = tlb_handler + 30; 847#if defined(CONFIG_HUGETLB_PAGE)
848 const enum label_id ls = label_tlb_huge_update;
849#elif defined(MODULE_START)
850 const enum label_id ls = label_module_alloc;
851#else
852 const enum label_id ls = label_vmalloc;
853#endif
854 u32 *split;
855 int ov = 0;
856 int i;
857
858 for (i = 0; i < ARRAY_SIZE(labels) && labels[i].lab != ls; i++)
859 ;
860 BUG_ON(i == ARRAY_SIZE(labels));
861 split = labels[i].addr;
727 862
728 /* 863 /*
729 * Find the split point. 864 * See if we have overflown one way or the other.
730 */ 865 */
731 if (uasm_insn_has_bdelay(relocs, split - 1)) 866 if (split > tlb_handler + MIPS64_REFILL_INSNS ||
732 split--; 867 split < p - MIPS64_REFILL_INSNS)
733 868 ov = 1;
869
870 if (ov) {
871 /*
872 * Split two instructions before the end. One
873 * for the branch and one for the instruction
874 * in the delay slot.
875 */
876 split = tlb_handler + MIPS64_REFILL_INSNS - 2;
877
878 /*
879 * If the branch would fall in a delay slot,
880 * we must back up an additional instruction
881 * so that it is no longer in a delay slot.
882 */
883 if (uasm_insn_has_bdelay(relocs, split - 1))
884 split--;
885 }
734 /* Copy first part of the handler. */ 886 /* Copy first part of the handler. */
735 uasm_copy_handler(relocs, labels, tlb_handler, split, f); 887 uasm_copy_handler(relocs, labels, tlb_handler, split, f);
736 f += split - tlb_handler; 888 f += split - tlb_handler;
737 889
738 /* Insert branch. */ 890 if (ov) {
739 uasm_l_split(&l, final_handler); 891 /* Insert branch. */
740 uasm_il_b(&f, &r, label_split); 892 uasm_l_split(&l, final_handler);
741 if (uasm_insn_has_bdelay(relocs, split)) 893 uasm_il_b(&f, &r, label_split);
742 uasm_i_nop(&f); 894 if (uasm_insn_has_bdelay(relocs, split))
743 else { 895 uasm_i_nop(&f);
744 uasm_copy_handler(relocs, labels, split, split + 1, f); 896 else {
745 uasm_move_labels(labels, f, f + 1, -1); 897 uasm_copy_handler(relocs, labels,
746 f++; 898 split, split + 1, f);
747 split++; 899 uasm_move_labels(labels, f, f + 1, -1);
900 f++;
901 split++;
902 }
748 } 903 }
749 904
750 /* Copy the rest of the handler. */ 905 /* Copy the rest of the handler. */
751 uasm_copy_handler(relocs, labels, split, p, final_handler); 906 uasm_copy_handler(relocs, labels, split, p, final_handler);
752 final_len = (f - (final_handler + 32)) + (p - split); 907 final_len = (f - (final_handler + MIPS64_REFILL_INSNS)) +
908 (p - split);
753 } 909 }
754#endif /* CONFIG_64BIT */ 910#endif /* CONFIG_64BIT */
755 911
@@ -782,7 +938,7 @@ u32 handle_tlbs[FASTPATH_SIZE] __cacheline_aligned;
782u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned; 938u32 handle_tlbm[FASTPATH_SIZE] __cacheline_aligned;
783 939
784static void __cpuinit 940static void __cpuinit
785iPTE_LW(u32 **p, struct uasm_label **l, unsigned int pte, unsigned int ptr) 941iPTE_LW(u32 **p, unsigned int pte, unsigned int ptr)
786{ 942{
787#ifdef CONFIG_SMP 943#ifdef CONFIG_SMP
788# ifdef CONFIG_64BIT_PHYS_ADDR 944# ifdef CONFIG_64BIT_PHYS_ADDR
@@ -862,13 +1018,13 @@ iPTE_SW(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr,
862 * with it's original value. 1018 * with it's original value.
863 */ 1019 */
864static void __cpuinit 1020static void __cpuinit
865build_pte_present(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 1021build_pte_present(u32 **p, struct uasm_reloc **r,
866 unsigned int pte, unsigned int ptr, enum label_id lid) 1022 unsigned int pte, unsigned int ptr, enum label_id lid)
867{ 1023{
868 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1024 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
869 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); 1025 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ);
870 uasm_il_bnez(p, r, pte, lid); 1026 uasm_il_bnez(p, r, pte, lid);
871 iPTE_LW(p, l, pte, ptr); 1027 iPTE_LW(p, pte, ptr);
872} 1028}
873 1029
874/* Make PTE valid, store result in PTR. */ 1030/* Make PTE valid, store result in PTR. */
@@ -886,13 +1042,13 @@ build_make_valid(u32 **p, struct uasm_reloc **r, unsigned int pte,
886 * restore PTE with value from PTR when done. 1042 * restore PTE with value from PTR when done.
887 */ 1043 */
888static void __cpuinit 1044static void __cpuinit
889build_pte_writable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 1045build_pte_writable(u32 **p, struct uasm_reloc **r,
890 unsigned int pte, unsigned int ptr, enum label_id lid) 1046 unsigned int pte, unsigned int ptr, enum label_id lid)
891{ 1047{
892 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1048 uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
893 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE); 1049 uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_WRITE);
894 uasm_il_bnez(p, r, pte, lid); 1050 uasm_il_bnez(p, r, pte, lid);
895 iPTE_LW(p, l, pte, ptr); 1051 iPTE_LW(p, pte, ptr);
896} 1052}
897 1053
898/* Make PTE writable, update software status bits as well, then store 1054/* Make PTE writable, update software status bits as well, then store
@@ -913,12 +1069,12 @@ build_make_write(u32 **p, struct uasm_reloc **r, unsigned int pte,
913 * restore PTE with value from PTR when done. 1069 * restore PTE with value from PTR when done.
914 */ 1070 */
915static void __cpuinit 1071static void __cpuinit
916build_pte_modifiable(u32 **p, struct uasm_label **l, struct uasm_reloc **r, 1072build_pte_modifiable(u32 **p, struct uasm_reloc **r,
917 unsigned int pte, unsigned int ptr, enum label_id lid) 1073 unsigned int pte, unsigned int ptr, enum label_id lid)
918{ 1074{
919 uasm_i_andi(p, pte, pte, _PAGE_WRITE); 1075 uasm_i_andi(p, pte, pte, _PAGE_WRITE);
920 uasm_il_beqz(p, r, pte, lid); 1076 uasm_il_beqz(p, r, pte, lid);
921 iPTE_LW(p, l, pte, ptr); 1077 iPTE_LW(p, pte, ptr);
922} 1078}
923 1079
924/* 1080/*
@@ -994,7 +1150,7 @@ static void __cpuinit build_r3000_tlb_load_handler(void)
994 memset(relocs, 0, sizeof(relocs)); 1150 memset(relocs, 0, sizeof(relocs));
995 1151
996 build_r3000_tlbchange_handler_head(&p, K0, K1); 1152 build_r3000_tlbchange_handler_head(&p, K0, K1);
997 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1153 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
998 uasm_i_nop(&p); /* load delay */ 1154 uasm_i_nop(&p); /* load delay */
999 build_make_valid(&p, &r, K0, K1); 1155 build_make_valid(&p, &r, K0, K1);
1000 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1156 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
@@ -1024,7 +1180,7 @@ static void __cpuinit build_r3000_tlb_store_handler(void)
1024 memset(relocs, 0, sizeof(relocs)); 1180 memset(relocs, 0, sizeof(relocs));
1025 1181
1026 build_r3000_tlbchange_handler_head(&p, K0, K1); 1182 build_r3000_tlbchange_handler_head(&p, K0, K1);
1027 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1183 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1028 uasm_i_nop(&p); /* load delay */ 1184 uasm_i_nop(&p); /* load delay */
1029 build_make_write(&p, &r, K0, K1); 1185 build_make_write(&p, &r, K0, K1);
1030 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1); 1186 build_r3000_tlb_reload_write(&p, &l, &r, K0, K1);
@@ -1054,7 +1210,7 @@ static void __cpuinit build_r3000_tlb_modify_handler(void)
1054 memset(relocs, 0, sizeof(relocs)); 1210 memset(relocs, 0, sizeof(relocs));
1055 1211
1056 build_r3000_tlbchange_handler_head(&p, K0, K1); 1212 build_r3000_tlbchange_handler_head(&p, K0, K1);
1057 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1213 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1058 uasm_i_nop(&p); /* load delay */ 1214 uasm_i_nop(&p); /* load delay */
1059 build_make_write(&p, &r, K0, K1); 1215 build_make_write(&p, &r, K0, K1);
1060 build_r3000_pte_reload_tlbwi(&p, K0, K1); 1216 build_r3000_pte_reload_tlbwi(&p, K0, K1);
@@ -1087,6 +1243,15 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1087 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */ 1243 build_get_pgde32(p, pte, ptr); /* get pgd in ptr */
1088#endif 1244#endif
1089 1245
1246#ifdef CONFIG_HUGETLB_PAGE
1247 /*
1248 * For huge tlb entries, pmd doesn't contain an address but
1249 * instead contains the tlb pte. Check the PAGE_HUGE bit and
1250 * see if we need to jump to huge tlb processing.
1251 */
1252 build_is_huge_pte(p, r, pte, ptr, label_tlb_huge_update);
1253#endif
1254
1090 UASM_i_MFC0(p, pte, C0_BADVADDR); 1255 UASM_i_MFC0(p, pte, C0_BADVADDR);
1091 UASM_i_LW(p, ptr, 0, ptr); 1256 UASM_i_LW(p, ptr, 0, ptr);
1092 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2); 1257 UASM_i_SRL(p, pte, pte, PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2);
@@ -1096,7 +1261,7 @@ build_r4000_tlbchange_handler_head(u32 **p, struct uasm_label **l,
1096#ifdef CONFIG_SMP 1261#ifdef CONFIG_SMP
1097 uasm_l_smp_pgtable_change(l, *p); 1262 uasm_l_smp_pgtable_change(l, *p);
1098#endif 1263#endif
1099 iPTE_LW(p, l, pte, ptr); /* get even pte */ 1264 iPTE_LW(p, pte, ptr); /* get even pte */
1100 if (!m4kc_tlbp_war()) 1265 if (!m4kc_tlbp_war())
1101 build_tlb_probe_entry(p); 1266 build_tlb_probe_entry(p);
1102} 1267}
@@ -1138,12 +1303,25 @@ static void __cpuinit build_r4000_tlb_load_handler(void)
1138 } 1303 }
1139 1304
1140 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1305 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1141 build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl); 1306 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1142 if (m4kc_tlbp_war()) 1307 if (m4kc_tlbp_war())
1143 build_tlb_probe_entry(&p); 1308 build_tlb_probe_entry(&p);
1144 build_make_valid(&p, &r, K0, K1); 1309 build_make_valid(&p, &r, K0, K1);
1145 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1310 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1146 1311
1312#ifdef CONFIG_HUGETLB_PAGE
1313 /*
1314 * This is the entry point when build_r4000_tlbchange_handler_head
1315 * spots a huge page.
1316 */
1317 uasm_l_tlb_huge_update(&l, p);
1318 iPTE_LW(&p, K0, K1);
1319 build_pte_present(&p, &r, K0, K1, label_nopage_tlbl);
1320 build_tlb_probe_entry(&p);
1321 uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID));
1322 build_huge_handler_tail(&p, &r, &l, K0, K1);
1323#endif
1324
1147 uasm_l_nopage_tlbl(&l, p); 1325 uasm_l_nopage_tlbl(&l, p);
1148 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff); 1326 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_0 & 0x0fffffff);
1149 uasm_i_nop(&p); 1327 uasm_i_nop(&p);
@@ -1169,12 +1347,26 @@ static void __cpuinit build_r4000_tlb_store_handler(void)
1169 memset(relocs, 0, sizeof(relocs)); 1347 memset(relocs, 0, sizeof(relocs));
1170 1348
1171 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1349 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1172 build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs); 1350 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1173 if (m4kc_tlbp_war()) 1351 if (m4kc_tlbp_war())
1174 build_tlb_probe_entry(&p); 1352 build_tlb_probe_entry(&p);
1175 build_make_write(&p, &r, K0, K1); 1353 build_make_write(&p, &r, K0, K1);
1176 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1354 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1177 1355
1356#ifdef CONFIG_HUGETLB_PAGE
1357 /*
1358 * This is the entry point when
1359 * build_r4000_tlbchange_handler_head spots a huge page.
1360 */
1361 uasm_l_tlb_huge_update(&l, p);
1362 iPTE_LW(&p, K0, K1);
1363 build_pte_writable(&p, &r, K0, K1, label_nopage_tlbs);
1364 build_tlb_probe_entry(&p);
1365 uasm_i_ori(&p, K0, K0,
1366 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1367 build_huge_handler_tail(&p, &r, &l, K0, K1);
1368#endif
1369
1178 uasm_l_nopage_tlbs(&l, p); 1370 uasm_l_nopage_tlbs(&l, p);
1179 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1371 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1180 uasm_i_nop(&p); 1372 uasm_i_nop(&p);
@@ -1200,13 +1392,27 @@ static void __cpuinit build_r4000_tlb_modify_handler(void)
1200 memset(relocs, 0, sizeof(relocs)); 1392 memset(relocs, 0, sizeof(relocs));
1201 1393
1202 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1); 1394 build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
1203 build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm); 1395 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1204 if (m4kc_tlbp_war()) 1396 if (m4kc_tlbp_war())
1205 build_tlb_probe_entry(&p); 1397 build_tlb_probe_entry(&p);
1206 /* Present and writable bits set, set accessed and dirty bits. */ 1398 /* Present and writable bits set, set accessed and dirty bits. */
1207 build_make_write(&p, &r, K0, K1); 1399 build_make_write(&p, &r, K0, K1);
1208 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); 1400 build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
1209 1401
1402#ifdef CONFIG_HUGETLB_PAGE
1403 /*
1404 * This is the entry point when
1405 * build_r4000_tlbchange_handler_head spots a huge page.
1406 */
1407 uasm_l_tlb_huge_update(&l, p);
1408 iPTE_LW(&p, K0, K1);
1409 build_pte_modifiable(&p, &r, K0, K1, label_nopage_tlbm);
1410 build_tlb_probe_entry(&p);
1411 uasm_i_ori(&p, K0, K0,
1412 _PAGE_ACCESSED | _PAGE_MODIFIED | _PAGE_VALID | _PAGE_DIRTY);
1413 build_huge_handler_tail(&p, &r, &l, K0, K1);
1414#endif
1415
1210 uasm_l_nopage_tlbm(&l, p); 1416 uasm_l_nopage_tlbm(&l, p);
1211 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff); 1417 uasm_i_j(&p, (unsigned long)tlb_do_page_fault_1 & 0x0fffffff);
1212 uasm_i_nop(&p); 1418 uasm_i_nop(&p);
diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile
new file mode 100644
index 000000000000..73d56b87cb9b
--- /dev/null
+++ b/arch/mips/power/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o
diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
new file mode 100644
index 000000000000..7995df45dc8d
--- /dev/null
+++ b/arch/mips/power/cpu.c
@@ -0,0 +1,43 @@
1/*
2 * Suspend support specific for mips.
3 *
4 * Licensed under the GPLv2
5 *
6 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
7 * Author: Hu Hongbing <huhb@lemote.com>
8 * Wu Zhangjin <wuzj@lemote.com>
9 */
10#include <asm/suspend.h>
11#include <asm/fpu.h>
12#include <asm/dsp.h>
13
14static u32 saved_status;
15struct pt_regs saved_regs;
16
17void save_processor_state(void)
18{
19 saved_status = read_c0_status();
20
21 if (is_fpu_owner())
22 save_fp(current);
23 if (cpu_has_dsp)
24 save_dsp(current);
25}
26
27void restore_processor_state(void)
28{
29 write_c0_status(saved_status);
30
31 if (is_fpu_owner())
32 restore_fp(current);
33 if (cpu_has_dsp)
34 restore_dsp(current);
35}
36
37int pfn_is_nosave(unsigned long pfn)
38{
39 unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin));
40 unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end));
41
42 return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
43}
diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
new file mode 100644
index 000000000000..486bd3fd01a1
--- /dev/null
+++ b/arch/mips/power/hibernate.S
@@ -0,0 +1,70 @@
1/*
2 * Hibernation support specific for mips - temporary page tables
3 *
4 * Licensed under the GPLv2
5 *
6 * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology
7 * Author: Hu Hongbing <huhb@lemote.com>
8 * Wu Zhangjin <wuzj@lemote.com>
9 */
10#include <asm/asm-offsets.h>
11#include <asm/regdef.h>
12#include <asm/asm.h>
13
14.text
15LEAF(swsusp_arch_suspend)
16 PTR_LA t0, saved_regs
17 PTR_S ra, PT_R31(t0)
18 PTR_S sp, PT_R29(t0)
19 PTR_S fp, PT_R30(t0)
20 PTR_S gp, PT_R28(t0)
21 PTR_S s0, PT_R16(t0)
22 PTR_S s1, PT_R17(t0)
23 PTR_S s2, PT_R18(t0)
24 PTR_S s3, PT_R19(t0)
25 PTR_S s4, PT_R20(t0)
26 PTR_S s5, PT_R21(t0)
27 PTR_S s6, PT_R22(t0)
28 PTR_S s7, PT_R23(t0)
29 j swsusp_save
30END(swsusp_arch_suspend)
31
32LEAF(swsusp_arch_resume)
33 PTR_L t0, restore_pblist
340:
35 PTR_L t1, PBE_ADDRESS(t0) /* source */
36 PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */
37 PTR_ADDIU t3, t1, _PAGE_SIZE
381:
39 REG_L t8, (t1)
40 REG_S t8, (t2)
41 PTR_ADDIU t1, t1, SZREG
42 PTR_ADDIU t2, t2, SZREG
43 bne t1, t3, 1b
44 PTR_L t0, PBE_NEXT(t0)
45 bnez t0, 0b
46 /* flush caches to make sure context is in memory */
47 PTR_L t0, __flush_cache_all
48 jalr t0
49 /* flush tlb entries */
50#ifdef CONFIG_SMP
51 jal flush_tlb_all
52#else
53 jal local_flush_tlb_all
54#endif
55 PTR_LA t0, saved_regs
56 PTR_L ra, PT_R31(t0)
57 PTR_L sp, PT_R29(t0)
58 PTR_L fp, PT_R30(t0)
59 PTR_L gp, PT_R28(t0)
60 PTR_L s0, PT_R16(t0)
61 PTR_L s1, PT_R17(t0)
62 PTR_L s2, PT_R18(t0)
63 PTR_L s3, PT_R19(t0)
64 PTR_L s4, PT_R20(t0)
65 PTR_L s5, PT_R21(t0)
66 PTR_L s6, PT_R22(t0)
67 PTR_L s7, PT_R23(t0)
68 PTR_LI v0, 0x0
69 jr ra
70END(swsusp_arch_resume)
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index 53eeb5e7bc5b..f07882029a90 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -151,7 +151,8 @@ static void rb532_disable_irq(unsigned int irq_nr)
151 mask |= intr_bit; 151 mask |= intr_bit;
152 WRITE_MASK(addr, mask); 152 WRITE_MASK(addr, mask);
153 153
154 if (group == GPIO_MAPPED_IRQ_GROUP) 154 /* There is a maximum of 14 GPIO interrupts */
155 if (group == GPIO_MAPPED_IRQ_GROUP && irq_nr <= (GROUP4_IRQ_BASE + 13))
155 rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE); 156 rb532_gpio_set_istat(0, irq_nr - GPIO_MAPPED_IRQ_BASE);
156 157
157 /* 158 /*
@@ -174,7 +175,7 @@ static int rb532_set_type(unsigned int irq_nr, unsigned type)
174 int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE; 175 int gpio = irq_nr - GPIO_MAPPED_IRQ_BASE;
175 int group = irq_to_group(irq_nr); 176 int group = irq_to_group(irq_nr);
176 177
177 if (group != GPIO_MAPPED_IRQ_GROUP) 178 if (group != GPIO_MAPPED_IRQ_GROUP || irq_nr > (GROUP4_IRQ_BASE + 13))
178 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL; 179 return (type == IRQ_TYPE_LEVEL_HIGH) ? 0 : -EINVAL;
179 180
180 switch (type) { 181 switch (type) {
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index 366b19d33f77..3e639bda43f7 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -75,6 +75,8 @@ config SIBYTE_SB1xxx_SOC
75 select SWAP_IO_SPACE 75 select SWAP_IO_SPACE
76 select SYS_SUPPORTS_32BIT_KERNEL 76 select SYS_SUPPORTS_32BIT_KERNEL
77 select SYS_SUPPORTS_64BIT_KERNEL 77 select SYS_SUPPORTS_64BIT_KERNEL
78 select CFE
79 select SYS_HAS_EARLY_PRINTK
78 80
79choice 81choice
80 prompt "SiByte SOC Stepping" 82 prompt "SiByte SOC Stepping"
@@ -128,13 +130,6 @@ config SIBYTE_ENABLE_LDT_IF_PCI
128 bool 130 bool
129 select SIBYTE_HAS_LDT if PCI 131 select SIBYTE_HAS_LDT if PCI
130 132
131config SIMULATION
132 bool "Running under simulation"
133 depends on SIBYTE_SB1xxx_SOC
134 help
135 Build a kernel suitable for running under the GDB simulator.
136 Primarily adjusts the kernel's notion of time.
137
138config SB1_CEX_ALWAYS_FATAL 133config SB1_CEX_ALWAYS_FATAL
139 bool "All cache exceptions considered fatal (no recovery attempted)" 134 bool "All cache exceptions considered fatal (no recovery attempted)"
140 depends on SIBYTE_SB1xxx_SOC 135 depends on SIBYTE_SB1xxx_SOC
@@ -143,34 +138,14 @@ config SB1_CERR_STALL
143 bool "Stall (rather than panic) on fatal cache error" 138 bool "Stall (rather than panic) on fatal cache error"
144 depends on SIBYTE_SB1xxx_SOC 139 depends on SIBYTE_SB1xxx_SOC
145 140
146config SIBYTE_CFE
147 bool "Booting from CFE"
148 depends on SIBYTE_SB1xxx_SOC
149 select CFE
150 select SYS_HAS_EARLY_PRINTK
151 help
152 Make use of the CFE API for enumerating available memory,
153 controlling secondary CPUs, and possibly console output.
154
155config SIBYTE_CFE_CONSOLE 141config SIBYTE_CFE_CONSOLE
156 bool "Use firmware console" 142 bool "Use firmware console"
157 depends on SIBYTE_CFE 143 depends on SIBYTE_SB1xxx_SOC
158 help 144 help
159 Use the CFE API's console write routines during boot. Other console 145 Use the CFE API's console write routines during boot. Other console
160 options (VT console, sb1250 duart console, etc.) should not be 146 options (VT console, sb1250 duart console, etc.) should not be
161 configured. 147 configured.
162 148
163config SIBYTE_STANDALONE
164 bool
165 depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE
166 select SYS_HAS_EARLY_PRINTK
167 default y
168
169config SIBYTE_STANDALONE_RAM_SIZE
170 int "Memory size (in megabytes)"
171 depends on SIBYTE_STANDALONE
172 default "32"
173
174config SIBYTE_BUS_WATCHER 149config SIBYTE_BUS_WATCHER
175 bool "Support for Bus Watcher statistics" 150 bool "Support for Bus Watcher statistics"
176 depends on SIBYTE_SB1xxx_SOC 151 depends on SIBYTE_SB1xxx_SOC
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
deleted file mode 100644
index 02b32e142adf..000000000000
--- a/arch/mips/sibyte/cfe/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
1lib-y = setup.o
2lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index 48a91b9e5870..4f659837c7c6 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -1,5 +1,5 @@
1obj-y := 1obj-y := cfe.o
2 2obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o 3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
4 4
5EXTRA_CFLAGS += -Werror 5EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/common/cfe.c
index eb5396cf81bb..eb5396cf81bb 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/common/cfe.c
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/common/cfe_console.c
index 81e3d54376e9..81e3d54376e9 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/common/cfe_console.c
diff --git a/arch/mips/sibyte/sb1250/Makefile b/arch/mips/sibyte/sb1250/Makefile
index 697793783a25..1896f4e77a30 100644
--- a/arch/mips/sibyte/sb1250/Makefile
+++ b/arch/mips/sibyte/sb1250/Makefile
@@ -1,7 +1,6 @@
1obj-y := setup.o irq.o time.o 1obj-y := setup.o irq.o time.o
2 2
3obj-$(CONFIG_SMP) += smp.o 3obj-$(CONFIG_SMP) += smp.o
4obj-$(CONFIG_SIBYTE_STANDALONE) += prom.o
5obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o 4obj-$(CONFIG_SIBYTE_BUS_WATCHER) += bus_watcher.o
6 5
7EXTRA_CFLAGS += -Werror 6EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 409dec798863..5e7f2016cceb 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -111,11 +111,6 @@ static int sb1250_set_affinity(unsigned int irq, const struct cpumask *mask)
111 111
112 i = cpumask_first(mask); 112 i = cpumask_first(mask);
113 113
114 if (cpumask_weight(mask) > 1) {
115 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
116 return -1;
117 }
118
119 /* Convert logical CPU to physical CPU */ 114 /* Convert logical CPU to physical CPU */
120 cpu = cpu_logical_map(i); 115 cpu = cpu_logical_map(i);
121 116
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
deleted file mode 100644
index 65b1af66b674..000000000000
--- a/arch/mips/sibyte/sb1250/prom.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Copyright (C) 2000, 2001 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19#include <linux/init.h>
20#include <linux/kernel.h>
21#include <linux/mm.h>
22#include <linux/blkdev.h>
23#include <linux/bootmem.h>
24#include <linux/smp.h>
25#include <linux/initrd.h>
26#include <linux/pm.h>
27
28#include <asm/bootinfo.h>
29#include <asm/reboot.h>
30
31#define MAX_RAM_SIZE ((CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - 1)
32
33static __init void prom_meminit(void)
34{
35#ifdef CONFIG_BLK_DEV_INITRD
36 unsigned long initrd_pstart;
37 unsigned long initrd_pend;
38
39 initrd_pstart = __pa(initrd_start);
40 initrd_pend = __pa(initrd_end);
41 if (initrd_start &&
42 ((initrd_pstart > MAX_RAM_SIZE)
43 || (initrd_pend > MAX_RAM_SIZE))) {
44 panic("initrd out of addressable memory");
45 }
46
47 add_memory_region(0, initrd_pstart,
48 BOOT_MEM_RAM);
49 add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
50 BOOT_MEM_RESERVED);
51 add_memory_region(initrd_pend,
52 (CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024) - initrd_pend,
53 BOOT_MEM_RAM);
54#else
55 add_memory_region(0, CONFIG_SIBYTE_STANDALONE_RAM_SIZE * 1024 * 1024,
56 BOOT_MEM_RAM);
57#endif
58}
59
60void prom_cpu0_exit(void *unused)
61{
62 while (1) ;
63}
64
65static void prom_linux_exit(void)
66{
67#ifdef CONFIG_SMP
68 if (smp_processor_id()) {
69 smp_call_function(prom_cpu0_exit, NULL, 1);
70 }
71#endif
72 while(1);
73}
74
75/*
76 * prom_init is called just after the cpu type is determined, from setup_arch()
77 */
78void __init prom_init(void)
79{
80 _machine_restart = (void (*)(char *))prom_linux_exit;
81 _machine_halt = prom_linux_exit;
82 pm_power_off = prom_linux_exit;
83
84 strcpy(arcs_cmdline, "root=/dev/ram0 ");
85
86 prom_meminit();
87}
88
89void __init prom_free_prom_memory(void)
90{
91 /* Not sure what I'm supposed to do here. Nothing, I think */
92}
93
94void prom_putchar(char c)
95{
96}
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 080c966263b7..672e45d495a9 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -136,20 +136,6 @@ void __init plat_mem_setup(void)
136 if (m41t81_probe()) 136 if (m41t81_probe())
137 swarm_rtc_type = RTC_M4LT81; 137 swarm_rtc_type = RTC_M4LT81;
138 138
139 printk("This kernel optimized for "
140#ifdef CONFIG_SIMULATION
141 "simulation"
142#else
143 "board"
144#endif
145 " runs "
146#ifdef CONFIG_SIBYTE_CFE
147 "with"
148#else
149 "without"
150#endif
151 " CFE\n");
152
153#ifdef CONFIG_VT 139#ifdef CONFIG_VT
154 screen_info = (struct screen_info) { 140 screen_info = (struct screen_info) {
155 0, 0, /* orig-x, orig-y */ 141 0, 0, /* orig-x, orig-y */
diff --git a/arch/mips/sni/eisa.c b/arch/mips/sni/eisa.c
index 7396cd719900..6827feb4de96 100644
--- a/arch/mips/sni/eisa.c
+++ b/arch/mips/sni/eisa.c
@@ -38,7 +38,7 @@ int __init sni_eisa_root_init(void)
38 if (!r) 38 if (!r)
39 return r; 39 return r;
40 40
41 eisa_root_dev.dev.driver_data = &eisa_bus_root; 41 dev_set_drvdata(&eisa_root_dev.dev, &eisa_bus_root);
42 42
43 if (eisa_root_register(&eisa_bus_root)) { 43 if (eisa_root_register(&eisa_bus_root)) {
44 /* A real bridge may have been registered before 44 /* A real bridge may have been registered before
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 0db7cf38ed8b..852ae4bb7a85 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -69,6 +69,7 @@ config SOC_TX4927
69 select IRQ_TXX9 69 select IRQ_TXX9
70 select PCI_TX4927 70 select PCI_TX4927
71 select GPIO_TXX9 71 select GPIO_TXX9
72 select HAS_TXX9_ACLC
72 73
73config SOC_TX4938 74config SOC_TX4938
74 bool 75 bool
@@ -78,6 +79,7 @@ config SOC_TX4938
78 select IRQ_TXX9 79 select IRQ_TXX9
79 select PCI_TX4927 80 select PCI_TX4927
80 select GPIO_TXX9 81 select GPIO_TXX9
82 select HAS_TXX9_ACLC
81 83
82config SOC_TX4939 84config SOC_TX4939
83 bool 85 bool
@@ -85,6 +87,7 @@ config SOC_TX4939
85 select HAS_TXX9_SERIAL 87 select HAS_TXX9_SERIAL
86 select HW_HAS_PCI 88 select HW_HAS_PCI
87 select PCI_TX4927 89 select PCI_TX4927
90 select HAS_TXX9_ACLC
88 91
89config TXX9_7SEGLED 92config TXX9_7SEGLED
90 bool 93 bool
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8a266c6a3f58..3b7d77d61ce0 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -24,6 +24,7 @@
24#include <linux/serial_core.h> 24#include <linux/serial_core.h>
25#include <linux/mtd/physmap.h> 25#include <linux/mtd/physmap.h>
26#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/sysdev.h>
27#include <asm/bootinfo.h> 28#include <asm/bootinfo.h>
28#include <asm/time.h> 29#include <asm/time.h>
29#include <asm/reboot.h> 30#include <asm/reboot.h>
@@ -33,6 +34,7 @@
33#include <asm/txx9/pci.h> 34#include <asm/txx9/pci.h>
34#include <asm/txx9tmr.h> 35#include <asm/txx9tmr.h>
35#include <asm/txx9/ndfmc.h> 36#include <asm/txx9/ndfmc.h>
37#include <asm/txx9/dmac.h>
36#ifdef CONFIG_CPU_TX49XX 38#ifdef CONFIG_CPU_TX49XX
37#include <asm/txx9/tx4938.h> 39#include <asm/txx9/tx4938.h>
38#endif 40#endif
@@ -821,3 +823,176 @@ void __init txx9_iocled_init(unsigned long baseaddr,
821{ 823{
822} 824}
823#endif /* CONFIG_LEDS_GPIO */ 825#endif /* CONFIG_LEDS_GPIO */
826
827void __init txx9_dmac_init(int id, unsigned long baseaddr, int irq,
828 const struct txx9dmac_platform_data *pdata)
829{
830#if defined(CONFIG_TXX9_DMAC) || defined(CONFIG_TXX9_DMAC_MODULE)
831 struct resource res[] = {
832 {
833 .start = baseaddr,
834 .end = baseaddr + 0x800 - 1,
835 .flags = IORESOURCE_MEM,
836#ifndef CONFIG_MACH_TX49XX
837 }, {
838 .start = irq,
839 .flags = IORESOURCE_IRQ,
840#endif
841 }
842 };
843#ifdef CONFIG_MACH_TX49XX
844 struct resource chan_res[] = {
845 {
846 .flags = IORESOURCE_IRQ,
847 }
848 };
849#endif
850 struct platform_device *pdev = platform_device_alloc("txx9dmac", id);
851 struct txx9dmac_chan_platform_data cpdata;
852 int i;
853
854 if (!pdev ||
855 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
856 platform_device_add_data(pdev, pdata, sizeof(*pdata)) ||
857 platform_device_add(pdev)) {
858 platform_device_put(pdev);
859 return;
860 }
861 memset(&cpdata, 0, sizeof(cpdata));
862 cpdata.dmac_dev = pdev;
863 for (i = 0; i < TXX9_DMA_MAX_NR_CHANNELS; i++) {
864#ifdef CONFIG_MACH_TX49XX
865 chan_res[0].start = irq + i;
866#endif
867 pdev = platform_device_alloc("txx9dmac-chan",
868 id * TXX9_DMA_MAX_NR_CHANNELS + i);
869 if (!pdev ||
870#ifdef CONFIG_MACH_TX49XX
871 platform_device_add_resources(pdev, chan_res,
872 ARRAY_SIZE(chan_res)) ||
873#endif
874 platform_device_add_data(pdev, &cpdata, sizeof(cpdata)) ||
875 platform_device_add(pdev))
876 platform_device_put(pdev);
877 }
878#endif
879}
880
881void __init txx9_aclc_init(unsigned long baseaddr, int irq,
882 unsigned int dmac_id,
883 unsigned int dma_chan_out,
884 unsigned int dma_chan_in)
885{
886#if defined(CONFIG_SND_SOC_TXX9ACLC) || \
887 defined(CONFIG_SND_SOC_TXX9ACLC_MODULE)
888 unsigned int dma_base = dmac_id * TXX9_DMA_MAX_NR_CHANNELS;
889 struct resource res[] = {
890 {
891 .start = baseaddr,
892 .end = baseaddr + 0x100 - 1,
893 .flags = IORESOURCE_MEM,
894 }, {
895 .start = irq,
896 .flags = IORESOURCE_IRQ,
897 }, {
898 .name = "txx9dmac-chan",
899 .start = dma_base + dma_chan_out,
900 .flags = IORESOURCE_DMA,
901 }, {
902 .name = "txx9dmac-chan",
903 .start = dma_base + dma_chan_in,
904 .flags = IORESOURCE_DMA,
905 }
906 };
907 struct platform_device *pdev =
908 platform_device_alloc("txx9aclc-ac97", -1);
909
910 if (!pdev ||
911 platform_device_add_resources(pdev, res, ARRAY_SIZE(res)) ||
912 platform_device_add(pdev))
913 platform_device_put(pdev);
914#endif
915}
916
917static struct sysdev_class txx9_sramc_sysdev_class;
918
919struct txx9_sramc_sysdev {
920 struct sys_device dev;
921 struct bin_attribute bindata_attr;
922 void __iomem *base;
923};
924
925static ssize_t txx9_sram_read(struct kobject *kobj,
926 struct bin_attribute *bin_attr,
927 char *buf, loff_t pos, size_t size)
928{
929 struct txx9_sramc_sysdev *dev = bin_attr->private;
930 size_t ramsize = bin_attr->size;
931
932 if (pos >= ramsize)
933 return 0;
934 if (pos + size > ramsize)
935 size = ramsize - pos;
936 memcpy_fromio(buf, dev->base + pos, size);
937 return size;
938}
939
940static ssize_t txx9_sram_write(struct kobject *kobj,
941 struct bin_attribute *bin_attr,
942 char *buf, loff_t pos, size_t size)
943{
944 struct txx9_sramc_sysdev *dev = bin_attr->private;
945 size_t ramsize = bin_attr->size;
946
947 if (pos >= ramsize)
948 return 0;
949 if (pos + size > ramsize)
950 size = ramsize - pos;
951 memcpy_toio(dev->base + pos, buf, size);
952 return size;
953}
954
955void __init txx9_sramc_init(struct resource *r)
956{
957 struct txx9_sramc_sysdev *dev;
958 size_t size;
959 int err;
960
961 if (!txx9_sramc_sysdev_class.name) {
962 txx9_sramc_sysdev_class.name = "txx9_sram";
963 err = sysdev_class_register(&txx9_sramc_sysdev_class);
964 if (err) {
965 txx9_sramc_sysdev_class.name = NULL;
966 return;
967 }
968 }
969 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
970 if (!dev)
971 return;
972 size = resource_size(r);
973 dev->base = ioremap(r->start, size);
974 if (!dev->base)
975 goto exit;
976 dev->dev.cls = &txx9_sramc_sysdev_class;
977 dev->bindata_attr.attr.name = "bindata";
978 dev->bindata_attr.attr.mode = S_IRUSR | S_IWUSR;
979 dev->bindata_attr.read = txx9_sram_read;
980 dev->bindata_attr.write = txx9_sram_write;
981 dev->bindata_attr.size = size;
982 dev->bindata_attr.private = dev;
983 err = sysdev_register(&dev->dev);
984 if (err)
985 goto exit;
986 err = sysfs_create_bin_file(&dev->dev.kobj, &dev->bindata_attr);
987 if (err) {
988 sysdev_unregister(&dev->dev);
989 goto exit;
990 }
991 return;
992exit:
993 if (dev) {
994 if (dev->base)
995 iounmap(dev->base);
996 kfree(dev);
997 }
998}
diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index 1093549df1a8..3418b2a90f7e 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -22,6 +22,7 @@
22#include <asm/txx9tmr.h> 22#include <asm/txx9tmr.h>
23#include <asm/txx9pio.h> 23#include <asm/txx9pio.h>
24#include <asm/txx9/generic.h> 24#include <asm/txx9/generic.h>
25#include <asm/txx9/dmac.h>
25#include <asm/txx9/tx4927.h> 26#include <asm/txx9/tx4927.h>
26 27
27static void __init tx4927_wdr_init(void) 28static void __init tx4927_wdr_init(void)
@@ -253,6 +254,60 @@ void __init tx4927_mtd_init(int ch)
253 txx9_physmap_flash_init(ch, start, size, &pdata); 254 txx9_physmap_flash_init(ch, start, size, &pdata);
254} 255}
255 256
257void __init tx4927_dmac_init(int memcpy_chan)
258{
259 struct txx9dmac_platform_data plat_data = {
260 .memcpy_chan = memcpy_chan,
261 .have_64bit_regs = true,
262 };
263
264 txx9_dmac_init(0, TX4927_DMA_REG & 0xfffffffffULL,
265 TXX9_IRQ_BASE + TX4927_IR_DMA(0), &plat_data);
266}
267
268void __init tx4927_aclc_init(unsigned int dma_chan_out,
269 unsigned int dma_chan_in)
270{
271 u64 pcfg = __raw_readq(&tx4927_ccfgptr->pcfg);
272 __u64 dmasel_mask = 0, dmasel = 0;
273 unsigned long flags;
274
275 if (!(pcfg & TX4927_PCFG_SEL2))
276 return;
277 /* setup DMASEL (playback:ACLC ch0, capture:ACLC ch1) */
278 switch (dma_chan_out) {
279 case 0:
280 dmasel_mask |= TX4927_PCFG_DMASEL0_MASK;
281 dmasel |= TX4927_PCFG_DMASEL0_ACL0;
282 break;
283 case 2:
284 dmasel_mask |= TX4927_PCFG_DMASEL2_MASK;
285 dmasel |= TX4927_PCFG_DMASEL2_ACL0;
286 break;
287 default:
288 return;
289 }
290 switch (dma_chan_in) {
291 case 1:
292 dmasel_mask |= TX4927_PCFG_DMASEL1_MASK;
293 dmasel |= TX4927_PCFG_DMASEL1_ACL1;
294 break;
295 case 3:
296 dmasel_mask |= TX4927_PCFG_DMASEL3_MASK;
297 dmasel |= TX4927_PCFG_DMASEL3_ACL1;
298 break;
299 default:
300 return;
301 }
302 local_irq_save(flags);
303 txx9_clear64(&tx4927_ccfgptr->pcfg, dmasel_mask);
304 txx9_set64(&tx4927_ccfgptr->pcfg, dmasel);
305 local_irq_restore(flags);
306 txx9_aclc_init(TX4927_ACLC_REG & 0xfffffffffULL,
307 TXX9_IRQ_BASE + TX4927_IR_ACLC,
308 0, dma_chan_out, dma_chan_in);
309}
310
256static void __init tx4927_stop_unused_modules(void) 311static void __init tx4927_stop_unused_modules(void)
257{ 312{
258 __u64 pcfg, rst = 0, ckd = 0; 313 __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 3925219b8973..eb2080110239 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -24,6 +24,7 @@
24#include <asm/txx9pio.h> 24#include <asm/txx9pio.h>
25#include <asm/txx9/generic.h> 25#include <asm/txx9/generic.h>
26#include <asm/txx9/ndfmc.h> 26#include <asm/txx9/ndfmc.h>
27#include <asm/txx9/dmac.h>
27#include <asm/txx9/tx4938.h> 28#include <asm/txx9/tx4938.h>
28 29
29static void __init tx4938_wdr_init(void) 30static void __init tx4938_wdr_init(void)
@@ -239,11 +240,6 @@ void __init tx4938_setup(void)
239 for (i = 0; i < TX4938_NR_TMR; i++) 240 for (i = 0; i < TX4938_NR_TMR; i++)
240 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL); 241 txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
241 242
242 /* DMA */
243 for (i = 0; i < 2; i++)
244 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
245 (void __iomem *)(TX4938_DMA_REG(i) + 0x50));
246
247 /* PIO */ 243 /* PIO */
248 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO); 244 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
249 __raw_writel(0, &tx4938_pioptr->maskcpu); 245 __raw_writel(0, &tx4938_pioptr->maskcpu);
@@ -403,6 +399,38 @@ void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw)
403 txx9_ndfmc_init(baseaddr, &plat_data); 399 txx9_ndfmc_init(baseaddr, &plat_data);
404} 400}
405 401
402void __init tx4938_dmac_init(int memcpy_chan0, int memcpy_chan1)
403{
404 struct txx9dmac_platform_data plat_data = {
405 .have_64bit_regs = true,
406 };
407 int i;
408
409 for (i = 0; i < 2; i++) {
410 plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
411 txx9_dmac_init(i, TX4938_DMA_REG(i) & 0xfffffffffULL,
412 TXX9_IRQ_BASE + TX4938_IR_DMA(i, 0),
413 &plat_data);
414 }
415}
416
417void __init tx4938_aclc_init(void)
418{
419 u64 pcfg = __raw_readq(&tx4938_ccfgptr->pcfg);
420
421 if ((pcfg & TX4938_PCFG_SEL2) &&
422 !(pcfg & TX4938_PCFG_ETH0_SEL))
423 txx9_aclc_init(TX4938_ACLC_REG & 0xfffffffffULL,
424 TXX9_IRQ_BASE + TX4938_IR_ACLC,
425 1, 0, 1);
426}
427
428void __init tx4938_sramc_init(void)
429{
430 if (tx4938_sram_resource.start)
431 txx9_sramc_init(&tx4938_sram_resource);
432}
433
406static void __init tx4938_stop_unused_modules(void) 434static void __init tx4938_stop_unused_modules(void)
407{ 435{
408 __u64 pcfg, rst = 0, ckd = 0; 436 __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index c2bf150c8838..3dc19f482959 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -28,6 +28,7 @@
28#include <asm/txx9tmr.h> 28#include <asm/txx9tmr.h>
29#include <asm/txx9/generic.h> 29#include <asm/txx9/generic.h>
30#include <asm/txx9/ndfmc.h> 30#include <asm/txx9/ndfmc.h>
31#include <asm/txx9/dmac.h>
31#include <asm/txx9/tx4939.h> 32#include <asm/txx9/tx4939.h>
32 33
33static void __init tx4939_wdr_init(void) 34static void __init tx4939_wdr_init(void)
@@ -259,11 +260,6 @@ void __init tx4939_setup(void)
259 for (i = 0; i < TX4939_NR_TMR; i++) 260 for (i = 0; i < TX4939_NR_TMR; i++)
260 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL); 261 txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
261 262
262 /* DMA */
263 for (i = 0; i < 2; i++)
264 ____raw_writeq(TX4938_DMA_MCR_MSTEN,
265 (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
266
267 /* set PCIC1 reset (required to prevent hangup on BIST) */ 263 /* set PCIC1 reset (required to prevent hangup on BIST) */
268 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST); 264 txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
269 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg); 265 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
@@ -474,6 +470,53 @@ void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw,
474 txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data); 470 txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data);
475} 471}
476 472
473void __init tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1)
474{
475 struct txx9dmac_platform_data plat_data = {
476 .have_64bit_regs = true,
477 };
478 int i;
479
480 for (i = 0; i < 2; i++) {
481 plat_data.memcpy_chan = i ? memcpy_chan1 : memcpy_chan0;
482 txx9_dmac_init(i, TX4939_DMA_REG(i) & 0xfffffffffULL,
483 TXX9_IRQ_BASE + TX4939_IR_DMA(i, 0),
484 &plat_data);
485 }
486}
487
488void __init tx4939_aclc_init(void)
489{
490 u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
491
492 if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_ACLC)
493 txx9_aclc_init(TX4939_ACLC_REG & 0xfffffffffULL,
494 TXX9_IRQ_BASE + TX4939_IR_ACLC, 1, 0, 1);
495}
496
497void __init tx4939_sramc_init(void)
498{
499 if (tx4939_sram_resource.start)
500 txx9_sramc_init(&tx4939_sram_resource);
501}
502
503void __init tx4939_rng_init(void)
504{
505 static struct resource res = {
506 .start = TX4939_RNG_REG & 0xfffffffffULL,
507 .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1,
508 .flags = IORESOURCE_MEM,
509 };
510 static struct platform_device pdev = {
511 .name = "tx4939-rng",
512 .id = -1,
513 .num_resources = 1,
514 .resource = &res,
515 };
516
517 platform_device_register(&pdev);
518}
519
477static void __init tx4939_stop_unused_modules(void) 520static void __init tx4939_stop_unused_modules(void)
478{ 521{
479 __u64 pcfg, rst = 0, ckd = 0; 522 __u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 01129a9d50fa..ee468eaee4f7 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -337,6 +337,14 @@ static void __init rbtx4927_device_init(void)
337 rbtx4927_ne_init(); 337 rbtx4927_ne_init();
338 tx4927_wdt_init(); 338 tx4927_wdt_init();
339 rbtx4927_mtd_init(); 339 rbtx4927_mtd_init();
340 if (TX4927_REV_PCODE() == 0x4927) {
341 tx4927_dmac_init(2);
342 tx4927_aclc_init(0, 1);
343 } else {
344 tx4938_dmac_init(0, 2);
345 tx4938_aclc_init();
346 }
347 platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
340 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL); 348 txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
341 rbtx4927_gpioled_init(); 349 rbtx4927_gpioled_init();
342} 350}
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index 65d13df8878a..d66509b14284 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -355,6 +355,10 @@ static void __init rbtx4938_device_init(void)
355 /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ 355 /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
356 tx4938_ndfmc_init(10, 35); 356 tx4938_ndfmc_init(10, 35);
357 tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1); 357 tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
358 tx4938_dmac_init(0, 2);
359 tx4938_aclc_init();
360 platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
361 tx4938_sramc_init();
358 txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL); 362 txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
359} 363}
360 364
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 4199c6fd4d1d..c033ffe71cdf 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -498,6 +498,11 @@ static void __init rbtx4939_device_init(void)
498 tx4939_wdt_init(); 498 tx4939_wdt_init();
499 tx4939_ata_init(); 499 tx4939_ata_init();
500 tx4939_rtc_init(); 500 tx4939_rtc_init();
501 tx4939_dmac_init(0, 2);
502 tx4939_aclc_init();
503 platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
504 tx4939_sramc_init();
505 tx4939_rng_init();
501} 506}
502 507
503static void __init rbtx4939_setup(void) 508static void __init rbtx4939_setup(void)
diff --git a/arch/mn10300/include/asm/kmap_types.h b/arch/mn10300/include/asm/kmap_types.h
index 3398f9f35603..76d093b58d4f 100644
--- a/arch/mn10300/include/asm/kmap_types.h
+++ b/arch/mn10300/include/asm/kmap_types.h
@@ -1,31 +1,6 @@
1/* MN10300 kmap_atomic() slot IDs
2 *
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
10 */
11#ifndef _ASM_KMAP_TYPES_H 1#ifndef _ASM_KMAP_TYPES_H
12#define _ASM_KMAP_TYPES_H 2#define _ASM_KMAP_TYPES_H
13 3
14enum km_type { 4#include <asm-generic/kmap_types.h>
15 KM_BOUNCE_READ,
16 KM_SKB_SUNRPC_DATA,
17 KM_SKB_DATA_SOFTIRQ,
18 KM_USER0,
19 KM_USER1,
20 KM_BIO_SRC_IRQ,
21 KM_BIO_DST_IRQ,
22 KM_PTE0,
23 KM_PTE1,
24 KM_IRQ0,
25 KM_IRQ1,
26 KM_SOFTIRQ0,
27 KM_SOFTIRQ1,
28 KM_TYPE_NR
29};
30 5
31#endif /* _ASM_KMAP_TYPES_H */ 6#endif /* _ASM_KMAP_TYPES_H */
diff --git a/arch/mn10300/kernel/init_task.c b/arch/mn10300/kernel/init_task.c
index 5ac3566f8c98..80d423b80af3 100644
--- a/arch/mn10300/kernel/init_task.c
+++ b/arch/mn10300/kernel/init_task.c
@@ -20,9 +20,6 @@
20 20
21static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 21static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
22static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 22static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
23struct mm_struct init_mm = INIT_MM(init_mm);
24EXPORT_SYMBOL(init_mm);
25
26/* 23/*
27 * Initial thread structure. 24 * Initial thread structure.
28 * 25 *
diff --git a/arch/parisc/include/asm/kmap_types.h b/arch/parisc/include/asm/kmap_types.h
index 806aae3c5338..58e91ed0388f 100644
--- a/arch/parisc/include/asm/kmap_types.h
+++ b/arch/parisc/include/asm/kmap_types.h
@@ -1,30 +1,12 @@
1#ifndef _ASM_KMAP_TYPES_H 1#ifndef _ASM_KMAP_TYPES_H
2#define _ASM_KMAP_TYPES_H 2#define _ASM_KMAP_TYPES_H
3 3
4
5#ifdef CONFIG_DEBUG_HIGHMEM 4#ifdef CONFIG_DEBUG_HIGHMEM
6# define D(n) __KM_FENCE_##n , 5#define __WITH_KM_FENCE
7#else
8# define D(n)
9#endif 6#endif
10 7
11enum km_type { 8#include <asm-generic/kmap_types.h>
12D(0) KM_BOUNCE_READ,
13D(1) KM_SKB_SUNRPC_DATA,
14D(2) KM_SKB_DATA_SOFTIRQ,
15D(3) KM_USER0,
16D(4) KM_USER1,
17D(5) KM_BIO_SRC_IRQ,
18D(6) KM_BIO_DST_IRQ,
19D(7) KM_PTE0,
20D(8) KM_PTE1,
21D(9) KM_IRQ0,
22D(10) KM_IRQ1,
23D(11) KM_SOFTIRQ0,
24D(12) KM_SOFTIRQ1,
25D(13) KM_TYPE_NR
26};
27 9
28#undef D 10#undef __WITH_KM_FENCE
29 11
30#endif 12#endif
diff --git a/arch/parisc/kernel/init_task.c b/arch/parisc/kernel/init_task.c
index 1e25a45d64c1..82974b20fc10 100644
--- a/arch/parisc/kernel/init_task.c
+++ b/arch/parisc/kernel/init_task.c
@@ -36,10 +36,6 @@
36 36
37static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 37static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
38static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 38static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
39struct mm_struct init_mm = INIT_MM(init_mm);
40
41EXPORT_SYMBOL(init_mm);
42
43/* 39/*
44 * Initial task structure. 40 * Initial task structure.
45 * 41 *
diff --git a/arch/powerpc/include/asm/8253pit.h b/arch/powerpc/include/asm/8253pit.h
index b70d6e53b303..a71c9c1455a7 100644
--- a/arch/powerpc/include/asm/8253pit.h
+++ b/arch/powerpc/include/asm/8253pit.h
@@ -1,10 +1,3 @@
1#ifndef _ASM_POWERPC_8253PIT_H
2#define _ASM_POWERPC_8253PIT_H
3
4/* 1/*
5 * 8253/8254 Programmable Interval Timer 2 * 8253/8254 Programmable Interval Timer
6 */ 3 */
7
8#define PIT_TICK_RATE 1193182UL
9
10#endif /* _ASM_POWERPC_8253PIT_H */
diff --git a/arch/powerpc/kernel/init_task.c b/arch/powerpc/kernel/init_task.c
index 688b329800bd..ffc4253fef55 100644
--- a/arch/powerpc/kernel/init_task.c
+++ b/arch/powerpc/kernel/init_task.c
@@ -9,10 +9,6 @@
9 9
10static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 10static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
11static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 11static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
12struct mm_struct init_mm = INIT_MM(init_mm);
13
14EXPORT_SYMBOL(init_mm);
15
16/* 12/*
17 * Initial thread structure. 13 * Initial thread structure.
18 * 14 *
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 2f0e64b53642..ef6f64950e9b 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -44,10 +44,7 @@
44#include <asm/sections.h> 44#include <asm/sections.h>
45#include <asm/machdep.h> 45#include <asm/machdep.h>
46 46
47#ifdef CONFIG_LOGO_LINUX_CLUT224
48#include <linux/linux_logo.h> 47#include <linux/linux_logo.h>
49extern const struct linux_logo logo_linux_clut224;
50#endif
51 48
52/* 49/*
53 * Properties whose value is longer than this get excluded from our 50 * Properties whose value is longer than this get excluded from our
diff --git a/arch/powerpc/platforms/cell/ras.c b/arch/powerpc/platforms/cell/ras.c
index 296b5268754e..5e0a191764fc 100644
--- a/arch/powerpc/platforms/cell/ras.c
+++ b/arch/powerpc/platforms/cell/ras.c
@@ -122,8 +122,8 @@ static int __init cbe_ptcal_enable_on_node(int nid, int order)
122 122
123 area->nid = nid; 123 area->nid = nid;
124 area->order = order; 124 area->order = order;
125 area->pages = alloc_pages_node(area->nid, GFP_KERNEL | GFP_THISNODE, 125 area->pages = alloc_pages_exact_node(area->nid, GFP_KERNEL|GFP_THISNODE,
126 area->order); 126 area->order);
127 127
128 if (!area->pages) { 128 if (!area->pages) {
129 printk(KERN_WARNING "%s: no page on node %d\n", 129 printk(KERN_WARNING "%s: no page on node %d\n",
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index 9abd210d87c1..8547e86bfb42 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -752,17 +752,8 @@ static int __init init_spu_base(void)
752 goto out_unregister_sysdev_class; 752 goto out_unregister_sysdev_class;
753 } 753 }
754 754
755 if (ret > 0) { 755 if (ret > 0)
756 /*
757 * We cannot put the forward declaration in
758 * <linux/linux_logo.h> because of conflicting session type
759 * conflicts for const and __initdata with different compiler
760 * versions
761 */
762 extern const struct linux_logo logo_spe_clut224;
763
764 fb_append_extra_logo(&logo_spe_clut224, ret); 756 fb_append_extra_logo(&logo_spe_clut224, ret);
765 }
766 757
767 mutex_lock(&spu_full_list_mutex); 758 mutex_lock(&spu_full_list_mutex);
768 xmon_register_spus(&spu_full_list); 759 xmon_register_spus(&spu_full_list);
diff --git a/arch/s390/include/asm/kmap_types.h b/arch/s390/include/asm/kmap_types.h
index fd1574648223..94ec3ee07983 100644
--- a/arch/s390/include/asm/kmap_types.h
+++ b/arch/s390/include/asm/kmap_types.h
@@ -2,22 +2,7 @@
2#ifndef _ASM_KMAP_TYPES_H 2#ifndef _ASM_KMAP_TYPES_H
3#define _ASM_KMAP_TYPES_H 3#define _ASM_KMAP_TYPES_H
4 4
5enum km_type { 5#include <asm-generic/kmap_types.h>
6 KM_BOUNCE_READ,
7 KM_SKB_SUNRPC_DATA,
8 KM_SKB_DATA_SOFTIRQ,
9 KM_USER0,
10 KM_USER1,
11 KM_BIO_SRC_IRQ,
12 KM_BIO_DST_IRQ,
13 KM_PTE0,
14 KM_PTE1,
15 KM_IRQ0,
16 KM_IRQ1,
17 KM_SOFTIRQ0,
18 KM_SOFTIRQ1,
19 KM_TYPE_NR
20};
21 6
22#endif 7#endif
23#endif /* __KERNEL__ */ 8#endif /* __KERNEL__ */
diff --git a/arch/s390/kernel/init_task.c b/arch/s390/kernel/init_task.c
index 7db95c0b8693..fe787f9e5f3f 100644
--- a/arch/s390/kernel/init_task.c
+++ b/arch/s390/kernel/init_task.c
@@ -18,10 +18,6 @@
18 18
19static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 19static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
20static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 20static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
21struct mm_struct init_mm = INIT_MM(init_mm);
22
23EXPORT_SYMBOL(init_mm);
24
25/* 21/*
26 * Initial thread structure. 22 * Initial thread structure.
27 * 23 *
diff --git a/arch/sh/include/asm/kmap_types.h b/arch/sh/include/asm/kmap_types.h
index 84d565c696be..5962b08b6dd8 100644
--- a/arch/sh/include/asm/kmap_types.h
+++ b/arch/sh/include/asm/kmap_types.h
@@ -3,30 +3,12 @@
3 3
4/* Dummy header just to define km_type. */ 4/* Dummy header just to define km_type. */
5 5
6
7#ifdef CONFIG_DEBUG_HIGHMEM 6#ifdef CONFIG_DEBUG_HIGHMEM
8# define D(n) __KM_FENCE_##n , 7#define __WITH_KM_FENCE
9#else
10# define D(n)
11#endif 8#endif
12 9
13enum km_type { 10#include <asm-generic/kmap_types.h>
14D(0) KM_BOUNCE_READ,
15D(1) KM_SKB_SUNRPC_DATA,
16D(2) KM_SKB_DATA_SOFTIRQ,
17D(3) KM_USER0,
18D(4) KM_USER1,
19D(5) KM_BIO_SRC_IRQ,
20D(6) KM_BIO_DST_IRQ,
21D(7) KM_PTE0,
22D(8) KM_PTE1,
23D(9) KM_IRQ0,
24D(10) KM_IRQ1,
25D(11) KM_SOFTIRQ0,
26D(12) KM_SOFTIRQ1,
27D(13) KM_TYPE_NR
28};
29 11
30#undef D 12#undef __WITH_KM_FENCE
31 13
32#endif 14#endif
diff --git a/arch/sh/kernel/init_task.c b/arch/sh/kernel/init_task.c
index 80c35ff71d56..1719957c0a69 100644
--- a/arch/sh/kernel/init_task.c
+++ b/arch/sh/kernel/init_task.c
@@ -10,9 +10,6 @@
10static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 10static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
11static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 11static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
12struct pt_regs fake_swapper_regs; 12struct pt_regs fake_swapper_regs;
13struct mm_struct init_mm = INIT_MM(init_mm);
14EXPORT_SYMBOL(init_mm);
15
16/* 13/*
17 * Initial thread structure. 14 * Initial thread structure.
18 * 15 *
diff --git a/arch/sparc/include/asm/kmap_types.h b/arch/sparc/include/asm/kmap_types.h
index 602f5e034f7a..aad21745fbb9 100644
--- a/arch/sparc/include/asm/kmap_types.h
+++ b/arch/sparc/include/asm/kmap_types.h
@@ -5,21 +5,6 @@
5 * is actually used on sparc. -DaveM 5 * is actually used on sparc. -DaveM
6 */ 6 */
7 7
8enum km_type { 8#include <asm-generic/kmap_types.h>
9 KM_BOUNCE_READ,
10 KM_SKB_SUNRPC_DATA,
11 KM_SKB_DATA_SOFTIRQ,
12 KM_USER0,
13 KM_USER1,
14 KM_BIO_SRC_IRQ,
15 KM_BIO_DST_IRQ,
16 KM_PTE0,
17 KM_PTE1,
18 KM_IRQ0,
19 KM_IRQ1,
20 KM_SOFTIRQ0,
21 KM_SOFTIRQ1,
22 KM_TYPE_NR
23};
24 9
25#endif 10#endif
diff --git a/arch/sparc/kernel/init_task.c b/arch/sparc/kernel/init_task.c
index f28cb8278e98..28125c5b3d3c 100644
--- a/arch/sparc/kernel/init_task.c
+++ b/arch/sparc/kernel/init_task.c
@@ -10,10 +10,7 @@
10 10
11static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 11static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
12static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 12static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
13struct mm_struct init_mm = INIT_MM(init_mm);
14struct task_struct init_task = INIT_TASK(init_task); 13struct task_struct init_task = INIT_TASK(init_task);
15
16EXPORT_SYMBOL(init_mm);
17EXPORT_SYMBOL(init_task); 14EXPORT_SYMBOL(init_task);
18 15
19/* .text section in head.S is aligned at 8k boundary and this gets linked 16/* .text section in head.S is aligned at 8k boundary and this gets linked
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 434ba121e3c5..3b44b47c7e1d 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -360,7 +360,7 @@ static struct platform_driver uml_net_driver = {
360 360
361static void net_device_release(struct device *dev) 361static void net_device_release(struct device *dev)
362{ 362{
363 struct uml_net *device = dev->driver_data; 363 struct uml_net *device = dev_get_drvdata(dev);
364 struct net_device *netdev = device->dev; 364 struct net_device *netdev = device->dev;
365 struct uml_net_private *lp = netdev_priv(netdev); 365 struct uml_net_private *lp = netdev_priv(netdev);
366 366
@@ -440,7 +440,7 @@ static void eth_configure(int n, void *init, char *mac,
440 device->pdev.id = n; 440 device->pdev.id = n;
441 device->pdev.name = DRIVER_NAME; 441 device->pdev.name = DRIVER_NAME;
442 device->pdev.dev.release = net_device_release; 442 device->pdev.dev.release = net_device_release;
443 device->pdev.dev.driver_data = device; 443 dev_set_drvdata(&device->pdev.dev, device);
444 if (platform_device_register(&device->pdev)) 444 if (platform_device_register(&device->pdev))
445 goto out_free_netdev; 445 goto out_free_netdev;
446 SET_NETDEV_DEV(dev,&device->pdev.dev); 446 SET_NETDEV_DEV(dev,&device->pdev.dev);
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index aa9e926e13d7..8f05d4d9da12 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -778,7 +778,7 @@ static int ubd_open_dev(struct ubd *ubd_dev)
778 778
779static void ubd_device_release(struct device *dev) 779static void ubd_device_release(struct device *dev)
780{ 780{
781 struct ubd *ubd_dev = dev->driver_data; 781 struct ubd *ubd_dev = dev_get_drvdata(dev);
782 782
783 blk_cleanup_queue(ubd_dev->queue); 783 blk_cleanup_queue(ubd_dev->queue);
784 *ubd_dev = ((struct ubd) DEFAULT_UBD); 784 *ubd_dev = ((struct ubd) DEFAULT_UBD);
@@ -807,7 +807,7 @@ static int ubd_disk_register(int major, u64 size, int unit,
807 ubd_devs[unit].pdev.id = unit; 807 ubd_devs[unit].pdev.id = unit;
808 ubd_devs[unit].pdev.name = DRIVER_NAME; 808 ubd_devs[unit].pdev.name = DRIVER_NAME;
809 ubd_devs[unit].pdev.dev.release = ubd_device_release; 809 ubd_devs[unit].pdev.dev.release = ubd_device_release;
810 ubd_devs[unit].pdev.dev.driver_data = &ubd_devs[unit]; 810 dev_set_drvdata(&ubd_devs[unit].pdev.dev, &ubd_devs[unit]);
811 platform_device_register(&ubd_devs[unit].pdev); 811 platform_device_register(&ubd_devs[unit].pdev);
812 disk->driverfs_dev = &ubd_devs[unit].pdev.dev; 812 disk->driverfs_dev = &ubd_devs[unit].pdev.dev;
813 } 813 }
diff --git a/arch/um/include/shared/init.h b/arch/um/include/shared/init.h
index 37dd097c16c0..b3906f860a87 100644
--- a/arch/um/include/shared/init.h
+++ b/arch/um/include/shared/init.h
@@ -27,7 +27,7 @@
27 * sign followed by value, e.g.: 27 * sign followed by value, e.g.:
28 * 28 *
29 * static int init_variable __initdata = 0; 29 * static int init_variable __initdata = 0;
30 * static char linux_logo[] __initdata = { 0x32, 0x36, ... }; 30 * static const char linux_logo[] __initconst = { 0x32, 0x36, ... };
31 * 31 *
32 * Don't forget to initialize data not at file scope, i.e. within a function, 32 * Don't forget to initialize data not at file scope, i.e. within a function,
33 * as gcc otherwise puts the data into the bss section and not into the init 33 * as gcc otherwise puts the data into the bss section and not into the init
diff --git a/arch/um/include/shared/net_user.h b/arch/um/include/shared/net_user.h
index 63bee158cd8e..3dabbe128e40 100644
--- a/arch/um/include/shared/net_user.h
+++ b/arch/um/include/shared/net_user.h
@@ -8,7 +8,7 @@
8 8
9#define ETH_ADDR_LEN (6) 9#define ETH_ADDR_LEN (6)
10#define ETH_HEADER_ETHERTAP (16) 10#define ETH_HEADER_ETHERTAP (16)
11#define ETH_HEADER_OTHER (14) 11#define ETH_HEADER_OTHER (26) /* 14 for ethernet + VLAN + MPLS for crazy people */
12#define ETH_MAX_PACKET (1500) 12#define ETH_MAX_PACKET (1500)
13 13
14#define UML_NET_VERSION (4) 14#define UML_NET_VERSION (4)
diff --git a/arch/um/kernel/init_task.c b/arch/um/kernel/init_task.c
index 806d381947bf..b25121b537d8 100644
--- a/arch/um/kernel/init_task.c
+++ b/arch/um/kernel/init_task.c
@@ -10,11 +10,8 @@
10#include "linux/mqueue.h" 10#include "linux/mqueue.h"
11#include "asm/uaccess.h" 11#include "asm/uaccess.h"
12 12
13struct mm_struct init_mm = INIT_MM(init_mm);
14static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 13static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
15static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 14static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
16EXPORT_SYMBOL(init_mm);
17
18/* 15/*
19 * Initial task structure. 16 * Initial task structure.
20 * 17 *
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
index 336b61569072..454cdb43e351 100644
--- a/arch/um/kernel/irq.c
+++ b/arch/um/kernel/irq.c
@@ -358,7 +358,7 @@ EXPORT_SYMBOL(um_request_irq);
358EXPORT_SYMBOL(reactivate_fd); 358EXPORT_SYMBOL(reactivate_fd);
359 359
360/* 360/*
361 * hw_interrupt_type must define (startup || enable) && 361 * irq_chip must define (startup || enable) &&
362 * (shutdown || disable) && end 362 * (shutdown || disable) && end
363 */ 363 */
364static void dummy(unsigned int irq) 364static void dummy(unsigned int irq)
@@ -366,7 +366,7 @@ static void dummy(unsigned int irq)
366} 366}
367 367
368/* This is used for everything else than the timer. */ 368/* This is used for everything else than the timer. */
369static struct hw_interrupt_type normal_irq_type = { 369static struct irq_chip normal_irq_type = {
370 .typename = "SIGIO", 370 .typename = "SIGIO",
371 .release = free_irq_by_irq_and_dev, 371 .release = free_irq_by_irq_and_dev,
372 .disable = dummy, 372 .disable = dummy,
@@ -375,7 +375,7 @@ static struct hw_interrupt_type normal_irq_type = {
375 .end = dummy 375 .end = dummy
376}; 376};
377 377
378static struct hw_interrupt_type SIGVTALRM_irq_type = { 378static struct irq_chip SIGVTALRM_irq_type = {
379 .typename = "SIGVTALRM", 379 .typename = "SIGVTALRM",
380 .release = free_irq_by_irq_and_dev, 380 .release = free_irq_by_irq_and_dev,
381 .shutdown = dummy, /* never called */ 381 .shutdown = dummy, /* never called */
diff --git a/arch/um/sys-i386/stub.S b/arch/um/sys-i386/stub.S
index c41b04bf5fa0..54a36ec20cb7 100644
--- a/arch/um/sys-i386/stub.S
+++ b/arch/um/sys-i386/stub.S
@@ -1,7 +1,7 @@
1#include "as-layout.h" 1#include "as-layout.h"
2 2
3 .globl syscall_stub 3 .globl syscall_stub
4.section .__syscall_stub, "x" 4.section .__syscall_stub, "ax"
5 5
6 .globl batch_syscall_stub 6 .globl batch_syscall_stub
7batch_syscall_stub: 7batch_syscall_stub:
diff --git a/arch/um/sys-x86_64/asm/elf.h b/arch/um/sys-x86_64/asm/elf.h
index 6e8a9195e952..04b9e87c8dad 100644
--- a/arch/um/sys-x86_64/asm/elf.h
+++ b/arch/um/sys-x86_64/asm/elf.h
@@ -66,28 +66,28 @@ typedef struct user_i387_struct elf_fpregset_t;
66 PT_REGS_R15(regs) = 0; \ 66 PT_REGS_R15(regs) = 0; \
67} while (0) 67} while (0)
68 68
69#define ELF_CORE_COPY_REGS(pr_reg, regs) \ 69#define ELF_CORE_COPY_REGS(pr_reg, _regs) \
70 (pr_reg)[0] = (regs)->regs.gp[0]; \ 70 (pr_reg)[0] = (_regs)->regs.gp[0]; \
71 (pr_reg)[1] = (regs)->regs.gp[1]; \ 71 (pr_reg)[1] = (_regs)->regs.gp[1]; \
72 (pr_reg)[2] = (regs)->regs.gp[2]; \ 72 (pr_reg)[2] = (_regs)->regs.gp[2]; \
73 (pr_reg)[3] = (regs)->regs.gp[3]; \ 73 (pr_reg)[3] = (_regs)->regs.gp[3]; \
74 (pr_reg)[4] = (regs)->regs.gp[4]; \ 74 (pr_reg)[4] = (_regs)->regs.gp[4]; \
75 (pr_reg)[5] = (regs)->regs.gp[5]; \ 75 (pr_reg)[5] = (_regs)->regs.gp[5]; \
76 (pr_reg)[6] = (regs)->regs.gp[6]; \ 76 (pr_reg)[6] = (_regs)->regs.gp[6]; \
77 (pr_reg)[7] = (regs)->regs.gp[7]; \ 77 (pr_reg)[7] = (_regs)->regs.gp[7]; \
78 (pr_reg)[8] = (regs)->regs.gp[8]; \ 78 (pr_reg)[8] = (_regs)->regs.gp[8]; \
79 (pr_reg)[9] = (regs)->regs.gp[9]; \ 79 (pr_reg)[9] = (_regs)->regs.gp[9]; \
80 (pr_reg)[10] = (regs)->regs.gp[10]; \ 80 (pr_reg)[10] = (_regs)->regs.gp[10]; \
81 (pr_reg)[11] = (regs)->regs.gp[11]; \ 81 (pr_reg)[11] = (_regs)->regs.gp[11]; \
82 (pr_reg)[12] = (regs)->regs.gp[12]; \ 82 (pr_reg)[12] = (_regs)->regs.gp[12]; \
83 (pr_reg)[13] = (regs)->regs.gp[13]; \ 83 (pr_reg)[13] = (_regs)->regs.gp[13]; \
84 (pr_reg)[14] = (regs)->regs.gp[14]; \ 84 (pr_reg)[14] = (_regs)->regs.gp[14]; \
85 (pr_reg)[15] = (regs)->regs.gp[15]; \ 85 (pr_reg)[15] = (_regs)->regs.gp[15]; \
86 (pr_reg)[16] = (regs)->regs.gp[16]; \ 86 (pr_reg)[16] = (_regs)->regs.gp[16]; \
87 (pr_reg)[17] = (regs)->regs.gp[17]; \ 87 (pr_reg)[17] = (_regs)->regs.gp[17]; \
88 (pr_reg)[18] = (regs)->regs.gp[18]; \ 88 (pr_reg)[18] = (_regs)->regs.gp[18]; \
89 (pr_reg)[19] = (regs)->regs.gp[19]; \ 89 (pr_reg)[19] = (_regs)->regs.gp[19]; \
90 (pr_reg)[20] = (regs)->regs.gp[20]; \ 90 (pr_reg)[20] = (_regs)->regs.gp[20]; \
91 (pr_reg)[21] = current->thread.arch.fs; \ 91 (pr_reg)[21] = current->thread.arch.fs; \
92 (pr_reg)[22] = 0; \ 92 (pr_reg)[22] = 0; \
93 (pr_reg)[23] = 0; \ 93 (pr_reg)[23] = 0; \
diff --git a/arch/um/sys-x86_64/stub.S b/arch/um/sys-x86_64/stub.S
index 6d9edf9fabce..20e4a96a6dcb 100644
--- a/arch/um/sys-x86_64/stub.S
+++ b/arch/um/sys-x86_64/stub.S
@@ -1,7 +1,7 @@
1#include "as-layout.h" 1#include "as-layout.h"
2 2
3 .globl syscall_stub 3 .globl syscall_stub
4.section .__syscall_stub, "x" 4.section .__syscall_stub, "ax"
5syscall_stub: 5syscall_stub:
6 syscall 6 syscall
7 /* We don't have 64-bit constants, so this constructs the address 7 /* We don't have 64-bit constants, so this constructs the address
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 356d2ec8e2fb..cf42fc305419 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -46,6 +46,7 @@ config X86
46 select HAVE_KERNEL_GZIP 46 select HAVE_KERNEL_GZIP
47 select HAVE_KERNEL_BZIP2 47 select HAVE_KERNEL_BZIP2
48 select HAVE_KERNEL_LZMA 48 select HAVE_KERNEL_LZMA
49 select HAVE_ARCH_KMEMCHECK
49 50
50config OUTPUT_FORMAT 51config OUTPUT_FORMAT
51 string 52 string
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index edbd0ca62067..1b68659c41b4 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -81,6 +81,11 @@ ifdef CONFIG_CC_STACKPROTECTOR
81 endif 81 endif
82endif 82endif
83 83
84# Don't unroll struct assignments with kmemcheck enabled
85ifeq ($(CONFIG_KMEMCHECK),y)
86 KBUILD_CFLAGS += $(call cc-option,-fno-builtin-memcpy)
87endif
88
84# Stackpointer is addressed different for 32 bit and 64 bit x86 89# Stackpointer is addressed different for 32 bit and 64 bit x86
85sp-$(CONFIG_X86_32) := esp 90sp-$(CONFIG_X86_32) := esp
86sp-$(CONFIG_X86_64) := rsp 91sp-$(CONFIG_X86_64) := rsp
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index f82fdc412c64..b93405b228b4 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -6,6 +6,7 @@
6 * Documentation/DMA-API.txt for documentation. 6 * Documentation/DMA-API.txt for documentation.
7 */ 7 */
8 8
9#include <linux/kmemcheck.h>
9#include <linux/scatterlist.h> 10#include <linux/scatterlist.h>
10#include <linux/dma-debug.h> 11#include <linux/dma-debug.h>
11#include <linux/dma-attrs.h> 12#include <linux/dma-attrs.h>
@@ -60,6 +61,7 @@ dma_map_single(struct device *hwdev, void *ptr, size_t size,
60 dma_addr_t addr; 61 dma_addr_t addr;
61 62
62 BUG_ON(!valid_dma_direction(dir)); 63 BUG_ON(!valid_dma_direction(dir));
64 kmemcheck_mark_initialized(ptr, size);
63 addr = ops->map_page(hwdev, virt_to_page(ptr), 65 addr = ops->map_page(hwdev, virt_to_page(ptr),
64 (unsigned long)ptr & ~PAGE_MASK, size, 66 (unsigned long)ptr & ~PAGE_MASK, size,
65 dir, NULL); 67 dir, NULL);
@@ -87,8 +89,12 @@ dma_map_sg(struct device *hwdev, struct scatterlist *sg,
87{ 89{
88 struct dma_map_ops *ops = get_dma_ops(hwdev); 90 struct dma_map_ops *ops = get_dma_ops(hwdev);
89 int ents; 91 int ents;
92 struct scatterlist *s;
93 int i;
90 94
91 BUG_ON(!valid_dma_direction(dir)); 95 BUG_ON(!valid_dma_direction(dir));
96 for_each_sg(sg, s, nents, i)
97 kmemcheck_mark_initialized(sg_virt(s), s->length);
92 ents = ops->map_sg(hwdev, sg, nents, dir, NULL); 98 ents = ops->map_sg(hwdev, sg, nents, dir, NULL);
93 debug_dma_map_sg(hwdev, sg, nents, ents, dir); 99 debug_dma_map_sg(hwdev, sg, nents, ents, dir);
94 100
@@ -200,6 +206,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
200 dma_addr_t addr; 206 dma_addr_t addr;
201 207
202 BUG_ON(!valid_dma_direction(dir)); 208 BUG_ON(!valid_dma_direction(dir));
209 kmemcheck_mark_initialized(page_address(page) + offset, size);
203 addr = ops->map_page(dev, page, offset, size, dir, NULL); 210 addr = ops->map_page(dev, page, offset, size, dir, NULL);
204 debug_dma_map_page(dev, page, offset, size, dir, addr, false); 211 debug_dma_map_page(dev, page, offset, size, dir, addr, false);
205 212
diff --git a/arch/x86/include/asm/kmap_types.h b/arch/x86/include/asm/kmap_types.h
index 5759c165a5cf..9e00a731a7fb 100644
--- a/arch/x86/include/asm/kmap_types.h
+++ b/arch/x86/include/asm/kmap_types.h
@@ -2,28 +2,11 @@
2#define _ASM_X86_KMAP_TYPES_H 2#define _ASM_X86_KMAP_TYPES_H
3 3
4#if defined(CONFIG_X86_32) && defined(CONFIG_DEBUG_HIGHMEM) 4#if defined(CONFIG_X86_32) && defined(CONFIG_DEBUG_HIGHMEM)
5# define D(n) __KM_FENCE_##n , 5#define __WITH_KM_FENCE
6#else
7# define D(n)
8#endif 6#endif
9 7
10enum km_type { 8#include <asm-generic/kmap_types.h>
11D(0) KM_BOUNCE_READ,
12D(1) KM_SKB_SUNRPC_DATA,
13D(2) KM_SKB_DATA_SOFTIRQ,
14D(3) KM_USER0,
15D(4) KM_USER1,
16D(5) KM_BIO_SRC_IRQ,
17D(6) KM_BIO_DST_IRQ,
18D(7) KM_PTE0,
19D(8) KM_PTE1,
20D(9) KM_IRQ0,
21D(10) KM_IRQ1,
22D(11) KM_SOFTIRQ0,
23D(12) KM_SOFTIRQ1,
24D(13) KM_TYPE_NR
25};
26 9
27#undef D 10#undef __WITH_KM_FENCE
28 11
29#endif /* _ASM_X86_KMAP_TYPES_H */ 12#endif /* _ASM_X86_KMAP_TYPES_H */
diff --git a/arch/x86/include/asm/kmemcheck.h b/arch/x86/include/asm/kmemcheck.h
new file mode 100644
index 000000000000..ed01518f297e
--- /dev/null
+++ b/arch/x86/include/asm/kmemcheck.h
@@ -0,0 +1,42 @@
1#ifndef ASM_X86_KMEMCHECK_H
2#define ASM_X86_KMEMCHECK_H
3
4#include <linux/types.h>
5#include <asm/ptrace.h>
6
7#ifdef CONFIG_KMEMCHECK
8bool kmemcheck_active(struct pt_regs *regs);
9
10void kmemcheck_show(struct pt_regs *regs);
11void kmemcheck_hide(struct pt_regs *regs);
12
13bool kmemcheck_fault(struct pt_regs *regs,
14 unsigned long address, unsigned long error_code);
15bool kmemcheck_trap(struct pt_regs *regs);
16#else
17static inline bool kmemcheck_active(struct pt_regs *regs)
18{
19 return false;
20}
21
22static inline void kmemcheck_show(struct pt_regs *regs)
23{
24}
25
26static inline void kmemcheck_hide(struct pt_regs *regs)
27{
28}
29
30static inline bool kmemcheck_fault(struct pt_regs *regs,
31 unsigned long address, unsigned long error_code)
32{
33 return false;
34}
35
36static inline bool kmemcheck_trap(struct pt_regs *regs)
37{
38 return false;
39}
40#endif /* CONFIG_KMEMCHECK */
41
42#endif
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 18ef7ebf2631..3cc06e3fceb8 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -317,6 +317,11 @@ static inline int pte_present(pte_t a)
317 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE); 317 return pte_flags(a) & (_PAGE_PRESENT | _PAGE_PROTNONE);
318} 318}
319 319
320static inline int pte_hidden(pte_t pte)
321{
322 return pte_flags(pte) & _PAGE_HIDDEN;
323}
324
320static inline int pmd_present(pmd_t pmd) 325static inline int pmd_present(pmd_t pmd)
321{ 326{
322 return pmd_flags(pmd) & _PAGE_PRESENT; 327 return pmd_flags(pmd) & _PAGE_PRESENT;
diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
index 4d258ad76a0f..54cb697f4900 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -18,7 +18,7 @@
18#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */ 18#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
19#define _PAGE_BIT_UNUSED1 9 /* available for programmer */ 19#define _PAGE_BIT_UNUSED1 9 /* available for programmer */
20#define _PAGE_BIT_IOMAP 10 /* flag used to indicate IO mapping */ 20#define _PAGE_BIT_IOMAP 10 /* flag used to indicate IO mapping */
21#define _PAGE_BIT_UNUSED3 11 21#define _PAGE_BIT_HIDDEN 11 /* hidden by kmemcheck */
22#define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */ 22#define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
23#define _PAGE_BIT_SPECIAL _PAGE_BIT_UNUSED1 23#define _PAGE_BIT_SPECIAL _PAGE_BIT_UNUSED1
24#define _PAGE_BIT_CPA_TEST _PAGE_BIT_UNUSED1 24#define _PAGE_BIT_CPA_TEST _PAGE_BIT_UNUSED1
@@ -41,13 +41,18 @@
41#define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL) 41#define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
42#define _PAGE_UNUSED1 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1) 42#define _PAGE_UNUSED1 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1)
43#define _PAGE_IOMAP (_AT(pteval_t, 1) << _PAGE_BIT_IOMAP) 43#define _PAGE_IOMAP (_AT(pteval_t, 1) << _PAGE_BIT_IOMAP)
44#define _PAGE_UNUSED3 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED3)
45#define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT) 44#define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
46#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE) 45#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
47#define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL) 46#define _PAGE_SPECIAL (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
48#define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST) 47#define _PAGE_CPA_TEST (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
49#define __HAVE_ARCH_PTE_SPECIAL 48#define __HAVE_ARCH_PTE_SPECIAL
50 49
50#ifdef CONFIG_KMEMCHECK
51#define _PAGE_HIDDEN (_AT(pteval_t, 1) << _PAGE_BIT_HIDDEN)
52#else
53#define _PAGE_HIDDEN (_AT(pteval_t, 0))
54#endif
55
51#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) 56#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
52#define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX) 57#define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
53#else 58#else
diff --git a/arch/x86/include/asm/string_32.h b/arch/x86/include/asm/string_32.h
index 0e0e3ba827f7..c86f452256de 100644
--- a/arch/x86/include/asm/string_32.h
+++ b/arch/x86/include/asm/string_32.h
@@ -177,10 +177,18 @@ static inline void *__memcpy3d(void *to, const void *from, size_t len)
177 * No 3D Now! 177 * No 3D Now!
178 */ 178 */
179 179
180#ifndef CONFIG_KMEMCHECK
180#define memcpy(t, f, n) \ 181#define memcpy(t, f, n) \
181 (__builtin_constant_p((n)) \ 182 (__builtin_constant_p((n)) \
182 ? __constant_memcpy((t), (f), (n)) \ 183 ? __constant_memcpy((t), (f), (n)) \
183 : __memcpy((t), (f), (n))) 184 : __memcpy((t), (f), (n)))
185#else
186/*
187 * kmemcheck becomes very happy if we use the REP instructions unconditionally,
188 * because it means that we know both memory operands in advance.
189 */
190#define memcpy(t, f, n) __memcpy((t), (f), (n))
191#endif
184 192
185#endif 193#endif
186 194
diff --git a/arch/x86/include/asm/string_64.h b/arch/x86/include/asm/string_64.h
index 2afe164bf1e6..19e2c468fc2c 100644
--- a/arch/x86/include/asm/string_64.h
+++ b/arch/x86/include/asm/string_64.h
@@ -27,6 +27,7 @@ static __always_inline void *__inline_memcpy(void *to, const void *from, size_t
27 function. */ 27 function. */
28 28
29#define __HAVE_ARCH_MEMCPY 1 29#define __HAVE_ARCH_MEMCPY 1
30#ifndef CONFIG_KMEMCHECK
30#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 3) || __GNUC__ > 4 31#if (__GNUC__ == 4 && __GNUC_MINOR__ >= 3) || __GNUC__ > 4
31extern void *memcpy(void *to, const void *from, size_t len); 32extern void *memcpy(void *to, const void *from, size_t len);
32#else 33#else
@@ -42,6 +43,13 @@ extern void *__memcpy(void *to, const void *from, size_t len);
42 __ret; \ 43 __ret; \
43}) 44})
44#endif 45#endif
46#else
47/*
48 * kmemcheck becomes very happy if we use the REP instructions unconditionally,
49 * because it means that we know both memory operands in advance.
50 */
51#define memcpy(dst, src, len) __inline_memcpy((dst), (src), (len))
52#endif
45 53
46#define __HAVE_ARCH_MEMSET 54#define __HAVE_ARCH_MEMSET
47void *memset(void *s, int c, size_t n); 55void *memset(void *s, int c, size_t n);
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 602c769fc98c..b0783520988b 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -154,9 +154,9 @@ struct thread_info {
154 154
155/* thread information allocation */ 155/* thread information allocation */
156#ifdef CONFIG_DEBUG_STACK_USAGE 156#ifdef CONFIG_DEBUG_STACK_USAGE
157#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO) 157#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO)
158#else 158#else
159#define THREAD_FLAGS GFP_KERNEL 159#define THREAD_FLAGS (GFP_KERNEL | __GFP_NOTRACK)
160#endif 160#endif
161 161
162#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR 162#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h
index b5c9d45c981f..1375cfc93960 100644
--- a/arch/x86/include/asm/timex.h
+++ b/arch/x86/include/asm/timex.h
@@ -4,9 +4,7 @@
4#include <asm/processor.h> 4#include <asm/processor.h>
5#include <asm/tsc.h> 5#include <asm/tsc.h>
6 6
7/* The PIT ticks at this frequency (in HZ): */ 7/* Assume we use the PIT time source for the clock tick */
8#define PIT_TICK_RATE 1193182
9
10#define CLOCK_TICK_RATE PIT_TICK_RATE 8#define CLOCK_TICK_RATE PIT_TICK_RATE
11 9
12#define ARCH_HAS_READ_CURRENT_TIMER 10#define ARCH_HAS_READ_CURRENT_TIMER
diff --git a/arch/x86/include/asm/xor.h b/arch/x86/include/asm/xor.h
index 11b3bb86e17b..7fcf6f3dbcc3 100644
--- a/arch/x86/include/asm/xor.h
+++ b/arch/x86/include/asm/xor.h
@@ -1,5 +1,10 @@
1#ifdef CONFIG_KMEMCHECK
2/* kmemcheck doesn't handle MMX/SSE/SSE2 instructions */
3# include <asm-generic/xor.h>
4#else
1#ifdef CONFIG_X86_32 5#ifdef CONFIG_X86_32
2# include "xor_32.h" 6# include "xor_32.h"
3#else 7#else
4# include "xor_64.h" 8# include "xor_64.h"
5#endif 9#endif
10#endif
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 3ffdcfa9abdf..9fa33886c0d7 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -487,7 +487,6 @@ out:
487static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c) 487static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
488{ 488{
489 char *v = c->x86_vendor_id; 489 char *v = c->x86_vendor_id;
490 static int printed;
491 int i; 490 int i;
492 491
493 for (i = 0; i < X86_VENDOR_NUM; i++) { 492 for (i = 0; i < X86_VENDOR_NUM; i++) {
@@ -504,13 +503,9 @@ static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
504 } 503 }
505 } 504 }
506 505
507 if (!printed) { 506 printk_once(KERN_ERR
508 printed++; 507 "CPU: vendor_id '%s' unknown, using generic init.\n" \
509 printk(KERN_ERR 508 "CPU: Your system may be unstable.\n", v);
510 "CPU: vendor_id '%s' unknown, using generic init.\n", v);
511
512 printk(KERN_ERR "CPU: Your system may be unstable.\n");
513 }
514 509
515 c->x86_vendor = X86_VENDOR_UNKNOWN; 510 c->x86_vendor = X86_VENDOR_UNKNOWN;
516 this_cpu = &default_cpu; 511 this_cpu = &default_cpu;
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index cf52215d9eb1..81cbe64ed6b4 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -1,3 +1,4 @@
1
1/* 2/*
2 * (c) 2003-2006 Advanced Micro Devices, Inc. 3 * (c) 2003-2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the 4 * Your use of this code is subject to the terms and conditions of the
@@ -117,20 +118,17 @@ static int query_current_values_with_pending_wait(struct powernow_k8_data *data)
117 u32 i = 0; 118 u32 i = 0;
118 119
119 if (cpu_family == CPU_HW_PSTATE) { 120 if (cpu_family == CPU_HW_PSTATE) {
120 if (data->currpstate == HW_PSTATE_INVALID) { 121 rdmsr(MSR_PSTATE_STATUS, lo, hi);
121 /* read (initial) hw pstate if not yet set */ 122 i = lo & HW_PSTATE_MASK;
122 rdmsr(MSR_PSTATE_STATUS, lo, hi); 123 data->currpstate = i;
123 i = lo & HW_PSTATE_MASK; 124
124 125 /*
125 /* 126 * a workaround for family 11h erratum 311 might cause
126 * a workaround for family 11h erratum 311 might cause 127 * an "out-of-range Pstate if the core is in Pstate-0
127 * an "out-of-range Pstate if the core is in Pstate-0 128 */
128 */ 129 if ((boot_cpu_data.x86 == 0x11) && (i >= data->numps))
129 if (i >= data->numps) 130 data->currpstate = HW_PSTATE_0;
130 data->currpstate = HW_PSTATE_0; 131
131 else
132 data->currpstate = i;
133 }
134 return 0; 132 return 0;
135 } 133 }
136 do { 134 do {
@@ -510,41 +508,34 @@ static int core_voltage_post_transition(struct powernow_k8_data *data,
510 return 0; 508 return 0;
511} 509}
512 510
513static int check_supported_cpu(unsigned int cpu) 511static void check_supported_cpu(void *_rc)
514{ 512{
515 cpumask_t oldmask;
516 u32 eax, ebx, ecx, edx; 513 u32 eax, ebx, ecx, edx;
517 unsigned int rc = 0; 514 int *rc = _rc;
518
519 oldmask = current->cpus_allowed;
520 set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
521 515
522 if (smp_processor_id() != cpu) { 516 *rc = -ENODEV;
523 printk(KERN_ERR PFX "limiting to cpu %u failed\n", cpu);
524 goto out;
525 }
526 517
527 if (current_cpu_data.x86_vendor != X86_VENDOR_AMD) 518 if (current_cpu_data.x86_vendor != X86_VENDOR_AMD)
528 goto out; 519 return;
529 520
530 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE); 521 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
531 if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) && 522 if (((eax & CPUID_XFAM) != CPUID_XFAM_K8) &&
532 ((eax & CPUID_XFAM) < CPUID_XFAM_10H)) 523 ((eax & CPUID_XFAM) < CPUID_XFAM_10H))
533 goto out; 524 return;
534 525
535 if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { 526 if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) {
536 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || 527 if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) ||
537 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) { 528 ((eax & CPUID_XMOD) > CPUID_XMOD_REV_MASK)) {
538 printk(KERN_INFO PFX 529 printk(KERN_INFO PFX
539 "Processor cpuid %x not supported\n", eax); 530 "Processor cpuid %x not supported\n", eax);
540 goto out; 531 return;
541 } 532 }
542 533
543 eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES); 534 eax = cpuid_eax(CPUID_GET_MAX_CAPABILITIES);
544 if (eax < CPUID_FREQ_VOLT_CAPABILITIES) { 535 if (eax < CPUID_FREQ_VOLT_CAPABILITIES) {
545 printk(KERN_INFO PFX 536 printk(KERN_INFO PFX
546 "No frequency change capabilities detected\n"); 537 "No frequency change capabilities detected\n");
547 goto out; 538 return;
548 } 539 }
549 540
550 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); 541 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
@@ -552,21 +543,17 @@ static int check_supported_cpu(unsigned int cpu)
552 != P_STATE_TRANSITION_CAPABLE) { 543 != P_STATE_TRANSITION_CAPABLE) {
553 printk(KERN_INFO PFX 544 printk(KERN_INFO PFX
554 "Power state transitions not supported\n"); 545 "Power state transitions not supported\n");
555 goto out; 546 return;
556 } 547 }
557 } else { /* must be a HW Pstate capable processor */ 548 } else { /* must be a HW Pstate capable processor */
558 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx); 549 cpuid(CPUID_FREQ_VOLT_CAPABILITIES, &eax, &ebx, &ecx, &edx);
559 if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE) 550 if ((edx & USE_HW_PSTATE) == USE_HW_PSTATE)
560 cpu_family = CPU_HW_PSTATE; 551 cpu_family = CPU_HW_PSTATE;
561 else 552 else
562 goto out; 553 return;
563 } 554 }
564 555
565 rc = 1; 556 *rc = 0;
566
567out:
568 set_cpus_allowed_ptr(current, &oldmask);
569 return rc;
570} 557}
571 558
572static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst, 559static int check_pst_table(struct powernow_k8_data *data, struct pst_s *pst,
@@ -823,13 +810,14 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data,
823 if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE)) 810 if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE))
824 return; 811 return;
825 812
826 control = data->acpi_data.states[index].control; data->irt = (control 813 control = data->acpi_data.states[index].control;
827 >> IRT_SHIFT) & IRT_MASK; data->rvo = (control >> 814 data->irt = (control >> IRT_SHIFT) & IRT_MASK;
828 RVO_SHIFT) & RVO_MASK; data->exttype = (control 815 data->rvo = (control >> RVO_SHIFT) & RVO_MASK;
829 >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK; 816 data->exttype = (control >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK;
830 data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK; data->vidmvs = 1 817 data->plllock = (control >> PLL_L_SHIFT) & PLL_L_MASK;
831 << ((control >> MVS_SHIFT) & MVS_MASK); data->vstable = 818 data->vidmvs = 1 << ((control >> MVS_SHIFT) & MVS_MASK);
832 (control >> VST_SHIFT) & VST_MASK; } 819 data->vstable = (control >> VST_SHIFT) & VST_MASK;
820}
833 821
834static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) 822static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
835{ 823{
@@ -1046,6 +1034,19 @@ static int get_transition_latency(struct powernow_k8_data *data)
1046 if (cur_latency > max_latency) 1034 if (cur_latency > max_latency)
1047 max_latency = cur_latency; 1035 max_latency = cur_latency;
1048 } 1036 }
1037 if (max_latency == 0) {
1038 /*
1039 * Fam 11h always returns 0 as transition latency.
1040 * This is intended and means "very fast". While cpufreq core
1041 * and governors currently can handle that gracefully, better
1042 * set it to 1 to avoid problems in the future.
1043 * For all others it's a BIOS bug.
1044 */
1045 if (!boot_cpu_data.x86 == 0x11)
1046 printk(KERN_ERR FW_WARN PFX "Invalid zero transition "
1047 "latency\n");
1048 max_latency = 1;
1049 }
1049 /* value in usecs, needs to be in nanoseconds */ 1050 /* value in usecs, needs to be in nanoseconds */
1050 return 1000 * max_latency; 1051 return 1000 * max_latency;
1051} 1052}
@@ -1093,7 +1094,7 @@ static int transition_frequency_fidvid(struct powernow_k8_data *data,
1093 freqs.old = find_khz_freq_from_fid(data->currfid); 1094 freqs.old = find_khz_freq_from_fid(data->currfid);
1094 freqs.new = find_khz_freq_from_fid(fid); 1095 freqs.new = find_khz_freq_from_fid(fid);
1095 1096
1096 for_each_cpu_mask_nr(i, *(data->available_cores)) { 1097 for_each_cpu(i, data->available_cores) {
1097 freqs.cpu = i; 1098 freqs.cpu = i;
1098 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 1099 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
1099 } 1100 }
@@ -1101,7 +1102,7 @@ static int transition_frequency_fidvid(struct powernow_k8_data *data,
1101 res = transition_fid_vid(data, fid, vid); 1102 res = transition_fid_vid(data, fid, vid);
1102 freqs.new = find_khz_freq_from_fid(data->currfid); 1103 freqs.new = find_khz_freq_from_fid(data->currfid);
1103 1104
1104 for_each_cpu_mask_nr(i, *(data->available_cores)) { 1105 for_each_cpu(i, data->available_cores) {
1105 freqs.cpu = i; 1106 freqs.cpu = i;
1106 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 1107 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
1107 } 1108 }
@@ -1126,7 +1127,7 @@ static int transition_frequency_pstate(struct powernow_k8_data *data,
1126 data->currpstate); 1127 data->currpstate);
1127 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); 1128 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate);
1128 1129
1129 for_each_cpu_mask_nr(i, *(data->available_cores)) { 1130 for_each_cpu(i, data->available_cores) {
1130 freqs.cpu = i; 1131 freqs.cpu = i;
1131 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 1132 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
1132 } 1133 }
@@ -1134,7 +1135,7 @@ static int transition_frequency_pstate(struct powernow_k8_data *data,
1134 res = transition_pstate(data, pstate); 1135 res = transition_pstate(data, pstate);
1135 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate); 1136 freqs.new = find_khz_freq_from_pstate(data->powernow_table, pstate);
1136 1137
1137 for_each_cpu_mask_nr(i, *(data->available_cores)) { 1138 for_each_cpu(i, data->available_cores) {
1138 freqs.cpu = i; 1139 freqs.cpu = i;
1139 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 1140 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
1140 } 1141 }
@@ -1235,21 +1236,47 @@ static int powernowk8_verify(struct cpufreq_policy *pol)
1235 return cpufreq_frequency_table_verify(pol, data->powernow_table); 1236 return cpufreq_frequency_table_verify(pol, data->powernow_table);
1236} 1237}
1237 1238
1238static const char ACPI_PSS_BIOS_BUG_MSG[] = 1239struct init_on_cpu {
1239 KERN_ERR FW_BUG PFX "No compatible ACPI _PSS objects found.\n" 1240 struct powernow_k8_data *data;
1240 KERN_ERR FW_BUG PFX "Try again with latest BIOS.\n"; 1241 int rc;
1242};
1243
1244static void __cpuinit powernowk8_cpu_init_on_cpu(void *_init_on_cpu)
1245{
1246 struct init_on_cpu *init_on_cpu = _init_on_cpu;
1247
1248 if (pending_bit_stuck()) {
1249 printk(KERN_ERR PFX "failing init, change pending bit set\n");
1250 init_on_cpu->rc = -ENODEV;
1251 return;
1252 }
1253
1254 if (query_current_values_with_pending_wait(init_on_cpu->data)) {
1255 init_on_cpu->rc = -ENODEV;
1256 return;
1257 }
1258
1259 if (cpu_family == CPU_OPTERON)
1260 fidvid_msr_init();
1261
1262 init_on_cpu->rc = 0;
1263}
1241 1264
1242/* per CPU init entry point to the driver */ 1265/* per CPU init entry point to the driver */
1243static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol) 1266static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1244{ 1267{
1268 static const char ACPI_PSS_BIOS_BUG_MSG[] =
1269 KERN_ERR FW_BUG PFX "No compatible ACPI _PSS objects found.\n"
1270 KERN_ERR FW_BUG PFX "Try again with latest BIOS.\n";
1245 struct powernow_k8_data *data; 1271 struct powernow_k8_data *data;
1246 cpumask_t oldmask; 1272 struct init_on_cpu init_on_cpu;
1247 int rc; 1273 int rc;
1248 1274
1249 if (!cpu_online(pol->cpu)) 1275 if (!cpu_online(pol->cpu))
1250 return -ENODEV; 1276 return -ENODEV;
1251 1277
1252 if (!check_supported_cpu(pol->cpu)) 1278 smp_call_function_single(pol->cpu, check_supported_cpu, &rc, 1);
1279 if (rc)
1253 return -ENODEV; 1280 return -ENODEV;
1254 1281
1255 data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL); 1282 data = kzalloc(sizeof(struct powernow_k8_data), GFP_KERNEL);
@@ -1289,27 +1316,12 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1289 pol->cpuinfo.transition_latency = get_transition_latency(data); 1316 pol->cpuinfo.transition_latency = get_transition_latency(data);
1290 1317
1291 /* only run on specific CPU from here on */ 1318 /* only run on specific CPU from here on */
1292 oldmask = current->cpus_allowed; 1319 init_on_cpu.data = data;
1293 set_cpus_allowed_ptr(current, &cpumask_of_cpu(pol->cpu)); 1320 smp_call_function_single(data->cpu, powernowk8_cpu_init_on_cpu,
1294 1321 &init_on_cpu, 1);
1295 if (smp_processor_id() != pol->cpu) { 1322 rc = init_on_cpu.rc;
1296 printk(KERN_ERR PFX "limiting to cpu %u failed\n", pol->cpu); 1323 if (rc != 0)
1297 goto err_out_unmask; 1324 goto err_out_exit_acpi;
1298 }
1299
1300 if (pending_bit_stuck()) {
1301 printk(KERN_ERR PFX "failing init, change pending bit set\n");
1302 goto err_out_unmask;
1303 }
1304
1305 if (query_current_values_with_pending_wait(data))
1306 goto err_out_unmask;
1307
1308 if (cpu_family == CPU_OPTERON)
1309 fidvid_msr_init();
1310
1311 /* run on any CPU again */
1312 set_cpus_allowed_ptr(current, &oldmask);
1313 1325
1314 if (cpu_family == CPU_HW_PSTATE) 1326 if (cpu_family == CPU_HW_PSTATE)
1315 cpumask_copy(pol->cpus, cpumask_of(pol->cpu)); 1327 cpumask_copy(pol->cpus, cpumask_of(pol->cpu));
@@ -1346,8 +1358,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1346 1358
1347 return 0; 1359 return 0;
1348 1360
1349err_out_unmask: 1361err_out_exit_acpi:
1350 set_cpus_allowed_ptr(current, &oldmask);
1351 powernow_k8_cpu_exit_acpi(data); 1362 powernow_k8_cpu_exit_acpi(data);
1352 1363
1353err_out: 1364err_out:
@@ -1372,28 +1383,25 @@ static int __devexit powernowk8_cpu_exit(struct cpufreq_policy *pol)
1372 return 0; 1383 return 0;
1373} 1384}
1374 1385
1386static void query_values_on_cpu(void *_err)
1387{
1388 int *err = _err;
1389 struct powernow_k8_data *data = __get_cpu_var(powernow_data);
1390
1391 *err = query_current_values_with_pending_wait(data);
1392}
1393
1375static unsigned int powernowk8_get(unsigned int cpu) 1394static unsigned int powernowk8_get(unsigned int cpu)
1376{ 1395{
1377 struct powernow_k8_data *data; 1396 struct powernow_k8_data *data = per_cpu(powernow_data, cpu);
1378 cpumask_t oldmask = current->cpus_allowed;
1379 unsigned int khz = 0; 1397 unsigned int khz = 0;
1380 unsigned int first; 1398 int err;
1381
1382 first = cpumask_first(cpu_core_mask(cpu));
1383 data = per_cpu(powernow_data, first);
1384 1399
1385 if (!data) 1400 if (!data)
1386 return -EINVAL; 1401 return -EINVAL;
1387 1402
1388 set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu)); 1403 smp_call_function_single(cpu, query_values_on_cpu, &err, true);
1389 if (smp_processor_id() != cpu) { 1404 if (err)
1390 printk(KERN_ERR PFX
1391 "limiting to CPU %d failed in powernowk8_get\n", cpu);
1392 set_cpus_allowed_ptr(current, &oldmask);
1393 return 0;
1394 }
1395
1396 if (query_current_values_with_pending_wait(data))
1397 goto out; 1405 goto out;
1398 1406
1399 if (cpu_family == CPU_HW_PSTATE) 1407 if (cpu_family == CPU_HW_PSTATE)
@@ -1404,7 +1412,6 @@ static unsigned int powernowk8_get(unsigned int cpu)
1404 1412
1405 1413
1406out: 1414out:
1407 set_cpus_allowed_ptr(current, &oldmask);
1408 return khz; 1415 return khz;
1409} 1416}
1410 1417
@@ -1430,7 +1437,9 @@ static int __cpuinit powernowk8_init(void)
1430 unsigned int i, supported_cpus = 0; 1437 unsigned int i, supported_cpus = 0;
1431 1438
1432 for_each_online_cpu(i) { 1439 for_each_online_cpu(i) {
1433 if (check_supported_cpu(i)) 1440 int rc;
1441 smp_call_function_single(i, check_supported_cpu, &rc, 1);
1442 if (rc == 0)
1434 supported_cpus++; 1443 supported_cpus++;
1435 } 1444 }
1436 1445
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
index 6c6698feade1..c9c1190b5e1f 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.h
@@ -223,14 +223,3 @@ static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned
223 223
224static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 224static int fill_powernow_table_pstate(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
225static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table); 225static int fill_powernow_table_fidvid(struct powernow_k8_data *data, struct cpufreq_frequency_table *powernow_table);
226
227#ifdef CONFIG_SMP
228static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
229{
230}
231#else
232static inline void define_siblings(int cpu, cpumask_t cpu_sharedcore_mask[])
233{
234 cpu_set(0, cpu_sharedcore_mask[0]);
235}
236#endif
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
index 55c831ed71ce..8d672ef162ce 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-centrino.c
@@ -323,14 +323,8 @@ static unsigned int get_cur_freq(unsigned int cpu)
323{ 323{
324 unsigned l, h; 324 unsigned l, h;
325 unsigned clock_freq; 325 unsigned clock_freq;
326 cpumask_t saved_mask;
327 326
328 saved_mask = current->cpus_allowed; 327 rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
329 set_cpus_allowed_ptr(current, &cpumask_of_cpu(cpu));
330 if (smp_processor_id() != cpu)
331 return 0;
332
333 rdmsr(MSR_IA32_PERF_STATUS, l, h);
334 clock_freq = extract_clock(l, cpu, 0); 328 clock_freq = extract_clock(l, cpu, 0);
335 329
336 if (unlikely(clock_freq == 0)) { 330 if (unlikely(clock_freq == 0)) {
@@ -340,11 +334,9 @@ static unsigned int get_cur_freq(unsigned int cpu)
340 * P-state transition (like TM2). Get the last freq set 334 * P-state transition (like TM2). Get the last freq set
341 * in PERF_CTL. 335 * in PERF_CTL.
342 */ 336 */
343 rdmsr(MSR_IA32_PERF_CTL, l, h); 337 rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
344 clock_freq = extract_clock(l, cpu, 1); 338 clock_freq = extract_clock(l, cpu, 1);
345 } 339 }
346
347 set_cpus_allowed_ptr(current, &saved_mask);
348 return clock_freq; 340 return clock_freq;
349} 341}
350 342
@@ -467,15 +459,10 @@ static int centrino_target (struct cpufreq_policy *policy,
467 struct cpufreq_freqs freqs; 459 struct cpufreq_freqs freqs;
468 int retval = 0; 460 int retval = 0;
469 unsigned int j, k, first_cpu, tmp; 461 unsigned int j, k, first_cpu, tmp;
470 cpumask_var_t saved_mask, covered_cpus; 462 cpumask_var_t covered_cpus;
471 463
472 if (unlikely(!alloc_cpumask_var(&saved_mask, GFP_KERNEL))) 464 if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
473 return -ENOMEM;
474 if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL))) {
475 free_cpumask_var(saved_mask);
476 return -ENOMEM; 465 return -ENOMEM;
477 }
478 cpumask_copy(saved_mask, &current->cpus_allowed);
479 466
480 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) { 467 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
481 retval = -ENODEV; 468 retval = -ENODEV;
@@ -493,7 +480,7 @@ static int centrino_target (struct cpufreq_policy *policy,
493 480
494 first_cpu = 1; 481 first_cpu = 1;
495 for_each_cpu(j, policy->cpus) { 482 for_each_cpu(j, policy->cpus) {
496 const struct cpumask *mask; 483 int good_cpu;
497 484
498 /* cpufreq holds the hotplug lock, so we are safe here */ 485 /* cpufreq holds the hotplug lock, so we are safe here */
499 if (!cpu_online(j)) 486 if (!cpu_online(j))
@@ -504,32 +491,30 @@ static int centrino_target (struct cpufreq_policy *policy,
504 * Make sure we are running on CPU that wants to change freq 491 * Make sure we are running on CPU that wants to change freq
505 */ 492 */
506 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) 493 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
507 mask = policy->cpus; 494 good_cpu = cpumask_any_and(policy->cpus,
495 cpu_online_mask);
508 else 496 else
509 mask = cpumask_of(j); 497 good_cpu = j;
510 498
511 set_cpus_allowed_ptr(current, mask); 499 if (good_cpu >= nr_cpu_ids) {
512 preempt_disable();
513 if (unlikely(!cpu_isset(smp_processor_id(), *mask))) {
514 dprintk("couldn't limit to CPUs in this domain\n"); 500 dprintk("couldn't limit to CPUs in this domain\n");
515 retval = -EAGAIN; 501 retval = -EAGAIN;
516 if (first_cpu) { 502 if (first_cpu) {
517 /* We haven't started the transition yet. */ 503 /* We haven't started the transition yet. */
518 goto migrate_end; 504 goto out;
519 } 505 }
520 preempt_enable();
521 break; 506 break;
522 } 507 }
523 508
524 msr = per_cpu(centrino_model, cpu)->op_points[newstate].index; 509 msr = per_cpu(centrino_model, cpu)->op_points[newstate].index;
525 510
526 if (first_cpu) { 511 if (first_cpu) {
527 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h); 512 rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
528 if (msr == (oldmsr & 0xffff)) { 513 if (msr == (oldmsr & 0xffff)) {
529 dprintk("no change needed - msr was and needs " 514 dprintk("no change needed - msr was and needs "
530 "to be %x\n", oldmsr); 515 "to be %x\n", oldmsr);
531 retval = 0; 516 retval = 0;
532 goto migrate_end; 517 goto out;
533 } 518 }
534 519
535 freqs.old = extract_clock(oldmsr, cpu, 0); 520 freqs.old = extract_clock(oldmsr, cpu, 0);
@@ -553,14 +538,11 @@ static int centrino_target (struct cpufreq_policy *policy,
553 oldmsr |= msr; 538 oldmsr |= msr;
554 } 539 }
555 540
556 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h); 541 wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
557 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY) { 542 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
558 preempt_enable();
559 break; 543 break;
560 }
561 544
562 cpu_set(j, *covered_cpus); 545 cpumask_set_cpu(j, covered_cpus);
563 preempt_enable();
564 } 546 }
565 547
566 for_each_cpu(k, policy->cpus) { 548 for_each_cpu(k, policy->cpus) {
@@ -578,10 +560,8 @@ static int centrino_target (struct cpufreq_policy *policy,
578 * Best effort undo.. 560 * Best effort undo..
579 */ 561 */
580 562
581 for_each_cpu_mask_nr(j, *covered_cpus) { 563 for_each_cpu(j, covered_cpus)
582 set_cpus_allowed_ptr(current, &cpumask_of_cpu(j)); 564 wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
583 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
584 }
585 565
586 tmp = freqs.new; 566 tmp = freqs.new;
587 freqs.new = freqs.old; 567 freqs.new = freqs.old;
@@ -593,15 +573,9 @@ static int centrino_target (struct cpufreq_policy *policy,
593 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 573 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
594 } 574 }
595 } 575 }
596 set_cpus_allowed_ptr(current, saved_mask);
597 retval = 0; 576 retval = 0;
598 goto out;
599 577
600migrate_end:
601 preempt_enable();
602 set_cpus_allowed_ptr(current, saved_mask);
603out: 578out:
604 free_cpumask_var(saved_mask);
605 free_cpumask_var(covered_cpus); 579 free_cpumask_var(covered_cpus);
606 return retval; 580 return retval;
607} 581}
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
index 016c1a4fa3fc..6911e91fb4f6 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-ich.c
@@ -89,7 +89,8 @@ static int speedstep_find_register(void)
89 * speedstep_set_state - set the SpeedStep state 89 * speedstep_set_state - set the SpeedStep state
90 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH) 90 * @state: new processor frequency state (SPEEDSTEP_LOW or SPEEDSTEP_HIGH)
91 * 91 *
92 * Tries to change the SpeedStep state. 92 * Tries to change the SpeedStep state. Can be called from
93 * smp_call_function_single.
93 */ 94 */
94static void speedstep_set_state(unsigned int state) 95static void speedstep_set_state(unsigned int state)
95{ 96{
@@ -143,6 +144,11 @@ static void speedstep_set_state(unsigned int state)
143 return; 144 return;
144} 145}
145 146
147/* Wrapper for smp_call_function_single. */
148static void _speedstep_set_state(void *_state)
149{
150 speedstep_set_state(*(unsigned int *)_state);
151}
146 152
147/** 153/**
148 * speedstep_activate - activate SpeedStep control in the chipset 154 * speedstep_activate - activate SpeedStep control in the chipset
@@ -226,22 +232,28 @@ static unsigned int speedstep_detect_chipset(void)
226 return 0; 232 return 0;
227} 233}
228 234
229static unsigned int _speedstep_get(const struct cpumask *cpus) 235struct get_freq_data {
230{
231 unsigned int speed; 236 unsigned int speed;
232 cpumask_t cpus_allowed; 237 unsigned int processor;
233 238};
234 cpus_allowed = current->cpus_allowed; 239
235 set_cpus_allowed_ptr(current, cpus); 240static void get_freq_data(void *_data)
236 speed = speedstep_get_frequency(speedstep_processor); 241{
237 set_cpus_allowed_ptr(current, &cpus_allowed); 242 struct get_freq_data *data = _data;
238 dprintk("detected %u kHz as current frequency\n", speed); 243
239 return speed; 244 data->speed = speedstep_get_frequency(data->processor);
240} 245}
241 246
242static unsigned int speedstep_get(unsigned int cpu) 247static unsigned int speedstep_get(unsigned int cpu)
243{ 248{
244 return _speedstep_get(cpumask_of(cpu)); 249 struct get_freq_data data = { .processor = cpu };
250
251 /* You're supposed to ensure CPU is online. */
252 if (smp_call_function_single(cpu, get_freq_data, &data, 1) != 0)
253 BUG();
254
255 dprintk("detected %u kHz as current frequency\n", data.speed);
256 return data.speed;
245} 257}
246 258
247/** 259/**
@@ -257,16 +269,16 @@ static int speedstep_target(struct cpufreq_policy *policy,
257 unsigned int target_freq, 269 unsigned int target_freq,
258 unsigned int relation) 270 unsigned int relation)
259{ 271{
260 unsigned int newstate = 0; 272 unsigned int newstate = 0, policy_cpu;
261 struct cpufreq_freqs freqs; 273 struct cpufreq_freqs freqs;
262 cpumask_t cpus_allowed;
263 int i; 274 int i;
264 275
265 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0], 276 if (cpufreq_frequency_table_target(policy, &speedstep_freqs[0],
266 target_freq, relation, &newstate)) 277 target_freq, relation, &newstate))
267 return -EINVAL; 278 return -EINVAL;
268 279
269 freqs.old = _speedstep_get(policy->cpus); 280 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
281 freqs.old = speedstep_get(policy_cpu);
270 freqs.new = speedstep_freqs[newstate].frequency; 282 freqs.new = speedstep_freqs[newstate].frequency;
271 freqs.cpu = policy->cpu; 283 freqs.cpu = policy->cpu;
272 284
@@ -276,20 +288,13 @@ static int speedstep_target(struct cpufreq_policy *policy,
276 if (freqs.old == freqs.new) 288 if (freqs.old == freqs.new)
277 return 0; 289 return 0;
278 290
279 cpus_allowed = current->cpus_allowed;
280
281 for_each_cpu(i, policy->cpus) { 291 for_each_cpu(i, policy->cpus) {
282 freqs.cpu = i; 292 freqs.cpu = i;
283 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 293 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
284 } 294 }
285 295
286 /* switch to physical CPU where state is to be changed */ 296 smp_call_function_single(policy_cpu, _speedstep_set_state, &newstate,
287 set_cpus_allowed_ptr(current, policy->cpus); 297 true);
288
289 speedstep_set_state(newstate);
290
291 /* allow to be run on all CPUs */
292 set_cpus_allowed_ptr(current, &cpus_allowed);
293 298
294 for_each_cpu(i, policy->cpus) { 299 for_each_cpu(i, policy->cpus) {
295 freqs.cpu = i; 300 freqs.cpu = i;
@@ -312,33 +317,43 @@ static int speedstep_verify(struct cpufreq_policy *policy)
312 return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]); 317 return cpufreq_frequency_table_verify(policy, &speedstep_freqs[0]);
313} 318}
314 319
320struct get_freqs {
321 struct cpufreq_policy *policy;
322 int ret;
323};
324
325static void get_freqs_on_cpu(void *_get_freqs)
326{
327 struct get_freqs *get_freqs = _get_freqs;
328
329 get_freqs->ret =
330 speedstep_get_freqs(speedstep_processor,
331 &speedstep_freqs[SPEEDSTEP_LOW].frequency,
332 &speedstep_freqs[SPEEDSTEP_HIGH].frequency,
333 &get_freqs->policy->cpuinfo.transition_latency,
334 &speedstep_set_state);
335}
315 336
316static int speedstep_cpu_init(struct cpufreq_policy *policy) 337static int speedstep_cpu_init(struct cpufreq_policy *policy)
317{ 338{
318 int result = 0; 339 int result;
319 unsigned int speed; 340 unsigned int policy_cpu, speed;
320 cpumask_t cpus_allowed; 341 struct get_freqs gf;
321 342
322 /* only run on CPU to be set, or on its sibling */ 343 /* only run on CPU to be set, or on its sibling */
323#ifdef CONFIG_SMP 344#ifdef CONFIG_SMP
324 cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu)); 345 cpumask_copy(policy->cpus, cpu_sibling_mask(policy->cpu));
325#endif 346#endif
326 347 policy_cpu = cpumask_any_and(policy->cpus, cpu_online_mask);
327 cpus_allowed = current->cpus_allowed;
328 set_cpus_allowed_ptr(current, policy->cpus);
329 348
330 /* detect low and high frequency and transition latency */ 349 /* detect low and high frequency and transition latency */
331 result = speedstep_get_freqs(speedstep_processor, 350 gf.policy = policy;
332 &speedstep_freqs[SPEEDSTEP_LOW].frequency, 351 smp_call_function_single(policy_cpu, get_freqs_on_cpu, &gf, 1);
333 &speedstep_freqs[SPEEDSTEP_HIGH].frequency, 352 if (gf.ret)
334 &policy->cpuinfo.transition_latency, 353 return gf.ret;
335 &speedstep_set_state);
336 set_cpus_allowed_ptr(current, &cpus_allowed);
337 if (result)
338 return result;
339 354
340 /* get current speed setting */ 355 /* get current speed setting */
341 speed = _speedstep_get(policy->cpus); 356 speed = speedstep_get(policy_cpu);
342 if (!speed) 357 if (!speed)
343 return -EIO; 358 return -EIO;
344 359
diff --git a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
index 2e3c6862657b..f4c290b8482f 100644
--- a/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
+++ b/arch/x86/kernel/cpu/cpufreq/speedstep-lib.c
@@ -226,6 +226,7 @@ static unsigned int pentium4_get_frequency(void)
226} 226}
227 227
228 228
229/* Warning: may get called from smp_call_function_single. */
229unsigned int speedstep_get_frequency(unsigned int processor) 230unsigned int speedstep_get_frequency(unsigned int processor)
230{ 231{
231 switch (processor) { 232 switch (processor) {
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index daed39ba2614..3260ab044996 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -86,6 +86,29 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
86 */ 86 */
87 if (c->x86 == 6 && c->x86_model < 15) 87 if (c->x86 == 6 && c->x86_model < 15)
88 clear_cpu_cap(c, X86_FEATURE_PAT); 88 clear_cpu_cap(c, X86_FEATURE_PAT);
89
90#ifdef CONFIG_KMEMCHECK
91 /*
92 * P4s have a "fast strings" feature which causes single-
93 * stepping REP instructions to only generate a #DB on
94 * cache-line boundaries.
95 *
96 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
97 * (model 2) with the same problem.
98 */
99 if (c->x86 == 15) {
100 u64 misc_enable;
101
102 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
103
104 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
105 printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
106
107 misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
108 wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
109 }
110 }
111#endif
89} 112}
90 113
91#ifdef CONFIG_X86_32 114#ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c
index 2ac1f0c2beb3..b07af8861244 100644
--- a/arch/x86/kernel/cpuid.c
+++ b/arch/x86/kernel/cpuid.c
@@ -182,6 +182,11 @@ static struct notifier_block __refdata cpuid_class_cpu_notifier =
182 .notifier_call = cpuid_class_cpu_callback, 182 .notifier_call = cpuid_class_cpu_callback,
183}; 183};
184 184
185static char *cpuid_nodename(struct device *dev)
186{
187 return kasprintf(GFP_KERNEL, "cpu/%u/cpuid", MINOR(dev->devt));
188}
189
185static int __init cpuid_init(void) 190static int __init cpuid_init(void)
186{ 191{
187 int i, err = 0; 192 int i, err = 0;
@@ -198,6 +203,7 @@ static int __init cpuid_init(void)
198 err = PTR_ERR(cpuid_class); 203 err = PTR_ERR(cpuid_class);
199 goto out_chrdev; 204 goto out_chrdev;
200 } 205 }
206 cpuid_class->nodename = cpuid_nodename;
201 for_each_online_cpu(i) { 207 for_each_online_cpu(i) {
202 err = cpuid_device_create(i); 208 err = cpuid_device_create(i);
203 if (err != 0) 209 if (err != 0)
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index c2e0bb0890d4..5cf36c053ac4 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -7,6 +7,7 @@
7#include <linux/spinlock.h> 7#include <linux/spinlock.h>
8#include <linux/jiffies.h> 8#include <linux/jiffies.h>
9#include <linux/module.h> 9#include <linux/module.h>
10#include <linux/timex.h>
10#include <linux/delay.h> 11#include <linux/delay.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/io.h> 13#include <linux/io.h>
diff --git a/arch/x86/kernel/init_task.c b/arch/x86/kernel/init_task.c
index df3bf269beab..270ff83efc11 100644
--- a/arch/x86/kernel/init_task.c
+++ b/arch/x86/kernel/init_task.c
@@ -12,7 +12,6 @@
12 12
13static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 13static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
14static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 14static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
15struct mm_struct init_mm = INIT_MM(init_mm);
16 15
17/* 16/*
18 * Initial thread structure. 17 * Initial thread structure.
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 9c4461501fcb..9371448290ac 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -236,6 +236,7 @@ static const struct file_operations microcode_fops = {
236static struct miscdevice microcode_dev = { 236static struct miscdevice microcode_dev = {
237 .minor = MICROCODE_MINOR, 237 .minor = MICROCODE_MINOR,
238 .name = "microcode", 238 .name = "microcode",
239 .devnode = "cpu/microcode",
239 .fops = &microcode_fops, 240 .fops = &microcode_fops,
240}; 241};
241 242
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 3cf3413ec626..98fd6cd4e3a4 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -196,6 +196,11 @@ static struct notifier_block __refdata msr_class_cpu_notifier = {
196 .notifier_call = msr_class_cpu_callback, 196 .notifier_call = msr_class_cpu_callback,
197}; 197};
198 198
199static char *msr_nodename(struct device *dev)
200{
201 return kasprintf(GFP_KERNEL, "cpu/%u/msr", MINOR(dev->devt));
202}
203
199static int __init msr_init(void) 204static int __init msr_init(void)
200{ 205{
201 int i, err = 0; 206 int i, err = 0;
@@ -212,6 +217,7 @@ static int __init msr_init(void)
212 err = PTR_ERR(msr_class); 217 err = PTR_ERR(msr_class);
213 goto out_chrdev; 218 goto out_chrdev;
214 } 219 }
220 msr_class->nodename = msr_nodename;
215 for_each_online_cpu(i) { 221 for_each_online_cpu(i) {
216 err = msr_device_create(i); 222 err = msr_device_create(i);
217 if (err != 0) 223 if (err != 0)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 3bb2be1649bd..994dd6a4a2a0 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -63,7 +63,7 @@ void arch_task_cache_init(void)
63 task_xstate_cachep = 63 task_xstate_cachep =
64 kmem_cache_create("task_xstate", xstate_size, 64 kmem_cache_create("task_xstate", xstate_size,
65 __alignof__(union thread_xstate), 65 __alignof__(union thread_xstate),
66 SLAB_PANIC, NULL); 66 SLAB_PANIC | SLAB_NOTRACK, NULL);
67} 67}
68 68
69/* 69/*
diff --git a/arch/x86/kernel/stacktrace.c b/arch/x86/kernel/stacktrace.c
index 4aaf7e48394f..c3eb207181fe 100644
--- a/arch/x86/kernel/stacktrace.c
+++ b/arch/x86/kernel/stacktrace.c
@@ -77,6 +77,13 @@ void save_stack_trace(struct stack_trace *trace)
77} 77}
78EXPORT_SYMBOL_GPL(save_stack_trace); 78EXPORT_SYMBOL_GPL(save_stack_trace);
79 79
80void save_stack_trace_bp(struct stack_trace *trace, unsigned long bp)
81{
82 dump_trace(current, NULL, NULL, bp, &save_stack_ops, trace);
83 if (trace->nr_entries < trace->max_entries)
84 trace->entries[trace->nr_entries++] = ULONG_MAX;
85}
86
80void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) 87void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
81{ 88{
82 dump_trace(tsk, NULL, NULL, 0, &save_stack_ops_nosched, trace); 89 dump_trace(tsk, NULL, NULL, 0, &save_stack_ops_nosched, trace);
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 1e1e27b7d438..5f935f0d5861 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -45,6 +45,7 @@
45#include <linux/edac.h> 45#include <linux/edac.h>
46#endif 46#endif
47 47
48#include <asm/kmemcheck.h>
48#include <asm/stacktrace.h> 49#include <asm/stacktrace.h>
49#include <asm/processor.h> 50#include <asm/processor.h>
50#include <asm/debugreg.h> 51#include <asm/debugreg.h>
@@ -534,6 +535,10 @@ dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code)
534 535
535 get_debugreg(condition, 6); 536 get_debugreg(condition, 6);
536 537
538 /* Catch kmemcheck conditions first of all! */
539 if (condition & DR_STEP && kmemcheck_trap(regs))
540 return;
541
537 /* 542 /*
538 * The processor cleared BTF, so don't mark that we need it set. 543 * The processor cleared BTF, so don't mark that we need it set.
539 */ 544 */
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 3e1c057e98fe..b0597ad02c93 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -9,6 +9,7 @@
9#include <linux/delay.h> 9#include <linux/delay.h>
10#include <linux/clocksource.h> 10#include <linux/clocksource.h>
11#include <linux/percpu.h> 11#include <linux/percpu.h>
12#include <linux/timex.h>
12 13
13#include <asm/hpet.h> 14#include <asm/hpet.h>
14#include <asm/timer.h> 15#include <asm/timer.h>
@@ -631,17 +632,15 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
631 void *data) 632 void *data)
632{ 633{
633 struct cpufreq_freqs *freq = data; 634 struct cpufreq_freqs *freq = data;
634 unsigned long *lpj, dummy; 635 unsigned long *lpj;
635 636
636 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) 637 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
637 return 0; 638 return 0;
638 639
639 lpj = &dummy; 640 lpj = &boot_cpu_data.loops_per_jiffy;
640 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
641#ifdef CONFIG_SMP 641#ifdef CONFIG_SMP
642 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
642 lpj = &cpu_data(freq->cpu).loops_per_jiffy; 643 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
643#else
644 lpj = &boot_cpu_data.loops_per_jiffy;
645#endif 644#endif
646 645
647 if (!ref_freq) { 646 if (!ref_freq) {
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 32d6ae8fb60e..e770bf349ec4 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -1277,7 +1277,7 @@ static struct vmcs *alloc_vmcs_cpu(int cpu)
1277 struct page *pages; 1277 struct page *pages;
1278 struct vmcs *vmcs; 1278 struct vmcs *vmcs;
1279 1279
1280 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); 1280 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1281 if (!pages) 1281 if (!pages)
1282 return NULL; 1282 return NULL;
1283 vmcs = page_address(pages); 1283 vmcs = page_address(pages);
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index fdd30d08ab52..eefdeee8a871 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_X86_PTDUMP) += dump_pagetables.o
10 10
11obj-$(CONFIG_HIGHMEM) += highmem_32.o 11obj-$(CONFIG_HIGHMEM) += highmem_32.o
12 12
13obj-$(CONFIG_KMEMCHECK) += kmemcheck/
14
13obj-$(CONFIG_MMIOTRACE) += mmiotrace.o 15obj-$(CONFIG_MMIOTRACE) += mmiotrace.o
14mmiotrace-y := kmmio.o pf_in.o mmio-mod.o 16mmiotrace-y := kmmio.o pf_in.o mmio-mod.o
15obj-$(CONFIG_MMIOTRACE_TEST) += testmmiotrace.o 17obj-$(CONFIG_MMIOTRACE_TEST) += testmmiotrace.o
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index c6acc6326374..baa0e86adfbc 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -14,6 +14,7 @@
14 14
15#include <asm/traps.h> /* dotraplinkage, ... */ 15#include <asm/traps.h> /* dotraplinkage, ... */
16#include <asm/pgalloc.h> /* pgd_*(), ... */ 16#include <asm/pgalloc.h> /* pgd_*(), ... */
17#include <asm/kmemcheck.h> /* kmemcheck_*(), ... */
17 18
18/* 19/*
19 * Page fault error code bits: 20 * Page fault error code bits:
@@ -956,6 +957,13 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
956 /* Get the faulting address: */ 957 /* Get the faulting address: */
957 address = read_cr2(); 958 address = read_cr2();
958 959
960 /*
961 * Detect and handle instructions that would cause a page fault for
962 * both a tracked kernel page and a userspace page.
963 */
964 if (kmemcheck_active(regs))
965 kmemcheck_hide(regs);
966
959 if (unlikely(kmmio_fault(regs, address))) 967 if (unlikely(kmmio_fault(regs, address)))
960 return; 968 return;
961 969
@@ -973,9 +981,13 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
973 * protection error (error_code & 9) == 0. 981 * protection error (error_code & 9) == 0.
974 */ 982 */
975 if (unlikely(fault_in_kernel_space(address))) { 983 if (unlikely(fault_in_kernel_space(address))) {
976 if (!(error_code & (PF_RSVD|PF_USER|PF_PROT)) && 984 if (!(error_code & (PF_RSVD | PF_USER | PF_PROT))) {
977 vmalloc_fault(address) >= 0) 985 if (vmalloc_fault(address) >= 0)
978 return; 986 return;
987
988 if (kmemcheck_fault(regs, address, error_code))
989 return;
990 }
979 991
980 /* Can handle a stale RO->RW TLB: */ 992 /* Can handle a stale RO->RW TLB: */
981 if (spurious_fault(error_code, address)) 993 if (spurious_fault(error_code, address))
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 34c1bfb64f1c..f53b57e4086f 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -213,7 +213,7 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
213 if (!after_bootmem) 213 if (!after_bootmem)
214 init_gbpages(); 214 init_gbpages();
215 215
216#ifdef CONFIG_DEBUG_PAGEALLOC 216#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KMEMCHECK)
217 /* 217 /*
218 * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages. 218 * For CONFIG_DEBUG_PAGEALLOC, identity mapping will use small pages.
219 * This will simplify cpa(), which otherwise needs to support splitting 219 * This will simplify cpa(), which otherwise needs to support splitting
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 9ff3c0816d15..3cd7711bb949 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -111,7 +111,7 @@ static pte_t * __init one_page_table_init(pmd_t *pmd)
111 pte_t *page_table = NULL; 111 pte_t *page_table = NULL;
112 112
113 if (after_bootmem) { 113 if (after_bootmem) {
114#ifdef CONFIG_DEBUG_PAGEALLOC 114#if defined(CONFIG_DEBUG_PAGEALLOC) || defined(CONFIG_KMEMCHECK)
115 page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE); 115 page_table = (pte_t *) alloc_bootmem_pages(PAGE_SIZE);
116#endif 116#endif
117 if (!page_table) 117 if (!page_table)
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index 52bb9519bb86..9c543290a813 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -104,7 +104,7 @@ static __ref void *spp_getpage(void)
104 void *ptr; 104 void *ptr;
105 105
106 if (after_bootmem) 106 if (after_bootmem)
107 ptr = (void *) get_zeroed_page(GFP_ATOMIC); 107 ptr = (void *) get_zeroed_page(GFP_ATOMIC | __GFP_NOTRACK);
108 else 108 else
109 ptr = alloc_bootmem_pages(PAGE_SIZE); 109 ptr = alloc_bootmem_pages(PAGE_SIZE);
110 110
@@ -281,7 +281,7 @@ static __ref void *alloc_low_page(unsigned long *phys)
281 void *adr; 281 void *adr;
282 282
283 if (after_bootmem) { 283 if (after_bootmem) {
284 adr = (void *)get_zeroed_page(GFP_ATOMIC); 284 adr = (void *)get_zeroed_page(GFP_ATOMIC | __GFP_NOTRACK);
285 *phys = __pa(adr); 285 *phys = __pa(adr);
286 286
287 return adr; 287 return adr;
diff --git a/arch/x86/mm/kmemcheck/Makefile b/arch/x86/mm/kmemcheck/Makefile
new file mode 100644
index 000000000000..520b3bce4095
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/Makefile
@@ -0,0 +1 @@
obj-y := error.o kmemcheck.o opcode.o pte.o selftest.o shadow.o
diff --git a/arch/x86/mm/kmemcheck/error.c b/arch/x86/mm/kmemcheck/error.c
new file mode 100644
index 000000000000..4901d0dafda6
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/error.c
@@ -0,0 +1,228 @@
1#include <linux/interrupt.h>
2#include <linux/kdebug.h>
3#include <linux/kmemcheck.h>
4#include <linux/kernel.h>
5#include <linux/types.h>
6#include <linux/ptrace.h>
7#include <linux/stacktrace.h>
8#include <linux/string.h>
9
10#include "error.h"
11#include "shadow.h"
12
13enum kmemcheck_error_type {
14 KMEMCHECK_ERROR_INVALID_ACCESS,
15 KMEMCHECK_ERROR_BUG,
16};
17
18#define SHADOW_COPY_SIZE (1 << CONFIG_KMEMCHECK_SHADOW_COPY_SHIFT)
19
20struct kmemcheck_error {
21 enum kmemcheck_error_type type;
22
23 union {
24 /* KMEMCHECK_ERROR_INVALID_ACCESS */
25 struct {
26 /* Kind of access that caused the error */
27 enum kmemcheck_shadow state;
28 /* Address and size of the erroneous read */
29 unsigned long address;
30 unsigned int size;
31 };
32 };
33
34 struct pt_regs regs;
35 struct stack_trace trace;
36 unsigned long trace_entries[32];
37
38 /* We compress it to a char. */
39 unsigned char shadow_copy[SHADOW_COPY_SIZE];
40 unsigned char memory_copy[SHADOW_COPY_SIZE];
41};
42
43/*
44 * Create a ring queue of errors to output. We can't call printk() directly
45 * from the kmemcheck traps, since this may call the console drivers and
46 * result in a recursive fault.
47 */
48static struct kmemcheck_error error_fifo[CONFIG_KMEMCHECK_QUEUE_SIZE];
49static unsigned int error_count;
50static unsigned int error_rd;
51static unsigned int error_wr;
52static unsigned int error_missed_count;
53
54static struct kmemcheck_error *error_next_wr(void)
55{
56 struct kmemcheck_error *e;
57
58 if (error_count == ARRAY_SIZE(error_fifo)) {
59 ++error_missed_count;
60 return NULL;
61 }
62
63 e = &error_fifo[error_wr];
64 if (++error_wr == ARRAY_SIZE(error_fifo))
65 error_wr = 0;
66 ++error_count;
67 return e;
68}
69
70static struct kmemcheck_error *error_next_rd(void)
71{
72 struct kmemcheck_error *e;
73
74 if (error_count == 0)
75 return NULL;
76
77 e = &error_fifo[error_rd];
78 if (++error_rd == ARRAY_SIZE(error_fifo))
79 error_rd = 0;
80 --error_count;
81 return e;
82}
83
84void kmemcheck_error_recall(void)
85{
86 static const char *desc[] = {
87 [KMEMCHECK_SHADOW_UNALLOCATED] = "unallocated",
88 [KMEMCHECK_SHADOW_UNINITIALIZED] = "uninitialized",
89 [KMEMCHECK_SHADOW_INITIALIZED] = "initialized",
90 [KMEMCHECK_SHADOW_FREED] = "freed",
91 };
92
93 static const char short_desc[] = {
94 [KMEMCHECK_SHADOW_UNALLOCATED] = 'a',
95 [KMEMCHECK_SHADOW_UNINITIALIZED] = 'u',
96 [KMEMCHECK_SHADOW_INITIALIZED] = 'i',
97 [KMEMCHECK_SHADOW_FREED] = 'f',
98 };
99
100 struct kmemcheck_error *e;
101 unsigned int i;
102
103 e = error_next_rd();
104 if (!e)
105 return;
106
107 switch (e->type) {
108 case KMEMCHECK_ERROR_INVALID_ACCESS:
109 printk(KERN_ERR "WARNING: kmemcheck: Caught %d-bit read "
110 "from %s memory (%p)\n",
111 8 * e->size, e->state < ARRAY_SIZE(desc) ?
112 desc[e->state] : "(invalid shadow state)",
113 (void *) e->address);
114
115 printk(KERN_INFO);
116 for (i = 0; i < SHADOW_COPY_SIZE; ++i)
117 printk("%02x", e->memory_copy[i]);
118 printk("\n");
119
120 printk(KERN_INFO);
121 for (i = 0; i < SHADOW_COPY_SIZE; ++i) {
122 if (e->shadow_copy[i] < ARRAY_SIZE(short_desc))
123 printk(" %c", short_desc[e->shadow_copy[i]]);
124 else
125 printk(" ?");
126 }
127 printk("\n");
128 printk(KERN_INFO "%*c\n", 2 + 2
129 * (int) (e->address & (SHADOW_COPY_SIZE - 1)), '^');
130 break;
131 case KMEMCHECK_ERROR_BUG:
132 printk(KERN_EMERG "ERROR: kmemcheck: Fatal error\n");
133 break;
134 }
135
136 __show_regs(&e->regs, 1);
137 print_stack_trace(&e->trace, 0);
138}
139
140static void do_wakeup(unsigned long data)
141{
142 while (error_count > 0)
143 kmemcheck_error_recall();
144
145 if (error_missed_count > 0) {
146 printk(KERN_WARNING "kmemcheck: Lost %d error reports because "
147 "the queue was too small\n", error_missed_count);
148 error_missed_count = 0;
149 }
150}
151
152static DECLARE_TASKLET(kmemcheck_tasklet, &do_wakeup, 0);
153
154/*
155 * Save the context of an error report.
156 */
157void kmemcheck_error_save(enum kmemcheck_shadow state,
158 unsigned long address, unsigned int size, struct pt_regs *regs)
159{
160 static unsigned long prev_ip;
161
162 struct kmemcheck_error *e;
163 void *shadow_copy;
164 void *memory_copy;
165
166 /* Don't report several adjacent errors from the same EIP. */
167 if (regs->ip == prev_ip)
168 return;
169 prev_ip = regs->ip;
170
171 e = error_next_wr();
172 if (!e)
173 return;
174
175 e->type = KMEMCHECK_ERROR_INVALID_ACCESS;
176
177 e->state = state;
178 e->address = address;
179 e->size = size;
180
181 /* Save regs */
182 memcpy(&e->regs, regs, sizeof(*regs));
183
184 /* Save stack trace */
185 e->trace.nr_entries = 0;
186 e->trace.entries = e->trace_entries;
187 e->trace.max_entries = ARRAY_SIZE(e->trace_entries);
188 e->trace.skip = 0;
189 save_stack_trace_bp(&e->trace, regs->bp);
190
191 /* Round address down to nearest 16 bytes */
192 shadow_copy = kmemcheck_shadow_lookup(address
193 & ~(SHADOW_COPY_SIZE - 1));
194 BUG_ON(!shadow_copy);
195
196 memcpy(e->shadow_copy, shadow_copy, SHADOW_COPY_SIZE);
197
198 kmemcheck_show_addr(address);
199 memory_copy = (void *) (address & ~(SHADOW_COPY_SIZE - 1));
200 memcpy(e->memory_copy, memory_copy, SHADOW_COPY_SIZE);
201 kmemcheck_hide_addr(address);
202
203 tasklet_hi_schedule_first(&kmemcheck_tasklet);
204}
205
206/*
207 * Save the context of a kmemcheck bug.
208 */
209void kmemcheck_error_save_bug(struct pt_regs *regs)
210{
211 struct kmemcheck_error *e;
212
213 e = error_next_wr();
214 if (!e)
215 return;
216
217 e->type = KMEMCHECK_ERROR_BUG;
218
219 memcpy(&e->regs, regs, sizeof(*regs));
220
221 e->trace.nr_entries = 0;
222 e->trace.entries = e->trace_entries;
223 e->trace.max_entries = ARRAY_SIZE(e->trace_entries);
224 e->trace.skip = 1;
225 save_stack_trace(&e->trace);
226
227 tasklet_hi_schedule_first(&kmemcheck_tasklet);
228}
diff --git a/arch/x86/mm/kmemcheck/error.h b/arch/x86/mm/kmemcheck/error.h
new file mode 100644
index 000000000000..0efc2e8d0a20
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/error.h
@@ -0,0 +1,15 @@
1#ifndef ARCH__X86__MM__KMEMCHECK__ERROR_H
2#define ARCH__X86__MM__KMEMCHECK__ERROR_H
3
4#include <linux/ptrace.h>
5
6#include "shadow.h"
7
8void kmemcheck_error_save(enum kmemcheck_shadow state,
9 unsigned long address, unsigned int size, struct pt_regs *regs);
10
11void kmemcheck_error_save_bug(struct pt_regs *regs);
12
13void kmemcheck_error_recall(void);
14
15#endif
diff --git a/arch/x86/mm/kmemcheck/kmemcheck.c b/arch/x86/mm/kmemcheck/kmemcheck.c
new file mode 100644
index 000000000000..2c55ed098654
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/kmemcheck.c
@@ -0,0 +1,640 @@
1/**
2 * kmemcheck - a heavyweight memory checker for the linux kernel
3 * Copyright (C) 2007, 2008 Vegard Nossum <vegardno@ifi.uio.no>
4 * (With a lot of help from Ingo Molnar and Pekka Enberg.)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License (version 2) as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/kallsyms.h>
14#include <linux/kernel.h>
15#include <linux/kmemcheck.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/page-flags.h>
19#include <linux/percpu.h>
20#include <linux/ptrace.h>
21#include <linux/string.h>
22#include <linux/types.h>
23
24#include <asm/cacheflush.h>
25#include <asm/kmemcheck.h>
26#include <asm/pgtable.h>
27#include <asm/tlbflush.h>
28
29#include "error.h"
30#include "opcode.h"
31#include "pte.h"
32#include "selftest.h"
33#include "shadow.h"
34
35
36#ifdef CONFIG_KMEMCHECK_DISABLED_BY_DEFAULT
37# define KMEMCHECK_ENABLED 0
38#endif
39
40#ifdef CONFIG_KMEMCHECK_ENABLED_BY_DEFAULT
41# define KMEMCHECK_ENABLED 1
42#endif
43
44#ifdef CONFIG_KMEMCHECK_ONESHOT_BY_DEFAULT
45# define KMEMCHECK_ENABLED 2
46#endif
47
48int kmemcheck_enabled = KMEMCHECK_ENABLED;
49
50int __init kmemcheck_init(void)
51{
52#ifdef CONFIG_SMP
53 /*
54 * Limit SMP to use a single CPU. We rely on the fact that this code
55 * runs before SMP is set up.
56 */
57 if (setup_max_cpus > 1) {
58 printk(KERN_INFO
59 "kmemcheck: Limiting number of CPUs to 1.\n");
60 setup_max_cpus = 1;
61 }
62#endif
63
64 if (!kmemcheck_selftest()) {
65 printk(KERN_INFO "kmemcheck: self-tests failed; disabling\n");
66 kmemcheck_enabled = 0;
67 return -EINVAL;
68 }
69
70 printk(KERN_INFO "kmemcheck: Initialized\n");
71 return 0;
72}
73
74early_initcall(kmemcheck_init);
75
76/*
77 * We need to parse the kmemcheck= option before any memory is allocated.
78 */
79static int __init param_kmemcheck(char *str)
80{
81 if (!str)
82 return -EINVAL;
83
84 sscanf(str, "%d", &kmemcheck_enabled);
85 return 0;
86}
87
88early_param("kmemcheck", param_kmemcheck);
89
90int kmemcheck_show_addr(unsigned long address)
91{
92 pte_t *pte;
93
94 pte = kmemcheck_pte_lookup(address);
95 if (!pte)
96 return 0;
97
98 set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT));
99 __flush_tlb_one(address);
100 return 1;
101}
102
103int kmemcheck_hide_addr(unsigned long address)
104{
105 pte_t *pte;
106
107 pte = kmemcheck_pte_lookup(address);
108 if (!pte)
109 return 0;
110
111 set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT));
112 __flush_tlb_one(address);
113 return 1;
114}
115
116struct kmemcheck_context {
117 bool busy;
118 int balance;
119
120 /*
121 * There can be at most two memory operands to an instruction, but
122 * each address can cross a page boundary -- so we may need up to
123 * four addresses that must be hidden/revealed for each fault.
124 */
125 unsigned long addr[4];
126 unsigned long n_addrs;
127 unsigned long flags;
128
129 /* Data size of the instruction that caused a fault. */
130 unsigned int size;
131};
132
133static DEFINE_PER_CPU(struct kmemcheck_context, kmemcheck_context);
134
135bool kmemcheck_active(struct pt_regs *regs)
136{
137 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
138
139 return data->balance > 0;
140}
141
142/* Save an address that needs to be shown/hidden */
143static void kmemcheck_save_addr(unsigned long addr)
144{
145 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
146
147 BUG_ON(data->n_addrs >= ARRAY_SIZE(data->addr));
148 data->addr[data->n_addrs++] = addr;
149}
150
151static unsigned int kmemcheck_show_all(void)
152{
153 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
154 unsigned int i;
155 unsigned int n;
156
157 n = 0;
158 for (i = 0; i < data->n_addrs; ++i)
159 n += kmemcheck_show_addr(data->addr[i]);
160
161 return n;
162}
163
164static unsigned int kmemcheck_hide_all(void)
165{
166 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
167 unsigned int i;
168 unsigned int n;
169
170 n = 0;
171 for (i = 0; i < data->n_addrs; ++i)
172 n += kmemcheck_hide_addr(data->addr[i]);
173
174 return n;
175}
176
177/*
178 * Called from the #PF handler.
179 */
180void kmemcheck_show(struct pt_regs *regs)
181{
182 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
183
184 BUG_ON(!irqs_disabled());
185
186 if (unlikely(data->balance != 0)) {
187 kmemcheck_show_all();
188 kmemcheck_error_save_bug(regs);
189 data->balance = 0;
190 return;
191 }
192
193 /*
194 * None of the addresses actually belonged to kmemcheck. Note that
195 * this is not an error.
196 */
197 if (kmemcheck_show_all() == 0)
198 return;
199
200 ++data->balance;
201
202 /*
203 * The IF needs to be cleared as well, so that the faulting
204 * instruction can run "uninterrupted". Otherwise, we might take
205 * an interrupt and start executing that before we've had a chance
206 * to hide the page again.
207 *
208 * NOTE: In the rare case of multiple faults, we must not override
209 * the original flags:
210 */
211 if (!(regs->flags & X86_EFLAGS_TF))
212 data->flags = regs->flags;
213
214 regs->flags |= X86_EFLAGS_TF;
215 regs->flags &= ~X86_EFLAGS_IF;
216}
217
218/*
219 * Called from the #DB handler.
220 */
221void kmemcheck_hide(struct pt_regs *regs)
222{
223 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
224 int n;
225
226 BUG_ON(!irqs_disabled());
227
228 if (data->balance == 0)
229 return;
230
231 if (unlikely(data->balance != 1)) {
232 kmemcheck_show_all();
233 kmemcheck_error_save_bug(regs);
234 data->n_addrs = 0;
235 data->balance = 0;
236
237 if (!(data->flags & X86_EFLAGS_TF))
238 regs->flags &= ~X86_EFLAGS_TF;
239 if (data->flags & X86_EFLAGS_IF)
240 regs->flags |= X86_EFLAGS_IF;
241 return;
242 }
243
244 if (kmemcheck_enabled)
245 n = kmemcheck_hide_all();
246 else
247 n = kmemcheck_show_all();
248
249 if (n == 0)
250 return;
251
252 --data->balance;
253
254 data->n_addrs = 0;
255
256 if (!(data->flags & X86_EFLAGS_TF))
257 regs->flags &= ~X86_EFLAGS_TF;
258 if (data->flags & X86_EFLAGS_IF)
259 regs->flags |= X86_EFLAGS_IF;
260}
261
262void kmemcheck_show_pages(struct page *p, unsigned int n)
263{
264 unsigned int i;
265
266 for (i = 0; i < n; ++i) {
267 unsigned long address;
268 pte_t *pte;
269 unsigned int level;
270
271 address = (unsigned long) page_address(&p[i]);
272 pte = lookup_address(address, &level);
273 BUG_ON(!pte);
274 BUG_ON(level != PG_LEVEL_4K);
275
276 set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT));
277 set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_HIDDEN));
278 __flush_tlb_one(address);
279 }
280}
281
282bool kmemcheck_page_is_tracked(struct page *p)
283{
284 /* This will also check the "hidden" flag of the PTE. */
285 return kmemcheck_pte_lookup((unsigned long) page_address(p));
286}
287
288void kmemcheck_hide_pages(struct page *p, unsigned int n)
289{
290 unsigned int i;
291
292 for (i = 0; i < n; ++i) {
293 unsigned long address;
294 pte_t *pte;
295 unsigned int level;
296
297 address = (unsigned long) page_address(&p[i]);
298 pte = lookup_address(address, &level);
299 BUG_ON(!pte);
300 BUG_ON(level != PG_LEVEL_4K);
301
302 set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT));
303 set_pte(pte, __pte(pte_val(*pte) | _PAGE_HIDDEN));
304 __flush_tlb_one(address);
305 }
306}
307
308/* Access may NOT cross page boundary */
309static void kmemcheck_read_strict(struct pt_regs *regs,
310 unsigned long addr, unsigned int size)
311{
312 void *shadow;
313 enum kmemcheck_shadow status;
314
315 shadow = kmemcheck_shadow_lookup(addr);
316 if (!shadow)
317 return;
318
319 kmemcheck_save_addr(addr);
320 status = kmemcheck_shadow_test(shadow, size);
321 if (status == KMEMCHECK_SHADOW_INITIALIZED)
322 return;
323
324 if (kmemcheck_enabled)
325 kmemcheck_error_save(status, addr, size, regs);
326
327 if (kmemcheck_enabled == 2)
328 kmemcheck_enabled = 0;
329
330 /* Don't warn about it again. */
331 kmemcheck_shadow_set(shadow, size);
332}
333
334/* Access may cross page boundary */
335static void kmemcheck_read(struct pt_regs *regs,
336 unsigned long addr, unsigned int size)
337{
338 unsigned long page = addr & PAGE_MASK;
339 unsigned long next_addr = addr + size - 1;
340 unsigned long next_page = next_addr & PAGE_MASK;
341
342 if (likely(page == next_page)) {
343 kmemcheck_read_strict(regs, addr, size);
344 return;
345 }
346
347 /*
348 * What we do is basically to split the access across the
349 * two pages and handle each part separately. Yes, this means
350 * that we may now see reads that are 3 + 5 bytes, for
351 * example (and if both are uninitialized, there will be two
352 * reports), but it makes the code a lot simpler.
353 */
354 kmemcheck_read_strict(regs, addr, next_page - addr);
355 kmemcheck_read_strict(regs, next_page, next_addr - next_page);
356}
357
358static void kmemcheck_write_strict(struct pt_regs *regs,
359 unsigned long addr, unsigned int size)
360{
361 void *shadow;
362
363 shadow = kmemcheck_shadow_lookup(addr);
364 if (!shadow)
365 return;
366
367 kmemcheck_save_addr(addr);
368 kmemcheck_shadow_set(shadow, size);
369}
370
371static void kmemcheck_write(struct pt_regs *regs,
372 unsigned long addr, unsigned int size)
373{
374 unsigned long page = addr & PAGE_MASK;
375 unsigned long next_addr = addr + size - 1;
376 unsigned long next_page = next_addr & PAGE_MASK;
377
378 if (likely(page == next_page)) {
379 kmemcheck_write_strict(regs, addr, size);
380 return;
381 }
382
383 /* See comment in kmemcheck_read(). */
384 kmemcheck_write_strict(regs, addr, next_page - addr);
385 kmemcheck_write_strict(regs, next_page, next_addr - next_page);
386}
387
388/*
389 * Copying is hard. We have two addresses, each of which may be split across
390 * a page (and each page will have different shadow addresses).
391 */
392static void kmemcheck_copy(struct pt_regs *regs,
393 unsigned long src_addr, unsigned long dst_addr, unsigned int size)
394{
395 uint8_t shadow[8];
396 enum kmemcheck_shadow status;
397
398 unsigned long page;
399 unsigned long next_addr;
400 unsigned long next_page;
401
402 uint8_t *x;
403 unsigned int i;
404 unsigned int n;
405
406 BUG_ON(size > sizeof(shadow));
407
408 page = src_addr & PAGE_MASK;
409 next_addr = src_addr + size - 1;
410 next_page = next_addr & PAGE_MASK;
411
412 if (likely(page == next_page)) {
413 /* Same page */
414 x = kmemcheck_shadow_lookup(src_addr);
415 if (x) {
416 kmemcheck_save_addr(src_addr);
417 for (i = 0; i < size; ++i)
418 shadow[i] = x[i];
419 } else {
420 for (i = 0; i < size; ++i)
421 shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
422 }
423 } else {
424 n = next_page - src_addr;
425 BUG_ON(n > sizeof(shadow));
426
427 /* First page */
428 x = kmemcheck_shadow_lookup(src_addr);
429 if (x) {
430 kmemcheck_save_addr(src_addr);
431 for (i = 0; i < n; ++i)
432 shadow[i] = x[i];
433 } else {
434 /* Not tracked */
435 for (i = 0; i < n; ++i)
436 shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
437 }
438
439 /* Second page */
440 x = kmemcheck_shadow_lookup(next_page);
441 if (x) {
442 kmemcheck_save_addr(next_page);
443 for (i = n; i < size; ++i)
444 shadow[i] = x[i - n];
445 } else {
446 /* Not tracked */
447 for (i = n; i < size; ++i)
448 shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
449 }
450 }
451
452 page = dst_addr & PAGE_MASK;
453 next_addr = dst_addr + size - 1;
454 next_page = next_addr & PAGE_MASK;
455
456 if (likely(page == next_page)) {
457 /* Same page */
458 x = kmemcheck_shadow_lookup(dst_addr);
459 if (x) {
460 kmemcheck_save_addr(dst_addr);
461 for (i = 0; i < size; ++i) {
462 x[i] = shadow[i];
463 shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
464 }
465 }
466 } else {
467 n = next_page - dst_addr;
468 BUG_ON(n > sizeof(shadow));
469
470 /* First page */
471 x = kmemcheck_shadow_lookup(dst_addr);
472 if (x) {
473 kmemcheck_save_addr(dst_addr);
474 for (i = 0; i < n; ++i) {
475 x[i] = shadow[i];
476 shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
477 }
478 }
479
480 /* Second page */
481 x = kmemcheck_shadow_lookup(next_page);
482 if (x) {
483 kmemcheck_save_addr(next_page);
484 for (i = n; i < size; ++i) {
485 x[i - n] = shadow[i];
486 shadow[i] = KMEMCHECK_SHADOW_INITIALIZED;
487 }
488 }
489 }
490
491 status = kmemcheck_shadow_test(shadow, size);
492 if (status == KMEMCHECK_SHADOW_INITIALIZED)
493 return;
494
495 if (kmemcheck_enabled)
496 kmemcheck_error_save(status, src_addr, size, regs);
497
498 if (kmemcheck_enabled == 2)
499 kmemcheck_enabled = 0;
500}
501
502enum kmemcheck_method {
503 KMEMCHECK_READ,
504 KMEMCHECK_WRITE,
505};
506
507static void kmemcheck_access(struct pt_regs *regs,
508 unsigned long fallback_address, enum kmemcheck_method fallback_method)
509{
510 const uint8_t *insn;
511 const uint8_t *insn_primary;
512 unsigned int size;
513
514 struct kmemcheck_context *data = &__get_cpu_var(kmemcheck_context);
515
516 /* Recursive fault -- ouch. */
517 if (data->busy) {
518 kmemcheck_show_addr(fallback_address);
519 kmemcheck_error_save_bug(regs);
520 return;
521 }
522
523 data->busy = true;
524
525 insn = (const uint8_t *) regs->ip;
526 insn_primary = kmemcheck_opcode_get_primary(insn);
527
528 kmemcheck_opcode_decode(insn, &size);
529
530 switch (insn_primary[0]) {
531#ifdef CONFIG_KMEMCHECK_BITOPS_OK
532 /* AND, OR, XOR */
533 /*
534 * Unfortunately, these instructions have to be excluded from
535 * our regular checking since they access only some (and not
536 * all) bits. This clears out "bogus" bitfield-access warnings.
537 */
538 case 0x80:
539 case 0x81:
540 case 0x82:
541 case 0x83:
542 switch ((insn_primary[1] >> 3) & 7) {
543 /* OR */
544 case 1:
545 /* AND */
546 case 4:
547 /* XOR */
548 case 6:
549 kmemcheck_write(regs, fallback_address, size);
550 goto out;
551
552 /* ADD */
553 case 0:
554 /* ADC */
555 case 2:
556 /* SBB */
557 case 3:
558 /* SUB */
559 case 5:
560 /* CMP */
561 case 7:
562 break;
563 }
564 break;
565#endif
566
567 /* MOVS, MOVSB, MOVSW, MOVSD */
568 case 0xa4:
569 case 0xa5:
570 /*
571 * These instructions are special because they take two
572 * addresses, but we only get one page fault.
573 */
574 kmemcheck_copy(regs, regs->si, regs->di, size);
575 goto out;
576
577 /* CMPS, CMPSB, CMPSW, CMPSD */
578 case 0xa6:
579 case 0xa7:
580 kmemcheck_read(regs, regs->si, size);
581 kmemcheck_read(regs, regs->di, size);
582 goto out;
583 }
584
585 /*
586 * If the opcode isn't special in any way, we use the data from the
587 * page fault handler to determine the address and type of memory
588 * access.
589 */
590 switch (fallback_method) {
591 case KMEMCHECK_READ:
592 kmemcheck_read(regs, fallback_address, size);
593 goto out;
594 case KMEMCHECK_WRITE:
595 kmemcheck_write(regs, fallback_address, size);
596 goto out;
597 }
598
599out:
600 data->busy = false;
601}
602
603bool kmemcheck_fault(struct pt_regs *regs, unsigned long address,
604 unsigned long error_code)
605{
606 pte_t *pte;
607
608 /*
609 * XXX: Is it safe to assume that memory accesses from virtual 86
610 * mode or non-kernel code segments will _never_ access kernel
611 * memory (e.g. tracked pages)? For now, we need this to avoid
612 * invoking kmemcheck for PnP BIOS calls.
613 */
614 if (regs->flags & X86_VM_MASK)
615 return false;
616 if (regs->cs != __KERNEL_CS)
617 return false;
618
619 pte = kmemcheck_pte_lookup(address);
620 if (!pte)
621 return false;
622
623 if (error_code & 2)
624 kmemcheck_access(regs, address, KMEMCHECK_WRITE);
625 else
626 kmemcheck_access(regs, address, KMEMCHECK_READ);
627
628 kmemcheck_show(regs);
629 return true;
630}
631
632bool kmemcheck_trap(struct pt_regs *regs)
633{
634 if (!kmemcheck_active(regs))
635 return false;
636
637 /* We're done. */
638 kmemcheck_hide(regs);
639 return true;
640}
diff --git a/arch/x86/mm/kmemcheck/opcode.c b/arch/x86/mm/kmemcheck/opcode.c
new file mode 100644
index 000000000000..63c19e27aa6f
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/opcode.c
@@ -0,0 +1,106 @@
1#include <linux/types.h>
2
3#include "opcode.h"
4
5static bool opcode_is_prefix(uint8_t b)
6{
7 return
8 /* Group 1 */
9 b == 0xf0 || b == 0xf2 || b == 0xf3
10 /* Group 2 */
11 || b == 0x2e || b == 0x36 || b == 0x3e || b == 0x26
12 || b == 0x64 || b == 0x65 || b == 0x2e || b == 0x3e
13 /* Group 3 */
14 || b == 0x66
15 /* Group 4 */
16 || b == 0x67;
17}
18
19#ifdef CONFIG_X86_64
20static bool opcode_is_rex_prefix(uint8_t b)
21{
22 return (b & 0xf0) == 0x40;
23}
24#else
25static bool opcode_is_rex_prefix(uint8_t b)
26{
27 return false;
28}
29#endif
30
31#define REX_W (1 << 3)
32
33/*
34 * This is a VERY crude opcode decoder. We only need to find the size of the
35 * load/store that caused our #PF and this should work for all the opcodes
36 * that we care about. Moreover, the ones who invented this instruction set
37 * should be shot.
38 */
39void kmemcheck_opcode_decode(const uint8_t *op, unsigned int *size)
40{
41 /* Default operand size */
42 int operand_size_override = 4;
43
44 /* prefixes */
45 for (; opcode_is_prefix(*op); ++op) {
46 if (*op == 0x66)
47 operand_size_override = 2;
48 }
49
50 /* REX prefix */
51 if (opcode_is_rex_prefix(*op)) {
52 uint8_t rex = *op;
53
54 ++op;
55 if (rex & REX_W) {
56 switch (*op) {
57 case 0x63:
58 *size = 4;
59 return;
60 case 0x0f:
61 ++op;
62
63 switch (*op) {
64 case 0xb6:
65 case 0xbe:
66 *size = 1;
67 return;
68 case 0xb7:
69 case 0xbf:
70 *size = 2;
71 return;
72 }
73
74 break;
75 }
76
77 *size = 8;
78 return;
79 }
80 }
81
82 /* escape opcode */
83 if (*op == 0x0f) {
84 ++op;
85
86 /*
87 * This is move with zero-extend and sign-extend, respectively;
88 * we don't have to think about 0xb6/0xbe, because this is
89 * already handled in the conditional below.
90 */
91 if (*op == 0xb7 || *op == 0xbf)
92 operand_size_override = 2;
93 }
94
95 *size = (*op & 1) ? operand_size_override : 1;
96}
97
98const uint8_t *kmemcheck_opcode_get_primary(const uint8_t *op)
99{
100 /* skip prefixes */
101 while (opcode_is_prefix(*op))
102 ++op;
103 if (opcode_is_rex_prefix(*op))
104 ++op;
105 return op;
106}
diff --git a/arch/x86/mm/kmemcheck/opcode.h b/arch/x86/mm/kmemcheck/opcode.h
new file mode 100644
index 000000000000..6956aad66b5b
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/opcode.h
@@ -0,0 +1,9 @@
1#ifndef ARCH__X86__MM__KMEMCHECK__OPCODE_H
2#define ARCH__X86__MM__KMEMCHECK__OPCODE_H
3
4#include <linux/types.h>
5
6void kmemcheck_opcode_decode(const uint8_t *op, unsigned int *size);
7const uint8_t *kmemcheck_opcode_get_primary(const uint8_t *op);
8
9#endif
diff --git a/arch/x86/mm/kmemcheck/pte.c b/arch/x86/mm/kmemcheck/pte.c
new file mode 100644
index 000000000000..4ead26eeaf96
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/pte.c
@@ -0,0 +1,22 @@
1#include <linux/mm.h>
2
3#include <asm/pgtable.h>
4
5#include "pte.h"
6
7pte_t *kmemcheck_pte_lookup(unsigned long address)
8{
9 pte_t *pte;
10 unsigned int level;
11
12 pte = lookup_address(address, &level);
13 if (!pte)
14 return NULL;
15 if (level != PG_LEVEL_4K)
16 return NULL;
17 if (!pte_hidden(*pte))
18 return NULL;
19
20 return pte;
21}
22
diff --git a/arch/x86/mm/kmemcheck/pte.h b/arch/x86/mm/kmemcheck/pte.h
new file mode 100644
index 000000000000..9f5966456492
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/pte.h
@@ -0,0 +1,10 @@
1#ifndef ARCH__X86__MM__KMEMCHECK__PTE_H
2#define ARCH__X86__MM__KMEMCHECK__PTE_H
3
4#include <linux/mm.h>
5
6#include <asm/pgtable.h>
7
8pte_t *kmemcheck_pte_lookup(unsigned long address);
9
10#endif
diff --git a/arch/x86/mm/kmemcheck/selftest.c b/arch/x86/mm/kmemcheck/selftest.c
new file mode 100644
index 000000000000..036efbea8b28
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/selftest.c
@@ -0,0 +1,69 @@
1#include <linux/kernel.h>
2
3#include "opcode.h"
4#include "selftest.h"
5
6struct selftest_opcode {
7 unsigned int expected_size;
8 const uint8_t *insn;
9 const char *desc;
10};
11
12static const struct selftest_opcode selftest_opcodes[] = {
13 /* REP MOVS */
14 {1, "\xf3\xa4", "rep movsb <mem8>, <mem8>"},
15 {4, "\xf3\xa5", "rep movsl <mem32>, <mem32>"},
16
17 /* MOVZX / MOVZXD */
18 {1, "\x66\x0f\xb6\x51\xf8", "movzwq <mem8>, <reg16>"},
19 {1, "\x0f\xb6\x51\xf8", "movzwq <mem8>, <reg32>"},
20
21 /* MOVSX / MOVSXD */
22 {1, "\x66\x0f\xbe\x51\xf8", "movswq <mem8>, <reg16>"},
23 {1, "\x0f\xbe\x51\xf8", "movswq <mem8>, <reg32>"},
24
25#ifdef CONFIG_X86_64
26 /* MOVZX / MOVZXD */
27 {1, "\x49\x0f\xb6\x51\xf8", "movzbq <mem8>, <reg64>"},
28 {2, "\x49\x0f\xb7\x51\xf8", "movzbq <mem16>, <reg64>"},
29
30 /* MOVSX / MOVSXD */
31 {1, "\x49\x0f\xbe\x51\xf8", "movsbq <mem8>, <reg64>"},
32 {2, "\x49\x0f\xbf\x51\xf8", "movsbq <mem16>, <reg64>"},
33 {4, "\x49\x63\x51\xf8", "movslq <mem32>, <reg64>"},
34#endif
35};
36
37static bool selftest_opcode_one(const struct selftest_opcode *op)
38{
39 unsigned size;
40
41 kmemcheck_opcode_decode(op->insn, &size);
42
43 if (size == op->expected_size)
44 return true;
45
46 printk(KERN_WARNING "kmemcheck: opcode %s: expected size %d, got %d\n",
47 op->desc, op->expected_size, size);
48 return false;
49}
50
51static bool selftest_opcodes_all(void)
52{
53 bool pass = true;
54 unsigned int i;
55
56 for (i = 0; i < ARRAY_SIZE(selftest_opcodes); ++i)
57 pass = pass && selftest_opcode_one(&selftest_opcodes[i]);
58
59 return pass;
60}
61
62bool kmemcheck_selftest(void)
63{
64 bool pass = true;
65
66 pass = pass && selftest_opcodes_all();
67
68 return pass;
69}
diff --git a/arch/x86/mm/kmemcheck/selftest.h b/arch/x86/mm/kmemcheck/selftest.h
new file mode 100644
index 000000000000..8fed4fe11f95
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/selftest.h
@@ -0,0 +1,6 @@
1#ifndef ARCH_X86_MM_KMEMCHECK_SELFTEST_H
2#define ARCH_X86_MM_KMEMCHECK_SELFTEST_H
3
4bool kmemcheck_selftest(void);
5
6#endif
diff --git a/arch/x86/mm/kmemcheck/shadow.c b/arch/x86/mm/kmemcheck/shadow.c
new file mode 100644
index 000000000000..e773b6bd0079
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/shadow.c
@@ -0,0 +1,162 @@
1#include <linux/kmemcheck.h>
2#include <linux/module.h>
3#include <linux/mm.h>
4#include <linux/module.h>
5
6#include <asm/page.h>
7#include <asm/pgtable.h>
8
9#include "pte.h"
10#include "shadow.h"
11
12/*
13 * Return the shadow address for the given address. Returns NULL if the
14 * address is not tracked.
15 *
16 * We need to be extremely careful not to follow any invalid pointers,
17 * because this function can be called for *any* possible address.
18 */
19void *kmemcheck_shadow_lookup(unsigned long address)
20{
21 pte_t *pte;
22 struct page *page;
23
24 if (!virt_addr_valid(address))
25 return NULL;
26
27 pte = kmemcheck_pte_lookup(address);
28 if (!pte)
29 return NULL;
30
31 page = virt_to_page(address);
32 if (!page->shadow)
33 return NULL;
34 return page->shadow + (address & (PAGE_SIZE - 1));
35}
36
37static void mark_shadow(void *address, unsigned int n,
38 enum kmemcheck_shadow status)
39{
40 unsigned long addr = (unsigned long) address;
41 unsigned long last_addr = addr + n - 1;
42 unsigned long page = addr & PAGE_MASK;
43 unsigned long last_page = last_addr & PAGE_MASK;
44 unsigned int first_n;
45 void *shadow;
46
47 /* If the memory range crosses a page boundary, stop there. */
48 if (page == last_page)
49 first_n = n;
50 else
51 first_n = page + PAGE_SIZE - addr;
52
53 shadow = kmemcheck_shadow_lookup(addr);
54 if (shadow)
55 memset(shadow, status, first_n);
56
57 addr += first_n;
58 n -= first_n;
59
60 /* Do full-page memset()s. */
61 while (n >= PAGE_SIZE) {
62 shadow = kmemcheck_shadow_lookup(addr);
63 if (shadow)
64 memset(shadow, status, PAGE_SIZE);
65
66 addr += PAGE_SIZE;
67 n -= PAGE_SIZE;
68 }
69
70 /* Do the remaining page, if any. */
71 if (n > 0) {
72 shadow = kmemcheck_shadow_lookup(addr);
73 if (shadow)
74 memset(shadow, status, n);
75 }
76}
77
78void kmemcheck_mark_unallocated(void *address, unsigned int n)
79{
80 mark_shadow(address, n, KMEMCHECK_SHADOW_UNALLOCATED);
81}
82
83void kmemcheck_mark_uninitialized(void *address, unsigned int n)
84{
85 mark_shadow(address, n, KMEMCHECK_SHADOW_UNINITIALIZED);
86}
87
88/*
89 * Fill the shadow memory of the given address such that the memory at that
90 * address is marked as being initialized.
91 */
92void kmemcheck_mark_initialized(void *address, unsigned int n)
93{
94 mark_shadow(address, n, KMEMCHECK_SHADOW_INITIALIZED);
95}
96EXPORT_SYMBOL_GPL(kmemcheck_mark_initialized);
97
98void kmemcheck_mark_freed(void *address, unsigned int n)
99{
100 mark_shadow(address, n, KMEMCHECK_SHADOW_FREED);
101}
102
103void kmemcheck_mark_unallocated_pages(struct page *p, unsigned int n)
104{
105 unsigned int i;
106
107 for (i = 0; i < n; ++i)
108 kmemcheck_mark_unallocated(page_address(&p[i]), PAGE_SIZE);
109}
110
111void kmemcheck_mark_uninitialized_pages(struct page *p, unsigned int n)
112{
113 unsigned int i;
114
115 for (i = 0; i < n; ++i)
116 kmemcheck_mark_uninitialized(page_address(&p[i]), PAGE_SIZE);
117}
118
119void kmemcheck_mark_initialized_pages(struct page *p, unsigned int n)
120{
121 unsigned int i;
122
123 for (i = 0; i < n; ++i)
124 kmemcheck_mark_initialized(page_address(&p[i]), PAGE_SIZE);
125}
126
127enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size)
128{
129 uint8_t *x;
130 unsigned int i;
131
132 x = shadow;
133
134#ifdef CONFIG_KMEMCHECK_PARTIAL_OK
135 /*
136 * Make sure _some_ bytes are initialized. Gcc frequently generates
137 * code to access neighboring bytes.
138 */
139 for (i = 0; i < size; ++i) {
140 if (x[i] == KMEMCHECK_SHADOW_INITIALIZED)
141 return x[i];
142 }
143#else
144 /* All bytes must be initialized. */
145 for (i = 0; i < size; ++i) {
146 if (x[i] != KMEMCHECK_SHADOW_INITIALIZED)
147 return x[i];
148 }
149#endif
150
151 return x[0];
152}
153
154void kmemcheck_shadow_set(void *shadow, unsigned int size)
155{
156 uint8_t *x;
157 unsigned int i;
158
159 x = shadow;
160 for (i = 0; i < size; ++i)
161 x[i] = KMEMCHECK_SHADOW_INITIALIZED;
162}
diff --git a/arch/x86/mm/kmemcheck/shadow.h b/arch/x86/mm/kmemcheck/shadow.h
new file mode 100644
index 000000000000..af46d9ab9d86
--- /dev/null
+++ b/arch/x86/mm/kmemcheck/shadow.h
@@ -0,0 +1,16 @@
1#ifndef ARCH__X86__MM__KMEMCHECK__SHADOW_H
2#define ARCH__X86__MM__KMEMCHECK__SHADOW_H
3
4enum kmemcheck_shadow {
5 KMEMCHECK_SHADOW_UNALLOCATED,
6 KMEMCHECK_SHADOW_UNINITIALIZED,
7 KMEMCHECK_SHADOW_INITIALIZED,
8 KMEMCHECK_SHADOW_FREED,
9};
10
11void *kmemcheck_shadow_lookup(unsigned long address);
12
13enum kmemcheck_shadow kmemcheck_shadow_test(void *shadow, unsigned int size);
14void kmemcheck_shadow_set(void *shadow, unsigned int size);
15
16#endif
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 6ce9518fe2ac..3cfe9ced8a4c 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -470,7 +470,7 @@ static int split_large_page(pte_t *kpte, unsigned long address)
470 470
471 if (!debug_pagealloc) 471 if (!debug_pagealloc)
472 spin_unlock(&cpa_lock); 472 spin_unlock(&cpa_lock);
473 base = alloc_pages(GFP_KERNEL, 0); 473 base = alloc_pages(GFP_KERNEL | __GFP_NOTRACK, 0);
474 if (!debug_pagealloc) 474 if (!debug_pagealloc)
475 spin_lock(&cpa_lock); 475 spin_lock(&cpa_lock);
476 if (!base) 476 if (!base)
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 7aa03a5389f5..8e43bdd45456 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -4,9 +4,11 @@
4#include <asm/tlb.h> 4#include <asm/tlb.h>
5#include <asm/fixmap.h> 5#include <asm/fixmap.h>
6 6
7#define PGALLOC_GFP GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO
8
7pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address) 9pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
8{ 10{
9 return (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); 11 return (pte_t *)__get_free_page(PGALLOC_GFP);
10} 12}
11 13
12pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) 14pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
@@ -14,9 +16,9 @@ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address)
14 struct page *pte; 16 struct page *pte;
15 17
16#ifdef CONFIG_HIGHPTE 18#ifdef CONFIG_HIGHPTE
17 pte = alloc_pages(GFP_KERNEL|__GFP_HIGHMEM|__GFP_REPEAT|__GFP_ZERO, 0); 19 pte = alloc_pages(PGALLOC_GFP | __GFP_HIGHMEM, 0);
18#else 20#else
19 pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); 21 pte = alloc_pages(PGALLOC_GFP, 0);
20#endif 22#endif
21 if (pte) 23 if (pte)
22 pgtable_page_ctor(pte); 24 pgtable_page_ctor(pte);
@@ -161,7 +163,7 @@ static int preallocate_pmds(pmd_t *pmds[])
161 bool failed = false; 163 bool failed = false;
162 164
163 for(i = 0; i < PREALLOCATED_PMDS; i++) { 165 for(i = 0; i < PREALLOCATED_PMDS; i++) {
164 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL|__GFP_REPEAT); 166 pmd_t *pmd = (pmd_t *)__get_free_page(PGALLOC_GFP);
165 if (pmd == NULL) 167 if (pmd == NULL)
166 failed = true; 168 failed = true;
167 pmds[i] = pmd; 169 pmds[i] = pmd;
@@ -228,7 +230,7 @@ pgd_t *pgd_alloc(struct mm_struct *mm)
228 pmd_t *pmds[PREALLOCATED_PMDS]; 230 pmd_t *pmds[PREALLOCATED_PMDS];
229 unsigned long flags; 231 unsigned long flags;
230 232
231 pgd = (pgd_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO); 233 pgd = (pgd_t *)__get_free_page(PGALLOC_GFP);
232 234
233 if (pgd == NULL) 235 if (pgd == NULL)
234 goto out; 236 goto out;
diff --git a/arch/xtensa/include/asm/kmap_types.h b/arch/xtensa/include/asm/kmap_types.h
index 9e822d2e3bce..11c687e527f1 100644
--- a/arch/xtensa/include/asm/kmap_types.h
+++ b/arch/xtensa/include/asm/kmap_types.h
@@ -1,31 +1,6 @@
1/*
2 * include/asm-xtensa/kmap_types.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_KMAP_TYPES_H 1#ifndef _XTENSA_KMAP_TYPES_H
12#define _XTENSA_KMAP_TYPES_H 2#define _XTENSA_KMAP_TYPES_H
13 3
14enum km_type { 4#include <asm-generic/kmap_types.h>
15 KM_BOUNCE_READ,
16 KM_SKB_SUNRPC_DATA,
17 KM_SKB_DATA_SOFTIRQ,
18 KM_USER0,
19 KM_USER1,
20 KM_BIO_SRC_IRQ,
21 KM_BIO_DST_IRQ,
22 KM_PTE0,
23 KM_PTE1,
24 KM_IRQ0,
25 KM_IRQ1,
26 KM_SOFTIRQ0,
27 KM_SOFTIRQ1,
28 KM_TYPE_NR
29};
30 5
31#endif /* _XTENSA_KMAP_TYPES_H */ 6#endif /* _XTENSA_KMAP_TYPES_H */
diff --git a/arch/xtensa/kernel/init_task.c b/arch/xtensa/kernel/init_task.c
index e07f5c9fcd35..c4302f0e4ba0 100644
--- a/arch/xtensa/kernel/init_task.c
+++ b/arch/xtensa/kernel/init_task.c
@@ -23,10 +23,6 @@
23 23
24static struct signal_struct init_signals = INIT_SIGNALS(init_signals); 24static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
25static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand); 25static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
26struct mm_struct init_mm = INIT_MM(init_mm);
27
28EXPORT_SYMBOL(init_mm);
29
30union thread_union init_thread_union 26union thread_union init_thread_union
31 __attribute__((__section__(".data.init_task"))) = 27 __attribute__((__section__(".data.init_task"))) =
32{ INIT_THREAD_INFO(init_task) }; 28{ INIT_THREAD_INFO(init_task) };
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 09:53:07 -0500