Merge nommu branch

15 files changed, 101 insertions, 125 deletions

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index efeebe77891f..6c731a4f70c9 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -440,11 +440,12 @@ __arm1020_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+
+        adr     r5, arm1020_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm1020_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm1020_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
@@ -456,12 +457,9 @@ __arm1020_setup:
          * .RVI ZFRS BLDP WCAM
          * .011 1001 ..11 0101
          */
-        .type   arm1020_cr1_clear, #object
-        .type   arm1020_cr1_set, #object
-arm1020_cr1_clear:
-        .word   0x593f
-arm1020_cr1_set:
-        .word   0x3935
+        .type   arm1020_crval, #object
+arm1020_crval:
+        crval   clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 78622ac1e732..269f485d092d 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -422,11 +422,11 @@ __arm1020e_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+        adr     r5, arm1020e_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm1020e_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm1020e_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
@@ -438,12 +438,9 @@ __arm1020e_setup:
          * .RVI ZFRS BLDP WCAM
          * .011 1001 ..11 0101
          */
-        .type   arm1020e_cr1_clear, #object
-        .type   arm1020e_cr1_set, #object
-arm1020e_cr1_clear:
-        .word   0x5f3f
-arm1020e_cr1_set:
-        .word   0x3935
+        .type   arm1020e_crval, #object
+arm1020e_crval:
+        crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 840dfc85ba6d..0643bd464969 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -404,11 +404,11 @@ __arm1022_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+        adr     r5, arm1022_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm1022_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm1022_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .R..............
 #endif
@@ -421,12 +421,9 @@ __arm1022_setup:
          * .011 1001 ..11 0101
          * 
          */
-        .type   arm1022_cr1_clear, #object
-        .type   arm1022_cr1_set, #object
-arm1022_cr1_clear:
-        .word   0x7f3f
-arm1022_cr1_set:
-        .word   0x3935
+        .type   arm1022_crval, #object
+arm1022_crval:
+        crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 72b75d9c712a..0668bfbac67b 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -399,11 +399,11 @@ __arm1026_setup:
         mov     r0, #4                          @ explicitly disable writeback
         mcr     p15, 7, r0, c15, c0, 0
 #endif
+        adr     r5, arm1026_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm1026_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm1026_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
@@ -416,12 +416,9 @@ __arm1026_setup:
          * .011 1001 ..11 0101
          * 
          */
-        .type   arm1026_cr1_clear, #object
-        .type   arm1026_cr1_set, #object
-arm1026_cr1_clear:
-        .word   0x7f3f
-arm1026_cr1_set:
-        .word   0x3935
+        .type   arm1026_crval, #object
+arm1026_crval:
+        crval   clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index fb4110a9db6f..0e6946ab6e5b 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -169,11 +169,11 @@ __arm720_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7, 0           @ flush TLB (v4)
 #endif
+        adr     r5, arm720_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register
-        ldr     r5, arm720_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm720_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
         mov     pc, lr                          @ __ret (head.S)
         .size   __arm720_setup, . - __arm720_setup
 
@@ -183,12 +183,9 @@ __arm720_setup:
          * ..1. 1001 ..11 1101
          * 
          */
-        .type   arm720_cr1_clear, #object
-        .type   arm720_cr1_set, #object
-arm720_cr1_clear:
-        .word   0x2f3f
-arm720_cr1_set:
-        .word   0x213d
+        .type   arm720_crval, #object
+arm720_crval:
+        crval   clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130
 
                 __INITDATA
 
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index b9f1bd11bc62..45292f46c3b2 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -391,11 +391,11 @@ __arm920_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+        adr     r5, arm920_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm920_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm920_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
         mov     pc, lr
         .size   __arm920_setup, . - __arm920_setup
 
@@ -405,12 +405,9 @@ __arm920_setup:
          * ..11 0001 ..11 0101
          * 
          */
-        .type   arm920_cr1_clear, #object
-        .type   arm920_cr1_set, #object
-arm920_cr1_clear:
-        .word   0x3f3f
-arm920_cr1_set:
-        .word   0x3135
+        .type   arm920_crval, #object
+arm920_crval:
+        crval   clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index bda0aea4ce82..3c57519494d7 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -395,11 +395,11 @@ __arm922_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+        adr     r5, arm922_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm922_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm922_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
         mov     pc, lr
         .size   __arm922_setup, . - __arm922_setup
 
@@ -409,12 +409,9 @@ __arm922_setup:
          * ..11 0001 ..11 0101
          * 
          */
-        .type   arm922_cr1_clear, #object
-        .type   arm922_cr1_set, #object
-arm922_cr1_clear:
-        .word   0x3f3f
-arm922_cr1_set:
-        .word   0x3135
+        .type   arm922_crval, #object
+arm922_crval:
+        crval   clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index a28da8f0578f..66d5a32ba0f5 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -455,11 +455,10 @@ __arm925_setup:
         mcr     p15, 7, r0, c15, c0, 0
 #endif
 
+        adr     r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm925_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm925_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .1.. .... .... ....
 #endif
@@ -472,12 +471,9 @@ __arm925_setup:
          * .011 0001 ..11 1101
          * 
          */
-        .type   arm925_cr1_clear, #object
-        .type   arm925_cr1_set, #object
-arm925_cr1_clear:
-        .word   0x7f3f
-arm925_cr1_set:
-        .word   0x313d
+        .type   arm925_crval, #object
+arm925_crval:
+        crval   clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 496a2335d69e..189820e25184 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -404,11 +404,11 @@ __arm926_setup:
         mcr     p15, 7, r0, c15, c0, 0
 #endif 
 
+        adr     r5, arm926_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, arm926_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, arm926_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
         orr     r0, r0, #0x4000                 @ .1.. .... .... ....
 #endif
@@ -421,12 +421,9 @@ __arm926_setup:
          * .011 0001 ..11 0101
          * 
          */
-        .type   arm926_cr1_clear, #object
-        .type   arm926_cr1_set, #object
-arm926_cr1_clear:
-        .word   0x7f3f
-arm926_cr1_set:
-        .word   0x3135
+        .type   arm926_crval, #object
+arm926_crval:
+        crval   clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7cfc2604a1ee..9e2c89eb2115 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -49,3 +49,13 @@
         .macro  asid, rd, rn
         and     \rd, \rn, #255
         .endm
+
+        .macro  crval, clear, mmuset, ucset
+#ifdef CONFIG_MMU
+        .word   \clear
+        .word   \mmuset
+#else
+        .word   \clear
+        .word   \ucset
+#endif
+        .endm
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 31a09087865d..e812246277cf 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -185,11 +185,12 @@ __sa110_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7             @ invalidate I,D TLBs on v4
 #endif
+
+        adr     r5, sa110_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, sa110_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, sa110_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
         mov     pc, lr
         .size   __sa110_setup, . - __sa110_setup
 
@@ -199,12 +200,9 @@ __sa110_setup:
          * ..01 0001 ..11 1101
          * 
          */
-        .type   sa110_cr1_clear, #object
-        .type   sa110_cr1_set, #object
-sa110_cr1_clear:
-        .word   0x3f3f
-sa110_cr1_set:
-        .word   0x113d
+        .type   sa110_crval, #object
+sa110_crval:
+        crval   clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 4e2489c3e1cc..ba32cc6296a0 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -198,11 +198,11 @@ __sa1100_setup:
 #ifdef CONFIG_MMU
         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+        adr     r5, sa1100_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0              @ get control register v4
-        ldr     r5, sa1100_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, sa1100_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
         mov     pc, lr
         .size   __sa1100_setup, . - __sa1100_setup
 
@@ -212,12 +212,9 @@ __sa1100_setup:
          * ..11 0001 ..11 1101
          * 
          */
-        .type   sa1100_cr1_clear, #object
-        .type   sa1100_cr1_set, #object
-sa1100_cr1_clear:
-        .word   0x3f3f
-sa1100_cr1_set:
-        .word   0x313d
+        .type   sa1100_crval, #object
+sa1100_crval:
+        crval   clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
 
         __INITDATA
 
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ff778967a005..6f72549f8843 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -212,11 +212,11 @@ __v6_setup:
         orr     r0, r0, #(0xf << 20)
         mcr     p15, 0, r0, c1, c0, 2           @ Enable full access to VFP
 #endif
+        adr     r5, v6_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0, 0           @ read control register
-        ldr     r5, v6_cr1_clear                @ get mask for bits to clear
         bic     r0, r0, r5                      @ clear bits them
-        ldr     r5, v6_cr1_set                  @ get mask for bits to set
-        orr     r0, r0, r5                      @ set them
+        orr     r0, r0, r6                      @ set them
         mov     pc, lr                          @ return to head.S:__ret
 
         /*
@@ -225,12 +225,9 @@ __v6_setup:
          * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
          *         0 110       0011 1.00 .111 1101 < we want
          */
-        .type   v6_cr1_clear, #object
-        .type   v6_cr1_set, #object
-v6_cr1_clear:
-        .word   0x01e0fb7f
-v6_cr1_set:
-        .word   0x00c0387d
+        .type   v6_crval, #object
+v6_crval:
+        crval   clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
 
         .type   v6_processor_functions, #object
 ENTRY(v6_processor_functions)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 9aea506d3e65..4ace2d8090c7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -426,23 +426,26 @@ __xsc3_setup:
         orr     r0, r0, #(1 << 10)              @ enable L2 for LLR cache
 #endif
         mcr     p15, 0, r0, c1, c0, 1           @ set auxiliary control reg
+
+        adr     r5, xsc3_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0, 0           @ get control register
-        bic     r0, r0, #0x0002                 @ .... .... .... ..A.
-        orr     r0, r0, #0x0005                 @ .... .... .... .C.M
+        bic     r0, r0, r5                      @ .... .... .... ..A.
+        orr     r0, r0, r6                      @ .... .... .... .C.M
 #if BTB_ENABLE
-        bic     r0, r0, #0x0200                 @ .... ..R. .... ....
-        orr     r0, r0, #0x3900                 @ ..VI Z..S .... ....
-#else
-        bic     r0, r0, #0x0a00                 @ .... Z.R. .... ....
-        orr     r0, r0, #0x3100                 @ ..VI ...S .... ....
+        orr     r0, r0, #0x00000800             @ ..VI Z..S .... ....
 #endif
 #if L2_CACHE_ENABLE
-        orr     r0, r0, #0x4000000              @ L2 enable
+        orr     r0, r0, #0x04000000             @ L2 enable
 #endif
         mov     pc, lr
 
         .size   __xsc3_setup, . - __xsc3_setup
 
+        .type   xsc3_crval, #object
+xsc3_crval:
+        crval   clear=0x04003b02, mmuset=0x00003105, ucset=0x00001100
+
         __INITDATA
 
 /*
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index f4aeb7b06911..535395e25a8a 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -475,11 +475,12 @@ __xscale_setup:
         orr     r0, r0, #1 << 6                 @ cp6 for IOP3xx and Bulverde
         orr     r0, r0, #1 << 13                @ Its undefined whether this
         mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
+
+        adr     r5, xscale_crval
+        ldmia   r5, {r5, r6}
         mrc     p15, 0, r0, c1, c0, 0           @ get control register
-        ldr     r5, xscale_cr1_clear
         bic     r0, r0, r5
-        ldr     r5, xscale_cr1_set
-        orr     r0, r0, r5
+        orr     r0, r0, r6
         mov     pc, lr
         .size   __xscale_setup, . - __xscale_setup
 
@@ -489,12 +490,9 @@ __xscale_setup:
          * ..11 1.01 .... .101
          * 
          */
-        .type   xscale_cr1_clear, #object
-        .type   xscale_cr1_set, #object
-xscale_cr1_clear:
-        .word   0x3b07
-xscale_cr1_set:
-        .word   0x3905
+        .type   xscale_crval, #object
+xscale_crval:
+        crval   clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
 
         __INITDATA