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authorGregory Bean <gbean@codeaurora.org>2010-09-10 18:03:36 -0400
committerDaniel Walker <dwalker@codeaurora.org>2010-10-06 12:01:19 -0400
commit2783cc265cc57c4bbf788b75fa8c3f06259dffd1 (patch)
treebb8d1b52c83ee451fd9b06e4bb4df5d2ed4bb1f3 /arch
parentab78cde589e89afa039a13bc75d23d249f1c1200 (diff)
msm: add gpio driver for single-core SoCs.
Install a gpiolib driver supporting the on-chip gpios for single-core MSMs in the 7x00 family, including 7x00A, 7x25, 7x27, 7x30, 8x50, and 8x50a. As part of the ongoing effort to converge on a common code base, this driver is based on the Google-Android msmgpio driver, whose authors include Brian Swetland and Arve Hjønnevåg. Cc: Arve Hjønnevåg <arve@android.com> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Ryan Mallon <ryan@bluewatersys.com> Cc: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Daniel Walker <dwalker@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-msm/Makefile3
-rw-r--r--arch/arm/mach-msm/gpio.c358
-rw-r--r--arch/arm/mach-msm/gpio_hw.h278
3 files changed, 639 insertions, 0 deletions
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 2263b8ffd6b9..c95d19a9045d 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -22,3 +22,6 @@ obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
22obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o 22obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
23obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o 23obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
24obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o 24obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
25ifndef CONFIG_MSM_V2_TLMM
26obj-y += gpio.o
27endif
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
new file mode 100644
index 000000000000..5040f1cb64f9
--- /dev/null
+++ b/arch/arm/mach-msm/gpio.c
@@ -0,0 +1,358 @@
1/* linux/arch/arm/mach-msm/gpio.c
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/bitops.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/module.h>
23#include "gpio_hw.h"
24
25#define FIRST_GPIO_IRQ MSM_GPIO_TO_INT(0)
26
27#define MSM_GPIO_BANK(bank, first, last) \
28 { \
29 .regs = { \
30 .out = MSM_GPIO_OUT_##bank, \
31 .in = MSM_GPIO_IN_##bank, \
32 .int_status = MSM_GPIO_INT_STATUS_##bank, \
33 .int_clear = MSM_GPIO_INT_CLEAR_##bank, \
34 .int_en = MSM_GPIO_INT_EN_##bank, \
35 .int_edge = MSM_GPIO_INT_EDGE_##bank, \
36 .int_pos = MSM_GPIO_INT_POS_##bank, \
37 .oe = MSM_GPIO_OE_##bank, \
38 }, \
39 .chip = { \
40 .base = (first), \
41 .ngpio = (last) - (first) + 1, \
42 .get = msm_gpio_get, \
43 .set = msm_gpio_set, \
44 .direction_input = msm_gpio_direction_input, \
45 .direction_output = msm_gpio_direction_output, \
46 .to_irq = msm_gpio_to_irq, \
47 } \
48 }
49
50#define MSM_GPIO_BROKEN_INT_CLEAR 1
51
52struct msm_gpio_regs {
53 void __iomem *out;
54 void __iomem *in;
55 void __iomem *int_status;
56 void __iomem *int_clear;
57 void __iomem *int_en;
58 void __iomem *int_edge;
59 void __iomem *int_pos;
60 void __iomem *oe;
61};
62
63struct msm_gpio_chip {
64 spinlock_t lock;
65 struct gpio_chip chip;
66 struct msm_gpio_regs regs;
67#if MSM_GPIO_BROKEN_INT_CLEAR
68 unsigned int_status_copy;
69#endif
70 unsigned int both_edge_detect;
71 unsigned int int_enable[2]; /* 0: awake, 1: sleep */
72};
73
74static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
75 unsigned offset, unsigned on)
76{
77 unsigned mask = BIT(offset);
78 unsigned val;
79
80 val = readl(msm_chip->regs.out);
81 if (on)
82 writel(val | mask, msm_chip->regs.out);
83 else
84 writel(val & ~mask, msm_chip->regs.out);
85 return 0;
86}
87
88static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
89{
90 int loop_limit = 100;
91 unsigned pol, val, val2, intstat;
92 do {
93 val = readl(msm_chip->regs.in);
94 pol = readl(msm_chip->regs.int_pos);
95 pol = (pol & ~msm_chip->both_edge_detect) |
96 (~val & msm_chip->both_edge_detect);
97 writel(pol, msm_chip->regs.int_pos);
98 intstat = readl(msm_chip->regs.int_status);
99 val2 = readl(msm_chip->regs.in);
100 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
101 return;
102 } while (loop_limit-- > 0);
103 printk(KERN_ERR "msm_gpio_update_both_edge_detect, "
104 "failed to reach stable state %x != %x\n", val, val2);
105}
106
107static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
108 unsigned offset)
109{
110 unsigned bit = BIT(offset);
111
112#if MSM_GPIO_BROKEN_INT_CLEAR
113 /* Save interrupts that already triggered before we loose them. */
114 /* Any interrupt that triggers between the read of int_status */
115 /* and the write to int_clear will still be lost though. */
116 msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
117 msm_chip->int_status_copy &= ~bit;
118#endif
119 writel(bit, msm_chip->regs.int_clear);
120 msm_gpio_update_both_edge_detect(msm_chip);
121 return 0;
122}
123
124static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
125{
126 struct msm_gpio_chip *msm_chip;
127 unsigned long irq_flags;
128
129 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
130 spin_lock_irqsave(&msm_chip->lock, irq_flags);
131 writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
132 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
133 return 0;
134}
135
136static int
137msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
138{
139 struct msm_gpio_chip *msm_chip;
140 unsigned long irq_flags;
141
142 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
143 spin_lock_irqsave(&msm_chip->lock, irq_flags);
144 msm_gpio_write(msm_chip, offset, value);
145 writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
146 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
147 return 0;
148}
149
150static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
151{
152 struct msm_gpio_chip *msm_chip;
153
154 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
155 return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
156}
157
158static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
159{
160 struct msm_gpio_chip *msm_chip;
161 unsigned long irq_flags;
162
163 msm_chip = container_of(chip, struct msm_gpio_chip, chip);
164 spin_lock_irqsave(&msm_chip->lock, irq_flags);
165 msm_gpio_write(msm_chip, offset, value);
166 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
167}
168
169static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
170{
171 return MSM_GPIO_TO_INT(chip->base + offset);
172}
173
174struct msm_gpio_chip msm_gpio_chips[] = {
175#if defined(CONFIG_ARCH_MSM7X00A)
176 MSM_GPIO_BANK(0, 0, 15),
177 MSM_GPIO_BANK(1, 16, 42),
178 MSM_GPIO_BANK(2, 43, 67),
179 MSM_GPIO_BANK(3, 68, 94),
180 MSM_GPIO_BANK(4, 95, 106),
181 MSM_GPIO_BANK(5, 107, 121),
182#elif defined(CONFIG_ARCH_MSM7X25) || defined(CONFIG_ARCH_MSM7X27)
183 MSM_GPIO_BANK(0, 0, 15),
184 MSM_GPIO_BANK(1, 16, 42),
185 MSM_GPIO_BANK(2, 43, 67),
186 MSM_GPIO_BANK(3, 68, 94),
187 MSM_GPIO_BANK(4, 95, 106),
188 MSM_GPIO_BANK(5, 107, 132),
189#elif defined(CONFIG_ARCH_MSM7X30)
190 MSM_GPIO_BANK(0, 0, 15),
191 MSM_GPIO_BANK(1, 16, 43),
192 MSM_GPIO_BANK(2, 44, 67),
193 MSM_GPIO_BANK(3, 68, 94),
194 MSM_GPIO_BANK(4, 95, 106),
195 MSM_GPIO_BANK(5, 107, 133),
196 MSM_GPIO_BANK(6, 134, 150),
197 MSM_GPIO_BANK(7, 151, 181),
198#elif defined(CONFIG_ARCH_QSD8X50)
199 MSM_GPIO_BANK(0, 0, 15),
200 MSM_GPIO_BANK(1, 16, 42),
201 MSM_GPIO_BANK(2, 43, 67),
202 MSM_GPIO_BANK(3, 68, 94),
203 MSM_GPIO_BANK(4, 95, 103),
204 MSM_GPIO_BANK(5, 104, 121),
205 MSM_GPIO_BANK(6, 122, 152),
206 MSM_GPIO_BANK(7, 153, 164),
207#endif
208};
209
210static void msm_gpio_irq_ack(unsigned int irq)
211{
212 unsigned long irq_flags;
213 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
214 spin_lock_irqsave(&msm_chip->lock, irq_flags);
215 msm_gpio_clear_detect_status(msm_chip,
216 irq - gpio_to_irq(msm_chip->chip.base));
217 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
218}
219
220static void msm_gpio_irq_mask(unsigned int irq)
221{
222 unsigned long irq_flags;
223 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
224 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
225
226 spin_lock_irqsave(&msm_chip->lock, irq_flags);
227 /* level triggered interrupts are also latched */
228 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
229 msm_gpio_clear_detect_status(msm_chip, offset);
230 msm_chip->int_enable[0] &= ~BIT(offset);
231 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
232 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
233}
234
235static void msm_gpio_irq_unmask(unsigned int irq)
236{
237 unsigned long irq_flags;
238 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
239 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
240
241 spin_lock_irqsave(&msm_chip->lock, irq_flags);
242 /* level triggered interrupts are also latched */
243 if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
244 msm_gpio_clear_detect_status(msm_chip, offset);
245 msm_chip->int_enable[0] |= BIT(offset);
246 writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
247 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
248}
249
250static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
251{
252 unsigned long irq_flags;
253 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
254 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
255
256 spin_lock_irqsave(&msm_chip->lock, irq_flags);
257
258 if (on)
259 msm_chip->int_enable[1] |= BIT(offset);
260 else
261 msm_chip->int_enable[1] &= ~BIT(offset);
262
263 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
264 return 0;
265}
266
267static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
268{
269 unsigned long irq_flags;
270 struct msm_gpio_chip *msm_chip = get_irq_chip_data(irq);
271 unsigned offset = irq - gpio_to_irq(msm_chip->chip.base);
272 unsigned val, mask = BIT(offset);
273
274 spin_lock_irqsave(&msm_chip->lock, irq_flags);
275 val = readl(msm_chip->regs.int_edge);
276 if (flow_type & IRQ_TYPE_EDGE_BOTH) {
277 writel(val | mask, msm_chip->regs.int_edge);
278 irq_desc[irq].handle_irq = handle_edge_irq;
279 } else {
280 writel(val & ~mask, msm_chip->regs.int_edge);
281 irq_desc[irq].handle_irq = handle_level_irq;
282 }
283 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
284 msm_chip->both_edge_detect |= mask;
285 msm_gpio_update_both_edge_detect(msm_chip);
286 } else {
287 msm_chip->both_edge_detect &= ~mask;
288 val = readl(msm_chip->regs.int_pos);
289 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
290 writel(val | mask, msm_chip->regs.int_pos);
291 else
292 writel(val & ~mask, msm_chip->regs.int_pos);
293 }
294 spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
295 return 0;
296}
297
298static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
299{
300 int i, j, mask;
301 unsigned val;
302
303 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
304 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
305 val = readl(msm_chip->regs.int_status);
306 val &= msm_chip->int_enable[0];
307 while (val) {
308 mask = val & -val;
309 j = fls(mask) - 1;
310 /* printk("%s %08x %08x bit %d gpio %d irq %d\n",
311 __func__, v, m, j, msm_chip->chip.start + j,
312 FIRST_GPIO_IRQ + msm_chip->chip.start + j); */
313 val &= ~mask;
314 generic_handle_irq(FIRST_GPIO_IRQ +
315 msm_chip->chip.base + j);
316 }
317 }
318 desc->chip->ack(irq);
319}
320
321static struct irq_chip msm_gpio_irq_chip = {
322 .name = "msmgpio",
323 .ack = msm_gpio_irq_ack,
324 .mask = msm_gpio_irq_mask,
325 .unmask = msm_gpio_irq_unmask,
326 .set_wake = msm_gpio_irq_set_wake,
327 .set_type = msm_gpio_irq_set_type,
328};
329
330static int __init msm_init_gpio(void)
331{
332 int i, j = 0;
333
334 for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
335 if (i - FIRST_GPIO_IRQ >=
336 msm_gpio_chips[j].chip.base +
337 msm_gpio_chips[j].chip.ngpio)
338 j++;
339 set_irq_chip_data(i, &msm_gpio_chips[j]);
340 set_irq_chip(i, &msm_gpio_irq_chip);
341 set_irq_handler(i, handle_edge_irq);
342 set_irq_flags(i, IRQF_VALID);
343 }
344
345 for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) {
346 spin_lock_init(&msm_gpio_chips[i].lock);
347 writel(0, msm_gpio_chips[i].regs.int_en);
348 gpiochip_add(&msm_gpio_chips[i].chip);
349 }
350
351 set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
352 set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
353 set_irq_wake(INT_GPIO_GROUP1, 1);
354 set_irq_wake(INT_GPIO_GROUP2, 2);
355 return 0;
356}
357
358postcore_initcall(msm_init_gpio);
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
new file mode 100644
index 000000000000..6b5066038baa
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw.h
@@ -0,0 +1,278 @@
1/* arch/arm/mach-msm/gpio_hw.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
19#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
20
21#include <mach/msm_iomap.h>
22
23/* see 80-VA736-2 Rev C pp 695-751
24**
25** These are actually the *shadow* gpio registers, since the
26** real ones (which allow full access) are only available to the
27** ARM9 side of the world.
28**
29** Since the _BASE need to be page-aligned when we're mapping them
30** to virtual addresses, adjust for the additional offset in these
31** macros.
32*/
33
34#if defined(CONFIG_ARCH_MSM7X30)
35#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
36#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
37#else
38#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
39#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
40#endif
41
42#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X25) ||\
43 defined(CONFIG_ARCH_MSM7X27)
44
45/* output value */
46#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
47#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
48#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
49#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
50#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
51#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 107-121 */
52
53/* same pin map as above, output enable */
54#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
55#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
56#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
57#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
58#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
59#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
60
61/* same pin map as above, input read */
62#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
63#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
64#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
65#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
66#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
67#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
68
69/* same pin map as above, 1=edge 0=level interrup */
70#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
71#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
72#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
73#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
74#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
75#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
76
77/* same pin map as above, 1=positive 0=negative */
78#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
79#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
80#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
81#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
82#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
83#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
84
85/* same pin map as above, interrupt enable */
86#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
87#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
88#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
89#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
90#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
91#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
92
93/* same pin map as above, write 1 to clear interrupt */
94#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
95#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
96#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
97#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
98#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
99#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
100
101/* same pin map as above, 1=interrupt pending */
102#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
103#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
104#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
105#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
106#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
107#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
108
109#endif
110
111#if defined(CONFIG_ARCH_QSD8X50)
112/* output value */
113#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
114#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 42-16 */
115#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-43 */
116#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
117#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 103-95 */
118#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x10) /* gpio 121-104 */
119#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0x14) /* gpio 152-122 */
120#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x18) /* gpio 164-153 */
121
122/* same pin map as above, output enable */
123#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x20)
124#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
125#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x24)
126#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x28)
127#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x2C)
128#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x30)
129#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0x34)
130#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x38)
131
132/* same pin map as above, input read */
133#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x50)
134#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
135#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x54)
136#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x58)
137#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x5C)
138#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x60)
139#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0x64)
140#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x68)
141
142/* same pin map as above, 1=edge 0=level interrup */
143#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x70)
144#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
145#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x74)
146#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x78)
147#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x7C)
148#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0x80)
149#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0x84)
150#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x88)
151
152/* same pin map as above, 1=positive 0=negative */
153#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x90)
154#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
155#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x94)
156#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x98)
157#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x9C)
158#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xA0)
159#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xA4)
160#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0xA8)
161
162/* same pin map as above, interrupt enable */
163#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0xB0)
164#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
165#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0xB4)
166#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0xB8)
167#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0xBC)
168#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xC0)
169#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xC4)
170#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0xC8)
171
172/* same pin map as above, write 1 to clear interrupt */
173#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0xD0)
174#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
175#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0xD4)
176#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0xD8)
177#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0xDC)
178#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xE0)
179#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xE4)
180#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0xE8)
181
182/* same pin map as above, 1=interrupt pending */
183#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xF0)
184#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
185#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xF4)
186#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xF8)
187#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xFC)
188#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0x100)
189#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0x104)
190#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x108)
191
192#endif
193
194#if defined(CONFIG_ARCH_MSM7X30)
195
196/* output value */
197#define MSM_GPIO_OUT_0 MSM_GPIO1_REG(0x00) /* gpio 15-0 */
198#define MSM_GPIO_OUT_1 MSM_GPIO2_REG(0x00) /* gpio 43-16 */
199#define MSM_GPIO_OUT_2 MSM_GPIO1_REG(0x04) /* gpio 67-44 */
200#define MSM_GPIO_OUT_3 MSM_GPIO1_REG(0x08) /* gpio 94-68 */
201#define MSM_GPIO_OUT_4 MSM_GPIO1_REG(0x0C) /* gpio 106-95 */
202#define MSM_GPIO_OUT_5 MSM_GPIO1_REG(0x50) /* gpio 133-107 */
203#define MSM_GPIO_OUT_6 MSM_GPIO1_REG(0xC4) /* gpio 150-134 */
204#define MSM_GPIO_OUT_7 MSM_GPIO1_REG(0x214) /* gpio 181-151 */
205
206/* same pin map as above, output enable */
207#define MSM_GPIO_OE_0 MSM_GPIO1_REG(0x10)
208#define MSM_GPIO_OE_1 MSM_GPIO2_REG(0x08)
209#define MSM_GPIO_OE_2 MSM_GPIO1_REG(0x14)
210#define MSM_GPIO_OE_3 MSM_GPIO1_REG(0x18)
211#define MSM_GPIO_OE_4 MSM_GPIO1_REG(0x1C)
212#define MSM_GPIO_OE_5 MSM_GPIO1_REG(0x54)
213#define MSM_GPIO_OE_6 MSM_GPIO1_REG(0xC8)
214#define MSM_GPIO_OE_7 MSM_GPIO1_REG(0x218)
215
216/* same pin map as above, input read */
217#define MSM_GPIO_IN_0 MSM_GPIO1_REG(0x34)
218#define MSM_GPIO_IN_1 MSM_GPIO2_REG(0x20)
219#define MSM_GPIO_IN_2 MSM_GPIO1_REG(0x38)
220#define MSM_GPIO_IN_3 MSM_GPIO1_REG(0x3C)
221#define MSM_GPIO_IN_4 MSM_GPIO1_REG(0x40)
222#define MSM_GPIO_IN_5 MSM_GPIO1_REG(0x44)
223#define MSM_GPIO_IN_6 MSM_GPIO1_REG(0xCC)
224#define MSM_GPIO_IN_7 MSM_GPIO1_REG(0x21C)
225
226/* same pin map as above, 1=edge 0=level interrup */
227#define MSM_GPIO_INT_EDGE_0 MSM_GPIO1_REG(0x60)
228#define MSM_GPIO_INT_EDGE_1 MSM_GPIO2_REG(0x50)
229#define MSM_GPIO_INT_EDGE_2 MSM_GPIO1_REG(0x64)
230#define MSM_GPIO_INT_EDGE_3 MSM_GPIO1_REG(0x68)
231#define MSM_GPIO_INT_EDGE_4 MSM_GPIO1_REG(0x6C)
232#define MSM_GPIO_INT_EDGE_5 MSM_GPIO1_REG(0xC0)
233#define MSM_GPIO_INT_EDGE_6 MSM_GPIO1_REG(0xD0)
234#define MSM_GPIO_INT_EDGE_7 MSM_GPIO1_REG(0x240)
235
236/* same pin map as above, 1=positive 0=negative */
237#define MSM_GPIO_INT_POS_0 MSM_GPIO1_REG(0x70)
238#define MSM_GPIO_INT_POS_1 MSM_GPIO2_REG(0x58)
239#define MSM_GPIO_INT_POS_2 MSM_GPIO1_REG(0x74)
240#define MSM_GPIO_INT_POS_3 MSM_GPIO1_REG(0x78)
241#define MSM_GPIO_INT_POS_4 MSM_GPIO1_REG(0x7C)
242#define MSM_GPIO_INT_POS_5 MSM_GPIO1_REG(0xBC)
243#define MSM_GPIO_INT_POS_6 MSM_GPIO1_REG(0xD4)
244#define MSM_GPIO_INT_POS_7 MSM_GPIO1_REG(0x228)
245
246/* same pin map as above, interrupt enable */
247#define MSM_GPIO_INT_EN_0 MSM_GPIO1_REG(0x80)
248#define MSM_GPIO_INT_EN_1 MSM_GPIO2_REG(0x60)
249#define MSM_GPIO_INT_EN_2 MSM_GPIO1_REG(0x84)
250#define MSM_GPIO_INT_EN_3 MSM_GPIO1_REG(0x88)
251#define MSM_GPIO_INT_EN_4 MSM_GPIO1_REG(0x8C)
252#define MSM_GPIO_INT_EN_5 MSM_GPIO1_REG(0xB8)
253#define MSM_GPIO_INT_EN_6 MSM_GPIO1_REG(0xD8)
254#define MSM_GPIO_INT_EN_7 MSM_GPIO1_REG(0x22C)
255
256/* same pin map as above, write 1 to clear interrupt */
257#define MSM_GPIO_INT_CLEAR_0 MSM_GPIO1_REG(0x90)
258#define MSM_GPIO_INT_CLEAR_1 MSM_GPIO2_REG(0x68)
259#define MSM_GPIO_INT_CLEAR_2 MSM_GPIO1_REG(0x94)
260#define MSM_GPIO_INT_CLEAR_3 MSM_GPIO1_REG(0x98)
261#define MSM_GPIO_INT_CLEAR_4 MSM_GPIO1_REG(0x9C)
262#define MSM_GPIO_INT_CLEAR_5 MSM_GPIO1_REG(0xB4)
263#define MSM_GPIO_INT_CLEAR_6 MSM_GPIO1_REG(0xDC)
264#define MSM_GPIO_INT_CLEAR_7 MSM_GPIO1_REG(0x230)
265
266/* same pin map as above, 1=interrupt pending */
267#define MSM_GPIO_INT_STATUS_0 MSM_GPIO1_REG(0xA0)
268#define MSM_GPIO_INT_STATUS_1 MSM_GPIO2_REG(0x70)
269#define MSM_GPIO_INT_STATUS_2 MSM_GPIO1_REG(0xA4)
270#define MSM_GPIO_INT_STATUS_3 MSM_GPIO1_REG(0xA8)
271#define MSM_GPIO_INT_STATUS_4 MSM_GPIO1_REG(0xAC)
272#define MSM_GPIO_INT_STATUS_5 MSM_GPIO1_REG(0xB0)
273#define MSM_GPIO_INT_STATUS_6 MSM_GPIO1_REG(0xE0)
274#define MSM_GPIO_INT_STATUS_7 MSM_GPIO1_REG(0x234)
275
276#endif
277
278#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 10:22:58 -0500