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authorManuel Lauss <manuel.lauss@googlemail.com>2011-11-01 15:03:29 -0400
committerRalf Baechle <ralf@linux-mips.org>2011-12-07 17:02:05 -0500
commitfb469f084fdf1631e31d87270f5263c20a7f5cd6 (patch)
treef53cd7f0d87cbd3f3571c55b6b1f76ce0c42c841 /arch
parent435037c630dcd984cf95c9cfff973f8626cea368 (diff)
MIPS: Alchemy: devboards: remove unneeded BCSR IRQ reg acc
Initially I had to write to both the MASK and ENABLE registers, otherwise the CPLD would generate tons of spurious interrupts. With the change to the demux handler to disable the muxed line, it is now sufficient to disable the interrupt by writing either the enable or mask register. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2865/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/alchemy/devboards/bcsr.c11
1 files changed, 2 insertions, 9 deletions
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index 463d2c4d9441..1e83ce2e1147 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -97,14 +97,9 @@ static void bcsr_csc_handler(unsigned int irq, struct irq_desc *d)
97 enable_irq(irq); 97 enable_irq(irq);
98} 98}
99 99
100/* NOTE: both the enable and mask bits must be cleared, otherwise the
101 * CPLD generates tons of spurious interrupts (at least on my DB1200).
102 * -- mlau
103 */
104static void bcsr_irq_mask(struct irq_data *d) 100static void bcsr_irq_mask(struct irq_data *d)
105{ 101{
106 unsigned short v = 1 << (d->irq - bcsr_csc_base); 102 unsigned short v = 1 << (d->irq - bcsr_csc_base);
107 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
108 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 103 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
109 wmb(); 104 wmb();
110} 105}
@@ -112,7 +107,6 @@ static void bcsr_irq_mask(struct irq_data *d)
112static void bcsr_irq_maskack(struct irq_data *d) 107static void bcsr_irq_maskack(struct irq_data *d)
113{ 108{
114 unsigned short v = 1 << (d->irq - bcsr_csc_base); 109 unsigned short v = 1 << (d->irq - bcsr_csc_base);
115 __raw_writew(v, bcsr_virt + BCSR_REG_INTCLR);
116 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR); 110 __raw_writew(v, bcsr_virt + BCSR_REG_MASKCLR);
117 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */ 111 __raw_writew(v, bcsr_virt + BCSR_REG_INTSTAT); /* ack */
118 wmb(); 112 wmb();
@@ -121,7 +115,6 @@ static void bcsr_irq_maskack(struct irq_data *d)
121static void bcsr_irq_unmask(struct irq_data *d) 115static void bcsr_irq_unmask(struct irq_data *d)
122{ 116{
123 unsigned short v = 1 << (d->irq - bcsr_csc_base); 117 unsigned short v = 1 << (d->irq - bcsr_csc_base);
124 __raw_writew(v, bcsr_virt + BCSR_REG_INTSET);
125 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET); 118 __raw_writew(v, bcsr_virt + BCSR_REG_MASKSET);
126 wmb(); 119 wmb();
127} 120}
@@ -137,9 +130,9 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
137{ 130{
138 unsigned int irq; 131 unsigned int irq;
139 132
140 /* mask & disable & ack all */ 133 /* mask & enable & ack all */
141 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTCLR);
142 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR); 134 __raw_writew(0xffff, bcsr_virt + BCSR_REG_MASKCLR);
135 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSET);
143 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT); 136 __raw_writew(0xffff, bcsr_virt + BCSR_REG_INTSTAT);
144 wmb(); 137 wmb();
145 138