diff options
author | Magnus Damm <damm@opensource.se> | 2012-05-09 03:24:59 -0400 |
---|---|---|
committer | Rafael J. Wysocki <rjw@sisk.pl> | 2012-05-12 16:13:52 -0400 |
commit | e994d5eb7c3e45e13eb4fc882a47238f8dc4d63e (patch) | |
tree | 5ac8f9e943fc3d9b9d46d8b1da37d4cff3c02bbb /arch | |
parent | d6720003c3732db891f6b5b10691a9c13ff6c46b (diff) |
ARM / mach-shmobile: Invalidate caches when booting secondary cores
Make sure L1 caches are invalidated when booting secondary
cores. Needed to boot all mach-shmobile SMP systems that
are using Cortex-A9 including sh73a0, r8a7779 and EMEV2.
Thanks to imx and tegra guys for actual code.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-shmobile/headsmp.S | 56 |
1 files changed, 55 insertions, 1 deletions
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index 6ac015c89206..b202c1272526 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S | |||
@@ -16,6 +16,59 @@ | |||
16 | 16 | ||
17 | __CPUINIT | 17 | __CPUINIT |
18 | 18 | ||
19 | /* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks! | ||
20 | * | ||
21 | * The secondary kernel init calls v7_flush_dcache_all before it enables | ||
22 | * the L1; however, the L1 comes out of reset in an undefined state, so | ||
23 | * the clean + invalidate performed by v7_flush_dcache_all causes a bunch | ||
24 | * of cache lines with uninitialized data and uninitialized tags to get | ||
25 | * written out to memory, which does really unpleasant things to the main | ||
26 | * processor. We fix this by performing an invalidate, rather than a | ||
27 | * clean + invalidate, before jumping into the kernel. | ||
28 | * | ||
29 | * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs | ||
30 | * to be called for both secondary cores startup and primary core resume | ||
31 | * procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S. | ||
32 | */ | ||
33 | ENTRY(v7_invalidate_l1) | ||
34 | mov r0, #0 | ||
35 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
36 | mcr p15, 2, r0, c0, c0, 0 | ||
37 | mrc p15, 1, r0, c0, c0, 0 | ||
38 | |||
39 | ldr r1, =0x7fff | ||
40 | and r2, r1, r0, lsr #13 | ||
41 | |||
42 | ldr r1, =0x3ff | ||
43 | |||
44 | and r3, r1, r0, lsr #3 @ NumWays - 1 | ||
45 | add r2, r2, #1 @ NumSets | ||
46 | |||
47 | and r0, r0, #0x7 | ||
48 | add r0, r0, #4 @ SetShift | ||
49 | |||
50 | clz r1, r3 @ WayShift | ||
51 | add r4, r3, #1 @ NumWays | ||
52 | 1: sub r2, r2, #1 @ NumSets-- | ||
53 | mov r3, r4 @ Temp = NumWays | ||
54 | 2: subs r3, r3, #1 @ Temp-- | ||
55 | mov r5, r3, lsl r1 | ||
56 | mov r6, r2, lsl r0 | ||
57 | orr r5, r5, r6 @ Reg = (Temp<<WayShift)|(NumSets<<SetShift) | ||
58 | mcr p15, 0, r5, c7, c6, 2 | ||
59 | bgt 2b | ||
60 | cmp r2, #0 | ||
61 | bgt 1b | ||
62 | dsb | ||
63 | isb | ||
64 | mov pc, lr | ||
65 | ENDPROC(v7_invalidate_l1) | ||
66 | |||
67 | ENTRY(shmobile_invalidate_start) | ||
68 | bl v7_invalidate_l1 | ||
69 | b secondary_startup | ||
70 | ENDPROC(shmobile_invalidate_start) | ||
71 | |||
19 | /* | 72 | /* |
20 | * Reset vector for secondary CPUs. | 73 | * Reset vector for secondary CPUs. |
21 | * This will be mapped at address 0 by SBAR register. | 74 | * This will be mapped at address 0 by SBAR register. |
@@ -24,4 +77,5 @@ | |||
24 | .align 12 | 77 | .align 12 |
25 | ENTRY(shmobile_secondary_vector) | 78 | ENTRY(shmobile_secondary_vector) |
26 | ldr pc, 1f | 79 | ldr pc, 1f |
27 | 1: .long secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET | 80 | 1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET |
81 | ENDPROC(shmobile_secondary_vector) | ||