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authorOlof Johansson <olof@lixom.net>2012-06-30 19:27:54 -0400
committerOlof Johansson <olof@lixom.net>2012-06-30 19:27:54 -0400
commitc53629413409782eeafb4e314dc8c6c8094bff3b (patch)
treee4b24dcf2052759dbf360f63e188b041cc6d909c /arch
parent51a1ec0164e2030e0492bdede4e68090a3394c52 (diff)
parentdf072717eb0050326f0f63eed98200412c395831 (diff)
Merge branch 'lpc32xx/devel' into next/soc
* lpc32xx/devel: (22 commits) ARM: LPC32xx: Move i2s1 dma enabling to clock.c ARM: LPC32xx: Move uart6 irda disable to serial.c ARM: LPC32xx: Cleanup board init, remove duplicate clock init ARM: LPC32xx: Remove spi chip definitions ARM: LPC32xx: Remove spi chipselect request from board init ARM: LPC32xx: Add dt settings to the at25 node ARM: LPC32xx: Build arch dtbs ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled" ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use default ARM: LPC32xx: High Speed UART configuration via DT ARM: LPC32xx: DT conversion of Standard UARTs ARM: LPC32xx: DTS adjustment for using pl18x primecell ARM: LPC32xx: Add MMC controller support ARM: LPC32xx: Defconfig update ARM: LPC32xx: Clock adjustment for key matrix controller ARM: LPC32xx: DTS adjustment for key matrix controller ARM: LPC32xx: Add dts for EA3250 reference board ARM: LPC32xx: Adjust dtsi file for MLC controller configuration ARM: LPC32xx: Add DMA configuration to platform data ARM: LPC32xx: Remove SLC controller initialization from platform init ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/ea3250.dts157
-rw-r--r--arch/arm/boot/dts/lpc32xx.dtsi74
-rw-r--r--arch/arm/boot/dts/phy3250.dts61
-rw-r--r--arch/arm/configs/lpc32xx_defconfig24
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig32
-rw-r--r--arch/arm/mach-lpc32xx/Makefile.boot1
-rw-r--r--arch/arm/mach-lpc32xx/clock.c21
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/gpio.h2
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c158
-rw-r--r--arch/arm/mach-lpc32xx/serial.c90
11 files changed, 376 insertions, 246 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3b9c64817d23..e86fe20b7d09 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1019,8 +1019,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
1019 1019
1020source "arch/arm/mach-ks8695/Kconfig" 1020source "arch/arm/mach-ks8695/Kconfig"
1021 1021
1022source "arch/arm/mach-lpc32xx/Kconfig"
1023
1024source "arch/arm/mach-msm/Kconfig" 1022source "arch/arm/mach-msm/Kconfig"
1025 1023
1026source "arch/arm/mach-mv78xx0/Kconfig" 1024source "arch/arm/mach-mv78xx0/Kconfig"
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
new file mode 100644
index 000000000000..c07ba8c2cc0d
--- /dev/null
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -0,0 +1,157 @@
1/*
2 * Embedded Artists LPC3250 board
3 *
4 * Copyright 2012 Roland Stigge <stigge@antcom.de>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "lpc32xx.dtsi"
16
17/ {
18 model = "Embedded Artists LPC3250 board based on NXP LPC3250";
19 compatible = "ea,ea3250", "nxp,lpc3250";
20 #address-cells = <1>;
21 #size-cells = <1>;
22
23 memory {
24 device_type = "memory";
25 reg = <0 0x4000000>;
26 };
27
28 ahb {
29 mac: ethernet@31060000 {
30 phy-mode = "rmii";
31 use-iram;
32 };
33
34 /* Here, choose exactly one from: ohci, usbd */
35 ohci@31020000 {
36 transceiver = <&isp1301>;
37 status = "okay";
38 };
39
40/*
41 usbd@31020000 {
42 transceiver = <&isp1301>;
43 status = "okay";
44 };
45*/
46
47 /* 128MB Flash via SLC NAND controller */
48 slc: flash@20020000 {
49 status = "okay";
50 #address-cells = <1>;
51 #size-cells = <1>;
52
53 nxp,wdr-clks = <14>;
54 nxp,wwidth = <260000000>;
55 nxp,whold = <104000000>;
56 nxp,wsetup = <200000000>;
57 nxp,rdr-clks = <14>;
58 nxp,rwidth = <34666666>;
59 nxp,rhold = <104000000>;
60 nxp,rsetup = <200000000>;
61 nand-on-flash-bbt;
62 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
63
64 mtd0@00000000 {
65 label = "ea3250-boot";
66 reg = <0x00000000 0x00080000>;
67 read-only;
68 };
69
70 mtd1@00080000 {
71 label = "ea3250-uboot";
72 reg = <0x00080000 0x000c0000>;
73 read-only;
74 };
75
76 mtd2@00140000 {
77 label = "ea3250-kernel";
78 reg = <0x00140000 0x00400000>;
79 };
80
81 mtd3@00540000 {
82 label = "ea3250-rootfs";
83 reg = <0x00540000 0x07ac0000>;
84 };
85 };
86
87 apb {
88 uart5: serial@40090000 {
89 status = "okay";
90 };
91
92 uart3: serial@40080000 {
93 status = "okay";
94 };
95
96 uart6: serial@40098000 {
97 status = "okay";
98 };
99
100 i2c1: i2c@400A0000 {
101 clock-frequency = <100000>;
102
103 eeprom@50 {
104 compatible = "at,24c256";
105 reg = <0x50>;
106 };
107
108 eeprom@57 {
109 compatible = "at,24c64";
110 reg = <0x57>;
111 };
112
113 uda1380: uda1380@18 {
114 compatible = "nxp,uda1380";
115 reg = <0x18>;
116 power-gpio = <&gpio 0x59 0>;
117 reset-gpio = <&gpio 0x51 0>;
118 dac-clk = "wspll";
119 };
120
121 pca9532: pca9532@60 {
122 compatible = "nxp,pca9532";
123 gpio-controller;
124 #gpio-cells = <2>;
125 reg = <0x60>;
126 };
127 };
128
129 i2c2: i2c@400A8000 {
130 clock-frequency = <100000>;
131 };
132
133 i2cusb: i2c@31020300 {
134 clock-frequency = <100000>;
135
136 isp1301: usb-transceiver@2d {
137 compatible = "nxp,isp1301";
138 reg = <0x2d>;
139 };
140 };
141
142 sd@20098000 {
143 wp-gpios = <&pca9532 5 0>;
144 cd-gpios = <&pca9532 4 0>;
145 cd-inverted;
146 bus-width = <4>;
147 status = "okay";
148 };
149 };
150
151 fab {
152 uart1: serial@40014000 {
153 status = "okay";
154 };
155 };
156 };
157};
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3f5dad801a98..c5f37fbd33e6 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -35,13 +35,14 @@
35 slc: flash@20020000 { 35 slc: flash@20020000 {
36 compatible = "nxp,lpc3220-slc"; 36 compatible = "nxp,lpc3220-slc";
37 reg = <0x20020000 0x1000>; 37 reg = <0x20020000 0x1000>;
38 status = "disable"; 38 status = "disabled";
39 }; 39 };
40 40
41 mlc: flash@200B0000 { 41 mlc: flash@200a8000 {
42 compatible = "nxp,lpc3220-mlc"; 42 compatible = "nxp,lpc3220-mlc";
43 reg = <0x200B0000 0x1000>; 43 reg = <0x200a8000 0x11000>;
44 status = "disable"; 44 interrupts = <11 0>;
45 status = "disabled";
45 }; 46 };
46 47
47 dma@31000000 { 48 dma@31000000 {
@@ -57,21 +58,21 @@
57 compatible = "nxp,ohci-nxp", "usb-ohci"; 58 compatible = "nxp,ohci-nxp", "usb-ohci";
58 reg = <0x31020000 0x300>; 59 reg = <0x31020000 0x300>;
59 interrupts = <0x3b 0>; 60 interrupts = <0x3b 0>;
60 status = "disable"; 61 status = "disabled";
61 }; 62 };
62 63
63 usbd@31020000 { 64 usbd@31020000 {
64 compatible = "nxp,lpc3220-udc"; 65 compatible = "nxp,lpc3220-udc";
65 reg = <0x31020000 0x300>; 66 reg = <0x31020000 0x300>;
66 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; 67 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
67 status = "disable"; 68 status = "disabled";
68 }; 69 };
69 70
70 clcd@31040000 { 71 clcd@31040000 {
71 compatible = "arm,pl110", "arm,primecell"; 72 compatible = "arm,pl110", "arm,primecell";
72 reg = <0x31040000 0x1000>; 73 reg = <0x31040000 0x1000>;
73 interrupts = <0x0e 0>; 74 interrupts = <0x0e 0>;
74 status = "disable"; 75 status = "disabled";
75 }; 76 };
76 77
77 mac: ethernet@31060000 { 78 mac: ethernet@31060000 {
@@ -114,9 +115,10 @@
114 }; 115 };
115 116
116 sd@20098000 { 117 sd@20098000 {
117 compatible = "arm,pl180", "arm,primecell"; 118 compatible = "arm,pl18x", "arm,primecell";
118 reg = <0x20098000 0x1000>; 119 reg = <0x20098000 0x1000>;
119 interrupts = <0x0f 0>, <0x0d 0>; 120 interrupts = <0x0f 0>, <0x0d 0>;
121 status = "disabled";
120 }; 122 };
121 123
122 i2s1: i2s@2009C000 { 124 i2s1: i2s@2009C000 {
@@ -124,24 +126,42 @@
124 reg = <0x2009C000 0x1000>; 126 reg = <0x2009C000 0x1000>;
125 }; 127 };
126 128
129 /* UART5 first since it is the default console, ttyS0 */
130 uart5: serial@40090000 {
131 /* actually, ns16550a w/ 64 byte fifos! */
132 compatible = "nxp,lpc3220-uart";
133 reg = <0x40090000 0x1000>;
134 interrupts = <9 0>;
135 clock-frequency = <13000000>;
136 reg-shift = <2>;
137 status = "disabled";
138 };
139
127 uart3: serial@40080000 { 140 uart3: serial@40080000 {
128 compatible = "nxp,serial"; 141 compatible = "nxp,lpc3220-uart";
129 reg = <0x40080000 0x1000>; 142 reg = <0x40080000 0x1000>;
143 interrupts = <7 0>;
144 clock-frequency = <13000000>;
145 reg-shift = <2>;
146 status = "disabled";
130 }; 147 };
131 148
132 uart4: serial@40088000 { 149 uart4: serial@40088000 {
133 compatible = "nxp,serial"; 150 compatible = "nxp,lpc3220-uart";
134 reg = <0x40088000 0x1000>; 151 reg = <0x40088000 0x1000>;
135 }; 152 interrupts = <8 0>;
136 153 clock-frequency = <13000000>;
137 uart5: serial@40090000 { 154 reg-shift = <2>;
138 compatible = "nxp,serial"; 155 status = "disabled";
139 reg = <0x40090000 0x1000>;
140 }; 156 };
141 157
142 uart6: serial@40098000 { 158 uart6: serial@40098000 {
143 compatible = "nxp,serial"; 159 compatible = "nxp,lpc3220-uart";
144 reg = <0x40098000 0x1000>; 160 reg = <0x40098000 0x1000>;
161 interrupts = <10 0>;
162 clock-frequency = <13000000>;
163 reg-shift = <2>;
164 status = "disabled";
145 }; 165 };
146 166
147 i2c1: i2c@400A0000 { 167 i2c1: i2c@400A0000 {
@@ -192,18 +212,24 @@
192 }; 212 };
193 213
194 uart1: serial@40014000 { 214 uart1: serial@40014000 {
195 compatible = "nxp,serial"; 215 compatible = "nxp,lpc3220-hsuart";
196 reg = <0x40014000 0x1000>; 216 reg = <0x40014000 0x1000>;
217 interrupts = <26 0>;
218 status = "disabled";
197 }; 219 };
198 220
199 uart2: serial@40018000 { 221 uart2: serial@40018000 {
200 compatible = "nxp,serial"; 222 compatible = "nxp,lpc3220-hsuart";
201 reg = <0x40018000 0x1000>; 223 reg = <0x40018000 0x1000>;
224 interrupts = <25 0>;
225 status = "disabled";
202 }; 226 };
203 227
204 uart7: serial@4001C000 { 228 uart7: serial@4001c000 {
205 compatible = "nxp,serial"; 229 compatible = "nxp,lpc3220-hsuart";
206 reg = <0x4001C000 0x1000>; 230 reg = <0x4001c000 0x1000>;
231 interrupts = <24 0>;
232 status = "disabled";
207 }; 233 };
208 234
209 rtc@40024000 { 235 rtc@40024000 {
@@ -235,19 +261,21 @@
235 compatible = "nxp,lpc3220-adc"; 261 compatible = "nxp,lpc3220-adc";
236 reg = <0x40048000 0x1000>; 262 reg = <0x40048000 0x1000>;
237 interrupts = <0x27 0>; 263 interrupts = <0x27 0>;
238 status = "disable"; 264 status = "disabled";
239 }; 265 };
240 266
241 tsc@40048000 { 267 tsc@40048000 {
242 compatible = "nxp,lpc3220-tsc"; 268 compatible = "nxp,lpc3220-tsc";
243 reg = <0x40048000 0x1000>; 269 reg = <0x40048000 0x1000>;
244 interrupts = <0x27 0>; 270 interrupts = <0x27 0>;
245 status = "disable"; 271 status = "disabled";
246 }; 272 };
247 273
248 key@40050000 { 274 key@40050000 {
249 compatible = "nxp,lpc3220-key"; 275 compatible = "nxp,lpc3220-key";
250 reg = <0x40050000 0x1000>; 276 reg = <0x40050000 0x1000>;
277 interrupts = <54 0>;
278 status = "disabled";
251 }; 279 };
252 280
253 }; 281 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index c4ff6d1a018b..802ec5b2fd00 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -54,6 +54,17 @@
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <1>; 55 #size-cells = <1>;
56 56
57 nxp,wdr-clks = <14>;
58 nxp,wwidth = <40000000>;
59 nxp,whold = <100000000>;
60 nxp,wsetup = <100000000>;
61 nxp,rdr-clks = <14>;
62 nxp,rwidth = <40000000>;
63 nxp,rhold = <66666666>;
64 nxp,rsetup = <100000000>;
65 nand-on-flash-bbt;
66 gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
67
57 mtd0@00000000 { 68 mtd0@00000000 {
58 label = "phy3250-boot"; 69 label = "phy3250-boot";
59 reg = <0x00000000 0x00064000>; 70 reg = <0x00000000 0x00064000>;
@@ -83,6 +94,14 @@
83 }; 94 };
84 95
85 apb { 96 apb {
97 uart5: serial@40090000 {
98 status = "okay";
99 };
100
101 uart3: serial@40080000 {
102 status = "okay";
103 };
104
86 i2c1: i2c@400A0000 { 105 i2c1: i2c@400A0000 {
87 clock-frequency = <100000>; 106 clock-frequency = <100000>;
88 107
@@ -114,16 +133,58 @@
114 }; 133 };
115 134
116 ssp0: ssp@20084000 { 135 ssp0: ssp@20084000 {
136 #address-cells = <1>;
137 #size-cells = <0>;
138 pl022,num-chipselects = <1>;
139 cs-gpios = <&gpio 3 5 0>;
140
117 eeprom: at25@0 { 141 eeprom: at25@0 {
142 pl022,hierarchy = <0>;
143 pl022,interface = <0>;
144 pl022,slave-tx-disable = <0>;
145 pl022,com-mode = <0>;
146 pl022,rx-level-trig = <1>;
147 pl022,tx-level-trig = <1>;
148 pl022,ctrl-len = <11>;
149 pl022,wait-state = <0>;
150 pl022,duplex = <0>;
151
152 at25,byte-len = <0x8000>;
153 at25,addr-mode = <2>;
154 at25,page-size = <64>;
155
118 compatible = "atmel,at25"; 156 compatible = "atmel,at25";
157 reg = <0>;
158 spi-max-frequency = <5000000>;
119 }; 159 };
120 }; 160 };
161
162 sd@20098000 {
163 wp-gpios = <&gpio 3 0 0>;
164 cd-gpios = <&gpio 3 1 0>;
165 cd-inverted;
166 bus-width = <4>;
167 status = "okay";
168 };
121 }; 169 };
122 170
123 fab { 171 fab {
172 uart2: serial@40018000 {
173 status = "okay";
174 };
175
124 tsc@40048000 { 176 tsc@40048000 {
125 status = "okay"; 177 status = "okay";
126 }; 178 };
179
180 key@40050000 {
181 status = "okay";
182 keypad,num-rows = <1>;
183 keypad,num-columns = <1>;
184 nxp,debounce-delay-ms = <3>;
185 nxp,scan-delay-ms = <34>;
186 linux,keymap = <0x00000002>;
187 };
127 }; 188 };
128 }; 189 };
129 190
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 4fa60547494a..eceed186a3c1 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,5 +1,7 @@
1CONFIG_EXPERIMENTAL=y 1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y
3CONFIG_IKCONFIG=y 5CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y 6CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16 7CONFIG_LOG_BUF_SHIFT=16
@@ -16,8 +18,6 @@ CONFIG_MODULE_UNLOAD=y
16# CONFIG_BLK_DEV_BSG is not set 18# CONFIG_BLK_DEV_BSG is not set
17CONFIG_PARTITION_ADVANCED=y 19CONFIG_PARTITION_ADVANCED=y
18CONFIG_ARCH_LPC32XX=y 20CONFIG_ARCH_LPC32XX=y
19CONFIG_NO_HZ=y
20CONFIG_HIGH_RES_TIMERS=y
21CONFIG_PREEMPT=y 21CONFIG_PREEMPT=y
22CONFIG_AEABI=y 22CONFIG_AEABI=y
23CONFIG_ZBOOT_ROM_TEXT=0x0 23CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -52,13 +52,17 @@ CONFIG_MTD=y
52CONFIG_MTD_CMDLINE_PARTS=y 52CONFIG_MTD_CMDLINE_PARTS=y
53CONFIG_MTD_CHAR=y 53CONFIG_MTD_CHAR=y
54CONFIG_MTD_BLOCK=y 54CONFIG_MTD_BLOCK=y
55CONFIG_MTD_M25P80=y
55CONFIG_MTD_NAND=y 56CONFIG_MTD_NAND=y
56CONFIG_MTD_NAND_MUSEUM_IDS=y 57CONFIG_MTD_NAND_MUSEUM_IDS=y
58CONFIG_MTD_NAND_SLC_LPC32XX=y
59CONFIG_MTD_NAND_MLC_LPC32XX=y
57CONFIG_BLK_DEV_LOOP=y 60CONFIG_BLK_DEV_LOOP=y
58CONFIG_BLK_DEV_CRYPTOLOOP=y 61CONFIG_BLK_DEV_CRYPTOLOOP=y
59CONFIG_BLK_DEV_RAM=y 62CONFIG_BLK_DEV_RAM=y
60CONFIG_BLK_DEV_RAM_COUNT=1 63CONFIG_BLK_DEV_RAM_COUNT=1
61CONFIG_BLK_DEV_RAM_SIZE=16384 64CONFIG_BLK_DEV_RAM_SIZE=16384
65CONFIG_EEPROM_AT24=y
62CONFIG_EEPROM_AT25=y 66CONFIG_EEPROM_AT25=y
63CONFIG_SCSI=y 67CONFIG_SCSI=y
64CONFIG_BLK_DEV_SD=y 68CONFIG_BLK_DEV_SD=y
@@ -79,16 +83,22 @@ CONFIG_LPC_ENET=y
79# CONFIG_NET_VENDOR_STMICRO is not set 83# CONFIG_NET_VENDOR_STMICRO is not set
80CONFIG_SMSC_PHY=y 84CONFIG_SMSC_PHY=y
81# CONFIG_WLAN is not set 85# CONFIG_WLAN is not set
86CONFIG_INPUT_MATRIXKMAP=y
82# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 87# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
83CONFIG_INPUT_MOUSEDEV_SCREEN_X=240 88CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
84CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320 89CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
85CONFIG_INPUT_EVDEV=y 90CONFIG_INPUT_EVDEV=y
91# CONFIG_KEYBOARD_ATKBD is not set
92CONFIG_KEYBOARD_LPC32XX=y
86# CONFIG_INPUT_MOUSE is not set 93# CONFIG_INPUT_MOUSE is not set
87CONFIG_INPUT_TOUCHSCREEN=y 94CONFIG_INPUT_TOUCHSCREEN=y
88CONFIG_TOUCHSCREEN_LPC32XX=y 95CONFIG_TOUCHSCREEN_LPC32XX=y
96CONFIG_SERIO_LIBPS2=y
89# CONFIG_LEGACY_PTYS is not set 97# CONFIG_LEGACY_PTYS is not set
90CONFIG_SERIAL_8250=y 98CONFIG_SERIAL_8250=y
91CONFIG_SERIAL_8250_CONSOLE=y 99CONFIG_SERIAL_8250_CONSOLE=y
100CONFIG_SERIAL_HS_LPC32XX=y
101CONFIG_SERIAL_OF_PLATFORM=y
92# CONFIG_HW_RANDOM is not set 102# CONFIG_HW_RANDOM is not set
93CONFIG_I2C=y 103CONFIG_I2C=y
94CONFIG_I2C_CHARDEV=y 104CONFIG_I2C_CHARDEV=y
@@ -96,7 +106,8 @@ CONFIG_I2C_PNX=y
96CONFIG_SPI=y 106CONFIG_SPI=y
97CONFIG_SPI_PL022=y 107CONFIG_SPI_PL022=y
98CONFIG_GPIO_SYSFS=y 108CONFIG_GPIO_SYSFS=y
99# CONFIG_HWMON is not set 109CONFIG_SENSORS_DS620=y
110CONFIG_SENSORS_MAX6639=y
100CONFIG_WATCHDOG=y 111CONFIG_WATCHDOG=y
101CONFIG_PNX4008_WATCHDOG=y 112CONFIG_PNX4008_WATCHDOG=y
102CONFIG_FB=y 113CONFIG_FB=y
@@ -133,6 +144,8 @@ CONFIG_MMC=y
133CONFIG_MMC_ARMMMCI=y 144CONFIG_MMC_ARMMMCI=y
134CONFIG_NEW_LEDS=y 145CONFIG_NEW_LEDS=y
135CONFIG_LEDS_CLASS=y 146CONFIG_LEDS_CLASS=y
147CONFIG_LEDS_PCA9532=y
148CONFIG_LEDS_PCA9532_GPIO=y
136CONFIG_LEDS_GPIO=y 149CONFIG_LEDS_GPIO=y
137CONFIG_LEDS_TRIGGERS=y 150CONFIG_LEDS_TRIGGERS=y
138CONFIG_LEDS_TRIGGER_TIMER=y 151CONFIG_LEDS_TRIGGER_TIMER=y
@@ -146,10 +159,10 @@ CONFIG_RTC_DRV_DS1374=y
146CONFIG_RTC_DRV_PCF8563=y 159CONFIG_RTC_DRV_PCF8563=y
147CONFIG_RTC_DRV_LPC32XX=y 160CONFIG_RTC_DRV_LPC32XX=y
148CONFIG_DMADEVICES=y 161CONFIG_DMADEVICES=y
149CONFIG_AMBA_PL08X=y
150CONFIG_STAGING=y 162CONFIG_STAGING=y
151CONFIG_IIO=y
152CONFIG_LPC32XX_ADC=y 163CONFIG_LPC32XX_ADC=y
164CONFIG_MAX517=y
165CONFIG_IIO=y
153CONFIG_EXT2_FS=y 166CONFIG_EXT2_FS=y
154CONFIG_AUTOFS4_FS=y 167CONFIG_AUTOFS4_FS=y
155CONFIG_MSDOS_FS=y 168CONFIG_MSDOS_FS=y
@@ -159,7 +172,6 @@ CONFIG_JFFS2_FS=y
159CONFIG_JFFS2_FS_WBUF_VERIFY=y 172CONFIG_JFFS2_FS_WBUF_VERIFY=y
160CONFIG_CRAMFS=y 173CONFIG_CRAMFS=y
161CONFIG_NFS_FS=y 174CONFIG_NFS_FS=y
162CONFIG_NFS_V3=y
163CONFIG_ROOT_NFS=y 175CONFIG_ROOT_NFS=y
164CONFIG_NLS_CODEPAGE_437=y 176CONFIG_NLS_CODEPAGE_437=y
165CONFIG_NLS_ASCII=y 177CONFIG_NLS_ASCII=y
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
deleted file mode 100644
index e0b3eee83834..000000000000
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
1if ARCH_LPC32XX
2
3menu "Individual UART enable selections"
4
5config ARCH_LPC32XX_UART3_SELECT
6 bool "Add support for standard UART3"
7 help
8 Adds support for standard UART 3 when the 8250 serial support
9 is enabled.
10
11config ARCH_LPC32XX_UART4_SELECT
12 bool "Add support for standard UART4"
13 help
14 Adds support for standard UART 4 when the 8250 serial support
15 is enabled.
16
17config ARCH_LPC32XX_UART5_SELECT
18 bool "Add support for standard UART5"
19 default y
20 help
21 Adds support for standard UART 5 when the 8250 serial support
22 is enabled.
23
24config ARCH_LPC32XX_UART6_SELECT
25 bool "Add support for standard UART6"
26 help
27 Adds support for standard UART 6 when the 8250 serial support
28 is enabled.
29
30endmenu
31
32endif
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
index 2cfe0ee635c5..697323b5f92d 100644
--- a/arch/arm/mach-lpc32xx/Makefile.boot
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -2,3 +2,4 @@
2params_phys-y := 0x80000100 2params_phys-y := 0x80000100
3initrd_phys-y := 0x82000000 3initrd_phys-y := 0x82000000
4 4
5dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f6a3ffec1f4b..e8d315e6db09 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -691,10 +691,21 @@ static struct clk clk_nand = {
691 .parent = &clk_hclk, 691 .parent = &clk_hclk,
692 .enable = local_onoff_enable, 692 .enable = local_onoff_enable,
693 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL, 693 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
694 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN, 694 .enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
695 LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
695 .get_rate = local_return_parent_rate, 696 .get_rate = local_return_parent_rate,
696}; 697};
697 698
699static struct clk clk_nand_mlc = {
700 .parent = &clk_hclk,
701 .enable = local_onoff_enable,
702 .enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
703 .enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
704 LPC32XX_CLKPWR_NANDCLK_DMA_INT |
705 LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
706 .get_rate = local_return_parent_rate,
707};
708
698static struct clk clk_i2s0 = { 709static struct clk clk_i2s0 = {
699 .parent = &clk_hclk, 710 .parent = &clk_hclk,
700 .enable = local_onoff_enable, 711 .enable = local_onoff_enable,
@@ -707,7 +718,8 @@ static struct clk clk_i2s1 = {
707 .parent = &clk_hclk, 718 .parent = &clk_hclk,
708 .enable = local_onoff_enable, 719 .enable = local_onoff_enable,
709 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL, 720 .enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
710 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN, 721 .enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
722 LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
711 .get_rate = local_return_parent_rate, 723 .get_rate = local_return_parent_rate,
712}; 724};
713 725
@@ -1120,8 +1132,9 @@ static struct clk_lookup lookups[] = {
1120 CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2), 1132 CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
1121 CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0), 1133 CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
1122 CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1), 1134 CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
1123 CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan), 1135 CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
1124 CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand), 1136 CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
1137 CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
1125 CLKDEV_INIT("40048000.adc", NULL, &clk_adc), 1138 CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
1126 CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0), 1139 CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
1127 CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1), 1140 CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 2ba6ca412bef..0052e7a76179 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -3,6 +3,4 @@
3 3
4#include "gpio-lpc32xx.h" 4#include "gpio-lpc32xx.h"
5 5
6#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
7
8#endif /* __MACH_GPIO_H */ 6#endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 540106cdb9ec..c1aabfcbde49 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -30,12 +30,13 @@
30#include <linux/amba/bus.h> 30#include <linux/amba/bus.h>
31#include <linux/amba/clcd.h> 31#include <linux/amba/clcd.h>
32#include <linux/amba/pl022.h> 32#include <linux/amba/pl022.h>
33#include <linux/amba/pl08x.h>
34#include <linux/amba/mmci.h>
33#include <linux/of.h> 35#include <linux/of.h>
34#include <linux/of_address.h> 36#include <linux/of_address.h>
35#include <linux/of_irq.h> 37#include <linux/of_irq.h>
36#include <linux/of_platform.h> 38#include <linux/of_platform.h>
37#include <linux/clk.h> 39#include <linux/clk.h>
38#include <linux/amba/pl08x.h>
39 40
40#include <asm/setup.h> 41#include <asm/setup.h>
41#include <asm/mach-types.h> 42#include <asm/mach-types.h>
@@ -50,9 +51,12 @@
50/* 51/*
51 * Mapped GPIOLIB GPIOs 52 * Mapped GPIOLIB GPIOs
52 */ 53 */
53#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5) 54#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
54#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0) 55#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
55#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4) 56#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
57#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
58#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
59#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
56 60
57/* 61/*
58 * AMBA LCD controller 62 * AMBA LCD controller
@@ -158,24 +162,6 @@ static struct clcd_board lpc32xx_clcd_data = {
158/* 162/*
159 * AMBA SSP (SPI) 163 * AMBA SSP (SPI)
160 */ 164 */
161static void phy3250_spi_cs_set(u32 control)
162{
163 gpio_set_value(SPI0_CS_GPIO, (int) control);
164}
165
166static struct pl022_config_chip spi0_chip_info = {
167 .com_mode = INTERRUPT_TRANSFER,
168 .iface = SSP_INTERFACE_MOTOROLA_SPI,
169 .hierarchy = SSP_MASTER,
170 .slave_tx_disable = 0,
171 .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
172 .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
173 .ctrl_len = SSP_BITS_8,
174 .wait_state = SSP_MWIRE_WAIT_ZERO,
175 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
176 .cs_control = phy3250_spi_cs_set,
177};
178
179static struct pl022_ssp_controller lpc32xx_ssp0_data = { 165static struct pl022_ssp_controller lpc32xx_ssp0_data = {
180 .bus_id = 0, 166 .bus_id = 0,
181 .num_chipselect = 1, 167 .num_chipselect = 1,
@@ -188,45 +174,57 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = {
188 .enable_dma = 0, 174 .enable_dma = 0,
189}; 175};
190 176
191/* AT25 driver registration */ 177static struct pl08x_channel_data pl08x_slave_channels[] = {
192static int __init phy3250_spi_board_register(void) 178 {
179 .bus_id = "nand-slc",
180 .min_signal = 1, /* SLC NAND Flash */
181 .max_signal = 1,
182 .periph_buses = PL08X_AHB1,
183 },
184 {
185 .bus_id = "nand-mlc",
186 .min_signal = 12, /* MLC NAND Flash */
187 .max_signal = 12,
188 .periph_buses = PL08X_AHB1,
189 },
190};
191
192/* NOTE: These will change, according to RMK */
193static int pl08x_get_signal(struct pl08x_dma_chan *ch)
194{
195 return ch->cd->min_signal;
196}
197
198static void pl08x_put_signal(struct pl08x_dma_chan *ch)
193{ 199{
194#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
195 static struct spi_board_info info[] = {
196 {
197 .modalias = "spidev",
198 .max_speed_hz = 5000000,
199 .bus_num = 0,
200 .chip_select = 0,
201 .controller_data = &spi0_chip_info,
202 },
203 };
204
205#else
206 static struct spi_eeprom eeprom = {
207 .name = "at25256a",
208 .byte_len = 0x8000,
209 .page_size = 64,
210 .flags = EE_ADDR2,
211 };
212
213 static struct spi_board_info info[] = {
214 {
215 .modalias = "at25",
216 .max_speed_hz = 5000000,
217 .bus_num = 0,
218 .chip_select = 0,
219 .mode = SPI_MODE_0,
220 .platform_data = &eeprom,
221 .controller_data = &spi0_chip_info,
222 },
223 };
224#endif
225 return spi_register_board_info(info, ARRAY_SIZE(info));
226} 200}
227arch_initcall(phy3250_spi_board_register);
228 201
229static struct pl08x_platform_data pl08x_pd = { 202static struct pl08x_platform_data pl08x_pd = {
203 .slave_channels = &pl08x_slave_channels[0],
204 .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
205 .get_signal = pl08x_get_signal,
206 .put_signal = pl08x_put_signal,
207 .lli_buses = PL08X_AHB1,
208 .mem_buses = PL08X_AHB1,
209};
210
211static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
212{
213 /* Only on and off are supported */
214 if (ios->power_mode == MMC_POWER_OFF)
215 gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
216 else
217 gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
218 return 0;
219}
220
221static struct mmci_platform_data lpc32xx_mmci_data = {
222 .ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
223 MMC_VDD_32_33 | MMC_VDD_33_34,
224 .ios_handler = mmc_handle_ios,
225 .dma_filter = NULL,
226 /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
227 * gather, and the MMCI driver doesn't do it this way */
230}; 228};
231 229
232static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = { 230static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
@@ -234,6 +232,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
234 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data), 232 OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
235 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data), 233 OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
236 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd), 234 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
235 OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
236 &lpc32xx_mmci_data),
237 { } 237 { }
238}; 238};
239 239
@@ -241,10 +241,6 @@ static void __init lpc3250_machine_init(void)
241{ 241{
242 u32 tmp; 242 u32 tmp;
243 243
244 /* Setup SLC NAND controller muxing */
245 __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
246 LPC32XX_CLKPWR_NAND_CLK_CTRL);
247
248 /* Setup LCD muxing to RGB565 */ 244 /* Setup LCD muxing to RGB565 */
249 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) & 245 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
250 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK | 246 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
@@ -264,34 +260,12 @@ static void __init lpc3250_machine_init(void)
264 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE; 260 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
265 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL); 261 __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
266 262
267 /* Disable IrDA pulsing support on UART6 */
268 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
269 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
270 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
271
272 /* Enable DMA for I2S1 channel */
273 tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
274 tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
275 __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
276
277 lpc32xx_serial_init(); 263 lpc32xx_serial_init();
278 264
279 /* 265 tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
280 * AMBA peripheral clocks need to be enabled prior to AMBA device 266 tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
281 * detection or a data fault will occur, so enable the clocks 267 LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
282 * here. 268 __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
283 */
284 tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
285 __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
286 LPC32XX_CLKPWR_LCDCLK_CTRL);
287
288 tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
289 __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
290 LPC32XX_CLKPWR_SSP_CLK_CTRL);
291
292 tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
293 __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
294 LPC32XX_CLKPWR_DMA_CLK_CTRL);
295 269
296 /* Test clock needed for UDA1380 initial init */ 270 /* Test clock needed for UDA1380 initial init */
297 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC | 271 __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
@@ -302,12 +276,10 @@ static void __init lpc3250_machine_init(void)
302 lpc32xx_auxdata_lookup, NULL); 276 lpc32xx_auxdata_lookup, NULL);
303 277
304 /* Register GPIOs used on this board */ 278 /* Register GPIOs used on this board */
305 if (gpio_request(SPI0_CS_GPIO, "spi0 cs")) 279 if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
306 printk(KERN_ERR "Error requesting gpio %u", 280 pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
307 SPI0_CS_GPIO); 281 else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
308 else if (gpio_direction_output(SPI0_CS_GPIO, 1)) 282 pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
309 printk(KERN_ERR "Error setting gpio %u to output",
310 SPI0_CS_GPIO);
311} 283}
312 284
313static char const *lpc32xx_dt_compat[] __initdata = { 285static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index f2735281616a..05621a29fba2 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -31,59 +31,6 @@
31 31
32#define LPC32XX_SUART_FIFO_SIZE 64 32#define LPC32XX_SUART_FIFO_SIZE 64
33 33
34/* Standard 8250/16550 compatible serial ports */
35static struct plat_serial8250_port serial_std_platform_data[] = {
36#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
37 {
38 .membase = io_p2v(LPC32XX_UART5_BASE),
39 .mapbase = LPC32XX_UART5_BASE,
40 .irq = IRQ_LPC32XX_UART_IIR5,
41 .uartclk = LPC32XX_MAIN_OSC_FREQ,
42 .regshift = 2,
43 .iotype = UPIO_MEM32,
44 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
45 UPF_SKIP_TEST,
46 },
47#endif
48#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
49 {
50 .membase = io_p2v(LPC32XX_UART3_BASE),
51 .mapbase = LPC32XX_UART3_BASE,
52 .irq = IRQ_LPC32XX_UART_IIR3,
53 .uartclk = LPC32XX_MAIN_OSC_FREQ,
54 .regshift = 2,
55 .iotype = UPIO_MEM32,
56 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
57 UPF_SKIP_TEST,
58 },
59#endif
60#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
61 {
62 .membase = io_p2v(LPC32XX_UART4_BASE),
63 .mapbase = LPC32XX_UART4_BASE,
64 .irq = IRQ_LPC32XX_UART_IIR4,
65 .uartclk = LPC32XX_MAIN_OSC_FREQ,
66 .regshift = 2,
67 .iotype = UPIO_MEM32,
68 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
69 UPF_SKIP_TEST,
70 },
71#endif
72#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
73 {
74 .membase = io_p2v(LPC32XX_UART6_BASE),
75 .mapbase = LPC32XX_UART6_BASE,
76 .irq = IRQ_LPC32XX_UART_IIR6,
77 .uartclk = LPC32XX_MAIN_OSC_FREQ,
78 .regshift = 2,
79 .iotype = UPIO_MEM32,
80 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
81 UPF_SKIP_TEST,
82 },
83#endif
84 { },
85};
86
87struct uartinit { 34struct uartinit {
88 char *uart_ck_name; 35 char *uart_ck_name;
89 u32 ck_mode_mask; 36 u32 ck_mode_mask;
@@ -92,7 +39,6 @@ struct uartinit {
92}; 39};
93 40
94static struct uartinit uartinit_data[] __initdata = { 41static struct uartinit uartinit_data[] __initdata = {
95#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
96 { 42 {
97 .uart_ck_name = "uart5_ck", 43 .uart_ck_name = "uart5_ck",
98 .ck_mode_mask = 44 .ck_mode_mask =
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = {
100 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL, 46 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
101 .mapbase = LPC32XX_UART5_BASE, 47 .mapbase = LPC32XX_UART5_BASE,
102 }, 48 },
103#endif
104#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
105 { 49 {
106 .uart_ck_name = "uart3_ck", 50 .uart_ck_name = "uart3_ck",
107 .ck_mode_mask = 51 .ck_mode_mask =
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = {
109 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL, 53 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
110 .mapbase = LPC32XX_UART3_BASE, 54 .mapbase = LPC32XX_UART3_BASE,
111 }, 55 },
112#endif
113#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
114 { 56 {
115 .uart_ck_name = "uart4_ck", 57 .uart_ck_name = "uart4_ck",
116 .ck_mode_mask = 58 .ck_mode_mask =
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = {
118 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL, 60 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
119 .mapbase = LPC32XX_UART4_BASE, 61 .mapbase = LPC32XX_UART4_BASE,
120 }, 62 },
121#endif
122#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
123 { 63 {
124 .uart_ck_name = "uart6_ck", 64 .uart_ck_name = "uart6_ck",
125 .ck_mode_mask = 65 .ck_mode_mask =
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = {
127 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL, 67 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
128 .mapbase = LPC32XX_UART6_BASE, 68 .mapbase = LPC32XX_UART6_BASE,
129 }, 69 },
130#endif
131};
132
133static struct platform_device serial_std_platform_device = {
134 .name = "serial8250",
135 .id = 0,
136 .dev = {
137 .platform_data = serial_std_platform_data,
138 },
139};
140
141static struct platform_device *lpc32xx_serial_devs[] __initdata = {
142 &serial_std_platform_device,
143}; 70};
144 71
145void __init lpc32xx_serial_init(void) 72void __init lpc32xx_serial_init(void)
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
156 clk = clk_get(NULL, uartinit_data[i].uart_ck_name); 83 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
157 if (!IS_ERR(clk)) { 84 if (!IS_ERR(clk)) {
158 clk_enable(clk); 85 clk_enable(clk);
159 serial_std_platform_data[i].uartclk =
160 clk_get_rate(clk);
161 } 86 }
162 87
163 /* Fall back on main osc rate if clock rate return fails */
164 if (serial_std_platform_data[i].uartclk == 0)
165 serial_std_platform_data[i].uartclk =
166 LPC32XX_MAIN_OSC_FREQ;
167
168 /* Setup UART clock modes for all UARTs, disable autoclock */ 88 /* Setup UART clock modes for all UARTs, disable autoclock */
169 clkmodes |= uartinit_data[i].ck_mode_mask; 89 clkmodes |= uartinit_data[i].ck_mode_mask;
170 90
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
189 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); 109 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
190 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) { 110 for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
191 /* Force a flush of the RX FIFOs to work around a HW bug */ 111 /* Force a flush of the RX FIFOs to work around a HW bug */
192 puart = serial_std_platform_data[i].mapbase; 112 puart = uartinit_data[i].mapbase;
193 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); 113 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
194 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); 114 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
195 j = LPC32XX_SUART_FIFO_SIZE; 115 j = LPC32XX_SUART_FIFO_SIZE;
@@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void)
198 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); 118 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
199 } 119 }
200 120
121 /* Disable IrDA pulsing support on UART6 */
122 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
123 tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
124 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
125
201 /* Disable UART5->USB transparent mode or USB won't work */ 126 /* Disable UART5->USB transparent mode or USB won't work */
202 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL); 127 tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
203 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB; 128 tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
204 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); 129 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
205
206 platform_add_devices(lpc32xx_serial_devs,
207 ARRAY_SIZE(lpc32xx_serial_devs));
208} 130}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-09 17:03:16 -0500