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authorPawel Moll <pawel.moll@arm.com>2011-12-09 13:47:39 -0500
committerPawel Moll <pawel.moll@arm.com>2012-02-24 04:18:20 -0500
commit6a3719562b69ffdfc36e829e19b35fda6ab19ca6 (patch)
tree0eb75a57e5f7b54d51d14c315f15cbc1433e2ee7 /arch
parent8deed1786a6479d0ccda51226582920ab1d6976c (diff)
ARM: vexpress: Motherboard RS1 memory map support
This patch adds support for RS1 memory map based Versatile Express motherboard. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi201
-rw-r--r--arch/arm/mach-vexpress/include/mach/debug-macro.S30
-rw-r--r--arch/arm/mach-vexpress/include/mach/uncompress.h22
-rw-r--r--arch/arm/mach-vexpress/v2m.c62
4 files changed, 309 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
new file mode 100644
index 000000000000..16076e2d0934
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -0,0 +1,201 @@
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20/ {
21 aliases {
22 arm,v2m_timer = &v2m_timer01;
23 };
24
25 motherboard {
26 compatible = "simple-bus";
27 arm,v2m-memory-map = "rs1";
28 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>;
30 #interrupt-cells = <1>;
31
32 flash@0,00000000 {
33 compatible = "arm,vexpress-flash", "cfi-flash";
34 reg = <0 0x00000000 0x04000000>,
35 <4 0x00000000 0x04000000>;
36 bank-width = <4>;
37 };
38
39 psram@1,00000000 {
40 compatible = "arm,vexpress-psram", "mtd-ram";
41 reg = <1 0x00000000 0x02000000>;
42 bank-width = <4>;
43 };
44
45 vram@2,00000000 {
46 compatible = "arm,vexpress-vram";
47 reg = <2 0x00000000 0x00800000>;
48 };
49
50 ethernet@2,02000000 {
51 compatible = "smsc,lan9118", "smsc,lan9115";
52 reg = <2 0x02000000 0x10000>;
53 interrupts = <15>;
54 phy-mode = "mii";
55 reg-io-width = <4>;
56 smsc,irq-active-high;
57 smsc,irq-push-pull;
58 };
59
60 usb@2,03000000 {
61 compatible = "nxp,usb-isp1761";
62 reg = <2 0x03000000 0x20000>;
63 interrupts = <16>;
64 port1-otg;
65 };
66
67 iofpga@3,00000000 {
68 compatible = "arm,amba-bus", "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 3 0 0x200000>;
72
73 sysreg@010000 {
74 compatible = "arm,vexpress-sysreg";
75 reg = <0x010000 0x1000>;
76 };
77
78 sysctl@020000 {
79 compatible = "arm,sp810", "arm,primecell";
80 reg = <0x020000 0x1000>;
81 };
82
83 /* PCI-E I2C bus */
84 v2m_i2c_pcie: i2c@030000 {
85 compatible = "arm,versatile-i2c";
86 reg = <0x030000 0x1000>;
87
88 #address-cells = <1>;
89 #size-cells = <0>;
90
91 pcie-switch@60 {
92 compatible = "idt,89hpes32h8";
93 reg = <0x60>;
94 };
95 };
96
97 aaci@040000 {
98 compatible = "arm,pl041", "arm,primecell";
99 reg = <0x040000 0x1000>;
100 interrupts = <11>;
101 };
102
103 mmci@050000 {
104 compatible = "arm,pl180", "arm,primecell";
105 reg = <0x050000 0x1000>;
106 interrupts = <9 10>;
107 };
108
109 kmi@060000 {
110 compatible = "arm,pl050", "arm,primecell";
111 reg = <0x060000 0x1000>;
112 interrupts = <12>;
113 };
114
115 kmi@070000 {
116 compatible = "arm,pl050", "arm,primecell";
117 reg = <0x070000 0x1000>;
118 interrupts = <13>;
119 };
120
121 v2m_serial0: uart@090000 {
122 compatible = "arm,pl011", "arm,primecell";
123 reg = <0x090000 0x1000>;
124 interrupts = <5>;
125 };
126
127 v2m_serial1: uart@0a0000 {
128 compatible = "arm,pl011", "arm,primecell";
129 reg = <0x0a0000 0x1000>;
130 interrupts = <6>;
131 };
132
133 v2m_serial2: uart@0b0000 {
134 compatible = "arm,pl011", "arm,primecell";
135 reg = <0x0b0000 0x1000>;
136 interrupts = <7>;
137 };
138
139 v2m_serial3: uart@0c0000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0x0c0000 0x1000>;
142 interrupts = <8>;
143 };
144
145 wdt@0f0000 {
146 compatible = "arm,sp805", "arm,primecell";
147 reg = <0x0f0000 0x1000>;
148 interrupts = <0>;
149 };
150
151 v2m_timer01: timer@110000 {
152 compatible = "arm,sp804", "arm,primecell";
153 reg = <0x110000 0x1000>;
154 interrupts = <2>;
155 };
156
157 v2m_timer23: timer@120000 {
158 compatible = "arm,sp804", "arm,primecell";
159 reg = <0x120000 0x1000>;
160 };
161
162 /* DVI I2C bus */
163 v2m_i2c_dvi: i2c@160000 {
164 compatible = "arm,versatile-i2c";
165 reg = <0x160000 0x1000>;
166
167 #address-cells = <1>;
168 #size-cells = <0>;
169
170 dvi-transmitter@39 {
171 compatible = "sil,sii9022-tpi", "sil,sii9022";
172 reg = <0x39>;
173 };
174
175 dvi-transmitter@60 {
176 compatible = "sil,sii9022-cpi", "sil,sii9022";
177 reg = <0x60>;
178 };
179 };
180
181 rtc@170000 {
182 compatible = "arm,pl031", "arm,primecell";
183 reg = <0x170000 0x1000>;
184 interrupts = <4>;
185 };
186
187 compact-flash@1a0000 {
188 compatible = "arm,vexpress-cf", "ata-generic";
189 reg = <0x1a0000 0x100
190 0x1a0100 0xf00>;
191 reg-shift = <2>;
192 };
193
194 clcd@1f0000 {
195 compatible = "arm,pl111", "arm,primecell";
196 reg = <0x1f0000 0x1000>;
197 interrupts = <14>;
198 };
199 };
200 };
201};
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fd9e6c7ea49f..fa8224794e0b 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -10,12 +10,34 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13#define DEBUG_LL_UART_OFFSET 0x00009000 13#define DEBUG_LL_PHYS_BASE 0x10000000
14#define DEBUG_LL_UART_OFFSET 0x00009000
15
16#define DEBUG_LL_PHYS_BASE_RS1 0x1c000000
17#define DEBUG_LL_UART_OFFSET_RS1 0x00090000
18
19#define DEBUG_LL_VIRT_BASE 0xf8000000
14 20
15 .macro addruart,rp,rv,tmp 21 .macro addruart,rp,rv,tmp
16 mov \rp, #DEBUG_LL_UART_OFFSET 22
17 orr \rv, \rp, #0xf8000000 @ virtual base 23 @ Make an educated guess regarding the memory map:
18 orr \rp, \rp, #0x10000000 @ physical base 24 @ - the original A9 core tile, which has MPCore peripherals
25 @ located at 0x1e000000, should use UART at 0x10009000
26 @ - all other (RS1 complaint) tiles use UART mapped
27 @ at 0x1c090000
28 mrc p15, 4, \tmp, c15, c0, 0
29 cmp \tmp, #0x1e000000
30
31 @ Original memory map
32 moveq \rp, #DEBUG_LL_UART_OFFSET
33 orreq \rv, \rp, #DEBUG_LL_VIRT_BASE
34 orreq \rp, \rp, #DEBUG_LL_PHYS_BASE
35
36 @ RS1 memory map
37 movne \rp, #DEBUG_LL_UART_OFFSET_RS1
38 orrne \rv, \rp, #DEBUG_LL_VIRT_BASE
39 orrne \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
40
19 .endm 41 .endm
20 42
21#include <asm/hardware/debug-pl01x.S> 43#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7972c5748d0e..7dab5596b868 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -22,7 +22,27 @@
22#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30)) 22#define AMBA_UART_CR(base) (*(volatile unsigned char *)((base) + 0x30))
23#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18)) 23#define AMBA_UART_FR(base) (*(volatile unsigned char *)((base) + 0x18))
24 24
25#define get_uart_base() (0x10000000 + 0x00009000) 25#define UART_BASE 0x10009000
26#define UART_BASE_RS1 0x1c090000
27
28static unsigned long get_uart_base(void)
29{
30 unsigned long mpcore_periph;
31
32 /*
33 * Make an educated guess regarding the memory map:
34 * - the original A9 core tile, which has MPCore peripherals
35 * located at 0x1e000000, should use UART at 0x10009000
36 * - all other (RS1 complaint) tiles use UART mapped
37 * at 0x1c090000
38 */
39 asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (mpcore_periph));
40
41 if (mpcore_periph == 0x1e000000)
42 return UART_BASE;
43 else
44 return UART_BASE_RS1;
45}
26 46
27/* 47/*
28 * This does not append a newline 48 * This does not append a newline
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index dbf055103000..9cab5417e5df 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -486,9 +486,36 @@ MACHINE_END
486 486
487#if defined(CONFIG_ARCH_VEXPRESS_DT) 487#if defined(CONFIG_ARCH_VEXPRESS_DT)
488 488
489static struct map_desc v2m_rs1_io_desc __initdata = {
490 .virtual = V2M_PERIPH,
491 .pfn = __phys_to_pfn(0x1c000000),
492 .length = SZ_2M,
493 .type = MT_DEVICE,
494};
495
496static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
497 int depth, void *data)
498{
499 const char **map = data;
500
501 if (strcmp(uname, "motherboard") != 0)
502 return 0;
503
504 *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
505
506 return 1;
507}
508
489void __init v2m_dt_map_io(void) 509void __init v2m_dt_map_io(void)
490{ 510{
491 iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc)); 511 const char *map = NULL;
512
513 of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
514
515 if (map && strcmp(map, "rs1") == 0)
516 iotable_init(&v2m_rs1_io_desc, 1);
517 else
518 iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
492 519
493#if defined(CONFIG_SMP) 520#if defined(CONFIG_SMP)
494 vexpress_dt_smp_map_io(); 521 vexpress_dt_smp_map_io();
@@ -535,6 +562,35 @@ static struct clk_lookup v2m_dt_lookups[] = {
535 .dev_id = "1001f000.clcd", 562 .dev_id = "1001f000.clcd",
536 .clk = &osc1_clk, 563 .clk = &osc1_clk,
537 }, 564 },
565 /* RS1 memory map */
566 { /* PL180 MMCI */
567 .dev_id = "mb:mmci", /* 1c050000.mmci */
568 .clk = &osc2_clk,
569 }, { /* PL050 KMI0 */
570 .dev_id = "1c060000.kmi",
571 .clk = &osc2_clk,
572 }, { /* PL050 KMI1 */
573 .dev_id = "1c070000.kmi",
574 .clk = &osc2_clk,
575 }, { /* PL011 UART0 */
576 .dev_id = "1c090000.uart",
577 .clk = &osc2_clk,
578 }, { /* PL011 UART1 */
579 .dev_id = "1c0a0000.uart",
580 .clk = &osc2_clk,
581 }, { /* PL011 UART2 */
582 .dev_id = "1c0b0000.uart",
583 .clk = &osc2_clk,
584 }, { /* PL011 UART3 */
585 .dev_id = "1c0c0000.uart",
586 .clk = &osc2_clk,
587 }, { /* SP805 WDT */
588 .dev_id = "1c0f0000.wdt",
589 .clk = &v2m_ref_clk,
590 }, { /* PL111 CLCD */
591 .dev_id = "1c1f0000.clcd",
592 .clk = &osc1_clk,
593 },
538}; 594};
539 595
540void __init v2m_dt_init_early(void) 596void __init v2m_dt_init_early(void)
@@ -597,6 +653,10 @@ static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
597 OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash", 653 OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
598 &v2m_flash_data), 654 &v2m_flash_data),
599 OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data), 655 OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
656 /* RS1 memory map */
657 OF_DEV_AUXDATA("arm,vexpress-flash", 0x08000000, "physmap-flash",
658 &v2m_flash_data),
659 OF_DEV_AUXDATA("arm,primecell", 0x1c050000, "mb:mmci", &v2m_mmci_data),
600 {} 660 {}
601}; 661};
602 662
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