diff options
author | Mark Mason <mason@broadcom.com> | 2006-10-10 20:03:10 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-10-11 14:30:59 -0400 |
commit | 472f291df59fc1c5eb3ade74a50bfa222030e736 (patch) | |
tree | 1ea4b1a03af63b7db42e71ab0366f227d0e5c78b /arch | |
parent | 9b95e629eab59ee140fe2b17bbd7fea6821c6085 (diff) |
[MIPS] Fix compilation warnings in arch/mips/sibyte/bcm1480/smp.c
Signed-off-by: Mark Mason <mason@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/sibyte/bcm1480/smp.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index 6eac36d1b8c8..bf328277c775 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c | |||
@@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void); | |||
34 | * independent of board/firmware | 34 | * independent of board/firmware |
35 | */ | 35 | */ |
36 | 36 | ||
37 | static void *mailbox_0_set_regs[] = { | 37 | static volatile void *mailbox_0_set_regs[] = { |
38 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 38 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
39 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 39 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
40 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 40 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
41 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), | 41 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), |
42 | }; | 42 | }; |
43 | 43 | ||
44 | static void *mailbox_0_clear_regs[] = { | 44 | static volatile void *mailbox_0_clear_regs[] = { |
45 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 45 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
46 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 46 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
47 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 47 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
48 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), | 48 | IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), |
49 | }; | 49 | }; |
50 | 50 | ||
51 | static void *mailbox_0_regs[] = { | 51 | static volatile void *mailbox_0_regs[] = { |
52 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), | 52 | IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |
53 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), | 53 | IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |
54 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), | 54 | IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |