diff options
author | Greg Ungerer <gerg@uclinux.org> | 2009-05-06 00:28:25 -0400 |
---|---|---|
committer | Greg Ungerer <gerg@uclinux.org> | 2009-09-15 19:43:48 -0400 |
commit | e47cc3d6acacffdc673779a44c21a4a12b20db23 (patch) | |
tree | c9ee91eaa1dcd12092e56b84deac38eae921e551 /arch | |
parent | 91b1b94f88219ea1b747264f4f6995a1202566cb (diff) |
m68knommu: mask off all interrupts in ColdFire intc-simr controller
The ColdFire intc-simr interrupt controller should mask off all
interrupt sources at init time. Doing it here instead of separately
in each platform setup.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/m68k/include/asm/m532xsim.h | 33 | ||||
-rw-r--r-- | arch/m68knommu/platform/coldfire/intc-simr.c | 5 |
2 files changed, 5 insertions, 33 deletions
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h index 41c57e0f445a..021a0e155270 100644 --- a/arch/m68k/include/asm/m532xsim.h +++ b/arch/m68k/include/asm/m532xsim.h | |||
@@ -56,8 +56,6 @@ | |||
56 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ | 56 | #define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ |
57 | 57 | ||
58 | 58 | ||
59 | #define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ | ||
60 | |||
61 | #define MCFINTC0_SIMR 0xFC04801C | 59 | #define MCFINTC0_SIMR 0xFC04801C |
62 | #define MCFINTC0_CIMR 0xFC04801D | 60 | #define MCFINTC0_CIMR 0xFC04801D |
63 | #define MCFINTC0_ICR0 0xFC048040 | 61 | #define MCFINTC0_ICR0 0xFC048040 |
@@ -70,37 +68,6 @@ | |||
70 | 68 | ||
71 | 69 | ||
72 | /* | 70 | /* |
73 | * Macro to set IMR register. It is 32 bits on the 5307. | ||
74 | */ | ||
75 | #define mcf_getimr() \ | ||
76 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) | ||
77 | |||
78 | #define mcf_setimr(imr) \ | ||
79 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); | ||
80 | |||
81 | #define mcf_getipr() \ | ||
82 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) | ||
83 | |||
84 | #define mcf_getiprl() \ | ||
85 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL)) | ||
86 | |||
87 | #define mcf_getiprh() \ | ||
88 | *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH)) | ||
89 | |||
90 | |||
91 | #define mcf_enable_irq0(irq) \ | ||
92 | *((volatile unsigned char *) (MCFINTC0_CIMR)) = (irq); | ||
93 | |||
94 | #define mcf_enable_irq1(irq) \ | ||
95 | *((volatile unsigned char *) (MCFINTC1_CIMR)) = (irq); | ||
96 | |||
97 | #define mcf_disable_irq0(irq) \ | ||
98 | *((volatile unsigned char *) (MCFINTC0_SIMR)) = (irq); | ||
99 | |||
100 | #define mcf_disable_irq1(irq) \ | ||
101 | *((volatile unsigned char *) (MCFINTC1_SIMR)) = (irq); | ||
102 | |||
103 | /* | ||
104 | * Define the Cache register flags. | 71 | * Define the Cache register flags. |
105 | */ | 72 | */ |
106 | #define CACR_EC (1<<31) | 73 | #define CACR_EC (1<<31) |
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c index 86fc2047d7ac..1b01e79c2f63 100644 --- a/arch/m68knommu/platform/coldfire/intc-simr.c +++ b/arch/m68knommu/platform/coldfire/intc-simr.c | |||
@@ -62,6 +62,11 @@ void __init init_IRQ(void) | |||
62 | 62 | ||
63 | init_vectors(); | 63 | init_vectors(); |
64 | 64 | ||
65 | /* Mask all interrupt sources */ | ||
66 | __raw_writeb(0xff, MCFINTC0_SIMR); | ||
67 | if (MCFINTC1_SIMR) | ||
68 | __raw_writeb(0xff, MCFINTC1_SIMR); | ||
69 | |||
65 | for (irq = 0; (irq < NR_IRQS); irq++) { | 70 | for (irq = 0; (irq < NR_IRQS); irq++) { |
66 | irq_desc[irq].status = IRQ_DISABLED; | 71 | irq_desc[irq].status = IRQ_DISABLED; |
67 | irq_desc[irq].action = NULL; | 72 | irq_desc[irq].action = NULL; |