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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-07 13:57:51 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-07 13:57:51 -0400
commita8c4b90e670be3b01e9395c7310639c8109fc77e (patch)
tree272f7988aeeaf930efd594f66c1a41a7d28ecd74 /arch
parenteac84105cddf8686440aaa9fbcb58093e37e4180 (diff)
parent9251c6c0dc929d8eec6751c12ef312597f84e147 (diff)
Merge tag 'soc-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates (part 2) from Arnd Bergmann: "These patches are all for Renesas shmobile, and depend on the earlier pinctrl updates. Remarkably, this adds support for three new SoCs: r8a73a4, r8a73a4 and r8a7778. The bulk of the code added for these is for pinctrl (using the new subsystem) and for clocks (not yet using the common clock subsystem). The latter will have to get converted in one of the upcoming releases, but shmobile is not ready for that yet. The series also contains Renesas shmobile board changes, adding one board file for each of the three new SoCs. These boards are using a mix of classic and device-tree based probing, as there is still a lot of infrastructure in shmobile that has not been converted to DT yet. Once those are resolved to the degree that no board specific setup code is needed, they can get folded into the respective SoC setup files." * tag 'soc-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits) ARM: shmobile: use r8a7790 timer setup code on Lager ARM: shmobile: force enable of r8a7790 arch timer ARM: shmobile: Add second I/O range for r8a7790 PFC ARM: shmobile: bockw: enable network settings on bootargs ARM: shmobile: bockw: add SMSC ethernet support ARM: shmobile: R8A7778: add Ether support ARM: shmobile: bockw: enable SMSC ethernet on defconfig ARM: shmobile: r8a7778: add r8a7778_init_irq_extpin() ARM: shmobile: r8a7778: remove pointless PLATFORM_INFO() ARM: shmobile: mackerel: clean up MMCIF vs. SDHI1 selection ARM: shmobile: mackerel: add interrupt names for SDHI0 ARM: shmobile: mackerel: switch SDHI and MMCIF interfaces to slot-gpio ARM: shmobile: mackerel: remove OCR masks, where regulators are used ARM: shmobile: mackerel: SDHI resources do not have to be numbered ARM: shmobile: Initial r8a7790 Lager board support ARM: shmobile: APE6EVM LAN9220 support ARM: shmobile: APE6EVM PFC support ARM: shmobile: APE6EVM base support ARM: shmobile: kzm9g-reference: add ethernet support ARM: shmobile: add R-Car M1A Bock-W platform support ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/dts/Makefile3
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts52
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi94
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts32
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi35
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts31
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi63
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts13
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi81
-rw-r--r--arch/arm/configs/bockw_defconfig94
-rw-r--r--arch/arm/mach-shmobile/Kconfig48
-rw-r--r--arch/arm/mach-shmobile/Makefile6
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm.c94
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c35
-rw-r--r--arch/arm/mach-shmobile/board-bockw.c81
-rw-r--r--arch/arm/mach-shmobile/board-lager.c46
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c111
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c32
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c115
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c114
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c107
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c196
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7790.c93
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c50
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c115
-rw-r--r--arch/arm/mach-shmobile/clock.c13
-rw-r--r--arch/arm/mach-shmobile/include/mach/clock.h39
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h54
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a73a4.h8
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7778.h32
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h330
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7790.h9
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h12
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h15
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c641
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c202
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c192
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c244
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c58
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7790.c150
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c2
43 files changed, 2368 insertions, 1385 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1e31dac36a5f..5c56fa8824e9 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -643,7 +643,7 @@ config ARCH_SHMOBILE
643 select MULTI_IRQ_HANDLER 643 select MULTI_IRQ_HANDLER
644 select NEED_MACH_MEMORY_H 644 select NEED_MACH_MEMORY_H
645 select NO_IOPORT 645 select NO_IOPORT
646 select PINCTRL 646 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
647 select PM_GENERIC_DOMAINS if PM 647 select PM_GENERIC_DOMAINS if PM
648 select SPARSE_IRQ 648 select SPARSE_IRQ
649 help 649 help
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 853e199ea89f..2ab88e91e65f 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -155,9 +155,12 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
155 ccu9540.dtb 155 ccu9540.dtb
156dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 156dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
157 r8a7740-armadillo800eva.dtb \ 157 r8a7740-armadillo800eva.dtb \
158 r8a7778-bockw.dtb \
158 r8a7779-marzen-reference.dtb \ 159 r8a7779-marzen-reference.dtb \
160 r8a7790-lager.dtb \
159 sh73a0-kzm9g.dtb \ 161 sh73a0-kzm9g.dtb \
160 sh73a0-kzm9g-reference.dtb \ 162 sh73a0-kzm9g-reference.dtb \
163 r8a73a4-ape6evm.dtb \
161 sh7372-mackerel.dtb 164 sh7372-mackerel.dtb
162dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ 165dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
163 socfpga_vt.dtb 166 socfpga_vt.dtb
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
new file mode 100644
index 000000000000..f603c6946c29
--- /dev/null
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -0,0 +1,52 @@
1/*
2 * Device Tree Source for the APE6EVM board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "r8a73a4.dtsi"
13
14/ {
15 model = "APE6EVM";
16 compatible = "renesas,ape6evm", "renesas,r8a73a4";
17
18 chosen {
19 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0 0x40000000 0 0x40000000>;
25 };
26
27 ape6evm_fixed_3v3: fixedregulator@0 {
28 compatible = "regulator-fixed";
29 regulator-name = "3V3";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 regulator-always-on;
33 };
34
35 lbsc {
36 #address-cells = <1>;
37 #size-cells = <1>;
38
39 ethernet@8000000 {
40 compatible = "smsc,lan9118", "smsc,lan9115";
41 reg = <0x08000000 0x1000>;
42 interrupt-parent = <&irqc1>;
43 interrupts = <8 0x4>;
44 phy-mode = "mii";
45 reg-io-width = <4>;
46 smsc,irq-active-high;
47 smsc,irq-push-pull;
48 vdd33a-supply = <&ape6evm_fixed_3v3>;
49 vddvario-supply = <&ape6evm_fixed_3v3>;
50 };
51 };
52};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
new file mode 100644
index 000000000000..fde2a337d1ff
--- /dev/null
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -0,0 +1,94 @@
1/*
2 * Device Tree Source for the r8a73a4 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/ {
13 compatible = "renesas,r8a73a4";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 device_type = "cpu";
24 compatible = "arm,cortex-a15";
25 reg = <0>;
26 clock-frequency = <1500000000>;
27 };
28 };
29
30 gic: interrupt-controller@f1001000 {
31 compatible = "arm,cortex-a15-gic";
32 #interrupt-cells = <3>;
33 #address-cells = <0>;
34 interrupt-controller;
35 reg = <0 0xf1001000 0 0x1000>,
36 <0 0xf1002000 0 0x1000>,
37 <0 0xf1004000 0 0x2000>,
38 <0 0xf1006000 0 0x2000>;
39 interrupts = <1 9 0xf04>;
40
41 gic-cpuif@4 {
42 compatible = "arm,gic-cpuif";
43 cpuif-id = <4>;
44 cpu = <&cpu0>;
45 };
46 };
47
48 timer {
49 compatible = "arm,armv7-timer";
50 interrupts = <1 13 0xf08>,
51 <1 14 0xf08>,
52 <1 11 0xf08>,
53 <1 10 0xf08>;
54 };
55
56 irqc0: interrupt-controller@e61c0000 {
57 compatible = "renesas,irqc";
58 #interrupt-cells = <2>;
59 interrupt-controller;
60 reg = <0 0xe61c0000 0 0x200>;
61 interrupt-parent = <&gic>;
62 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>,
63 <0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
64 <0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
65 <0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
66 <0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
67 <0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
68 <0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
69 <0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
70 };
71
72 irqc1: interrupt-controller@e61c0200 {
73 compatible = "renesas,irqc";
74 #interrupt-cells = <2>;
75 interrupt-controller;
76 reg = <0 0xe61c0200 0 0x200>;
77 interrupt-parent = <&gic>;
78 interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
79 <0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
80 <0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
81 <0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
82 <0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
83 <0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
84 <0 56 4>, <0 57 4>;
85 };
86
87 thermal@e61f0000 {
88 compatible = "renesas,rcar-thermal";
89 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
90 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
91 interrupt-parent = <&gic>;
92 interrupts = <0 69 4>;
93 };
94};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
new file mode 100644
index 000000000000..0076b1e8a0fb
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -0,0 +1,32 @@
1/*
2 * Reference Device Tree Source for the Bock-W board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2013 Renesas Solutions Corp.
10 * Copyright (C) 2013 Simon Horman
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17/dts-v1/;
18/include/ "r8a7778.dtsi"
19
20/ {
21 model = "bockw";
22 compatible = "renesas,bockw", "renesas,r8a7778";
23
24 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs";
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x60000000 0x10000000>;
31 };
32};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
new file mode 100644
index 000000000000..474373559bdc
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -0,0 +1,35 @@
1/*
2 * Device Tree Source for Renesas r8a7778
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2013 Renesas Solutions Corp.
10 * Copyright (C) 2013 Simon Horman
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17/include/ "skeleton.dtsi"
18
19/ {
20 compatible = "renesas,r8a7778";
21
22 cpus {
23 cpu@0 {
24 compatible = "arm,cortex-a9";
25 };
26 };
27
28 gic: interrupt-controller@fe438000 {
29 compatible = "arm,cortex-a9-gic";
30 #interrupt-cells = <3>;
31 interrupt-controller;
32 reg = <0xfe438000 0x1000>,
33 <0xfe430000 0x100>;
34 };
35};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
new file mode 100644
index 000000000000..09a84fce89d6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -0,0 +1,31 @@
1/*
2 * Device Tree Source for the Lager board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "r8a7790.dtsi"
13
14/ {
15 model = "Lager";
16 compatible = "renesas,lager", "renesas,r8a7790";
17
18 chosen {
19 bootargs = "console=ttySC6,115200 ignore_loglevel";
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0 0x40000000 0 0x80000000>;
25 };
26
27 lbsc {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 };
31};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
new file mode 100644
index 000000000000..7a1711027e41
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -0,0 +1,63 @@
1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/ {
12 compatible = "renesas,r8a7790";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu0: cpu@0 {
22 device_type = "cpu";
23 compatible = "arm,cortex-a15";
24 reg = <0>;
25 clock-frequency = <1300000000>;
26 };
27 };
28
29 gic: interrupt-controller@f1001000 {
30 compatible = "arm,cortex-a15-gic";
31 #interrupt-cells = <3>;
32 #address-cells = <0>;
33 interrupt-controller;
34 reg = <0 0xf1001000 0 0x1000>,
35 <0 0xf1002000 0 0x1000>,
36 <0 0xf1004000 0 0x2000>,
37 <0 0xf1006000 0 0x2000>;
38 interrupts = <1 9 0xf04>;
39
40 gic-cpuif@4 {
41 compatible = "arm,gic-cpuif";
42 cpuif-id = <4>;
43 cpu = <&cpu0>;
44 };
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <1 13 0xf08>,
50 <1 14 0xf08>,
51 <1 11 0xf08>,
52 <1 10 0xf08>;
53 };
54
55 irqc0: interrupt-controller@e61c0000 {
56 compatible = "renesas,irqc";
57 #interrupt-cells = <2>;
58 interrupt-controller;
59 reg = <0 0xe61c0000 0 0x200>;
60 interrupt-parent = <&gic>;
61 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
62 };
63};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index f33b5ccb7446..5972abb55f9c 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -44,6 +44,19 @@
44 regulator-always-on; 44 regulator-always-on;
45 regulator-boot-on; 45 regulator-boot-on;
46 }; 46 };
47
48 lan9220@10000000 {
49 compatible = "smsc,lan9220", "smsc,lan9115";
50 reg = <0x10000000 0x100>;
51 phy-mode = "mii";
52 interrupt-parent = <&irqpin0>;
53 interrupts = <3 0>; /* active low */
54 reg-io-width = <4>;
55 smsc,irq-push-pull;
56 smsc,save-mac-address;
57 vddvario-supply = <&reg_1p8v>;
58 vdd33a-supply = <&reg_3p3v>;
59 };
47}; 60};
48 61
49&mmcif { 62&mmcif {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 3e4d383ac6d9..ec40bf78289e 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -38,6 +38,87 @@
38 <0xf0000100 0x100>; 38 <0xf0000100 0x100>;
39 }; 39 };
40 40
41 irqpin0: irqpin@e6900000 {
42 compatible = "renesas,intc-irqpin";
43 #interrupt-cells = <2>;
44 interrupt-controller;
45 reg = <0xe6900000 4>,
46 <0xe6900010 4>,
47 <0xe6900020 1>,
48 <0xe6900040 1>,
49 <0xe6900060 1>;
50 interrupt-parent = <&gic>;
51 interrupts = <0 1 0x4
52 0 2 0x4
53 0 3 0x4
54 0 4 0x4
55 0 5 0x4
56 0 6 0x4
57 0 7 0x4
58 0 8 0x4>;
59 };
60
61 irqpin1: irqpin@e6900004 {
62 compatible = "renesas,intc-irqpin";
63 #interrupt-cells = <2>;
64 interrupt-controller;
65 reg = <0xe6900004 4>,
66 <0xe6900014 4>,
67 <0xe6900024 1>,
68 <0xe6900044 1>,
69 <0xe6900064 1>;
70 interrupt-parent = <&gic>;
71 interrupts = <0 9 0x4
72 0 10 0x4
73 0 11 0x4
74 0 12 0x4
75 0 13 0x4
76 0 14 0x4
77 0 15 0x4
78 0 16 0x4>;
79 control-parent;
80 };
81
82 irqpin2: irqpin@e6900008 {
83 compatible = "renesas,intc-irqpin";
84 #interrupt-cells = <2>;
85 interrupt-controller;
86 reg = <0xe6900008 4>,
87 <0xe6900018 4>,
88 <0xe6900028 1>,
89 <0xe6900048 1>,
90 <0xe6900068 1>;
91 interrupt-parent = <&gic>;
92 interrupts = <0 17 0x4
93 0 18 0x4
94 0 19 0x4
95 0 20 0x4
96 0 21 0x4
97 0 22 0x4
98 0 23 0x4
99 0 24 0x4>;
100 };
101
102 irqpin3: irqpin@e690000c {
103 compatible = "renesas,intc-irqpin";
104 #interrupt-cells = <2>;
105 interrupt-controller;
106 reg = <0xe690000c 4>,
107 <0xe690001c 4>,
108 <0xe690002c 1>,
109 <0xe690004c 1>,
110 <0xe690006c 1>;
111 interrupt-parent = <&gic>;
112 interrupts = <0 25 0x4
113 0 26 0x4
114 0 27 0x4
115 0 28 0x4
116 0 29 0x4
117 0 30 0x4
118 0 31 0x4
119 0 32 0x4>;
120 };
121
41 i2c0: i2c@0xe6820000 { 122 i2c0: i2c@0xe6820000 {
42 #address-cells = <1>; 123 #address-cells = <1>;
43 #size-cells = <0>; 124 #size-cells = <0>;
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
new file mode 100644
index 000000000000..6524cdf3b08d
--- /dev/null
+++ b/arch/arm/configs/bockw_defconfig
@@ -0,0 +1,94 @@
1# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2CONFIG_KERNEL_LZMA=y
3CONFIG_NO_HZ=y
4CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=16
7CONFIG_SYSCTL_SYSCALL=y
8CONFIG_EMBEDDED=y
9CONFIG_SLAB=y
10# CONFIG_IOSCHED_CFQ is not set
11CONFIG_ARCH_SHMOBILE=y
12CONFIG_ARCH_R8A7778=y
13CONFIG_MACH_BOCKW=y
14CONFIG_MEMORY_START=0x60000000
15CONFIG_MEMORY_SIZE=0x10000000
16CONFIG_SHMOBILE_TIMER_HZ=1024
17# CONFIG_SH_TIMER_CMT is not set
18# CONFIG_EM_TIMER_STI is not set
19CONFIG_ARM_ERRATA_430973=y
20CONFIG_ARM_ERRATA_458693=y
21CONFIG_ARM_ERRATA_460075=y
22CONFIG_ARM_ERRATA_743622=y
23CONFIG_ARM_ERRATA_754322=y
24CONFIG_AEABI=y
25# CONFIG_OABI_COMPAT is not set
26CONFIG_HIGHMEM=y
27CONFIG_ZBOOT_ROM_TEXT=0x0
28CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_ARM_APPENDED_DTB=y
30CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"
31CONFIG_CMDLINE_FORCE=y
32# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
33# CONFIG_SUSPEND is not set
34CONFIG_NET=y
35CONFIG_UNIX=y
36CONFIG_INET=y
37CONFIG_IP_PNP=y
38CONFIG_IP_PNP_DHCP=y
39# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
40# CONFIG_INET_XFRM_MODE_TUNNEL is not set
41# CONFIG_INET_XFRM_MODE_BEET is not set
42# CONFIG_INET_LRO is not set
43# CONFIG_INET_DIAG is not set
44# CONFIG_IPV6 is not set
45CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
46CONFIG_DEVTMPFS=y
47CONFIG_DEVTMPFS_MOUNT=y
48# CONFIG_STANDALONE is not set
49# CONFIG_PREVENT_FIRMWARE_BUILD is not set
50# CONFIG_FW_LOADER is not set
51CONFIG_NETDEVICES=y
52# CONFIG_NET_CADENCE is not set
53# CONFIG_NET_VENDOR_BROADCOM is not set
54# CONFIG_NET_VENDOR_CIRRUS is not set
55# CONFIG_NET_VENDOR_FARADAY is not set
56# CONFIG_NET_VENDOR_INTEL is not set
57# CONFIG_NET_VENDOR_MARVELL is not set
58# CONFIG_NET_VENDOR_MICREL is not set
59# CONFIG_NET_VENDOR_NATSEMI is not set
60# CONFIG_NET_VENDOR_SEEQ is not set
61CONFIG_SMSC911X=y
62# CONFIG_NET_VENDOR_STMICRO is not set
63# CONFIG_NET_VENDOR_WIZNET is not set
64# CONFIG_INPUT is not set
65# CONFIG_SERIO is not set
66# CONFIG_VT is not set
67# CONFIG_LEGACY_PTYS is not set
68# CONFIG_DEVKMEM is not set
69CONFIG_SERIAL_SH_SCI=y
70CONFIG_SERIAL_SH_SCI_NR_UARTS=6
71CONFIG_SERIAL_SH_SCI_CONSOLE=y
72# CONFIG_HW_RANDOM is not set
73# CONFIG_HWMON is not set
74# CONFIG_USB_SUPPORT is not set
75CONFIG_UIO=y
76CONFIG_UIO_PDRV_GENIRQ=y
77# CONFIG_IOMMU_SUPPORT is not set
78# CONFIG_DNOTIFY is not set
79# CONFIG_INOTIFY_USER is not set
80CONFIG_TMPFS=y
81# CONFIG_MISC_FILESYSTEMS is not set
82CONFIG_NFS_FS=y
83CONFIG_NFS_V3_ACL=y
84CONFIG_NFS_V4=y
85CONFIG_NFS_SWAP=y
86CONFIG_NFS_V4_1=y
87CONFIG_ROOT_NFS=y
88# CONFIG_ENABLE_WARN_DEPRECATED is not set
89# CONFIG_ENABLE_MUST_CHECK is not set
90# CONFIG_SCHED_DEBUG is not set
91# CONFIG_DEBUG_BUGVERBOSE is not set
92# CONFIG_FTRACE is not set
93# CONFIG_ARM_UNWIND is not set
94CONFIG_AVERAGE=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index eb3a7ff19e72..1a517e2fe449 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -18,11 +18,28 @@ config ARCH_SH73A0
18 select SH_CLK_CPG 18 select SH_CLK_CPG
19 select RENESAS_INTC_IRQPIN 19 select RENESAS_INTC_IRQPIN
20 20
21config ARCH_R8A73A4
22 bool "R-Mobile APE6 (R8A73A40)"
23 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select ARM_GIC
25 select CPU_V7
26 select ARM_ARCH_TIMER
27 select SH_CLK_CPG
28 select RENESAS_IRQC
29
21config ARCH_R8A7740 30config ARCH_R8A7740
22 bool "R-Mobile A1 (R8A77400)" 31 bool "R-Mobile A1 (R8A77400)"
23 select ARCH_WANT_OPTIONAL_GPIOLIB 32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select ARM_GIC
24 select CPU_V7 34 select CPU_V7
25 select SH_CLK_CPG 35 select SH_CLK_CPG
36 select RENESAS_INTC_IRQPIN
37
38config ARCH_R8A7778
39 bool "R-Car M1 (R8A77780)"
40 select CPU_V7
41 select SH_CLK_CPG
42 select ARM_GIC
26 43
27config ARCH_R8A7779 44config ARCH_R8A7779
28 bool "R-Car H1 (R8A77790)" 45 bool "R-Car H1 (R8A77790)"
@@ -34,6 +51,15 @@ config ARCH_R8A7779
34 select USB_ARCH_HAS_OHCI 51 select USB_ARCH_HAS_OHCI
35 select RENESAS_INTC_IRQPIN 52 select RENESAS_INTC_IRQPIN
36 53
54config ARCH_R8A7790
55 bool "R-Car H2 (R8A77900)"
56 select ARCH_WANT_OPTIONAL_GPIOLIB
57 select ARM_GIC
58 select CPU_V7
59 select ARM_ARCH_TIMER
60 select SH_CLK_CPG
61 select RENESAS_IRQC
62
37config ARCH_EMEV2 63config ARCH_EMEV2
38 bool "Emma Mobile EV2" 64 bool "Emma Mobile EV2"
39 select ARCH_WANT_OPTIONAL_GPIOLIB 65 select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -70,6 +96,11 @@ config MACH_AG5EVM
70 select REGULATOR_FIXED_VOLTAGE if REGULATOR 96 select REGULATOR_FIXED_VOLTAGE if REGULATOR
71 select SH_LCD_MIPI_DSI 97 select SH_LCD_MIPI_DSI
72 98
99config MACH_APE6EVM
100 bool "APE6EVM board"
101 depends on ARCH_R8A73A4
102 select USE_OF
103
73config MACH_MACKEREL 104config MACH_MACKEREL
74 bool "mackerel board" 105 bool "mackerel board"
75 depends on ARCH_SH7372 106 depends on ARCH_SH7372
@@ -98,6 +129,13 @@ config MACH_ARMADILLO800EVA
98 select SND_SOC_WM8978 if SND_SIMPLE_CARD 129 select SND_SOC_WM8978 if SND_SIMPLE_CARD
99 select USE_OF 130 select USE_OF
100 131
132config MACH_BOCKW
133 bool "BOCK-W platform"
134 depends on ARCH_R8A7778
135 select ARCH_REQUIRE_GPIOLIB
136 select RENESAS_INTC_IRQPIN
137 select USE_OF
138
101config MACH_MARZEN 139config MACH_MARZEN
102 bool "MARZEN board" 140 bool "MARZEN board"
103 depends on ARCH_R8A7779 141 depends on ARCH_R8A7779
@@ -117,6 +155,11 @@ config MACH_MARZEN_REFERENCE
117 155
118 This is intended to aid developers 156 This is intended to aid developers
119 157
158config MACH_LAGER
159 bool "Lager board"
160 depends on ARCH_R8A7790
161 select USE_OF
162
120config MACH_KZM9D 163config MACH_KZM9D
121 bool "KZM9D board" 164 bool "KZM9D board"
122 depends on ARCH_EMEV2 165 depends on ARCH_EMEV2
@@ -157,7 +200,8 @@ config MEMORY_START
157 hex "Physical memory start address" 200 hex "Physical memory start address"
158 default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \ 201 default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
159 MACH_MACKEREL || MACH_BONITO || \ 202 MACH_MACKEREL || MACH_BONITO || \
160 MACH_ARMADILLO800EVA 203 MACH_ARMADILLO800EVA || MACH_APE6EVM || \
204 MACH_LAGER
161 default "0x41000000" if MACH_KOTA2 205 default "0x41000000" if MACH_KOTA2
162 default "0x00000000" 206 default "0x00000000"
163 ---help--- 207 ---help---
@@ -167,6 +211,8 @@ config MEMORY_START
167 211
168config MEMORY_SIZE 212config MEMORY_SIZE
169 hex "Physical memory size" 213 hex "Physical memory size"
214 default "0x80000000" if MACH_LAGER
215 default "0x40000000" if MACH_APE6EVM
170 default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \ 216 default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
171 MACH_ARMADILLO800EVA 217 MACH_ARMADILLO800EVA
172 default "0x1e000000" if MACH_KOTA2 218 default "0x1e000000" if MACH_KOTA2
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index c621edfa6ead..068f1dadc46b 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -8,8 +8,11 @@ obj-y := timer.o console.o clock.o
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o
11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o 12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o
12obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o 14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o
13obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o 16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
14 17
15# SMP objects 18# SMP objects
@@ -34,11 +37,14 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
34# Board objects 37# Board objects
35obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o 38obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
36obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 39obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
40obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
37obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 41obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
38obj-$(CONFIG_MACH_KOTA2) += board-kota2.o 42obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
39obj-$(CONFIG_MACH_BONITO) += board-bonito.o 43obj-$(CONFIG_MACH_BONITO) += board-bonito.o
44obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
40obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 45obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
41obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o 46obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
47obj-$(CONFIG_MACH_LAGER) += board-lager.o
42obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 48obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
43obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o 49obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
44obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 50obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
new file mode 100644
index 000000000000..55b8c9fef954
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -0,0 +1,94 @@
1/*
2 * APE6EVM board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/gpio.h>
22#include <linux/interrupt.h>
23#include <linux/irqchip.h>
24#include <linux/kernel.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/fixed.h>
28#include <linux/regulator/machine.h>
29#include <linux/smsc911x.h>
30#include <mach/common.h>
31#include <mach/irqs.h>
32#include <mach/r8a73a4.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35
36/* Dummy supplies, where voltage doesn't matter */
37static struct regulator_consumer_supply dummy_supplies[] = {
38 REGULATOR_SUPPLY("vddvario", "smsc911x"),
39 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
40};
41
42/* SMSC LAN9220 */
43static const struct resource lan9220_res[] = {
44 DEFINE_RES_MEM(0x08000000, 0x1000),
45 {
46 .start = irq_pin(40), /* IRQ40 */
47 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
48 },
49};
50
51static const struct smsc911x_platform_config lan9220_data = {
52 .flags = SMSC911X_USE_32BIT,
53 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
54 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
55};
56
57static const struct pinctrl_map ape6evm_pinctrl_map[] = {
58 /* SCIFA0 console */
59 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
60 "scifa0_data", "scifa0"),
61 /* SMSC */
62 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
63 "irqc_irq40", "irqc"),
64};
65
66static void __init ape6evm_add_standard_devices(void)
67{
68 r8a73a4_clock_init();
69 pinctrl_register_mappings(ape6evm_pinctrl_map,
70 ARRAY_SIZE(ape6evm_pinctrl_map));
71 r8a73a4_pinmux_init();
72 r8a73a4_add_standard_devices();
73
74 /* LAN9220 ethernet */
75 gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
76
77 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
78
79 platform_device_register_resndata(&platform_bus, "smsc911x", -1,
80 lan9220_res, ARRAY_SIZE(lan9220_res),
81 &lan9220_data, sizeof(lan9220_data));
82}
83
84static const char *ape6evm_boards_compat_dt[] __initdata = {
85 "renesas,ape6evm",
86 NULL,
87};
88
89DT_MACHINE_START(APE6EVM_DT, "ape6evm")
90 .init_irq = irqchip_init,
91 .init_time = shmobile_timer_init,
92 .init_machine = ape6evm_add_standard_devices,
93 .dt_compat = ape6evm_boards_compat_dt,
94MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 4dfe32262eb7..b85b2882dbd0 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -149,7 +149,7 @@
149 * see 149 * see
150 * usbhsf_power_ctrl() 150 * usbhsf_power_ctrl()
151 */ 151 */
152#define IRQ7 evt2irq(0x02e0) 152#define IRQ7 irq_pin(7)
153#define USBCR1 IOMEM(0xe605810a) 153#define USBCR1 IOMEM(0xe605810a)
154#define USBH 0xC6700000 154#define USBH 0xC6700000
155#define USBH_USBCTR 0x10834 155#define USBH_USBCTR 0x10834
@@ -338,7 +338,7 @@ static struct resource usbhsf_resources[] = {
338 .flags = IORESOURCE_MEM, 338 .flags = IORESOURCE_MEM,
339 }, 339 },
340 { 340 {
341 .start = evt2irq(0x0A20), 341 .start = gic_spi(51),
342 .flags = IORESOURCE_IRQ, 342 .flags = IORESOURCE_IRQ,
343 }, 343 },
344}; 344};
@@ -371,7 +371,7 @@ static struct resource sh_eth_resources[] = {
371 .end = 0xe9a02000 - 1, 371 .end = 0xe9a02000 - 1,
372 .flags = IORESOURCE_MEM, 372 .flags = IORESOURCE_MEM,
373 }, { 373 }, {
374 .start = evt2irq(0x0500), 374 .start = gic_spi(110),
375 .flags = IORESOURCE_IRQ, 375 .flags = IORESOURCE_IRQ,
376 }, 376 },
377}; 377};
@@ -425,7 +425,7 @@ static struct resource lcdc0_resources[] = {
425 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
426 }, 426 },
427 [1] = { 427 [1] = {
428 .start = intcs_evt2irq(0x580), 428 .start = gic_spi(177),
429 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
430 }, 430 },
431}; 431};
@@ -460,7 +460,7 @@ static struct resource hdmi_resources[] = {
460 .flags = IORESOURCE_MEM, 460 .flags = IORESOURCE_MEM,
461 }, 461 },
462 [1] = { 462 [1] = {
463 .start = evt2irq(0x1700), 463 .start = gic_spi(131),
464 .flags = IORESOURCE_IRQ, 464 .flags = IORESOURCE_IRQ,
465 }, 465 },
466 [2] = { 466 [2] = {
@@ -522,7 +522,7 @@ static struct resource hdmi_lcdc_resources[] = {
522 .flags = IORESOURCE_MEM, 522 .flags = IORESOURCE_MEM,
523 }, 523 },
524 [1] = { 524 [1] = {
525 .start = intcs_evt2irq(0x1780), 525 .start = gic_spi(178),
526 .flags = IORESOURCE_IRQ, 526 .flags = IORESOURCE_IRQ,
527 }, 527 },
528}; 528};
@@ -686,7 +686,7 @@ static struct platform_device vcc_sdhi1 = {
686 * We can use IRQ31 as card detect irq, 686 * We can use IRQ31 as card detect irq,
687 * but it needs chattering removal operation 687 * but it needs chattering removal operation
688 */ 688 */
689#define IRQ31 evt2irq(0x33E0) 689#define IRQ31 irq_pin(31)
690static struct sh_mobile_sdhi_info sdhi0_info = { 690static struct sh_mobile_sdhi_info sdhi0_info = {
691 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 691 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
692 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 692 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -708,12 +708,12 @@ static struct resource sdhi0_resources[] = {
708 */ 708 */
709 { 709 {
710 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 710 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
711 .start = evt2irq(0x0E20), 711 .start = gic_spi(118),
712 .flags = IORESOURCE_IRQ, 712 .flags = IORESOURCE_IRQ,
713 }, 713 },
714 { 714 {
715 .name = SH_MOBILE_SDHI_IRQ_SDIO, 715 .name = SH_MOBILE_SDHI_IRQ_SDIO,
716 .start = evt2irq(0x0E40), 716 .start = gic_spi(119),
717 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
718 }, 718 },
719}; 719};
@@ -747,15 +747,15 @@ static struct resource sdhi1_resources[] = {
747 .flags = IORESOURCE_MEM, 747 .flags = IORESOURCE_MEM,
748 }, 748 },
749 [1] = { 749 [1] = {
750 .start = evt2irq(0x0E80), 750 .start = gic_spi(121),
751 .flags = IORESOURCE_IRQ, 751 .flags = IORESOURCE_IRQ,
752 }, 752 },
753 [2] = { 753 [2] = {
754 .start = evt2irq(0x0EA0), 754 .start = gic_spi(122),
755 .flags = IORESOURCE_IRQ, 755 .flags = IORESOURCE_IRQ,
756 }, 756 },
757 [3] = { 757 [3] = {
758 .start = evt2irq(0x0EC0), 758 .start = gic_spi(123),
759 .flags = IORESOURCE_IRQ, 759 .flags = IORESOURCE_IRQ,
760 }, 760 },
761}; 761};
@@ -798,12 +798,12 @@ static struct resource sh_mmcif_resources[] = {
798 }, 798 },
799 [1] = { 799 [1] = {
800 /* MMC ERR */ 800 /* MMC ERR */
801 .start = evt2irq(0x1AC0), 801 .start = gic_spi(56),
802 .flags = IORESOURCE_IRQ, 802 .flags = IORESOURCE_IRQ,
803 }, 803 },
804 [2] = { 804 [2] = {
805 /* MMC NOR */ 805 /* MMC NOR */
806 .start = evt2irq(0x1AE0), 806 .start = gic_spi(57),
807 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
808 }, 808 },
809}; 809};
@@ -880,7 +880,7 @@ static struct resource ceu0_resources[] = {
880 .flags = IORESOURCE_MEM, 880 .flags = IORESOURCE_MEM,
881 }, 881 },
882 [1] = { 882 [1] = {
883 .start = intcs_evt2irq(0x0500), 883 .start = gic_spi(160),
884 .flags = IORESOURCE_IRQ, 884 .flags = IORESOURCE_IRQ,
885 }, 885 },
886 [2] = { 886 [2] = {
@@ -922,7 +922,7 @@ static struct resource fsi_resources[] = {
922 .flags = IORESOURCE_MEM, 922 .flags = IORESOURCE_MEM,
923 }, 923 },
924 [1] = { 924 [1] = {
925 .start = evt2irq(0x1840), 925 .start = gic_spi(9),
926 .flags = IORESOURCE_IRQ, 926 .flags = IORESOURCE_IRQ,
927 }, 927 },
928}; 928};
@@ -1009,7 +1009,7 @@ static struct st1232_pdata st1232_i2c0_pdata = {
1009static struct i2c_board_info i2c0_devices[] = { 1009static struct i2c_board_info i2c0_devices[] = {
1010 { 1010 {
1011 I2C_BOARD_INFO("st1232-ts", 0x55), 1011 I2C_BOARD_INFO("st1232-ts", 0x55),
1012 .irq = evt2irq(0x0340), 1012 .irq = irq_pin(10),
1013 .platform_data = &st1232_i2c0_pdata, 1013 .platform_data = &st1232_i2c0_pdata,
1014 }, 1014 },
1015 { 1015 {
@@ -1292,7 +1292,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1292 .map_io = r8a7740_map_io, 1292 .map_io = r8a7740_map_io,
1293 .init_early = eva_add_early_devices, 1293 .init_early = eva_add_early_devices,
1294 .init_irq = r8a7740_init_irq, 1294 .init_irq = r8a7740_init_irq,
1295 .handle_irq = shmobile_handle_irq_intc,
1296 .init_machine = eva_init, 1295 .init_machine = eva_init,
1297 .init_late = shmobile_init_late, 1296 .init_late = shmobile_init_late,
1298 .init_time = eva_earlytimer_init, 1297 .init_time = eva_earlytimer_init,
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
new file mode 100644
index 000000000000..38e5e50fb318
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -0,0 +1,81 @@
1/*
2 * Bock-W board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/platform_device.h>
22#include <linux/smsc911x.h>
23#include <mach/common.h>
24#include <mach/irqs.h>
25#include <mach/r8a7778.h>
26#include <asm/mach/arch.h>
27
28static struct smsc911x_platform_config smsc911x_data = {
29 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
30 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
31 .flags = SMSC911X_USE_32BIT,
32 .phy_interface = PHY_INTERFACE_MODE_MII,
33};
34
35static struct resource smsc911x_resources[] = {
36 DEFINE_RES_MEM(0x18300000, 0x1000),
37 DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
38};
39
40#define IRQ0MR 0x30
41static void __init bockw_init(void)
42{
43 void __iomem *fpga;
44
45 r8a7778_clock_init();
46 r8a7778_init_irq_extpin(1);
47 r8a7778_add_standard_devices();
48
49 fpga = ioremap_nocache(0x18200000, SZ_1M);
50 if (fpga) {
51 /*
52 * CAUTION
53 *
54 * IRQ0/1 is cascaded interrupt from FPGA.
55 * it should be cared in the future
56 * Now, it is assuming IRQ0 was used only from SMSC.
57 */
58 u16 val = ioread16(fpga + IRQ0MR);
59 val &= ~(1 << 4); /* enable SMSC911x */
60 iowrite16(val, fpga + IRQ0MR);
61 iounmap(fpga);
62
63 platform_device_register_resndata(
64 &platform_bus, "smsc911x", -1,
65 smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
66 &smsc911x_data, sizeof(smsc911x_data));
67 }
68}
69
70static const char *bockw_boards_compat_dt[] __initdata = {
71 "renesas,bockw",
72 NULL,
73};
74
75DT_MACHINE_START(BOCKW_DT, "bockw")
76 .init_early = r8a7778_init_delay,
77 .init_irq = r8a7778_init_irq_dt,
78 .init_machine = bockw_init,
79 .init_time = shmobile_timer_init,
80 .dt_compat = bockw_boards_compat_dt,
81MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
new file mode 100644
index 000000000000..f587187a8603
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -0,0 +1,46 @@
1/*
2 * Lager board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/interrupt.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h>
24#include <linux/platform_device.h>
25#include <mach/common.h>
26#include <mach/r8a7790.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29
30static void __init lager_add_standard_devices(void)
31{
32 r8a7790_clock_init();
33 r8a7790_add_standard_devices();
34}
35
36static const char *lager_boards_compat_dt[] __initdata = {
37 "renesas,lager",
38 NULL,
39};
40
41DT_MACHINE_START(LAGER_DT, "lager")
42 .init_irq = irqchip_init,
43 .init_time = r8a7790_timer_init,
44 .init_machine = lager_add_standard_devices,
45 .dt_compat = lager_boards_compat_dt,
46MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 2b60f2bf1fbb..fa3407da682a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -969,15 +969,6 @@ static struct platform_device nand_flash_device = {
969 }, 969 },
970}; 970};
971 971
972/*
973 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
974 * connected to GPIO A22 of SH7372 (GPIO 41).
975 */
976static int slot_cn7_get_cd(struct platform_device *pdev)
977{
978 return !gpio_get_value(41);
979}
980
981/* SDHI0 */ 972/* SDHI0 */
982static struct sh_mobile_sdhi_info sdhi0_info = { 973static struct sh_mobile_sdhi_info sdhi0_info = {
983 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 974 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
@@ -988,21 +979,17 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
988}; 979};
989 980
990static struct resource sdhi0_resources[] = { 981static struct resource sdhi0_resources[] = {
991 [0] = { 982 {
992 .name = "SDHI0", 983 .name = "SDHI0",
993 .start = 0xe6850000, 984 .start = 0xe6850000,
994 .end = 0xe68500ff, 985 .end = 0xe68500ff,
995 .flags = IORESOURCE_MEM, 986 .flags = IORESOURCE_MEM,
996 }, 987 }, {
997 [1] = { 988 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
998 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
999 .flags = IORESOURCE_IRQ,
1000 },
1001 [2] = {
1002 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */, 989 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
1003 .flags = IORESOURCE_IRQ, 990 .flags = IORESOURCE_IRQ,
1004 }, 991 }, {
1005 [3] = { 992 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1006 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */, 993 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
1007 .flags = IORESOURCE_IRQ, 994 .flags = IORESOURCE_IRQ,
1008 }, 995 },
@@ -1018,36 +1005,30 @@ static struct platform_device sdhi0_device = {
1018 }, 1005 },
1019}; 1006};
1020 1007
1021#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1008#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1022/* SDHI1 */ 1009/* SDHI1 */
1010
1011/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
1023static struct sh_mobile_sdhi_info sdhi1_info = { 1012static struct sh_mobile_sdhi_info sdhi1_info = {
1024 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX, 1013 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
1025 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX, 1014 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
1026 .tmio_ocr_mask = MMC_VDD_165_195, 1015 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
1027 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
1028 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 1016 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
1029 MMC_CAP_NEEDS_POLL, 1017 MMC_CAP_NEEDS_POLL,
1030 .get_cd = slot_cn7_get_cd, 1018 .cd_gpio = 41,
1031}; 1019};
1032 1020
1033static struct resource sdhi1_resources[] = { 1021static struct resource sdhi1_resources[] = {
1034 [0] = { 1022 {
1035 .name = "SDHI1", 1023 .name = "SDHI1",
1036 .start = 0xe6860000, 1024 .start = 0xe6860000,
1037 .end = 0xe68600ff, 1025 .end = 0xe68600ff,
1038 .flags = IORESOURCE_MEM, 1026 .flags = IORESOURCE_MEM,
1039 }, 1027 }, {
1040 [1] = {
1041 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
1042 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
1043 .flags = IORESOURCE_IRQ,
1044 },
1045 [2] = {
1046 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 1028 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
1047 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */ 1029 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
1048 .flags = IORESOURCE_IRQ, 1030 .flags = IORESOURCE_IRQ,
1049 }, 1031 }, {
1050 [3] = {
1051 .name = SH_MOBILE_SDHI_IRQ_SDIO, 1032 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1052 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */ 1033 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
1053 .flags = IORESOURCE_IRQ, 1034 .flags = IORESOURCE_IRQ,
@@ -1065,43 +1046,32 @@ static struct platform_device sdhi1_device = {
1065}; 1046};
1066#endif 1047#endif
1067 1048
1049/* SDHI2 */
1050
1068/* 1051/*
1069 * The card detect pin of the top SD/MMC slot (CN23) is active low and is 1052 * The card detect pin of the top SD/MMC slot (CN23) is active low and is
1070 * connected to GPIO SCIFB_SCK of SH7372 (162). 1053 * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
1071 */ 1054 */
1072static int slot_cn23_get_cd(struct platform_device *pdev)
1073{
1074 return !gpio_get_value(162);
1075}
1076
1077/* SDHI2 */
1078static struct sh_mobile_sdhi_info sdhi2_info = { 1055static struct sh_mobile_sdhi_info sdhi2_info = {
1079 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX, 1056 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
1080 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX, 1057 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
1081 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE, 1058 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
1082 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 1059 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
1083 MMC_CAP_NEEDS_POLL, 1060 MMC_CAP_NEEDS_POLL,
1084 .get_cd = slot_cn23_get_cd, 1061 .cd_gpio = 162,
1085}; 1062};
1086 1063
1087static struct resource sdhi2_resources[] = { 1064static struct resource sdhi2_resources[] = {
1088 [0] = { 1065 {
1089 .name = "SDHI2", 1066 .name = "SDHI2",
1090 .start = 0xe6870000, 1067 .start = 0xe6870000,
1091 .end = 0xe68700ff, 1068 .end = 0xe68700ff,
1092 .flags = IORESOURCE_MEM, 1069 .flags = IORESOURCE_MEM,
1093 }, 1070 }, {
1094 [1] = {
1095 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
1096 .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
1097 .flags = IORESOURCE_IRQ,
1098 },
1099 [2] = {
1100 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 1071 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
1101 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */ 1072 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
1102 .flags = IORESOURCE_IRQ, 1073 .flags = IORESOURCE_IRQ,
1103 }, 1074 }, {
1104 [3] = {
1105 .name = SH_MOBILE_SDHI_IRQ_SDIO, 1075 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1106 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */ 1076 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
1107 .flags = IORESOURCE_IRQ, 1077 .flags = IORESOURCE_IRQ,
@@ -1119,6 +1089,7 @@ static struct platform_device sdhi2_device = {
1119}; 1089};
1120 1090
1121/* SH_MMCIF */ 1091/* SH_MMCIF */
1092#if IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1122static struct resource sh_mmcif_resources[] = { 1093static struct resource sh_mmcif_resources[] = {
1123 [0] = { 1094 [0] = {
1124 .name = "MMCIF", 1095 .name = "MMCIF",
@@ -1140,16 +1111,17 @@ static struct resource sh_mmcif_resources[] = {
1140 1111
1141static struct sh_mmcif_plat_data sh_mmcif_plat = { 1112static struct sh_mmcif_plat_data sh_mmcif_plat = {
1142 .sup_pclk = 0, 1113 .sup_pclk = 0,
1143 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
1144 .caps = MMC_CAP_4_BIT_DATA | 1114 .caps = MMC_CAP_4_BIT_DATA |
1145 MMC_CAP_8_BIT_DATA | 1115 MMC_CAP_8_BIT_DATA |
1146 MMC_CAP_NEEDS_POLL, 1116 MMC_CAP_NEEDS_POLL,
1147 .get_cd = slot_cn7_get_cd, 1117 .use_cd_gpio = true,
1118 /* card detect pin for SD/MMC slot (CN7) */
1119 .cd_gpio = 41,
1148 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX, 1120 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
1149 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX, 1121 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
1150}; 1122};
1151 1123
1152static struct platform_device sh_mmcif_device __maybe_unused = { 1124static struct platform_device sh_mmcif_device = {
1153 .name = "sh_mmcif", 1125 .name = "sh_mmcif",
1154 .id = 0, 1126 .id = 0,
1155 .dev = { 1127 .dev = {
@@ -1160,7 +1132,7 @@ static struct platform_device sh_mmcif_device __maybe_unused = {
1160 .num_resources = ARRAY_SIZE(sh_mmcif_resources), 1132 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
1161 .resource = sh_mmcif_resources, 1133 .resource = sh_mmcif_resources,
1162}; 1134};
1163 1135#endif
1164 1136
1165static int mackerel_camera_add(struct soc_camera_device *icd); 1137static int mackerel_camera_add(struct soc_camera_device *icd);
1166static void mackerel_camera_del(struct soc_camera_device *icd); 1138static void mackerel_camera_del(struct soc_camera_device *icd);
@@ -1267,11 +1239,12 @@ static struct platform_device *mackerel_devices[] __initdata = {
1267 &fsi_hdmi_device, 1239 &fsi_hdmi_device,
1268 &nand_flash_device, 1240 &nand_flash_device,
1269 &sdhi0_device, 1241 &sdhi0_device,
1270#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1242#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1271 &sdhi1_device, 1243 &sdhi1_device,
1244#else
1245 &sh_mmcif_device,
1272#endif 1246#endif
1273 &sdhi2_device, 1247 &sdhi2_device,
1274 &sh_mmcif_device,
1275 &ceu_device, 1248 &ceu_device,
1276 &mackerel_camera, 1249 &mackerel_camera,
1277 &hdmi_device, 1250 &hdmi_device,
@@ -1336,11 +1309,6 @@ static struct i2c_board_info i2c1_devices[] = {
1336}; 1309};
1337 1310
1338static const struct pinctrl_map mackerel_pinctrl_map[] = { 1311static const struct pinctrl_map mackerel_pinctrl_map[] = {
1339 /* MMCIF */
1340 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1341 "mmc0_data8_0", "mmc0"),
1342 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1343 "mmc0_ctrl_0", "mmc0"),
1344 /* SDHI0 */ 1312 /* SDHI0 */
1345 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", 1313 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1346 "sdhi0_data4", "sdhi0"), 1314 "sdhi0_data4", "sdhi0"),
@@ -1349,11 +1317,17 @@ static const struct pinctrl_map mackerel_pinctrl_map[] = {
1349 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372", 1317 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1350 "sdhi0_wp", "sdhi0"), 1318 "sdhi0_wp", "sdhi0"),
1351 /* SDHI1 */ 1319 /* SDHI1 */
1352#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1320#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1353 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", 1321 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1354 "sdhi1_data4", "sdhi1"), 1322 "sdhi1_data4", "sdhi1"),
1355 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372", 1323 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1356 "sdhi1_ctrl", "sdhi1"), 1324 "sdhi1_ctrl", "sdhi1"),
1325#else
1326 /* MMCIF */
1327 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1328 "mmc0_data8_0", "mmc0"),
1329 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1330 "mmc0_ctrl_0", "mmc0"),
1357#endif 1331#endif
1358 /* SDHI2 */ 1332 /* SDHI2 */
1359 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372", 1333 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
@@ -1378,10 +1352,11 @@ static void __init mackerel_init(void)
1378 { "A3SP", &usbhs0_device, }, 1352 { "A3SP", &usbhs0_device, },
1379 { "A3SP", &usbhs1_device, }, 1353 { "A3SP", &usbhs1_device, },
1380 { "A3SP", &nand_flash_device, }, 1354 { "A3SP", &nand_flash_device, },
1381 { "A3SP", &sh_mmcif_device, },
1382 { "A3SP", &sdhi0_device, }, 1355 { "A3SP", &sdhi0_device, },
1383#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE) 1356#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1384 { "A3SP", &sdhi1_device, }, 1357 { "A3SP", &sdhi1_device, },
1358#else
1359 { "A3SP", &sh_mmcif_device, },
1385#endif 1360#endif
1386 { "A3SP", &sdhi2_device, }, 1361 { "A3SP", &sdhi2_device, },
1387 { "A4R", &ceu_device, }, 1362 { "A4R", &ceu_device, },
@@ -1492,12 +1467,6 @@ static void __init mackerel_init(void)
1492 /* SDHI0 PORT172 card-detect IRQ26 */ 1467 /* SDHI0 PORT172 card-detect IRQ26 */
1493 gpio_request(GPIO_FN_IRQ26_172, NULL); 1468 gpio_request(GPIO_FN_IRQ26_172, NULL);
1494 1469
1495 /* card detect pin for MMC slot (CN7) */
1496 gpio_request_one(41, GPIOF_IN, NULL);
1497
1498 /* card detect pin for microSD slot (CN23) */
1499 gpio_request_one(162, GPIOF_IN, NULL);
1500
1501 /* FLCTL */ 1470 /* FLCTL */
1502 gpio_request(GPIO_FN_D0_NAF0, NULL); 1471 gpio_request(GPIO_FN_D0_NAF0, NULL);
1503 gpio_request(GPIO_FN_D1_NAF1, NULL); 1472 gpio_request(GPIO_FN_D1_NAF1, NULL);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index 2333a2d7c937..91052855cc12 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,6 +25,7 @@
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/leds.h>
28#include <linux/dma-mapping.h> 29#include <linux/dma-mapping.h>
29#include <linux/pinctrl/machine.h> 30#include <linux/pinctrl/machine.h>
30#include <linux/regulator/fixed.h> 31#include <linux/regulator/fixed.h>
@@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
168 .num_resources = ARRAY_SIZE(usb_phy_resources), 169 .num_resources = ARRAY_SIZE(usb_phy_resources),
169}; 170};
170 171
172/* LEDS */
173static struct gpio_led marzen_leds[] = {
174 {
175 .name = "led2",
176 .gpio = 157,
177 .default_state = LEDS_GPIO_DEFSTATE_ON,
178 }, {
179 .name = "led3",
180 .gpio = 158,
181 .default_state = LEDS_GPIO_DEFSTATE_ON,
182 }, {
183 .name = "led4",
184 .gpio = 159,
185 .default_state = LEDS_GPIO_DEFSTATE_ON,
186 },
187};
188
189static struct gpio_led_platform_data marzen_leds_pdata = {
190 .leds = marzen_leds,
191 .num_leds = ARRAY_SIZE(marzen_leds),
192};
193
194static struct platform_device leds_device = {
195 .name = "leds-gpio",
196 .id = 0,
197 .dev = {
198 .platform_data = &marzen_leds_pdata,
199 },
200};
201
171static struct platform_device *marzen_devices[] __initdata = { 202static struct platform_device *marzen_devices[] __initdata = {
172 &eth_device, 203 &eth_device,
173 &sdhi0_device, 204 &sdhi0_device,
174 &thermal_device, 205 &thermal_device,
175 &hspi_device, 206 &hspi_device,
176 &usb_phy_device, 207 &usb_phy_device,
208 &leds_device,
177}; 209};
178 210
179/* USB */ 211/* USB */
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
new file mode 100644
index 000000000000..e710c00c3822
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -0,0 +1,115 @@
1/*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x270
29
30#define MPCKCR 0xe6150080
31#define SMSTPCR2 0xe6150138
32#define SMSTPCR5 0xe6150144
33
34static struct clk_mapping cpg_mapping = {
35 .phys = CPG_BASE,
36 .len = CPG_LEN,
37};
38
39static struct clk extalr_clk = {
40 .rate = 32768,
41 .mapping = &cpg_mapping,
42};
43
44static struct clk extal1_clk = {
45 .rate = 26000000,
46 .mapping = &cpg_mapping,
47};
48
49static struct clk extal2_clk = {
50 .rate = 48000000,
51 .mapping = &cpg_mapping,
52};
53
54static struct clk *main_clks[] = {
55 &extalr_clk,
56 &extal1_clk,
57 &extal2_clk,
58};
59
60enum {
61 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
62 MSTP522,
63 MSTP_NR
64};
65
66static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
68 [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
69 [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
70 [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
71 [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
72 [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
73 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
74};
75
76static struct clk_lookup lookups[] = {
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
80 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
81 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
82 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
83 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
84
85 /* for DT */
86 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
87};
88
89void __init r8a73a4_clock_init(void)
90{
91 void __iomem *cpg_base, *reg;
92 int k, ret = 0;
93
94 /* fix MPCLK to EXTAL2 for now.
95 * this is needed until more detailed clock topology is supported
96 */
97 cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
98 BUG_ON(!cpg_base);
99 reg = cpg_base + (MPCKCR - CPG_BASE);
100 iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
101 iounmap(cpg_base);
102
103 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
104 ret = clk_register(main_clks[k]);
105
106 if (!ret)
107 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
108
109 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
110
111 if (!ret)
112 shmobile_clk_init();
113 else
114 panic("failed to setup r8a73a4 clocks\n");
115}
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index 1feb9a2286a8..c0d39aa6de50 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/sh_clk.h> 23#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h>
25#include <mach/common.h> 26#include <mach/common.h>
26#include <mach/r8a7740.h> 27#include <mach/r8a7740.h>
27 28
@@ -97,42 +98,13 @@ static struct clk dv_clk = {
97 .rate = 27000000, 98 .rate = 27000000,
98}; 99};
99 100
100static unsigned long div_recalc(struct clk *clk) 101SH_CLK_RATIO(div2, 1, 2);
101{ 102SH_CLK_RATIO(div1k, 1, 1024);
102 return clk->parent->rate / (int)(clk->priv);
103}
104
105static struct sh_clk_ops div_clk_ops = {
106 .recalc = div_recalc,
107};
108
109/* extal1 / 2 */
110static struct clk extal1_div2_clk = {
111 .ops = &div_clk_ops,
112 .priv = (void *)2,
113 .parent = &extal1_clk,
114};
115
116/* extal1 / 1024 */
117static struct clk extal1_div1024_clk = {
118 .ops = &div_clk_ops,
119 .priv = (void *)1024,
120 .parent = &extal1_clk,
121};
122
123/* extal1 / 2 / 1024 */
124static struct clk extal1_div2048_clk = {
125 .ops = &div_clk_ops,
126 .priv = (void *)1024,
127 .parent = &extal1_div2_clk,
128};
129 103
130/* extal2 / 2 */ 104SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
131static struct clk extal2_div2_clk = { 105SH_FIXED_RATIO_CLK(extal1_div1024_clk, extal1_clk, div1k);
132 .ops = &div_clk_ops, 106SH_FIXED_RATIO_CLK(extal1_div2048_clk, extal1_div2_clk, div1k);
133 .priv = (void *)2, 107SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
134 .parent = &extal2_clk,
135};
136 108
137static struct sh_clk_ops followparent_clk_ops = { 109static struct sh_clk_ops followparent_clk_ops = {
138 .recalc = followparent_recalc, 110 .recalc = followparent_recalc,
@@ -143,11 +115,7 @@ static struct clk system_clk = {
143 .ops = &followparent_clk_ops, 115 .ops = &followparent_clk_ops,
144}; 116};
145 117
146static struct clk system_div2_clk = { 118SH_FIXED_RATIO_CLK(system_div2_clk, system_clk, div2);
147 .ops = &div_clk_ops,
148 .priv = (void *)2,
149 .parent = &system_clk,
150};
151 119
152/* r_clk */ 120/* r_clk */
153static struct clk r_clk = { 121static struct clk r_clk = {
@@ -184,11 +152,7 @@ static struct clk pllc1_clk = {
184}; 152};
185 153
186/* PLLC1 / 2 */ 154/* PLLC1 / 2 */
187static struct clk pllc1_div2_clk = { 155SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
188 .ops = &div_clk_ops,
189 .priv = (void *)2,
190 .parent = &pllc1_clk,
191};
192 156
193/* USB clock */ 157/* USB clock */
194/* 158/*
@@ -323,6 +287,7 @@ struct clk *main_clks[] = {
323 &fsibck_clk, 287 &fsibck_clk,
324}; 288};
325 289
290/* DIV4 clocks */
326static void div4_kick(struct clk *clk) 291static void div4_kick(struct clk *clk)
327{ 292{
328 unsigned long value; 293 unsigned long value;
@@ -346,6 +311,26 @@ static struct clk_div4_table div4_table = {
346 .kick = div4_kick, 311 .kick = div4_kick,
347}; 312};
348 313
314enum {
315 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
316 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
317 DIV4_NR
318};
319
320struct clk div4_clks[DIV4_NR] = {
321 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
326 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
327 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
328 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
330 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
332};
333
349/* DIV6 reparent */ 334/* DIV6 reparent */
350enum { 335enum {
351 DIV6_HDMI, 336 DIV6_HDMI,
@@ -391,6 +376,16 @@ static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
391 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2), 376 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
392}; 377};
393 378
379/* DIV6 clocks */
380enum {
381 DIV6_SUB,
382 DIV6_NR
383};
384
385static struct clk div6_clks[DIV6_NR] = {
386 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
387};
388
394/* HDMI1/2 clock */ 389/* HDMI1/2 clock */
395static unsigned long hdmi12_recalc(struct clk *clk) 390static unsigned long hdmi12_recalc(struct clk *clk)
396{ 391{
@@ -456,35 +451,6 @@ static struct clk fsidivs[] = {
456 451
457/* MSTP */ 452/* MSTP */
458enum { 453enum {
459 DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
460 DIV4_HPP, DIV4_USBP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
461 DIV4_NR
462};
463
464struct clk div4_clks[DIV4_NR] = {
465 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
466 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
467 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
468 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
469 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
470 [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
471 [DIV4_USBP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 16, 0x6fff, 0),
472 [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
473 [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
474 [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
475 [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
476};
477
478enum {
479 DIV6_SUB,
480 DIV6_NR
481};
482
483static struct clk div6_clks[DIV6_NR] = {
484 [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
485};
486
487enum {
488 MSTP128, MSTP127, MSTP125, 454 MSTP128, MSTP127, MSTP125,
489 MSTP116, MSTP111, MSTP100, MSTP117, 455 MSTP116, MSTP111, MSTP100, MSTP117,
490 456
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
new file mode 100644
index 000000000000..cd6855290b1f
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -0,0 +1,107 @@
1/*
2 * r8a7778 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2011 Renesas Solutions Corp.
10 * Copyright (C) 2011 Magnus Damm
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 */
25
26#include <linux/io.h>
27#include <linux/sh_clk.h>
28#include <linux/clkdev.h>
29#include <mach/common.h>
30
31#define MSTPCR0 IOMEM(0xffc80030)
32#define MSTPCR1 IOMEM(0xffc80034)
33#define MSTPCR3 IOMEM(0xffc8003c)
34#define MSTPSR1 IOMEM(0xffc80044)
35#define MSTPSR4 IOMEM(0xffc80048)
36#define MSTPSR6 IOMEM(0xffc8004c)
37#define MSTPCR4 IOMEM(0xffc80050)
38#define MSTPCR5 IOMEM(0xffc80054)
39#define MSTPCR6 IOMEM(0xffc80058)
40
41/* ioremap() through clock mapping mandatory to avoid
42 * collision with ARM coherent DMA virtual memory range.
43 */
44
45static struct clk_mapping cpg_mapping = {
46 .phys = 0xffc80000,
47 .len = 0x80,
48};
49
50static struct clk clkp = {
51 .rate = 62500000, /* FIXME: shortcut */
52 .flags = CLK_ENABLE_ON_INIT,
53 .mapping = &cpg_mapping,
54};
55
56static struct clk *main_clks[] = {
57 &clkp,
58};
59
60enum {
61 MSTP114,
62 MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
63 MSTP016, MSTP015,
64 MSTP_NR };
65
66static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP114] = SH_CLK_MSTP32(&clkp, MSTPCR1, 14, 0), /* Ether */
68 [MSTP026] = SH_CLK_MSTP32(&clkp, MSTPCR0, 26, 0), /* SCIF0 */
69 [MSTP025] = SH_CLK_MSTP32(&clkp, MSTPCR0, 25, 0), /* SCIF1 */
70 [MSTP024] = SH_CLK_MSTP32(&clkp, MSTPCR0, 24, 0), /* SCIF2 */
71 [MSTP023] = SH_CLK_MSTP32(&clkp, MSTPCR0, 23, 0), /* SCIF3 */
72 [MSTP022] = SH_CLK_MSTP32(&clkp, MSTPCR0, 22, 0), /* SCIF4 */
73 [MSTP021] = SH_CLK_MSTP32(&clkp, MSTPCR0, 21, 0), /* SCIF5 */
74 [MSTP016] = SH_CLK_MSTP32(&clkp, MSTPCR0, 16, 0), /* TMU0 */
75 [MSTP015] = SH_CLK_MSTP32(&clkp, MSTPCR0, 15, 0), /* TMU1 */
76};
77
78static struct clk_lookup lookups[] = {
79 /* MSTP32 clocks */
80 CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
81 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
82 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
83 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
84 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
85 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
86 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
87 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
88 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
89};
90
91void __init r8a7778_clock_init(void)
92{
93 int k, ret = 0;
94
95 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
96 ret = clk_register(main_clks[k]);
97
98 if (!ret)
99 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
100
101 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
102
103 if (!ret)
104 shmobile_clk_init();
105 else
106 panic("failed to setup r8a7778 clocks\n");
107}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index d9edeaf66007..7d86bfbb5b06 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -17,13 +17,17 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20#include <linux/bitops.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
24#include <linux/clkdev.h> 25#include <linux/clkdev.h>
26#include <mach/clock.h>
25#include <mach/common.h> 27#include <mach/common.h>
26 28
29#define MD(nr) BIT(nr)
30
27#define FRQMR IOMEM(0xffc80014) 31#define FRQMR IOMEM(0xffc80014)
28#define MSTPCR0 IOMEM(0xffc80030) 32#define MSTPCR0 IOMEM(0xffc80030)
29#define MSTPCR1 IOMEM(0xffc80034) 33#define MSTPCR1 IOMEM(0xffc80034)
@@ -36,6 +40,9 @@
36#define MSTPCR6 IOMEM(0xffc80058) 40#define MSTPCR6 IOMEM(0xffc80058)
37#define MSTPCR7 IOMEM(0xffc80040) 41#define MSTPCR7 IOMEM(0xffc80040)
38 42
43#define MODEMR 0xffcc0020
44
45
39/* ioremap() through clock mapping mandatory to avoid 46/* ioremap() through clock mapping mandatory to avoid
40 * collision with ARM coherent DMA virtual memory range. 47 * collision with ARM coherent DMA virtual memory range.
41 */ 48 */
@@ -50,40 +57,39 @@ static struct clk_mapping cpg_mapping = {
50 * from the platform code. 57 * from the platform code.
51 */ 58 */
52static struct clk plla_clk = { 59static struct clk plla_clk = {
53 .rate = 1500000000, 60 /* .rate will be updated on r8a7779_clock_init() */
54 .mapping = &cpg_mapping, 61 .mapping = &cpg_mapping,
55}; 62};
56 63
64/*
65 * clock ratio of these clock will be updated
66 * on r8a7779_clock_init()
67 */
68SH_FIXED_RATIO_CLK_SET(clkz_clk, plla_clk, 1, 1);
69SH_FIXED_RATIO_CLK_SET(clkzs_clk, plla_clk, 1, 1);
70SH_FIXED_RATIO_CLK_SET(clki_clk, plla_clk, 1, 1);
71SH_FIXED_RATIO_CLK_SET(clks_clk, plla_clk, 1, 1);
72SH_FIXED_RATIO_CLK_SET(clks1_clk, plla_clk, 1, 1);
73SH_FIXED_RATIO_CLK_SET(clks3_clk, plla_clk, 1, 1);
74SH_FIXED_RATIO_CLK_SET(clks4_clk, plla_clk, 1, 1);
75SH_FIXED_RATIO_CLK_SET(clkb_clk, plla_clk, 1, 1);
76SH_FIXED_RATIO_CLK_SET(clkout_clk, plla_clk, 1, 1);
77SH_FIXED_RATIO_CLK_SET(clkp_clk, plla_clk, 1, 1);
78SH_FIXED_RATIO_CLK_SET(clkg_clk, plla_clk, 1, 1);
79
57static struct clk *main_clks[] = { 80static struct clk *main_clks[] = {
58 &plla_clk, 81 &plla_clk,
59}; 82 &clkz_clk,
60 83 &clkzs_clk,
61static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 }; 84 &clki_clk,
62 85 &clks_clk,
63static struct clk_div_mult_table div4_div_mult_table = { 86 &clks1_clk,
64 .divisors = divisors, 87 &clks3_clk,
65 .nr_divisors = ARRAY_SIZE(divisors), 88 &clks4_clk,
66}; 89 &clkb_clk,
67 90 &clkout_clk,
68static struct clk_div4_table div4_table = { 91 &clkp_clk,
69 .div_mult_table = &div4_div_mult_table, 92 &clkg_clk,
70};
71
72enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
73
74static struct clk div4_clks[DIV4_NR] = {
75 [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
76 0x0018, CLK_ENABLE_ON_INIT),
77 [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
78 0x0700, CLK_ENABLE_ON_INIT),
79 [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
80 0x0040, CLK_ENABLE_ON_INIT),
81 [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
82 0x0010, CLK_ENABLE_ON_INIT),
83 [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
84 0x0060, CLK_ENABLE_ON_INIT),
85 [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
86 0x0300, CLK_ENABLE_ON_INIT),
87}; 93};
88 94
89enum { MSTP323, MSTP322, MSTP321, MSTP320, 95enum { MSTP323, MSTP322, MSTP321, MSTP320,
@@ -96,52 +102,28 @@ enum { MSTP323, MSTP322, MSTP321, MSTP320,
96 MSTP_NR }; 102 MSTP_NR };
97 103
98static struct clk mstp_clks[MSTP_NR] = { 104static struct clk mstp_clks[MSTP_NR] = {
99 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */ 105 [MSTP323] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 23, 0), /* SDHI0 */
100 [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */ 106 [MSTP322] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 22, 0), /* SDHI1 */
101 [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */ 107 [MSTP321] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 21, 0), /* SDHI2 */
102 [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */ 108 [MSTP320] = SH_CLK_MSTP32(&clkp_clk, MSTPCR3, 20, 0), /* SDHI3 */
103 [MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */ 109 [MSTP115] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 15, 0), /* SATA */
104 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */ 110 [MSTP103] = SH_CLK_MSTP32(&clks_clk, MSTPCR1, 3, 0), /* DU */
105 [MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */ 111 [MSTP101] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 1, 0), /* USB2 */
106 [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */ 112 [MSTP100] = SH_CLK_MSTP32(&clkp_clk, MSTPCR1, 0, 0), /* USB0/1 */
107 [MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */ 113 [MSTP030] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 30, 0), /* I2C0 */
108 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0), /* I2C1 */ 114 [MSTP029] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 29, 0), /* I2C1 */
109 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0), /* I2C2 */ 115 [MSTP028] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 28, 0), /* I2C2 */
110 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0), /* I2C3 */ 116 [MSTP027] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 27, 0), /* I2C3 */
111 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */ 117 [MSTP026] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 26, 0), /* SCIF0 */
112 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */ 118 [MSTP025] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 25, 0), /* SCIF1 */
113 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */ 119 [MSTP024] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 24, 0), /* SCIF2 */
114 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */ 120 [MSTP023] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 23, 0), /* SCIF3 */
115 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */ 121 [MSTP022] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 22, 0), /* SCIF4 */
116 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */ 122 [MSTP021] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 21, 0), /* SCIF5 */
117 [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */ 123 [MSTP016] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 16, 0), /* TMU0 */
118 [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */ 124 [MSTP015] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 15, 0), /* TMU1 */
119 [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */ 125 [MSTP014] = SH_CLK_MSTP32(&clkp_clk, MSTPCR0, 14, 0), /* TMU2 */
120 [MSTP007] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR0, 7, 0), /* HSPI */ 126 [MSTP007] = SH_CLK_MSTP32(&clks_clk, MSTPCR0, 7, 0), /* HSPI */
121};
122
123static unsigned long mul4_recalc(struct clk *clk)
124{
125 return clk->parent->rate * 4;
126}
127
128static struct sh_clk_ops mul4_clk_ops = {
129 .recalc = mul4_recalc,
130};
131
132struct clk clkz_clk = {
133 .ops = &mul4_clk_ops,
134 .parent = &div4_clks[DIV4_S],
135};
136
137struct clk clkzs_clk = {
138 /* clks x 4 / 4 = clks */
139 .parent = &div4_clks[DIV4_S],
140};
141
142static struct clk *late_main_clks[] = {
143 &clkz_clk,
144 &clkzs_clk,
145}; 127};
146 128
147static struct clk_lookup lookups[] = { 129static struct clk_lookup lookups[] = {
@@ -151,12 +133,12 @@ static struct clk_lookup lookups[] = {
151 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk), 133 CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
152 134
153 /* DIV4 clocks */ 135 /* DIV4 clocks */
154 CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]), 136 CLKDEV_CON_ID("shyway_clk", &clks_clk),
155 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]), 137 CLKDEV_CON_ID("bus_clk", &clkout_clk),
156 CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]), 138 CLKDEV_CON_ID("shyway4_clk", &clks4_clk),
157 CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]), 139 CLKDEV_CON_ID("shyway3_clk", &clks3_clk),
158 CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]), 140 CLKDEV_CON_ID("shyway1_clk", &clks1_clk),
159 CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), 141 CLKDEV_CON_ID("peripheral_clk", &clkp_clk),
160 142
161 /* MSTP32 clocks */ 143 /* MSTP32 clocks */
162 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */ 144 CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
@@ -190,20 +172,60 @@ static struct clk_lookup lookups[] = {
190 172
191void __init r8a7779_clock_init(void) 173void __init r8a7779_clock_init(void)
192{ 174{
175 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
176 u32 mode;
193 int k, ret = 0; 177 int k, ret = 0;
194 178
179 BUG_ON(!modemr);
180 mode = ioread32(modemr);
181 iounmap(modemr);
182
183 if (mode & MD(1)) {
184 plla_clk.rate = 1500000000;
185
186 SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3);
187 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6);
188 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
189 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6);
190 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12);
191 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
192 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
193 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24);
194 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
195 if (mode & MD(2)) {
196 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36);
197 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 36);
198 } else {
199 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
200 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
201 }
202 } else {
203 plla_clk.rate = 1600000000;
204
205 SH_CLK_SET_RATIO(&clkz_clk_ratio, 1, 2);
206 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 8);
207 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2);
208 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 8);
209 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 16);
210 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8);
211 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16);
212 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 32);
213 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24);
214 if (mode & MD(2)) {
215 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 32);
216 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 32);
217 } else {
218 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 24);
219 SH_CLK_SET_RATIO(&clkout_clk_ratio, 1, 24);
220 }
221 }
222
195 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) 223 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
196 ret = clk_register(main_clks[k]); 224 ret = clk_register(main_clks[k]);
197 225
198 if (!ret) 226 if (!ret)
199 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
200
201 if (!ret)
202 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR); 227 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
203 228
204 for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
205 ret = clk_register(late_main_clks[k]);
206
207 clkdev_add_table(lookups, ARRAY_SIZE(lookups)); 229 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
208 230
209 if (!ret) 231 if (!ret)
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
new file mode 100644
index 000000000000..bad9bf2e34d6
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -0,0 +1,93 @@
1/*
2 * r8a7790 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/sh_clk.h>
24#include <linux/clkdev.h>
25#include <mach/common.h>
26
27#define CPG_BASE 0xe6150000
28#define CPG_LEN 0x1000
29
30#define SMSTPCR2 0xe6150138
31#define SMSTPCR7 0xe615014c
32
33static struct clk_mapping cpg_mapping = {
34 .phys = CPG_BASE,
35 .len = CPG_LEN,
36};
37
38static struct clk p_clk = {
39 .rate = 65000000, /* shortcut for now */
40 .mapping = &cpg_mapping,
41};
42
43static struct clk mp_clk = {
44 .rate = 52000000, /* shortcut for now */
45 .mapping = &cpg_mapping,
46};
47
48static struct clk *main_clks[] = {
49 &p_clk,
50 &mp_clk,
51};
52
53enum { MSTP721, MSTP720,
54 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP_NR };
55static struct clk mstp_clks[MSTP_NR] = {
56 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
57 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
58 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
59 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
60 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
61 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
62 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
63 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
64};
65
66static struct clk_lookup lookups[] = {
67 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
68 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
69 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
70 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
71 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
72 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
73 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
74 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
75};
76
77void __init r8a7790_clock_init(void)
78{
79 int k, ret = 0;
80
81 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
82 ret = clk_register(main_clks[k]);
83
84 if (!ret)
85 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
86
87 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
88
89 if (!ret)
90 shmobile_clk_init();
91 else
92 panic("failed to setup r8a7790 clocks\n");
93}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 45d21fe317f4..7e105932c09d 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -21,6 +21,7 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <mach/clock.h>
24#include <mach/common.h> 25#include <mach/common.h>
25 26
26/* SH7372 registers */ 27/* SH7372 registers */
@@ -83,39 +84,12 @@ struct clk sh7372_extal2_clk = {
83 .rate = 48000000, 84 .rate = 48000000,
84}; 85};
85 86
86/* A fixed divide-by-2 block */ 87SH_CLK_RATIO(div2, 1, 2);
87static unsigned long div2_recalc(struct clk *clk)
88{
89 return clk->parent->rate / 2;
90}
91
92static struct sh_clk_ops div2_clk_ops = {
93 .recalc = div2_recalc,
94};
95 88
96/* Divide dv_clki by two */ 89SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
97struct clk sh7372_dv_clki_div2_clk = { 90SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
98 .ops = &div2_clk_ops, 91SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
99 .parent = &sh7372_dv_clki_clk, 92SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
100};
101
102/* Divide extal1 by two */
103static struct clk extal1_div2_clk = {
104 .ops = &div2_clk_ops,
105 .parent = &sh7372_extal1_clk,
106};
107
108/* Divide extal2 by two */
109static struct clk extal2_div2_clk = {
110 .ops = &div2_clk_ops,
111 .parent = &sh7372_extal2_clk,
112};
113
114/* Divide extal2 by four */
115static struct clk extal2_div4_clk = {
116 .ops = &div2_clk_ops,
117 .parent = &extal2_div2_clk,
118};
119 93
120/* PLLC0 and PLLC1 */ 94/* PLLC0 and PLLC1 */
121static unsigned long pllc01_recalc(struct clk *clk) 95static unsigned long pllc01_recalc(struct clk *clk)
@@ -147,10 +121,7 @@ static struct clk pllc1_clk = {
147}; 121};
148 122
149/* Divide PLLC1 by two */ 123/* Divide PLLC1 by two */
150static struct clk pllc1_div2_clk = { 124SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
151 .ops = &div2_clk_ops,
152 .parent = &pllc1_clk,
153};
154 125
155/* PLLC2 */ 126/* PLLC2 */
156 127
@@ -342,7 +313,7 @@ static struct clk_div4_table div4_table = {
342}; 313};
343 314
344enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, 315enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
345 DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, 316 DIV4_ZX, DIV4_HP,
346 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP, 317 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
347 DIV4_DDRP, DIV4_NR }; 318 DIV4_DDRP, DIV4_NR };
348 319
@@ -355,8 +326,6 @@ static struct clk div4_clks[DIV4_NR] = {
355 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 326 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
356 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT), 327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
357 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0), 328 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
358 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0x6fff, 0),
359 [DIV4_ZT] = DIV4(FRQCRB, 16, 0x6fff, 0),
360 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0), 329 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
361 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0), 330 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
362 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0), 331 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
@@ -516,8 +485,6 @@ static struct clk_lookup lookups[] = {
516 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), 485 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
517 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]), 486 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
518 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]), 487 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
519 CLKDEV_CON_ID("ztr_clk", &div4_clks[DIV4_ZTR]),
520 CLKDEV_CON_ID("zt_clk", &div4_clks[DIV4_ZT]),
521 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]), 488 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
522 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]), 489 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
523 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]), 490 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
@@ -654,5 +621,4 @@ void __init sh7372_clock_init(void)
654 shmobile_clk_init(); 621 shmobile_clk_init();
655 else 622 else
656 panic("failed to setup sh7372 clocks\n"); 623 panic("failed to setup sh7372 clocks\n");
657
658} 624}
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 71843dd39e16..784fbaa4cc55 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -21,6 +21,8 @@
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/sh_clk.h> 22#include <linux/sh_clk.h>
23#include <linux/clkdev.h> 23#include <linux/clkdev.h>
24#include <asm/processor.h>
25#include <mach/clock.h>
24#include <mach/common.h> 26#include <mach/common.h>
25 27
26#define FRQCRA IOMEM(0xe6150000) 28#define FRQCRA IOMEM(0xe6150000)
@@ -82,61 +84,16 @@ struct clk sh73a0_extal2_clk = {
82 .rate = 48000000, 84 .rate = 48000000,
83}; 85};
84 86
85/* A fixed divide-by-2 block */
86static unsigned long div2_recalc(struct clk *clk)
87{
88 return clk->parent->rate / 2;
89}
90
91static struct sh_clk_ops div2_clk_ops = {
92 .recalc = div2_recalc,
93};
94
95static unsigned long div7_recalc(struct clk *clk)
96{
97 return clk->parent->rate / 7;
98}
99
100static struct sh_clk_ops div7_clk_ops = {
101 .recalc = div7_recalc,
102};
103
104static unsigned long div13_recalc(struct clk *clk)
105{
106 return clk->parent->rate / 13;
107}
108
109static struct sh_clk_ops div13_clk_ops = {
110 .recalc = div13_recalc,
111};
112
113/* Divide extal1 by two */
114static struct clk extal1_div2_clk = {
115 .ops = &div2_clk_ops,
116 .parent = &sh73a0_extal1_clk,
117};
118
119/* Divide extal2 by two */
120static struct clk extal2_div2_clk = {
121 .ops = &div2_clk_ops,
122 .parent = &sh73a0_extal2_clk,
123};
124
125static struct sh_clk_ops main_clk_ops = { 87static struct sh_clk_ops main_clk_ops = {
126 .recalc = followparent_recalc, 88 .recalc = followparent_recalc,
127}; 89};
128 90
129/* Main clock */ 91/* Main clock */
130static struct clk main_clk = { 92static struct clk main_clk = {
93 /* .parent wll be set on sh73a0_clock_init() */
131 .ops = &main_clk_ops, 94 .ops = &main_clk_ops,
132}; 95};
133 96
134/* Divide Main clock by two */
135static struct clk main_div2_clk = {
136 .ops = &div2_clk_ops,
137 .parent = &main_clk,
138};
139
140/* PLL0, PLL1, PLL2, PLL3 */ 97/* PLL0, PLL1, PLL2, PLL3 */
141static unsigned long pll_recalc(struct clk *clk) 98static unsigned long pll_recalc(struct clk *clk)
142{ 99{
@@ -192,21 +149,17 @@ static struct clk pll3_clk = {
192 .enable_bit = 3, 149 .enable_bit = 3,
193}; 150};
194 151
195/* Divide PLL */ 152/* A fixed divide block */
196static struct clk pll1_div2_clk = { 153SH_CLK_RATIO(div2, 1, 2);
197 .ops = &div2_clk_ops, 154SH_CLK_RATIO(div7, 1, 7);
198 .parent = &pll1_clk, 155SH_CLK_RATIO(div13, 1, 13);
199};
200
201static struct clk pll1_div7_clk = {
202 .ops = &div7_clk_ops,
203 .parent = &pll1_clk,
204};
205 156
206static struct clk pll1_div13_clk = { 157SH_FIXED_RATIO_CLK(extal1_div2_clk, sh73a0_extal1_clk, div2);
207 .ops = &div13_clk_ops, 158SH_FIXED_RATIO_CLK(extal2_div2_clk, sh73a0_extal2_clk, div2);
208 .parent = &pll1_clk, 159SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
209}; 160SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
161SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
162SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
210 163
211/* External input clock */ 164/* External input clock */
212struct clk sh73a0_extcki_clk = { 165struct clk sh73a0_extcki_clk = {
@@ -234,14 +187,24 @@ static struct clk *main_clks[] = {
234 &sh73a0_extalr_clk, 187 &sh73a0_extalr_clk,
235}; 188};
236 189
237static void div4_kick(struct clk *clk) 190static int frqcr_kick(void)
238{ 191{
239 unsigned long value; 192 int i;
193
194 /* set KICK bit in FRQCRB to update hardware setting, check success */
195 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB);
196 for (i = 1000; i; i--)
197 if (__raw_readl(FRQCRB) & (1 << 31))
198 cpu_relax();
199 else
200 return i;
240 201
241 /* set KICK bit in FRQCRB to update hardware setting */ 202 return -ETIMEDOUT;
242 value = __raw_readl(FRQCRB); 203}
243 value |= (1 << 31); 204
244 __raw_writel(value, FRQCRB); 205static void div4_kick(struct clk *clk)
206{
207 frqcr_kick();
245} 208}
246 209
247static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 210static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
@@ -258,7 +221,7 @@ static struct clk_div4_table div4_table = {
258}; 221};
259 222
260enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2, 223enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
261 DIV4_Z, DIV4_ZTR, DIV4_ZT, DIV4_ZX, DIV4_HP, DIV4_NR }; 224 DIV4_Z, DIV4_ZX, DIV4_HP, DIV4_NR };
262 225
263#define DIV4(_reg, _bit, _mask, _flags) \ 226#define DIV4(_reg, _bit, _mask, _flags) \
264 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags) 227 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
@@ -271,12 +234,24 @@ static struct clk div4_clks[DIV4_NR] = {
271 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0), 234 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
272 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0), 235 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
273 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0), 236 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
274 [DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
275 [DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
276 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0), 237 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
277 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0), 238 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
278}; 239};
279 240
241static unsigned long twd_recalc(struct clk *clk)
242{
243 return clk_get_rate(clk->parent) / 4;
244}
245
246static struct sh_clk_ops twd_clk_ops = {
247 .recalc = twd_recalc,
248};
249
250static struct clk twd_clk = {
251 .parent = &div4_clks[DIV4_Z],
252 .ops = &twd_clk_ops,
253};
254
280enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1, 255enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
281 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2, 256 DIV6_FLCTL, DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
282 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, 257 DIV6_FSIA, DIV6_FSIB, DIV6_SUB,
@@ -471,6 +446,7 @@ static struct clk dsi1phy_clk = {
471static struct clk *late_main_clks[] = { 446static struct clk *late_main_clks[] = {
472 &dsi0phy_clk, 447 &dsi0phy_clk,
473 &dsi1phy_clk, 448 &dsi1phy_clk,
449 &twd_clk,
474}; 450};
475 451
476enum { MSTP001, 452enum { MSTP001,
@@ -535,6 +511,7 @@ static struct clk mstp_clks[MSTP_NR] = {
535static struct clk_lookup lookups[] = { 511static struct clk_lookup lookups[] = {
536 /* main clocks */ 512 /* main clocks */
537 CLKDEV_CON_ID("r_clk", &r_clk), 513 CLKDEV_CON_ID("r_clk", &r_clk),
514 CLKDEV_DEV_ID("smp_twd", &twd_clk), /* smp_twd */
538 515
539 /* DIV6 clocks */ 516 /* DIV6 clocks */
540 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]), 517 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index e816ca9bd213..ad7df629d995 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -23,6 +23,19 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/sh_clk.h> 24#include <linux/sh_clk.h>
25#include <linux/export.h> 25#include <linux/export.h>
26#include <mach/clock.h>
27#include <mach/common.h>
28
29unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk)
30{
31 struct clk_ratio *p = clk->priv;
32
33 return clk->parent->rate / p->div * p->mul;
34};
35
36struct sh_clk_ops shmobile_fixed_ratio_clk_ops = {
37 .recalc = shmobile_fixed_ratio_clk_recalc,
38};
26 39
27int __init shmobile_clk_init(void) 40int __init shmobile_clk_init(void)
28{ 41{
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
new file mode 100644
index 000000000000..76ac61292e48
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -0,0 +1,39 @@
1#ifndef CLOCK_H
2#define CLOCK_H
3
4unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
5extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
6
7/* clock ratio */
8struct clk_ratio {
9 int mul;
10 int div;
11};
12
13#define SH_CLK_RATIO(name, m, d) \
14static struct clk_ratio name ##_ratio = { \
15 .mul = m, \
16 .div = d, \
17}
18
19#define SH_FIXED_RATIO_CLKg(name, p, r) \
20struct clk name = { \
21 .parent = &p, \
22 .ops = &shmobile_fixed_ratio_clk_ops,\
23 .priv = &r ## _ratio, \
24}
25
26#define SH_FIXED_RATIO_CLK(name, p, r) \
27static SH_FIXED_RATIO_CLKg(name, p, r);
28
29#define SH_FIXED_RATIO_CLK_SET(name, p, m, d) \
30 SH_CLK_RATIO(name, m, d); \
31 SH_FIXED_RATIO_CLK(name, p, name);
32
33#define SH_CLK_SET_RATIO(p, m, d) \
34{ \
35 (p)->mul = m; \
36 (p)->div = d; \
37}
38
39#endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 1fef737a4c1a..4634a5d4b63f 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -16,60 +16,6 @@ extern struct platform_suspend_ops shmobile_suspend_ops;
16struct cpuidle_driver; 16struct cpuidle_driver;
17extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 17extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
18 18
19extern void sh7372_init_irq(void);
20extern void sh7372_map_io(void);
21extern void sh7372_earlytimer_init(void);
22extern void sh7372_add_early_devices(void);
23extern void sh7372_add_standard_devices(void);
24extern void sh7372_add_early_devices_dt(void);
25extern void sh7372_add_standard_devices_dt(void);
26extern void sh7372_clock_init(void);
27extern void sh7372_pinmux_init(void);
28extern void sh7372_pm_init(void);
29extern void sh7372_resume_core_standby_sysc(void);
30extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
31extern struct clk sh7372_extal1_clk;
32extern struct clk sh7372_extal2_clk;
33
34extern void sh73a0_init_delay(void);
35extern void sh73a0_init_irq(void);
36extern void sh73a0_init_irq_dt(void);
37extern void sh73a0_map_io(void);
38extern void sh73a0_earlytimer_init(void);
39extern void sh73a0_add_early_devices(void);
40extern void sh73a0_add_standard_devices(void);
41extern void sh73a0_add_standard_devices_dt(void);
42extern void sh73a0_clock_init(void);
43extern void sh73a0_pinmux_init(void);
44extern void sh73a0_pm_init(void);
45extern struct clk sh73a0_extal1_clk;
46extern struct clk sh73a0_extal2_clk;
47extern struct clk sh73a0_extcki_clk;
48extern struct clk sh73a0_extalr_clk;
49
50extern void r8a7740_meram_workaround(void);
51extern void r8a7740_init_irq(void);
52extern void r8a7740_map_io(void);
53extern void r8a7740_add_early_devices(void);
54extern void r8a7740_add_standard_devices(void);
55extern void r8a7740_clock_init(u8 md_ck);
56extern void r8a7740_pinmux_init(void);
57extern void r8a7740_pm_init(void);
58
59extern void r8a7779_init_delay(void);
60extern void r8a7779_init_irq(void);
61extern void r8a7779_init_irq_extpin(int irlm);
62extern void r8a7779_init_irq_dt(void);
63extern void r8a7779_map_io(void);
64extern void r8a7779_earlytimer_init(void);
65extern void r8a7779_add_early_devices(void);
66extern void r8a7779_add_standard_devices(void);
67extern void r8a7779_add_standard_devices_dt(void);
68extern void r8a7779_clock_init(void);
69extern void r8a7779_pinmux_init(void);
70extern void r8a7779_pm_init(void);
71extern void r8a7779_register_twd(void);
72
73#ifdef CONFIG_SUSPEND 19#ifdef CONFIG_SUSPEND
74int shmobile_suspend_init(void); 20int shmobile_suspend_init(void);
75#else 21#else
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
new file mode 100644
index 000000000000..f043103e32c9
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_R8A73A4_H__
2#define __ASM_R8A73A4_H__
3
4void r8a73a4_add_standard_devices(void);
5void r8a73a4_clock_init(void);
6void r8a73a4_pinmux_init(void);
7
8#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index c2583610ad36..abdc4d4efa28 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -532,6 +532,15 @@ enum {
532 SHDMA_SLAVE_USBHS_RX, 532 SHDMA_SLAVE_USBHS_RX,
533}; 533};
534 534
535extern void r8a7740_meram_workaround(void);
536extern void r8a7740_init_irq(void);
537extern void r8a7740_map_io(void);
538extern void r8a7740_add_early_devices(void);
539extern void r8a7740_add_standard_devices(void);
540extern void r8a7740_clock_init(u8 md_ck);
541extern void r8a7740_pinmux_init(void);
542extern void r8a7740_pm_init(void);
543
535#ifdef CONFIG_PM 544#ifdef CONFIG_PM
536extern void __init r8a7740_init_pm_domains(void); 545extern void __init r8a7740_init_pm_domains(void);
537#else 546#else
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
new file mode 100644
index 000000000000..951149e6bcca
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18#ifndef __ASM_R8A7778_H__
19#define __ASM_R8A7778_H__
20
21#include <linux/sh_eth.h>
22
23extern void r8a7778_add_standard_devices(void);
24extern void r8a7778_add_standard_devices_dt(void);
25extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
26extern void r8a7778_init_delay(void);
27extern void r8a7778_init_irq(void);
28extern void r8a7778_init_irq_dt(void);
29extern void r8a7778_clock_init(void);
30extern void r8a7778_init_irq_extpin(int irlm);
31
32#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 8ea0ad18cdff..945299ed1638 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,323 +4,6 @@
4#include <linux/sh_clk.h> 4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h> 5#include <linux/pm_domain.h>
6 6
7/* Pin Function Controller:
8 * GPIO_FN_xx - GPIO used to select pin function
9 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
10 */
11enum {
12 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
13 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
14 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
15 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
16 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
17 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
18 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
19 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
20
21 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
22 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
23 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
24 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
25 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
26 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
27 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
28 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
29
30 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
31 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
32 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
33 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
34 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
35 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
36 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
37 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
38
39 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
40 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
41 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
42 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
43 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
44 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
45 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
46 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
47
48 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
49 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
50 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
51 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
52 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
53 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
54 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
55 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
56
57 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
58 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
59 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
60 GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
61 GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
62 GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
63 GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
64 GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
65
66 GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
67 GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
68 GPIO_GP_6_8,
69
70 GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
71 GPIO_FN_A19,
72
73 /* IPSR0 */
74 GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS,
76 GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_A0,
78 GPIO_FN_FD3, GPIO_FN_A20,
79 GPIO_FN_A21,
80 GPIO_FN_A22, GPIO_FN_VI1_R0,
81 GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_VI1_R1,
82 GPIO_FN_A24, GPIO_FN_FD4,
83 GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
84 GPIO_FN_FD5,
85 GPIO_FN_VI1_R3, GPIO_FN_SSI_SDATA7_B,
86 GPIO_FN_CLKOUT, GPIO_FN_PWM0_B,
87 GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
88 GPIO_FN_VI1_R7, GPIO_FN_HRTS1,
89
90 /* IPSR1 */
91 GPIO_FN_FD6, GPIO_FN_FD7,
92 GPIO_FN_FALE,
93 GPIO_FN_ATACS00,
94 GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4,
95 GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B,
96 GPIO_FN_SSI_SDATA9,
97 GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5,
98 GPIO_FN_HTX1, GPIO_FN_SSI_SCK9,
99 GPIO_FN_FD1,
100 GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1,
101 GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
102 GPIO_FN_MLB_SIG, GPIO_FN_PWM3,
103 GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_HTX0,
104 GPIO_FN_SDATA, GPIO_FN_SUB_TCK,
105 GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
106 GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
107
108 /* IPSR2 */
109 GPIO_FN_HRX0, GPIO_FN_SCKZ,
110 GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
111 GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
112 GPIO_FN_HSCK0, GPIO_FN_MTS, GPIO_FN_PWM5,
113 GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
114 GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
115 GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0,
116 GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_SCIF_CLK_C,
117 GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
118 GPIO_FN_MDATA, GPIO_FN_SUB_TMS,
119 GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
120 GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33,
121 GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
122 GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
123 GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1,
124 GPIO_FN_LCDOUT2, GPIO_FN_LCDOUT3,
125 GPIO_FN_LCDOUT4, GPIO_FN_LCDOUT5,
126 GPIO_FN_LCDOUT6, GPIO_FN_LCDOUT7,
127 GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
128 GPIO_FN_AUDATA2,
129
130 /* IPSR3 */
131 GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
132 GPIO_FN_AUDATA3, GPIO_FN_LCDOUT10,
133 GPIO_FN_LCDOUT11, GPIO_FN_LCDOUT12,
134 GPIO_FN_LCDOUT13, GPIO_FN_LCDOUT14,
135 GPIO_FN_LCDOUT15, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
136 GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4,
137 GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
138 GPIO_FN_AUDATA5, GPIO_FN_LCDOUT18,
139 GPIO_FN_LCDOUT19, GPIO_FN_LCDOUT20,
140 GPIO_FN_LCDOUT21, GPIO_FN_LCDOUT22,
141 GPIO_FN_LCDOUT23,
142 GPIO_FN_QSTVA_QVS, GPIO_FN_SCL3_B,
143 GPIO_FN_QCLK,
144 GPIO_FN_QSTVB_QVE, GPIO_FN_SDA3_B,
145 GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
146 GPIO_FN_QSTH_QHS,
147 GPIO_FN_QSTB_QHE,
148 GPIO_FN_QCPV_QDE,
149 GPIO_FN_CAN1_TX, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
150
151 /* IPSR4 */
152 GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C,
153 GPIO_FN_QPOLB, GPIO_FN_CAN1_RX,
154 GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B,
155 GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6,
156 GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
157 GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
158 GPIO_FN_AUDSYNC,
159 GPIO_FN_VI2_G0,
160 GPIO_FN_VI2_G1, GPIO_FN_VI2_G2,
161 GPIO_FN_VI2_G3, GPIO_FN_VI2_G4,
162 GPIO_FN_VI2_G5, GPIO_FN_VI2_DATA2_VI2_B2,
163 GPIO_FN_SCL1_B, GPIO_FN_AUDATA6,
164 GPIO_FN_VI2_DATA3_VI2_B3,
165 GPIO_FN_SDA1_B, GPIO_FN_AUDATA7,
166 GPIO_FN_VI2_G6,
167 GPIO_FN_VI2_G7, GPIO_FN_VI2_R0,
168 GPIO_FN_VI2_R1, GPIO_FN_VI2_R2,
169 GPIO_FN_VI2_R3, GPIO_FN_VI2_DATA4_VI2_B4,
170 GPIO_FN_SCL2_B,
171
172 /* IPSR5 */
173 GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
174 GPIO_FN_VI2_R4, GPIO_FN_VI2_R5,
175 GPIO_FN_VI2_R6, GPIO_FN_VI2_R7,
176 GPIO_FN_SCL2_D, GPIO_FN_SDA2_D,
177 GPIO_FN_VI2_CLKENB,
178 GPIO_FN_SCL1_D, GPIO_FN_VI2_FIELD,
179 GPIO_FN_SDA1_D, GPIO_FN_VI2_HSYNC,
180 GPIO_FN_VI3_HSYNC, GPIO_FN_VI2_VSYNC,
181 GPIO_FN_VI3_VSYNC,
182 GPIO_FN_VI2_CLK,
183 GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
184 GPIO_FN_AUDIO_CLKC, GPIO_FN_SPEEDIN,
185 GPIO_FN_GPS_SIGN_D, GPIO_FN_VI2_DATA6_VI2_B6,
186 GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B,
187 GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
188 GPIO_FN_VI2_DATA7_VI2_B7,
189 GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
190 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_GPS_CLK_C,
191 GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
192 GPIO_FN_AUDIO_CLKB, GPIO_FN_CAN_DEBUGOUT0,
193 GPIO_FN_MOUT0,
194
195 /* IPSR6 */
196 GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
197 GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
198 GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
199 GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
200 GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
201 GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
202 GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
203 GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
204 GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
205 GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
206 GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
207 GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
208 GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
209 GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_SSI_SDATA5,
210 GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12,
211 GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
212
213 /* IPSR7 */
214 GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
215 GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
216 GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13,
217 GPIO_FN_SSI_SCK9_B, GPIO_FN_SSI_WS78,
218 GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_SSI_WS9_B,
219 GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
220 GPIO_FN_TCLK1_C,
221 GPIO_FN_SSI_SDATA8, GPIO_FN_VSP,
222 GPIO_FN_ATACS01,
223 GPIO_FN_ATACS11, GPIO_FN_CC5_TDO,
224 GPIO_FN_ATADIR1, GPIO_FN_CC5_TRST,
225 GPIO_FN_ATAG1, GPIO_FN_CC5_TMS,
226 GPIO_FN_ATARD1, GPIO_FN_CC5_TCK,
227 GPIO_FN_ATAWR1, GPIO_FN_CC5_TDI,
228 GPIO_FN_DREQ2, GPIO_FN_DACK2,
229
230 /* IPSR8 */
231 GPIO_FN_AD_CLK,
232 GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
233 GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36,
234 GPIO_FN_AD_DI,
235 GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
236 GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37,
237 GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
238 GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
239 GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38,
240 GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
241 GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
242 GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
243 GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
244 GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB,
245 GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD,
246 GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
247 GPIO_FN_HSCK1_B,
248 GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
249 GPIO_FN_PWMFSW0_C,
250
251 /* IPSR9 */
252 GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
253 GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
254 GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_VI0_DATA3_VI0_B3,
255 GPIO_FN_VI0_DATA4_VI0_B4,
256 GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_VI0_DATA6_VI0_B6,
257 GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
258 GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
259 GPIO_FN_SSI_SCK78_C, GPIO_FN_ARM_TRACEDATA_2,
260 GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C,
261 GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
262 GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
263 GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV,
264 GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
265 GPIO_FN_ETH_TX_EN, GPIO_FN_ARM_TRACEDATA_6,
266 GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER,
267 GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
268 GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
269 GPIO_FN_ETH_RXD1, GPIO_FN_ARM_TRACEDATA_9,
270
271 /* IPSR10 */
272 GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_DREQ1_B,
273 GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
274 GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
275 GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
276 GPIO_FN_ARM_TRACEDATA_12,
277 GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC,
278 GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
279 GPIO_FN_ARM_TRACEDATA_14,
280 GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
281 GPIO_FN_ARM_TRACEDATA_15,
282 GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
283 GPIO_FN_DREQ2_C, GPIO_FN_TRACECLK,
284 GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
285 GPIO_FN_DACK2_C, GPIO_FN_SCIF_CLK_D,
286 GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
287 GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
288 GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
289 GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
290 GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
291
292 /* IPSR11 */
293 GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SIM_RST,
294 GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
295 GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
296 GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2,
297 GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
298 GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_MT0_BEN,
299 GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
300 GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
301 GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
302 GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
303 GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
304 GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS,
305 GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_MT0_PWM,
306 GPIO_FN_SPA_TDI, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
307 GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B,
308 GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
309 GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B,
310 GPIO_FN_HRTS0_B,
311
312 /* IPSR12 */
313 GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
314 GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
315 GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
316 GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
317 GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
318 GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_SIM_D_B,
319 GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
320 GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
321 GPIO_FN_GPS_MAG, GPIO_FN_FCE,
322};
323
324struct platform_device; 7struct platform_device;
325 8
326struct r8a7779_pm_ch { 9struct r8a7779_pm_ch {
@@ -339,6 +22,19 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
339 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; 22 return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
340} 23}
341 24
25extern void r8a7779_init_delay(void);
26extern void r8a7779_init_irq(void);
27extern void r8a7779_init_irq_extpin(int irlm);
28extern void r8a7779_init_irq_dt(void);
29extern void r8a7779_map_io(void);
30extern void r8a7779_earlytimer_init(void);
31extern void r8a7779_add_early_devices(void);
32extern void r8a7779_add_standard_devices(void);
33extern void r8a7779_add_standard_devices_dt(void);
34extern void r8a7779_clock_init(void);
35extern void r8a7779_pinmux_init(void);
36extern void r8a7779_pm_init(void);
37extern void r8a7779_register_twd(void);
342extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch); 38extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
343extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch); 39extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
344 40
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
new file mode 100644
index 000000000000..2e919e61fa0d
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_R8A7790_H__
2#define __ASM_R8A7790_H__
3
4void r8a7790_add_standard_devices(void);
5void r8a7790_clock_init(void);
6void r8a7790_pinmux_init(void);
7void r8a7790_timer_init(void);
8
9#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 7ded4ebaf5cc..fd7cba024c39 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -449,6 +449,18 @@ extern struct clk sh7372_dv_clki_clk;
449extern struct clk sh7372_dv_clki_div2_clk; 449extern struct clk sh7372_dv_clki_div2_clk;
450extern struct clk sh7372_pllc2_clk; 450extern struct clk sh7372_pllc2_clk;
451 451
452extern void sh7372_init_irq(void);
453extern void sh7372_map_io(void);
454extern void sh7372_earlytimer_init(void);
455extern void sh7372_add_early_devices(void);
456extern void sh7372_add_standard_devices(void);
457extern void sh7372_add_early_devices_dt(void);
458extern void sh7372_add_standard_devices_dt(void);
459extern void sh7372_clock_init(void);
460extern void sh7372_pinmux_init(void);
461extern void sh7372_pm_init(void);
462extern void sh7372_resume_core_standby_sysc(void);
463extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
452extern void sh7372_intcs_suspend(void); 464extern void sh7372_intcs_suspend(void);
453extern void sh7372_intcs_resume(void); 465extern void sh7372_intcs_resume(void);
454extern void sh7372_intca_suspend(void); 466extern void sh7372_intca_suspend(void);
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index fbc1584d6712..eb7a4320d487 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -444,6 +444,21 @@ enum {
444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700) 444#define SH73A0_PINT0_IRQ(irq) ((irq) + 700)
445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732) 445#define SH73A0_PINT1_IRQ(irq) ((irq) + 732)
446 446
447extern void sh73a0_init_delay(void);
448extern void sh73a0_init_irq(void);
449extern void sh73a0_init_irq_dt(void);
450extern void sh73a0_map_io(void);
451extern void sh73a0_earlytimer_init(void);
452extern void sh73a0_add_early_devices(void);
453extern void sh73a0_add_standard_devices(void);
454extern void sh73a0_add_standard_devices_dt(void);
455extern void sh73a0_clock_init(void);
456extern void sh73a0_pinmux_init(void);
457extern void sh73a0_pm_init(void);
458extern struct clk sh73a0_extal1_clk;
459extern struct clk sh73a0_extal2_clk;
460extern struct clk sh73a0_extcki_clk;
461extern struct clk sh73a0_extalr_clk;
447extern struct smp_operations sh73a0_smp_ops; 462extern struct smp_operations sh73a0_smp_ops;
448 463
449#endif /* __ASM_SH73A0_H__ */ 464#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index 9a69a31918ba..b741c8409a5a 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -18,620 +18,39 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/kernel.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h> 22#include <linux/io.h>
26#include <linux/sh_intc.h> 23#include <linux/irqchip/arm-gic.h>
27#include <mach/intc.h>
28#include <mach/irqs.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/*
33 * INTCA
34 */
35enum {
36 UNUSED_INTCA = 0,
37
38 /* interrupt sources INTCA */
39 DIRC,
40 ATAPI,
41 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
42 AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI, MFIS,
44 BBIF1, BBIF2,
45 USBHSDMAC,
46 USBF_OUL_SOF, USBF_IXL_INT,
47 SGX540,
48 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
49 CMT2,
50 CMT3,
51 KEYSC,
52 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
53 MSIOF2, MSIOF1,
54 SCIFA4, SCIFA5, SCIFB,
55 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
56 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
57 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
58 AP_ARM_L2CINT,
59 IRDA,
60 TPU0,
61 SCIFA6, SCIFA7,
62 GbEther,
63 ICBS0,
64 DDM,
65 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
66 RWDT0,
67 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
68 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 HDMI,
75 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
76 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
77 SPU2_0, SPU2_1,
78 FSI, FMSI,
79 HDMI_SSS, HDMI_KEY,
80 IPMMU,
81 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 MMCIF_0, MMCIF_1, MMCIF_2,
86 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
87 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
88
89 /* interrupt groups INTCA */
90 DMAC1_1, DMAC1_2,
91 DMAC2_1, DMAC2_2,
92 DMAC3_1, DMAC3_2,
93 AP_ARM1, AP_ARM2,
94 SDHI0, SDHI1, SDHI2,
95 SHWYSTAT,
96 USBF, USBH1, USBH2,
97 RSPI, SPU2, FLCTL, IIC1,
98};
99
100static struct intc_vect intca_vectors[] __initdata = {
101 INTC_VECT(DIRC, 0x0560),
102 INTC_VECT(ATAPI, 0x05E0),
103 INTC_VECT(IIC1_ALI, 0x0780),
104 INTC_VECT(IIC1_TACKI, 0x07A0),
105 INTC_VECT(IIC1_WAITI, 0x07C0),
106 INTC_VECT(IIC1_DTEI, 0x07E0),
107 INTC_VECT(AP_ARM_COMMTX, 0x0840),
108 INTC_VECT(AP_ARM_COMMRX, 0x0860),
109 INTC_VECT(MFI, 0x0900),
110 INTC_VECT(MFIS, 0x0920),
111 INTC_VECT(BBIF1, 0x0940),
112 INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC, 0x0A00),
114 INTC_VECT(USBF_OUL_SOF, 0x0A20),
115 INTC_VECT(USBF_IXL_INT, 0x0A40),
116 INTC_VECT(SGX540, 0x0A60),
117 INTC_VECT(CMT1_0, 0x0B00),
118 INTC_VECT(CMT1_1, 0x0B20),
119 INTC_VECT(CMT1_2, 0x0B40),
120 INTC_VECT(CMT1_3, 0x0B60),
121 INTC_VECT(CMT2, 0x0B80),
122 INTC_VECT(CMT3, 0x0BA0),
123 INTC_VECT(KEYSC, 0x0BE0),
124 INTC_VECT(SCIFA0, 0x0C00),
125 INTC_VECT(SCIFA1, 0x0C20),
126 INTC_VECT(SCIFA2, 0x0C40),
127 INTC_VECT(SCIFA3, 0x0C60),
128 INTC_VECT(MSIOF2, 0x0C80),
129 INTC_VECT(MSIOF1, 0x0D00),
130 INTC_VECT(SCIFA4, 0x0D20),
131 INTC_VECT(SCIFA5, 0x0D40),
132 INTC_VECT(SCIFB, 0x0D60),
133 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
134 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
135 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
136 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
137 INTC_VECT(SDHI0_0, 0x0E00),
138 INTC_VECT(SDHI0_1, 0x0E20),
139 INTC_VECT(SDHI0_2, 0x0E40),
140 INTC_VECT(SDHI0_3, 0x0E60),
141 INTC_VECT(SDHI1_0, 0x0E80),
142 INTC_VECT(SDHI1_1, 0x0EA0),
143 INTC_VECT(SDHI1_2, 0x0EC0),
144 INTC_VECT(SDHI1_3, 0x0EE0),
145 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
146 INTC_VECT(IRDA, 0x0480),
147 INTC_VECT(TPU0, 0x04A0),
148 INTC_VECT(SCIFA6, 0x04C0),
149 INTC_VECT(SCIFA7, 0x04E0),
150 INTC_VECT(GbEther, 0x0500),
151 INTC_VECT(ICBS0, 0x0540),
152 INTC_VECT(DDM, 0x1140),
153 INTC_VECT(SDHI2_0, 0x1200),
154 INTC_VECT(SDHI2_1, 0x1220),
155 INTC_VECT(SDHI2_2, 0x1240),
156 INTC_VECT(SDHI2_3, 0x1260),
157 INTC_VECT(RWDT0, 0x1280),
158 INTC_VECT(DMAC1_1_DEI0, 0x2000),
159 INTC_VECT(DMAC1_1_DEI1, 0x2020),
160 INTC_VECT(DMAC1_1_DEI2, 0x2040),
161 INTC_VECT(DMAC1_1_DEI3, 0x2060),
162 INTC_VECT(DMAC1_2_DEI4, 0x2080),
163 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
164 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
165 INTC_VECT(DMAC2_1_DEI0, 0x2100),
166 INTC_VECT(DMAC2_1_DEI1, 0x2120),
167 INTC_VECT(DMAC2_1_DEI2, 0x2140),
168 INTC_VECT(DMAC2_1_DEI3, 0x2160),
169 INTC_VECT(DMAC2_2_DEI4, 0x2180),
170 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
171 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
172 INTC_VECT(DMAC3_1_DEI0, 0x2200),
173 INTC_VECT(DMAC3_1_DEI1, 0x2220),
174 INTC_VECT(DMAC3_1_DEI2, 0x2240),
175 INTC_VECT(DMAC3_1_DEI3, 0x2260),
176 INTC_VECT(DMAC3_2_DEI4, 0x2280),
177 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
178 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
179 INTC_VECT(SHWYSTAT_RT, 0x1300),
180 INTC_VECT(SHWYSTAT_HS, 0x1320),
181 INTC_VECT(SHWYSTAT_COM, 0x1340),
182 INTC_VECT(USBH_INT, 0x1540),
183 INTC_VECT(USBH_OHCI, 0x1560),
184 INTC_VECT(USBH_EHCI, 0x1580),
185 INTC_VECT(USBH_PME, 0x15A0),
186 INTC_VECT(USBH_BIND, 0x15C0),
187 INTC_VECT(HDMI, 0x1700),
188 INTC_VECT(RSPI_OVRF, 0x1780),
189 INTC_VECT(RSPI_SPTEF, 0x17A0),
190 INTC_VECT(RSPI_SPRF, 0x17C0),
191 INTC_VECT(SPU2_0, 0x1800),
192 INTC_VECT(SPU2_1, 0x1820),
193 INTC_VECT(FSI, 0x1840),
194 INTC_VECT(FMSI, 0x1860),
195 INTC_VECT(HDMI_SSS, 0x18A0),
196 INTC_VECT(HDMI_KEY, 0x18C0),
197 INTC_VECT(IPMMU, 0x1920),
198 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
199 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
200 INTC_VECT(MFIS2, 0x1A00),
201 INTC_VECT(CPORTR2S, 0x1A20),
202 INTC_VECT(CMT14, 0x1A40),
203 INTC_VECT(CMT15, 0x1A60),
204 INTC_VECT(MMCIF_0, 0x1AA0),
205 INTC_VECT(MMCIF_1, 0x1AC0),
206 INTC_VECT(MMCIF_2, 0x1AE0),
207 INTC_VECT(SIM_ERI, 0x1C00),
208 INTC_VECT(SIM_RXI, 0x1C20),
209 INTC_VECT(SIM_TXI, 0x1C40),
210 INTC_VECT(SIM_TEI, 0x1C60),
211 INTC_VECT(STPRO_0, 0x1C80),
212 INTC_VECT(STPRO_1, 0x1CA0),
213 INTC_VECT(STPRO_2, 0x1CC0),
214 INTC_VECT(STPRO_3, 0x1CE0),
215 INTC_VECT(STPRO_4, 0x1D00),
216};
217
218static struct intc_group intca_groups[] __initdata = {
219 INTC_GROUP(DMAC1_1,
220 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
221 INTC_GROUP(DMAC1_2,
222 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
223 INTC_GROUP(DMAC2_1,
224 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
225 INTC_GROUP(DMAC2_2,
226 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
227 INTC_GROUP(DMAC3_1,
228 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
229 INTC_GROUP(DMAC3_2,
230 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
231 INTC_GROUP(AP_ARM1,
232 AP_ARM_COMMTX, AP_ARM_COMMRX),
233 INTC_GROUP(AP_ARM2,
234 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
235 INTC_GROUP(USBF,
236 USBF_OUL_SOF, USBF_IXL_INT),
237 INTC_GROUP(SDHI0,
238 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
239 INTC_GROUP(SDHI1,
240 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
241 INTC_GROUP(SDHI2,
242 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
243 INTC_GROUP(SHWYSTAT,
244 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
245 INTC_GROUP(USBH1, /* FIXME */
246 USBH_INT, USBH_OHCI),
247 INTC_GROUP(USBH2, /* FIXME */
248 USBH_EHCI,
249 USBH_PME, USBH_BIND),
250 INTC_GROUP(RSPI,
251 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
252 INTC_GROUP(SPU2,
253 SPU2_0, SPU2_1),
254 INTC_GROUP(FLCTL,
255 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
256 INTC_GROUP(IIC1,
257 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
258};
259
260static struct intc_mask_reg intca_mask_registers[] __initdata = {
261 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
262 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
263 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
264 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
265 { ATAPI, 0, DIRC, 0,
266 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
267 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
268 { 0, 0, 0, 0,
269 BBIF1, BBIF2, MFIS, MFI } },
270 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
271 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
272 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
273 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
274 { DDM, 0, 0, 0,
275 0, 0, 0, 0 } },
276 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
277 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
278 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
279 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
280 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
281 0, 0, MSIOF2, 0 } },
282 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
283 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
284 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
285 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
286 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
287 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
288 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
289 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
290 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
291 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
292 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
293 0, 0, 0, 0 } },
294 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
295 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
296 ICBS0, 0, 0, 0 } },
297 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
298 { 0, 0, TPU0, SCIFA6,
299 SCIFA7, GbEther, 0, 0 } },
300 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
301 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
302 0, CMT3, 0, RWDT0 } },
303 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
304 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
305 0, 0, 0, 0 } },
306 /* IMR1A3 / IMCR1A3 */
307 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
308 { 0, 0, USBH_INT, USBH_OHCI,
309 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
310 /* IMR3A3 / IMCR3A3 */
311 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
312 { HDMI, 0, 0, 0,
313 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
314 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
315 { SPU2_0, SPU2_1, FSI, FMSI,
316 0, HDMI_SSS, HDMI_KEY, 0 } },
317 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
318 { 0, IPMMU, 0, 0,
319 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
320 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
321 { MFIS2, CPORTR2S, CMT14, CMT15,
322 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
323 /* IMR8A3 / IMCR8A3 */
324 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
325 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
326 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
327 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
328 { STPRO_4, 0, 0, 0,
329 0, 0, 0, 0 } },
330};
331
332static struct intc_prio_reg intca_prio_registers[] __initdata = {
333 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
334 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
335 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
336 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
337 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
338 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
339 SGX540, CMT1_0 } },
340 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
341 SCIFA2, SCIFA3 } },
342 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
343 FLCTL, SDHI0 } },
344 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
345 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
346 AP_ARM_L2CINT, 0 } },
347 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
348 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
349 SCIFA7, GbEther } },
350 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
351 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
352 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
353 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
354 /* IPRBA3 */
355 /* IPRCA3 */
356 /* IPRDA3 */
357 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
358 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
359 /* IPRGA3 */
360 /* IPRHA3 */
361 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
362 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
363 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
364 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
365 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
366 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
367 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
368 CMT14, CMT15 } },
369 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
370 /* IPRQA3 */
371 /* IPRRA3 */
372 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
373 SIM_TXI, SIM_TEI } },
374 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
375 STPRO_2, STPRO_3 } },
376 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
377};
378
379static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
380 intca_vectors, intca_groups,
381 intca_mask_registers, intca_prio_registers,
382 NULL);
383
384INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
385 INTC_VECT, "r8a7740-intca-irq-pins");
386
387
388/*
389 * INTCS
390 */
391enum {
392 UNUSED_INTCS = 0,
393
394 INTCS,
395
396 /* interrupt sources INTCS */
397
398 /* HUDI */
399 /* STPRO */
400 /* RTDMAC(1) */
401 VPU5HA2,
402 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
403 /* MFI */
404 /* BBIF2 */
405 VPU5F,
406 _2DG_BRK_INT,
407 /* SGX540 */
408 /* 2DDMAC */
409 /* IPMMU */
410 /* RTDMAC 2 */
411 /* KEYSC */
412 /* MSIOF */
413 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
414 TMU0_0, TMU0_1, TMU0_2,
415 CMT0,
416 /* CMT2 */
417 LMB,
418 CTI,
419 VOU,
420 /* RWDT0 */
421 ICB,
422 VIO6C,
423 CEU20, CEU21,
424 JPU,
425 LCDC0,
426 LCRC,
427 /* RTDMAC2(1) */
428 /* RTDMAC2(2) */
429 LCDC1,
430 /* SPU2 */
431 /* FSI */
432 /* FMSI */
433 TMU1_0, TMU1_1, TMU1_2,
434 CMT4,
435 DISP,
436 DSRV,
437 /* MFIS2 */
438 CPORTS2R,
439
440 /* interrupt groups INTCS */
441 _2DG1,
442 IIC0, TMU1,
443};
444
445static struct intc_vect intcs_vectors[] = {
446 /* HUDI */
447 /* STPRO */
448 /* RTDMAC(1) */
449 INTCS_VECT(VPU5HA2, 0x0880),
450 INTCS_VECT(_2DG_TRAP, 0x08A0),
451 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
452 INTCS_VECT(_2DG_CER_INT, 0x08E0),
453 /* MFI */
454 /* BBIF2 */
455 INTCS_VECT(VPU5F, 0x0980),
456 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
457 /* SGX540 */
458 /* 2DDMAC */
459 /* IPMMU */
460 /* RTDMAC(2) */
461 /* KEYSC */
462 /* MSIOF */
463 INTCS_VECT(IIC0_ALI, 0x0E00),
464 INTCS_VECT(IIC0_TACKI, 0x0E20),
465 INTCS_VECT(IIC0_WAITI, 0x0E40),
466 INTCS_VECT(IIC0_DTEI, 0x0E60),
467 INTCS_VECT(TMU0_0, 0x0E80),
468 INTCS_VECT(TMU0_1, 0x0EA0),
469 INTCS_VECT(TMU0_2, 0x0EC0),
470 INTCS_VECT(CMT0, 0x0F00),
471 /* CMT2 */
472 INTCS_VECT(LMB, 0x0F60),
473 INTCS_VECT(CTI, 0x0400),
474 INTCS_VECT(VOU, 0x0420),
475 /* RWDT0 */
476 INTCS_VECT(ICB, 0x0480),
477 INTCS_VECT(VIO6C, 0x04E0),
478 INTCS_VECT(CEU20, 0x0500),
479 INTCS_VECT(CEU21, 0x0520),
480 INTCS_VECT(JPU, 0x0560),
481 INTCS_VECT(LCDC0, 0x0580),
482 INTCS_VECT(LCRC, 0x05A0),
483 /* RTDMAC2(1) */
484 /* RTDMAC2(2) */
485 INTCS_VECT(LCDC1, 0x1780),
486 /* SPU2 */
487 /* FSI */
488 /* FMSI */
489 INTCS_VECT(TMU1_0, 0x1900),
490 INTCS_VECT(TMU1_1, 0x1920),
491 INTCS_VECT(TMU1_2, 0x1940),
492 INTCS_VECT(CMT4, 0x1980),
493 INTCS_VECT(DISP, 0x19A0),
494 INTCS_VECT(DSRV, 0x19C0),
495 /* MFIS2 */
496 INTCS_VECT(CPORTS2R, 0x1A20),
497
498 INTC_VECT(INTCS, 0xf80),
499};
500
501static struct intc_group intcs_groups[] __initdata = {
502 INTC_GROUP(_2DG1, /*FIXME*/
503 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
504 INTC_GROUP(IIC0,
505 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
506 INTC_GROUP(TMU1,
507 TMU1_0, TMU1_1, TMU1_2),
508};
509
510static struct intc_mask_reg intcs_mask_registers[] = {
511 /* IMR0SA / IMCR0SA */ /* all 0 */
512 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
513 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
514 0, 0, 0, 0 /*STPRO*/ } },
515 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
516 { 0/*STPRO*/, 0, CEU21, VPU5F,
517 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
518 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
519 { 0, 0, 0, 0, /*2DDMAC*/
520 VIO6C, 0, 0, ICB } },
521 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
522 { 0, 0, VOU, CTI,
523 JPU, 0, LCRC, LCDC0 } },
524 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
525 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
526 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
527 { 0, TMU0_2, TMU0_1, TMU0_0,
528 0, 0, 0, 0 } },
529 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
530 { 0, 0, 0, 0,
531 CEU20, 0, 0, 0 } },
532 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
533 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
534 0, 0, 0, 0 } },
535 /* IMR10SA / IMCR10SA */ /*IPMMU*/
536 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
537 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
538 0, _2DG_BRK_INT, LMB, 0 } },
539 /* IMR12SA / IMCR12SA */
540 /* IMR13SA / IMCR13SA */
541 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
542 /* IMR1SA3 / IMCR1SA3 */
543 /* IMR2SA3 / IMCR2SA3 */
544 /* IMR3SA3 / IMCR3SA3 */
545 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
546 { 0, 0, 0, 0,
547 LCDC1, 0, 0, 0 } },
548 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
549 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
550 { TMU1_0, TMU1_1, TMU1_2, 0,
551 CMT4, DISP, DSRV, 0 } },
552 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
553 { 0/*MFIS2*/, CPORTS2R, 0, 0,
554 0, 0, 0, 0 } },
555 { /* INTAMASK */ 0xffd20104, 0, 16,
556 { 0, 0, 0, 0, 0, 0, 0, 0,
557 0, 0, 0, 0, 0, 0, 0, INTCS } },
558};
559
560/* Priority is needed for INTCA to receive the INTCS interrupt */
561static struct intc_prio_reg intcs_prio_registers[] = {
562 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
563 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
564 /* IPRCS */ /*BBIF2*/
565 /* IPRDS */
566 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
567 0/*MFI*/, VPU5F } },
568 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
569 0/*CMT2*/, CMT0 } },
570 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
571 TMU0_2, _2DG1 } },
572 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
573 _2DG_BRK_INT/*FIXME*/ } },
574 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
575 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
576 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
577 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
578 /* IPRMS */ /*RWDT0*/
579 /* IPRAS3 */ /*RTDMAC2(1)*/
580 /* IPRBS3 */ /*RTDMAC2(2)*/
581 /* IPRCS3 */
582 /* IPRDS3 */
583 /* IPRES3 */
584 /* IPRFS3 */
585 /* IPRGS3 */
586 /* IPRHS3 */
587 /* IPRIS3 */
588 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
589 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
590 /* IPRLS3 */
591 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
592 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
593 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
594 /* IPRPS3 */
595};
596
597static struct resource intcs_resources[] __initdata = {
598 [0] = {
599 .start = 0xffd20000,
600 .end = 0xffd201ff,
601 .flags = IORESOURCE_MEM,
602 },
603 [1] = {
604 .start = 0xffd50000,
605 .end = 0xffd501ff,
606 .flags = IORESOURCE_MEM,
607 }
608};
609
610static struct intc_desc intcs_desc __initdata = {
611 .name = "r8a7740-intcs",
612 .resource = intcs_resources,
613 .num_resources = ARRAY_SIZE(intcs_resources),
614 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
615 intcs_prio_registers, NULL, NULL),
616};
617
618static void intcs_demux(unsigned int irq, struct irq_desc *desc)
619{
620 void __iomem *reg = (void *)irq_get_handler_data(irq);
621 unsigned int evtcodeas = ioread32(reg);
622
623 generic_handle_irq(intcs_evt2irq(evtcodeas));
624}
625 24
626void __init r8a7740_init_irq(void) 25void __init r8a7740_init_irq(void)
627{ 26{
628 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 27 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
629 28 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
630 register_intc_controller(&intca_desc); 29 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
631 register_intc_controller(&intca_irq_pins_desc); 30 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
632 register_intc_controller(&intcs_desc); 31 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
633 32
634 /* demux using INTEVTSA */ 33 /* initialize the Generic Interrupt Controller PL390 r0p0 */
635 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); 34 gic_init(0, 29, gic_dist_base, gic_cpu_base);
636 irq_set_chained_handler(evt2irq(0xf80), intcs_demux); 35
36 /* route signals to GIC */
37 iowrite32(0x0, pfc_inta_ctrl);
38
39 /*
40 * To mask the shared interrupt to SPI 149 we must ensure to set
41 * PRIO *and* MASK. Else we run into IRQ floods when registering
42 * the intc_irqpin devices
43 */
44 iowrite32(0x0, intc_prio_base + 0x0);
45 iowrite32(0x0, intc_prio_base + 0x4);
46 iowrite32(0x0, intc_prio_base + 0x8);
47 iowrite32(0x0, intc_prio_base + 0xc);
48 iowrite8(0xff, intc_msk_base + 0x0);
49 iowrite8(0xff, intc_msk_base + 0x4);
50 iowrite8(0xff, intc_msk_base + 0x8);
51 iowrite8(0xff, intc_msk_base + 0xc);
52
53 iounmap(intc_prio_base);
54 iounmap(intc_msk_base);
55 iounmap(pfc_inta_ctrl);
637} 56}
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
new file mode 100644
index 000000000000..c5a75a7a508f
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -0,0 +1,202 @@
1/*
2 * r8a73a4 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/kernel.h>
23#include <linux/of_platform.h>
24#include <linux/platform_data/irq-renesas-irqc.h>
25#include <linux/serial_sci.h>
26#include <mach/common.h>
27#include <mach/irqs.h>
28#include <mach/r8a73a4.h>
29#include <asm/mach/arch.h>
30
31static const struct resource pfc_resources[] = {
32 DEFINE_RES_MEM(0xe6050000, 0x9000),
33};
34
35void __init r8a73a4_pinmux_init(void)
36{
37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
38 ARRAY_SIZE(pfc_resources));
39}
40
41#define SCIF_COMMON(scif_type, baseaddr, irq) \
42 .type = scif_type, \
43 .mapbase = baseaddr, \
44 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
45 .scbrr_algo_id = SCBRR_ALGO_4, \
46 .irqs = SCIx_IRQ_MUXED(irq)
47
48#define SCIFA_DATA(index, baseaddr, irq) \
49[index] = { \
50 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
51 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
52}
53
54#define SCIFB_DATA(index, baseaddr, irq) \
55[index] = { \
56 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
57 .scscr = SCSCR_RE | SCSCR_TE, \
58}
59
60enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
61
62static const struct plat_sci_port scif[] = {
63 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
64 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
65 SCIFB_DATA(SCIFB0, 0xe6c50000, gic_spi(145)), /* SCIFB0 */
66 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
67 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
68 SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
69};
70
71static inline void r8a73a4_register_scif(int idx)
72{
73 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
74 sizeof(struct plat_sci_port));
75}
76
77static const struct renesas_irqc_config irqc0_data = {
78 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
79};
80
81static const struct resource irqc0_resources[] = {
82 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
83 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
84 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
85 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
86 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
87 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
88 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
89 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
90 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
91 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
92 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
93 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
94 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
95 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
96 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
97 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
98 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
99 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
100 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
101 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
102 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
103 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
104 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
105 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
106 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
107 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
108 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
109 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
110 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
111 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
112 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
113 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
114 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
115};
116
117static const struct renesas_irqc_config irqc1_data = {
118 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
119};
120
121static const struct resource irqc1_resources[] = {
122 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
123 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
124 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
125 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
126 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
127 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
128 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
129 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
130 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
131 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
132 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
133 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
134 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
135 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
136 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
137 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
138 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
139 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
140 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
141 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
142 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
143 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
144 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
145 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
146 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
147 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
148 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
149};
150
151#define r8a73a4_register_irqc(idx) \
152 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
153 idx, irqc##idx##_resources, \
154 ARRAY_SIZE(irqc##idx##_resources), \
155 &irqc##idx##_data, \
156 sizeof(struct renesas_irqc_config))
157
158/* Thermal0 -> Thermal2 */
159static const struct resource thermal0_resources[] = {
160 DEFINE_RES_MEM(0xe61f0000, 0x14),
161 DEFINE_RES_MEM(0xe61f0100, 0x38),
162 DEFINE_RES_MEM(0xe61f0200, 0x38),
163 DEFINE_RES_MEM(0xe61f0300, 0x38),
164 DEFINE_RES_IRQ(gic_spi(69)),
165};
166
167#define r8a73a4_register_thermal() \
168 platform_device_register_simple("rcar_thermal", -1, \
169 thermal0_resources, \
170 ARRAY_SIZE(thermal0_resources))
171
172void __init r8a73a4_add_standard_devices(void)
173{
174 r8a73a4_register_scif(SCIFA0);
175 r8a73a4_register_scif(SCIFA1);
176 r8a73a4_register_scif(SCIFB0);
177 r8a73a4_register_scif(SCIFB1);
178 r8a73a4_register_scif(SCIFB2);
179 r8a73a4_register_scif(SCIFB3);
180 r8a73a4_register_irqc(0);
181 r8a73a4_register_irqc(1);
182 r8a73a4_register_thermal();
183}
184
185#ifdef CONFIG_USE_OF
186void __init r8a73a4_add_standard_devices_dt(void)
187{
188 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
189}
190
191static const char *r8a73a4_boards_compat_dt[] __initdata = {
192 "renesas,r8a73a4",
193 NULL,
194};
195
196DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
197 .init_irq = irqchip_init,
198 .init_machine = r8a73a4_add_standard_devices_dt,
199 .init_time = shmobile_timer_init,
200 .dt_compat = r8a73a4_boards_compat_dt,
201MACHINE_END
202#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8b85d4d8fab6..228d7aba4a7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
27#include <linux/serial_sci.h> 28#include <linux/serial_sci.h>
@@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void)
94 platform_device_register(&r8a7740_pfc_device); 95 platform_device_register(&r8a7740_pfc_device);
95} 96}
96 97
98static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
100};
101
102static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
104 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
105 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
106 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
107 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
108 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
109 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
110 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
111 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
112 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
113 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
114 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
115 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
116};
117
118static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
120 .id = 0,
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
123 .dev = {
124 .platform_data = &irqpin0_platform_data,
125 },
126};
127
128static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
130};
131
132static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
134 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
135 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
136 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
137 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
138 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
139 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
140 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
141 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
142 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
143 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
144 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
145 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
146};
147
148static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
150 .id = 1,
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
153 .dev = {
154 .platform_data = &irqpin1_platform_data,
155 },
156};
157
158static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
160};
161
162static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
164 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
165 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
166 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
167 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
168 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
169 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
170 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
171 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
172 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
173 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
174 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
175 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
176};
177
178static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
180 .id = 2,
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
183 .dev = {
184 .platform_data = &irqpin2_platform_data,
185 },
186};
187
188static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
190};
191
192static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
194 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
195 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
196 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
197 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
198 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
199 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
200 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
201 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
202 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
203 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
204 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
205 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
206};
207
208static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
210 .id = 3,
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
213 .dev = {
214 .platform_data = &irqpin3_platform_data,
215 },
216};
217
97/* SCIFA0 */ 218/* SCIFA0 */
98static struct plat_sci_port scif0_platform_data = { 219static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000, 220 .mapbase = 0xe6c40000,
@@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = {
101 .scscr = SCSCR_RE | SCSCR_TE, 222 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4, 223 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 224 .type = PORT_SCIFA,
104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), 225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
105}; 226};
106 227
107static struct platform_device scif0_device = { 228static struct platform_device scif0_device = {
@@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = {
119 .scscr = SCSCR_RE | SCSCR_TE, 240 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4, 241 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA, 242 .type = PORT_SCIFA,
122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), 243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
123}; 244};
124 245
125static struct platform_device scif1_device = { 246static struct platform_device scif1_device = {
@@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = {
137 .scscr = SCSCR_RE | SCSCR_TE, 258 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4, 259 .scbrr_algo_id = SCBRR_ALGO_4,
139 .type = PORT_SCIFA, 260 .type = PORT_SCIFA,
140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), 261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
141}; 262};
142 263
143static struct platform_device scif2_device = { 264static struct platform_device scif2_device = {
@@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = {
155 .scscr = SCSCR_RE | SCSCR_TE, 276 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4, 277 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA, 278 .type = PORT_SCIFA,
158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), 279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
159}; 280};
160 281
161static struct platform_device scif3_device = { 282static struct platform_device scif3_device = {
@@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE, 294 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4, 295 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFA, 296 .type = PORT_SCIFA,
176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), 297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
177}; 298};
178 299
179static struct platform_device scif4_device = { 300static struct platform_device scif4_device = {
@@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = {
191 .scscr = SCSCR_RE | SCSCR_TE, 312 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4, 313 .scbrr_algo_id = SCBRR_ALGO_4,
193 .type = PORT_SCIFA, 314 .type = PORT_SCIFA,
194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), 315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
195}; 316};
196 317
197static struct platform_device scif5_device = { 318static struct platform_device scif5_device = {
@@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = {
209 .scscr = SCSCR_RE | SCSCR_TE, 330 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4, 331 .scbrr_algo_id = SCBRR_ALGO_4,
211 .type = PORT_SCIFA, 332 .type = PORT_SCIFA,
212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), 333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
213}; 334};
214 335
215static struct platform_device scif6_device = { 336static struct platform_device scif6_device = {
@@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = {
227 .scscr = SCSCR_RE | SCSCR_TE, 348 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4, 349 .scbrr_algo_id = SCBRR_ALGO_4,
229 .type = PORT_SCIFA, 350 .type = PORT_SCIFA,
230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), 351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
231}; 352};
232 353
233static struct platform_device scif7_device = { 354static struct platform_device scif7_device = {
@@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = {
245 .scscr = SCSCR_RE | SCSCR_TE, 366 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4, 367 .scbrr_algo_id = SCBRR_ALGO_4,
247 .type = PORT_SCIFB, 368 .type = PORT_SCIFB,
248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), 369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
249}; 370};
250 371
251static struct platform_device scifb_device = { 372static struct platform_device scifb_device = {
@@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = {
273 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
274 }, 395 },
275 [1] = { 396 [1] = {
276 .start = evt2irq(0x0b00), 397 .start = gic_spi(58),
277 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
278 }, 399 },
279}; 400};
@@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = {
304 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
305 }, 426 },
306 [1] = { 427 [1] = {
307 .start = intcs_evt2irq(0xe80), 428 .start = gic_spi(198),
308 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
309 }, 430 },
310}; 431};
@@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = {
334 .flags = IORESOURCE_MEM, 455 .flags = IORESOURCE_MEM,
335 }, 456 },
336 [1] = { 457 [1] = {
337 .start = intcs_evt2irq(0xea0), 458 .start = gic_spi(199),
338 .flags = IORESOURCE_IRQ, 459 .flags = IORESOURCE_IRQ,
339 }, 460 },
340}; 461};
@@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = {
364 .flags = IORESOURCE_MEM, 485 .flags = IORESOURCE_MEM,
365 }, 486 },
366 [1] = { 487 [1] = {
367 .start = intcs_evt2irq(0xec0), 488 .start = gic_spi(200),
368 .flags = IORESOURCE_IRQ, 489 .flags = IORESOURCE_IRQ,
369 }, 490 },
370}; 491};
@@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = {
411}; 532};
412 533
413static struct platform_device *r8a7740_early_devices[] __initdata = { 534static struct platform_device *r8a7740_early_devices[] __initdata = {
535 &irqpin0_device,
536 &irqpin1_device,
537 &irqpin2_device,
538 &irqpin3_device,
414 &scif0_device, 539 &scif0_device,
415 &scif1_device, 540 &scif1_device,
416 &scif2_device, 541 &scif2_device,
@@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = {
525 }, 650 },
526 { 651 {
527 .name = "error_irq", 652 .name = "error_irq",
528 .start = evt2irq(0x20c0), 653 .start = gic_spi(34),
529 .end = evt2irq(0x20c0), 654 .end = gic_spi(34),
530 .flags = IORESOURCE_IRQ, 655 .flags = IORESOURCE_IRQ,
531 }, 656 },
532 { 657 {
533 /* IRQ for channels 0-5 */ 658 /* IRQ for channels 0-5 */
534 .start = evt2irq(0x2000), 659 .start = gic_spi(28),
535 .end = evt2irq(0x20a0), 660 .end = gic_spi(33),
536 .flags = IORESOURCE_IRQ, 661 .flags = IORESOURCE_IRQ,
537 }, 662 },
538}; 663};
@@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = {
553 }, 678 },
554 { 679 {
555 .name = "error_irq", 680 .name = "error_irq",
556 .start = evt2irq(0x21c0), 681 .start = gic_spi(41),
557 .end = evt2irq(0x21c0), 682 .end = gic_spi(41),
558 .flags = IORESOURCE_IRQ, 683 .flags = IORESOURCE_IRQ,
559 }, 684 },
560 { 685 {
561 /* IRQ for channels 0-5 */ 686 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2100), 687 .start = gic_spi(35),
563 .end = evt2irq(0x21a0), 688 .end = gic_spi(40),
564 .flags = IORESOURCE_IRQ, 689 .flags = IORESOURCE_IRQ,
565 }, 690 },
566}; 691};
@@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = {
581 }, 706 },
582 { 707 {
583 .name = "error_irq", 708 .name = "error_irq",
584 .start = evt2irq(0x22c0), 709 .start = gic_spi(48),
585 .end = evt2irq(0x22c0), 710 .end = gic_spi(48),
586 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
587 }, 712 },
588 { 713 {
589 /* IRQ for channels 0-5 */ 714 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2200), 715 .start = gic_spi(42),
591 .end = evt2irq(0x22a0), 716 .end = gic_spi(47),
592 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
593 }, 718 },
594}; 719};
@@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = {
677 }, 802 },
678 { 803 {
679 /* IRQ for channels */ 804 /* IRQ for channels */
680 .start = evt2irq(0x0a00), 805 .start = gic_spi(49),
681 .end = evt2irq(0x0a00), 806 .end = gic_spi(49),
682 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
683 }, 808 },
684}; 809};
@@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = {
702 .flags = IORESOURCE_MEM, 827 .flags = IORESOURCE_MEM,
703 }, 828 },
704 [1] = { 829 [1] = {
705 .start = intcs_evt2irq(0xe00), 830 .start = gic_spi(201),
706 .end = intcs_evt2irq(0xe60), 831 .end = gic_spi(204),
707 .flags = IORESOURCE_IRQ, 832 .flags = IORESOURCE_IRQ,
708 }, 833 },
709}; 834};
@@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = {
716 .flags = IORESOURCE_MEM, 841 .flags = IORESOURCE_MEM,
717 }, 842 },
718 [1] = { 843 [1] = {
719 .start = evt2irq(0x780), /* IIC1_ALI1 */ 844 .start = gic_spi(70), /* IIC1_ALI1 */
720 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ 845 .end = gic_spi(73), /* IIC1_DTEI1 */
721 .flags = IORESOURCE_IRQ, 846 .flags = IORESOURCE_IRQ,
722 }, 847 },
723}; 848};
@@ -738,8 +863,8 @@ static struct platform_device i2c1_device = {
738 863
739static struct resource pmu_resources[] = { 864static struct resource pmu_resources[] = {
740 [0] = { 865 [0] = {
741 .start = evt2irq(0x19a0), 866 .start = gic_spi(83),
742 .end = evt2irq(0x19a0), 867 .end = gic_spi(83),
743 .flags = IORESOURCE_IRQ, 868 .flags = IORESOURCE_IRQ,
744 }, 869 },
745}; 870};
@@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
904 .map_io = r8a7740_map_io, 1029 .map_io = r8a7740_map_io,
905 .init_early = r8a7740_add_early_devices_dt, 1030 .init_early = r8a7740_add_early_devices_dt,
906 .init_irq = r8a7740_init_irq, 1031 .init_irq = r8a7740_init_irq,
907 .handle_irq = shmobile_handle_irq_intc,
908 .init_machine = r8a7740_add_standard_devices_dt, 1032 .init_machine = r8a7740_add_standard_devices_dt,
909 .init_time = shmobile_timer_init, 1033 .init_time = shmobile_timer_init,
910 .dt_compat = r8a7740_boards_compat_dt, 1034 .dt_compat = r8a7740_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
new file mode 100644
index 000000000000..30b4a336308f
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -0,0 +1,244 @@
1/*
2 * r8a7778 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 * Copyright (C) 2013 Cogent Embedded, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/irqchip/arm-gic.h>
25#include <linux/of.h>
26#include <linux/of_platform.h>
27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
28#include <linux/platform_device.h>
29#include <linux/irqchip.h>
30#include <linux/serial_sci.h>
31#include <linux/sh_timer.h>
32#include <mach/irqs.h>
33#include <mach/r8a7778.h>
34#include <mach/common.h>
35#include <asm/mach/arch.h>
36#include <asm/hardware/cache-l2x0.h>
37
38/* SCIF */
39#define SCIF_INFO(baseaddr, irq) \
40{ \
41 .mapbase = baseaddr, \
42 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
43 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
44 .scbrr_algo_id = SCBRR_ALGO_2, \
45 .type = PORT_SCIF, \
46 .irqs = SCIx_IRQ_MUXED(irq), \
47}
48
49static struct plat_sci_port scif_platform_data[] = {
50 SCIF_INFO(0xffe40000, gic_iid(0x66)),
51 SCIF_INFO(0xffe41000, gic_iid(0x67)),
52 SCIF_INFO(0xffe42000, gic_iid(0x68)),
53 SCIF_INFO(0xffe43000, gic_iid(0x69)),
54 SCIF_INFO(0xffe44000, gic_iid(0x6a)),
55 SCIF_INFO(0xffe45000, gic_iid(0x6b)),
56};
57
58/* TMU */
59static struct resource sh_tmu0_resources[] = {
60 DEFINE_RES_MEM(0xffd80008, 12),
61 DEFINE_RES_IRQ(gic_iid(0x40)),
62};
63
64static struct sh_timer_config sh_tmu0_platform_data = {
65 .name = "TMU00",
66 .channel_offset = 0x4,
67 .timer_bit = 0,
68 .clockevent_rating = 200,
69};
70
71static struct resource sh_tmu1_resources[] = {
72 DEFINE_RES_MEM(0xffd80014, 12),
73 DEFINE_RES_IRQ(gic_iid(0x41)),
74};
75
76static struct sh_timer_config sh_tmu1_platform_data = {
77 .name = "TMU01",
78 .channel_offset = 0x10,
79 .timer_bit = 1,
80 .clocksource_rating = 200,
81};
82
83/* Ether */
84static struct resource ether_resources[] = {
85 DEFINE_RES_MEM(0xfde00000, 0x400),
86 DEFINE_RES_IRQ(gic_iid(0x89)),
87};
88
89#define r8a7778_register_tmu(idx) \
90 platform_device_register_resndata( \
91 &platform_bus, "sh_tmu", idx, \
92 sh_tmu##idx##_resources, \
93 ARRAY_SIZE(sh_tmu##idx##_resources), \
94 &sh_tmu##idx##_platform_data, \
95 sizeof(sh_tmu##idx##_platform_data))
96
97void __init r8a7778_add_standard_devices(void)
98{
99 int i;
100
101#ifdef CONFIG_CACHE_L2X0
102 void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
103 if (base) {
104 /*
105 * Early BRESP enable, Shared attribute override enable, 64K*16way
106 * don't call iounmap(base)
107 */
108 l2x0_init(base, 0x40470000, 0x82000fff);
109 }
110#endif
111
112 for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++)
113 platform_device_register_data(&platform_bus, "sh-sci", i,
114 &scif_platform_data[i],
115 sizeof(struct plat_sci_port));
116
117 r8a7778_register_tmu(0);
118 r8a7778_register_tmu(1);
119}
120
121void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
122{
123 platform_device_register_resndata(&platform_bus, "sh_eth", -1,
124 ether_resources,
125 ARRAY_SIZE(ether_resources),
126 pdata, sizeof(*pdata));
127}
128
129static struct renesas_intc_irqpin_config irqpin_platform_data = {
130 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
131 .sense_bitfield_width = 2,
132};
133
134static struct resource irqpin_resources[] = {
135 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
136 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
137 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
138 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
139 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
140 DEFINE_RES_IRQ(gic_iid(0x3b)), /* IRQ0 */
141 DEFINE_RES_IRQ(gic_iid(0x3c)), /* IRQ1 */
142 DEFINE_RES_IRQ(gic_iid(0x3d)), /* IRQ2 */
143 DEFINE_RES_IRQ(gic_iid(0x3e)), /* IRQ3 */
144};
145
146void __init r8a7778_init_irq_extpin(int irlm)
147{
148 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
149 unsigned long tmp;
150
151 if (!icr0) {
152 pr_warn("r8a7778: unable to setup external irq pin mode\n");
153 return;
154 }
155
156 tmp = ioread32(icr0);
157 if (irlm)
158 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
159 else
160 tmp &= ~(1 << 23); /* IRL mode - not supported */
161 tmp |= (1 << 21); /* LVLMODE = 1 */
162 iowrite32(tmp, icr0);
163 iounmap(icr0);
164
165 if (irlm)
166 platform_device_register_resndata(
167 &platform_bus, "renesas_intc_irqpin", -1,
168 irqpin_resources, ARRAY_SIZE(irqpin_resources),
169 &irqpin_platform_data, sizeof(irqpin_platform_data));
170}
171
172#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
173#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
174
175#define INT2NTSR0 0x00018 /* 0xfe700018 */
176#define INT2NTSR1 0x0002c /* 0xfe70002c */
177static void __init r8a7778_init_irq_common(void)
178{
179 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
180
181 BUG_ON(!base);
182
183 /* route all interrupts to ARM */
184 __raw_writel(0x73ffffff, base + INT2NTSR0);
185 __raw_writel(0xffffffff, base + INT2NTSR1);
186
187 /* unmask all known interrupts in INTCS2 */
188 __raw_writel(0x08330773, base + INT2SMSKCR0);
189 __raw_writel(0x00311110, base + INT2SMSKCR1);
190
191 iounmap(base);
192}
193
194void __init r8a7778_init_irq(void)
195{
196 void __iomem *gic_dist_base;
197 void __iomem *gic_cpu_base;
198
199 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
200 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
201 BUG_ON(!gic_dist_base || !gic_cpu_base);
202
203 /* use GIC to handle interrupts */
204 gic_init(0, 29, gic_dist_base, gic_cpu_base);
205
206 r8a7778_init_irq_common();
207}
208
209void __init r8a7778_init_delay(void)
210{
211 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
212}
213
214#ifdef CONFIG_USE_OF
215void __init r8a7778_init_irq_dt(void)
216{
217 irqchip_init();
218 r8a7778_init_irq_common();
219}
220
221static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
222 {},
223};
224
225void __init r8a7778_add_standard_devices_dt(void)
226{
227 of_platform_populate(NULL, of_default_bus_match_table,
228 r8a7778_auxdata_lookup, NULL);
229}
230
231static const char *r8a7778_compat_dt[] __initdata = {
232 "renesas,r8a7778",
233 NULL,
234};
235
236DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
237 .init_early = r8a7778_init_delay,
238 .init_irq = r8a7778_init_irq_dt,
239 .init_machine = r8a7778_add_standard_devices_dt,
240 .init_time = shmobile_timer_init,
241 .dt_compat = r8a7778_compat_dt,
242MACHINE_END
243
244#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35e71a0..a460ba3dedcb 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/delay.h> 27#include <linux/delay.h>
27#include <linux/input.h> 28#include <linux/input.h>
@@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
68 .end = 0xfffc023b, 69 .end = 0xfffc023b,
69 .flags = IORESOURCE_MEM, 70 .flags = IORESOURCE_MEM,
70 }, 71 },
71 [1] = {
72 .start = 0xffc40000,
73 .end = 0xffc46fff,
74 .flags = IORESOURCE_MEM,
75 }
76}; 72};
77 73
78static struct platform_device r8a7779_pfc_device = { 74static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
82 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 78 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
83}; 79};
84 80
81#define R8A7779_GPIO(idx, npins) \
82static struct resource r8a7779_gpio##idx##_resources[] = { \
83 [0] = { \
84 .start = 0xffc40000 + 0x1000 * (idx), \
85 .end = 0xffc4002b + 0x1000 * (idx), \
86 .flags = IORESOURCE_MEM, \
87 }, \
88 [1] = { \
89 .start = gic_iid(0xad + (idx)), \
90 .flags = IORESOURCE_IRQ, \
91 } \
92}; \
93 \
94static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
95 .gpio_base = 32 * (idx), \
96 .irq_base = 0, \
97 .number_of_pins = npins, \
98 .pctl_name = "pfc-r8a7779", \
99}; \
100 \
101static struct platform_device r8a7779_gpio##idx##_device = { \
102 .name = "gpio_rcar", \
103 .id = idx, \
104 .resource = r8a7779_gpio##idx##_resources, \
105 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
106 .dev = { \
107 .platform_data = &r8a7779_gpio##idx##_platform_data, \
108 }, \
109}
110
111R8A7779_GPIO(0, 32);
112R8A7779_GPIO(1, 32);
113R8A7779_GPIO(2, 32);
114R8A7779_GPIO(3, 32);
115R8A7779_GPIO(4, 32);
116R8A7779_GPIO(5, 32);
117R8A7779_GPIO(6, 9);
118
119static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
120 &r8a7779_pfc_device,
121 &r8a7779_gpio0_device,
122 &r8a7779_gpio1_device,
123 &r8a7779_gpio2_device,
124 &r8a7779_gpio3_device,
125 &r8a7779_gpio4_device,
126 &r8a7779_gpio5_device,
127 &r8a7779_gpio6_device,
128};
129
85void __init r8a7779_pinmux_init(void) 130void __init r8a7779_pinmux_init(void)
86{ 131{
87 platform_device_register(&r8a7779_pfc_device); 132 platform_add_devices(r8a7779_pinctrl_devices,
133 ARRAY_SIZE(r8a7779_pinctrl_devices));
88} 134}
89 135
90static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
new file mode 100644
index 000000000000..49de2d56f86d
--- /dev/null
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -0,0 +1,150 @@
1/*
2 * r8a7790 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/irq.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h>
24#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/platform_data/irq-renesas-irqc.h>
27#include <mach/common.h>
28#include <mach/irqs.h>
29#include <mach/r8a7790.h>
30#include <asm/mach/arch.h>
31
32static const struct resource pfc_resources[] = {
33 DEFINE_RES_MEM(0xe6060000, 0x250),
34 DEFINE_RES_MEM(0xe6050000, 0x5050),
35};
36
37void __init r8a7790_pinmux_init(void)
38{
39 platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
40 ARRAY_SIZE(pfc_resources));
41}
42
43#define SCIF_COMMON(scif_type, baseaddr, irq) \
44 .type = scif_type, \
45 .mapbase = baseaddr, \
46 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
47 .irqs = SCIx_IRQ_MUXED(irq)
48
49#define SCIFA_DATA(index, baseaddr, irq) \
50[index] = { \
51 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
52 .scbrr_algo_id = SCBRR_ALGO_4, \
53 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
54}
55
56#define SCIFB_DATA(index, baseaddr, irq) \
57[index] = { \
58 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
59 .scbrr_algo_id = SCBRR_ALGO_4, \
60 .scscr = SCSCR_RE | SCSCR_TE, \
61}
62
63#define SCIF_DATA(index, baseaddr, irq) \
64[index] = { \
65 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
66 .scbrr_algo_id = SCBRR_ALGO_2, \
67 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \
68}
69
70enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
71
72static const struct plat_sci_port scif[] = {
73 SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
74 SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
75 SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
76 SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
77 SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
78 SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
79 SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
80 SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
81};
82
83static inline void r8a7790_register_scif(int idx)
84{
85 platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
86 sizeof(struct plat_sci_port));
87}
88
89static struct renesas_irqc_config irqc0_data = {
90 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
91};
92
93static struct resource irqc0_resources[] = {
94 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
95 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
96 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
97 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
98 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
99};
100
101#define r8a7790_register_irqc(idx) \
102 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
103 idx, irqc##idx##_resources, \
104 ARRAY_SIZE(irqc##idx##_resources), \
105 &irqc##idx##_data, \
106 sizeof(struct renesas_irqc_config))
107
108void __init r8a7790_add_standard_devices(void)
109{
110 r8a7790_register_scif(SCIFA0);
111 r8a7790_register_scif(SCIFA1);
112 r8a7790_register_scif(SCIFB0);
113 r8a7790_register_scif(SCIFB1);
114 r8a7790_register_scif(SCIFB2);
115 r8a7790_register_scif(SCIFA2);
116 r8a7790_register_scif(SCIF0);
117 r8a7790_register_scif(SCIF1);
118 r8a7790_register_irqc(0);
119}
120
121void __init r8a7790_timer_init(void)
122{
123 void __iomem *cntcr;
124
125 /* make sure arch timer is started by setting bit 0 of CNTCT */
126 cntcr = ioremap(0xe6080000, PAGE_SIZE);
127 iowrite32(1, cntcr);
128 iounmap(cntcr);
129
130 shmobile_timer_init();
131}
132
133#ifdef CONFIG_USE_OF
134void __init r8a7790_add_standard_devices_dt(void)
135{
136 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
137}
138
139static const char *r8a7790_boards_compat_dt[] __initdata = {
140 "renesas,r8a7790",
141 NULL,
142};
143
144DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
145 .init_irq = irqchip_init,
146 .init_machine = r8a7790_add_standard_devices_dt,
147 .init_time = r8a7790_timer_init,
148 .dt_compat = r8a7790_boards_compat_dt,
149MACHINE_END
150#endif /* CONFIG_USE_OF */
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index 1825b0bd523d..4c17fb6970b1 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -9,7 +9,9 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11 11
12#include <linux/bug.h>
12#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h>
13#include <linux/kernel.h> 15#include <linux/kernel.h>
14#include <cpu/pfc.h> 16#include <cpu/pfc.h>
15 17
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 10:58:54 -0500