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authorRajeshwari Shinde <rajeshwari.s@samsung.com>2011-10-24 11:05:58 -0400
committerKukjin Kim <kgene.kim@samsung.com>2011-12-22 20:09:16 -0500
commita361d10a2b490812b051433b1aad5b4351372597 (patch)
tree7132392c01d78d275d12313056803e15e97c5f6b /arch
parenta60879e7ca17ea41bacd57e3cb2b56e48135f7a3 (diff)
ARM: SAMSUNG: Add lookup of sdhci-s3c clocks using generic names
Add support for lookup of sdhci-s3c controller clocks using generic names for s3c2416, s3c64xx, s5pc100, s5pv210 and exynos4 SoC's. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> [kgene.kim@samsung.com: fixed trailing whitespace] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-exynos/clock.c88
-rw-r--r--arch/arm/mach-s3c2416/clock.c68
-rw-r--r--arch/arm/mach-s3c64xx/clock.c126
-rw-r--r--arch/arm/mach-s5pc100/clock.c130
-rw-r--r--arch/arm/mach-s5pv210/clock.c167
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c16
6 files changed, 359 insertions, 236 deletions
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 7dee8694486a..5d8d4831e244 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1156,42 +1156,6 @@ static struct clksrc_clk clksrcs[] = {
1156 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 }, 1156 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1157 }, { 1157 }, {
1158 .clk = { 1158 .clk = {
1159 .name = "sclk_mmc",
1160 .devname = "s3c-sdhci.0",
1161 .parent = &clk_dout_mmc0.clk,
1162 .enable = exynos4_clksrc_mask_fsys_ctrl,
1163 .ctrlbit = (1 << 0),
1164 },
1165 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1166 }, {
1167 .clk = {
1168 .name = "sclk_mmc",
1169 .devname = "s3c-sdhci.1",
1170 .parent = &clk_dout_mmc1.clk,
1171 .enable = exynos4_clksrc_mask_fsys_ctrl,
1172 .ctrlbit = (1 << 4),
1173 },
1174 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1175 }, {
1176 .clk = {
1177 .name = "sclk_mmc",
1178 .devname = "s3c-sdhci.2",
1179 .parent = &clk_dout_mmc2.clk,
1180 .enable = exynos4_clksrc_mask_fsys_ctrl,
1181 .ctrlbit = (1 << 8),
1182 },
1183 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1184 }, {
1185 .clk = {
1186 .name = "sclk_mmc",
1187 .devname = "s3c-sdhci.3",
1188 .parent = &clk_dout_mmc3.clk,
1189 .enable = exynos4_clksrc_mask_fsys_ctrl,
1190 .ctrlbit = (1 << 12),
1191 },
1192 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1193 }, {
1194 .clk = {
1195 .name = "sclk_dwmmc", 1159 .name = "sclk_dwmmc",
1196 .parent = &clk_dout_mmc4.clk, 1160 .parent = &clk_dout_mmc4.clk,
1197 .enable = exynos4_clksrc_mask_fsys_ctrl, 1161 .enable = exynos4_clksrc_mask_fsys_ctrl,
@@ -1249,6 +1213,50 @@ static struct clksrc_clk clk_sclk_uart3 = {
1249 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 }, 1213 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1250}; 1214};
1251 1215
1216static struct clksrc_clk clk_sclk_mmc0 = {
1217 .clk = {
1218 .name = "sclk_mmc",
1219 .devname = "s3c-sdhci.0",
1220 .parent = &clk_dout_mmc0.clk,
1221 .enable = exynos4_clksrc_mask_fsys_ctrl,
1222 .ctrlbit = (1 << 0),
1223 },
1224 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1225};
1226
1227static struct clksrc_clk clk_sclk_mmc1 = {
1228 .clk = {
1229 .name = "sclk_mmc",
1230 .devname = "s3c-sdhci.1",
1231 .parent = &clk_dout_mmc1.clk,
1232 .enable = exynos4_clksrc_mask_fsys_ctrl,
1233 .ctrlbit = (1 << 4),
1234 },
1235 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1236};
1237
1238static struct clksrc_clk clk_sclk_mmc2 = {
1239 .clk = {
1240 .name = "sclk_mmc",
1241 .devname = "s3c-sdhci.2",
1242 .parent = &clk_dout_mmc2.clk,
1243 .enable = exynos4_clksrc_mask_fsys_ctrl,
1244 .ctrlbit = (1 << 8),
1245 },
1246 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1247};
1248
1249static struct clksrc_clk clk_sclk_mmc3 = {
1250 .clk = {
1251 .name = "sclk_mmc",
1252 .devname = "s3c-sdhci.3",
1253 .parent = &clk_dout_mmc3.clk,
1254 .enable = exynos4_clksrc_mask_fsys_ctrl,
1255 .ctrlbit = (1 << 12),
1256 },
1257 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1258};
1259
1252/* Clock initialization code */ 1260/* Clock initialization code */
1253static struct clksrc_clk *sysclks[] = { 1261static struct clksrc_clk *sysclks[] = {
1254 &clk_mout_apll, 1262 &clk_mout_apll,
@@ -1293,6 +1301,10 @@ static struct clksrc_clk *clksrc_cdev[] = {
1293 &clk_sclk_uart1, 1301 &clk_sclk_uart1,
1294 &clk_sclk_uart2, 1302 &clk_sclk_uart2,
1295 &clk_sclk_uart3, 1303 &clk_sclk_uart3,
1304 &clk_sclk_mmc0,
1305 &clk_sclk_mmc1,
1306 &clk_sclk_mmc2,
1307 &clk_sclk_mmc3,
1296}; 1308};
1297 1309
1298static struct clk_lookup exynos4_clk_lookup[] = { 1310static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1300,6 +1312,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
1300 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk), 1312 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1301 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk), 1313 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1302 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk), 1314 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1315 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1316 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1317 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1318 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1303 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0), 1319 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1304 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1), 1320 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1305}; 1321};
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index afbbe8bc21d1..59f54d1d7f8b 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -90,39 +90,38 @@ static struct clksrc_clk hsmmc_div[] = {
90 }, 90 },
91}; 91};
92 92
93static struct clksrc_clk hsmmc_mux[] = { 93static struct clksrc_clk hsmmc_mux0 = {
94 [0] = { 94 .clk = {
95 .clk = { 95 .name = "hsmmc-if",
96 .name = "hsmmc-if", 96 .devname = "s3c-sdhci.0",
97 .devname = "s3c-sdhci.0", 97 .ctrlbit = (1 << 6),
98 .ctrlbit = (1 << 6), 98 .enable = s3c2443_clkcon_enable_s,
99 .enable = s3c2443_clkcon_enable_s,
100 },
101 .sources = &(struct clksrc_sources) {
102 .nr_sources = 2,
103 .sources = (struct clk *[]) {
104 [0] = &hsmmc_div[0].clk,
105 [1] = NULL, /* to fix */
106 },
107 },
108 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
109 }, 99 },
110 [1] = { 100 .sources = &(struct clksrc_sources) {
111 .clk = { 101 .nr_sources = 2,
112 .name = "hsmmc-if", 102 .sources = (struct clk * []) {
113 .devname = "s3c-sdhci.1", 103 [0] = &hsmmc_div[0].clk,
114 .ctrlbit = (1 << 12), 104 [1] = NULL, /* to fix */
115 .enable = s3c2443_clkcon_enable_s,
116 }, 105 },
117 .sources = &(struct clksrc_sources) { 106 },
118 .nr_sources = 2, 107 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
119 .sources = (struct clk *[]) { 108};
120 [0] = &hsmmc_div[1].clk, 109
121 [1] = NULL, /* to fix */ 110static struct clksrc_clk hsmmc_mux1 = {
122 }, 111 .clk = {
112 .name = "hsmmc-if",
113 .devname = "s3c-sdhci.1",
114 .ctrlbit = (1 << 12),
115 .enable = s3c2443_clkcon_enable_s,
116 },
117 .sources = &(struct clksrc_sources) {
118 .nr_sources = 2,
119 .sources = (struct clk * []) {
120 [0] = &hsmmc_div[1].clk,
121 [1] = NULL, /* to fix */
123 }, 122 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
125 }, 123 },
124 .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
126}; 125};
127 126
128static struct clk hsmmc0_clk = { 127static struct clk hsmmc0_clk = {
@@ -144,8 +143,14 @@ static struct clksrc_clk *clksrcs[] __initdata = {
144 &hsspi_mux, 143 &hsspi_mux,
145 &hsmmc_div[0], 144 &hsmmc_div[0],
146 &hsmmc_div[1], 145 &hsmmc_div[1],
147 &hsmmc_mux[0], 146 &hsmmc_mux0,
148 &hsmmc_mux[1], 147 &hsmmc_mux1,
148};
149
150static struct clk_lookup s3c2416_clk_lookup[] = {
151 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
152 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
153 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
149}; 154};
150 155
151void __init s3c2416_init_clocks(int xtal) 156void __init s3c2416_init_clocks(int xtal)
@@ -167,6 +172,7 @@ void __init s3c2416_init_clocks(int xtal)
167 s3c_register_clksrc(clksrcs[ptr], 1); 172 s3c_register_clksrc(clksrcs[ptr], 1);
168 173
169 s3c24xx_register_clock(&hsmmc0_clk); 174 s3c24xx_register_clock(&hsmmc0_clk);
175 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170 176
171 s3c_pwmclk_init(); 177 s3c_pwmclk_init();
172 178
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2addd988141c..415c5406b17c 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -243,24 +243,6 @@ static struct clk init_clocks[] = {
243 .enable = s3c64xx_hclk_ctrl, 243 .enable = s3c64xx_hclk_ctrl,
244 .ctrlbit = S3C_CLKCON_HCLK_UHOST, 244 .ctrlbit = S3C_CLKCON_HCLK_UHOST,
245 }, { 245 }, {
246 .name = "hsmmc",
247 .devname = "s3c-sdhci.0",
248 .parent = &clk_h,
249 .enable = s3c64xx_hclk_ctrl,
250 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
251 }, {
252 .name = "hsmmc",
253 .devname = "s3c-sdhci.1",
254 .parent = &clk_h,
255 .enable = s3c64xx_hclk_ctrl,
256 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
257 }, {
258 .name = "hsmmc",
259 .devname = "s3c-sdhci.2",
260 .parent = &clk_h,
261 .enable = s3c64xx_hclk_ctrl,
262 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
263 }, {
264 .name = "otg", 246 .name = "otg",
265 .parent = &clk_h, 247 .parent = &clk_h,
266 .enable = s3c64xx_hclk_ctrl, 248 .enable = s3c64xx_hclk_ctrl,
@@ -310,6 +292,29 @@ static struct clk init_clocks[] = {
310 } 292 }
311}; 293};
312 294
295static struct clk clk_hsmmc0 = {
296 .name = "hsmmc",
297 .devname = "s3c-sdhci.0",
298 .parent = &clk_h,
299 .enable = s3c64xx_hclk_ctrl,
300 .ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
301};
302
303static struct clk clk_hsmmc1 = {
304 .name = "hsmmc",
305 .devname = "s3c-sdhci.1",
306 .parent = &clk_h,
307 .enable = s3c64xx_hclk_ctrl,
308 .ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
309};
310
311static struct clk clk_hsmmc2 = {
312 .name = "hsmmc",
313 .devname = "s3c-sdhci.2",
314 .parent = &clk_h,
315 .enable = s3c64xx_hclk_ctrl,
316 .ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
317};
313 318
314static struct clk clk_fout_apll = { 319static struct clk clk_fout_apll = {
315 .name = "fout_apll", 320 .name = "fout_apll",
@@ -578,36 +583,6 @@ static struct clksrc_sources clkset_camif = {
578static struct clksrc_clk clksrcs[] = { 583static struct clksrc_clk clksrcs[] = {
579 { 584 {
580 .clk = { 585 .clk = {
581 .name = "mmc_bus",
582 .devname = "s3c-sdhci.0",
583 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
584 .enable = s3c64xx_sclk_ctrl,
585 },
586 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
587 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
588 .sources = &clkset_spi_mmc,
589 }, {
590 .clk = {
591 .name = "mmc_bus",
592 .devname = "s3c-sdhci.1",
593 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
594 .enable = s3c64xx_sclk_ctrl,
595 },
596 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
597 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
598 .sources = &clkset_spi_mmc,
599 }, {
600 .clk = {
601 .name = "mmc_bus",
602 .devname = "s3c-sdhci.2",
603 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
604 .enable = s3c64xx_sclk_ctrl,
605 },
606 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
607 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
608 .sources = &clkset_spi_mmc,
609 }, {
610 .clk = {
611 .name = "usb-bus-host", 586 .name = "usb-bus-host",
612 .ctrlbit = S3C_CLKCON_SCLK_UHOST, 587 .ctrlbit = S3C_CLKCON_SCLK_UHOST,
613 .enable = s3c64xx_sclk_ctrl, 588 .enable = s3c64xx_sclk_ctrl,
@@ -697,6 +672,42 @@ static struct clksrc_clk clk_sclk_uclk = {
697 .sources = &clkset_uart, 672 .sources = &clkset_uart,
698}; 673};
699 674
675static struct clksrc_clk clk_sclk_mmc0 = {
676 .clk = {
677 .name = "mmc_bus",
678 .devname = "s3c-sdhci.0",
679 .ctrlbit = S3C_CLKCON_SCLK_MMC0,
680 .enable = s3c64xx_sclk_ctrl,
681 },
682 .reg_src = { .reg = S3C_CLK_SRC, .shift = 18, .size = 2 },
683 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
684 .sources = &clkset_spi_mmc,
685};
686
687static struct clksrc_clk clk_sclk_mmc1 = {
688 .clk = {
689 .name = "mmc_bus",
690 .devname = "s3c-sdhci.1",
691 .ctrlbit = S3C_CLKCON_SCLK_MMC1,
692 .enable = s3c64xx_sclk_ctrl,
693 },
694 .reg_src = { .reg = S3C_CLK_SRC, .shift = 20, .size = 2 },
695 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
696 .sources = &clkset_spi_mmc,
697};
698
699static struct clksrc_clk clk_sclk_mmc2 = {
700 .clk = {
701 .name = "mmc_bus",
702 .devname = "s3c-sdhci.2",
703 .ctrlbit = S3C_CLKCON_SCLK_MMC2,
704 .enable = s3c64xx_sclk_ctrl,
705 },
706 .reg_src = { .reg = S3C_CLK_SRC, .shift = 22, .size = 2 },
707 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
708 .sources = &clkset_spi_mmc,
709};
710
700/* Clock initialisation code */ 711/* Clock initialisation code */
701 712
702static struct clksrc_clk *init_parents[] = { 713static struct clksrc_clk *init_parents[] = {
@@ -707,11 +718,26 @@ static struct clksrc_clk *init_parents[] = {
707 718
708static struct clksrc_clk *clksrc_cdev[] = { 719static struct clksrc_clk *clksrc_cdev[] = {
709 &clk_sclk_uclk, 720 &clk_sclk_uclk,
721 &clk_sclk_mmc0,
722 &clk_sclk_mmc1,
723 &clk_sclk_mmc2,
724};
725
726static struct clk *clk_cdev[] = {
727 &clk_hsmmc0,
728 &clk_hsmmc1,
729 &clk_hsmmc2,
710}; 730};
711 731
712static struct clk_lookup s3c64xx_clk_lookup[] = { 732static struct clk_lookup s3c64xx_clk_lookup[] = {
713 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 733 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
714 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), 734 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
735 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
736 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
737 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
738 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
739 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
740 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
715}; 741};
716 742
717#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) 743#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
@@ -834,6 +860,10 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
834 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 860 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
835 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 861 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
836 862
863 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
864 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
865 s3c_disable_clocks(clk_cdev[cnt], 1);
866
837 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1)); 867 s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
838 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 868 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
839 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) 869 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 9d644ece2604..69829ba9c01b 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -426,24 +426,6 @@ static struct clk init_clocks_off[] = {
426 .enable = s5pc100_d0_2_ctrl, 426 .enable = s5pc100_d0_2_ctrl,
427 .ctrlbit = (1 << 1), 427 .ctrlbit = (1 << 1),
428 }, { 428 }, {
429 .name = "hsmmc",
430 .devname = "s3c-sdhci.2",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 7),
434 }, {
435 .name = "hsmmc",
436 .devname = "s3c-sdhci.1",
437 .parent = &clk_div_d1_bus.clk,
438 .enable = s5pc100_d1_0_ctrl,
439 .ctrlbit = (1 << 6),
440 }, {
441 .name = "hsmmc",
442 .devname = "s3c-sdhci.0",
443 .parent = &clk_div_d1_bus.clk,
444 .enable = s5pc100_d1_0_ctrl,
445 .ctrlbit = (1 << 5),
446 }, {
447 .name = "modemif", 429 .name = "modemif",
448 .parent = &clk_div_d1_bus.clk, 430 .parent = &clk_div_d1_bus.clk,
449 .enable = s5pc100_d1_0_ctrl, 431 .enable = s5pc100_d1_0_ctrl,
@@ -711,6 +693,30 @@ static struct clk init_clocks_off[] = {
711 }, 693 },
712}; 694};
713 695
696static struct clk clk_hsmmc2 = {
697 .name = "hsmmc",
698 .devname = "s3c-sdhci.2",
699 .parent = &clk_div_d1_bus.clk,
700 .enable = s5pc100_d1_0_ctrl,
701 .ctrlbit = (1 << 7),
702};
703
704static struct clk clk_hsmmc1 = {
705 .name = "hsmmc",
706 .devname = "s3c-sdhci.1",
707 .parent = &clk_div_d1_bus.clk,
708 .enable = s5pc100_d1_0_ctrl,
709 .ctrlbit = (1 << 6),
710};
711
712static struct clk clk_hsmmc0 = {
713 .name = "hsmmc",
714 .devname = "s3c-sdhci.0",
715 .parent = &clk_div_d1_bus.clk,
716 .enable = s5pc100_d1_0_ctrl,
717 .ctrlbit = (1 << 5),
718};
719
714static struct clk clk_vclk54m = { 720static struct clk clk_vclk54m = {
715 .name = "vclk_54m", 721 .name = "vclk_54m",
716 .rate = 54000000, 722 .rate = 54000000,
@@ -1014,39 +1020,6 @@ static struct clksrc_clk clksrcs[] = {
1014 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, 1020 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1015 }, { 1021 }, {
1016 .clk = { 1022 .clk = {
1017 .name = "sclk_mmc",
1018 .devname = "s3c-sdhci.0",
1019 .ctrlbit = (1 << 12),
1020 .enable = s5pc100_sclk1_ctrl,
1021
1022 },
1023 .sources = &clk_src_mmc0,
1024 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1025 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1026 }, {
1027 .clk = {
1028 .name = "sclk_mmc",
1029 .devname = "s3c-sdhci.1",
1030 .ctrlbit = (1 << 13),
1031 .enable = s5pc100_sclk1_ctrl,
1032
1033 },
1034 .sources = &clk_src_mmc12,
1035 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1036 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1037 }, {
1038 .clk = {
1039 .name = "sclk_mmc",
1040 .devname = "s3c-sdhci.2",
1041 .ctrlbit = (1 << 14),
1042 .enable = s5pc100_sclk1_ctrl,
1043
1044 },
1045 .sources = &clk_src_mmc12,
1046 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1047 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1048 }, {
1049 .clk = {
1050 .name = "sclk_irda", 1023 .name = "sclk_irda",
1051 .ctrlbit = (1 << 10), 1024 .ctrlbit = (1 << 10),
1052 .enable = s5pc100_sclk0_ctrl, 1025 .enable = s5pc100_sclk0_ctrl,
@@ -1099,6 +1072,42 @@ static struct clksrc_clk clk_sclk_uart = {
1099 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 1072 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1100}; 1073};
1101 1074
1075static struct clksrc_clk clk_sclk_mmc0 = {
1076 .clk = {
1077 .name = "sclk_mmc",
1078 .devname = "s3c-sdhci.0",
1079 .ctrlbit = (1 << 12),
1080 .enable = s5pc100_sclk1_ctrl,
1081 },
1082 .sources = &clk_src_mmc0,
1083 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1084 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1085};
1086
1087static struct clksrc_clk clk_sclk_mmc1 = {
1088 .clk = {
1089 .name = "sclk_mmc",
1090 .devname = "s3c-sdhci.1",
1091 .ctrlbit = (1 << 13),
1092 .enable = s5pc100_sclk1_ctrl,
1093 },
1094 .sources = &clk_src_mmc12,
1095 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1096 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1097};
1098
1099static struct clksrc_clk clk_sclk_mmc2 = {
1100 .clk = {
1101 .name = "sclk_mmc",
1102 .devname = "s3c-sdhci.2",
1103 .ctrlbit = (1 << 14),
1104 .enable = s5pc100_sclk1_ctrl,
1105 },
1106 .sources = &clk_src_mmc12,
1107 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1108 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1109};
1110
1102/* Clock initialisation code */ 1111/* Clock initialisation code */
1103static struct clksrc_clk *sysclks[] = { 1112static struct clksrc_clk *sysclks[] = {
1104 &clk_mout_apll, 1113 &clk_mout_apll,
@@ -1128,8 +1137,17 @@ static struct clksrc_clk *sysclks[] = {
1128 &clk_sclk_spdif, 1137 &clk_sclk_spdif,
1129}; 1138};
1130 1139
1140static struct clk *clk_cdev[] = {
1141 &clk_hsmmc0,
1142 &clk_hsmmc1,
1143 &clk_hsmmc2,
1144};
1145
1131static struct clksrc_clk *clksrc_cdev[] = { 1146static struct clksrc_clk *clksrc_cdev[] = {
1132 &clk_sclk_uart, 1147 &clk_sclk_uart,
1148 &clk_sclk_mmc0,
1149 &clk_sclk_mmc1,
1150 &clk_sclk_mmc2,
1133}; 1151};
1134 1152
1135void __init_or_cpufreq s5pc100_setup_clocks(void) 1153void __init_or_cpufreq s5pc100_setup_clocks(void)
@@ -1274,6 +1292,12 @@ static struct clk *clks[] __initdata = {
1274static struct clk_lookup s5pc100_clk_lookup[] = { 1292static struct clk_lookup s5pc100_clk_lookup[] = {
1275 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 1293 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1276 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), 1294 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1295 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1296 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1297 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1298 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1299 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1300 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1277}; 1301};
1278 1302
1279void __init s5pc100_register_clocks(void) 1303void __init s5pc100_register_clocks(void)
@@ -1294,6 +1318,10 @@ void __init s5pc100_register_clocks(void)
1294 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1318 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1295 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); 1319 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1296 1320
1321 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1322 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1323 s3c_disable_clocks(clk_cdev[ptr], 1);
1324
1297 s3c24xx_register_clock(&dummy_apb_pclk); 1325 s3c24xx_register_clock(&dummy_apb_pclk);
1298 1326
1299 s3c_pwmclk_init(); 1327 s3c_pwmclk_init();
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 43a045d354ec..dc4586b2b322 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -399,30 +399,6 @@ static struct clk init_clocks_off[] = {
399 .enable = s5pv210_clk_ip1_ctrl, 399 .enable = s5pv210_clk_ip1_ctrl,
400 .ctrlbit = (1<<25), 400 .ctrlbit = (1<<25),
401 }, { 401 }, {
402 .name = "hsmmc",
403 .devname = "s3c-sdhci.0",
404 .parent = &clk_hclk_psys.clk,
405 .enable = s5pv210_clk_ip2_ctrl,
406 .ctrlbit = (1<<16),
407 }, {
408 .name = "hsmmc",
409 .devname = "s3c-sdhci.1",
410 .parent = &clk_hclk_psys.clk,
411 .enable = s5pv210_clk_ip2_ctrl,
412 .ctrlbit = (1<<17),
413 }, {
414 .name = "hsmmc",
415 .devname = "s3c-sdhci.2",
416 .parent = &clk_hclk_psys.clk,
417 .enable = s5pv210_clk_ip2_ctrl,
418 .ctrlbit = (1<<18),
419 }, {
420 .name = "hsmmc",
421 .devname = "s3c-sdhci.3",
422 .parent = &clk_hclk_psys.clk,
423 .enable = s5pv210_clk_ip2_ctrl,
424 .ctrlbit = (1<<19),
425 }, {
426 .name = "systimer", 402 .name = "systimer",
427 .parent = &clk_pclk_psys.clk, 403 .parent = &clk_pclk_psys.clk,
428 .enable = s5pv210_clk_ip3_ctrl, 404 .enable = s5pv210_clk_ip3_ctrl,
@@ -559,6 +535,38 @@ static struct clk init_clocks[] = {
559 }, 535 },
560}; 536};
561 537
538static struct clk clk_hsmmc0 = {
539 .name = "hsmmc",
540 .devname = "s3c-sdhci.0",
541 .parent = &clk_hclk_psys.clk,
542 .enable = s5pv210_clk_ip2_ctrl,
543 .ctrlbit = (1<<16),
544};
545
546static struct clk clk_hsmmc1 = {
547 .name = "hsmmc",
548 .devname = "s3c-sdhci.1",
549 .parent = &clk_hclk_psys.clk,
550 .enable = s5pv210_clk_ip2_ctrl,
551 .ctrlbit = (1<<17),
552};
553
554static struct clk clk_hsmmc2 = {
555 .name = "hsmmc",
556 .devname = "s3c-sdhci.2",
557 .parent = &clk_hclk_psys.clk,
558 .enable = s5pv210_clk_ip2_ctrl,
559 .ctrlbit = (1<<18),
560};
561
562static struct clk clk_hsmmc3 = {
563 .name = "hsmmc",
564 .devname = "s3c-sdhci.3",
565 .parent = &clk_hclk_psys.clk,
566 .enable = s5pv210_clk_ip2_ctrl,
567 .ctrlbit = (1<<19),
568};
569
562static struct clk *clkset_uart_list[] = { 570static struct clk *clkset_uart_list[] = {
563 [6] = &clk_mout_mpll.clk, 571 [6] = &clk_mout_mpll.clk,
564 [7] = &clk_mout_epll.clk, 572 [7] = &clk_mout_epll.clk,
@@ -866,46 +874,6 @@ static struct clksrc_clk clksrcs[] = {
866 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 }, 874 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
867 }, { 875 }, {
868 .clk = { 876 .clk = {
869 .name = "sclk_mmc",
870 .devname = "s3c-sdhci.0",
871 .enable = s5pv210_clk_mask0_ctrl,
872 .ctrlbit = (1 << 8),
873 },
874 .sources = &clkset_group2,
875 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
876 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
877 }, {
878 .clk = {
879 .name = "sclk_mmc",
880 .devname = "s3c-sdhci.1",
881 .enable = s5pv210_clk_mask0_ctrl,
882 .ctrlbit = (1 << 9),
883 },
884 .sources = &clkset_group2,
885 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
886 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
887 }, {
888 .clk = {
889 .name = "sclk_mmc",
890 .devname = "s3c-sdhci.2",
891 .enable = s5pv210_clk_mask0_ctrl,
892 .ctrlbit = (1 << 10),
893 },
894 .sources = &clkset_group2,
895 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
896 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
897 }, {
898 .clk = {
899 .name = "sclk_mmc",
900 .devname = "s3c-sdhci.3",
901 .enable = s5pv210_clk_mask0_ctrl,
902 .ctrlbit = (1 << 11),
903 },
904 .sources = &clkset_group2,
905 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
906 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
907 }, {
908 .clk = {
909 .name = "sclk_mfc", 877 .name = "sclk_mfc",
910 .devname = "s5p-mfc", 878 .devname = "s5p-mfc",
911 .enable = s5pv210_clk_ip0_ctrl, 879 .enable = s5pv210_clk_ip0_ctrl,
@@ -1030,11 +998,70 @@ static struct clksrc_clk clk_sclk_uart3 = {
1030 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 }, 998 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
1031}; 999};
1032 1000
1001static struct clksrc_clk clk_sclk_mmc0 = {
1002 .clk = {
1003 .name = "sclk_mmc",
1004 .devname = "s3c-sdhci.0",
1005 .enable = s5pv210_clk_mask0_ctrl,
1006 .ctrlbit = (1 << 8),
1007 },
1008 .sources = &clkset_group2,
1009 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
1010 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
1011};
1012
1013static struct clksrc_clk clk_sclk_mmc1 = {
1014 .clk = {
1015 .name = "sclk_mmc",
1016 .devname = "s3c-sdhci.1",
1017 .enable = s5pv210_clk_mask0_ctrl,
1018 .ctrlbit = (1 << 9),
1019 },
1020 .sources = &clkset_group2,
1021 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
1022 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
1023};
1024
1025static struct clksrc_clk clk_sclk_mmc2 = {
1026 .clk = {
1027 .name = "sclk_mmc",
1028 .devname = "s3c-sdhci.2",
1029 .enable = s5pv210_clk_mask0_ctrl,
1030 .ctrlbit = (1 << 10),
1031 },
1032 .sources = &clkset_group2,
1033 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
1034 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
1035};
1036
1037static struct clksrc_clk clk_sclk_mmc3 = {
1038 .clk = {
1039 .name = "sclk_mmc",
1040 .devname = "s3c-sdhci.3",
1041 .enable = s5pv210_clk_mask0_ctrl,
1042 .ctrlbit = (1 << 11),
1043 },
1044 .sources = &clkset_group2,
1045 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
1046 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
1047};
1048
1033static struct clksrc_clk *clksrc_cdev[] = { 1049static struct clksrc_clk *clksrc_cdev[] = {
1034 &clk_sclk_uart0, 1050 &clk_sclk_uart0,
1035 &clk_sclk_uart1, 1051 &clk_sclk_uart1,
1036 &clk_sclk_uart2, 1052 &clk_sclk_uart2,
1037 &clk_sclk_uart3, 1053 &clk_sclk_uart3,
1054 &clk_sclk_mmc0,
1055 &clk_sclk_mmc1,
1056 &clk_sclk_mmc2,
1057 &clk_sclk_mmc3,
1058};
1059
1060static struct clk *clk_cdev[] = {
1061 &clk_hsmmc0,
1062 &clk_hsmmc1,
1063 &clk_hsmmc2,
1064 &clk_hsmmc3,
1038}; 1065};
1039 1066
1040/* Clock initialisation code */ 1067/* Clock initialisation code */
@@ -1282,6 +1309,14 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
1282 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), 1309 CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk),
1283 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), 1310 CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk),
1284 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), 1311 CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk),
1312 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1313 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1314 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1315 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3),
1316 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1317 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1318 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1319 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1285}; 1320};
1286 1321
1287void __init s5pv210_register_clocks(void) 1322void __init s5pv210_register_clocks(void)
@@ -1306,6 +1341,10 @@ void __init s5pv210_register_clocks(void)
1306 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 1341 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1307 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup)); 1342 clkdev_add_table(s5pv210_clk_lookup, ARRAY_SIZE(s5pv210_clk_lookup));
1308 1343
1344 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1345 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1346 s3c_disable_clocks(clk_cdev[ptr], 1);
1347
1309 s3c24xx_register_clock(&dummy_apb_pclk); 1348 s3c24xx_register_clock(&dummy_apb_pclk);
1310 s3c_pwmclk_init(); 1349 s3c_pwmclk_init();
1311} 1350}
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 4eab2cca2d92..95e68190d593 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -427,12 +427,6 @@ static struct clk init_clocks[] = {
427 .enable = s3c2443_clkcon_enable_h, 427 .enable = s3c2443_clkcon_enable_h,
428 .ctrlbit = S3C2443_HCLKCON_DMA5, 428 .ctrlbit = S3C2443_HCLKCON_DMA5,
429 }, { 429 }, {
430 .name = "hsmmc",
431 .devname = "s3c-sdhci.1",
432 .parent = &clk_h,
433 .enable = s3c2443_clkcon_enable_h,
434 .ctrlbit = S3C2443_HCLKCON_HSMMC,
435 }, {
436 .name = "gpio", 430 .name = "gpio",
437 .parent = &clk_p, 431 .parent = &clk_p,
438 .enable = s3c2443_clkcon_enable_p, 432 .enable = s3c2443_clkcon_enable_p,
@@ -514,6 +508,14 @@ static struct clk init_clocks[] = {
514 } 508 }
515}; 509};
516 510
511static struct clk hsmmc1_clk = {
512 .name = "hsmmc",
513 .devname = "s3c-sdhci.1",
514 .parent = &clk_h,
515 .enable = s3c2443_clkcon_enable_h,
516 .ctrlbit = S3C2443_HCLKCON_HSMMC,
517};
518
517static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0) 519static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
518{ 520{
519 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK; 521 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
@@ -579,6 +581,7 @@ static struct clk *clks[] __initdata = {
579 &clk_epll, 581 &clk_epll,
580 &clk_usb_bus, 582 &clk_usb_bus,
581 &clk_armdiv, 583 &clk_armdiv,
584 &hsmmc1_clk,
582}; 585};
583 586
584static struct clksrc_clk *clksrcs[] __initdata = { 587static struct clksrc_clk *clksrcs[] __initdata = {
@@ -595,6 +598,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
595 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), 598 CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
596 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), 599 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
597 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), 600 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
601 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
598}; 602};
599 603
600void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, 604void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-21 01:48:49 -0500