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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-05-19 23:43:47 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-05-19 23:43:47 -0400
commit3d07f0e83d4323d2cd45cc583f7cf1957aca3cac (patch)
tree279203d24b3a366ed6da93a3f9664409eb1a8488 /arch
parent593adf317cf165f7c66facf2285db9d4befbd1c0 (diff)
parentbbfff72ee3e76bd4712b87386af00bfe97114bc9 (diff)
Merge remote branch 'kumar/next' into next
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/boot/dts/p1020rdb.dts332
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core0.dts213
-rw-r--r--arch/powerpc/boot/dts/p1020rdb_camp_core1.dts148
-rw-r--r--arch/powerpc/boot/dts/p1020si.dtsi377
-rw-r--r--arch/powerpc/boot/dts/p1022ds.dts106
-rw-r--r--arch/powerpc/boot/dts/p2020ds.dts374
-rw-r--r--arch/powerpc/boot/dts/p2020rdb.dts378
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core0.dts245
-rw-r--r--arch/powerpc/boot/dts/p2020rdb_camp_core1.dts150
-rw-r--r--arch/powerpc/boot/dts/p2020si.dtsi382
-rw-r--r--arch/powerpc/configs/83xx/mpc8313_rdb_defconfig1
-rw-r--r--arch/powerpc/configs/83xx/mpc8315_rdb_defconfig1
-rw-r--r--arch/powerpc/configs/85xx/mpc8540_ads_defconfig1
-rw-r--r--arch/powerpc/configs/85xx/mpc8560_ads_defconfig1
-rw-r--r--arch/powerpc/configs/85xx/mpc85xx_cds_defconfig1
-rw-r--r--arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig1
-rw-r--r--arch/powerpc/configs/e55xx_smp_defconfig39
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig1
-rw-r--r--arch/powerpc/configs/mpc86xx_defconfig1
-rw-r--r--arch/powerpc/include/asm/cputable.h4
-rw-r--r--arch/powerpc/include/asm/mpic.h5
-rw-r--r--arch/powerpc/include/asm/reg_booke.h4
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S3
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S112
-rw-r--r--arch/powerpc/kernel/setup_64.c8
-rw-r--r--arch/powerpc/platforms/86xx/mpc8610_hpcd.c99
-rw-r--r--arch/powerpc/sysdev/mpic.c129
28 files changed, 1759 insertions, 1358 deletions
diff --git a/arch/powerpc/boot/dts/p1020rdb.dts b/arch/powerpc/boot/dts/p1020rdb.dts
index e0668f877794..d6a8ae458137 100644
--- a/arch/powerpc/boot/dts/p1020rdb.dts
+++ b/arch/powerpc/boot/dts/p1020rdb.dts
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p1020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P1020"; 15 model = "fsl,P1020RDB";
15 compatible = "fsl,P1020RDB"; 16 compatible = "fsl,P1020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 serial0 = &serial0; 19 serial0 = &serial0;
@@ -26,34 +25,11 @@
26 pci1 = &pci1; 25 pci1 = &pci1;
27 }; 26 };
28 27
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P1020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P1020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory { 28 memory {
47 device_type = "memory"; 29 device_type = "memory";
48 }; 30 };
49 31
50 localbus@ffe05000 { 32 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57 33
58 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */ 34 /* NOR, NAND Flashes and Vitesse 5 port L2 switch */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,88 +141,14 @@
165 }; 141 };
166 142
167 soc@ffe00000 { 143 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p1020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p1020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <16 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p1020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <16 2>;
193 };
194
195 i2c@3000 { 144 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 { 145 rtc@68 {
205 compatible = "dallas,ds1339"; 146 compatible = "dallas,ds1339";
206 reg = <0x68>; 147 reg = <0x68>;
207 }; 148 };
208 }; 149 };
209 150
210 i2c@3100 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240
241 spi@7000 { 151 spi@7000 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250 152
251 fsl_m25p80@0 { 153 fsl_m25p80@0 {
252 #address-cells = <1>; 154 #address-cells = <1>;
@@ -294,66 +196,7 @@
294 }; 196 };
295 }; 197 };
296 198
297 gpio: gpio-controller@f000 {
298 #gpio-cells = <2>;
299 compatible = "fsl,mpc8572-gpio";
300 reg = <0xf000 0x100>;
301 interrupts = <47 0x2>;
302 interrupt-parent = <&mpic>;
303 gpio-controller;
304 };
305
306 L2: l2-cache-controller@20000 {
307 compatible = "fsl,p1020-l2-cache-controller";
308 reg = <0x20000 0x1000>;
309 cache-line-size = <32>; // 32 bytes
310 cache-size = <0x40000>; // L2,256K
311 interrupt-parent = <&mpic>;
312 interrupts = <16 2>;
313 };
314
315 dma@21300 {
316 #address-cells = <1>;
317 #size-cells = <1>;
318 compatible = "fsl,eloplus-dma";
319 reg = <0x21300 0x4>;
320 ranges = <0x0 0x21100 0x200>;
321 cell-index = <0>;
322 dma-channel@0 {
323 compatible = "fsl,eloplus-dma-channel";
324 reg = <0x0 0x80>;
325 cell-index = <0>;
326 interrupt-parent = <&mpic>;
327 interrupts = <20 2>;
328 };
329 dma-channel@80 {
330 compatible = "fsl,eloplus-dma-channel";
331 reg = <0x80 0x80>;
332 cell-index = <1>;
333 interrupt-parent = <&mpic>;
334 interrupts = <21 2>;
335 };
336 dma-channel@100 {
337 compatible = "fsl,eloplus-dma-channel";
338 reg = <0x100 0x80>;
339 cell-index = <2>;
340 interrupt-parent = <&mpic>;
341 interrupts = <22 2>;
342 };
343 dma-channel@180 {
344 compatible = "fsl,eloplus-dma-channel";
345 reg = <0x180 0x80>;
346 cell-index = <3>;
347 interrupt-parent = <&mpic>;
348 interrupts = <23 2>;
349 };
350 };
351
352 mdio@24000 { 199 mdio@24000 {
353 #address-cells = <1>;
354 #size-cells = <0>;
355 compatible = "fsl,etsec2-mdio";
356 reg = <0x24000 0x1000 0xb0030 0x4>;
357 200
358 phy0: ethernet-phy@0 { 201 phy0: ethernet-phy@0 {
359 interrupt-parent = <&mpic>; 202 interrupt-parent = <&mpic>;
@@ -369,10 +212,6 @@
369 }; 212 };
370 213
371 mdio@25000 { 214 mdio@25000 {
372 #address-cells = <1>;
373 #size-cells = <0>;
374 compatible = "fsl,etsec2-tbi";
375 reg = <0x25000 0x1000 0xb1030 0x4>;
376 215
377 tbi0: tbi-phy@11 { 216 tbi0: tbi-phy@11 {
378 reg = <0x11>; 217 reg = <0x11>;
@@ -381,97 +220,25 @@
381 }; 220 };
382 221
383 enet0: ethernet@b0000 { 222 enet0: ethernet@b0000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 device_type = "network";
387 model = "eTSEC";
388 compatible = "fsl,etsec2";
389 fsl,num_rx_queues = <0x8>;
390 fsl,num_tx_queues = <0x8>;
391 local-mac-address = [ 00 00 00 00 00 00 ];
392 interrupt-parent = <&mpic>;
393 fixed-link = <1 1 1000 0 0>; 223 fixed-link = <1 1 1000 0 0>;
394 phy-connection-type = "rgmii-id"; 224 phy-connection-type = "rgmii-id";
395 225
396 queue-group@0 {
397 #address-cells = <1>;
398 #size-cells = <1>;
399 reg = <0xb0000 0x1000>;
400 interrupts = <29 2 30 2 34 2>;
401 };
402
403 queue-group@1 {
404 #address-cells = <1>;
405 #size-cells = <1>;
406 reg = <0xb4000 0x1000>;
407 interrupts = <17 2 18 2 24 2>;
408 };
409 }; 226 };
410 227
411 enet1: ethernet@b1000 { 228 enet1: ethernet@b1000 {
412 #address-cells = <1>;
413 #size-cells = <1>;
414 device_type = "network";
415 model = "eTSEC";
416 compatible = "fsl,etsec2";
417 fsl,num_rx_queues = <0x8>;
418 fsl,num_tx_queues = <0x8>;
419 local-mac-address = [ 00 00 00 00 00 00 ];
420 interrupt-parent = <&mpic>;
421 phy-handle = <&phy0>; 229 phy-handle = <&phy0>;
422 tbi-handle = <&tbi0>; 230 tbi-handle = <&tbi0>;
423 phy-connection-type = "sgmii"; 231 phy-connection-type = "sgmii";
424 232
425 queue-group@0 {
426 #address-cells = <1>;
427 #size-cells = <1>;
428 reg = <0xb1000 0x1000>;
429 interrupts = <35 2 36 2 40 2>;
430 };
431
432 queue-group@1 {
433 #address-cells = <1>;
434 #size-cells = <1>;
435 reg = <0xb5000 0x1000>;
436 interrupts = <51 2 52 2 67 2>;
437 };
438 }; 233 };
439 234
440 enet2: ethernet@b2000 { 235 enet2: ethernet@b2000 {
441 #address-cells = <1>;
442 #size-cells = <1>;
443 device_type = "network";
444 model = "eTSEC";
445 compatible = "fsl,etsec2";
446 fsl,num_rx_queues = <0x8>;
447 fsl,num_tx_queues = <0x8>;
448 local-mac-address = [ 00 00 00 00 00 00 ];
449 interrupt-parent = <&mpic>;
450 phy-handle = <&phy1>; 236 phy-handle = <&phy1>;
451 phy-connection-type = "rgmii-id"; 237 phy-connection-type = "rgmii-id";
452 238
453 queue-group@0 {
454 #address-cells = <1>;
455 #size-cells = <1>;
456 reg = <0xb2000 0x1000>;
457 interrupts = <31 2 32 2 33 2>;
458 };
459
460 queue-group@1 {
461 #address-cells = <1>;
462 #size-cells = <1>;
463 reg = <0xb6000 0x1000>;
464 interrupts = <25 2 26 2 27 2>;
465 };
466 }; 239 };
467 240
468 usb@22000 { 241 usb@22000 {
469 #address-cells = <1>;
470 #size-cells = <0>;
471 compatible = "fsl-usb2-dr";
472 reg = <0x22000 0x1000>;
473 interrupt-parent = <&mpic>;
474 interrupts = <28 0x2>;
475 phy_type = "ulpi"; 242 phy_type = "ulpi";
476 }; 243 };
477 244
@@ -481,82 +248,23 @@
481 it enables USB2. OTOH, U-Boot does create a new node 248 it enables USB2. OTOH, U-Boot does create a new node
482 when there isn't any. So, just comment it out. 249 when there isn't any. So, just comment it out.
483 usb@23000 { 250 usb@23000 {
484 #address-cells = <1>;
485 #size-cells = <0>;
486 compatible = "fsl-usb2-dr";
487 reg = <0x23000 0x1000>;
488 interrupt-parent = <&mpic>;
489 interrupts = <46 0x2>;
490 phy_type = "ulpi"; 251 phy_type = "ulpi";
491 }; 252 };
492 */ 253 */
493 254
494 sdhci@2e000 {
495 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
496 reg = <0x2e000 0x1000>;
497 interrupts = <72 0x2>;
498 interrupt-parent = <&mpic>;
499 /* Filled in by U-Boot */
500 clock-frequency = <0>;
501 };
502
503 crypto@30000 {
504 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
505 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
506 reg = <0x30000 0x10000>;
507 interrupts = <45 2 58 2>;
508 interrupt-parent = <&mpic>;
509 fsl,num-channels = <4>;
510 fsl,channel-fifo-len = <24>;
511 fsl,exec-units-mask = <0xbfe>;
512 fsl,descriptor-types-mask = <0x3ab0ebf>;
513 };
514
515 mpic: pic@40000 {
516 interrupt-controller;
517 #address-cells = <0>;
518 #interrupt-cells = <2>;
519 reg = <0x40000 0x40000>;
520 compatible = "chrp,open-pic";
521 device_type = "open-pic";
522 };
523
524 msi@41600 {
525 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
526 reg = <0x41600 0x80>;
527 msi-available-ranges = <0 0x100>;
528 interrupts = <
529 0xe0 0
530 0xe1 0
531 0xe2 0
532 0xe3 0
533 0xe4 0
534 0xe5 0
535 0xe6 0
536 0xe7 0>;
537 interrupt-parent = <&mpic>;
538 };
539
540 global-utilities@e0000 { //global utilities block
541 compatible = "fsl,p1020-guts";
542 reg = <0xe0000 0x1000>;
543 fsl,has-rstcr;
544 };
545 }; 255 };
546 256
547 pci0: pcie@ffe09000 { 257 pci0: pcie@ffe09000 {
548 compatible = "fsl,mpc8548-pcie";
549 device_type = "pci";
550 #interrupt-cells = <1>;
551 #size-cells = <2>;
552 #address-cells = <3>;
553 reg = <0 0xffe09000 0 0x1000>;
554 bus-range = <0 255>;
555 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 258 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
556 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 259 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
557 clock-frequency = <33333333>; 260 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
558 interrupt-parent = <&mpic>; 261 interrupt-map = <
559 interrupts = <16 2>; 262 /* IDSEL 0x0 */
263 0000 0x0 0x0 0x1 &mpic 0x4 0x1
264 0000 0x0 0x0 0x2 &mpic 0x5 0x1
265 0000 0x0 0x0 0x3 &mpic 0x6 0x1
266 0000 0x0 0x0 0x4 &mpic 0x7 0x1
267 >;
560 pcie@0 { 268 pcie@0 {
561 reg = <0x0 0x0 0x0 0x0 0x0>; 269 reg = <0x0 0x0 0x0 0x0 0x0>;
562 #size-cells = <2>; 270 #size-cells = <2>;
@@ -573,18 +281,16 @@
573 }; 281 };
574 282
575 pci1: pcie@ffe0a000 { 283 pci1: pcie@ffe0a000 {
576 compatible = "fsl,mpc8548-pcie";
577 device_type = "pci";
578 #interrupt-cells = <1>;
579 #size-cells = <2>;
580 #address-cells = <3>;
581 reg = <0 0xffe0a000 0 0x1000>;
582 bus-range = <0 255>;
583 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 284 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
584 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 285 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
585 clock-frequency = <33333333>; 286 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
586 interrupt-parent = <&mpic>; 287 interrupt-map = <
587 interrupts = <16 2>; 288 /* IDSEL 0x0 */
289 0000 0x0 0x0 0x1 &mpic 0x0 0x1
290 0000 0x0 0x0 0x2 &mpic 0x1 0x1
291 0000 0x0 0x0 0x3 &mpic 0x2 0x1
292 0000 0x0 0x0 0x4 &mpic 0x3 0x1
293 >;
588 pcie@0 { 294 pcie@0 {
589 reg = <0x0 0x0 0x0 0x0 0x0>; 295 reg = <0x0 0x0 0x0 0x0 0x0>;
590 #size-cells = <2>; 296 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
new file mode 100644
index 000000000000..f0bf7f42f097
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core0.dts
@@ -0,0 +1,213 @@
1/*
2 * P1020 RDB Core0 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts file allows core0 to have memory, l2, i2c, spi, gpio, tdm, dma, usb,
7 * eth1, eth2, sdhc, crypto, global-util, message, pci0, pci1, msi.
8 *
9 * Please note to add "-b 0" for core0's dts compiling.
10 *
11 * Copyright 2011 Freescale Semiconductor Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19/include/ "p1020si.dtsi"
20
21/ {
22 model = "fsl,P1020RDB";
23 compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
24
25 aliases {
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 serial0 = &serial0;
29 pci0 = &pci0;
30 pci1 = &pci1;
31 };
32
33 cpus {
34 PowerPC,P1020@1 {
35 status = "disabled";
36 };
37 };
38
39 memory {
40 device_type = "memory";
41 };
42
43 localbus@ffe05000 {
44 status = "disabled";
45 };
46
47 soc@ffe00000 {
48 i2c@3000 {
49 rtc@68 {
50 compatible = "dallas,ds1339";
51 reg = <0x68>;
52 };
53 };
54
55 serial1: serial@4600 {
56 status = "disabled";
57 };
58
59 spi@7000 {
60 fsl_m25p80@0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,espi-flash";
64 reg = <0>;
65 linux,modalias = "fsl_m25p80";
66 spi-max-frequency = <40000000>;
67
68 partition@0 {
69 /* 512KB for u-boot Bootloader Image */
70 reg = <0x0 0x00080000>;
71 label = "SPI (RO) U-Boot Image";
72 read-only;
73 };
74
75 partition@80000 {
76 /* 512KB for DTB Image */
77 reg = <0x00080000 0x00080000>;
78 label = "SPI (RO) DTB Image";
79 read-only;
80 };
81
82 partition@100000 {
83 /* 4MB for Linux Kernel Image */
84 reg = <0x00100000 0x00400000>;
85 label = "SPI (RO) Linux Kernel Image";
86 read-only;
87 };
88
89 partition@500000 {
90 /* 4MB for Compressed RFS Image */
91 reg = <0x00500000 0x00400000>;
92 label = "SPI (RO) Compressed RFS Image";
93 read-only;
94 };
95
96 partition@900000 {
97 /* 7MB for JFFS2 based RFS */
98 reg = <0x00900000 0x00700000>;
99 label = "SPI (RW) JFFS2 RFS";
100 };
101 };
102 };
103
104 mdio@24000 {
105 phy0: ethernet-phy@0 {
106 interrupt-parent = <&mpic>;
107 interrupts = <3 1>;
108 reg = <0x0>;
109 };
110 phy1: ethernet-phy@1 {
111 interrupt-parent = <&mpic>;
112 interrupts = <2 1>;
113 reg = <0x1>;
114 };
115 };
116
117 mdio@25000 {
118 tbi0: tbi-phy@11 {
119 reg = <0x11>;
120 device_type = "tbi-phy";
121 };
122 };
123
124 enet0: ethernet@b0000 {
125 status = "disabled";
126 };
127
128 enet1: ethernet@b1000 {
129 phy-handle = <&phy0>;
130 tbi-handle = <&tbi0>;
131 phy-connection-type = "sgmii";
132 };
133
134 enet2: ethernet@b2000 {
135 phy-handle = <&phy1>;
136 phy-connection-type = "rgmii-id";
137 };
138
139 usb@22000 {
140 phy_type = "ulpi";
141 };
142
143 /* USB2 is shared with localbus, so it must be disabled
144 by default. We can't put 'status = "disabled";' here
145 since U-Boot doesn't clear the status property when
146 it enables USB2. OTOH, U-Boot does create a new node
147 when there isn't any. So, just comment it out.
148 usb@23000 {
149 phy_type = "ulpi";
150 };
151 */
152
153 mpic: pic@40000 {
154 protected-sources = <
155 42 29 30 34 /* serial1, enet0-queue-group0 */
156 17 18 24 45 /* enet0-queue-group1, crypto */
157 >;
158 };
159
160 };
161
162 pci0: pcie@ffe09000 {
163 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
164 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
165 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
166 interrupt-map = <
167 /* IDSEL 0x0 */
168 0000 0x0 0x0 0x1 &mpic 0x4 0x1
169 0000 0x0 0x0 0x2 &mpic 0x5 0x1
170 0000 0x0 0x0 0x3 &mpic 0x6 0x1
171 0000 0x0 0x0 0x4 &mpic 0x7 0x1
172 >;
173 pcie@0 {
174 reg = <0x0 0x0 0x0 0x0 0x0>;
175 #size-cells = <2>;
176 #address-cells = <3>;
177 device_type = "pci";
178 ranges = <0x2000000 0x0 0xa0000000
179 0x2000000 0x0 0xa0000000
180 0x0 0x20000000
181
182 0x1000000 0x0 0x0
183 0x1000000 0x0 0x0
184 0x0 0x100000>;
185 };
186 };
187
188 pci1: pcie@ffe0a000 {
189 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
190 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
191 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
192 interrupt-map = <
193 /* IDSEL 0x0 */
194 0000 0x0 0x0 0x1 &mpic 0x0 0x1
195 0000 0x0 0x0 0x2 &mpic 0x1 0x1
196 0000 0x0 0x0 0x3 &mpic 0x2 0x1
197 0000 0x0 0x0 0x4 &mpic 0x3 0x1
198 >;
199 pcie@0 {
200 reg = <0x0 0x0 0x0 0x0 0x0>;
201 #size-cells = <2>;
202 #address-cells = <3>;
203 device_type = "pci";
204 ranges = <0x2000000 0x0 0x80000000
205 0x2000000 0x0 0x80000000
206 0x0 0x20000000
207
208 0x1000000 0x0 0x0
209 0x1000000 0x0 0x0
210 0x0 0x100000>;
211 };
212 };
213};
diff --git a/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
new file mode 100644
index 000000000000..6ec02204a44e
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb_camp_core1.dts
@@ -0,0 +1,148 @@
1/*
2 * P1020 RDB Core1 Device Tree Source in CAMP mode.
3 *
4 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
5 * can be shared, all the other devices must be assigned to one core only.
6 * This dts allows core1 to have l2, eth0, crypto.
7 *
8 * Please note to add "-b 1" for core1's dts compiling.
9 *
10 * Copyright 2011 Freescale Semiconductor Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 */
17
18/include/ "p1020si.dtsi"
19
20/ {
21 model = "fsl,P1020RDB";
22 compatible = "fsl,P1020RDB", "fsl,MPC85XXRDB-CAMP";
23
24 aliases {
25 ethernet0 = &enet0;
26 serial0 = &serial1;
27 };
28
29 cpus {
30 PowerPC,P1020@0 {
31 status = "disabled";
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 };
38
39 localbus@ffe05000 {
40 status = "disabled";
41 };
42
43 soc@ffe00000 {
44 ecm-law@0 {
45 status = "disabled";
46 };
47
48 ecm@1000 {
49 status = "disabled";
50 };
51
52 memory-controller@2000 {
53 status = "disabled";
54 };
55
56 i2c@3000 {
57 status = "disabled";
58 };
59
60 i2c@3100 {
61 status = "disabled";
62 };
63
64 serial0: serial@4500 {
65 status = "disabled";
66 };
67
68 spi@7000 {
69 status = "disabled";
70 };
71
72 gpio: gpio-controller@f000 {
73 status = "disabled";
74 };
75
76 dma@21300 {
77 status = "disabled";
78 };
79
80 mdio@24000 {
81 status = "disabled";
82 };
83
84 mdio@25000 {
85 status = "disabled";
86 };
87
88 enet0: ethernet@b0000 {
89 fixed-link = <1 1 1000 0 0>;
90 phy-connection-type = "rgmii-id";
91
92 };
93
94 enet1: ethernet@b1000 {
95 status = "disabled";
96 };
97
98 enet2: ethernet@b2000 {
99 status = "disabled";
100 };
101
102 usb@22000 {
103 status = "disabled";
104 };
105
106 sdhci@2e000 {
107 status = "disabled";
108 };
109
110 mpic: pic@40000 {
111 protected-sources = <
112 16 /* ecm, mem, L2, pci0, pci1 */
113 43 42 59 /* i2c, serial0, spi */
114 47 63 62 /* gpio, tdm */
115 20 21 22 23 /* dma */
116 03 02 /* mdio */
117 35 36 40 /* enet1-queue-group0 */
118 51 52 67 /* enet1-queue-group1 */
119 31 32 33 /* enet2-queue-group0 */
120 25 26 27 /* enet2-queue-group1 */
121 28 72 58 /* usb, sdhci, crypto */
122 0xb0 0xb1 0xb2 /* message */
123 0xb3 0xb4 0xb5
124 0xb6 0xb7
125 0xe0 0xe1 0xe2 /* msi */
126 0xe3 0xe4 0xe5
127 0xe6 0xe7 /* sdhci, crypto , pci */
128 >;
129 };
130
131 msi@41600 {
132 status = "disabled";
133 };
134
135 global-utilities@e0000 { //global utilities block
136 status = "disabled";
137 };
138
139 };
140
141 pci0: pcie@ffe09000 {
142 status = "disabled";
143 };
144
145 pci1: pcie@ffe0a000 {
146 status = "disabled";
147 };
148};
diff --git a/arch/powerpc/boot/dts/p1020si.dtsi b/arch/powerpc/boot/dts/p1020si.dtsi
new file mode 100644
index 000000000000..5c5acb66c3fc
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020si.dtsi
@@ -0,0 +1,377 @@
1/*
2 * P1020si Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P1020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P1020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P1020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p1020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p1020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <16 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p1020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <16 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 gpio: gpio-controller@f000 {
126 #gpio-cells = <2>;
127 compatible = "fsl,mpc8572-gpio";
128 reg = <0xf000 0x100>;
129 interrupts = <47 0x2>;
130 interrupt-parent = <&mpic>;
131 gpio-controller;
132 };
133
134 L2: l2-cache-controller@20000 {
135 compatible = "fsl,p1020-l2-cache-controller";
136 reg = <0x20000 0x1000>;
137 cache-line-size = <32>; // 32 bytes
138 cache-size = <0x40000>; // L2,256K
139 interrupt-parent = <&mpic>;
140 interrupts = <16 2>;
141 };
142
143 dma@21300 {
144 #address-cells = <1>;
145 #size-cells = <1>;
146 compatible = "fsl,eloplus-dma";
147 reg = <0x21300 0x4>;
148 ranges = <0x0 0x21100 0x200>;
149 cell-index = <0>;
150 dma-channel@0 {
151 compatible = "fsl,eloplus-dma-channel";
152 reg = <0x0 0x80>;
153 cell-index = <0>;
154 interrupt-parent = <&mpic>;
155 interrupts = <20 2>;
156 };
157 dma-channel@80 {
158 compatible = "fsl,eloplus-dma-channel";
159 reg = <0x80 0x80>;
160 cell-index = <1>;
161 interrupt-parent = <&mpic>;
162 interrupts = <21 2>;
163 };
164 dma-channel@100 {
165 compatible = "fsl,eloplus-dma-channel";
166 reg = <0x100 0x80>;
167 cell-index = <2>;
168 interrupt-parent = <&mpic>;
169 interrupts = <22 2>;
170 };
171 dma-channel@180 {
172 compatible = "fsl,eloplus-dma-channel";
173 reg = <0x180 0x80>;
174 cell-index = <3>;
175 interrupt-parent = <&mpic>;
176 interrupts = <23 2>;
177 };
178 };
179
180 mdio@24000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,etsec2-mdio";
184 reg = <0x24000 0x1000 0xb0030 0x4>;
185
186 };
187
188 mdio@25000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 compatible = "fsl,etsec2-tbi";
192 reg = <0x25000 0x1000 0xb1030 0x4>;
193
194 };
195
196 enet0: ethernet@b0000 {
197 #address-cells = <1>;
198 #size-cells = <1>;
199 device_type = "network";
200 model = "eTSEC";
201 compatible = "fsl,etsec2";
202 fsl,num_rx_queues = <0x8>;
203 fsl,num_tx_queues = <0x8>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupt-parent = <&mpic>;
206
207 queue-group@0 {
208 #address-cells = <1>;
209 #size-cells = <1>;
210 reg = <0xb0000 0x1000>;
211 interrupts = <29 2 30 2 34 2>;
212 };
213
214 queue-group@1 {
215 #address-cells = <1>;
216 #size-cells = <1>;
217 reg = <0xb4000 0x1000>;
218 interrupts = <17 2 18 2 24 2>;
219 };
220 };
221
222 enet1: ethernet@b1000 {
223 #address-cells = <1>;
224 #size-cells = <1>;
225 device_type = "network";
226 model = "eTSEC";
227 compatible = "fsl,etsec2";
228 fsl,num_rx_queues = <0x8>;
229 fsl,num_tx_queues = <0x8>;
230 local-mac-address = [ 00 00 00 00 00 00 ];
231 interrupt-parent = <&mpic>;
232
233 queue-group@0 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 reg = <0xb1000 0x1000>;
237 interrupts = <35 2 36 2 40 2>;
238 };
239
240 queue-group@1 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 reg = <0xb5000 0x1000>;
244 interrupts = <51 2 52 2 67 2>;
245 };
246 };
247
248 enet2: ethernet@b2000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "fsl,etsec2";
254 fsl,num_rx_queues = <0x8>;
255 fsl,num_tx_queues = <0x8>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupt-parent = <&mpic>;
258
259 queue-group@0 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 reg = <0xb2000 0x1000>;
263 interrupts = <31 2 32 2 33 2>;
264 };
265
266 queue-group@1 {
267 #address-cells = <1>;
268 #size-cells = <1>;
269 reg = <0xb6000 0x1000>;
270 interrupts = <25 2 26 2 27 2>;
271 };
272 };
273
274 usb@22000 {
275 #address-cells = <1>;
276 #size-cells = <0>;
277 compatible = "fsl-usb2-dr";
278 reg = <0x22000 0x1000>;
279 interrupt-parent = <&mpic>;
280 interrupts = <28 0x2>;
281 };
282
283 /* USB2 is shared with localbus, so it must be disabled
284 by default. We can't put 'status = "disabled";' here
285 since U-Boot doesn't clear the status property when
286 it enables USB2. OTOH, U-Boot does create a new node
287 when there isn't any. So, just comment it out.
288 usb@23000 {
289 #address-cells = <1>;
290 #size-cells = <0>;
291 compatible = "fsl-usb2-dr";
292 reg = <0x23000 0x1000>;
293 interrupt-parent = <&mpic>;
294 interrupts = <46 0x2>;
295 phy_type = "ulpi";
296 };
297 */
298
299 sdhci@2e000 {
300 compatible = "fsl,p1020-esdhc", "fsl,esdhc";
301 reg = <0x2e000 0x1000>;
302 interrupts = <72 0x2>;
303 interrupt-parent = <&mpic>;
304 /* Filled in by U-Boot */
305 clock-frequency = <0>;
306 };
307
308 crypto@30000 {
309 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
310 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
311 reg = <0x30000 0x10000>;
312 interrupts = <45 2 58 2>;
313 interrupt-parent = <&mpic>;
314 fsl,num-channels = <4>;
315 fsl,channel-fifo-len = <24>;
316 fsl,exec-units-mask = <0xbfe>;
317 fsl,descriptor-types-mask = <0x3ab0ebf>;
318 };
319
320 mpic: pic@40000 {
321 interrupt-controller;
322 #address-cells = <0>;
323 #interrupt-cells = <2>;
324 reg = <0x40000 0x40000>;
325 compatible = "chrp,open-pic";
326 device_type = "open-pic";
327 };
328
329 msi@41600 {
330 compatible = "fsl,p1020-msi", "fsl,mpic-msi";
331 reg = <0x41600 0x80>;
332 msi-available-ranges = <0 0x100>;
333 interrupts = <
334 0xe0 0
335 0xe1 0
336 0xe2 0
337 0xe3 0
338 0xe4 0
339 0xe5 0
340 0xe6 0
341 0xe7 0>;
342 interrupt-parent = <&mpic>;
343 };
344
345 global-utilities@e0000 { //global utilities block
346 compatible = "fsl,p1020-guts","fsl,p2020-guts";
347 reg = <0xe0000 0x1000>;
348 fsl,has-rstcr;
349 };
350 };
351
352 pci0: pcie@ffe09000 {
353 compatible = "fsl,mpc8548-pcie";
354 device_type = "pci";
355 #interrupt-cells = <1>;
356 #size-cells = <2>;
357 #address-cells = <3>;
358 reg = <0 0xffe09000 0 0x1000>;
359 bus-range = <0 255>;
360 clock-frequency = <33333333>;
361 interrupt-parent = <&mpic>;
362 interrupts = <16 2>;
363 };
364
365 pci1: pcie@ffe0a000 {
366 compatible = "fsl,mpc8548-pcie";
367 device_type = "pci";
368 #interrupt-cells = <1>;
369 #size-cells = <2>;
370 #address-cells = <3>;
371 reg = <0 0xffe0a000 0 0x1000>;
372 bus-range = <0 255>;
373 clock-frequency = <33333333>;
374 interrupt-parent = <&mpic>;
375 interrupts = <16 2>;
376 };
377};
diff --git a/arch/powerpc/boot/dts/p1022ds.dts b/arch/powerpc/boot/dts/p1022ds.dts
index 59ef405c1c91..4f685a779f4c 100644
--- a/arch/powerpc/boot/dts/p1022ds.dts
+++ b/arch/powerpc/boot/dts/p1022ds.dts
@@ -52,7 +52,7 @@
52 #size-cells = <1>; 52 #size-cells = <1>;
53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus"; 53 compatible = "fsl,p1022-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>; 54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>; 55 interrupts = <19 2 0 0>;
56 56
57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 57 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
58 0x1 0x0 0xf 0xe0000000 0x08000000 58 0x1 0x0 0xf 0xe0000000 0x08000000
@@ -157,7 +157,7 @@
157 * IRQ8 is generated if the "EVENT" switch is pressed 157 * IRQ8 is generated if the "EVENT" switch is pressed
158 * and PX_CTL[EVESEL] is set to 00. 158 * and PX_CTL[EVESEL] is set to 00.
159 */ 159 */
160 interrupts = <8 8>; 160 interrupts = <8 8 0 0>;
161 }; 161 };
162 }; 162 };
163 163
@@ -178,13 +178,13 @@
178 ecm@1000 { 178 ecm@1000 {
179 compatible = "fsl,p1022-ecm", "fsl,ecm"; 179 compatible = "fsl,p1022-ecm", "fsl,ecm";
180 reg = <0x1000 0x1000>; 180 reg = <0x1000 0x1000>;
181 interrupts = <16 2>; 181 interrupts = <16 2 0 0>;
182 }; 182 };
183 183
184 memory-controller@2000 { 184 memory-controller@2000 {
185 compatible = "fsl,p1022-memory-controller"; 185 compatible = "fsl,p1022-memory-controller";
186 reg = <0x2000 0x1000>; 186 reg = <0x2000 0x1000>;
187 interrupts = <16 2>; 187 interrupts = <16 2 0 0>;
188 }; 188 };
189 189
190 i2c@3000 { 190 i2c@3000 {
@@ -193,7 +193,7 @@
193 cell-index = <0>; 193 cell-index = <0>;
194 compatible = "fsl-i2c"; 194 compatible = "fsl-i2c";
195 reg = <0x3000 0x100>; 195 reg = <0x3000 0x100>;
196 interrupts = <43 2>; 196 interrupts = <43 2 0 0>;
197 dfsrr; 197 dfsrr;
198 }; 198 };
199 199
@@ -203,7 +203,7 @@
203 cell-index = <1>; 203 cell-index = <1>;
204 compatible = "fsl-i2c"; 204 compatible = "fsl-i2c";
205 reg = <0x3100 0x100>; 205 reg = <0x3100 0x100>;
206 interrupts = <43 2>; 206 interrupts = <43 2 0 0>;
207 dfsrr; 207 dfsrr;
208 208
209 wm8776:codec@1a { 209 wm8776:codec@1a {
@@ -220,7 +220,7 @@
220 compatible = "ns16550"; 220 compatible = "ns16550";
221 reg = <0x4500 0x100>; 221 reg = <0x4500 0x100>;
222 clock-frequency = <0>; 222 clock-frequency = <0>;
223 interrupts = <42 2>; 223 interrupts = <42 2 0 0>;
224 }; 224 };
225 225
226 serial1: serial@4600 { 226 serial1: serial@4600 {
@@ -229,7 +229,7 @@
229 compatible = "ns16550"; 229 compatible = "ns16550";
230 reg = <0x4600 0x100>; 230 reg = <0x4600 0x100>;
231 clock-frequency = <0>; 231 clock-frequency = <0>;
232 interrupts = <42 2>; 232 interrupts = <42 2 0 0>;
233 }; 233 };
234 234
235 spi@7000 { 235 spi@7000 {
@@ -238,7 +238,7 @@
238 #size-cells = <0>; 238 #size-cells = <0>;
239 compatible = "fsl,espi"; 239 compatible = "fsl,espi";
240 reg = <0x7000 0x1000>; 240 reg = <0x7000 0x1000>;
241 interrupts = <59 0x2>; 241 interrupts = <59 0x2 0 0>;
242 espi,num-ss-bits = <4>; 242 espi,num-ss-bits = <4>;
243 mode = "cpu"; 243 mode = "cpu";
244 244
@@ -275,7 +275,7 @@
275 compatible = "fsl,mpc8610-ssi"; 275 compatible = "fsl,mpc8610-ssi";
276 cell-index = <0>; 276 cell-index = <0>;
277 reg = <0x15000 0x100>; 277 reg = <0x15000 0x100>;
278 interrupts = <75 2>; 278 interrupts = <75 2 0 0>;
279 fsl,mode = "i2s-slave"; 279 fsl,mode = "i2s-slave";
280 codec-handle = <&wm8776>; 280 codec-handle = <&wm8776>;
281 fsl,playback-dma = <&dma00>; 281 fsl,playback-dma = <&dma00>;
@@ -294,25 +294,25 @@
294 compatible = "fsl,ssi-dma-channel"; 294 compatible = "fsl,ssi-dma-channel";
295 reg = <0x0 0x80>; 295 reg = <0x0 0x80>;
296 cell-index = <0>; 296 cell-index = <0>;
297 interrupts = <76 2>; 297 interrupts = <76 2 0 0>;
298 }; 298 };
299 dma01: dma-channel@80 { 299 dma01: dma-channel@80 {
300 compatible = "fsl,ssi-dma-channel"; 300 compatible = "fsl,ssi-dma-channel";
301 reg = <0x80 0x80>; 301 reg = <0x80 0x80>;
302 cell-index = <1>; 302 cell-index = <1>;
303 interrupts = <77 2>; 303 interrupts = <77 2 0 0>;
304 }; 304 };
305 dma-channel@100 { 305 dma-channel@100 {
306 compatible = "fsl,eloplus-dma-channel"; 306 compatible = "fsl,eloplus-dma-channel";
307 reg = <0x100 0x80>; 307 reg = <0x100 0x80>;
308 cell-index = <2>; 308 cell-index = <2>;
309 interrupts = <78 2>; 309 interrupts = <78 2 0 0>;
310 }; 310 };
311 dma-channel@180 { 311 dma-channel@180 {
312 compatible = "fsl,eloplus-dma-channel"; 312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x180 0x80>; 313 reg = <0x180 0x80>;
314 cell-index = <3>; 314 cell-index = <3>;
315 interrupts = <79 2>; 315 interrupts = <79 2 0 0>;
316 }; 316 };
317 }; 317 };
318 318
@@ -320,7 +320,7 @@
320 #gpio-cells = <2>; 320 #gpio-cells = <2>;
321 compatible = "fsl,mpc8572-gpio"; 321 compatible = "fsl,mpc8572-gpio";
322 reg = <0xf000 0x100>; 322 reg = <0xf000 0x100>;
323 interrupts = <47 0x2>; 323 interrupts = <47 0x2 0 0>;
324 gpio-controller; 324 gpio-controller;
325 }; 325 };
326 326
@@ -329,7 +329,7 @@
329 reg = <0x20000 0x1000>; 329 reg = <0x20000 0x1000>;
330 cache-line-size = <32>; // 32 bytes 330 cache-line-size = <32>; // 32 bytes
331 cache-size = <0x40000>; // L2, 256K 331 cache-size = <0x40000>; // L2, 256K
332 interrupts = <16 2>; 332 interrupts = <16 2 0 0>;
333 }; 333 };
334 334
335 dma@21300 { 335 dma@21300 {
@@ -343,25 +343,25 @@
343 compatible = "fsl,eloplus-dma-channel"; 343 compatible = "fsl,eloplus-dma-channel";
344 reg = <0x0 0x80>; 344 reg = <0x0 0x80>;
345 cell-index = <0>; 345 cell-index = <0>;
346 interrupts = <20 2>; 346 interrupts = <20 2 0 0>;
347 }; 347 };
348 dma-channel@80 { 348 dma-channel@80 {
349 compatible = "fsl,eloplus-dma-channel"; 349 compatible = "fsl,eloplus-dma-channel";
350 reg = <0x80 0x80>; 350 reg = <0x80 0x80>;
351 cell-index = <1>; 351 cell-index = <1>;
352 interrupts = <21 2>; 352 interrupts = <21 2 0 0>;
353 }; 353 };
354 dma-channel@100 { 354 dma-channel@100 {
355 compatible = "fsl,eloplus-dma-channel"; 355 compatible = "fsl,eloplus-dma-channel";
356 reg = <0x100 0x80>; 356 reg = <0x100 0x80>;
357 cell-index = <2>; 357 cell-index = <2>;
358 interrupts = <22 2>; 358 interrupts = <22 2 0 0>;
359 }; 359 };
360 dma-channel@180 { 360 dma-channel@180 {
361 compatible = "fsl,eloplus-dma-channel"; 361 compatible = "fsl,eloplus-dma-channel";
362 reg = <0x180 0x80>; 362 reg = <0x180 0x80>;
363 cell-index = <3>; 363 cell-index = <3>;
364 interrupts = <23 2>; 364 interrupts = <23 2 0 0>;
365 }; 365 };
366 }; 366 };
367 367
@@ -370,7 +370,7 @@
370 #size-cells = <0>; 370 #size-cells = <0>;
371 compatible = "fsl-usb2-dr"; 371 compatible = "fsl-usb2-dr";
372 reg = <0x22000 0x1000>; 372 reg = <0x22000 0x1000>;
373 interrupts = <28 0x2>; 373 interrupts = <28 0x2 0 0>;
374 phy_type = "ulpi"; 374 phy_type = "ulpi";
375 }; 375 };
376 376
@@ -381,11 +381,11 @@
381 reg = <0x24000 0x1000 0xb0030 0x4>; 381 reg = <0x24000 0x1000 0xb0030 0x4>;
382 382
383 phy0: ethernet-phy@0 { 383 phy0: ethernet-phy@0 {
384 interrupts = <3 1>; 384 interrupts = <3 1 0 0>;
385 reg = <0x1>; 385 reg = <0x1>;
386 }; 386 };
387 phy1: ethernet-phy@1 { 387 phy1: ethernet-phy@1 {
388 interrupts = <9 1>; 388 interrupts = <9 1 0 0>;
389 reg = <0x2>; 389 reg = <0x2>;
390 }; 390 };
391 }; 391 };
@@ -416,13 +416,13 @@
416 #address-cells = <1>; 416 #address-cells = <1>;
417 #size-cells = <1>; 417 #size-cells = <1>;
418 reg = <0xB0000 0x1000>; 418 reg = <0xB0000 0x1000>;
419 interrupts = <29 2 30 2 34 2>; 419 interrupts = <29 2 0 0 30 2 0 0 34 2 0 0>;
420 }; 420 };
421 queue-group@1{ 421 queue-group@1{
422 #address-cells = <1>; 422 #address-cells = <1>;
423 #size-cells = <1>; 423 #size-cells = <1>;
424 reg = <0xB4000 0x1000>; 424 reg = <0xB4000 0x1000>;
425 interrupts = <17 2 18 2 24 2>; 425 interrupts = <17 2 0 0 18 2 0 0 24 2 0 0>;
426 }; 426 };
427 }; 427 };
428 428
@@ -443,20 +443,20 @@
443 #address-cells = <1>; 443 #address-cells = <1>;
444 #size-cells = <1>; 444 #size-cells = <1>;
445 reg = <0xB1000 0x1000>; 445 reg = <0xB1000 0x1000>;
446 interrupts = <35 2 36 2 40 2>; 446 interrupts = <35 2 0 0 36 2 0 0 40 2 0 0>;
447 }; 447 };
448 queue-group@1{ 448 queue-group@1{
449 #address-cells = <1>; 449 #address-cells = <1>;
450 #size-cells = <1>; 450 #size-cells = <1>;
451 reg = <0xB5000 0x1000>; 451 reg = <0xB5000 0x1000>;
452 interrupts = <51 2 52 2 67 2>; 452 interrupts = <51 2 0 0 52 2 0 0 67 2 0 0>;
453 }; 453 };
454 }; 454 };
455 455
456 sdhci@2e000 { 456 sdhci@2e000 {
457 compatible = "fsl,p1022-esdhc", "fsl,esdhc"; 457 compatible = "fsl,p1022-esdhc", "fsl,esdhc";
458 reg = <0x2e000 0x1000>; 458 reg = <0x2e000 0x1000>;
459 interrupts = <72 0x2>; 459 interrupts = <72 0x2 0 0>;
460 fsl,sdhci-auto-cmd12; 460 fsl,sdhci-auto-cmd12;
461 /* Filled in by U-Boot */ 461 /* Filled in by U-Boot */
462 clock-frequency = <0>; 462 clock-frequency = <0>;
@@ -467,7 +467,7 @@
467 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1", 467 "fsl,sec2.4", "fsl,sec2.2", "fsl,sec2.1",
468 "fsl,sec2.0"; 468 "fsl,sec2.0";
469 reg = <0x30000 0x10000>; 469 reg = <0x30000 0x10000>;
470 interrupts = <45 2 58 2>; 470 interrupts = <45 2 0 0 58 2 0 0>;
471 fsl,num-channels = <4>; 471 fsl,num-channels = <4>;
472 fsl,channel-fifo-len = <24>; 472 fsl,channel-fifo-len = <24>;
473 fsl,exec-units-mask = <0x97c>; 473 fsl,exec-units-mask = <0x97c>;
@@ -478,14 +478,14 @@
478 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2"; 478 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
479 reg = <0x18000 0x1000>; 479 reg = <0x18000 0x1000>;
480 cell-index = <1>; 480 cell-index = <1>;
481 interrupts = <74 0x2>; 481 interrupts = <74 0x2 0 0>;
482 }; 482 };
483 483
484 sata@19000 { 484 sata@19000 {
485 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2"; 485 compatible = "fsl,p1022-sata", "fsl,pq-sata-v2";
486 reg = <0x19000 0x1000>; 486 reg = <0x19000 0x1000>;
487 cell-index = <2>; 487 cell-index = <2>;
488 interrupts = <41 0x2>; 488 interrupts = <41 0x2 0 0>;
489 }; 489 };
490 490
491 power@e0070{ 491 power@e0070{
@@ -496,21 +496,33 @@
496 display@10000 { 496 display@10000 {
497 compatible = "fsl,diu", "fsl,p1022-diu"; 497 compatible = "fsl,diu", "fsl,p1022-diu";
498 reg = <0x10000 1000>; 498 reg = <0x10000 1000>;
499 interrupts = <64 2>; 499 interrupts = <64 2 0 0>;
500 }; 500 };
501 501
502 timer@41100 { 502 timer@41100 {
503 compatible = "fsl,mpic-global-timer"; 503 compatible = "fsl,mpic-global-timer";
504 reg = <0x41100 0x204>; 504 reg = <0x41100 0x100 0x41300 4>;
505 interrupts = <0xf7 0x2>; 505 interrupts = <0 0 3 0
506 1 0 3 0
507 2 0 3 0
508 3 0 3 0>;
509 };
510
511 timer@42100 {
512 compatible = "fsl,mpic-global-timer";
513 reg = <0x42100 0x100 0x42300 4>;
514 interrupts = <4 0 3 0
515 5 0 3 0
516 6 0 3 0
517 7 0 3 0>;
506 }; 518 };
507 519
508 mpic: pic@40000 { 520 mpic: pic@40000 {
509 interrupt-controller; 521 interrupt-controller;
510 #address-cells = <0>; 522 #address-cells = <0>;
511 #interrupt-cells = <2>; 523 #interrupt-cells = <4>;
512 reg = <0x40000 0x40000>; 524 reg = <0x40000 0x40000>;
513 compatible = "chrp,open-pic"; 525 compatible = "fsl,mpic";
514 device_type = "open-pic"; 526 device_type = "open-pic";
515 }; 527 };
516 528
@@ -519,14 +531,14 @@
519 reg = <0x41600 0x80>; 531 reg = <0x41600 0x80>;
520 msi-available-ranges = <0 0x100>; 532 msi-available-ranges = <0 0x100>;
521 interrupts = < 533 interrupts = <
522 0xe0 0 534 0xe0 0 0 0
523 0xe1 0 535 0xe1 0 0 0
524 0xe2 0 536 0xe2 0 0 0
525 0xe3 0 537 0xe3 0 0 0
526 0xe4 0 538 0xe4 0 0 0
527 0xe5 0 539 0xe5 0 0 0
528 0xe6 0 540 0xe6 0 0 0
529 0xe7 0>; 541 0xe7 0 0 0>;
530 }; 542 };
531 543
532 global-utilities@e0000 { //global utilities block 544 global-utilities@e0000 { //global utilities block
@@ -547,7 +559,7 @@
547 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000 559 ranges = <0x2000000 0x0 0xa0000000 0xc 0x20000000 0x0 0x20000000
548 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>; 560 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
549 clock-frequency = <33333333>; 561 clock-frequency = <33333333>;
550 interrupts = <16 2>; 562 interrupts = <16 2 0 0>;
551 interrupt-map-mask = <0xf800 0 0 7>; 563 interrupt-map-mask = <0xf800 0 0 7>;
552 interrupt-map = < 564 interrupt-map = <
553 /* IDSEL 0x0 */ 565 /* IDSEL 0x0 */
@@ -582,7 +594,7 @@
582 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000 594 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
583 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>; 595 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x10000>;
584 clock-frequency = <33333333>; 596 clock-frequency = <33333333>;
585 interrupts = <16 2>; 597 interrupts = <16 2 0 0>;
586 interrupt-map-mask = <0xf800 0 0 7>; 598 interrupt-map-mask = <0xf800 0 0 7>;
587 interrupt-map = < 599 interrupt-map = <
588 /* IDSEL 0x0 */ 600 /* IDSEL 0x0 */
@@ -618,7 +630,7 @@
618 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000 630 ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
619 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>; 631 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
620 clock-frequency = <33333333>; 632 clock-frequency = <33333333>;
621 interrupts = <16 2>; 633 interrupts = <16 2 0 0>;
622 interrupt-map-mask = <0xf800 0 0 7>; 634 interrupt-map-mask = <0xf800 0 0 7>;
623 interrupt-map = < 635 interrupt-map = <
624 /* IDSEL 0x0 */ 636 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 11019142813c..2bcf3683d223 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -1,7 +1,7 @@
1/* 1/*
2 * P2020 DS Device Tree Source 2 * P2020 DS Device Tree Source
3 * 3 *
4 * Copyright 2009 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p2020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P2020"; 15 model = "fsl,P2020DS";
15 compatible = "fsl,P2020DS"; 16 compatible = "fsl,P2020DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -27,35 +26,13 @@
27 pci2 = &pci2; 26 pci2 = &pci2;
28 }; 27 };
29 28
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33
34 PowerPC,P2020@0 {
35 device_type = "cpu";
36 reg = <0x0>;
37 next-level-cache = <&L2>;
38 };
39
40 PowerPC,P2020@1 {
41 device_type = "cpu";
42 reg = <0x1>;
43 next-level-cache = <&L2>;
44 };
45 };
46 29
47 memory { 30 memory {
48 device_type = "memory"; 31 device_type = "memory";
49 }; 32 };
50 33
51 localbus@ffe05000 { 34 localbus@ffe05000 {
52 #address-cells = <2>;
53 #size-cells = <1>;
54 compatible = "fsl,elbc", "simple-bus"; 35 compatible = "fsl,elbc", "simple-bus";
55 reg = <0 0xffe05000 0 0x1000>;
56 interrupts = <19 2>;
57 interrupt-parent = <&mpic>;
58
59 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000 36 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
60 0x1 0x0 0x0 0xe0000000 0x08000000 37 0x1 0x0 0x0 0xe0000000 0x08000000
61 0x2 0x0 0x0 0xffa00000 0x00040000 38 0x2 0x0 0x0 0xffa00000 0x00040000
@@ -158,352 +135,77 @@
158 }; 135 };
159 136
160 soc@ffe00000 { 137 soc@ffe00000 {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 device_type = "soc";
164 compatible = "fsl,p2020-immr", "simple-bus";
165 ranges = <0x0 0 0xffe00000 0x100000>;
166 bus-frequency = <0>; // Filled out by uboot.
167
168 ecm-law@0 {
169 compatible = "fsl,ecm-law";
170 reg = <0x0 0x1000>;
171 fsl,num-laws = <12>;
172 };
173
174 ecm@1000 {
175 compatible = "fsl,p2020-ecm", "fsl,ecm";
176 reg = <0x1000 0x1000>;
177 interrupts = <17 2>;
178 interrupt-parent = <&mpic>;
179 };
180
181 memory-controller@2000 {
182 compatible = "fsl,p2020-memory-controller";
183 reg = <0x2000 0x1000>;
184 interrupt-parent = <&mpic>;
185 interrupts = <18 2>;
186 };
187
188 i2c@3000 {
189 #address-cells = <1>;
190 #size-cells = <0>;
191 cell-index = <0>;
192 compatible = "fsl-i2c";
193 reg = <0x3000 0x100>;
194 interrupts = <43 2>;
195 interrupt-parent = <&mpic>;
196 dfsrr;
197 };
198
199 i2c@3100 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 cell-index = <1>;
203 compatible = "fsl-i2c";
204 reg = <0x3100 0x100>;
205 interrupts = <43 2>;
206 interrupt-parent = <&mpic>;
207 dfsrr;
208 };
209 138
210 serial0: serial@4500 { 139 usb@22000 {
211 cell-index = <0>; 140 phy_type = "ulpi";
212 device_type = "serial";
213 compatible = "ns16550";
214 reg = <0x4500 0x100>;
215 clock-frequency = <0>;
216 interrupts = <42 2>;
217 interrupt-parent = <&mpic>;
218 };
219
220 serial1: serial@4600 {
221 cell-index = <1>;
222 device_type = "serial";
223 compatible = "ns16550";
224 reg = <0x4600 0x100>;
225 clock-frequency = <0>;
226 interrupts = <42 2>;
227 interrupt-parent = <&mpic>;
228 };
229
230 spi@7000 {
231 compatible = "fsl,espi";
232 reg = <0x7000 0x1000>;
233 interrupts = <59 0x2>;
234 interrupt-parent = <&mpic>;
235 }; 141 };
236 142
237 dma@c300 { 143 mdio@24520 {
238 #address-cells = <1>; 144 phy0: ethernet-phy@0 {
239 #size-cells = <1>;
240 compatible = "fsl,eloplus-dma";
241 reg = <0xc300 0x4>;
242 ranges = <0x0 0xc100 0x200>;
243 cell-index = <1>;
244 dma-channel@0 {
245 compatible = "fsl,eloplus-dma-channel";
246 reg = <0x0 0x80>;
247 cell-index = <0>;
248 interrupt-parent = <&mpic>; 145 interrupt-parent = <&mpic>;
249 interrupts = <76 2>; 146 interrupts = <3 1>;
147 reg = <0x0>;
250 }; 148 };
251 dma-channel@80 { 149 phy1: ethernet-phy@1 {
252 compatible = "fsl,eloplus-dma-channel";
253 reg = <0x80 0x80>;
254 cell-index = <1>;
255 interrupt-parent = <&mpic>; 150 interrupt-parent = <&mpic>;
256 interrupts = <77 2>; 151 interrupts = <3 1>;
152 reg = <0x1>;
257 }; 153 };
258 dma-channel@100 { 154 phy2: ethernet-phy@2 {
259 compatible = "fsl,eloplus-dma-channel";
260 reg = <0x100 0x80>;
261 cell-index = <2>;
262 interrupt-parent = <&mpic>; 155 interrupt-parent = <&mpic>;
263 interrupts = <78 2>; 156 interrupts = <3 1>;
157 reg = <0x2>;
264 }; 158 };
265 dma-channel@180 { 159 tbi0: tbi-phy@11 {
266 compatible = "fsl,eloplus-dma-channel"; 160 reg = <0x11>;
267 reg = <0x180 0x80>; 161 device_type = "tbi-phy";
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 }; 162 };
272 };
273 163
274 gpio: gpio-controller@f000 {
275 #gpio-cells = <2>;
276 compatible = "fsl,mpc8572-gpio";
277 reg = <0xf000 0x100>;
278 interrupts = <47 0x2>;
279 interrupt-parent = <&mpic>;
280 gpio-controller;
281 }; 164 };
282 165
283 L2: l2-cache-controller@20000 { 166 mdio@25520 {
284 compatible = "fsl,p2020-l2-cache-controller"; 167 tbi1: tbi-phy@11 {
285 reg = <0x20000 0x1000>; 168 reg = <0x11>;
286 cache-line-size = <32>; // 32 bytes 169 device_type = "tbi-phy";
287 cache-size = <0x80000>; // L2, 512k 170 };
288 interrupt-parent = <&mpic>;
289 interrupts = <16 2>;
290 }; 171 };
291 172
292 dma@21300 { 173 mdio@26520 {
293 #address-cells = <1>; 174 tbi2: tbi-phy@11 {
294 #size-cells = <1>; 175 reg = <0x11>;
295 compatible = "fsl,eloplus-dma"; 176 device_type = "tbi-phy";
296 reg = <0x21300 0x4>;
297 ranges = <0x0 0x21100 0x200>;
298 cell-index = <0>;
299 dma-channel@0 {
300 compatible = "fsl,eloplus-dma-channel";
301 reg = <0x0 0x80>;
302 cell-index = <0>;
303 interrupt-parent = <&mpic>;
304 interrupts = <20 2>;
305 };
306 dma-channel@80 {
307 compatible = "fsl,eloplus-dma-channel";
308 reg = <0x80 0x80>;
309 cell-index = <1>;
310 interrupt-parent = <&mpic>;
311 interrupts = <21 2>;
312 }; 177 };
313 dma-channel@100 {
314 compatible = "fsl,eloplus-dma-channel";
315 reg = <0x100 0x80>;
316 cell-index = <2>;
317 interrupt-parent = <&mpic>;
318 interrupts = <22 2>;
319 };
320 dma-channel@180 {
321 compatible = "fsl,eloplus-dma-channel";
322 reg = <0x180 0x80>;
323 cell-index = <3>;
324 interrupt-parent = <&mpic>;
325 interrupts = <23 2>;
326 };
327 };
328 178
329 usb@22000 {
330 #address-cells = <1>;
331 #size-cells = <0>;
332 compatible = "fsl-usb2-dr";
333 reg = <0x22000 0x1000>;
334 interrupt-parent = <&mpic>;
335 interrupts = <28 0x2>;
336 phy_type = "ulpi";
337 }; 179 };
338 180
339 enet0: ethernet@24000 { 181 enet0: ethernet@24000 {
340 #address-cells = <1>;
341 #size-cells = <1>;
342 cell-index = <0>;
343 device_type = "network";
344 model = "eTSEC";
345 compatible = "gianfar";
346 reg = <0x24000 0x1000>;
347 ranges = <0x0 0x24000 0x1000>;
348 local-mac-address = [ 00 00 00 00 00 00 ];
349 interrupts = <29 2 30 2 34 2>;
350 interrupt-parent = <&mpic>;
351 tbi-handle = <&tbi0>; 182 tbi-handle = <&tbi0>;
352 phy-handle = <&phy0>; 183 phy-handle = <&phy0>;
353 phy-connection-type = "rgmii-id"; 184 phy-connection-type = "rgmii-id";
354
355 mdio@520 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "fsl,gianfar-mdio";
359 reg = <0x520 0x20>;
360
361 phy0: ethernet-phy@0 {
362 interrupt-parent = <&mpic>;
363 interrupts = <3 1>;
364 reg = <0x0>;
365 };
366 phy1: ethernet-phy@1 {
367 interrupt-parent = <&mpic>;
368 interrupts = <3 1>;
369 reg = <0x1>;
370 };
371 phy2: ethernet-phy@2 {
372 interrupt-parent = <&mpic>;
373 interrupts = <3 1>;
374 reg = <0x2>;
375 };
376 tbi0: tbi-phy@11 {
377 reg = <0x11>;
378 device_type = "tbi-phy";
379 };
380 };
381 }; 185 };
382 186
383 enet1: ethernet@25000 { 187 enet1: ethernet@25000 {
384 #address-cells = <1>;
385 #size-cells = <1>;
386 cell-index = <1>;
387 device_type = "network";
388 model = "eTSEC";
389 compatible = "gianfar";
390 reg = <0x25000 0x1000>;
391 ranges = <0x0 0x25000 0x1000>;
392 local-mac-address = [ 00 00 00 00 00 00 ];
393 interrupts = <35 2 36 2 40 2>;
394 interrupt-parent = <&mpic>;
395 tbi-handle = <&tbi1>; 188 tbi-handle = <&tbi1>;
396 phy-handle = <&phy1>; 189 phy-handle = <&phy1>;
397 phy-connection-type = "rgmii-id"; 190 phy-connection-type = "rgmii-id";
398 191
399 mdio@520 {
400 #address-cells = <1>;
401 #size-cells = <0>;
402 compatible = "fsl,gianfar-tbi";
403 reg = <0x520 0x20>;
404
405 tbi1: tbi-phy@11 {
406 reg = <0x11>;
407 device_type = "tbi-phy";
408 };
409 };
410 }; 192 };
411 193
412 enet2: ethernet@26000 { 194 enet2: ethernet@26000 {
413 #address-cells = <1>;
414 #size-cells = <1>;
415 cell-index = <2>;
416 device_type = "network";
417 model = "eTSEC";
418 compatible = "gianfar";
419 reg = <0x26000 0x1000>;
420 ranges = <0x0 0x26000 0x1000>;
421 local-mac-address = [ 00 00 00 00 00 00 ];
422 interrupts = <31 2 32 2 33 2>;
423 interrupt-parent = <&mpic>;
424 tbi-handle = <&tbi2>; 195 tbi-handle = <&tbi2>;
425 phy-handle = <&phy2>; 196 phy-handle = <&phy2>;
426 phy-connection-type = "rgmii-id"; 197 phy-connection-type = "rgmii-id";
427
428 mdio@520 {
429 #address-cells = <1>;
430 #size-cells = <0>;
431 compatible = "fsl,gianfar-tbi";
432 reg = <0x520 0x20>;
433
434 tbi2: tbi-phy@11 {
435 reg = <0x11>;
436 device_type = "tbi-phy";
437 };
438 };
439 };
440
441 sdhci@2e000 {
442 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
443 reg = <0x2e000 0x1000>;
444 interrupts = <72 0x2>;
445 interrupt-parent = <&mpic>;
446 /* Filled in by U-Boot */
447 clock-frequency = <0>;
448 };
449
450 crypto@30000 {
451 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
452 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
453 reg = <0x30000 0x10000>;
454 interrupts = <45 2 58 2>;
455 interrupt-parent = <&mpic>;
456 fsl,num-channels = <4>;
457 fsl,channel-fifo-len = <24>;
458 fsl,exec-units-mask = <0xbfe>;
459 fsl,descriptor-types-mask = <0x3ab0ebf>;
460 }; 198 };
461 199
462 mpic: pic@40000 {
463 interrupt-controller;
464 #address-cells = <0>;
465 #interrupt-cells = <2>;
466 reg = <0x40000 0x40000>;
467 compatible = "chrp,open-pic";
468 device_type = "open-pic";
469 };
470 200
471 msi@41600 { 201 msi@41600 {
472 compatible = "fsl,mpic-msi"; 202 compatible = "fsl,mpic-msi";
473 reg = <0x41600 0x80>;
474 msi-available-ranges = <0 0x100>;
475 interrupts = <
476 0xe0 0
477 0xe1 0
478 0xe2 0
479 0xe3 0
480 0xe4 0
481 0xe5 0
482 0xe6 0
483 0xe7 0>;
484 interrupt-parent = <&mpic>;
485 };
486
487 global-utilities@e0000 { //global utilities block
488 compatible = "fsl,p2020-guts";
489 reg = <0xe0000 0x1000>;
490 fsl,has-rstcr;
491 }; 203 };
492 }; 204 };
493 205
494 pci0: pcie@ffe08000 { 206 pci0: pcie@ffe08000 {
495 compatible = "fsl,mpc8548-pcie";
496 device_type = "pci";
497 #interrupt-cells = <1>;
498 #size-cells = <2>;
499 #address-cells = <3>;
500 reg = <0 0xffe08000 0 0x1000>;
501 bus-range = <0 255>;
502 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 207 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
503 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 208 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
504 clock-frequency = <33333333>;
505 interrupt-parent = <&mpic>;
506 interrupts = <24 2>;
507 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 209 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
508 interrupt-map = < 210 interrupt-map = <
509 /* IDSEL 0x0 */ 211 /* IDSEL 0x0 */
@@ -528,18 +230,8 @@
528 }; 230 };
529 231
530 pci1: pcie@ffe09000 { 232 pci1: pcie@ffe09000 {
531 compatible = "fsl,mpc8548-pcie";
532 device_type = "pci";
533 #interrupt-cells = <1>;
534 #size-cells = <2>;
535 #address-cells = <3>;
536 reg = <0 0xffe09000 0 0x1000>;
537 bus-range = <0 255>;
538 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 233 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
539 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 234 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
540 clock-frequency = <33333333>;
541 interrupt-parent = <&mpic>;
542 interrupts = <25 2>;
543 interrupt-map-mask = <0xff00 0x0 0x0 0x7>; 235 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
544 interrupt-map = < 236 interrupt-map = <
545 237
@@ -667,18 +359,8 @@
667 }; 359 };
668 360
669 pci2: pcie@ffe0a000 { 361 pci2: pcie@ffe0a000 {
670 compatible = "fsl,mpc8548-pcie";
671 device_type = "pci";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xffe0a000 0 0x1000>;
676 bus-range = <0 255>;
677 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 362 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
678 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 363 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
681 interrupts = <26 2>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 364 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
683 interrupt-map = < 365 interrupt-map = <
684 /* IDSEL 0x0 */ 366 /* IDSEL 0x0 */
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index e2d48fd4416e..3782a58f13be 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -9,12 +9,11 @@
9 * option) any later version. 9 * option) any later version.
10 */ 10 */
11 11
12/dts-v1/; 12/include/ "p2020si.dtsi"
13
13/ { 14/ {
14 model = "fsl,P2020"; 15 model = "fsl,P2020RDB";
15 compatible = "fsl,P2020RDB"; 16 compatible = "fsl,P2020RDB";
16 #address-cells = <2>;
17 #size-cells = <2>;
18 17
19 aliases { 18 aliases {
20 ethernet0 = &enet0; 19 ethernet0 = &enet0;
@@ -26,34 +25,11 @@
26 pci1 = &pci1; 25 pci1 = &pci1;
27 }; 26 };
28 27
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,P2020@0 {
34 device_type = "cpu";
35 reg = <0x0>;
36 next-level-cache = <&L2>;
37 };
38
39 PowerPC,P2020@1 {
40 device_type = "cpu";
41 reg = <0x1>;
42 next-level-cache = <&L2>;
43 };
44 };
45
46 memory { 28 memory {
47 device_type = "memory"; 29 device_type = "memory";
48 }; 30 };
49 31
50 localbus@ffe05000 { 32 localbus@ffe05000 {
51 #address-cells = <2>;
52 #size-cells = <1>;
53 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
54 reg = <0 0xffe05000 0 0x1000>;
55 interrupts = <19 2>;
56 interrupt-parent = <&mpic>;
57 33
58 /* NOR and NAND Flashes */ 34 /* NOR and NAND Flashes */
59 ranges = <0x0 0x0 0x0 0xef000000 0x01000000 35 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
@@ -165,90 +141,16 @@
165 }; 141 };
166 142
167 soc@ffe00000 { 143 soc@ffe00000 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "fsl,p2020-immr", "simple-bus";
172 ranges = <0x0 0x0 0xffe00000 0x100000>;
173 bus-frequency = <0>; // Filled out by uboot.
174
175 ecm-law@0 {
176 compatible = "fsl,ecm-law";
177 reg = <0x0 0x1000>;
178 fsl,num-laws = <12>;
179 };
180
181 ecm@1000 {
182 compatible = "fsl,p2020-ecm", "fsl,ecm";
183 reg = <0x1000 0x1000>;
184 interrupts = <17 2>;
185 interrupt-parent = <&mpic>;
186 };
187
188 memory-controller@2000 {
189 compatible = "fsl,p2020-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
194
195 i2c@3000 { 144 i2c@3000 {
196 #address-cells = <1>;
197 #size-cells = <0>;
198 cell-index = <0>;
199 compatible = "fsl-i2c";
200 reg = <0x3000 0x100>;
201 interrupts = <43 2>;
202 interrupt-parent = <&mpic>;
203 dfsrr;
204 rtc@68 { 145 rtc@68 {
205 compatible = "dallas,ds1339"; 146 compatible = "dallas,ds1339";
206 reg = <0x68>; 147 reg = <0x68>;
207 }; 148 };
208 }; 149 };
209 150
210 i2c@3100 { 151 spi@7000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 cell-index = <1>;
214 compatible = "fsl-i2c";
215 reg = <0x3100 0x100>;
216 interrupts = <43 2>;
217 interrupt-parent = <&mpic>;
218 dfsrr;
219 };
220
221 serial0: serial@4500 {
222 cell-index = <0>;
223 device_type = "serial";
224 compatible = "ns16550";
225 reg = <0x4500 0x100>;
226 clock-frequency = <0>;
227 interrupts = <42 2>;
228 interrupt-parent = <&mpic>;
229 };
230
231 serial1: serial@4600 {
232 cell-index = <1>;
233 device_type = "serial";
234 compatible = "ns16550";
235 reg = <0x4600 0x100>;
236 clock-frequency = <0>;
237 interrupts = <42 2>;
238 interrupt-parent = <&mpic>;
239 };
240 152
241 spi@7000 { 153 fsl_m25p80@0 {
242 cell-index = <0>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "fsl,espi";
246 reg = <0x7000 0x1000>;
247 interrupts = <59 0x2>;
248 interrupt-parent = <&mpic>;
249 mode = "cpu";
250
251 fsl_m25p80@0 {
252 #address-cells = <1>; 154 #address-cells = <1>;
253 #size-cells = <1>; 155 #size-cells = <1>;
254 compatible = "fsl,espi-flash"; 156 compatible = "fsl,espi-flash";
@@ -294,254 +196,68 @@
294 }; 196 };
295 }; 197 };
296 198
297 dma@c300 { 199 usb@22000 {
298 #address-cells = <1>; 200 phy_type = "ulpi";
299 #size-cells = <1>;
300 compatible = "fsl,eloplus-dma";
301 reg = <0xc300 0x4>;
302 ranges = <0x0 0xc100 0x200>;
303 cell-index = <1>;
304 dma-channel@0 {
305 compatible = "fsl,eloplus-dma-channel";
306 reg = <0x0 0x80>;
307 cell-index = <0>;
308 interrupt-parent = <&mpic>;
309 interrupts = <76 2>;
310 };
311 dma-channel@80 {
312 compatible = "fsl,eloplus-dma-channel";
313 reg = <0x80 0x80>;
314 cell-index = <1>;
315 interrupt-parent = <&mpic>;
316 interrupts = <77 2>;
317 };
318 dma-channel@100 {
319 compatible = "fsl,eloplus-dma-channel";
320 reg = <0x100 0x80>;
321 cell-index = <2>;
322 interrupt-parent = <&mpic>;
323 interrupts = <78 2>;
324 };
325 dma-channel@180 {
326 compatible = "fsl,eloplus-dma-channel";
327 reg = <0x180 0x80>;
328 cell-index = <3>;
329 interrupt-parent = <&mpic>;
330 interrupts = <79 2>;
331 };
332 };
333
334 gpio: gpio-controller@f000 {
335 #gpio-cells = <2>;
336 compatible = "fsl,mpc8572-gpio";
337 reg = <0xf000 0x100>;
338 interrupts = <47 0x2>;
339 interrupt-parent = <&mpic>;
340 gpio-controller;
341 };
342
343 L2: l2-cache-controller@20000 {
344 compatible = "fsl,p2020-l2-cache-controller";
345 reg = <0x20000 0x1000>;
346 cache-line-size = <32>; // 32 bytes
347 cache-size = <0x80000>; // L2,512K
348 interrupt-parent = <&mpic>;
349 interrupts = <16 2>;
350 }; 201 };
351 202
352 dma@21300 { 203 mdio@24520 {
353 #address-cells = <1>; 204 phy0: ethernet-phy@0 {
354 #size-cells = <1>;
355 compatible = "fsl,eloplus-dma";
356 reg = <0x21300 0x4>;
357 ranges = <0x0 0x21100 0x200>;
358 cell-index = <0>;
359 dma-channel@0 {
360 compatible = "fsl,eloplus-dma-channel";
361 reg = <0x0 0x80>;
362 cell-index = <0>;
363 interrupt-parent = <&mpic>; 205 interrupt-parent = <&mpic>;
364 interrupts = <20 2>; 206 interrupts = <3 1>;
365 }; 207 reg = <0x0>;
366 dma-channel@80 { 208 };
367 compatible = "fsl,eloplus-dma-channel"; 209 phy1: ethernet-phy@1 {
368 reg = <0x80 0x80>;
369 cell-index = <1>;
370 interrupt-parent = <&mpic>;
371 interrupts = <21 2>;
372 };
373 dma-channel@100 {
374 compatible = "fsl,eloplus-dma-channel";
375 reg = <0x100 0x80>;
376 cell-index = <2>;
377 interrupt-parent = <&mpic>;
378 interrupts = <22 2>;
379 };
380 dma-channel@180 {
381 compatible = "fsl,eloplus-dma-channel";
382 reg = <0x180 0x80>;
383 cell-index = <3>;
384 interrupt-parent = <&mpic>; 210 interrupt-parent = <&mpic>;
385 interrupts = <23 2>; 211 interrupts = <3 1>;
212 reg = <0x1>;
213 };
214 };
215
216 mdio@25520 {
217 tbi0: tbi-phy@11 {
218 reg = <0x11>;
219 device_type = "tbi-phy";
386 }; 220 };
387 }; 221 };
388 222
389 usb@22000 { 223 mdio@26520 {
390 #address-cells = <1>; 224 status = "disabled";
391 #size-cells = <0>;
392 compatible = "fsl-usb2-dr";
393 reg = <0x22000 0x1000>;
394 interrupt-parent = <&mpic>;
395 interrupts = <28 0x2>;
396 phy_type = "ulpi";
397 }; 225 };
398 226
399 enet0: ethernet@24000 { 227 enet0: ethernet@24000 {
400 #address-cells = <1>;
401 #size-cells = <1>;
402 cell-index = <0>;
403 device_type = "network";
404 model = "eTSEC";
405 compatible = "gianfar";
406 reg = <0x24000 0x1000>;
407 ranges = <0x0 0x24000 0x1000>;
408 local-mac-address = [ 00 00 00 00 00 00 ];
409 interrupts = <29 2 30 2 34 2>;
410 interrupt-parent = <&mpic>;
411 fixed-link = <1 1 1000 0 0>; 228 fixed-link = <1 1 1000 0 0>;
412 phy-connection-type = "rgmii-id"; 229 phy-connection-type = "rgmii-id";
413
414 mdio@520 {
415 #address-cells = <1>;
416 #size-cells = <0>;
417 compatible = "fsl,gianfar-mdio";
418 reg = <0x520 0x20>;
419
420 phy0: ethernet-phy@0 {
421 interrupt-parent = <&mpic>;
422 interrupts = <3 1>;
423 reg = <0x0>;
424 };
425 phy1: ethernet-phy@1 {
426 interrupt-parent = <&mpic>;
427 interrupts = <3 1>;
428 reg = <0x1>;
429 };
430 };
431 }; 230 };
432 231
433 enet1: ethernet@25000 { 232 enet1: ethernet@25000 {
434 #address-cells = <1>;
435 #size-cells = <1>;
436 cell-index = <1>;
437 device_type = "network";
438 model = "eTSEC";
439 compatible = "gianfar";
440 reg = <0x25000 0x1000>;
441 ranges = <0x0 0x25000 0x1000>;
442 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupts = <35 2 36 2 40 2>;
444 interrupt-parent = <&mpic>;
445 tbi-handle = <&tbi0>; 233 tbi-handle = <&tbi0>;
446 phy-handle = <&phy0>; 234 phy-handle = <&phy0>;
447 phy-connection-type = "sgmii"; 235 phy-connection-type = "sgmii";
448
449 mdio@520 {
450 #address-cells = <1>;
451 #size-cells = <0>;
452 compatible = "fsl,gianfar-tbi";
453 reg = <0x520 0x20>;
454
455 tbi0: tbi-phy@11 {
456 reg = <0x11>;
457 device_type = "tbi-phy";
458 };
459 };
460 }; 236 };
461 237
462 enet2: ethernet@26000 { 238 enet2: ethernet@26000 {
463 #address-cells = <1>;
464 #size-cells = <1>;
465 cell-index = <2>;
466 device_type = "network";
467 model = "eTSEC";
468 compatible = "gianfar";
469 reg = <0x26000 0x1000>;
470 ranges = <0x0 0x26000 0x1000>;
471 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupts = <31 2 32 2 33 2>;
473 interrupt-parent = <&mpic>;
474 phy-handle = <&phy1>; 239 phy-handle = <&phy1>;
475 phy-connection-type = "rgmii-id"; 240 phy-connection-type = "rgmii-id";
476 }; 241 };
477 242
478 sdhci@2e000 { 243 };
479 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
480 reg = <0x2e000 0x1000>;
481 interrupts = <72 0x2>;
482 interrupt-parent = <&mpic>;
483 /* Filled in by U-Boot */
484 clock-frequency = <0>;
485 };
486
487 crypto@30000 {
488 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
489 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
490 reg = <0x30000 0x10000>;
491 interrupts = <45 2 58 2>;
492 interrupt-parent = <&mpic>;
493 fsl,num-channels = <4>;
494 fsl,channel-fifo-len = <24>;
495 fsl,exec-units-mask = <0xbfe>;
496 fsl,descriptor-types-mask = <0x3ab0ebf>;
497 };
498
499 mpic: pic@40000 {
500 interrupt-controller;
501 #address-cells = <0>;
502 #interrupt-cells = <2>;
503 reg = <0x40000 0x40000>;
504 compatible = "chrp,open-pic";
505 device_type = "open-pic";
506 };
507
508 msi@41600 {
509 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
510 reg = <0x41600 0x80>;
511 msi-available-ranges = <0 0x100>;
512 interrupts = <
513 0xe0 0
514 0xe1 0
515 0xe2 0
516 0xe3 0
517 0xe4 0
518 0xe5 0
519 0xe6 0
520 0xe7 0>;
521 interrupt-parent = <&mpic>;
522 };
523 244
524 global-utilities@e0000 { //global utilities block 245 pci0: pcie@ffe08000 {
525 compatible = "fsl,p2020-guts"; 246 status = "disabled";
526 reg = <0xe0000 0x1000>;
527 fsl,has-rstcr;
528 };
529 }; 247 };
530 248
531 pci0: pcie@ffe09000 { 249 pci1: pcie@ffe09000 {
532 compatible = "fsl,mpc8548-pcie";
533 device_type = "pci";
534 #interrupt-cells = <1>;
535 #size-cells = <2>;
536 #address-cells = <3>;
537 reg = <0 0xffe09000 0 0x1000>;
538 bus-range = <0 255>;
539 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 250 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
540 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 251 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
541 clock-frequency = <33333333>; 252 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
542 interrupt-parent = <&mpic>; 253 interrupt-map = <
543 interrupts = <25 2>; 254 /* IDSEL 0x0 */
544 pcie@0 { 255 0000 0x0 0x0 0x1 &mpic 0x4 0x1
256 0000 0x0 0x0 0x2 &mpic 0x5 0x1
257 0000 0x0 0x0 0x3 &mpic 0x6 0x1
258 0000 0x0 0x0 0x4 &mpic 0x7 0x1
259 >;
260 pcie@0 {
545 reg = <0x0 0x0 0x0 0x0 0x0>; 261 reg = <0x0 0x0 0x0 0x0 0x0>;
546 #size-cells = <2>; 262 #size-cells = <2>;
547 #address-cells = <3>; 263 #address-cells = <3>;
@@ -556,19 +272,17 @@
556 }; 272 };
557 }; 273 };
558 274
559 pci1: pcie@ffe0a000 { 275 pci2: pcie@ffe0a000 {
560 compatible = "fsl,mpc8548-pcie";
561 device_type = "pci";
562 #interrupt-cells = <1>;
563 #size-cells = <2>;
564 #address-cells = <3>;
565 reg = <0 0xffe0a000 0 0x1000>;
566 bus-range = <0 255>;
567 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 276 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
568 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 277 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
569 clock-frequency = <33333333>; 278 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
570 interrupt-parent = <&mpic>; 279 interrupt-map = <
571 interrupts = <26 2>; 280 /* IDSEL 0x0 */
281 0000 0x0 0x0 0x1 &mpic 0x0 0x1
282 0000 0x0 0x0 0x2 &mpic 0x1 0x1
283 0000 0x0 0x0 0x3 &mpic 0x2 0x1
284 0000 0x0 0x0 0x4 &mpic 0x3 0x1
285 >;
572 pcie@0 { 286 pcie@0 {
573 reg = <0x0 0x0 0x0 0x0 0x0>; 287 reg = <0x0 0x0 0x0 0x0 0x0>;
574 #size-cells = <2>; 288 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
index b69c3a5dc858..fc8ddddfccb6 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
@@ -14,12 +14,11 @@
14 * option) any later version. 14 * option) any later version.
15 */ 15 */
16 16
17/dts-v1/; 17/include/ "p2020si.dtsi"
18
18/ { 19/ {
19 model = "fsl,P2020"; 20 model = "fsl,P2020RDB";
20 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
21 #address-cells = <2>;
22 #size-cells = <2>;
23 22
24 aliases { 23 aliases {
25 ethernet1 = &enet1; 24 ethernet1 = &enet1;
@@ -29,91 +28,33 @@
29 }; 28 };
30 29
31 cpus { 30 cpus {
32 #address-cells = <1>; 31 PowerPC,P2020@1 {
33 #size-cells = <0>; 32 status = "disabled";
34
35 PowerPC,P2020@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 next-level-cache = <&L2>;
39 }; 33 };
34
40 }; 35 };
41 36
42 memory { 37 memory {
43 device_type = "memory"; 38 device_type = "memory";
44 }; 39 };
45 40
46 soc@ffe00000 { 41 localbus@ffe05000 {
47 #address-cells = <1>; 42 status = "disabled";
48 #size-cells = <1>; 43 };
49 device_type = "soc";
50 compatible = "fsl,p2020-immr", "simple-bus";
51 ranges = <0x0 0x0 0xffe00000 0x100000>;
52 bus-frequency = <0>; // Filled out by uboot.
53
54 ecm-law@0 {
55 compatible = "fsl,ecm-law";
56 reg = <0x0 0x1000>;
57 fsl,num-laws = <12>;
58 };
59
60 ecm@1000 {
61 compatible = "fsl,p2020-ecm", "fsl,ecm";
62 reg = <0x1000 0x1000>;
63 interrupts = <17 2>;
64 interrupt-parent = <&mpic>;
65 };
66
67 memory-controller@2000 {
68 compatible = "fsl,p2020-memory-controller";
69 reg = <0x2000 0x1000>;
70 interrupt-parent = <&mpic>;
71 interrupts = <18 2>;
72 };
73 44
45 soc@ffe00000 {
74 i2c@3000 { 46 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <43 2>;
81 interrupt-parent = <&mpic>;
82 dfsrr;
83 rtc@68 { 47 rtc@68 {
84 compatible = "dallas,ds1339"; 48 compatible = "dallas,ds1339";
85 reg = <0x68>; 49 reg = <0x68>;
86 }; 50 };
87 }; 51 };
88 52
89 i2c@3100 { 53 serial1: serial@4600 {
90 #address-cells = <1>; 54 status = "disabled";
91 #size-cells = <0>;
92 cell-index = <1>;
93 compatible = "fsl-i2c";
94 reg = <0x3100 0x100>;
95 interrupts = <43 2>;
96 interrupt-parent = <&mpic>;
97 dfsrr;
98 };
99
100 serial0: serial@4500 {
101 cell-index = <0>;
102 device_type = "serial";
103 compatible = "ns16550";
104 reg = <0x4500 0x100>;
105 clock-frequency = <0>;
106 }; 55 };
107 56
108 spi@7000 { 57 spi@7000 {
109 cell-index = <0>;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 compatible = "fsl,espi";
113 reg = <0x7000 0x1000>;
114 interrupts = <59 0x2>;
115 interrupt-parent = <&mpic>;
116 mode = "cpu";
117 58
118 fsl_m25p80@0 { 59 fsl_m25p80@0 {
119 #address-cells = <1>; 60 #address-cells = <1>;
@@ -161,76 +102,15 @@
161 }; 102 };
162 }; 103 };
163 104
164 gpio: gpio-controller@f000 { 105 dma@c300 {
165 #gpio-cells = <2>; 106 status = "disabled";
166 compatible = "fsl,mpc8572-gpio";
167 reg = <0xf000 0x100>;
168 interrupts = <47 0x2>;
169 interrupt-parent = <&mpic>;
170 gpio-controller;
171 };
172
173 L2: l2-cache-controller@20000 {
174 compatible = "fsl,p2020-l2-cache-controller";
175 reg = <0x20000 0x1000>;
176 cache-line-size = <32>; // 32 bytes
177 cache-size = <0x80000>; // L2,512K
178 interrupt-parent = <&mpic>;
179 interrupts = <16 2>;
180 };
181
182 dma@21300 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "fsl,eloplus-dma";
186 reg = <0x21300 0x4>;
187 ranges = <0x0 0x21100 0x200>;
188 cell-index = <0>;
189 dma-channel@0 {
190 compatible = "fsl,eloplus-dma-channel";
191 reg = <0x0 0x80>;
192 cell-index = <0>;
193 interrupt-parent = <&mpic>;
194 interrupts = <20 2>;
195 };
196 dma-channel@80 {
197 compatible = "fsl,eloplus-dma-channel";
198 reg = <0x80 0x80>;
199 cell-index = <1>;
200 interrupt-parent = <&mpic>;
201 interrupts = <21 2>;
202 };
203 dma-channel@100 {
204 compatible = "fsl,eloplus-dma-channel";
205 reg = <0x100 0x80>;
206 cell-index = <2>;
207 interrupt-parent = <&mpic>;
208 interrupts = <22 2>;
209 };
210 dma-channel@180 {
211 compatible = "fsl,eloplus-dma-channel";
212 reg = <0x180 0x80>;
213 cell-index = <3>;
214 interrupt-parent = <&mpic>;
215 interrupts = <23 2>;
216 };
217 }; 107 };
218 108
219 usb@22000 { 109 usb@22000 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 compatible = "fsl-usb2-dr";
223 reg = <0x22000 0x1000>;
224 interrupt-parent = <&mpic>;
225 interrupts = <28 0x2>;
226 phy_type = "ulpi"; 110 phy_type = "ulpi";
227 }; 111 };
228 112
229 mdio@24520 { 113 mdio@24520 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,gianfar-mdio";
233 reg = <0x24520 0x20>;
234 114
235 phy0: ethernet-phy@0 { 115 phy0: ethernet-phy@0 {
236 interrupt-parent = <&mpic>; 116 interrupt-parent = <&mpic>;
@@ -245,29 +125,21 @@
245 }; 125 };
246 126
247 mdio@25520 { 127 mdio@25520 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "fsl,gianfar-tbi";
251 reg = <0x26520 0x20>;
252
253 tbi0: tbi-phy@11 { 128 tbi0: tbi-phy@11 {
254 reg = <0x11>; 129 reg = <0x11>;
255 device_type = "tbi-phy"; 130 device_type = "tbi-phy";
256 }; 131 };
257 }; 132 };
258 133
134 mdio@26520 {
135 status = "disabled";
136 };
137
138 enet0: ethernet@24000 {
139 status = "disabled";
140 };
141
259 enet1: ethernet@25000 { 142 enet1: ethernet@25000 {
260 #address-cells = <1>;
261 #size-cells = <1>;
262 cell-index = <1>;
263 device_type = "network";
264 model = "eTSEC";
265 compatible = "gianfar";
266 reg = <0x25000 0x1000>;
267 ranges = <0x0 0x25000 0x1000>;
268 local-mac-address = [ 00 00 00 00 00 00 ];
269 interrupts = <35 2 36 2 40 2>;
270 interrupt-parent = <&mpic>;
271 tbi-handle = <&tbi0>; 143 tbi-handle = <&tbi0>;
272 phy-handle = <&phy0>; 144 phy-handle = <&phy0>;
273 phy-connection-type = "sgmii"; 145 phy-connection-type = "sgmii";
@@ -275,49 +147,12 @@
275 }; 147 };
276 148
277 enet2: ethernet@26000 { 149 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network";
282 model = "eTSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <31 2 32 2 33 2>;
288 interrupt-parent = <&mpic>;
289 phy-handle = <&phy1>; 150 phy-handle = <&phy1>;
290 phy-connection-type = "rgmii-id"; 151 phy-connection-type = "rgmii-id";
291 }; 152 };
292 153
293 sdhci@2e000 {
294 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
295 reg = <0x2e000 0x1000>;
296 interrupts = <72 0x2>;
297 interrupt-parent = <&mpic>;
298 /* Filled in by U-Boot */
299 clock-frequency = <0>;
300 };
301
302 crypto@30000 {
303 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
304 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
305 reg = <0x30000 0x10000>;
306 interrupts = <45 2 58 2>;
307 interrupt-parent = <&mpic>;
308 fsl,num-channels = <4>;
309 fsl,channel-fifo-len = <24>;
310 fsl,exec-units-mask = <0xbfe>;
311 fsl,descriptor-types-mask = <0x3ab0ebf>;
312 };
313 154
314 mpic: pic@40000 { 155 mpic: pic@40000 {
315 interrupt-controller;
316 #address-cells = <0>;
317 #interrupt-cells = <2>;
318 reg = <0x40000 0x40000>;
319 compatible = "chrp,open-pic";
320 device_type = "open-pic";
321 protected-sources = < 156 protected-sources = <
322 42 76 77 78 79 /* serial1 , dma2 */ 157 42 76 77 78 79 /* serial1 , dma2 */
323 29 30 34 26 /* enet0, pci1 */ 158 29 30 34 26 /* enet0, pci1 */
@@ -326,26 +161,28 @@
326 >; 161 >;
327 }; 162 };
328 163
329 global-utilities@e0000 { 164 msi@41600 {
330 compatible = "fsl,p2020-guts"; 165 status = "disabled";
331 reg = <0xe0000 0x1000>;
332 fsl,has-rstcr;
333 }; 166 };
167
168
334 }; 169 };
335 170
336 pci0: pcie@ffe09000 { 171 pci0: pcie@ffe08000 {
337 compatible = "fsl,mpc8548-pcie"; 172 status = "disabled";
338 device_type = "pci"; 173 };
339 #interrupt-cells = <1>; 174
340 #size-cells = <2>; 175 pci1: pcie@ffe09000 {
341 #address-cells = <3>;
342 reg = <0 0xffe09000 0 0x1000>;
343 bus-range = <0 255>;
344 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 176 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
345 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>; 177 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
346 clock-frequency = <33333333>; 178 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
347 interrupt-parent = <&mpic>; 179 interrupt-map = <
348 interrupts = <25 2>; 180 /* IDSEL 0x0 */
181 0000 0x0 0x0 0x1 &mpic 0x4 0x1
182 0000 0x0 0x0 0x2 &mpic 0x5 0x1
183 0000 0x0 0x0 0x3 &mpic 0x6 0x1
184 0000 0x0 0x0 0x4 &mpic 0x7 0x1
185 >;
349 pcie@0 { 186 pcie@0 {
350 reg = <0x0 0x0 0x0 0x0 0x0>; 187 reg = <0x0 0x0 0x0 0x0 0x0>;
351 #size-cells = <2>; 188 #size-cells = <2>;
@@ -360,4 +197,8 @@
360 0x0 0x100000>; 197 0x0 0x100000>;
361 }; 198 };
362 }; 199 };
200
201 pci2: pcie@ffe0a000 {
202 status = "disabled";
203 };
363}; 204};
diff --git a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
index 7a31d46c01b0..261c34ba45ec 100644
--- a/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
+++ b/arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
@@ -15,27 +15,21 @@
15 * option) any later version. 15 * option) any later version.
16 */ 16 */
17 17
18/dts-v1/; 18/include/ "p2020si.dtsi"
19
19/ { 20/ {
20 model = "fsl,P2020"; 21 model = "fsl,P2020RDB";
21 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP"; 22 compatible = "fsl,P2020RDB", "fsl,MPC85XXRDB-CAMP";
22 #address-cells = <2>;
23 #size-cells = <2>;
24 23
25 aliases { 24 aliases {
26 ethernet0 = &enet0; 25 ethernet0 = &enet0;
27 serial0 = &serial0; 26 serial0 = &serial1;
28 pci1 = &pci1; 27 pci1 = &pci1;
29 }; 28 };
30 29
31 cpus { 30 cpus {
32 #address-cells = <1>; 31 PowerPC,P2020@0 {
33 #size-cells = <0>; 32 status = "disabled";
34
35 PowerPC,P2020@1 {
36 device_type = "cpu";
37 reg = <0x1>;
38 next-level-cache = <&L2>;
39 }; 33 };
40 }; 34 };
41 35
@@ -43,20 +37,37 @@
43 device_type = "memory"; 37 device_type = "memory";
44 }; 38 };
45 39
40 localbus@ffe05000 {
41 status = "disabled";
42 };
43
46 soc@ffe00000 { 44 soc@ffe00000 {
47 #address-cells = <1>; 45 ecm-law@0 {
48 #size-cells = <1>; 46 status = "disabled";
49 device_type = "soc"; 47 };
50 compatible = "fsl,p2020-immr", "simple-bus"; 48
51 ranges = <0x0 0x0 0xffe00000 0x100000>; 49 ecm@1000 {
52 bus-frequency = <0>; // Filled out by uboot. 50 status = "disabled";
53 51 };
54 serial0: serial@4600 { 52
55 cell-index = <1>; 53 memory-controller@2000 {
56 device_type = "serial"; 54 status = "disabled";
57 compatible = "ns16550"; 55 };
58 reg = <0x4600 0x100>; 56
59 clock-frequency = <0>; 57 i2c@3000 {
58 status = "disabled";
59 };
60
61 i2c@3100 {
62 status = "disabled";
63 };
64
65 serial0: serial@4500 {
66 status = "disabled";
67 };
68
69 spi@7000 {
70 status = "disabled";
60 }; 71 };
61 72
62 dma@c300 { 73 dma@c300 {
@@ -96,6 +107,10 @@
96 }; 107 };
97 }; 108 };
98 109
110 gpio: gpio-controller@f000 {
111 status = "disabled";
112 };
113
99 L2: l2-cache-controller@20000 { 114 L2: l2-cache-controller@20000 {
100 compatible = "fsl,p2020-l2-cache-controller"; 115 compatible = "fsl,p2020-l2-cache-controller";
101 reg = <0x20000 0x1000>; 116 reg = <0x20000 0x1000>;
@@ -104,31 +119,49 @@
104 interrupt-parent = <&mpic>; 119 interrupt-parent = <&mpic>;
105 }; 120 };
106 121
122 dma@21300 {
123 status = "disabled";
124 };
125
126 usb@22000 {
127 status = "disabled";
128 };
129
130 mdio@24520 {
131 status = "disabled";
132 };
133
134 mdio@25520 {
135 status = "disabled";
136 };
137
138 mdio@26520 {
139 status = "disabled";
140 };
107 141
108 enet0: ethernet@24000 { 142 enet0: ethernet@24000 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 cell-index = <0>;
112 device_type = "network";
113 model = "eTSEC";
114 compatible = "gianfar";
115 reg = <0x24000 0x1000>;
116 ranges = <0x0 0x24000 0x1000>;
117 local-mac-address = [ 00 00 00 00 00 00 ];
118 interrupts = <29 2 30 2 34 2>;
119 interrupt-parent = <&mpic>;
120 fixed-link = <1 1 1000 0 0>; 143 fixed-link = <1 1 1000 0 0>;
121 phy-connection-type = "rgmii-id"; 144 phy-connection-type = "rgmii-id";
122 145
123 }; 146 };
124 147
148 enet1: ethernet@25000 {
149 status = "disabled";
150 };
151
152 enet2: ethernet@26000 {
153 status = "disabled";
154 };
155
156 sdhci@2e000 {
157 status = "disabled";
158 };
159
160 crypto@30000 {
161 status = "disabled";
162 };
163
125 mpic: pic@40000 { 164 mpic: pic@40000 {
126 interrupt-controller;
127 #address-cells = <0>;
128 #interrupt-cells = <2>;
129 reg = <0x40000 0x40000>;
130 compatible = "chrp,open-pic";
131 device_type = "open-pic";
132 protected-sources = < 165 protected-sources = <
133 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */ 166 17 18 43 42 59 47 /*ecm, mem, i2c, serial0, spi,gpio */
134 16 20 21 22 23 28 /* L2, dma1, USB */ 167 16 20 21 22 23 28 /* L2, dma1, USB */
@@ -152,21 +185,32 @@
152 0xe7 0>; 185 0xe7 0>;
153 interrupt-parent = <&mpic>; 186 interrupt-parent = <&mpic>;
154 }; 187 };
188
189 global-utilities@e0000 { //global utilities block
190 status = "disabled";
191 };
192
155 }; 193 };
156 194
157 pci1: pcie@ffe0a000 { 195 pci0: pcie@ffe08000 {
158 compatible = "fsl,mpc8548-pcie"; 196 status = "disabled";
159 device_type = "pci"; 197 };
160 #interrupt-cells = <1>; 198
161 #size-cells = <2>; 199 pci1: pcie@ffe09000 {
162 #address-cells = <3>; 200 status = "disabled";
163 reg = <0 0xffe0a000 0 0x1000>; 201 };
164 bus-range = <0 255>; 202
203 pci2: pcie@ffe0a000 {
165 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000 204 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
166 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>; 205 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
167 clock-frequency = <33333333>; 206 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
168 interrupt-parent = <&mpic>; 207 interrupt-map = <
169 interrupts = <26 2>; 208 /* IDSEL 0x0 */
209 0000 0x0 0x0 0x1 &mpic 0x0 0x1
210 0000 0x0 0x0 0x2 &mpic 0x1 0x1
211 0000 0x0 0x0 0x3 &mpic 0x2 0x1
212 0000 0x0 0x0 0x4 &mpic 0x3 0x1
213 >;
170 pcie@0 { 214 pcie@0 {
171 reg = <0x0 0x0 0x0 0x0 0x0>; 215 reg = <0x0 0x0 0x0 0x0 0x0>;
172 #size-cells = <2>; 216 #size-cells = <2>;
diff --git a/arch/powerpc/boot/dts/p2020si.dtsi b/arch/powerpc/boot/dts/p2020si.dtsi
new file mode 100644
index 000000000000..6def17f265d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/p2020si.dtsi
@@ -0,0 +1,382 @@
1/*
2 * P2020 Device Tree Source
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/dts-v1/;
13/ {
14 compatible = "fsl,P2020";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 PowerPC,P2020@0 {
23 device_type = "cpu";
24 reg = <0x0>;
25 next-level-cache = <&L2>;
26 };
27
28 PowerPC,P2020@1 {
29 device_type = "cpu";
30 reg = <0x1>;
31 next-level-cache = <&L2>;
32 };
33 };
34
35 localbus@ffe05000 {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p2020-elbc", "fsl,elbc", "simple-bus";
39 reg = <0 0xffe05000 0 0x1000>;
40 interrupts = <19 2>;
41 interrupt-parent = <&mpic>;
42 };
43
44 soc@ffe00000 {
45 #address-cells = <1>;
46 #size-cells = <1>;
47 device_type = "soc";
48 compatible = "fsl,p2020-immr", "simple-bus";
49 ranges = <0x0 0x0 0xffe00000 0x100000>;
50 bus-frequency = <0>; // Filled out by uboot.
51
52 ecm-law@0 {
53 compatible = "fsl,ecm-law";
54 reg = <0x0 0x1000>;
55 fsl,num-laws = <12>;
56 };
57
58 ecm@1000 {
59 compatible = "fsl,p2020-ecm", "fsl,ecm";
60 reg = <0x1000 0x1000>;
61 interrupts = <17 2>;
62 interrupt-parent = <&mpic>;
63 };
64
65 memory-controller@2000 {
66 compatible = "fsl,p2020-memory-controller";
67 reg = <0x2000 0x1000>;
68 interrupt-parent = <&mpic>;
69 interrupts = <18 2>;
70 };
71
72 i2c@3000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 cell-index = <0>;
76 compatible = "fsl-i2c";
77 reg = <0x3000 0x100>;
78 interrupts = <43 2>;
79 interrupt-parent = <&mpic>;
80 dfsrr;
81 };
82
83 i2c@3100 {
84 #address-cells = <1>;
85 #size-cells = <0>;
86 cell-index = <1>;
87 compatible = "fsl-i2c";
88 reg = <0x3100 0x100>;
89 interrupts = <43 2>;
90 interrupt-parent = <&mpic>;
91 dfsrr;
92 };
93
94 serial0: serial@4500 {
95 cell-index = <0>;
96 device_type = "serial";
97 compatible = "ns16550";
98 reg = <0x4500 0x100>;
99 clock-frequency = <0>;
100 interrupts = <42 2>;
101 interrupt-parent = <&mpic>;
102 };
103
104 serial1: serial@4600 {
105 cell-index = <1>;
106 device_type = "serial";
107 compatible = "ns16550";
108 reg = <0x4600 0x100>;
109 clock-frequency = <0>;
110 interrupts = <42 2>;
111 interrupt-parent = <&mpic>;
112 };
113
114 spi@7000 {
115 cell-index = <0>;
116 #address-cells = <1>;
117 #size-cells = <0>;
118 compatible = "fsl,espi";
119 reg = <0x7000 0x1000>;
120 interrupts = <59 0x2>;
121 interrupt-parent = <&mpic>;
122 mode = "cpu";
123 };
124
125 dma@c300 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,eloplus-dma";
129 reg = <0xc300 0x4>;
130 ranges = <0x0 0xc100 0x200>;
131 cell-index = <1>;
132 dma-channel@0 {
133 compatible = "fsl,eloplus-dma-channel";
134 reg = <0x0 0x80>;
135 cell-index = <0>;
136 interrupt-parent = <&mpic>;
137 interrupts = <76 2>;
138 };
139 dma-channel@80 {
140 compatible = "fsl,eloplus-dma-channel";
141 reg = <0x80 0x80>;
142 cell-index = <1>;
143 interrupt-parent = <&mpic>;
144 interrupts = <77 2>;
145 };
146 dma-channel@100 {
147 compatible = "fsl,eloplus-dma-channel";
148 reg = <0x100 0x80>;
149 cell-index = <2>;
150 interrupt-parent = <&mpic>;
151 interrupts = <78 2>;
152 };
153 dma-channel@180 {
154 compatible = "fsl,eloplus-dma-channel";
155 reg = <0x180 0x80>;
156 cell-index = <3>;
157 interrupt-parent = <&mpic>;
158 interrupts = <79 2>;
159 };
160 };
161
162 gpio: gpio-controller@f000 {
163 #gpio-cells = <2>;
164 compatible = "fsl,mpc8572-gpio";
165 reg = <0xf000 0x100>;
166 interrupts = <47 0x2>;
167 interrupt-parent = <&mpic>;
168 gpio-controller;
169 };
170
171 L2: l2-cache-controller@20000 {
172 compatible = "fsl,p2020-l2-cache-controller";
173 reg = <0x20000 0x1000>;
174 cache-line-size = <32>; // 32 bytes
175 cache-size = <0x80000>; // L2,512K
176 interrupt-parent = <&mpic>;
177 interrupts = <16 2>;
178 };
179
180 dma@21300 {
181 #address-cells = <1>;
182 #size-cells = <1>;
183 compatible = "fsl,eloplus-dma";
184 reg = <0x21300 0x4>;
185 ranges = <0x0 0x21100 0x200>;
186 cell-index = <0>;
187 dma-channel@0 {
188 compatible = "fsl,eloplus-dma-channel";
189 reg = <0x0 0x80>;
190 cell-index = <0>;
191 interrupt-parent = <&mpic>;
192 interrupts = <20 2>;
193 };
194 dma-channel@80 {
195 compatible = "fsl,eloplus-dma-channel";
196 reg = <0x80 0x80>;
197 cell-index = <1>;
198 interrupt-parent = <&mpic>;
199 interrupts = <21 2>;
200 };
201 dma-channel@100 {
202 compatible = "fsl,eloplus-dma-channel";
203 reg = <0x100 0x80>;
204 cell-index = <2>;
205 interrupt-parent = <&mpic>;
206 interrupts = <22 2>;
207 };
208 dma-channel@180 {
209 compatible = "fsl,eloplus-dma-channel";
210 reg = <0x180 0x80>;
211 cell-index = <3>;
212 interrupt-parent = <&mpic>;
213 interrupts = <23 2>;
214 };
215 };
216
217 usb@22000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "fsl-usb2-dr";
221 reg = <0x22000 0x1000>;
222 interrupt-parent = <&mpic>;
223 interrupts = <28 0x2>;
224 };
225
226 mdio@24520 {
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "fsl,gianfar-mdio";
230 reg = <0x24520 0x20>;
231 };
232
233 mdio@25520 {
234 #address-cells = <1>;
235 #size-cells = <0>;
236 compatible = "fsl,gianfar-tbi";
237 reg = <0x26520 0x20>;
238 };
239
240 mdio@26520 {
241 #address-cells = <1>;
242 #size-cells = <0>;
243 compatible = "fsl,gianfar-tbi";
244 reg = <0x520 0x20>;
245 };
246
247 enet0: ethernet@24000 {
248 #address-cells = <1>;
249 #size-cells = <1>;
250 cell-index = <0>;
251 device_type = "network";
252 model = "eTSEC";
253 compatible = "gianfar";
254 reg = <0x24000 0x1000>;
255 ranges = <0x0 0x24000 0x1000>;
256 local-mac-address = [ 00 00 00 00 00 00 ];
257 interrupts = <29 2 30 2 34 2>;
258 interrupt-parent = <&mpic>;
259 };
260
261 enet1: ethernet@25000 {
262 #address-cells = <1>;
263 #size-cells = <1>;
264 cell-index = <1>;
265 device_type = "network";
266 model = "eTSEC";
267 compatible = "gianfar";
268 reg = <0x25000 0x1000>;
269 ranges = <0x0 0x25000 0x1000>;
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 interrupts = <35 2 36 2 40 2>;
272 interrupt-parent = <&mpic>;
273
274 };
275
276 enet2: ethernet@26000 {
277 #address-cells = <1>;
278 #size-cells = <1>;
279 cell-index = <2>;
280 device_type = "network";
281 model = "eTSEC";
282 compatible = "gianfar";
283 reg = <0x26000 0x1000>;
284 ranges = <0x0 0x26000 0x1000>;
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 interrupts = <31 2 32 2 33 2>;
287 interrupt-parent = <&mpic>;
288
289 };
290
291 sdhci@2e000 {
292 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
293 reg = <0x2e000 0x1000>;
294 interrupts = <72 0x2>;
295 interrupt-parent = <&mpic>;
296 /* Filled in by U-Boot */
297 clock-frequency = <0>;
298 };
299
300 crypto@30000 {
301 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
302 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
303 reg = <0x30000 0x10000>;
304 interrupts = <45 2 58 2>;
305 interrupt-parent = <&mpic>;
306 fsl,num-channels = <4>;
307 fsl,channel-fifo-len = <24>;
308 fsl,exec-units-mask = <0xbfe>;
309 fsl,descriptor-types-mask = <0x3ab0ebf>;
310 };
311
312 mpic: pic@40000 {
313 interrupt-controller;
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
316 reg = <0x40000 0x40000>;
317 compatible = "chrp,open-pic";
318 device_type = "open-pic";
319 };
320
321 msi@41600 {
322 compatible = "fsl,p2020-msi", "fsl,mpic-msi";
323 reg = <0x41600 0x80>;
324 msi-available-ranges = <0 0x100>;
325 interrupts = <
326 0xe0 0
327 0xe1 0
328 0xe2 0
329 0xe3 0
330 0xe4 0
331 0xe5 0
332 0xe6 0
333 0xe7 0>;
334 interrupt-parent = <&mpic>;
335 };
336
337 global-utilities@e0000 { //global utilities block
338 compatible = "fsl,p2020-guts";
339 reg = <0xe0000 0x1000>;
340 fsl,has-rstcr;
341 };
342 };
343
344 pci0: pcie@ffe08000 {
345 compatible = "fsl,mpc8548-pcie";
346 device_type = "pci";
347 #interrupt-cells = <1>;
348 #size-cells = <2>;
349 #address-cells = <3>;
350 reg = <0 0xffe08000 0 0x1000>;
351 bus-range = <0 255>;
352 clock-frequency = <33333333>;
353 interrupt-parent = <&mpic>;
354 interrupts = <24 2>;
355 };
356
357 pci1: pcie@ffe09000 {
358 compatible = "fsl,mpc8548-pcie";
359 device_type = "pci";
360 #interrupt-cells = <1>;
361 #size-cells = <2>;
362 #address-cells = <3>;
363 reg = <0 0xffe09000 0 0x1000>;
364 bus-range = <0 255>;
365 clock-frequency = <33333333>;
366 interrupt-parent = <&mpic>;
367 interrupts = <25 2>;
368 };
369
370 pci2: pcie@ffe0a000 {
371 compatible = "fsl,mpc8548-pcie";
372 device_type = "pci";
373 #interrupt-cells = <1>;
374 #size-cells = <2>;
375 #address-cells = <3>;
376 reg = <0 0xffe0a000 0 0x1000>;
377 bus-range = <0 255>;
378 clock-frequency = <33333333>;
379 interrupt-parent = <&mpic>;
380 interrupts = <26 2>;
381 };
382};
diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index c683bce4c26e..126ef1b08a01 100644
--- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -104,7 +104,6 @@ CONFIG_ROOT_NFS=y
104CONFIG_PARTITION_ADVANCED=y 104CONFIG_PARTITION_ADVANCED=y
105CONFIG_DEBUG_KERNEL=y 105CONFIG_DEBUG_KERNEL=y
106CONFIG_DETECT_HUNG_TASK=y 106CONFIG_DETECT_HUNG_TASK=y
107# CONFIG_DEBUG_BUGVERBOSE is not set
108# CONFIG_RCU_CPU_STALL_DETECTOR is not set 107# CONFIG_RCU_CPU_STALL_DETECTOR is not set
109CONFIG_SYSCTL_SYSCALL_CHECK=y 108CONFIG_SYSCTL_SYSCALL_CHECK=y
110CONFIG_CRYPTO_PCBC=m 109CONFIG_CRYPTO_PCBC=m
diff --git a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
index a721cd3d793f..abcf00ad939e 100644
--- a/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8315_rdb_defconfig
@@ -101,7 +101,6 @@ CONFIG_ROOT_NFS=y
101CONFIG_PARTITION_ADVANCED=y 101CONFIG_PARTITION_ADVANCED=y
102CONFIG_DEBUG_KERNEL=y 102CONFIG_DEBUG_KERNEL=y
103CONFIG_DETECT_HUNG_TASK=y 103CONFIG_DETECT_HUNG_TASK=y
104# CONFIG_DEBUG_BUGVERBOSE is not set
105# CONFIG_RCU_CPU_STALL_DETECTOR is not set 104# CONFIG_RCU_CPU_STALL_DETECTOR is not set
106CONFIG_SYSCTL_SYSCALL_CHECK=y 105CONFIG_SYSCTL_SYSCALL_CHECK=y
107CONFIG_CRYPTO_PCBC=m 106CONFIG_CRYPTO_PCBC=m
diff --git a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
index 55e0725500dc..11662c217ac0 100644
--- a/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8540_ads_defconfig
@@ -58,7 +58,6 @@ CONFIG_PARTITION_ADVANCED=y
58CONFIG_DEBUG_KERNEL=y 58CONFIG_DEBUG_KERNEL=y
59CONFIG_DETECT_HUNG_TASK=y 59CONFIG_DETECT_HUNG_TASK=y
60CONFIG_DEBUG_MUTEXES=y 60CONFIG_DEBUG_MUTEXES=y
61# CONFIG_DEBUG_BUGVERBOSE is not set
62# CONFIG_RCU_CPU_STALL_DETECTOR is not set 61# CONFIG_RCU_CPU_STALL_DETECTOR is not set
63CONFIG_SYSCTL_SYSCALL_CHECK=y 62CONFIG_SYSCTL_SYSCALL_CHECK=y
64# CONFIG_CRYPTO_ANSI_CPRNG is not set 63# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
index d724095530a6..ebe9b30b0721 100644
--- a/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
+++ b/arch/powerpc/configs/85xx/mpc8560_ads_defconfig
@@ -59,7 +59,6 @@ CONFIG_PARTITION_ADVANCED=y
59CONFIG_DEBUG_KERNEL=y 59CONFIG_DEBUG_KERNEL=y
60CONFIG_DETECT_HUNG_TASK=y 60CONFIG_DETECT_HUNG_TASK=y
61CONFIG_DEBUG_MUTEXES=y 61CONFIG_DEBUG_MUTEXES=y
62# CONFIG_DEBUG_BUGVERBOSE is not set
63# CONFIG_RCU_CPU_STALL_DETECTOR is not set 62# CONFIG_RCU_CPU_STALL_DETECTOR is not set
64CONFIG_SYSCTL_SYSCALL_CHECK=y 63CONFIG_SYSCTL_SYSCALL_CHECK=y
65# CONFIG_CRYPTO_ANSI_CPRNG is not set 64# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
index 4b44beaa21ae..eb25229b387a 100644
--- a/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
+++ b/arch/powerpc/configs/85xx/mpc85xx_cds_defconfig
@@ -63,7 +63,6 @@ CONFIG_PARTITION_ADVANCED=y
63CONFIG_DEBUG_KERNEL=y 63CONFIG_DEBUG_KERNEL=y
64CONFIG_DETECT_HUNG_TASK=y 64CONFIG_DETECT_HUNG_TASK=y
65CONFIG_DEBUG_MUTEXES=y 65CONFIG_DEBUG_MUTEXES=y
66# CONFIG_DEBUG_BUGVERBOSE is not set
67# CONFIG_RCU_CPU_STALL_DETECTOR is not set 66# CONFIG_RCU_CPU_STALL_DETECTOR is not set
68CONFIG_SYSCTL_SYSCALL_CHECK=y 67CONFIG_SYSCTL_SYSCALL_CHECK=y
69# CONFIG_CRYPTO_ANSI_CPRNG is not set 68# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig
index b614508d6fd2..f51c7ebc181e 100644
--- a/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig
+++ b/arch/powerpc/configs/86xx/mpc8641_hpcn_defconfig
@@ -168,7 +168,6 @@ CONFIG_MAC_PARTITION=y
168CONFIG_CRC_T10DIF=y 168CONFIG_CRC_T10DIF=y
169CONFIG_DEBUG_KERNEL=y 169CONFIG_DEBUG_KERNEL=y
170CONFIG_DETECT_HUNG_TASK=y 170CONFIG_DETECT_HUNG_TASK=y
171# CONFIG_DEBUG_BUGVERBOSE is not set
172CONFIG_DEBUG_INFO=y 171CONFIG_DEBUG_INFO=y
173# CONFIG_RCU_CPU_STALL_DETECTOR is not set 172# CONFIG_RCU_CPU_STALL_DETECTOR is not set
174CONFIG_SYSCTL_SYSCALL_CHECK=y 173CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/configs/e55xx_smp_defconfig b/arch/powerpc/configs/e55xx_smp_defconfig
index 9fa1613e5e2b..d32283555b53 100644
--- a/arch/powerpc/configs/e55xx_smp_defconfig
+++ b/arch/powerpc/configs/e55xx_smp_defconfig
@@ -6,10 +6,10 @@ CONFIG_NR_CPUS=2
6CONFIG_EXPERIMENTAL=y 6CONFIG_EXPERIMENTAL=y
7CONFIG_SYSVIPC=y 7CONFIG_SYSVIPC=y
8CONFIG_BSD_PROCESS_ACCT=y 8CONFIG_BSD_PROCESS_ACCT=y
9CONFIG_SPARSE_IRQ=y
9CONFIG_IKCONFIG=y 10CONFIG_IKCONFIG=y
10CONFIG_IKCONFIG_PROC=y 11CONFIG_IKCONFIG_PROC=y
11CONFIG_LOG_BUF_SHIFT=14 12CONFIG_LOG_BUF_SHIFT=14
12CONFIG_SYSFS_DEPRECATED_V2=y
13CONFIG_BLK_DEV_INITRD=y 13CONFIG_BLK_DEV_INITRD=y
14# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 14# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
15CONFIG_EXPERT=y 15CONFIG_EXPERT=y
@@ -25,8 +25,32 @@ CONFIG_P5020_DS=y
25CONFIG_NO_HZ=y 25CONFIG_NO_HZ=y
26CONFIG_HIGH_RES_TIMERS=y 26CONFIG_HIGH_RES_TIMERS=y
27CONFIG_BINFMT_MISC=m 27CONFIG_BINFMT_MISC=m
28CONFIG_SPARSE_IRQ=y
29# CONFIG_PCI is not set 28# CONFIG_PCI is not set
29CONFIG_NET=y
30CONFIG_PACKET=y
31CONFIG_UNIX=y
32CONFIG_XFRM_USER=y
33CONFIG_NET_KEY=y
34CONFIG_INET=y
35CONFIG_IP_MULTICAST=y
36CONFIG_IP_ADVANCED_ROUTER=y
37CONFIG_IP_MULTIPLE_TABLES=y
38CONFIG_IP_ROUTE_MULTIPATH=y
39CONFIG_IP_ROUTE_VERBOSE=y
40CONFIG_IP_PNP=y
41CONFIG_IP_PNP_DHCP=y
42CONFIG_IP_PNP_BOOTP=y
43CONFIG_IP_PNP_RARP=y
44CONFIG_NET_IPIP=y
45CONFIG_IP_MROUTE=y
46CONFIG_IP_PIMSM_V1=y
47CONFIG_IP_PIMSM_V2=y
48CONFIG_ARPD=y
49CONFIG_INET_ESP=y
50# CONFIG_INET_XFRM_MODE_BEET is not set
51# CONFIG_INET_LRO is not set
52CONFIG_IPV6=y
53CONFIG_IP_SCTP=m
30CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 54CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
31CONFIG_PROC_DEVICETREE=y 55CONFIG_PROC_DEVICETREE=y
32CONFIG_BLK_DEV_LOOP=y 56CONFIG_BLK_DEV_LOOP=y
@@ -34,6 +58,9 @@ CONFIG_BLK_DEV_RAM=y
34CONFIG_BLK_DEV_RAM_SIZE=131072 58CONFIG_BLK_DEV_RAM_SIZE=131072
35CONFIG_MISC_DEVICES=y 59CONFIG_MISC_DEVICES=y
36CONFIG_EEPROM_LEGACY=y 60CONFIG_EEPROM_LEGACY=y
61CONFIG_NETDEVICES=y
62CONFIG_DUMMY=y
63CONFIG_NET_ETHERNET=y
37CONFIG_INPUT_FF_MEMLESS=m 64CONFIG_INPUT_FF_MEMLESS=m
38# CONFIG_INPUT_MOUSEDEV is not set 65# CONFIG_INPUT_MOUSEDEV is not set
39# CONFIG_INPUT_KEYBOARD is not set 66# CONFIG_INPUT_KEYBOARD is not set
@@ -64,22 +91,14 @@ CONFIG_NLS=y
64CONFIG_NLS_UTF8=m 91CONFIG_NLS_UTF8=m
65CONFIG_CRC_T10DIF=y 92CONFIG_CRC_T10DIF=y
66CONFIG_CRC_ITU_T=m 93CONFIG_CRC_ITU_T=m
67CONFIG_LIBCRC32C=m
68CONFIG_FRAME_WARN=1024 94CONFIG_FRAME_WARN=1024
69CONFIG_DEBUG_FS=y 95CONFIG_DEBUG_FS=y
70CONFIG_DEBUG_KERNEL=y 96CONFIG_DEBUG_KERNEL=y
71CONFIG_DETECT_HUNG_TASK=y 97CONFIG_DETECT_HUNG_TASK=y
72# CONFIG_DEBUG_BUGVERBOSE is not set
73CONFIG_DEBUG_INFO=y 98CONFIG_DEBUG_INFO=y
74# CONFIG_RCU_CPU_STALL_DETECTOR is not set 99# CONFIG_RCU_CPU_STALL_DETECTOR is not set
75CONFIG_SYSCTL_SYSCALL_CHECK=y 100CONFIG_SYSCTL_SYSCALL_CHECK=y
76CONFIG_VIRQ_DEBUG=y 101CONFIG_VIRQ_DEBUG=y
77CONFIG_CRYPTO=y
78CONFIG_CRYPTO_CBC=y
79CONFIG_CRYPTO_PCBC=m 102CONFIG_CRYPTO_PCBC=m
80CONFIG_CRYPTO_HMAC=y
81CONFIG_CRYPTO_MD5=y
82CONFIG_CRYPTO_SHA1=m
83CONFIG_CRYPTO_DES=y
84# CONFIG_CRYPTO_ANSI_CPRNG is not set 103# CONFIG_CRYPTO_ANSI_CPRNG is not set
85CONFIG_CRYPTO_DEV_TALITOS=y 104CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index c06a86c33098..96b89df7752a 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -204,7 +204,6 @@ CONFIG_CRC_T10DIF=y
204CONFIG_DEBUG_FS=y 204CONFIG_DEBUG_FS=y
205CONFIG_DEBUG_KERNEL=y 205CONFIG_DEBUG_KERNEL=y
206CONFIG_DETECT_HUNG_TASK=y 206CONFIG_DETECT_HUNG_TASK=y
207# CONFIG_DEBUG_BUGVERBOSE is not set
208CONFIG_DEBUG_INFO=y 207CONFIG_DEBUG_INFO=y
209# CONFIG_RCU_CPU_STALL_DETECTOR is not set 208# CONFIG_RCU_CPU_STALL_DETECTOR is not set
210CONFIG_SYSCTL_SYSCALL_CHECK=y 209CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 942ced90557c..de65841aa04e 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -206,7 +206,6 @@ CONFIG_CRC_T10DIF=y
206CONFIG_DEBUG_FS=y 206CONFIG_DEBUG_FS=y
207CONFIG_DEBUG_KERNEL=y 207CONFIG_DEBUG_KERNEL=y
208CONFIG_DETECT_HUNG_TASK=y 208CONFIG_DETECT_HUNG_TASK=y
209# CONFIG_DEBUG_BUGVERBOSE is not set
210CONFIG_DEBUG_INFO=y 209CONFIG_DEBUG_INFO=y
211# CONFIG_RCU_CPU_STALL_DETECTOR is not set 210# CONFIG_RCU_CPU_STALL_DETECTOR is not set
212CONFIG_SYSCTL_SYSCALL_CHECK=y 211CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/configs/mpc86xx_defconfig b/arch/powerpc/configs/mpc86xx_defconfig
index 038a308cbfc4..a1cc8179e9fd 100644
--- a/arch/powerpc/configs/mpc86xx_defconfig
+++ b/arch/powerpc/configs/mpc86xx_defconfig
@@ -171,7 +171,6 @@ CONFIG_MAC_PARTITION=y
171CONFIG_CRC_T10DIF=y 171CONFIG_CRC_T10DIF=y
172CONFIG_DEBUG_KERNEL=y 172CONFIG_DEBUG_KERNEL=y
173CONFIG_DETECT_HUNG_TASK=y 173CONFIG_DETECT_HUNG_TASK=y
174# CONFIG_DEBUG_BUGVERBOSE is not set
175CONFIG_DEBUG_INFO=y 174CONFIG_DEBUG_INFO=y
176# CONFIG_RCU_CPU_STALL_DETECTOR is not set 175# CONFIG_RCU_CPU_STALL_DETECTOR is not set
177CONFIG_SYSCTL_SYSCALL_CHECK=y 176CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 4efbfb3f3254..c0d842cfd012 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -157,6 +157,7 @@ extern const char *powerpc_base_platform;
157#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000) 157#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) 158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
159#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) 159#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
160#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x0000000000080000)
160#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) 161#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
161#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 162#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
162#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 163#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
@@ -385,7 +386,8 @@ extern const char *powerpc_base_platform;
385 CPU_FTR_DBELL) 386 CPU_FTR_DBELL)
386#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 387#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
387 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 388 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
388 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD) 389 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
390 CPU_FTR_DEBUG_LVL_EXC)
389#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 391#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
390 392
391/* 64-bit CPUs */ 393/* 64-bit CPUs */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 7005ee0b074d..664bee6622e7 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -263,6 +263,7 @@ struct mpic
263#ifdef CONFIG_SMP 263#ifdef CONFIG_SMP
264 struct irq_chip hc_ipi; 264 struct irq_chip hc_ipi;
265#endif 265#endif
266 struct irq_chip hc_tm;
266 const char *name; 267 const char *name;
267 /* Flags */ 268 /* Flags */
268 unsigned int flags; 269 unsigned int flags;
@@ -281,7 +282,7 @@ struct mpic
281 282
282 /* vector numbers used for internal sources (ipi/timers) */ 283 /* vector numbers used for internal sources (ipi/timers) */
283 unsigned int ipi_vecs[4]; 284 unsigned int ipi_vecs[4];
284 unsigned int timer_vecs[4]; 285 unsigned int timer_vecs[8];
285 286
286 /* Spurious vector to program into unused sources */ 287 /* Spurious vector to program into unused sources */
287 unsigned int spurious_vec; 288 unsigned int spurious_vec;
@@ -371,6 +372,8 @@ struct mpic
371 * NOTE: This flag trumps MPIC_WANTS_RESET. 372 * NOTE: This flag trumps MPIC_WANTS_RESET.
372 */ 373 */
373#define MPIC_NO_RESET 0x00004000 374#define MPIC_NO_RESET 0x00004000
375/* Freescale MPIC (compatible includes "fsl,mpic") */
376#define MPIC_FSL 0x00008000
374 377
375/* MPIC HW modification ID */ 378/* MPIC HW modification ID */
376#define MPIC_REGSET_MASK 0xf0000000 379#define MPIC_REGSET_MASK 0xf0000000
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 817bd1ac1752..0f0ad9fa01c1 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -83,6 +83,10 @@
83#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ 83#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
84#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ 84#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
85#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ 85#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
86#define SPRN_IVOR38 0x1B0 /* Interrupt Vector Offset Register 38 */
87#define SPRN_IVOR39 0x1B1 /* Interrupt Vector Offset Register 39 */
88#define SPRN_IVOR40 0x1B2 /* Interrupt Vector Offset Register 40 */
89#define SPRN_IVOR41 0x1B3 /* Interrupt Vector Offset Register 41 */
86#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 90#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
87#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 91#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
88#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 92#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index 913611105c1f..8053db02b85e 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -88,6 +88,9 @@ _GLOBAL(__setup_cpu_e5500)
88 bl __e500_dcache_setup 88 bl __e500_dcache_setup
89#ifdef CONFIG_PPC_BOOK3E_64 89#ifdef CONFIG_PPC_BOOK3E_64
90 bl .__setup_base_ivors 90 bl .__setup_base_ivors
91 bl .setup_perfmon_ivor
92 bl .setup_doorbell_ivors
93 bl .setup_ehv_ivors
91#else 94#else
92 bl __setup_e500mc_ivors 95 bl __setup_e500mc_ivors
93#endif 96#endif
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 4d0abb4930a1..d24d4400cc79 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -253,9 +253,6 @@ exception_marker:
253 .balign 0x1000 253 .balign 0x1000
254 .globl interrupt_base_book3e 254 .globl interrupt_base_book3e
255interrupt_base_book3e: /* fake trap */ 255interrupt_base_book3e: /* fake trap */
256 /* Note: If real debug exceptions are supported by the HW, the vector
257 * below will have to be patched up to point to an appropriate handler
258 */
259 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */ 256 EXCEPTION_STUB(0x000, machine_check) /* 0x0200 */
260 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */ 257 EXCEPTION_STUB(0x020, critical_input) /* 0x0580 */
261 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */ 258 EXCEPTION_STUB(0x040, debug_crit) /* 0x0d00 */
@@ -272,8 +269,13 @@ interrupt_base_book3e: /* fake trap */
272 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 269 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
273 EXCEPTION_STUB(0x1c0, data_tlb_miss) 270 EXCEPTION_STUB(0x1c0, data_tlb_miss)
274 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 271 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
272 EXCEPTION_STUB(0x260, perfmon)
275 EXCEPTION_STUB(0x280, doorbell) 273 EXCEPTION_STUB(0x280, doorbell)
276 EXCEPTION_STUB(0x2a0, doorbell_crit) 274 EXCEPTION_STUB(0x2a0, doorbell_crit)
275 EXCEPTION_STUB(0x2c0, guest_doorbell)
276 EXCEPTION_STUB(0x2e0, guest_doorbell_crit)
277 EXCEPTION_STUB(0x300, hypercall)
278 EXCEPTION_STUB(0x320, ehpriv)
277 279
278 .globl interrupt_end_book3e 280 .globl interrupt_end_book3e
279interrupt_end_book3e: 281interrupt_end_book3e:
@@ -455,6 +457,70 @@ interrupt_end_book3e:
455kernel_dbg_exc: 457kernel_dbg_exc:
456 b . /* NYI */ 458 b . /* NYI */
457 459
460/* Debug exception as a debug interrupt*/
461 START_EXCEPTION(debug_debug);
462 DBG_EXCEPTION_PROLOG(0xd00, PROLOG_ADDITION_2REGS)
463
464 /*
465 * If there is a single step or branch-taken exception in an
466 * exception entry sequence, it was probably meant to apply to
467 * the code where the exception occurred (since exception entry
468 * doesn't turn off DE automatically). We simulate the effect
469 * of turning off DE on entry to an exception handler by turning
470 * off DE in the DSRR1 value and clearing the debug status.
471 */
472
473 mfspr r14,SPRN_DBSR /* check single-step/branch taken */
474 andis. r15,r14,DBSR_IC@h
475 beq+ 1f
476
477 LOAD_REG_IMMEDIATE(r14,interrupt_base_book3e)
478 LOAD_REG_IMMEDIATE(r15,interrupt_end_book3e)
479 cmpld cr0,r10,r14
480 cmpld cr1,r10,r15
481 blt+ cr0,1f
482 bge+ cr1,1f
483
484 /* here it looks like we got an inappropriate debug exception. */
485 lis r14,DBSR_IC@h /* clear the IC event */
486 rlwinm r11,r11,0,~MSR_DE /* clear DE in the DSRR1 value */
487 mtspr SPRN_DBSR,r14
488 mtspr SPRN_DSRR1,r11
489 lwz r10,PACA_EXDBG+EX_CR(r13) /* restore registers */
490 ld r1,PACA_EXDBG+EX_R1(r13)
491 ld r14,PACA_EXDBG+EX_R14(r13)
492 ld r15,PACA_EXDBG+EX_R15(r13)
493 mtcr r10
494 ld r10,PACA_EXDBG+EX_R10(r13) /* restore registers */
495 ld r11,PACA_EXDBG+EX_R11(r13)
496 mfspr r13,SPRN_SPRG_DBG_SCRATCH
497 rfdi
498
499 /* Normal debug exception */
500 /* XXX We only handle coming from userspace for now since we can't
501 * quite save properly an interrupted kernel state yet
502 */
5031: andi. r14,r11,MSR_PR; /* check for userspace again */
504 beq kernel_dbg_exc; /* if from kernel mode */
505
506 /* Now we mash up things to make it look like we are coming on a
507 * normal exception
508 */
509 mfspr r15,SPRN_SPRG_DBG_SCRATCH
510 mtspr SPRN_SPRG_GEN_SCRATCH,r15
511 mfspr r14,SPRN_DBSR
512 EXCEPTION_COMMON(0xd00, PACA_EXDBG, INTS_DISABLE_ALL)
513 std r14,_DSISR(r1)
514 addi r3,r1,STACK_FRAME_OVERHEAD
515 mr r4,r14
516 ld r14,PACA_EXDBG+EX_R14(r13)
517 ld r15,PACA_EXDBG+EX_R15(r13)
518 bl .save_nvgprs
519 bl .DebugException
520 b .ret_from_except
521
522 MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE)
523
458/* Doorbell interrupt */ 524/* Doorbell interrupt */
459 MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE) 525 MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE)
460 526
@@ -469,6 +535,11 @@ kernel_dbg_exc:
469// b ret_from_crit_except 535// b ret_from_crit_except
470 b . 536 b .
471 537
538 MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE)
539 MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE)
540 MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE)
541 MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE)
542
472 543
473/* 544/*
474 * An interrupt came in while soft-disabled; clear EE in SRR1, 545 * An interrupt came in while soft-disabled; clear EE in SRR1,
@@ -588,7 +659,12 @@ fast_exception_return:
588BAD_STACK_TRAMPOLINE(0x000) 659BAD_STACK_TRAMPOLINE(0x000)
589BAD_STACK_TRAMPOLINE(0x100) 660BAD_STACK_TRAMPOLINE(0x100)
590BAD_STACK_TRAMPOLINE(0x200) 661BAD_STACK_TRAMPOLINE(0x200)
662BAD_STACK_TRAMPOLINE(0x260)
663BAD_STACK_TRAMPOLINE(0x2c0)
664BAD_STACK_TRAMPOLINE(0x2e0)
591BAD_STACK_TRAMPOLINE(0x300) 665BAD_STACK_TRAMPOLINE(0x300)
666BAD_STACK_TRAMPOLINE(0x310)
667BAD_STACK_TRAMPOLINE(0x320)
592BAD_STACK_TRAMPOLINE(0x400) 668BAD_STACK_TRAMPOLINE(0x400)
593BAD_STACK_TRAMPOLINE(0x500) 669BAD_STACK_TRAMPOLINE(0x500)
594BAD_STACK_TRAMPOLINE(0x600) 670BAD_STACK_TRAMPOLINE(0x600)
@@ -1124,3 +1200,33 @@ _GLOBAL(__setup_base_ivors)
1124 sync 1200 sync
1125 1201
1126 blr 1202 blr
1203
1204_GLOBAL(setup_perfmon_ivor)
1205 SET_IVOR(35, 0x260) /* Performance Monitor */
1206 blr
1207
1208_GLOBAL(setup_doorbell_ivors)
1209 SET_IVOR(36, 0x280) /* Processor Doorbell */
1210 SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */
1211
1212 /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */
1213 mfspr r10,SPRN_MMUCFG
1214 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1215 beqlr
1216
1217 SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */
1218 SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */
1219 blr
1220
1221_GLOBAL(setup_ehv_ivors)
1222 /*
1223 * We may be running as a guest and lack E.HV even on a chip
1224 * that normally has it.
1225 */
1226 mfspr r10,SPRN_MMUCFG
1227 rlwinm. r10,r10,0,MMUCFG_LPIDSIZE
1228 beqlr
1229
1230 SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */
1231 SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */
1232 blr
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
index c2ec0a12e14f..a88bf2713d41 100644
--- a/arch/powerpc/kernel/setup_64.c
+++ b/arch/powerpc/kernel/setup_64.c
@@ -62,6 +62,7 @@
62#include <asm/udbg.h> 62#include <asm/udbg.h>
63#include <asm/kexec.h> 63#include <asm/kexec.h>
64#include <asm/mmu_context.h> 64#include <asm/mmu_context.h>
65#include <asm/code-patching.h>
65 66
66#include "setup.h" 67#include "setup.h"
67 68
@@ -477,6 +478,9 @@ static void __init irqstack_early_init(void)
477#ifdef CONFIG_PPC_BOOK3E 478#ifdef CONFIG_PPC_BOOK3E
478static void __init exc_lvl_early_init(void) 479static void __init exc_lvl_early_init(void)
479{ 480{
481 extern unsigned int interrupt_base_book3e;
482 extern unsigned int exc_debug_debug_book3e;
483
480 unsigned int i; 484 unsigned int i;
481 485
482 for_each_possible_cpu(i) { 486 for_each_possible_cpu(i) {
@@ -487,6 +491,10 @@ static void __init exc_lvl_early_init(void)
487 mcheckirq_ctx[i] = (struct thread_info *) 491 mcheckirq_ctx[i] = (struct thread_info *)
488 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE)); 492 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
489 } 493 }
494
495 if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
496 patch_branch(&interrupt_base_book3e + (0x040 / 4) + 1,
497 (unsigned long)&exc_debug_debug_book3e, 0);
490} 498}
491#else 499#else
492#define exc_lvl_early_init() 500#define exc_lvl_early_init()
diff --git a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
index 018cc67be426..a896511690c2 100644
--- a/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
+++ b/arch/powerpc/platforms/86xx/mpc8610_hpcd.c
@@ -66,7 +66,7 @@ static void __init mpc8610_suspend_init(void)
66 return; 66 return;
67 } 67 }
68 68
69 ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9/wakeup", NULL); 69 ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
70 if (ret) { 70 if (ret) {
71 pr_err("%s: can't request pixis event IRQ: %d\n", 71 pr_err("%s: can't request pixis event IRQ: %d\n",
72 __func__, ret); 72 __func__, ret);
@@ -105,45 +105,77 @@ machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
105 105
106#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE) 106#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
107 107
108static u32 get_busfreq(void) 108/*
109{ 109 * DIU Area Descriptor
110 struct device_node *node; 110 *
111 111 * The MPC8610 reference manual shows the bits of the AD register in
112 u32 fs_busfreq = 0; 112 * little-endian order, which causes the BLUE_C field to be split into two
113 node = of_find_node_by_type(NULL, "cpu"); 113 * parts. To simplify the definition of the MAKE_AD() macro, we define the
114 if (node) { 114 * fields in big-endian order and byte-swap the result.
115 unsigned int size; 115 *
116 const unsigned int *prop = 116 * So even though the registers don't look like they're in the
117 of_get_property(node, "bus-frequency", &size); 117 * same bit positions as they are on the P1022, the same value is written to
118 if (prop) 118 * the AD register on the MPC8610 and on the P1022.
119 fs_busfreq = *prop; 119 */
120 of_node_put(node); 120#define AD_BYTE_F 0x10000000
121 }; 121#define AD_ALPHA_C_MASK 0x0E000000
122 return fs_busfreq; 122#define AD_ALPHA_C_SHIFT 25
123} 123#define AD_BLUE_C_MASK 0x01800000
124#define AD_BLUE_C_SHIFT 23
125#define AD_GREEN_C_MASK 0x00600000
126#define AD_GREEN_C_SHIFT 21
127#define AD_RED_C_MASK 0x00180000
128#define AD_RED_C_SHIFT 19
129#define AD_PALETTE 0x00040000
130#define AD_PIXEL_S_MASK 0x00030000
131#define AD_PIXEL_S_SHIFT 16
132#define AD_COMP_3_MASK 0x0000F000
133#define AD_COMP_3_SHIFT 12
134#define AD_COMP_2_MASK 0x00000F00
135#define AD_COMP_2_SHIFT 8
136#define AD_COMP_1_MASK 0x000000F0
137#define AD_COMP_1_SHIFT 4
138#define AD_COMP_0_MASK 0x0000000F
139#define AD_COMP_0_SHIFT 0
140
141#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
142 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
143 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
144 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
145 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
146 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
124 147
125unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel, 148unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
126 int monitor_port) 149 int monitor_port)
127{ 150{
128 static const unsigned long pixelformat[][3] = { 151 static const unsigned long pixelformat[][3] = {
129 {0x88882317, 0x88083218, 0x65052119}, 152 {
130 {0x88883316, 0x88082219, 0x65053118}, 153 MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
154 MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
155 MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
156 },
157 {
158 MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
159 MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
160 MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
161 },
131 }; 162 };
132 unsigned int pix_fmt, arch_monitor; 163 unsigned int arch_monitor;
133 164
165 /* The DVI port is mis-wired on revision 1 of this board. */
134 arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1; 166 arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
135 /* DVI port for board version 0x01 */ 167
136 168 switch (bits_per_pixel) {
137 if (bits_per_pixel == 32) 169 case 32:
138 pix_fmt = pixelformat[arch_monitor][0]; 170 return pixelformat[arch_monitor][0];
139 else if (bits_per_pixel == 24) 171 case 24:
140 pix_fmt = pixelformat[arch_monitor][1]; 172 return pixelformat[arch_monitor][1];
141 else if (bits_per_pixel == 16) 173 case 16:
142 pix_fmt = pixelformat[arch_monitor][2]; 174 return pixelformat[arch_monitor][2];
143 else 175 default:
144 pix_fmt = pixelformat[1][0]; 176 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
145 177 return 0;
146 return pix_fmt; 178 }
147} 179}
148 180
149void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base) 181void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
@@ -190,8 +222,7 @@ void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
190 } 222 }
191 223
192 /* Pixel Clock configuration */ 224 /* Pixel Clock configuration */
193 pr_debug("DIU: Bus Frequency = %d\n", get_busfreq()); 225 speed_ccb = fsl_get_sys_freq();
194 speed_ccb = get_busfreq();
195 226
196 /* Calculate the pixel clock with the smallest error */ 227 /* Calculate the pixel clock with the smallest error */
197 /* calculate the following in steps to avoid overflow */ 228 /* calculate the following in steps to avoid overflow */
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 53121f625068..57e954142c70 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -6,6 +6,7 @@
6 * with various broken implementations of this HW. 6 * with various broken implementations of this HW.
7 * 7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp. 8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
9 * 10 *
10 * This file is subject to the terms and conditions of the GNU General Public 11 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive 12 * License. See the file COPYING in the main directory of this archive
@@ -218,6 +219,28 @@ static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 valu
218 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value); 219 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
219} 220}
220 221
222static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
223{
224 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
225 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
226
227 if (tm >= 4)
228 offset += 0x1000 / 4;
229
230 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
231}
232
233static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
234{
235 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
236 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
237
238 if (tm >= 4)
239 offset += 0x1000 / 4;
240
241 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
242}
243
221static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg) 244static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
222{ 245{
223 unsigned int cpu = mpic_processor_id(mpic); 246 unsigned int cpu = mpic_processor_id(mpic);
@@ -268,6 +291,8 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
268#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v)) 291#define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
269#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i)) 292#define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
270#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v)) 293#define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
294#define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
295#define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
271#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i)) 296#define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
272#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v)) 297#define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
273#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r)) 298#define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
@@ -624,6 +649,13 @@ static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
624 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]); 649 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
625} 650}
626 651
652/* Determine if the linux irq is a timer */
653static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
654{
655 unsigned int src = virq_to_hw(irq);
656
657 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
658}
627 659
628/* Convert a cpu mask from logical to physical cpu numbers. */ 660/* Convert a cpu mask from logical to physical cpu numbers. */
629static inline u32 mpic_physmask(u32 cpumask) 661static inline u32 mpic_physmask(u32 cpumask)
@@ -810,6 +842,25 @@ static void mpic_end_ipi(struct irq_data *d)
810 842
811#endif /* CONFIG_SMP */ 843#endif /* CONFIG_SMP */
812 844
845static void mpic_unmask_tm(struct irq_data *d)
846{
847 struct mpic *mpic = mpic_from_irq_data(d);
848 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
849
850 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, irq, src);
851 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
852 mpic_tm_read(src);
853}
854
855static void mpic_mask_tm(struct irq_data *d)
856{
857 struct mpic *mpic = mpic_from_irq_data(d);
858 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
859
860 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
861 mpic_tm_read(src);
862}
863
813int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, 864int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
814 bool force) 865 bool force)
815{ 866{
@@ -936,6 +987,12 @@ static struct irq_chip mpic_ipi_chip = {
936}; 987};
937#endif /* CONFIG_SMP */ 988#endif /* CONFIG_SMP */
938 989
990static struct irq_chip mpic_tm_chip = {
991 .irq_mask = mpic_mask_tm,
992 .irq_unmask = mpic_unmask_tm,
993 .irq_eoi = mpic_end_irq,
994};
995
939#ifdef CONFIG_MPIC_U3_HT_IRQS 996#ifdef CONFIG_MPIC_U3_HT_IRQS
940static struct irq_chip mpic_irq_ht_chip = { 997static struct irq_chip mpic_irq_ht_chip = {
941 .irq_startup = mpic_startup_ht_irq, 998 .irq_startup = mpic_startup_ht_irq,
@@ -979,6 +1036,16 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
979 } 1036 }
980#endif /* CONFIG_SMP */ 1037#endif /* CONFIG_SMP */
981 1038
1039 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1040 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1041
1042 DBG("mpic: mapping as timer\n");
1043 irq_set_chip_data(virq, mpic);
1044 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1045 handle_fasteoi_irq);
1046 return 0;
1047 }
1048
982 if (hw >= mpic->irq_count) 1049 if (hw >= mpic->irq_count)
983 return -EINVAL; 1050 return -EINVAL;
984 1051
@@ -1019,6 +1086,7 @@ static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1019 irq_hw_number_t *out_hwirq, unsigned int *out_flags) 1086 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1020 1087
1021{ 1088{
1089 struct mpic *mpic = h->host_data;
1022 static unsigned char map_mpic_senses[4] = { 1090 static unsigned char map_mpic_senses[4] = {
1023 IRQ_TYPE_EDGE_RISING, 1091 IRQ_TYPE_EDGE_RISING,
1024 IRQ_TYPE_LEVEL_LOW, 1092 IRQ_TYPE_LEVEL_LOW,
@@ -1027,7 +1095,38 @@ static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1027 }; 1095 };
1028 1096
1029 *out_hwirq = intspec[0]; 1097 *out_hwirq = intspec[0];
1030 if (intsize > 1) { 1098 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1099 /*
1100 * Freescale MPIC with extended intspec:
1101 * First two cells are as usual. Third specifies
1102 * an "interrupt type". Fourth is type-specific data.
1103 *
1104 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1105 */
1106 switch (intspec[2]) {
1107 case 0:
1108 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1109 break;
1110 case 2:
1111 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1112 return -EINVAL;
1113
1114 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1115 break;
1116 case 3:
1117 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1118 return -EINVAL;
1119
1120 *out_hwirq = mpic->timer_vecs[intspec[0]];
1121 break;
1122 default:
1123 pr_debug("%s: unknown irq type %u\n",
1124 __func__, intspec[2]);
1125 return -EINVAL;
1126 }
1127
1128 *out_flags = map_mpic_senses[intspec[1] & 3];
1129 } else if (intsize > 1) {
1031 u32 mask = 0x3; 1130 u32 mask = 0x3;
1032 1131
1033 /* Apple invented a new race of encoding on machines with 1132 /* Apple invented a new race of encoding on machines with
@@ -1103,6 +1202,9 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1103 mpic->hc_ipi.name = name; 1202 mpic->hc_ipi.name = name;
1104#endif /* CONFIG_SMP */ 1203#endif /* CONFIG_SMP */
1105 1204
1205 mpic->hc_tm = mpic_tm_chip;
1206 mpic->hc_tm.name = name;
1207
1106 mpic->flags = flags; 1208 mpic->flags = flags;
1107 mpic->isu_size = isu_size; 1209 mpic->isu_size = isu_size;
1108 mpic->irq_count = irq_count; 1210 mpic->irq_count = irq_count;
@@ -1113,10 +1215,14 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1113 else 1215 else
1114 intvec_top = 255; 1216 intvec_top = 255;
1115 1217
1116 mpic->timer_vecs[0] = intvec_top - 8; 1218 mpic->timer_vecs[0] = intvec_top - 12;
1117 mpic->timer_vecs[1] = intvec_top - 7; 1219 mpic->timer_vecs[1] = intvec_top - 11;
1118 mpic->timer_vecs[2] = intvec_top - 6; 1220 mpic->timer_vecs[2] = intvec_top - 10;
1119 mpic->timer_vecs[3] = intvec_top - 5; 1221 mpic->timer_vecs[3] = intvec_top - 9;
1222 mpic->timer_vecs[4] = intvec_top - 8;
1223 mpic->timer_vecs[5] = intvec_top - 7;
1224 mpic->timer_vecs[6] = intvec_top - 6;
1225 mpic->timer_vecs[7] = intvec_top - 5;
1120 mpic->ipi_vecs[0] = intvec_top - 4; 1226 mpic->ipi_vecs[0] = intvec_top - 4;
1121 mpic->ipi_vecs[1] = intvec_top - 3; 1227 mpic->ipi_vecs[1] = intvec_top - 3;
1122 mpic->ipi_vecs[2] = intvec_top - 2; 1228 mpic->ipi_vecs[2] = intvec_top - 2;
@@ -1126,6 +1232,8 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1126 /* Check for "big-endian" in device-tree */ 1232 /* Check for "big-endian" in device-tree */
1127 if (node && of_get_property(node, "big-endian", NULL) != NULL) 1233 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1128 mpic->flags |= MPIC_BIG_ENDIAN; 1234 mpic->flags |= MPIC_BIG_ENDIAN;
1235 if (node && of_device_is_compatible(node, "fsl,mpic"))
1236 mpic->flags |= MPIC_FSL;
1129 1237
1130 /* Look for protected sources */ 1238 /* Look for protected sources */
1131 if (node) { 1239 if (node) {
@@ -1317,15 +1425,17 @@ void __init mpic_init(struct mpic *mpic)
1317 /* Set current processor priority to max */ 1425 /* Set current processor priority to max */
1318 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf); 1426 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1319 1427
1320 /* Initialize timers: just disable them all */ 1428 /* Initialize timers to our reserved vectors and mask them for now */
1321 for (i = 0; i < 4; i++) { 1429 for (i = 0; i < 4; i++) {
1322 mpic_write(mpic->tmregs, 1430 mpic_write(mpic->tmregs,
1323 i * MPIC_INFO(TIMER_STRIDE) + 1431 i * MPIC_INFO(TIMER_STRIDE) +
1324 MPIC_INFO(TIMER_DESTINATION), 0); 1432 MPIC_INFO(TIMER_DESTINATION),
1433 1 << hard_smp_processor_id());
1325 mpic_write(mpic->tmregs, 1434 mpic_write(mpic->tmregs,
1326 i * MPIC_INFO(TIMER_STRIDE) + 1435 i * MPIC_INFO(TIMER_STRIDE) +
1327 MPIC_INFO(TIMER_VECTOR_PRI), 1436 MPIC_INFO(TIMER_VECTOR_PRI),
1328 MPIC_VECPRI_MASK | 1437 MPIC_VECPRI_MASK |
1438 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1329 (mpic->timer_vecs[0] + i)); 1439 (mpic->timer_vecs[0] + i));
1330 } 1440 }
1331 1441
@@ -1434,6 +1544,11 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1434 ~MPIC_VECPRI_PRIORITY_MASK; 1544 ~MPIC_VECPRI_PRIORITY_MASK;
1435 mpic_ipi_write(src - mpic->ipi_vecs[0], 1545 mpic_ipi_write(src - mpic->ipi_vecs[0],
1436 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1546 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1547 } else if (mpic_is_tm(mpic, irq)) {
1548 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1549 ~MPIC_VECPRI_PRIORITY_MASK;
1550 mpic_tm_write(src - mpic->timer_vecs[0],
1551 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1437 } else { 1552 } else {
1438 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) 1553 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1439 & ~MPIC_VECPRI_PRIORITY_MASK; 1554 & ~MPIC_VECPRI_PRIORITY_MASK;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 23:01:04 -0500