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authorLinus Torvalds <torvalds@linux-foundation.org>2011-01-21 16:38:26 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-01-21 16:38:26 -0500
commit0f5c2ac58f22fd41deaeeb45ee752d4ae55f0d01 (patch)
tree6e13ef4d7247e53d7a0f18e04549a8847cc80214 /arch
parentcfd74486eace27a0899b30529d01bc1a09a5b973 (diff)
parentdfff95c394b0dd977a6b65bd52b99703fae94d9b (diff)
Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (37 commits) um: Use generic irq Kconfig tile: Use generic irq Kconfig sparc: Use generic irq Kconfig score: Use generic irq Kconfig powerpc: Use generic irq Kconfig parisc: Use generic irq Kconfig mn10300: Use generic irq Kconfig microblaze: Use generic irq Kconfig m68knommu: Use generic irq Kconfig ia64: Use generic irq Kconfig frv: Use generic irq Kconfig blackfin: Use generic irq Kconfig alpha: Use generic irq Kconfig genirq: Remove __do_IRQ m32r: Convert to generic irq Kconfig m32r: Convert usrv platform irq handling m32r: Convert opsput_lcdpld irq chip m32r: Convert opsput lanpld irq chip m32r: Convert opsput pld irq chip m32r: Convert opsput irq chip ...
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/Kconfig19
-rw-r--r--arch/blackfin/Kconfig17
-rw-r--r--arch/cris/Kconfig6
-rw-r--r--arch/cris/arch-v10/kernel/irq.c41
-rw-r--r--arch/cris/arch-v32/kernel/irq.c50
-rw-r--r--arch/cris/kernel/irq.c6
-rw-r--r--arch/frv/Kconfig9
-rw-r--r--arch/h8300/Kconfig6
-rw-r--r--arch/h8300/kernel/irq.c50
-rw-r--r--arch/ia64/Kconfig26
-rw-r--r--arch/m32r/Kconfig11
-rw-r--r--arch/m32r/kernel/irq.c10
-rw-r--r--arch/m32r/platforms/m32104ut/setup.c58
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c214
-rw-r--r--arch/m32r/platforms/mappi/setup.c78
-rw-r--r--arch/m32r/platforms/mappi2/setup.c89
-rw-r--r--arch/m32r/platforms/mappi3/setup.c92
-rw-r--r--arch/m32r/platforms/oaks32r/setup.c65
-rw-r--r--arch/m32r/platforms/opsput/setup.c220
-rw-r--r--arch/m32r/platforms/usrv/setup.c115
-rw-r--r--arch/m68knommu/Kconfig9
-rw-r--r--arch/microblaze/Kconfig11
-rw-r--r--arch/mips/Kconfig3
-rw-r--r--arch/mn10300/Kconfig8
-rw-r--r--arch/parisc/Kconfig18
-rw-r--r--arch/powerpc/Kconfig28
-rw-r--r--arch/score/Kconfig10
-rw-r--r--arch/sparc/Kconfig9
-rw-r--r--arch/tile/Kconfig53
-rw-r--r--arch/um/Kconfig.common6
-rw-r--r--arch/um/Kconfig.um3
31 files changed, 428 insertions, 912 deletions
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index fc95ee1bcf6f..47f63d480141 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -8,6 +8,9 @@ config ALPHA
8 select HAVE_IRQ_WORK 8 select HAVE_IRQ_WORK
9 select HAVE_PERF_EVENTS 9 select HAVE_PERF_EVENTS
10 select HAVE_DMA_ATTRS 10 select HAVE_DMA_ATTRS
11 select HAVE_GENERIC_HARDIRQS
12 select GENERIC_IRQ_PROBE
13 select AUTO_IRQ_AFFINITY if SMP
11 help 14 help
12 The Alpha is a 64-bit general-purpose processor designed and 15 The Alpha is a 64-bit general-purpose processor designed and
13 marketed by the Digital Equipment Corporation of blessed memory, 16 marketed by the Digital Equipment Corporation of blessed memory,
@@ -68,22 +71,6 @@ config GENERIC_IOMAP
68 bool 71 bool
69 default n 72 default n
70 73
71config GENERIC_HARDIRQS_NO__DO_IRQ
72 def_bool y
73
74config GENERIC_HARDIRQS
75 bool
76 default y
77
78config GENERIC_IRQ_PROBE
79 bool
80 default y
81
82config AUTO_IRQ_AFFINITY
83 bool
84 depends on SMP
85 default y
86
87source "init/Kconfig" 74source "init/Kconfig"
88source "kernel/Kconfig.freezer" 75source "kernel/Kconfig.freezer"
89 76
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 0a221d48152d..c09577ddc3c5 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -30,6 +30,9 @@ config BLACKFIN
30 select HAVE_KERNEL_LZO if RAMKERNEL 30 select HAVE_KERNEL_LZO if RAMKERNEL
31 select HAVE_OPROFILE 31 select HAVE_OPROFILE
32 select ARCH_WANT_OPTIONAL_GPIOLIB 32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select HAVE_GENERIC_HARDIRQS
34 select GENERIC_IRQ_PROBE
35 select IRQ_PER_CPU if SMP
33 36
34config GENERIC_CSUM 37config GENERIC_CSUM
35 def_bool y 38 def_bool y
@@ -44,15 +47,6 @@ config ZONE_DMA
44config GENERIC_FIND_NEXT_BIT 47config GENERIC_FIND_NEXT_BIT
45 def_bool y 48 def_bool y
46 49
47config GENERIC_HARDIRQS
48 def_bool y
49
50config GENERIC_IRQ_PROBE
51 def_bool y
52
53config GENERIC_HARDIRQS_NO__DO_IRQ
54 def_bool y
55
56config GENERIC_GPIO 50config GENERIC_GPIO
57 def_bool y 51 def_bool y
58 52
@@ -254,11 +248,6 @@ config HOTPLUG_CPU
254 depends on SMP && HOTPLUG 248 depends on SMP && HOTPLUG
255 default y 249 default y
256 250
257config IRQ_PER_CPU
258 bool
259 depends on SMP
260 default y
261
262config HAVE_LEGACY_PER_CPU_AREA 251config HAVE_LEGACY_PER_CPU_AREA
263 def_bool y 252 def_bool y
264 depends on SMP 253 depends on SMP
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 613e62831c55..0a7a4c11d8b1 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -54,6 +54,8 @@ config CRIS
54 bool 54 bool
55 default y 55 default y
56 select HAVE_IDE 56 select HAVE_IDE
57 select HAVE_GENERIC_HARDIRQS
58 select GENERIC_HARDIRQS_NO_DEPRECATED
57 59
58config HZ 60config HZ
59 int 61 int
@@ -67,10 +69,6 @@ menu "General setup"
67 69
68source "fs/Kconfig.binfmt" 70source "fs/Kconfig.binfmt"
69 71
70config GENERIC_HARDIRQS
71 bool
72 default y
73
74config ETRAX_CMDLINE 72config ETRAX_CMDLINE
75 string "Kernel command line" 73 string "Kernel command line"
76 default "root=/dev/mtdblock3" 74 default "root=/dev/mtdblock3"
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c
index a0c0df8be9c8..7328a7cf7449 100644
--- a/arch/cris/arch-v10/kernel/irq.c
+++ b/arch/cris/arch-v10/kernel/irq.c
@@ -104,43 +104,21 @@ static void (*interrupt[NR_IRQS])(void) = {
104 IRQ31_interrupt 104 IRQ31_interrupt
105}; 105};
106 106
107static void enable_crisv10_irq(unsigned int irq); 107static void enable_crisv10_irq(struct irq_data *data)
108
109static unsigned int startup_crisv10_irq(unsigned int irq)
110{
111 enable_crisv10_irq(irq);
112 return 0;
113}
114
115#define shutdown_crisv10_irq disable_crisv10_irq
116
117static void enable_crisv10_irq(unsigned int irq)
118{
119 crisv10_unmask_irq(irq);
120}
121
122static void disable_crisv10_irq(unsigned int irq)
123{
124 crisv10_mask_irq(irq);
125}
126
127static void ack_crisv10_irq(unsigned int irq)
128{ 108{
109 crisv10_unmask_irq(data->irq);
129} 110}
130 111
131static void end_crisv10_irq(unsigned int irq) 112static void disable_crisv10_irq(struct irq_data *data)
132{ 113{
114 crisv10_mask_irq(data->irq);
133} 115}
134 116
135static struct irq_chip crisv10_irq_type = { 117static struct irq_chip crisv10_irq_type = {
136 .name = "CRISv10", 118 .name = "CRISv10",
137 .startup = startup_crisv10_irq, 119 .irq_shutdown = disable_crisv10_irq,
138 .shutdown = shutdown_crisv10_irq, 120 .irq_enable = enable_crisv10_irq,
139 .enable = enable_crisv10_irq, 121 .irq_disable = disable_crisv10_irq,
140 .disable = disable_crisv10_irq,
141 .ack = ack_crisv10_irq,
142 .end = end_crisv10_irq,
143 .set_affinity = NULL
144}; 122};
145 123
146void weird_irq(void); 124void weird_irq(void);
@@ -221,7 +199,8 @@ init_IRQ(void)
221 199
222 /* Initialize IRQ handler descriptors. */ 200 /* Initialize IRQ handler descriptors. */
223 for(i = 2; i < NR_IRQS; i++) { 201 for(i = 2; i < NR_IRQS; i++) {
224 irq_desc[i].chip = &crisv10_irq_type; 202 set_irq_desc_and_handler(i, &crisv10_irq_type,
203 handle_simple_irq);
225 set_int_vector(i, interrupt[i]); 204 set_int_vector(i, interrupt[i]);
226 } 205 }
227 206
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index 2ed48ae3d313..0ad9db5126c7 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -291,54 +291,33 @@ void crisv32_unmask_irq(int irq)
291} 291}
292 292
293 293
294static unsigned int startup_crisv32_irq(unsigned int irq) 294static void enable_crisv32_irq(struct irq_data *data)
295{ 295{
296 crisv32_unmask_irq(irq); 296 crisv32_unmask_irq(data->irq);
297 return 0;
298}
299
300static void shutdown_crisv32_irq(unsigned int irq)
301{
302 crisv32_mask_irq(irq);
303} 297}
304 298
305static void enable_crisv32_irq(unsigned int irq) 299static void disable_crisv32_irq(struct irq_data *data)
306{ 300{
307 crisv32_unmask_irq(irq); 301 crisv32_mask_irq(data->irq);
308} 302}
309 303
310static void disable_crisv32_irq(unsigned int irq) 304static int set_affinity_crisv32_irq(struct irq_data *data,
311{ 305 const struct cpumask *dest, bool force)
312 crisv32_mask_irq(irq);
313}
314
315static void ack_crisv32_irq(unsigned int irq)
316{
317}
318
319static void end_crisv32_irq(unsigned int irq)
320{
321}
322
323int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
324{ 306{
325 unsigned long flags; 307 unsigned long flags;
308
326 spin_lock_irqsave(&irq_lock, flags); 309 spin_lock_irqsave(&irq_lock, flags);
327 irq_allocations[irq - FIRST_IRQ].mask = *dest; 310 irq_allocations[data->irq - FIRST_IRQ].mask = *dest;
328 spin_unlock_irqrestore(&irq_lock, flags); 311 spin_unlock_irqrestore(&irq_lock, flags);
329
330 return 0; 312 return 0;
331} 313}
332 314
333static struct irq_chip crisv32_irq_type = { 315static struct irq_chip crisv32_irq_type = {
334 .name = "CRISv32", 316 .name = "CRISv32",
335 .startup = startup_crisv32_irq, 317 .irq_shutdown = disable_crisv32_irq,
336 .shutdown = shutdown_crisv32_irq, 318 .irq_enable = enable_crisv32_irq,
337 .enable = enable_crisv32_irq, 319 .irq_disable = disable_crisv32_irq,
338 .disable = disable_crisv32_irq, 320 .irq_set_affinity = set_affinity_crisv32_irq,
339 .ack = ack_crisv32_irq,
340 .end = end_crisv32_irq,
341 .set_affinity = set_affinity_crisv32_irq
342}; 321};
343 322
344void 323void
@@ -472,7 +451,8 @@ init_IRQ(void)
472 451
473 /* Point all IRQ's to bad handlers. */ 452 /* Point all IRQ's to bad handlers. */
474 for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) { 453 for (i = FIRST_IRQ, j = 0; j < NR_IRQS; i++, j++) {
475 irq_desc[j].chip = &crisv32_irq_type; 454 set_irq_chip_and_handler(j, &crisv32_irq_type,
455 handle_simple_irq);
476 set_exception_vector(i, interrupt[j]); 456 set_exception_vector(i, interrupt[j]);
477 } 457 }
478 458
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
index 469f7f9d62e0..c346952f06dc 100644
--- a/arch/cris/kernel/irq.c
+++ b/arch/cris/kernel/irq.c
@@ -62,7 +62,7 @@ int show_interrupts(struct seq_file *p, void *v)
62 for_each_online_cpu(j) 62 for_each_online_cpu(j)
63 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 63 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
64#endif 64#endif
65 seq_printf(p, " %14s", irq_desc[i].chip->name); 65 seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
66 seq_printf(p, " %s", action->name); 66 seq_printf(p, " %s", action->name);
67 67
68 for (action=action->next; action; action = action->next) 68 for (action=action->next; action; action = action->next)
@@ -93,8 +93,8 @@ asmlinkage void do_IRQ(int irq, struct pt_regs * regs)
93 printk("do_IRQ: stack overflow: %lX\n", sp); 93 printk("do_IRQ: stack overflow: %lX\n", sp);
94 show_stack(NULL, (unsigned long *)sp); 94 show_stack(NULL, (unsigned long *)sp);
95 } 95 }
96 __do_IRQ(irq); 96 generic_handle_irq(irq);
97 irq_exit(); 97 irq_exit();
98 set_irq_regs(old_regs); 98 set_irq_regs(old_regs);
99} 99}
100 100
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index f6bcb039cd6d..747499a1b31e 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -5,6 +5,7 @@ config FRV
5 select HAVE_ARCH_TRACEHOOK 5 select HAVE_ARCH_TRACEHOOK
6 select HAVE_IRQ_WORK 6 select HAVE_IRQ_WORK
7 select HAVE_PERF_EVENTS 7 select HAVE_PERF_EVENTS
8 select HAVE_GENERIC_HARDIRQS
8 9
9config ZONE_DMA 10config ZONE_DMA
10 bool 11 bool
@@ -29,14 +30,6 @@ config GENERIC_CALIBRATE_DELAY
29 bool 30 bool
30 default n 31 default n
31 32
32config GENERIC_HARDIRQS
33 bool
34 default y
35
36config GENERIC_HARDIRQS_NO__DO_IRQ
37 bool
38 default y
39
40config TIME_LOW_RES 33config TIME_LOW_RES
41 bool 34 bool
42 default y 35 default y
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 65f897d8c1e9..6df692d1475f 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -2,6 +2,8 @@ config H8300
2 bool 2 bool
3 default y 3 default y
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_GENERIC_HARDIRQS
6 select GENERIC_HARDIRQS_NO_DEPRECATED
5 7
6config SYMBOL_PREFIX 8config SYMBOL_PREFIX
7 string 9 string
@@ -47,10 +49,6 @@ config GENERIC_HWEIGHT
47 bool 49 bool
48 default y 50 default y
49 51
50config GENERIC_HARDIRQS
51 bool
52 default y
53
54config GENERIC_CALIBRATE_DELAY 52config GENERIC_CALIBRATE_DELAY
55 bool 53 bool
56 default y 54 default y
diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c
index c25dc2c2b1da..7643d39925d6 100644
--- a/arch/h8300/kernel/irq.c
+++ b/arch/h8300/kernel/irq.c
@@ -38,34 +38,30 @@ static inline int is_ext_irq(unsigned int irq)
38 return (irq >= EXT_IRQ0 && irq <= (EXT_IRQ0 + EXT_IRQS)); 38 return (irq >= EXT_IRQ0 && irq <= (EXT_IRQ0 + EXT_IRQS));
39} 39}
40 40
41static void h8300_enable_irq(unsigned int irq) 41static void h8300_enable_irq(struct irq_data *data)
42{ 42{
43 if (is_ext_irq(irq)) 43 if (is_ext_irq(data->irq))
44 IER_REGS |= 1 << (irq - EXT_IRQ0); 44 IER_REGS |= 1 << (data->irq - EXT_IRQ0);
45} 45}
46 46
47static void h8300_disable_irq(unsigned int irq) 47static void h8300_disable_irq(struct irq_data *data)
48{ 48{
49 if (is_ext_irq(irq)) 49 if (is_ext_irq(data->irq))
50 IER_REGS &= ~(1 << (irq - EXT_IRQ0)); 50 IER_REGS &= ~(1 << (data->irq - EXT_IRQ0));
51} 51}
52 52
53static void h8300_end_irq(unsigned int irq) 53static unsigned int h8300_startup_irq(struct irq_data *data)
54{ 54{
55} 55 if (is_ext_irq(data->irq))
56 56 return h8300_enable_irq_pin(data->irq);
57static unsigned int h8300_startup_irq(unsigned int irq)
58{
59 if (is_ext_irq(irq))
60 return h8300_enable_irq_pin(irq);
61 else 57 else
62 return 0; 58 return 0;
63} 59}
64 60
65static void h8300_shutdown_irq(unsigned int irq) 61static void h8300_shutdown_irq(struct irq_data *data)
66{ 62{
67 if (is_ext_irq(irq)) 63 if (is_ext_irq(data->irq))
68 h8300_disable_irq_pin(irq); 64 h8300_disable_irq_pin(data->irq);
69} 65}
70 66
71/* 67/*
@@ -73,12 +69,10 @@ static void h8300_shutdown_irq(unsigned int irq)
73 */ 69 */
74struct irq_chip h8300irq_chip = { 70struct irq_chip h8300irq_chip = {
75 .name = "H8300-INTC", 71 .name = "H8300-INTC",
76 .startup = h8300_startup_irq, 72 .irq_startup = h8300_startup_irq,
77 .shutdown = h8300_shutdown_irq, 73 .irq_shutdown = h8300_shutdown_irq,
78 .enable = h8300_enable_irq, 74 .irq_enable = h8300_enable_irq,
79 .disable = h8300_disable_irq, 75 .irq_disable = h8300_disable_irq,
80 .ack = NULL,
81 .end = h8300_end_irq,
82}; 76};
83 77
84#if defined(CONFIG_RAMKERNEL) 78#if defined(CONFIG_RAMKERNEL)
@@ -160,18 +154,14 @@ void __init init_IRQ(void)
160 154
161 setup_vector(); 155 setup_vector();
162 156
163 for (c = 0; c < NR_IRQS; c++) { 157 for (c = 0; c < NR_IRQS; c++)
164 irq_desc[c].status = IRQ_DISABLED; 158 set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq);
165 irq_desc[c].action = NULL;
166 irq_desc[c].depth = 1;
167 irq_desc[c].chip = &h8300irq_chip;
168 }
169} 159}
170 160
171asmlinkage void do_IRQ(int irq) 161asmlinkage void do_IRQ(int irq)
172{ 162{
173 irq_enter(); 163 irq_enter();
174 __do_IRQ(irq); 164 generic_handle_irq(irq);
175 irq_exit(); 165 irq_exit();
176} 166}
177 167
@@ -192,7 +182,7 @@ int show_interrupts(struct seq_file *p, void *v)
192 goto unlock; 182 goto unlock;
193 seq_printf(p, "%3d: ",i); 183 seq_printf(p, "%3d: ",i);
194 seq_printf(p, "%10u ", kstat_irqs(i)); 184 seq_printf(p, "%10u ", kstat_irqs(i));
195 seq_printf(p, " %14s", irq_desc[i].chip->name); 185 seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
196 seq_printf(p, "-%-8s", irq_desc[i].name); 186 seq_printf(p, "-%-8s", irq_desc[i].name);
197 seq_printf(p, " %s", action->name); 187 seq_printf(p, " %s", action->name);
198 188
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index e0f5b6d7f849..fcf3b437a2d9 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -22,6 +22,10 @@ config IA64
22 select HAVE_KVM 22 select HAVE_KVM
23 select HAVE_ARCH_TRACEHOOK 23 select HAVE_ARCH_TRACEHOOK
24 select HAVE_DMA_API_DEBUG 24 select HAVE_DMA_API_DEBUG
25 select HAVE_GENERIC_HARDIRQS
26 select GENERIC_IRQ_PROBE
27 select GENERIC_PENDING_IRQ if SMP
28 select IRQ_PER_CPU
25 default y 29 default y
26 help 30 help
27 The Itanium Processor Family is Intel's 64-bit successor to 31 The Itanium Processor Family is Intel's 64-bit successor to
@@ -678,28 +682,6 @@ source "arch/ia64/kvm/Kconfig"
678 682
679source "lib/Kconfig" 683source "lib/Kconfig"
680 684
681#
682# Use the generic interrupt handling code in kernel/irq/:
683#
684config GENERIC_HARDIRQS
685 def_bool y
686
687config GENERIC_HARDIRQS_NO__DO_IRQ
688 def_bool y
689
690config GENERIC_IRQ_PROBE
691 bool
692 default y
693
694config GENERIC_PENDING_IRQ
695 bool
696 depends on GENERIC_HARDIRQS && SMP
697 default y
698
699config IRQ_PER_CPU
700 bool
701 default y
702
703config IOMMU_HELPER 685config IOMMU_HELPER
704 def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB) 686 def_bool (IA64_HP_ZX1 || IA64_HP_ZX1_SWIOTLB || IA64_GENERIC || SWIOTLB)
705 687
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 5c291d65196b..ef4c1e442be3 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -7,6 +7,9 @@ config M32R
7 select HAVE_KERNEL_GZIP 7 select HAVE_KERNEL_GZIP
8 select HAVE_KERNEL_BZIP2 8 select HAVE_KERNEL_BZIP2
9 select HAVE_KERNEL_LZMA 9 select HAVE_KERNEL_LZMA
10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_HARDIRQS_NO_DEPRECATED
12 select GENERIC_IRQ_PROBE
10 13
11config SBUS 14config SBUS
12 bool 15 bool
@@ -19,14 +22,6 @@ config ZONE_DMA
19 bool 22 bool
20 default y 23 default y
21 24
22config GENERIC_HARDIRQS
23 bool
24 default y
25
26config GENERIC_IRQ_PROBE
27 bool
28 default y
29
30config NO_IOPORT 25config NO_IOPORT
31 def_bool y 26 def_bool y
32 27
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
index 7db26f1f082d..f745c1287f3a 100644
--- a/arch/m32r/kernel/irq.c
+++ b/arch/m32r/kernel/irq.c
@@ -40,8 +40,10 @@ int show_interrupts(struct seq_file *p, void *v)
40 } 40 }
41 41
42 if (i < NR_IRQS) { 42 if (i < NR_IRQS) {
43 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 43 struct irq_desc *desc = irq_to_desc(i);
44 action = irq_desc[i].action; 44
45 raw_spin_lock_irqsave(&desc->lock, flags);
46 action = desc->action;
45 if (!action) 47 if (!action)
46 goto skip; 48 goto skip;
47 seq_printf(p, "%3d: ",i); 49 seq_printf(p, "%3d: ",i);
@@ -51,7 +53,7 @@ int show_interrupts(struct seq_file *p, void *v)
51 for_each_online_cpu(j) 53 for_each_online_cpu(j)
52 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 54 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
53#endif 55#endif
54 seq_printf(p, " %14s", irq_desc[i].chip->name); 56 seq_printf(p, " %14s", desc->irq_data.chip->name);
55 seq_printf(p, " %s", action->name); 57 seq_printf(p, " %s", action->name);
56 58
57 for (action=action->next; action; action = action->next) 59 for (action=action->next; action; action = action->next)
@@ -59,7 +61,7 @@ int show_interrupts(struct seq_file *p, void *v)
59 61
60 seq_putc(p, '\n'); 62 seq_putc(p, '\n');
61skip: 63skip:
62 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 64 raw_spin_unlock_irqrestore(&desc->lock, flags);
63 } 65 }
64 return 0; 66 return 0;
65} 67}
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 402a59d7219b..4a693d02c1e1 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -39,39 +39,30 @@ static void enable_m32104ut_irq(unsigned int irq)
39 outl(data, port); 39 outl(data, port);
40} 40}
41 41
42static void mask_and_ack_m32104ut(unsigned int irq) 42static void mask_m32104ut_irq(struct irq_data *data)
43{ 43{
44 disable_m32104ut_irq(irq); 44 disable_m32104ut_irq(data->irq);
45} 45}
46 46
47static void end_m32104ut_irq(unsigned int irq) 47static void unmask_m32104ut_irq(struct irq_data *data)
48{ 48{
49 enable_m32104ut_irq(irq); 49 enable_m32104ut_irq(data->irq);
50} 50}
51 51
52static unsigned int startup_m32104ut_irq(unsigned int irq) 52static void shutdown_m32104ut_irq(struct irq_data *data)
53{ 53{
54 enable_m32104ut_irq(irq); 54 unsigned int irq = data->irq;
55 return (0); 55 unsigned long port = irq2port(irq);
56}
57
58static void shutdown_m32104ut_irq(unsigned int irq)
59{
60 unsigned long port;
61 56
62 port = irq2port(irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 57 outl(M32R_ICUCR_ILEVEL7, port);
64} 58}
65 59
66static struct irq_chip m32104ut_irq_type = 60static struct irq_chip m32104ut_irq_type =
67{ 61{
68 .name = "M32104UT-IRQ", 62 .name = "M32104UT-IRQ",
69 .startup = startup_m32104ut_irq, 63 .irq_shutdown = shutdown_m32104ut_irq,
70 .shutdown = shutdown_m32104ut_irq, 64 .irq_unmask = unmask_m32104ut_irq,
71 .enable = enable_m32104ut_irq, 65 .irq_mask = mask_m32104ut_irq,
72 .disable = disable_m32104ut_irq,
73 .ack = mask_and_ack_m32104ut,
74 .end = end_m32104ut_irq
75}; 66};
76 67
77void __init init_IRQ(void) 68void __init init_IRQ(void)
@@ -85,36 +76,29 @@ void __init init_IRQ(void)
85 76
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 79 set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &m32104ut_irq_type; 80 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0; 81 /* "H" level sense */
91 irq_desc[M32R_IRQ_INT0].depth = 1; 82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; /* "H" level sense */
93 disable_m32104ut_irq(M32R_IRQ_INT0); 83 disable_m32104ut_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 84#endif /* CONFIG_SMC91X */
95 85
96 /* MFT2 : system timer */ 86 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 87 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &m32104ut_irq_type; 88 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_m32104ut_irq(M32R_IRQ_MFT2); 90 disable_m32104ut_irq(M32R_IRQ_MFT2);
103 91
104#ifdef CONFIG_SERIAL_M32R_SIO 92#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 93 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 94 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &m32104ut_irq_type; 95 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
111 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 97 disable_m32104ut_irq(M32R_IRQ_SIO0_R);
112 98
113 /* SIO0_S : uart send data */ 99 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 100 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &m32104ut_irq_type; 101 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
119 disable_m32104ut_irq(M32R_IRQ_SIO0_S); 103 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
120#endif /* CONFIG_SERIAL_M32R_SIO */ 104#endif /* CONFIG_SERIAL_M32R_SIO */
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 80b1a026795a..2074bcc841eb 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -45,39 +45,30 @@ static void enable_m32700ut_irq(unsigned int irq)
45 outl(data, port); 45 outl(data, port);
46} 46}
47 47
48static void mask_and_ack_m32700ut(unsigned int irq) 48static void mask_m32700ut(struct irq_data *data)
49{ 49{
50 disable_m32700ut_irq(irq); 50 disable_m32700ut_irq(data->irq);
51} 51}
52 52
53static void end_m32700ut_irq(unsigned int irq) 53static void unmask_m32700ut(struct irq_data *data)
54{ 54{
55 enable_m32700ut_irq(irq); 55 enable_m32700ut_irq(data->irq);
56} 56}
57 57
58static unsigned int startup_m32700ut_irq(unsigned int irq) 58static void shutdown_m32700ut(struct irq_data *data)
59{
60 enable_m32700ut_irq(irq);
61 return (0);
62}
63
64static void shutdown_m32700ut_irq(unsigned int irq)
65{ 59{
66 unsigned long port; 60 unsigned long port;
67 61
68 port = irq2port(irq); 62 port = irq2port(data->irq);
69 outl(M32R_ICUCR_ILEVEL7, port); 63 outl(M32R_ICUCR_ILEVEL7, port);
70} 64}
71 65
72static struct irq_chip m32700ut_irq_type = 66static struct irq_chip m32700ut_irq_type =
73{ 67{
74 .name = "M32700UT-IRQ", 68 .name = "M32700UT-IRQ",
75 .startup = startup_m32700ut_irq, 69 .irq_shutdown = shutdown_m32700ut,
76 .shutdown = shutdown_m32700ut_irq, 70 .irq_mask = mask_m32700ut,
77 .enable = enable_m32700ut_irq, 71 .irq_unmask = unmask_m32700ut
78 .disable = disable_m32700ut_irq,
79 .ack = mask_and_ack_m32700ut,
80 .end = end_m32700ut_irq
81}; 72};
82 73
83/* 74/*
@@ -99,7 +90,6 @@ static void disable_m32700ut_pld_irq(unsigned int irq)
99 unsigned int pldirq; 90 unsigned int pldirq;
100 91
101 pldirq = irq2pldirq(irq); 92 pldirq = irq2pldirq(irq);
102// disable_m32700ut_irq(M32R_IRQ_INT1);
103 port = pldirq2port(pldirq); 93 port = pldirq2port(pldirq);
104 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 94 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
105 outw(data, port); 95 outw(data, port);
@@ -111,50 +101,38 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
111 unsigned int pldirq; 101 unsigned int pldirq;
112 102
113 pldirq = irq2pldirq(irq); 103 pldirq = irq2pldirq(irq);
114// enable_m32700ut_irq(M32R_IRQ_INT1);
115 port = pldirq2port(pldirq); 104 port = pldirq2port(pldirq);
116 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
117 outw(data, port); 106 outw(data, port);
118} 107}
119 108
120static void mask_and_ack_m32700ut_pld(unsigned int irq) 109static void mask_m32700ut_pld(struct irq_data *data)
121{
122 disable_m32700ut_pld_irq(irq);
123// mask_and_ack_m32700ut(M32R_IRQ_INT1);
124}
125
126static void end_m32700ut_pld_irq(unsigned int irq)
127{ 110{
128 enable_m32700ut_pld_irq(irq); 111 disable_m32700ut_pld_irq(data->irq);
129 end_m32700ut_irq(M32R_IRQ_INT1);
130} 112}
131 113
132static unsigned int startup_m32700ut_pld_irq(unsigned int irq) 114static void unmask_m32700ut_pld(struct irq_data *data)
133{ 115{
134 enable_m32700ut_pld_irq(irq); 116 enable_m32700ut_pld_irq(data->irq);
135 return (0); 117 enable_m32700ut_irq(M32R_IRQ_INT1);
136} 118}
137 119
138static void shutdown_m32700ut_pld_irq(unsigned int irq) 120static void shutdown_m32700ut_pld_irq(struct irq_data *data)
139{ 121{
140 unsigned long port; 122 unsigned long port;
141 unsigned int pldirq; 123 unsigned int pldirq;
142 124
143 pldirq = irq2pldirq(irq); 125 pldirq = irq2pldirq(data->irq);
144// shutdown_m32700ut_irq(M32R_IRQ_INT1);
145 port = pldirq2port(pldirq); 126 port = pldirq2port(pldirq);
146 outw(PLD_ICUCR_ILEVEL7, port); 127 outw(PLD_ICUCR_ILEVEL7, port);
147} 128}
148 129
149static struct irq_chip m32700ut_pld_irq_type = 130static struct irq_chip m32700ut_pld_irq_type =
150{ 131{
151 .name = "M32700UT-PLD-IRQ", 132 .name = "M32700UT-PLD-IRQ",
152 .startup = startup_m32700ut_pld_irq, 133 .irq_shutdown = shutdown_m32700ut_pld_irq,
153 .shutdown = shutdown_m32700ut_pld_irq, 134 .irq_mask = mask_m32700ut_pld,
154 .enable = enable_m32700ut_pld_irq, 135 .irq_unmask = unmask_m32700ut_pld,
155 .disable = disable_m32700ut_pld_irq,
156 .ack = mask_and_ack_m32700ut_pld,
157 .end = end_m32700ut_pld_irq
158}; 136};
159 137
160/* 138/*
@@ -188,42 +166,33 @@ static void enable_m32700ut_lanpld_irq(unsigned int irq)
188 outw(data, port); 166 outw(data, port);
189} 167}
190 168
191static void mask_and_ack_m32700ut_lanpld(unsigned int irq) 169static void mask_m32700ut_lanpld(struct irq_data *data)
192{ 170{
193 disable_m32700ut_lanpld_irq(irq); 171 disable_m32700ut_lanpld_irq(data->irq);
194} 172}
195 173
196static void end_m32700ut_lanpld_irq(unsigned int irq) 174static void unmask_m32700ut_lanpld(struct irq_data *data)
197{ 175{
198 enable_m32700ut_lanpld_irq(irq); 176 enable_m32700ut_lanpld_irq(data->irq);
199 end_m32700ut_irq(M32R_IRQ_INT0); 177 enable_m32700ut_irq(M32R_IRQ_INT0);
200}
201
202static unsigned int startup_m32700ut_lanpld_irq(unsigned int irq)
203{
204 enable_m32700ut_lanpld_irq(irq);
205 return (0);
206} 178}
207 179
208static void shutdown_m32700ut_lanpld_irq(unsigned int irq) 180static void shutdown_m32700ut_lanpld(struct irq_data *data)
209{ 181{
210 unsigned long port; 182 unsigned long port;
211 unsigned int pldirq; 183 unsigned int pldirq;
212 184
213 pldirq = irq2lanpldirq(irq); 185 pldirq = irq2lanpldirq(data->irq);
214 port = lanpldirq2port(pldirq); 186 port = lanpldirq2port(pldirq);
215 outw(PLD_ICUCR_ILEVEL7, port); 187 outw(PLD_ICUCR_ILEVEL7, port);
216} 188}
217 189
218static struct irq_chip m32700ut_lanpld_irq_type = 190static struct irq_chip m32700ut_lanpld_irq_type =
219{ 191{
220 .name = "M32700UT-PLD-LAN-IRQ", 192 .name = "M32700UT-PLD-LAN-IRQ",
221 .startup = startup_m32700ut_lanpld_irq, 193 .irq_shutdown = shutdown_m32700ut_lanpld,
222 .shutdown = shutdown_m32700ut_lanpld_irq, 194 .irq_mask = mask_m32700ut_lanpld,
223 .enable = enable_m32700ut_lanpld_irq, 195 .irq_unmask = unmask_m32700ut_lanpld,
224 .disable = disable_m32700ut_lanpld_irq,
225 .ack = mask_and_ack_m32700ut_lanpld,
226 .end = end_m32700ut_lanpld_irq
227}; 196};
228 197
229/* 198/*
@@ -257,143 +226,110 @@ static void enable_m32700ut_lcdpld_irq(unsigned int irq)
257 outw(data, port); 226 outw(data, port);
258} 227}
259 228
260static void mask_and_ack_m32700ut_lcdpld(unsigned int irq) 229static void mask_m32700ut_lcdpld(struct irq_data *data)
261{ 230{
262 disable_m32700ut_lcdpld_irq(irq); 231 disable_m32700ut_lcdpld_irq(data->irq);
263} 232}
264 233
265static void end_m32700ut_lcdpld_irq(unsigned int irq) 234static void unmask_m32700ut_lcdpld(struct irq_data *data)
266{ 235{
267 enable_m32700ut_lcdpld_irq(irq); 236 enable_m32700ut_lcdpld_irq(data->irq);
268 end_m32700ut_irq(M32R_IRQ_INT2); 237 enable_m32700ut_irq(M32R_IRQ_INT2);
269}
270
271static unsigned int startup_m32700ut_lcdpld_irq(unsigned int irq)
272{
273 enable_m32700ut_lcdpld_irq(irq);
274 return (0);
275} 238}
276 239
277static void shutdown_m32700ut_lcdpld_irq(unsigned int irq) 240static void shutdown_m32700ut_lcdpld(struct irq_data *data)
278{ 241{
279 unsigned long port; 242 unsigned long port;
280 unsigned int pldirq; 243 unsigned int pldirq;
281 244
282 pldirq = irq2lcdpldirq(irq); 245 pldirq = irq2lcdpldirq(data->irq);
283 port = lcdpldirq2port(pldirq); 246 port = lcdpldirq2port(pldirq);
284 outw(PLD_ICUCR_ILEVEL7, port); 247 outw(PLD_ICUCR_ILEVEL7, port);
285} 248}
286 249
287static struct irq_chip m32700ut_lcdpld_irq_type = 250static struct irq_chip m32700ut_lcdpld_irq_type =
288{ 251{
289 .name = "M32700UT-PLD-LCD-IRQ", 252 .name = "M32700UT-PLD-LCD-IRQ",
290 .startup = startup_m32700ut_lcdpld_irq, 253 .irq_shutdown = shutdown_m32700ut_lcdpld,
291 .shutdown = shutdown_m32700ut_lcdpld_irq, 254 .irq_mask = mask_m32700ut_lcdpld,
292 .enable = enable_m32700ut_lcdpld_irq, 255 .irq_unmask = unmask_m32700ut_lcdpld,
293 .disable = disable_m32700ut_lcdpld_irq,
294 .ack = mask_and_ack_m32700ut_lcdpld,
295 .end = end_m32700ut_lcdpld_irq
296}; 256};
297 257
298void __init init_IRQ(void) 258void __init init_IRQ(void)
299{ 259{
300#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
301 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
302 irq_desc[M32700UT_LAN_IRQ_LAN].status = IRQ_DISABLED; 262 set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN,
303 irq_desc[M32700UT_LAN_IRQ_LAN].chip = &m32700ut_lanpld_irq_type; 263 &m32700ut_lanpld_irq_type, handle_level_irq);
304 irq_desc[M32700UT_LAN_IRQ_LAN].action = 0;
305 irq_desc[M32700UT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
306 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
307 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); 265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
308#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
309 267
310 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
311 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 269 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
312 irq_desc[M32R_IRQ_MFT2].chip = &m32700ut_irq_type; 270 handle_level_irq);
313 irq_desc[M32R_IRQ_MFT2].action = 0;
314 irq_desc[M32R_IRQ_MFT2].depth = 1;
315 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
316 disable_m32700ut_irq(M32R_IRQ_MFT2); 272 disable_m32700ut_irq(M32R_IRQ_MFT2);
317 273
318 /* SIO0 : receive */ 274 /* SIO0 : receive */
319 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 275 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
320 irq_desc[M32R_IRQ_SIO0_R].chip = &m32700ut_irq_type; 276 handle_level_irq);
321 irq_desc[M32R_IRQ_SIO0_R].action = 0;
322 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
323 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
324 disable_m32700ut_irq(M32R_IRQ_SIO0_R); 278 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
325 279
326 /* SIO0 : send */ 280 /* SIO0 : send */
327 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 281 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
328 irq_desc[M32R_IRQ_SIO0_S].chip = &m32700ut_irq_type; 282 handle_level_irq);
329 irq_desc[M32R_IRQ_SIO0_S].action = 0;
330 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
331 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
332 disable_m32700ut_irq(M32R_IRQ_SIO0_S); 284 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
333 285
334 /* SIO1 : receive */ 286 /* SIO1 : receive */
335 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 287 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
336 irq_desc[M32R_IRQ_SIO1_R].chip = &m32700ut_irq_type; 288 handle_level_irq);
337 irq_desc[M32R_IRQ_SIO1_R].action = 0;
338 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
339 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
340 disable_m32700ut_irq(M32R_IRQ_SIO1_R); 290 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
341 291
342 /* SIO1 : send */ 292 /* SIO1 : send */
343 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 293 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
344 irq_desc[M32R_IRQ_SIO1_S].chip = &m32700ut_irq_type; 294 handle_level_irq);
345 irq_desc[M32R_IRQ_SIO1_S].action = 0;
346 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
347 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
348 disable_m32700ut_irq(M32R_IRQ_SIO1_S); 296 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
349 297
350 /* DMA1 : */ 298 /* DMA1 : */
351 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 299 set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
352 irq_desc[M32R_IRQ_DMA1].chip = &m32700ut_irq_type; 300 handle_level_irq);
353 irq_desc[M32R_IRQ_DMA1].action = 0;
354 irq_desc[M32R_IRQ_DMA1].depth = 1;
355 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
356 disable_m32700ut_irq(M32R_IRQ_DMA1); 302 disable_m32700ut_irq(M32R_IRQ_DMA1);
357 303
358#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
359 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
360 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 306 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
361 irq_desc[PLD_IRQ_SIO0_RCV].chip = &m32700ut_pld_irq_type; 307 handle_level_irq);
362 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
363 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
364 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
365 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
366 310
367 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
368 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 312 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
369 irq_desc[PLD_IRQ_SIO0_SND].chip = &m32700ut_pld_irq_type; 313 handle_level_irq);
370 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
371 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
372 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
373 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
374#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
375 317
376 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
377 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 319 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
378 irq_desc[PLD_IRQ_CFIREQ].chip = &m32700ut_pld_irq_type; 320 handle_level_irq);
379 irq_desc[PLD_IRQ_CFIREQ].action = 0;
380 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
381 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
382 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); 322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
383 323
384 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
385 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 325 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
386 irq_desc[PLD_IRQ_CFC_INSERT].chip = &m32700ut_pld_irq_type; 326 handle_level_irq);
387 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
388 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
389 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
390 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
391 329
392 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
393 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 331 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
394 irq_desc[PLD_IRQ_CFC_EJECT].chip = &m32700ut_pld_irq_type; 332 handle_level_irq);
395 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
396 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
397 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
398 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
399 335
@@ -413,13 +349,11 @@ void __init init_IRQ(void)
413 349
414#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
415 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
352 set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
353 &m32700ut_lcdpld_irq_type, handle_level_irq);
416 354
417 irq_desc[M32700UT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
418 irq_desc[M32700UT_LCD_IRQ_USB_INT1].chip = &m32700ut_lcdpld_irq_type; 356 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
419 irq_desc[M32700UT_LCD_IRQ_USB_INT1].action = 0;
420 irq_desc[M32700UT_LCD_IRQ_USB_INT1].depth = 1;
421 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
422 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
423#endif 357#endif
424 /* 358 /*
425 * INT2# is used for BAT, USB, AUDIO 359 * INT2# is used for BAT, USB, AUDIO
@@ -432,10 +366,8 @@ void __init init_IRQ(void)
432 /* 366 /*
433 * INT3# is used for AR 367 * INT3# is used for AR
434 */ 368 */
435 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 369 set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
436 irq_desc[M32R_IRQ_INT3].chip = &m32700ut_irq_type; 370 handle_level_irq);
437 irq_desc[M32R_IRQ_INT3].action = 0;
438 irq_desc[M32R_IRQ_INT3].depth = 1;
439 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
440 disable_m32700ut_irq(M32R_IRQ_INT3); 372 disable_m32700ut_irq(M32R_IRQ_INT3);
441#endif /* CONFIG_VIDEO_M32R_AR */ 373#endif /* CONFIG_VIDEO_M32R_AR */
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index ea00c84d6b1b..cdd8c4574027 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -38,40 +38,30 @@ static void enable_mappi_irq(unsigned int irq)
38 outl(data, port); 38 outl(data, port);
39} 39}
40 40
41static void mask_and_ack_mappi(unsigned int irq) 41static void mask_mappi(struct irq_data *data)
42{ 42{
43 disable_mappi_irq(irq); 43 disable_mappi_irq(data->irq);
44} 44}
45 45
46static void end_mappi_irq(unsigned int irq) 46static void unmask_mappi(struct irq_data *data)
47{ 47{
48 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 48 enable_mappi_irq(data->irq);
49 enable_mappi_irq(irq);
50} 49}
51 50
52static unsigned int startup_mappi_irq(unsigned int irq) 51static void shutdown_mappi(struct irq_data *data)
53{
54 enable_mappi_irq(irq);
55 return (0);
56}
57
58static void shutdown_mappi_irq(unsigned int irq)
59{ 52{
60 unsigned long port; 53 unsigned long port;
61 54
62 port = irq2port(irq); 55 port = irq2port(data->irq);
63 outl(M32R_ICUCR_ILEVEL7, port); 56 outl(M32R_ICUCR_ILEVEL7, port);
64} 57}
65 58
66static struct irq_chip mappi_irq_type = 59static struct irq_chip mappi_irq_type =
67{ 60{
68 .name = "MAPPI-IRQ", 61 .name = "MAPPI-IRQ",
69 .startup = startup_mappi_irq, 62 .irq_shutdown = shutdown_mappi,
70 .shutdown = shutdown_mappi_irq, 63 .irq_mask = mask_mappi,
71 .enable = enable_mappi_irq, 64 .irq_unmask = unmask_mappi,
72 .disable = disable_mappi_irq,
73 .ack = mask_and_ack_mappi,
74 .end = end_mappi_irq
75}; 65};
76 66
77void __init init_IRQ(void) 67void __init init_IRQ(void)
@@ -85,70 +75,54 @@ void __init init_IRQ(void)
85 75
86#ifdef CONFIG_NE2000 76#ifdef CONFIG_NE2000
87 /* INT0 : LAN controller (RTL8019AS) */ 77 /* INT0 : LAN controller (RTL8019AS) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi_irq_type; 79 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = NULL;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
93 disable_mappi_irq(M32R_IRQ_INT0); 81 disable_mappi_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_M32R_NE2000 */ 82#endif /* CONFIG_M32R_NE2000 */
95 83
96 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 86 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = NULL;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi_irq(M32R_IRQ_MFT2); 88 disable_mappi_irq(M32R_IRQ_MFT2);
103 89
104#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 93 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = NULL;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi_irq(M32R_IRQ_SIO0_R); 95 disable_mappi_irq(M32R_IRQ_SIO0_R);
112 96
113 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 99 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = NULL;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi_irq(M32R_IRQ_SIO0_S); 101 disable_mappi_irq(M32R_IRQ_SIO0_S);
120 102
121 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
122 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
123 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 105 handle_level_irq);
124 irq_desc[M32R_IRQ_SIO1_R].action = NULL;
125 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
126 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
127 disable_mappi_irq(M32R_IRQ_SIO1_R); 107 disable_mappi_irq(M32R_IRQ_SIO1_R);
128 108
129 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
130 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
131 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 111 handle_level_irq);
132 irq_desc[M32R_IRQ_SIO1_S].action = NULL;
133 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
134 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
135 disable_mappi_irq(M32R_IRQ_SIO1_S); 113 disable_mappi_irq(M32R_IRQ_SIO1_S);
136#endif /* CONFIG_SERIAL_M32R_SIO */ 114#endif /* CONFIG_SERIAL_M32R_SIO */
137 115
138#if defined(CONFIG_M32R_PCC) 116#if defined(CONFIG_M32R_PCC)
139 /* INT1 : pccard0 interrupt */ 117 /* INT1 : pccard0 interrupt */
140 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
141 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type; 119 handle_level_irq);
142 irq_desc[M32R_IRQ_INT1].action = NULL;
143 irq_desc[M32R_IRQ_INT1].depth = 1;
144 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
145 disable_mappi_irq(M32R_IRQ_INT1); 121 disable_mappi_irq(M32R_IRQ_INT1);
146 122
147 /* INT2 : pccard1 interrupt */ 123 /* INT2 : pccard1 interrupt */
148 irq_desc[M32R_IRQ_INT2].status = IRQ_DISABLED; 124 set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
149 irq_desc[M32R_IRQ_INT2].chip = &mappi_irq_type; 125 handle_level_irq);
150 irq_desc[M32R_IRQ_INT2].action = NULL;
151 irq_desc[M32R_IRQ_INT2].depth = 1;
152 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
153 disable_mappi_irq(M32R_IRQ_INT2); 127 disable_mappi_irq(M32R_IRQ_INT2);
154#endif /* CONFIG_M32RPCC */ 128#endif /* CONFIG_M32RPCC */
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index c049376d0270..9117c30ea365 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -46,126 +46,97 @@ static void enable_mappi2_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_mappi2(unsigned int irq) 49static void mask_mappi2(struct irq_data *data)
50{ 50{
51 disable_mappi2_irq(irq); 51 disable_mappi2_irq(data->irq);
52} 52}
53 53
54static void end_mappi2_irq(unsigned int irq) 54static void unmask_mappi2(struct irq_data *data)
55{ 55{
56 enable_mappi2_irq(irq); 56 enable_mappi2_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_mappi2_irq(unsigned int irq) 59static void shutdown_mappi2(struct irq_data *data)
60{
61 enable_mappi2_irq(irq);
62 return (0);
63}
64
65static void shutdown_mappi2_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip mappi2_irq_type = 67static struct irq_chip mappi2_irq_type =
74{ 68{
75 .name = "MAPPI2-IRQ", 69 .name = "MAPPI2-IRQ",
76 .startup = startup_mappi2_irq, 70 .irq_shutdown = shutdown_mappi2,
77 .shutdown = shutdown_mappi2_irq, 71 .irq_mask = mask_mappi2,
78 .enable = enable_mappi2_irq, 72 .irq_unmask = unmask_mappi2,
79 .disable = disable_mappi2_irq,
80 .ack = mask_and_ack_mappi2,
81 .end = end_mappi2_irq
82}; 73};
83 74
84void __init init_IRQ(void) 75void __init init_IRQ(void)
85{ 76{
86#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 78 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 79 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi2_irq_type; 80 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi2_irq(M32R_IRQ_INT0); 82 disable_mappi2_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 83#endif /* CONFIG_SMC91X */
95 84
96 /* MFT2 : system timer */ 85 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 86 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi2_irq_type; 87 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi2_irq(M32R_IRQ_MFT2); 89 disable_mappi2_irq(M32R_IRQ_MFT2);
103 90
104#ifdef CONFIG_SERIAL_M32R_SIO 91#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 92 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 93 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi2_irq_type; 94 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi2_irq(M32R_IRQ_SIO0_R); 96 disable_mappi2_irq(M32R_IRQ_SIO0_R);
112 97
113 /* SIO0_S : uart send data */ 98 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 99 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi2_irq_type; 100 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi2_irq(M32R_IRQ_SIO0_S); 102 disable_mappi2_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi2_irq_type; 105 handle_level_irq);
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi2_irq(M32R_IRQ_SIO1_R); 107 disable_mappi2_irq(M32R_IRQ_SIO1_R);
127 108
128 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi2_irq_type; 111 handle_level_irq);
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi2_irq(M32R_IRQ_SIO1_S); 113 disable_mappi2_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 114#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 115
137#if defined(CONFIG_USB) 116#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 117 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
140 irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type; 119 handle_level_irq);
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi2_irq(M32R_IRQ_INT1); 121 disable_mappi2_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 122#endif /* CONFIG_USB */
146 123
147 /* ICUCR40: CFC IREQ */ 124 /* ICUCR40: CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 125 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi2_irq_type; 126 handle_level_irq);
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi2_irq(PLD_IRQ_CFIREQ); 128 disable_mappi2_irq(PLD_IRQ_CFIREQ);
154 129
155#if defined(CONFIG_M32R_CFC) 130#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert */ 131 /* ICUCR41: CFC Insert */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 132 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi2_irq_type; 133 handle_level_irq);
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi2_irq(PLD_IRQ_CFC_INSERT); 135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
163 136
164 /* ICUCR42: CFC Eject */ 137 /* ICUCR42: CFC Eject */
165 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 138 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
166 irq_desc[PLD_IRQ_CFC_EJECT].chip = &mappi2_irq_type; 139 handle_level_irq);
167 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
168 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
169 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
170 disable_mappi2_irq(PLD_IRQ_CFC_EJECT); 141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
171#endif /* CONFIG_MAPPI2_CFC */ 142#endif /* CONFIG_MAPPI2_CFC */
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index 882de25c6e8c..b44f5ded2bbe 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -46,128 +46,98 @@ static void enable_mappi3_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_mappi3(unsigned int irq) 49static void mask_mappi3(struct irq_data *data)
50{ 50{
51 disable_mappi3_irq(irq); 51 disable_mappi3_irq(data->irq);
52} 52}
53 53
54static void end_mappi3_irq(unsigned int irq) 54static void unmask_mappi3(struct irq_data *data)
55{ 55{
56 enable_mappi3_irq(irq); 56 enable_mappi3_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_mappi3_irq(unsigned int irq) 59static void shutdown_mappi3(struct irq_data *data)
60{
61 enable_mappi3_irq(irq);
62 return (0);
63}
64
65static void shutdown_mappi3_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip mappi3_irq_type = 67static struct irq_chip mappi3_irq_type = {
74{ 68 .name = "MAPPI3-IRQ",
75 .name = "MAPPI3-IRQ", 69 .irq_shutdown = shutdown_mappi3,
76 .startup = startup_mappi3_irq, 70 .irq_mask = mask_mappi3,
77 .shutdown = shutdown_mappi3_irq, 71 .irq_unmask = unmask_mappi3,
78 .enable = enable_mappi3_irq,
79 .disable = disable_mappi3_irq,
80 .ack = mask_and_ack_mappi3,
81 .end = end_mappi3_irq
82}; 72};
83 73
84void __init init_IRQ(void) 74void __init init_IRQ(void)
85{ 75{
86#if defined(CONFIG_SMC91X) 76#if defined(CONFIG_SMC91X)
87 /* INT0 : LAN controller (SMC91111) */ 77 /* INT0 : LAN controller (SMC91111) */
88 irq_desc[M32R_IRQ_INT0].status = IRQ_DISABLED; 78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
89 irq_desc[M32R_IRQ_INT0].chip = &mappi3_irq_type; 79 handle_level_irq);
90 irq_desc[M32R_IRQ_INT0].action = 0;
91 irq_desc[M32R_IRQ_INT0].depth = 1;
92 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
93 disable_mappi3_irq(M32R_IRQ_INT0); 81 disable_mappi3_irq(M32R_IRQ_INT0);
94#endif /* CONFIG_SMC91X */ 82#endif /* CONFIG_SMC91X */
95 83
96 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
97 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
98 irq_desc[M32R_IRQ_MFT2].chip = &mappi3_irq_type; 86 handle_level_irq);
99 irq_desc[M32R_IRQ_MFT2].action = 0;
100 irq_desc[M32R_IRQ_MFT2].depth = 1;
101 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
102 disable_mappi3_irq(M32R_IRQ_MFT2); 88 disable_mappi3_irq(M32R_IRQ_MFT2);
103 89
104#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
105 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
106 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
107 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi3_irq_type; 93 handle_level_irq);
108 irq_desc[M32R_IRQ_SIO0_R].action = 0;
109 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
110 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
111 disable_mappi3_irq(M32R_IRQ_SIO0_R); 95 disable_mappi3_irq(M32R_IRQ_SIO0_R);
112 96
113 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
114 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
115 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi3_irq_type; 99 handle_level_irq);
116 irq_desc[M32R_IRQ_SIO0_S].action = 0;
117 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
118 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
119 disable_mappi3_irq(M32R_IRQ_SIO0_S); 101 disable_mappi3_irq(M32R_IRQ_SIO0_S);
120 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
121 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
122 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi3_irq_type; 104 handle_level_irq);
123 irq_desc[M32R_IRQ_SIO1_R].action = 0;
124 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
125 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
126 disable_mappi3_irq(M32R_IRQ_SIO1_R); 106 disable_mappi3_irq(M32R_IRQ_SIO1_R);
127 107
128 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
129 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
130 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi3_irq_type; 110 handle_level_irq);
131 irq_desc[M32R_IRQ_SIO1_S].action = 0;
132 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
133 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
134 disable_mappi3_irq(M32R_IRQ_SIO1_S); 112 disable_mappi3_irq(M32R_IRQ_SIO1_S);
135#endif /* CONFIG_M32R_USE_DBG_CONSOLE */ 113#endif /* CONFIG_M32R_USE_DBG_CONSOLE */
136 114
137#if defined(CONFIG_USB) 115#if defined(CONFIG_USB)
138 /* INT1 : USB Host controller interrupt */ 116 /* INT1 : USB Host controller interrupt */
139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED; 117 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
140 irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type; 118 handle_level_irq);
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi3_irq(M32R_IRQ_INT1); 120 disable_mappi3_irq(M32R_IRQ_INT1);
145#endif /* CONFIG_USB */ 121#endif /* CONFIG_USB */
146 122
147 /* CFC IREQ */ 123 /* CFC IREQ */
148 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 124 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
149 irq_desc[PLD_IRQ_CFIREQ].chip = &mappi3_irq_type; 125 handle_level_irq);
150 irq_desc[PLD_IRQ_CFIREQ].action = 0;
151 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
152 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
153 disable_mappi3_irq(PLD_IRQ_CFIREQ); 127 disable_mappi3_irq(PLD_IRQ_CFIREQ);
154 128
155#if defined(CONFIG_M32R_CFC) 129#if defined(CONFIG_M32R_CFC)
156 /* ICUCR41: CFC Insert & eject */ 130 /* ICUCR41: CFC Insert & eject */
157 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 131 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
158 irq_desc[PLD_IRQ_CFC_INSERT].chip = &mappi3_irq_type; 132 handle_level_irq);
159 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
160 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
161 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
162 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
163 135
164#endif /* CONFIG_M32R_CFC */ 136#endif /* CONFIG_M32R_CFC */
165 137
166 /* IDE IREQ */ 138 /* IDE IREQ */
167 irq_desc[PLD_IRQ_IDEIREQ].status = IRQ_DISABLED; 139 set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
168 irq_desc[PLD_IRQ_IDEIREQ].chip = &mappi3_irq_type; 140 handle_level_irq);
169 irq_desc[PLD_IRQ_IDEIREQ].action = 0;
170 irq_desc[PLD_IRQ_IDEIREQ].depth = 1; /* disable nested irq */
171 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
172 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
173 143
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index d11d93bf74f5..19a02db7b818 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -37,39 +37,30 @@ static void enable_oaks32r_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_oaks32r(struct irq_data *data)
41{ 41{
42 disable_oaks32r_irq(irq); 42 disable_oaks32r_irq(data->irq);
43} 43}
44 44
45static void end_oaks32r_irq(unsigned int irq) 45static void unmask_oaks32r(struct irq_data *data)
46{ 46{
47 enable_oaks32r_irq(irq); 47 enable_oaks32r_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_oaks32r_irq(unsigned int irq) 50static void shutdown_oaks32r(struct irq_data *data)
51{
52 enable_oaks32r_irq(irq);
53 return (0);
54}
55
56static void shutdown_oaks32r_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip oaks32r_irq_type = 58static struct irq_chip oaks32r_irq_type =
65{ 59{
66 .name = "OAKS32R-IRQ", 60 .name = "OAKS32R-IRQ",
67 .startup = startup_oaks32r_irq, 61 .irq_shutdown = shutdown_oaks32r,
68 .shutdown = shutdown_oaks32r_irq, 62 .irq_mask = mask_oaks32r,
69 .enable = enable_oaks32r_irq, 63 .irq_unmask = unmask_oaks32r,
70 .disable = disable_oaks32r_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_oaks32r_irq
73}; 64};
74 65
75void __init init_IRQ(void) 66void __init init_IRQ(void)
@@ -83,52 +74,40 @@ void __init init_IRQ(void)
83 74
84#ifdef CONFIG_NE2000 75#ifdef CONFIG_NE2000
85 /* INT3 : LAN controller (RTL8019AS) */ 76 /* INT3 : LAN controller (RTL8019AS) */
86 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 77 set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
87 irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type; 78 handle_level_irq);
88 irq_desc[M32R_IRQ_INT3].action = 0;
89 irq_desc[M32R_IRQ_INT3].depth = 1;
90 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
91 disable_oaks32r_irq(M32R_IRQ_INT3); 80 disable_oaks32r_irq(M32R_IRQ_INT3);
92#endif /* CONFIG_M32R_NE2000 */ 81#endif /* CONFIG_M32R_NE2000 */
93 82
94 /* MFT2 : system timer */ 83 /* MFT2 : system timer */
95 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 84 set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
96 irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type; 85 handle_level_irq);
97 irq_desc[M32R_IRQ_MFT2].action = 0;
98 irq_desc[M32R_IRQ_MFT2].depth = 1;
99 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
100 disable_oaks32r_irq(M32R_IRQ_MFT2); 87 disable_oaks32r_irq(M32R_IRQ_MFT2);
101 88
102#ifdef CONFIG_SERIAL_M32R_SIO 89#ifdef CONFIG_SERIAL_M32R_SIO
103 /* SIO0_R : uart receive data */ 90 /* SIO0_R : uart receive data */
104 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 91 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
105 irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type; 92 handle_level_irq);
106 irq_desc[M32R_IRQ_SIO0_R].action = 0;
107 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
108 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 93 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
109 disable_oaks32r_irq(M32R_IRQ_SIO0_R); 94 disable_oaks32r_irq(M32R_IRQ_SIO0_R);
110 95
111 /* SIO0_S : uart send data */ 96 /* SIO0_S : uart send data */
112 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 97 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
113 irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type; 98 handle_level_irq);
114 irq_desc[M32R_IRQ_SIO0_S].action = 0;
115 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
116 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 99 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
117 disable_oaks32r_irq(M32R_IRQ_SIO0_S); 100 disable_oaks32r_irq(M32R_IRQ_SIO0_S);
118 101
119 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
120 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
121 irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type; 104 handle_level_irq);
122 irq_desc[M32R_IRQ_SIO1_R].action = 0;
123 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
124 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
125 disable_oaks32r_irq(M32R_IRQ_SIO1_R); 106 disable_oaks32r_irq(M32R_IRQ_SIO1_R);
126 107
127 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
128 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
129 irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type; 110 handle_level_irq);
130 irq_desc[M32R_IRQ_SIO1_S].action = 0;
131 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
132 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
133 disable_oaks32r_irq(M32R_IRQ_SIO1_S); 112 disable_oaks32r_irq(M32R_IRQ_SIO1_S);
134#endif /* CONFIG_SERIAL_M32R_SIO */ 113#endif /* CONFIG_SERIAL_M32R_SIO */
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index 5f3402a2fbaf..12731547e8bf 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq)
46 outl(data, port); 46 outl(data, port);
47} 47}
48 48
49static void mask_and_ack_opsput(unsigned int irq) 49static void mask_opsput(struct irq_data *data)
50{ 50{
51 disable_opsput_irq(irq); 51 disable_opsput_irq(data->irq);
52} 52}
53 53
54static void end_opsput_irq(unsigned int irq) 54static void unmask_opsput(struct irq_data *data)
55{ 55{
56 enable_opsput_irq(irq); 56 enable_opsput_irq(data->irq);
57} 57}
58 58
59static unsigned int startup_opsput_irq(unsigned int irq) 59static void shutdown_opsput(struct irq_data *data)
60{
61 enable_opsput_irq(irq);
62 return (0);
63}
64
65static void shutdown_opsput_irq(unsigned int irq)
66{ 60{
67 unsigned long port; 61 unsigned long port;
68 62
69 port = irq2port(irq); 63 port = irq2port(data->irq);
70 outl(M32R_ICUCR_ILEVEL7, port); 64 outl(M32R_ICUCR_ILEVEL7, port);
71} 65}
72 66
73static struct irq_chip opsput_irq_type = 67static struct irq_chip opsput_irq_type =
74{ 68{
75 .name = "OPSPUT-IRQ", 69 .name = "OPSPUT-IRQ",
76 .startup = startup_opsput_irq, 70 .irq_shutdown = shutdown_opsput,
77 .shutdown = shutdown_opsput_irq, 71 .irq_mask = mask_opsput,
78 .enable = enable_opsput_irq, 72 .irq_unmask = unmask_opsput,
79 .disable = disable_opsput_irq,
80 .ack = mask_and_ack_opsput,
81 .end = end_opsput_irq
82}; 73};
83 74
84/* 75/*
@@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq)
100 unsigned int pldirq; 91 unsigned int pldirq;
101 92
102 pldirq = irq2pldirq(irq); 93 pldirq = irq2pldirq(irq);
103// disable_opsput_irq(M32R_IRQ_INT1);
104 port = pldirq2port(pldirq); 94 port = pldirq2port(pldirq);
105 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7; 95 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
106 outw(data, port); 96 outw(data, port);
@@ -112,50 +102,38 @@ static void enable_opsput_pld_irq(unsigned int irq)
112 unsigned int pldirq; 102 unsigned int pldirq;
113 103
114 pldirq = irq2pldirq(irq); 104 pldirq = irq2pldirq(irq);
115// enable_opsput_irq(M32R_IRQ_INT1);
116 port = pldirq2port(pldirq); 105 port = pldirq2port(pldirq);
117 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6; 106 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
118 outw(data, port); 107 outw(data, port);
119} 108}
120 109
121static void mask_and_ack_opsput_pld(unsigned int irq) 110static void mask_opsput_pld(struct irq_data *data)
122{
123 disable_opsput_pld_irq(irq);
124// mask_and_ack_opsput(M32R_IRQ_INT1);
125}
126
127static void end_opsput_pld_irq(unsigned int irq)
128{ 111{
129 enable_opsput_pld_irq(irq); 112 disable_opsput_pld_irq(data->irq);
130 end_opsput_irq(M32R_IRQ_INT1);
131} 113}
132 114
133static unsigned int startup_opsput_pld_irq(unsigned int irq) 115static void unmask_opsput_pld(struct irq_data *data)
134{ 116{
135 enable_opsput_pld_irq(irq); 117 enable_opsput_pld_irq(data->irq);
136 return (0); 118 enable_opsput_irq(M32R_IRQ_INT1);
137} 119}
138 120
139static void shutdown_opsput_pld_irq(unsigned int irq) 121static void shutdown_opsput_pld(struct irq_data *data)
140{ 122{
141 unsigned long port; 123 unsigned long port;
142 unsigned int pldirq; 124 unsigned int pldirq;
143 125
144 pldirq = irq2pldirq(irq); 126 pldirq = irq2pldirq(data->irq);
145// shutdown_opsput_irq(M32R_IRQ_INT1);
146 port = pldirq2port(pldirq); 127 port = pldirq2port(pldirq);
147 outw(PLD_ICUCR_ILEVEL7, port); 128 outw(PLD_ICUCR_ILEVEL7, port);
148} 129}
149 130
150static struct irq_chip opsput_pld_irq_type = 131static struct irq_chip opsput_pld_irq_type =
151{ 132{
152 .name = "OPSPUT-PLD-IRQ", 133 .name = "OPSPUT-PLD-IRQ",
153 .startup = startup_opsput_pld_irq, 134 .irq_shutdown = shutdown_opsput_pld,
154 .shutdown = shutdown_opsput_pld_irq, 135 .irq_mask = mask_opsput_pld,
155 .enable = enable_opsput_pld_irq, 136 .irq_unmask = unmask_opsput_pld,
156 .disable = disable_opsput_pld_irq,
157 .ack = mask_and_ack_opsput_pld,
158 .end = end_opsput_pld_irq
159}; 137};
160 138
161/* 139/*
@@ -189,42 +167,33 @@ static void enable_opsput_lanpld_irq(unsigned int irq)
189 outw(data, port); 167 outw(data, port);
190} 168}
191 169
192static void mask_and_ack_opsput_lanpld(unsigned int irq) 170static void mask_opsput_lanpld(struct irq_data *data)
193{
194 disable_opsput_lanpld_irq(irq);
195}
196
197static void end_opsput_lanpld_irq(unsigned int irq)
198{ 171{
199 enable_opsput_lanpld_irq(irq); 172 disable_opsput_lanpld_irq(data->irq);
200 end_opsput_irq(M32R_IRQ_INT0);
201} 173}
202 174
203static unsigned int startup_opsput_lanpld_irq(unsigned int irq) 175static void unmask_opsput_lanpld(struct irq_data *data)
204{ 176{
205 enable_opsput_lanpld_irq(irq); 177 enable_opsput_lanpld_irq(data->irq);
206 return (0); 178 enable_opsput_irq(M32R_IRQ_INT0);
207} 179}
208 180
209static void shutdown_opsput_lanpld_irq(unsigned int irq) 181static void shutdown_opsput_lanpld(struct irq_data *data)
210{ 182{
211 unsigned long port; 183 unsigned long port;
212 unsigned int pldirq; 184 unsigned int pldirq;
213 185
214 pldirq = irq2lanpldirq(irq); 186 pldirq = irq2lanpldirq(data->irq);
215 port = lanpldirq2port(pldirq); 187 port = lanpldirq2port(pldirq);
216 outw(PLD_ICUCR_ILEVEL7, port); 188 outw(PLD_ICUCR_ILEVEL7, port);
217} 189}
218 190
219static struct irq_chip opsput_lanpld_irq_type = 191static struct irq_chip opsput_lanpld_irq_type =
220{ 192{
221 .name = "OPSPUT-PLD-LAN-IRQ", 193 .name = "OPSPUT-PLD-LAN-IRQ",
222 .startup = startup_opsput_lanpld_irq, 194 .irq_shutdown = shutdown_opsput_lanpld,
223 .shutdown = shutdown_opsput_lanpld_irq, 195 .irq_mask = mask_opsput_lanpld,
224 .enable = enable_opsput_lanpld_irq, 196 .irq_unmask = unmask_opsput_lanpld,
225 .disable = disable_opsput_lanpld_irq,
226 .ack = mask_and_ack_opsput_lanpld,
227 .end = end_opsput_lanpld_irq
228}; 197};
229 198
230/* 199/*
@@ -258,143 +227,109 @@ static void enable_opsput_lcdpld_irq(unsigned int irq)
258 outw(data, port); 227 outw(data, port);
259} 228}
260 229
261static void mask_and_ack_opsput_lcdpld(unsigned int irq) 230static void mask_opsput_lcdpld(struct irq_data *data)
262{
263 disable_opsput_lcdpld_irq(irq);
264}
265
266static void end_opsput_lcdpld_irq(unsigned int irq)
267{ 231{
268 enable_opsput_lcdpld_irq(irq); 232 disable_opsput_lcdpld_irq(data->irq);
269 end_opsput_irq(M32R_IRQ_INT2);
270} 233}
271 234
272static unsigned int startup_opsput_lcdpld_irq(unsigned int irq) 235static void unmask_opsput_lcdpld(struct irq_data *data)
273{ 236{
274 enable_opsput_lcdpld_irq(irq); 237 enable_opsput_lcdpld_irq(data->irq);
275 return (0); 238 enable_opsput_irq(M32R_IRQ_INT2);
276} 239}
277 240
278static void shutdown_opsput_lcdpld_irq(unsigned int irq) 241static void shutdown_opsput_lcdpld(struct irq_data *data)
279{ 242{
280 unsigned long port; 243 unsigned long port;
281 unsigned int pldirq; 244 unsigned int pldirq;
282 245
283 pldirq = irq2lcdpldirq(irq); 246 pldirq = irq2lcdpldirq(data->irq);
284 port = lcdpldirq2port(pldirq); 247 port = lcdpldirq2port(pldirq);
285 outw(PLD_ICUCR_ILEVEL7, port); 248 outw(PLD_ICUCR_ILEVEL7, port);
286} 249}
287 250
288static struct irq_chip opsput_lcdpld_irq_type = 251static struct irq_chip opsput_lcdpld_irq_type = {
289{ 252 .name = "OPSPUT-PLD-LCD-IRQ",
290 "OPSPUT-PLD-LCD-IRQ", 253 .irq_shutdown = shutdown_opsput_lcdpld,
291 startup_opsput_lcdpld_irq, 254 .irq_mask = mask_opsput_lcdpld,
292 shutdown_opsput_lcdpld_irq, 255 .irq_unmask = unmask_opsput_lcdpld,
293 enable_opsput_lcdpld_irq,
294 disable_opsput_lcdpld_irq,
295 mask_and_ack_opsput_lcdpld,
296 end_opsput_lcdpld_irq
297}; 256};
298 257
299void __init init_IRQ(void) 258void __init init_IRQ(void)
300{ 259{
301#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
302 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
303 irq_desc[OPSPUT_LAN_IRQ_LAN].status = IRQ_DISABLED; 262 set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
304 irq_desc[OPSPUT_LAN_IRQ_LAN].chip = &opsput_lanpld_irq_type; 263 handle_level_irq);
305 irq_desc[OPSPUT_LAN_IRQ_LAN].action = 0;
306 irq_desc[OPSPUT_LAN_IRQ_LAN].depth = 1; /* disable nested irq */
307 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
308 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); 265 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
309#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
310 267
311 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
312 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 269 set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
313 irq_desc[M32R_IRQ_MFT2].chip = &opsput_irq_type; 270 handle_level_irq);
314 irq_desc[M32R_IRQ_MFT2].action = 0;
315 irq_desc[M32R_IRQ_MFT2].depth = 1;
316 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
317 disable_opsput_irq(M32R_IRQ_MFT2); 272 disable_opsput_irq(M32R_IRQ_MFT2);
318 273
319 /* SIO0 : receive */ 274 /* SIO0 : receive */
320 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 275 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
321 irq_desc[M32R_IRQ_SIO0_R].chip = &opsput_irq_type; 276 handle_level_irq);
322 irq_desc[M32R_IRQ_SIO0_R].action = 0;
323 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
324 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
325 disable_opsput_irq(M32R_IRQ_SIO0_R); 278 disable_opsput_irq(M32R_IRQ_SIO0_R);
326 279
327 /* SIO0 : send */ 280 /* SIO0 : send */
328 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 281 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
329 irq_desc[M32R_IRQ_SIO0_S].chip = &opsput_irq_type; 282 handle_level_irq);
330 irq_desc[M32R_IRQ_SIO0_S].action = 0;
331 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
332 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
333 disable_opsput_irq(M32R_IRQ_SIO0_S); 284 disable_opsput_irq(M32R_IRQ_SIO0_S);
334 285
335 /* SIO1 : receive */ 286 /* SIO1 : receive */
336 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 287 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
337 irq_desc[M32R_IRQ_SIO1_R].chip = &opsput_irq_type; 288 handle_level_irq);
338 irq_desc[M32R_IRQ_SIO1_R].action = 0;
339 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
340 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
341 disable_opsput_irq(M32R_IRQ_SIO1_R); 290 disable_opsput_irq(M32R_IRQ_SIO1_R);
342 291
343 /* SIO1 : send */ 292 /* SIO1 : send */
344 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 293 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
345 irq_desc[M32R_IRQ_SIO1_S].chip = &opsput_irq_type; 294 handle_level_irq);
346 irq_desc[M32R_IRQ_SIO1_S].action = 0;
347 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
348 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
349 disable_opsput_irq(M32R_IRQ_SIO1_S); 296 disable_opsput_irq(M32R_IRQ_SIO1_S);
350 297
351 /* DMA1 : */ 298 /* DMA1 : */
352 irq_desc[M32R_IRQ_DMA1].status = IRQ_DISABLED; 299 set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
353 irq_desc[M32R_IRQ_DMA1].chip = &opsput_irq_type; 300 handle_level_irq);
354 irq_desc[M32R_IRQ_DMA1].action = 0;
355 irq_desc[M32R_IRQ_DMA1].depth = 1;
356 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
357 disable_opsput_irq(M32R_IRQ_DMA1); 302 disable_opsput_irq(M32R_IRQ_DMA1);
358 303
359#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
360 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
361 irq_desc[PLD_IRQ_SIO0_RCV].status = IRQ_DISABLED; 306 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
362 irq_desc[PLD_IRQ_SIO0_RCV].chip = &opsput_pld_irq_type; 307 handle_level_irq);
363 irq_desc[PLD_IRQ_SIO0_RCV].action = 0;
364 irq_desc[PLD_IRQ_SIO0_RCV].depth = 1; /* disable nested irq */
365 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
366 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
367 310
368 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
369 irq_desc[PLD_IRQ_SIO0_SND].status = IRQ_DISABLED; 312 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
370 irq_desc[PLD_IRQ_SIO0_SND].chip = &opsput_pld_irq_type; 313 handle_level_irq);
371 irq_desc[PLD_IRQ_SIO0_SND].action = 0;
372 irq_desc[PLD_IRQ_SIO0_SND].depth = 1; /* disable nested irq */
373 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
374 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
375#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
376 317
377 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
378 irq_desc[PLD_IRQ_CFIREQ].status = IRQ_DISABLED; 319 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
379 irq_desc[PLD_IRQ_CFIREQ].chip = &opsput_pld_irq_type; 320 handle_level_irq);
380 irq_desc[PLD_IRQ_CFIREQ].action = 0;
381 irq_desc[PLD_IRQ_CFIREQ].depth = 1; /* disable nested irq */
382 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
383 disable_opsput_pld_irq(PLD_IRQ_CFIREQ); 322 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
384 323
385 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
386 irq_desc[PLD_IRQ_CFC_INSERT].status = IRQ_DISABLED; 325 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
387 irq_desc[PLD_IRQ_CFC_INSERT].chip = &opsput_pld_irq_type; 326 handle_level_irq);
388 irq_desc[PLD_IRQ_CFC_INSERT].action = 0;
389 irq_desc[PLD_IRQ_CFC_INSERT].depth = 1; /* disable nested irq */
390 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
391 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
392 329
393 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
394 irq_desc[PLD_IRQ_CFC_EJECT].status = IRQ_DISABLED; 331 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
395 irq_desc[PLD_IRQ_CFC_EJECT].chip = &opsput_pld_irq_type; 332 handle_level_irq);
396 irq_desc[PLD_IRQ_CFC_EJECT].action = 0;
397 irq_desc[PLD_IRQ_CFC_EJECT].depth = 1; /* disable nested irq */
398 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
399 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
400 335
@@ -413,14 +348,11 @@ void __init init_IRQ(void)
413 enable_opsput_irq(M32R_IRQ_INT1); 348 enable_opsput_irq(M32R_IRQ_INT1);
414 349
415#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
416 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
417 352 set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1,
418 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].status = IRQ_DISABLED; 353 &opsput_lcdpld_irq_type, handle_level_irq);
419 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].chip = &opsput_lcdpld_irq_type; 354 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
420 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].action = 0; 355 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
421 irq_desc[OPSPUT_LCD_IRQ_USB_INT1].depth = 1;
422 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
423 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
424#endif 356#endif
425 /* 357 /*
426 * INT2# is used for BAT, USB, AUDIO 358 * INT2# is used for BAT, USB, AUDIO
@@ -433,10 +365,8 @@ void __init init_IRQ(void)
433 /* 365 /*
434 * INT3# is used for AR 366 * INT3# is used for AR
435 */ 367 */
436 irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED; 368 set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
437 irq_desc[M32R_IRQ_INT3].chip = &opsput_irq_type; 369 handle_level_irq);
438 irq_desc[M32R_IRQ_INT3].action = 0;
439 irq_desc[M32R_IRQ_INT3].depth = 1;
440 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 370 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
441 disable_opsput_irq(M32R_IRQ_INT3); 371 disable_opsput_irq(M32R_IRQ_INT3);
442#endif /* CONFIG_VIDEO_M32R_AR */ 372#endif /* CONFIG_VIDEO_M32R_AR */
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index 1beac7a51ed4..f3cff26d6e74 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -37,39 +37,30 @@ static void enable_mappi_irq(unsigned int irq)
37 outl(data, port); 37 outl(data, port);
38} 38}
39 39
40static void mask_and_ack_mappi(unsigned int irq) 40static void mask_mappi(struct irq_data *data)
41{ 41{
42 disable_mappi_irq(irq); 42 disable_mappi_irq(data->irq);
43} 43}
44 44
45static void end_mappi_irq(unsigned int irq) 45static void unmask_mappi(struct irq_data *data)
46{ 46{
47 enable_mappi_irq(irq); 47 enable_mappi_irq(data->irq);
48} 48}
49 49
50static unsigned int startup_mappi_irq(unsigned int irq) 50static void shutdown_mappi(struct irq_data *data)
51{
52 enable_mappi_irq(irq);
53 return 0;
54}
55
56static void shutdown_mappi_irq(unsigned int irq)
57{ 51{
58 unsigned long port; 52 unsigned long port;
59 53
60 port = irq2port(irq); 54 port = irq2port(data->irq);
61 outl(M32R_ICUCR_ILEVEL7, port); 55 outl(M32R_ICUCR_ILEVEL7, port);
62} 56}
63 57
64static struct irq_chip mappi_irq_type = 58static struct irq_chip mappi_irq_type =
65{ 59{
66 .name = "M32700-IRQ", 60 .name = "M32700-IRQ",
67 .startup = startup_mappi_irq, 61 .irq_shutdown = shutdown_mappi,
68 .shutdown = shutdown_mappi_irq, 62 .irq_mask = mask_mappi,
69 .enable = enable_mappi_irq, 63 .irq_unmask = unmask_mappi,
70 .disable = disable_mappi_irq,
71 .ack = mask_and_ack_mappi,
72 .end = end_mappi_irq
73}; 64};
74 65
75/* 66/*
@@ -107,42 +98,33 @@ static void enable_m32700ut_pld_irq(unsigned int irq)
107 outw(data, port); 98 outw(data, port);
108} 99}
109 100
110static void mask_and_ack_m32700ut_pld(unsigned int irq) 101static void mask_m32700ut_pld(struct irq_data *data)
111{ 102{
112 disable_m32700ut_pld_irq(irq); 103 disable_m32700ut_pld_irq(data->irq);
113} 104}
114 105
115static void end_m32700ut_pld_irq(unsigned int irq) 106static void unmask_m32700ut_pld(struct irq_data *data)
116{ 107{
117 enable_m32700ut_pld_irq(irq); 108 enable_m32700ut_pld_irq(data->irq);
118 end_mappi_irq(M32R_IRQ_INT1); 109 enable_mappi_irq(M32R_IRQ_INT1);
119}
120
121static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
122{
123 enable_m32700ut_pld_irq(irq);
124 return 0;
125} 110}
126 111
127static void shutdown_m32700ut_pld_irq(unsigned int irq) 112static void shutdown_m32700ut_pld(struct irq_data *data)
128{ 113{
129 unsigned long port; 114 unsigned long port;
130 unsigned int pldirq; 115 unsigned int pldirq;
131 116
132 pldirq = irq2pldirq(irq); 117 pldirq = irq2pldirq(data->irq);
133 port = pldirq2port(pldirq); 118 port = pldirq2port(pldirq);
134 outw(PLD_ICUCR_ILEVEL7, port); 119 outw(PLD_ICUCR_ILEVEL7, port);
135} 120}
136 121
137static struct irq_chip m32700ut_pld_irq_type = 122static struct irq_chip m32700ut_pld_irq_type =
138{ 123{
139 .name = "USRV-PLD-IRQ", 124 .name = "USRV-PLD-IRQ",
140 .startup = startup_m32700ut_pld_irq, 125 .irq_shutdown = shutdown_m32700ut_pld,
141 .shutdown = shutdown_m32700ut_pld_irq, 126 .irq_mask = mask_m32700ut_pld,
142 .enable = enable_m32700ut_pld_irq, 127 .irq_unmask = unmask_m32700ut_pld,
143 .disable = disable_m32700ut_pld_irq,
144 .ack = mask_and_ack_m32700ut_pld,
145 .end = end_m32700ut_pld_irq
146}; 128};
147 129
148void __init init_IRQ(void) 130void __init init_IRQ(void)
@@ -156,53 +138,42 @@ void __init init_IRQ(void)
156 once++; 138 once++;
157 139
158 /* MFT2 : system timer */ 140 /* MFT2 : system timer */
159 irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED; 141 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
160 irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type; 142 handle_level_irq);
161 irq_desc[M32R_IRQ_MFT2].action = 0;
162 irq_desc[M32R_IRQ_MFT2].depth = 1;
163 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
164 disable_mappi_irq(M32R_IRQ_MFT2); 144 disable_mappi_irq(M32R_IRQ_MFT2);
165 145
166#if defined(CONFIG_SERIAL_M32R_SIO) 146#if defined(CONFIG_SERIAL_M32R_SIO)
167 /* SIO0_R : uart receive data */ 147 /* SIO0_R : uart receive data */
168 irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED; 148 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
169 irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type; 149 handle_level_irq);
170 irq_desc[M32R_IRQ_SIO0_R].action = 0;
171 irq_desc[M32R_IRQ_SIO0_R].depth = 1;
172 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 150 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
173 disable_mappi_irq(M32R_IRQ_SIO0_R); 151 disable_mappi_irq(M32R_IRQ_SIO0_R);
174 152
175 /* SIO0_S : uart send data */ 153 /* SIO0_S : uart send data */
176 irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED; 154 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
177 irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type; 155 handle_level_irq);
178 irq_desc[M32R_IRQ_SIO0_S].action = 0;
179 irq_desc[M32R_IRQ_SIO0_S].depth = 1;
180 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 156 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
181 disable_mappi_irq(M32R_IRQ_SIO0_S); 157 disable_mappi_irq(M32R_IRQ_SIO0_S);
182 158
183 /* SIO1_R : uart receive data */ 159 /* SIO1_R : uart receive data */
184 irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED; 160 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
185 irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type; 161 handle_level_irq);
186 irq_desc[M32R_IRQ_SIO1_R].action = 0;
187 irq_desc[M32R_IRQ_SIO1_R].depth = 1;
188 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 162 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
189 disable_mappi_irq(M32R_IRQ_SIO1_R); 163 disable_mappi_irq(M32R_IRQ_SIO1_R);
190 164
191 /* SIO1_S : uart send data */ 165 /* SIO1_S : uart send data */
192 irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED; 166 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
193 irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type; 167 handle_level_irq);
194 irq_desc[M32R_IRQ_SIO1_S].action = 0;
195 irq_desc[M32R_IRQ_SIO1_S].depth = 1;
196 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 168 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
197 disable_mappi_irq(M32R_IRQ_SIO1_S); 169 disable_mappi_irq(M32R_IRQ_SIO1_S);
198#endif /* CONFIG_SERIAL_M32R_SIO */ 170#endif /* CONFIG_SERIAL_M32R_SIO */
199 171
200 /* INT#67-#71: CFC#0 IREQ on PLD */ 172 /* INT#67-#71: CFC#0 IREQ on PLD */
201 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { 173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
202 irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED; 174 set_irq_chip_and_handler(PLD_IRQ_CF0 + i,
203 irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type; 175 &m32700ut_pld_irq_type,
204 irq_desc[PLD_IRQ_CF0 + i].action = 0; 176 handle_level_irq);
205 irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
206 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr 177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
207 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 178 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
208 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i); 179 disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
@@ -210,19 +181,15 @@ void __init init_IRQ(void)
210 181
211#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 182#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
212 /* INT#76: 16552D#0 IREQ on PLD */ 183 /* INT#76: 16552D#0 IREQ on PLD */
213 irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED; 184 set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
214 irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type; 185 handle_level_irq);
215 irq_desc[PLD_IRQ_UART0].action = 0;
216 irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
217 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
218 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
219 disable_m32700ut_pld_irq(PLD_IRQ_UART0); 188 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
220 189
221 /* INT#77: 16552D#1 IREQ on PLD */ 190 /* INT#77: 16552D#1 IREQ on PLD */
222 irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED; 191 set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
223 irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type; 192 handle_level_irq);
224 irq_desc[PLD_IRQ_UART1].action = 0;
225 irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
226 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
227 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
228 disable_m32700ut_pld_irq(PLD_IRQ_UART1); 195 disable_m32700ut_pld_irq(PLD_IRQ_UART1);
@@ -230,10 +197,8 @@ void __init init_IRQ(void)
230 197
231#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 198#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
232 /* INT#80: AK4524 IREQ on PLD */ 199 /* INT#80: AK4524 IREQ on PLD */
233 irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED; 200 set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
234 irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type; 201 handle_level_irq);
235 irq_desc[PLD_IRQ_SNDINT].action = 0;
236 irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
237 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
238 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
239 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT); 204 disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 704e7b92334c..8b9dacaa0f6e 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -2,6 +2,7 @@ config M68K
2 bool 2 bool
3 default y 3 default y
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_GENERIC_HARDIRQS
5 6
6config MMU 7config MMU
7 bool 8 bool
@@ -48,14 +49,6 @@ config GENERIC_HWEIGHT
48 bool 49 bool
49 default y 50 default y
50 51
51config GENERIC_HARDIRQS
52 bool
53 default y
54
55config GENERIC_HARDIRQS_NO__DO_IRQ
56 bool
57 default y
58
59config GENERIC_CALIBRATE_DELAY 52config GENERIC_CALIBRATE_DELAY
60 bool 53 bool
61 default y 54 default y
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 5f5018a71a3d..31680032053e 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -15,6 +15,8 @@ config MICROBLAZE
15 select TRACING_SUPPORT 15 select TRACING_SUPPORT
16 select OF 16 select OF
17 select OF_EARLY_FLATTREE 17 select OF_EARLY_FLATTREE
18 select HAVE_GENERIC_HARDIRQS
19 select GENERIC_IRQ_PROBE
18 20
19config SWAP 21config SWAP
20 def_bool n 22 def_bool n
@@ -37,12 +39,6 @@ config GENERIC_FIND_NEXT_BIT
37config GENERIC_HWEIGHT 39config GENERIC_HWEIGHT
38 def_bool y 40 def_bool y
39 41
40config GENERIC_HARDIRQS
41 def_bool y
42
43config GENERIC_IRQ_PROBE
44 def_bool y
45
46config GENERIC_CALIBRATE_DELAY 42config GENERIC_CALIBRATE_DELAY
47 def_bool y 43 def_bool y
48 44
@@ -52,9 +48,6 @@ config GENERIC_TIME_VSYSCALL
52config GENERIC_CLOCKEVENTS 48config GENERIC_CLOCKEVENTS
53 def_bool y 49 def_bool y
54 50
55config GENERIC_HARDIRQS_NO__DO_IRQ
56 def_bool y
57
58config GENERIC_GPIO 51config GENERIC_GPIO
59 def_bool y 52 def_bool y
60 53
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 548e6cc3bc28..f5ecc0566bc2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -793,9 +793,6 @@ config SCHED_OMIT_FRAME_POINTER
793 bool 793 bool
794 default y 794 default y
795 795
796config GENERIC_HARDIRQS_NO__DO_IRQ
797 def_bool y
798
799# 796#
800# Select some configuration options automatically based on user selections. 797# Select some configuration options automatically based on user selections.
801# 798#
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 8ed41cf2b08d..243bfa23fd58 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -1,6 +1,7 @@
1config MN10300 1config MN10300
2 def_bool y 2 def_bool y
3 select HAVE_OPROFILE 3 select HAVE_OPROFILE
4 select GENERIC_HARDIRQS
4 5
5config AM33_2 6config AM33_2
6 def_bool n 7 def_bool n
@@ -34,9 +35,6 @@ config RWSEM_GENERIC_SPINLOCK
34config RWSEM_XCHGADD_ALGORITHM 35config RWSEM_XCHGADD_ALGORITHM
35 bool 36 bool
36 37
37config GENERIC_HARDIRQS_NO__DO_IRQ
38 def_bool y
39
40config GENERIC_CALIBRATE_DELAY 38config GENERIC_CALIBRATE_DELAY
41 def_bool y 39 def_bool y
42 40
@@ -79,10 +77,6 @@ config QUICKLIST
79config ARCH_HAS_ILOG2_U32 77config ARCH_HAS_ILOG2_U32
80 def_bool y 78 def_bool y
81 79
82# Use the generic interrupt handling code in kernel/irq/
83config GENERIC_HARDIRQS
84 def_bool y
85
86config HOTPLUG_CPU 80config HOTPLUG_CPU
87 def_bool n 81 def_bool n
88 82
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 0888675c98dd..fed2946f7335 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -12,7 +12,10 @@ config PARISC
12 select HAVE_IRQ_WORK 12 select HAVE_IRQ_WORK
13 select HAVE_PERF_EVENTS 13 select HAVE_PERF_EVENTS
14 select GENERIC_ATOMIC64 if !64BIT 14 select GENERIC_ATOMIC64 if !64BIT
15 select GENERIC_HARDIRQS_NO__DO_IRQ 15 select HAVE_GENERIC_HARDIRQS
16 select GENERIC_IRQ_PROBE
17 select IRQ_PER_CPU
18
16 help 19 help
17 The PA-RISC microprocessor is designed by Hewlett-Packard and used 20 The PA-RISC microprocessor is designed by Hewlett-Packard and used
18 in many of their workstations & servers (HP9000 700 and 800 series, 21 in many of their workstations & servers (HP9000 700 and 800 series,
@@ -66,22 +69,9 @@ config TIME_LOW_RES
66 depends on SMP 69 depends on SMP
67 default y 70 default y
68 71
69config GENERIC_HARDIRQS
70 def_bool y
71
72config GENERIC_IRQ_PROBE
73 def_bool y
74
75config HAVE_LATENCYTOP_SUPPORT 72config HAVE_LATENCYTOP_SUPPORT
76 def_bool y 73 def_bool y
77 74
78config IRQ_PER_CPU
79 bool
80 default y
81
82config GENERIC_HARDIRQS_NO__DO_IRQ
83 def_bool y
84
85# unless you want to implement ACPI on PA-RISC ... ;-) 75# unless you want to implement ACPI on PA-RISC ... ;-)
86config PM 76config PM
87 bool 77 bool
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 959f38ccb9a7..7d69e9bf5e64 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -36,24 +36,12 @@ config GENERIC_TIME_VSYSCALL
36config GENERIC_CLOCKEVENTS 36config GENERIC_CLOCKEVENTS
37 def_bool y 37 def_bool y
38 38
39config GENERIC_HARDIRQS
40 bool
41 default y
42
43config GENERIC_HARDIRQS_NO__DO_IRQ
44 bool
45 default y
46
47config HAVE_SETUP_PER_CPU_AREA 39config HAVE_SETUP_PER_CPU_AREA
48 def_bool PPC64 40 def_bool PPC64
49 41
50config NEED_PER_CPU_EMBED_FIRST_CHUNK 42config NEED_PER_CPU_EMBED_FIRST_CHUNK
51 def_bool PPC64 43 def_bool PPC64
52 44
53config IRQ_PER_CPU
54 bool
55 default y
56
57config NR_IRQS 45config NR_IRQS
58 int "Number of virtual interrupt numbers" 46 int "Number of virtual interrupt numbers"
59 range 32 32768 47 range 32 32768
@@ -143,6 +131,9 @@ config PPC
143 select HAVE_PERF_EVENTS 131 select HAVE_PERF_EVENTS
144 select HAVE_REGS_AND_STACK_ACCESS_API 132 select HAVE_REGS_AND_STACK_ACCESS_API
145 select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64 133 select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
134 select HAVE_GENERIC_HARDIRQS
135 select HAVE_SPARSE_IRQ
136 select IRQ_PER_CPU
146 137
147config EARLY_PRINTK 138config EARLY_PRINTK
148 bool 139 bool
@@ -392,19 +383,6 @@ config IRQ_ALL_CPUS
392 CPU. Generally saying Y is safe, although some problems have been 383 CPU. Generally saying Y is safe, although some problems have been
393 reported with SMP Power Macintoshes with this option enabled. 384 reported with SMP Power Macintoshes with this option enabled.
394 385
395config SPARSE_IRQ
396 bool "Support sparse irq numbering"
397 default n
398 help
399 This enables support for sparse irqs. This is useful for distro
400 kernels that want to define a high CONFIG_NR_CPUS value but still
401 want to have low kernel memory footprint on smaller machines.
402
403 ( Sparse IRQs can also be beneficial on NUMA boxes, as they spread
404 out the irq_desc[] array in a more NUMA-friendly way. )
405
406 If you don't know what to do here, say N.
407
408config NUMA 386config NUMA
409 bool "NUMA support" 387 bool "NUMA support"
410 depends on PPC64 388 depends on PPC64
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 4293fdcb5398..27b2295f41f3 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -1,5 +1,9 @@
1menu "Machine selection" 1menu "Machine selection"
2 2
3config SCORE
4 def_bool y
5 select HAVE_GENERIC_HARDIRQS
6
3choice 7choice
4 prompt "System type" 8 prompt "System type"
5 default MACH_SPCT6600 9 default MACH_SPCT6600
@@ -53,9 +57,6 @@ config GENERIC_CLOCKEVENTS
53config SCHED_NO_NO_OMIT_FRAME_POINTER 57config SCHED_NO_NO_OMIT_FRAME_POINTER
54 def_bool y 58 def_bool y
55 59
56config GENERIC_HARDIRQS_NO__DO_IRQ
57 def_bool y
58
59config GENERIC_SYSCALL_TABLE 60config GENERIC_SYSCALL_TABLE
60 def_bool y 61 def_bool y
61 62
@@ -68,9 +69,6 @@ menu "Kernel type"
68config 32BIT 69config 32BIT
69 def_bool y 70 def_bool y
70 71
71config GENERIC_HARDIRQS
72 def_bool y
73
74config ARCH_FLATMEM_ENABLE 72config ARCH_FLATMEM_ENABLE
75 def_bool y 73 def_bool y
76 74
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 45d9c87d083a..95695e97703e 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -50,6 +50,7 @@ config SPARC64
50 select RTC_DRV_STARFIRE 50 select RTC_DRV_STARFIRE
51 select HAVE_PERF_EVENTS 51 select HAVE_PERF_EVENTS
52 select PERF_USE_VMALLOC 52 select PERF_USE_VMALLOC
53 select HAVE_GENERIC_HARDIRQS
53 54
54config ARCH_DEFCONFIG 55config ARCH_DEFCONFIG
55 string 56 string
@@ -107,10 +108,6 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
107config NEED_PER_CPU_PAGE_FIRST_CHUNK 108config NEED_PER_CPU_PAGE_FIRST_CHUNK
108 def_bool y if SPARC64 109 def_bool y if SPARC64
109 110
110config GENERIC_HARDIRQS_NO__DO_IRQ
111 bool
112 def_bool y if SPARC64
113
114config MMU 111config MMU
115 bool 112 bool
116 default y 113 default y
@@ -276,10 +273,6 @@ config HOTPLUG_CPU
276 can be controlled through /sys/devices/system/cpu/cpu#. 273 can be controlled through /sys/devices/system/cpu/cpu#.
277 Say N if you want to disable CPU hotplug. 274 Say N if you want to disable CPU hotplug.
278 275
279config GENERIC_HARDIRQS
280 bool
281 default y if SPARC64
282
283source "kernel/time/Kconfig" 276source "kernel/time/Kconfig"
284 277
285if SPARC64 278if SPARC64
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index 4e8b82bca9e5..08948e4e1503 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -1,24 +1,33 @@
1# For a description of the syntax of this configuration file, 1# For a description of the syntax of this configuration file,
2# see Documentation/kbuild/config-language.txt. 2# see Documentation/kbuild/config-language.txt.
3 3
4config MMU 4config TILE
5 def_bool y
6
7config GENERIC_CSUM
8 def_bool y
9
10config GENERIC_HARDIRQS
11 def_bool y 5 def_bool y
6 select HAVE_KVM if !TILEGX
7 select GENERIC_FIND_FIRST_BIT
8 select GENERIC_FIND_NEXT_BIT
9 select USE_GENERIC_SMP_HELPERS
10 select CC_OPTIMIZE_FOR_SIZE
11 select HAVE_GENERIC_HARDIRQS
12 select GENERIC_IRQ_PROBE
13 select GENERIC_PENDING_IRQ if SMP
12 14
13config GENERIC_HARDIRQS_NO__DO_IRQ 15# FIXME: investigate whether we need/want these options.
14 def_bool y 16# select HAVE_IOREMAP_PROT
17# select HAVE_OPTPROBES
18# select HAVE_REGS_AND_STACK_ACCESS_API
19# select HAVE_HW_BREAKPOINT
20# select PERF_EVENTS
21# select HAVE_USER_RETURN_NOTIFIER
22# config NO_BOOTMEM
23# config ARCH_SUPPORTS_DEBUG_PAGEALLOC
24# config HUGETLB_PAGE_SIZE_VARIABLE
15 25
16config GENERIC_IRQ_PROBE 26config MMU
17 def_bool y 27 def_bool y
18 28
19config GENERIC_PENDING_IRQ 29config GENERIC_CSUM
20 def_bool y 30 def_bool y
21 depends on GENERIC_HARDIRQS && SMP
22 31
23config SEMAPHORE_SLEEPERS 32config SEMAPHORE_SLEEPERS
24 def_bool y 33 def_bool y
@@ -97,26 +106,6 @@ config HVC_TILE
97 select HVC_DRIVER 106 select HVC_DRIVER
98 def_bool y 107 def_bool y
99 108
100config TILE
101 def_bool y
102 select HAVE_KVM if !TILEGX
103 select GENERIC_FIND_FIRST_BIT
104 select GENERIC_FIND_NEXT_BIT
105 select USE_GENERIC_SMP_HELPERS
106 select CC_OPTIMIZE_FOR_SIZE
107
108# FIXME: investigate whether we need/want these options.
109# select HAVE_IOREMAP_PROT
110# select HAVE_OPTPROBES
111# select HAVE_REGS_AND_STACK_ACCESS_API
112# select HAVE_HW_BREAKPOINT
113# select PERF_EVENTS
114# select HAVE_USER_RETURN_NOTIFIER
115# config NO_BOOTMEM
116# config ARCH_SUPPORTS_DEBUG_PAGEALLOC
117# config HUGETLB_PAGE_SIZE_VARIABLE
118
119
120# Please note: TILE-Gx support is not yet finalized; this is 109# Please note: TILE-Gx support is not yet finalized; this is
121# the preliminary support. TILE-Gx drivers are only provided 110# the preliminary support. TILE-Gx drivers are only provided
122# with the alpha or beta test versions for Tilera customers. 111# with the alpha or beta test versions for Tilera customers.
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index 049d048b070d..e351e14b4339 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -3,14 +3,10 @@ config DEFCONFIG_LIST
3 option defconfig_list 3 option defconfig_list
4 default "arch/$ARCH/defconfig" 4 default "arch/$ARCH/defconfig"
5 5
6# UML uses the generic IRQ subsystem
7config GENERIC_HARDIRQS
8 bool
9 default y
10
11config UML 6config UML
12 bool 7 bool
13 default y 8 default y
9 select HAVE_GENERIC_HARDIRQS
14 10
15config MMU 11config MMU
16 bool 12 bool
diff --git a/arch/um/Kconfig.um b/arch/um/Kconfig.um
index f8d1d0d47fe6..90a438acbfaf 100644
--- a/arch/um/Kconfig.um
+++ b/arch/um/Kconfig.um
@@ -120,9 +120,6 @@ config SMP
120 120
121 If you don't know what to do, say N. 121 If you don't know what to do, say N.
122 122
123config GENERIC_HARDIRQS_NO__DO_IRQ
124 def_bool y
125
126config NR_CPUS 123config NR_CPUS
127 int "Maximum number of CPUs (2-32)" 124 int "Maximum number of CPUs (2-32)"
128 range 2 32 125 range 2 32
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-30 11:58:00 -0500