Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6 into sh-fixes-for-linus

840 files changed, 27360 insertions, 26065 deletions

diff --git a/arch/Kconfig b/arch/Kconfig
index 8d24bacaa61e..26b0e2397a57 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -175,4 +175,7 @@ config HAVE_ARCH_JUMP_LABEL
 config HAVE_ARCH_MUTEX_CPU_RELAX
         bool
 
+config HAVE_RCU_TABLE_FREE
+        bool
+
 source "kernel/gcov/Kconfig"
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 9808998cc073..60219bf94198 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -12,6 +12,7 @@ config ALPHA
         select GENERIC_IRQ_PROBE
         select AUTO_IRQ_AFFINITY if SMP
         select GENERIC_IRQ_SHOW
+        select ARCH_WANT_OPTIONAL_GPIOLIB
         help
           The Alpha is a 64-bit general-purpose processor designed and
           marketed by the Digital Equipment Corporation of blessed memory,
@@ -40,10 +41,6 @@ config ARCH_HAS_ILOG2_U64
         bool
         default n
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
 config GENERIC_CALIBRATE_DELAY
         bool
         default y
@@ -51,6 +48,9 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_CMOS_UPDATE
         def_bool y
 
+config GENERIC_GPIO
+        def_bool y
+
 config ZONE_DMA
         bool
         default y
diff --git a/arch/alpha/include/asm/gpio.h b/arch/alpha/include/asm/gpio.h
new file mode 100644
index 000000000000..7dc6a6343c06
--- /dev/null
+++ b/arch/alpha/include/asm/gpio.h
@@ -0,0 +1,55 @@
+/*
+ * Generic GPIO API implementation for Alpha.
+ *
+ * A stright copy of that for PowerPC which was:
+ *
+ * Copyright (c) 2007-2008  MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _ASM_ALPHA_GPIO_H
+#define _ASM_ALPHA_GPIO_H
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_GPIOLIB
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+        return -EINVAL;
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+#endif /* _ASM_ALPHA_GPIO_H */
diff --git a/arch/alpha/include/asm/smp.h b/arch/alpha/include/asm/smp.h
index 3f390e8cc0b3..c46e714aa3e0 100644
--- a/arch/alpha/include/asm/smp.h
+++ b/arch/alpha/include/asm/smp.h
@@ -39,8 +39,6 @@ struct cpuinfo_alpha {
 
 extern struct cpuinfo_alpha cpu_data[NR_CPUS];
 
-#define PROC_CHANGE_PENALTY     20
-
 #define hard_smp_processor_id() __hard_smp_processor_id()
 #define raw_smp_processor_id()  (current_thread_info()->cpu)
 
diff --git a/arch/alpha/include/asm/unistd.h b/arch/alpha/include/asm/unistd.h
index b1834166922d..4ac48a095f3a 100644
--- a/arch/alpha/include/asm/unistd.h
+++ b/arch/alpha/include/asm/unistd.h
@@ -456,10 +456,11 @@
 #define __NR_open_by_handle_at          498
 #define __NR_clock_adjtime              499
 #define __NR_syncfs                     500
+#define __NR_setns                      501
 
 #ifdef __KERNEL__
 
-#define NR_SYSCALLS                     501
+#define NR_SYSCALLS                     502
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 3ec35066f1dc..838eac128409 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -121,7 +121,7 @@ common_shutdown_1(void *generic_ptr)
         /* Wait for the secondaries to halt. */
         set_cpu_present(boot_cpuid, false);
         set_cpu_possible(boot_cpuid, false);
-        while (cpus_weight(cpu_present_map))
+        while (cpumask_weight(cpu_present_mask))
                 barrier();
 #endif
 
diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c
index edbddcbd5bc6..cc0fd862cf26 100644
--- a/arch/alpha/kernel/setup.c
+++ b/arch/alpha/kernel/setup.c
@@ -1257,7 +1257,7 @@ show_cpuinfo(struct seq_file *f, void *slot)
 #ifdef CONFIG_SMP
         seq_printf(f, "cpus active\t\t: %u\n"
                       "cpu active mask\t\t: %016lx\n",
-                       num_online_cpus(), cpus_addr(cpu_possible_map)[0]);
+                       num_online_cpus(), cpumask_bits(cpu_possible_mask)[0]);
 #endif
 
         show_cache_size (f, "L1 Icache", alpha_l1i_cacheshape);
diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index 5a621c6d22ab..d739703608fc 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -451,7 +451,7 @@ setup_smp(void)
         }
 
         printk(KERN_INFO "SMP: %d CPUs probed -- cpu_present_map = %lx\n",
-               smp_num_probed, cpu_present_map.bits[0]);
+               smp_num_probed, cpumask_bits(cpu_present_mask)[0]);
 }
 
 /*
@@ -629,8 +629,9 @@ smp_send_reschedule(int cpu)
 void
 smp_send_stop(void)
 {
-        cpumask_t to_whom = cpu_possible_map;
-        cpu_clear(smp_processor_id(), to_whom);
+        cpumask_t to_whom;
+        cpumask_copy(&to_whom, cpu_possible_mask);
+        cpumask_clear_cpu(smp_processor_id(), &to_whom);
 #ifdef DEBUG_IPI_MSG
         if (hard_smp_processor_id() != boot_cpu_id)
                 printk(KERN_WARNING "smp_send_stop: Not on boot cpu.\n");
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index 5ac00fd4cd0c..f8856829c22a 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -140,7 +140,7 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
 
         for (cpu = 0; cpu < 4; cpu++) {
                 unsigned long aff = cpu_irq_affinity[cpu];
-                if (cpu_isset(cpu, affinity))
+                if (cpumask_test_cpu(cpu, &affinity))
                         aff |= 1UL << irq;
                 else
                         aff &= ~(1UL << irq);
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index fea0e4620994..6994407e242a 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -65,10 +65,11 @@ titan_update_irq_hw(unsigned long mask)
         register int bcpu = boot_cpuid;
 
 #ifdef CONFIG_SMP
-        cpumask_t cpm = cpu_present_map;
+        cpumask_t cpm;
         volatile unsigned long *dim0, *dim1, *dim2, *dim3;
         unsigned long mask0, mask1, mask2, mask3, dummy;
 
+        cpumask_copy(&cpm, cpu_present_mask);
         mask &= ~isa_enable;
         mask0 = mask & titan_cpu_irq_affinity[0];
         mask1 = mask & titan_cpu_irq_affinity[1];
@@ -84,10 +85,10 @@ titan_update_irq_hw(unsigned long mask)
         dim1 = &cchip->dim1.csr;
         dim2 = &cchip->dim2.csr;
         dim3 = &cchip->dim3.csr;
-        if (!cpu_isset(0, cpm)) dim0 = &dummy;
-        if (!cpu_isset(1, cpm)) dim1 = &dummy;
-        if (!cpu_isset(2, cpm)) dim2 = &dummy;
-        if (!cpu_isset(3, cpm)) dim3 = &dummy;
+        if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
+        if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
+        if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
+        if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
 
         *dim0 = mask0;
         *dim1 = mask1;
@@ -137,7 +138,7 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
         int cpu;
 
         for (cpu = 0; cpu < 4; cpu++) {
-                if (cpu_isset(cpu, affinity))
+                if (cpumask_test_cpu(cpu, &affinity))
                         titan_cpu_irq_affinity[cpu] |= 1UL << irq;
                 else
                         titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
diff --git a/arch/alpha/kernel/systbls.S b/arch/alpha/kernel/systbls.S
index 15f999d41c75..b9c28f3f1956 100644
--- a/arch/alpha/kernel/systbls.S
+++ b/arch/alpha/kernel/systbls.S
@@ -519,6 +519,7 @@ sys_call_table:
         .quad sys_open_by_handle_at
         .quad sys_clock_adjtime
         .quad sys_syncfs                        /* 500 */
+        .quad sys_setns
 
         .size sys_call_table, . - sys_call_table
         .type sys_call_table, @object
diff --git a/arch/alpha/kernel/vmlinux.lds.S b/arch/alpha/kernel/vmlinux.lds.S
index 3d890a98a08b..f937ad123852 100644
--- a/arch/alpha/kernel/vmlinux.lds.S
+++ b/arch/alpha/kernel/vmlinux.lds.S
@@ -39,7 +39,7 @@ SECTIONS
         __init_begin = ALIGN(PAGE_SIZE);
         INIT_TEXT_SECTION(PAGE_SIZE)
         INIT_DATA_SECTION(16)
-        PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+        PERCPU_SECTION(L1_CACHE_BYTES)
         /* Align to THREAD_SIZE rather than PAGE_SIZE here so any padding page
            needed for the THREAD_SIZE aligned init_task gets freed after init */
         . = ALIGN(THREAD_SIZE);
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 86425ab53bf5..69d0c5761e2f 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -32,8 +32,6 @@
 #include <asm/console.h>
 #include <asm/tlb.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 extern void die_if_kernel(char *,struct pt_regs *,long);
 
 static struct pcb_struct original_pcb;
diff --git a/arch/alpha/mm/numa.c b/arch/alpha/mm/numa.c
index 7b2c56d8f930..3973ae395772 100644
--- a/arch/alpha/mm/numa.c
+++ b/arch/alpha/mm/numa.c
@@ -313,6 +313,7 @@ void __init paging_init(void)
                         zones_size[ZONE_DMA] = dma_local_pfn;
                         zones_size[ZONE_NORMAL] = (end_pfn - start_pfn) - dma_local_pfn;
                 }
+                node_set_state(nid, N_NORMAL_MEMORY);
                 free_area_init_node(nid, zones_size, start_pfn, NULL);
         }
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7275009686e6..9adc278a22ab 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -294,6 +294,8 @@ config ARCH_AT91
         bool "Atmel AT91"
         select ARCH_REQUIRE_GPIOLIB
         select HAVE_CLK
+        select CLKDEV_LOOKUP
+        select ARM_PATCH_PHYS_VIRT if MMU
         help
           This enables support for systems based on the Atmel AT91RM9200,
           AT91SAM9 and AT91CAP9 processors.
@@ -730,16 +732,6 @@ config ARCH_S5P64X0
           Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
           SMDK6450.
 
-config ARCH_S5P6442
-        bool "Samsung S5P6442"
-        select CPU_V6
-        select GENERIC_GPIO
-        select HAVE_CLK
-        select ARCH_USES_GETTIMEOFFSET
-        select HAVE_S3C2410_WATCHDOG if WATCHDOG
-        help
-          Samsung S5P6442 CPU based systems
-
 config ARCH_S5PC100
         bool "Samsung S5PC100"
         select GENERIC_GPIO
@@ -991,8 +983,6 @@ endif
 
 source "arch/arm/mach-s5p64x0/Kconfig"
 
-source "arch/arm/mach-s5p6442/Kconfig"
-
 source "arch/arm/mach-s5pc100/Kconfig"
 
 source "arch/arm/mach-s5pv210/Kconfig"
@@ -1399,7 +1389,6 @@ config NR_CPUS
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
         depends on SMP && HOTPLUG && EXPERIMENTAL
-        depends on !ARCH_MSM
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
@@ -1420,7 +1409,7 @@ source kernel/Kconfig.preempt
 config HZ
         int
         default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
-                ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
+                ARCH_S5PV210 || ARCH_EXYNOS4
         default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
         default AT91_TIMER_HZ if ARCH_AT91
         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
@@ -1516,6 +1505,9 @@ config ARCH_SPARSEMEM_DEFAULT
 config ARCH_SELECT_MEMORY_MODEL
         def_bool ARCH_SPARSEMEM_ENABLE
 
+config HAVE_ARCH_PFN_VALID
+        def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
+
 config HIGHMEM
         bool "High Memory Support"
         depends on MMU
@@ -1683,6 +1675,13 @@ endmenu
 
 menu "Boot options"
 
+config USE_OF
+        bool "Flattened Device Tree support"
+        select OF
+        select OF_EARLY_FLATTREE
+        help
+          Include support for flattened device tree machine descriptions.
+
 # Compressed boot loader in ROM.  Yes, we really want to ask about
 # TEXT and BSS so we preserve their values in the config files.
 config ZBOOT_ROM_TEXT
@@ -2021,7 +2020,7 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
-        depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100
+        depends on !ARCH_S5P64X0 && !ARCH_S5PC100
         depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
         def_bool y
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 03d01d783e3b..81cbe40c159c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -63,13 +63,6 @@ config DEBUG_USER
               8 - SIGSEGV faults
              16 - SIGBUS faults
 
-config DEBUG_STACK_USAGE
-        bool "Enable stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T output.
-
 # These options are only for real kernel hackers who want to get their hands dirty.
 config DEBUG_LL
         bool "Kernel low-level debugging functions"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 25750bcb3397..f5b2b390c8f2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -176,7 +176,6 @@ machine-$(CONFIG_ARCH_S3C2410)		:= s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c24
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c64xx
 machine-$(CONFIG_ARCH_S5P64X0)          := s5p64x0
-machine-$(CONFIG_ARCH_S5P6442)          := s5p6442
 machine-$(CONFIG_ARCH_S5PC100)          := s5pc100
 machine-$(CONFIG_ARCH_S5PV210)          := s5pv210
 machine-$(CONFIG_ARCH_EXYNOS4)          := exynos4
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index ea5ee4d067f3..4b71766fb21d 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -7,7 +7,7 @@ config ARM_VIC
 config ARM_VIC_NR
         int
         default 4 if ARCH_S5PV210
-        default 3 if ARCH_S5P6442 || ARCH_S5PC100
+        default 3 if ARCH_S5PC100
         default 2
         depends on ARM_VIC
         help
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig
deleted file mode 100644
index 1b1158ae8f82..000000000000
--- a/arch/arm/configs/at572d940hfek_defconfig
+++ /dev/null
@@ -1,358 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-AT572D940HF"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_XACCT=y
-CONFIG_TASK_IO_ACCOUNTING=y
-CONFIG_AUDIT=y
-CONFIG_CGROUPS=y
-CONFIG_CGROUP_CPUACCT=y
-CONFIG_CGROUP_SCHED=y
-CONFIG_RT_GROUP_SCHED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_RELAY=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT572D940HF=y
-CONFIG_MACH_AT572D940HFEB=y
-CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181"
-CONFIG_KEXEC=y
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_NET_PKTGEN=m
-CONFIG_NET_TCPPROBE=m
-CONFIG_CAN=m
-CONFIG_CAN_RAW=m
-CONFIG_CAN_BCM=m
-CONFIG_CAN_VCAN=m
-CONFIG_CAN_DEBUG_DEVICES=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_CONNECTOR=m
-CONFIG_MTD=m
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
-CONFIG_MTD_CONCAT=m
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_BLOCK_RO=m
-CONFIG_FTL=m
-CONFIG_NFTL=m
-CONFIG_NFTL_RW=y
-CONFIG_INFTL=m
-CONFIG_RFD_FTL=m
-CONFIG_SSFDC=m
-CONFIG_MTD_OOPS=m
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_CFI_INTELEXT=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_CFI_STAA=m
-CONFIG_MTD_ROM=m
-CONFIG_MTD_ABSENT=m
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=m
-CONFIG_MTD_PLATRAM=m
-CONFIG_MTD_DATAFLASH=m
-CONFIG_MTD_M25P80=m
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_BLOCK2MTD=m
-CONFIG_MTD_NAND=m
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_DISKONCHIP=m
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_MTD_NAND_PLATFORM=m
-CONFIG_MTD_ALAUDA=m
-CONFIG_MTD_UBI=m
-CONFIG_MTD_UBI_GLUEBI=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_ATMEL_TCLIB=y
-CONFIG_ATMEL_SSC=m
-CONFIG_SENSORS_TSL2550=m
-CONFIG_DS1682=m
-CONFIG_RAID_ATTRS=m
-CONFIG_SCSI=m
-CONFIG_SCSI_TGT=m
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
-CONFIG_SCSI_ISCSI_ATTRS=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_MACVLAN=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_VETH=m
-CONFIG_PHYLIB=y
-CONFIG_MARVELL_PHY=m
-CONFIG_DAVICOM_PHY=m
-CONFIG_QSEMI_PHY=m
-CONFIG_LXT_PHY=m
-CONFIG_CICADA_PHY=m
-CONFIG_VITESSE_PHY=m
-CONFIG_SMSC_PHY=m
-CONFIG_BROADCOM_PHY=m
-CONFIG_ICPLUS_PHY=m
-CONFIG_MDIO_BITBANG=m
-CONFIG_NET_ETHERNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_USB_ZD1201=m
-CONFIG_HOSTAP=m
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_DM9601=m
-CONFIG_USB_NET_GL620A=m
-CONFIG_USB_NET_PLUSB=m
-CONFIG_USB_NET_MCS7830=m
-CONFIG_USB_NET_RNDIS_HOST=m
-CONFIG_USB_ALI_M5632=y
-CONFIG_USB_AN2720=y
-CONFIG_USB_EPSON2888=y
-CONFIG_USB_KC2190=y
-# CONFIG_USB_NET_ZAURUS is not set
-CONFIG_INPUT_MOUSEDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_GPIO=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_STOWAWAY=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_APPLETOUCH=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_MOUSE_GPIO=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_N_HDLC=m
-CONFIG_SPECIALIX=m
-CONFIG_STALDRV=y
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_IPMI_HANDLER=m
-CONFIG_IPMI_DEVICE_INTERFACE=m
-CONFIG_IPMI_SI=m
-CONFIG_IPMI_WATCHDOG=m
-CONFIG_IPMI_POWEROFF=m
-CONFIG_HW_RANDOM=y
-CONFIG_R3964=m
-CONFIG_RAW_DRIVER=m
-CONFIG_TCG_TPM=m
-CONFIG_TCG_NSC=m
-CONFIG_TCG_ATMEL=m
-CONFIG_I2C=m
-CONFIG_I2C_CHARDEV=m
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_BITBANG=m
-CONFIG_SPI_SPIDEV=m
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-# CONFIG_SND_PCM_OSS_PLUGINS is not set
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DYNAMIC_MINORS=y
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SND_USB_CAIAQ=m
-CONFIG_SND_USB_CAIAQ_INPUT=y
-CONFIG_HID=m
-CONFIG_HIDRAW=y
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_PANTHERLORD=m
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-CONFIG_USB_DYNAMIC_MINORS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_ISD200=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_STORAGE_ALAUDA=m
-CONFIG_USB_STORAGE_KARMA=m
-CONFIG_USB_LIBUSUAL=y
-CONFIG_USB_SERIAL=m
-CONFIG_USB_EZUSB=y
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SPCP8X5=m
-CONFIG_USB_SERIAL_DEBUG=m
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-CONFIG_USB_ADUTUX=m
-CONFIG_USB_TEST=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_GADGET_DEBUG_FS=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_MIDI_GADGET=m
-CONFIG_MMC=y
-CONFIG_SDIO_UART=m
-CONFIG_MMC_AT91=m
-CONFIG_MMC_SPI=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_DS1307=m
-CONFIG_RTC_DRV_DS1305=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_JBD_DEBUG=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_CHECK=y
-CONFIG_REISERFS_PROC_INFO=y
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_INOTIFY=y
-CONFIG_FUSE_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_NTFS_FS=m
-CONFIG_NTFS_RW=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_CMODE_FAVOURLZO=y
-CONFIG_CRAMFS=m
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3_ACL=y
-CONFIG_NFSD_V4=y
-CONFIG_CIFS=m
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-CONFIG_SGI_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=m
-CONFIG_DLM=m
-CONFIG_PRINTK_TIME=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_UNUSED_SYMBOLS=y
-CONFIG_DEBUG_FS=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261_defconfig
index b46025b66b64..ade6b2f23116 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261_defconfig
@@ -1,9 +1,13 @@
 CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -15,18 +19,27 @@ CONFIG_ARCH_AT91SAM9261=y
 CONFIG_MACH_AT91SAM9261EK=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
 CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_INET_LRO is not set
 # CONFIG_IPV6 is not set
+CONFIG_CFG80211=y
+CONFIG_LIB80211=y
+CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
@@ -34,8 +47,12 @@ CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_TCLIB=y
 CONFIG_ATMEL_SSC=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
@@ -45,12 +62,27 @@ CONFIG_NET_ETHERNET=y
 CONFIG_DM9000=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_RTL8187=m
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+CONFIG_LIBERTAS_SPI=m
+CONFIG_RT2X00=m
+CONFIG_RT2500USB=m
+CONFIG_RT73USB=m
+CONFIG_ZD1211RW=m
+CONFIG_INPUT_POLLDEV=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
+CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -65,31 +97,62 @@ CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_ATMEL_LCDC=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_AT73C213=y
+CONFIG_SND_USB_AUDIO=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DEBUG=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
 CONFIG_MMC_AT91=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
+CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
-CONFIG_CRAMFS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_FTRACE=y
+CONFIG_CRC_CCITT=m
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263_defconfig
index 8a04d6f4e065..1cf96264cba1 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263_defconfig
@@ -1,9 +1,13 @@
 CONFIG_EXPERIMENTAL=y
 # CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZMA=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
+CONFIG_NAMESPACES=y
+CONFIG_EMBEDDED=y
 CONFIG_SLAB=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
@@ -13,53 +17,81 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9263=y
 CONFIG_MACH_AT91SAM9263EK=y
+CONFIG_MACH_USB_A9263=y
+CONFIG_MACH_NEOCORE926=y
 CONFIG_MTD_AT91_DATAFLASH_CARD=y
 # CONFIG_ARM_THUMB is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
-CONFIG_FPE_NWFPE=y
+CONFIG_AUTO_ZRELADDR=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
+CONFIG_NET_KEY=y
 CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_ROUTE_VERBOSE=y
 CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 CONFIG_IP_PNP_RARP=y
+CONFIG_NET_IPIP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
 # CONFIG_INET_XFRM_MODE_TRANSPORT is not set
 # CONFIG_INET_XFRM_MODE_TUNNEL is not set
 # CONFIG_INET_XFRM_MODE_BEET is not set
 # CONFIG_INET_LRO is not set
 # CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
 CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
 CONFIG_MTD_DATAFLASH=y
+CONFIG_MTD_BLOCK2MTD=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_ATMEL_SSC=y
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_PWM=y
+CONFIG_ATMEL_TCLIB=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_ETHERNET=y
 CONFIG_MACB=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_USB_ZD1201=m
+CONFIG_INPUT_POLLDEV=m
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
 # CONFIG_KEYBOARD_ATKBD is not set
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
 CONFIG_HW_RANDOM=y
@@ -74,8 +106,25 @@ CONFIG_WATCHDOG_NOWAYOUT=y
 CONFIG_AT91SAM9X_WATCHDOG=y
 CONFIG_FB=y
 CONFIG_FB_ATMEL=y
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_ATMEL_LCDC=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+CONFIG_SND_ATMEL_AC97C=y
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=m
 CONFIG_USB=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
@@ -83,24 +132,37 @@ CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
 CONFIG_USB_GADGETFS=m
 CONFIG_USB_FILE_STORAGE=m
 CONFIG_USB_G_SERIAL=m
 CONFIG_MMC=y
+CONFIG_SDIO_UART=m
 CONFIG_MMC_AT91=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_ATMEL_PWM=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
 CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
+CONFIG_FUSE_FS=m
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
+CONFIG_FTRACE=y
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
+CONFIG_XZ_DEC=y
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
index 2ffba24d2e2a..da53ff3b4d70 100644
--- a/arch/arm/configs/exynos4_defconfig
+++ b/arch/arm/configs/exynos4_defconfig
@@ -8,7 +8,9 @@ CONFIG_ARCH_EXYNOS4=y
 CONFIG_S3C_LOWLEVEL_UART_PORT=1
 CONFIG_MACH_SMDKC210=y
 CONFIG_MACH_SMDKV310=y
+CONFIG_MACH_ARMLEX4210=y
 CONFIG_MACH_UNIVERSAL_C210=y
+CONFIG_MACH_NURI=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
diff --git a/arch/arm/configs/neocore926_defconfig b/arch/arm/configs/neocore926_defconfig
deleted file mode 100644
index 462dd1850d15..000000000000
--- a/arch/arm/configs/neocore926_defconfig
+++ /dev/null
@@ -1,104 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9263=y
-CONFIG_MACH_NEOCORE926=y
-CONFIG_MTD_AT91_DATAFLASH_CARD=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_NET_KEY=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_NET_IPIP=y
-# CONFIG_INET_LRO is not set
-CONFIG_IPV6=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-CONFIG_MTD_BLOCK2MTD=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC_SMC=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_PLATFORM=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_ATMEL_PWM=y
-CONFIG_ATMEL_TCLIB=y
-CONFIG_SCSI=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MACB=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_DEVKMEM is not set
-CONFIG_SERIAL_NONSTANDARD=y
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-# CONFIG_SERIAL_ATMEL_PDC is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-CONFIG_VIDEO_OUTPUT_CONTROL=y
-CONFIG_FB=y
-CONFIG_FB_ATMEL=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_ATMEL_LCDC=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-CONFIG_LOGO=y
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_SDIO_UART=y
-CONFIG_MMC_AT91=m
-CONFIG_EXT2_FS=y
-# CONFIG_DNOTIFY is not set
-CONFIG_AUTOFS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 076db52ff672..d5f00d7eb075 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -21,58 +21,22 @@ CONFIG_MODVERSIONS=y
 CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_OMAP=y
-CONFIG_ARCH_OMAP2=y
-CONFIG_ARCH_OMAP3=y
-CONFIG_ARCH_OMAP4=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
-CONFIG_OMAP_32K_TIMER=y
-CONFIG_MACH_OMAP_GENERIC=y
-CONFIG_ARCH_OMAP2420=y
-CONFIG_ARCH_OMAP2430=y
-CONFIG_ARCH_OMAP3430=y
-CONFIG_MACH_OMAP_H4=y
-CONFIG_MACH_OMAP_APOLLON=y
-CONFIG_MACH_OMAP_2430SDP=y
-CONFIG_MACH_OMAP3_BEAGLE=y
-CONFIG_MACH_DEVKIT8000=y
-CONFIG_MACH_OMAP_LDP=y
-CONFIG_MACH_OVERO=y
-CONFIG_MACH_OMAP3EVM=y
-CONFIG_MACH_OMAP3517EVM=y
-CONFIG_MACH_OMAP3_PANDORA=y
-CONFIG_MACH_OMAP3_TOUCHBOOK=y
-CONFIG_MACH_OMAP_3430SDP=y
-CONFIG_MACH_NOKIA_N8X0=y
-CONFIG_MACH_NOKIA_RX51=y
-CONFIG_MACH_OMAP_ZOOM2=y
-CONFIG_MACH_OMAP_ZOOM3=y
-CONFIG_MACH_CM_T35=y
-CONFIG_MACH_IGEP0020=y
-CONFIG_MACH_SBC3530=y
-CONFIG_MACH_OMAP_3630SDP=y
-CONFIG_MACH_OMAP_4430SDP=y
 CONFIG_ARM_THUMBEE=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
-# CONFIG_LOCAL_TIMERS is not set
-CONFIG_AEABI=y
 CONFIG_LEDS=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
 CONFIG_KEXEC=y
 CONFIG_FPE_NWFPE=y
-CONFIG_VFP=y
-CONFIG_NEON=y
 CONFIG_BINFMT_MISC=y
-CONFIG_PM=y
 CONFIG_PM_DEBUG=y
-CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -89,14 +53,6 @@ CONFIG_IP_PNP_RARP=y
 # CONFIG_IPV6 is not set
 CONFIG_NETFILTER=y
 CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
 CONFIG_BT_HCIUART=m
 CONFIG_BT_HCIUART_H4=y
 CONFIG_BT_HCIUART_BCSP=y
@@ -107,11 +63,9 @@ CONFIG_CFG80211=m
 CONFIG_MAC80211=m
 CONFIG_MAC80211_RC_PID=y
 CONFIG_MAC80211_RC_DEFAULT_PID=y
-CONFIG_MAC80211_LEDS=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -127,7 +81,6 @@ CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_EEPROM_LEGACY=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_MULTI_LUN=y
@@ -158,19 +111,15 @@ CONFIG_TOUCHSCREEN_ADS7846=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_TWL4030_PWRBUTTON=y
 CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250_NR_UARTS=32
 CONFIG_SERIAL_8250_EXTENDED=y
 CONFIG_SERIAL_8250_MANY_PORTS=y
 CONFIG_SERIAL_8250_SHARE_IRQ=y
 CONFIG_SERIAL_8250_DETECT_IRQ=y
 CONFIG_SERIAL_8250_RSA=y
-# CONFIG_LEGACY_PTYS is not set
 CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_OMAP=y
 CONFIG_SPI=y
 CONFIG_SPI_OMAP24XX=y
 CONFIG_DEBUG_GPIO=y
@@ -181,10 +130,6 @@ CONFIG_POWER_SUPPLY=y
 CONFIG_WATCHDOG=y
 CONFIG_OMAP_WATCHDOG=y
 CONFIG_TWL4030_WATCHDOG=y
-CONFIG_MENELAUS=y
-CONFIG_TWL4030_CORE=y
-CONFIG_TWL4030_POWER=y
-CONFIG_REGULATOR=y
 CONFIG_REGULATOR_TWL4030=y
 CONFIG_REGULATOR_TPS65023=y
 CONFIG_REGULATOR_TPS6507X=y
@@ -208,7 +153,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_PLATFORM=y
 CONFIG_DISPLAY_SUPPORT=y
-# CONFIG_VGA_CONSOLE is not set
 CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_FONTS=y
@@ -217,25 +161,20 @@ CONFIG_FONT_8x16=y
 CONFIG_LOGO=y
 CONFIG_SOUND=m
 CONFIG_SND=m
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
 CONFIG_SND_VERBOSE_PRINTK=y
 CONFIG_SND_DEBUG=y
-CONFIG_SND_USB_AUDIO=y
-CONFIG_SND_SOC=y
-CONFIG_SND_OMAP_SOC=y
-CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=m
+CONFIG_SND_OMAP_SOC=m
+CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
 CONFIG_USB=y
 CONFIG_USB_DEBUG=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG_WHITELIST is not set
 CONFIG_USB_MON=y
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_MUSB_OTG is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-CONFIG_USB_MUSB_DEBUG=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
@@ -250,18 +189,12 @@ CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_SDIO_UART=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_TWL92330=y
 CONFIG_RTC_DRV_TWL4030=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_QUOTA=y
 CONFIG_QFMT_V2=y
 CONFIG_MSDOS_FS=y
@@ -285,12 +218,10 @@ CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 CONFIG_PRINTK_TIME=y
 CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
 CONFIG_DEBUG_KERNEL=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 CONFIG_PROVE_LOCKING=y
-# CONFIG_LOCK_STAT is not set
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
diff --git a/arch/arm/configs/s5p6442_defconfig b/arch/arm/configs/s5p6442_defconfig
deleted file mode 100644
index 0e92a784af66..000000000000
--- a/arch/arm/configs/s5p6442_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_S5P6442=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
-CONFIG_MACH_SMDK6442=y
-CONFIG_CPU_32v6K=y
-CONFIG_AEABI=y
-CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
-CONFIG_FPE_NWFPE=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_NR_UARTS=3
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_HW_RANDOM=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-CONFIG_CRAMFS=y
-CONFIG_ROMFS_FS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_ARM_UNWIND is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_S3C_UART=1
-CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/usb-a9263_defconfig b/arch/arm/configs/usb-a9263_defconfig
deleted file mode 100644
index ee82d09249c6..000000000000
--- a/arch/arm/configs/usb-a9263_defconfig
+++ /dev/null
@@ -1,106 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_AT91SAM9263=y
-CONFIG_MACH_USB_A9263=y
-CONFIG_AT91_SLOW_CLOCK=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_DATAFLASH=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ATMEL=y
-CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MACB=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_EVBUG=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_SPI=y
-CONFIG_SPI_ATMEL=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_HID is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_ETH=m
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_EXT2_FS=y
-CONFIG_INOTIFY=y
-CONFIG_FUSE_FS=m
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_LL=y
-# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 6b7403fd8f54..b4892a06442c 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -203,8 +203,6 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 #define find_first_bit(p,sz)            _find_first_bit_le(p,sz)
 #define find_next_bit(p,sz,off)         _find_next_bit_le(p,sz,off)
 
-#define WORD_BITOFF_TO_LE(x)            ((x))
-
 #else
 /*
  * These are the big endian, atomic definitions.
@@ -214,8 +212,6 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
 #define find_first_bit(p,sz)            _find_first_bit_be(p,sz)
 #define find_next_bit(p,sz,off)         _find_next_bit_be(p,sz,off)
 
-#define WORD_BITOFF_TO_LE(x)            ((x) ^ 0x18)
-
 #endif
 
 #if __LINUX_ARM_ARCH__ < 5
@@ -287,55 +283,29 @@ static inline int fls(int x)
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 
-static inline void __set_bit_le(int nr, void *addr)
-{
-        __set_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
-
-static inline void __clear_bit_le(int nr, void *addr)
-{
-        __clear_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
-
-static inline int __test_and_set_bit_le(int nr, void *addr)
-{
-        return __test_and_set_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
-
-static inline int test_and_set_bit_le(int nr, void *addr)
-{
-        return test_and_set_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
-
-static inline int __test_and_clear_bit_le(int nr, void *addr)
-{
-        return __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
-
-static inline int test_and_clear_bit_le(int nr, void *addr)
-{
-        return test_and_clear_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
-
-static inline int test_bit_le(int nr, const void *addr)
-{
-        return test_bit(WORD_BITOFF_TO_LE(nr), addr);
-}
+#ifdef __ARMEB__
 
 static inline int find_first_zero_bit_le(const void *p, unsigned size)
 {
         return _find_first_zero_bit_le(p, size);
 }
+#define find_first_zero_bit_le find_first_zero_bit_le
 
 static inline int find_next_zero_bit_le(const void *p, int size, int offset)
 {
         return _find_next_zero_bit_le(p, size, offset);
 }
+#define find_next_zero_bit_le find_next_zero_bit_le
 
 static inline int find_next_bit_le(const void *p, int size, int offset)
 {
         return _find_next_bit_le(p, size, offset);
 }
+#define find_next_bit_le find_next_bit_le
+
+#endif
+
+#include <asm-generic/bitops/le.h>
 
 /*
  * Ext2 is defined to use little-endian byte ordering.
diff --git a/arch/arm/include/asm/fiq.h b/arch/arm/include/asm/fiq.h
index 2242ce22ec6c..d493d0b742a1 100644
--- a/arch/arm/include/asm/fiq.h
+++ b/arch/arm/include/asm/fiq.h
@@ -4,6 +4,13 @@
  * Support for FIQ on ARM architectures.
  * Written by Philip Blundell <philb@gnu.org>, 1998
  * Re-written by Russell King
+ *
+ * NOTE: The FIQ mode registers are not magically preserved across
+ * suspend/resume.
+ *
+ * Drivers which require these registers to be preserved across power
+ * management operations must implement appropriate suspend/resume handlers to
+ * save and restore them.
  */
 
 #ifndef __ASM_FIQ_H
@@ -29,9 +36,21 @@ struct fiq_handler {
 extern int claim_fiq(struct fiq_handler *f);
 extern void release_fiq(struct fiq_handler *f);
 extern void set_fiq_handler(void *start, unsigned int length);
-extern void set_fiq_regs(struct pt_regs *regs);
-extern void get_fiq_regs(struct pt_regs *regs);
 extern void enable_fiq(int fiq);
 extern void disable_fiq(int fiq);
 
+/* helpers defined in fiqasm.S: */
+extern void __set_fiq_regs(unsigned long const *regs);
+extern void __get_fiq_regs(unsigned long *regs);
+
+static inline void set_fiq_regs(struct pt_regs const *regs)
+{
+        __set_fiq_regs(&regs->ARM_r8);
+}
+
+static inline void get_fiq_regs(struct pt_regs *regs)
+{
+        __get_fiq_regs(&regs->ARM_r8);
+}
+
 #endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index bf13b814c1b8..946f4d778f71 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -18,6 +18,8 @@ struct machine_desc {
         unsigned int            nr;             /* architecture number  */
         const char              *name;          /* architecture name    */
         unsigned long           boot_params;    /* tagged list          */
+        const char              **dt_compat;    /* array of device tree
+                                                 * 'compatible' strings */
 
         unsigned int            nr_irqs;        /* number of IRQs */
 
@@ -48,6 +50,13 @@ struct machine_desc {
 extern struct machine_desc *machine_desc;
 
 /*
+ * Machine type table - also only accessible during boot
+ */
+extern struct machine_desc __arch_info_begin[], __arch_info_end[];
+#define for_each_machine_desc(p)                        \
+        for (p = __arch_info_begin; p < __arch_info_end; p++)
+
+/*
  * Set of macros to define architecture features.  This is built into
  * a table by the linker.
  */
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index f51a69595f6e..ac75d0848889 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -197,7 +197,7 @@ typedef unsigned long pgprot_t;
 
 typedef struct page *pgtable_t;
 
-#ifndef CONFIG_SPARSEMEM
+#ifdef CONFIG_HAVE_ARCH_PFN_VALID
 extern int pfn_valid(unsigned long);
 #endif
 
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
new file mode 100644
index 000000000000..11b8708fc4db
--- /dev/null
+++ b/arch/arm/include/asm/prom.h
@@ -0,0 +1,37 @@
+/*
+ *  arch/arm/include/asm/prom.h
+ *
+ *  Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASMARM_PROM_H
+#define __ASMARM_PROM_H
+
+#ifdef CONFIG_OF
+
+#include <asm/setup.h>
+#include <asm/irq.h>
+
+static inline void irq_dispose_mapping(unsigned int virq)
+{
+        return;
+}
+
+extern struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
+extern void arm_dt_memblock_reserve(void);
+
+#else /* CONFIG_OF */
+
+static inline struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
+{
+        return NULL;
+}
+
+static inline void arm_dt_memblock_reserve(void) { }
+
+#endif /* CONFIG_OF */
+#endif /* ASMARM_PROM_H */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 95176af3df8c..ee2ad8ae07af 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -217,6 +217,10 @@ extern struct meminfo meminfo;
 #define bank_phys_end(bank)     ((bank)->start + (bank)->size)
 #define bank_phys_size(bank)    (bank)->size
 
+extern int arm_add_memory(phys_addr_t start, unsigned long size);
+extern void early_print(const char *str, ...);
+extern void dump_machine_table(void);
+
 #endif  /*  __KERNEL__  */
 
 #endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index a87664f54f93..e42d96a45d3e 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -20,12 +20,6 @@
 
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 
-/*
- * at the moment, there's not a big penalty for changing CPUs
- * (the >big< penalty is running SMP in the first place)
- */
-#define PROC_CHANGE_PENALTY             15
-
 struct seq_file;
 
 /*
@@ -76,6 +70,7 @@ extern void platform_smp_prepare_cpus(unsigned int);
  */
 struct secondary_data {
         unsigned long pgdir;
+        unsigned long swapper_pg_dir;
         void *stack;
 };
 extern struct secondary_data secondary_data;
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 82dfe5d0c41e..265f908c4a6e 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -41,12 +41,12 @@
  */
 #if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
 #define tlb_fast_mode(tlb)      0
-#define FREE_PTE_NR             500
 #else
 #define tlb_fast_mode(tlb)      1
-#define FREE_PTE_NR             0
 #endif
 
+#define MMU_GATHER_BUNDLE       8
+
 /*
  * TLB handling.  This allows us to remove pages from the page
  * tables, and efficiently handle the TLB issues.
@@ -58,7 +58,9 @@ struct mmu_gather {
         unsigned long           range_start;
         unsigned long           range_end;
         unsigned int            nr;
-        struct page             *pages[FREE_PTE_NR];
+        unsigned int            max;
+        struct page             **pages;
+        struct page             *local[MMU_GATHER_BUNDLE];
 };
 
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -97,26 +99,37 @@ static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
         }
 }
 
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
+{
+        unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
+
+        if (addr) {
+                tlb->pages = (void *)addr;
+                tlb->max = PAGE_SIZE / sizeof(struct page *);
+        }
+}
+
 static inline void tlb_flush_mmu(struct mmu_gather *tlb)
 {
         tlb_flush(tlb);
         if (!tlb_fast_mode(tlb)) {
                 free_pages_and_swap_cache(tlb->pages, tlb->nr);
                 tlb->nr = 0;
+                if (tlb->pages == tlb->local)
+                        __tlb_alloc_page(tlb);
         }
 }
 
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm)
 {
-        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
         tlb->mm = mm;
-        tlb->fullmm = full_mm_flush;
+        tlb->fullmm = fullmm;
         tlb->vma = NULL;
+        tlb->max = ARRAY_SIZE(tlb->local);
+        tlb->pages = tlb->local;
         tlb->nr = 0;
-
-        return tlb;
+        __tlb_alloc_page(tlb);
 }
 
 static inline void
@@ -127,7 +140,8 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
         /* keep the page table cache within bounds */
         check_pgt_cache();
 
-        put_cpu_var(mmu_gathers);
+        if (tlb->pages != tlb->local)
+                free_pages((unsigned long)tlb->pages, 0);
 }
 
 /*
@@ -162,15 +176,22 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
                 tlb_flush(tlb);
 }
 
-static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
         if (tlb_fast_mode(tlb)) {
                 free_page_and_swap_cache(page);
-        } else {
-                tlb->pages[tlb->nr++] = page;
-                if (tlb->nr >= FREE_PTE_NR)
-                        tlb_flush_mmu(tlb);
+                return 1; /* avoid calling tlb_flush_mmu */
         }
+
+        tlb->pages[tlb->nr++] = page;
+        VM_BUG_ON(tlb->nr > tlb->max);
+        return tlb->max - tlb->nr;
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        if (!__tlb_remove_page(tlb, page))
+                tlb_flush_mmu(tlb);
 }
 
 static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 87dbe3e21970..2c04ed5efeb5 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -400,6 +400,8 @@
 #define __NR_open_by_handle_at          (__NR_SYSCALL_BASE+371)
 #define __NR_clock_adjtime              (__NR_SYSCALL_BASE+372)
 #define __NR_syncfs                     (__NR_SYSCALL_BASE+373)
+#define __NR_sendmmsg                   (__NR_SYSCALL_BASE+374)
+#define __NR_setns                      (__NR_SYSCALL_BASE+375)
 
 /*
  * The following SWIs are ARM private.
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 8d95446150a3..a5b31af5c2b8 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -24,7 +24,7 @@ obj-$(CONFIG_OC_ETM)		+= etm.o
 
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
 obj-$(CONFIG_ARCH_ACORN)        += ecard.o 
-obj-$(CONFIG_FIQ)               += fiq.o
+obj-$(CONFIG_FIQ)               += fiq.o fiqasm.o
 obj-$(CONFIG_MODULES)           += armksyms.o module.o
 obj-$(CONFIG_ARTHUR)            += arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
@@ -44,6 +44,7 @@ obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)              += kgdb.o
 obj-$(CONFIG_ARM_UNWIND)        += unwind.o
 obj-$(CONFIG_HAVE_TCM)          += tcm.o
+obj-$(CONFIG_OF)                += devtree.o
 obj-$(CONFIG_CRASH_DUMP)        += crash_dump.o
 obj-$(CONFIG_SWP_EMULATE)       += swp_emulate.o
 CFLAGS_swp_emulate.o            := -Wa,-march=armv7-a
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index 7fbf28c35bb2..80f7896cc016 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -383,6 +383,8 @@
                 CALL(sys_open_by_handle_at)
                 CALL(sys_clock_adjtime)
                 CALL(sys_syncfs)
+                CALL(sys_sendmmsg)
+/* 375 */       CALL(sys_setns)
 #ifndef syscalls_counted
 .equ syscalls_padding, ((NR_syscalls + 3) & ~3) - NR_syscalls
 #define syscalls_counted
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
new file mode 100644
index 000000000000..a701e4226a6c
--- /dev/null
+++ b/arch/arm/kernel/devtree.c
@@ -0,0 +1,145 @@
+/*
+ *  linux/arch/arm/kernel/devtree.c
+ *
+ *  Copyright (C) 2009 Canonical Ltd. <jeremy.kerr@canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/bootmem.h>
+#include <linux/memblock.h>
+#include <linux/of.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+void __init early_init_dt_add_memory_arch(u64 base, u64 size)
+{
+        arm_add_memory(base, size);
+}
+
+void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
+{
+        return alloc_bootmem_align(size, align);
+}
+
+void __init arm_dt_memblock_reserve(void)
+{
+        u64 *reserve_map, base, size;
+
+        if (!initial_boot_params)
+                return;
+
+        /* Reserve the dtb region */
+        memblock_reserve(virt_to_phys(initial_boot_params),
+                         be32_to_cpu(initial_boot_params->totalsize));
+
+        /*
+         * Process the reserve map.  This will probably overlap the initrd
+         * and dtb locations which are already reserved, but overlaping
+         * doesn't hurt anything
+         */
+        reserve_map = ((void*)initial_boot_params) +
+                        be32_to_cpu(initial_boot_params->off_mem_rsvmap);
+        while (1) {
+                base = be64_to_cpup(reserve_map++);
+                size = be64_to_cpup(reserve_map++);
+                if (!size)
+                        break;
+                memblock_reserve(base, size);
+        }
+}
+
+/**
+ * setup_machine_fdt - Machine setup when an dtb was passed to the kernel
+ * @dt_phys: physical address of dt blob
+ *
+ * If a dtb was passed to the kernel in r2, then use it to choose the
+ * correct machine_desc and to setup the system.
+ */
+struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
+{
+        struct boot_param_header *devtree;
+        struct machine_desc *mdesc, *mdesc_best = NULL;
+        unsigned int score, mdesc_score = ~1;
+        unsigned long dt_root;
+        const char *model;
+
+        devtree = phys_to_virt(dt_phys);
+
+        /* check device tree validity */
+        if (be32_to_cpu(devtree->magic) != OF_DT_HEADER)
+                return NULL;
+
+        /* Search the mdescs for the 'best' compatible value match */
+        initial_boot_params = devtree;
+        dt_root = of_get_flat_dt_root();
+        for_each_machine_desc(mdesc) {
+                score = of_flat_dt_match(dt_root, mdesc->dt_compat);
+                if (score > 0 && score < mdesc_score) {
+                        mdesc_best = mdesc;
+                        mdesc_score = score;
+                }
+        }
+        if (!mdesc_best) {
+                const char *prop;
+                long size;
+
+                early_print("\nError: unrecognized/unsupported "
+                            "device tree compatible list:\n[ ");
+
+                prop = of_get_flat_dt_prop(dt_root, "compatible", &size);
+                while (size > 0) {
+                        early_print("'%s' ", prop);
+                        size -= strlen(prop) + 1;
+                        prop += strlen(prop) + 1;
+                }
+                early_print("]\n\n");
+
+                dump_machine_table(); /* does not return */
+        }
+
+        model = of_get_flat_dt_prop(dt_root, "model", NULL);
+        if (!model)
+                model = of_get_flat_dt_prop(dt_root, "compatible", NULL);
+        if (!model)
+                model = "<unknown>";
+        pr_info("Machine: %s, model: %s\n", mdesc_best->name, model);
+
+        /* Retrieve various information from the /chosen node */
+        of_scan_flat_dt(early_init_dt_scan_chosen, boot_command_line);
+        /* Initialize {size,address}-cells info */
+        of_scan_flat_dt(early_init_dt_scan_root, NULL);
+        /* Setup memory, calling early_init_dt_add_memory_arch */
+        of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+
+        /* Change machine number to match the mdesc we're using */
+        __machine_arch_type = mdesc_best->nr;
+
+        return mdesc_best;
+}
+
+/**
+ * irq_create_of_mapping - Hook to resolve OF irq specifier into a Linux irq#
+ *
+ * Currently the mapping mechanism is trivial; simple flat hwirq numbers are
+ * mapped 1:1 onto Linux irq numbers.  Cascaded irq controllers are not
+ * supported.
+ */
+unsigned int irq_create_of_mapping(struct device_node *controller,
+                                   const u32 *intspec, unsigned int intsize)
+{
+        return intspec[0];
+}
+EXPORT_SYMBOL_GPL(irq_create_of_mapping);
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index e72dc34eea1c..4c164ece5891 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -89,47 +89,6 @@ void set_fiq_handler(void *start, unsigned int length)
                 flush_icache_range(0x1c, 0x1c + length);
 }
 
-/*
- * Taking an interrupt in FIQ mode is death, so both these functions
- * disable irqs for the duration.  Note - these functions are almost
- * entirely coded in assembly.
- */
-void __naked set_fiq_regs(struct pt_regs *regs)
-{
-        register unsigned long tmp;
-        asm volatile (
-        "mov    ip, sp\n\
-        stmfd   sp!, {fp, ip, lr, pc}\n\
-        sub     fp, ip, #4\n\
-        mrs     %0, cpsr\n\
-        msr     cpsr_c, %2      @ select FIQ mode\n\
-        mov     r0, r0\n\
-        ldmia   %1, {r8 - r14}\n\
-        msr     cpsr_c, %0      @ return to SVC mode\n\
-        mov     r0, r0\n\
-        ldmfd   sp, {fp, sp, pc}"
-        : "=&r" (tmp)
-        : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
-}
-
-void __naked get_fiq_regs(struct pt_regs *regs)
-{
-        register unsigned long tmp;
-        asm volatile (
-        "mov    ip, sp\n\
-        stmfd   sp!, {fp, ip, lr, pc}\n\
-        sub     fp, ip, #4\n\
-        mrs     %0, cpsr\n\
-        msr     cpsr_c, %2      @ select FIQ mode\n\
-        mov     r0, r0\n\
-        stmia   %1, {r8 - r14}\n\
-        msr     cpsr_c, %0      @ return to SVC mode\n\
-        mov     r0, r0\n\
-        ldmfd   sp, {fp, sp, pc}"
-        : "=&r" (tmp)
-        : "r" (&regs->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
-}
-
 int claim_fiq(struct fiq_handler *f)
 {
         int ret = 0;
@@ -174,8 +133,8 @@ void disable_fiq(int fiq)
 }
 
 EXPORT_SYMBOL(set_fiq_handler);
-EXPORT_SYMBOL(set_fiq_regs);
-EXPORT_SYMBOL(get_fiq_regs);
+EXPORT_SYMBOL(__set_fiq_regs);  /* defined in fiqasm.S */
+EXPORT_SYMBOL(__get_fiq_regs);  /* defined in fiqasm.S */
 EXPORT_SYMBOL(claim_fiq);
 EXPORT_SYMBOL(release_fiq);
 EXPORT_SYMBOL(enable_fiq);
diff --git a/arch/arm/kernel/fiqasm.S b/arch/arm/kernel/fiqasm.S
new file mode 100644
index 000000000000..207f9d652010
--- /dev/null
+++ b/arch/arm/kernel/fiqasm.S
@@ -0,0 +1,49 @@
+/*
+ *  linux/arch/arm/kernel/fiqasm.S
+ *
+ *  Derived from code originally in linux/arch/arm/kernel/fiq.c:
+ *
+ *  Copyright (C) 1998 Russell King
+ *  Copyright (C) 1998, 1999 Phil Blundell
+ *  Copyright (C) 2011, Linaro Limited
+ *
+ *  FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
+ *
+ *  FIQ support re-written by Russell King to be more generic
+ *
+ *  v7/Thumb-2 compatibility modifications by Linaro Limited, 2011.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * Taking an interrupt in FIQ mode is death, so both these functions
+ * disable irqs for the duration.
+ */
+
+ENTRY(__set_fiq_regs)
+        mov     r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+        mrs     r1, cpsr
+        msr     cpsr_c, r2      @ select FIQ mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        ldmia   r0!, {r8 - r12}
+        ldr     sp, [r0], #4
+        ldr     lr, [r0]
+        msr     cpsr_c, r1      @ return to SVC mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        mov     pc, lr
+ENDPROC(__set_fiq_regs)
+
+ENTRY(__get_fiq_regs)
+        mov     r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
+        mrs     r1, cpsr
+        msr     cpsr_c, r2      @ select FIQ mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        stmia   r0!, {r8 - r12}
+        str     sp, [r0], #4
+        str     lr, [r0]
+        msr     cpsr_c, r1      @ return to SVC mode
+        mov     r0, r0          @ avoid hazard prior to ARMv4
+        mov     pc, lr
+ENDPROC(__get_fiq_regs)
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index c84b57d27d07..854bd22380d3 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -15,6 +15,12 @@
 #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
 #define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2)
 
+#ifdef CONFIG_CPU_BIG_ENDIAN
+#define OF_DT_MAGIC 0xd00dfeed
+#else
+#define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
+#endif
+
 /*
  * Exception handling.  Something went wrong and we can't proceed.  We
  * ought to tell the user, but since we don't have any guarantee that
@@ -28,20 +34,26 @@
 
 /* Determine validity of the r2 atags pointer.  The heuristic requires
  * that the pointer be aligned, in the first 16k of physical RAM and
- * that the ATAG_CORE marker is first and present.  Future revisions
+ * that the ATAG_CORE marker is first and present.  If CONFIG_OF_FLATTREE
+ * is selected, then it will also accept a dtb pointer.  Future revisions
  * of this function may be more lenient with the physical address and
  * may also be able to move the ATAGS block if necessary.
  *
  * Returns:
- *  r2 either valid atags pointer, or zero
+ *  r2 either valid atags pointer, valid dtb pointer, or zero
  *  r5, r6 corrupted
  */
 __vet_atags:
         tst     r2, #0x3                        @ aligned?
         bne     1f
 
-        ldr     r5, [r2, #0]                    @ is first tag ATAG_CORE?
-        cmp     r5, #ATAG_CORE_SIZE
+        ldr     r5, [r2, #0]
+#ifdef CONFIG_OF_FLATTREE
+        ldr     r6, =OF_DT_MAGIC                @ is it a DTB?
+        cmp     r5, r6
+        beq     2f
+#endif
+        cmp     r5, #ATAG_CORE_SIZE             @ is first tag ATAG_CORE?
         cmpne   r5, #ATAG_CORE_SIZE_EMPTY
         bne     1f
         ldr     r5, [r2, #4]
@@ -49,7 +61,7 @@ __vet_atags:
         cmp     r5, r6
         bne     1f
 
-        mov     pc, lr                          @ atag pointer is ok
+2:      mov     pc, lr                          @ atag/dtb pointer is ok
 
 1:      mov     r2, #0
         mov     pc, lr
@@ -61,7 +73,7 @@ ENDPROC(__vet_atags)
  *
  *  r0  = cp#15 control register
  *  r1  = machine ID
- *  r2  = atags pointer
+ *  r2  = atags/dtb pointer
  *  r9  = processor ID
  */
         __INIT
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index c9173cfbbc74..278c1b0ebb2e 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -59,7 +59,7 @@
  *
  * This is normally called from the decompressor code.  The requirements
  * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
- * r1 = machine nr, r2 = atags pointer.
+ * r1 = machine nr, r2 = atags or dtb pointer.
  *
  * This code is mostly position independent, so if you link the kernel at
  * 0xc0008000, you call this at __pa(0xc0008000).
@@ -91,7 +91,7 @@ ENTRY(stext)
 #endif
 
         /*
-         * r1 = machine no, r2 = atags,
+         * r1 = machine no, r2 = atags or dtb,
          * r8 = phys_offset, r9 = cpuid, r10 = procinfo
          */
         bl      __vet_atags
@@ -113,6 +113,7 @@ ENTRY(stext)
         ldr     r13, =__mmap_switched           @ address to jump to after
                                                 @ mmu has been enabled
         adr     lr, BSYM(1f)                    @ return (PIC) address
+        mov     r8, r4                          @ set TTBR1 to swapper_pg_dir
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
  THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
  THUMB( mov     pc, r12                         )
@@ -302,8 +303,10 @@ ENTRY(secondary_startup)
          */
         adr     r4, __secondary_data
         ldmia   r4, {r5, r7, r12}               @ address to jump to after
-        sub     r4, r4, r5                      @ mmu has been enabled
-        ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
+        sub     lr, r4, r5                      @ mmu has been enabled
+        ldr     r4, [r7, lr]                    @ get secondary_data.pgdir
+        add     r7, r7, #4
+        ldr     r8, [r7, lr]                    @ get secondary_data.swapper_pg_dir
         adr     lr, BSYM(__enable_mmu)          @ return address
         mov     r13, r12                        @ __secondary_switched address
  ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
@@ -339,7 +342,7 @@ __secondary_data:
  *
  *  r0  = cp#15 control register
  *  r1  = machine ID
- *  r2  = atags pointer
+ *  r2  = atags or dtb pointer
  *  r4  = page table pointer
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
@@ -376,7 +379,7 @@ ENDPROC(__enable_mmu)
  *
  *  r0  = cp#15 control register
  *  r1  = machine ID
- *  r2  = atags pointer
+ *  r2  = atags or dtb pointer
  *  r9  = processor ID
  *  r13 = *virtual* address to jump to upon completion
  *
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 6dce209a623b..ed11fb08b05a 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -20,6 +20,7 @@
 #include <linux/screen_info.h>
 #include <linux/init.h>
 #include <linux/kexec.h>
+#include <linux/of_fdt.h>
 #include <linux/crash_dump.h>
 #include <linux/root_dev.h>
 #include <linux/cpu.h>
@@ -42,6 +43,7 @@
 #include <asm/cachetype.h>
 #include <asm/tlbflush.h>
 
+#include <asm/prom.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
@@ -309,7 +311,7 @@ static void __init cacheid_init(void)
  */
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 
-static void __init early_print(const char *str, ...)
+void __init early_print(const char *str, ...)
 {
         extern void printascii(const char *);
         char buf[256];
@@ -439,25 +441,12 @@ void cpu_init(void)
             : "r14");
 }
 
-static struct machine_desc * __init setup_machine(unsigned int nr)
+void __init dump_machine_table(void)
 {
-        extern struct machine_desc __arch_info_begin[], __arch_info_end[];
         struct machine_desc *p;
 
-        /*
-         * locate machine in the list of supported machines.
-         */
-        for (p = __arch_info_begin; p < __arch_info_end; p++)
-                if (nr == p->nr) {
-                        printk("Machine: %s\n", p->name);
-                        return p;
-                }
-
-        early_print("\n"
-                "Error: unrecognized/unsupported machine ID (r1 = 0x%08x).\n\n"
-                "Available machine support:\n\nID (hex)\tNAME\n", nr);
-
-        for (p = __arch_info_begin; p < __arch_info_end; p++)
+        early_print("Available machine support:\n\nID (hex)\tNAME\n");
+        for_each_machine_desc(p)
                 early_print("%08x\t%s\n", p->nr, p->name);
 
         early_print("\nPlease check your kernel config and/or bootloader.\n");
@@ -466,7 +455,7 @@ static struct machine_desc * __init setup_machine(unsigned int nr)
                 /* can't use cpu_relax() here as it may require MMU setup */;
 }
 
-static int __init arm_add_memory(phys_addr_t start, unsigned long size)
+int __init arm_add_memory(phys_addr_t start, unsigned long size)
 {
         struct membank *bank = &meminfo.bank[meminfo.nr_banks];
 
@@ -801,23 +790,29 @@ static void __init squash_mem_tags(struct tag *tag)
                         tag->hdr.tag = ATAG_NONE;
 }
 
-void __init setup_arch(char **cmdline_p)
+static struct machine_desc * __init setup_machine_tags(unsigned int nr)
 {
         struct tag *tags = (struct tag *)&init_tags;
-        struct machine_desc *mdesc;
+        struct machine_desc *mdesc = NULL, *p;
         char *from = default_command_line;
 
         init_tags.mem.start = PHYS_OFFSET;
 
-        unwind_init();
-
-        setup_processor();
-        mdesc = setup_machine(machine_arch_type);
-        machine_desc = mdesc;
-        machine_name = mdesc->name;
+        /*
+         * locate machine in the list of supported machines.
+         */
+        for_each_machine_desc(p)
+                if (nr == p->nr) {
+                        printk("Machine: %s\n", p->name);
+                        mdesc = p;
+                        break;
+                }
 
-        if (mdesc->soft_reboot)
-                reboot_setup("s");
+        if (!mdesc) {
+                early_print("\nError: unrecognized/unsupported machine ID"
+                        " (r1 = 0x%08x).\n\n", nr);
+                dump_machine_table(); /* does not return */
+        }
 
         if (__atags_pointer)
                 tags = phys_to_virt(__atags_pointer);
@@ -849,8 +844,17 @@ void __init setup_arch(char **cmdline_p)
         if (tags->hdr.tag != ATAG_CORE)
                 convert_to_tag_list(tags);
 #endif
-        if (tags->hdr.tag != ATAG_CORE)
+
+        if (tags->hdr.tag != ATAG_CORE) {
+#if defined(CONFIG_OF)
+                /*
+                 * If CONFIG_OF is set, then assume this is a reasonably
+                 * modern system that should pass boot parameters
+                 */
+                early_print("Warning: Neither atags nor dtb found\n");
+#endif
                 tags = (struct tag *)&init_tags;
+        }
 
         if (mdesc->fixup)
                 mdesc->fixup(mdesc, tags, &from, &meminfo);
@@ -862,14 +866,34 @@ void __init setup_arch(char **cmdline_p)
                 parse_tags(tags);
         }
 
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+
+        return mdesc;
+}
+
+
+void __init setup_arch(char **cmdline_p)
+{
+        struct machine_desc *mdesc;
+
+        unwind_init();
+
+        setup_processor();
+        mdesc = setup_machine_fdt(__atags_pointer);
+        if (!mdesc)
+                mdesc = setup_machine_tags(machine_arch_type);
+        machine_desc = mdesc;
+        machine_name = mdesc->name;
+
+        if (mdesc->soft_reboot)
+                reboot_setup("s");
+
         init_mm.start_code = (unsigned long) _text;
         init_mm.end_code   = (unsigned long) _etext;
         init_mm.end_data   = (unsigned long) _edata;
         init_mm.brk        = (unsigned long) _end;
 
-        /* parse_early_param needs a boot_command_line */
-        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-
         /* populate cmd_line too for later use, preserving boot_command_line */
         strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
         *cmdline_p = cmd_line;
@@ -881,6 +905,8 @@ void __init setup_arch(char **cmdline_p)
         paging_init(mdesc);
         request_standard_resources(mdesc);
 
+        unflatten_device_tree();
+
 #ifdef CONFIG_SMP
         if (is_smp())
                 smp_init_cpus();
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index d439a8f4c078..344e52b16c8c 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -105,6 +105,7 @@ int __cpuinit __cpu_up(unsigned int cpu)
          */
         secondary_data.stack = task_stack_page(idle) + THREAD_START_SP;
         secondary_data.pgdir = virt_to_phys(pgd);
+        secondary_data.swapper_pg_dir = virt_to_phys(swapper_pg_dir);
         __cpuc_flush_dcache_area(&secondary_data, sizeof(secondary_data));
         outer_clean_range(__pa(&secondary_data), __pa(&secondary_data + 1));
 
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b4348e62ef06..e5287f21badc 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -82,7 +82,7 @@ SECTIONS
 #endif
         }
 
-        PERCPU(32, PAGE_SIZE)
+        PERCPU_SECTION(32)
 
 #ifndef CONFIG_XIP_KERNEL
         . = ALIGN(PAGE_SIZE);
diff --git a/arch/arm/lib/lib1funcs.S b/arch/arm/lib/lib1funcs.S
index 6dc06487f3c3..c562f649734c 100644
--- a/arch/arm/lib/lib1funcs.S
+++ b/arch/arm/lib/lib1funcs.S
@@ -35,7 +35,7 @@ Boston, MA 02111-1307, USA.  */
 
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-
+#include <asm/unwind.h>
 
 .macro ARM_DIV_BODY dividend, divisor, result, curbit
 
@@ -207,6 +207,7 @@ Boston, MA 02111-1307, USA.  */
 
 ENTRY(__udivsi3)
 ENTRY(__aeabi_uidiv)
+UNWIND(.fnstart)
 
         subs    r2, r1, #1
         moveq   pc, lr
@@ -230,10 +231,12 @@ ENTRY(__aeabi_uidiv)
         mov     r0, r0, lsr r2
         mov     pc, lr
 
+UNWIND(.fnend)
 ENDPROC(__udivsi3)
 ENDPROC(__aeabi_uidiv)
 
 ENTRY(__umodsi3)
+UNWIND(.fnstart)
 
         subs    r2, r1, #1                      @ compare divisor with 1
         bcc     Ldiv0
@@ -247,10 +250,12 @@ ENTRY(__umodsi3)
 
         mov     pc, lr
 
+UNWIND(.fnend)
 ENDPROC(__umodsi3)
 
 ENTRY(__divsi3)
 ENTRY(__aeabi_idiv)
+UNWIND(.fnstart)
 
         cmp     r1, #0
         eor     ip, r0, r1                      @ save the sign of the result.
@@ -287,10 +292,12 @@ ENTRY(__aeabi_idiv)
         rsbmi   r0, r0, #0
         mov     pc, lr
 
+UNWIND(.fnend)
 ENDPROC(__divsi3)
 ENDPROC(__aeabi_idiv)
 
 ENTRY(__modsi3)
+UNWIND(.fnstart)
 
         cmp     r1, #0
         beq     Ldiv0
@@ -310,11 +317,14 @@ ENTRY(__modsi3)
         rsbmi   r0, r0, #0
         mov     pc, lr
 
+UNWIND(.fnend)
 ENDPROC(__modsi3)
 
 #ifdef CONFIG_AEABI
 
 ENTRY(__aeabi_uidivmod)
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr}   )
 
         stmfd   sp!, {r0, r1, ip, lr}
         bl      __aeabi_uidiv
@@ -323,10 +333,12 @@ ENTRY(__aeabi_uidivmod)
         sub     r1, r1, r3
         mov     pc, lr
 
+UNWIND(.fnend)
 ENDPROC(__aeabi_uidivmod)
 
 ENTRY(__aeabi_idivmod)
-
+UNWIND(.fnstart)
+UNWIND(.save {r0, r1, ip, lr}   )
         stmfd   sp!, {r0, r1, ip, lr}
         bl      __aeabi_idiv
         ldmfd   sp!, {r1, r2, ip, lr}
@@ -334,15 +346,18 @@ ENTRY(__aeabi_idivmod)
         sub     r1, r1, r3
         mov     pc, lr
 
+UNWIND(.fnend)
 ENDPROC(__aeabi_idivmod)
 
 #endif
 
 Ldiv0:
-
+UNWIND(.fnstart)
+UNWIND(.pad #4)
+UNWIND(.save {lr})
         str     lr, [sp, #-8]!
         bl      __div0
         mov     r0, #0                  @ About as wrong as it could be.
         ldr     pc, [sp], #8
-
-
+UNWIND(.fnend)
+ENDPROC(Ldiv0)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 2d299bf5d72f..22484670e7ba 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -3,9 +3,6 @@ if ARCH_AT91
 config HAVE_AT91_DATAFLASH_CARD
         bool
 
-config HAVE_NAND_ATMEL_BUSWIDTH_16
-        bool
-
 config HAVE_AT91_USART3
         bool
 
@@ -85,11 +82,6 @@ config ARCH_AT91CAP9
         select HAVE_FB_ATMEL
         select HAVE_NET_MACB
 
-config ARCH_AT572D940HF
-        bool "AT572D940HF"
-        select CPU_ARM926T
-        select GENERIC_CLOCKEVENTS
-
 config ARCH_AT91X40
         bool "AT91x40"
         select ARCH_USES_GETTIMEOFFSET
@@ -209,7 +201,6 @@ comment "AT91SAM9260 / AT91SAM9XE Board Type"
 config MACH_AT91SAM9260EK
         bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
@@ -270,7 +261,6 @@ comment "AT91SAM9261 Board Type"
 config MACH_AT91SAM9261EK
         bool "Atmel AT91SAM9261-EK Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
@@ -286,7 +276,6 @@ comment "AT91SAM9G10 Board Type"
 config MACH_AT91SAM9G10EK
         bool "Atmel AT91SAM9G10-EK Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
@@ -302,7 +291,6 @@ comment "AT91SAM9263 Board Type"
 config MACH_AT91SAM9263EK
         bool "Atmel AT91SAM9263-EK Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
@@ -343,7 +331,6 @@ comment "AT91SAM9G20 Board Type"
 config MACH_AT91SAM9G20EK
         bool "Atmel AT91SAM9G20-EK Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
           that embeds only one SD/MMC slot.
@@ -351,7 +338,6 @@ config MACH_AT91SAM9G20EK
 config MACH_AT91SAM9G20EK_2MMC
         depends on MACH_AT91SAM9G20EK
         bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
           with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
@@ -416,7 +402,6 @@ comment "AT91SAM9G45 Board Type"
 
 config MACH_AT91SAM9M10G45EK
         bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
           "ES" at the end of the name means that this board is an
@@ -433,7 +418,6 @@ comment "AT91CAP9 Board Type"
 config MACH_AT91CAP9ADK
         bool "Atmel AT91CAP9A-DK Evaluation Kit"
         select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
         help
           Select this if you are using Atmel's AT91CAP9A-DK Evaluation Kit.
           <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4138>
@@ -442,23 +426,6 @@ endif
 
 # ----------------------------------------------------------
 
-if ARCH_AT572D940HF
-
-comment "AT572D940HF Board Type"
-
-config MACH_AT572D940HFEB
-        bool "AT572D940HF-EK"
-        depends on ARCH_AT572D940HF
-        select HAVE_AT91_DATAFLASH_CARD
-        select HAVE_NAND_ATMEL_BUSWIDTH_16
-        help
-          Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
-          <http://www.atmel.com/products/diopsis/default.asp>
-
-endif
-
-# ----------------------------------------------------------
-
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
@@ -483,13 +450,6 @@ config MTD_AT91_DATAFLASH_CARD
         help
           Enable support for the DataFlash card.
 
-config MTD_NAND_ATMEL_BUSWIDTH_16
-        bool "Enable 16-bit data bus interface to NAND flash"
-        depends on HAVE_NAND_ATMEL_BUSWIDTH_16
-        help
-          On AT91SAM926x boards both types of NAND flash can be present
-          (8 and 16 bit data bus width).
-
 # ----------------------------------------------------------
 
 comment "AT91 Feature Selections"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index a83835e0c185..96966231920c 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
 obj-$(CONFIG_ARCH_AT91SAM9G45)  += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
-obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -78,9 +77,6 @@ obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
 
-# AT572D940HF board-specific support
-obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
-
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
 
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
deleted file mode 100644
index a6b9c68c003a..000000000000
--- a/arch/arm/mach-at91/at572d940hf.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * arch/arm/mach-at91/at572d940hf.c
- *
- * Antonio R. Costa <costa.antonior@gmail.com>
- * Copyright (C) 2008 Atmel
- *
- * Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <linux/module.h>
-
-#include <asm/mach/irq.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/at572d940hf.h>
-#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
-
-#include "generic.h"
-#include "clock.h"
-
-static struct map_desc at572d940hf_io_desc[] __initdata = {
-        {
-                .virtual        = AT91_VA_BASE_SYS,
-                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
-                .pfn            = __phys_to_pfn(AT572D940HF_SRAM_BASE),
-                .length         = AT572D940HF_SRAM_SIZE,
-                .type           = MT_DEVICE,
-        },
-};
-
-/* --------------------------------------------------------------------
- *  Clocks
- * -------------------------------------------------------------------- */
-
-/*
- * The peripheral clocks.
- */
-static struct clk pioA_clk = {
-        .name           = "pioA_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_PIOA,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioB_clk = {
-        .name           = "pioB_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_PIOB,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk pioC_clk = {
-        .name           = "pioC_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_PIOC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk macb_clk = {
-        .name           = "macb_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_EMAC,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart0_clk = {
-        .name           = "usart0_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_US0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart1_clk = {
-        .name           = "usart1_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_US1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk usart2_clk = {
-        .name           = "usart2_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_US2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mmc_clk = {
-        .name           = "mci_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_MCI,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk udc_clk = {
-        .name           = "udc_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_UDP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi0_clk = {
-        .name           = "twi0_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_TWI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi0_clk = {
-        .name           = "spi0_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_SPI0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk spi1_clk = {
-        .name           = "spi1_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_SPI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc0_clk = {
-        .name           = "ssc0_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_SSC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc1_clk = {
-        .name           = "ssc1_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_SSC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc2_clk = {
-        .name           = "ssc2_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_SSC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc0_clk = {
-        .name           = "tc0_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_TC0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc1_clk = {
-        .name           = "tc1_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_TC1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk tc2_clk = {
-        .name           = "tc2_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_TC2,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_UHP,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk ssc3_clk = {
-        .name           = "ssc3_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_SSC3,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk twi1_clk = {
-        .name           = "twi1_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_TWI1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can0_clk = {
-        .name           = "can0_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_CAN0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk can1_clk = {
-        .name           = "can1_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_CAN1,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-static struct clk mAgicV_clk = {
-        .name           = "mAgicV_clk",
-        .pmc_mask       = 1 << AT572D940HF_ID_MSIRQ0,
-        .type           = CLK_TYPE_PERIPHERAL,
-};
-
-
-static struct clk *periph_clocks[] __initdata = {
-        &pioA_clk,
-        &pioB_clk,
-        &pioC_clk,
-        &macb_clk,
-        &usart0_clk,
-        &usart1_clk,
-        &usart2_clk,
-        &mmc_clk,
-        &udc_clk,
-        &twi0_clk,
-        &spi0_clk,
-        &spi1_clk,
-        &ssc0_clk,
-        &ssc1_clk,
-        &ssc2_clk,
-        &tc0_clk,
-        &tc1_clk,
-        &tc2_clk,
-        &ohci_clk,
-        &ssc3_clk,
-        &twi1_clk,
-        &can0_clk,
-        &can1_clk,
-        &mAgicV_clk,
-        /* irq0 .. irq2 */
-};
-
-/*
- * The five programmable clocks.
- * You must configure pin multiplexing to bring these signals out.
- */
-static struct clk pck0 = {
-        .name           = "pck0",
-        .pmc_mask       = AT91_PMC_PCK0,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 0,
-};
-static struct clk pck1 = {
-        .name           = "pck1",
-        .pmc_mask       = AT91_PMC_PCK1,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 1,
-};
-static struct clk pck2 = {
-        .name           = "pck2",
-        .pmc_mask       = AT91_PMC_PCK2,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 2,
-};
-static struct clk pck3 = {
-        .name           = "pck3",
-        .pmc_mask       = AT91_PMC_PCK3,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 3,
-};
-
-static struct clk mAgicV_mem_clk = {
-        .name           = "mAgicV_mem_clk",
-        .pmc_mask       = AT91_PMC_PCK4,
-        .type           = CLK_TYPE_PROGRAMMABLE,
-        .id             = 4,
-};
-
-/* HClocks */
-static struct clk hck0 = {
-        .name           = "hck0",
-        .pmc_mask       = AT91_PMC_HCK0,
-        .type           = CLK_TYPE_SYSTEM,
-        .id             = 0,
-};
-static struct clk hck1 = {
-        .name           = "hck1",
-        .pmc_mask       = AT91_PMC_HCK1,
-        .type           = CLK_TYPE_SYSTEM,
-        .id             = 1,
-};
-
-static void __init at572d940hf_register_clocks(void)
-{
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
-                clk_register(periph_clocks[i]);
-
-        clk_register(&pck0);
-        clk_register(&pck1);
-        clk_register(&pck2);
-        clk_register(&pck3);
-        clk_register(&mAgicV_mem_clk);
-
-        clk_register(&hck0);
-        clk_register(&hck1);
-}
-
-/* --------------------------------------------------------------------
- *  GPIO
- * -------------------------------------------------------------------- */
-
-static struct at91_gpio_bank at572d940hf_gpio[] = {
-        {
-                .id             = AT572D940HF_ID_PIOA,
-                .offset         = AT91_PIOA,
-                .clock          = &pioA_clk,
-        }, {
-                .id             = AT572D940HF_ID_PIOB,
-                .offset         = AT91_PIOB,
-                .clock          = &pioB_clk,
-        }, {
-                .id             = AT572D940HF_ID_PIOC,
-                .offset         = AT91_PIOC,
-                .clock          = &pioC_clk,
-        }
-};
-
-static void at572d940hf_reset(void)
-{
-        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
-
-/* --------------------------------------------------------------------
- *  AT572D940HF processor initialization
- * -------------------------------------------------------------------- */
-
-void __init at572d940hf_initialize(unsigned long main_clock)
-{
-        /* Map peripherals */
-        iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
-
-        at91_arch_reset = at572d940hf_reset;
-        at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
-                        | (1 << AT572D940HF_ID_IRQ2);
-
-        /* Init clock subsystem */
-        at91_clock_init(main_clock);
-
-        /* Register the processor-specific clocks */
-        at572d940hf_register_clocks();
-
-        /* Register GPIO subsystem */
-        at91_gpio_init(at572d940hf_gpio, 3);
-}
-
-/* --------------------------------------------------------------------
- *  Interrupt initialization
- * -------------------------------------------------------------------- */
-
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller */
-        7,      /* System Peripherals */
-        0,      /* Parallel IO Controller A */
-        0,      /* Parallel IO Controller B */
-        0,      /* Parallel IO Controller C */
-        3,      /* Ethernet */
-        6,      /* USART 0 */
-        6,      /* USART 1 */
-        6,      /* USART 2 */
-        0,      /* Multimedia Card Interface */
-        4,      /* USB Device Port */
-        0,      /* Two-Wire Interface 0 */
-        6,      /* Serial Peripheral Interface 0 */
-        6,      /* Serial Peripheral Interface 1 */
-        5,      /* Serial Synchronous Controller 0 */
-        5,      /* Serial Synchronous Controller 1 */
-        5,      /* Serial Synchronous Controller 2 */
-        0,      /* Timer Counter 0 */
-        0,      /* Timer Counter 1 */
-        0,      /* Timer Counter 2 */
-        3,      /* USB Host port */
-        3,      /* Serial Synchronous Controller 3 */
-        0,      /* Two-Wire Interface 1 */
-        0,      /* CAN Controller 0 */
-        0,      /* CAN Controller 1 */
-        0,      /* mAgicV HALT line */
-        0,      /* mAgicV SIRQ0 line */
-        0,      /* mAgicV exception line */
-        0,      /* mAgicV end of DMA line */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-        0,      /* Advanced Interrupt Controller */
-};
-
-void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
-{
-        if (!priority)
-                priority = at572d940hf_default_irq_priority;
-
-        /* Initialize the AIC interrupt controller */
-        at91_aic_init(priority);
-
-        /* Enable GPIO interrupts */
-        at91_gpio_irq_setup();
-}
-
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
deleted file mode 100644
index 0fc20a240782..000000000000
--- a/arch/arm/mach-at91/at572d940hf_devices.c
+++ /dev/null
@@ -1,970 +0,0 @@
-/*
- * arch/arm/mach-at91/at572d940hf_devices.c
- *
- * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
- * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
- * Copyright (C) 2005 David Brownell
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/at572d940hf.h>
-#include <mach/at572d940hf_matrix.h>
-#include <mach/at91sam9_smc.h>
-
-#include "generic.h"
-#include "sam9_smc.h"
-
-
-/* --------------------------------------------------------------------
- *  USB Host
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static u64 ohci_dmamask = DMA_BIT_MASK(32);
-static struct at91_usbh_data usbh_data;
-
-static struct resource usbh_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_UHP_BASE,
-                .end    = AT572D940HF_UHP_BASE + SZ_1M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_UHP,
-                .end    = AT572D940HF_ID_UHP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_usbh_device = {
-        .name           = "at91_ohci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &ohci_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &usbh_data,
-        },
-        .resource       = usbh_resources,
-        .num_resources  = ARRAY_SIZE(usbh_resources),
-};
-
-void __init at91_add_device_usbh(struct at91_usbh_data *data)
-{
-        if (!data)
-                return;
-
-        usbh_data = *data;
-        platform_device_register(&at572d940hf_usbh_device);
-
-}
-#else
-void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  USB Device (Gadget)
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_USB_GADGET_AT91
-static struct at91_udc_data udc_data;
-
-static struct resource udc_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_UDP,
-                .end    = AT572D940HF_BASE_UDP + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_UDP,
-                .end    = AT572D940HF_ID_UDP,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_udc_device = {
-        .name           = "at91_udc",
-        .id             = -1,
-        .dev            = {
-                                .platform_data          = &udc_data,
-        },
-        .resource       = udc_resources,
-        .num_resources  = ARRAY_SIZE(udc_resources),
-};
-
-void __init at91_add_device_udc(struct at91_udc_data *data)
-{
-        if (!data)
-                return;
-
-        if (data->vbus_pin) {
-                at91_set_gpio_input(data->vbus_pin, 0);
-                at91_set_deglitch(data->vbus_pin, 1);
-        }
-
-        /* Pullup pin is handled internally */
-
-        udc_data = *data;
-        platform_device_register(&at572d940hf_udc_device);
-}
-#else
-void __init at91_add_device_udc(struct at91_udc_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Ethernet
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
-static u64 eth_dmamask = DMA_BIT_MASK(32);
-static struct at91_eth_data eth_data;
-
-static struct resource eth_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_EMAC,
-                .end    = AT572D940HF_BASE_EMAC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_EMAC,
-                .end    = AT572D940HF_ID_EMAC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_eth_device = {
-        .name           = "macb",
-        .id             = -1,
-        .dev            = {
-                        .dma_mask               = &eth_dmamask,
-                        .coherent_dma_mask      = DMA_BIT_MASK(32),
-                        .platform_data          = &eth_data,
-        },
-        .resource       = eth_resources,
-        .num_resources  = ARRAY_SIZE(eth_resources),
-};
-
-void __init at91_add_device_eth(struct at91_eth_data *data)
-{
-        if (!data)
-                return;
-
-        if (data->phy_irq_pin) {
-                at91_set_gpio_input(data->phy_irq_pin, 0);
-                at91_set_deglitch(data->phy_irq_pin, 1);
-        }
-
-        /* Only RMII is supported */
-        data->is_rmii = 1;
-
-        /* Pins used for RMII */
-        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXCK_EREFCK */
-        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
-        at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERX0 */
-        at91_set_A_periph(AT91_PIN_PA19, 0);    /* ERX1 */
-        at91_set_A_periph(AT91_PIN_PA20, 0);    /* ERXER */
-        at91_set_A_periph(AT91_PIN_PA23, 0);    /* ETXEN */
-        at91_set_A_periph(AT91_PIN_PA21, 0);    /* ETX0 */
-        at91_set_A_periph(AT91_PIN_PA22, 0);    /* ETX1 */
-        at91_set_A_periph(AT91_PIN_PA13, 0);    /* EMDIO */
-        at91_set_A_periph(AT91_PIN_PA14, 0);    /* EMDC */
-
-        eth_data = *data;
-        platform_device_register(&at572d940hf_eth_device);
-}
-#else
-void __init at91_add_device_eth(struct at91_eth_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  MMC / SD
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
-static u64 mmc_dmamask = DMA_BIT_MASK(32);
-static struct at91_mmc_data mmc_data;
-
-static struct resource mmc_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_MCI,
-                .end    = AT572D940HF_BASE_MCI + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_MCI,
-                .end    = AT572D940HF_ID_MCI,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_mmc_device = {
-        .name           = "at91_mci",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &mmc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &mmc_data,
-        },
-        .resource       = mmc_resources,
-        .num_resources  = ARRAY_SIZE(mmc_resources),
-};
-
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
-{
-        if (!data)
-                return;
-
-        /* input/irq */
-        if (data->det_pin) {
-                at91_set_gpio_input(data->det_pin, 1);
-                at91_set_deglitch(data->det_pin, 1);
-        }
-        if (data->wp_pin)
-                at91_set_gpio_input(data->wp_pin, 1);
-        if (data->vcc_pin)
-                at91_set_gpio_output(data->vcc_pin, 0);
-
-        /* CLK */
-        at91_set_A_periph(AT91_PIN_PC22, 0);
-
-        /* CMD */
-        at91_set_A_periph(AT91_PIN_PC23, 1);
-
-        /* DAT0, maybe DAT1..DAT3 */
-        at91_set_A_periph(AT91_PIN_PC24, 1);
-        if (data->wire4) {
-                at91_set_A_periph(AT91_PIN_PC25, 1);
-                at91_set_A_periph(AT91_PIN_PC26, 1);
-                at91_set_A_periph(AT91_PIN_PC27, 1);
-        }
-
-        mmc_data = *data;
-        platform_device_register(&at572d940hf_mmc_device);
-}
-#else
-void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  NAND / SmartMedia
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
-static struct atmel_nand_data nand_data;
-
-#define NAND_BASE       AT91_CHIPSELECT_3
-
-static struct resource nand_resources[] = {
-        {
-                .start  = NAND_BASE,
-                .end    = NAND_BASE + SZ_256M - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at572d940hf_nand_device = {
-        .name           = "atmel_nand",
-        .id             = -1,
-        .dev            = {
-                                .platform_data  = &nand_data,
-        },
-        .resource       = nand_resources,
-        .num_resources  = ARRAY_SIZE(nand_resources),
-};
-
-void __init at91_add_device_nand(struct atmel_nand_data *data)
-{
-        unsigned long csa;
-
-        if (!data)
-                return;
-
-        csa = at91_sys_read(AT91_MATRIX_EBICSA);
-        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
-
-        /* enable pin */
-        if (data->enable_pin)
-                at91_set_gpio_output(data->enable_pin, 1);
-
-        /* ready/busy pin */
-        if (data->rdy_pin)
-                at91_set_gpio_input(data->rdy_pin, 1);
-
-        /* card detect pin */
-        if (data->det_pin)
-                at91_set_gpio_input(data->det_pin, 1);
-
-        at91_set_A_periph(AT91_PIN_PB28, 0);            /* A[22] */
-        at91_set_B_periph(AT91_PIN_PA28, 0);            /* NANDOE */
-        at91_set_B_periph(AT91_PIN_PA29, 0);            /* NANDWE */
-
-        nand_data = *data;
-        platform_device_register(&at572d940hf_nand_device);
-}
-
-#else
-void __init at91_add_device_nand(struct atmel_nand_data *data) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  TWI (i2c)
- * -------------------------------------------------------------------- */
-
-/*
- * Prefer the GPIO code since the TWI controller isn't robust
- * (gets overruns and underruns under load) and can only issue
- * repeated STARTs in one scenario (the driver doesn't yet handle them).
- */
-
-#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
-
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = AT91_PIN_PC7,
-        .sda_is_open_drain      = 1,
-        .scl_pin                = AT91_PIN_PC8,
-        .scl_is_open_drain      = 1,
-        .udelay                 = 2,            /* ~100 kHz */
-};
-
-static struct platform_device at572d940hf_twi_device {
-        .name                   = "i2c-gpio",
-        .id                     = -1,
-        .dev.platform_data      = &pdata,
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        at91_set_GPIO_periph(AT91_PIN_PC7, 1);          /* TWD (SDA) */
-        at91_set_multi_drive(AT91_PIN_PC7, 1);
-
-        at91_set_GPIO_periph(AT91_PIN_PA8, 1);          /* TWCK (SCL) */
-        at91_set_multi_drive(AT91_PIN_PC8, 1);
-
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at572d940hf_twi_device);
-}
-
-#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
-
-static struct resource twi0_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_TWI0,
-                .end    = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_TWI0,
-                .end    = AT572D940HF_ID_TWI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_twi0_device = {
-        .name           = "at91_i2c",
-        .id             = 0,
-        .resource       = twi0_resources,
-        .num_resources  = ARRAY_SIZE(twi0_resources),
-};
-
-static struct resource twi1_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_TWI1,
-                .end    = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_TWI1,
-                .end    = AT572D940HF_ID_TWI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_twi1_device = {
-        .name           = "at91_i2c",
-        .id             = 1,
-        .resource       = twi1_resources,
-        .num_resources  = ARRAY_SIZE(twi1_resources),
-};
-
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
-{
-        /* pins used for TWI0 interface */
-        at91_set_A_periph(AT91_PIN_PC7, 0);             /* TWD */
-        at91_set_multi_drive(AT91_PIN_PC7, 1);
-
-        at91_set_A_periph(AT91_PIN_PC8, 0);             /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PC8, 1);
-
-        /* pins used for TWI1 interface */
-        at91_set_A_periph(AT91_PIN_PC20, 0);            /* TWD */
-        at91_set_multi_drive(AT91_PIN_PC20, 1);
-
-        at91_set_A_periph(AT91_PIN_PC21, 0);            /* TWCK */
-        at91_set_multi_drive(AT91_PIN_PC21, 1);
-
-        i2c_register_board_info(0, devices, nr_devices);
-        platform_device_register(&at572d940hf_twi0_device);
-        platform_device_register(&at572d940hf_twi1_device);
-}
-#else
-void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  SPI
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-static struct resource spi0_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_SPI0,
-                .end    = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_SPI0,
-                .end    = AT572D940HF_ID_SPI0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_spi0_device = {
-        .name           = "atmel_spi",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi0_resources,
-        .num_resources  = ARRAY_SIZE(spi0_resources),
-};
-
-static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
-
-static struct resource spi1_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_SPI1,
-                .end    = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_SPI1,
-                .end    = AT572D940HF_ID_SPI1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_spi1_device = {
-        .name           = "atmel_spi",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &spi_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-        },
-        .resource       = spi1_resources,
-        .num_resources  = ARRAY_SIZE(spi1_resources),
-};
-
-static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
-
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
-{
-        int i;
-        unsigned long cs_pin;
-        short enable_spi0 = 0;
-        short enable_spi1 = 0;
-
-        /* Choose SPI chip-selects */
-        for (i = 0; i < nr_devices; i++) {
-                if (devices[i].controller_data)
-                        cs_pin = (unsigned long) devices[i].controller_data;
-                else if (devices[i].bus_num == 0)
-                        cs_pin = spi0_standard_cs[devices[i].chip_select];
-                else
-                        cs_pin = spi1_standard_cs[devices[i].chip_select];
-
-                if (devices[i].bus_num == 0)
-                        enable_spi0 = 1;
-                else
-                        enable_spi1 = 1;
-
-                /* enable chip-select pin */
-                at91_set_gpio_output(cs_pin, 1);
-
-                /* pass chip-select pin to driver */
-                devices[i].controller_data = (void *) cs_pin;
-        }
-
-        spi_register_board_info(devices, nr_devices);
-
-        /* Configure SPI bus(es) */
-        if (enable_spi0) {
-                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
-                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
-                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
-
-                at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
-                platform_device_register(&at572d940hf_spi0_device);
-        }
-        if (enable_spi1) {
-                at91_set_A_periph(AT91_PIN_PC0, 0);     /* SPI1_MISO */
-                at91_set_A_periph(AT91_PIN_PC1, 0);     /* SPI1_MOSI */
-                at91_set_A_periph(AT91_PIN_PC2, 0);     /* SPI1_SPCK */
-
-                at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
-                platform_device_register(&at572d940hf_spi1_device);
-        }
-}
-#else
-void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  Timer/Counter blocks
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_ATMEL_TCLIB
-
-static struct resource tcb_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_TCB,
-                .end    = AT572D940HF_BASE_TCB + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_TC0,
-                .end    = AT572D940HF_ID_TC0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                .start  = AT572D940HF_ID_TC1,
-                .end    = AT572D940HF_ID_TC1,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [3] = {
-                .start  = AT572D940HF_ID_TC2,
-                .end    = AT572D940HF_ID_TC2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device at572d940hf_tcb_device = {
-        .name           = "atmel_tcb",
-        .id             = 0,
-        .resource       = tcb_resources,
-        .num_resources  = ARRAY_SIZE(tcb_resources),
-};
-
-static void __init at91_add_device_tc(void)
-{
-        /* this chip has a separate clock and irq for each TC channel */
-        at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
-        at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
-        at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
-        platform_device_register(&at572d940hf_tcb_device);
-}
-#else
-static void __init at91_add_device_tc(void) { }
-#endif
-
-
-/* --------------------------------------------------------------------
- *  RTT
- * -------------------------------------------------------------------- */
-
-static struct resource rtt_resources[] = {
-        {
-                .start  = AT91_BASE_SYS + AT91_RTT,
-                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
-                .flags  = IORESOURCE_MEM,
-        }
-};
-
-static struct platform_device at572d940hf_rtt_device = {
-        .name           = "at91_rtt",
-        .id             = 0,
-        .resource       = rtt_resources,
-        .num_resources  = ARRAY_SIZE(rtt_resources),
-};
-
-static void __init at91_add_device_rtt(void)
-{
-        platform_device_register(&at572d940hf_rtt_device);
-}
-
-
-/* --------------------------------------------------------------------
- *  Watchdog
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
-static struct platform_device at572d940hf_wdt_device = {
-        .name           = "at91_wdt",
-        .id             = -1,
-        .num_resources  = 0,
-};
-
-static void __init at91_add_device_watchdog(void)
-{
-        platform_device_register(&at572d940hf_wdt_device);
-}
-#else
-static void __init at91_add_device_watchdog(void) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  UART
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_SERIAL_ATMEL)
-static struct resource dbgu_resources[] = {
-        [0] = {
-                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
-                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data dbgu_data = {
-        .use_dma_tx     = 0,
-        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
-};
-
-static u64 dbgu_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at572d940hf_dbgu_device = {
-        .name           = "atmel_usart",
-        .id             = 0,
-        .dev            = {
-                                .dma_mask               = &dbgu_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &dbgu_data,
-        },
-        .resource       = dbgu_resources,
-        .num_resources  = ARRAY_SIZE(dbgu_resources),
-};
-
-static inline void configure_dbgu_pins(void)
-{
-        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
-        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
-}
-
-static struct resource uart0_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_US0,
-                .end    = AT572D940HF_BASE_US0 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_US0,
-                .end    = AT572D940HF_ID_US0,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart0_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart0_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at572d940hf_uart0_device = {
-        .name           = "atmel_usart",
-        .id             = 1,
-        .dev            = {
-                                .dma_mask               = &uart0_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart0_data,
-        },
-        .resource       = uart0_resources,
-        .num_resources  = ARRAY_SIZE(uart0_resources),
-};
-
-static inline void configure_usart0_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PA8, 1);             /* TXD0 */
-        at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PA10, 0);    /* RTS0 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PA9, 0);     /* CTS0 */
-}
-
-static struct resource uart1_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_US1,
-                .end    = AT572D940HF_BASE_US1 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_US1,
-                .end    = AT572D940HF_ID_US1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart1_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart1_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at572d940hf_uart1_device = {
-        .name           = "atmel_usart",
-        .id             = 2,
-        .dev            = {
-                                .dma_mask               = &uart1_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart1_data,
-        },
-        .resource       = uart1_resources,
-        .num_resources  = ARRAY_SIZE(uart1_resources),
-};
-
-static inline void configure_usart1_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PC10, 1);            /* TXD1 */
-        at91_set_A_periph(AT91_PIN_PC9 , 0);            /* RXD1 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PC12, 0);    /* RTS1 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PC11, 0);    /* CTS1 */
-}
-
-static struct resource uart2_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_BASE_US2,
-                .end    = AT572D940HF_BASE_US2 + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = AT572D940HF_ID_US2,
-                .end    = AT572D940HF_ID_US2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct atmel_uart_data uart2_data = {
-        .use_dma_tx     = 1,
-        .use_dma_rx     = 1,
-};
-
-static u64 uart2_dmamask = DMA_BIT_MASK(32);
-
-static struct platform_device at572d940hf_uart2_device = {
-        .name           = "atmel_usart",
-        .id             = 3,
-        .dev            = {
-                                .dma_mask               = &uart2_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &uart2_data,
-        },
-        .resource       = uart2_resources,
-        .num_resources  = ARRAY_SIZE(uart2_resources),
-};
-
-static inline void configure_usart2_pins(unsigned pins)
-{
-        at91_set_A_periph(AT91_PIN_PC15, 1);            /* TXD2 */
-        at91_set_A_periph(AT91_PIN_PC14, 0);            /* RXD2 */
-
-        if (pins & ATMEL_UART_RTS)
-                at91_set_A_periph(AT91_PIN_PC17, 0);    /* RTS2 */
-        if (pins & ATMEL_UART_CTS)
-                at91_set_A_periph(AT91_PIN_PC16, 0);    /* CTS2 */
-}
-
-static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
-struct platform_device *atmel_default_console_device;   /* the serial console device */
-
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
-{
-        struct platform_device *pdev;
-
-        switch (id) {
-                case 0:         /* DBGU */
-                        pdev = &at572d940hf_dbgu_device;
-                        configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
-                        break;
-                case AT572D940HF_ID_US0:
-                        pdev = &at572d940hf_uart0_device;
-                        configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
-                        break;
-                case AT572D940HF_ID_US1:
-                        pdev = &at572d940hf_uart1_device;
-                        configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
-                        break;
-                case AT572D940HF_ID_US2:
-                        pdev = &at572d940hf_uart2_device;
-                        configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
-                        break;
-                default:
-                        return;
-        }
-        pdev->id = portnr;              /* update to mapped ID */
-
-        if (portnr < ATMEL_MAX_UART)
-                at91_uarts[portnr] = pdev;
-}
-
-void __init at91_set_serial_console(unsigned portnr)
-{
-        if (portnr < ATMEL_MAX_UART)
-                atmel_default_console_device = at91_uarts[portnr];
-}
-
-void __init at91_add_device_serial(void)
-{
-        int i;
-
-        for (i = 0; i < ATMEL_MAX_UART; i++) {
-                if (at91_uarts[i])
-                        platform_device_register(at91_uarts[i]);
-        }
-
-        if (!atmel_default_console_device)
-                printk(KERN_INFO "AT91: No default serial console defined.\n");
-}
-
-#else
-void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
-void __init at91_set_serial_console(unsigned portnr) {}
-void __init at91_add_device_serial(void) {}
-#endif
-
-
-/* --------------------------------------------------------------------
- *  mAgic
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_MAGICV
-static struct resource mAgic_resources[] = {
-        {
-                .start = AT91_MAGIC_PM_BASE,
-                .end   = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = AT91_MAGIC_DM_I_BASE,
-                .end   = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = AT91_MAGIC_DM_F_BASE,
-                .end   = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = AT91_MAGIC_DM_DB_BASE,
-                .end   = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = AT91_MAGIC_REGS_BASE,
-                .end   = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start = AT91_MAGIC_EXTPAGE_BASE,
-                .end   = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        {
-                .start  = AT572D940HF_ID_MSIRQ0,
-                .end    = AT572D940HF_ID_MSIRQ0,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = AT572D940HF_ID_MHALT,
-                .end    = AT572D940HF_ID_MHALT,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = AT572D940HF_ID_MEXC,
-                .end    = AT572D940HF_ID_MEXC,
-                .flags  = IORESOURCE_IRQ,
-        },
-        {
-                .start  = AT572D940HF_ID_MEDMA,
-                .end    = AT572D940HF_ID_MEDMA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device mAgic_device = {
-        .name           = "mAgic",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(mAgic_resources),
-        .resource       = mAgic_resources,
-};
-
-void __init at91_add_device_mAgic(void)
-{
-        platform_device_register(&mAgic_device);
-}
-#else
-void __init at91_add_device_mAgic(void) {}
-#endif
-
-
-/* -------------------------------------------------------------------- */
-
-/*
- * These devices are always present and don't need any board-specific
- * setup.
- */
-static int __init at91_add_standard_devices(void)
-{
-        at91_add_device_rtt();
-        at91_add_device_watchdog();
-        at91_add_device_tc();
-        return 0;
-}
-
-arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index 73376170fb91..17fae4a42ab5 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -222,6 +222,25 @@ static struct clk *periph_clocks[] __initdata = {
         // irq0 .. irq1
 };
 
+static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc.0", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc.0", &udphs_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
+        CLKDEV_CON_DEV_ID("ssc", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("ssc", "ssc.1", &ssc1_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+};
+
 /*
  * The four programmable clocks.
  * You must configure pin multiplexing to bring these signals out.
@@ -258,12 +277,29 @@ static void __init at91cap9_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         clk_register(&pck0);
         clk_register(&pck1);
         clk_register(&pck2);
         clk_register(&pck3);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91cap9_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -303,11 +339,14 @@ static void at91cap9_poweroff(void)
  *  AT91CAP9 processor initialization
  * -------------------------------------------------------------------- */
 
-void __init at91cap9_initialize(unsigned long main_clock)
+void __init at91cap9_map_io(void)
 {
         /* Map peripherals */
         iotable_init(at91cap9_io_desc, ARRAY_SIZE(at91cap9_io_desc));
+}
 
+void __init at91cap9_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91cap9_reset;
         pm_power_off = at91cap9_poweroff;
         at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index 21020ceb2f3a..cd850ed6f335 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -181,10 +181,6 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
 
         /* Pullup pin is handled internally by USB device peripheral */
 
-        /* Clocks */
-        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
-        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
-
         platform_device_register(&at91_usba_udc_device);
 }
 #else
@@ -355,7 +351,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 }
 
                 mmc0_data = *data;
-                at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk");
                 platform_device_register(&at91cap9_mmc0_device);
         } else {                        /* MCI1 */
                 /* CLK */
@@ -373,7 +368,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 }
 
                 mmc1_data = *data;
-                at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
                 platform_device_register(&at91cap9_mmc1_device);
         }
 }
@@ -614,7 +608,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 
-                at91_clock_associate("spi0_clk", &at91cap9_spi0_device.dev, "spi_clk");
                 platform_device_register(&at91cap9_spi0_device);
         }
         if (enable_spi1) {
@@ -622,7 +615,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
 
-                at91_clock_associate("spi1_clk", &at91cap9_spi1_device.dev, "spi_clk");
                 platform_device_register(&at91cap9_spi1_device);
         }
 }
@@ -659,8 +651,6 @@ static struct platform_device at91cap9_tcb_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has one clock and irq for all three TC channels */
-        at91_clock_associate("tcb_clk", &at91cap9_tcb_device.dev, "t0_clk");
         platform_device_register(&at91cap9_tcb_device);
 }
 #else
@@ -1001,12 +991,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91CAP9_ID_SSC0:
                 pdev = &at91cap9_ssc0_device;
                 configure_ssc0_pins(pins);
-                at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
                 break;
         case AT91CAP9_ID_SSC1:
                 pdev = &at91cap9_ssc1_device;
                 configure_ssc1_pins(pins);
-                at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
                 break;
         default:
                 return;
@@ -1199,32 +1187,30 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91cap9_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91CAP9_ID_US0:
                         pdev = &at91cap9_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91CAP9_ID_US1:
                         pdev = &at91cap9_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91CAP9_ID_US2:
                         pdev = &at91cap9_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1232,8 +1218,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91cap9_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 2e9ecad97f3d..b228ce9e21a1 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -18,6 +18,7 @@
 #include <mach/at91rm9200.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -191,6 +192,26 @@ static struct clk *periph_clocks[] __initdata = {
         // irq0 .. irq6
 };
 
+static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
+        CLKDEV_CON_DEV_ID("ssc", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("ssc", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("ssc", "ssc.2", &ssc2_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+};
+
 /*
  * The four programmable clocks.
  * You must configure pin multiplexing to bring these signals out.
@@ -227,12 +248,29 @@ static void __init at91rm9200_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         clk_register(&pck0);
         clk_register(&pck1);
         clk_register(&pck2);
         clk_register(&pck3);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91rm9200_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -266,15 +304,25 @@ static void at91rm9200_reset(void)
         at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 }
 
+int rm9200_type;
+EXPORT_SYMBOL(rm9200_type);
+
+void __init at91rm9200_set_type(int type)
+{
+        rm9200_type = type;
+}
 
 /* --------------------------------------------------------------------
  *  AT91RM9200 processor initialization
  * -------------------------------------------------------------------- */
-void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks)
+void __init at91rm9200_map_io(void)
 {
         /* Map peripherals */
         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
+}
 
+void __init at91rm9200_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91rm9200_reset;
         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
@@ -288,7 +336,8 @@ void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks
         at91rm9200_register_clocks();
 
         /* Initialize GPIO subsystem */
-        at91_gpio_init(at91rm9200_gpio, banks);
+        at91_gpio_init(at91rm9200_gpio,
+                cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 }
 
 
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 7b539228e0ef..a0ba475be04c 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -644,15 +644,7 @@ static struct platform_device at91rm9200_tcb1_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has a separate clock and irq for each TC channel */
-        at91_clock_associate("tc0_clk", &at91rm9200_tcb0_device.dev, "t0_clk");
-        at91_clock_associate("tc1_clk", &at91rm9200_tcb0_device.dev, "t1_clk");
-        at91_clock_associate("tc2_clk", &at91rm9200_tcb0_device.dev, "t2_clk");
         platform_device_register(&at91rm9200_tcb0_device);
-
-        at91_clock_associate("tc3_clk", &at91rm9200_tcb1_device.dev, "t0_clk");
-        at91_clock_associate("tc4_clk", &at91rm9200_tcb1_device.dev, "t1_clk");
-        at91_clock_associate("tc5_clk", &at91rm9200_tcb1_device.dev, "t2_clk");
         platform_device_register(&at91rm9200_tcb1_device);
 }
 #else
@@ -849,17 +841,14 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91RM9200_ID_SSC0:
                 pdev = &at91rm9200_ssc0_device;
                 configure_ssc0_pins(pins);
-                at91_clock_associate("ssc0_clk", &pdev->dev, "ssc");
                 break;
         case AT91RM9200_ID_SSC1:
                 pdev = &at91rm9200_ssc1_device;
                 configure_ssc1_pins(pins);
-                at91_clock_associate("ssc1_clk", &pdev->dev, "ssc");
                 break;
         case AT91RM9200_ID_SSC2:
                 pdev = &at91rm9200_ssc2_device;
                 configure_ssc2_pins(pins);
-                at91_clock_associate("ssc2_clk", &pdev->dev, "ssc");
                 break;
         default:
                 return;
@@ -1109,37 +1098,34 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91rm9200_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91RM9200_ID_US0:
                         pdev = &at91rm9200_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91RM9200_ID_US1:
                         pdev = &at91rm9200_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91RM9200_ID_US2:
                         pdev = &at91rm9200_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 case AT91RM9200_ID_US3:
                         pdev = &at91rm9200_uart3_device;
                         configure_usart3_pins(pins);
-                        at91_clock_associate("usart3_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1147,8 +1133,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91rm9200_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 195208b30024..7d606b04d313 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -231,6 +231,28 @@ static struct clk *periph_clocks[] __initdata = {
         // irq0 .. irq2
 };
 
+static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
+        CLKDEV_CON_DEV_ID("t3_clk", "atmel_tcb.1", &tc3_clk),
+        CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
+        CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
+};
+
 /*
  * The two programmable clocks.
  * You must configure pin multiplexing to bring these signals out.
@@ -255,10 +277,27 @@ static void __init at91sam9260_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         clk_register(&pck0);
         clk_register(&pck1);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91sam9260_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -289,7 +328,7 @@ static void at91sam9260_poweroff(void)
  *  AT91SAM9260 processor initialization
  * -------------------------------------------------------------------- */
 
-static void __init at91sam9xe_initialize(void)
+static void __init at91sam9xe_map_io(void)
 {
         unsigned long cidr, sram_size;
 
@@ -310,18 +349,21 @@ static void __init at91sam9xe_initialize(void)
         iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
 }
 
-void __init at91sam9260_initialize(unsigned long main_clock)
+void __init at91sam9260_map_io(void)
 {
         /* Map peripherals */
         iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
 
         if (cpu_is_at91sam9xe())
-                at91sam9xe_initialize();
+                at91sam9xe_map_io();
         else if (cpu_is_at91sam9g20())
                 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
         else
                 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
+}
 
+void __init at91sam9260_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91sam9_alt_reset;
         pm_power_off = at91sam9260_poweroff;
         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 07eb7b07e442..1fdeb9058a76 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -609,7 +609,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
                 at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI1_SPCK */
 
-                at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
                 platform_device_register(&at91sam9260_spi0_device);
         }
         if (enable_spi1) {
@@ -617,7 +616,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI1_MOSI */
                 at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI1_SPCK */
 
-                at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
                 platform_device_register(&at91sam9260_spi1_device);
         }
 }
@@ -694,15 +692,7 @@ static struct platform_device at91sam9260_tcb1_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has a separate clock and irq for each TC channel */
-        at91_clock_associate("tc0_clk", &at91sam9260_tcb0_device.dev, "t0_clk");
-        at91_clock_associate("tc1_clk", &at91sam9260_tcb0_device.dev, "t1_clk");
-        at91_clock_associate("tc2_clk", &at91sam9260_tcb0_device.dev, "t2_clk");
         platform_device_register(&at91sam9260_tcb0_device);
-
-        at91_clock_associate("tc3_clk", &at91sam9260_tcb1_device.dev, "t0_clk");
-        at91_clock_associate("tc4_clk", &at91sam9260_tcb1_device.dev, "t1_clk");
-        at91_clock_associate("tc5_clk", &at91sam9260_tcb1_device.dev, "t2_clk");
         platform_device_register(&at91sam9260_tcb1_device);
 }
 #else
@@ -820,7 +810,6 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91SAM9260_ID_SSC:
                 pdev = &at91sam9260_ssc_device;
                 configure_ssc_pins(pins);
-                at91_clock_associate("ssc_clk", &pdev->dev, "pclk");
                 break;
         default:
                 return;
@@ -1139,47 +1128,42 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91sam9260_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91SAM9260_ID_US0:
                         pdev = &at91sam9260_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9260_ID_US1:
                         pdev = &at91sam9260_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9260_ID_US2:
                         pdev = &at91sam9260_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9260_ID_US3:
                         pdev = &at91sam9260_uart3_device;
                         configure_usart3_pins(pins);
-                        at91_clock_associate("usart3_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9260_ID_US4:
                         pdev = &at91sam9260_uart4_device;
                         configure_usart4_pins();
-                        at91_clock_associate("usart4_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9260_ID_US5:
                         pdev = &at91sam9260_uart5_device;
                         configure_usart5_pins();
-                        at91_clock_associate("usart5_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1187,8 +1171,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91sam9260_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index fcad88668504..c1483168c97a 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -178,6 +178,24 @@ static struct clk *periph_clocks[] __initdata = {
         // irq0 .. irq2
 };
 
+static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+};
+
 /*
  * The four programmable clocks.
  * You must configure pin multiplexing to bring these signals out.
@@ -228,6 +246,11 @@ static void __init at91sam9261_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         clk_register(&pck0);
         clk_register(&pck1);
         clk_register(&pck2);
@@ -237,6 +260,18 @@ static void __init at91sam9261_register_clocks(void)
         clk_register(&hck1);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91sam9261_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -267,7 +302,7 @@ static void at91sam9261_poweroff(void)
  *  AT91SAM9261 processor initialization
  * -------------------------------------------------------------------- */
 
-void __init at91sam9261_initialize(unsigned long main_clock)
+void __init at91sam9261_map_io(void)
 {
         /* Map peripherals */
         iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
@@ -276,8 +311,10 @@ void __init at91sam9261_initialize(unsigned long main_clock)
                 iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
         else
                 iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
+}
 
-
+void __init at91sam9261_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91sam9_alt_reset;
         pm_power_off = at91sam9261_poweroff;
         at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 59fc48311fb0..3eb4538fceeb 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -426,7 +426,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
                 at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 
-                at91_clock_associate("spi0_clk", &at91sam9261_spi0_device.dev, "spi_clk");
                 platform_device_register(&at91sam9261_spi0_device);
         }
         if (enable_spi1) {
@@ -434,7 +433,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PB31, 0);    /* SPI1_MOSI */
                 at91_set_A_periph(AT91_PIN_PB29, 0);    /* SPI1_SPCK */
 
-                at91_clock_associate("spi1_clk", &at91sam9261_spi1_device.dev, "spi_clk");
                 platform_device_register(&at91sam9261_spi1_device);
         }
 }
@@ -581,10 +579,6 @@ static struct platform_device at91sam9261_tcb_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has a separate clock and irq for each TC channel */
-        at91_clock_associate("tc0_clk", &at91sam9261_tcb_device.dev, "t0_clk");
-        at91_clock_associate("tc1_clk", &at91sam9261_tcb_device.dev, "t1_clk");
-        at91_clock_associate("tc2_clk", &at91sam9261_tcb_device.dev, "t2_clk");
         platform_device_register(&at91sam9261_tcb_device);
 }
 #else
@@ -786,17 +780,14 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91SAM9261_ID_SSC0:
                 pdev = &at91sam9261_ssc0_device;
                 configure_ssc0_pins(pins);
-                at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
                 break;
         case AT91SAM9261_ID_SSC1:
                 pdev = &at91sam9261_ssc1_device;
                 configure_ssc1_pins(pins);
-                at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
                 break;
         case AT91SAM9261_ID_SSC2:
                 pdev = &at91sam9261_ssc2_device;
                 configure_ssc2_pins(pins);
-                at91_clock_associate("ssc2_clk", &pdev->dev, "pclk");
                 break;
         default:
                 return;
@@ -989,32 +980,30 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91sam9261_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91SAM9261_ID_US0:
                         pdev = &at91sam9261_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9261_ID_US1:
                         pdev = &at91sam9261_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9261_ID_US2:
                         pdev = &at91sam9261_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1022,8 +1011,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91sam9261_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 249f900954d8..dc28477d14ff 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -199,6 +199,23 @@ static struct clk *periph_clocks[] __initdata = {
         // irq0 .. irq1
 };
 
+static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+};
+
 /*
  * The four programmable clocks.
  * You must configure pin multiplexing to bring these signals out.
@@ -235,12 +252,29 @@ static void __init at91sam9263_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         clk_register(&pck0);
         clk_register(&pck1);
         clk_register(&pck2);
         clk_register(&pck3);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91sam9263_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -279,11 +313,14 @@ static void at91sam9263_poweroff(void)
  *  AT91SAM9263 processor initialization
  * -------------------------------------------------------------------- */
 
-void __init at91sam9263_initialize(unsigned long main_clock)
+void __init at91sam9263_map_io(void)
 {
         /* Map peripherals */
         iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
+}
 
+void __init at91sam9263_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91sam9_alt_reset;
         pm_power_off = at91sam9263_poweroff;
         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index fb5c23af1017..ffe081b77ed0 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -308,7 +308,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 }
 
                 mmc0_data = *data;
-                at91_clock_associate("mci0_clk", &at91sam9263_mmc0_device.dev, "mci_clk");
                 platform_device_register(&at91sam9263_mmc0_device);
         } else {                        /* MCI1 */
                 /* CLK */
@@ -339,7 +338,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
                 }
 
                 mmc1_data = *data;
-                at91_clock_associate("mci1_clk", &at91sam9263_mmc1_device.dev, "mci_clk");
                 platform_device_register(&at91sam9263_mmc1_device);
         }
 }
@@ -686,7 +684,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_B_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
                 at91_set_B_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 
-                at91_clock_associate("spi0_clk", &at91sam9263_spi0_device.dev, "spi_clk");
                 platform_device_register(&at91sam9263_spi0_device);
         }
         if (enable_spi1) {
@@ -694,7 +691,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PB13, 0);    /* SPI1_MOSI */
                 at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_SPCK */
 
-                at91_clock_associate("spi1_clk", &at91sam9263_spi1_device.dev, "spi_clk");
                 platform_device_register(&at91sam9263_spi1_device);
         }
 }
@@ -941,8 +937,6 @@ static struct platform_device at91sam9263_tcb_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has one clock and irq for all three TC channels */
-        at91_clock_associate("tcb_clk", &at91sam9263_tcb_device.dev, "t0_clk");
         platform_device_register(&at91sam9263_tcb_device);
 }
 #else
@@ -1171,12 +1165,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91SAM9263_ID_SSC0:
                 pdev = &at91sam9263_ssc0_device;
                 configure_ssc0_pins(pins);
-                at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
                 break;
         case AT91SAM9263_ID_SSC1:
                 pdev = &at91sam9263_ssc1_device;
                 configure_ssc1_pins(pins);
-                at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
                 break;
         default:
                 return;
@@ -1370,32 +1362,30 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91sam9263_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91SAM9263_ID_US0:
                         pdev = &at91sam9263_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9263_ID_US1:
                         pdev = &at91sam9263_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9263_ID_US2:
                         pdev = &at91sam9263_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1403,8 +1393,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91sam9263_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index c67b47f1c0fd..2bb6ff9af1c7 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -184,22 +184,6 @@ static struct clk vdec_clk = {
         .type           = CLK_TYPE_PERIPHERAL,
 };
 
-/* One additional fake clock for ohci */
-static struct clk ohci_clk = {
-        .name           = "ohci_clk",
-        .pmc_mask       = 0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .parent         = &uhphs_clk,
-};
-
-/* One additional fake clock for second TC block */
-static struct clk tcb1_clk = {
-        .name           = "tcb1_clk",
-        .pmc_mask       = 0,
-        .type           = CLK_TYPE_PERIPHERAL,
-        .parent         = &tcb0_clk,
-};
-
 static struct clk *periph_clocks[] __initdata = {
         &pioA_clk,
         &pioB_clk,
@@ -228,8 +212,30 @@ static struct clk *periph_clocks[] __initdata = {
         &udphs_clk,
         &mmc1_clk,
         // irq0
-        &ohci_clk,
-        &tcb1_clk,
+};
+
+static struct clk_lookup periph_clocks_lookups[] = {
+        /* One additional fake clock for ohci */
+        CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci.0", &uhphs_clk),
+        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc.0", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc.0", &udphs_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
+        CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
+        CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 };
 
 /*
@@ -256,6 +262,11 @@ static void __init at91sam9g45_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
                 clk_register(&vdec_clk);
 
@@ -263,6 +274,18 @@ static void __init at91sam9g45_register_clocks(void)
         clk_register(&pck1);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91sam9g45_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -306,11 +329,14 @@ static void at91sam9g45_poweroff(void)
  *  AT91SAM9G45 processor initialization
  * -------------------------------------------------------------------- */
 
-void __init at91sam9g45_initialize(unsigned long main_clock)
+void __init at91sam9g45_map_io(void)
 {
         /* Map peripherals */
         iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
+}
 
+void __init at91sam9g45_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91sam9g45_reset;
         pm_power_off = at91sam9g45_poweroff;
         at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 5e9f8a4c38df..05674865bc21 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -180,7 +180,6 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
         }
 
         usbh_ehci_data = *data;
-        at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
         platform_device_register(&at91_usbh_ehci_device);
 }
 #else
@@ -266,10 +265,6 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
 
         /* Pullup pin is handled internally by USB device peripheral */
 
-        /* Clocks */
-        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
-        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
-
         platform_device_register(&at91_usba_udc_device);
 }
 #else
@@ -478,7 +473,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
                 }
 
                 mmc0_data = *data;
-                at91_clock_associate("mci0_clk", &at91sam9g45_mmc0_device.dev, "mci_clk");
                 platform_device_register(&at91sam9g45_mmc0_device);
 
         } else {                        /* MCI1 */
@@ -504,7 +498,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
                 }
 
                 mmc1_data = *data;
-                at91_clock_associate("mci1_clk", &at91sam9g45_mmc1_device.dev, "mci_clk");
                 platform_device_register(&at91sam9g45_mmc1_device);
 
         }
@@ -801,7 +794,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
                 at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
 
-                at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
                 platform_device_register(&at91sam9g45_spi0_device);
         }
         if (enable_spi1) {
@@ -809,7 +801,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
                 at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
                 at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
 
-                at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
                 platform_device_register(&at91sam9g45_spi1_device);
         }
 }
@@ -999,10 +990,7 @@ static struct platform_device at91sam9g45_tcb1_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has one clock and irq for all six TC channels */
-        at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
         platform_device_register(&at91sam9g45_tcb0_device);
-        at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
         platform_device_register(&at91sam9g45_tcb1_device);
 }
 #else
@@ -1286,12 +1274,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91SAM9G45_ID_SSC0:
                 pdev = &at91sam9g45_ssc0_device;
                 configure_ssc0_pins(pins);
-                at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
                 break;
         case AT91SAM9G45_ID_SSC1:
                 pdev = &at91sam9g45_ssc1_device;
                 configure_ssc1_pins(pins);
-                at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
                 break;
         default:
                 return;
@@ -1527,37 +1513,34 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91sam9g45_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91SAM9G45_ID_US0:
                         pdev = &at91sam9g45_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9G45_ID_US1:
                         pdev = &at91sam9g45_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9G45_ID_US2:
                         pdev = &at91sam9g45_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9G45_ID_US3:
                         pdev = &at91sam9g45_uart3_device;
                         configure_usart3_pins(pins);
-                        at91_clock_associate("usart3_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1565,8 +1548,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91sam9g45_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 6a9d24e5ed8e..1a40f16b66c8 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -190,6 +190,24 @@ static struct clk *periph_clocks[] __initdata = {
         // irq0
 };
 
+static struct clk_lookup periph_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc.0", &utmi_clk),
+        CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc.0", &udphs_clk),
+        CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
+        CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
+        CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
+        CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
+};
+
+static struct clk_lookup usart_clocks_lookups[] = {
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
+        CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
+};
+
 /*
  * The two programmable clocks.
  * You must configure pin multiplexing to bring these signals out.
@@ -214,10 +232,27 @@ static void __init at91sam9rl_register_clocks(void)
         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
                 clk_register(periph_clocks[i]);
 
+        clkdev_add_table(periph_clocks_lookups,
+                         ARRAY_SIZE(periph_clocks_lookups));
+        clkdev_add_table(usart_clocks_lookups,
+                         ARRAY_SIZE(usart_clocks_lookups));
+
         clk_register(&pck0);
         clk_register(&pck1);
 }
 
+static struct clk_lookup console_clock_lookup;
+
+void __init at91sam9rl_set_console_clock(int id)
+{
+        if (id >= ARRAY_SIZE(usart_clocks_lookups))
+                return;
+
+        console_clock_lookup.con_id = "usart";
+        console_clock_lookup.clk = usart_clocks_lookups[id].clk;
+        clkdev_add(&console_clock_lookup);
+}
+
 /* --------------------------------------------------------------------
  *  GPIO
  * -------------------------------------------------------------------- */
@@ -252,7 +287,7 @@ static void at91sam9rl_poweroff(void)
  *  AT91SAM9RL processor initialization
  * -------------------------------------------------------------------- */
 
-void __init at91sam9rl_initialize(unsigned long main_clock)
+void __init at91sam9rl_map_io(void)
 {
         unsigned long cidr, sram_size;
 
@@ -275,7 +310,10 @@ void __init at91sam9rl_initialize(unsigned long main_clock)
 
         /* Map SRAM */
         iotable_init(at91sam9rl_sram_desc, ARRAY_SIZE(at91sam9rl_sram_desc));
+}
 
+void __init at91sam9rl_initialize(unsigned long main_clock)
+{
         at91_arch_reset = at91sam9_alt_reset;
         pm_power_off = at91sam9rl_poweroff;
         at91_extern_irq = (1 << AT91SAM9RL_ID_IRQ0);
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index c49262bddd85..c296045f2b6a 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -155,10 +155,6 @@ void __init at91_add_device_usba(struct usba_platform_data *data)
 
         /* Pullup pin is handled internally by USB device peripheral */
 
-        /* Clocks */
-        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
-        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
-
         platform_device_register(&at91_usba_udc_device);
 }
 #else
@@ -605,10 +601,6 @@ static struct platform_device at91sam9rl_tcb_device = {
 
 static void __init at91_add_device_tc(void)
 {
-        /* this chip has a separate clock and irq for each TC channel */
-        at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
-        at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
-        at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
         platform_device_register(&at91sam9rl_tcb_device);
 }
 #else
@@ -892,12 +884,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)
         case AT91SAM9RL_ID_SSC0:
                 pdev = &at91sam9rl_ssc0_device;
                 configure_ssc0_pins(pins);
-                at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
                 break;
         case AT91SAM9RL_ID_SSC1:
                 pdev = &at91sam9rl_ssc1_device;
                 configure_ssc1_pins(pins);
-                at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
                 break;
         default:
                 return;
@@ -1141,37 +1131,34 @@ struct platform_device *atmel_default_console_device;	/* the serial console devi
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (id) {
                 case 0:         /* DBGU */
                         pdev = &at91sam9rl_dbgu_device;
                         configure_dbgu_pins();
-                        at91_clock_associate("mck", &pdev->dev, "usart");
                         break;
                 case AT91SAM9RL_ID_US0:
                         pdev = &at91sam9rl_uart0_device;
                         configure_usart0_pins(pins);
-                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9RL_ID_US1:
                         pdev = &at91sam9rl_uart1_device;
                         configure_usart1_pins(pins);
-                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9RL_ID_US2:
                         pdev = &at91sam9rl_uart2_device;
                         configure_usart2_pins(pins);
-                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
                         break;
                 case AT91SAM9RL_ID_US3:
                         pdev = &at91sam9rl_uart3_device;
                         configure_usart3_pins(pins);
-                        at91_clock_associate("usart3_clk", &pdev->dev, "usart");
                         break;
                 default:
                         return;
         }
-        pdev->id = portnr;              /* update to mapped ID */
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;            /* update to mapped ID */
 
         if (portnr < ATMEL_MAX_UART)
                 at91_uarts[portnr] = pdev;
@@ -1179,8 +1166,10 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
 
 void __init at91_set_serial_console(unsigned portnr)
 {
-        if (portnr < ATMEL_MAX_UART)
+        if (portnr < ATMEL_MAX_UART) {
                 atmel_default_console_device = at91_uarts[portnr];
+                at91sam9rl_set_console_clock(portnr);
+        }
 }
 
 void __init at91_add_device_serial(void)
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index ad3ec85b2790..56ba3bd035ae 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -37,11 +37,6 @@ unsigned long clk_get_rate(struct clk *clk)
         return AT91X40_MASTER_CLOCK;
 }
 
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        return NULL;
-}
-
 void __init at91x40_initialize(unsigned long main_clock)
 {
         at91_extern_irq = (1 << AT91X40_ID_IRQ0) | (1 << AT91X40_ID_IRQ1)
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 8a3fc84847c1..ab1d463aa47d 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -35,14 +35,18 @@
 
 #include <mach/board.h>
 #include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 
 
-static void __init onearm_map_io(void)
+static void __init onearm_init_early(void)
 {
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        at91rm9200_initialize(18432000);
 
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -92,9 +96,9 @@ static void __init onearm_board_init(void)
 
 MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = onearm_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = onearm_init_early,
         .init_irq       = onearm_init_irq,
         .init_machine   = onearm_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index cba7f7771fee..a4924de48c36 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -48,7 +48,7 @@
 #include "generic.h"
 
 
-static void __init afeb9260_map_io(void)
+static void __init afeb9260_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -218,9 +218,9 @@ static void __init afeb9260_board_init(void)
 
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
         /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = afeb9260_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = afeb9260_init_early,
         .init_irq       = afeb9260_init_irq,
         .init_machine   = afeb9260_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
deleted file mode 100644
index 3929f1c9e4e5..000000000000
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/board-at572d940hf_ek.c
- *
- * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
- * Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/ds1305.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/irq.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <mach/board.h>
-#include <mach/gpio.h>
-#include <mach/at91sam9_smc.h>
-
-#include "sam9_smc.h"
-#include "generic.h"
-
-
-static void __init eb_map_io(void)
-{
-        /* Initialize processor: 12.500 MHz crystal */
-        at572d940hf_initialize(12000000);
-
-        /* DBGU on ttyS0. (Rx & Tx only) */
-        at91_register_uart(0, 0, 0);
-
-        /* USART0 on ttyS1. (Rx & Tx only) */
-        at91_register_uart(AT572D940HF_ID_US0, 1, 0);
-
-        /* USART1 on ttyS2. (Rx & Tx only) */
-        at91_register_uart(AT572D940HF_ID_US1, 2, 0);
-
-        /* USART2 on ttyS3. (Tx & Rx only */
-        at91_register_uart(AT572D940HF_ID_US2, 3, 0);
-
-        /* set serial console to ttyS0 (ie, DBGU) */
-        at91_set_serial_console(0);
-}
-
-static void __init eb_init_irq(void)
-{
-        at572d940hf_init_interrupts(NULL);
-}
-
-
-/*
- * USB Host Port
- */
-static struct at91_usbh_data __initdata eb_usbh_data = {
-        .ports          = 2,
-};
-
-
-/*
- * USB Device Port
- */
-static struct at91_udc_data __initdata eb_udc_data = {
-        .vbus_pin       = 0,            /* no VBUS detection,UDC always on */
-        .pullup_pin     = 0,            /* pull-up driven by UDC */
-};
-
-
-/*
- * MCI (SD/MMC)
- */
-static struct at91_mmc_data __initdata eb_mmc_data = {
-        .wire4          = 1,
-/*      .det_pin        = ... not connected */
-/*      .wp_pin         = ... not connected */
-/*      .vcc_pin        = ... not connected */
-};
-
-
-/*
- * MACB Ethernet device
- */
-static struct at91_eth_data __initdata eb_eth_data = {
-        .phy_irq_pin    = AT91_PIN_PB25,
-        .is_rmii        = 1,
-};
-
-/*
- * NOR flash
- */
-
-static struct mtd_partition eb_nor_partitions[] = {
-        {
-                .name           = "Raw Environment",
-                .offset         = 0,
-                .size           = SZ_4M,
-                .mask_flags     = 0,
-        },
-        {
-                .name           = "OS FS",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 3 * SZ_1M,
-                .mask_flags     = 0,
-        },
-        {
-                .name           = "APP FS",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-                .mask_flags     = 0,
-        },
-};
-
-static void nor_flash_set_vpp(struct map_info* mi, int i) {
-};
-
-static struct physmap_flash_data nor_flash_data = {
-        .width          = 4,
-        .parts          = eb_nor_partitions,
-        .nr_parts       = ARRAY_SIZE(eb_nor_partitions),
-        .set_vpp        = nor_flash_set_vpp,
-};
-
-static struct resource nor_flash_resources[] = {
-        {
-                .start  = AT91_CHIPSELECT_0,
-                .end    = AT91_CHIPSELECT_0 + SZ_16M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device nor_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                                .platform_data = &nor_flash_data,
-                        },
-        .resource       = nor_flash_resources,
-        .num_resources  = ARRAY_SIZE(nor_flash_resources),
-};
-
-static struct sam9_smc_config __initdata eb_nor_smc_config = {
-        .ncs_read_setup         = 1,
-        .nrd_setup              = 1,
-        .ncs_write_setup        = 1,
-        .nwe_setup              = 1,
-
-        .ncs_read_pulse         = 7,
-        .nrd_pulse              = 7,
-        .ncs_write_pulse        = 7,
-        .nwe_pulse              = 7,
-
-        .read_cycle             = 9,
-        .write_cycle            = 9,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
-        .tdf_cycles             = 1,
-};
-
-static void __init eb_add_device_nor(void)
-{
-        /* configure chip-select 0 (NOR) */
-        sam9_smc_configure(0, &eb_nor_smc_config);
-        platform_device_register(&nor_flash);
-}
-
-/*
- * NAND flash
- */
-static struct mtd_partition __initdata eb_nand_partition[] = {
-        {
-                .name   = "Partition 1",
-                .offset = 0,
-                .size   = SZ_16M,
-        },
-        {
-                .name   = "Partition 2",
-                .offset = MTDPART_OFS_NXTBLK,
-                .size   = MTDPART_SIZ_FULL,
-        }
-};
-
-static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
-{
-        *num_partitions = ARRAY_SIZE(eb_nand_partition);
-        return eb_nand_partition;
-}
-
-static struct atmel_nand_data __initdata eb_nand_data = {
-        .ale            = 22,
-        .cle            = 21,
-/*      .det_pin        = ... not connected */
-/*      .rdy_pin        = AT91_PIN_PC16, */
-        .enable_pin     = AT91_PIN_PA15,
-        .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
-};
-
-static struct sam9_smc_config __initdata eb_nand_smc_config = {
-        .ncs_read_setup         = 0,
-        .nrd_setup              = 0,
-        .ncs_write_setup        = 1,
-        .nwe_setup              = 1,
-
-        .ncs_read_pulse         = 3,
-        .nrd_pulse              = 3,
-        .ncs_write_pulse        = 3,
-        .nwe_pulse              = 3,
-
-        .read_cycle             = 5,
-        .write_cycle            = 5,
-
-        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
-        .tdf_cycles             = 12,
-};
-
-static void __init eb_add_device_nand(void)
-{
-        /* setup bus-width (8 or 16) */
-        if (eb_nand_data.bus_width_16)
-                eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
-        else
-                eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
-
-        /* configure chip-select 3 (NAND) */
-        sam9_smc_configure(3, &eb_nand_smc_config);
-
-        at91_add_device_nand(&eb_nand_data);
-}
-
-
-/*
- * SPI devices
- */
-static struct resource rtc_resources[] = {
-        [0] = {
-                .start  = AT572D940HF_ID_IRQ1,
-                .end    = AT572D940HF_ID_IRQ1,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct ds1305_platform_data ds1306_data = {
-        .is_ds1306      = true,
-        .en_1hz         = false,
-};
-
-static struct spi_board_info eb_spi_devices[] = {
-        {       /* RTC Dallas DS1306 */
-                .modalias       = "rtc-ds1305",
-                .chip_select    = 3,
-                .mode           = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
-                .max_speed_hz   = 500000,
-                .bus_num        = 0,
-                .irq            = AT572D940HF_ID_IRQ1,
-                .platform_data  = (void *) &ds1306_data,
-        },
-#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
-        {       /* Dataflash card */
-                .modalias       = "mtd_dataflash",
-                .chip_select    = 0,
-                .max_speed_hz   = 15 * 1000 * 1000,
-                .bus_num        = 0,
-        },
-#endif
-};
-
-static void __init eb_board_init(void)
-{
-        /* Serial */
-        at91_add_device_serial();
-        /* USB Host */
-        at91_add_device_usbh(&eb_usbh_data);
-        /* USB Device */
-        at91_add_device_udc(&eb_udc_data);
-        /* I2C */
-        at91_add_device_i2c(NULL, 0);
-        /* NOR */
-        eb_add_device_nor();
-        /* NAND */
-        eb_add_device_nand();
-        /* SPI */
-        at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
-        /* MMC */
-        at91_add_device_mmc(0, &eb_mmc_data);
-        /* Ethernet */
-        at91_add_device_eth(&eb_eth_data);
-        /* mAgic */
-        at91_add_device_mAgic();
-}
-
-MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
-        /* Maintainer: Atmel <costa.antonior@gmail.com> */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
-        .timer          = &at91sam926x_timer,
-        .map_io         = eb_map_io,
-        .init_irq       = eb_init_irq,
-        .init_machine   = eb_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index b54e3e6fceb6..148fccb9a25a 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -45,7 +45,7 @@
 #include "generic.h"
 
 
-static void __init cam60_map_io(void)
+static void __init cam60_init_early(void)
 {
         /* Initialize processor: 10 MHz crystal */
         at91sam9260_initialize(10000000);
@@ -198,9 +198,9 @@ static void __init cam60_board_init(void)
 
 MACHINE_START(CAM60, "KwikByte CAM60")
         /* Maintainer: KwikByte */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = cam60_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = cam60_init_early,
         .init_irq       = cam60_init_irq,
         .init_machine   = cam60_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index e7274440ead9..1904fdf87613 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -44,12 +44,13 @@
 #include <mach/gpio.h>
 #include <mach/at91cap9_matrix.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
 
 
-static void __init cap9adk_map_io(void)
+static void __init cap9adk_init_early(void)
 {
         /* Initialize processor: 12 MHz crystal */
         at91cap9_initialize(12000000);
@@ -187,11 +188,6 @@ static struct atmel_nand_data __initdata cap9adk_nand_data = {
 //      .rdy_pin        = ... not connected
         .enable_pin     = AT91_PIN_PD15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata cap9adk_nand_smc_config = {
@@ -219,6 +215,7 @@ static void __init cap9adk_add_device_nand(void)
         csa = at91_sys_read(AT91_MATRIX_EBICSA);
         at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
 
+        cap9adk_nand_data.bus_width_16 = !board_have_nand_8bit();
         /* setup bus-width (8 or 16) */
         if (cap9adk_nand_data.bus_width_16)
                 cap9adk_nand_smc_config.mode |= AT91_SMC_DBW_16;
@@ -399,9 +396,9 @@ static void __init cap9adk_board_init(void)
 
 MACHINE_START(AT91CAP9ADK, "Atmel AT91CAP9A-DK")
         /* Maintainer: Stelian Pop <stelian.pop@leadtechdesign.com> */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = cap9adk_map_io,
+        .map_io         = at91cap9_map_io,
+        .init_early     = cap9adk_init_early,
         .init_irq       = cap9adk_init_irq,
         .init_machine   = cap9adk_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 295e1e77fa60..f36b18687494 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -40,10 +40,10 @@
 #include "generic.h"
 
 
-static void __init carmeva_map_io(void)
+static void __init carmeva_init_early(void)
 {
         /* Initialize processor: 20.000 MHz crystal */
-        at91rm9200_initialize(20000000, AT91RM9200_BGA);
+        at91rm9200_initialize(20000000);
 
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -162,9 +162,9 @@ static void __init carmeva_board_init(void)
 
 MACHINE_START(CARMEVA, "Carmeva")
         /* Maintainer: Conitec Datasystems */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = carmeva_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = carmeva_init_early,
         .init_irq       = carmeva_init_irq,
         .init_machine   = carmeva_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 3838594578f3..980511084fe4 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -47,7 +47,7 @@
 #include "sam9_smc.h"
 #include "generic.h"
 
-static void __init cpu9krea_map_io(void)
+static void __init cpu9krea_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -375,9 +375,9 @@ MACHINE_START(CPUAT9260, "Eukrea CPU9260")
 MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
 #endif
         /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = cpu9krea_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = cpu9krea_init_early,
         .init_irq       = cpu9krea_init_irq,
         .init_machine   = cpu9krea_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 2f4dd8cdd484..6daabe3907a1 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -38,6 +38,7 @@
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 
@@ -50,10 +51,13 @@ static struct gpio_led cpuat91_leds[] = {
         },
 };
 
-static void __init cpuat91_map_io(void)
+static void __init cpuat91_init_early(void)
 {
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        at91rm9200_initialize(18432000);
 
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -175,9 +179,9 @@ static void __init cpuat91_board_init(void)
 
 MACHINE_START(CPUAT91, "Eukrea")
         /* Maintainer: Eric Benard - EUKREA Electromatique */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = cpuat91_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = cpuat91_init_early,
         .init_irq       = cpuat91_init_irq,
         .init_machine   = cpuat91_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index 464839dc39bd..d98bcec1dfe0 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -43,10 +43,10 @@
 #include "generic.h"
 
 
-static void __init csb337_map_io(void)
+static void __init csb337_init_early(void)
 {
         /* Initialize processor: 3.6864 MHz crystal */
-        at91rm9200_initialize(3686400, AT91RM9200_BGA);
+        at91rm9200_initialize(3686400);
 
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
@@ -257,9 +257,9 @@ static void __init csb337_board_init(void)
 
 MACHINE_START(CSB337, "Cogent CSB337")
         /* Maintainer: Bill Gatliff */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = csb337_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = csb337_init_early,
         .init_irq       = csb337_init_irq,
         .init_machine   = csb337_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 431688c61412..019aab4e20b0 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -40,10 +40,10 @@
 #include "generic.h"
 
 
-static void __init csb637_map_io(void)
+static void __init csb637_init_early(void)
 {
         /* Initialize processor: 3.6864 MHz crystal */
-        at91rm9200_initialize(3686400, AT91RM9200_BGA);
+        at91rm9200_initialize(3686400);
 
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -138,9 +138,9 @@ static void __init csb637_board_init(void)
 
 MACHINE_START(CSB637, "Cogent CSB637")
         /* Maintainer: Bill Gatliff */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = csb637_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = csb637_init_early,
         .init_irq       = csb637_init_irq,
         .init_machine   = csb637_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index d8df59a3426d..d2023f27c652 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -35,7 +35,7 @@ static void __init at91eb01_init_irq(void)
         at91x40_init_interrupts(NULL);
 }
 
-static void __init at91eb01_map_io(void)
+static void __init at91eb01_init_early(void)
 {
         at91x40_initialize(40000000);
 }
@@ -43,7 +43,7 @@ static void __init at91eb01_map_io(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
         /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
         .timer          = &at91x40_timer,
+        .init_early     = at91eb01_init_early,
         .init_irq       = at91eb01_init_irq,
-        .map_io         = at91eb01_map_io,
 MACHINE_END
 
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index 6cf6566ae346..e9484535cbc8 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,10 +40,10 @@
 #include "generic.h"
 
 
-static void __init eb9200_map_io(void)
+static void __init eb9200_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_BGA);
+        at91rm9200_initialize(18432000);
 
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -120,9 +120,9 @@ static void __init eb9200_board_init(void)
 }
 
 MACHINE_START(ATEB9200, "Embest ATEB9200")
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = eb9200_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = eb9200_init_early,
         .init_irq       = eb9200_init_irq,
         .init_machine   = eb9200_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index de2fd04e7c8a..a6f57faa10a7 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -38,14 +38,18 @@
 
 #include <mach/board.h>
 #include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 
 
-static void __init ecb_at91map_io(void)
+static void __init ecb_at91init_early(void)
 {
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        at91rm9200_initialize(18432000);
 
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PC7, AT91_PIN_PC7);
@@ -168,9 +172,9 @@ static void __init ecb_at91board_init(void)
 
 MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
         /* Maintainer: emQbit.com */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = ecb_at91map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = ecb_at91init_early,
         .init_irq       = ecb_at91init_irq,
         .init_machine   = ecb_at91board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index a158a0ce458f..bfc0062d1483 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -26,11 +26,16 @@
 
 #include <mach/board.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/cpu.h>
+
 #include "generic.h"
 
-static void __init eco920_map_io(void)
+static void __init eco920_init_early(void)
 {
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
+        at91rm9200_initialize(18432000);
 
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB0, AT91_PIN_PB1);
@@ -86,21 +91,6 @@ static struct platform_device eco920_flash = {
         .num_resources  = 1,
 };
 
-static struct resource at91_beeper_resources[] = {
-        [0] = {
-                .start          = AT91RM9200_BASE_TC3,
-                .end            = AT91RM9200_BASE_TC3 + 0x39,
-                .flags          = IORESOURCE_MEM,
-        },
-};
-
-static struct platform_device at91_beeper = {
-        .name           = "at91_beeper",
-        .id             = 0,
-        .resource       = at91_beeper_resources,
-        .num_resources  = ARRAY_SIZE(at91_beeper_resources),
-};
-
 static struct spi_board_info eco920_spi_devices[] = {
         {       /* CAN controller */
                 .modalias       = "tlv5638",
@@ -139,18 +129,14 @@ static void __init eco920_board_init(void)
                 AT91_SMC_TDF_(1)        /* float time */
         );
 
-        at91_clock_associate("tc3_clk", &at91_beeper.dev, "at91_beeper");
-        at91_set_B_periph(AT91_PIN_PB6, 0);
-        platform_device_register(&at91_beeper);
-
         at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
 }
 
 MACHINE_START(ECO920, "eco920")
         /* Maintainer: Sascha Hauer */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = eco920_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = eco920_init_early,
         .init_irq       = eco920_init_irq,
         .init_machine   = eco920_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index c8a62dc8fa65..466c063b8d21 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -37,7 +37,7 @@
 
 #include "generic.h"
 
-static void __init flexibity_map_io(void)
+static void __init flexibity_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -154,9 +154,9 @@ static void __init flexibity_board_init(void)
 
 MACHINE_START(FLEXIBITY, "Flexibity Connect")
         /* Maintainer: Maxim Osipov */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = flexibity_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = flexibity_init_early,
         .init_irq       = flexibity_init_irq,
         .init_machine   = flexibity_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index dfc7dfe738e4..e2d1dc9eff45 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -57,7 +57,7 @@
  */
 
 
-static void __init foxg20_map_io(void)
+static void __init foxg20_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -266,9 +266,9 @@ static void __init foxg20_board_init(void)
 
 MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
         /* Maintainer: Sergio Tanzilli */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = foxg20_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = foxg20_init_early,
         .init_irq       = foxg20_init_irq,
         .init_machine   = foxg20_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index bc28136ee249..1d4f36b3cb27 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -38,9 +38,9 @@
 #include "sam9_smc.h"
 #include "generic.h"
 
-static void __init gsia18s_map_io(void)
+static void __init gsia18s_init_early(void)
 {
-        stamp9g20_map_io();
+        stamp9g20_init_early();
 
         /*
          * USART0 on ttyS1 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI).
@@ -576,9 +576,9 @@ static void __init gsia18s_board_init(void)
 }
 
 MACHINE_START(GSIA18S, "GS_IA18_S")
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = gsia18s_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = gsia18s_init_early,
         .init_irq       = init_irq,
         .init_machine   = gsia18s_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index d2e1f4ec1fcc..9b003ff744ba 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -35,14 +35,18 @@
 
 #include <mach/board.h>
 #include <mach/gpio.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 
 
-static void __init kafa_map_io(void)
+static void __init kafa_init_early(void)
 {
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        at91rm9200_initialize(18432000);
 
         /* Set up the LEDs */
         at91_init_leds(AT91_PIN_PB4, AT91_PIN_PB4);
@@ -94,9 +98,9 @@ static void __init kafa_board_init(void)
 
 MACHINE_START(KAFA, "Sperry-Sun KAFA")
         /* Maintainer: Sergei Sharonov */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = kafa_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = kafa_init_early,
         .init_irq       = kafa_init_irq,
         .init_machine   = kafa_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index a13d2063faff..a813a74b65f9 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -36,16 +36,19 @@
 
 #include <mach/board.h>
 #include <mach/gpio.h>
-
+#include <mach/cpu.h>
 #include <mach/at91rm9200_mc.h>
 
 #include "generic.h"
 
 
-static void __init kb9202_map_io(void)
+static void __init kb9202_init_early(void)
 {
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
         /* Initialize processor: 10 MHz crystal */
-        at91rm9200_initialize(10000000, AT91RM9200_PQFP);
+        at91rm9200_initialize(10000000);
 
         /* Set up the LEDs */
         at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
@@ -136,9 +139,9 @@ static void __init kb9202_board_init(void)
 
 MACHINE_START(KB9200, "KB920x")
         /* Maintainer: KwikByte, Inc. */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = kb9202_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = kb9202_init_early,
         .init_irq       = kb9202_init_irq,
         .init_machine   = kb9202_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index fe5f1d47e6e2..961e805db68c 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -51,7 +51,7 @@
 #include "generic.h"
 
 
-static void __init neocore926_map_io(void)
+static void __init neocore926_init_early(void)
 {
         /* Initialize processor: 20 MHz crystal */
         at91sam9263_initialize(20000000);
@@ -387,9 +387,9 @@ static void __init neocore926_board_init(void)
 
 MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
         /* Maintainer: ADENEO */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = neocore926_map_io,
+        .map_io         = at91sam9263_map_io,
+        .init_early     = neocore926_init_early,
         .init_irq       = neocore926_init_irq,
         .init_machine   = neocore926_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index feb65787c30b..21a21af25878 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -37,9 +37,9 @@
 #include "generic.h"
 
 
-static void __init pcontrol_g20_map_io(void)
+static void __init pcontrol_g20_init_early(void)
 {
-        stamp9g20_map_io();
+        stamp9g20_init_early();
 
         /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback  A2 */
         at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@@ -222,9 +222,9 @@ static void __init pcontrol_g20_board_init(void)
 
 MACHINE_START(PCONTROL_G20, "PControl G20")
         /* Maintainer: pgsellmann@portner-elektronik.at */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = pcontrol_g20_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = pcontrol_g20_init_early,
         .init_irq       = init_irq,
         .init_machine   = pcontrol_g20_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index 55dad3a46547..756cc2a745dd 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -43,10 +43,10 @@
 #include "generic.h"
 
 
-static void __init picotux200_map_io(void)
+static void __init picotux200_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_BGA);
+        at91rm9200_initialize(18432000);
 
         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
@@ -123,9 +123,9 @@ static void __init picotux200_board_init(void)
 
 MACHINE_START(PICOTUX2XX, "picotux 200")
         /* Maintainer: Kleinhenz Elektronik GmbH */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = picotux200_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = picotux200_init_early,
         .init_irq       = picotux200_init_irq,
         .init_machine   = picotux200_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 69d15a875b66..d1a6001b0bd8 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -48,7 +48,7 @@
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91sam9260_initialize(12000000);
@@ -268,9 +268,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
         /* Maintainer: calao-systems */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index 4c1047c8200d..aef9627710b0 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -45,10 +45,10 @@
 #include "generic.h"
 
 
-static void __init dk_map_io(void)
+static void __init dk_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_BGA);
+        at91rm9200_initialize(18432000);
 
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
@@ -227,9 +227,9 @@ static void __init dk_board_init(void)
 
 MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
         /* Maintainer: SAN People/Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = dk_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = dk_init_early,
         .init_irq       = dk_init_irq,
         .init_machine   = dk_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 9df1be8818c0..015a02183080 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -45,10 +45,10 @@
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_BGA);
+        at91rm9200_initialize(18432000);
 
         /* Setup the LEDs */
         at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
@@ -193,9 +193,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
         /* Maintainer: SAN People/Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 25a26beaa728..aaf1bf0989b3 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -44,7 +44,7 @@
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -212,9 +212,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
         /* Maintainer: Olimex */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index de1816e0e1d9..d600dc123227 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -44,12 +44,13 @@
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -191,11 +192,6 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -218,6 +214,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 
 static void __init ek_add_device_nand(void)
 {
+        ek_nand_data.bus_width_16 = !board_have_nand_8bit();
         /* setup bus-width (8 or 16) */
         if (ek_nand_data.bus_width_16)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
@@ -356,9 +353,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 14acc901e24c..f897f84d43dc 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -48,12 +48,13 @@
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9261_initialize(18432000);
@@ -197,11 +198,6 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC15,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -224,6 +220,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 
 static void __init ek_add_device_nand(void)
 {
+        ek_nand_data.bus_width_16 = !board_have_nand_8bit();
         /* setup bus-width (8 or 16) */
         if (ek_nand_data.bus_width_16)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
@@ -623,9 +620,9 @@ MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
 MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
 #endif
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9261_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index bfe490df58be..605b26f40a4c 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -47,12 +47,13 @@
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 16.367 MHz crystal */
         at91sam9263_initialize(16367660);
@@ -198,11 +199,6 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PA22,
         .enable_pin     = AT91_PIN_PD15,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -225,6 +221,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 
 static void __init ek_add_device_nand(void)
 {
+        ek_nand_data.bus_width_16 = !board_have_nand_8bit();
         /* setup bus-width (8 or 16) */
         if (ek_nand_data.bus_width_16)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
@@ -454,9 +451,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9263_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index ca8198b3c168..7624cf0d006b 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -43,6 +43,7 @@
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
+#include <mach/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
@@ -60,7 +61,7 @@ static int inline ek_have_2mmc(void)
 }
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -175,11 +176,6 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC13,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -202,6 +198,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 
 static void __init ek_add_device_nand(void)
 {
+        ek_nand_data.bus_width_16 = !board_have_nand_8bit();
         /* setup bus-width (8 or 16) */
         if (ek_nand_data.bus_width_16)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
@@ -406,18 +403,18 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
 
 MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 6c999dbd2bcf..063c95d0e8f0 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -41,12 +41,13 @@
 #include <mach/gpio.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
+#include <mach/system_rev.h>
 
 #include "sam9_smc.h"
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91sam9g45_initialize(12000000);
@@ -155,11 +156,6 @@ static struct atmel_nand_data __initdata ek_nand_data = {
         .rdy_pin        = AT91_PIN_PC8,
         .enable_pin     = AT91_PIN_PC14,
         .partition_info = nand_partitions,
-#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
-        .bus_width_16   = 1,
-#else
-        .bus_width_16   = 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata ek_nand_smc_config = {
@@ -182,6 +178,7 @@ static struct sam9_smc_config __initdata ek_nand_smc_config = {
 
 static void __init ek_add_device_nand(void)
 {
+        ek_nand_data.bus_width_16 = !board_have_nand_8bit();
         /* setup bus-width (8 or 16) */
         if (ek_nand_data.bus_width_16)
                 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
@@ -424,9 +421,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9g45_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 3bf3408e94c1..effb399a80a6 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -38,7 +38,7 @@
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91sam9rl_initialize(12000000);
@@ -329,9 +329,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
         /* Maintainer: Atmel */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9rl_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 17f7d9b32142..3eb0a1153cc8 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -40,7 +40,7 @@
 
 #define SNAPPER9260_IO_EXP_GPIO(x)      (NR_BUILTIN_GPIO + (x))
 
-static void __init snapper9260_map_io(void)
+static void __init snapper9260_init_early(void)
 {
         at91sam9260_initialize(18432000);
 
@@ -178,9 +178,9 @@ static void __init snapper9260_board_init(void)
 }
 
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = snapper9260_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = snapper9260_init_early,
         .init_irq       = snapper9260_init_irq,
         .init_machine   = snapper9260_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index f8902b118960..5e5c85688f5f 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,7 +32,7 @@
 #include "generic.h"
 
 
-void __init stamp9g20_map_io(void)
+void __init stamp9g20_init_early(void)
 {
         /* Initialize processor: 18.432 MHz crystal */
         at91sam9260_initialize(18432000);
@@ -44,9 +44,9 @@ void __init stamp9g20_map_io(void)
         at91_set_serial_console(0);
 }
 
-static void __init stamp9g20evb_map_io(void)
+static void __init stamp9g20evb_init_early(void)
 {
-        stamp9g20_map_io();
+        stamp9g20_init_early();
 
         /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
         at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
@@ -54,9 +54,9 @@ static void __init stamp9g20evb_map_io(void)
                                                 | ATMEL_UART_DCD | ATMEL_UART_RI);
 }
 
-static void __init portuxg20_map_io(void)
+static void __init portuxg20_init_early(void)
 {
-        stamp9g20_map_io();
+        stamp9g20_init_early();
 
         /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
         at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
@@ -298,18 +298,18 @@ static void __init stamp9g20evb_board_init(void)
 
 MACHINE_START(PORTUXG20, "taskit PortuxG20")
         /* Maintainer: taskit GmbH */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = portuxg20_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = portuxg20_init_early,
         .init_irq       = init_irq,
         .init_machine   = portuxg20_board_init,
 MACHINE_END
 
 MACHINE_START(STAMP9G20, "taskit Stamp9G20")
         /* Maintainer: taskit GmbH */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = stamp9g20evb_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = stamp9g20evb_init_early,
         .init_irq       = init_irq,
         .init_machine   = stamp9g20evb_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
index 07784baeae84..0e784e6fedec 100644
--- a/arch/arm/mach-at91/board-usb-a9260.c
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -48,7 +48,7 @@
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 12.000 MHz crystal */
         at91sam9260_initialize(12000000);
@@ -228,9 +228,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(USB_A9260, "CALAO USB_A9260")
         /* Maintainer: calao-systems */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9260_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
index b614508931fd..cf626dd14b2c 100644
--- a/arch/arm/mach-at91/board-usb-a9263.c
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -47,7 +47,7 @@
 #include "generic.h"
 
 
-static void __init ek_map_io(void)
+static void __init ek_init_early(void)
 {
         /* Initialize processor: 12.00 MHz crystal */
         at91sam9263_initialize(12000000);
@@ -244,9 +244,9 @@ static void __init ek_board_init(void)
 
 MACHINE_START(USB_A9263, "CALAO USB_A9263")
         /* Maintainer: calao-systems */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91sam926x_timer,
-        .map_io         = ek_map_io,
+        .map_io         = at91sam9263_map_io,
+        .init_early     = ek_init_early,
         .init_irq       = ek_init_irq,
         .init_machine   = ek_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index e0f0080eb639..c208cc334d7d 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -45,14 +45,18 @@
 #include <mach/board.h>
 #include <mach/gpio.h>
 #include <mach/at91rm9200_mc.h>
+#include <mach/cpu.h>
 
 #include "generic.h"
 
 
-static void __init yl9200_map_io(void)
+static void __init yl9200_init_early(void)
 {
+        /* Set cpu type: PQFP */
+        at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
+
         /* Initialize processor: 18.432 MHz crystal */
-        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        at91rm9200_initialize(18432000);
 
         /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
         at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
@@ -594,9 +598,9 @@ static void __init yl9200_board_init(void)
 
 MACHINE_START(YL9200, "uCdragon YL-9200")
         /* Maintainer: S.Birtles */
-        .boot_params    = AT91_SDRAM_BASE + 0x100,
         .timer          = &at91rm9200_timer,
-        .map_io         = yl9200_map_io,
+        .map_io         = at91rm9200_map_io,
+        .init_early     = yl9200_init_early,
         .init_irq       = yl9200_init_irq,
         .init_machine   = yl9200_board_init,
 MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 9113da6845f1..61873f3aa92d 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -163,7 +163,7 @@ static struct clk udpck = {
         .parent         = &pllb,
         .mode           = pmc_sys_mode,
 };
-static struct clk utmi_clk = {
+struct clk utmi_clk = {
         .name           = "utmi_clk",
         .parent         = &main_clk,
         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
@@ -182,7 +182,7 @@ static struct clk uhpck = {
  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
  */
-static struct clk mck = {
+struct clk mck = {
         .name           = "mck",
         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 };
@@ -215,43 +215,6 @@ static struct clk __init *at91_css_to_clk(unsigned long css)
         return NULL;
 }
 
-/*
- * Associate a particular clock with a function (eg, "uart") and device.
- * The drivers can then request the same 'function' with several different
- * devices and not care about which clock name to use.
- */
-void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
-{
-        struct clk *clk = clk_get(NULL, id);
-
-        if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
-                return;
-
-        clk->function = func;
-        clk->dev = dev;
-}
-
-/* clocks cannot be de-registered no refcounting necessary */
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *clk;
-
-        list_for_each_entry(clk, &clocks, node) {
-                if (strcmp(id, clk->name) == 0)
-                        return clk;
-                if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
-                        return clk;
-        }
-
-        return ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_put);
-
 static void __clk_enable(struct clk *clk)
 {
         if (clk->parent)
@@ -498,32 +461,38 @@ postcore_initcall(at91_clk_debugfs_init);
 /*------------------------------------------------------------------------*/
 
 /* Register a new clock */
+static void __init at91_clk_add(struct clk *clk)
+{
+        list_add_tail(&clk->node, &clocks);
+
+        clk->cl.con_id = clk->name;
+        clk->cl.clk = clk;
+        clkdev_add(&clk->cl);
+}
+
 int __init clk_register(struct clk *clk)
 {
         if (clk_is_peripheral(clk)) {
                 if (!clk->parent)
                         clk->parent = &mck;
                 clk->mode = pmc_periph_mode;
-                list_add_tail(&clk->node, &clocks);
         }
         else if (clk_is_sys(clk)) {
                 clk->parent = &mck;
                 clk->mode = pmc_sys_mode;
-
-                list_add_tail(&clk->node, &clocks);
         }
 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
         else if (clk_is_programmable(clk)) {
                 clk->mode = pmc_sys_mode;
                 init_programmable_clock(clk);
-                list_add_tail(&clk->node, &clocks);
         }
 #endif
 
+        at91_clk_add(clk);
+
         return 0;
 }
 
-
 /*------------------------------------------------------------------------*/
 
 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
@@ -630,7 +599,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
-                   cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
+                   cpu_is_at91sam9g10()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         } else if (cpu_is_at91cap9()) {
@@ -754,19 +723,19 @@ int __init at91_clock_init(unsigned long main_clock)
 
         /* Register the PMC's standard clocks */
         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-                list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
+                at91_clk_add(standard_pmc_clocks[i]);
 
         if (cpu_has_pllb())
-                list_add_tail(&pllb.node, &clocks);
+                at91_clk_add(&pllb);
 
         if (cpu_has_uhp())
-                list_add_tail(&uhpck.node, &clocks);
+                at91_clk_add(&uhpck);
 
         if (cpu_has_udpfs())
-                list_add_tail(&udpck.node, &clocks);
+                at91_clk_add(&udpck);
 
         if (cpu_has_utmi())
-                list_add_tail(&utmi_clk.node, &clocks);
+                at91_clk_add(&utmi_clk);
 
         /* MCK and CPU clock are "always on" */
         clk_enable(&mck);
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index 6cf4b78e175d..c2e63e47dcbe 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -6,6 +6,8 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/clkdev.h>
+
 #define CLK_TYPE_PRIMARY        0x1
 #define CLK_TYPE_PLL            0x2
 #define CLK_TYPE_PROGRAMMABLE   0x4
@@ -16,8 +18,7 @@
 struct clk {
         struct list_head node;
         const char      *name;          /* unique clock name */
-        const char      *function;      /* function of the clock */
-        struct device   *dev;           /* device associated with function */
+        struct clk_lookup cl;
         unsigned long   rate_hz;
         struct clk      *parent;
         u32             pmc_mask;
@@ -29,3 +30,18 @@ struct clk {
 
 
 extern int __init clk_register(struct clk *clk);
+extern struct clk mck;
+extern struct clk utmi_clk;
+
+#define CLKDEV_CON_ID(_id, _clk)                        \
+        {                                               \
+                .con_id = _id,                          \
+                .clk = _clk,                            \
+        }
+
+#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk)       \
+        {                                               \
+                .con_id = _con_id,                      \
+                .dev_id = _dev_id,                      \
+                .clk = _clk,                            \
+        }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0c66deb2db39..8ff3418f3430 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -8,8 +8,21 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/clkdev.h>
+
+ /* Map io */
+extern void __init at91rm9200_map_io(void);
+extern void __init at91sam9260_map_io(void);
+extern void __init at91sam9261_map_io(void);
+extern void __init at91sam9263_map_io(void);
+extern void __init at91sam9rl_map_io(void);
+extern void __init at91sam9g45_map_io(void);
+extern void __init at91x40_map_io(void);
+extern void __init at91cap9_map_io(void);
+
  /* Processors */
-extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
+extern void __init at91rm9200_set_type(int type);
+extern void __init at91rm9200_initialize(unsigned long main_clock);
 extern void __init at91sam9260_initialize(unsigned long main_clock);
 extern void __init at91sam9261_initialize(unsigned long main_clock);
 extern void __init at91sam9263_initialize(unsigned long main_clock);
@@ -17,7 +30,6 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
 extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
-extern void __init at572d940hf_initialize(unsigned long main_clock);
 
  /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -28,7 +40,6 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
-extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
@@ -39,8 +50,19 @@ extern struct sys_timer at91x40_timer;
 
  /* Clocks */
 extern int __init at91_clock_init(unsigned long main_clock);
+/*
+ * function to specify the clock of the default console. As we do not
+ * use the device/driver bus, the dev_name is not intialize. So we need
+ * to link the clock to a specific con_id only "usart"
+ */
+extern void __init at91rm9200_set_console_clock(int id);
+extern void __init at91sam9260_set_console_clock(int id);
+extern void __init at91sam9261_set_console_clock(int id);
+extern void __init at91sam9263_set_console_clock(int id);
+extern void __init at91sam9rl_set_console_clock(int id);
+extern void __init at91sam9g45_set_console_clock(int id);
+extern void __init at91cap9_set_console_clock(int id);
 struct device;
-extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func);
 
  /* Power Management */
 extern void at91_irq_suspend(void);
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
deleted file mode 100644
index be510cfc56be..000000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * include/mach/at572d940hf.h
- *
- * Antonio R. Costa <costa.antonior@gmail.com>
- * Copyright (C) 2008 Atmel
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#ifndef AT572D940HF_H
-#define AT572D940HF_H
-
-/*
- * Peripheral identifiers/interrupts.
- */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
-#define AT572D940HF_ID_PIOA     2       /* Parallel IO Controller A */
-#define AT572D940HF_ID_PIOB     3       /* Parallel IO Controller B */
-#define AT572D940HF_ID_PIOC     4       /* Parallel IO Controller C */
-#define AT572D940HF_ID_EMAC     5       /* MACB ethernet controller */
-#define AT572D940HF_ID_US0      6       /* USART 0 */
-#define AT572D940HF_ID_US1      7       /* USART 1 */
-#define AT572D940HF_ID_US2      8       /* USART 2 */
-#define AT572D940HF_ID_MCI      9       /* Multimedia Card Interface */
-#define AT572D940HF_ID_UDP      10      /* USB Device Port */
-#define AT572D940HF_ID_TWI0     11      /* Two-Wire Interface 0 */
-#define AT572D940HF_ID_SPI0     12      /* Serial Peripheral Interface 0 */
-#define AT572D940HF_ID_SPI1     13      /* Serial Peripheral Interface 1 */
-#define AT572D940HF_ID_SSC0     14      /* Serial Synchronous Controller 0 */
-#define AT572D940HF_ID_SSC1     15      /* Serial Synchronous Controller 1 */
-#define AT572D940HF_ID_SSC2     16      /* Serial Synchronous Controller 2 */
-#define AT572D940HF_ID_TC0      17      /* Timer Counter 0 */
-#define AT572D940HF_ID_TC1      18      /* Timer Counter 1 */
-#define AT572D940HF_ID_TC2      19      /* Timer Counter 2 */
-#define AT572D940HF_ID_UHP      20      /* USB Host port */
-#define AT572D940HF_ID_SSC3     21      /* Serial Synchronous Controller 3 */
-#define AT572D940HF_ID_TWI1     22      /* Two-Wire Interface 1 */
-#define AT572D940HF_ID_CAN0     23      /* CAN Controller 0 */
-#define AT572D940HF_ID_CAN1     24      /* CAN Controller 1 */
-#define AT572D940HF_ID_MHALT    25      /* mAgicV HALT line */
-#define AT572D940HF_ID_MSIRQ0   26      /* mAgicV SIRQ0 line */
-#define AT572D940HF_ID_MEXC     27      /* mAgicV exception line */
-#define AT572D940HF_ID_MEDMA    28      /* mAgicV end of DMA line */
-#define AT572D940HF_ID_IRQ0     29      /* External Interrupt Source (IRQ0) */
-#define AT572D940HF_ID_IRQ1     30      /* External Interrupt Source (IRQ1) */
-#define AT572D940HF_ID_IRQ2     31      /* External Interrupt Source (IRQ2) */
-
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT572D940HF_BASE_TCB    0xfffa0000
-#define AT572D940HF_BASE_TC0    0xfffa0000
-#define AT572D940HF_BASE_TC1    0xfffa0040
-#define AT572D940HF_BASE_TC2    0xfffa0080
-#define AT572D940HF_BASE_UDP    0xfffa4000
-#define AT572D940HF_BASE_MCI    0xfffa8000
-#define AT572D940HF_BASE_TWI0   0xfffac000
-#define AT572D940HF_BASE_US0    0xfffb0000
-#define AT572D940HF_BASE_US1    0xfffb4000
-#define AT572D940HF_BASE_US2    0xfffb8000
-#define AT572D940HF_BASE_SSC0   0xfffbc000
-#define AT572D940HF_BASE_SSC1   0xfffc0000
-#define AT572D940HF_BASE_SSC2   0xfffc4000
-#define AT572D940HF_BASE_SPI0   0xfffc8000
-#define AT572D940HF_BASE_SPI1   0xfffcc000
-#define AT572D940HF_BASE_SSC3   0xfffd0000
-#define AT572D940HF_BASE_TWI1   0xfffd4000
-#define AT572D940HF_BASE_EMAC   0xfffd8000
-#define AT572D940HF_BASE_CAN0   0xfffdc000
-#define AT572D940HF_BASE_CAN1   0xfffe0000
-#define AT91_BASE_SYS           0xffffea00
-
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
-
-#define AT91_USART0     AT572D940HF_ID_US0
-#define AT91_USART1     AT572D940HF_ID_US1
-#define AT91_USART2     AT572D940HF_ID_US2
-
-
-/*
- * Internal Memory.
- */
-#define AT572D940HF_SRAM_BASE   0x00300000      /* Internal SRAM base address */
-#define AT572D940HF_SRAM_SIZE   (48 * SZ_1K)    /* Internal SRAM size (48Kb) */
-
-#define AT572D940HF_ROM_BASE    0x00400000      /* Internal ROM base address */
-#define AT572D940HF_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
-
-#define AT572D940HF_UHP_BASE    0x00500000      /* USB Host controller */
-
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
deleted file mode 100644
index b6751df09488..000000000000
--- a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * include/mach//at572d940hf_matrix.h
- *
- * Antonio R. Costa <costa.antonior@gmail.com>
- * Copyright (C) 2008 Atmel
- *
- * Copyright (C) 2005 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef AT572D940HF_MATRIX_H
-#define AT572D940HF_MATRIX_H
-
-#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
-
-#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
-#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
-#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
-#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
-#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
-#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
-
-#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
-#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
-#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
-#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
-#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
-#define         AT91_MATRIX_FIXED_DEFMSTR       (0x7  << 18)    /* Fixed Index of Default Master */
-#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
-#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
-#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-
-#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
-
-#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
-#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
-#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
-#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
-#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
-#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
-#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
-
-#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
-#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-
-#define AT91_MATRIX_SFR0        (AT91_MATRIX + 0x110)   /* Special Function Register 0 */
-#define AT91_MATRIX_SFR1        (AT91_MATRIX + 0x114)   /* Special Function Register 1 */
-#define AT91_MATRIX_SFR2        (AT91_MATRIX + 0x118)   /* Special Function Register 2 */
-#define AT91_MATRIX_SFR3        (AT91_MATRIX + 0x11C)   /* Special Function Register 3 */
-#define AT91_MATRIX_SFR4        (AT91_MATRIX + 0x120)   /* Special Function Register 4 */
-#define AT91_MATRIX_SFR5        (AT91_MATRIX + 0x124)   /* Special Function Register 5 */
-#define AT91_MATRIX_SFR6        (AT91_MATRIX + 0x128)   /* Special Function Register 6 */
-#define AT91_MATRIX_SFR7        (AT91_MATRIX + 0x12C)   /* Special Function Register 7 */
-#define AT91_MATRIX_SFR8        (AT91_MATRIX + 0x130)   /* Special Function Register 8 */
-#define AT91_MATRIX_SFR9        (AT91_MATRIX + 0x134)   /* Special Function Register 9 */
-#define AT91_MATRIX_SFR10       (AT91_MATRIX + 0x138)   /* Special Function Register 10 */
-#define AT91_MATRIX_SFR11       (AT91_MATRIX + 0x13C)   /* Special Function Register 11 */
-#define AT91_MATRIX_SFR12       (AT91_MATRIX + 0x140)   /* Special Function Register 12 */
-#define AT91_MATRIX_SFR13       (AT91_MATRIX + 0x144)   /* Special Function Register 13 */
-#define AT91_MATRIX_SFR14       (AT91_MATRIX + 0x148)   /* Special Function Register 14 */
-#define AT91_MATRIX_SFR15       (AT91_MATRIX + 0x14C)   /* Special Function Register 15 */
-
-
-/*
- * The following registers / bits are not defined in the Datasheet (Revision A)
- */
-
-#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x100)   /* TCM Configuration Register */
-#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
-#define                 AT91_MATRIX_ITCM_0              (0 << 0)
-#define                 AT91_MATRIX_ITCM_16             (5 << 0)
-#define                 AT91_MATRIX_ITCM_32             (6 << 0)
-#define                 AT91_MATRIX_ITCM_64             (7 << 0)
-#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
-#define                 AT91_MATRIX_DTCM_0              (0 << 4)
-#define                 AT91_MATRIX_DTCM_16             (5 << 4)
-#define                 AT91_MATRIX_DTCM_32             (6 << 4)
-#define                 AT91_MATRIX_DTCM_64             (7 << 4)
-
-#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
-#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
-#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
-#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
-#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
-#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
-#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
-#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
-#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
-#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
-#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
-#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
-#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 9c6af9737485..665993849a7b 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -20,8 +20,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
 #define AT91CAP9_ID_PIOABCD     2       /* Parallel IO Controller A, B, C and D */
 #define AT91CAP9_ID_MPB0        3       /* MP Block Peripheral 0 */
 #define AT91CAP9_ID_MPB1        4       /* MP Block Peripheral 1 */
@@ -123,6 +121,4 @@
 #define AT91CAP9_UDPHS_FIFO     0x00600000      /* USB High Speed Device Port */
 #define AT91CAP9_UHP_BASE       0x00700000      /* USB Host controller */
 
-#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 78983155a074..99e0f8d02d7b 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -19,8 +19,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripheral */
 #define AT91RM9200_ID_PIOA      2       /* Parallel IO Controller A */
 #define AT91RM9200_ID_PIOB      3       /* Parallel IO Controller B */
 #define AT91RM9200_ID_PIOC      4       /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 4e79036d3b80..8b6bf835cd73 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -20,8 +20,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
 #define AT91SAM9260_ID_PIOA     2       /* Parallel IO Controller A */
 #define AT91SAM9260_ID_PIOB     3       /* Parallel IO Controller B */
 #define AT91SAM9260_ID_PIOC     4       /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 2b5618518129..eafbddaf523c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -18,8 +18,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
 #define AT91SAM9261_ID_PIOA     2       /* Parallel IO Controller A */
 #define AT91SAM9261_ID_PIOB     3       /* Parallel IO Controller B */
 #define AT91SAM9261_ID_PIOC     4       /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 2091f1e42d43..e2d348213a7b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -18,8 +18,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Peripherals */
 #define AT91SAM9263_ID_PIOA     2       /* Parallel IO Controller A */
 #define AT91SAM9263_ID_PIOB     3       /* Parallel IO Controller B */
 #define AT91SAM9263_ID_PIOCDE   4       /* Parallel IO Controller C, D and E */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index a526869aee37..659304aa73d9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -18,8 +18,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Controller Interrupt */
 #define AT91SAM9G45_ID_PIOA     2       /* Parallel I/O Controller A */
 #define AT91SAM9G45_ID_PIOB     3       /* Parallel I/O Controller B */
 #define AT91SAM9G45_ID_PIOC     4       /* Parallel I/O Controller C */
@@ -131,8 +129,6 @@
 #define AT91SAM9G45_EHCI_BASE   0x00800000      /* USB Host controller (EHCI) */
 #define AT91SAM9G45_VDEC_BASE   0x00900000      /* Video Decoder Controller */
 
-#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
-
 #define CONSISTENT_DMA_SIZE     SZ_4M
 
 /*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 87ba8517ad98..41dbbe61055c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -17,8 +17,6 @@
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS             1       /* System Controller */
 #define AT91SAM9RL_ID_PIOA      2       /* Parallel IO Controller A */
 #define AT91SAM9RL_ID_PIOB      3       /* Parallel IO Controller B */
 #define AT91SAM9RL_ID_PIOC      4       /* Parallel IO Controller C */
diff --git a/arch/arm/mach-at91/include/mach/at91x40.h b/arch/arm/mach-at91/include/mach/at91x40.h
index 063ac44a0204..a152ff87e688 100644
--- a/arch/arm/mach-at91/include/mach/at91x40.h
+++ b/arch/arm/mach-at91/include/mach/at91x40.h
@@ -15,8 +15,6 @@
 /*
  *      IRQ list.
  */
-#define AT91_ID_FIQ             0       /* FIQ */
-#define AT91_ID_SYS             1       /* System Peripheral */
 #define AT91X40_ID_USART0       2       /* USART port 0 */
 #define AT91X40_ID_USART1       3       /* USART port 1 */
 #define AT91X40_ID_TC0          4       /* Timer/Counter 0 */
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 2b499eb343a1..ed544a0d5a1d 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -90,7 +90,7 @@ struct at91_eth_data {
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 #define eth_platform_data       at91_eth_data
 #endif
 
@@ -140,6 +140,7 @@ extern void __init at91_set_serial_console(unsigned portnr);
 extern struct platform_device *atmel_default_console_device;
 
 struct atmel_uart_data {
+        int                     num;            /* port num */
         short                   use_dma_tx;     /* use transmit DMA? */
         short                   use_dma_rx;     /* use receive DMA? */
         void __iomem            *regs;          /* virt. base address, if any */
@@ -203,9 +204,6 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
- /* AT572D940HF DSP */
-extern void __init at91_add_device_mAgic(void);
-
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
 
diff --git a/arch/arm/mach-at91/include/mach/clkdev.h b/arch/arm/mach-at91/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index 0700f2125305..df966c2bc2d4 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -34,8 +34,6 @@
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
 
-#define ARCH_ID_AT572D940HF     0x0e0303e0
-
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -90,9 +88,16 @@ static inline unsigned long at91cap9_rev_identify(void)
 #endif
 
 #ifdef CONFIG_ARCH_AT91RM9200
+extern int rm9200_type;
+#define ARCH_REVISON_9200_BGA   (0 << 0)
+#define ARCH_REVISON_9200_PQFP  (1 << 0)
 #define cpu_is_at91rm9200()     (at91_cpu_identify() == ARCH_ID_AT91RM9200)
+#define cpu_is_at91rm9200_bga() (!cpu_is_at91rm9200_pqfp())
+#define cpu_is_at91rm9200_pqfp() (cpu_is_at91rm9200() && rm9200_type & ARCH_REVISON_9200_PQFP)
 #else
 #define cpu_is_at91rm9200()     (0)
+#define cpu_is_at91rm9200_bga() (0)
+#define cpu_is_at91rm9200_pqfp() (0)
 #endif
 
 #ifdef CONFIG_ARCH_AT91SAM9260
@@ -181,12 +186,6 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91cap9_revC()  (0)
 #endif
 
-#ifdef CONFIG_ARCH_AT572D940HF
-#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
-#else
-#define cpu_is_at572d940hf() (0)
-#endif
-
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 3d64a75e3ed5..1008b9fb5074 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,13 +32,17 @@
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
-#elif defined(CONFIG_ARCH_AT572D940HF)
-#include <mach/at572d940hf.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
 
 
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+
 #ifdef CONFIG_MMU
 /*
  * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
@@ -82,13 +86,6 @@
 #define AT91_CHIPSELECT_6       0x70000000
 #define AT91_CHIPSELECT_7       0x80000000
 
-/* SDRAM */
-#ifdef CONFIG_DRAM_BASE
-#define AT91_SDRAM_BASE         CONFIG_DRAM_BASE
-#else
-#define AT91_SDRAM_BASE         AT91_CHIPSELECT_1
-#endif
-
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
 
diff --git a/arch/arm/mach-at91/include/mach/memory.h b/arch/arm/mach-at91/include/mach/memory.h
index c2cfe5040642..401c207f2f39 100644
--- a/arch/arm/mach-at91/include/mach/memory.h
+++ b/arch/arm/mach-at91/include/mach/memory.h
@@ -23,6 +23,4 @@
 
 #include <mach/hardware.h>
 
-#define PLAT_PHYS_OFFSET        (AT91_SDRAM_BASE)
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/stamp9g20.h b/arch/arm/mach-at91/include/mach/stamp9g20.h
index 6120f9c46d59..f62c0abca4b4 100644
--- a/arch/arm/mach-at91/include/mach/stamp9g20.h
+++ b/arch/arm/mach-at91/include/mach/stamp9g20.h
@@ -1,7 +1,7 @@
 #ifndef __MACH_STAMP9G20_H
 #define __MACH_STAMP9G20_H
 
-void stamp9g20_map_io(void);
+void stamp9g20_init_early(void);
 void stamp9g20_board_init(void);
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/system_rev.h b/arch/arm/mach-at91/include/mach/system_rev.h
new file mode 100644
index 000000000000..b855ee75f72c
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/system_rev.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+ *
+ * Under GPLv2 only
+ */
+
+#ifndef __ARCH_SYSTEM_REV_H__
+#define __ARCH_SYSTEM_REV_H__
+
+/*
+ * board revision encoding
+ * mach specific
+ * the 16-31 bit are reserved for at91 generic information
+ *
+ * bit 31:
+ *      0 => nand 16 bit
+ *      1 => nand 8 bit
+ */
+#define BOARD_HAVE_NAND_8BIT    (1 << 31)
+static int inline board_have_nand_8bit(void)
+{
+        return system_rev & BOARD_HAVE_NAND_8BIT;
+}
+
+#endif /* __ARCH_SYSTEM_REV_H__ */
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 05a6e8af80c4..31ac2d97f14c 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,11 +82,6 @@
 #define AT91X40_MASTER_CLOCK    40000000
 #define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 
-#elif defined(CONFIG_ARCH_AT572D940HF)
-
-#define AT572D940HF_MASTER_CLOCK        80000000
-#define CLOCK_TICK_RATE         (AT572D940HF_MASTER_CLOCK/16)
-
 #endif
 
 #endif
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index b95b9196deed..133aac405853 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1055,7 +1055,7 @@ int da850_register_pm(struct platform_device *pdev)
         if (!pdata->cpupll_reg_base)
                 return -ENOMEM;
 
-        pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
+        pdata->ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K);
         if (!pdata->ddrpll_reg_base) {
                 ret = -ENOMEM;
                 goto no_ddrpll_mem;
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 58a02dc7b15a..4e66881c7aee 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,23 +24,25 @@
 #include "clock.h"
 
 #define DA8XX_TPCC_BASE                 0x01c00000
-#define DA850_MMCSD1_BASE               0x01e1b000
-#define DA850_TPCC1_BASE                0x01e30000
 #define DA8XX_TPTC0_BASE                0x01c08000
 #define DA8XX_TPTC1_BASE                0x01c08400
-#define DA850_TPTC2_BASE                0x01e38000
 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
 #define DA8XX_I2C0_BASE                 0x01c22000
-#define DA8XX_RTC_BASE                  0x01C23000
+#define DA8XX_RTC_BASE                  0x01c23000
+#define DA8XX_MMCSD0_BASE               0x01c40000
+#define DA8XX_SPI0_BASE                 0x01c41000
+#define DA830_SPI1_BASE                 0x01e12000
+#define DA8XX_LCD_CNTRL_BASE            0x01e13000
+#define DA850_MMCSD1_BASE               0x01e1b000
 #define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
 #define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
 #define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
 #define DA8XX_EMAC_MDIO_BASE            0x01e24000
-#define DA8XX_GPIO_BASE                 0x01e26000
 #define DA8XX_I2C1_BASE                 0x01e28000
-#define DA8XX_SPI0_BASE                 0x01c41000
-#define DA830_SPI1_BASE                 0x01e12000
+#define DA850_TPCC1_BASE                0x01e30000
+#define DA850_TPTC2_BASE                0x01e38000
 #define DA850_SPI1_BASE                 0x01f0e000
+#define DA8XX_DDR2_CTL_BASE             0xb0000000
 
 #define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
 #define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
diff --git a/arch/arm/mach-davinci/devices.c b/arch/arm/mach-davinci/devices.c
index 22ebc64bc9d9..8f4f736aa267 100644
--- a/arch/arm/mach-davinci/devices.c
+++ b/arch/arm/mach-davinci/devices.c
@@ -33,6 +33,9 @@
 #define DM365_MMCSD0_BASE            0x01D11000
 #define DM365_MMCSD1_BASE            0x01D00000
 
+/* System control register offsets */
+#define DM64XX_VDD3P3V_PWDN     0x48
+
 static struct resource i2c_resources[] = {
         {
                 .start          = DAVINCI_I2C_BASE,
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index e4fc1af8500e..ad64da713fc8 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -64,13 +64,9 @@ extern unsigned int da850_max_speed;
 #define DA8XX_TIMER64P1_BASE    0x01c21000
 #define DA8XX_GPIO_BASE         0x01e26000
 #define DA8XX_PSC1_BASE         0x01e27000
-#define DA8XX_LCD_CNTRL_BASE    0x01e13000
-#define DA8XX_PLL1_BASE         0x01e1a000
-#define DA8XX_MMCSD0_BASE       0x01c40000
 #define DA8XX_AEMIF_CS2_BASE    0x60000000
 #define DA8XX_AEMIF_CS3_BASE    0x62000000
 #define DA8XX_AEMIF_CTL_BASE    0x68000000
-#define DA8XX_DDR2_CTL_BASE     0xb0000000
 #define DA8XX_ARM_RAM_BASE      0xffff0000
 
 void __init da830_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index c45ba1f62a11..414e0b93e741 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -21,9 +21,6 @@
  */
 #define DAVINCI_SYSTEM_MODULE_BASE        0x01C40000
 
-/* System control register offsets */
-#define DM64XX_VDD3P3V_PWDN     0x48
-
 /*
  * I/O mapping
  */
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 805196207ce8..b92c1e557145 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -169,9 +169,11 @@ config MACH_NURI
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
         select S3C_DEV_I2C1
+        select S3C_DEV_I2C3
         select S3C_DEV_I2C5
         select S5P_DEV_USB_EHCI
         select EXYNOS4_SETUP_I2C1
+        select EXYNOS4_SETUP_I2C3
         select EXYNOS4_SETUP_I2C5
         select EXYNOS4_SETUP_SDHCI
         select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 777897551e42..a9bb94fabaa7 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,9 +13,10 @@ obj-				:=
 # Core support for EXYNOS4 system
 
 obj-$(CONFIG_CPU_EXYNOS4210)    += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o gpiolib.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210)    += setup-i2c0.o irq-eint.o dma.o
 obj-$(CONFIG_PM)                += pm.o sleep.o
 obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
+obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
 
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 
diff --git a/arch/arm/mach-exynos4/cpuidle.c b/arch/arm/mach-exynos4/cpuidle.c
new file mode 100644
index 000000000000..bf7e96f2793a
--- /dev/null
+++ b/arch/arm/mach-exynos4/cpuidle.c
@@ -0,0 +1,86 @@
+/* linux/arch/arm/mach-exynos4/cpuidle.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/cpuidle.h>
+#include <linux/io.h>
+
+#include <asm/proc-fns.h>
+
+static int exynos4_enter_idle(struct cpuidle_device *dev,
+                              struct cpuidle_state *state);
+
+static struct cpuidle_state exynos4_cpuidle_set[] = {
+        [0] = {
+                .enter                  = exynos4_enter_idle,
+                .exit_latency           = 1,
+                .target_residency       = 100000,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "IDLE",
+                .desc                   = "ARM clock gating(WFI)",
+        },
+};
+
+static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
+
+static struct cpuidle_driver exynos4_idle_driver = {
+        .name           = "exynos4_idle",
+        .owner          = THIS_MODULE,
+};
+
+static int exynos4_enter_idle(struct cpuidle_device *dev,
+                              struct cpuidle_state *state)
+{
+        struct timeval before, after;
+        int idle_time;
+
+        local_irq_disable();
+        do_gettimeofday(&before);
+
+        cpu_do_idle();
+
+        do_gettimeofday(&after);
+        local_irq_enable();
+        idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
+                    (after.tv_usec - before.tv_usec);
+
+        return idle_time;
+}
+
+static int __init exynos4_init_cpuidle(void)
+{
+        int i, max_cpuidle_state, cpu_id;
+        struct cpuidle_device *device;
+
+        cpuidle_register_driver(&exynos4_idle_driver);
+
+        for_each_cpu(cpu_id, cpu_online_mask) {
+                device = &per_cpu(exynos4_cpuidle_device, cpu_id);
+                device->cpu = cpu_id;
+
+                device->state_count = (sizeof(exynos4_cpuidle_set) /
+                                               sizeof(struct cpuidle_state));
+
+                max_cpuidle_state = device->state_count;
+
+                for (i = 0; i < max_cpuidle_state; i++) {
+                        memcpy(&device->states[i], &exynos4_cpuidle_set[i],
+                                        sizeof(struct cpuidle_state));
+                }
+
+                if (cpuidle_register_device(device)) {
+                        printk(KERN_ERR "CPUidle register device failed\n,");
+                        return -EIO;
+                }
+        }
+        return 0;
+}
+device_initcall(exynos4_init_cpuidle);
diff --git a/arch/arm/mach-exynos4/gpiolib.c b/arch/arm/mach-exynos4/gpiolib.c
deleted file mode 100644
index d54ca6adb660..000000000000
--- a/arch/arm/mach-exynos4/gpiolib.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/* linux/arch/arm/mach-exynos4/gpiolib.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * EXYNOS4 - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-
-static struct s3c_gpio_cfg gpio_cfg = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_noint = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-/*
- * Following are the gpio banks in v310.
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure gpio_cfg in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of s3c_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS4_GPA0(0),
-                        .ngpio  = EXYNOS4_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPA1(0),
-                        .ngpio  = EXYNOS4_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPB(0),
-                        .ngpio  = EXYNOS4_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPC0(0),
-                        .ngpio  = EXYNOS4_GPIO_C0_NR,
-                        .label  = "GPC0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPC1(0),
-                        .ngpio  = EXYNOS4_GPIO_C1_NR,
-                        .label  = "GPC1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPD0(0),
-                        .ngpio  = EXYNOS4_GPIO_D0_NR,
-                        .label  = "GPD0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPD1(0),
-                        .ngpio  = EXYNOS4_GPIO_D1_NR,
-                        .label  = "GPD1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE0(0),
-                        .ngpio  = EXYNOS4_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE1(0),
-                        .ngpio  = EXYNOS4_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE2(0),
-                        .ngpio  = EXYNOS4_GPIO_E2_NR,
-                        .label  = "GPE2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE3(0),
-                        .ngpio  = EXYNOS4_GPIO_E3_NR,
-                        .label  = "GPE3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPE4(0),
-                        .ngpio  = EXYNOS4_GPIO_E4_NR,
-                        .label  = "GPE4",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF0(0),
-                        .ngpio  = EXYNOS4_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF1(0),
-                        .ngpio  = EXYNOS4_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF2(0),
-                        .ngpio  = EXYNOS4_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPF3(0),
-                        .ngpio  = EXYNOS4_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        },
-};
-
-static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS4_GPJ0(0),
-                        .ngpio  = EXYNOS4_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPJ1(0),
-                        .ngpio  = EXYNOS4_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK0(0),
-                        .ngpio  = EXYNOS4_GPIO_K0_NR,
-                        .label  = "GPK0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK1(0),
-                        .ngpio  = EXYNOS4_GPIO_K1_NR,
-                        .label  = "GPK1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK2(0),
-                        .ngpio  = EXYNOS4_GPIO_K2_NR,
-                        .label  = "GPK2",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPK3(0),
-                        .ngpio  = EXYNOS4_GPIO_K3_NR,
-                        .label  = "GPK3",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPL0(0),
-                        .ngpio  = EXYNOS4_GPIO_L0_NR,
-                        .label  = "GPL0",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPL1(0),
-                        .ngpio  = EXYNOS4_GPIO_L1_NR,
-                        .label  = "GPL1",
-                },
-        }, {
-                .chip   = {
-                        .base   = EXYNOS4_GPL2(0),
-                        .ngpio  = EXYNOS4_GPIO_L2_NR,
-                        .label  = "GPL2",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY0(0),
-                        .ngpio  = EXYNOS4_GPIO_Y0_NR,
-                        .label  = "GPY0",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY1(0),
-                        .ngpio  = EXYNOS4_GPIO_Y1_NR,
-                        .label  = "GPY1",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY2(0),
-                        .ngpio  = EXYNOS4_GPIO_Y2_NR,
-                        .label  = "GPY2",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY3(0),
-                        .ngpio  = EXYNOS4_GPIO_Y3_NR,
-                        .label  = "GPY3",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY4(0),
-                        .ngpio  = EXYNOS4_GPIO_Y4_NR,
-                        .label  = "GPY4",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY5(0),
-                        .ngpio  = EXYNOS4_GPIO_Y5_NR,
-                        .label  = "GPY5",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = EXYNOS4_GPY6(0),
-                        .ngpio  = EXYNOS4_GPIO_Y6_NR,
-                        .label  = "GPY6",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC00),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = EXYNOS4_GPX0(0),
-                        .ngpio  = EXYNOS4_GPIO_X0_NR,
-                        .label  = "GPX0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC20),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = EXYNOS4_GPX1(0),
-                        .ngpio  = EXYNOS4_GPIO_X1_NR,
-                        .label  = "GPX1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC40),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = EXYNOS4_GPX2(0),
-                        .ngpio  = EXYNOS4_GPIO_X2_NR,
-                        .label  = "GPX2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO2 + 0xC60),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = EXYNOS4_GPX3(0),
-                        .ngpio  = EXYNOS4_GPIO_X3_NR,
-                        .label  = "GPX3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-};
-
-static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
-        {
-                .chip   = {
-                        .base   = EXYNOS4_GPZ(0),
-                        .ngpio  = EXYNOS4_GPIO_Z_NR,
-                        .label  = "GPZ",
-                },
-        },
-};
-
-static __init int exynos4_gpiolib_init(void)
-{
-        struct s3c_gpio_chip *chip;
-        int i;
-        int group = 0;
-        int nr_chips;
-
-        /* GPIO part 1 */
-
-        chip = exynos4_gpio_part1_4bit;
-        nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL) {
-                        chip->config = &gpio_cfg;
-                        /* Assign the GPIO interrupt group */
-                        chip->group = group++;
-                }
-                if (chip->base == NULL)
-                        chip->base = S5P_VA_GPIO1 + (i) * 0x20;
-        }
-
-        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
-
-        /* GPIO part 2 */
-
-        chip = exynos4_gpio_part2_4bit;
-        nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL) {
-                        chip->config = &gpio_cfg;
-                        /* Assign the GPIO interrupt group */
-                        chip->group = group++;
-                }
-                if (chip->base == NULL)
-                        chip->base = S5P_VA_GPIO2 + (i) * 0x20;
-        }
-
-        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
-
-        /* GPIO part 3 */
-
-        chip = exynos4_gpio_part3_4bit;
-        nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL) {
-                        chip->config = &gpio_cfg;
-                        /* Assign the GPIO interrupt group */
-                        chip->group = group++;
-                }
-                if (chip->base == NULL)
-                        chip->base = S5P_VA_GPIO3 + (i) * 0x20;
-        }
-
-        samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
-        s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
-        s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
-
-        return 0;
-}
-core_initcall(exynos4_gpiolib_init);
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index bb5d12f43af8..642702bb5b12 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -12,6 +12,7 @@
 #include <linux/serial_core.h>
 #include <linux/input.h>
 #include <linux/i2c.h>
+#include <linux/i2c/atmel_mxt_ts.h>
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
 #include <linux/regulator/machine.h>
@@ -32,6 +33,8 @@
 #include <plat/sdhci.h>
 #include <plat/ehci.h>
 #include <plat/clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/iic.h>
 
 #include <mach/map.h>
 
@@ -259,6 +262,88 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
         /* Gyro, To be updated */
 };
 
+/* TSP */
+static u8 mxt_init_vals[] = {
+        /* MXT_GEN_COMMAND(6) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        /* MXT_GEN_POWER(7) */
+        0x20, 0xff, 0x32,
+        /* MXT_GEN_ACQUIRE(8) */
+        0x0a, 0x00, 0x05, 0x00, 0x00, 0x00, 0x09, 0x23,
+        /* MXT_TOUCH_MULTI(9) */
+        0x00, 0x00, 0x00, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00,
+        0x00, 0x01, 0x01, 0x0e, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00,
+        /* MXT_TOUCH_KEYARRAY(15) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00,
+        0x00,
+        /* MXT_SPT_GPIOPWM(19) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        /* MXT_PROCI_GRIPFACE(20) */
+        0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x28, 0x04,
+        0x0f, 0x0a,
+        /* MXT_PROCG_NOISE(22) */
+        0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x23, 0x00,
+        0x00, 0x05, 0x0f, 0x19, 0x23, 0x2d, 0x03,
+        /* MXT_TOUCH_PROXIMITY(23) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00,
+        /* MXT_PROCI_ONETOUCH(24) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        /* MXT_SPT_SELFTEST(25) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        0x00, 0x00, 0x00, 0x00,
+        /* MXT_PROCI_TWOTOUCH(27) */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+        /* MXT_SPT_CTECONFIG(28) */
+        0x00, 0x00, 0x02, 0x08, 0x10, 0x00,
+};
+
+static struct mxt_platform_data mxt_platform_data = {
+        .config                 = mxt_init_vals,
+        .config_length          = ARRAY_SIZE(mxt_init_vals),
+
+        .x_line                 = 18,
+        .y_line                 = 11,
+        .x_size                 = 1024,
+        .y_size                 = 600,
+        .blen                   = 0x1,
+        .threshold              = 0x28,
+        .voltage                = 2800000,              /* 2.8V */
+        .orient                 = MXT_DIAGONAL_COUNTER,
+        .irqflags               = IRQF_TRIGGER_FALLING,
+};
+
+static struct s3c2410_platform_i2c i2c3_data __initdata = {
+        .flags          = 0,
+        .bus_num        = 3,
+        .slave_addr     = 0x10,
+        .frequency      = 400 * 1000,
+        .sda_delay      = 100,
+};
+
+static struct i2c_board_info i2c3_devs[] __initdata = {
+        {
+                I2C_BOARD_INFO("atmel_mxt_ts", 0x4a),
+                .platform_data  = &mxt_platform_data,
+                .irq            = IRQ_EINT(4),
+        },
+};
+
+static void __init nuri_tsp_init(void)
+{
+        int gpio;
+
+        /* TOUCH_INT: XEINT_4 */
+        gpio = EXYNOS4_GPX0(4);
+        gpio_request(gpio, "TOUCH_INT");
+        s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+        s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+}
+
 /* GPIO I2C 5 (PMIC) */
 static struct i2c_board_info i2c5_devs[] __initdata = {
         /* max8997, To be updated */
@@ -283,6 +368,7 @@ static struct platform_device *nuri_devices[] __initdata = {
         &s3c_device_wdt,
         &s3c_device_timer[0],
         &s5p_device_ehci,
+        &s3c_device_i2c3,
 
         /* NURI Devices */
         &nuri_gpio_keys,
@@ -300,8 +386,11 @@ static void __init nuri_map_io(void)
 static void __init nuri_machine_init(void)
 {
         nuri_sdhci_init();
+        nuri_tsp_init();
 
         i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+        s3c_i2c3_set_platdata(&i2c3_data);
+        i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
         i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
 
         nuri_ehci_init();
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index af7b68a6b258..88cc422ee444 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -84,7 +84,6 @@ static struct sys_timer wbd111_timer = {
         .init   = gemini_timer_init,
 };
 
-#ifdef CONFIG_MTD_PARTITIONS
 static struct mtd_partition wbd111_partitions[] = {
         {
                 .name           = "RedBoot",
@@ -116,11 +115,7 @@ static struct mtd_partition wbd111_partitions[] = {
                 .mask_flags     = MTD_WRITEABLE,
         }
 };
-#define wbd111_num_partitions   ARRAY_SIZE(wbd111_partitions)
-#else
-#define wbd111_partitions       NULL
-#define wbd111_num_partitions   0
-#endif /* CONFIG_MTD_PARTITIONS */
+#define wbd111_num_partitions  ARRAY_SIZE(wbd111_partitions)
 
 static void __init wbd111_init(void)
 {
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index 99e5bbecf923..3a220347bc88 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -84,7 +84,6 @@ static struct sys_timer wbd222_timer = {
         .init   = gemini_timer_init,
 };
 
-#ifdef CONFIG_MTD_PARTITIONS
 static struct mtd_partition wbd222_partitions[] = {
         {
                 .name           = "RedBoot",
@@ -116,11 +115,7 @@ static struct mtd_partition wbd222_partitions[] = {
                 .mask_flags     = MTD_WRITEABLE,
         }
 };
-#define wbd222_num_partitions   ARRAY_SIZE(wbd222_partitions)
-#else
-#define wbd222_partitions       NULL
-#define wbd222_num_partitions   0
-#endif /* CONFIG_MTD_PARTITIONS */
+#define wbd222_num_partitions  ARRAY_SIZE(wbd222_partitions)
 
 static void __init wbd222_init(void)
 {
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 000000000000..292d55ed2113
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF0000029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+        u32 ch_control;  /* 0x40 Time Synchronization Channel Control */
+        u32 ch_event;    /* 0x44 Time Synchronization Channel Event */
+        u32 tx_snap_lo;  /* 0x48 Transmit Snapshot Low Register */
+        u32 tx_snap_hi;  /* 0x4C Transmit Snapshot High Register */
+        u32 rx_snap_lo;  /* 0x50 Receive Snapshot Low Register */
+        u32 rx_snap_hi;  /* 0x54 Receive Snapshot High Register */
+        u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+        u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+        u32 control;     /* 0x00 Time Sync Control Register */
+        u32 event;       /* 0x04 Time Sync Event Register */
+        u32 addend;      /* 0x08 Time Sync Addend Register */
+        u32 accum;       /* 0x0C Time Sync Accumulator Register */
+        u32 test;        /* 0x10 Time Sync Test Register */
+        u32 unused;      /* 0x14 */
+        u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+        u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+        u32 systime_lo;  /* 0x20 SystemTime_Low Register */
+        u32 systime_hi;  /* 0x24 SystemTime_High Register */
+        u32 trgt_lo;     /* 0x28 TargetTime_Low Register */
+        u32 trgt_hi;     /* 0x2C TargetTime_High Register */
+        u32 asms_lo;     /* 0x30 Auxiliary Slave Mode Snapshot Low  */
+        u32 asms_hi;     /* 0x34 Auxiliary Slave Mode Snapshot High */
+        u32 amms_lo;     /* 0x38 Auxiliary Master Mode Snapshot Low */
+        u32 amms_hi;     /* 0x3C Auxiliary Master Mode Snapshot High */
+
+        struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND  (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE   (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 140783386785..dca4f7f9f4f7 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -60,7 +60,6 @@ static struct platform_device ixdp425_flash = {
 #if defined(CONFIG_MTD_NAND_PLATFORM) || \
     defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 
-#ifdef CONFIG_MTD_PARTITIONS
 const char *part_probes[] = { "cmdlinepart", NULL };
 
 static struct mtd_partition ixdp425_partitions[] = {
@@ -74,7 +73,6 @@ static struct mtd_partition ixdp425_partitions[] = {
                 .size   = MTDPART_SIZ_FULL
         },
 };
-#endif
 
 static void
 ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
@@ -103,11 +101,9 @@ static struct platform_nand_data ixdp425_flash_nand_data = {
                 .nr_chips               = 1,
                 .chip_delay             = 30,
                 .options                = NAND_NO_AUTOINCR,
-#ifdef CONFIG_MTD_PARTITIONS
                 .part_probe_types       = part_probes,
                 .partitions             = ixdp425_partitions,
                 .nr_partitions          = ARRAY_SIZE(ixdp425_partitions),
-#endif
         },
         .ctrl = {
                 .cmd_ctrl               = ixdp425_flash_nand_cmd_ctrl
diff --git a/arch/arm/mach-netx/fb.c b/arch/arm/mach-netx/fb.c
index 5b84bcd30271..b9913234bbf6 100644
--- a/arch/arm/mach-netx/fb.c
+++ b/arch/arm/mach-netx/fb.c
@@ -103,7 +103,6 @@ static struct amba_device fb_device = {
                 .flags  = IORESOURCE_MEM,
         },
         .irq            = { NETX_IRQ_LCD, NO_IRQ },
-        .periphid       = 0x10112400,
 };
 
 int netx_fb_init(struct clcd_board *board, struct clcd_panel *panel)
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 71f3ea623974..3c5e0f522e9c 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -6,7 +6,6 @@ config MACH_NOMADIK_8815NHK
         bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
         select NOMADIK_8815
         select HAS_MTU
-        select NOMADIK_GPIO
 
 endmenu
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b997a35830fc..19d5891c48e3 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -288,6 +288,7 @@ config MACH_IGEP0030
         depends on ARCH_OMAP3
         default y
         select OMAP_PACKAGE_CBB
+        select MACH_IGEP0020
 
 config MACH_SBC3530
         bool "OMAP3 SBC STALKER board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 66dfbccacd25..b14807794401 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -229,8 +229,6 @@ obj-$(CONFIG_MACH_CM_T35)		+= board-cm-t35.o \
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o \
                                            hsmmc.o
-obj-$(CONFIG_MACH_IGEP0030)             += board-igep0030.o \
-                                           hsmmc.o
 obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o \
@@ -270,3 +268,5 @@ obj-$(CONFIG_ARCH_OMAP4)		+= hwspinlock.o
 
 disp-$(CONFIG_OMAP2_DSS)                := display.o
 obj-y                                   += $(disp-m) $(disp-y)
+
+obj-y                                   += common-board-devices.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 1fa6bb896f41..d54969be0a54 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -41,6 +41,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define SDP2430_CS0_BASE        0x04000000
 #define SECONDARY_LCD_GPIO              147
@@ -180,15 +181,6 @@ static struct twl4030_platform_data sdp2430_twldata = {
         .vmmc1          = &sdp2430_vmmc1,
 };
 
-static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_24XX_SYS_NIRQ,
-                .platform_data = &sdp2430_twldata,
-        },
-};
-
 static struct i2c_board_info __initdata sdp2430_i2c1_boardinfo[] = {
         {
                 I2C_BOARD_INFO("isp1301_omap", 0x2D),
@@ -201,8 +193,7 @@ static int __init omap2430_i2c_init(void)
 {
         omap_register_i2c_bus(1, 100, sdp2430_i2c1_boardinfo,
                         ARRAY_SIZE(sdp2430_i2c1_boardinfo));
-        omap_register_i2c_bus(2, 2600, sdp2430_i2c_boardinfo,
-                        ARRAY_SIZE(sdp2430_i2c_boardinfo));
+        omap2_pmic_init("twl4030", &sdp2430_twldata);
         return 0;
 }
 
@@ -217,11 +208,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {}      /* Terminator */
 };
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
 static struct omap_usb_config sdp2430_usb_config __initdata = {
         .otg            = 1,
 #ifdef  CONFIG_USB_GADGET_OMAP
@@ -240,8 +226,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 
 static void __init omap_2430sdp_init(void)
 {
-        int ret;
-
         omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
 
         omap_board_config = sdp2430_config;
@@ -255,14 +239,13 @@ static void __init omap_2430sdp_init(void)
         omap2_usbfs_init(&sdp2430_usb_config);
 
         omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
 
         board_smc91x_init();
 
         /* Turn off secondary LCD backlight */
-        ret = gpio_request(SECONDARY_LCD_GPIO, "Secondary LCD backlight");
-        if (ret == 0)
-                gpio_direction_output(SECONDARY_LCD_GPIO, 0);
+        gpio_request_one(SECONDARY_LCD_GPIO, GPIOF_OUT_INIT_LOW,
+                         "Secondary LCD backlight");
 }
 
 static void __init omap_2430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 9afd087cc29c..ae2963a98041 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -19,7 +19,6 @@
 #include <linux/input.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
 #include <linux/io.h>
@@ -37,8 +36,8 @@
 #include <plat/common.h>
 #include <plat/dma.h>
 #include <plat/gpmc.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/gpmc-smc91x.h>
 
@@ -48,6 +47,7 @@
 #include "hsmmc.h"
 #include "pm.h"
 #include "control.h"
+#include "common-board-devices.h"
 
 #define CONFIG_DISABLE_HFCLK 1
 
@@ -59,24 +59,6 @@
 
 #define TWL4030_MSECURE_GPIO 22
 
-/* FIXME: These values need to be updated based on more profiling on 3430sdp*/
-static struct cpuidle_params omap3_cpuidle_params_table[] = {
-        /* C1 */
-        {1, 2, 2, 5},
-        /* C2 */
-        {1, 10, 10, 30},
-        /* C3 */
-        {1, 50, 50, 300},
-        /* C4 */
-        {1, 1500, 1800, 4000},
-        /* C5 */
-        {1, 2500, 7500, 12000},
-        /* C6 */
-        {1, 3000, 8500, 15000},
-        /* C7 */
-        {1, 10000, 30000, 300000},
-};
-
 static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_LEFT),
         KEY(0, 1, KEY_RIGHT),
@@ -123,63 +105,14 @@ static struct twl4030_keypad_data sdp3430_kp_data = {
         .rep            = 1,
 };
 
-static int ts_gpio;     /* Needed for ads7846_get_pendown_state */
-
-/**
- * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
- *
- * @return - void. If request gpio fails then Flag KERN_ERR.
- */
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) {
-                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
-                return;
-        }
-
-        gpio_direction_input(ts_gpio);
-        gpio_set_debounce(ts_gpio, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(ts_gpio);
-}
-
-static struct ads7846_platform_data tsc2046_config __initdata = {
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .wakeup                         = true,
-};
-
-
-static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info sdp3430_spi_board_info[] __initdata = {
-        [0] = {
-                /*
-                 * TSC2046 operates at a max freqency of 2MHz, so
-                 * operate slightly below at 1.5MHz
-                 */
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &tsc2046_mcspi_config,
-                .irq                    = 0,
-                .platform_data          = &tsc2046_config,
-        },
-};
-
-
 #define SDP3430_LCD_PANEL_BACKLIGHT_GPIO        8
 #define SDP3430_LCD_PANEL_ENABLE_GPIO           5
 
-static unsigned backlight_gpio;
-static unsigned enable_gpio;
+static struct gpio sdp3430_dss_gpios[] __initdata = {
+        {SDP3430_LCD_PANEL_ENABLE_GPIO,    GPIOF_OUT_INIT_LOW, "LCD reset"    },
+        {SDP3430_LCD_PANEL_BACKLIGHT_GPIO, GPIOF_OUT_INIT_LOW, "LCD Backlight"},
+};
+
 static int lcd_enabled;
 static int dvi_enabled;
 
@@ -187,29 +120,11 @@ static void __init sdp3430_display_init(void)
 {
         int r;
 
-        enable_gpio    = SDP3430_LCD_PANEL_ENABLE_GPIO;
-        backlight_gpio = SDP3430_LCD_PANEL_BACKLIGHT_GPIO;
-
-        r = gpio_request(enable_gpio, "LCD reset");
-        if (r) {
-                printk(KERN_ERR "failed to get LCD reset GPIO\n");
-                goto err0;
-        }
-
-        r = gpio_request(backlight_gpio, "LCD Backlight");
-        if (r) {
-                printk(KERN_ERR "failed to get LCD backlight GPIO\n");
-                goto err1;
-        }
-
-        gpio_direction_output(enable_gpio, 0);
-        gpio_direction_output(backlight_gpio, 0);
+        r = gpio_request_array(sdp3430_dss_gpios,
+                               ARRAY_SIZE(sdp3430_dss_gpios));
+        if (r)
+                printk(KERN_ERR "failed to get LCD control GPIOs\n");
 
-        return;
-err1:
-        gpio_free(enable_gpio);
-err0:
-        return;
 }
 
 static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
@@ -219,8 +134,8 @@ static int sdp3430_panel_enable_lcd(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_direction_output(enable_gpio, 1);
-        gpio_direction_output(backlight_gpio, 1);
+        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 1);
+        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 1);
 
         lcd_enabled = 1;
 
@@ -231,8 +146,8 @@ static void sdp3430_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
         lcd_enabled = 0;
 
-        gpio_direction_output(enable_gpio, 0);
-        gpio_direction_output(backlight_gpio, 0);
+        gpio_direction_output(SDP3430_LCD_PANEL_ENABLE_GPIO, 0);
+        gpio_direction_output(SDP3430_LCD_PANEL_BACKLIGHT_GPIO, 0);
 }
 
 static int sdp3430_panel_enable_dvi(struct omap_dss_device *dssdev)
@@ -360,12 +275,10 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
         omap2_hsmmc_init(mmc);
 
         /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
-        gpio_request(gpio + 7, "sub_lcd_en_bkl");
-        gpio_direction_output(gpio + 7, 0);
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
 
         /* gpio + 15 is "sub_lcd_nRST" (output) */
-        gpio_request(gpio + 15, "sub_lcd_nRST");
-        gpio_direction_output(gpio + 15, 0);
+        gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
 
         return 0;
 }
@@ -580,20 +493,10 @@ static struct twl4030_platform_data sdp3430_twldata = {
         .vpll2          = &sdp3430_vpll2,
 };
 
-static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &sdp3430_twldata,
-        },
-};
-
 static int __init omap3430_i2c_init(void)
 {
         /* i2c1 for PMIC only */
-        omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo,
-                        ARRAY_SIZE(sdp3430_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &sdp3430_twldata);
         /* i2c2 on camera connector (for sensor control) and optional isp1301 */
         omap_register_i2c_bus(2, 400, NULL, 0);
         /* i2c3 on display connector (for DVI, tfp410) */
@@ -872,30 +775,22 @@ static struct flash_partitions sdp_flash_partitions[] = {
         },
 };
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init omap_3430sdp_init(void)
 {
+        int gpio_pendown;
+
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_board_config = sdp3430_config;
         omap_board_config_size = ARRAY_SIZE(sdp3430_config);
-        omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
         omap3430_i2c_init();
         omap_display_init(&sdp3430_dss_data);
         if (omap_rev() > OMAP3430_REV_ES1_0)
-                ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
+                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
         else
-                ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1;
-        sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
-        spi_register_board_info(sdp3430_spi_board_info,
-                                ARRAY_SIZE(sdp3430_spi_board_info));
-        ads7846_dev_init();
+                gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
+        omap_ads7846_init(1, gpio_pendown, 310, NULL);
         board_serial_init();
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         board_smc91x_init();
         board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 56702c5e577f..73fa90bb6953 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -36,12 +36,13 @@
 #include <plat/usb.h>
 #include <plat/mmc.h>
 #include <plat/omap4-keypad.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #include "mux.h"
 #include "hsmmc.h"
 #include "timer-gp.h"
 #include "control.h"
+#include "common-board-devices.h"
 
 #define ETH_KS8851_IRQ                  34
 #define ETH_KS8851_POWER_ON             48
@@ -251,58 +252,22 @@ static struct spi_board_info sdp4430_spi_board_info[] __initdata = {
         },
 };
 
+static struct gpio sdp4430_eth_gpios[] __initdata = {
+        { ETH_KS8851_POWER_ON,  GPIOF_OUT_INIT_HIGH,    "eth_power"     },
+        { ETH_KS8851_QUART,     GPIOF_OUT_INIT_HIGH,    "quart"         },
+        { ETH_KS8851_IRQ,       GPIOF_IN,               "eth_irq"       },
+};
+
 static int omap_ethernet_init(void)
 {
         int status;
 
         /* Request of GPIO lines */
+        status = gpio_request_array(sdp4430_eth_gpios,
+                                    ARRAY_SIZE(sdp4430_eth_gpios));
+        if (status)
+                pr_err("Cannot request ETH GPIOs\n");
 
-        status = gpio_request(ETH_KS8851_POWER_ON, "eth_power");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", ETH_KS8851_POWER_ON);
-                return status;
-        }
-
-        status = gpio_request(ETH_KS8851_QUART, "quart");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", ETH_KS8851_QUART);
-                goto error1;
-        }
-
-        status = gpio_request(ETH_KS8851_IRQ, "eth_irq");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", ETH_KS8851_IRQ);
-                goto error2;
-        }
-
-        /* Configuration of requested GPIO lines */
-
-        status = gpio_direction_output(ETH_KS8851_POWER_ON, 1);
-        if (status) {
-                pr_err("Cannot set output GPIO %d\n", ETH_KS8851_IRQ);
-                goto error3;
-        }
-
-        status = gpio_direction_output(ETH_KS8851_QUART, 1);
-        if (status) {
-                pr_err("Cannot set output GPIO %d\n", ETH_KS8851_QUART);
-                goto error3;
-        }
-
-        status = gpio_direction_input(ETH_KS8851_IRQ);
-        if (status) {
-                pr_err("Cannot set input GPIO %d\n", ETH_KS8851_IRQ);
-                goto error3;
-        }
-
-        return 0;
-
-error3:
-        gpio_free(ETH_KS8851_IRQ);
-error2:
-        gpio_free(ETH_KS8851_QUART);
-error1:
-        gpio_free(ETH_KS8851_POWER_ON);
         return status;
 }
 
@@ -575,14 +540,6 @@ static struct twl4030_platform_data sdp4430_twldata = {
         .usb            = &omap4_usbphy_data
 };
 
-static struct i2c_board_info __initdata sdp4430_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl6030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = OMAP44XX_IRQ_SYS_1N,
-                .platform_data = &sdp4430_twldata,
-        },
-};
 static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
         {
                 I2C_BOARD_INFO("tmp105", 0x48),
@@ -598,12 +555,7 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
 };
 static int __init omap4_i2c_init(void)
 {
-        /*
-         * Phoenix Audio IC needs I2C1 to
-         * start with 400 KHz or less
-         */
-        omap_register_i2c_bus(1, 400, sdp4430_i2c_boardinfo,
-                        ARRAY_SIZE(sdp4430_i2c_boardinfo));
+        omap4_pmic_init("twl6030", &sdp4430_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
@@ -614,21 +566,13 @@ static int __init omap4_i2c_init(void)
 
 static void __init omap_sfh7741prox_init(void)
 {
-        int  error;
+        int error;
 
-        error = gpio_request(OMAP4_SFH7741_ENABLE_GPIO, "sfh7741");
-        if (error < 0) {
+        error = gpio_request_one(OMAP4_SFH7741_ENABLE_GPIO,
+                                 GPIOF_OUT_INIT_LOW, "sfh7741");
+        if (error < 0)
                 pr_err("%s:failed to request GPIO %d, error %d\n",
                         __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
-                return;
-        }
-
-        error = gpio_direction_output(OMAP4_SFH7741_ENABLE_GPIO , 0);
-        if (error < 0) {
-                pr_err("%s: GPIO configuration failed: GPIO %d,error %d\n",
-                         __func__, OMAP4_SFH7741_ENABLE_GPIO, error);
-                gpio_free(OMAP4_SFH7741_ENABLE_GPIO);
-        }
 }
 
 static void sdp4430_hdmi_mux_init(void)
@@ -645,27 +589,19 @@ static void sdp4430_hdmi_mux_init(void)
                         OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct gpio sdp4430_hdmi_gpios[] = {
+        { HDMI_GPIO_HPD,        GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_hpd"   },
+        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH,    "hdmi_gpio_ls_oe" },
+};
+
 static int sdp4430_panel_enable_hdmi(struct omap_dss_device *dssdev)
 {
         int status;
 
-        status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH,
-                                                        "hdmi_gpio_hpd");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD);
-                return status;
-        }
-        status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH,
-                                                        "hdmi_gpio_ls_oe");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE);
-                goto error1;
-        }
-
-        return 0;
-
-error1:
-        gpio_free(HDMI_GPIO_HPD);
+        status = gpio_request_array(sdp4430_hdmi_gpios,
+                                    ARRAY_SIZE(sdp4430_hdmi_gpios));
+        if (status)
+                pr_err("%s: Cannot request HDMI GPIOs\n", __func__);
 
         return status;
 }
@@ -680,6 +616,15 @@ static struct omap_dss_device sdp4430_hdmi_device = {
         .name = "hdmi",
         .driver_name = "hdmi_panel",
         .type = OMAP_DISPLAY_TYPE_HDMI,
+        .clocks = {
+                .dispc  = {
+                        .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
+                },
+                .hdmi   = {
+                        .regn   = 15,
+                        .regm2  = 1,
+                },
+        },
         .platform_enable = sdp4430_panel_enable_hdmi,
         .platform_disable = sdp4430_panel_disable_hdmi,
         .channel = OMAP_DSS_CHANNEL_DIGIT,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index a890d244fec6..5e438a77cd72 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -89,19 +89,13 @@ static void __init am3517_crane_init(void)
                 return;
         }
 
-        ret = gpio_request(GPIO_USB_POWER, "usb_ehci_enable");
+        ret = gpio_request_one(GPIO_USB_POWER, GPIOF_OUT_INIT_HIGH,
+                               "usb_ehci_enable");
         if (ret < 0) {
                 pr_err("Can not request GPIO %d\n", GPIO_USB_POWER);
                 return;
         }
 
-        ret = gpio_direction_output(GPIO_USB_POWER, 1);
-        if (ret < 0) {
-                gpio_free(GPIO_USB_POWER);
-                pr_err("Unable to initialize EHCI power\n");
-                return;
-        }
-
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index ce7d5e6e4150..63af4171c043 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -34,8 +34,8 @@
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include "mux.h"
 #include "control.h"
@@ -174,19 +174,14 @@ static void __init am3517_evm_rtc_init(void)
         int r;
 
         omap_mux_init_gpio(GPIO_RTCS35390A_IRQ, OMAP_PIN_INPUT_PULLUP);
-        r = gpio_request(GPIO_RTCS35390A_IRQ, "rtcs35390a-irq");
+
+        r = gpio_request_one(GPIO_RTCS35390A_IRQ, GPIOF_IN, "rtcs35390a-irq");
         if (r < 0) {
                 printk(KERN_WARNING "failed to request GPIO#%d\n",
                                 GPIO_RTCS35390A_IRQ);
                 return;
         }
-        r = gpio_direction_input(GPIO_RTCS35390A_IRQ);
-        if (r < 0) {
-                printk(KERN_WARNING "GPIO#%d cannot be configured as input\n",
-                                GPIO_RTCS35390A_IRQ);
-                gpio_free(GPIO_RTCS35390A_IRQ);
-                return;
-        }
+
         am3517evm_i2c1_boardinfo[0].irq = gpio_to_irq(GPIO_RTCS35390A_IRQ);
 }
 
@@ -242,6 +237,15 @@ static int dvi_enabled;
 
 #if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
                 defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
+static struct gpio am3517_evm_dss_gpios[] __initdata = {
+        /* GPIO 182 = LCD Backlight Power */
+        { LCD_PANEL_BKLIGHT_PWR, GPIOF_OUT_INIT_HIGH, "lcd_backlight_pwr" },
+        /* GPIO 181 = LCD Panel PWM */
+        { LCD_PANEL_PWM,         GPIOF_OUT_INIT_HIGH, "lcd bl enable"     },
+        /* GPIO 176 = LCD Panel Power enable pin */
+        { LCD_PANEL_PWR,         GPIOF_OUT_INIT_HIGH, "dvi enable"        },
+};
+
 static void __init am3517_evm_display_init(void)
 {
         int r;
@@ -249,41 +253,15 @@ static void __init am3517_evm_display_init(void)
         omap_mux_init_gpio(LCD_PANEL_PWR, OMAP_PIN_INPUT_PULLUP);
         omap_mux_init_gpio(LCD_PANEL_BKLIGHT_PWR, OMAP_PIN_INPUT_PULLDOWN);
         omap_mux_init_gpio(LCD_PANEL_PWM, OMAP_PIN_INPUT_PULLDOWN);
-        /*
-         * Enable GPIO 182 = LCD Backlight Power
-         */
-        r = gpio_request(LCD_PANEL_BKLIGHT_PWR, "lcd_backlight_pwr");
+
+        r = gpio_request_array(am3517_evm_dss_gpios,
+                               ARRAY_SIZE(am3517_evm_dss_gpios));
         if (r) {
-                printk(KERN_ERR "failed to get lcd_backlight_pwr\n");
+                printk(KERN_ERR "failed to get DSS panel control GPIOs\n");
                 return;
         }
-        gpio_direction_output(LCD_PANEL_BKLIGHT_PWR, 1);
-        /*
-         * Enable GPIO 181 = LCD Panel PWM
-         */
-        r = gpio_request(LCD_PANEL_PWM, "lcd_pwm");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_pwm\n");
-                goto err_1;
-        }
-        gpio_direction_output(LCD_PANEL_PWM, 1);
-        /*
-         * Enable GPIO 176 = LCD Panel Power enable pin
-         */
-        r = gpio_request(LCD_PANEL_PWR, "lcd_panel_pwr");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_pwr\n");
-                goto err_2;
-        }
-        gpio_direction_output(LCD_PANEL_PWR, 1);
 
         printk(KERN_INFO "Display initialized successfully\n");
-        return;
-
-err_2:
-        gpio_free(LCD_PANEL_PWM);
-err_1:
-        gpio_free(LCD_PANEL_BKLIGHT_PWR);
 }
 #else
 static void __init am3517_evm_display_init(void) {}
@@ -396,7 +374,7 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 500,
         .set_phy_power          = am35x_musb_phy_power,
         .clear_irq              = am35x_musb_clear_irq,
-        .set_mode               = am35x_musb_set_mode,
+        .set_mode               = am35x_set_mode,
         .reset                  = am35x_musb_reset,
 };
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index f4f8374a0298..f3beb8eeef77 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -202,6 +202,7 @@ static inline void __init apollon_init_smc91x(void)
         unsigned int rate;
         struct clk *gpmc_fck;
         int eth_cs;
+        int err;
 
         gpmc_fck = clk_get(NULL, "gpmc_fck");   /* Always on ENABLE_ON_INIT */
         if (IS_ERR(gpmc_fck)) {
@@ -245,15 +246,13 @@ static inline void __init apollon_init_smc91x(void)
         apollon_smc91x_resources[0].end   = base + 0x30f;
         udelay(100);
 
-        omap_mux_init_gpio(74, 0);
-        if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
+        omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0);
+        err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq");
+        if (err) {
                 printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
                         APOLLON_ETHR_GPIO_IRQ);
                 gpmc_cs_free(APOLLON_ETH_CS);
-                goto out;
         }
-        gpio_direction_input(APOLLON_ETHR_GPIO_IRQ);
-
 out:
         clk_disable(gpmc_fck);
         clk_put(gpmc_fck);
@@ -280,20 +279,19 @@ static void __init omap_apollon_init_early(void)
         omap2_init_common_devices(NULL, NULL);
 }
 
+static struct gpio apollon_gpio_leds[] __initdata = {
+        { LED0_GPIO13, GPIOF_OUT_INIT_LOW, "LED0" }, /* LED0 - AA10 */
+        { LED1_GPIO14, GPIOF_OUT_INIT_LOW, "LED1" }, /* LED1 - AA6  */
+        { LED2_GPIO15, GPIOF_OUT_INIT_LOW, "LED2" }, /* LED2 - AA4  */
+};
+
 static void __init apollon_led_init(void)
 {
-        /* LED0 - AA10 */
         omap_mux_init_signal("vlynq_clk.gpio_13", 0);
-        gpio_request(LED0_GPIO13, "LED0");
-        gpio_direction_output(LED0_GPIO13, 0);
-        /* LED1  - AA6 */
         omap_mux_init_signal("vlynq_rx1.gpio_14", 0);
-        gpio_request(LED1_GPIO14, "LED1");
-        gpio_direction_output(LED1_GPIO14, 0);
-        /* LED2  - AA4 */
         omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
-        gpio_request(LED2_GPIO15, "LED2");
-        gpio_direction_output(LED2_GPIO15, 0);
+
+        gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
 }
 
 static void __init apollon_usb_init(void)
@@ -301,8 +299,7 @@ static void __init apollon_usb_init(void)
         /* USB device */
         /* DEVICE_SUSPEND */
         omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
-        gpio_request(12, "USB suspend");
-        gpio_direction_output(12, 0);
+        gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend");
         omap2_usbfs_init(&apollon_usb_config);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 02a12b41c0ff..c63115bc1536 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -45,8 +45,8 @@
 #include <plat/nand.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/mcspi.h>
 
 #include <mach/hardware.h>
@@ -54,6 +54,7 @@
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define CM_T35_GPIO_PENDOWN     57
 
@@ -66,86 +67,28 @@
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 #include <linux/smsc911x.h>
+#include <plat/gpmc-smsc911x.h>
 
-static struct smsc911x_platform_config cm_t35_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource cm_t35_smsc911x_resources[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP_GPIO_IRQ(CM_T35_SMSC911X_GPIO),
-                .end    = OMAP_GPIO_IRQ(CM_T35_SMSC911X_GPIO),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct platform_device cm_t35_smsc911x_device = {
-        .name           = "smsc911x",
+static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = {
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(cm_t35_smsc911x_resources),
-        .resource       = cm_t35_smsc911x_resources,
-        .dev            = {
-                .platform_data = &cm_t35_smsc911x_config,
-        },
-};
-
-static struct resource sb_t35_smsc911x_resources[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP_GPIO_IRQ(SB_T35_SMSC911X_GPIO),
-                .end    = OMAP_GPIO_IRQ(SB_T35_SMSC911X_GPIO),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
+        .cs             = CM_T35_SMSC911X_CS,
+        .gpio_irq       = CM_T35_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
-static struct platform_device sb_t35_smsc911x_device = {
-        .name           = "smsc911x",
+static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = {
         .id             = 1,
-        .num_resources  = ARRAY_SIZE(sb_t35_smsc911x_resources),
-        .resource       = sb_t35_smsc911x_resources,
-        .dev            = {
-                .platform_data = &cm_t35_smsc911x_config,
-        },
+        .cs             = SB_T35_SMSC911X_CS,
+        .gpio_irq       = SB_T35_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
-static void __init cm_t35_init_smsc911x(struct platform_device *dev,
-                                        int cs, int irq_gpio)
-{
-        unsigned long cs_mem_base;
-
-        if (gpmc_cs_request(cs, SZ_16M, &cs_mem_base) < 0) {
-                pr_err("CM-T35: Failed request for GPMC mem for smsc911x\n");
-                return;
-        }
-
-        dev->resource[0].start = cs_mem_base + 0x0;
-        dev->resource[0].end   = cs_mem_base + 0xff;
-
-        if ((gpio_request(irq_gpio, "ETH IRQ") == 0) &&
-            (gpio_direction_input(irq_gpio) == 0)) {
-                gpio_export(irq_gpio, 0);
-        } else {
-                pr_err("CM-T35: could not obtain gpio for SMSC911X IRQ\n");
-                return;
-        }
-
-        platform_device_register(dev);
-}
-
 static void __init cm_t35_init_ethernet(void)
 {
-        cm_t35_init_smsc911x(&cm_t35_smsc911x_device,
-                             CM_T35_SMSC911X_CS, CM_T35_SMSC911X_GPIO);
-        cm_t35_init_smsc911x(&sb_t35_smsc911x_device,
-                             SB_T35_SMSC911X_CS, SB_T35_SMSC911X_GPIO);
+        gpmc_smsc911x_init(&cm_t35_smsc911x_cfg);
+        gpmc_smsc911x_init(&sb_t35_smsc911x_cfg);
 }
 #else
 static inline void __init cm_t35_init_ethernet(void) { return; }
@@ -235,69 +178,10 @@ static void __init cm_t35_init_nand(void)
 static inline void cm_t35_init_nand(void) {}
 #endif
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
-        defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-#include <linux/spi/ads7846.h>
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(CM_T35_GPIO_PENDOWN);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct spi_board_info cm_t35_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(CM_T35_GPIO_PENDOWN),
-                .platform_data          = &ads7846_config,
-        },
-};
-
-static void __init cm_t35_init_ads7846(void)
-{
-        if ((gpio_request(CM_T35_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) &&
-            (gpio_direction_input(CM_T35_GPIO_PENDOWN) == 0)) {
-                gpio_export(CM_T35_GPIO_PENDOWN, 0);
-        } else {
-                pr_err("CM-T35: could not obtain gpio for ADS7846_PENDOWN\n");
-                return;
-        }
-
-        spi_register_board_info(cm_t35_spi_board_info,
-                                ARRAY_SIZE(cm_t35_spi_board_info));
-}
-#else
-static inline void cm_t35_init_ads7846(void) {}
-#endif
-
 #define CM_T35_LCD_EN_GPIO 157
 #define CM_T35_LCD_BL_GPIO 58
 #define CM_T35_DVI_EN_GPIO 54
 
-static int lcd_bl_gpio;
-static int lcd_en_gpio;
-static int dvi_en_gpio;
-
 static int lcd_enabled;
 static int dvi_enabled;
 
@@ -308,8 +192,8 @@ static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(lcd_en_gpio, 1);
-        gpio_set_value(lcd_bl_gpio, 1);
+        gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
+        gpio_set_value(CM_T35_LCD_BL_GPIO, 1);
 
         lcd_enabled = 1;
 
@@ -320,8 +204,8 @@ static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
         lcd_enabled = 0;
 
-        gpio_set_value(lcd_bl_gpio, 0);
-        gpio_set_value(lcd_en_gpio, 0);
+        gpio_set_value(CM_T35_LCD_BL_GPIO, 0);
+        gpio_set_value(CM_T35_LCD_EN_GPIO, 0);
 }
 
 static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
@@ -331,7 +215,7 @@ static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(dvi_en_gpio, 0);
+        gpio_set_value(CM_T35_DVI_EN_GPIO, 0);
         dvi_enabled = 1;
 
         return 0;
@@ -339,7 +223,7 @@ static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev)
 
 static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
-        gpio_set_value(dvi_en_gpio, 1);
+        gpio_set_value(CM_T35_DVI_EN_GPIO, 1);
         dvi_enabled = 0;
 }
 
@@ -421,62 +305,38 @@ static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = {
         },
 };
 
+static struct gpio cm_t35_dss_gpios[] __initdata = {
+        { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW,  "lcd enable"    },
+        { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW,  "lcd bl enable" },
+        { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable"    },
+};
+
 static void __init cm_t35_init_display(void)
 {
         int err;
 
-        lcd_en_gpio = CM_T35_LCD_EN_GPIO;
-        lcd_bl_gpio = CM_T35_LCD_BL_GPIO;
-        dvi_en_gpio = CM_T35_DVI_EN_GPIO;
-
         spi_register_board_info(cm_t35_lcd_spi_board_info,
                                 ARRAY_SIZE(cm_t35_lcd_spi_board_info));
 
-        err = gpio_request(lcd_en_gpio, "LCD RST");
-        if (err) {
-                pr_err("CM-T35: failed to get LCD reset GPIO\n");
-                goto out;
-        }
-
-        err = gpio_request(lcd_bl_gpio, "LCD BL");
+        err = gpio_request_array(cm_t35_dss_gpios,
+                                 ARRAY_SIZE(cm_t35_dss_gpios));
         if (err) {
-                pr_err("CM-T35: failed to get LCD backlight control GPIO\n");
-                goto err_lcd_bl;
-        }
-
-        err = gpio_request(dvi_en_gpio, "DVI EN");
-        if (err) {
-                pr_err("CM-T35: failed to get DVI reset GPIO\n");
-                goto err_dvi_en;
+                pr_err("CM-T35: failed to request DSS control GPIOs\n");
+                return;
         }
 
-        gpio_export(lcd_en_gpio, 0);
-        gpio_export(lcd_bl_gpio, 0);
-        gpio_export(dvi_en_gpio, 0);
-        gpio_direction_output(lcd_en_gpio, 0);
-        gpio_direction_output(lcd_bl_gpio, 0);
-        gpio_direction_output(dvi_en_gpio, 1);
+        gpio_export(CM_T35_LCD_EN_GPIO, 0);
+        gpio_export(CM_T35_LCD_BL_GPIO, 0);
+        gpio_export(CM_T35_DVI_EN_GPIO, 0);
 
         msleep(50);
-        gpio_set_value(lcd_en_gpio, 1);
+        gpio_set_value(CM_T35_LCD_EN_GPIO, 1);
 
         err = omap_display_init(&cm_t35_dss_data);
         if (err) {
                 pr_err("CM-T35: failed to register DSS device\n");
-                goto err_dev_reg;
+                gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios));
         }
-
-        return;
-
-err_dev_reg:
-        gpio_free(dvi_en_gpio);
-err_dvi_en:
-        gpio_free(lcd_bl_gpio);
-err_lcd_bl:
-        gpio_free(lcd_en_gpio);
-out:
-
-        return;
 }
 
 static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
@@ -609,10 +469,8 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
 {
         int wlan_rst = gpio + 2;
 
-        if ((gpio_request(wlan_rst, "WLAN RST") == 0) &&
-            (gpio_direction_output(wlan_rst, 1) == 0)) {
+        if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
                 gpio_export(wlan_rst, 0);
-
                 udelay(10);
                 gpio_set_value(wlan_rst, 0);
                 udelay(10);
@@ -653,19 +511,9 @@ static struct twl4030_platform_data cm_t35_twldata = {
         .vpll2          = &cm_t35_vpll2,
 };
 
-static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65930", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &cm_t35_twldata,
-        },
-};
-
 static void __init cm_t35_init_i2c(void)
 {
-        omap_register_i2c_bus(1, 2600, cm_t35_i2c_boardinfo,
-                              ARRAY_SIZE(cm_t35_i2c_boardinfo));
+        omap3_pmic_init("tps65930", &cm_t35_twldata);
 }
 
 static void __init cm_t35_init_early(void)
@@ -775,12 +623,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static struct omap_board_config_kernel cm_t35_config[] __initdata = {
 };
 
@@ -792,12 +634,12 @@ static void __init cm_t35_init(void)
         omap_serial_init();
         cm_t35_init_i2c();
         cm_t35_init_nand();
-        cm_t35_init_ads7846();
+        omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
         cm_t35_init_ethernet();
         cm_t35_init_led();
         cm_t35_init_display();
 
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
 }
 
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index a27e3eee8292..08f08e812492 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -148,14 +148,13 @@ static void __init cm_t3517_init_rtc(void)
 {
         int err;
 
-        err = gpio_request(RTC_CS_EN_GPIO, "rtc cs en");
+        err = gpio_request_one(RTC_CS_EN_GPIO, GPIOF_OUT_INIT_HIGH,
+                               "rtc cs en");
         if (err) {
                 pr_err("CM-T3517: rtc cs en gpio request failed: %d\n", err);
                 return;
         }
 
-        gpio_direction_output(RTC_CS_EN_GPIO, 1);
-
         platform_device_register(&cm_t3517_rtc_device);
 }
 #else
@@ -182,11 +181,11 @@ static int cm_t3517_init_usbh(void)
 {
         int err;
 
-        err = gpio_request(USB_HUB_RESET_GPIO, "usb hub rst");
+        err = gpio_request_one(USB_HUB_RESET_GPIO, GPIOF_OUT_INIT_LOW,
+                               "usb hub rst");
         if (err) {
                 pr_err("CM-T3517: usb hub rst gpio request failed: %d\n", err);
         } else {
-                gpio_direction_output(USB_HUB_RESET_GPIO, 0);
                 udelay(10);
                 gpio_set_value(USB_HUB_RESET_GPIO, 1);
                 msleep(1);
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 65f9fde2c567..cf520d7dd614 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -45,13 +45,12 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/dm9000.h>
 #include <linux/interrupt.h>
 
@@ -60,6 +59,7 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "timer-gp.h"
+#include "common-board-devices.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
@@ -97,13 +97,6 @@ static struct mtd_partition devkit8000_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data devkit8000_nand_data = {
-        .options        = NAND_BUSWIDTH_16,
-        .parts          = devkit8000_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(devkit8000_nand_partitions),
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-};
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -249,7 +242,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
         /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */
         devkit8000_lcd_device.reset_gpio = gpio + TWL4030_GPIO_MAX + 0;
         ret = gpio_request_one(devkit8000_lcd_device.reset_gpio,
-                        GPIOF_DIR_OUT | GPIOF_INIT_LOW, "LCD_PWREN");
+                               GPIOF_OUT_INIT_LOW, "LCD_PWREN");
         if (ret < 0) {
                 devkit8000_lcd_device.reset_gpio = -EINVAL;
                 printk(KERN_ERR "Failed to request GPIO for LCD_PWRN\n");
@@ -258,7 +251,7 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
         /* gpio + 7 is "DVI_PD" (out, active low) */
         devkit8000_dvi_device.reset_gpio = gpio + 7;
         ret = gpio_request_one(devkit8000_dvi_device.reset_gpio,
-                        GPIOF_DIR_OUT | GPIOF_INIT_LOW, "DVI PowerDown");
+                               GPIOF_OUT_INIT_LOW, "DVI PowerDown");
         if (ret < 0) {
                 devkit8000_dvi_device.reset_gpio = -EINVAL;
                 printk(KERN_ERR "Failed to request GPIO for DVI PowerDown\n");
@@ -366,19 +359,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
         .keypad         = &devkit8000_kp_data,
 };
 
-static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65930", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &devkit8000_twldata,
-        },
-};
-
 static int __init devkit8000_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, devkit8000_i2c_boardinfo,
-                        ARRAY_SIZE(devkit8000_i2c_boardinfo));
+        omap3_pmic_init("tps65930", &devkit8000_twldata);
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -463,56 +446,6 @@ static void __init devkit8000_init_irq(void)
 #endif
 }
 
-static void __init devkit8000_ads7846_init(void)
-{
-        int gpio = OMAP3_DEVKIT_TS_GPIO;
-        int ret;
-
-        ret = gpio_request(gpio, "ads7846_pen_down");
-        if (ret < 0) {
-                printk(KERN_ERR "Failed to request GPIO %d for "
-                                "ads7846 pen down IRQ\n", gpio);
-                return;
-        }
-
-        gpio_direction_input(gpio);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_DEVKIT_TS_GPIO);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 5,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .settle_delay_usecs     = 150,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info devkit8000_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 2,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_DEVKIT_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        }
-};
-
 #define OMAP_DM9000_BASE        0x2c000000
 
 static struct resource omap_dm9000_resources[] = {
@@ -550,14 +483,14 @@ static void __init omap_dm9000_init(void)
 {
         unsigned char *eth_addr = omap_dm9000_platdata.dev_addr;
         struct omap_die_id odi;
+        int ret;
 
-        if (gpio_request(OMAP_DM9000_GPIO_IRQ, "dm9000 irq") < 0) {
+        ret = gpio_request_one(OMAP_DM9000_GPIO_IRQ, GPIOF_IN, "dm9000 irq");
+        if (ret < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for dm9000 IRQ\n",
                         OMAP_DM9000_GPIO_IRQ);
                 return;
-                }
-
-        gpio_direction_input(OMAP_DM9000_GPIO_IRQ);
+        }
 
         /* init the mac address using DIE id */
         omap_get_die_id(&odi);
@@ -576,45 +509,6 @@ static struct platform_device *devkit8000_devices[] __initdata = {
         &omap_dm9000_dev,
 };
 
-static void __init devkit8000_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                devkit8000_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&devkit8000_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
@@ -795,14 +689,13 @@ static void __init devkit8000_init(void)
                         ARRAY_SIZE(devkit8000_devices));
 
         omap_display_init(&devkit8000_dss_data);
-        spi_register_board_info(devkit8000_spi_board_info,
-        ARRAY_SIZE(devkit8000_spi_board_info));
 
-        devkit8000_ads7846_init();
+        omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL);
 
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        devkit8000_flash_init();
+        omap_nand_flash_init(NAND_BUSWIDTH_16, devkit8000_nand_partitions,
+                             ARRAY_SIZE(devkit8000_nand_partitions));
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 34cf982b9679..0c1bfca3f731 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -31,13 +31,14 @@
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/onenand.h>
 
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-numonyx-m65kxxxxam.h"
+#include "common-board-devices.h"
 
 #define IGEP2_SMSC911X_CS       5
 #define IGEP2_SMSC911X_GPIO     176
@@ -54,6 +55,11 @@
 #define IGEP2_RC_GPIO_WIFI_NRESET  139
 #define IGEP2_RC_GPIO_BT_NRESET    137
 
+#define IGEP3_GPIO_LED0_GREEN   54
+#define IGEP3_GPIO_LED0_RED     53
+#define IGEP3_GPIO_LED1_RED     16
+#define IGEP3_GPIO_USBH_NRESET  183
+
 /*
  * IGEP2 Hardware Revision Table
  *
@@ -68,6 +74,7 @@
 
 #define IGEP2_BOARD_HWREV_B     0
 #define IGEP2_BOARD_HWREV_C     1
+#define IGEP3_BOARD_HWREV       2
 
 static u8 hwrev;
 
@@ -75,24 +82,29 @@ static void __init igep2_get_revision(void)
 {
         u8 ret;
 
+        if (machine_is_igep0030()) {
+                hwrev = IGEP3_BOARD_HWREV;
+                return;
+        }
+
         omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT);
 
-        if ((gpio_request(IGEP2_GPIO_LED1_RED, "GPIO_HW0_REV") == 0) &&
-            (gpio_direction_input(IGEP2_GPIO_LED1_RED) == 0)) {
-                ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
-                if (ret == 0) {
-                        pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
-                        hwrev = IGEP2_BOARD_HWREV_C;
-                } else if (ret ==  1) {
-                        pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
-                        hwrev = IGEP2_BOARD_HWREV_B;
-                } else {
-                        pr_err("IGEP2: Unknown Hardware Revision\n");
-                        hwrev = -1;
-                }
-        } else {
+        if (gpio_request_one(IGEP2_GPIO_LED1_RED, GPIOF_IN, "GPIO_HW0_REV")) {
                 pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n");
                 pr_err("IGEP2: Unknown Hardware Revision\n");
+                return;
+        }
+
+        ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
+        if (ret == 0) {
+                pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
+                hwrev = IGEP2_BOARD_HWREV_C;
+        } else if (ret ==  1) {
+                pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
+                hwrev = IGEP2_BOARD_HWREV_B;
+        } else {
+                pr_err("IGEP2: Unknown Hardware Revision\n");
+                hwrev = -1;
         }
 
         gpio_free(IGEP2_GPIO_LED1_RED);
@@ -111,7 +123,7 @@ static void __init igep2_get_revision(void)
  * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
  */
 
-static struct mtd_partition igep2_onenand_partitions[] = {
+static struct mtd_partition igep_onenand_partitions[] = {
         {
                 .name           = "X-Loader",
                 .offset         = 0,
@@ -139,21 +151,21 @@ static struct mtd_partition igep2_onenand_partitions[] = {
         },
 };
 
-static struct omap_onenand_platform_data igep2_onenand_data = {
-        .parts = igep2_onenand_partitions,
-        .nr_parts = ARRAY_SIZE(igep2_onenand_partitions),
+static struct omap_onenand_platform_data igep_onenand_data = {
+        .parts = igep_onenand_partitions,
+        .nr_parts = ARRAY_SIZE(igep_onenand_partitions),
         .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
 };
 
-static struct platform_device igep2_onenand_device = {
+static struct platform_device igep_onenand_device = {
         .name           = "omap2-onenand",
         .id             = -1,
         .dev = {
-                .platform_data = &igep2_onenand_data,
+                .platform_data = &igep_onenand_data,
         },
 };
 
-static void __init igep2_flash_init(void)
+static void __init igep_flash_init(void)
 {
         u8 cs = 0;
         u8 onenandcs = GPMC_CS_NUM + 1;
@@ -165,7 +177,7 @@ static void __init igep2_flash_init(void)
                 /* Check if NAND/oneNAND is configured */
                 if ((ret & 0xC00) == 0x800)
                         /* NAND found */
-                        pr_err("IGEP2: Unsupported NAND found\n");
+                        pr_err("IGEP: Unsupported NAND found\n");
                 else {
                         ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
                         if ((ret & 0x3F) == (ONENAND_MAP >> 24))
@@ -175,85 +187,46 @@ static void __init igep2_flash_init(void)
         }
 
         if (onenandcs > GPMC_CS_NUM) {
-                pr_err("IGEP2: Unable to find configuration in GPMC\n");
+                pr_err("IGEP: Unable to find configuration in GPMC\n");
                 return;
         }
 
-        igep2_onenand_data.cs = onenandcs;
+        igep_onenand_data.cs = onenandcs;
 
-        if (platform_device_register(&igep2_onenand_device) < 0)
-                pr_err("IGEP2: Unable to register OneNAND device\n");
+        if (platform_device_register(&igep_onenand_device) < 0)
+                pr_err("IGEP: Unable to register OneNAND device\n");
 }
 
 #else
-static void __init igep2_flash_init(void) {}
+static void __init igep_flash_init(void) {}
 #endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
+#include <plat/gpmc-smsc911x.h>
 
-static struct smsc911x_platform_config igep2_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS  ,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource igep2_smsc911x_resources[] = {
-        {
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = OMAP_GPIO_IRQ(IGEP2_SMSC911X_GPIO),
-                .end    = OMAP_GPIO_IRQ(IGEP2_SMSC911X_GPIO),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct platform_device igep2_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(igep2_smsc911x_resources),
-        .resource       = igep2_smsc911x_resources,
-        .dev            = {
-                .platform_data = &igep2_smsc911x_config,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = IGEP2_SMSC911X_CS,
+        .gpio_irq       = IGEP2_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
 static inline void __init igep2_init_smsc911x(void)
 {
-        unsigned long cs_mem_base;
-
-        if (gpmc_cs_request(IGEP2_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
-                pr_err("IGEP v2: Failed request for GPMC mem for smsc911x\n");
-                gpmc_cs_free(IGEP2_SMSC911X_CS);
-                return;
-        }
-
-        igep2_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        igep2_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-
-        if ((gpio_request(IGEP2_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
-            (gpio_direction_input(IGEP2_SMSC911X_GPIO) == 0)) {
-                gpio_export(IGEP2_SMSC911X_GPIO, 0);
-        } else {
-                pr_err("IGEP v2: Could not obtain gpio for for SMSC911X IRQ\n");
-                return;
-        }
-
-        platform_device_register(&igep2_smsc911x_device);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 #else
 static inline void __init igep2_init_smsc911x(void) { }
 #endif
 
-static struct regulator_consumer_supply igep2_vmmc1_supply =
+static struct regulator_consumer_supply igep_vmmc1_supply =
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
-static struct regulator_init_data igep2_vmmc1 = {
+static struct regulator_init_data igep_vmmc1 = {
         .constraints = {
                 .min_uV                 = 1850000,
                 .max_uV                 = 3150000,
@@ -264,13 +237,13 @@ static struct regulator_init_data igep2_vmmc1 = {
                                         | REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vmmc1_supply,
+        .consumer_supplies      = &igep_vmmc1_supply,
 };
 
-static struct regulator_consumer_supply igep2_vio_supply =
+static struct regulator_consumer_supply igep_vio_supply =
         REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
 
-static struct regulator_init_data igep2_vio = {
+static struct regulator_init_data igep_vio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
@@ -282,34 +255,34 @@ static struct regulator_init_data igep2_vio = {
                                         | REGULATOR_CHANGE_STATUS,
         },
         .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vio_supply,
+        .consumer_supplies      = &igep_vio_supply,
 };
 
-static struct regulator_consumer_supply igep2_vmmc2_supply =
+static struct regulator_consumer_supply igep_vmmc2_supply =
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
 
-static struct regulator_init_data igep2_vmmc2 = {
+static struct regulator_init_data igep_vmmc2 = {
         .constraints            = {
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
                 .always_on              = 1,
         },
         .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep2_vmmc2_supply,
+        .consumer_supplies      = &igep_vmmc2_supply,
 };
 
-static struct fixed_voltage_config igep2_vwlan = {
+static struct fixed_voltage_config igep_vwlan = {
         .supply_name            = "vwlan",
         .microvolts             = 3300000,
         .gpio                   = -EINVAL,
         .enabled_at_boot        = 1,
-        .init_data              = &igep2_vmmc2,
+        .init_data              = &igep_vmmc2,
 };
 
-static struct platform_device igep2_vwlan_device = {
+static struct platform_device igep_vwlan_device = {
         .name           = "reg-fixed-voltage",
         .id             = 0,
         .dev = {
-                .platform_data  = &igep2_vwlan,
+                .platform_data  = &igep_vwlan,
         },
 };
 
@@ -334,20 +307,17 @@ static struct omap2_hsmmc_info mmc[] = {
 #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 #include <linux/leds.h>
 
-static struct gpio_led igep2_gpio_leds[] = {
+static struct gpio_led igep_gpio_leds[] = {
         [0] = {
                 .name                   = "gpio-led:red:d0",
-                .gpio                   = IGEP2_GPIO_LED0_RED,
                 .default_trigger        = "default-off"
         },
         [1] = {
                 .name                   = "gpio-led:green:d0",
-                .gpio                   = IGEP2_GPIO_LED0_GREEN,
                 .default_trigger        = "default-off",
         },
         [2] = {
                 .name                   = "gpio-led:red:d1",
-                .gpio                   = IGEP2_GPIO_LED1_RED,
                 .default_trigger        = "default-off",
         },
         [3] = {
@@ -358,94 +328,119 @@ static struct gpio_led igep2_gpio_leds[] = {
         },
 };
 
-static struct gpio_led_platform_data igep2_led_pdata = {
-        .leds           = igep2_gpio_leds,
-        .num_leds       = ARRAY_SIZE(igep2_gpio_leds),
+static struct gpio_led_platform_data igep_led_pdata = {
+        .leds           = igep_gpio_leds,
+        .num_leds       = ARRAY_SIZE(igep_gpio_leds),
 };
 
-static struct platform_device igep2_led_device = {
+static struct platform_device igep_led_device = {
          .name   = "leds-gpio",
          .id     = -1,
          .dev    = {
-                 .platform_data  =  &igep2_led_pdata,
+                 .platform_data  =  &igep_led_pdata,
         },
 };
 
-static void __init igep2_leds_init(void)
+static void __init igep_leds_init(void)
 {
-        platform_device_register(&igep2_led_device);
+        if (machine_is_igep0020()) {
+                igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
+        } else {
+                igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
+        }
+
+        platform_device_register(&igep_led_device);
 }
 
 #else
-static inline void igep2_leds_init(void)
+static struct gpio igep_gpio_leds[] __initdata = {
+        { -EINVAL,      GPIOF_OUT_INIT_LOW, "gpio-led:red:d0"   },
+        { -EINVAL,      GPIOF_OUT_INIT_LOW, "gpio-led:green:d0" },
+        { -EINVAL,      GPIOF_OUT_INIT_LOW, "gpio-led:red:d1"   },
+};
+
+static inline void igep_leds_init(void)
 {
-        if ((gpio_request(IGEP2_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_RED, 0) == 0))
-                gpio_export(IGEP2_GPIO_LED0_RED, 0);
-        else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_RED\n");
+        int i;
 
-        if ((gpio_request(IGEP2_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED0_GREEN, 0) == 0))
-                gpio_export(IGEP2_GPIO_LED0_GREEN, 0);
-        else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED0_GREEN\n");
+        if (machine_is_igep0020()) {
+                igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
+        } else {
+                igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
+                igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
+                igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
+        }
 
-        if ((gpio_request(IGEP2_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
-            (gpio_direction_output(IGEP2_GPIO_LED1_RED, 0) == 0))
-                gpio_export(IGEP2_GPIO_LED1_RED, 0);
-        else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_RED\n");
+        if (gpio_request_array(igep_gpio_leds, ARRAY_SIZE(igep_gpio_leds))) {
+                pr_warning("IGEP v2: Could not obtain leds gpios\n");
+                return;
+        }
 
+        for (i = 0; i < ARRAY_SIZE(igep_gpio_leds); i++)
+                gpio_export(igep_gpio_leds[i].gpio, 0);
 }
 #endif
 
-static int igep2_twl_gpio_setup(struct device *dev,
+static struct gpio igep2_twl_gpios[] = {
+        { -EINVAL, GPIOF_IN,            "GPIO_EHCI_NOC"  },
+        { -EINVAL, GPIOF_OUT_INIT_LOW,  "GPIO_USBH_CPEN" },
+};
+
+static int igep_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int ret;
+
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         mmc[0].gpio_cd = gpio + 0;
         omap2_hsmmc_init(mmc);
 
-        /*
-         * REVISIT: need ehci-omap hooks for external VBUS
-         * power switch and overcurrent detect
-         */
-        if ((gpio_request(gpio + 1, "GPIO_EHCI_NOC") < 0) ||
-            (gpio_direction_input(gpio + 1) < 0))
-                pr_err("IGEP2: Could not obtain gpio for EHCI NOC");
-
-        /*
-         * TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN
-         * (out, active low)
-         */
-        if ((gpio_request(gpio + TWL4030_GPIO_MAX, "GPIO_USBH_CPEN") < 0) ||
-            (gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0) < 0))
-                pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
-
         /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
 #if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
-        if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
-            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0))
+        ret = gpio_request_one(gpio + TWL4030_GPIO_MAX + 1, GPIOF_OUT_INIT_HIGH,
+                               "gpio-led:green:d1");
+        if (ret == 0)
                 gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
         else
-                pr_warning("IGEP v2: Could not obtain gpio GPIO_LED1_GREEN\n");
+                pr_warning("IGEP: Could not obtain gpio GPIO_LED1_GREEN\n");
 #else
-        igep2_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
+        igep_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
 #endif
 
+        if (machine_is_igep0030())
+                return 0;
+
+        /*
+         * REVISIT: need ehci-omap hooks for external VBUS
+         * power switch and overcurrent detect
+         */
+        igep2_twl_gpios[0].gpio = gpio + 1;
+
+        /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */
+        igep2_twl_gpios[1].gpio = gpio + TWL4030_GPIO_MAX;
+
+        ret = gpio_request_array(igep2_twl_gpios, ARRAY_SIZE(igep2_twl_gpios));
+        if (ret < 0)
+                pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
+
         return 0;
 };
 
-static struct twl4030_gpio_platform_data igep2_twl4030_gpio_pdata = {
+static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
         .irq_end        = TWL4030_GPIO_IRQ_END,
         .use_leds       = true,
-        .setup          = igep2_twl_gpio_setup,
+        .setup          = igep_twl_gpio_setup,
 };
 
-static struct twl4030_usb_data igep2_usb_data = {
+static struct twl4030_usb_data igep_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
@@ -507,16 +502,17 @@ static struct regulator_init_data igep2_vpll2 = {
 
 static void __init igep2_display_init(void)
 {
-        if (gpio_request(IGEP2_GPIO_DVI_PUP, "GPIO_DVI_PUP") &&
-            gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1))
+        int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
+                                   "GPIO_DVI_PUP");
+        if (err)
                 pr_err("IGEP v2: Could not obtain gpio GPIO_DVI_PUP\n");
 }
 
-static struct platform_device *igep2_devices[] __initdata = {
-        &igep2_vwlan_device,
+static struct platform_device *igep_devices[] __initdata = {
+        &igep_vwlan_device,
 };
 
-static void __init igep2_init_early(void)
+static void __init igep_init_early(void)
 {
         omap2_init_common_infrastructure();
         omap2_init_common_devices(m65kxxxxam_sdrc_params,
@@ -561,27 +557,15 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
         .rep            = 1,
 };
 
-static struct twl4030_platform_data igep2_twldata = {
+static struct twl4030_platform_data igep_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
 
         /* platform_data for children goes here */
-        .usb            = &igep2_usb_data,
-        .codec          = &igep2_codec_data,
-        .gpio           = &igep2_twl4030_gpio_pdata,
-        .keypad         = &igep2_keypad_pdata,
-        .vmmc1          = &igep2_vmmc1,
-        .vpll2          = &igep2_vpll2,
-        .vio            = &igep2_vio,
-};
-
-static struct i2c_board_info __initdata igep2_i2c1_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &igep2_twldata,
-        },
+        .usb            = &igep_usb_data,
+        .gpio           = &igep_twl4030_gpio_pdata,
+        .vmmc1          = &igep_vmmc1,
+        .vio            = &igep_vio,
 };
 
 static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
@@ -590,32 +574,29 @@ static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
         },
 };
 
-static void __init igep2_i2c_init(void)
+static void __init igep_i2c_init(void)
 {
         int ret;
 
-        ret = omap_register_i2c_bus(1, 2600, igep2_i2c1_boardinfo,
-                ARRAY_SIZE(igep2_i2c1_boardinfo));
-        if (ret)
-                pr_warning("IGEP2: Could not register I2C1 bus (%d)\n", ret);
+        if (machine_is_igep0020()) {
+                /*
+                 * Bus 3 is attached to the DVI port where devices like the
+                 * pico DLP projector don't work reliably with 400kHz
+                 */
+                ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
+                                            ARRAY_SIZE(igep2_i2c3_boardinfo));
+                if (ret)
+                        pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
+
+                igep_twldata.codec      = &igep2_codec_data;
+                igep_twldata.keypad     = &igep2_keypad_pdata;
+                igep_twldata.vpll2      = &igep2_vpll2;
+        }
 
-        /*
-         * Bus 3 is attached to the DVI port where devices like the pico DLP
-         * projector don't work reliably with 400kHz
-         */
-        ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
-                ARRAY_SIZE(igep2_i2c3_boardinfo));
-        if (ret)
-                pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
+        omap3_pmic_init("twl4030", &igep_twldata);
 }
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
+static const struct usbhs_omap_board_data igep2_usbhs_bdata __initconst = {
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
@@ -626,6 +607,17 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
         .reset_gpio_port[2] = -EINVAL,
 };
 
+static const struct usbhs_omap_board_data igep3_usbhs_bdata __initconst = {
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
+        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+
+        .phy_reset = true,
+        .reset_gpio_port[0] = -EINVAL,
+        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
+        .reset_gpio_port[2] = -EINVAL,
+};
+
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -633,82 +625,95 @@ static struct omap_board_mux board_mux[] __initdata = {
 #endif
 
 #if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
+static struct gpio igep_wlan_bt_gpios[] __initdata = {
+        { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NPD"    },
+        { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NRESET" },
+        { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_BT_NRESET"   },
+};
 
-static void __init igep2_wlan_bt_init(void)
+static void __init igep_wlan_bt_init(void)
 {
-        unsigned npd, wreset, btreset;
+        int err;
 
         /* GPIO's for WLAN-BT combo depends on hardware revision */
         if (hwrev == IGEP2_BOARD_HWREV_B) {
-                npd = IGEP2_RB_GPIO_WIFI_NPD;
-                wreset = IGEP2_RB_GPIO_WIFI_NRESET;
-                btreset = IGEP2_RB_GPIO_BT_NRESET;
-        } else if (hwrev == IGEP2_BOARD_HWREV_C) {
-                npd = IGEP2_RC_GPIO_WIFI_NPD;
-                wreset = IGEP2_RC_GPIO_WIFI_NRESET;
-                btreset = IGEP2_RC_GPIO_BT_NRESET;
+                igep_wlan_bt_gpios[0].gpio = IGEP2_RB_GPIO_WIFI_NPD;
+                igep_wlan_bt_gpios[1].gpio = IGEP2_RB_GPIO_WIFI_NRESET;
+                igep_wlan_bt_gpios[2].gpio = IGEP2_RB_GPIO_BT_NRESET;
+        } else if (hwrev == IGEP2_BOARD_HWREV_C || machine_is_igep0030()) {
+                igep_wlan_bt_gpios[0].gpio = IGEP2_RC_GPIO_WIFI_NPD;
+                igep_wlan_bt_gpios[1].gpio = IGEP2_RC_GPIO_WIFI_NRESET;
+                igep_wlan_bt_gpios[2].gpio = IGEP2_RC_GPIO_BT_NRESET;
         } else
                 return;
 
-        /* Set GPIO's for  WLAN-BT combo module */
-        if ((gpio_request(npd, "GPIO_WIFI_NPD") == 0) &&
-            (gpio_direction_output(npd, 1) == 0)) {
-                gpio_export(npd, 0);
-        } else
-                pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NPD\n");
-
-        if ((gpio_request(wreset, "GPIO_WIFI_NRESET") == 0) &&
-            (gpio_direction_output(wreset, 1) == 0)) {
-                gpio_export(wreset, 0);
-                gpio_set_value(wreset, 0);
-                udelay(10);
-                gpio_set_value(wreset, 1);
-        } else
-                pr_warning("IGEP2: Could not obtain gpio GPIO_WIFI_NRESET\n");
+        err = gpio_request_array(igep_wlan_bt_gpios,
+                                 ARRAY_SIZE(igep_wlan_bt_gpios));
+        if (err) {
+                pr_warning("IGEP2: Could not obtain WIFI/BT gpios\n");
+                return;
+        }
+
+        gpio_export(igep_wlan_bt_gpios[0].gpio, 0);
+        gpio_export(igep_wlan_bt_gpios[1].gpio, 0);
+        gpio_export(igep_wlan_bt_gpios[2].gpio, 0);
+
+        gpio_set_value(igep_wlan_bt_gpios[1].gpio, 0);
+        udelay(10);
+        gpio_set_value(igep_wlan_bt_gpios[1].gpio, 1);
 
-        if ((gpio_request(btreset, "GPIO_BT_NRESET") == 0) &&
-            (gpio_direction_output(btreset, 1) == 0)) {
-                gpio_export(btreset, 0);
-        } else
-                pr_warning("IGEP2: Could not obtain gpio GPIO_BT_NRESET\n");
 }
 #else
-static inline void __init igep2_wlan_bt_init(void) { }
+static inline void __init igep_wlan_bt_init(void) { }
 #endif
 
-static void __init igep2_init(void)
+static void __init igep_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         /* Get IGEP2 hardware revision */
         igep2_get_revision();
         /* Register I2C busses and drivers */
-        igep2_i2c_init();
-        platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
-        omap_display_init(&igep2_dss_data);
+        igep_i2c_init();
+        platform_add_devices(igep_devices, ARRAY_SIZE(igep_devices));
         omap_serial_init();
-        usb_musb_init(&musb_board_data);
-        usbhs_init(&usbhs_bdata);
+        usb_musb_init(NULL);
 
-        igep2_flash_init();
-        igep2_leds_init();
-        igep2_display_init();
-        igep2_init_smsc911x();
+        igep_flash_init();
+        igep_leds_init();
 
         /*
          * WLAN-BT combo module from MuRata which has a Marvell WLAN
          * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
          */
-        igep2_wlan_bt_init();
+        igep_wlan_bt_init();
 
+        if (machine_is_igep0020()) {
+                omap_display_init(&igep2_dss_data);
+                igep2_display_init();
+                igep2_init_smsc911x();
+                usbhs_init(&igep2_usbhs_bdata);
+        } else {
+                usbhs_init(&igep3_usbhs_bdata);
+        }
 }
 
 MACHINE_START(IGEP0020, "IGEP v2 board")
         .boot_params    = 0x80000100,
         .reserve        = omap_reserve,
         .map_io         = omap3_map_io,
-        .init_early     = igep2_init_early,
+        .init_early     = igep_init_early,
+        .init_irq       = omap_init_irq,
+        .init_machine   = igep_init,
+        .timer          = &omap_timer,
+MACHINE_END
+
+MACHINE_START(IGEP0030, "IGEP OMAP3 module")
+        .boot_params    = 0x80000100,
+        .reserve        = omap_reserve,
+        .map_io         = omap3_map_io,
+        .init_early     = igep_init_early,
         .init_irq       = omap_init_irq,
-        .init_machine   = igep2_init,
+        .init_machine   = igep_init,
         .timer          = &omap_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
deleted file mode 100644
index 2cf86c3cb1a3..000000000000
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * Copyright (C) 2010 - ISEE 2007 SL
- *
- * Modified from mach-omap2/board-generic.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/i2c/twl.h>
-#include <linux/mmc/host.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <plat/board.h>
-#include <plat/common.h>
-#include <plat/gpmc.h>
-#include <plat/usb.h>
-#include <plat/onenand.h>
-
-#include "mux.h"
-#include "hsmmc.h"
-#include "sdram-numonyx-m65kxxxxam.h"
-
-#define IGEP3_GPIO_LED0_GREEN   54
-#define IGEP3_GPIO_LED0_RED     53
-#define IGEP3_GPIO_LED1_RED     16
-
-#define IGEP3_GPIO_WIFI_NPD     138
-#define IGEP3_GPIO_WIFI_NRESET  139
-#define IGEP3_GPIO_BT_NRESET    137
-
-#define IGEP3_GPIO_USBH_NRESET  183
-
-
-#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
-        defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
-
-#define ONENAND_MAP             0x20000000
-
-/*
- * x2 Flash built-in COMBO POP MEMORY
- * Since the device is equipped with two DataRAMs, and two-plane NAND
- * Flash memory array, these two component enables simultaneous program
- * of 4KiB. Plane1 has only even blocks such as block0, block2, block4
- * while Plane2 has only odd blocks such as block1, block3, block5.
- * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
- */
-
-static struct mtd_partition igep3_onenand_partitions[] = {
-        {
-                .name           = "X-Loader",
-                .offset         = 0,
-                .size           = 2 * (64*(2*2048))
-        },
-        {
-                .name           = "U-Boot",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 6 * (64*(2*2048)),
-        },
-        {
-                .name           = "Environment",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 2 * (64*(2*2048)),
-        },
-        {
-                .name           = "Kernel",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = 12 * (64*(2*2048)),
-        },
-        {
-                .name           = "File System",
-                .offset         = MTDPART_OFS_APPEND,
-                .size           = MTDPART_SIZ_FULL,
-        },
-};
-
-static struct omap_onenand_platform_data igep3_onenand_pdata = {
-        .parts = igep3_onenand_partitions,
-        .nr_parts = ARRAY_SIZE(igep3_onenand_partitions),
-        .onenand_setup = NULL,
-        .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
-};
-
-static struct platform_device igep3_onenand_device = {
-        .name           = "omap2-onenand",
-        .id             = -1,
-        .dev = {
-                .platform_data = &igep3_onenand_pdata,
-        },
-};
-
-static void __init igep3_flash_init(void)
-{
-        u8 cs = 0;
-        u8 onenandcs = GPMC_CS_NUM + 1;
-
-        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-                u32 ret;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                /* Check if NAND/oneNAND is configured */
-                if ((ret & 0xC00) == 0x800)
-                        /* NAND found */
-                        pr_err("IGEP3: Unsupported NAND found\n");
-                else {
-                        ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
-
-                        if ((ret & 0x3F) == (ONENAND_MAP >> 24))
-                                /* OneNAND found */
-                                onenandcs = cs;
-                }
-        }
-
-        if (onenandcs > GPMC_CS_NUM) {
-                pr_err("IGEP3: Unable to find configuration in GPMC\n");
-                return;
-        }
-
-        igep3_onenand_pdata.cs = onenandcs;
-
-        if (platform_device_register(&igep3_onenand_device) < 0)
-                pr_err("IGEP3: Unable to register OneNAND device\n");
-}
-
-#else
-static void __init igep3_flash_init(void) {}
-#endif
-
-static struct regulator_consumer_supply igep3_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
-
-/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
-static struct regulator_init_data igep3_vmmc1 = {
-        .constraints = {
-                .min_uV                 = 1850000,
-                .max_uV                 = 3150000,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep3_vmmc1_supply,
-};
-
-static struct regulator_consumer_supply igep3_vio_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
-
-static struct regulator_init_data igep3_vio = {
-        .constraints = {
-                .min_uV                 = 1800000,
-                .max_uV                 = 1800000,
-                .apply_uV               = 1,
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL
-                                        | REGULATOR_MODE_STANDBY,
-                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
-                                        | REGULATOR_CHANGE_MODE
-                                        | REGULATOR_CHANGE_STATUS,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep3_vio_supply,
-};
-
-static struct regulator_consumer_supply igep3_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
-
-static struct regulator_init_data igep3_vmmc2 = {
-        .constraints    = {
-                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
-                .always_on              = 1,
-        },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &igep3_vmmc2_supply,
-};
-
-static struct fixed_voltage_config igep3_vwlan = {
-        .supply_name            = "vwlan",
-        .microvolts             = 3300000,
-        .gpio                   = -EINVAL,
-        .enabled_at_boot        = 1,
-        .init_data              = &igep3_vmmc2,
-};
-
-static struct platform_device igep3_vwlan_device = {
-        .name   = "reg-fixed-voltage",
-        .id     = 0,
-        .dev    = {
-                .platform_data = &igep3_vwlan,
-        },
-};
-
-static struct omap2_hsmmc_info mmc[] = {
-        [0] = {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-        },
-#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
-        [1] = {
-                .mmc            = 2,
-                .caps           = MMC_CAP_4_BIT_DATA,
-                .gpio_cd        = -EINVAL,
-                .gpio_wp        = -EINVAL,
-        },
-#endif
-        {}      /* Terminator */
-};
-
-#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
-#include <linux/leds.h>
-
-static struct gpio_led igep3_gpio_leds[] = {
-        [0] = {
-                .name                   = "gpio-led:red:d0",
-                .gpio                   = IGEP3_GPIO_LED0_RED,
-                .default_trigger        = "default-off"
-        },
-        [1] = {
-                .name                   = "gpio-led:green:d0",
-                .gpio                   = IGEP3_GPIO_LED0_GREEN,
-                .default_trigger        = "default-off",
-        },
-        [2] = {
-                .name                   = "gpio-led:red:d1",
-                .gpio                   = IGEP3_GPIO_LED1_RED,
-                .default_trigger        = "default-off",
-        },
-        [3] = {
-                .name                   = "gpio-led:green:d1",
-                .default_trigger        = "heartbeat",
-                .gpio                   = -EINVAL, /* gets replaced */
-        },
-};
-
-static struct gpio_led_platform_data igep3_led_pdata = {
-        .leds           = igep3_gpio_leds,
-        .num_leds       = ARRAY_SIZE(igep3_gpio_leds),
-};
-
-static struct platform_device igep3_led_device = {
-         .name   = "leds-gpio",
-         .id     = -1,
-         .dev    = {
-                 .platform_data = &igep3_led_pdata,
-        },
-};
-
-static void __init igep3_leds_init(void)
-{
-        platform_device_register(&igep3_led_device);
-}
-
-#else
-static inline void igep3_leds_init(void)
-{
-        if ((gpio_request(IGEP3_GPIO_LED0_RED, "gpio-led:red:d0") == 0) &&
-            (gpio_direction_output(IGEP3_GPIO_LED0_RED, 1) == 0)) {
-                gpio_export(IGEP3_GPIO_LED0_RED, 0);
-                gpio_set_value(IGEP3_GPIO_LED0_RED, 1);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_RED\n");
-
-        if ((gpio_request(IGEP3_GPIO_LED0_GREEN, "gpio-led:green:d0") == 0) &&
-            (gpio_direction_output(IGEP3_GPIO_LED0_GREEN, 1) == 0)) {
-                gpio_export(IGEP3_GPIO_LED0_GREEN, 0);
-                gpio_set_value(IGEP3_GPIO_LED0_GREEN, 1);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_LED0_GREEN\n");
-
-        if ((gpio_request(IGEP3_GPIO_LED1_RED, "gpio-led:red:d1") == 0) &&
-                (gpio_direction_output(IGEP3_GPIO_LED1_RED, 1) == 0)) {
-                gpio_export(IGEP3_GPIO_LED1_RED, 0);
-                gpio_set_value(IGEP3_GPIO_LED1_RED, 1);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_RED\n");
-}
-#endif
-
-static int igep3_twl4030_gpio_setup(struct device *dev,
-                unsigned gpio, unsigned ngpio)
-{
-        /* gpio + 0 is "mmc0_cd" (input/IRQ) */
-        mmc[0].gpio_cd = gpio + 0;
-        omap2_hsmmc_init(mmc);
-
-        /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
-#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
-        if ((gpio_request(gpio+TWL4030_GPIO_MAX+1, "gpio-led:green:d1") == 0)
-            && (gpio_direction_output(gpio + TWL4030_GPIO_MAX + 1, 1) == 0)) {
-                gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
-                gpio_set_value(gpio + TWL4030_GPIO_MAX + 1, 0);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_LED1_GREEN\n");
-#else
-        igep3_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
-#endif
-
-        return 0;
-};
-
-static struct twl4030_gpio_platform_data igep3_twl4030_gpio_pdata = {
-        .gpio_base      = OMAP_MAX_GPIO_LINES,
-        .irq_base       = TWL4030_GPIO_IRQ_BASE,
-        .irq_end        = TWL4030_GPIO_IRQ_END,
-        .use_leds       = true,
-        .setup          = igep3_twl4030_gpio_setup,
-};
-
-static struct twl4030_usb_data igep3_twl4030_usb_data = {
-        .usb_mode       = T2_USB_MODE_ULPI,
-};
-
-static struct platform_device *igep3_devices[] __initdata = {
-        &igep3_vwlan_device,
-};
-
-static void __init igep3_init_early(void)
-{
-        omap2_init_common_infrastructure();
-        omap2_init_common_devices(m65kxxxxam_sdrc_params,
-                                  m65kxxxxam_sdrc_params);
-}
-
-static struct twl4030_platform_data igep3_twl4030_pdata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
-        /* platform_data for children goes here */
-        .usb            = &igep3_twl4030_usb_data,
-        .gpio           = &igep3_twl4030_gpio_pdata,
-        .vmmc1          = &igep3_vmmc1,
-        .vio            = &igep3_vio,
-};
-
-static struct i2c_board_info __initdata igep3_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &igep3_twl4030_pdata,
-        },
-};
-
-static int __init igep3_i2c_init(void)
-{
-        omap_register_i2c_bus(1, 2600, igep3_i2c_boardinfo,
-                        ARRAY_SIZE(igep3_i2c_boardinfo));
-
-        return 0;
-}
-
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type = MUSB_INTERFACE_ULPI,
-        .mode           = MUSB_OTG,
-        .power          = 100,
-};
-
-#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
-
-static void __init igep3_wifi_bt_init(void)
-{
-        /* Configure MUX values for W-LAN + Bluetooth GPIO's */
-        omap_mux_init_gpio(IGEP3_GPIO_WIFI_NPD, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(IGEP3_GPIO_WIFI_NRESET, OMAP_PIN_OUTPUT);
-        omap_mux_init_gpio(IGEP3_GPIO_BT_NRESET, OMAP_PIN_OUTPUT);
-
-        /* Set GPIO's for  W-LAN + Bluetooth combo module */
-        if ((gpio_request(IGEP3_GPIO_WIFI_NPD, "GPIO_WIFI_NPD") == 0) &&
-            (gpio_direction_output(IGEP3_GPIO_WIFI_NPD, 1) == 0)) {
-                gpio_export(IGEP3_GPIO_WIFI_NPD, 0);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NPD\n");
-
-        if ((gpio_request(IGEP3_GPIO_WIFI_NRESET, "GPIO_WIFI_NRESET") == 0) &&
-            (gpio_direction_output(IGEP3_GPIO_WIFI_NRESET, 1) == 0)) {
-                gpio_export(IGEP3_GPIO_WIFI_NRESET, 0);
-                gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 0);
-                udelay(10);
-                gpio_set_value(IGEP3_GPIO_WIFI_NRESET, 1);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_WIFI_NRESET\n");
-
-        if ((gpio_request(IGEP3_GPIO_BT_NRESET, "GPIO_BT_NRESET") == 0) &&
-            (gpio_direction_output(IGEP3_GPIO_BT_NRESET, 1) == 0)) {
-                gpio_export(IGEP3_GPIO_BT_NRESET, 0);
-        } else
-                pr_warning("IGEP3: Could not obtain gpio GPIO_BT_NRESET\n");
-}
-#else
-void __init igep3_wifi_bt_init(void) {}
-#endif
-
-static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
-        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
-        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
-
-        .phy_reset = true,
-        .reset_gpio_port[0] = -EINVAL,
-        .reset_gpio_port[1] = IGEP3_GPIO_USBH_NRESET,
-        .reset_gpio_port[2] = -EINVAL,
-};
-
-#ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
-        OMAP3_MUX(I2C2_SDA, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
-        { .reg_offset = OMAP_MUX_TERMINATOR },
-};
-#endif
-
-static void __init igep3_init(void)
-{
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-
-        /* Register I2C busses and drivers */
-        igep3_i2c_init();
-        platform_add_devices(igep3_devices, ARRAY_SIZE(igep3_devices));
-        omap_serial_init();
-        usb_musb_init(&musb_board_data);
-        usbhs_init(&usbhs_bdata);
-
-        igep3_flash_init();
-        igep3_leds_init();
-
-        /*
-         * WLAN-BT combo module from MuRata which has a Marvell WLAN
-         * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
-         */
-        igep3_wifi_bt_init();
-
-}
-
-MACHINE_START(IGEP0030, "IGEP OMAP3 module")
-        .boot_params    = 0x80000100,
-        .reserve        = omap_reserve,
-        .map_io         = omap3_map_io,
-        .init_early     = igep3_init_early,
-        .init_irq       = omap_init_irq,
-        .init_machine   = igep3_init,
-        .timer          = &omap_timer,
-MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index e2ba77957a8c..f7d6038075f0 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -22,7 +22,6 @@
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/io.h>
@@ -43,47 +42,19 @@
 
 #include <asm/delay.h>
 #include <plat/usb.h>
+#include <plat/gpmc-smsc911x.h>
 
 #include "board-flash.h"
 #include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
+#include "common-board-devices.h"
 
 #define LDP_SMSC911X_CS         1
 #define LDP_SMSC911X_GPIO       152
 #define DEBUG_BASE              0x08000000
 #define LDP_ETHR_START          DEBUG_BASE
 
-static struct resource ldp_smsc911x_resources[] = {
-        [0] = {
-                .start  = LDP_ETHR_START,
-                .end    = LDP_ETHR_START + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = 0,
-                .end    = 0,
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct smsc911x_platform_config ldp_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device ldp_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(ldp_smsc911x_resources),
-        .resource       = ldp_smsc911x_resources,
-        .dev            = {
-                .platform_data = &ldp_smsc911x_config,
-        },
-};
-
 static uint32_t board_keymap[] = {
         KEY(0, 0, KEY_1),
         KEY(1, 0, KEY_2),
@@ -197,82 +168,16 @@ static struct platform_device ldp_gpio_keys_device = {
         },
 };
 
-static int ts_gpio;
-
-/**
- * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq
- *
- * @return - void. If request gpio fails then Flag KERN_ERR.
- */
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(ts_gpio, "ads7846 irq") < 0) {
-                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
-                return;
-        }
-
-        gpio_direction_input(ts_gpio);
-        gpio_set_debounce(ts_gpio, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(ts_gpio);
-}
-
-static struct ads7846_platform_data tsc2046_config __initdata = {
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct omap2_mcspi_device_config tsc2046_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info ldp_spi_board_info[] __initdata = {
-        [0] = {
-                /*
-                 * TSC2046 operates at a max freqency of 2MHz, so
-                 * operate slightly below at 1.5MHz
-                 */
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &tsc2046_mcspi_config,
-                .irq                    = 0,
-                .platform_data          = &tsc2046_config,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = LDP_SMSC911X_CS,
+        .gpio_irq       = LDP_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT,
 };
 
 static inline void __init ldp_init_smsc911x(void)
 {
-        int eth_cs;
-        unsigned long cs_mem_base;
-        int eth_gpio = 0;
-
-        eth_cs = LDP_SMSC911X_CS;
-
-        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
-                return;
-        }
-
-        ldp_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        ldp_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-        udelay(100);
-
-        eth_gpio = LDP_SMSC911X_GPIO;
-
-        ldp_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
-
-        if (gpio_request(eth_gpio, "smsc911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                                eth_gpio);
-                return;
-        }
-        gpio_direction_input(eth_gpio);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 static struct platform_device ldp_lcd_device = {
@@ -360,19 +265,9 @@ static struct twl4030_platform_data ldp_twldata = {
         .keypad         = &ldp_kp_twl4030_data,
 };
 
-static struct i2c_board_info __initdata ldp_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &ldp_twldata,
-        },
-};
-
 static int __init omap_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, ldp_i2c_boardinfo,
-                        ARRAY_SIZE(ldp_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &ldp_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
@@ -389,7 +284,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
 };
 
 static struct platform_device *ldp_devices[] __initdata = {
-        &ldp_smsc911x_device,
         &ldp_lcd_device,
         &ldp_gpio_keys_device,
 };
@@ -400,12 +294,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static struct mtd_partition ldp_nand_partitions[] = {
         /* All the partition sizes are listed in terms of NAND block size */
         {
@@ -446,13 +334,9 @@ static void __init omap_ldp_init(void)
         ldp_init_smsc911x();
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
-        ts_gpio = 54;
-        ldp_spi_board_info[0].irq = gpio_to_irq(ts_gpio);
-        spi_register_board_info(ldp_spi_board_info,
-                                ARRAY_SIZE(ldp_spi_board_info));
-        ads7846_dev_init();
+        omap_ads7846_init(1, 54, 310, NULL);
         omap_serial_init();
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         board_nand_init(ldp_nand_partitions,
                 ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e710cd9e079b..8d74318ed495 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -106,14 +106,13 @@ static void __init n8x0_usb_init(void)
         static char     announce[] __initdata = KERN_INFO "TUSB 6010\n";
 
         /* PM companion chip power control pin */
-        ret = gpio_request(TUSB6010_GPIO_ENABLE, "TUSB6010 enable");
+        ret = gpio_request_one(TUSB6010_GPIO_ENABLE, GPIOF_OUT_INIT_LOW,
+                               "TUSB6010 enable");
         if (ret != 0) {
                 printk(KERN_ERR "Could not get TUSB power GPIO%i\n",
                        TUSB6010_GPIO_ENABLE);
                 return;
         }
-        gpio_direction_output(TUSB6010_GPIO_ENABLE, 0);
-
         tusb_set_power(0);
 
         ret = tusb6010_setup_interface(&tusb_data, TUSB6010_REFCLK_19, 2,
@@ -494,8 +493,12 @@ static struct omap_mmc_platform_data mmc1_data = {
 
 static struct omap_mmc_platform_data *mmc_data[OMAP24XX_NR_MMC];
 
-static void __init n8x0_mmc_init(void)
+static struct gpio n810_emmc_gpios[] __initdata = {
+        { N810_EMMC_VSD_GPIO, GPIOF_OUT_INIT_LOW,  "MMC slot 2 Vddf" },
+        { N810_EMMC_VIO_GPIO, GPIOF_OUT_INIT_LOW,  "MMC slot 2 Vdd"  },
+};
 
+static void __init n8x0_mmc_init(void)
 {
         int err;
 
@@ -512,27 +515,18 @@ static void __init n8x0_mmc_init(void)
                 mmc1_data.slots[1].ban_openended = 1;
         }
 
-        err = gpio_request(N8X0_SLOT_SWITCH_GPIO, "MMC slot switch");
+        err = gpio_request_one(N8X0_SLOT_SWITCH_GPIO, GPIOF_OUT_INIT_LOW,
+                               "MMC slot switch");
         if (err)
                 return;
 
-        gpio_direction_output(N8X0_SLOT_SWITCH_GPIO, 0);
-
         if (machine_is_nokia_n810()) {
-                err = gpio_request(N810_EMMC_VSD_GPIO, "MMC slot 2 Vddf");
-                if (err) {
-                        gpio_free(N8X0_SLOT_SWITCH_GPIO);
-                        return;
-                }
-                gpio_direction_output(N810_EMMC_VSD_GPIO, 0);
-
-                err = gpio_request(N810_EMMC_VIO_GPIO, "MMC slot 2 Vdd");
+                err = gpio_request_array(n810_emmc_gpios,
+                                         ARRAY_SIZE(n810_emmc_gpios));
                 if (err) {
                         gpio_free(N8X0_SLOT_SWITCH_GPIO);
-                        gpio_free(N810_EMMC_VSD_GPIO);
                         return;
                 }
-                gpio_direction_output(N810_EMMC_VIO_GPIO, 0);
         }
 
         mmc_data[0] = &mmc1_data;
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 33007fd4a083..be71426359f2 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -41,8 +41,8 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
@@ -52,6 +52,7 @@
 #include "hsmmc.h"
 #include "timer-gp.h"
 #include "pm.h"
+#include "common-board-devices.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
@@ -79,6 +80,12 @@ static u8 omap3_beagle_get_rev(void)
         return omap3_beagle_version;
 }
 
+static struct gpio omap3_beagle_rev_gpios[] __initdata = {
+        { 171, GPIOF_IN, "rev_id_0"    },
+        { 172, GPIOF_IN, "rev_id_1" },
+        { 173, GPIOF_IN, "rev_id_2"    },
+};
+
 static void __init omap3_beagle_init_rev(void)
 {
         int ret;
@@ -88,21 +95,13 @@ static void __init omap3_beagle_init_rev(void)
         omap_mux_init_gpio(172, OMAP_PIN_INPUT_PULLUP);
         omap_mux_init_gpio(173, OMAP_PIN_INPUT_PULLUP);
 
-        ret = gpio_request(171, "rev_id_0");
-        if (ret < 0)
-                goto fail0;
-
-        ret = gpio_request(172, "rev_id_1");
-        if (ret < 0)
-                goto fail1;
-
-        ret = gpio_request(173, "rev_id_2");
-        if (ret < 0)
-                goto fail2;
-
-        gpio_direction_input(171);
-        gpio_direction_input(172);
-        gpio_direction_input(173);
+        ret = gpio_request_array(omap3_beagle_rev_gpios,
+                                 ARRAY_SIZE(omap3_beagle_rev_gpios));
+        if (ret < 0) {
+                printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
+                omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
+                return;
+        }
 
         beagle_rev = gpio_get_value(171) | (gpio_get_value(172) << 1)
                         | (gpio_get_value(173) << 2);
@@ -128,18 +127,6 @@ static void __init omap3_beagle_init_rev(void)
                 printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
                 omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
         }
-
-        return;
-
-fail2:
-        gpio_free(172);
-fail1:
-        gpio_free(171);
-fail0:
-        printk(KERN_ERR "Unable to get revision detection GPIO pins\n");
-        omap3_beagle_version = OMAP3BEAGLE_BOARD_UNKN;
-
-        return;
 }
 
 static struct mtd_partition omap3beagle_nand_partitions[] = {
@@ -173,15 +160,6 @@ static struct mtd_partition omap3beagle_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data omap3beagle_nand_data = {
-        .options        = NAND_BUSWIDTH_16,
-        .parts          = omap3beagle_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(omap3beagle_nand_partitions),
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-        .nand_setup     = NULL,
-        .dev_ready      = NULL,
-};
-
 /* DSS */
 
 static int beagle_enable_dvi(struct omap_dss_device *dssdev)
@@ -243,13 +221,10 @@ static void __init beagle_display_init(void)
 {
         int r;
 
-        r = gpio_request(beagle_dvi_device.reset_gpio, "DVI reset");
-        if (r < 0) {
+        r = gpio_request_one(beagle_dvi_device.reset_gpio, GPIOF_OUT_INIT_LOW,
+                             "DVI reset");
+        if (r < 0)
                 printk(KERN_ERR "Unable to get DVI reset GPIO\n");
-                return;
-        }
-
-        gpio_direction_output(beagle_dvi_device.reset_gpio, 0);
 }
 
 #include "sdram-micron-mt46h32m32lf-6.h"
@@ -276,7 +251,7 @@ static struct gpio_led gpio_leds[];
 static int beagle_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        int r;
+        int r, usb_pwr_level;
 
         if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
                 mmc[0].gpio_wp = -EINVAL;
@@ -295,66 +270,46 @@ static int beagle_twl_gpio_setup(struct device *dev,
         beagle_vmmc1_supply.dev = mmc[0].dev;
         beagle_vsim_supply.dev = mmc[0].dev;
 
-        /* REVISIT: need ehci-omap hooks for external VBUS
-         * power switch and overcurrent detect
-         */
-        if (omap3_beagle_get_rev() != OMAP3BEAGLE_BOARD_XM) {
-                r = gpio_request(gpio + 1, "EHCI_nOC");
-                if (!r) {
-                        r = gpio_direction_input(gpio + 1);
-                        if (r)
-                                gpio_free(gpio + 1);
-                }
-                if (r)
-                        pr_err("%s: unable to configure EHCI_nOC\n", __func__);
-        }
-
         /*
          * TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
          * high / others active low)
-         */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
-        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM)
-                gpio_direction_output(gpio + TWL4030_GPIO_MAX, 1);
-        else
-                gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
-
-        /* DVI reset GPIO is different between beagle revisions */
-        if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM)
-                beagle_dvi_device.reset_gpio = 129;
-        else
-                beagle_dvi_device.reset_gpio = 170;
-
-        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
-        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
-
-        /*
-         * gpio + 1 on Xm controls the TFP410's enable line (active low)
-         * gpio + 2 control varies depending on the board rev as follows:
-         * P7/P8 revisions(prototype): Camera EN
-         * A2+ revisions (production): LDO (supplies DVI, serial, led blocks)
+         * DVI reset GPIO is different between beagle revisions
          */
         if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
-                r = gpio_request(gpio + 1, "nDVI_PWR_EN");
-                if (!r) {
-                        r = gpio_direction_output(gpio + 1, 0);
-                        if (r)
-                                gpio_free(gpio + 1);
-                }
+                usb_pwr_level = GPIOF_OUT_INIT_HIGH;
+                beagle_dvi_device.reset_gpio = 129;
+                /*
+                 * gpio + 1 on Xm controls the TFP410's enable line (active low)
+                 * gpio + 2 control varies depending on the board rev as below:
+                 * P7/P8 revisions(prototype): Camera EN
+                 * A2+ revisions (production): LDO (DVI, serial, led blocks)
+                 */
+                r = gpio_request_one(gpio + 1, GPIOF_OUT_INIT_LOW,
+                                     "nDVI_PWR_EN");
                 if (r)
                         pr_err("%s: unable to configure nDVI_PWR_EN\n",
                                 __func__);
-                r = gpio_request(gpio + 2, "DVI_LDO_EN");
-                if (!r) {
-                        r = gpio_direction_output(gpio + 2, 1);
-                        if (r)
-                                gpio_free(gpio + 2);
-                }
+                r = gpio_request_one(gpio + 2, GPIOF_OUT_INIT_HIGH,
+                                     "DVI_LDO_EN");
                 if (r)
                         pr_err("%s: unable to configure DVI_LDO_EN\n",
                                 __func__);
+        } else {
+                usb_pwr_level = GPIOF_OUT_INIT_LOW;
+                beagle_dvi_device.reset_gpio = 170;
+                /*
+                 * REVISIT: need ehci-omap hooks for external VBUS
+                 * power switch and overcurrent detect
+                 */
+                if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
+                        pr_err("%s: unable to configure EHCI_nOC\n", __func__);
         }
 
+        gpio_request_one(gpio + TWL4030_GPIO_MAX, usb_pwr_level, "nEN_USB_PWR");
+
+        /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+        gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+
         return 0;
 }
 
@@ -453,15 +408,6 @@ static struct twl4030_platform_data beagle_twldata = {
         .vpll2          = &beagle_vpll2,
 };
 
-static struct i2c_board_info __initdata beagle_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &beagle_twldata,
-        },
-};
-
 static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
        {
                I2C_BOARD_INFO("eeprom", 0x50),
@@ -470,8 +416,7 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
 
 static int __init omap3_beagle_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo,
-                        ARRAY_SIZE(beagle_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &beagle_twldata);
         /* Bus 3 is attached to the DVI port where devices like the pico DLP
          * projector don't work reliably with 400kHz */
         omap_register_i2c_bus(3, 100, beagle_i2c_eeprom, ARRAY_SIZE(beagle_i2c_eeprom));
@@ -551,39 +496,6 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
         &keys_gpio,
 };
 
-static void __init omap3beagle_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                omap3beagle_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&omap3beagle_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
@@ -602,12 +514,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init beagle_opp_init(void)
 {
         int r = 0;
@@ -665,13 +571,13 @@ static void __init omap3_beagle_init(void)
         omap_serial_init();
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
-        gpio_request(170, "DVI_nPD");
         /* REVISIT leave DVI powered down until it's needed ... */
-        gpio_direction_output(170, true);
+        gpio_request_one(170, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
 
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        omap3beagle_flash_init();
+        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3beagle_nand_partitions,
+                             ARRAY_SIZE(omap3beagle_nand_partitions));
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5a1a916e5cc8..b4d43464a303 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -44,12 +44,13 @@
 #include <plat/usb.h>
 #include <plat/common.h>
 #include <plat/mcspi.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define OMAP3_EVM_TS_GPIO       175
 #define OMAP3_EVM_EHCI_VBUS     22
@@ -101,49 +102,20 @@ static void __init omap3_evm_get_revision(void)
 }
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-static struct resource omap3evm_smsc911x_resources[] = {
-        [0] =   {
-                .start  = OMAP3EVM_ETHR_START,
-                .end    = (OMAP3EVM_ETHR_START + OMAP3EVM_ETHR_SIZE - 1),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] =   {
-                .start  = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ),
-                .end    = OMAP_GPIO_IRQ(OMAP3EVM_ETHR_GPIO_IRQ),
-                .flags  = (IORESOURCE_IRQ | IRQF_TRIGGER_LOW),
-        },
-};
+#include <plat/gpmc-smsc911x.h>
 
-static struct smsc911x_platform_config smsc911x_config = {
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS),
-};
-
-static struct platform_device omap3evm_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(omap3evm_smsc911x_resources),
-        .resource       = &omap3evm_smsc911x_resources[0],
-        .dev            = {
-                .platform_data = &smsc911x_config,
-        },
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = OMAP3EVM_SMSC911X_CS,
+        .gpio_irq       = OMAP3EVM_ETHR_GPIO_IRQ,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 };
 
 static inline void __init omap3evm_init_smsc911x(void)
 {
-        int eth_cs, eth_rst;
         struct clk *l3ck;
         unsigned int rate;
 
-        if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
-                eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
-        else
-                eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
-
-        eth_cs = OMAP3EVM_SMSC911X_CS;
-
         l3ck = clk_get(NULL, "l3_ck");
         if (IS_ERR(l3ck))
                 rate = 100000000;
@@ -152,33 +124,13 @@ static inline void __init omap3evm_init_smsc911x(void)
 
         /* Configure ethernet controller reset gpio */
         if (cpu_is_omap3430()) {
-                if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
-                        pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
-                                        eth_rst);
-                        return;
-                }
-
-                if (gpio_direction_output(eth_rst, 1) < 0) {
-                        pr_err(KERN_ERR "Failed to set direction of %d for" \
-                                        " smsc911x\n", eth_rst);
-                        return;
-                }
-                /* reset pulse to ethernet controller*/
-                usleep_range(150, 220);
-                gpio_set_value(eth_rst, 0);
-                usleep_range(150, 220);
-                gpio_set_value(eth_rst, 1);
-                usleep_range(1, 2);
-        }
-
-        if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                        OMAP3EVM_ETHR_GPIO_IRQ);
-                return;
+                if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
+                        smsc911x_cfg.gpio_reset = OMAP3EVM_GEN1_ETHR_GPIO_RST;
+                else
+                        smsc911x_cfg.gpio_reset = OMAP3EVM_GEN2_ETHR_GPIO_RST;
         }
 
-        gpio_direction_input(OMAP3EVM_ETHR_GPIO_IRQ);
-        platform_device_register(&omap3evm_smsc911x_device);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 #else
@@ -197,6 +149,15 @@ static inline void __init omap3evm_init_smsc911x(void) { return; }
 #define OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO 210
 #define OMAP3EVM_DVI_PANEL_EN_GPIO      199
 
+static struct gpio omap3_evm_dss_gpios[] __initdata = {
+        { OMAP3EVM_LCD_PANEL_RESB,  GPIOF_OUT_INIT_HIGH, "lcd_panel_resb"  },
+        { OMAP3EVM_LCD_PANEL_INI,   GPIOF_OUT_INIT_HIGH, "lcd_panel_ini"   },
+        { OMAP3EVM_LCD_PANEL_QVGA,  GPIOF_OUT_INIT_LOW,  "lcd_panel_qvga"  },
+        { OMAP3EVM_LCD_PANEL_LR,    GPIOF_OUT_INIT_HIGH, "lcd_panel_lr"    },
+        { OMAP3EVM_LCD_PANEL_UD,    GPIOF_OUT_INIT_HIGH, "lcd_panel_ud"    },
+        { OMAP3EVM_LCD_PANEL_ENVDD, GPIOF_OUT_INIT_LOW,  "lcd_panel_envdd" },
+};
+
 static int lcd_enabled;
 static int dvi_enabled;
 
@@ -204,61 +165,10 @@ static void __init omap3_evm_display_init(void)
 {
         int r;
 
-        r = gpio_request(OMAP3EVM_LCD_PANEL_RESB, "lcd_panel_resb");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_resb\n");
-                return;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_RESB, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_INI, "lcd_panel_ini");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_ini\n");
-                goto err_1;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_INI, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_QVGA, "lcd_panel_qvga");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_qvga\n");
-                goto err_2;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_QVGA, 0);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_LR, "lcd_panel_lr");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_lr\n");
-                goto err_3;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_LR, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_UD, "lcd_panel_ud");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_ud\n");
-                goto err_4;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_UD, 1);
-
-        r = gpio_request(OMAP3EVM_LCD_PANEL_ENVDD, "lcd_panel_envdd");
-        if (r) {
-                printk(KERN_ERR "failed to get lcd_panel_envdd\n");
-                goto err_5;
-        }
-        gpio_direction_output(OMAP3EVM_LCD_PANEL_ENVDD, 0);
-
-        return;
-
-err_5:
-        gpio_free(OMAP3EVM_LCD_PANEL_UD);
-err_4:
-        gpio_free(OMAP3EVM_LCD_PANEL_LR);
-err_3:
-        gpio_free(OMAP3EVM_LCD_PANEL_QVGA);
-err_2:
-        gpio_free(OMAP3EVM_LCD_PANEL_INI);
-err_1:
-        gpio_free(OMAP3EVM_LCD_PANEL_RESB);
-
+        r = gpio_request_array(omap3_evm_dss_gpios,
+                               ARRAY_SIZE(omap3_evm_dss_gpios));
+        if (r)
+                printk(KERN_ERR "failed to get lcd_panel_* gpios\n");
 }
 
 static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
@@ -448,7 +358,7 @@ static struct platform_device leds_gpio = {
 static int omap3evm_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
-        int r;
+        int r, lcd_bl_en;
 
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         omap_mux_init_gpio(63, OMAP_PIN_INPUT);
@@ -465,16 +375,14 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
          */
 
         /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
-        if (!r)
-                r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
-                        (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
+        lcd_bl_en = get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2 ?
+                GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
+        r = gpio_request_one(gpio + TWL4030_GPIO_MAX, lcd_bl_en, "EN_LCD_BKL");
         if (r)
                 printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
 
         /* gpio + 7 == DVI Enable */
-        gpio_request(gpio + 7, "EN_DVI");
-        gpio_direction_output(gpio + 7, 0);
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
 
         /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -652,78 +560,18 @@ static struct twl4030_platform_data omap3evm_twldata = {
         .vdac           = &omap3_evm_vdac,
         .vpll2          = &omap3_evm_vpll2,
         .vio            = &omap3evm_vio,
-};
-
-static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &omap3evm_twldata,
-        },
+        .vmmc1          = &omap3evm_vmmc1,
+        .vsim           = &omap3evm_vsim,
 };
 
 static int __init omap3_evm_i2c_init(void)
 {
-        /*
-         * REVISIT: These entries can be set in omap3evm_twl_data
-         * after a merge with MFD tree
-         */
-        omap3evm_twldata.vmmc1 = &omap3evm_vmmc1;
-        omap3evm_twldata.vsim = &omap3evm_vsim;
-
-        omap_register_i2c_bus(1, 2600, omap3evm_i2c_boardinfo,
-                        ARRAY_SIZE(omap3evm_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &omap3evm_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
 }
 
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(OMAP3_EVM_TS_GPIO, "ADS7846 pendown") < 0)
-                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
-
-        gpio_direction_input(OMAP3_EVM_TS_GPIO);
-        gpio_set_debounce(OMAP3_EVM_TS_GPIO, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_EVM_TS_GPIO);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .settle_delay_usecs     = 150,
-        .wakeup                         = true,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info omap3evm_spi_board_info[] = {
-        [0] = {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_EVM_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        },
-};
-
 static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 };
 
@@ -825,6 +673,11 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 100,
 };
 
+static struct gpio omap3_evm_ehci_gpios[] __initdata = {
+        { OMAP3_EVM_EHCI_VBUS,   GPIOF_OUT_INIT_HIGH,  "enable EHCI VBUS" },
+        { OMAP3_EVM_EHCI_SELECT, GPIOF_OUT_INIT_LOW,   "select EHCI port" },
+};
+
 static void __init omap3_evm_init(void)
 {
         omap3_evm_get_revision();
@@ -841,9 +694,6 @@ static void __init omap3_evm_init(void)
 
         omap_display_init(&omap3_evm_dss_data);
 
-        spi_register_board_info(omap3evm_spi_board_info,
-                                ARRAY_SIZE(omap3evm_spi_board_info));
-
         omap_serial_init();
 
         /* OMAP3EVM uses ISP1504 phy and so register nop transceiver */
@@ -851,16 +701,12 @@ static void __init omap3_evm_init(void)
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) {
                 /* enable EHCI VBUS using GPIO22 */
-                omap_mux_init_gpio(22, OMAP_PIN_INPUT_PULLUP);
-                gpio_request(OMAP3_EVM_EHCI_VBUS, "enable EHCI VBUS");
-                gpio_direction_output(OMAP3_EVM_EHCI_VBUS, 0);
-                gpio_set_value(OMAP3_EVM_EHCI_VBUS, 1);
-
+                omap_mux_init_gpio(OMAP3_EVM_EHCI_VBUS, OMAP_PIN_INPUT_PULLUP);
                 /* Select EHCI port on main board */
-                omap_mux_init_gpio(61, OMAP_PIN_INPUT_PULLUP);
-                gpio_request(OMAP3_EVM_EHCI_SELECT, "select EHCI port");
-                gpio_direction_output(OMAP3_EVM_EHCI_SELECT, 0);
-                gpio_set_value(OMAP3_EVM_EHCI_SELECT, 0);
+                omap_mux_init_gpio(OMAP3_EVM_EHCI_SELECT,
+                                   OMAP_PIN_INPUT_PULLUP);
+                gpio_request_array(omap3_evm_ehci_gpios,
+                                   ARRAY_SIZE(omap3_evm_ehci_gpios));
 
                 /* setup EHCI phy reset config */
                 omap_mux_init_gpio(21, OMAP_PIN_INPUT_PULLUP);
@@ -876,7 +722,7 @@ static void __init omap3_evm_init(void)
         }
         usb_musb_init(&musb_board_data);
         usbhs_init(&usbhs_bdata);
-        ads7846_dev_init();
+        omap_ads7846_init(1, OMAP3_EVM_TS_GPIO, 310, NULL);
         omap3evm_init_smsc911x();
         omap3_evm_display_init();
 
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index b726943d7c93..60d9be49dbab 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -37,6 +37,7 @@
 #include "hsmmc.h"
 #include "timer-gp.h"
 #include "control.h"
+#include "common-board-devices.h"
 
 #include <plat/mux.h>
 #include <plat/board.h>
@@ -93,19 +94,9 @@ static struct twl4030_platform_data omap3logic_twldata = {
         .vmmc1          = &omap3logic_vmmc1,
 };
 
-static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &omap3logic_twldata,
-        },
-};
-
 static int __init omap3logic_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo,
-                                ARRAY_SIZE(omap3logic_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &omap3logic_twldata);
         return 0;
 }
 
@@ -147,7 +138,6 @@ static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
         .cs             = OMAP3LOGIC_SMSC911X_CS,
         .gpio_irq       = -EINVAL,
         .gpio_reset     = -EINVAL,
-        .flags          = IORESOURCE_IRQ_LOWLEVEL,
 };
 
 /* TODO/FIXME (comment by Peter Barada, LogicPD):
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 07dba888f450..1d10736c6d3c 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -22,7 +22,6 @@
 #include <linux/platform_device.h>
 
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
 #include <linux/wl12xx.h>
@@ -46,12 +45,13 @@
 #include <mach/hardware.h>
 #include <plat/mcspi.h>
 #include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/nand.h>
 
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define PANDORA_WIFI_IRQ_GPIO           21
 #define PANDORA_WIFI_NRESET_GPIO        23
@@ -305,24 +305,13 @@ static int omap3pandora_twl_gpio_setup(struct device *dev,
 
         /* gpio + 13 drives 32kHz buffer for wifi module */
         gpio_32khz = gpio + 13;
-        ret = gpio_request(gpio_32khz, "wifi 32kHz");
+        ret = gpio_request_one(gpio_32khz, GPIOF_OUT_INIT_HIGH, "wifi 32kHz");
         if (ret < 0) {
                 pr_err("Cannot get GPIO line %d, ret=%d\n", gpio_32khz, ret);
-                goto fail;
-        }
-
-        ret = gpio_direction_output(gpio_32khz, 1);
-        if (ret < 0) {
-                pr_err("Cannot set GPIO line %d, ret=%d\n", gpio_32khz, ret);
-                goto fail_direction;
+                return -ENODEV;
         }
 
         return 0;
-
-fail_direction:
-        gpio_free(gpio_32khz);
-fail:
-        return -ENODEV;
 }
 
 static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
@@ -544,15 +533,6 @@ static struct twl4030_platform_data omap3pandora_twldata = {
         .bci            = &pandora_bci_data,
 };
 
-static struct i2c_board_info __initdata omap3pandora_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65950", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &omap3pandora_twldata,
-        },
-};
-
 static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
         {
                 I2C_BOARD_INFO("bq27500", 0x55),
@@ -562,61 +542,15 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
 
 static int __init omap3pandora_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, omap3pandora_i2c_boardinfo,
-                        ARRAY_SIZE(omap3pandora_i2c_boardinfo));
+        omap3_pmic_init("tps65950", &omap3pandora_twldata);
         /* i2c2 pins are not connected */
         omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
                         ARRAY_SIZE(omap3pandora_i2c3_boardinfo));
         return 0;
 }
 
-static void __init omap3pandora_ads7846_init(void)
-{
-        int gpio = OMAP3_PANDORA_TS_GPIO;
-        int ret;
-
-        ret = gpio_request(gpio, "ads7846_pen_down");
-        if (ret < 0) {
-                printk(KERN_ERR "Failed to request GPIO %d for "
-                                "ads7846 pen down IRQ\n", gpio);
-                return;
-        }
-
-        gpio_direction_input(gpio);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_PANDORA_TS_GPIO);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
 static struct spi_board_info omap3pandora_spi_board_info[] __initdata = {
         {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_PANDORA_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        }, {
                 .modalias               = "tpo_td043mtea1_panel_spi",
                 .bus_num                = 1,
                 .chip_select            = 1,
@@ -639,14 +573,10 @@ static void __init pandora_wl1251_init(void)
 
         memset(&pandora_wl1251_pdata, 0, sizeof(pandora_wl1251_pdata));
 
-        ret = gpio_request(PANDORA_WIFI_IRQ_GPIO, "wl1251 irq");
+        ret = gpio_request_one(PANDORA_WIFI_IRQ_GPIO, GPIOF_IN, "wl1251 irq");
         if (ret < 0)
                 goto fail;
 
-        ret = gpio_direction_input(PANDORA_WIFI_IRQ_GPIO);
-        if (ret < 0)
-                goto fail_irq;
-
         pandora_wl1251_pdata.irq = gpio_to_irq(PANDORA_WIFI_IRQ_GPIO);
         if (pandora_wl1251_pdata.irq < 0)
                 goto fail_irq;
@@ -688,12 +618,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init omap3pandora_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -705,9 +629,9 @@ static void __init omap3pandora_init(void)
         omap_serial_init();
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
-        omap3pandora_ads7846_init();
+        omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);
         usbhs_init(&usbhs_bdata);
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         gpmc_nand_init(&pandora_nand_data);
 
         /* Ensure SDRC pins are mux'd for self-refresh */
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index a6e0b9161c99..0c108a212ea2 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -39,13 +39,12 @@
 #include <plat/gpmc.h>
 #include <plat/nand.h>
 #include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 
 #include <plat/mcspi.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/spi/spi.h>
-#include <linux/spi/ads7846.h>
 #include <linux/interrupt.h>
 #include <linux/smsc911x.h>
 #include <linux/i2c/at24.h>
@@ -54,52 +53,28 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "timer-gp.h"
+#include "common-board-devices.h"
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+#include <plat/gpmc-smsc911x.h>
+
 #define OMAP3STALKER_ETHR_START 0x2c000000
 #define OMAP3STALKER_ETHR_SIZE  1024
 #define OMAP3STALKER_ETHR_GPIO_IRQ      19
 #define OMAP3STALKER_SMC911X_CS 5
 
-static struct resource omap3stalker_smsc911x_resources[] = {
-        [0] = {
-               .start   = OMAP3STALKER_ETHR_START,
-               .end     =
-               (OMAP3STALKER_ETHR_START + OMAP3STALKER_ETHR_SIZE - 1),
-               .flags   = IORESOURCE_MEM,
-        },
-        [1] = {
-               .start   = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ),
-               .end     = OMAP_GPIO_IRQ(OMAP3STALKER_ETHR_GPIO_IRQ),
-               .flags   = (IORESOURCE_IRQ | IRQF_TRIGGER_LOW),
-        },
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
+        .cs             = OMAP3STALKER_SMC911X_CS,
+        .gpio_irq       = OMAP3STALKER_ETHR_GPIO_IRQ,
+        .gpio_reset     = -EINVAL,
         .flags          = (SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS),
 };
 
-static struct platform_device omap3stalker_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(omap3stalker_smsc911x_resources),
-        .resource       = &omap3stalker_smsc911x_resources[0],
-        .dev            = {
-                .platform_data  = &smsc911x_config,
-        },
-};
-
 static inline void __init omap3stalker_init_eth(void)
 {
-        int eth_cs;
         struct clk *l3ck;
         unsigned int rate;
 
-        eth_cs = OMAP3STALKER_SMC911X_CS;
-
         l3ck = clk_get(NULL, "l3_ck");
         if (IS_ERR(l3ck))
                 rate = 100000000;
@@ -107,16 +82,7 @@ static inline void __init omap3stalker_init_eth(void)
                 rate = clk_get_rate(l3ck);
 
         omap_mux_init_gpio(19, OMAP_PIN_INPUT_PULLUP);
-        if (gpio_request(OMAP3STALKER_ETHR_GPIO_IRQ, "SMC911x irq") < 0) {
-                printk(KERN_ERR
-                       "Failed to request GPIO%d for smc911x IRQ\n",
-                       OMAP3STALKER_ETHR_GPIO_IRQ);
-                return;
-        }
-
-        gpio_direction_input(OMAP3STALKER_ETHR_GPIO_IRQ);
-
-        platform_device_register(&omap3stalker_smsc911x_device);
+        gpmc_smsc911x_init(&smsc911x_cfg);
 }
 
 #else
@@ -365,12 +331,11 @@ omap3stalker_twl_gpio_setup(struct device *dev,
          */
 
         /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        gpio_request_one(gpio + TWL4030_GPIO_MAX, GPIOF_OUT_INIT_LOW,
+                         "EN_LCD_BKL");
 
         /* gpio + 7 == DVI Enable */
-        gpio_request(gpio + 7, "EN_DVI");
-        gpio_direction_output(gpio + 7, 0);
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "EN_DVI");
 
         /* TWL4030_GPIO_MAX + 1 == ledB (out, mmc0) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -489,15 +454,8 @@ static struct twl4030_platform_data omap3stalker_twldata = {
         .codec          = &omap3stalker_codec_data,
         .vdac           = &omap3_stalker_vdac,
         .vpll2          = &omap3_stalker_vpll2,
-};
-
-static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo[] = {
-        {
-         I2C_BOARD_INFO("twl4030", 0x48),
-         .flags         = I2C_CLIENT_WAKE,
-         .irq           = INT_34XX_SYS_NIRQ,
-         .platform_data = &omap3stalker_twldata,
-         },
+        .vmmc1          = &omap3stalker_vmmc1,
+        .vsim           = &omap3stalker_vsim,
 };
 
 static struct at24_platform_data fram_info = {
@@ -516,15 +474,7 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
 
 static int __init omap3_stalker_i2c_init(void)
 {
-        /*
-         * REVISIT: These entries can be set in omap3evm_twl_data
-         * after a merge with MFD tree
-         */
-        omap3stalker_twldata.vmmc1 = &omap3stalker_vmmc1;
-        omap3stalker_twldata.vsim = &omap3stalker_vsim;
-
-        omap_register_i2c_bus(1, 2600, omap3stalker_i2c_boardinfo,
-                              ARRAY_SIZE(omap3stalker_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &omap3stalker_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
                               ARRAY_SIZE(omap3stalker_i2c_boardinfo3));
@@ -532,49 +482,6 @@ static int __init omap3_stalker_i2c_init(void)
 }
 
 #define OMAP3_STALKER_TS_GPIO   175
-static void ads7846_dev_init(void)
-{
-        if (gpio_request(OMAP3_STALKER_TS_GPIO, "ADS7846 pendown") < 0)
-                printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
-
-        gpio_direction_input(OMAP3_STALKER_TS_GPIO);
-        gpio_set_debounce(OMAP3_STALKER_TS_GPIO, 310);
-}
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OMAP3_STALKER_TS_GPIO);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-        .settle_delay_usecs     = 150,
-};
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode             = 0,
-        .single_channel         = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info omap3stalker_spi_board_info[] = {
-        [0] = {
-               .modalias        = "ads7846",
-               .bus_num         = 1,
-               .chip_select     = 0,
-               .max_speed_hz    = 1500000,
-               .controller_data = &ads7846_mcspi_config,
-               .irq             = OMAP_GPIO_IRQ(OMAP3_STALKER_TS_GPIO),
-               .platform_data   = &ads7846_config,
-        },
-};
 
 static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
 };
@@ -618,12 +525,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type = MUSB_INTERFACE_ULPI,
-        .mode           = MUSB_OTG,
-        .power          = 100,
-};
-
 static void __init omap3_stalker_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
@@ -636,13 +537,11 @@ static void __init omap3_stalker_init(void)
                              ARRAY_SIZE(omap3_stalker_devices));
 
         omap_display_init(&omap3_stalker_dss_data);
-        spi_register_board_info(omap3stalker_spi_board_info,
-                                ARRAY_SIZE(omap3stalker_spi_board_info));
 
         omap_serial_init();
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        ads7846_dev_init();
+        omap_ads7846_init(1, OMAP3_STALKER_TS_GPIO, 310, NULL);
 
         omap_mux_init_gpio(21, OMAP_PIN_OUTPUT);
         omap_mux_init_gpio(18, OMAP_PIN_INPUT_PULLUP);
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 127cb1752bdd..82872d7d313b 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -52,6 +52,7 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "timer-gp.h"
+#include "common-board-devices.h"
 
 #include <asm/setup.h>
 
@@ -95,15 +96,6 @@ static struct mtd_partition omap3touchbook_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data omap3touchbook_nand_data = {
-        .options        = NAND_BUSWIDTH_16,
-        .parts          = omap3touchbook_nand_partitions,
-        .nr_parts       = ARRAY_SIZE(omap3touchbook_nand_partitions),
-        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
-        .nand_setup     = NULL,
-        .dev_ready      = NULL,
-};
-
 #include "sdram-micron-mt46h32m32lf-6.h"
 
 static struct omap2_hsmmc_info mmc[] = {
@@ -154,13 +146,11 @@ static int touchbook_twl_gpio_setup(struct device *dev,
         /* REVISIT: need ehci-omap hooks for external VBUS
          * power switch and overcurrent detect
          */
-
-        gpio_request(gpio + 1, "EHCI_nOC");
-        gpio_direction_input(gpio + 1);
+        gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC");
 
         /* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, active low) */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "nEN_USB_PWR");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        gpio_request_one(gpio + TWL4030_GPIO_MAX, GPIOF_OUT_INIT_LOW,
+                         "nEN_USB_PWR");
 
         /* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
         gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -273,15 +263,6 @@ static struct twl4030_platform_data touchbook_twldata = {
         .vpll2          = &touchbook_vpll2,
 };
 
-static struct i2c_board_info __initdata touchbook_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl4030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &touchbook_twldata,
-        },
-};
-
 static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
         {
                 I2C_BOARD_INFO("bq27200", 0x55),
@@ -291,8 +272,7 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
 static int __init omap3_touchbook_i2c_init(void)
 {
         /* Standard TouchBook bus */
-        omap_register_i2c_bus(1, 2600, touchbook_i2c_boardinfo,
-                        ARRAY_SIZE(touchbook_i2c_boardinfo));
+        omap3_pmic_init("twl4030", &touchbook_twldata);
 
         /* Additional TouchBook bus */
         omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
@@ -301,19 +281,7 @@ static int __init omap3_touchbook_i2c_init(void)
         return 0;
 }
 
-static void __init omap3_ads7846_init(void)
-{
-        if (gpio_request(OMAP3_TS_GPIO, "ads7846_pen_down")) {
-                printk(KERN_ERR "Failed to request GPIO %d for "
-                                "ads7846 pen down IRQ\n", OMAP3_TS_GPIO);
-                return;
-        }
-
-        gpio_direction_input(OMAP3_TS_GPIO);
-        gpio_set_debounce(OMAP3_TS_GPIO, 310);
-}
-
-static struct ads7846_platform_data ads7846_config = {
+static struct ads7846_platform_data ads7846_pdata = {
         .x_min                  = 100,
         .y_min                  = 265,
         .x_max                  = 3950,
@@ -327,23 +295,6 @@ static struct ads7846_platform_data ads7846_config = {
         .keep_vref_on           = 1,
 };
 
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static struct spi_board_info omap3_ads7846_spi_board_info[] __initdata = {
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 4,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OMAP3_TS_GPIO),
-                .platform_data          = &ads7846_config,
-        }
-};
-
 static struct gpio_led gpio_leds[] = {
         {
                 .name                   = "touchbook::usr0",
@@ -434,39 +385,6 @@ static struct platform_device *omap3_touchbook_devices[] __initdata = {
         &keys_gpio,
 };
 
-static void __init omap3touchbook_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                omap3touchbook_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&omap3touchbook_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
         .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
@@ -481,15 +399,10 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
 static void omap3_touchbook_poweroff(void)
 {
-        int r;
+        int pwr_off = TB_KILL_POWER_GPIO;
 
-        r = gpio_request(TB_KILL_POWER_GPIO, "DVI reset");
-        if (r < 0) {
+        if (gpio_request_one(pwr_off, GPIOF_OUT_INIT_LOW, "DVI reset") < 0)
                 printk(KERN_ERR "Unable to get kill power GPIO\n");
-                return;
-        }
-
-        gpio_direction_output(TB_KILL_POWER_GPIO, 0);
 }
 
 static int __init early_touchbook_revision(char *p)
@@ -501,12 +414,6 @@ static int __init early_touchbook_revision(char *p)
 }
 early_param("tbr", early_touchbook_revision);
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void __init omap3_touchbook_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
@@ -521,17 +428,15 @@ static void __init omap3_touchbook_init(void)
         omap_serial_init();
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
-        gpio_request(176, "DVI_nPD");
         /* REVISIT leave DVI powered down until it's needed ... */
-        gpio_direction_output(176, true);
+        gpio_request_one(176, GPIOF_OUT_INIT_HIGH, "DVI_nPD");
 
         /* Touchscreen and accelerometer */
-        spi_register_board_info(omap3_ads7846_spi_board_info,
-                                ARRAY_SIZE(omap3_ads7846_spi_board_info));
-        omap3_ads7846_init();
-        usb_musb_init(&musb_board_data);
+        omap_ads7846_init(4, OMAP3_TS_GPIO, 310, &ads7846_pdata);
+        usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
-        omap3touchbook_flash_init();
+        omap_nand_flash_init(NAND_BUSWIDTH_16, omap3touchbook_nand_partitions,
+                             ARRAY_SIZE(omap3touchbook_nand_partitions));
 
         /* Ensure SDRC pins are mux'd for self-refresh */
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index f3a7b1011914..90485fced973 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -34,18 +34,19 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omap-panel-generic-dpi.h>
 #include "timer-gp.h"
 
 #include "hsmmc.h"
 #include "control.h"
 #include "mux.h"
+#include "common-board-devices.h"
 
 #define GPIO_HUB_POWER          1
 #define GPIO_HUB_NRESET         62
@@ -111,6 +112,11 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
         .reset_gpio_port[2]  = -EINVAL
 };
 
+static struct gpio panda_ehci_gpios[] __initdata = {
+        { GPIO_HUB_POWER,       GPIOF_OUT_INIT_LOW,  "hub_power"  },
+        { GPIO_HUB_NRESET,      GPIOF_OUT_INIT_LOW,  "hub_nreset" },
+};
+
 static void __init omap4_ehci_init(void)
 {
         int ret;
@@ -120,44 +126,27 @@ static void __init omap4_ehci_init(void)
         phy_ref_clk = clk_get(NULL, "auxclk3_ck");
         if (IS_ERR(phy_ref_clk)) {
                 pr_err("Cannot request auxclk3\n");
-                goto error1;
+                return;
         }
         clk_set_rate(phy_ref_clk, 19200000);
         clk_enable(phy_ref_clk);
 
-        /* disable the power to the usb hub prior to init */
-        ret = gpio_request(GPIO_HUB_POWER, "hub_power");
+        /* disable the power to the usb hub prior to init and reset phy+hub */
+        ret = gpio_request_array(panda_ehci_gpios,
+                                 ARRAY_SIZE(panda_ehci_gpios));
         if (ret) {
-                pr_err("Cannot request GPIO %d\n", GPIO_HUB_POWER);
-                goto error1;
+                pr_err("Unable to initialize EHCI power/reset\n");
+                return;
         }
-        gpio_export(GPIO_HUB_POWER, 0);
-        gpio_direction_output(GPIO_HUB_POWER, 0);
-        gpio_set_value(GPIO_HUB_POWER, 0);
 
-        /* reset phy+hub */
-        ret = gpio_request(GPIO_HUB_NRESET, "hub_nreset");
-        if (ret) {
-                pr_err("Cannot request GPIO %d\n", GPIO_HUB_NRESET);
-                goto error2;
-        }
+        gpio_export(GPIO_HUB_POWER, 0);
         gpio_export(GPIO_HUB_NRESET, 0);
-        gpio_direction_output(GPIO_HUB_NRESET, 0);
-        gpio_set_value(GPIO_HUB_NRESET, 0);
         gpio_set_value(GPIO_HUB_NRESET, 1);
 
         usbhs_init(&usbhs_bdata);
 
         /* enable power to hub */
         gpio_set_value(GPIO_HUB_POWER, 1);
-        return;
-
-error2:
-        gpio_free(GPIO_HUB_POWER);
-error1:
-        pr_err("Unable to initialize EHCI power/reset\n");
-        return;
-
 }
 
 static struct omap_musb_board_data musb_board_data = {
@@ -408,15 +397,6 @@ static struct twl4030_platform_data omap4_panda_twldata = {
         .usb            = &omap4_usbphy_data,
 };
 
-static struct i2c_board_info __initdata omap4_panda_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl6030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = OMAP44XX_IRQ_SYS_1N,
-                .platform_data = &omap4_panda_twldata,
-        },
-};
-
 /*
  * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
  * is connected as I2C slave device, and can be accessed at address 0x50
@@ -429,12 +409,7 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
 
 static int __init omap4_panda_i2c_init(void)
 {
-        /*
-         * Phoenix Audio IC needs I2C1 to
-         * start with 400 KHz or less
-         */
-        omap_register_i2c_bus(1, 400, omap4_panda_i2c_boardinfo,
-                        ARRAY_SIZE(omap4_panda_i2c_boardinfo));
+        omap4_pmic_init("twl6030", &omap4_panda_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         /*
          * Bus 3 is attached to the DVI port where devices like the pico DLP
@@ -651,27 +626,19 @@ static void omap4_panda_hdmi_mux_init(void)
                         OMAP_PIN_INPUT_PULLUP);
 }
 
+static struct gpio panda_hdmi_gpios[] = {
+        { HDMI_GPIO_HPD,        GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd"   },
+        { HDMI_GPIO_LS_OE,      GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
+};
+
 static int omap4_panda_panel_enable_hdmi(struct omap_dss_device *dssdev)
 {
         int status;
 
-        status = gpio_request_one(HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH,
-                                                        "hdmi_gpio_hpd");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", HDMI_GPIO_HPD);
-                return status;
-        }
-        status = gpio_request_one(HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH,
-                                                        "hdmi_gpio_ls_oe");
-        if (status) {
-                pr_err("Cannot request GPIO %d\n", HDMI_GPIO_LS_OE);
-                goto error1;
-        }
-
-        return 0;
-
-error1:
-        gpio_free(HDMI_GPIO_HPD);
+        status = gpio_request_array(panda_hdmi_gpios,
+                                    ARRAY_SIZE(panda_hdmi_gpios));
+        if (status)
+                pr_err("Cannot request HDMI GPIOs\n");
 
         return status;
 }
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 59ca33326b8c..1555918e3ffa 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -43,8 +43,8 @@
 
 #include <plat/board.h>
 #include <plat/common.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
 #include <mach/gpio.h>
 #include <plat/gpmc.h>
 #include <mach/hardware.h>
@@ -56,6 +56,7 @@
 #include "mux.h"
 #include "sdram-micron-mt46h32m32lf-6.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define OVERO_GPIO_BT_XGATE     15
 #define OVERO_GPIO_W2W_NRESET   16
@@ -74,30 +75,6 @@
 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
         defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 
-#include <linux/spi/ads7846.h>
-
-static struct omap2_mcspi_device_config ads7846_mcspi_config = {
-        .turbo_mode     = 0,
-        .single_channel = 1,    /* 0: slave, 1: master */
-};
-
-static int ads7846_get_pendown_state(void)
-{
-        return !gpio_get_value(OVERO_GPIO_PENDOWN);
-}
-
-static struct ads7846_platform_data ads7846_config = {
-        .x_max                  = 0x0fff,
-        .y_max                  = 0x0fff,
-        .x_plate_ohms           = 180,
-        .pressure_max           = 255,
-        .debounce_max           = 10,
-        .debounce_tol           = 3,
-        .debounce_rep           = 1,
-        .get_pendown_state      = ads7846_get_pendown_state,
-        .keep_vref_on           = 1,
-};
-
 /* fixed regulator for ads7846 */
 static struct regulator_consumer_supply ads7846_supply =
         REGULATOR_SUPPLY("vcc", "spi1.0");
@@ -128,14 +105,7 @@ static struct platform_device vads7846_device = {
 
 static void __init overo_ads7846_init(void)
 {
-        if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) &&
-            (gpio_direction_input(OVERO_GPIO_PENDOWN) == 0)) {
-                gpio_export(OVERO_GPIO_PENDOWN, 0);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n");
-                return;
-        }
-
+        omap_ads7846_init(1, OVERO_GPIO_PENDOWN, 0, NULL);
         platform_device_register(&vads7846_device);
 }
 
@@ -146,106 +116,28 @@ static inline void __init overo_ads7846_init(void) { return; }
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 #include <linux/smsc911x.h>
+#include <plat/gpmc-smsc911x.h>
 
-static struct resource overo_smsc911x_resources[] = {
-        {
-                .name   = "smsc911x-memory",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct resource overo_smsc911x2_resources[] = {
-        {
-                .name   = "smsc911x2-memory",
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct smsc911x_platform_config overo_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
-        .flags          = SMSC911X_USE_32BIT ,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device overo_smsc911x_device = {
-        .name           = "smsc911x",
+static struct omap_smsc911x_platform_data smsc911x_cfg = {
         .id             = 0,
-        .num_resources  = ARRAY_SIZE(overo_smsc911x_resources),
-        .resource       = overo_smsc911x_resources,
-        .dev            = {
-                .platform_data = &overo_smsc911x_config,
-        },
+        .cs             = OVERO_SMSC911X_CS,
+        .gpio_irq       = OVERO_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT,
 };
 
-static struct platform_device overo_smsc911x2_device = {
-        .name           = "smsc911x",
+static struct omap_smsc911x_platform_data smsc911x2_cfg = {
         .id             = 1,
-        .num_resources  = ARRAY_SIZE(overo_smsc911x2_resources),
-        .resource       = overo_smsc911x2_resources,
-        .dev            = {
-                .platform_data = &overo_smsc911x_config,
-        },
+        .cs             = OVERO_SMSC911X2_CS,
+        .gpio_irq       = OVERO_SMSC911X2_GPIO,
+        .gpio_reset     = -EINVAL,
+        .flags          = SMSC911X_USE_32BIT,
 };
 
-static struct platform_device *smsc911x_devices[] = {
-        &overo_smsc911x_device,
-        &overo_smsc911x2_device,
-};
-
-static inline void __init overo_init_smsc911x(void)
+static void __init overo_init_smsc911x(void)
 {
-        unsigned long cs_mem_base, cs_mem_base2;
-
-        /* set up first smsc911x chip */
-
-        if (gpmc_cs_request(OVERO_SMSC911X_CS, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed request for GPMC mem for smsc911x\n");
-                return;
-        }
-
-        overo_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        overo_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-
-        if ((gpio_request(OVERO_SMSC911X_GPIO, "SMSC911X IRQ") == 0) &&
-            (gpio_direction_input(OVERO_SMSC911X_GPIO) == 0)) {
-                gpio_export(OVERO_SMSC911X_GPIO, 0);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for SMSC911X IRQ\n");
-                return;
-        }
-
-        overo_smsc911x_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X_GPIO);
-        overo_smsc911x_resources[1].end   = 0;
-
-        /* set up second smsc911x chip */
-
-        if (gpmc_cs_request(OVERO_SMSC911X2_CS, SZ_16M, &cs_mem_base2) < 0) {
-                printk(KERN_ERR "Failed request for GPMC mem for smsc911x2\n");
-                return;
-        }
-
-        overo_smsc911x2_resources[0].start = cs_mem_base2 + 0x0;
-        overo_smsc911x2_resources[0].end   = cs_mem_base2 + 0xff;
-
-        if ((gpio_request(OVERO_SMSC911X2_GPIO, "SMSC911X2 IRQ") == 0) &&
-            (gpio_direction_input(OVERO_SMSC911X2_GPIO) == 0)) {
-                gpio_export(OVERO_SMSC911X2_GPIO, 0);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for SMSC911X2 IRQ\n");
-                return;
-        }
-
-        overo_smsc911x2_resources[1].start = OMAP_GPIO_IRQ(OVERO_SMSC911X2_GPIO);
-        overo_smsc911x2_resources[1].end   = 0;
-
-        platform_add_devices(smsc911x_devices, ARRAY_SIZE(smsc911x_devices));
+        gpmc_smsc911x_init(&smsc911x_cfg);
+        gpmc_smsc911x_init(&smsc911x2_cfg);
 }
 
 #else
@@ -259,21 +151,20 @@ static int dvi_enabled;
 #define OVERO_GPIO_LCD_EN 144
 #define OVERO_GPIO_LCD_BL 145
 
+static struct gpio overo_dss_gpios[] __initdata = {
+        { OVERO_GPIO_LCD_EN, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_EN" },
+        { OVERO_GPIO_LCD_BL, GPIOF_OUT_INIT_HIGH, "OVERO_GPIO_LCD_BL" },
+};
+
 static void __init overo_display_init(void)
 {
-        if ((gpio_request(OVERO_GPIO_LCD_EN, "OVERO_GPIO_LCD_EN") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_LCD_EN, 1) == 0))
-                gpio_export(OVERO_GPIO_LCD_EN, 0);
-        else
-                printk(KERN_ERR "could not obtain gpio for "
-                                        "OVERO_GPIO_LCD_EN\n");
+        if (gpio_request_array(overo_dss_gpios, ARRAY_SIZE(overo_dss_gpios))) {
+                printk(KERN_ERR "could not obtain DSS control GPIOs\n");
+                return;
+        }
 
-        if ((gpio_request(OVERO_GPIO_LCD_BL, "OVERO_GPIO_LCD_BL") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_LCD_BL, 1) == 0))
-                gpio_export(OVERO_GPIO_LCD_BL, 0);
-        else
-                printk(KERN_ERR "could not obtain gpio for "
-                                        "OVERO_GPIO_LCD_BL\n");
+        gpio_export(OVERO_GPIO_LCD_EN, 0);
+        gpio_export(OVERO_GPIO_LCD_BL, 0);
 }
 
 static int overo_panel_enable_dvi(struct omap_dss_device *dssdev)
@@ -412,45 +303,6 @@ static struct mtd_partition overo_nand_partitions[] = {
         },
 };
 
-static struct omap_nand_platform_data overo_nand_data = {
-        .parts = overo_nand_partitions,
-        .nr_parts = ARRAY_SIZE(overo_nand_partitions),
-        .dma_channel = -1,      /* disable DMA in OMAP NAND driver */
-};
-
-static void __init overo_flash_init(void)
-{
-        u8 cs = 0;
-        u8 nandcs = GPMC_CS_NUM + 1;
-
-        /* find out the chip-select on which NAND exists */
-        while (cs < GPMC_CS_NUM) {
-                u32 ret = 0;
-                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
-
-                if ((ret & 0xC00) == 0x800) {
-                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
-                        if (nandcs > GPMC_CS_NUM)
-                                nandcs = cs;
-                }
-                cs++;
-        }
-
-        if (nandcs > GPMC_CS_NUM) {
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                 "in GPMC\n ");
-                return;
-        }
-
-        if (nandcs < GPMC_CS_NUM) {
-                overo_nand_data.cs = nandcs;
-
-                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
-                if (gpmc_nand_init(&overo_nand_data) < 0)
-                        printk(KERN_ERR "Unable to register NAND device\n");
-        }
-}
-
 static struct omap2_hsmmc_info mmc[] = {
         {
                 .mmc            = 1,
@@ -648,37 +500,15 @@ static struct twl4030_platform_data overo_twldata = {
         .vpll2          = &overo_vpll2,
 };
 
-static struct i2c_board_info __initdata overo_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("tps65950", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &overo_twldata,
-        },
-};
-
 static int __init overo_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2600, overo_i2c_boardinfo,
-                        ARRAY_SIZE(overo_i2c_boardinfo));
+        omap3_pmic_init("tps65950", &overo_twldata);
         /* i2c2 pins are used for gpio */
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
 }
 
 static struct spi_board_info overo_spi_board_info[] __initdata = {
-#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
-        defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        {
-                .modalias               = "ads7846",
-                .bus_num                = 1,
-                .chip_select            = 0,
-                .max_speed_hz           = 1500000,
-                .controller_data        = &ads7846_mcspi_config,
-                .irq                    = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN),
-                .platform_data          = &ads7846_config,
-        },
-#endif
 #if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \
         defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE)
         {
@@ -722,20 +552,22 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
+static struct gpio overo_bt_gpios[] __initdata = {
+        { OVERO_GPIO_BT_XGATE,  GPIOF_OUT_INIT_LOW,     "lcd enable"    },
+        { OVERO_GPIO_BT_NRESET, GPIOF_OUT_INIT_HIGH,    "lcd bl enable" },
 };
 
 static void __init overo_init(void)
 {
+        int ret;
+
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         overo_i2c_init();
         omap_display_init(&overo_dss_data);
         omap_serial_init();
-        overo_flash_init();
-        usb_musb_init(&musb_board_data);
+        omap_nand_flash_init(0, overo_nand_partitions,
+                             ARRAY_SIZE(overo_nand_partitions));
+        usb_musb_init(NULL);
         usbhs_init(&usbhs_bdata);
         overo_spi_init();
         overo_ads7846_init();
@@ -748,9 +580,9 @@ static void __init overo_init(void)
         omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
         omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
 
-        if ((gpio_request(OVERO_GPIO_W2W_NRESET,
-                          "OVERO_GPIO_W2W_NRESET") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_W2W_NRESET, 1) == 0)) {
+        ret = gpio_request_one(OVERO_GPIO_W2W_NRESET, GPIOF_OUT_INIT_HIGH,
+                               "OVERO_GPIO_W2W_NRESET");
+        if (ret == 0) {
                 gpio_export(OVERO_GPIO_W2W_NRESET, 0);
                 gpio_set_value(OVERO_GPIO_W2W_NRESET, 0);
                 udelay(10);
@@ -760,25 +592,20 @@ static void __init overo_init(void)
                                         "OVERO_GPIO_W2W_NRESET\n");
         }
 
-        if ((gpio_request(OVERO_GPIO_BT_XGATE, "OVERO_GPIO_BT_XGATE") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_BT_XGATE, 0) == 0))
+        ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
+        if (ret) {
+                pr_err("%s: could not obtain BT gpios\n", __func__);
+        } else {
                 gpio_export(OVERO_GPIO_BT_XGATE, 0);
-        else
-                printk(KERN_ERR "could not obtain gpio for OVERO_GPIO_BT_XGATE\n");
-
-        if ((gpio_request(OVERO_GPIO_BT_NRESET, "OVERO_GPIO_BT_NRESET") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_BT_NRESET, 1) == 0)) {
                 gpio_export(OVERO_GPIO_BT_NRESET, 0);
                 gpio_set_value(OVERO_GPIO_BT_NRESET, 0);
                 mdelay(6);
                 gpio_set_value(OVERO_GPIO_BT_NRESET, 1);
-        } else {
-                printk(KERN_ERR "could not obtain gpio for "
-                                        "OVERO_GPIO_BT_NRESET\n");
         }
 
-        if ((gpio_request(OVERO_GPIO_USBH_CPEN, "OVERO_GPIO_USBH_CPEN") == 0) &&
-            (gpio_direction_output(OVERO_GPIO_USBH_CPEN, 1) == 0))
+        ret = gpio_request_one(OVERO_GPIO_USBH_CPEN, GPIOF_OUT_INIT_HIGH,
+                               "OVERO_GPIO_USBH_CPEN");
+        if (ret == 0)
                 gpio_export(OVERO_GPIO_USBH_CPEN, 0);
         else
                 printk(KERN_ERR "could not obtain gpio for "
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 2af8b05e786d..42d10b12da3c 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -31,6 +31,7 @@
 #include "mux.h"
 #include "hsmmc.h"
 #include "sdram-nokia.h"
+#include "common-board-devices.h"
 
 static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
         REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
@@ -90,19 +91,9 @@ static struct twl4030_platform_data rm680_twl_data = {
         /* add rest of the children here */
 };
 
-static struct i2c_board_info __initdata rm680_twl_i2c_board_info[] = {
-        {
-                I2C_BOARD_INFO("twl5031", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &rm680_twl_data,
-        },
-};
-
 static void __init rm680_i2c_init(void)
 {
-        omap_register_i2c_bus(1, 2900, rm680_twl_i2c_board_info,
-                                ARRAY_SIZE(rm680_twl_i2c_board_info));
+        omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
 }
@@ -153,17 +144,11 @@ static struct omap_board_mux board_mux[] __initdata = {
 };
 #endif
 
-static struct omap_musb_board_data rm680_musb_data = {
-        .interface_type = MUSB_INTERFACE_ULPI,
-        .mode           = MUSB_PERIPHERAL,
-        .power          = 100,
-};
-
 static void __init rm680_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
-        usb_musb_init(&rm680_musb_data);
+        usb_musb_init(NULL);
         rm680_peripherals_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index bbcb6775a6a3..f6247e71a194 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/mmc/host.h>
+#include <linux/power/isp1704_charger.h>
 
 #include <plat/mcspi.h>
 #include <plat/board.h>
@@ -43,6 +44,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define SYSTEM_REV_B_USES_VAUX3 0x1699
 #define SYSTEM_REV_S_USES_VAUX3 0x8
@@ -52,6 +54,8 @@
 #define RX51_FMTX_RESET_GPIO            163
 #define RX51_FMTX_IRQ                   53
 
+#define RX51_USB_TRANSCEIVER_RST_GPIO   67
+
 /* list all spi devices here */
 enum {
         RX51_SPI_WL1251,
@@ -110,10 +114,30 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = {
         },
 };
 
+static void rx51_charger_set_power(bool on)
+{
+        gpio_set_value(RX51_USB_TRANSCEIVER_RST_GPIO, on);
+}
+
+static struct isp1704_charger_data rx51_charger_data = {
+        .set_power      = rx51_charger_set_power,
+};
+
 static struct platform_device rx51_charger_device = {
-        .name = "isp1704_charger",
+        .name   = "isp1704_charger",
+        .dev    = {
+                .platform_data = &rx51_charger_data,
+        },
 };
 
+static void __init rx51_charger_init(void)
+{
+        WARN_ON(gpio_request_one(RX51_USB_TRANSCEIVER_RST_GPIO,
+                GPIOF_OUT_INIT_LOW, "isp1704_reset"));
+
+        platform_device_register(&rx51_charger_device);
+}
+
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 
 #define RX51_GPIO_CAMERA_LENS_COVER     110
@@ -557,10 +581,8 @@ static __init void rx51_init_si4713(void)
 static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 {
         /* FIXME this gpio setup is just a placeholder for now */
-        gpio_request(gpio + 6, "backlight_pwm");
-        gpio_direction_output(gpio + 6, 0);
-        gpio_request(gpio + 7, "speaker_en");
-        gpio_direction_output(gpio + 7, 1);
+        gpio_request_one(gpio + 6, GPIOF_OUT_INIT_LOW, "backlight_pwm");
+        gpio_request_one(gpio + 7, GPIOF_OUT_INIT_HIGH, "speaker_en");
 
         return 0;
 }
@@ -730,7 +752,7 @@ static struct twl4030_resconfig twl4030_rconfig[] __initdata = {
         { .resource = RES_RESET, .devgroup = -1,
           .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
         },
-        { .resource = RES_Main_Ref, .devgroup = -1,
+        { .resource = RES_MAIN_REF, .devgroup = -1,
           .type = 1, .type2 = -1, .remap_off = -1, .remap_sleep = -1
         },
         { 0, 0},
@@ -777,15 +799,6 @@ static struct tpa6130a2_platform_data rx51_tpa6130a2_data __initdata_or_module =
         .power_gpio             = 98,
 };
 
-static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = {
-        {
-                I2C_BOARD_INFO("twl5030", 0x48),
-                .flags = I2C_CLIENT_WAKE,
-                .irq = INT_34XX_SYS_NIRQ,
-                .platform_data = &rx51_twldata,
-        },
-};
-
 /* Audio setup data */
 static struct aic3x_setup_data rx51_aic34_setup = {
         .gpio_func[0] = AIC3X_GPIO1_FUNC_DISABLED,
@@ -833,8 +846,7 @@ static int __init rx51_i2c_init(void)
                 rx51_twldata.vaux3 = &rx51_vaux3_cam;
         }
         rx51_twldata.vmmc2 = &rx51_vmmc2;
-        omap_register_i2c_bus(1, 2200, rx51_peripherals_i2c_board_info_1,
-                              ARRAY_SIZE(rx51_peripherals_i2c_board_info_1));
+        omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
         omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
                               ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
         omap_register_i2c_bus(3, 400, NULL, 0);
@@ -921,26 +933,20 @@ static void rx51_wl1251_set_power(bool enable)
         gpio_set_value(RX51_WL1251_POWER_GPIO, enable);
 }
 
+static struct gpio rx51_wl1251_gpios[] __initdata = {
+        { RX51_WL1251_POWER_GPIO, GPIOF_OUT_INIT_LOW,   "wl1251 power"  },
+        { RX51_WL1251_IRQ_GPIO,   GPIOF_IN,             "wl1251 irq"    },
+};
+
 static void __init rx51_init_wl1251(void)
 {
         int irq, ret;
 
-        ret = gpio_request(RX51_WL1251_POWER_GPIO, "wl1251 power");
+        ret = gpio_request_array(rx51_wl1251_gpios,
+                                 ARRAY_SIZE(rx51_wl1251_gpios));
         if (ret < 0)
                 goto error;
 
-        ret = gpio_direction_output(RX51_WL1251_POWER_GPIO, 0);
-        if (ret < 0)
-                goto err_power;
-
-        ret = gpio_request(RX51_WL1251_IRQ_GPIO, "wl1251 irq");
-        if (ret < 0)
-                goto err_power;
-
-        ret = gpio_direction_input(RX51_WL1251_IRQ_GPIO);
-        if (ret < 0)
-                goto err_irq;
-
         irq = gpio_to_irq(RX51_WL1251_IRQ_GPIO);
         if (irq < 0)
                 goto err_irq;
@@ -952,10 +958,7 @@ static void __init rx51_init_wl1251(void)
 
 err_irq:
         gpio_free(RX51_WL1251_IRQ_GPIO);
-
-err_power:
         gpio_free(RX51_WL1251_POWER_GPIO);
-
 error:
         printk(KERN_ERR "wl1251 board initialisation failed\n");
         wl1251_pdata.set_power = NULL;
@@ -981,6 +984,6 @@ void __init rx51_peripherals_init(void)
         if (partition)
                 omap2_hsmmc_init(mmc);
 
-        platform_device_register(&rx51_charger_device);
+        rx51_charger_init();
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 89a66db8b77d..2c1289bd5e6a 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -15,7 +15,7 @@
 #include <linux/spi/spi.h>
 #include <linux/mm.h>
 #include <asm/mach-types.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/vram.h>
 #include <plat/mcspi.h>
 
@@ -76,13 +76,12 @@ static int __init rx51_video_init(void)
                 return 0;
         }
 
-        if (gpio_request(RX51_LCD_RESET_GPIO, "LCD ACX565AKM reset")) {
+        if (gpio_request_one(RX51_LCD_RESET_GPIO, GPIOF_OUT_INIT_HIGH,
+                             "LCD ACX565AKM reset")) {
                 pr_err("%s failed to get LCD Reset GPIO\n", __func__);
                 return 0;
         }
 
-        gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
-
         omap_display_init(&rx51_dss_board_info);
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index f8ba20a14e62..fec4cac8fa0a 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -58,21 +58,25 @@ static struct platform_device leds_gpio = {
         },
 };
 
+/*
+ * cpuidle C-states definition override from the default values.
+ * The 'exit_latency' field is the sum of sleep and wake-up latencies.
+ */
 static struct cpuidle_params rx51_cpuidle_params[] = {
         /* C1 */
-        {1, 110, 162, 5},
+        {110 + 162, 5 , 1},
         /* C2 */
-        {1, 106, 180, 309},
+        {106 + 180, 309, 1},
         /* C3 */
-        {0, 107, 410, 46057},
+        {107 + 410, 46057, 0},
         /* C4 */
-        {0, 121, 3374, 46057},
+        {121 + 3374, 46057, 0},
         /* C5 */
-        {1, 855, 1146, 46057},
+        {855 + 1146, 46057, 1},
         /* C6 */
-        {0, 7580, 4134, 484329},
+        {7580 + 4134, 484329, 0},
         /* C7 */
-        {1, 7505, 15274, 484329},
+        {7505 + 15274, 484329, 1},
 };
 
 static struct omap_lcd_config rx51_lcd_config = {
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 007ebdc6c993..6402e781c458 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -15,6 +15,7 @@
 #include <linux/interrupt.h>
 
 #include <plat/gpmc.h>
+#include <plat/gpmc-smsc911x.h>
 
 #include <mach/board-zoom.h>
 
@@ -26,60 +27,16 @@
 #define DEBUG_BASE              0x08000000
 #define ZOOM_ETHR_START DEBUG_BASE
 
-static struct resource zoom_smsc911x_resources[] = {
-        [0] = {
-                .start  = ZOOM_ETHR_START,
-                .end    = ZOOM_ETHR_START + SZ_4K,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-        },
-};
-
-static struct smsc911x_platform_config zoom_smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+static struct omap_smsc911x_platform_data zoom_smsc911x_cfg = {
+        .cs             = ZOOM_SMSC911X_CS,
+        .gpio_irq       = ZOOM_SMSC911X_GPIO,
+        .gpio_reset     = -EINVAL,
         .flags          = SMSC911X_USE_32BIT,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device zoom_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(zoom_smsc911x_resources),
-        .resource       = zoom_smsc911x_resources,
-        .dev            = {
-                .platform_data = &zoom_smsc911x_config,
-        },
 };
 
 static inline void __init zoom_init_smsc911x(void)
 {
-        int eth_cs;
-        unsigned long cs_mem_base;
-        int eth_gpio = 0;
-
-        eth_cs = ZOOM_SMSC911X_CS;
-
-        if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
-                return;
-        }
-
-        zoom_smsc911x_resources[0].start = cs_mem_base + 0x0;
-        zoom_smsc911x_resources[0].end   = cs_mem_base + 0xff;
-
-        eth_gpio = ZOOM_SMSC911X_GPIO;
-
-        zoom_smsc911x_resources[1].start = OMAP_GPIO_IRQ(eth_gpio);
-
-        if (gpio_request(eth_gpio, "smsc911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                                eth_gpio);
-                return;
-        }
-        gpio_direction_input(eth_gpio);
+        gpmc_smsc911x_init(&zoom_smsc911x_cfg);
 }
 
 static struct plat_serial8250_port serial_platform_data[] = {
@@ -120,12 +77,9 @@ static inline void __init zoom_init_quaduart(void)
 
         quart_gpio = ZOOM_QUADUART_GPIO;
 
-        if (gpio_request(quart_gpio, "TL16CP754C GPIO") < 0) {
+        if (gpio_request_one(quart_gpio, GPIOF_IN, "TL16CP754C GPIO") < 0)
                 printk(KERN_ERR "Failed to request GPIO%d for TL16CP754C\n",
                                                                 quart_gpio);
-                return;
-        }
-        gpio_direction_input(quart_gpio);
 }
 
 static inline int omap_zoom_debugboard_detect(void)
@@ -135,12 +89,12 @@ static inline int omap_zoom_debugboard_detect(void)
 
         debug_board_detect = ZOOM_SMSC911X_GPIO;
 
-        if (gpio_request(debug_board_detect, "Zoom debug board detect") < 0) {
+        if (gpio_request_one(debug_board_detect, GPIOF_IN,
+                             "Zoom debug board detect") < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
                 "board detect\n", debug_board_detect);
                 return 0;
         }
-        gpio_direction_input(debug_board_detect);
 
         if (!gpio_get_value(debug_board_detect)) {
                 ret = 0;
@@ -150,7 +104,6 @@ static inline int omap_zoom_debugboard_detect(void)
 }
 
 static struct platform_device *zoom_devices[] __initdata = {
-        &zoom_smsc911x_device,
         &zoom_debugboard_serial_device,
 };
 
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 37b84c2b850f..c7c6beb1ec24 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -15,40 +15,25 @@
 #include <linux/i2c/twl.h>
 #include <linux/spi/spi.h>
 #include <plat/mcspi.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #define LCD_PANEL_RESET_GPIO_PROD       96
 #define LCD_PANEL_RESET_GPIO_PILOT      55
 #define LCD_PANEL_QVGA_GPIO             56
 
+static struct gpio zoom_lcd_gpios[] __initdata = {
+        { -EINVAL,              GPIOF_OUT_INIT_HIGH, "lcd reset" },
+        { LCD_PANEL_QVGA_GPIO,  GPIOF_OUT_INIT_HIGH, "lcd qvga"  },
+};
+
 static void zoom_lcd_panel_init(void)
 {
-        int ret;
-        unsigned char lcd_panel_reset_gpio;
-
-        lcd_panel_reset_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
+        zoom_lcd_gpios[0].gpio = (omap_rev() > OMAP3430_REV_ES3_0) ?
                         LCD_PANEL_RESET_GPIO_PROD :
                         LCD_PANEL_RESET_GPIO_PILOT;
 
-        ret = gpio_request(lcd_panel_reset_gpio, "lcd reset");
-        if (ret) {
-                pr_err("Failed to get LCD reset GPIO (gpio%d).\n",
-                        lcd_panel_reset_gpio);
-                return;
-        }
-        gpio_direction_output(lcd_panel_reset_gpio, 1);
-
-        ret = gpio_request(LCD_PANEL_QVGA_GPIO, "lcd qvga");
-        if (ret) {
-                pr_err("Failed to get LCD_PANEL_QVGA_GPIO (gpio%d).\n",
-                        LCD_PANEL_QVGA_GPIO);
-                goto err0;
-        }
-        gpio_direction_output(LCD_PANEL_QVGA_GPIO, 1);
-
-        return;
-err0:
-        gpio_free(lcd_panel_reset_gpio);
+        if (gpio_request_array(zoom_lcd_gpios, ARRAY_SIZE(zoom_lcd_gpios)))
+                pr_err("%s: Failed to get LCD GPIOs.\n", __func__);
 }
 
 static int zoom_panel_enable_lcd(struct omap_dss_device *dssdev)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 8dee7549fbdf..118c6f53c5eb 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -31,6 +31,7 @@
 
 #include "mux.h"
 #include "hsmmc.h"
+#include "common-board-devices.h"
 
 #define OMAP_ZOOM_WLAN_PMENA_GPIO       (101)
 #define OMAP_ZOOM_WLAN_IRQ_GPIO         (162)
@@ -276,13 +277,11 @@ static int zoom_twl_gpio_setup(struct device *dev,
         zoom_vsim_supply.dev = mmc[0].dev;
         zoom_vmmc2_supply.dev = mmc[1].dev;
 
-        ret = gpio_request(LCD_PANEL_ENABLE_GPIO, "lcd enable");
-        if (ret) {
+        ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
+                               "lcd enable");
+        if (ret)
                 pr_err("Failed to get LCD_PANEL_ENABLE_GPIO (gpio%d).\n",
                                 LCD_PANEL_ENABLE_GPIO);
-                return ret;
-        }
-        gpio_direction_output(LCD_PANEL_ENABLE_GPIO, 0);
 
         return ret;
 }
@@ -349,15 +348,6 @@ static struct twl4030_platform_data zoom_twldata = {
         .vdac           = &zoom_vdac,
 };
 
-static struct i2c_board_info __initdata zoom_i2c_boardinfo[] = {
-        {
-                I2C_BOARD_INFO("twl5030", 0x48),
-                .flags          = I2C_CLIENT_WAKE,
-                .irq            = INT_34XX_SYS_NIRQ,
-                .platform_data  = &zoom_twldata,
-        },
-};
-
 static int __init omap_i2c_init(void)
 {
         if (machine_is_omap_zoom2()) {
@@ -365,19 +355,12 @@ static int __init omap_i2c_init(void)
                 zoom_audio_data.hs_extmute = 1;
                 zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
         }
-        omap_register_i2c_bus(1, 2400, zoom_i2c_boardinfo,
-                        ARRAY_SIZE(zoom_i2c_boardinfo));
+        omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, NULL, 0);
         return 0;
 }
 
-static struct omap_musb_board_data musb_board_data = {
-        .interface_type         = MUSB_INTERFACE_ULPI,
-        .mode                   = MUSB_OTG,
-        .power                  = 100,
-};
-
 static void enable_board_wakeup_source(void)
 {
         /* T2 interrupt line (keypad) */
@@ -392,7 +375,7 @@ void __init zoom_peripherals_init(void)
 
         omap_i2c_init();
         platform_device_register(&omap_vwlan_device);
-        usb_musb_init(&musb_board_data);
+        usb_musb_init(NULL);
         enable_board_wakeup_source();
         omap_serial_init();
 }
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
new file mode 100644
index 000000000000..e94903b2c65b
--- /dev/null
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -0,0 +1,163 @@
+/*
+ * common-board-devices.c
+ *
+ * Copyright (C) 2011 CompuLab, Ltd.
+ * Author: Mike Rapoport <mike@compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c/twl.h>
+
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+
+#include <plat/i2c.h>
+#include <plat/mcspi.h>
+#include <plat/nand.h>
+
+#include "common-board-devices.h"
+
+static struct i2c_board_info __initdata pmic_i2c_board_info = {
+        .addr           = 0x48,
+        .flags          = I2C_CLIENT_WAKE,
+};
+
+void __init omap_pmic_init(int bus, u32 clkrate,
+                           const char *pmic_type, int pmic_irq,
+                           struct twl4030_platform_data *pmic_data)
+{
+        strncpy(pmic_i2c_board_info.type, pmic_type,
+                sizeof(pmic_i2c_board_info.type));
+        pmic_i2c_board_info.irq = pmic_irq;
+        pmic_i2c_board_info.platform_data = pmic_data;
+
+        omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
+}
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
+        defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+static struct omap2_mcspi_device_config ads7846_mcspi_config = {
+        .turbo_mode     = 0,
+        .single_channel = 1,    /* 0: slave, 1: master */
+};
+
+static struct ads7846_platform_data ads7846_config = {
+        .x_max                  = 0x0fff,
+        .y_max                  = 0x0fff,
+        .x_plate_ohms           = 180,
+        .pressure_max           = 255,
+        .debounce_max           = 10,
+        .debounce_tol           = 3,
+        .debounce_rep           = 1,
+        .gpio_pendown           = -EINVAL,
+        .keep_vref_on           = 1,
+};
+
+static struct spi_board_info ads7846_spi_board_info __initdata = {
+        .modalias               = "ads7846",
+        .bus_num                = -EINVAL,
+        .chip_select            = 0,
+        .max_speed_hz           = 1500000,
+        .controller_data        = &ads7846_mcspi_config,
+        .irq                    = -EINVAL,
+        .platform_data          = &ads7846_config,
+};
+
+void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+                              struct ads7846_platform_data *board_pdata)
+{
+        struct spi_board_info *spi_bi = &ads7846_spi_board_info;
+        int err;
+
+        err = gpio_request(gpio_pendown, "TS PenDown");
+        if (err) {
+                pr_err("Could not obtain gpio for TS PenDown: %d\n", err);
+                return;
+        }
+
+        gpio_direction_input(gpio_pendown);
+        gpio_export(gpio_pendown, 0);
+
+        if (gpio_debounce)
+                gpio_set_debounce(gpio_pendown, gpio_debounce);
+
+        ads7846_config.gpio_pendown = gpio_pendown;
+
+        spi_bi->bus_num = bus_num;
+        spi_bi->irq     = OMAP_GPIO_IRQ(gpio_pendown);
+
+        if (board_pdata)
+                spi_bi->platform_data = board_pdata;
+
+        spi_register_board_info(&ads7846_spi_board_info, 1);
+}
+#else
+void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+                              struct ads7846_platform_data *board_pdata)
+{
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
+static struct omap_nand_platform_data nand_data = {
+        .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
+};
+
+void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
+                                 int nr_parts)
+{
+        u8 cs = 0;
+        u8 nandcs = GPMC_CS_NUM + 1;
+
+        /* find out the chip-select on which NAND exists */
+        while (cs < GPMC_CS_NUM) {
+                u32 ret = 0;
+                ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+                if ((ret & 0xC00) == 0x800) {
+                        printk(KERN_INFO "Found NAND on CS%d\n", cs);
+                        if (nandcs > GPMC_CS_NUM)
+                                nandcs = cs;
+                }
+                cs++;
+        }
+
+        if (nandcs > GPMC_CS_NUM) {
+                printk(KERN_INFO "NAND: Unable to find configuration "
+                                 "in GPMC\n ");
+                return;
+        }
+
+        if (nandcs < GPMC_CS_NUM) {
+                nand_data.cs = nandcs;
+                nand_data.parts = parts;
+                nand_data.nr_parts = nr_parts;
+                nand_data.options = options;
+
+                printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
+                if (gpmc_nand_init(&nand_data) < 0)
+                        printk(KERN_ERR "Unable to register NAND device\n");
+        }
+}
+#else
+void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
+                                 int nr_parts)
+{
+}
+#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
new file mode 100644
index 000000000000..eb80b3b0ef47
--- /dev/null
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -0,0 +1,35 @@
+#ifndef __OMAP_COMMON_BOARD_DEVICES__
+#define __OMAP_COMMON_BOARD_DEVICES__
+
+struct twl4030_platform_data;
+struct mtd_partition;
+
+void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+                    struct twl4030_platform_data *pmic_data);
+
+static inline void omap2_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap3_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap4_pmic_init(const char *pmic_type,
+                                   struct twl4030_platform_data *pmic_data)
+{
+        /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
+        omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+}
+
+struct ads7846_platform_data;
+
+void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
+                       struct ads7846_platform_data *board_pdata);
+void omap_nand_flash_init(int opts, struct mtd_partition *parts, int n_parts);
+
+#endif /* __OMAP_COMMON_BOARD_DEVICES__ */
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 1c240eff3918..4bf6e6e8b100 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,36 +36,6 @@
 
 #ifdef CONFIG_CPU_IDLE
 
-#define OMAP3_MAX_STATES 7
-#define OMAP3_STATE_C1 0 /* C1 - MPU WFI + Core active */
-#define OMAP3_STATE_C2 1 /* C2 - MPU WFI + Core inactive */
-#define OMAP3_STATE_C3 2 /* C3 - MPU CSWR + Core inactive */
-#define OMAP3_STATE_C4 3 /* C4 - MPU OFF + Core iactive */
-#define OMAP3_STATE_C5 4 /* C5 - MPU RET + Core RET */
-#define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
-#define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
-
-#define OMAP3_STATE_MAX OMAP3_STATE_C7
-
-#define CPUIDLE_FLAG_CHECK_BM   0x10000 /* use omap3_enter_idle_bm() */
-
-struct omap3_processor_cx {
-        u8 valid;
-        u8 type;
-        u32 sleep_latency;
-        u32 wakeup_latency;
-        u32 mpu_state;
-        u32 core_state;
-        u32 threshold;
-        u32 flags;
-        const char *desc;
-};
-
-struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
-struct omap3_processor_cx current_cx_state;
-struct powerdomain *mpu_pd, *core_pd, *per_pd;
-struct powerdomain *cam_pd;
-
 /*
  * The latencies/thresholds for various C states have
  * to be configured from the respective board files.
@@ -75,27 +45,31 @@ struct powerdomain *cam_pd;
  */
 static struct cpuidle_params cpuidle_params_table[] = {
         /* C1 */
-        {1, 2, 2, 5},
+        {2 + 2, 5, 1},
         /* C2 */
-        {1, 10, 10, 30},
+        {10 + 10, 30, 1},
         /* C3 */
-        {1, 50, 50, 300},
+        {50 + 50, 300, 1},
         /* C4 */
-        {1, 1500, 1800, 4000},
+        {1500 + 1800, 4000, 1},
         /* C5 */
-        {1, 2500, 7500, 12000},
+        {2500 + 7500, 12000, 1},
         /* C6 */
-        {1, 3000, 8500, 15000},
+        {3000 + 8500, 15000, 1},
         /* C7 */
-        {1, 10000, 30000, 300000},
+        {10000 + 30000, 300000, 1},
 };
+#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
 
-static int omap3_idle_bm_check(void)
-{
-        if (!omap3_can_sleep())
-                return 1;
-        return 0;
-}
+/* Mach specific information to be recorded in the C-state driver_data */
+struct omap3_idle_statedata {
+        u32 mpu_state;
+        u32 core_state;
+        u8 valid;
+};
+struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
+
+struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
 
 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
                                 struct clockdomain *clkdm)
@@ -122,12 +96,10 @@ static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
 static int omap3_enter_idle(struct cpuidle_device *dev,
                         struct cpuidle_state *state)
 {
-        struct omap3_processor_cx *cx = cpuidle_get_statedata(state);
+        struct omap3_idle_statedata *cx = cpuidle_get_statedata(state);
         struct timespec ts_preidle, ts_postidle, ts_idle;
         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 
-        current_cx_state = *cx;
-
         /* Used to keep track of the total time in idle */
         getnstimeofday(&ts_preidle);
 
@@ -140,7 +112,8 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
         if (omap_irq_pending() || need_resched())
                 goto return_sleep_time;
 
-        if (cx->type == OMAP3_STATE_C1) {
+        /* Deny idle for C1 */
+        if (state == &dev->states[0]) {
                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
         }
@@ -148,7 +121,8 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
         /* Execute ARM wfi */
         omap_sram_idle();
 
-        if (cx->type == OMAP3_STATE_C1) {
+        /* Re-allow idle for C1 */
+        if (state == &dev->states[0]) {
                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
         }
@@ -164,41 +138,53 @@ return_sleep_time:
 }
 
 /**
- * next_valid_state - Find next valid c-state
+ * next_valid_state - Find next valid C-state
  * @dev: cpuidle device
- * @state: Currently selected c-state
+ * @state: Currently selected C-state
  *
  * If the current state is valid, it is returned back to the caller.
  * Else, this function searches for a lower c-state which is still
- * valid (as defined in omap3_power_states[]).
+ * valid.
+ *
+ * A state is valid if the 'valid' field is enabled and
+ * if it satisfies the enable_off_mode condition.
  */
 static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
-                                                struct cpuidle_state *curr)
+                                              struct cpuidle_state *curr)
 {
         struct cpuidle_state *next = NULL;
-        struct omap3_processor_cx *cx;
+        struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr);
+        u32 mpu_deepest_state = PWRDM_POWER_RET;
+        u32 core_deepest_state = PWRDM_POWER_RET;
 
-        cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
+        if (enable_off_mode) {
+                mpu_deepest_state = PWRDM_POWER_OFF;
+                /*
+                 * Erratum i583: valable for ES rev < Es1.2 on 3630.
+                 * CORE OFF mode is not supported in a stable form, restrict
+                 * instead the CORE state to RET.
+                 */
+                if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
+                        core_deepest_state = PWRDM_POWER_OFF;
+        }
 
         /* Check if current state is valid */
-        if (cx->valid) {
+        if ((cx->valid) &&
+            (cx->mpu_state >= mpu_deepest_state) &&
+            (cx->core_state >= core_deepest_state)) {
                 return curr;
         } else {
-                u8 idx = OMAP3_STATE_MAX;
+                int idx = OMAP3_NUM_STATES - 1;
 
-                /*
-                 * Reach the current state starting at highest C-state
-                 */
-                for (; idx >= OMAP3_STATE_C1; idx--) {
+                /* Reach the current state starting at highest C-state */
+                for (; idx >= 0; idx--) {
                         if (&dev->states[idx] == curr) {
                                 next = &dev->states[idx];
                                 break;
                         }
                 }
 
-                /*
-                 * Should never hit this condition.
-                 */
+                /* Should never hit this condition */
                 WARN_ON(next == NULL);
 
                 /*
@@ -206,17 +192,17 @@ static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
                  * Start search from the next (lower) state.
                  */
                 idx--;
-                for (; idx >= OMAP3_STATE_C1; idx--) {
-                        struct omap3_processor_cx *cx;
-
+                for (; idx >= 0; idx--) {
                         cx = cpuidle_get_statedata(&dev->states[idx]);
-                        if (cx->valid) {
+                        if ((cx->valid) &&
+                            (cx->mpu_state >= mpu_deepest_state) &&
+                            (cx->core_state >= core_deepest_state)) {
                                 next = &dev->states[idx];
                                 break;
                         }
                 }
                 /*
-                 * C1 and C2 are always valid.
+                 * C1 is always valid.
                  * So, no need to check for 'next==NULL' outside this loop.
                  */
         }
@@ -229,36 +215,22 @@ static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
  * @dev: cpuidle device
  * @state: The target state to be programmed
  *
- * Used for C states with CPUIDLE_FLAG_CHECK_BM flag set. This
- * function checks for any pending activity and then programs the
- * device to the specified or a safer state.
+ * This function checks for any pending activity and then programs
+ * the device to the specified or a safer state.
  */
 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
                                struct cpuidle_state *state)
 {
-        struct cpuidle_state *new_state = next_valid_state(dev, state);
-        u32 core_next_state, per_next_state = 0, per_saved_state = 0;
-        u32 cam_state;
-        struct omap3_processor_cx *cx;
+        struct cpuidle_state *new_state;
+        u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
+        struct omap3_idle_statedata *cx;
         int ret;
 
-        if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
-                BUG_ON(!dev->safe_state);
+        if (!omap3_can_sleep()) {
                 new_state = dev->safe_state;
                 goto select_state;
         }
 
-        cx = cpuidle_get_statedata(state);
-        core_next_state = cx->core_state;
-
-        /*
-         * FIXME: we currently manage device-specific idle states
-         *        for PER and CORE in combination with CPU-specific
-         *        idle states.  This is wrong, and device-specific
-         *        idle management needs to be separated out into 
-         *        its own code.
-         */
-
         /*
          * Prevent idle completely if CAM is active.
          * CAM does not have wakeup capability in OMAP3.
@@ -270,9 +242,19 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
         }
 
         /*
+         * FIXME: we currently manage device-specific idle states
+         *        for PER and CORE in combination with CPU-specific
+         *        idle states.  This is wrong, and device-specific
+         *        idle management needs to be separated out into
+         *        its own code.
+         */
+
+        /*
          * Prevent PER off if CORE is not in retention or off as this
          * would disable PER wakeups completely.
          */
+        cx = cpuidle_get_statedata(state);
+        core_next_state = cx->core_state;
         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
         if ((per_next_state == PWRDM_POWER_OFF) &&
             (core_next_state > PWRDM_POWER_RET))
@@ -282,6 +264,8 @@ static int omap3_enter_idle_bm(struct cpuidle_device *dev,
         if (per_next_state != per_saved_state)
                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 
+        new_state = next_valid_state(dev, state);
+
 select_state:
         dev->last_state = new_state;
         ret = omap3_enter_idle(dev, new_state);
@@ -295,31 +279,6 @@ select_state:
 
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 
-/**
- * omap3_cpuidle_update_states() - Update the cpuidle states
- * @mpu_deepest_state:  Enable states up to and including this for mpu domain
- * @core_deepest_state: Enable states up to and including this for core domain
- *
- * This goes through the list of states available and enables and disables the
- * validity of C states based on deepest state that can be achieved for the
- * variable domain
- */
-void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
-{
-        int i;
-
-        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
-                struct omap3_processor_cx *cx = &omap3_power_states[i];
-
-                if ((cx->mpu_state >= mpu_deepest_state) &&
-                    (cx->core_state >= core_deepest_state)) {
-                        cx->valid = 1;
-                } else {
-                        cx->valid = 0;
-                }
-        }
-}
-
 void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
 {
         int i;
@@ -327,212 +286,109 @@ void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
         if (!cpuidle_board_params)
                 return;
 
-        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
-                cpuidle_params_table[i].valid =
-                        cpuidle_board_params[i].valid;
-                cpuidle_params_table[i].sleep_latency =
-                        cpuidle_board_params[i].sleep_latency;
-                cpuidle_params_table[i].wake_latency =
-                        cpuidle_board_params[i].wake_latency;
-                cpuidle_params_table[i].threshold =
-                        cpuidle_board_params[i].threshold;
+        for (i = 0; i < OMAP3_NUM_STATES; i++) {
+                cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
+                cpuidle_params_table[i].exit_latency =
+                        cpuidle_board_params[i].exit_latency;
+                cpuidle_params_table[i].target_residency =
+                        cpuidle_board_params[i].target_residency;
         }
         return;
 }
 
-/* omap3_init_power_states - Initialises the OMAP3 specific C states.
- *
- * Below is the desciption of each C state.
- *      C1 . MPU WFI + Core active
- *      C2 . MPU WFI + Core inactive
- *      C3 . MPU CSWR + Core inactive
- *      C4 . MPU OFF + Core inactive
- *      C5 . MPU CSWR + Core CSWR
- *      C6 . MPU OFF + Core CSWR
- *      C7 . MPU OFF + Core OFF
- */
-void omap_init_power_states(void)
-{
-        /* C1 . MPU WFI + Core active */
-        omap3_power_states[OMAP3_STATE_C1].valid =
-                        cpuidle_params_table[OMAP3_STATE_C1].valid;
-        omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
-        omap3_power_states[OMAP3_STATE_C1].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
-        omap3_power_states[OMAP3_STATE_C1].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C1].threshold;
-        omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
-        omap3_power_states[OMAP3_STATE_C1].desc = "MPU ON + CORE ON";
-
-        /* C2 . MPU WFI + Core inactive */
-        omap3_power_states[OMAP3_STATE_C2].valid =
-                        cpuidle_params_table[OMAP3_STATE_C2].valid;
-        omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
-        omap3_power_states[OMAP3_STATE_C2].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
-        omap3_power_states[OMAP3_STATE_C2].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C2].threshold;
-        omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-        omap3_power_states[OMAP3_STATE_C2].desc = "MPU ON + CORE ON";
-
-        /* C3 . MPU CSWR + Core inactive */
-        omap3_power_states[OMAP3_STATE_C3].valid =
-                        cpuidle_params_table[OMAP3_STATE_C3].valid;
-        omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
-        omap3_power_states[OMAP3_STATE_C3].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
-        omap3_power_states[OMAP3_STATE_C3].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C3].threshold;
-        omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-        omap3_power_states[OMAP3_STATE_C3].desc = "MPU RET + CORE ON";
-
-        /* C4 . MPU OFF + Core inactive */
-        omap3_power_states[OMAP3_STATE_C4].valid =
-                        cpuidle_params_table[OMAP3_STATE_C4].valid;
-        omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
-        omap3_power_states[OMAP3_STATE_C4].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
-        omap3_power_states[OMAP3_STATE_C4].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C4].threshold;
-        omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
-        omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-        omap3_power_states[OMAP3_STATE_C4].desc = "MPU OFF + CORE ON";
-
-        /* C5 . MPU CSWR + Core CSWR*/
-        omap3_power_states[OMAP3_STATE_C5].valid =
-                        cpuidle_params_table[OMAP3_STATE_C5].valid;
-        omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
-        omap3_power_states[OMAP3_STATE_C5].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
-        omap3_power_states[OMAP3_STATE_C5].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C5].threshold;
-        omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-        omap3_power_states[OMAP3_STATE_C5].desc = "MPU RET + CORE RET";
-
-        /* C6 . MPU OFF + Core CSWR */
-        omap3_power_states[OMAP3_STATE_C6].valid =
-                        cpuidle_params_table[OMAP3_STATE_C6].valid;
-        omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
-        omap3_power_states[OMAP3_STATE_C6].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
-        omap3_power_states[OMAP3_STATE_C6].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C6].threshold;
-        omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
-        omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-        omap3_power_states[OMAP3_STATE_C6].desc = "MPU OFF + CORE RET";
-
-        /* C7 . MPU OFF + Core OFF */
-        omap3_power_states[OMAP3_STATE_C7].valid =
-                        cpuidle_params_table[OMAP3_STATE_C7].valid;
-        omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
-        omap3_power_states[OMAP3_STATE_C7].sleep_latency =
-                        cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
-        omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
-                        cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
-        omap3_power_states[OMAP3_STATE_C7].threshold =
-                        cpuidle_params_table[OMAP3_STATE_C7].threshold;
-        omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
-        omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
-                                CPUIDLE_FLAG_CHECK_BM;
-        omap3_power_states[OMAP3_STATE_C7].desc = "MPU OFF + CORE OFF";
-
-        /*
-         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
-         * enable OFF mode in a stable form for previous revisions.
-         * we disable C7 state as a result.
-         */
-        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
-                omap3_power_states[OMAP3_STATE_C7].valid = 0;
-                cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
-                pr_warn("%s: core off state C7 disabled due to i583\n",
-                                __func__);
-        }
-}
-
 struct cpuidle_driver omap3_idle_driver = {
         .name =         "omap3_idle",
         .owner =        THIS_MODULE,
 };
 
+/* Helper to fill the C-state common data and register the driver_data */
+static inline struct omap3_idle_statedata *_fill_cstate(
+                                        struct cpuidle_device *dev,
+                                        int idx, const char *descr)
+{
+        struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
+        struct cpuidle_state *state = &dev->states[idx];
+
+        state->exit_latency     = cpuidle_params_table[idx].exit_latency;
+        state->target_residency = cpuidle_params_table[idx].target_residency;
+        state->flags            = CPUIDLE_FLAG_TIME_VALID;
+        state->enter            = omap3_enter_idle_bm;
+        cx->valid               = cpuidle_params_table[idx].valid;
+        sprintf(state->name, "C%d", idx + 1);
+        strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
+        cpuidle_set_statedata(state, cx);
+
+        return cx;
+}
+
 /**
  * omap3_idle_init - Init routine for OMAP3 idle
  *
- * Registers the OMAP3 specific cpuidle driver with the cpuidle
+ * Registers the OMAP3 specific cpuidle driver to the cpuidle
  * framework with the valid set of states.
  */
 int __init omap3_idle_init(void)
 {
-        int i, count = 0;
-        struct omap3_processor_cx *cx;
-        struct cpuidle_state *state;
         struct cpuidle_device *dev;
+        struct omap3_idle_statedata *cx;
 
         mpu_pd = pwrdm_lookup("mpu_pwrdm");
         core_pd = pwrdm_lookup("core_pwrdm");
         per_pd = pwrdm_lookup("per_pwrdm");
         cam_pd = pwrdm_lookup("cam_pwrdm");
 
-        omap_init_power_states();
         cpuidle_register_driver(&omap3_idle_driver);
-
         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 
-        for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
-                cx = &omap3_power_states[i];
-                state = &dev->states[count];
-
-                if (!cx->valid)
-                        continue;
-                cpuidle_set_statedata(state, cx);
-                state->exit_latency = cx->sleep_latency + cx->wakeup_latency;
-                state->target_residency = cx->threshold;
-                state->flags = cx->flags;
-                state->enter = (state->flags & CPUIDLE_FLAG_CHECK_BM) ?
-                        omap3_enter_idle_bm : omap3_enter_idle;
-                if (cx->type == OMAP3_STATE_C1)
-                        dev->safe_state = state;
-                sprintf(state->name, "C%d", count+1);
-                strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
-                count++;
-        }
+        /* C1 . MPU WFI + Core active */
+        cx = _fill_cstate(dev, 0, "MPU ON + CORE ON");
+        (&dev->states[0])->enter = omap3_enter_idle;
+        dev->safe_state = &dev->states[0];
+        cx->valid = 1;  /* C1 is always valid */
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->core_state = PWRDM_POWER_ON;
 
-        if (!count)
-                return -EINVAL;
-        dev->state_count = count;
+        /* C2 . MPU WFI + Core inactive */
+        cx = _fill_cstate(dev, 1, "MPU ON + CORE ON");
+        cx->mpu_state = PWRDM_POWER_ON;
+        cx->core_state = PWRDM_POWER_ON;
+
+        /* C3 . MPU CSWR + Core inactive */
+        cx = _fill_cstate(dev, 2, "MPU RET + CORE ON");
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->core_state = PWRDM_POWER_ON;
 
-        if (enable_off_mode)
-                omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
-        else
-                omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
+        /* C4 . MPU OFF + Core inactive */
+        cx = _fill_cstate(dev, 3, "MPU OFF + CORE ON");
+        cx->mpu_state = PWRDM_POWER_OFF;
+        cx->core_state = PWRDM_POWER_ON;
+
+        /* C5 . MPU RET + Core RET */
+        cx = _fill_cstate(dev, 4, "MPU RET + CORE RET");
+        cx->mpu_state = PWRDM_POWER_RET;
+        cx->core_state = PWRDM_POWER_RET;
+
+        /* C6 . MPU OFF + Core RET */
+        cx = _fill_cstate(dev, 5, "MPU OFF + CORE RET");
+        cx->mpu_state = PWRDM_POWER_OFF;
+        cx->core_state = PWRDM_POWER_RET;
+
+        /* C7 . MPU OFF + Core OFF */
+        cx = _fill_cstate(dev, 6, "MPU OFF + CORE OFF");
+        /*
+         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
+         * enable OFF mode in a stable form for previous revisions.
+         * We disable C7 state as a result.
+         */
+        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
+                cx->valid = 0;
+                pr_warn("%s: core off state C7 disabled due to i583\n",
+                        __func__);
+        }
+        cx->mpu_state = PWRDM_POWER_OFF;
+        cx->core_state = PWRDM_POWER_OFF;
 
+        dev->state_count = OMAP3_NUM_STATES;
         if (cpuidle_register_device(dev)) {
                 printk(KERN_ERR "%s: CPUidle register device failed\n",
                        __func__);
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 256d23fb79ab..543fcb8b518c 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -22,7 +22,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 
-#include <plat/display.h>
+#include <video/omapdss.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
 
@@ -56,37 +56,58 @@ static bool opt_clock_available(const char *clk_role)
         return false;
 }
 
+struct omap_dss_hwmod_data {
+        const char *oh_name;
+        const char *dev_name;
+        const int id;
+};
+
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+        { "dss_core", "omapdss_dss", -1 },
+        { "dss_dispc", "omapdss_dispc", -1 },
+        { "dss_rfbi", "omapdss_rfbi", -1 },
+        { "dss_venc", "omapdss_venc", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+        { "dss_core", "omapdss_dss", -1 },
+        { "dss_dispc", "omapdss_dispc", -1 },
+        { "dss_rfbi", "omapdss_rfbi", -1 },
+        { "dss_venc", "omapdss_venc", -1 },
+        { "dss_dsi1", "omapdss_dsi1", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+        { "dss_core", "omapdss_dss", -1 },
+        { "dss_dispc", "omapdss_dispc", -1 },
+        { "dss_rfbi", "omapdss_rfbi", -1 },
+        { "dss_venc", "omapdss_venc", -1 },
+        { "dss_dsi1", "omapdss_dsi1", -1 },
+        { "dss_dsi2", "omapdss_dsi2", -1 },
+        { "dss_hdmi", "omapdss_hdmi", -1 },
+};
+
 int __init omap_display_init(struct omap_dss_board_info *board_data)
 {
         int r = 0;
         struct omap_hwmod *oh;
         struct omap_device *od;
-        int i;
+        int i, oh_count;
         struct omap_display_platform_data pdata;
-
-        /*
-         * omap: valid DSS hwmod names
-         * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc
-         * omap3,4: dss_dsi1
-         * omap4: dss_dsi2, dss_hdmi
-         */
-        char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc",
-                "dss_dsi1", "dss_dsi2", "dss_hdmi" };
-        char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi",
-                "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2",
-                "omapdss_hdmi" };
-        int oh_count;
+        const struct omap_dss_hwmod_data *curr_dss_hwmod;
 
         memset(&pdata, 0, sizeof(pdata));
 
-        if (cpu_is_omap24xx())
-                oh_count = ARRAY_SIZE(oh_name) - 3;
-                /* last 3 hwmod dev in oh_name are not available for omap2 */
-        else if (cpu_is_omap44xx())
-                oh_count = ARRAY_SIZE(oh_name);
-        else
-                oh_count = ARRAY_SIZE(oh_name) - 2;
-                /* last 2 hwmod dev in oh_name are not available for omap3 */
+        if (cpu_is_omap24xx()) {
+                curr_dss_hwmod = omap2_dss_hwmod_data;
+                oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
+        } else if (cpu_is_omap34xx()) {
+                curr_dss_hwmod = omap3_dss_hwmod_data;
+                oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
+        } else {
+                curr_dss_hwmod = omap4_dss_hwmod_data;
+                oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
+        }
 
         /* opt_clks are always associated with dss hwmod */
         oh_core = omap_hwmod_lookup("dss_core");
@@ -100,19 +121,21 @@ int __init omap_display_init(struct omap_dss_board_info *board_data)
         pdata.opt_clock_available = opt_clock_available;
 
         for (i = 0; i < oh_count; i++) {
-                oh = omap_hwmod_lookup(oh_name[i]);
+                oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
                 if (!oh) {
-                        pr_err("Could not look up %s\n", oh_name[i]);
+                        pr_err("Could not look up %s\n",
+                                curr_dss_hwmod[i].oh_name);
                         return -ENODEV;
                 }
 
-                od = omap_device_build(dev_name[i], -1, oh, &pdata,
+                od = omap_device_build(curr_dss_hwmod[i].dev_name,
+                                curr_dss_hwmod[i].id, oh, &pdata,
                                 sizeof(struct omap_display_platform_data),
                                 omap_dss_latency,
                                 ARRAY_SIZE(omap_dss_latency), 0);
 
                 if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
-                                oh_name[i]))
+                                curr_dss_hwmod[i].oh_name))
                         return -ENODEV;
         }
         omap_display_device.dev.platform_data = board_data;
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
index 877c6f5807b7..ba10c24f3d8d 100644
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ b/arch/arm/mach-omap2/gpmc-smc91x.c
@@ -147,25 +147,24 @@ void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
                         goto free1;
         }
 
-        if (gpio_request(gpmc_cfg->gpio_irq, "SMC91X irq") < 0)
+        if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "SMC91X irq") < 0)
                 goto free1;
 
-        gpio_direction_input(gpmc_cfg->gpio_irq);
         gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
 
         if (gpmc_cfg->gpio_pwrdwn) {
-                ret = gpio_request(gpmc_cfg->gpio_pwrdwn, "SMC91X powerdown");
+                ret = gpio_request_one(gpmc_cfg->gpio_pwrdwn,
+                                       GPIOF_OUT_INIT_LOW, "SMC91X powerdown");
                 if (ret)
                         goto free2;
-                gpio_direction_output(gpmc_cfg->gpio_pwrdwn, 0);
         }
 
         if (gpmc_cfg->gpio_reset) {
-                ret = gpio_request(gpmc_cfg->gpio_reset, "SMC91X reset");
+                ret = gpio_request_one(gpmc_cfg->gpio_reset,
+                                       GPIOF_OUT_INIT_LOW, "SMC91X reset");
                 if (ret)
                         goto free3;
 
-                gpio_direction_output(gpmc_cfg->gpio_reset, 0);
                 gpio_set_value(gpmc_cfg->gpio_reset, 1);
                 msleep(100);
                 gpio_set_value(gpmc_cfg->gpio_reset, 0);
diff --git a/arch/arm/mach-omap2/gpmc-smsc911x.c b/arch/arm/mach-omap2/gpmc-smsc911x.c
index 703f150dd01d..997033129d26 100644
--- a/arch/arm/mach-omap2/gpmc-smsc911x.c
+++ b/arch/arm/mach-omap2/gpmc-smsc911x.c
@@ -10,6 +10,7 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#define pr_fmt(fmt) "%s: " fmt, __func__
 
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
@@ -30,7 +31,7 @@ static struct resource gpmc_smsc911x_resources[] = {
                 .flags          = IORESOURCE_MEM,
         },
         [1] = {
-                .flags          = IORESOURCE_IRQ,
+                .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
         },
 };
 
@@ -41,16 +42,6 @@ static struct smsc911x_platform_config gpmc_smsc911x_config = {
         .flags          = SMSC911X_USE_16BIT,
 };
 
-static struct platform_device gpmc_smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(gpmc_smsc911x_resources),
-        .resource       = gpmc_smsc911x_resources,
-        .dev            = {
-                .platform_data = &gpmc_smsc911x_config,
-        },
-};
-
 /*
  * Initialize smsc911x device connected to the GPMC. Note that we
  * assume that pin multiplexing is done in the board-*.c file,
@@ -58,46 +49,49 @@ static struct platform_device gpmc_smsc911x_device = {
  */
 void __init gpmc_smsc911x_init(struct omap_smsc911x_platform_data *board_data)
 {
+        struct platform_device *pdev;
         unsigned long cs_mem_base;
         int ret;
 
         gpmc_cfg = board_data;
 
         if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
-                printk(KERN_ERR "Failed to request GPMC mem for smsc911x\n");
+                pr_err("Failed to request GPMC mem region\n");
                 return;
         }
 
         gpmc_smsc911x_resources[0].start = cs_mem_base + 0x0;
         gpmc_smsc911x_resources[0].end = cs_mem_base + 0xff;
 
-        if (gpio_request(gpmc_cfg->gpio_irq, "smsc911x irq") < 0) {
-                printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
-                                gpmc_cfg->gpio_irq);
+        if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "smsc911x irq")) {
+                pr_err("Failed to request IRQ GPIO%d\n", gpmc_cfg->gpio_irq);
                 goto free1;
         }
 
-        gpio_direction_input(gpmc_cfg->gpio_irq);
         gpmc_smsc911x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
-        gpmc_smsc911x_resources[1].flags |=
-                                        (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
 
         if (gpio_is_valid(gpmc_cfg->gpio_reset)) {
-                ret = gpio_request(gpmc_cfg->gpio_reset, "smsc911x reset");
+                ret = gpio_request_one(gpmc_cfg->gpio_reset,
+                                       GPIOF_OUT_INIT_HIGH, "smsc911x reset");
                 if (ret) {
-                        printk(KERN_ERR "Failed to request GPIO%d for smsc911x reset\n",
-                                        gpmc_cfg->gpio_reset);
+                        pr_err("Failed to request reset GPIO%d\n",
+                               gpmc_cfg->gpio_reset);
                         goto free2;
                 }
 
-                gpio_direction_output(gpmc_cfg->gpio_reset, 1);
                 gpio_set_value(gpmc_cfg->gpio_reset, 0);
                 msleep(100);
                 gpio_set_value(gpmc_cfg->gpio_reset, 1);
         }
 
-        if (platform_device_register(&gpmc_smsc911x_device) < 0) {
-                printk(KERN_ERR "Unable to register smsc911x device\n");
+        if (gpmc_cfg->flags)
+                gpmc_smsc911x_config.flags = gpmc_cfg->flags;
+
+        pdev = platform_device_register_resndata(NULL, "smsc911x", gpmc_cfg->id,
+                 gpmc_smsc911x_resources, ARRAY_SIZE(gpmc_smsc911x_resources),
+                 &gpmc_smsc911x_config, sizeof(gpmc_smsc911x_config));
+        if (!pdev) {
+                pr_err("Unable to register platform device\n");
                 gpio_free(gpmc_cfg->gpio_reset);
                 goto free2;
         }
@@ -109,5 +103,5 @@ free2:
 free1:
         gpmc_cs_free(gpmc_cfg->cs);
 
-        printk(KERN_ERR "Could not initialize smsc911x\n");
+        pr_err("Could not initialize smsc911x device\n");
 }
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index d20bd9c1a106..775fdc3b000b 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,7 +1,7 @@
 /*
  * Defines for zoom boards
  */
-#include <plat/display.h>
+#include <video/omapdss.h>
 
 #define ZOOM_NAND_CS    0
 
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
index 82632c24076f..7b9f1909ddb2 100644
--- a/arch/arm/mach-omap2/omap_l3_noc.c
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -63,10 +63,7 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
         char *source_name;
 
         /* Get the Type of interrupt */
-        if (irq == l3->app_irq)
-                inttype = L3_APPLICATION_ERROR;
-        else
-                inttype = L3_DEBUG_ERROR;
+        inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
 
         for (i = 0; i < L3_MODULES; i++) {
                 /*
@@ -84,10 +81,10 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
 
                         err_src = j;
                         /* Read the stderrlog_main_source from clk domain */
-                        std_err_main_addr = base + (*(l3_targ[i] + err_src));
-                        std_err_main =  readl(std_err_main_addr);
+                        std_err_main_addr = base + *(l3_targ[i] + err_src);
+                        std_err_main = readl(std_err_main_addr);
 
-                        switch ((std_err_main & CUSTOM_ERROR)) {
+                        switch (std_err_main & CUSTOM_ERROR) {
                         case STANDARD_ERROR:
                                 source_name =
                                 l3_targ_stderrlog_main_name[i][err_src];
@@ -132,49 +129,49 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
 
         l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
         if (!l3)
-                ret = -ENOMEM;
+                return -ENOMEM;
 
         platform_set_drvdata(pdev, l3);
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!res) {
                 dev_err(&pdev->dev, "couldn't find resource 0\n");
                 ret = -ENODEV;
-                goto err1;
+                goto err0;
         }
 
         l3->l3_base[0] = ioremap(res->start, resource_size(res));
-        if (!(l3->l3_base[0])) {
+        if (!l3->l3_base[0]) {
                 dev_err(&pdev->dev, "ioremap failed\n");
                 ret = -ENOMEM;
-                goto err2;
+                goto err0;
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
         if (!res) {
                 dev_err(&pdev->dev, "couldn't find resource 1\n");
                 ret = -ENODEV;
-                goto err3;
+                goto err1;
         }
 
         l3->l3_base[1] = ioremap(res->start, resource_size(res));
-        if (!(l3->l3_base[1])) {
+        if (!l3->l3_base[1]) {
                 dev_err(&pdev->dev, "ioremap failed\n");
                 ret = -ENOMEM;
-                goto err4;
+                goto err1;
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
         if (!res) {
                 dev_err(&pdev->dev, "couldn't find resource 2\n");
                 ret = -ENODEV;
-                goto err5;
+                goto err2;
         }
 
         l3->l3_base[2] = ioremap(res->start, resource_size(res));
-        if (!(l3->l3_base[2])) {
+        if (!l3->l3_base[2]) {
                 dev_err(&pdev->dev, "ioremap failed\n");
                 ret = -ENOMEM;
-                goto err6;
+                goto err2;
         }
 
         /*
@@ -187,7 +184,7 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
         if (ret) {
                 pr_crit("L3: request_irq failed to register for 0x%x\n",
                                          OMAP44XX_IRQ_L3_DBG);
-                goto err7;
+                goto err3;
         }
         l3->debug_irq = irq;
 
@@ -198,24 +195,22 @@ static int __init omap4_l3_probe(struct platform_device *pdev)
         if (ret) {
                 pr_crit("L3: request_irq failed to register for 0x%x\n",
                                          OMAP44XX_IRQ_L3_APP);
-                goto err8;
+                goto err4;
         }
         l3->app_irq = irq;
 
-        goto err0;
-err8:
-err7:
-        iounmap(l3->l3_base[2]);
-err6:
-err5:
-        iounmap(l3->l3_base[1]);
+        return 0;
+
 err4:
+        free_irq(l3->debug_irq, l3);
 err3:
-        iounmap(l3->l3_base[0]);
+        iounmap(l3->l3_base[2]);
 err2:
+        iounmap(l3->l3_base[1]);
 err1:
-        kfree(l3);
+        iounmap(l3->l3_base[0]);
 err0:
+        kfree(l3);
         return ret;
 }
 
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
index 4321e7938929..873c0e33b512 100644
--- a/arch/arm/mach-omap2/omap_l3_smx.c
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -155,7 +155,7 @@ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
         u8                      multi = error & L3_ERROR_LOG_MULTI;
         u32                     address = omap3_l3_decode_addr(error_addr);
 
-        WARN(true, "%s Error seen by %s %s at address %x\n",
+        WARN(true, "%s seen by %s %s at address %x\n",
                                  omap3_l3_code_string(code),
                           omap3_l3_initiator_string(initid),
                              multi ? "Multiple Errors" : "",
@@ -167,21 +167,15 @@ static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
 static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
 {
         struct omap3_l3         *l3 = _l3;
-
         u64                     status, clear;
         u64                     error;
         u64                     error_addr;
         u64                     err_source = 0;
         void                    __iomem *base;
         int                     int_type;
-
         irqreturn_t             ret = IRQ_NONE;
 
-        if (irq == l3->app_irq)
-                int_type = L3_APPLICATION_ERROR;
-        else
-                int_type = L3_DEBUG_ERROR;
-
+        int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
         if (!int_type) {
                 status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
                 /*
@@ -202,7 +196,6 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
 
         base = l3->rt + *(omap3_l3_bases[int_type] + err_source);
         error = omap3_l3_readll(base, L3_ERROR_LOG);
-
         if (error) {
                 error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
 
@@ -210,9 +203,8 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
         }
 
         /* Clear the status register */
-        clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) |
-                 (L3_AGENT_STATUS_CLEAR_TA));
-
+        clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
+                L3_AGENT_STATUS_CLEAR_TA;
         omap3_l3_writell(base, L3_AGENT_STATUS, clear);
 
         /* clear the error log register */
@@ -228,10 +220,8 @@ static int __init omap3_l3_probe(struct platform_device *pdev)
         int                     ret;
 
         l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
-        if (!l3) {
-                ret = -ENOMEM;
-                goto err0;
-        }
+        if (!l3)
+                return -ENOMEM;
 
         platform_set_drvdata(pdev, l3);
 
@@ -239,13 +229,13 @@ static int __init omap3_l3_probe(struct platform_device *pdev)
         if (!res) {
                 dev_err(&pdev->dev, "couldn't find resource\n");
                 ret = -ENODEV;
-                goto err1;
+                goto err0;
         }
         l3->rt = ioremap(res->start, resource_size(res));
-        if (!(l3->rt)) {
+        if (!l3->rt) {
                 dev_err(&pdev->dev, "ioremap failed\n");
                 ret = -ENOMEM;
-                goto err2;
+                goto err0;
         }
 
         l3->debug_irq = platform_get_irq(pdev, 0);
@@ -254,28 +244,26 @@ static int __init omap3_l3_probe(struct platform_device *pdev)
                 "l3-debug-irq", l3);
         if (ret) {
                 dev_err(&pdev->dev, "couldn't request debug irq\n");
-                goto err3;
+                goto err1;
         }
 
         l3->app_irq = platform_get_irq(pdev, 1);
         ret = request_irq(l3->app_irq, omap3_l3_app_irq,
                 IRQF_DISABLED | IRQF_TRIGGER_RISING,
                 "l3-app-irq", l3);
-
         if (ret) {
                 dev_err(&pdev->dev, "couldn't request app irq\n");
-                goto err4;
+                goto err2;
         }
 
-        goto err0;
+        return 0;
 
-err4:
-err3:
-        iounmap(l3->rt);
 err2:
+        free_irq(l3->debug_irq, l3);
 err1:
-        kfree(l3);
+        iounmap(l3->rt);
 err0:
+        kfree(l3);
         return ret;
 }
 
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index 05f6abc96b0d..f47813edd951 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -50,13 +50,16 @@ int omap4430_phy_init(struct device *dev)
 {
         ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
         if (!ctrl_base) {
-                dev_err(dev, "control module ioremap failed\n");
+                pr_err("control module ioremap failed\n");
                 return -ENOMEM;
         }
         /* Power down the phy */
         __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
-        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
 
+        if (!dev)
+                return 0;
+
+        phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
         if (IS_ERR(phyclk)) {
                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
                 iounmap(ctrl_base);
@@ -228,7 +231,7 @@ void am35x_musb_clear_irq(void)
         regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
 }
 
-void am35x_musb_set_mode(u8 musb_mode)
+void am35x_set_mode(u8 musb_mode)
 {
         u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
 
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 797bfd12b643..45bcfce77352 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -36,11 +36,16 @@ static inline int omap4_opp_init(void)
 }
 #endif
 
+/*
+ * cpuidle mach specific parameters
+ *
+ * The board code can override the default C-states definition using
+ * omap3_pm_init_cpuidle
+ */
 struct cpuidle_params {
-        u8  valid;
-        u32 sleep_latency;
-        u32 wake_latency;
-        u32 threshold;
+        u32 exit_latency;       /* exit_latency = sleep + wake-up latencies */
+        u32 target_residency;
+        u8 valid;               /* validates the C-state */
 };
 
 #if defined(CONFIG_PM) && defined(CONFIG_CPU_IDLE)
@@ -73,10 +78,6 @@ extern u32 sleep_while_idle;
 #define sleep_while_idle 0
 #endif
 
-#if defined(CONFIG_CPU_IDLE)
-extern void omap3_cpuidle_update_states(u32, u32);
-#endif
-
 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
 extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
 extern int pm_dbg_regset_save(int reg_set);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0c5e3a46a3ad..c155c9d1c82c 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -779,18 +779,6 @@ void omap3_pm_off_mode_enable(int enable)
         else
                 state = PWRDM_POWER_RET;
 
-#ifdef CONFIG_CPU_IDLE
-        /*
-         * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
-         * enable OFF mode in a stable form for previous revisions, restrict
-         * instead to RET
-         */
-        if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
-                omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
-        else
-                omap3_cpuidle_update_states(state, state);
-#endif
-
         list_for_each_entry(pwrst, &pwrst_list, node) {
                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
                                 pwrst->pwrdm == core_pwrdm &&
@@ -895,8 +883,6 @@ static int __init omap3_pm_init(void)
 
         pm_errata_configure();
 
-        printk(KERN_ERR "Power Management for TI OMAP3.\n");
-
         /* XXX prcm_setup_regs needs to be before enabling hw
          * supervised mode for powerdomains */
         prcm_setup_regs();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 76cfff2db514..59a870be8390 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -105,13 +105,11 @@ static int __init omap4_pm_init(void)
 
         pr_err("Power Management for TI OMAP4.\n");
 
-#ifdef CONFIG_PM
         ret = pwrdm_for_each(pwrdms_setup, NULL);
         if (ret) {
                 pr_err("Failed to setup powerdomains\n");
                 goto err2;
         }
-#endif
 
 #ifdef CONFIG_SUSPEND
         suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 13e24f913dd4..fb7dc52394a8 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -847,6 +847,14 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 goto err_free_devinfo;
         }
 
+        mem = request_mem_region(mem->start, resource_size(mem),
+                                        dev_name(&pdev->dev));
+        if (!mem) {
+                dev_err(&pdev->dev, "%s: no mem region\n", __func__);
+                ret = -EBUSY;
+                goto err_free_devinfo;
+        }
+
         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 
         pm_runtime_enable(&pdev->dev);
@@ -883,7 +891,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 ret = sr_late_init(sr_info);
                 if (ret) {
                         pr_warning("%s: Error in SR late init\n", __func__);
-                        goto err_release_region;
+                        return ret;
                 }
         }
 
@@ -896,7 +904,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
         vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
         if (!vdd_dbg_dir) {
                 ret = -EINVAL;
-                goto err_release_region;
+                goto err_iounmap;
         }
 
         sr_info->dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
@@ -904,7 +912,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
                         __func__);
                 ret = PTR_ERR(sr_info->dbg_dir);
-                goto err_release_region;
+                goto err_iounmap;
         }
 
         (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR,
@@ -921,7 +929,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
                         "for n-values\n", __func__);
                 ret = PTR_ERR(nvalue_dir);
-                goto err_release_region;
+                goto err_debugfs;
         }
 
         omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
@@ -931,7 +939,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                         "entries for n-values\n",
                         __func__, sr_info->voltdm->name);
                 ret = -ENODATA;
-                goto err_release_region;
+                goto err_debugfs;
         }
 
         for (i = 0; i < sr_info->nvalue_count; i++) {
@@ -945,6 +953,11 @@ static int __init omap_sr_probe(struct platform_device *pdev)
 
         return ret;
 
+err_debugfs:
+        debugfs_remove_recursive(sr_info->dbg_dir);
+err_iounmap:
+        list_del(&sr_info->node);
+        iounmap(sr_info->base);
 err_release_region:
         release_mem_region(mem->start, resource_size(mem));
 err_free_devinfo:
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 35559f77e2de..c7ed540d868d 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -108,7 +108,13 @@ static void usb_musb_mux_init(struct omap_musb_board_data *board_data)
         }
 }
 
-void __init usb_musb_init(struct omap_musb_board_data *board_data)
+static struct omap_musb_board_data musb_default_board_data = {
+        .interface_type         = MUSB_INTERFACE_ULPI,
+        .mode                   = MUSB_OTG,
+        .power                  = 100,
+};
+
+void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
 {
         struct omap_hwmod               *oh;
         struct omap_device              *od;
@@ -116,11 +122,12 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
         struct device                   *dev;
         int                             bus_id = -1;
         const char                      *oh_name, *name;
+        struct omap_musb_board_data     *board_data;
 
-        if (cpu_is_omap3517() || cpu_is_omap3505()) {
-        } else if (cpu_is_omap44xx()) {
-                usb_musb_mux_init(board_data);
-        }
+        if (musb_board_data)
+                board_data = musb_board_data;
+        else
+                board_data = &musb_default_board_data;
 
         /*
          * REVISIT: This line can be removed once all the platforms using
@@ -164,10 +171,15 @@ void __init usb_musb_init(struct omap_musb_board_data *board_data)
         dev->dma_mask = &musb_dmamask;
         dev->coherent_dma_mask = musb_dmamask;
         put_device(dev);
+
+        if (cpu_is_omap44xx())
+                omap4430_phy_init(dev);
 }
 
 #else
 void __init usb_musb_init(struct omap_musb_board_data *board_data)
 {
+        if (cpu_is_omap44xx())
+                omap4430_phy_init(NULL);
 }
 #endif /* CONFIG_USB_MUSB_SOC */
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 8a3c05f3c1d6..8dd26b765b7d 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -293,12 +293,11 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
                         );
 
         /* IRQ */
-        status = gpio_request(irq, "TUSB6010 irq");
+        status = gpio_request_one(irq, GPIOF_IN, "TUSB6010 irq");
         if (status < 0) {
                 printk(error, 3, status);
                 return status;
         }
-        gpio_direction_input(irq);
         tusb_resources[2].start = irq + IH_GPIO_BASE;
 
         /* set up memory timings ... can speed them up later */
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 0c1552d9d995..9ef3789ded4b 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -148,7 +148,6 @@ static int vp_volt_debug_get(void *data, u64 *val)
         }
 
         vsel = vdd->read_reg(prm_mod_offs, vdd->vp_data->voltage);
-        pr_notice("curr_vsel = %x\n", vsel);
 
         if (!vdd->pmic_info->vsel_to_uv) {
                 pr_warning("PMIC function to convert vsel to voltage"
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 2fc9f94cdd29..cd19309fd3b8 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -153,7 +153,6 @@ config MACH_XCEP
         bool "Iskratel Electronics XCEP"
         select PXA25x
         select MTD
-        select MTD_PARTITIONS
         select MTD_PHYSMAP
         select MTD_CFI_INTELEXT
         select MTD_CFI
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 44440cbd7620..dabc141243f3 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -58,8 +58,6 @@
 #include <plat/cpu.h>
 #include <plat/gpio-cfg.h>
 
-#ifdef CONFIG_MTD_PARTITIONS
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
@@ -113,7 +111,6 @@ static struct platform_device amlm5900_device_nor = {
         .num_resources  = 1,
         .resource       = &amlm5900_nor_resource,
 };
-#endif
 
 static struct map_desc amlm5900_iodesc[] __initdata = {
 };
@@ -158,9 +155,7 @@ static struct platform_device *amlm5900_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_usbgadget,
         &s3c_device_sdi,
-#ifdef CONFIG_MTD_PARTITIONS
         &amlm5900_device_nor,
-#endif
 };
 
 static void __init amlm5900_map_io(void)
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index a15d0621c22f..43c2b831b9e8 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -49,8 +49,6 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
-#ifdef CONFIG_MTD_PARTITIONS
-
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/map.h>
@@ -91,8 +89,6 @@ static struct platform_device tct_hammer_device_nor = {
         .resource       = &tct_hammer_nor_resource,
 };
 
-#endif
-
 static struct map_desc tct_hammer_iodesc[] __initdata = {
 };
 
@@ -133,9 +129,7 @@ static struct platform_device *tct_hammer_devices[] __initdata = {
         &s3c_device_rtc,
         &s3c_device_usbgadget,
         &s3c_device_sdi,
-#ifdef CONFIG_MTD_PARTITIONS
         &tct_hammer_device_nor,
-#endif
 };
 
 static void __init tct_hammer_map_io(void)
diff --git a/arch/arm/mach-s3c64xx/dev-spi.c b/arch/arm/mach-s3c64xx/dev-spi.c
index 405e62128917..82db072cb836 100644
--- a/arch/arm/mach-s3c64xx/dev-spi.c
+++ b/arch/arm/mach-s3c64xx/dev-spi.c
@@ -16,7 +16,6 @@
 
 #include <mach/dma.h>
 #include <mach/map.h>
-#include <mach/gpio-bank-c.h>
 #include <mach/spi-clocks.h>
 #include <mach/irqs.h>
 
@@ -40,23 +39,15 @@ static char *spi_src_clks[] = {
  */
 static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
 {
+        unsigned int base;
+
         switch (pdev->id) {
         case 0:
-                s3c_gpio_cfgpin(S3C64XX_GPC(0), S3C64XX_GPC0_SPI_MISO0);
-                s3c_gpio_cfgpin(S3C64XX_GPC(1), S3C64XX_GPC1_SPI_CLKO);
-                s3c_gpio_cfgpin(S3C64XX_GPC(2), S3C64XX_GPC2_SPI_MOSIO);
-                s3c_gpio_setpull(S3C64XX_GPC(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S3C64XX_GPC(1), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S3C64XX_GPC(2), S3C_GPIO_PULL_UP);
+                base = S3C64XX_GPC(0);
                 break;
 
         case 1:
-                s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C64XX_GPC4_SPI_MISO1);
-                s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C64XX_GPC5_SPI_CLK1);
-                s3c_gpio_cfgpin(S3C64XX_GPC(6), S3C64XX_GPC6_SPI_MOSI1);
-                s3c_gpio_setpull(S3C64XX_GPC(4), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S3C64XX_GPC(5), S3C_GPIO_PULL_UP);
-                s3c_gpio_setpull(S3C64XX_GPC(6), S3C_GPIO_PULL_UP);
+                base = S3C64XX_GPC(4);
                 break;
 
         default:
@@ -64,6 +55,9 @@ static int s3c64xx_spi_cfg_gpio(struct platform_device *pdev)
                 return -EINVAL;
         }
 
+        s3c_gpio_cfgall_range(base, 3,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
+
         return 0;
 }
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
deleted file mode 100644
index 34212e1a7e81..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-a.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank A register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPACON                  (S3C64XX_GPA_BASE + 0x00)
-#define S3C64XX_GPADAT                  (S3C64XX_GPA_BASE + 0x04)
-#define S3C64XX_GPAPUD                  (S3C64XX_GPA_BASE + 0x08)
-#define S3C64XX_GPACONSLP               (S3C64XX_GPA_BASE + 0x0c)
-#define S3C64XX_GPAPUDSLP               (S3C64XX_GPA_BASE + 0x10)
-
-#define S3C64XX_GPA_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPA_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPA_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPA0_UART_RXD0          (0x02 << 0)
-#define S3C64XX_GPA0_EINT_G1_0          (0x07 << 0)
-
-#define S3C64XX_GPA1_UART_TXD0          (0x02 << 4)
-#define S3C64XX_GPA1_EINT_G1_1          (0x07 << 4)
-
-#define S3C64XX_GPA2_UART_nCTS0         (0x02 << 8)
-#define S3C64XX_GPA2_EINT_G1_2          (0x07 << 8)
-
-#define S3C64XX_GPA3_UART_nRTS0         (0x02 << 12)
-#define S3C64XX_GPA3_EINT_G1_3          (0x07 << 12)
-
-#define S3C64XX_GPA4_UART_RXD1          (0x02 << 16)
-#define S3C64XX_GPA4_EINT_G1_4          (0x07 << 16)
-
-#define S3C64XX_GPA5_UART_TXD1          (0x02 << 20)
-#define S3C64XX_GPA5_EINT_G1_5          (0x07 << 20)
-
-#define S3C64XX_GPA6_UART_nCTS1         (0x02 << 24)
-#define S3C64XX_GPA6_EINT_G1_6          (0x07 << 24)
-
-#define S3C64XX_GPA7_UART_nRTS1         (0x02 << 28)
-#define S3C64XX_GPA7_EINT_G1_7          (0x07 << 28)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
deleted file mode 100644
index 7232c037e642..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-b.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank B register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPBCON                  (S3C64XX_GPB_BASE + 0x00)
-#define S3C64XX_GPBDAT                  (S3C64XX_GPB_BASE + 0x04)
-#define S3C64XX_GPBPUD                  (S3C64XX_GPB_BASE + 0x08)
-#define S3C64XX_GPBCONSLP               (S3C64XX_GPB_BASE + 0x0c)
-#define S3C64XX_GPBPUDSLP               (S3C64XX_GPB_BASE + 0x10)
-
-#define S3C64XX_GPB_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPB_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPB_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPB0_UART_RXD2          (0x02 << 0)
-#define S3C64XX_GPB0_EXTDMA_REQ         (0x03 << 0)
-#define S3C64XX_GPB0_IrDA_RXD           (0x04 << 0)
-#define S3C64XX_GPB0_ADDR_CF0           (0x05 << 0)
-#define S3C64XX_GPB0_EINT_G1_8          (0x07 << 0)
-
-#define S3C64XX_GPB1_UART_TXD2          (0x02 << 4)
-#define S3C64XX_GPB1_EXTDMA_ACK         (0x03 << 4)
-#define S3C64XX_GPB1_IrDA_TXD           (0x04 << 4)
-#define S3C64XX_GPB1_ADDR_CF1           (0x05 << 4)
-#define S3C64XX_GPB1_EINT_G1_9          (0x07 << 4)
-
-#define S3C64XX_GPB2_UART_RXD3          (0x02 << 8)
-#define S3C64XX_GPB2_IrDA_RXD           (0x03 << 8)
-#define S3C64XX_GPB2_EXTDMA_REQ         (0x04 << 8)
-#define S3C64XX_GPB2_ADDR_CF2           (0x05 << 8)
-#define S3C64XX_GPB2_I2C_SCL1           (0x06 << 8)
-#define S3C64XX_GPB2_EINT_G1_10         (0x07 << 8)
-
-#define S3C64XX_GPB3_UART_TXD3          (0x02 << 12)
-#define S3C64XX_GPB3_IrDA_TXD           (0x03 << 12)
-#define S3C64XX_GPB3_EXTDMA_ACK         (0x04 << 12)
-#define S3C64XX_GPB3_I2C_SDA1           (0x06 << 12)
-#define S3C64XX_GPB3_EINT_G1_11         (0x07 << 12)
-
-#define S3C64XX_GPB4_IrDA_SDBW          (0x02 << 16)
-#define S3C64XX_GPB4_CAM_FIELD          (0x03 << 16)
-#define S3C64XX_GPB4_CF_DATA_DIR        (0x04 << 16)
-#define S3C64XX_GPB4_EINT_G1_12         (0x07 << 16)
-
-#define S3C64XX_GPB5_I2C_SCL0           (0x02 << 20)
-#define S3C64XX_GPB5_EINT_G1_13         (0x07 << 20)
-
-#define S3C64XX_GPB6_I2C_SDA0           (0x02 << 24)
-#define S3C64XX_GPB6_EINT_G1_14         (0x07 << 24)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
deleted file mode 100644
index db189ab1639a..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-c.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank C register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPCCON                  (S3C64XX_GPC_BASE + 0x00)
-#define S3C64XX_GPCDAT                  (S3C64XX_GPC_BASE + 0x04)
-#define S3C64XX_GPCPUD                  (S3C64XX_GPC_BASE + 0x08)
-#define S3C64XX_GPCCONSLP               (S3C64XX_GPC_BASE + 0x0c)
-#define S3C64XX_GPCPUDSLP               (S3C64XX_GPC_BASE + 0x10)
-
-#define S3C64XX_GPC_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPC_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPC_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPC0_SPI_MISO0          (0x02 << 0)
-#define S3C64XX_GPC0_EINT_G2_0          (0x07 << 0)
-
-#define S3C64XX_GPC1_SPI_CLKO           (0x02 << 4)
-#define S3C64XX_GPC1_EINT_G2_1          (0x07 << 4)
-
-#define S3C64XX_GPC2_SPI_MOSIO          (0x02 << 8)
-#define S3C64XX_GPC2_EINT_G2_2          (0x07 << 8)
-
-#define S3C64XX_GPC3_SPI_nCSO           (0x02 << 12)
-#define S3C64XX_GPC3_EINT_G2_3          (0x07 << 12)
-
-#define S3C64XX_GPC4_SPI_MISO1          (0x02 << 16)
-#define S3C64XX_GPC4_MMC2_CMD           (0x03 << 16)
-#define S3C64XX_GPC4_I2S_V40_DO0        (0x05 << 16)
-#define S3C64XX_GPC4_EINT_G2_4          (0x07 << 16)
-
-#define S3C64XX_GPC5_SPI_CLK1           (0x02 << 20)
-#define S3C64XX_GPC5_MMC2_CLK           (0x03 << 20)
-#define S3C64XX_GPC5_I2S_V40_DO1        (0x05 << 20)
-#define S3C64XX_GPC5_EINT_G2_5          (0x07 << 20)
-
-#define S3C64XX_GPC6_SPI_MOSI1          (0x02 << 24)
-#define S3C64XX_GPC6_EINT_G2_6          (0x07 << 24)
-
-#define S3C64XX_GPC7_SPI_nCS1           (0x02 << 28)
-#define S3C64XX_GPC7_I2S_V40_DO2        (0x05 << 28)
-#define S3C64XX_GPC7_EINT_G2_7          (0x07 << 28)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
deleted file mode 100644
index 1a01cee7aca3..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-d.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank D register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPDCON                  (S3C64XX_GPD_BASE + 0x00)
-#define S3C64XX_GPDDAT                  (S3C64XX_GPD_BASE + 0x04)
-#define S3C64XX_GPDPUD                  (S3C64XX_GPD_BASE + 0x08)
-#define S3C64XX_GPDCONSLP               (S3C64XX_GPD_BASE + 0x0c)
-#define S3C64XX_GPDPUDSLP               (S3C64XX_GPD_BASE + 0x10)
-
-#define S3C64XX_GPD_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPD_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPD_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPD0_PCM0_SCLK          (0x02 << 0)
-#define S3C64XX_GPD0_I2S0_CLK           (0x03 << 0)
-#define S3C64XX_GPD0_AC97_BITCLK        (0x04 << 0)
-#define S3C64XX_GPD0_EINT_G3_0          (0x07 << 0)
-
-#define S3C64XX_GPD1_PCM0_EXTCLK        (0x02 << 4)
-#define S3C64XX_GPD1_I2S0_CDCLK         (0x03 << 4)
-#define S3C64XX_GPD1_AC97_nRESET        (0x04 << 4)
-#define S3C64XX_GPD1_EINT_G3_1          (0x07 << 4)
-
-#define S3C64XX_GPD2_PCM0_FSYNC         (0x02 << 8)
-#define S3C64XX_GPD2_I2S0_LRCLK         (0x03 << 8)
-#define S3C64XX_GPD2_AC97_SYNC          (0x04 << 8)
-#define S3C64XX_GPD2_EINT_G3_2          (0x07 << 8)
-
-#define S3C64XX_GPD3_PCM0_SIN           (0x02 << 12)
-#define S3C64XX_GPD3_I2S0_DI            (0x03 << 12)
-#define S3C64XX_GPD3_AC97_SDI           (0x04 << 12)
-#define S3C64XX_GPD3_EINT_G3_3          (0x07 << 12)
-
-#define S3C64XX_GPD4_PCM0_SOUT          (0x02 << 16)
-#define S3C64XX_GPD4_I2S0_D0            (0x03 << 16)
-#define S3C64XX_GPD4_AC97_SDO           (0x04 << 16)
-#define S3C64XX_GPD4_EINT_G3_4          (0x07 << 16)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
deleted file mode 100644
index f057adb627dd..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank E register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPECON                  (S3C64XX_GPE_BASE + 0x00)
-#define S3C64XX_GPEDAT                  (S3C64XX_GPE_BASE + 0x04)
-#define S3C64XX_GPEPUD                  (S3C64XX_GPE_BASE + 0x08)
-#define S3C64XX_GPECONSLP               (S3C64XX_GPE_BASE + 0x0c)
-#define S3C64XX_GPEPUDSLP               (S3C64XX_GPE_BASE + 0x10)
-
-#define S3C64XX_GPE_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPE_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPE_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPE0_PCM1_SCLK          (0x02 << 0)
-#define S3C64XX_GPE0_I2S1_CLK           (0x03 << 0)
-#define S3C64XX_GPE0_AC97_BITCLK        (0x04 << 0)
-
-#define S3C64XX_GPE1_PCM1_EXTCLK        (0x02 << 4)
-#define S3C64XX_GPE1_I2S1_CDCLK         (0x03 << 4)
-#define S3C64XX_GPE1_AC97_nRESET        (0x04 << 4)
-
-#define S3C64XX_GPE2_PCM1_FSYNC         (0x02 << 8)
-#define S3C64XX_GPE2_I2S1_LRCLK         (0x03 << 8)
-#define S3C64XX_GPE2_AC97_SYNC          (0x04 << 8)
-
-#define S3C64XX_GPE3_PCM1_SIN           (0x02 << 12)
-#define S3C64XX_GPE3_I2S1_DI            (0x03 << 12)
-#define S3C64XX_GPE3_AC97_SDI           (0x04 << 12)
-
-#define S3C64XX_GPE4_PCM1_SOUT          (0x02 << 16)
-#define S3C64XX_GPE4_I2S1_D0            (0x03 << 16)
-#define S3C64XX_GPE4_AC97_SDO           (0x04 << 16)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
deleted file mode 100644
index 62ab8f5e7835..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-f.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank F register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPFCON                  (S3C64XX_GPF_BASE + 0x00)
-#define S3C64XX_GPFDAT                  (S3C64XX_GPF_BASE + 0x04)
-#define S3C64XX_GPFPUD                  (S3C64XX_GPF_BASE + 0x08)
-#define S3C64XX_GPFCONSLP               (S3C64XX_GPF_BASE + 0x0c)
-#define S3C64XX_GPFPUDSLP               (S3C64XX_GPF_BASE + 0x10)
-
-#define S3C64XX_GPF_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPF_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPF_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPF0_CAMIF_CLK          (0x02 << 0)
-#define S3C64XX_GPF0_EINT_G4_0          (0x03 << 0)
-
-#define S3C64XX_GPF1_CAMIF_HREF         (0x02 << 2)
-#define S3C64XX_GPF1_EINT_G4_1          (0x03 << 2)
-
-#define S3C64XX_GPF2_CAMIF_PCLK         (0x02 << 4)
-#define S3C64XX_GPF2_EINT_G4_2          (0x03 << 4)
-
-#define S3C64XX_GPF3_CAMIF_nRST         (0x02 << 6)
-#define S3C64XX_GPF3_EINT_G4_3          (0x03 << 6)
-
-#define S3C64XX_GPF4_CAMIF_VSYNC        (0x02 << 8)
-#define S3C64XX_GPF4_EINT_G4_4          (0x03 << 8)
-
-#define S3C64XX_GPF5_CAMIF_YDATA0       (0x02 << 10)
-#define S3C64XX_GPF5_EINT_G4_5          (0x03 << 10)
-
-#define S3C64XX_GPF6_CAMIF_YDATA1       (0x02 << 12)
-#define S3C64XX_GPF6_EINT_G4_6          (0x03 << 12)
-
-#define S3C64XX_GPF7_CAMIF_YDATA2       (0x02 << 14)
-#define S3C64XX_GPF7_EINT_G4_7          (0x03 << 14)
-
-#define S3C64XX_GPF8_CAMIF_YDATA3       (0x02 << 16)
-#define S3C64XX_GPF8_EINT_G4_8          (0x03 << 16)
-
-#define S3C64XX_GPF9_CAMIF_YDATA4       (0x02 << 18)
-#define S3C64XX_GPF9_EINT_G4_9          (0x03 << 18)
-
-#define S3C64XX_GPF10_CAMIF_YDATA5      (0x02 << 20)
-#define S3C64XX_GPF10_EINT_G4_10        (0x03 << 20)
-
-#define S3C64XX_GPF11_CAMIF_YDATA6      (0x02 << 22)
-#define S3C64XX_GPF11_EINT_G4_11        (0x03 << 22)
-
-#define S3C64XX_GPF12_CAMIF_YDATA7      (0x02 << 24)
-#define S3C64XX_GPF12_EINT_G4_12        (0x03 << 24)
-
-#define S3C64XX_GPF13_PWM_ECLK          (0x02 << 26)
-#define S3C64XX_GPF13_EINT_G4_13        (0x03 << 26)
-
-#define S3C64XX_GPF14_PWM_TOUT0         (0x02 << 28)
-#define S3C64XX_GPF14_CLKOUT0           (0x03 << 28)
-
-#define S3C64XX_GPF15_PWM_TOUT1         (0x02 << 30)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
deleted file mode 100644
index b94954af1598..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-g.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank G register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPGCON                  (S3C64XX_GPG_BASE + 0x00)
-#define S3C64XX_GPGDAT                  (S3C64XX_GPG_BASE + 0x04)
-#define S3C64XX_GPGPUD                  (S3C64XX_GPG_BASE + 0x08)
-#define S3C64XX_GPGCONSLP               (S3C64XX_GPG_BASE + 0x0c)
-#define S3C64XX_GPGPUDSLP               (S3C64XX_GPG_BASE + 0x10)
-
-#define S3C64XX_GPG_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPG_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPG_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPG0_MMC0_CLK           (0x02 << 0)
-#define S3C64XX_GPG0_EINT_G5_0          (0x07 << 0)
-
-#define S3C64XX_GPG1_MMC0_CMD           (0x02 << 4)
-#define S3C64XX_GPG1_EINT_G5_1          (0x07 << 4)
-
-#define S3C64XX_GPG2_MMC0_DATA0         (0x02 << 8)
-#define S3C64XX_GPG2_EINT_G5_2          (0x07 << 8)
-
-#define S3C64XX_GPG3_MMC0_DATA1         (0x02 << 12)
-#define S3C64XX_GPG3_EINT_G5_3          (0x07 << 12)
-
-#define S3C64XX_GPG4_MMC0_DATA2         (0x02 << 16)
-#define S3C64XX_GPG4_EINT_G5_4          (0x07 << 16)
-
-#define S3C64XX_GPG5_MMC0_DATA3         (0x02 << 20)
-#define S3C64XX_GPG5_EINT_G5_5          (0x07 << 20)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
deleted file mode 100644
index 5d75aaad865e..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-h.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank H register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPHCON0                 (S3C64XX_GPH_BASE + 0x00)
-#define S3C64XX_GPHCON1                 (S3C64XX_GPH_BASE + 0x04)
-#define S3C64XX_GPHDAT                  (S3C64XX_GPH_BASE + 0x08)
-#define S3C64XX_GPHPUD                  (S3C64XX_GPH_BASE + 0x0c)
-#define S3C64XX_GPHCONSLP               (S3C64XX_GPH_BASE + 0x10)
-#define S3C64XX_GPHPUDSLP               (S3C64XX_GPH_BASE + 0x14)
-
-#define S3C64XX_GPH_CONMASK(__gpio)     (0xf << ((__gpio) * 4))
-#define S3C64XX_GPH_INPUT(__gpio)       (0x0 << ((__gpio) * 4))
-#define S3C64XX_GPH_OUTPUT(__gpio)      (0x1 << ((__gpio) * 4))
-
-#define S3C64XX_GPH0_MMC1_CLK           (0x02 << 0)
-#define S3C64XX_GPH0_KP_COL0            (0x04 << 0)
-#define S3C64XX_GPH0_EINT_G6_0          (0x07 << 0)
-
-#define S3C64XX_GPH1_MMC1_CMD           (0x02 << 4)
-#define S3C64XX_GPH1_KP_COL1            (0x04 << 4)
-#define S3C64XX_GPH1_EINT_G6_1          (0x07 << 4)
-
-#define S3C64XX_GPH2_MMC1_DATA0         (0x02 << 8)
-#define S3C64XX_GPH2_KP_COL2            (0x04 << 8)
-#define S3C64XX_GPH2_EINT_G6_2          (0x07 << 8)
-
-#define S3C64XX_GPH3_MMC1_DATA1         (0x02 << 12)
-#define S3C64XX_GPH3_KP_COL3            (0x04 << 12)
-#define S3C64XX_GPH3_EINT_G6_3          (0x07 << 12)
-
-#define S3C64XX_GPH4_MMC1_DATA2         (0x02 << 16)
-#define S3C64XX_GPH4_KP_COL4            (0x04 << 16)
-#define S3C64XX_GPH4_EINT_G6_4          (0x07 << 16)
-
-#define S3C64XX_GPH5_MMC1_DATA3         (0x02 << 20)
-#define S3C64XX_GPH5_KP_COL5            (0x04 << 20)
-#define S3C64XX_GPH5_EINT_G6_5          (0x07 << 20)
-
-#define S3C64XX_GPH6_MMC1_DATA4         (0x02 << 24)
-#define S3C64XX_GPH6_MMC2_DATA0         (0x03 << 24)
-#define S3C64XX_GPH6_KP_COL6            (0x04 << 24)
-#define S3C64XX_GPH6_I2S_V40_BCLK       (0x05 << 24)
-#define S3C64XX_GPH6_ADDR_CF0           (0x06 << 24)
-#define S3C64XX_GPH6_EINT_G6_6          (0x07 << 24)
-
-#define S3C64XX_GPH7_MMC1_DATA5         (0x02 << 28)
-#define S3C64XX_GPH7_MMC2_DATA1         (0x03 << 28)
-#define S3C64XX_GPH7_KP_COL7            (0x04 << 28)
-#define S3C64XX_GPH7_I2S_V40_CDCLK      (0x05 << 28)
-#define S3C64XX_GPH7_ADDR_CF1           (0x06 << 28)
-#define S3C64XX_GPH7_EINT_G6_7          (0x07 << 28)
-
-#define S3C64XX_GPH8_MMC1_DATA6         (0x02 <<  0)
-#define S3C64XX_GPH8_MMC2_DATA2         (0x03 <<  0)
-#define S3C64XX_GPH8_I2S_V40_LRCLK      (0x05 <<  0)
-#define S3C64XX_GPH8_ADDR_CF2           (0x06 <<  0)
-#define S3C64XX_GPH8_EINT_G6_8          (0x07 <<  0)
-
-#define S3C64XX_GPH9_OUTPUT             (0x01 <<  4)
-#define S3C64XX_GPH9_MMC1_DATA7         (0x02 <<  4)
-#define S3C64XX_GPH9_MMC2_DATA3         (0x03 <<  4)
-#define S3C64XX_GPH9_I2S_V40_DI         (0x05 <<  4)
-#define S3C64XX_GPH9_EINT_G6_9          (0x07 <<  4)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
deleted file mode 100644
index 4ceaa6098bc7..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-i.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank I register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPICON                  (S3C64XX_GPI_BASE + 0x00)
-#define S3C64XX_GPIDAT                  (S3C64XX_GPI_BASE + 0x04)
-#define S3C64XX_GPIPUD                  (S3C64XX_GPI_BASE + 0x08)
-#define S3C64XX_GPICONSLP               (S3C64XX_GPI_BASE + 0x0c)
-#define S3C64XX_GPIPUDSLP               (S3C64XX_GPI_BASE + 0x10)
-
-#define S3C64XX_GPI_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPI_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPI_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPI0_VD0                (0x02 << 0)
-#define S3C64XX_GPI1_VD1                (0x02 << 2)
-#define S3C64XX_GPI2_VD2                (0x02 << 4)
-#define S3C64XX_GPI3_VD3                (0x02 << 6)
-#define S3C64XX_GPI4_VD4                (0x02 << 8)
-#define S3C64XX_GPI5_VD5                (0x02 << 10)
-#define S3C64XX_GPI6_VD6                (0x02 << 12)
-#define S3C64XX_GPI7_VD7                (0x02 << 14)
-#define S3C64XX_GPI8_VD8                (0x02 << 16)
-#define S3C64XX_GPI9_VD9                (0x02 << 18)
-#define S3C64XX_GPI10_VD10              (0x02 << 20)
-#define S3C64XX_GPI11_VD11              (0x02 << 22)
-#define S3C64XX_GPI12_VD12              (0x02 << 24)
-#define S3C64XX_GPI13_VD13              (0x02 << 26)
-#define S3C64XX_GPI14_VD14              (0x02 << 28)
-#define S3C64XX_GPI15_VD15              (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
deleted file mode 100644
index 6f25cd079a40..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-j.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank J register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPJCON                  (S3C64XX_GPJ_BASE + 0x00)
-#define S3C64XX_GPJDAT                  (S3C64XX_GPJ_BASE + 0x04)
-#define S3C64XX_GPJPUD                  (S3C64XX_GPJ_BASE + 0x08)
-#define S3C64XX_GPJCONSLP               (S3C64XX_GPJ_BASE + 0x0c)
-#define S3C64XX_GPJPUDSLP               (S3C64XX_GPJ_BASE + 0x10)
-
-#define S3C64XX_GPJ_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPJ_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPJ_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPJ0_VD16               (0x02 << 0)
-#define S3C64XX_GPJ1_VD17               (0x02 << 2)
-#define S3C64XX_GPJ2_VD18               (0x02 << 4)
-#define S3C64XX_GPJ3_VD19               (0x02 << 6)
-#define S3C64XX_GPJ4_VD20               (0x02 << 8)
-#define S3C64XX_GPJ5_VD21               (0x02 << 10)
-#define S3C64XX_GPJ6_VD22               (0x02 << 12)
-#define S3C64XX_GPJ7_VD23               (0x02 << 14)
-#define S3C64XX_GPJ8_LCD_HSYNC          (0x02 << 16)
-#define S3C64XX_GPJ9_LCD_VSYNC          (0x02 << 18)
-#define S3C64XX_GPJ10_LCD_VDEN          (0x02 << 20)
-#define S3C64XX_GPJ11_LCD_VCLK          (0x02 << 22)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
deleted file mode 100644
index d0aeda1cd9de..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-n.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank N register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPNCON                  (S3C64XX_GPN_BASE + 0x00)
-#define S3C64XX_GPNDAT                  (S3C64XX_GPN_BASE + 0x04)
-#define S3C64XX_GPNPUD                  (S3C64XX_GPN_BASE + 0x08)
-
-#define S3C64XX_GPN_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPN_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPN_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPN0_EINT0              (0x02 << 0)
-#define S3C64XX_GPN0_KP_ROW0            (0x03 << 0)
-
-#define S3C64XX_GPN1_EINT1              (0x02 << 2)
-#define S3C64XX_GPN1_KP_ROW1            (0x03 << 2)
-
-#define S3C64XX_GPN2_EINT2              (0x02 << 4)
-#define S3C64XX_GPN2_KP_ROW2            (0x03 << 4)
-
-#define S3C64XX_GPN3_EINT3              (0x02 << 6)
-#define S3C64XX_GPN3_KP_ROW3            (0x03 << 6)
-
-#define S3C64XX_GPN4_EINT4              (0x02 << 8)
-#define S3C64XX_GPN4_KP_ROW4            (0x03 << 8)
-
-#define S3C64XX_GPN5_EINT5              (0x02 << 10)
-#define S3C64XX_GPN5_KP_ROW5            (0x03 << 10)
-
-#define S3C64XX_GPN6_EINT6              (0x02 << 12)
-#define S3C64XX_GPN6_KP_ROW6            (0x03 << 12)
-
-#define S3C64XX_GPN7_EINT7              (0x02 << 14)
-#define S3C64XX_GPN7_KP_ROW7            (0x03 << 14)
-
-#define S3C64XX_GPN8_EINT8              (0x02 << 16)
-#define S3C64XX_GPN9_EINT9              (0x02 << 18)
-#define S3C64XX_GPN10_EINT10            (0x02 << 20)
-#define S3C64XX_GPN11_EINT11            (0x02 << 22)
-#define S3C64XX_GPN12_EINT12            (0x02 << 24)
-#define S3C64XX_GPN13_EINT13            (0x02 << 26)
-#define S3C64XX_GPN14_EINT14            (0x02 << 28)
-#define S3C64XX_GPN15_EINT15            (0x02 << 30)
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
deleted file mode 100644
index 21868fa102d0..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-o.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank O register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPOCON                  (S3C64XX_GPO_BASE + 0x00)
-#define S3C64XX_GPODAT                  (S3C64XX_GPO_BASE + 0x04)
-#define S3C64XX_GPOPUD                  (S3C64XX_GPO_BASE + 0x08)
-#define S3C64XX_GPOCONSLP               (S3C64XX_GPO_BASE + 0x0c)
-#define S3C64XX_GPOPUDSLP               (S3C64XX_GPO_BASE + 0x10)
-
-#define S3C64XX_GPO_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPO_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPO_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPO0_MEM0_nCS2          (0x02 << 0)
-#define S3C64XX_GPO0_EINT_G7_0          (0x03 << 0)
-
-#define S3C64XX_GPO1_MEM0_nCS3          (0x02 << 2)
-#define S3C64XX_GPO1_EINT_G7_1          (0x03 << 2)
-
-#define S3C64XX_GPO2_MEM0_nCS4          (0x02 << 4)
-#define S3C64XX_GPO2_EINT_G7_2          (0x03 << 4)
-
-#define S3C64XX_GPO3_MEM0_nCS5          (0x02 << 6)
-#define S3C64XX_GPO3_EINT_G7_3          (0x03 << 6)
-
-#define S3C64XX_GPO4_EINT_G7_4          (0x03 << 8)
-
-#define S3C64XX_GPO5_EINT_G7_5          (0x03 << 10)
-
-#define S3C64XX_GPO6_MEM0_ADDR6         (0x02 << 12)
-#define S3C64XX_GPO6_EINT_G7_6          (0x03 << 12)
-
-#define S3C64XX_GPO7_MEM0_ADDR7         (0x02 << 14)
-#define S3C64XX_GPO7_EINT_G7_7          (0x03 << 14)
-
-#define S3C64XX_GPO8_MEM0_ADDR8         (0x02 << 16)
-#define S3C64XX_GPO8_EINT_G7_8          (0x03 << 16)
-
-#define S3C64XX_GPO9_MEM0_ADDR9         (0x02 << 18)
-#define S3C64XX_GPO9_EINT_G7_9          (0x03 << 18)
-
-#define S3C64XX_GPO10_MEM0_ADDR10       (0x02 << 20)
-#define S3C64XX_GPO10_EINT_G7_10        (0x03 << 20)
-
-#define S3C64XX_GPO11_MEM0_ADDR11       (0x02 << 22)
-#define S3C64XX_GPO11_EINT_G7_11        (0x03 << 22)
-
-#define S3C64XX_GPO12_MEM0_ADDR12       (0x02 << 24)
-#define S3C64XX_GPO12_EINT_G7_12        (0x03 << 24)
-
-#define S3C64XX_GPO13_MEM0_ADDR13       (0x02 << 26)
-#define S3C64XX_GPO13_EINT_G7_13        (0x03 << 26)
-
-#define S3C64XX_GPO14_MEM0_ADDR14       (0x02 << 28)
-#define S3C64XX_GPO14_EINT_G7_14        (0x03 << 28)
-
-#define S3C64XX_GPO15_MEM0_ADDR15       (0x02 << 30)
-#define S3C64XX_GPO15_EINT_G7_15        (0x03 << 30)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
deleted file mode 100644
index 46bcfb63b8de..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-p.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank P register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPPCON                  (S3C64XX_GPP_BASE + 0x00)
-#define S3C64XX_GPPDAT                  (S3C64XX_GPP_BASE + 0x04)
-#define S3C64XX_GPPPUD                  (S3C64XX_GPP_BASE + 0x08)
-#define S3C64XX_GPPCONSLP               (S3C64XX_GPP_BASE + 0x0c)
-#define S3C64XX_GPPPUDSLP               (S3C64XX_GPP_BASE + 0x10)
-
-#define S3C64XX_GPP_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPP_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPP_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPP0_MEM0_ADDRV         (0x02 << 0)
-#define S3C64XX_GPP0_EINT_G8_0          (0x03 << 0)
-
-#define S3C64XX_GPP1_MEM0_SMCLK         (0x02 << 2)
-#define S3C64XX_GPP1_EINT_G8_1          (0x03 << 2)
-
-#define S3C64XX_GPP2_MEM0_nWAIT         (0x02 << 4)
-#define S3C64XX_GPP2_EINT_G8_2          (0x03 << 4)
-
-#define S3C64XX_GPP3_MEM0_RDY0_ALE      (0x02 << 6)
-#define S3C64XX_GPP3_EINT_G8_3          (0x03 << 6)
-
-#define S3C64XX_GPP4_MEM0_RDY1_CLE      (0x02 << 8)
-#define S3C64XX_GPP4_EINT_G8_4          (0x03 << 8)
-
-#define S3C64XX_GPP5_MEM0_INTsm0_FWE    (0x02 << 10)
-#define S3C64XX_GPP5_EINT_G8_5          (0x03 << 10)
-
-#define S3C64XX_GPP6_MEM0_(null)        (0x02 << 12)
-#define S3C64XX_GPP6_EINT_G8_6          (0x03 << 12)
-
-#define S3C64XX_GPP7_MEM0_INTsm1_FRE    (0x02 << 14)
-#define S3C64XX_GPP7_EINT_G8_7          (0x03 << 14)
-
-#define S3C64XX_GPP8_MEM0_RPn_RnB       (0x02 << 16)
-#define S3C64XX_GPP8_EINT_G8_8          (0x03 << 16)
-
-#define S3C64XX_GPP9_MEM0_ATA_RESET     (0x02 << 18)
-#define S3C64XX_GPP9_EINT_G8_9          (0x03 << 18)
-
-#define S3C64XX_GPP10_MEM0_ATA_INPACK   (0x02 << 20)
-#define S3C64XX_GPP10_EINT_G8_10        (0x03 << 20)
-
-#define S3C64XX_GPP11_MEM0_ATA_REG      (0x02 << 22)
-#define S3C64XX_GPP11_EINT_G8_11        (0x03 << 22)
-
-#define S3C64XX_GPP12_MEM0_ATA_WE       (0x02 << 24)
-#define S3C64XX_GPP12_EINT_G8_12        (0x03 << 24)
-
-#define S3C64XX_GPP13_MEM0_ATA_OE       (0x02 << 26)
-#define S3C64XX_GPP13_EINT_G8_13        (0x03 << 26)
-
-#define S3C64XX_GPP14_MEM0_ATA_CD       (0x02 << 28)
-#define S3C64XX_GPP14_EINT_G8_14        (0x03 << 28)
-
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
deleted file mode 100644
index 1712223487b0..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-q.h
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * GPIO Bank Q register and configuration definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C64XX_GPQCON                  (S3C64XX_GPQ_BASE + 0x00)
-#define S3C64XX_GPQDAT                  (S3C64XX_GPQ_BASE + 0x04)
-#define S3C64XX_GPQPUD                  (S3C64XX_GPQ_BASE + 0x08)
-#define S3C64XX_GPQCONSLP               (S3C64XX_GPQ_BASE + 0x0c)
-#define S3C64XX_GPQPUDSLP               (S3C64XX_GPQ_BASE + 0x10)
-
-#define S3C64XX_GPQ_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
-#define S3C64XX_GPQ_INPUT(__gpio)       (0x0 << ((__gpio) * 2))
-#define S3C64XX_GPQ_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
-
-#define S3C64XX_GPQ0_MEM0_ADDR18_RAS    (0x02 << 0)
-#define S3C64XX_GPQ0_EINT_G9_0          (0x03 << 0)
-
-#define S3C64XX_GPQ1_MEM0_ADDR19_CAS    (0x02 << 2)
-#define S3C64XX_GPQ1_EINT_G9_1          (0x03 << 2)
-
-#define S3C64XX_GPQ2_EINT_G9_2          (0x03 << 4)
-
-#define S3C64XX_GPQ3_EINT_G9_3          (0x03 << 6)
-
-#define S3C64XX_GPQ4_EINT_G9_4          (0x03 << 8)
-
-#define S3C64XX_GPQ5_EINT_G9_5          (0x03 << 10)
-
-#define S3C64XX_GPQ6_EINT_G9_6          (0x03 << 12)
-
-#define S3C64XX_GPQ7_MEM0_ADDR17_WENDMC (0x02 << 14)
-#define S3C64XX_GPQ7_EINT_G9_7          (0x03 << 14)
-
-#define S3C64XX_GPQ8_MEM0_ADDR16_APDMC  (0x02 << 16)
-#define S3C64XX_GPQ8_EINT_G9_8          (0x03 << 16)
-
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 686a4f270b12..2c0353a80906 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -50,7 +50,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-fb.h>
 #include <mach/map.h>
-#include <mach/gpio-bank-f.h>
 
 #include <asm/irq.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 79412f735a8d..bc1c470b7de6 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -30,26 +30,18 @@
 #include <mach/regs-gpio-memport.h>
 
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
-#include <mach/gpio-bank-n.h>
-
 void s3c_pm_debug_smdkled(u32 set, u32 clear)
 {
         unsigned long flags;
-        u32 reg;
+        int i;
 
         local_irq_save(flags);
-        reg = __raw_readl(S3C64XX_GPNCON);
-        reg &= ~(S3C64XX_GPN_CONMASK(12) | S3C64XX_GPN_CONMASK(13) |
-                 S3C64XX_GPN_CONMASK(14) | S3C64XX_GPN_CONMASK(15));
-        reg |= S3C64XX_GPN_OUTPUT(12) | S3C64XX_GPN_OUTPUT(13) |
-               S3C64XX_GPN_OUTPUT(14) | S3C64XX_GPN_OUTPUT(15);
-        __raw_writel(reg, S3C64XX_GPNCON);
-
-        reg = __raw_readl(S3C64XX_GPNDAT);
-        reg &= ~(clear << 12);
-        reg |= set << 12;
-        __raw_writel(reg, S3C64XX_GPNDAT);
-
+        for (i = 0; i < 4; i++) {
+                if (clear & (1 << i))
+                        gpio_set_value(S3C64XX_GPN(12 + i), 0);
+                if (set & (1 << i))
+                        gpio_set_value(S3C64XX_GPN(12 + i), 1);
+        }
         local_irq_restore(flags);
 }
 #endif
@@ -187,6 +179,18 @@ static int s3c64xx_pm_init(void)
         pm_cpu_prep = s3c64xx_pm_prepare;
         pm_cpu_sleep = s3c64xx_cpu_suspend;
         pm_uart_udivslot = 1;
+
+#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+        gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
+        gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
+        gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
+        gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
+        gpio_direction_output(S3C64XX_GPN(12), 0);
+        gpio_direction_output(S3C64XX_GPN(13), 0);
+        gpio_direction_output(S3C64XX_GPN(14), 0);
+        gpio_direction_output(S3C64XX_GPN(15), 0);
+#endif
+
         return 0;
 }
 
diff --git a/arch/arm/mach-s3c64xx/setup-i2c0.c b/arch/arm/mach-s3c64xx/setup-i2c0.c
index 406192a43c6e..241af94a9e70 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c0.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c0.c
@@ -18,14 +18,11 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <mach/gpio-bank-b.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c0_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S3C64XX_GPB(5), S3C64XX_GPB5_I2C_SCL0);
-        s3c_gpio_cfgpin(S3C64XX_GPB(6), S3C64XX_GPB6_I2C_SDA0);
-        s3c_gpio_setpull(S3C64XX_GPB(5), S3C_GPIO_PULL_UP);
-        s3c_gpio_setpull(S3C64XX_GPB(6), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S3C64XX_GPB(5), 2,
+                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s3c64xx/setup-i2c1.c b/arch/arm/mach-s3c64xx/setup-i2c1.c
index 1ee62c97cd7f..3d13a961986d 100644
--- a/arch/arm/mach-s3c64xx/setup-i2c1.c
+++ b/arch/arm/mach-s3c64xx/setup-i2c1.c
@@ -18,14 +18,11 @@
 
 struct platform_device; /* don't need the contents */
 
-#include <mach/gpio-bank-b.h>
 #include <plat/iic.h>
 #include <plat/gpio-cfg.h>
 
 void s3c_i2c1_cfg_gpio(struct platform_device *dev)
 {
-        s3c_gpio_cfgpin(S3C64XX_GPB(2), S3C64XX_GPB2_I2C_SCL1);
-        s3c_gpio_cfgpin(S3C64XX_GPB(3), S3C64XX_GPB3_I2C_SDA1);
-        s3c_gpio_setpull(S3C64XX_GPB(2), S3C_GPIO_PULL_UP);
-        s3c_gpio_setpull(S3C64XX_GPB(3), S3C_GPIO_PULL_UP);
+        s3c_gpio_cfgall_range(S3C64XX_GPB(2), 2,
+                              S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
 }
diff --git a/arch/arm/mach-s3c64xx/sleep.S b/arch/arm/mach-s3c64xx/sleep.S
index afe5a762f46e..1f87732b2320 100644
--- a/arch/arm/mach-s3c64xx/sleep.S
+++ b/arch/arm/mach-s3c64xx/sleep.S
@@ -20,7 +20,6 @@
 #define S3C64XX_VA_GPIO (0x0)
 
 #include <mach/regs-gpio.h>
-#include <mach/gpio-bank-n.h>
 
 #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT))
 
@@ -68,6 +67,13 @@ ENTRY(s3c_cpu_resume)
         ldr     r2, =LL_UART            /* for debug */
 
 #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
+
+#define S3C64XX_GPNCON                  (S3C64XX_GPN_BASE + 0x00)
+#define S3C64XX_GPNDAT                  (S3C64XX_GPN_BASE + 0x04)
+
+#define S3C64XX_GPN_CONMASK(__gpio)     (0x3 << ((__gpio) * 2))
+#define S3C64XX_GPN_OUTPUT(__gpio)      (0x1 << ((__gpio) * 2))
+
         /* Initialise the GPIO state if we are debugging via the SMDK LEDs,
          * as the uboot version supplied resets these to inputs during the
          * resume checks.
diff --git a/arch/arm/mach-s5p6442/Kconfig b/arch/arm/mach-s5p6442/Kconfig
deleted file mode 100644
index 33569e4007c4..000000000000
--- a/arch/arm/mach-s5p6442/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-# arch/arm/mach-s5p6442/Kconfig
-#
-# Copyright (c) 2010 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-# Configuration options for the S5P6442
-
-if ARCH_S5P6442
-
-config CPU_S5P6442
-        bool
-        select S3C_PL330_DMA
-        help
-          Enable S5P6442 CPU support
-
-config MACH_SMDK6442
-        bool "SMDK6442"
-        select CPU_S5P6442
-        select S3C_DEV_WDT
-        help
-          Machine support for Samsung SMDK6442
-
-endif
diff --git a/arch/arm/mach-s5p6442/Makefile b/arch/arm/mach-s5p6442/Makefile
deleted file mode 100644
index 90a3d8373416..000000000000
--- a/arch/arm/mach-s5p6442/Makefile
+++ /dev/null
@@ -1,24 +0,0 @@
-# arch/arm/mach-s5p6442/Makefile
-#
-# Copyright (c) 2010 Samsung Electronics Co., Ltd.
-#               http://www.samsung.com/
-#
-# Licensed under GPLv2
-
-obj-y                           :=
-obj-m                           :=
-obj-n                           :=
-obj-                            :=
-
-# Core support for S5P6442 system
-
-obj-$(CONFIG_CPU_S5P6442)       += cpu.o init.o clock.o dma.o
-obj-$(CONFIG_CPU_S5P6442)       += setup-i2c0.o
-
-# machine support
-
-obj-$(CONFIG_MACH_SMDK6442)     += mach-smdk6442.o
-
-# device support
-obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
diff --git a/arch/arm/mach-s5p6442/Makefile.boot b/arch/arm/mach-s5p6442/Makefile.boot
deleted file mode 100644
index ff90aa13bd67..000000000000
--- a/arch/arm/mach-s5p6442/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-y   := 0x20008000
-params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
deleted file mode 100644
index fbbc7bede685..000000000000
--- a/arch/arm/mach-s5p6442/clock.c
+++ /dev/null
@@ -1,420 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/clock.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/map.h>
-
-#include <plat/cpu-freq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-#include <plat/pll.h>
-#include <plat/s5p-clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/s5p6442.h>
-
-static struct clksrc_clk clk_mout_apll = {
-        .clk    = {
-                .name           = "mout_apll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_apll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_mpll = {
-        .clk = {
-                .name           = "mout_mpll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_mpll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
-};
-
-static struct clksrc_clk clk_mout_epll = {
-        .clk    = {
-                .name           = "mout_epll",
-                .id             = -1,
-        },
-        .sources        = &clk_src_epll,
-        .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
-};
-
-/* Possible clock sources for ARM Mux */
-static struct clk *clk_src_arm_list[] = {
-        [1] = &clk_mout_apll.clk,
-        [2] = &clk_mout_mpll.clk,
-};
-
-static struct clksrc_sources clk_src_arm = {
-        .sources        = clk_src_arm_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_arm_list),
-};
-
-static struct clksrc_clk clk_mout_arm = {
-        .clk    = {
-                .name           = "mout_arm",
-                .id             = -1,
-        },
-        .sources        = &clk_src_arm,
-        .reg_src        = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
-};
-
-static struct clk clk_dout_a2m = {
-        .name           = "dout_a2m",
-        .id             = -1,
-        .parent         = &clk_mout_apll.clk,
-};
-
-/* Possible clock sources for D0 Mux */
-static struct clk *clk_src_d0_list[] = {
-        [1] = &clk_mout_mpll.clk,
-        [2] = &clk_dout_a2m,
-};
-
-static struct clksrc_sources clk_src_d0 = {
-        .sources        = clk_src_d0_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_d0_list),
-};
-
-static struct clksrc_clk clk_mout_d0 = {
-        .clk = {
-                .name           = "mout_d0",
-                .id             = -1,
-        },
-        .sources        = &clk_src_d0,
-        .reg_src        = { .reg = S5P_CLK_MUX_STAT0, .shift = 20, .size = 3 },
-};
-
-static struct clk clk_dout_apll = {
-        .name           = "dout_apll",
-        .id             = -1,
-        .parent         = &clk_mout_arm.clk,
-};
-
-/* Possible clock sources for D0SYNC Mux */
-static struct clk *clk_src_d0sync_list[] = {
-        [1] = &clk_mout_d0.clk,
-        [2] = &clk_dout_apll,
-};
-
-static struct clksrc_sources clk_src_d0sync = {
-        .sources        = clk_src_d0sync_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_d0sync_list),
-};
-
-static struct clksrc_clk clk_mout_d0sync = {
-        .clk    = {
-                .name           = "mout_d0sync",
-                .id             = -1,
-        },
-        .sources        = &clk_src_d0sync,
-        .reg_src        = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
-};
-
-/* Possible clock sources for D1 Mux */
-static struct clk *clk_src_d1_list[] = {
-        [1] = &clk_mout_mpll.clk,
-        [2] = &clk_dout_a2m,
-};
-
-static struct clksrc_sources clk_src_d1 = {
-        .sources        = clk_src_d1_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_d1_list),
-};
-
-static struct clksrc_clk clk_mout_d1 = {
-        .clk    = {
-                .name           = "mout_d1",
-                .id             = -1,
-        },
-        .sources        = &clk_src_d1,
-        .reg_src        = { .reg = S5P_CLK_MUX_STAT0, .shift = 24, .size = 3 },
-};
-
-/* Possible clock sources for D1SYNC Mux */
-static struct clk *clk_src_d1sync_list[] = {
-        [1] = &clk_mout_d1.clk,
-        [2] = &clk_dout_apll,
-};
-
-static struct clksrc_sources clk_src_d1sync = {
-        .sources        = clk_src_d1sync_list,
-        .nr_sources     = ARRAY_SIZE(clk_src_d1sync_list),
-};
-
-static struct clksrc_clk clk_mout_d1sync = {
-        .clk    = {
-                .name           = "mout_d1sync",
-                .id             = -1,
-        },
-        .sources        = &clk_src_d1sync,
-        .reg_src        = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
-};
-
-static struct clk clk_hclkd0 = {
-        .name           = "hclkd0",
-        .id             = -1,
-        .parent         = &clk_mout_d0sync.clk,
-};
-
-static struct clk clk_hclkd1 = {
-        .name           = "hclkd1",
-        .id             = -1,
-        .parent         = &clk_mout_d1sync.clk,
-};
-
-static struct clk clk_pclkd0 = {
-        .name           = "pclkd0",
-        .id             = -1,
-        .parent         = &clk_hclkd0,
-};
-
-static struct clk clk_pclkd1 = {
-        .name           = "pclkd1",
-        .id             = -1,
-        .parent         = &clk_hclkd1,
-};
-
-int s5p6442_clk_ip0_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
-}
-
-int s5p6442_clk_ip3_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
-}
-
-static struct clksrc_clk clksrcs[] = {
-        {
-                .clk    = {
-                        .name           = "dout_a2m",
-                        .id             = -1,
-                        .parent         = &clk_mout_apll.clk,
-                },
-                .sources = &clk_src_apll,
-                .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
-                .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "dout_apll",
-                        .id             = -1,
-                        .parent         = &clk_mout_arm.clk,
-                },
-                .sources = &clk_src_arm,
-                .reg_src = { .reg = S5P_CLK_MUX_STAT0, .shift = 16, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "hclkd1",
-                        .id             = -1,
-                        .parent         = &clk_mout_d1sync.clk,
-                },
-                .sources = &clk_src_d1sync,
-                .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "hclkd0",
-                        .id             = -1,
-                        .parent         = &clk_mout_d0sync.clk,
-                },
-                .sources = &clk_src_d0sync,
-                .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
-        }, {
-                .clk    = {
-                        .name           = "pclkd0",
-                        .id             = -1,
-                        .parent         = &clk_hclkd0,
-                },
-                .sources = &clk_src_d0sync,
-                .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 28, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
-        }, {
-                .clk    = {
-                        .name           = "pclkd1",
-                        .id             = -1,
-                        .parent         = &clk_hclkd1,
-                },
-                .sources = &clk_src_d1sync,
-                .reg_src = { .reg = S5P_CLK_MUX_STAT1, .shift = 24, .size = 3 },
-                .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
-        }
-};
-
-/* Clock initialisation code */
-static struct clksrc_clk *init_parents[] = {
-        &clk_mout_apll,
-        &clk_mout_mpll,
-        &clk_mout_epll,
-        &clk_mout_arm,
-        &clk_mout_d0,
-        &clk_mout_d0sync,
-        &clk_mout_d1,
-        &clk_mout_d1sync,
-};
-
-void __init_or_cpufreq s5p6442_setup_clocks(void)
-{
-        struct clk *pclkd0_clk;
-        struct clk *pclkd1_clk;
-
-        unsigned long xtal;
-        unsigned long arm;
-        unsigned long hclkd0 = 0;
-        unsigned long hclkd1 = 0;
-        unsigned long pclkd0 = 0;
-        unsigned long pclkd1 = 0;
-
-        unsigned long apll;
-        unsigned long mpll;
-        unsigned long epll;
-        unsigned int ptr;
-
-        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
-
-        xtal = clk_get_rate(&clk_xtal);
-
-        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
-
-        apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
-        mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
-        epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
-
-        printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
-                        apll, mpll, epll);
-
-        clk_fout_apll.rate = apll;
-        clk_fout_mpll.rate = mpll;
-        clk_fout_epll.rate = epll;
-
-        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
-                s3c_set_clksrc(init_parents[ptr], true);
-
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_set_clksrc(&clksrcs[ptr], true);
-
-        arm = clk_get_rate(&clk_dout_apll);
-        hclkd0 = clk_get_rate(&clk_hclkd0);
-        hclkd1 = clk_get_rate(&clk_hclkd1);
-
-        pclkd0_clk = clk_get(NULL, "pclkd0");
-        BUG_ON(IS_ERR(pclkd0_clk));
-
-        pclkd0 = clk_get_rate(pclkd0_clk);
-        clk_put(pclkd0_clk);
-
-        pclkd1_clk = clk_get(NULL, "pclkd1");
-        BUG_ON(IS_ERR(pclkd1_clk));
-
-        pclkd1 = clk_get_rate(pclkd1_clk);
-        clk_put(pclkd1_clk);
-
-        printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
-                        hclkd0, hclkd1, pclkd0, pclkd1);
-
-        /* For backward compatibility */
-        clk_f.rate = arm;
-        clk_h.rate = hclkd1;
-        clk_p.rate = pclkd1;
-
-        clk_pclkd0.rate = pclkd0;
-        clk_pclkd1.rate = pclkd1;
-}
-
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "pdma",
-                .id             = -1,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip0_ctrl,
-                .ctrlbit        = (1 << 3),
-        },
-};
-
-static struct clk init_clocks[] = {
-        {
-                .name           = "systimer",
-                .id             = -1,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip3_ctrl,
-                .ctrlbit        = (1<<16),
-        }, {
-                .name           = "uart",
-                .id             = 0,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip3_ctrl,
-                .ctrlbit        = (1<<17),
-        }, {
-                .name           = "uart",
-                .id             = 1,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip3_ctrl,
-                .ctrlbit        = (1<<18),
-        }, {
-                .name           = "uart",
-                .id             = 2,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip3_ctrl,
-                .ctrlbit        = (1<<19),
-        }, {
-                .name           = "watchdog",
-                .id             = -1,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip3_ctrl,
-                .ctrlbit        = (1 << 22),
-        }, {
-                .name           = "timers",
-                .id             = -1,
-                .parent         = &clk_pclkd1,
-                .enable         = s5p6442_clk_ip3_ctrl,
-                .ctrlbit        = (1<<23),
-        },
-};
-
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_epll,
-        &clk_mout_apll.clk,
-        &clk_mout_mpll.clk,
-        &clk_mout_epll.clk,
-        &clk_mout_d0.clk,
-        &clk_mout_d0sync.clk,
-        &clk_mout_d1.clk,
-        &clk_mout_d1sync.clk,
-        &clk_hclkd0,
-        &clk_pclkd0,
-        &clk_hclkd1,
-        &clk_pclkd1,
-};
-
-void __init s5p6442_register_clocks(void)
-{
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-
-        s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-
-        s3c_pwmclk_init();
-}
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
deleted file mode 100644
index 842af86bda6d..000000000000
--- a/arch/arm/mach-s5p6442/cpu.c
+++ /dev/null
@@ -1,143 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/cpu.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/sysdev.h>
-#include <linux/serial_core.h>
-#include <linux/platform_device.h>
-#include <linux/sched.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-
-#include <asm/proc-fns.h>
-
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/irq.h>
-
-#include <plat/regs-serial.h>
-#include <mach/regs-clock.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/clock.h>
-#include <plat/s5p6442.h>
-
-/* Initial IO mappings */
-
-static struct map_desc s5p6442_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSTIMER,
-                .pfn            = __phys_to_pfn(S5P6442_PA_SYSTIMER),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S5P_VA_GPIO,
-                .pfn            = __phys_to_pfn(S5P6442_PA_GPIO),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC0,
-                .pfn            = __phys_to_pfn(S5P6442_PA_VIC0),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC1,
-                .pfn            = __phys_to_pfn(S5P6442_PA_VIC1),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)VA_VIC2,
-                .pfn            = __phys_to_pfn(S5P6442_PA_VIC2),
-                .length         = SZ_16K,
-                .type           = MT_DEVICE,
-        }, {
-                .virtual        = (unsigned long)S3C_VA_UART,
-                .pfn            = __phys_to_pfn(S3C_PA_UART),
-                .length         = SZ_512K,
-                .type           = MT_DEVICE,
-        }
-};
-
-static void s5p6442_idle(void)
-{
-        if (!need_resched())
-                cpu_do_idle();
-
-        local_irq_enable();
-}
-
-/*
- * s5p6442_map_io
- *
- * register the standard cpu IO areas
- */
-
-void __init s5p6442_map_io(void)
-{
-        iotable_init(s5p6442_iodesc, ARRAY_SIZE(s5p6442_iodesc));
-}
-
-void __init s5p6442_init_clocks(int xtal)
-{
-        printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
-
-        s3c24xx_register_baseclocks(xtal);
-        s5p_register_clocks(xtal);
-        s5p6442_register_clocks();
-        s5p6442_setup_clocks();
-}
-
-void __init s5p6442_init_irq(void)
-{
-        /* S5P6442 supports 3 VIC */
-        u32 vic[3];
-
-        /* VIC0, VIC1, and VIC2: some interrupt reserved */
-        vic[0] = 0x7fefffff;
-        vic[1] = 0X7f389c81;
-        vic[2] = 0X1bbbcfff;
-
-        s5p_init_irq(vic, ARRAY_SIZE(vic));
-}
-
-struct sysdev_class s5p6442_sysclass = {
-        .name   = "s5p6442-core",
-};
-
-static struct sys_device s5p6442_sysdev = {
-        .cls    = &s5p6442_sysclass,
-};
-
-static int __init s5p6442_core_init(void)
-{
-        return sysdev_class_register(&s5p6442_sysclass);
-}
-
-core_initcall(s5p6442_core_init);
-
-int __init s5p6442_init(void)
-{
-        printk(KERN_INFO "S5P6442: Initializing architecture\n");
-
-        /* set idle function */
-        pm_idle = s5p6442_idle;
-
-        return sysdev_register(&s5p6442_sysdev);
-}
diff --git a/arch/arm/mach-s5p6442/dev-audio.c b/arch/arm/mach-s5p6442/dev-audio.c
deleted file mode 100644
index 8719dc41fe32..000000000000
--- a/arch/arm/mach-s5p6442/dev-audio.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/dev-audio.c
- *
- * Copyright (c) 2010 Samsung Electronics Co. Ltd
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <plat/gpio-cfg.h>
-#include <plat/audio.h>
-
-#include <mach/map.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-
-static int s5p6442_cfg_i2s(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        /* configure GPIO for i2s port */
-        switch (pdev->id) {
-        case 1:
-                base = S5P6442_GPC1(0);
-                break;
-
-        case 0:
-                base = S5P6442_GPC0(0);
-                break;
-
-        default:
-                printk(KERN_ERR "Invalid Device %d\n", pdev->id);
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
-        return 0;
-}
-
-static const char *rclksrc_v35[] = {
-        [0] = "busclk",
-        [1] = "i2sclk",
-};
-
-static struct s3c_audio_pdata i2sv35_pdata = {
-        .cfg_gpio = s5p6442_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .quirks = QUIRK_SEC_DAI | QUIRK_NEED_RSTCLR,
-                        .src_clk = rclksrc_v35,
-                },
-        },
-};
-
-static struct resource s5p6442_iis0_resource[] = {
-        [0] = {
-                .start = S5P6442_PA_I2S0,
-                .end   = S5P6442_PA_I2S0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S0_TX,
-                .end   = DMACH_I2S0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S0_RX,
-                .end   = DMACH_I2S0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = DMACH_I2S0S_TX,
-                .end = DMACH_I2S0S_TX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6442_device_iis0 = {
-        .name = "samsung-i2s",
-        .id = 0,
-        .num_resources    = ARRAY_SIZE(s5p6442_iis0_resource),
-        .resource         = s5p6442_iis0_resource,
-        .dev = {
-                .platform_data = &i2sv35_pdata,
-        },
-};
-
-static const char *rclksrc_v3[] = {
-        [0] = "iis",
-        [1] = "sclk_audio",
-};
-
-static struct s3c_audio_pdata i2sv3_pdata = {
-        .cfg_gpio = s5p6442_cfg_i2s,
-        .type = {
-                .i2s = {
-                        .src_clk = rclksrc_v3,
-                },
-        },
-};
-
-static struct resource s5p6442_iis1_resource[] = {
-        [0] = {
-                .start = S5P6442_PA_I2S1,
-                .end   = S5P6442_PA_I2S1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_I2S1_TX,
-                .end   = DMACH_I2S1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_I2S1_RX,
-                .end   = DMACH_I2S1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6442_device_iis1 = {
-        .name             = "samsung-i2s",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5p6442_iis1_resource),
-        .resource         = s5p6442_iis1_resource,
-        .dev = {
-                .platform_data = &i2sv3_pdata,
-        },
-};
-
-/* PCM Controller platform_devices */
-
-static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
-{
-        unsigned int base;
-
-        switch (pdev->id) {
-        case 0:
-                base = S5P6442_GPC0(0);
-                break;
-
-        case 1:
-                base = S5P6442_GPC1(0);
-                break;
-
-        default:
-                printk(KERN_DEBUG "Invalid PCM Controller number!");
-                return -EINVAL;
-        }
-
-        s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
-        return 0;
-}
-
-static struct s3c_audio_pdata s3c_pcm_pdata = {
-        .cfg_gpio = s5p6442_pcm_cfg_gpio,
-};
-
-static struct resource s5p6442_pcm0_resource[] = {
-        [0] = {
-                .start = S5P6442_PA_PCM0,
-                .end   = S5P6442_PA_PCM0 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM0_TX,
-                .end   = DMACH_PCM0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM0_RX,
-                .end   = DMACH_PCM0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6442_device_pcm0 = {
-        .name             = "samsung-pcm",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5p6442_pcm0_resource),
-        .resource         = s5p6442_pcm0_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
-
-static struct resource s5p6442_pcm1_resource[] = {
-        [0] = {
-                .start = S5P6442_PA_PCM1,
-                .end   = S5P6442_PA_PCM1 + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_PCM1_TX,
-                .end   = DMACH_PCM1_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_PCM1_RX,
-                .end   = DMACH_PCM1_RX,
-                .flags = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device s5p6442_device_pcm1 = {
-        .name             = "samsung-pcm",
-        .id               = 1,
-        .num_resources    = ARRAY_SIZE(s5p6442_pcm1_resource),
-        .resource         = s5p6442_pcm1_resource,
-        .dev = {
-                .platform_data = &s3c_pcm_pdata,
-        },
-};
diff --git a/arch/arm/mach-s5p6442/dev-spi.c b/arch/arm/mach-s5p6442/dev-spi.c
deleted file mode 100644
index cce8c2470709..000000000000
--- a/arch/arm/mach-s5p6442/dev-spi.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/dev-spi.c
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio.h>
-
-#include <mach/dma.h>
-#include <mach/map.h>
-#include <mach/irqs.h>
-#include <mach/spi-clocks.h>
-
-#include <plat/s3c64xx-spi.h>
-#include <plat/gpio-cfg.h>
-
-static char *spi_src_clks[] = {
-        [S5P6442_SPI_SRCCLK_PCLK] = "pclk",
-        [S5P6442_SPI_SRCCLK_SCLK] = "spi_epll",
-};
-
-/* SPI Controller platform_devices */
-
-/* Since we emulate multi-cs capability, we do not touch the CS.
- * The emulated CS is toggled by board specific mechanism, as it can
- * be either some immediate GPIO or some signal out of some other
- * chip in between ... or some yet another way.
- * We simply do not assume anything about CS.
- */
-static int s5p6442_spi_cfg_gpio(struct platform_device *pdev)
-{
-        switch (pdev->id) {
-        case 0:
-                s3c_gpio_cfgpin(S5P6442_GPB(0), S3C_GPIO_SFN(2));
-                s3c_gpio_setpull(S5P6442_GPB(0), S3C_GPIO_PULL_UP);
-                s3c_gpio_cfgall_range(S5P6442_GPB(2), 2,
-                                      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-                break;
-
-        default:
-                dev_err(&pdev->dev, "Invalid SPI Controller number!");
-                return -EINVAL;
-        }
-
-        return 0;
-}
-
-static struct resource s5p6442_spi0_resource[] = {
-        [0] = {
-                .start = S5P6442_PA_SPI,
-                .end   = S5P6442_PA_SPI + 0x100 - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = DMACH_SPI0_TX,
-                .end   = DMACH_SPI0_TX,
-                .flags = IORESOURCE_DMA,
-        },
-        [2] = {
-                .start = DMACH_SPI0_RX,
-                .end   = DMACH_SPI0_RX,
-                .flags = IORESOURCE_DMA,
-        },
-        [3] = {
-                .start = IRQ_SPI0,
-                .end   = IRQ_SPI0,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c64xx_spi_info s5p6442_spi0_pdata = {
-        .cfg_gpio = s5p6442_spi_cfg_gpio,
-        .fifo_lvl_mask = 0x1ff,
-        .rx_lvl_offset = 15,
-};
-
-static u64 spi_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device s5p6442_device_spi = {
-        .name             = "s3c64xx-spi",
-        .id               = 0,
-        .num_resources    = ARRAY_SIZE(s5p6442_spi0_resource),
-        .resource         = s5p6442_spi0_resource,
-        .dev = {
-                .dma_mask               = &spi_dmamask,
-                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                .platform_data = &s5p6442_spi0_pdata,
-        },
-};
-
-void __init s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs)
-{
-        struct s3c64xx_spi_info *pd;
-
-        /* Reject invalid configuration */
-        if (!num_cs || src_clk_nr < 0
-                        || src_clk_nr > S5P6442_SPI_SRCCLK_SCLK) {
-                printk(KERN_ERR "%s: Invalid SPI configuration\n", __func__);
-                return;
-        }
-
-        switch (cntrlr) {
-        case 0:
-                pd = &s5p6442_spi0_pdata;
-                break;
-        default:
-                printk(KERN_ERR "%s: Invalid SPI controller(%d)\n",
-                                                        __func__, cntrlr);
-                return;
-        }
-
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        pd->src_clk_name = spi_src_clks[src_clk_nr];
-}
diff --git a/arch/arm/mach-s5p6442/dma.c b/arch/arm/mach-s5p6442/dma.c
deleted file mode 100644
index 7dfb13654f8a..000000000000
--- a/arch/arm/mach-s5p6442/dma.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
-#include <plat/devs.h>
-#include <plat/irqs.h>
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#include <plat/s3c-pl330-pdata.h>
-
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
-static struct resource s5p6442_pdma_resource[] = {
-        [0] = {
-                .start  = S5P6442_PA_PDMA,
-                .end    = S5P6442_PA_PDMA + SZ_4K,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PDMA,
-                .end    = IRQ_PDMA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
-        .peri = {
-                [0] = DMACH_UART0_RX,
-                [1] = DMACH_UART0_TX,
-                [2] = DMACH_UART1_RX,
-                [3] = DMACH_UART1_TX,
-                [4] = DMACH_UART2_RX,
-                [5] = DMACH_UART2_TX,
-                [6] = DMACH_MAX,
-                [7] = DMACH_MAX,
-                [8] = DMACH_MAX,
-                [9] = DMACH_I2S0_RX,
-                [10] = DMACH_I2S0_TX,
-                [11] = DMACH_I2S0S_TX,
-                [12] = DMACH_I2S1_RX,
-                [13] = DMACH_I2S1_TX,
-                [14] = DMACH_MAX,
-                [15] = DMACH_MAX,
-                [16] = DMACH_SPI0_RX,
-                [17] = DMACH_SPI0_TX,
-                [18] = DMACH_MAX,
-                [19] = DMACH_MAX,
-                [20] = DMACH_PCM0_RX,
-                [21] = DMACH_PCM0_TX,
-                [22] = DMACH_PCM1_RX,
-                [23] = DMACH_PCM1_TX,
-                [24] = DMACH_MAX,
-                [25] = DMACH_MAX,
-                [26] = DMACH_MAX,
-                [27] = DMACH_MSM_REQ0,
-                [28] = DMACH_MSM_REQ1,
-                [29] = DMACH_MSM_REQ2,
-                [30] = DMACH_MSM_REQ3,
-                [31] = DMACH_MAX,
-        },
-};
-
-static struct platform_device s5p6442_device_pdma = {
-        .name           = "s3c-pl330",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(s5p6442_pdma_resource),
-        .resource       = s5p6442_pdma_resource,
-        .dev            = {
-                .dma_mask = &dma_dmamask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-                .platform_data = &s5p6442_pdma_pdata,
-        },
-};
-
-static struct platform_device *s5p6442_dmacs[] __initdata = {
-        &s5p6442_device_pdma,
-};
-
-static int __init s5p6442_dma_init(void)
-{
-        platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
-
-        return 0;
-}
-arch_initcall(s5p6442_dma_init);
diff --git a/arch/arm/mach-s5p6442/include/mach/debug-macro.S b/arch/arm/mach-s5p6442/include/mach/debug-macro.S
deleted file mode 100644
index e2213205d780..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/debug-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/debug-macro.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <mach/map.h>
-#include <plat/regs-serial.h>
-
-        .macro addruart, rp, rv
-                ldr     \rp, = S3C_PA_UART
-                ldr     \rv, = S3C_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
-                add     \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-
-#define fifo_full fifo_full_s5pv210
-#define fifo_level fifo_level_s5pv210
-
-/* include the reset of the code which will do the work, we're only
- * compiling for a single cpu processor type so the default of s3c2440
- * will be fine with us.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5p6442/include/mach/dma.h b/arch/arm/mach-s5p6442/include/mach/dma.h
deleted file mode 100644
index 81209eb1409b..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __MACH_DMA_H
-#define __MACH_DMA_H
-
-/* This platform uses the common S3C DMA API driver for PL330 */
-#include <plat/s3c-dma-pl330.h>
-
-#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/entry-macro.S b/arch/arm/mach-s5p6442/include/mach/entry-macro.S
deleted file mode 100644
index 6d574edbf1ae..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/entry-macro.S
+++ /dev/null
@@ -1,48 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/entry-macro.S
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Low-level IRQ helper macros for the Samsung S5P6442
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-#include <plat/irqs.h>
-
-        .macro  disable_fiq
-        .endm
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =VA_VIC0
-        .endm
-
-        .macro  arch_ret_to_user, tmp1, tmp2
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-        @ check the vic0
-        mov     \irqnr, # S5P_IRQ_OFFSET + 31
-        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
-        teq     \irqstat, #0
-
-        @ otherwise try vic1
-        addeq   \tmp, \base, #(VA_VIC1 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-
-        @ otherwise try vic2
-        addeq   \tmp, \base, #(VA_VIC2 - VA_VIC0)
-        addeq   \irqnr, \irqnr, #32
-        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
-        teqeq   \irqstat, #0
-
-        clzne   \irqstat, \irqstat
-        subne   \irqnr, \irqnr, \irqstat
-        .endm
diff --git a/arch/arm/mach-s5p6442/include/mach/gpio.h b/arch/arm/mach-s5p6442/include/mach/gpio.h
deleted file mode 100644
index b8715df2fdab..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/gpio.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/gpio.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-#define gpio_to_irq     __gpio_to_irq
-
-/* GPIO bank sizes */
-#define S5P6442_GPIO_A0_NR      (8)
-#define S5P6442_GPIO_A1_NR      (2)
-#define S5P6442_GPIO_B_NR       (4)
-#define S5P6442_GPIO_C0_NR      (5)
-#define S5P6442_GPIO_C1_NR      (5)
-#define S5P6442_GPIO_D0_NR      (2)
-#define S5P6442_GPIO_D1_NR      (6)
-#define S5P6442_GPIO_E0_NR      (8)
-#define S5P6442_GPIO_E1_NR      (5)
-#define S5P6442_GPIO_F0_NR      (8)
-#define S5P6442_GPIO_F1_NR      (8)
-#define S5P6442_GPIO_F2_NR      (8)
-#define S5P6442_GPIO_F3_NR      (6)
-#define S5P6442_GPIO_G0_NR      (7)
-#define S5P6442_GPIO_G1_NR      (7)
-#define S5P6442_GPIO_G2_NR      (7)
-#define S5P6442_GPIO_H0_NR      (8)
-#define S5P6442_GPIO_H1_NR      (8)
-#define S5P6442_GPIO_H2_NR      (8)
-#define S5P6442_GPIO_H3_NR      (8)
-#define S5P6442_GPIO_J0_NR      (8)
-#define S5P6442_GPIO_J1_NR      (6)
-#define S5P6442_GPIO_J2_NR      (8)
-#define S5P6442_GPIO_J3_NR      (8)
-#define S5P6442_GPIO_J4_NR      (5)
-
-/* GPIO bank numbers */
-
-/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
- * space for debugging purposes so that any accidental
- * change from one gpio bank to another can be caught.
-*/
-
-#define S5P6442_GPIO_NEXT(__gpio) \
-        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-enum s5p_gpio_number {
-        S5P6442_GPIO_A0_START   = 0,
-        S5P6442_GPIO_A1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_A0),
-        S5P6442_GPIO_B_START    = S5P6442_GPIO_NEXT(S5P6442_GPIO_A1),
-        S5P6442_GPIO_C0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_B),
-        S5P6442_GPIO_C1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_C0),
-        S5P6442_GPIO_D0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_C1),
-        S5P6442_GPIO_D1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_D0),
-        S5P6442_GPIO_E0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_D1),
-        S5P6442_GPIO_E1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_E0),
-        S5P6442_GPIO_F0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_E1),
-        S5P6442_GPIO_F1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_F0),
-        S5P6442_GPIO_F2_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_F1),
-        S5P6442_GPIO_F3_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_F2),
-        S5P6442_GPIO_G0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_F3),
-        S5P6442_GPIO_G1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_G0),
-        S5P6442_GPIO_G2_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_G1),
-        S5P6442_GPIO_H0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_G2),
-        S5P6442_GPIO_H1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_H0),
-        S5P6442_GPIO_H2_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_H1),
-        S5P6442_GPIO_H3_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_H2),
-        S5P6442_GPIO_J0_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_H3),
-        S5P6442_GPIO_J1_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_J0),
-        S5P6442_GPIO_J2_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_J1),
-        S5P6442_GPIO_J3_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_J2),
-        S5P6442_GPIO_J4_START   = S5P6442_GPIO_NEXT(S5P6442_GPIO_J3),
-};
-
-/* S5P6442 GPIO number definitions. */
-#define S5P6442_GPA0(_nr)       (S5P6442_GPIO_A0_START + (_nr))
-#define S5P6442_GPA1(_nr)       (S5P6442_GPIO_A1_START + (_nr))
-#define S5P6442_GPB(_nr)        (S5P6442_GPIO_B_START + (_nr))
-#define S5P6442_GPC0(_nr)       (S5P6442_GPIO_C0_START + (_nr))
-#define S5P6442_GPC1(_nr)       (S5P6442_GPIO_C1_START + (_nr))
-#define S5P6442_GPD0(_nr)       (S5P6442_GPIO_D0_START + (_nr))
-#define S5P6442_GPD1(_nr)       (S5P6442_GPIO_D1_START + (_nr))
-#define S5P6442_GPE0(_nr)       (S5P6442_GPIO_E0_START + (_nr))
-#define S5P6442_GPE1(_nr)       (S5P6442_GPIO_E1_START + (_nr))
-#define S5P6442_GPF0(_nr)       (S5P6442_GPIO_F0_START + (_nr))
-#define S5P6442_GPF1(_nr)       (S5P6442_GPIO_F1_START + (_nr))
-#define S5P6442_GPF2(_nr)       (S5P6442_GPIO_F2_START + (_nr))
-#define S5P6442_GPF3(_nr)       (S5P6442_GPIO_F3_START + (_nr))
-#define S5P6442_GPG0(_nr)       (S5P6442_GPIO_G0_START + (_nr))
-#define S5P6442_GPG1(_nr)       (S5P6442_GPIO_G1_START + (_nr))
-#define S5P6442_GPG2(_nr)       (S5P6442_GPIO_G2_START + (_nr))
-#define S5P6442_GPH0(_nr)       (S5P6442_GPIO_H0_START + (_nr))
-#define S5P6442_GPH1(_nr)       (S5P6442_GPIO_H1_START + (_nr))
-#define S5P6442_GPH2(_nr)       (S5P6442_GPIO_H2_START + (_nr))
-#define S5P6442_GPH3(_nr)       (S5P6442_GPIO_H3_START + (_nr))
-#define S5P6442_GPJ0(_nr)       (S5P6442_GPIO_J0_START + (_nr))
-#define S5P6442_GPJ1(_nr)       (S5P6442_GPIO_J1_START + (_nr))
-#define S5P6442_GPJ2(_nr)       (S5P6442_GPIO_J2_START + (_nr))
-#define S5P6442_GPJ3(_nr)       (S5P6442_GPIO_J3_START + (_nr))
-#define S5P6442_GPJ4(_nr)       (S5P6442_GPIO_J4_START + (_nr))
-
-/* the end of the S5P6442 specific gpios */
-#define S5P6442_GPIO_END        (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) + 1)
-#define S3C_GPIO_END            S5P6442_GPIO_END
-
-/* define the number of gpios we need to the one after the GPJ4() range */
-#define ARCH_NR_GPIOS           (S5P6442_GPJ4(S5P6442_GPIO_J4_NR) +     \
-                                 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
-
-#include <asm-generic/gpio.h>
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/hardware.h b/arch/arm/mach-s5p6442/include/mach/hardware.h
deleted file mode 100644
index 8cd7b67b49d4..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/hardware.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - Hardware support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H __FILE__
-
-/* currently nothing here, placeholder */
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h
deleted file mode 100644
index 5d2195ad0b67..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/io.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* arch/arm/mach-s5p6442/include/mach/io.h
- *
- * Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Default IO routines for S5P6442
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s5p6442/include/mach/irqs.h b/arch/arm/mach-s5p6442/include/mach/irqs.h
deleted file mode 100644
index 3fbc6c3ad2da..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/irqs.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/irqs.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* VIC0 */
-#define IRQ_EINT16_31           S5P_IRQ_VIC0(16)
-#define IRQ_BATF                S5P_IRQ_VIC0(17)
-#define IRQ_MDMA                S5P_IRQ_VIC0(18)
-#define IRQ_PDMA                S5P_IRQ_VIC0(19)
-#define IRQ_TIMER0_VIC          S5P_IRQ_VIC0(21)
-#define IRQ_TIMER1_VIC          S5P_IRQ_VIC0(22)
-#define IRQ_TIMER2_VIC          S5P_IRQ_VIC0(23)
-#define IRQ_TIMER3_VIC          S5P_IRQ_VIC0(24)
-#define IRQ_TIMER4_VIC          S5P_IRQ_VIC0(25)
-#define IRQ_SYSTIMER            S5P_IRQ_VIC0(26)
-#define IRQ_WDT                 S5P_IRQ_VIC0(27)
-#define IRQ_RTC_ALARM           S5P_IRQ_VIC0(28)
-#define IRQ_RTC_TIC             S5P_IRQ_VIC0(29)
-#define IRQ_GPIOINT             S5P_IRQ_VIC0(30)
-
-/* VIC1 */
-#define IRQ_PMU                 S5P_IRQ_VIC1(0)
-#define IRQ_ONENAND             S5P_IRQ_VIC1(7)
-#define IRQ_UART0               S5P_IRQ_VIC1(10)
-#define IRQ_UART1               S5P_IRQ_VIC1(11)
-#define IRQ_UART2               S5P_IRQ_VIC1(12)
-#define IRQ_SPI0                S5P_IRQ_VIC1(15)
-#define IRQ_IIC                 S5P_IRQ_VIC1(19)
-#define IRQ_IIC1                S5P_IRQ_VIC1(20)
-#define IRQ_IIC2                S5P_IRQ_VIC1(21)
-#define IRQ_OTG                 S5P_IRQ_VIC1(24)
-#define IRQ_MSM                 S5P_IRQ_VIC1(25)
-#define IRQ_HSMMC0              S5P_IRQ_VIC1(26)
-#define IRQ_HSMMC1              S5P_IRQ_VIC1(27)
-#define IRQ_HSMMC2              S5P_IRQ_VIC1(28)
-#define IRQ_COMMRX              S5P_IRQ_VIC1(29)
-#define IRQ_COMMTX              S5P_IRQ_VIC1(30)
-
-/* VIC2 */
-#define IRQ_LCD0                S5P_IRQ_VIC2(0)
-#define IRQ_LCD1                S5P_IRQ_VIC2(1)
-#define IRQ_LCD2                S5P_IRQ_VIC2(2)
-#define IRQ_LCD3                S5P_IRQ_VIC2(3)
-#define IRQ_ROTATOR             S5P_IRQ_VIC2(4)
-#define IRQ_FIMC0               S5P_IRQ_VIC2(5)
-#define IRQ_FIMC1               S5P_IRQ_VIC2(6)
-#define IRQ_FIMC2               S5P_IRQ_VIC2(7)
-#define IRQ_JPEG                S5P_IRQ_VIC2(8)
-#define IRQ_3D                  S5P_IRQ_VIC2(10)
-#define IRQ_Mixer               S5P_IRQ_VIC2(11)
-#define IRQ_MFC                 S5P_IRQ_VIC2(14)
-#define IRQ_TVENC               S5P_IRQ_VIC2(15)
-#define IRQ_I2S0                S5P_IRQ_VIC2(16)
-#define IRQ_I2S1                S5P_IRQ_VIC2(17)
-#define IRQ_RP                  S5P_IRQ_VIC2(19)
-#define IRQ_PCM0                S5P_IRQ_VIC2(20)
-#define IRQ_PCM1                S5P_IRQ_VIC2(21)
-#define IRQ_ADC                 S5P_IRQ_VIC2(23)
-#define IRQ_PENDN               S5P_IRQ_VIC2(24)
-#define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
-#define IRQ_SSS_INT             S5P_IRQ_VIC2(27)
-#define IRQ_SSS_HASH            S5P_IRQ_VIC2(28)
-#define IRQ_VIC_END             S5P_IRQ_VIC2(31)
-
-#define S5P_IRQ_EINT_BASE       (IRQ_VIC_END + 1)
-
-#define S5P_EINT_BASE1          (S5P_IRQ_VIC0(0))
-#define S5P_EINT_BASE2          (S5P_IRQ_EINT_BASE)
-
-/* Set the default NR_IRQS */
-
-#define NR_IRQS                 (IRQ_EINT(31) + 1)
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
deleted file mode 100644
index 058dab4482a1..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/map.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MAP_H
-#define __ASM_ARCH_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map-s5p.h>
-
-#define S5P6442_PA_SDRAM        0x20000000
-
-#define S5P6442_PA_I2S0         0xC0B00000
-#define S5P6442_PA_I2S1         0xF2200000
-
-#define S5P6442_PA_CHIPID       0xE0000000
-
-#define S5P6442_PA_SYSCON       0xE0100000
-
-#define S5P6442_PA_GPIO         0xE0200000
-
-#define S5P6442_PA_VIC0         0xE4000000
-#define S5P6442_PA_VIC1         0xE4100000
-#define S5P6442_PA_VIC2         0xE4200000
-
-#define S5P6442_PA_SROMC        0xE7000000
-
-#define S5P6442_PA_MDMA         0xE8000000
-#define S5P6442_PA_PDMA         0xE9000000
-
-#define S5P6442_PA_TIMER        0xEA000000
-
-#define S5P6442_PA_SYSTIMER     0xEA100000
-
-#define S5P6442_PA_WATCHDOG     0xEA200000
-
-#define S5P6442_PA_UART         0xEC000000
-
-#define S5P6442_PA_IIC0         0xEC100000
-
-#define S5P6442_PA_SPI          0xEC300000
-
-#define S5P6442_PA_PCM0         0xF2400000
-#define S5P6442_PA_PCM1         0xF2500000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_IIC              S5P6442_PA_IIC0
-#define S3C_PA_WDT              S5P6442_PA_WATCHDOG
-
-#define S5P_PA_CHIPID           S5P6442_PA_CHIPID
-#define S5P_PA_SDRAM            S5P6442_PA_SDRAM
-#define S5P_PA_SROMC            S5P6442_PA_SROMC
-#define S5P_PA_SYSCON           S5P6442_PA_SYSCON
-#define S5P_PA_TIMER            S5P6442_PA_TIMER
-
-/* UART */
-
-#define S3C_PA_UART             S5P6442_PA_UART
-
-#define S5P_PA_UART(x)          (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0            S5P_PA_UART(0)
-#define S5P_PA_UART1            S5P_PA_UART(1)
-#define S5P_PA_UART2            S5P_PA_UART(2)
-
-#define S5P_SZ_UART             SZ_256
-
-#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/memory.h b/arch/arm/mach-s5p6442/include/mach/memory.h
deleted file mode 100644
index cfe259dded33..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/memory.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - Memory definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PLAT_PHYS_OFFSET                UL(0x20000000)
-#define CONSISTENT_DMA_SIZE     SZ_8M
-
-#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
deleted file mode 100644
index 2724b37def31..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
- *
- * S5P6442 - pwm clock and timer support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_PWMCLK_H
-#define __ASM_ARCH_PWMCLK_H __FILE__
-
-/**
- * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
- * @tcfg: The timer TCFG1 register bits shifted down to 0.
- *
- * Return true if the given configuration from TCFG1 is a TCLK instead
- * any of the TDIV clocks.
- */
-static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
-{
-        return tcfg == S3C64XX_TCFG1_MUX_TCLK;
-}
-
-/**
- * tcfg_to_divisor() - convert tcfg1 setting to a divisor
- * @tcfg1: The tcfg1 setting, shifted down.
- *
- * Get the divisor value for the given tcfg1 setting. We assume the
- * caller has already checked to see if this is not a TCLK source.
- */
-static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
-{
-        return 1 << tcfg1;
-}
-
-/**
- * pwm_tdiv_has_div1() - does the tdiv setting have a /1
- *
- * Return true if we have a /1 in the tdiv setting.
- */
-static inline unsigned int pwm_tdiv_has_div1(void)
-{
-        return 1;
-}
-
-/**
- * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
- * @div: The divisor to calculate the bit information for.
- *
- * Turn a divisor into the necessary bit field for TCFG1.
- */
-static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
-{
-        return ilog2(div);
-}
-
-#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
-
-#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-clock.h b/arch/arm/mach-s5p6442/include/mach/regs-clock.h
deleted file mode 100644
index 00828a336991..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/regs-clock.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - Clock register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_CLOCK_H
-#define __ASM_ARCH_REGS_CLOCK_H __FILE__
-
-#include <mach/map.h>
-
-#define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
-
-#define S5P_APLL_LOCK           S5P_CLKREG(0x00)
-#define S5P_MPLL_LOCK           S5P_CLKREG(0x08)
-#define S5P_EPLL_LOCK           S5P_CLKREG(0x10)
-#define S5P_VPLL_LOCK           S5P_CLKREG(0x20)
-
-#define S5P_APLL_CON            S5P_CLKREG(0x100)
-#define S5P_MPLL_CON            S5P_CLKREG(0x108)
-#define S5P_EPLL_CON            S5P_CLKREG(0x110)
-#define S5P_VPLL_CON            S5P_CLKREG(0x120)
-
-#define S5P_CLK_SRC0            S5P_CLKREG(0x200)
-#define S5P_CLK_SRC1            S5P_CLKREG(0x204)
-#define S5P_CLK_SRC2            S5P_CLKREG(0x208)
-#define S5P_CLK_SRC3            S5P_CLKREG(0x20C)
-#define S5P_CLK_SRC4            S5P_CLKREG(0x210)
-#define S5P_CLK_SRC5            S5P_CLKREG(0x214)
-#define S5P_CLK_SRC6            S5P_CLKREG(0x218)
-
-#define S5P_CLK_SRC_MASK0       S5P_CLKREG(0x280)
-#define S5P_CLK_SRC_MASK1       S5P_CLKREG(0x284)
-
-#define S5P_CLK_DIV0            S5P_CLKREG(0x300)
-#define S5P_CLK_DIV1            S5P_CLKREG(0x304)
-#define S5P_CLK_DIV2            S5P_CLKREG(0x308)
-#define S5P_CLK_DIV3            S5P_CLKREG(0x30C)
-#define S5P_CLK_DIV4            S5P_CLKREG(0x310)
-#define S5P_CLK_DIV5            S5P_CLKREG(0x314)
-#define S5P_CLK_DIV6            S5P_CLKREG(0x318)
-
-#define S5P_CLKGATE_IP0         S5P_CLKREG(0x460)
-#define S5P_CLKGATE_IP3         S5P_CLKREG(0x46C)
-
-/* CLK_OUT */
-#define S5P_CLK_OUT_SHIFT       (12)
-#define S5P_CLK_OUT_MASK        (0x1F << S5P_CLK_OUT_SHIFT)
-#define S5P_CLK_OUT             S5P_CLKREG(0x500)
-
-#define S5P_CLK_DIV_STAT0       S5P_CLKREG(0x1000)
-#define S5P_CLK_DIV_STAT1       S5P_CLKREG(0x1004)
-
-#define S5P_CLK_MUX_STAT0       S5P_CLKREG(0x1100)
-#define S5P_CLK_MUX_STAT1       S5P_CLKREG(0x1104)
-
-#define S5P_MDNIE_SEL           S5P_CLKREG(0x7008)
-
-/* Register Bit definition */
-#define S5P_EPLL_EN                     (1<<31)
-#define S5P_EPLL_MASK                   0xffffffff
-#define S5P_EPLLVAL(_m, _p, _s)         ((_m) << 16 | ((_p) << 8) | ((_s)))
-
-/* CLKDIV0 */
-#define S5P_CLKDIV0_APLL_SHIFT          (0)
-#define S5P_CLKDIV0_APLL_MASK           (0x7 << S5P_CLKDIV0_APLL_SHIFT)
-#define S5P_CLKDIV0_A2M_SHIFT           (4)
-#define S5P_CLKDIV0_A2M_MASK            (0x7 << S5P_CLKDIV0_A2M_SHIFT)
-#define S5P_CLKDIV0_D0CLK_SHIFT         (16)
-#define S5P_CLKDIV0_D0CLK_MASK          (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
-#define S5P_CLKDIV0_P0CLK_SHIFT         (20)
-#define S5P_CLKDIV0_P0CLK_MASK          (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
-#define S5P_CLKDIV0_D1CLK_SHIFT         (24)
-#define S5P_CLKDIV0_D1CLK_MASK          (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
-#define S5P_CLKDIV0_P1CLK_SHIFT         (28)
-#define S5P_CLKDIV0_P1CLK_MASK          (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
-
-/* Clock MUX status Registers */
-#define S5P_CLK_MUX_STAT0_APLL_SHIFT    (0)
-#define S5P_CLK_MUX_STAT0_APLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
-#define S5P_CLK_MUX_STAT0_MPLL_SHIFT    (4)
-#define S5P_CLK_MUX_STAT0_MPLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
-#define S5P_CLK_MUX_STAT0_EPLL_SHIFT    (8)
-#define S5P_CLK_MUX_STAT0_EPLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
-#define S5P_CLK_MUX_STAT0_VPLL_SHIFT    (12)
-#define S5P_CLK_MUX_STAT0_VPLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
-#define S5P_CLK_MUX_STAT0_MUXARM_SHIFT  (16)
-#define S5P_CLK_MUX_STAT0_MUXARM_MASK   (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
-#define S5P_CLK_MUX_STAT0_MUXD0_SHIFT   (20)
-#define S5P_CLK_MUX_STAT0_MUXD0_MASK    (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
-#define S5P_CLK_MUX_STAT0_MUXD1_SHIFT   (24)
-#define S5P_CLK_MUX_STAT0_MUXD1_MASK    (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
-#define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT  (24)
-#define S5P_CLK_MUX_STAT1_D1SYNC_MASK   (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
-#define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT  (28)
-#define S5P_CLK_MUX_STAT1_D0SYNC_MASK   (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
-
-#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/regs-irq.h b/arch/arm/mach-s5p6442/include/mach/regs-irq.h
deleted file mode 100644
index 73782b52a83b..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/regs-irq.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/regs-irq.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - IRQ register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_IRQ_H
-#define __ASM_ARCH_REGS_IRQ_H __FILE__
-
-#include <asm/hardware/vic.h>
-#include <mach/map.h>
-
-#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h b/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
deleted file mode 100644
index 7fd88205a97c..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5P6442_PLAT_SPI_CLKS_H
-#define __S5P6442_PLAT_SPI_CLKS_H __FILE__
-
-#define S5P6442_SPI_SRCCLK_PCLK         0
-#define S5P6442_SPI_SRCCLK_SCLK         1
-
-#endif /* __S5P6442_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h
deleted file mode 100644
index c30c1cc1b97e..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/system.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/system.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - system support header
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H __FILE__
-
-#include <plat/system-reset.h>
-
-static void arch_idle(void)
-{
-        /* nothing here yet */
-}
-
-#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/tick.h b/arch/arm/mach-s5p6442/include/mach/tick.h
deleted file mode 100644
index e1d4cabf8297..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/tick.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/tick.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Based on arch/arm/mach-s3c6400/include/mach/tick.h
- *
- * S5P6442 - Timer tick support definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_TICK_H
-#define __ASM_ARCH_TICK_H __FILE__
-
-static inline u32 s3c24xx_ostimer_pending(void)
-{
-        u32 pend = __raw_readl(VA_VIC0 + VIC_RAW_STATUS);
-        return pend & (1 << (IRQ_TIMER4_VIC - S5P_IRQ_VIC0(0)));
-}
-
-#define TICK_MAX        (0xffffffff)
-
-#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/timex.h b/arch/arm/mach-s5p6442/include/mach/timex.h
deleted file mode 100644
index ff8f2fcadeb7..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/timex.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* arch/arm/mach-s5p6442/include/mach/timex.h
- *
- * Copyright (c) 2003-2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S5P6442 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
- * a variable is useless. It seems as long as we make our timers an
- * exact multiple of HZ, any value that makes a 1->1 correspondence
- * for the time conversion functions to/from jiffies is acceptable.
-*/
-
-#define CLOCK_TICK_RATE 12000000
-
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/uncompress.h b/arch/arm/mach-s5p6442/include/mach/uncompress.h
deleted file mode 100644
index 5ac7cbeeb987..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/uncompress.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/include/mach/uncompress.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5P6442 - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <mach/map.h>
-#include <plat/uncompress.h>
-
-static void arch_detect_cpu(void)
-{
-        /* we do not need to do any cpu detection here at the moment. */
-}
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5p6442/include/mach/vmalloc.h b/arch/arm/mach-s5p6442/include/mach/vmalloc.h
deleted file mode 100644
index 4aa55e55ac47..000000000000
--- a/arch/arm/mach-s5p6442/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* arch/arm/mach-s5p6442/include/mach/vmalloc.h
- *
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S5P6442 vmalloc definition
-*/
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END     0xF6000000UL
-
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5p6442/init.c b/arch/arm/mach-s5p6442/init.c
deleted file mode 100644
index 1874bdb71e1d..000000000000
--- a/arch/arm/mach-s5p6442/init.c
+++ /dev/null
@@ -1,44 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/s5p6442-init.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-
-#include <plat/cpu.h>
-#include <plat/devs.h>
-#include <plat/s5p6442.h>
-#include <plat/regs-serial.h>
-
-static struct s3c24xx_uart_clksrc s5p6442_serial_clocks[] = {
-        [0] = {
-                .name           = "pclk",
-                .divisor        = 1,
-                .min_baud       = 0,
-                .max_baud       = 0,
-        },
-};
-
-/* uart registration process */
-void __init s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
-{
-        struct s3c2410_uartcfg *tcfg = cfg;
-        u32 ucnt;
-
-        for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
-                if (!tcfg->clocks) {
-                        tcfg->clocks = s5p6442_serial_clocks;
-                        tcfg->clocks_size = ARRAY_SIZE(s5p6442_serial_clocks);
-                }
-        }
-
-        s3c24xx_init_uartdevs("s5pv210-uart", s5p_uart_resources, cfg, no);
-}
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
deleted file mode 100644
index eaf6b9c489ff..000000000000
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/mach-smdk6442.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/serial_core.h>
-#include <linux/i2c.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-#include <plat/regs-serial.h>
-#include <plat/s5p6442.h>
-#include <plat/devs.h>
-#include <plat/cpu.h>
-#include <plat/iic.h>
-
-/* Following are default values for UCON, ULCON and UFCON UART registers */
-#define SMDK6442_UCON_DEFAULT   (S3C2410_UCON_TXILEVEL |        \
-                                 S3C2410_UCON_RXILEVEL |        \
-                                 S3C2410_UCON_TXIRQMODE |       \
-                                 S3C2410_UCON_RXIRQMODE |       \
-                                 S3C2410_UCON_RXFIFO_TOI |      \
-                                 S3C2443_UCON_RXERR_IRQEN)
-
-#define SMDK6442_ULCON_DEFAULT  S3C2410_LCON_CS8
-
-#define SMDK6442_UFCON_DEFAULT  (S3C2410_UFCON_FIFOMODE |       \
-                                 S5PV210_UFCON_TXTRIG4 |        \
-                                 S5PV210_UFCON_RXTRIG4)
-
-static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
-        [0] = {
-                .hwport         = 0,
-                .flags          = 0,
-                .ucon           = SMDK6442_UCON_DEFAULT,
-                .ulcon          = SMDK6442_ULCON_DEFAULT,
-                .ufcon          = SMDK6442_UFCON_DEFAULT,
-        },
-        [1] = {
-                .hwport         = 1,
-                .flags          = 0,
-                .ucon           = SMDK6442_UCON_DEFAULT,
-                .ulcon          = SMDK6442_ULCON_DEFAULT,
-                .ufcon          = SMDK6442_UFCON_DEFAULT,
-        },
-        [2] = {
-                .hwport         = 2,
-                .flags          = 0,
-                .ucon           = SMDK6442_UCON_DEFAULT,
-                .ulcon          = SMDK6442_ULCON_DEFAULT,
-                .ufcon          = SMDK6442_UFCON_DEFAULT,
-        },
-};
-
-static struct platform_device *smdk6442_devices[] __initdata = {
-        &s3c_device_i2c0,
-        &samsung_asoc_dma,
-        &s5p6442_device_iis0,
-        &s3c_device_wdt,
-};
-
-static struct i2c_board_info smdk6442_i2c_devs0[] __initdata = {
-        { I2C_BOARD_INFO("wm8580", 0x1b), },
-};
-
-static void __init smdk6442_map_io(void)
-{
-        s5p_init_io(NULL, 0, S5P_VA_CHIPID);
-        s3c24xx_init_clocks(12000000);
-        s3c24xx_init_uarts(smdk6442_uartcfgs, ARRAY_SIZE(smdk6442_uartcfgs));
-}
-
-static void __init smdk6442_machine_init(void)
-{
-        s3c_i2c0_set_platdata(NULL);
-        i2c_register_board_info(0, smdk6442_i2c_devs0,
-                        ARRAY_SIZE(smdk6442_i2c_devs0));
-        platform_add_devices(smdk6442_devices, ARRAY_SIZE(smdk6442_devices));
-}
-
-MACHINE_START(SMDK6442, "SMDK6442")
-        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
-        .boot_params    = S5P_PA_SDRAM + 0x100,
-        .init_irq       = s5p6442_init_irq,
-        .map_io         = smdk6442_map_io,
-        .init_machine   = smdk6442_machine_init,
-        .timer          = &s3c24xx_timer,
-MACHINE_END
diff --git a/arch/arm/mach-s5p6442/setup-i2c0.c b/arch/arm/mach-s5p6442/setup-i2c0.c
deleted file mode 100644
index aad85656b0cc..000000000000
--- a/arch/arm/mach-s5p6442/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * I2C0 GPIO configuration.
- *
- * Based on plat-s3c64xx/setup-i2c0.c
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/gpio.h>
-
-struct platform_device; /* don't need the contents */
-
-#include <plat/gpio-cfg.h>
-#include <plat/iic.h>
-
-void s3c_i2c0_cfg_gpio(struct platform_device *dev)
-{
-        s3c_gpio_cfgall_range(S5P6442_GPD1(0), 2,
-                              S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
-}
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index eecab57d2e5d..a5e6e608b498 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o gpiolib.o
+obj-$(CONFIG_CPU_S5PC100)       += cpu.o init.o clock.o
 obj-$(CONFIG_CPU_S5PC100)       += setup-i2c0.o
 obj-$(CONFIG_CPU_S5PC100)       += dma.o
 
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
deleted file mode 100644
index 2842394b28b5..000000000000
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/gpiolib.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- *  Copyright 2009 Samsung Electronics Co
- *  Kyungmin Park <kyungmin.park@samsung.com>
- *
- * S5PC100 - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-
-/* S5PC100 GPIO bank summary:
- *
- * Bank GPIOs   Style   INT Type
- * A0   8       4Bit    GPIO_INT0
- * A1   5       4Bit    GPIO_INT1
- * B    8       4Bit    GPIO_INT2
- * C    5       4Bit    GPIO_INT3
- * D    7       4Bit    GPIO_INT4
- * E0   8       4Bit    GPIO_INT5
- * E1   6       4Bit    GPIO_INT6
- * F0   8       4Bit    GPIO_INT7
- * F1   8       4Bit    GPIO_INT8
- * F2   8       4Bit    GPIO_INT9
- * F3   4       4Bit    GPIO_INT10
- * G0   8       4Bit    GPIO_INT11
- * G1   3       4Bit    GPIO_INT12
- * G2   7       4Bit    GPIO_INT13
- * G3   7       4Bit    GPIO_INT14
- * H0   8       4Bit    WKUP_INT
- * H1   8       4Bit    WKUP_INT
- * H2   8       4Bit    WKUP_INT
- * H3   8       4Bit    WKUP_INT
- * I    8       4Bit    GPIO_INT15
- * J0   8       4Bit    GPIO_INT16
- * J1   5       4Bit    GPIO_INT17
- * J2   8       4Bit    GPIO_INT18
- * J3   8       4Bit    GPIO_INT19
- * J4   4       4Bit    GPIO_INT20
- * K0   8       4Bit    None
- * K1   6       4Bit    None
- * K2   8       4Bit    None
- * K3   8       4Bit    None
- * L0   8       4Bit    None
- * L1   8       4Bit    None
- * L2   8       4Bit    None
- * L3   8       4Bit    None
- */
-
-static struct s3c_gpio_cfg gpio_cfg = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_eint = {
-        .cfg_eint       = 0xf,
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_noint = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-/*
- * GPIO bank's base address given the index of the bank in the
- * list of all gpio banks.
- */
-#define S5PC100_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
-
-/*
- * Following are the gpio banks in S5PC100.
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure gpio_cfg in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of s3c_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
-        {
-                .chip   = {
-                        .base   = S5PC100_GPA0(0),
-                        .ngpio  = S5PC100_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPA1(0),
-                        .ngpio  = S5PC100_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPB(0),
-                        .ngpio  = S5PC100_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPC(0),
-                        .ngpio  = S5PC100_GPIO_C_NR,
-                        .label  = "GPC",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPD(0),
-                        .ngpio  = S5PC100_GPIO_D_NR,
-                        .label  = "GPD",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPE0(0),
-                        .ngpio  = S5PC100_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPE1(0),
-                        .ngpio  = S5PC100_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF0(0),
-                        .ngpio  = S5PC100_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF1(0),
-                        .ngpio  = S5PC100_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF2(0),
-                        .ngpio  = S5PC100_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPF3(0),
-                        .ngpio  = S5PC100_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG0(0),
-                        .ngpio  = S5PC100_GPIO_G0_NR,
-                        .label  = "GPG0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG1(0),
-                        .ngpio  = S5PC100_GPIO_G1_NR,
-                        .label  = "GPG1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG2(0),
-                        .ngpio  = S5PC100_GPIO_G2_NR,
-                        .label  = "GPG2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPG3(0),
-                        .ngpio  = S5PC100_GPIO_G3_NR,
-                        .label  = "GPG3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPI(0),
-                        .ngpio  = S5PC100_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ0(0),
-                        .ngpio  = S5PC100_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ1(0),
-                        .ngpio  = S5PC100_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ2(0),
-                        .ngpio  = S5PC100_GPIO_J2_NR,
-                        .label  = "GPJ2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ3(0),
-                        .ngpio  = S5PC100_GPIO_J3_NR,
-                        .label  = "GPJ3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PC100_GPJ4(0),
-                        .ngpio  = S5PC100_GPIO_J4_NR,
-                        .label  = "GPJ4",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPK0(0),
-                        .ngpio  = S5PC100_GPIO_K0_NR,
-                        .label  = "GPK0",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPK1(0),
-                        .ngpio  = S5PC100_GPIO_K1_NR,
-                        .label  = "GPK1",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPK2(0),
-                        .ngpio  = S5PC100_GPIO_K2_NR,
-                        .label  = "GPK2",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPK3(0),
-                        .ngpio  = S5PC100_GPIO_K3_NR,
-                        .label  = "GPK3",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPL0(0),
-                        .ngpio  = S5PC100_GPIO_L0_NR,
-                        .label  = "GPL0",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPL1(0),
-                        .ngpio  = S5PC100_GPIO_L1_NR,
-                        .label  = "GPL1",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPL2(0),
-                        .ngpio  = S5PC100_GPIO_L2_NR,
-                        .label  = "GPL2",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPL3(0),
-                        .ngpio  = S5PC100_GPIO_L3_NR,
-                        .label  = "GPL3",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PC100_GPL4(0),
-                        .ngpio  = S5PC100_GPIO_L4_NR,
-                        .label  = "GPL4",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC00),
-                .config = &gpio_cfg_eint,
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = S5PC100_GPH0(0),
-                        .ngpio  = S5PC100_GPIO_H0_NR,
-                        .label  = "GPH0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC20),
-                .config = &gpio_cfg_eint,
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = S5PC100_GPH1(0),
-                        .ngpio  = S5PC100_GPIO_H1_NR,
-                        .label  = "GPH1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC40),
-                .config = &gpio_cfg_eint,
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = S5PC100_GPH2(0),
-                        .ngpio  = S5PC100_GPIO_H2_NR,
-                        .label  = "GPH2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC60),
-                .config = &gpio_cfg_eint,
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = S5PC100_GPH3(0),
-                        .ngpio  = S5PC100_GPIO_H3_NR,
-                        .label  = "GPH3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-};
-
-static __init int s5pc100_gpiolib_init(void)
-{
-        struct s3c_gpio_chip *chip = s5pc100_gpio_chips;
-        int nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
-        int gpioint_group = 0;
-        int i;
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL) {
-                        chip->config = &gpio_cfg;
-                        chip->group = gpioint_group++;
-                }
-                if (chip->base == NULL)
-                        chip->base = S5PC100_BANK_BASE(i);
-        }
-
-        samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
-        s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
-
-        return 0;
-}
-core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 11f17907b4e8..50907aca006c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -12,7 +12,7 @@ obj-				:=
 
 # Core support for S5PV210 system
 
-obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o gpiolib.o
+obj-$(CONFIG_CPU_S5PV210)       += cpu.o init.o clock.o dma.o
 obj-$(CONFIG_CPU_S5PV210)       += setup-i2c0.o
 obj-$(CONFIG_S5PV210_PM)        += pm.o sleep.o
 obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
deleted file mode 100644
index 1ba20a703e05..000000000000
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/gpiolib.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * S5PV210 - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-#include <mach/map.h>
-
-static struct s3c_gpio_cfg gpio_cfg = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-static struct s3c_gpio_cfg gpio_cfg_noint = {
-        .set_config     = s3c_gpio_setcfg_s3c64xx_4bit,
-        .set_pull       = s3c_gpio_setpull_updown,
-        .get_pull       = s3c_gpio_getpull_updown,
-};
-
-/* GPIO bank's base address given the index of the bank in the
- * list of all gpio banks.
- */
-#define S5PV210_BANK_BASE(bank_nr)      (S5P_VA_GPIO + ((bank_nr) * 0x20))
-
-/*
- * Following are the gpio banks in v210.
- *
- * The 'config' member when left to NULL, is initialized to the default
- * structure gpio_cfg in the init function below.
- *
- * The 'base' member is also initialized in the init function below.
- * Note: The initialization of 'base' member of s3c_gpio_chip structure
- * uses the above macro and depends on the banks being listed in order here.
- */
-static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
-        {
-                .chip   = {
-                        .base   = S5PV210_GPA0(0),
-                        .ngpio  = S5PV210_GPIO_A0_NR,
-                        .label  = "GPA0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPA1(0),
-                        .ngpio  = S5PV210_GPIO_A1_NR,
-                        .label  = "GPA1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPB(0),
-                        .ngpio  = S5PV210_GPIO_B_NR,
-                        .label  = "GPB",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPC0(0),
-                        .ngpio  = S5PV210_GPIO_C0_NR,
-                        .label  = "GPC0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPC1(0),
-                        .ngpio  = S5PV210_GPIO_C1_NR,
-                        .label  = "GPC1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPD0(0),
-                        .ngpio  = S5PV210_GPIO_D0_NR,
-                        .label  = "GPD0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPD1(0),
-                        .ngpio  = S5PV210_GPIO_D1_NR,
-                        .label  = "GPD1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPE0(0),
-                        .ngpio  = S5PV210_GPIO_E0_NR,
-                        .label  = "GPE0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPE1(0),
-                        .ngpio  = S5PV210_GPIO_E1_NR,
-                        .label  = "GPE1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF0(0),
-                        .ngpio  = S5PV210_GPIO_F0_NR,
-                        .label  = "GPF0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF1(0),
-                        .ngpio  = S5PV210_GPIO_F1_NR,
-                        .label  = "GPF1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF2(0),
-                        .ngpio  = S5PV210_GPIO_F2_NR,
-                        .label  = "GPF2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPF3(0),
-                        .ngpio  = S5PV210_GPIO_F3_NR,
-                        .label  = "GPF3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG0(0),
-                        .ngpio  = S5PV210_GPIO_G0_NR,
-                        .label  = "GPG0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG1(0),
-                        .ngpio  = S5PV210_GPIO_G1_NR,
-                        .label  = "GPG1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG2(0),
-                        .ngpio  = S5PV210_GPIO_G2_NR,
-                        .label  = "GPG2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPG3(0),
-                        .ngpio  = S5PV210_GPIO_G3_NR,
-                        .label  = "GPG3",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PV210_GPI(0),
-                        .ngpio  = S5PV210_GPIO_I_NR,
-                        .label  = "GPI",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ0(0),
-                        .ngpio  = S5PV210_GPIO_J0_NR,
-                        .label  = "GPJ0",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ1(0),
-                        .ngpio  = S5PV210_GPIO_J1_NR,
-                        .label  = "GPJ1",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ2(0),
-                        .ngpio  = S5PV210_GPIO_J2_NR,
-                        .label  = "GPJ2",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ3(0),
-                        .ngpio  = S5PV210_GPIO_J3_NR,
-                        .label  = "GPJ3",
-                },
-        }, {
-                .chip   = {
-                        .base   = S5PV210_GPJ4(0),
-                        .ngpio  = S5PV210_GPIO_J4_NR,
-                        .label  = "GPJ4",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PV210_MP01(0),
-                        .ngpio  = S5PV210_GPIO_MP01_NR,
-                        .label  = "MP01",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PV210_MP02(0),
-                        .ngpio  = S5PV210_GPIO_MP02_NR,
-                        .label  = "MP02",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PV210_MP03(0),
-                        .ngpio  = S5PV210_GPIO_MP03_NR,
-                        .label  = "MP03",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PV210_MP04(0),
-                        .ngpio  = S5PV210_GPIO_MP04_NR,
-                        .label  = "MP04",
-                },
-        }, {
-                .config = &gpio_cfg_noint,
-                .chip   = {
-                        .base   = S5PV210_MP05(0),
-                        .ngpio  = S5PV210_GPIO_MP05_NR,
-                        .label  = "MP05",
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC00),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(0),
-                .chip   = {
-                        .base   = S5PV210_GPH0(0),
-                        .ngpio  = S5PV210_GPIO_H0_NR,
-                        .label  = "GPH0",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC20),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(8),
-                .chip   = {
-                        .base   = S5PV210_GPH1(0),
-                        .ngpio  = S5PV210_GPIO_H1_NR,
-                        .label  = "GPH1",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC40),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(16),
-                .chip   = {
-                        .base   = S5PV210_GPH2(0),
-                        .ngpio  = S5PV210_GPIO_H2_NR,
-                        .label  = "GPH2",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        }, {
-                .base   = (S5P_VA_GPIO + 0xC60),
-                .config = &gpio_cfg_noint,
-                .irq_base = IRQ_EINT(24),
-                .chip   = {
-                        .base   = S5PV210_GPH3(0),
-                        .ngpio  = S5PV210_GPIO_H3_NR,
-                        .label  = "GPH3",
-                        .to_irq = samsung_gpiolib_to_irq,
-                },
-        },
-};
-
-static __init int s5pv210_gpiolib_init(void)
-{
-        struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
-        int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
-        int gpioint_group = 0;
-        int i = 0;
-
-        for (i = 0; i < nr_chips; i++, chip++) {
-                if (chip->config == NULL) {
-                        chip->config = &gpio_cfg;
-                        chip->group = gpioint_group++;
-                }
-                if (chip->base == NULL)
-                        chip->base = S5PV210_BANK_BASE(i);
-        }
-
-        samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
-        s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
-
-        return 0;
-}
-core_initcall(s5pv210_gpiolib_init);
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e2507f66f9d5..612b27000c3e 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -30,6 +30,11 @@ obj-$(CONFIG_ARCH_SH7377)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)       += entry-intc.o
 obj-$(CONFIG_ARCH_SH73A0)       += entry-gic.o
 
+# PM objects
+obj-$(CONFIG_SUSPEND)           += suspend.o
+obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
+obj-$(CONFIG_ARCH_SH7372)       += pm-sh7372.o sleep-sh7372.o
+
 # Board objects
 obj-$(CONFIG_MACH_G3EVM)        += board-g3evm.o
 obj-$(CONFIG_MACH_G4EVM)        += board-g4evm.o
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 3e6f0aab460b..c95258c274c1 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -34,6 +34,8 @@
 #include <linux/input/sh_keysc.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
 #include <linux/sh_clk.h>
 #include <video/sh_mobile_lcdc.h>
 #include <video/sh_mipi_dsi.h>
@@ -156,10 +158,19 @@ static struct resource sh_mmcif_resources[] = {
         },
 };
 
+static struct sh_mmcif_dma sh_mmcif_dma = {
+        .chan_priv_rx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+        },
+        .chan_priv_tx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+        },
+};
 static struct sh_mmcif_plat_data sh_mmcif_platdata = {
         .sup_pclk       = 0,
         .ocr            = MMC_VDD_165_195,
         .caps           = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+        .dma            = &sh_mmcif_dma,
 };
 
 static struct platform_device mmc_device = {
@@ -296,11 +307,13 @@ static struct platform_device lcdc0_device = {
 /* MIPI-DSI */
 static struct resource mipidsi0_resources[] = {
         [0] = {
+                .name   = "DSI0",
                 .start  = 0xfeab0000,
                 .end    = 0xfeab3fff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
+                .name   = "DSI0",
                 .start  = 0xfeab4000,
                 .end    = 0xfeab7fff,
                 .flags  = IORESOURCE_MEM,
@@ -325,6 +338,89 @@ static struct platform_device mipidsi0_device = {
         },
 };
 
+static struct sh_mobile_sdhi_info sdhi0_info = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI0_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI0_RX,
+        .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
+        .tmio_ocr_mask  = MMC_VDD_27_28 | MMC_VDD_28_29,
+};
+
+static struct resource sdhi0_resources[] = {
+        [0] = {
+                .name   = "SDHI0",
+                .start  = 0xee100000,
+                .end    = 0xee1000ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(83),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = gic_spi(84),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = gic_spi(85),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi0_device = {
+        .name           = "sh_mobile_sdhi",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(sdhi0_resources),
+        .resource       = sdhi0_resources,
+        .dev    = {
+                .platform_data  = &sdhi0_info,
+        },
+};
+
+void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
+{
+        gpio_set_value(GPIO_PORT114, state);
+}
+
+static struct sh_mobile_sdhi_info sh_sdhi1_platdata = {
+        .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
+        .dma_slave_rx   = SHDMA_SLAVE_SDHI1_RX,
+        .tmio_flags     = TMIO_MMC_WRPROTECT_DISABLE,
+        .tmio_caps      = MMC_CAP_NONREMOVABLE,
+        .tmio_ocr_mask  = MMC_VDD_32_33 | MMC_VDD_33_34,
+        .set_pwr        = ag5evm_sdhi1_set_pwr,
+};
+
+static struct resource sdhi1_resources[] = {
+        [0] = {
+                .name   = "SDHI1",
+                .start  = 0xee120000,
+                .end    = 0xee1200ff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = gic_spi(87),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = gic_spi(88),
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = gic_spi(89),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device sdhi1_device = {
+        .name           = "sh_mobile_sdhi",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &sh_sdhi1_platdata,
+        },
+        .num_resources  = ARRAY_SIZE(sdhi1_resources),
+        .resource       = sdhi1_resources,
+};
+
 static struct platform_device *ag5evm_devices[] __initdata = {
         &eth_device,
         &keysc_device,
@@ -333,6 +429,8 @@ static struct platform_device *ag5evm_devices[] __initdata = {
         &irda_device,
         &lcdc0_device,
         &mipidsi0_device,
+        &sdhi0_device,
+        &sdhi1_device,
 };
 
 static struct map_desc ag5evm_io_desc[] __initdata = {
@@ -454,6 +552,26 @@ static void __init ag5evm_init(void)
         /* MIPI-DSI clock setup */
         __raw_writel(0x2a809010, DSI0PHYCR);
 
+        /* enable SDHI0 on CN15 [SD I/F] */
+        gpio_request(GPIO_FN_SDHICD0, NULL);
+        gpio_request(GPIO_FN_SDHIWP0, NULL);
+        gpio_request(GPIO_FN_SDHICMD0, NULL);
+        gpio_request(GPIO_FN_SDHICLK0, NULL);
+        gpio_request(GPIO_FN_SDHID0_3, NULL);
+        gpio_request(GPIO_FN_SDHID0_2, NULL);
+        gpio_request(GPIO_FN_SDHID0_1, NULL);
+        gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+        /* enable SDHI1 on CN4 [WLAN I/F] */
+        gpio_request(GPIO_FN_SDHICLK1, NULL);
+        gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
+        gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
+        gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
+        gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
+        gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
+        gpio_request(GPIO_PORT114, "sdhi1_power");
+        gpio_direction_output(GPIO_PORT114, 0);
+
 #ifdef CONFIG_CACHE_L2X0
         /* Shared attribute override enable, 64K*8way */
         l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 1e35fa976d64..08acb6ec8139 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -316,8 +316,16 @@ static struct resource sdhi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = evt2irq(0x0e00) /* SDHI0 */,
-                .flags  = IORESOURCE_IRQ,
+                .start  = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -349,8 +357,16 @@ static struct resource sdhi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = evt2irq(0x0e80),
-                .flags  = IORESOURCE_IRQ,
+                .start  = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
+                .flags  = IORESOURCE_IRQ,
         },
 };
 
@@ -980,11 +996,6 @@ static void __init hdmi_init_pm_clock(void)
                 goto out;
         }
 
-        ret = clk_enable(&sh7372_pllc2_clk);
-        if (ret < 0) {
-                pr_err("Cannot enable pllc2 clock\n");
-                goto out;
-        }
         pr_debug("PLLC2 set frequency %lu\n", rate);
 
         ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -1343,6 +1354,7 @@ static void __init ap4evb_init(void)
 
         hdmi_init_pm_clock();
         fsi_init_pm_clock();
+        sh7372_pm_init();
 }
 
 static void __init ap4evb_timer_init(void)
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index c87a7b7c5832..8e3c5559f27f 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0xe6d50000,
-                .end    = 0xe6d50nff,
+                .end    = 0xe6d500ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7da2ca24229d..448ddbe43335 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -43,6 +43,7 @@
 #include <linux/sh_intc.h>
 #include <linux/tca6416_keypad.h>
 #include <linux/usb/r8a66597.h>
+#include <linux/usb/renesas_usbhs.h>
 
 #include <video/sh_mobile_hdmi.h>
 #include <video/sh_mobile_lcdc.h>
@@ -143,7 +144,30 @@
  * open      | external VBUS | Function
  *
  * *1
- * CN31 is used as Host in Linux.
+ * CN31 is used as
+ * CONFIG_USB_R8A66597_HCD      Host
+ * CONFIG_USB_RENESAS_USBHS     Function
+ *
+ * CAUTION
+ *
+ * renesas_usbhs driver can use external interrupt mode
+ * (which come from USB-PHY) or autonomy mode (it use own interrupt)
+ * for detecting connection/disconnection when Function.
+ * USB will be power OFF while it has been disconnecting
+ * if external interrupt mode, and it is always power ON if autonomy mode,
+ *
+ * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
+ * because Touchscreen is using IRQ7-PORT40.
+ * It is impossible to use IRQ7 demux on this board.
+ *
+ * We can use external interrupt mode USB-Function on "USB1".
+ * USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
+ * But don't select both drivers in same time.
+ * These uses same IRQ number for request_irq(), and aren't supporting
+ * IRQF_SHARD / IORESOURCE_IRQ_SHAREABLE.
+ *
+ * Actually these are old/new version of USB driver.
+ * This mean its register will be broken if it supports SHARD IRQ,
  */
 
 /*
@@ -185,6 +209,7 @@
  * FIXME !!
  *
  * gpio_no_direction
+ * gpio_pull_down
  * are quick_hack.
  *
  * current gpio frame work doesn't have
@@ -196,6 +221,16 @@ static void __init gpio_no_direction(u32 addr)
         __raw_writeb(0x00, addr);
 }
 
+static void __init gpio_pull_down(u32 addr)
+{
+        u8 data = __raw_readb(addr);
+
+        data &= 0x0F;
+        data |= 0xA0;
+
+        __raw_writeb(data, addr);
+}
+
 /* MTD */
 static struct mtd_partition nor_flash_partitions[] = {
         {
@@ -458,12 +493,6 @@ static void __init hdmi_init_pm_clock(void)
                 goto out;
         }
 
-        ret = clk_enable(&sh7372_pllc2_clk);
-        if (ret < 0) {
-                pr_err("Cannot enable pllc2 clock\n");
-                goto out;
-        }
-
         pr_debug("PLLC2 set frequency %lu\n", rate);
 
         ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -515,6 +544,157 @@ static struct platform_device usb1_host_device = {
         .resource       = usb1_host_resources,
 };
 
+/* USB1 (Function) */
+#define USB_PHY_MODE            (1 << 4)
+#define USB_PHY_INT_EN          ((1 << 3) | (1 << 2))
+#define USB_PHY_ON              (1 << 1)
+#define USB_PHY_OFF             (1 << 0)
+#define USB_PHY_INT_CLR         (USB_PHY_ON | USB_PHY_OFF)
+
+struct usbhs_private {
+        unsigned int irq;
+        unsigned int usbphyaddr;
+        unsigned int usbcrcaddr;
+        struct renesas_usbhs_platform_info info;
+};
+
+#define usbhs_get_priv(pdev)                            \
+        container_of(renesas_usbhs_get_info(pdev),      \
+                     struct usbhs_private, info)
+
+#define usbhs_is_connected(priv)                        \
+        (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
+
+static int usbhs1_get_id(struct platform_device *pdev)
+{
+        return USBHS_GADGET;
+}
+
+static int usbhs1_get_vbus(struct platform_device *pdev)
+{
+        return usbhs_is_connected(usbhs_get_priv(pdev));
+}
+
+static irqreturn_t usbhs1_interrupt(int irq, void *data)
+{
+        struct platform_device *pdev = data;
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        dev_dbg(&pdev->dev, "%s\n", __func__);
+
+        renesas_usbhs_call_notify_hotplug(pdev);
+
+        /* clear status */
+        __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
+                     priv->usbphyaddr);
+
+        return IRQ_HANDLED;
+}
+
+static int usbhs1_hardware_init(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+        int ret;
+
+        irq_set_irq_type(priv->irq, IRQ_TYPE_LEVEL_HIGH);
+
+        /* clear interrupt status */
+        __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
+
+        ret = request_irq(priv->irq, usbhs1_interrupt, 0,
+                          dev_name(&pdev->dev), pdev);
+        if (ret) {
+                dev_err(&pdev->dev, "request_irq err\n");
+                return ret;
+        }
+
+        /* enable USB phy interrupt */
+        __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
+
+        return 0;
+}
+
+static void usbhs1_hardware_exit(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        /* clear interrupt status */
+        __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
+
+        free_irq(priv->irq, pdev);
+}
+
+static void usbhs1_phy_reset(struct platform_device *pdev)
+{
+        struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+        /* init phy */
+        __raw_writew(0x8a0a, priv->usbcrcaddr);
+}
+
+static u32 usbhs1_pipe_cfg[] = {
+        USB_ENDPOINT_XFER_CONTROL,
+        USB_ENDPOINT_XFER_ISOC,
+        USB_ENDPOINT_XFER_ISOC,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_INT,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+        USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usbhs_private usbhs1_private = {
+        .irq            = evt2irq(0x0300),      /* IRQ8 */
+        .usbphyaddr     = 0xE60581E2,           /* USBPHY1INTAP */
+        .usbcrcaddr     = 0xE6058130,           /* USBCR4 */
+        .info = {
+                .platform_callback = {
+                        .hardware_init  = usbhs1_hardware_init,
+                        .hardware_exit  = usbhs1_hardware_exit,
+                        .phy_reset      = usbhs1_phy_reset,
+                        .get_id         = usbhs1_get_id,
+                        .get_vbus       = usbhs1_get_vbus,
+                },
+                .driver_param = {
+                        .buswait_bwait  = 4,
+                        .pipe_type      = usbhs1_pipe_cfg,
+                        .pipe_size      = ARRAY_SIZE(usbhs1_pipe_cfg),
+                },
+        },
+};
+
+static struct resource usbhs1_resources[] = {
+        [0] = {
+                .name   = "USBHS",
+                .start  = 0xE68B0000,
+                .end    = 0xE68B00E6 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device usbhs1_device = {
+        .name   = "renesas_usbhs",
+        .id     = 1,
+        .dev = {
+                .platform_data          = &usbhs1_private.info,
+        },
+        .num_resources  = ARRAY_SIZE(usbhs1_resources),
+        .resource       = usbhs1_resources,
+};
+
+
 /* LED */
 static struct gpio_led mackerel_leds[] = {
         {
@@ -690,7 +870,15 @@ static struct resource sdhi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = evt2irq(0x0e00) /* SDHI0 */,
+                .start  = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -705,7 +893,7 @@ static struct platform_device sdhi0_device = {
         },
 };
 
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
 /* SDHI1 */
 static struct sh_mobile_sdhi_info sdhi1_info = {
         .dma_slave_tx   = SHDMA_SLAVE_SDHI1_TX,
@@ -725,7 +913,15 @@ static struct resource sdhi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = evt2irq(0x0e80),
+                .start  = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -768,7 +964,15 @@ static struct resource sdhi2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = evt2irq(0x1200),
+                .start  = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -803,6 +1007,15 @@ static struct resource sh_mmcif_resources[] = {
         },
 };
 
+static struct sh_mmcif_dma sh_mmcif_dma = {
+        .chan_priv_rx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+        },
+        .chan_priv_tx   = {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+        },
+};
+
 static struct sh_mmcif_plat_data sh_mmcif_plat = {
         .sup_pclk       = 0,
         .ocr            = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -810,6 +1023,7 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
                           MMC_CAP_8_BIT_DATA |
                           MMC_CAP_NEEDS_POLL,
         .get_cd         = slot_cn7_get_cd,
+        .dma            = &sh_mmcif_dma,
 };
 
 static struct platform_device sh_mmcif_device = {
@@ -858,37 +1072,23 @@ static struct soc_camera_link camera_link = {
         .priv           = &camera_info,
 };
 
-static void dummy_release(struct device *dev)
+static struct platform_device *camera_device;
+
+static void mackerel_camera_release(struct device *dev)
 {
+        soc_camera_platform_release(&camera_device);
 }
 
-static struct platform_device camera_device = {
-        .name           = "soc_camera_platform",
-        .dev            = {
-                .platform_data  = &camera_info,
-                .release        = dummy_release,
-        },
-};
-
 static int mackerel_camera_add(struct soc_camera_link *icl,
                                struct device *dev)
 {
-        if (icl != &camera_link)
-                return -ENODEV;
-
-        camera_info.dev = dev;
-
-        return platform_device_register(&camera_device);
+        return soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
+                                       mackerel_camera_release, 0);
 }
 
 static void mackerel_camera_del(struct soc_camera_link *icl)
 {
-        if (icl != &camera_link)
-                return;
-
-        platform_device_unregister(&camera_device);
-        memset(&camera_device.dev.kobj, 0,
-               sizeof(camera_device.dev.kobj));
+        soc_camera_platform_del(icl, camera_device, &camera_link);
 }
 
 static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
@@ -935,12 +1135,13 @@ static struct platform_device *mackerel_devices[] __initdata = {
         &smc911x_device,
         &lcdc_device,
         &usb1_host_device,
+        &usbhs1_device,
         &leds_device,
         &fsi_device,
         &fsi_ak4643_device,
         &fsi_hdmi_device,
         &sdhi0_device,
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
         &sdhi1_device,
 #endif
         &sdhi2_device,
@@ -1030,6 +1231,7 @@ static void __init mackerel_map_io(void)
 
 #define GPIO_PORT9CR    0xE6051009
 #define GPIO_PORT10CR   0xE605100A
+#define GPIO_PORT168CR  0xE60520A8
 #define SRCR4           0xe61580bc
 #define USCCR1          0xE6058144
 static void __init mackerel_init(void)
@@ -1088,6 +1290,7 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_OVCN_1_114, NULL);
         gpio_request(GPIO_FN_EXTLP_1,    NULL);
         gpio_request(GPIO_FN_OVCN2_1,    NULL);
+        gpio_pull_down(GPIO_PORT168CR);
 
         /* setup USB phy */
         __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
@@ -1140,7 +1343,7 @@ static void __init mackerel_init(void)
         gpio_request(GPIO_FN_SDHID0_1, NULL);
         gpio_request(GPIO_FN_SDHID0_0, NULL);
 
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
         /* enable SDHI1 */
         gpio_request(GPIO_FN_SDHICMD1, NULL);
         gpio_request(GPIO_FN_SDHICLK1, NULL);
@@ -1216,6 +1419,7 @@ static void __init mackerel_init(void)
         platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
 
         hdmi_init_pm_clock();
+        sh7372_pm_init();
 }
 
 static void __init mackerel_timer_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index e9731b5a73ed..d17eb66f4ac2 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -44,6 +44,11 @@
 #define DSI1PCKCR       0xe6150098
 #define PLLC01CR        0xe6150028
 #define PLLC2CR         0xe615002c
+#define RMSTPCR0        0xe6150110
+#define RMSTPCR1        0xe6150114
+#define RMSTPCR2        0xe6150118
+#define RMSTPCR3        0xe615011c
+#define RMSTPCR4        0xe6150120
 #define SMSTPCR0        0xe6150130
 #define SMSTPCR1        0xe6150134
 #define SMSTPCR2        0xe6150138
@@ -421,9 +426,6 @@ static unsigned long fsidiv_recalc(struct clk *clk)
 
         value = __raw_readl(clk->mapping->base);
 
-        if ((value & 0x3) != 0x3)
-                return 0;
-
         value >>= 16;
         if (value < 2)
                 return 0;
@@ -504,7 +506,7 @@ static struct clk *late_main_clks[] = {
 enum { MSTP001,
        MSTP131, MSTP130,
        MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
-       MSTP118, MSTP117, MSTP116,
+       MSTP118, MSTP117, MSTP116, MSTP113,
        MSTP106, MSTP101, MSTP100,
        MSTP223,
        MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -527,6 +529,7 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
         [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
         [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+        [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
         [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
         [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
         [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
@@ -617,6 +620,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
         CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+        CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
         CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
         CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
         CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
@@ -634,6 +638,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
         CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
         CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
+        CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
@@ -644,6 +649,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
         CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
         CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
+        CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
 
         CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
@@ -655,6 +661,13 @@ void __init sh7372_clock_init(void)
 {
         int k, ret = 0;
 
+        /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
+        __raw_writel(0xe4ef8087, RMSTPCR0);
+        __raw_writel(0xffffffff, RMSTPCR1);
+        __raw_writel(0x37c7f7ff, RMSTPCR2);
+        __raw_writel(0xffffffff, RMSTPCR3);
+        __raw_writel(0xffe0fffd, RMSTPCR4);
+
         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
                 ret = clk_register(main_clks[k]);
 
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7e58904c1c8c..bcacb1e8cf85 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -266,7 +266,8 @@ enum { MSTP001,
         MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
         MSTP219,
         MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
-        MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
+        MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
+        MSTP314, MSTP313, MSTP312, MSTP311,
         MSTP411, MSTP410, MSTP403,
         MSTP_NR };
 
@@ -295,7 +296,11 @@ static struct clk mstp_clks[MSTP_NR] = {
         [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
         [MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
         [MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+        [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
+        [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
+        [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
         [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
+        [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
         [MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
         [MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
         [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
@@ -313,6 +318,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
         CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
         CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+        CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
+        CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
+        CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
         CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
         CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
         CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@@ -341,7 +349,11 @@ static struct clk_lookup lookups[] = {
         CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
         CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
         CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+        CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
         CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
         CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
         CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
@@ -351,6 +363,11 @@ void __init sh73a0_clock_init(void)
 {
         int k, ret = 0;
 
+        /* Set SDHI clocks to a known state */
+        __raw_writel(0x108, SD0CKCR);
+        __raw_writel(0x108, SD1CKCR);
+        __raw_writel(0x108, SD2CKCR);
+
         /* detect main clock parent */
         switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
         case 0:
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
new file mode 100644
index 000000000000..2e44f11f592e
--- /dev/null
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -0,0 +1,92 @@
+/*
+ * CPUIdle support code for SH-Mobile ARM
+ *
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/cpuidle.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static void shmobile_enter_wfi(void)
+{
+        cpu_do_idle();
+}
+
+void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
+        shmobile_enter_wfi, /* regular sleep mode */
+};
+
+static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
+                                  struct cpuidle_state *state)
+{
+        ktime_t before, after;
+        int requested_state = state - &dev->states[0];
+
+        dev->last_state = &dev->states[requested_state];
+        before = ktime_get();
+
+        local_irq_disable();
+        local_fiq_disable();
+
+        shmobile_cpuidle_modes[requested_state]();
+
+        local_irq_enable();
+        local_fiq_enable();
+
+        after = ktime_get();
+        return ktime_to_ns(ktime_sub(after, before)) >> 10;
+}
+
+static struct cpuidle_device shmobile_cpuidle_dev;
+static struct cpuidle_driver shmobile_cpuidle_driver = {
+        .name =         "shmobile_cpuidle",
+        .owner =        THIS_MODULE,
+};
+
+void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
+
+static int shmobile_cpuidle_init(void)
+{
+        struct cpuidle_device *dev = &shmobile_cpuidle_dev;
+        struct cpuidle_state *state;
+        int i;
+
+        cpuidle_register_driver(&shmobile_cpuidle_driver);
+
+        for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
+                dev->states[i].name[0] = '\0';
+                dev->states[i].desc[0] = '\0';
+                dev->states[i].enter = shmobile_cpuidle_enter;
+        }
+
+        i = CPUIDLE_DRIVER_STATE_START;
+
+        state = &dev->states[i++];
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
+        strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
+        state->exit_latency = 1;
+        state->target_residency = 1 * 2;
+        state->power_usage = 3;
+        state->flags = 0;
+        state->flags |= CPUIDLE_FLAG_TIME_VALID;
+
+        dev->safe_state = state;
+        dev->state_count = i;
+
+        if (shmobile_cpuidle_setup)
+                shmobile_cpuidle_setup(dev);
+
+        cpuidle_register_device(dev);
+
+        return 0;
+}
+late_initcall(shmobile_cpuidle_init);
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index d4cec6b4c7d9..26079d933d91 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -24,4 +24,4 @@
         .align  12
 ENTRY(shmobile_secondary_vector)
         ldr     pc, 1f
-1:      .long   secondary_startup - PAGE_OFFSET + PHYS_OFFSET
+1:      .long   secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 013ac0ee8256..06aecb31d9c7 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,10 @@ struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
 extern void shmobile_handle_irq_gic(struct pt_regs *);
+extern struct platform_suspend_ops shmobile_suspend_ops;
+struct cpuidle_device;
+extern void (*shmobile_cpuidle_modes[])(void);
+extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
 
 extern void sh7367_init_irq(void);
 extern void sh7367_add_early_devices(void);
@@ -30,6 +34,9 @@ extern void sh7372_add_early_devices(void);
 extern void sh7372_add_standard_devices(void);
 extern void sh7372_clock_init(void);
 extern void sh7372_pinmux_init(void);
+extern void sh7372_pm_init(void);
+extern void sh7372_cpu_suspend(void);
+extern void sh7372_cpu_resume(void);
 extern struct clk sh7372_extal1_clk;
 extern struct clk sh7372_extal2_clk;
 
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
index 3029aba38688..9f134dfeffdc 100644
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -87,8 +87,7 @@ WAIT 1, 0xFE40009C
 ED 0xFE400354, 0x01AD8002
 
 LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0x11
 EB 0xE6053098, 0xe1
 EW 0xE6C40000, 0x0000
 EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x3000
+EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
index 3029aba38688..9f134dfeffdc 100644
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -87,8 +87,7 @@ WAIT 1, 0xFE40009C
 ED 0xFE400354, 0x01AD8002
 
 LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0x11
 EB 0xE6053098, 0xe1
 EW 0xE6C40000, 0x0000
 EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x3000
+EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 5736efcca60c..df20d7670172 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -435,6 +435,7 @@ enum {
 
 /* DMA slave IDs */
 enum {
+        SHDMA_SLAVE_INVALID,
         SHDMA_SLAVE_SCIF0_TX,
         SHDMA_SLAVE_SCIF0_RX,
         SHDMA_SLAVE_SCIF1_TX,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index ceb2cdc92bf9..216c3d695ef1 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -463,5 +463,35 @@ enum {
         GPIO_FN_FSIAIBT_PU,
         GPIO_FN_FSIAISLD_PU,
 };
+/* DMA slave IDs */
+enum {
+        SHDMA_SLAVE_INVALID,
+        SHDMA_SLAVE_SCIF0_TX,
+        SHDMA_SLAVE_SCIF0_RX,
+        SHDMA_SLAVE_SCIF1_TX,
+        SHDMA_SLAVE_SCIF1_RX,
+        SHDMA_SLAVE_SCIF2_TX,
+        SHDMA_SLAVE_SCIF2_RX,
+        SHDMA_SLAVE_SCIF3_TX,
+        SHDMA_SLAVE_SCIF3_RX,
+        SHDMA_SLAVE_SCIF4_TX,
+        SHDMA_SLAVE_SCIF4_RX,
+        SHDMA_SLAVE_SCIF5_TX,
+        SHDMA_SLAVE_SCIF5_RX,
+        SHDMA_SLAVE_SCIF6_TX,
+        SHDMA_SLAVE_SCIF6_RX,
+        SHDMA_SLAVE_SCIF7_TX,
+        SHDMA_SLAVE_SCIF7_RX,
+        SHDMA_SLAVE_SCIF8_TX,
+        SHDMA_SLAVE_SCIF8_RX,
+        SHDMA_SLAVE_SDHI0_TX,
+        SHDMA_SLAVE_SDHI0_RX,
+        SHDMA_SLAVE_SDHI1_TX,
+        SHDMA_SLAVE_SDHI1_RX,
+        SHDMA_SLAVE_SDHI2_TX,
+        SHDMA_SLAVE_SDHI2_RX,
+        SHDMA_SLAVE_MMCIF_TX,
+        SHDMA_SLAVE_MMCIF_RX,
+};
 
 #endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 7a4960f9c1e3..3b28743c77eb 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -27,8 +27,6 @@
 
 enum {
         UNUSED_INTCA = 0,
-        ENABLED,
-        DISABLED,
 
         /* interrupt sources INTCA */
         IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -49,14 +47,14 @@ enum {
         MSIOF2, MSIOF1,
         SCIFA4, SCIFA5, SCIFB,
         FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
-        SDHI0,
-        SDHI1,
+        SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
+        SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
         IRREM,
         IRDA,
         TPU0,
         TTI20,
         DDM,
-        SDHI2,
+        SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
         RWDT0,
         DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
         DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
@@ -84,7 +82,7 @@ enum {
 
         /* interrupt groups INTCA */
         DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
-        AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
+        AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
 };
 
 static struct intc_vect intca_vectors[] __initdata = {
@@ -125,17 +123,17 @@ static struct intc_vect intca_vectors[] __initdata = {
         INTC_VECT(SCIFB, 0x0d60),
         INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
         INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
-        INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
-        INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
-        INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
-        INTC_VECT(SDHI1, 0x0ec0),
+        INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
+        INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
+        INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
+        INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
         INTC_VECT(IRREM, 0x0f60),
         INTC_VECT(IRDA, 0x0480),
         INTC_VECT(TPU0, 0x04a0),
         INTC_VECT(TTI20, 0x1100),
         INTC_VECT(DDM, 0x1140),
-        INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
-        INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
+        INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
+        INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
         INTC_VECT(RWDT0, 0x1280),
         INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
         INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
@@ -195,6 +193,12 @@ static struct intc_group intca_groups[] __initdata = {
         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
         INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
+        INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
+                   SDHI0_SDHI0I2, SDHI0_SDHI0I3),
+        INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
+                   SDHI1_SDHI1I2),
+        INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
+                   SDHI2_SDHI2I2, SDHI2_SDHI2I3),
         INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
 };
 
@@ -230,10 +234,10 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
           { SCIFB, SCIFA5, SCIFA4, MSIOF1,
             0, 0, MSIOF2, 0 } },
         { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
-          { DISABLED, ENABLED, ENABLED, ENABLED,
+          { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
         { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
-          { 0, ENABLED, ENABLED, ENABLED,
+          { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
             TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
         { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
           { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -248,7 +252,7 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
           { 0, 0, TPU0, 0,
             0, 0, 0, 0 } },
         { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
-          { DISABLED, DISABLED, ENABLED, ENABLED,
+          { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
             0, CMT3, 0, RWDT0 } },
         { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
           { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
@@ -354,14 +358,10 @@ static struct intc_mask_reg intca_ack_registers[] __initdata = {
           { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
 };
 
-static struct intc_desc intca_desc __initdata = {
-        .name = "sh7372-intca",
-        .force_enable = ENABLED,
-        .force_disable = DISABLED,
-        .hw = INTC_HW_DESC(intca_vectors, intca_groups,
-                           intca_mask_registers, intca_prio_registers,
-                           intca_sense_registers, intca_ack_registers),
-};
+static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
+                             intca_vectors, intca_groups,
+                             intca_mask_registers, intca_prio_registers,
+                             intca_sense_registers, intca_ack_registers);
 
 enum {
         UNUSED_INTCS = 0,
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
new file mode 100644
index 000000000000..8e4aadf14c9f
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -0,0 +1,108 @@
+/*
+ * sh7372 Power management support
+ *
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/tlbflush.h>
+#include <mach/common.h>
+
+#define SMFRAM 0xe6a70000
+#define SYSTBCR 0xe6150024
+#define SBAR 0xe6180020
+#define APARMBAREA 0xe6f10020
+
+static void sh7372_enter_core_standby(void)
+{
+        void __iomem *smfram = (void __iomem *)SMFRAM;
+
+        __raw_writel(0, APARMBAREA); /* translate 4k */
+        __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
+        __raw_writel(0x10, SYSTBCR); /* enable core standby */
+
+        __raw_writel(0, smfram + 0x3c); /* clear page table address */
+
+        sh7372_cpu_suspend();
+        cpu_init();
+
+        /* if page table address is non-NULL then we have been powered down */
+        if (__raw_readl(smfram + 0x3c)) {
+                __raw_writel(__raw_readl(smfram + 0x40),
+                             __va(__raw_readl(smfram + 0x3c)));
+
+                flush_tlb_all();
+                set_cr(__raw_readl(smfram + 0x38));
+        }
+
+        __raw_writel(0, SYSTBCR); /* disable core standby */
+        __raw_writel(0, SBAR); /* disable reset vector translation */
+}
+
+#ifdef CONFIG_CPU_IDLE
+static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
+{
+        struct cpuidle_state *state;
+        int i = dev->state_count;
+
+        state = &dev->states[i];
+        snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+        strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
+        state->exit_latency = 10;
+        state->target_residency = 20 + 10;
+        state->power_usage = 1; /* perhaps not */
+        state->flags = 0;
+        state->flags |= CPUIDLE_FLAG_TIME_VALID;
+        shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
+
+        dev->state_count = i + 1;
+}
+
+static void sh7372_cpuidle_init(void)
+{
+        shmobile_cpuidle_setup = sh7372_cpuidle_setup;
+}
+#else
+static void sh7372_cpuidle_init(void) {}
+#endif
+
+#ifdef CONFIG_SUSPEND
+static int sh7372_enter_suspend(suspend_state_t suspend_state)
+{
+        sh7372_enter_core_standby();
+        return 0;
+}
+
+static void sh7372_suspend_init(void)
+{
+        shmobile_suspend_ops.enter = sh7372_enter_suspend;
+}
+#else
+static void sh7372_suspend_init(void) {}
+#endif
+
+#define DBGREG1 0xe6100020
+#define DBGREG9 0xe6100040
+
+void __init sh7372_pm_init(void)
+{
+        /* enable DBG hardware block to kick SYSC */
+        __raw_writel(0x0000a500, DBGREG9);
+        __raw_writel(0x0000a501, DBGREG9);
+        __raw_writel(0x00000000, DBGREG1);
+
+        sh7372_suspend_init();
+        sh7372_cpuidle_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index ce28141662da..2c10190dbb55 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -195,6 +196,214 @@ static struct platform_device cmt10_device = {
         .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
 
+/* VPU */
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5",
+        .version = "0",
+        .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe902807,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+        .name = "VEU0",
+        .version = "0",
+        .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU0",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200b7,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+        .name = "VEU1",
+        .version = "0",
+        .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU1",
+                .start  = 0xfe924000,
+                .end    = 0xfe9240b7,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+        .name = "VEU2",
+        .version = "0",
+        .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+        [0] = {
+                .name   = "VEU2",
+                .start  = 0xfe928000,
+                .end    = 0xfe9280b7,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu2_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &veu2_platform_data,
+        },
+        .resource       = veu2_resources,
+        .num_resources  = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+        .name = "VEU3",
+        .version = "0",
+        .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+        [0] = {
+                .name   = "VEU3",
+                .start  = 0xfe92c000,
+                .end    = 0xfe92c0b7,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu3_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &veu3_platform_data,
+        },
+        .resource       = veu3_resources,
+        .num_resources  = ARRAY_SIZE(veu3_resources),
+};
+
+/* VEU2H */
+static struct uio_info veu2h_platform_data = {
+        .name = "VEU2H",
+        .version = "0",
+        .irq = intcs_evt2irq(0x520),
+};
+
+static struct resource veu2h_resources[] = {
+        [0] = {
+                .name   = "VEU2H",
+                .start  = 0xfe93c000,
+                .end    = 0xfe93c27b,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu2h_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &veu2h_platform_data,
+        },
+        .resource       = veu2h_resources,
+        .num_resources  = ARRAY_SIZE(veu2h_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+        .name = "JPU",
+        .version = "0",
+        .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+        [0] = {
+                .name   = "JPU",
+                .start  = 0xfe980000,
+                .end    = 0xfe9902d3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device jpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &jpu_platform_data,
+        },
+        .resource       = jpu_resources,
+        .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU1 */
+static struct uio_info spu1_platform_data = {
+        .name = "SPU1",
+        .version = "0",
+        .irq = evt2irq(0xfc0),
+};
+
+static struct resource spu1_resources[] = {
+        [0] = {
+                .name   = "SPU1",
+                .start  = 0xfe300000,
+                .end    = 0xfe3fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device spu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &spu1_platform_data,
+        },
+        .resource       = spu1_resources,
+        .num_resources  = ARRAY_SIZE(spu1_resources),
+};
+
 static struct platform_device *sh7367_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -206,10 +415,24 @@ static struct platform_device *sh7367_early_devices[] __initdata = {
         &cmt10_device,
 };
 
+static struct platform_device *sh7367_devices[] __initdata = {
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
+        &veu2_device,
+        &veu3_device,
+        &veu2h_device,
+        &jpu_device,
+        &spu1_device,
+};
+
 void __init sh7367_add_standard_devices(void)
 {
         platform_add_devices(sh7367_early_devices,
                              ARRAY_SIZE(sh7367_early_devices));
+
+        platform_add_devices(sh7367_devices,
+                            ARRAY_SIZE(sh7367_devices));
 }
 
 #define SYMSTPCR2 0xe6158048
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index ff0494f3d00c..cd807eea69e2 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -601,6 +602,214 @@ static struct platform_device dma2_device = {
         },
 };
 
+/* VPU */
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5HG",
+        .version = "0",
+        .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe900157,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+        .name = "VEU0",
+        .version = "0",
+        .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU0",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200cb,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+        .name = "VEU1",
+        .version = "0",
+        .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU1",
+                .start  = 0xfe924000,
+                .end    = 0xfe9240cb,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+        .name = "VEU2",
+        .version = "0",
+        .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+        [0] = {
+                .name   = "VEU2",
+                .start  = 0xfe928000,
+                .end    = 0xfe928307,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu2_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &veu2_platform_data,
+        },
+        .resource       = veu2_resources,
+        .num_resources  = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+        .name = "VEU3",
+        .version = "0",
+        .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+        [0] = {
+                .name   = "VEU3",
+                .start  = 0xfe92c000,
+                .end    = 0xfe92c307,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu3_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &veu3_platform_data,
+        },
+        .resource       = veu3_resources,
+        .num_resources  = ARRAY_SIZE(veu3_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+        .name = "JPU",
+        .version = "0",
+        .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+        [0] = {
+                .name   = "JPU",
+                .start  = 0xfe980000,
+                .end    = 0xfe9902d3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device jpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &jpu_platform_data,
+        },
+        .resource       = jpu_resources,
+        .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+        .name = "SPU2DSP0",
+        .version = "0",
+        .irq = evt2irq(0x1800),
+};
+
+static struct resource spu0_resources[] = {
+        [0] = {
+                .name   = "SPU2DSP0",
+                .start  = 0xfe200000,
+                .end    = 0xfe2fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device spu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &spu0_platform_data,
+        },
+        .resource       = spu0_resources,
+        .num_resources  = ARRAY_SIZE(spu0_resources),
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+        .name = "SPU2DSP1",
+        .version = "0",
+        .irq = evt2irq(0x1820),
+};
+
+static struct resource spu1_resources[] = {
+        [0] = {
+                .name   = "SPU2DSP1",
+                .start  = 0xfe300000,
+                .end    = 0xfe3fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device spu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &spu1_platform_data,
+        },
+        .resource       = spu1_resources,
+        .num_resources  = ARRAY_SIZE(spu1_resources),
+};
+
 static struct platform_device *sh7372_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -620,6 +829,14 @@ static struct platform_device *sh7372_late_devices[] __initdata = {
         &dma0_device,
         &dma1_device,
         &dma2_device,
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
+        &veu2_device,
+        &veu3_device,
+        &jpu_device,
+        &spu0_device,
+        &spu1_device,
 };
 
 void __init sh7372_add_standard_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 8099b0b8a934..bb405b8e459b 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -22,6 +22,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/uio_driver.h>
 #include <linux/delay.h>
 #include <linux/input.h>
 #include <linux/io.h>
@@ -38,7 +39,7 @@ static struct plat_sci_port scif0_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { evt2irq(0xc00), evt2irq(0xc00),
                             evt2irq(0xc00), evt2irq(0xc00) },
 };
@@ -57,7 +58,7 @@ static struct plat_sci_port scif1_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { evt2irq(0xc20), evt2irq(0xc20),
                             evt2irq(0xc20), evt2irq(0xc20) },
 };
@@ -76,7 +77,7 @@ static struct plat_sci_port scif2_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { evt2irq(0xc40), evt2irq(0xc40),
                             evt2irq(0xc40), evt2irq(0xc40) },
 };
@@ -95,7 +96,7 @@ static struct plat_sci_port scif3_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { evt2irq(0xc60), evt2irq(0xc60),
                             evt2irq(0xc60), evt2irq(0xc60) },
 };
@@ -114,7 +115,7 @@ static struct plat_sci_port scif4_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { evt2irq(0xd20), evt2irq(0xd20),
                             evt2irq(0xd20), evt2irq(0xd20) },
 };
@@ -133,7 +134,7 @@ static struct plat_sci_port scif5_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { evt2irq(0xd40), evt2irq(0xd40),
                             evt2irq(0xd40), evt2irq(0xd40) },
 };
@@ -152,7 +153,7 @@ static struct plat_sci_port scif6_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFA,
         .irqs           = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
                             intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
 };
@@ -171,7 +172,7 @@ static struct plat_sci_port scif7_platform_data = {
         .flags          = UPF_BOOT_AUTOCONF,
         .scscr          = SCSCR_RE | SCSCR_TE,
         .scbrr_algo_id  = SCBRR_ALGO_4,
-        .type           = PORT_SCIF,
+        .type           = PORT_SCIFB,
         .irqs           = { evt2irq(0xd60), evt2irq(0xd60),
                             evt2irq(0xd60), evt2irq(0xd60) },
 };
@@ -215,6 +216,214 @@ static struct platform_device cmt10_device = {
         .num_resources  = ARRAY_SIZE(cmt10_resources),
 };
 
+/* VPU */
+static struct uio_info vpu_platform_data = {
+        .name = "VPU5HG",
+        .version = "0",
+        .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+        [0] = {
+                .name   = "VPU",
+                .start  = 0xfe900000,
+                .end    = 0xfe900157,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device vpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &vpu_platform_data,
+        },
+        .resource       = vpu_resources,
+        .num_resources  = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+        .name = "VEU0",
+        .version = "0",
+        .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+        [0] = {
+                .name   = "VEU0",
+                .start  = 0xfe920000,
+                .end    = 0xfe9200cb,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &veu0_platform_data,
+        },
+        .resource       = veu0_resources,
+        .num_resources  = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+        .name = "VEU1",
+        .version = "0",
+        .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+        [0] = {
+                .name   = "VEU1",
+                .start  = 0xfe924000,
+                .end    = 0xfe9240cb,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 2,
+        .dev = {
+                .platform_data  = &veu1_platform_data,
+        },
+        .resource       = veu1_resources,
+        .num_resources  = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+        .name = "VEU2",
+        .version = "0",
+        .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+        [0] = {
+                .name   = "VEU2",
+                .start  = 0xfe928000,
+                .end    = 0xfe928307,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu2_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 3,
+        .dev = {
+                .platform_data  = &veu2_platform_data,
+        },
+        .resource       = veu2_resources,
+        .num_resources  = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+        .name = "VEU3",
+        .version = "0",
+        .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+        [0] = {
+                .name   = "VEU3",
+                .start  = 0xfe92c000,
+                .end    = 0xfe92c307,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device veu3_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 4,
+        .dev = {
+                .platform_data  = &veu3_platform_data,
+        },
+        .resource       = veu3_resources,
+        .num_resources  = ARRAY_SIZE(veu3_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+        .name = "JPU",
+        .version = "0",
+        .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+        [0] = {
+                .name   = "JPU",
+                .start  = 0xfe980000,
+                .end    = 0xfe9902d3,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device jpu_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 5,
+        .dev = {
+                .platform_data  = &jpu_platform_data,
+        },
+        .resource       = jpu_resources,
+        .num_resources  = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+        .name = "SPU2DSP0",
+        .version = "0",
+        .irq = evt2irq(0x1800),
+};
+
+static struct resource spu0_resources[] = {
+        [0] = {
+                .name   = "SPU2DSP0",
+                .start  = 0xfe200000,
+                .end    = 0xfe2fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device spu0_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 6,
+        .dev = {
+                .platform_data  = &spu0_platform_data,
+        },
+        .resource       = spu0_resources,
+        .num_resources  = ARRAY_SIZE(spu0_resources),
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+        .name = "SPU2DSP1",
+        .version = "0",
+        .irq = evt2irq(0x1820),
+};
+
+static struct resource spu1_resources[] = {
+        [0] = {
+                .name   = "SPU2DSP1",
+                .start  = 0xfe300000,
+                .end    = 0xfe3fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device spu1_device = {
+        .name           = "uio_pdrv_genirq",
+        .id             = 7,
+        .dev = {
+                .platform_data  = &spu1_platform_data,
+        },
+        .resource       = spu1_resources,
+        .num_resources  = ARRAY_SIZE(spu1_resources),
+};
+
 static struct platform_device *sh7377_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -227,10 +436,24 @@ static struct platform_device *sh7377_early_devices[] __initdata = {
         &cmt10_device,
 };
 
+static struct platform_device *sh7377_devices[] __initdata = {
+        &vpu_device,
+        &veu0_device,
+        &veu1_device,
+        &veu2_device,
+        &veu3_device,
+        &jpu_device,
+        &spu0_device,
+        &spu1_device,
+};
+
 void __init sh7377_add_standard_devices(void)
 {
         platform_add_devices(sh7377_early_devices,
                             ARRAY_SIZE(sh7377_early_devices));
+
+        platform_add_devices(sh7377_devices,
+                            ARRAY_SIZE(sh7377_devices));
 }
 
 #define SMSTPCR3 0xe615013c
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 685c40a2f5e6..e46821c0a62e 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -27,9 +27,11 @@
 #include <linux/input.h>
 #include <linux/io.h>
 #include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
 #include <linux/sh_intc.h>
 #include <linux/sh_timer.h>
 #include <mach/hardware.h>
+#include <mach/sh73a0.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
@@ -392,6 +394,242 @@ static struct platform_device i2c4_device = {
         .num_resources  = ARRAY_SIZE(i2c4_resources),
 };
 
+/* Transmit sizes and respective CHCR register values */
+enum {
+        XMIT_SZ_8BIT            = 0,
+        XMIT_SZ_16BIT           = 1,
+        XMIT_SZ_32BIT           = 2,
+        XMIT_SZ_64BIT           = 7,
+        XMIT_SZ_128BIT          = 3,
+        XMIT_SZ_256BIT          = 4,
+        XMIT_SZ_512BIT          = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT {                      \
+        [XMIT_SZ_8BIT]          = 0,    \
+        [XMIT_SZ_16BIT]         = 1,    \
+        [XMIT_SZ_32BIT]         = 2,    \
+        [XMIT_SZ_64BIT]         = 3,    \
+        [XMIT_SZ_128BIT]        = 4,    \
+        [XMIT_SZ_256BIT]        = 5,    \
+        [XMIT_SZ_512BIT]        = 6,    \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+
+static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
+        {
+                .slave_id       = SHDMA_SLAVE_SCIF0_TX,
+                .addr           = 0xe6c40020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x21,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF0_RX,
+                .addr           = 0xe6c40024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x22,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_TX,
+                .addr           = 0xe6c50020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x25,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF1_RX,
+                .addr           = 0xe6c50024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x26,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_TX,
+                .addr           = 0xe6c60020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x29,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF2_RX,
+                .addr           = 0xe6c60024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2a,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF3_TX,
+                .addr           = 0xe6c70020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2d,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF3_RX,
+                .addr           = 0xe6c70024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x2e,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF4_TX,
+                .addr           = 0xe6c80020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x39,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF4_RX,
+                .addr           = 0xe6c80024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x3a,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF5_TX,
+                .addr           = 0xe6cb0020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x35,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF5_RX,
+                .addr           = 0xe6cb0024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x36,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF6_TX,
+                .addr           = 0xe6cc0020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x1d,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF6_RX,
+                .addr           = 0xe6cc0024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x1e,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF7_TX,
+                .addr           = 0xe6cd0020,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x19,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF7_RX,
+                .addr           = 0xe6cd0024,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x1a,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF8_TX,
+                .addr           = 0xe6c30040,
+                .chcr           = CHCR_TX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x3d,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SCIF8_RX,
+                .addr           = 0xe6c30060,
+                .chcr           = CHCR_RX(XMIT_SZ_8BIT),
+                .mid_rid        = 0x3e,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_TX,
+                .addr           = 0xee100030,
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI0_RX,
+                .addr           = 0xee100030,
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc2,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_TX,
+                .addr           = 0xee120030,
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xc9,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI1_RX,
+                .addr           = 0xee120030,
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xca,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI2_TX,
+                .addr           = 0xee140030,
+                .chcr           = CHCR_TX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xcd,
+        }, {
+                .slave_id       = SHDMA_SLAVE_SDHI2_RX,
+                .addr           = 0xee140030,
+                .chcr           = CHCR_RX(XMIT_SZ_16BIT),
+                .mid_rid        = 0xce,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_TX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_TX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd1,
+        }, {
+                .slave_id       = SHDMA_SLAVE_MMCIF_RX,
+                .addr           = 0xe6bd0034,
+                .chcr           = CHCR_RX(XMIT_SZ_32BIT),
+                .mid_rid        = 0xd2,
+        },
+};
+
+#define DMAE_CHANNEL(_offset)                                   \
+        {                                                       \
+                .offset         = _offset - 0x20,               \
+                .dmars          = _offset - 0x20 + 0x40,        \
+        }
+
+static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
+        DMAE_CHANNEL(0x8000),
+        DMAE_CHANNEL(0x8080),
+        DMAE_CHANNEL(0x8100),
+        DMAE_CHANNEL(0x8180),
+        DMAE_CHANNEL(0x8200),
+        DMAE_CHANNEL(0x8280),
+        DMAE_CHANNEL(0x8300),
+        DMAE_CHANNEL(0x8380),
+        DMAE_CHANNEL(0x8400),
+        DMAE_CHANNEL(0x8480),
+        DMAE_CHANNEL(0x8500),
+        DMAE_CHANNEL(0x8580),
+        DMAE_CHANNEL(0x8600),
+        DMAE_CHANNEL(0x8680),
+        DMAE_CHANNEL(0x8700),
+        DMAE_CHANNEL(0x8780),
+        DMAE_CHANNEL(0x8800),
+        DMAE_CHANNEL(0x8880),
+        DMAE_CHANNEL(0x8900),
+        DMAE_CHANNEL(0x8980),
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
+        .slave          = sh73a0_dmae_slaves,
+        .slave_num      = ARRAY_SIZE(sh73a0_dmae_slaves),
+        .channel        = sh73a0_dmae_channels,
+        .channel_num    = ARRAY_SIZE(sh73a0_dmae_channels),
+        .ts_low_shift   = 3,
+        .ts_low_mask    = 0x18,
+        .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
+        .ts_high_mask   = 0x00300000,
+        .ts_shift       = ts_shift,
+        .ts_shift_num   = ARRAY_SIZE(ts_shift),
+        .dmaor_init     = DMAOR_DME,
+};
+
+static struct resource sh73a0_dmae_resources[] = {
+        {
+                /* Registers including DMAOR and channels including DMARSx */
+                .start  = 0xfe000020,
+                .end    = 0xfe008a00 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                /* DMA error IRQ */
+                .start  = gic_spi(129),
+                .end    = gic_spi(129),
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                /* IRQ for channels 0-19 */
+                .start  = gic_spi(109),
+                .end    = gic_spi(128),
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dma0_device = {
+        .name           = "sh-dma-engine",
+        .id             = 0,
+        .resource       = sh73a0_dmae_resources,
+        .num_resources  = ARRAY_SIZE(sh73a0_dmae_resources),
+        .dev            = {
+                .platform_data  = &sh73a0_dmae_platform_data,
+        },
+};
+
 static struct platform_device *sh73a0_early_devices[] __initdata = {
         &scif0_device,
         &scif1_device,
@@ -413,10 +651,16 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &i2c2_device,
         &i2c3_device,
         &i2c4_device,
+        &dma0_device,
 };
 
+#define SRCR2          0xe61580b0
+
 void __init sh73a0_add_standard_devices(void)
 {
+        /* Clear software reset bit on SY-DMAC module */
+        __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
+
         platform_add_devices(sh73a0_early_devices,
                             ARRAY_SIZE(sh73a0_early_devices));
         platform_add_devices(sh73a0_late_devices,
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
new file mode 100644
index 000000000000..d37d3ca4d18f
--- /dev/null
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -0,0 +1,260 @@
+/*
+ * sh7372 lowlevel sleep code for "Core Standby Mode"
+ *
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
+ *
+ * Based on mach-omap2/sleep34xx.S
+ *
+ * (C) Copyright 2007 Texas Instruments
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * (C) Copyright 2004 Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#define SMFRAM 0xe6a70000
+
+        .align
+kernel_flush:
+        .word   v7_flush_dcache_all
+
+        .align  3
+ENTRY(sh7372_cpu_suspend)
+        stmfd   sp!, {r0-r12, lr}       @ save registers on stack
+
+        ldr     r8, =SMFRAM
+
+        mov     r4, sp                  @ Store sp
+        mrs     r5, spsr                @ Store spsr
+        mov     r6, lr                  @ Store lr
+        stmia   r8!, {r4-r6}
+
+        mrc     p15, 0, r4, c1, c0, 2   @ Coprocessor access control register
+        mrc     p15, 0, r5, c2, c0, 0   @ TTBR0
+        mrc     p15, 0, r6, c2, c0, 1   @ TTBR1
+        mrc     p15, 0, r7, c2, c0, 2   @ TTBCR
+        stmia   r8!, {r4-r7}
+
+        mrc     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+        mrc     p15, 0, r5, c10, c2, 0  @ PRRR
+        mrc     p15, 0, r6, c10, c2, 1  @ NMRR
+        stmia   r8!,{r4-r6}
+
+        mrc     p15, 0, r4, c13, c0, 1  @ Context ID
+        mrc     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+        mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+        mrs     r7, cpsr                @ Store current cpsr
+        stmia   r8!, {r4-r7}
+
+        mrc     p15, 0, r4, c1, c0, 0   @ save control register
+        stmia   r8!, {r4}
+
+        /*
+         * jump out to kernel flush routine
+         *  - reuse that code is better
+         *  - it executes in a cached space so is faster than refetch per-block
+         *  - should be faster and will change with kernel
+         *  - 'might' have to copy address, load and jump to it
+         * Flush all data from the L1 data cache before disabling
+         * SCTLR.C bit.
+         */
+        ldr     r1, kernel_flush
+        mov     lr, pc
+        bx      r1
+
+        /*
+         * Clear the SCTLR.C bit to prevent further data cache
+         * allocation. Clearing SCTLR.C would make all the data accesses
+         * strongly ordered and would not hit the cache.
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        bic     r0, r0, #(1 << 2)       @ Disable the C bit
+        mcr     p15, 0, r0, c1, c0, 0
+        isb
+
+        /*
+         * Invalidate L1 data cache. Even though only invalidate is
+         * necessary exported flush API is used here. Doing clean
+         * on already clean cache would be almost NOP.
+         */
+        ldr     r1, kernel_flush
+        blx     r1
+        /*
+         * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+         * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+         * This sequence switches back to ARM.  Note that .align may insert a
+         * nop: bx pc needs to be word-aligned in order to work.
+         */
+ THUMB( .thumb          )
+ THUMB( .align          )
+ THUMB( bx      pc      )
+ THUMB( nop             )
+        .arm
+
+        /* Data memory barrier and Data sync barrier */
+        dsb
+        dmb
+
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
+        wfi                             @ wait for interrupt
+
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
+        mrc     p15, 0, r0, c1, c0, 0
+        tst     r0, #(1 << 2)           @ Check C bit enabled?
+        orreq   r0, r0, #(1 << 2)       @ Enable the C bit if cleared
+        mcreq   p15, 0, r0, c1, c0, 0
+        isb
+
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
+
+        .pool
+
+        .align  12
+        .text
+        .global sh7372_cpu_resume
+sh7372_cpu_resume:
+
+        mov     r1, #0
+        /*
+         * Invalidate all instruction caches to PoU
+         * and flush branch target cache
+         */
+        mcr     p15, 0, r1, c7, c5, 0
+
+        ldr     r3, =SMFRAM
+
+        ldmia   r3!, {r4-r6}
+        mov     sp, r4                  @ Restore sp
+        msr     spsr_cxsf, r5           @ Restore spsr
+        mov     lr, r6                  @ Restore lr
+
+        ldmia   r3!, {r4-r7}
+        mcr     p15, 0, r4, c1, c0, 2   @ Coprocessor access Control Register
+        mcr     p15, 0, r5, c2, c0, 0   @ TTBR0
+        mcr     p15, 0, r6, c2, c0, 1   @ TTBR1
+        mcr     p15, 0, r7, c2, c0, 2   @ TTBCR
+
+        ldmia   r3!,{r4-r6}
+        mcr     p15, 0, r4, c3, c0, 0   @ Domain access Control Register
+        mcr     p15, 0, r5, c10, c2, 0  @ PRRR
+        mcr     p15, 0, r6, c10, c2, 1  @ NMRR
+
+        ldmia   r3!,{r4-r7}
+        mcr     p15, 0, r4, c13, c0, 1  @ Context ID
+        mcr     p15, 0, r5, c13, c0, 2  @ User r/w thread and process ID
+        mrc     p15, 0, r6, c12, c0, 0  @ Secure or NS vector base address
+        msr     cpsr, r7                @ store cpsr
+
+        /* Starting to enable MMU here */
+        mrc     p15, 0, r7, c2, c0, 2   @ Read TTBRControl
+        /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
+        and     r7, #0x7
+        cmp     r7, #0x0
+        beq     usettbr0
+ttbr_error:
+        /*
+         * More work needs to be done to support N[0:2] value other than 0
+         * So looping here so that the error can be detected
+         */
+        b       ttbr_error
+
+        .align
+cache_pred_disable_mask:
+        .word   0xFFFFE7FB
+ttbrbit_mask:
+        .word   0xFFFFC000
+table_index_mask:
+        .word   0xFFF00000
+table_entry:
+        .word   0x00000C02
+usettbr0:
+
+        mrc     p15, 0, r2, c2, c0, 0
+        ldr     r5, ttbrbit_mask
+        and     r2, r5
+        mov     r4, pc
+        ldr     r5, table_index_mask
+        and     r4, r5                  @ r4 = 31 to 20 bits of pc
+        /* Extract the value to be written to table entry */
+        ldr     r6, table_entry
+        /* r6 has the value to be written to table entry */
+        add     r6, r6, r4
+        /* Getting the address of table entry to modify */
+        lsr     r4, #18
+        /* r2 has the location which needs to be modified */
+        add     r2, r4
+        ldr     r4, [r2]
+        str     r6, [r2] /* modify the table entry */
+
+        mov     r7, r6
+        mov     r5, r2
+        mov     r6, r4
+        /* r5 = original page table address */
+        /* r6 = original page table data */
+
+        mov     r0, #0
+        mcr     p15, 0, r0, c7, c5, 4   @ Flush prefetch buffer
+        mcr     p15, 0, r0, c7, c5, 6   @ Invalidate branch predictor array
+        mcr     p15, 0, r0, c8, c5, 0   @ Invalidate instruction TLB
+        mcr     p15, 0, r0, c8, c6, 0   @ Invalidate data TLB
+
+        /*
+         * Restore control register. This enables the MMU.
+         * The caches and prediction are not enabled here, they
+         * will be enabled after restoring the MMU table entry.
+         */
+        ldmia   r3!, {r4}
+        stmia   r3!, {r5} /* save original page table address */
+        stmia   r3!, {r6} /* save original page table data */
+        stmia   r3!, {r7} /* save modified page table data */
+
+        ldr     r2, cache_pred_disable_mask
+        and     r4, r2
+        mcr     p15, 0, r4, c1, c0, 0
+        dsb
+        isb
+
+        ldr     r0, =restoremmu_on
+        bx      r0
+
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
+restoremmu_on:
+
+        ldmfd   sp!, {r0-r12, pc}       @ restore regs and return
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index a156d2108df1..3ffdbc92ba82 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -59,6 +59,11 @@ unsigned int __init sh73a0_get_core_count(void)
 {
         void __iomem *scu_base = scu_base_addr();
 
+#ifdef CONFIG_HAVE_ARM_TWD
+        /* twd_base needs to be initialized before percpu_timer_setup() */
+        twd_base = (void __iomem *)0xf0000600;
+#endif
+
         return scu_get_core_count(scu_base);
 }
 
@@ -82,10 +87,6 @@ int __cpuinit sh73a0_boot_secondary(unsigned int cpu)
 
 void __init sh73a0_smp_prepare_cpus(void)
 {
-#ifdef CONFIG_HAVE_ARM_TWD
-        twd_base = (void __iomem *)0xf0000600;
-#endif
-
         scu_enable(scu_base_addr());
 
         /* Map the reset vector (in headsmp.S) */
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
new file mode 100644
index 000000000000..c1febe13f709
--- /dev/null
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -0,0 +1,47 @@
+/*
+ * Suspend-to-RAM support code for SH-Mobile ARM
+ *
+ *  Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
+{
+        cpu_do_idle();
+        return 0;
+}
+
+static int shmobile_suspend_begin(suspend_state_t state)
+{
+        disable_hlt();
+        return 0;
+}
+
+static void shmobile_suspend_end(void)
+{
+        enable_hlt();
+}
+
+struct platform_suspend_ops shmobile_suspend_ops = {
+        .begin          = shmobile_suspend_begin,
+        .end            = shmobile_suspend_end,
+        .enter          = shmobile_suspend_default_enter,
+        .valid          = suspend_valid_only_mem,
+};
+
+static int __init shmobile_suspend_init(void)
+{
+        suspend_set_ops(&shmobile_suspend_ops);
+        return 0;
+}
+late_initcall(shmobile_suspend_init);
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 04c779832c78..4f3572a1c684 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -50,13 +50,11 @@ struct tegra_kbc_platform_data {
         unsigned int debounce_cnt;
         unsigned int repeat_cnt;
 
-        unsigned int wake_cnt; /* 0:wake on any key >1:wake on wake_cfg */
-        const struct tegra_kbc_wake_key *wake_cfg;
-
         struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
         const struct matrix_keymap_data *keymap_data;
 
         bool wakeup;
         bool use_fn_map;
+        bool use_ghost_filter;
 };
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
index 3ad086e859c3..4231bc7b8652 100644
--- a/arch/arm/mach-tegra/include/mach/sdhci.h
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -24,6 +24,7 @@ struct tegra_sdhci_platform_data {
         int wp_gpio;
         int power_gpio;
         int is_8bit;
+        int pm_flags;
 };
 
 #endif
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index fab46fe9a71f..8fd354aaf0a7 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux kernel, U300 machine.
 #
 
-obj-y           := core.o clock.o timer.o gpio.o padmux.o
+obj-y           := core.o clock.o timer.o padmux.o
 obj-m           :=
 obj-n           :=
 obj-            :=
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
deleted file mode 100644
index d92790140fe5..000000000000
--- a/arch/arm/mach-u300/gpio.c
+++ /dev/null
@@ -1,700 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/gpio.c
- *
- *
- * Copyright (C) 2007-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * U300 GPIO module.
- * This can driver either of the two basic GPIO cores
- * available in the U300 platforms:
- * COH 901 335   - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
- * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
- * Notice that you also have inline macros in <asm-arch/gpio.h>
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- *
- */
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-
-/* Reference to GPIO block clock */
-static struct clk *clk;
-
-/* Memory resource */
-static struct resource *memres;
-static void __iomem *virtbase;
-static struct device *gpiodev;
-
-struct u300_gpio_port {
-        const char *name;
-        int irq;
-        int number;
-};
-
-
-static struct u300_gpio_port gpio_ports[] = {
-        {
-                .name = "gpio0",
-                .number = 0,
-        },
-        {
-                .name = "gpio1",
-                .number = 1,
-        },
-        {
-                .name = "gpio2",
-                .number = 2,
-        },
-#ifdef U300_COH901571_3
-        {
-                .name = "gpio3",
-                .number = 3,
-        },
-        {
-                .name = "gpio4",
-                .number = 4,
-        },
-#ifdef CONFIG_MACH_U300_BS335
-        {
-                .name = "gpio5",
-                .number = 5,
-        },
-        {
-                .name = "gpio6",
-                .number = 6,
-        },
-#endif
-#endif
-
-};
-
-
-#ifdef U300_COH901571_3
-
-/* Default input value */
-#define DEFAULT_OUTPUT_LOW   0
-#define DEFAULT_OUTPUT_HIGH  1
-
-/* GPIO Pull-Up status */
-#define DISABLE_PULL_UP  0
-#define ENABLE_PULL_UP  1
-
-#define GPIO_NOT_USED 0
-#define GPIO_IN       1
-#define GPIO_OUT      2
-
-struct u300_gpio_configuration_data {
-        unsigned char pin_usage;
-        unsigned char default_output_value;
-        unsigned char pull_up;
-};
-
-/* Initial configuration */
-const struct u300_gpio_configuration_data
-u300_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
-#ifdef CONFIG_MACH_U300_BS335
-        /* Port 0, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_HIGH,  DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 1, pins 0-7 */
-        {
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_HIGH,  DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 2, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
-        },
-        /* Port 3, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 4, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 5, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 6, pind 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        }
-#endif
-
-#ifdef CONFIG_MACH_U300_BS365
-        /* Port 0, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 1, pins 0-7 */
-        {
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_HIGH,  DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP}
-        },
-        /* Port 2, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,   DISABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
-        },
-        /* Port 3, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
-        },
-        /* Port 4, pins 0-7 */
-        {
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_IN,  DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                /* These 4 pins doesn't exist on DB3210 */
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP},
-                {GPIO_OUT, DEFAULT_OUTPUT_LOW,    ENABLE_PULL_UP}
-        }
-#endif
-};
-#endif
-
-
-/* No users == we can power down GPIO */
-static int gpio_users;
-
-struct gpio_struct {
-        int (*callback)(void *);
-        void *data;
-        int users;
-};
-
-static struct gpio_struct gpio_pin[U300_GPIO_MAX];
-
-/*
- * Let drivers register callback in order to get notified when there is
- * an interrupt on the gpio pin
- */
-int gpio_register_callback(unsigned gpio, int (*func)(void *arg), void *data)
-{
-        if (gpio_pin[gpio].callback)
-                dev_warn(gpiodev, "%s: WARNING: callback already "
-                         "registered for gpio pin#%d\n", __func__, gpio);
-        gpio_pin[gpio].callback = func;
-        gpio_pin[gpio].data = data;
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_register_callback);
-
-int gpio_unregister_callback(unsigned gpio)
-{
-        if (!gpio_pin[gpio].callback)
-                dev_warn(gpiodev, "%s: WARNING: callback already "
-                         "unregistered for gpio pin#%d\n", __func__, gpio);
-        gpio_pin[gpio].callback = NULL;
-        gpio_pin[gpio].data = NULL;
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_unregister_callback);
-
-/* Non-zero means valid */
-int gpio_is_valid(int number)
-{
-        if (number >= 0 &&
-            number < (U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT))
-                return 1;
-        return 0;
-}
-EXPORT_SYMBOL(gpio_is_valid);
-
-int gpio_request(unsigned gpio, const char *label)
-{
-        if (gpio_pin[gpio].users)
-                return -EINVAL;
-        else
-                gpio_pin[gpio].users++;
-
-        gpio_users++;
-
-        return 0;
-}
-EXPORT_SYMBOL(gpio_request);
-
-void gpio_free(unsigned gpio)
-{
-        gpio_users--;
-        gpio_pin[gpio].users--;
-        if (unlikely(gpio_pin[gpio].users < 0)) {
-                dev_warn(gpiodev, "warning: gpio#%d release mismatch\n",
-                         gpio);
-                gpio_pin[gpio].users = 0;
-        }
-
-        return;
-}
-EXPORT_SYMBOL(gpio_free);
-
-/* This returns zero or nonzero */
-int gpio_get_value(unsigned gpio)
-{
-        return readl(virtbase + U300_GPIO_PXPDIR +
-          PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING) & (1 << (gpio & 0x07));
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-/*
- * We hope that the compiler will optimize away the unused branch
- * in case "value" is a constant
- */
-void gpio_set_value(unsigned gpio, int value)
-{
-        u32 val;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        if (value) {
-                /* set */
-                val = readl(virtbase + U300_GPIO_PXPDOR +
-                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
-                  & (1 << (gpio & 0x07));
-                writel(val | (1 << (gpio & 0x07)), virtbase +
-                  U300_GPIO_PXPDOR +
-                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
-        } else {
-                /* clear */
-                val = readl(virtbase + U300_GPIO_PXPDOR +
-                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING)
-                  & (1 << (gpio & 0x07));
-                writel(val & ~(1 << (gpio & 0x07)), virtbase +
-                  U300_GPIO_PXPDOR +
-                  PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
-        }
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(gpio_set_value);
-
-int gpio_direction_input(unsigned gpio)
-{
-        unsigned long flags;
-        u32 val;
-
-        if (gpio > U300_GPIO_MAX)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        /* Mask out this pin*/
-        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
-        /* This is not needed since it sets the bits to zero.*/
-        /* val |= (U300_GPIO_PXPCR_PIN_MODE_INPUT << (gpio*2)); */
-        writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-        unsigned long flags;
-        u32 val;
-
-        if (gpio > U300_GPIO_MAX)
-                return -EINVAL;
-
-        local_irq_save(flags);
-        val = readl(virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        /* Mask out this pin */
-        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((gpio & 0x07) << 1));
-        /*
-         * FIXME: configure for push/pull, open drain or open source per pin
-         * in setup. The current driver will only support push/pull.
-         */
-        val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
-                        << ((gpio & 0x07) << 1));
-        writel(val, virtbase + U300_GPIO_PXPCR + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        gpio_set_value(gpio, value);
-        local_irq_restore(flags);
-        return 0;
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-/*
- * Enable an IRQ, edge is rising edge (!= 0) or falling edge (==0).
- */
-void enable_irq_on_gpio_pin(unsigned gpio, int edge)
-{
-        u32 val;
-        unsigned long flags;
-        local_irq_save(flags);
-
-        val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        val |= (1 << (gpio & 0x07));
-        writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        val = readl(virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        if (edge)
-                val |= (1 << (gpio & 0x07));
-        else
-                val &= ~(1 << (gpio & 0x07));
-        writel(val, virtbase + U300_GPIO_PXICR + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(enable_irq_on_gpio_pin);
-
-void disable_irq_on_gpio_pin(unsigned gpio)
-{
-        u32 val;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        val = readl(virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        val &= ~(1 << (gpio & 0x07));
-        writel(val, virtbase + U300_GPIO_PXIEN + PIN_TO_PORT(gpio) *
-                                U300_GPIO_PORTX_SPACING);
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(disable_irq_on_gpio_pin);
-
-/* Enable (value == 0) or disable (value == 1) internal pullup */
-void gpio_pullup(unsigned gpio, int value)
-{
-        u32 val;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        if (value) {
-                val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
-                                        U300_GPIO_PORTX_SPACING);
-                writel(val | (1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
-                                PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
-        } else {
-                val = readl(virtbase + U300_GPIO_PXPER + PIN_TO_PORT(gpio) *
-                                        U300_GPIO_PORTX_SPACING);
-                writel(val & ~(1 << (gpio & 0x07)), virtbase + U300_GPIO_PXPER +
-                                PIN_TO_PORT(gpio) * U300_GPIO_PORTX_SPACING);
-        }
-        local_irq_restore(flags);
-}
-EXPORT_SYMBOL(gpio_pullup);
-
-static irqreturn_t gpio_irq_handler(int irq, void *dev_id)
-{
-        struct u300_gpio_port *port = dev_id;
-        u32 val;
-        int pin;
-
-        /* Read event register */
-        val = readl(virtbase + U300_GPIO_PXIEV + port->number *
-                                U300_GPIO_PORTX_SPACING);
-        /* Mask with enable register */
-        val &= readl(virtbase + U300_GPIO_PXIEV + port->number *
-                                U300_GPIO_PORTX_SPACING);
-        /* Mask relevant bits */
-        val &= U300_GPIO_PXIEV_ALL_IRQ_EVENT_MASK;
-        /* ACK IRQ (clear event) */
-        writel(val, virtbase + U300_GPIO_PXIEV + port->number *
-                                U300_GPIO_PORTX_SPACING);
-        /* Print message */
-        while (val != 0) {
-                unsigned gpio;
-
-                pin = __ffs(val);
-                /* mask off this pin */
-                val &= ~(1 << pin);
-                gpio = (port->number << 3) + pin;
-
-                if (gpio_pin[gpio].callback)
-                        (void)gpio_pin[gpio].callback(gpio_pin[gpio].data);
-                else
-                        dev_dbg(gpiodev, "stray GPIO IRQ on line %d\n",
-                               gpio);
-        }
-        return IRQ_HANDLED;
-}
-
-static void gpio_set_initial_values(void)
-{
-#ifdef U300_COH901571_3
-        int i, j;
-        unsigned long flags;
-        u32 val;
-
-        /* Write default values to all pins */
-        for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
-                val = 0;
-                for (j = 0; j < 8; j++)
-                        val |= (u32) (u300_gpio_config[i][j].default_output_value != DEFAULT_OUTPUT_LOW) << j;
-                local_irq_save(flags);
-                writel(val, virtbase + U300_GPIO_PXPDOR + i * U300_GPIO_PORTX_SPACING);
-                local_irq_restore(flags);
-        }
-
-        /*
-         * Put all pins that are set to either 'GPIO_OUT' or 'GPIO_NOT_USED'
-         * to output and 'GPIO_IN' to input for each port. And initialize
-         * default value on outputs.
-         */
-        for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
-                for (j = 0; j < U300_GPIO_PINS_PER_PORT; j++) {
-                        local_irq_save(flags);
-                        val = readl(virtbase + U300_GPIO_PXPCR +
-                                         i * U300_GPIO_PORTX_SPACING);
-                        /* Mask out this pin */
-                        val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << (j << 1));
-
-                        if (u300_gpio_config[i][j].pin_usage != GPIO_IN)
-                                val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL << (j << 1));
-                        writel(val, virtbase + U300_GPIO_PXPCR +
-                                         i * U300_GPIO_PORTX_SPACING);
-                        local_irq_restore(flags);
-                }
-        }
-
-        /* Enable or disable the internal pull-ups in the GPIO ASIC block */
-        for (i = 0; i < U300_GPIO_MAX; i++) {
-                val = 0;
-                for (j = 0; j < 8; j++)
-                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
-                local_irq_save(flags);
-                writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
-                local_irq_restore(flags);
-        }
-#endif
-}
-
-static int __init gpio_probe(struct platform_device *pdev)
-{
-        u32 val;
-        int err = 0;
-        int i;
-        int num_irqs;
-
-        gpiodev = &pdev->dev;
-        memset(gpio_pin, 0, sizeof(gpio_pin));
-
-        /* Get GPIO clock */
-        clk = clk_get(&pdev->dev, NULL);
-        if (IS_ERR(clk)) {
-                err = PTR_ERR(clk);
-                dev_err(gpiodev, "could not get GPIO clock\n");
-                goto err_no_clk;
-        }
-        err = clk_enable(clk);
-        if (err) {
-                dev_err(gpiodev, "could not enable GPIO clock\n");
-                goto err_no_clk_enable;
-        }
-
-        memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!memres)
-                goto err_no_resource;
-
-        if (request_mem_region(memres->start, memres->end - memres->start, "GPIO Controller")
-            == NULL) {
-                err = -ENODEV;
-                goto err_no_ioregion;
-        }
-
-        virtbase = ioremap(memres->start, resource_size(memres));
-        if (!virtbase) {
-                err = -ENOMEM;
-                goto err_no_ioremap;
-        }
-        dev_info(gpiodev, "remapped 0x%08x to %p\n",
-                 memres->start, virtbase);
-
-#ifdef U300_COH901335
-        dev_info(gpiodev, "initializing GPIO Controller COH 901 335\n");
-        /* Turn on the GPIO block */
-        writel(U300_GPIO_CR_BLOCK_CLOCK_ENABLE, virtbase + U300_GPIO_CR);
-#endif
-
-#ifdef U300_COH901571_3
-        dev_info(gpiodev, "initializing GPIO Controller COH 901 571/3\n");
-        val = readl(virtbase + U300_GPIO_CR);
-        dev_info(gpiodev, "COH901571/3 block version: %d, " \
-               "number of cores: %d\n",
-               ((val & 0x0000FE00) >> 9),
-               ((val & 0x000001FC) >> 2));
-        writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, virtbase + U300_GPIO_CR);
-#endif
-
-        gpio_set_initial_values();
-
-        for (num_irqs = 0 ; num_irqs < U300_GPIO_NUM_PORTS; num_irqs++) {
-
-                gpio_ports[num_irqs].irq =
-                        platform_get_irq_byname(pdev,
-                                                gpio_ports[num_irqs].name);
-
-                err = request_irq(gpio_ports[num_irqs].irq,
-                                  gpio_irq_handler, IRQF_DISABLED,
-                                  gpio_ports[num_irqs].name,
-                                  &gpio_ports[num_irqs]);
-                if (err) {
-                        dev_err(gpiodev, "cannot allocate IRQ for %s!\n",
-                                gpio_ports[num_irqs].name);
-                        goto err_no_irq;
-                }
-                /* Turns off PortX_irq_force */
-                writel(0x0, virtbase + U300_GPIO_PXIFR +
-                                 num_irqs * U300_GPIO_PORTX_SPACING);
-        }
-
-        return 0;
-
- err_no_irq:
-        for (i = 0; i < num_irqs; i++)
-                free_irq(gpio_ports[i].irq, &gpio_ports[i]);
-        iounmap(virtbase);
- err_no_ioremap:
-        release_mem_region(memres->start, memres->end - memres->start);
- err_no_ioregion:
- err_no_resource:
-        clk_disable(clk);
- err_no_clk_enable:
-        clk_put(clk);
- err_no_clk:
-        dev_info(gpiodev, "module ERROR:%d\n", err);
-        return err;
-}
-
-static int __exit gpio_remove(struct platform_device *pdev)
-{
-        int i;
-
-        /* Turn off the GPIO block */
-        writel(0x00000000U, virtbase + U300_GPIO_CR);
-        for (i = 0 ; i < U300_GPIO_NUM_PORTS; i++)
-                free_irq(gpio_ports[i].irq, &gpio_ports[i]);
-        iounmap(virtbase);
-        release_mem_region(memres->start, memres->end - memres->start);
-        clk_disable(clk);
-        clk_put(clk);
-        return 0;
-}
-
-static struct platform_driver gpio_driver = {
-        .driver         = {
-                .name   = "u300-gpio",
-        },
-        .remove         = __exit_p(gpio_remove),
-};
-
-
-static int __init u300_gpio_init(void)
-{
-        return platform_driver_probe(&gpio_driver, gpio_probe);
-}
-
-static void __exit u300_gpio_exit(void)
-{
-        platform_driver_unregister(&gpio_driver);
-}
-
-arch_initcall(u300_gpio_init);
-module_exit(u300_gpio_exit);
-
-MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
-
-#ifdef U300_COH901571_3
-MODULE_DESCRIPTION("ST-Ericsson AB COH 901 571/3 GPIO driver");
-#endif
-
-#ifdef U300_COH901335
-MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335 GPIO driver");
-#endif
-
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 58626013aa32..f8b9392ee347 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -5,16 +5,18 @@ config UX500_SOC_COMMON
         default y
         select ARM_GIC
         select HAS_MTU
-        select NOMADIK_GPIO
         select ARM_ERRATA_753970
 
 menu "Ux500 SoC"
 
 config UX500_SOC_DB5500
         bool "DB5500"
+        select MFD_DB5500_PRCMU
 
 config UX500_SOC_DB8500
         bool "DB8500"
+        select MFD_DB8500_PRCMU
+        select REGULATOR_DB8500_PRCMU
 
 endmenu
 
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index b549a8fb4231..1694916e6822 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,7 +5,7 @@
 obj-y                           := clock.o cpu.o devices.o devices-common.o \
                                    id.o usb.o
 obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
-obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o prcmu.o
+obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o
 obj-$(CONFIG_MACH_U8500)        += board-mop500.o board-mop500-sdi.o \
                                 board-mop500-regulators.o \
                                 board-mop500-uib.o board-mop500-stuib.o \
@@ -17,4 +17,4 @@ obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
 obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
-obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
+
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index bf0b02414e5b..7c6cb4fa47a9 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -99,8 +99,11 @@ static void sdi0_configure(void)
         gpio_direction_output(sdi0_vsel, 0);
         gpio_direction_output(sdi0_en, 1);
 
-        /* Add the device */
-        db8500_add_sdi0(&mop500_sdi0_data);
+        /* Add the device, force v2 to subrevision 1 */
+        if (cpu_is_u8500v2())
+                db8500_add_sdi0(&mop500_sdi0_data, 0x10480180);
+        else
+                db8500_add_sdi0(&mop500_sdi0_data, 0);
 }
 
 void mop500_sdi_tc35892_init(void)
@@ -188,13 +191,18 @@ static struct mmci_platform_data mop500_sdi4_data = {
 
 void __init mop500_sdi_init(void)
 {
+        u32 periphid = 0;
+
+        /* v2 has a new version of this block that need to be forced */
+        if (cpu_is_u8500v2())
+                periphid = 0x10480180;
         /* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
         if (!cpu_is_u8500v10())
                 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
-        db8500_add_sdi2(&mop500_sdi2_data);
+        db8500_add_sdi2(&mop500_sdi2_data, periphid);
 
         /* On-board eMMC */
-        db8500_add_sdi4(&mop500_sdi4_data);
+        db8500_add_sdi4(&mop500_sdi4_data, periphid);
 
         if (machine_is_hrefv60()) {
                 mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 6e1907fa94f0..bb26f40493e6 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -204,7 +204,7 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         },
 };
 
-#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm)    \
 static struct nmk_i2c_controller u8500_i2c##id##_data = { \
         /*                              \
          * slave data setup time, which is      \
@@ -219,19 +219,21 @@ static struct nmk_i2c_controller u8500_i2c##id##_data = { \
         .rft            = _rft,         \
         /* std. mode operation */       \
         .clk_freq       = clk,          \
+        /* Slave response timeout(ms) */\
+        .timeout        = t_out,        \
         .sm             = _sm,          \
 }
 
 /*
  * The board uses 4 i2c controllers, initialize all of
  * them with slave data setup time of 250 ns,
- * Tx & Rx FIFO threshold values as 1 and standard
+ * Tx & Rx FIFO threshold values as 8 and standard
  * mode of operation
  */
-U8500_I2C_CONTROLLER(0, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
-U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
-U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
-U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
 
 static void __init mop500_i2c_init(void)
 {
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index c9dc2eff3cb2..c01bc19e3c5e 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -188,6 +188,8 @@ void __init u5500_map_io(void)
         ux500_map_io();
 
         iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
+
+        _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
 }
 
 static int usb_db5500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 516126cb357d..c3c417656bd9 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -87,6 +87,8 @@ void __init u8500_map_io(void)
                 iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
         else if (cpu_is_u8500v2())
                 iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
+
+        _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
 }
 
 static struct resource db8500_pmu_resources[] = {
@@ -129,9 +131,14 @@ static struct platform_device db8500_pmu_device = {
         .dev.platform_data      = &db8500_pmu_platdata,
 };
 
+static struct platform_device db8500_prcmu_device = {
+        .name                   = "db8500-prcmu",
+};
+
 static struct platform_device *platform_devs[] __initdata = {
         &u8500_dma40_device,
         &db8500_pmu_device,
+        &db8500_prcmu_device,
 };
 
 static resource_size_t __initdata db8500_gpio_base[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 5a43107c6232..1da23bb87c16 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,6 +8,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <linux/mfd/db5500-prcmu.h>
 
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -19,10 +21,11 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
-#include <mach/prcmu.h>
 
 #include "clock.h"
 
+void __iomem *_PRCMU_BASE;
+
 #ifdef CONFIG_CACHE_L2X0
 static void __iomem *l2x0_base;
 #endif
@@ -47,6 +50,8 @@ void __init ux500_init_irq(void)
          * Init clocks here so that they are available for system timer
          * initialization.
          */
+        if (cpu_is_u5500())
+                db5500_prcmu_early_init();
         if (cpu_is_u8500())
                 prcmu_early_init();
         clk_init();
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
deleted file mode 100644
index 5c5b747f134d..000000000000
--- a/arch/arm/mach-ux500/cpufreq.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * CPU frequency scaling for u8500
- * Inspired by linux/arch/arm/mach-davinci/cpufreq.c
- *
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- *
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Martin Persson <martin.persson@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <mach/prcmu.h>
-#include <mach/prcmu-defs.h>
-
-#define DRIVER_NAME "cpufreq-u8500"
-#define CPUFREQ_NAME "u8500"
-
-static struct device *dev;
-
-static struct cpufreq_frequency_table freq_table[] = {
-        [0] = {
-                .index = 0,
-                .frequency = 200000,
-        },
-        [1] = {
-                .index = 1,
-                .frequency = 300000,
-        },
-        [2] = {
-                .index = 2,
-                .frequency = 600000,
-        },
-        [3] = {
-                /* Used for CPU_OPP_MAX, if available */
-                .index = 3,
-                .frequency = CPUFREQ_TABLE_END,
-        },
-        [4] = {
-                .index = 4,
-                .frequency = CPUFREQ_TABLE_END,
-        },
-};
-
-static enum prcmu_cpu_opp index2opp[] = {
-        CPU_OPP_EXT_CLK,
-        CPU_OPP_50,
-        CPU_OPP_100,
-        CPU_OPP_MAX
-};
-
-static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
-{
-        return cpufreq_frequency_table_verify(policy, freq_table);
-}
-
-static int u8500_cpufreq_target(struct cpufreq_policy *policy,
-                                unsigned int target_freq,
-                                unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        unsigned int index;
-        int ret = 0;
-
-        /*
-         * Ensure desired rate is within allowed range.  Some govenors
-         * (ondemand) will just pass target_freq=0 to get the minimum.
-         */
-        if (target_freq < policy->cpuinfo.min_freq)
-                target_freq = policy->cpuinfo.min_freq;
-        if (target_freq > policy->cpuinfo.max_freq)
-                target_freq = policy->cpuinfo.max_freq;
-
-        ret = cpufreq_frequency_table_target(policy, freq_table,
-                                             target_freq, relation, &index);
-        if (ret < 0) {
-                dev_err(dev, "Could not look up next frequency\n");
-                return ret;
-        }
-
-        freqs.old = policy->cur;
-        freqs.new = freq_table[index].frequency;
-        freqs.cpu = policy->cpu;
-
-        if (freqs.old == freqs.new) {
-                dev_dbg(dev, "Current and target frequencies are equal\n");
-                return 0;
-        }
-
-        dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new);
-        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-        ret = prcmu_set_cpu_opp(index2opp[index]);
-        if (ret < 0) {
-                dev_err(dev, "Failed to set OPP level\n");
-                return ret;
-        }
-
-        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
-        return ret;
-}
-
-static unsigned int u8500_cpufreq_getspeed(unsigned int cpu)
-{
-        int i;
-
-        for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++)
-                ;
-        return freq_table[i].frequency;
-}
-
-static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
-{
-        int res;
-
-        BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table));
-
-        if (cpu_is_u8500v2()) {
-                freq_table[1].frequency = 400000;
-                freq_table[2].frequency = 800000;
-                if (prcmu_has_arm_maxopp())
-                        freq_table[3].frequency = 1000000;
-        }
-
-        /* get policy fields based on the table */
-        res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
-        if (!res)
-                cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
-        else {
-                dev_err(dev, "u8500-cpufreq : Failed to read policy table\n");
-                return res;
-        }
-
-        policy->min = policy->cpuinfo.min_freq;
-        policy->max = policy->cpuinfo.max_freq;
-        policy->cur = u8500_cpufreq_getspeed(policy->cpu);
-        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-
-        /*
-         * FIXME : Need to take time measurement across the target()
-         *         function with no/some/all drivers in the notification
-         *         list.
-         */
-        policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
-
-        /* policy sharing between dual CPUs */
-        cpumask_copy(policy->cpus, &cpu_present_map);
-
-        policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
-
-        return res;
-}
-
-static struct freq_attr *u8500_cpufreq_attr[] = {
-        &cpufreq_freq_attr_scaling_available_freqs,
-        NULL,
-};
-static int u8500_cpu_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-        return 0;
-}
-
-static struct cpufreq_driver u8500_driver = {
-        .owner = THIS_MODULE,
-        .flags = CPUFREQ_STICKY,
-        .verify = u8500_cpufreq_verify_speed,
-        .target = u8500_cpufreq_target,
-        .get = u8500_cpufreq_getspeed,
-        .init = u8500_cpu_init,
-        .exit = u8500_cpu_exit,
-        .name = CPUFREQ_NAME,
-        .attr = u8500_cpufreq_attr,
-};
-
-static int __init u8500_cpufreq_probe(struct platform_device *pdev)
-{
-        dev = &pdev->dev;
-        return cpufreq_register_driver(&u8500_driver);
-}
-
-static int __exit u8500_cpufreq_remove(struct platform_device *pdev)
-{
-        return cpufreq_unregister_driver(&u8500_driver);
-}
-
-static struct platform_driver u8500_cpufreq_driver = {
-        .driver = {
-                .name    = DRIVER_NAME,
-                .owner   = THIS_MODULE,
-        },
-        .remove = __exit_p(u8500_cpufreq_remove),
-};
-
-static int __init u8500_cpufreq_init(void)
-{
-        return platform_driver_probe(&u8500_cpufreq_driver,
-                                     &u8500_cpufreq_probe);
-}
-
-device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
index c719b5a1d913..7825705033bf 100644
--- a/arch/arm/mach-ux500/devices-common.h
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -28,18 +28,20 @@ dbx500_add_msp_spi(const char *name, resource_size_t base, int irq,
 
 static inline struct amba_device *
 dbx500_add_spi(const char *name, resource_size_t base, int irq,
-                                   struct spi_master_cntlr *pdata)
+               struct spi_master_cntlr *pdata,
+               u32 periphid)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+        return dbx500_add_amba_device(name, base, irq, pdata, periphid);
 }
 
 struct mmci_platform_data;
 
 static inline struct amba_device *
 dbx500_add_sdi(const char *name, resource_size_t base, int irq,
-               struct mmci_platform_data *pdata)
+               struct mmci_platform_data *pdata,
+               u32 periphid)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+        return dbx500_add_amba_device(name, base, irq, pdata, periphid);
 }
 
 struct amba_pl011_data;
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
index 94627f7783b0..0c4bccd02b90 100644
--- a/arch/arm/mach-ux500/devices-db5500.h
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -38,24 +38,34 @@
         ux500_add_usb(U5500_USBOTG_BASE, IRQ_DB5500_USBOTG, rx_cfg, tx_cfg)
 
 #define db5500_add_sdi0(pdata) \
-        dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata)
+        dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata, \
+                       0x10480180)
 #define db5500_add_sdi1(pdata) \
-        dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata)
+        dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata, \
+                       0x10480180)
 #define db5500_add_sdi2(pdata) \
-        dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata)
+        dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata \
+                       0x10480180)
 #define db5500_add_sdi3(pdata) \
-        dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata)
+        dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata \
+                       0x10480180)
 #define db5500_add_sdi4(pdata) \
-        dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata)
+        dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata \
+                       0x10480180)
 
+/* This one has a bad peripheral ID in the U5500 silicon */
 #define db5500_add_spi0(pdata) \
-        dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata)
+        dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata, \
+                       0x10080023)
 #define db5500_add_spi1(pdata) \
-        dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata)
+        dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata, \
+                       0x10080023)
 #define db5500_add_spi2(pdata) \
-        dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata)
+        dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata \
+                       0x10080023)
 #define db5500_add_spi3(pdata) \
-        dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata)
+        dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata \
+                       0x10080023)
 
 #define db5500_add_uart0(plat) \
         dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0, plat)
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
index 9cc6f8f5d3e6..cbd4a9ae8109 100644
--- a/arch/arm/mach-ux500/devices-db8500.h
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -25,7 +25,7 @@ static inline struct amba_device *
 db8500_add_ssp(const char *name, resource_size_t base, int irq,
                struct pl022_ssp_controller *pdata)
 {
-        return dbx500_add_amba_device(name, base, irq, pdata, SSP_PER_ID);
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
 }
 
 
@@ -64,18 +64,18 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
 #define db8500_add_usb(rx_cfg, tx_cfg) \
         ux500_add_usb(U8500_USBOTG_BASE, IRQ_DB8500_USBOTG, rx_cfg, tx_cfg)
 
-#define db8500_add_sdi0(pdata) \
-        dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata)
-#define db8500_add_sdi1(pdata) \
-        dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata)
-#define db8500_add_sdi2(pdata) \
-        dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata)
-#define db8500_add_sdi3(pdata) \
-        dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata)
-#define db8500_add_sdi4(pdata) \
-        dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata)
-#define db8500_add_sdi5(pdata) \
-        dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata)
+#define db8500_add_sdi0(pdata, pid) \
+        dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata, pid)
+#define db8500_add_sdi1(pdata, pid) \
+        dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata, pid)
+#define db8500_add_sdi2(pdata, pid) \
+        dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata, pid)
+#define db8500_add_sdi3(pdata, pid) \
+        dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata, pid)
+#define db8500_add_sdi4(pdata, pid) \
+        dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata, pid)
+#define db8500_add_sdi5(pdata, pid) \
+        dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata, pid)
 
 #define db8500_add_ssp0(pdata) \
         db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata)
@@ -83,13 +83,13 @@ db8500_add_ssp(const char *name, resource_size_t base, int irq,
         db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata)
 
 #define db8500_add_spi0(pdata) \
-        dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata)
+        dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata, 0)
 #define db8500_add_spi1(pdata) \
-        dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata)
+        dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata, 0)
 #define db8500_add_spi2(pdata) \
-        dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata)
+        dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata, 0)
 #define db8500_add_spi3(pdata) \
-        dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata)
+        dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata, 0)
 
 #define db8500_add_uart0(pdata) \
         dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0, pdata)
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index bd88c1e74060..6ad983294103 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -17,6 +17,8 @@
 #define U5500_GIC_DIST_BASE     0xA0411000
 #define U5500_GIC_CPU_BASE      0xA0410100
 #define U5500_DMA_BASE          0x90030000
+#define U5500_STM_BASE          0x90020000
+#define U5500_STM_REG_BASE      (U5500_STM_BASE + 0xF000)
 #define U5500_MCDE_BASE         0xA0400000
 #define U5500_MODEM_BASE        0xB0000000
 #define U5500_L2CC_BASE         0xA0412000
@@ -29,7 +31,9 @@
 #define U5500_NAND0_BASE        0x60000000
 #define U5500_NAND1_BASE        0x70000000
 #define U5500_TWD_BASE          0xa0410600
+#define U5500_ICN_BASE          0xA0040000
 #define U5500_B2R2_BASE         0xa0200000
+#define U5500_BOOT_ROM_BASE     0x90000000
 
 #define U5500_FSMC_BASE         (U5500_PER1_BASE + 0x0000)
 #define U5500_SDI0_BASE         (U5500_PER1_BASE + 0x1000)
@@ -60,6 +64,7 @@
 #define U5500_MSP1_BASE         (U5500_PER4_BASE + 0x9000)
 #define U5500_GPIO2_BASE        (U5500_PER4_BASE + 0xA000)
 #define U5500_CDETECT_BASE      (U5500_PER4_BASE + 0xF000)
+#define U5500_PRCMU_TCDM_BASE   (U5500_PER4_BASE + 0x18000)
 
 #define U5500_SPI0_BASE         (U5500_PER5_BASE + 0x0000)
 #define U5500_SPI1_BASE         (U5500_PER5_BASE + 0x1000)
@@ -83,7 +88,7 @@
 #define U5500_HASH0_BASE        (U5500_PER6_BASE + 0x1000)
 #define U5500_HASH1_BASE        (U5500_PER6_BASE + 0x2000)
 #define U5500_PKA_BASE          (U5500_PER6_BASE + 0x4000)
-#define U5500_PKAM_BASE         (U5500_PER6_BASE + 0x5000)
+#define U5500_PKAM_BASE         (U5500_PER6_BASE + 0x5100)
 #define U5500_MTU0_BASE         (U5500_PER6_BASE + 0x6000)
 #define U5500_MTU1_BASE         (U5500_PER6_BASE + 0x7000)
 #define U5500_CR_BASE           (U5500_PER6_BASE + 0x8000)
@@ -114,8 +119,19 @@
 #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
 #define U5500_MBOX2_LOCAL_END   (U5500_MBOX_BASE + 0x3F)
 
-#define U5500_ESRAM_BASE                0x40000000
+#define U5500_ACCCON_BASE_SEC   (0xBFFF0000)
+#define U5500_ACCCON_BASE               (0xBFFF1000)
+#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
+#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
+
+#define U5500_ESRAM_BASE                0x40000000
 #define U5500_ESRAM_DMA_LCPA_OFFSET     0x10000
 #define U5500_DMA_LCPA_BASE    (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
 
+#define U5500_MCDE_SIZE         0x1000
+#define U5500_DSI_LINK_SIZE     0x1000
+#define U5500_DSI_LINK_COUNT    0x2
+#define U5500_DSI_LINK1_BASE    (U5500_MCDE_BASE + U5500_MCDE_SIZE)
+#define U5500_DSI_LINK2_BASE    (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 16647b255378..049997109cf9 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -15,8 +15,13 @@
 #define U8500_ESRAM_BANK2       (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
 #define U8500_ESRAM_BANK3       (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
 #define U8500_ESRAM_BANK4       (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
-/* Use bank 4 for DMA LCPA */
-#define U8500_DMA_LCPA_BASE     U8500_ESRAM_BANK4
+/*
+ * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
+ * reserved for security
+ */
+#define U8500_ESRAM_DMA_LCPA_OFFSET     0x10000
+
+#define U8500_DMA_LCPA_BASE    (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
 #define U8500_DMA_LCPA_BASE_ED  (U8500_ESRAM_BANK4 + 0x4000)
 
 #define U8500_PER3_BASE         0x80000000
@@ -27,9 +32,12 @@
 #define U8500_B2R2_BASE         0x80130000
 #define U8500_HSEM_BASE         0x80140000
 #define U8500_PER4_BASE         0x80150000
+#define U8500_TPIU_BASE         0x80190000
 #define U8500_ICN_BASE          0x81000000
 
 #define U8500_BOOT_ROM_BASE     0x90000000
+/* ASIC ID is at 0xbf4 offset within this region */
+#define U8500_ASIC_ID_BASE      0x9001D000
 
 #define U8500_PER6_BASE         0xa03c0000
 #define U8500_PER5_BASE         0xa03e0000
@@ -70,13 +78,15 @@
 
 /* per6 base addresses */
 #define U8500_RNG_BASE          (U8500_PER6_BASE + 0x0000)
-#define U8500_PKA_BASE          (U8500_PER6_BASE + 0x1000)
-#define U8500_PKAM_BASE         (U8500_PER6_BASE + 0x2000)
+#define U8500_HASH0_BASE        (U8500_PER6_BASE + 0x1000)
+#define U8500_HASH1_BASE        (U8500_PER6_BASE + 0x2000)
+#define U8500_PKA_BASE          (U8500_PER6_BASE + 0x4000)
+#define U8500_PKAM_BASE         (U8500_PER6_BASE + 0x5100)
 #define U8500_MTU0_BASE         (U8500_PER6_BASE + 0x6000) /* v1 */
 #define U8500_MTU1_BASE         (U8500_PER6_BASE + 0x7000) /* v1 */
 #define U8500_CR_BASE           (U8500_PER6_BASE + 0x8000) /* v1 */
-#define U8500_CRYPTO0_BASE      (U8500_PER6_BASE + 0xa000)
-#define U8500_CRYPTO1_BASE      (U8500_PER6_BASE + 0xb000)
+#define U8500_CRYP0_BASE        (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYP1_BASE        (U8500_PER6_BASE + 0xb000)
 #define U8500_CLKRST6_BASE      (U8500_PER6_BASE + 0xf000)
 
 /* per5 base addresses */
@@ -93,7 +103,8 @@
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
 #define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
-#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
+#define U8500_PRCMU_TCPM_BASE   (U8500_PER4_BASE + 0x60000)
 
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
@@ -124,6 +135,7 @@
 #define U8500_I2C1_BASE         (U8500_PER1_BASE + 0x2000)
 #define U8500_MSP0_BASE         (U8500_PER1_BASE + 0x3000)
 #define U8500_MSP1_BASE         (U8500_PER1_BASE + 0x4000)
+#define U8500_MSP3_BASE         (U8500_PER1_BASE + 0x5000)
 #define U8500_SDI0_BASE         (U8500_PER1_BASE + 0x6000)
 #define U8500_I2C2_BASE         (U8500_PER1_BASE + 0x8000)
 #define U8500_SPI3_BASE         (U8500_PER1_BASE + 0x9000)
@@ -143,4 +155,15 @@
 #define U8500_GPIOBANK7_BASE    (U8500_GPIO2_BASE + 0x80)
 #define U8500_GPIOBANK8_BASE    U8500_GPIO3_BASE
 
+#define U8500_MCDE_SIZE         0x1000
+#define U8500_DSI_LINK_SIZE     0x1000
+#define U8500_DSI_LINK1_BASE    (U8500_MCDE_BASE + U8500_MCDE_SIZE)
+#define U8500_DSI_LINK2_BASE    (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK3_BASE    (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK_COUNT    0x3
+
+/* Modem and APE physical addresses */
+#define U8500_MODEM_BASE        0xe000000
+#define U8500_APE_BASE          0x6000000
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index bf63f2631ba0..470ac52663d6 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -29,12 +29,10 @@
 #include <mach/db8500-regs.h>
 #include <mach/db5500-regs.h>
 
-/* ST-Ericsson modified pl022 id */
-#define SSP_PER_ID              0x01080022
-
 #ifndef __ASSEMBLY__
 
 #include <mach/id.h>
+extern void __iomem *_PRCMU_BASE;
 
 #define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
 
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index f1288d10b6ab..02b541a37ee5 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -75,6 +75,26 @@ static inline bool __attribute_const__ cpu_is_u8500v2(void)
         return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0);
 }
 
+static inline bool cpu_is_u8500v20(void)
+{
+        return cpu_is_u8500() && (dbx500_revision() == 0xB0);
+}
+
+static inline bool cpu_is_u8500v21(void)
+{
+        return cpu_is_u8500() && (dbx500_revision() == 0xB1);
+}
+
+static inline bool cpu_is_u8500v20_or_later(void)
+{
+        return cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11();
+}
+
+static inline bool ux500_is_svp(void)
+{
+        return false;
+}
+
 #define ux500_unknown_soc()     BUG()
 
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 97ef55f84934..47969909836c 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -50,6 +50,11 @@
 
 #define MOP500_IRQ_END          MOP500_NR_IRQS
 
+/*
+ * We may have several boards, but only one will run at a
+ * time, so the one with most IRQs will bump this ahead,
+ * but the IRQ_BOARD_START remains the same for either board.
+ */
 #if MOP500_IRQ_END > IRQ_BOARD_END
 #undef IRQ_BOARD_END
 #define IRQ_BOARD_END   MOP500_IRQ_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
new file mode 100644
index 000000000000..29d972c7717b
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_BOARD_U5500_H
+#define __MACH_IRQS_BOARD_U5500_H
+
+#define AB5500_NR_IRQS          5
+#define IRQ_AB5500_BASE         IRQ_BOARD_START
+#define IRQ_AB5500_END          (IRQ_AB5500_BASE + AB5500_NR_IRQS)
+
+#define U5500_IRQ_END           IRQ_AB5500_END
+
+#if IRQ_BOARD_END < U5500_IRQ_END
+#undef IRQ_BOARD_END
+#define IRQ_BOARD_END           U5500_IRQ_END
+#endif
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index bfa123dbec3b..77239776a6f2 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -83,4 +83,31 @@
 #define IRQ_DB5500_GPIO6                (IRQ_SHPI_START + 125)
 #define IRQ_DB5500_GPIO7                (IRQ_SHPI_START + 126)
 
+#ifdef CONFIG_UX500_SOC_DB5500
+
+/*
+ * After the GPIO ones we reserve a range of IRQ:s in which virtual
+ * IRQ:s representing modem IRQ:s can be allocated
+ */
+#define IRQ_MODEM_EVENTS_BASE   IRQ_SOC_START
+#define IRQ_MODEM_EVENTS_NBR    72
+#define IRQ_MODEM_EVENTS_END    (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
+
+/* List of virtual IRQ:s that are allocated from the range above */
+#define MBOX_PAIR0_VIRT_IRQ     (IRQ_MODEM_EVENTS_BASE + 43)
+#define MBOX_PAIR1_VIRT_IRQ     (IRQ_MODEM_EVENTS_BASE + 45)
+#define MBOX_PAIR2_VIRT_IRQ     (IRQ_MODEM_EVENTS_BASE + 41)
+
+/*
+ * We may have several SoCs, but only one will run at a
+ * time, so the one with most IRQs will bump this ahead,
+ * but the IRQ_SOC_START remains the same for either SoC.
+ */
+#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
+#undef IRQ_SOC_END
+#define IRQ_SOC_END             IRQ_MODEM_EVENTS_END
+#endif
+
+#endif /* CONFIG_UX500_SOC_DB5500 */
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
index 8b5d9f0a1633..68bc14974608 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -93,4 +93,58 @@
 #define IRQ_DB8500_GPIO7                (IRQ_SHPI_START + 126)
 #define IRQ_DB8500_GPIO8                (IRQ_SHPI_START + 127)
 
+#define IRQ_CA_WAKE_REQ_ED                      (IRQ_SHPI_START + 71)
+#define IRQ_AC_READ_NOTIFICATION_0_ED           (IRQ_SHPI_START + 66)
+#define IRQ_AC_READ_NOTIFICATION_1_ED           (IRQ_SHPI_START + 64)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED       (IRQ_SHPI_START + 67)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED       (IRQ_SHPI_START + 65)
+
+#define IRQ_CA_WAKE_REQ_V1                      (IRQ_SHPI_START + 83)
+#define IRQ_AC_READ_NOTIFICATION_0_V1           (IRQ_SHPI_START + 78)
+#define IRQ_AC_READ_NOTIFICATION_1_V1           (IRQ_SHPI_START + 76)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1       (IRQ_SHPI_START + 79)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1       (IRQ_SHPI_START + 77)
+
+#ifdef CONFIG_UX500_SOC_DB8500
+
+/* Virtual interrupts corresponding to the PRCMU wakeups.  */
+#define IRQ_PRCMU_BASE IRQ_SOC_START
+#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
+
+#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
+#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
+#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
+#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
+#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
+#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
+#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
+#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
+#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
+#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
+#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
+#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
+#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
+#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
+#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
+#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
+#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
+#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
+#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
+#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
+#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
+#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
+#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
+#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
+
+/*
+ * We may have several SoCs, but only one will run at a
+ * time, so the one with most IRQs will bump this ahead,
+ * but the IRQ_SOC_START remains the same for either SoC.
+ */
+#if IRQ_SOC_END < IRQ_PRCMU_END
+#undef IRQ_SOC_END
+#define IRQ_SOC_END IRQ_PRCMU_END
+#endif
+
+#endif /* CONFIG_UX500_SOC_DB8500 */
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index ba1294c13c4d..9db68d264c5f 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,49 +10,47 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
 
-#include <mach/irqs-db5500.h>
-#include <mach/irqs-db8500.h>
+#include <mach/hardware.h>
 
-#define IRQ_LOCALTIMER                  29
-#define IRQ_LOCALWDOG                   30
+#define IRQ_LOCALTIMER                  29
+#define IRQ_LOCALWDOG                   30
 
 /* Shared Peripheral Interrupt (SHPI) */
 #define IRQ_SHPI_START                  32
 
-/* Interrupt numbers generic for shared peripheral */
+/*
+ * MTU0 preserved for now until plat-nomadik is taught not to use it.  Don't
+ * add any other IRQs here, use the irqs-dbx500.h files.
+ */
 #define IRQ_MTU0                (IRQ_SHPI_START + 4)
 
-/* There are 128 shared peripheral interrupts assigned to
- * INTID[160:32]. The first 32 interrupts are reserved.
- */
-#define DBX500_NR_INTERNAL_IRQS         161
+#define DBX500_NR_INTERNAL_IRQS         160
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                 288
 #define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + DBX500_NR_INTERNAL_IRQS)
 #define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - DBX500_NR_INTERNAL_IRQS)
-#define IRQ_BOARD_START                 NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define IRQ_GPIO_END                    NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+
+#define IRQ_SOC_START           IRQ_GPIO_END
+/* This will be overridden by SoC-specific irq headers */
+#define IRQ_SOC_END             IRQ_SOC_START
 
+#include <mach/irqs-db5500.h>
+#include <mach/irqs-db8500.h>
+
+#define IRQ_BOARD_START         IRQ_SOC_END
 /* This will be overridden by board-specific irq headers */
-#define IRQ_BOARD_END                   IRQ_BOARD_START
+#define IRQ_BOARD_END           IRQ_BOARD_START
 
 #ifdef CONFIG_MACH_U8500
 #include <mach/irqs-board-mop500.h>
 #endif
 
-/*
- * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual
- * IRQ:s representing modem IRQ:s can be allocated
- */
-#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
-#define IRQ_MODEM_EVENTS_NBR 72
-#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
-
-/* List of virtual IRQ:s that are allocated from the range above */
-#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
-#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
-#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
+#ifdef CONFIG_MACH_U5500
+#include <mach/irqs-board-u5500.h>
+#endif
 
-#define NR_IRQS                         IRQ_MODEM_EVENTS_END
+#define NR_IRQS                 IRQ_BOARD_END
 
 #endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
deleted file mode 100644
index 848ba64b561f..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-defs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Martin Persson <martin.persson@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit definitions
- */
-
-#ifndef __MACH_PRCMU_DEFS_H
-#define __MACH_PRCMU_DEFS_H
-
-enum prcmu_cpu_opp {
-        CPU_OPP_INIT      = 0x00,
-        CPU_OPP_NO_CHANGE = 0x01,
-        CPU_OPP_100       = 0x02,
-        CPU_OPP_50        = 0x03,
-        CPU_OPP_MAX       = 0x04,
-        CPU_OPP_EXT_CLK   = 0x07
-};
-enum prcmu_ape_opp {
-        APE_OPP_NO_CHANGE = 0x00,
-        APE_OPP_100       = 0x02,
-        APE_OPP_50        = 0x03,
-};
-
-#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
deleted file mode 100644
index 455467e88791..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit registers
- */
-
-#ifndef __MACH_PRCMU_REGS_H
-#define __MACH_PRCMU_REGS_H
-
-#include <mach/hardware.h>
-
-#define _PRCMU_BASE             IO_ADDRESS(U8500_PRCMU_BASE)
-
-#define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
-#define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
-#define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
-#define PRCM_ARMCLKFIX_MGT      (_PRCMU_BASE + 0x0)
-#define PRCM_A9_RESETN_CLR      (_PRCMU_BASE + 0x1f4)
-#define PRCM_A9_RESETN_SET      (_PRCMU_BASE + 0x1f0)
-#define PRCM_ARM_LS_CLAMP       (_PRCMU_BASE + 0x30c)
-#define PRCM_SRAM_A9            (_PRCMU_BASE + 0x308)
-
-/* ARM WFI Standby signal register */
-#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
-#define PRCMU_IOCR              (_PRCMU_BASE + 0x310)
-
-/* CPU mailbox registers */
-#define PRCM_MBOX_CPU_VAL       (_PRCMU_BASE + 0x0fc)
-#define PRCM_MBOX_CPU_SET       (_PRCMU_BASE + 0x100)
-#define PRCM_MBOX_CPU_CLR       (_PRCMU_BASE + 0x104)
-
-/* Dual A9 core interrupt management unit registers */
-#define PRCM_A9_MASK_REQ        (_PRCMU_BASE + 0x328)
-#define PRCM_A9_MASK_ACK        (_PRCMU_BASE + 0x32c)
-#define PRCM_ARMITMSK31TO0      (_PRCMU_BASE + 0x11c)
-#define PRCM_ARMITMSK63TO32     (_PRCMU_BASE + 0x120)
-#define PRCM_ARMITMSK95TO64     (_PRCMU_BASE + 0x124)
-#define PRCM_ARMITMSK127TO96    (_PRCMU_BASE + 0x128)
-#define PRCM_POWER_STATE_VAL    (_PRCMU_BASE + 0x25C)
-#define PRCM_ARMITVAL31TO0      (_PRCMU_BASE + 0x260)
-#define PRCM_ARMITVAL63TO32     (_PRCMU_BASE + 0x264)
-#define PRCM_ARMITVAL95TO64     (_PRCMU_BASE + 0x268)
-#define PRCM_ARMITVAL127TO96    (_PRCMU_BASE + 0x26C)
-
-#define PRCM_HOSTACCESS_REQ     (_PRCMU_BASE + 0x334)
-#define ARM_WAKEUP_MODEM        0x1
-
-#define PRCM_ARM_IT1_CLEAR      (_PRCMU_BASE + 0x48C)
-#define PRCM_ARM_IT1_VAL        (_PRCMU_BASE + 0x494)
-#define PRCM_HOLD_EVT           (_PRCMU_BASE + 0x174)
-
-#define PRCM_ITSTATUS0          (_PRCMU_BASE + 0x148)
-#define PRCM_ITSTATUS1          (_PRCMU_BASE + 0x150)
-#define PRCM_ITSTATUS2          (_PRCMU_BASE + 0x158)
-#define PRCM_ITSTATUS3          (_PRCMU_BASE + 0x160)
-#define PRCM_ITSTATUS4          (_PRCMU_BASE + 0x168)
-#define PRCM_ITSTATUS5          (_PRCMU_BASE + 0x484)
-#define PRCM_ITCLEAR5           (_PRCMU_BASE + 0x488)
-#define PRCM_ARMIT_MASKXP70_IT  (_PRCMU_BASE + 0x1018)
-
-/* System reset register */
-#define PRCM_APE_SOFTRST        (_PRCMU_BASE + 0x228)
-
-/* Level shifter and clamp control registers */
-#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
-#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
-
-/* PRCMU clock/PLL/reset registers */
-#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
-#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
-#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + 0x044)
-#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + 0x064)
-#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + 0x058)
-#define PRCM_TVCLK_MGT             (_PRCMU_BASE + 0x07c)
-#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
-#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
-#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
-#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
-
-/* ePOD and memory power signal control registers */
-#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
-#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)
-
-/* Debug power control unit registers */
-#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)
-
-/* Miscellaneous unit registers */
-#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
-
-#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
deleted file mode 100644
index c49e456162ef..000000000000
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit f/w API
- */
-#ifndef __MACH_PRCMU_H
-#define __MACH_PRCMU_H
-#include <mach/prcmu-defs.h>
-
-void __init prcmu_early_init(void);
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
-int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
-int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
-                           enum prcmu_cpu_opp cpu_opp);
-int prcmu_get_ape_opp(void);
-int prcmu_get_cpu_opp(void);
-bool prcmu_has_arm_maxopp(void);
-
-#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
deleted file mode 100644
index c522d26ef348..000000000000
--- a/arch/arm/mach-ux500/prcmu.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
- *
- * U8500 PRCM Unit interface driver
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/mutex.h>
-#include <linux/completion.h>
-#include <linux/jiffies.h>
-#include <linux/bitops.h>
-#include <linux/interrupt.h>
-
-#include <mach/hardware.h>
-#include <mach/prcmu-regs.h>
-#include <mach/prcmu-defs.h>
-
-/* Global var to runtime determine TCDM base for v2 or v1 */
-static __iomem void *tcdm_base;
-
-#define _MBOX_HEADER            (tcdm_base + 0xFE8)
-#define MBOX_HEADER_REQ_MB0     (_MBOX_HEADER + 0x0)
-
-#define REQ_MB1 (tcdm_base + 0xFD0)
-#define REQ_MB5 (tcdm_base + 0xE44)
-
-#define REQ_MB1_ARMOPP          (REQ_MB1 + 0x0)
-#define REQ_MB1_APEOPP          (REQ_MB1 + 0x1)
-#define REQ_MB1_BOOSTOPP        (REQ_MB1 + 0x2)
-
-#define ACK_MB1 (tcdm_base + 0xE04)
-#define ACK_MB5 (tcdm_base + 0xDF4)
-
-#define ACK_MB1_CURR_ARMOPP             (ACK_MB1 + 0x0)
-#define ACK_MB1_CURR_APEOPP             (ACK_MB1 + 0x1)
-
-#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
-#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
-#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
-#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
-
-#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
-#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
-
-#define PRCM_AVS_VARM_MAX_OPP           (tcdm_base + 0x2E4)
-#define PRCM_AVS_ISMODEENABLE           7
-#define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
-
-#define I2C_WRITE(slave) \
-        (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
-#define I2C_READ(slave) \
-        (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
-#define I2C_STOP_EN BIT(3)
-
-enum mb1_h {
-        MB1H_ARM_OPP = 1,
-        MB1H_APE_OPP,
-        MB1H_ARM_APE_OPP,
-};
-
-static struct {
-        struct mutex lock;
-        struct completion work;
-        struct {
-                u8 arm_opp;
-                u8 ape_opp;
-                u8 arm_status;
-                u8 ape_status;
-        } ack;
-} mb1_transfer;
-
-enum ack_mb5_status {
-        I2C_WR_OK = 0x01,
-        I2C_RD_OK = 0x02,
-};
-
-#define MBOX_BIT BIT
-#define NUM_MBOX 8
-
-static struct {
-        struct mutex lock;
-        struct completion work;
-        bool failed;
-        struct {
-                u8 status;
-                u8 value;
-        } ack;
-} mb5_transfer;
-
-/**
- * prcmu_abb_read() - Read register value(s) from the ABB.
- * @slave:      The I2C slave address.
- * @reg:        The (start) register address.
- * @value:      The read out value(s).
- * @size:       The number of registers to read.
- *
- * Reads register value(s) from the ABB.
- * @size has to be 1 for the current firmware version.
- */
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
-{
-        int r;
-
-        if (size != 1)
-                return -EINVAL;
-
-        r = mutex_lock_interruptible(&mb5_transfer.lock);
-        if (r)
-                return r;
-
-        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
-                cpu_relax();
-
-        writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
-        writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
-        writeb(reg, REQ_MB5_I2C_REG);
-
-        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
-        if (!wait_for_completion_timeout(&mb5_transfer.work,
-                        msecs_to_jiffies(500))) {
-                pr_err("prcmu: prcmu_abb_read timed out.\n");
-                r = -EIO;
-                goto unlock_and_return;
-        }
-        r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
-        if (!r)
-                *value = mb5_transfer.ack.value;
-
-unlock_and_return:
-        mutex_unlock(&mb5_transfer.lock);
-        return r;
-}
-EXPORT_SYMBOL(prcmu_abb_read);
-
-/**
- * prcmu_abb_write() - Write register value(s) to the ABB.
- * @slave:      The I2C slave address.
- * @reg:        The (start) register address.
- * @value:      The value(s) to write.
- * @size:       The number of registers to write.
- *
- * Reads register value(s) from the ABB.
- * @size has to be 1 for the current firmware version.
- */
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
-{
-        int r;
-
-        if (size != 1)
-                return -EINVAL;
-
-        r = mutex_lock_interruptible(&mb5_transfer.lock);
-        if (r)
-                return r;
-
-
-        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
-                cpu_relax();
-
-        writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
-        writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
-        writeb(reg, REQ_MB5_I2C_REG);
-        writeb(*value, REQ_MB5_I2C_VAL);
-
-        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
-        if (!wait_for_completion_timeout(&mb5_transfer.work,
-                        msecs_to_jiffies(500))) {
-                pr_err("prcmu: prcmu_abb_write timed out.\n");
-                r = -EIO;
-                goto unlock_and_return;
-        }
-        r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
-
-unlock_and_return:
-        mutex_unlock(&mb5_transfer.lock);
-        return r;
-}
-EXPORT_SYMBOL(prcmu_abb_write);
-
-static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
-                            enum prcmu_cpu_opp cpu_opp)
-{
-        bool do_ape;
-        bool do_arm;
-        int err = 0;
-
-        do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
-        do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
-
-        mutex_lock(&mb1_transfer.lock);
-
-        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
-                cpu_relax();
-
-        writeb(0, MBOX_HEADER_REQ_MB0);
-        writeb(cpu_opp, REQ_MB1_ARMOPP);
-        writeb(ape_opp, REQ_MB1_APEOPP);
-        writeb(0, REQ_MB1_BOOSTOPP);
-        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
-        wait_for_completion(&mb1_transfer.work);
-        if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
-                err = -EIO;
-        if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
-                err = -EIO;
-
-        mutex_unlock(&mb1_transfer.lock);
-
-        return err;
-}
-
-/**
- * prcmu_set_ape_opp() - Set the OPP of the APE.
- * @opp:        The OPP to set.
- *
- * This function sets the OPP of the APE.
- */
-int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
-{
-        return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
-}
-EXPORT_SYMBOL(prcmu_set_ape_opp);
-
-/**
- * prcmu_set_cpu_opp() - Set the OPP of the CPU.
- * @opp:        The OPP to set.
- *
- * This function sets the OPP of the CPU.
- */
-int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
-{
-        return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
-}
-EXPORT_SYMBOL(prcmu_set_cpu_opp);
-
-/**
- * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
- * @ape_opp:    The APE OPP to set.
- * @cpu_opp:    The CPU OPP to set.
- *
- * This function sets the OPPs of the APE and the CPU.
- */
-int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
-                           enum prcmu_cpu_opp cpu_opp)
-{
-        return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
-}
-EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
-
-/**
- * prcmu_get_ape_opp() - Get the OPP of the APE.
- *
- * This function gets the OPP of the APE.
- */
-enum prcmu_ape_opp prcmu_get_ape_opp(void)
-{
-        return readb(ACK_MB1_CURR_APEOPP);
-}
-EXPORT_SYMBOL(prcmu_get_ape_opp);
-
-/**
- * prcmu_get_cpu_opp() - Get the OPP of the CPU.
- *
- * This function gets the OPP of the CPU. The OPP is specified in %%.
- * PRCMU_OPP_EXT is a special OPP value, not specified in %%.
- */
-int prcmu_get_cpu_opp(void)
-{
-        return readb(ACK_MB1_CURR_ARMOPP);
-}
-EXPORT_SYMBOL(prcmu_get_cpu_opp);
-
-bool prcmu_has_arm_maxopp(void)
-{
-        return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
-                == PRCM_AVS_ISMODEENABLE_MASK;
-}
-
-static void read_mailbox_0(void)
-{
-        writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_1(void)
-{
-        mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
-        mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
-        complete(&mb1_transfer.work);
-        writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_2(void)
-{
-        writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_3(void)
-{
-        writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_4(void)
-{
-        writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_5(void)
-{
-        mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
-        mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
-        complete(&mb5_transfer.work);
-        writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_6(void)
-{
-        writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_7(void)
-{
-        writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
-}
-
-static void (* const read_mailbox[NUM_MBOX])(void) = {
-        read_mailbox_0,
-        read_mailbox_1,
-        read_mailbox_2,
-        read_mailbox_3,
-        read_mailbox_4,
-        read_mailbox_5,
-        read_mailbox_6,
-        read_mailbox_7
-};
-
-static irqreturn_t prcmu_irq_handler(int irq, void *data)
-{
-        u32 bits;
-        u8 n;
-
-        bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
-        if (unlikely(!bits))
-                return IRQ_NONE;
-
-        for (n = 0; bits; n++) {
-                if (bits & MBOX_BIT(n)) {
-                        bits -= MBOX_BIT(n);
-                        read_mailbox[n]();
-                }
-        }
-        return IRQ_HANDLED;
-}
-
-void __init prcmu_early_init(void)
-{
-        if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
-                tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
-        } else if (cpu_is_u8500v2()) {
-                tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
-        } else {
-                pr_err("prcmu: Unsupported chip version\n");
-                BUG();
-        }
-}
-
-static int __init prcmu_init(void)
-{
-        if (cpu_is_u8500ed()) {
-                pr_err("prcmu: Unsupported chip version\n");
-                return 0;
-        }
-
-        mutex_init(&mb1_transfer.lock);
-        init_completion(&mb1_transfer.work);
-        mutex_init(&mb5_transfer.lock);
-        init_completion(&mb5_transfer.work);
-
-        /* Clean up the mailbox interrupts after pre-kernel code. */
-        writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
-
-        return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
-                           "prcmu", NULL);
-}
-
-arch_initcall(prcmu_init);
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index c96fa1b3f49f..73b4a8b66a57 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -176,6 +176,7 @@ ENDPROC(v6_coherent_kern_range)
  */
 ENTRY(v6_flush_kern_dcache_area)
         add     r1, r0, r1
+        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index dc18d81ef8ce..d32f02b61866 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -221,6 +221,8 @@ ENDPROC(v7_coherent_user_range)
 ENTRY(v7_flush_kern_dcache_area)
         dcache_line_size r2, r3
         add     r1, r0, r1
+        sub     r3, r2, #1
+        bic     r0, r0, r3
 1:
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line / unified line
         add     r0, r0, r2
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index b0ee9ba3cfab..8bfae964b133 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -24,9 +24,7 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
 
 /*
  * We fork()ed a process, and we need a new context for the child
- * to run in.  We reserve version 0 for initial tasks so we will
- * always allocate an ASID. The ASID 0 is reserved for the TTBR
- * register changing sequence.
+ * to run in.
  */
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
@@ -36,8 +34,11 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 
 static void flush_context(void)
 {
-        /* set the reserved ASID before flushing the TLB */
-        asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (0));
+        u32 ttb;
+        /* Copy TTBR1 into TTBR0 */
+        asm volatile("mrc       p15, 0, %0, c2, c0, 1\n"
+                     "mcr       p15, 0, %0, c2, c0, 0"
+                     : "=r" (ttb));
         isb();
         local_flush_tlb_all();
         if (icache_is_vivt_asid_tagged()) {
@@ -93,7 +94,7 @@ static void reset_context(void *info)
                 return;
 
         smp_rmb();
-        asid = cpu_last_asid + cpu + 1;
+        asid = cpu_last_asid + cpu;
 
         flush_context();
         set_mm_context(mm, asid);
@@ -143,13 +144,13 @@ void __new_context(struct mm_struct *mm)
          * to start a new version and flush the TLB.
          */
         if (unlikely((asid & ~ASID_MASK) == 0)) {
-                asid = cpu_last_asid + smp_processor_id() + 1;
+                asid = cpu_last_asid + smp_processor_id();
                 flush_context();
 #ifdef CONFIG_SMP
                 smp_wmb();
                 smp_call_function(reset_context, NULL, 1);
 #endif
-                cpu_last_asid += NR_CPUS;
+                cpu_last_asid += NR_CPUS - 1;
         }
 
         set_mm_context(mm, asid);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 76f82ae44efb..2c2cce9cd8c8 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -15,12 +15,14 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 #include <linux/initrd.h>
+#include <linux/of_fdt.h>
 #include <linux/highmem.h>
 #include <linux/gfp.h>
 #include <linux/memblock.h>
 #include <linux/sort.h>
 
 #include <asm/mach-types.h>
+#include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
 #include <asm/sizes.h>
@@ -71,6 +73,14 @@ static int __init parse_tag_initrd2(const struct tag *tag)
 
 __tagtable(ATAG_INITRD2, parse_tag_initrd2);
 
+#ifdef CONFIG_OF_FLATTREE
+void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end)
+{
+        phys_initrd_start = start;
+        phys_initrd_size = end - start;
+}
+#endif /* CONFIG_OF_FLATTREE */
+
 /*
  * This keeps memory configuration data used by a couple memory
  * initialization functions, as well as show_mem() for the skipping
@@ -85,7 +95,7 @@ void show_mem(unsigned int filter)
         struct meminfo * mi = &meminfo;
 
         printk("Mem-info:\n");
-        show_free_areas();
+        show_free_areas(filter);
 
         for_each_bank (i, mi) {
                 struct membank *bank = &mi->bank[i];
@@ -273,13 +283,15 @@ static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
         free_area_init_node(0, zone_size, min, zhole_size);
 }
 
-#ifndef CONFIG_SPARSEMEM
+#ifdef CONFIG_HAVE_ARCH_PFN_VALID
 int pfn_valid(unsigned long pfn)
 {
         return memblock_is_memory(pfn << PAGE_SHIFT);
 }
 EXPORT_SYMBOL(pfn_valid);
+#endif
 
+#ifndef CONFIG_SPARSEMEM
 static void arm_memory_present(void)
 {
 }
@@ -334,6 +346,7 @@ void __init arm_memblock_init(struct meminfo *mi, struct machine_desc *mdesc)
 #endif
 
         arm_mm_memblock_reserve();
+        arm_dt_memblock_reserve();
 
         /* reserve any platform specific memblock areas */
         if (mdesc->reserve)
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index d2384106af9c..5b3d7d543659 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -5,14 +5,9 @@ extern pmd_t *top_pmd;
 
 #define TOP_PTE(x)      pte_offset_kernel(top_pmd, x)
 
-static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
-{
-        return pmd_offset(pud_offset(pgd, virt), virt);
-}
-
 static inline pmd_t *pmd_off_k(unsigned long virt)
 {
-        return pmd_off(pgd_offset_k(virt), virt);
+        return pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
 }
 
 struct mem_type {
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6cf76b3b68d1..9d9e736c2b4f 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,8 +31,6 @@
 
 #include "mm.h"
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * empty_zero_page is a special page that is used for
  * zero-initialized data and COW.
@@ -765,15 +763,12 @@ static void __init sanity_check_meminfo(void)
 {
         int i, j, highmem = 0;
 
-        lowmem_limit = __pa(vmalloc_min - 1) + 1;
-        memblock_set_current_limit(lowmem_limit);
-
         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
                 struct membank *bank = &meminfo.bank[j];
                 *bank = meminfo.bank[i];
 
 #ifdef CONFIG_HIGHMEM
-                if (__va(bank->start) > vmalloc_min ||
+                if (__va(bank->start) >= vmalloc_min ||
                     __va(bank->start) < (void *)PAGE_OFFSET)
                         highmem = 1;
 
@@ -831,6 +826,9 @@ static void __init sanity_check_meminfo(void)
                         bank->size = newsize;
                 }
 #endif
+                if (!bank->highmem && bank->start + bank->size > lowmem_limit)
+                        lowmem_limit = bank->start + bank->size;
+
                 j++;
         }
 #ifdef CONFIG_HIGHMEM
@@ -854,6 +852,7 @@ static void __init sanity_check_meminfo(void)
         }
 #endif
         meminfo.nr_banks = j;
+        memblock_set_current_limit(lowmem_limit);
 }
 
 static inline void prepare_page_table(void)
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index ab17cc0d3fa7..1d2b8451bf25 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -213,7 +213,9 @@ __v6_setup:
         mcr     p15, 0, r0, c2, c0, 2           @ TTB control register
         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
-        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
+        ALT_SMP(orr     r8, r8, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
+        mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
 #endif /* CONFIG_MMU */
         adr     r5, v6_crval
         ldmia   r5, {r5, r6}
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index babfba09c89f..b3b566ec83d3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,18 +108,16 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_ARM_ERRATA_430973
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 #endif
-#ifdef CONFIG_ARM_ERRATA_754322
-        dsb
-#endif
-        mcr     p15, 0, r2, c13, c0, 1          @ set reserved context ID
-        isb
-1:      mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+        mrc     p15, 0, r2, c2, c0, 1           @ load TTB 1
+        mcr     p15, 0, r2, c2, c0, 0           @ into TTB 0
         isb
 #ifdef CONFIG_ARM_ERRATA_754322
         dsb
 #endif
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
         isb
+        mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+        isb
 #endif
         mov     pc, lr
 ENDPROC(cpu_v7_switch_mm)
@@ -368,7 +366,9 @@ __v7_setup:
         mcr     p15, 0, r10, c2, c0, 2          @ TTB control register
         ALT_SMP(orr     r4, r4, #TTB_FLAGS_SMP)
         ALT_UP(orr      r4, r4, #TTB_FLAGS_UP)
-        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
+        ALT_SMP(orr     r8, r8, #TTB_FLAGS_SMP)
+        ALT_UP(orr      r8, r8, #TTB_FLAGS_UP)
+        mcr     p15, 0, r8, c2, c0, 1           @ load TTB1
         ldr     r5, =PRRR                       @ PRRR
         ldr     r6, =NMRR                       @ NMRR
         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index 18296ee68802..ce659015535e 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -21,9 +21,4 @@ config HAS_MTU
           to multiple interrupt generating programmable
           32-bit free running decrementing counters.
 
-config NOMADIK_GPIO
-        bool
-        help
-          Support for the Nomadik GPIO controller.
-
 endif
diff --git a/arch/arm/plat-nomadik/Makefile b/arch/arm/plat-nomadik/Makefile
index c33547361bd7..37c7cdd0f8f0 100644
--- a/arch/arm/plat-nomadik/Makefile
+++ b/arch/arm/plat-nomadik/Makefile
@@ -3,4 +3,3 @@
 # Licensed under GPLv2
 
 obj-$(CONFIG_HAS_MTU)   += timer.o
-obj-$(CONFIG_NOMADIK_GPIO)      += gpio.o
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
deleted file mode 100644
index 307b8131aa8c..000000000000
--- a/arch/arm/plat-nomadik/gpio.c
+++ /dev/null
@@ -1,1020 +0,0 @@
-/*
- * Generic GPIO driver for logic cells found in the Nomadik SoC
- *
- * Copyright (C) 2008,2009 STMicroelectronics
- * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
- *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/gpio.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/slab.h>
-
-#include <asm/mach/irq.h>
-
-#include <plat/pincfg.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-
-/*
- * The GPIO module in the Nomadik family of Systems-on-Chip is an
- * AMBA device, managing 32 pins and alternate functions.  The logic block
- * is currently used in the Nomadik and ux500.
- *
- * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
- */
-
-#define NMK_GPIO_PER_CHIP       32
-
-struct nmk_gpio_chip {
-        struct gpio_chip chip;
-        void __iomem *addr;
-        struct clk *clk;
-        unsigned int bank;
-        unsigned int parent_irq;
-        int secondary_parent_irq;
-        u32 (*get_secondary_status)(unsigned int bank);
-        void (*set_ioforce)(bool enable);
-        spinlock_t lock;
-        /* Keep track of configured edges */
-        u32 edge_rising;
-        u32 edge_falling;
-        u32 real_wake;
-        u32 rwimsc;
-        u32 fwimsc;
-        u32 slpm;
-        u32 enabled;
-};
-
-static struct nmk_gpio_chip *
-nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
-
-static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
-
-#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
-
-static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
-                                unsigned offset, int gpio_mode)
-{
-        u32 bit = 1 << offset;
-        u32 afunc, bfunc;
-
-        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
-        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
-        if (gpio_mode & NMK_GPIO_ALT_A)
-                afunc |= bit;
-        if (gpio_mode & NMK_GPIO_ALT_B)
-                bfunc |= bit;
-        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
-        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
-}
-
-static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
-                                unsigned offset, enum nmk_gpio_slpm mode)
-{
-        u32 bit = 1 << offset;
-        u32 slpm;
-
-        slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
-        if (mode == NMK_GPIO_SLPM_NOCHANGE)
-                slpm |= bit;
-        else
-                slpm &= ~bit;
-        writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
-}
-
-static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
-                                unsigned offset, enum nmk_gpio_pull pull)
-{
-        u32 bit = 1 << offset;
-        u32 pdis;
-
-        pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
-        if (pull == NMK_GPIO_PULL_NONE)
-                pdis |= bit;
-        else
-                pdis &= ~bit;
-        writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
-
-        if (pull == NMK_GPIO_PULL_UP)
-                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
-        else if (pull == NMK_GPIO_PULL_DOWN)
-                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
-}
-
-static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
-                                  unsigned offset)
-{
-        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
-}
-
-static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
-                                  unsigned offset, int val)
-{
-        if (val)
-                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
-        else
-                writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
-}
-
-static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
-                                  unsigned offset, int val)
-{
-        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
-        __nmk_gpio_set_output(nmk_chip, offset, val);
-}
-
-static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
-                                     unsigned offset, int gpio_mode,
-                                     bool glitch)
-{
-        u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
-        u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
-
-        if (glitch && nmk_chip->set_ioforce) {
-                u32 bit = BIT(offset);
-
-                /* Prevent spurious wakeups */
-                writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
-                writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
-
-                nmk_chip->set_ioforce(true);
-        }
-
-        __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
-
-        if (glitch && nmk_chip->set_ioforce) {
-                nmk_chip->set_ioforce(false);
-
-                writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
-                writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
-        }
-}
-
-static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
-                             pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
-{
-        static const char *afnames[] = {
-                [NMK_GPIO_ALT_GPIO]     = "GPIO",
-                [NMK_GPIO_ALT_A]        = "A",
-                [NMK_GPIO_ALT_B]        = "B",
-                [NMK_GPIO_ALT_C]        = "C"
-        };
-        static const char *pullnames[] = {
-                [NMK_GPIO_PULL_NONE]    = "none",
-                [NMK_GPIO_PULL_UP]      = "up",
-                [NMK_GPIO_PULL_DOWN]    = "down",
-                [3] /* illegal */       = "??"
-        };
-        static const char *slpmnames[] = {
-                [NMK_GPIO_SLPM_INPUT]           = "input/wakeup",
-                [NMK_GPIO_SLPM_NOCHANGE]        = "no-change/no-wakeup",
-        };
-
-        int pin = PIN_NUM(cfg);
-        int pull = PIN_PULL(cfg);
-        int af = PIN_ALT(cfg);
-        int slpm = PIN_SLPM(cfg);
-        int output = PIN_DIR(cfg);
-        int val = PIN_VAL(cfg);
-        bool glitch = af == NMK_GPIO_ALT_C;
-
-        dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
-                pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
-                output ? "output " : "input",
-                output ? (val ? "high" : "low") : "");
-
-        if (sleep) {
-                int slpm_pull = PIN_SLPM_PULL(cfg);
-                int slpm_output = PIN_SLPM_DIR(cfg);
-                int slpm_val = PIN_SLPM_VAL(cfg);
-
-                af = NMK_GPIO_ALT_GPIO;
-
-                /*
-                 * The SLPM_* values are normal values + 1 to allow zero to
-                 * mean "same as normal".
-                 */
-                if (slpm_pull)
-                        pull = slpm_pull - 1;
-                if (slpm_output)
-                        output = slpm_output - 1;
-                if (slpm_val)
-                        val = slpm_val - 1;
-
-                dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
-                        pin,
-                        slpm_pull ? pullnames[pull] : "same",
-                        slpm_output ? (output ? "output" : "input") : "same",
-                        slpm_val ? (val ? "high" : "low") : "same");
-        }
-
-        if (output)
-                __nmk_gpio_make_output(nmk_chip, offset, val);
-        else {
-                __nmk_gpio_make_input(nmk_chip, offset);
-                __nmk_gpio_set_pull(nmk_chip, offset, pull);
-        }
-
-        /*
-         * If we've backed up the SLPM registers (glitch workaround), modify
-         * the backups since they will be restored.
-         */
-        if (slpmregs) {
-                if (slpm == NMK_GPIO_SLPM_NOCHANGE)
-                        slpmregs[nmk_chip->bank] |= BIT(offset);
-                else
-                        slpmregs[nmk_chip->bank] &= ~BIT(offset);
-        } else
-                __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
-
-        __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
-}
-
-/*
- * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
- *  - Save SLPM registers
- *  - Set SLPM=0 for the IOs you want to switch and others to 1
- *  - Configure the GPIO registers for the IOs that are being switched
- *  - Set IOFORCE=1
- *  - Modify the AFLSA/B registers for the IOs that are being switched
- *  - Set IOFORCE=0
- *  - Restore SLPM registers
- *  - Any spurious wake up event during switch sequence to be ignored and
- *    cleared
- */
-static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
-{
-        int i;
-
-        for (i = 0; i < NUM_BANKS; i++) {
-                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-                unsigned int temp = slpm[i];
-
-                if (!chip)
-                        break;
-
-                slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
-                writel(temp, chip->addr + NMK_GPIO_SLPC);
-        }
-}
-
-static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
-{
-        int i;
-
-        for (i = 0; i < NUM_BANKS; i++) {
-                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
-                if (!chip)
-                        break;
-
-                writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
-        }
-}
-
-static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
-{
-        static unsigned int slpm[NUM_BANKS];
-        unsigned long flags;
-        bool glitch = false;
-        int ret = 0;
-        int i;
-
-        for (i = 0; i < num; i++) {
-                if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
-                        glitch = true;
-                        break;
-                }
-        }
-
-        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
-
-        if (glitch) {
-                memset(slpm, 0xff, sizeof(slpm));
-
-                for (i = 0; i < num; i++) {
-                        int pin = PIN_NUM(cfgs[i]);
-                        int offset = pin % NMK_GPIO_PER_CHIP;
-
-                        if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
-                                slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
-                }
-
-                nmk_gpio_glitch_slpm_init(slpm);
-        }
-
-        for (i = 0; i < num; i++) {
-                struct nmk_gpio_chip *nmk_chip;
-                int pin = PIN_NUM(cfgs[i]);
-
-                nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
-                if (!nmk_chip) {
-                        ret = -EINVAL;
-                        break;
-                }
-
-                spin_lock(&nmk_chip->lock);
-                __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base,
-                                 cfgs[i], sleep, glitch ? slpm : NULL);
-                spin_unlock(&nmk_chip->lock);
-        }
-
-        if (glitch)
-                nmk_gpio_glitch_slpm_restore(slpm);
-
-        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
-
-        return ret;
-}
-
-/**
- * nmk_config_pin - configure a pin's mux attributes
- * @cfg: pin confguration
- *
- * Configures a pin's mode (alternate function or GPIO), its pull up status,
- * and its sleep mode based on the specified configuration.  The @cfg is
- * usually one of the SoC specific macros defined in mach/<soc>-pins.h.  These
- * are constructed using, and can be further enhanced with, the macros in
- * plat/pincfg.h.
- *
- * If a pin's mode is set to GPIO, it is configured as an input to avoid
- * side-effects.  The gpio can be manipulated later using standard GPIO API
- * calls.
- */
-int nmk_config_pin(pin_cfg_t cfg, bool sleep)
-{
-        return __nmk_config_pins(&cfg, 1, sleep);
-}
-EXPORT_SYMBOL(nmk_config_pin);
-
-/**
- * nmk_config_pins - configure several pins at once
- * @cfgs: array of pin configurations
- * @num: number of elments in the array
- *
- * Configures several pins using nmk_config_pin().  Refer to that function for
- * further information.
- */
-int nmk_config_pins(pin_cfg_t *cfgs, int num)
-{
-        return __nmk_config_pins(cfgs, num, false);
-}
-EXPORT_SYMBOL(nmk_config_pins);
-
-int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
-{
-        return __nmk_config_pins(cfgs, num, true);
-}
-EXPORT_SYMBOL(nmk_config_pins_sleep);
-
-/**
- * nmk_gpio_set_slpm() - configure the sleep mode of a pin
- * @gpio: pin number
- * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
- *
- * Sets the sleep mode of a pin.  If @mode is NMK_GPIO_SLPM_INPUT, the pin is
- * changed to an input (with pullup/down enabled) in sleep and deep sleep.  If
- * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was
- * configured even when in sleep and deep sleep.
- *
- * On DB8500v2 onwards, this setting loses the previous meaning and instead
- * indicates if wakeup detection is enabled on the pin.  Note that
- * enable_irq_wake() will automatically enable wakeup detection.
- */
-int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        unsigned long flags;
-
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
-        if (!nmk_chip)
-                return -EINVAL;
-
-        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
-        spin_lock(&nmk_chip->lock);
-
-        __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode);
-
-        spin_unlock(&nmk_chip->lock);
-        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
-
-        return 0;
-}
-
-/**
- * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
- * @gpio: pin number
- * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
- *
- * Enables/disables pull up/down on a specified pin.  This only takes effect if
- * the pin is configured as an input (either explicitly or by the alternate
- * function).
- *
- * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
- * configured as an input.  Otherwise, due to the way the controller registers
- * work, this function will change the value output on the pin.
- */
-int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        unsigned long flags;
-
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
-        if (!nmk_chip)
-                return -EINVAL;
-
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
-
-        return 0;
-}
-
-/* Mode functions */
-/**
- * nmk_gpio_set_mode() - set the mux mode of a gpio pin
- * @gpio: pin number
- * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
- *             NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
- *
- * Sets the mode of the specified pin to one of the alternate functions or
- * plain GPIO.
- */
-int nmk_gpio_set_mode(int gpio, int gpio_mode)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        unsigned long flags;
-
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
-        if (!nmk_chip)
-                return -EINVAL;
-
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode);
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(nmk_gpio_set_mode);
-
-int nmk_gpio_get_mode(int gpio)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        u32 afunc, bfunc, bit;
-
-        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
-        if (!nmk_chip)
-                return -EINVAL;
-
-        bit = 1 << (gpio - nmk_chip->chip.base);
-
-        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
-        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
-
-        return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
-}
-EXPORT_SYMBOL(nmk_gpio_get_mode);
-
-
-/* IRQ functions */
-static inline int nmk_gpio_get_bitmask(int gpio)
-{
-        return 1 << (gpio % 32);
-}
-
-static void nmk_gpio_irq_ack(struct irq_data *d)
-{
-        int gpio;
-        struct nmk_gpio_chip *nmk_chip;
-
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
-        nmk_chip = irq_data_get_irq_chip_data(d);
-        if (!nmk_chip)
-                return;
-        writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
-}
-
-enum nmk_gpio_irq_type {
-        NORMAL,
-        WAKE,
-};
-
-static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
-                                  int gpio, enum nmk_gpio_irq_type which,
-                                  bool enable)
-{
-        u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
-        u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
-        u32 bitmask = nmk_gpio_get_bitmask(gpio);
-        u32 reg;
-
-        /* we must individually set/clear the two edges */
-        if (nmk_chip->edge_rising & bitmask) {
-                reg = readl(nmk_chip->addr + rimsc);
-                if (enable)
-                        reg |= bitmask;
-                else
-                        reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + rimsc);
-        }
-        if (nmk_chip->edge_falling & bitmask) {
-                reg = readl(nmk_chip->addr + fimsc);
-                if (enable)
-                        reg |= bitmask;
-                else
-                        reg &= ~bitmask;
-                writel(reg, nmk_chip->addr + fimsc);
-        }
-}
-
-static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
-                                int gpio, bool on)
-{
-        __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
-}
-
-static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
-{
-        int gpio;
-        struct nmk_gpio_chip *nmk_chip;
-        unsigned long flags;
-        u32 bitmask;
-
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
-        nmk_chip = irq_data_get_irq_chip_data(d);
-        bitmask = nmk_gpio_get_bitmask(gpio);
-        if (!nmk_chip)
-                return -EINVAL;
-
-        if (enable)
-                nmk_chip->enabled |= bitmask;
-        else
-                nmk_chip->enabled &= ~bitmask;
-
-        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
-        spin_lock(&nmk_chip->lock);
-
-        __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable);
-
-        if (!(nmk_chip->real_wake & bitmask))
-                __nmk_gpio_set_wake(nmk_chip, gpio, enable);
-
-        spin_unlock(&nmk_chip->lock);
-        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
-
-        return 0;
-}
-
-static void nmk_gpio_irq_mask(struct irq_data *d)
-{
-        nmk_gpio_irq_maskunmask(d, false);
-}
-
-static void nmk_gpio_irq_unmask(struct irq_data *d)
-{
-        nmk_gpio_irq_maskunmask(d, true);
-}
-
-static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        unsigned long flags;
-        u32 bitmask;
-        int gpio;
-
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
-        nmk_chip = irq_data_get_irq_chip_data(d);
-        if (!nmk_chip)
-                return -EINVAL;
-        bitmask = nmk_gpio_get_bitmask(gpio);
-
-        spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
-        spin_lock(&nmk_chip->lock);
-
-        if (!(nmk_chip->enabled & bitmask))
-                __nmk_gpio_set_wake(nmk_chip, gpio, on);
-
-        if (on)
-                nmk_chip->real_wake |= bitmask;
-        else
-                nmk_chip->real_wake &= ~bitmask;
-
-        spin_unlock(&nmk_chip->lock);
-        spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
-
-        return 0;
-}
-
-static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
-{
-        bool enabled, wake = irqd_is_wakeup_set(d);
-        int gpio;
-        struct nmk_gpio_chip *nmk_chip;
-        unsigned long flags;
-        u32 bitmask;
-
-        gpio = NOMADIK_IRQ_TO_GPIO(d->irq);
-        nmk_chip = irq_data_get_irq_chip_data(d);
-        bitmask = nmk_gpio_get_bitmask(gpio);
-        if (!nmk_chip)
-                return -EINVAL;
-
-        if (type & IRQ_TYPE_LEVEL_HIGH)
-                return -EINVAL;
-        if (type & IRQ_TYPE_LEVEL_LOW)
-                return -EINVAL;
-
-        enabled = nmk_chip->enabled & bitmask;
-
-        spin_lock_irqsave(&nmk_chip->lock, flags);
-
-        if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
-
-        if (enabled || wake)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
-
-        nmk_chip->edge_rising &= ~bitmask;
-        if (type & IRQ_TYPE_EDGE_RISING)
-                nmk_chip->edge_rising |= bitmask;
-
-        nmk_chip->edge_falling &= ~bitmask;
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                nmk_chip->edge_falling |= bitmask;
-
-        if (enabled)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
-
-        if (enabled || wake)
-                __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
-
-        spin_unlock_irqrestore(&nmk_chip->lock, flags);
-
-        return 0;
-}
-
-static struct irq_chip nmk_gpio_irq_chip = {
-        .name           = "Nomadik-GPIO",
-        .irq_ack        = nmk_gpio_irq_ack,
-        .irq_mask       = nmk_gpio_irq_mask,
-        .irq_unmask     = nmk_gpio_irq_unmask,
-        .irq_set_type   = nmk_gpio_irq_set_type,
-        .irq_set_wake   = nmk_gpio_irq_set_wake,
-};
-
-static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
-                                   u32 status)
-{
-        struct nmk_gpio_chip *nmk_chip;
-        struct irq_chip *host_chip = irq_get_chip(irq);
-        unsigned int first_irq;
-
-        chained_irq_enter(host_chip, desc);
-
-        nmk_chip = irq_get_handler_data(irq);
-        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        while (status) {
-                int bit = __ffs(status);
-
-                generic_handle_irq(first_irq + bit);
-                status &= ~BIT(bit);
-        }
-
-        chained_irq_exit(host_chip, desc);
-}
-
-static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
-        u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
-
-        __nmk_gpio_irq_handler(irq, desc, status);
-}
-
-static void nmk_gpio_secondary_irq_handler(unsigned int irq,
-                                           struct irq_desc *desc)
-{
-        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
-        u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
-
-        __nmk_gpio_irq_handler(irq, desc, status);
-}
-
-static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
-{
-        unsigned int first_irq;
-        int i;
-
-        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
-        for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
-                irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
-                                         handle_edge_irq);
-                set_irq_flags(i, IRQF_VALID);
-                irq_set_chip_data(i, nmk_chip);
-                irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
-        }
-
-        irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
-        irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
-
-        if (nmk_chip->secondary_parent_irq >= 0) {
-                irq_set_chained_handler(nmk_chip->secondary_parent_irq,
-                                        nmk_gpio_secondary_irq_handler);
-                irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
-        }
-
-        return 0;
-}
-
-/* I/O Functions */
-static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-
-        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
-        return 0;
-}
-
-static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-        u32 bit = 1 << offset;
-
-        return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
-}
-
-static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
-                                int val)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-
-        __nmk_gpio_set_output(nmk_chip, offset, val);
-}
-
-static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
-                                int val)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-
-        __nmk_gpio_make_output(nmk_chip, offset, val);
-
-        return 0;
-}
-
-static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-
-        return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
-}
-
-#ifdef CONFIG_DEBUG_FS
-
-#include <linux/seq_file.h>
-
-static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
-        int mode;
-        unsigned                i;
-        unsigned                gpio = chip->base;
-        int                     is_out;
-        struct nmk_gpio_chip *nmk_chip =
-                container_of(chip, struct nmk_gpio_chip, chip);
-        const char *modes[] = {
-                [NMK_GPIO_ALT_GPIO]     = "gpio",
-                [NMK_GPIO_ALT_A]        = "altA",
-                [NMK_GPIO_ALT_B]        = "altB",
-                [NMK_GPIO_ALT_C]        = "altC",
-        };
-
-        for (i = 0; i < chip->ngpio; i++, gpio++) {
-                const char *label = gpiochip_is_requested(chip, i);
-                bool pull;
-                u32 bit = 1 << i;
-
-                if (!label)
-                        continue;
-
-                is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit;
-                pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
-                mode = nmk_gpio_get_mode(gpio);
-                seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
-                        gpio, label,
-                        is_out ? "out" : "in ",
-                        chip->get
-                                ? (chip->get(chip, i) ? "hi" : "lo")
-                                : "?  ",
-                        (mode < 0) ? "unknown" : modes[mode],
-                        pull ? "pull" : "none");
-                seq_printf(s, "\n");
-        }
-}
-
-#else
-#define nmk_gpio_dbg_show       NULL
-#endif
-
-/* This structure is replicated for each GPIO block allocated at probe time */
-static struct gpio_chip nmk_gpio_template = {
-        .direction_input        = nmk_gpio_make_input,
-        .get                    = nmk_gpio_get_input,
-        .direction_output       = nmk_gpio_make_output,
-        .set                    = nmk_gpio_set_output,
-        .to_irq                 = nmk_gpio_to_irq,
-        .dbg_show               = nmk_gpio_dbg_show,
-        .can_sleep              = 0,
-};
-
-/*
- * Called from the suspend/resume path to only keep the real wakeup interrupts
- * (those that have had set_irq_wake() called on them) as wakeup interrupts,
- * and not the rest of the interrupts which we needed to have as wakeups for
- * cpuidle.
- *
- * PM ops are not used since this needs to be done at the end, after all the
- * other drivers are done with their suspend callbacks.
- */
-void nmk_gpio_wakeups_suspend(void)
-{
-        int i;
-
-        for (i = 0; i < NUM_BANKS; i++) {
-                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
-                if (!chip)
-                        break;
-
-                chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
-                chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
-
-                writel(chip->rwimsc & chip->real_wake,
-                       chip->addr + NMK_GPIO_RWIMSC);
-                writel(chip->fwimsc & chip->real_wake,
-                       chip->addr + NMK_GPIO_FWIMSC);
-
-                if (cpu_is_u8500v2()) {
-                        chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
-
-                        /* 0 -> wakeup enable */
-                        writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
-                }
-        }
-}
-
-void nmk_gpio_wakeups_resume(void)
-{
-        int i;
-
-        for (i = 0; i < NUM_BANKS; i++) {
-                struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
-
-                if (!chip)
-                        break;
-
-                writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
-                writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
-
-                if (cpu_is_u8500v2())
-                        writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
-        }
-}
-
-static int __devinit nmk_gpio_probe(struct platform_device *dev)
-{
-        struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
-        struct nmk_gpio_chip *nmk_chip;
-        struct gpio_chip *chip;
-        struct resource *res;
-        struct clk *clk;
-        int secondary_irq;
-        int irq;
-        int ret;
-
-        if (!pdata)
-                return -ENODEV;
-
-        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-        if (!res) {
-                ret = -ENOENT;
-                goto out;
-        }
-
-        irq = platform_get_irq(dev, 0);
-        if (irq < 0) {
-                ret = irq;
-                goto out;
-        }
-
-        secondary_irq = platform_get_irq(dev, 1);
-        if (secondary_irq >= 0 && !pdata->get_secondary_status) {
-                ret = -EINVAL;
-                goto out;
-        }
-
-        if (request_mem_region(res->start, resource_size(res),
-                               dev_name(&dev->dev)) == NULL) {
-                ret = -EBUSY;
-                goto out;
-        }
-
-        clk = clk_get(&dev->dev, NULL);
-        if (IS_ERR(clk)) {
-                ret = PTR_ERR(clk);
-                goto out_release;
-        }
-
-        clk_enable(clk);
-
-        nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
-        if (!nmk_chip) {
-                ret = -ENOMEM;
-                goto out_clk;
-        }
-        /*
-         * The virt address in nmk_chip->addr is in the nomadik register space,
-         * so we can simply convert the resource address, without remapping
-         */
-        nmk_chip->bank = dev->id;
-        nmk_chip->clk = clk;
-        nmk_chip->addr = io_p2v(res->start);
-        nmk_chip->chip = nmk_gpio_template;
-        nmk_chip->parent_irq = irq;
-        nmk_chip->secondary_parent_irq = secondary_irq;
-        nmk_chip->get_secondary_status = pdata->get_secondary_status;
-        nmk_chip->set_ioforce = pdata->set_ioforce;
-        spin_lock_init(&nmk_chip->lock);
-
-        chip = &nmk_chip->chip;
-        chip->base = pdata->first_gpio;
-        chip->ngpio = pdata->num_gpio;
-        chip->label = pdata->name ?: dev_name(&dev->dev);
-        chip->dev = &dev->dev;
-        chip->owner = THIS_MODULE;
-
-        ret = gpiochip_add(&nmk_chip->chip);
-        if (ret)
-                goto out_free;
-
-        BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
-
-        nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
-        platform_set_drvdata(dev, nmk_chip);
-
-        nmk_gpio_init_irq(nmk_chip);
-
-        dev_info(&dev->dev, "Bits %i-%i at address %p\n",
-                 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
-        return 0;
-
-out_free:
-        kfree(nmk_chip);
-out_clk:
-        clk_disable(clk);
-        clk_put(clk);
-out_release:
-        release_mem_region(res->start, resource_size(res));
-out:
-        dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
-                  pdata->first_gpio, pdata->first_gpio+31);
-        return ret;
-}
-
-static struct platform_driver nmk_gpio_driver = {
-        .driver = {
-                .owner = THIS_MODULE,
-                .name = "gpio",
-        },
-        .probe = nmk_gpio_probe,
-};
-
-static int __init nmk_gpio_init(void)
-{
-        return platform_driver_register(&nmk_gpio_driver);
-}
-
-core_initcall(nmk_gpio_init);
-
-MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
-MODULE_DESCRIPTION("Nomadik GPIO Driver");
-MODULE_LICENSE("GPL");
-
-
diff --git a/arch/arm/plat-nomadik/include/plat/gpio.h b/arch/arm/plat-nomadik/include/plat/gpio.h
index 1b9f6f0843d1..ea19a5b2f227 100644
--- a/arch/arm/plat-nomadik/include/plat/gpio.h
+++ b/arch/arm/plat-nomadik/include/plat/gpio.h
@@ -78,6 +78,8 @@ extern int nmk_gpio_get_mode(int gpio);
 extern void nmk_gpio_wakeups_suspend(void);
 extern void nmk_gpio_wakeups_resume(void);
 
+extern void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up);
+
 /*
  * Platform data to register a block: only the initial gpio/irq number.
  */
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h
index 1621db67a53d..8ba70ffc31ec 100644
--- a/arch/arm/plat-nomadik/include/plat/i2c.h
+++ b/arch/arm/plat-nomadik/include/plat/i2c.h
@@ -11,8 +11,8 @@
 enum i2c_freq_mode {
         I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
         I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
+        I2C_FREQ_MODE_HIGH_SPEED,       /* up to 3.4 Mb/s */
         I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
-        I2C_FREQ_MODE_HIGH_SPEED        /* up to 3.4 Mb/s */
 };
 
 /**
@@ -24,13 +24,15 @@ enum i2c_freq_mode {
  *              to the values of 14, 6, 2 for a 48 MHz i2c clk
  * @tft:        Tx FIFO Threshold in bytes
  * @rft:        Rx FIFO Threshold in bytes
+ * @timeout     Slave response timeout(ms)
  * @sm:         speed mode
  */
 struct nmk_i2c_controller {
         unsigned long   clk_freq;
         unsigned short  slsu;
-        unsigned char   tft;
-        unsigned char   rft;
+        unsigned char   tft;
+        unsigned char   rft;
+        int timeout;
         enum i2c_freq_mode      sm;
 };
 
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index a4a12859fdd5..f0233e6abcdf 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
 #
 
 # Common support
-obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
+obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
          usb.o fb.o io.o counter_32k.o
 obj-m :=
 obj-n :=
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
deleted file mode 100644
index efb869390199..000000000000
--- a/arch/arm/plat-omap/gpio.c
+++ /dev/null
@@ -1,2112 +0,0 @@
-/*
- *  linux/arch/arm/plat-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- *
- * Copyright (C) 2009 Texas Instruments
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/syscore_ops.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/pm_runtime.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <mach/gpio.h>
-#include <asm/mach/irq.h>
-
-/*
- * OMAP1510 GPIO registers
- */
-#define OMAP1510_GPIO_DATA_INPUT        0x00
-#define OMAP1510_GPIO_DATA_OUTPUT       0x04
-#define OMAP1510_GPIO_DIR_CONTROL       0x08
-#define OMAP1510_GPIO_INT_CONTROL       0x0c
-#define OMAP1510_GPIO_INT_MASK          0x10
-#define OMAP1510_GPIO_INT_STATUS        0x14
-#define OMAP1510_GPIO_PIN_CONTROL       0x18
-
-#define OMAP1510_IH_GPIO_BASE           64
-
-/*
- * OMAP1610 specific GPIO registers
- */
-#define OMAP1610_GPIO_REVISION          0x0000
-#define OMAP1610_GPIO_SYSCONFIG         0x0010
-#define OMAP1610_GPIO_SYSSTATUS         0x0014
-#define OMAP1610_GPIO_IRQSTATUS1        0x0018
-#define OMAP1610_GPIO_IRQENABLE1        0x001c
-#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
-#define OMAP1610_GPIO_DATAIN            0x002c
-#define OMAP1610_GPIO_DATAOUT           0x0030
-#define OMAP1610_GPIO_DIRECTION         0x0034
-#define OMAP1610_GPIO_EDGE_CTRL1        0x0038
-#define OMAP1610_GPIO_EDGE_CTRL2        0x003c
-#define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
-#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
-#define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
-#define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
-#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
-#define OMAP1610_GPIO_SET_DATAOUT       0x00f0
-
-/*
- * OMAP7XX specific GPIO registers
- */
-#define OMAP7XX_GPIO_DATA_INPUT         0x00
-#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
-#define OMAP7XX_GPIO_DIR_CONTROL        0x08
-#define OMAP7XX_GPIO_INT_CONTROL        0x0c
-#define OMAP7XX_GPIO_INT_MASK           0x10
-#define OMAP7XX_GPIO_INT_STATUS         0x14
-
-/*
- * omap2+ specific GPIO registers
- */
-#define OMAP24XX_GPIO_REVISION          0x0000
-#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2        0x0028
-#define OMAP24XX_GPIO_IRQENABLE2        0x002c
-#define OMAP24XX_GPIO_IRQENABLE1        0x001c
-#define OMAP24XX_GPIO_WAKE_EN           0x0020
-#define OMAP24XX_GPIO_CTRL              0x0030
-#define OMAP24XX_GPIO_OE                0x0034
-#define OMAP24XX_GPIO_DATAIN            0x0038
-#define OMAP24XX_GPIO_DATAOUT           0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
-#define OMAP24XX_GPIO_RISINGDETECT      0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN       0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL      0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
-#define OMAP24XX_GPIO_SETWKUENA         0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
-#define OMAP24XX_GPIO_SETDATAOUT        0x0094
-
-#define OMAP4_GPIO_REVISION             0x0000
-#define OMAP4_GPIO_EOI                  0x0020
-#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
-#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
-#define OMAP4_GPIO_IRQSTATUS0           0x002c
-#define OMAP4_GPIO_IRQSTATUS1           0x0030
-#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
-#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
-#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
-#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
-#define OMAP4_GPIO_IRQWAKEN0            0x0044
-#define OMAP4_GPIO_IRQWAKEN1            0x0048
-#define OMAP4_GPIO_IRQENABLE1           0x011c
-#define OMAP4_GPIO_WAKE_EN              0x0120
-#define OMAP4_GPIO_IRQSTATUS2           0x0128
-#define OMAP4_GPIO_IRQENABLE2           0x012c
-#define OMAP4_GPIO_CTRL                 0x0130
-#define OMAP4_GPIO_OE                   0x0134
-#define OMAP4_GPIO_DATAIN               0x0138
-#define OMAP4_GPIO_DATAOUT              0x013c
-#define OMAP4_GPIO_LEVELDETECT0         0x0140
-#define OMAP4_GPIO_LEVELDETECT1         0x0144
-#define OMAP4_GPIO_RISINGDETECT         0x0148
-#define OMAP4_GPIO_FALLINGDETECT        0x014c
-#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
-#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
-#define OMAP4_GPIO_CLEARIRQENABLE1      0x0160
-#define OMAP4_GPIO_SETIRQENABLE1        0x0164
-#define OMAP4_GPIO_CLEARWKUENA          0x0180
-#define OMAP4_GPIO_SETWKUENA            0x0184
-#define OMAP4_GPIO_CLEARDATAOUT         0x0190
-#define OMAP4_GPIO_SETDATAOUT           0x0194
-
-struct gpio_bank {
-        unsigned long pbase;
-        void __iomem *base;
-        u16 irq;
-        u16 virtual_irq_start;
-        int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-        u32 suspend_wakeup;
-        u32 saved_wakeup;
-#endif
-        u32 non_wakeup_gpios;
-        u32 enabled_non_wakeup_gpios;
-
-        u32 saved_datain;
-        u32 saved_fallingdetect;
-        u32 saved_risingdetect;
-        u32 level_mask;
-        u32 toggle_mask;
-        spinlock_t lock;
-        struct gpio_chip chip;
-        struct clk *dbck;
-        u32 mod_usage;
-        u32 dbck_enable_mask;
-        struct device *dev;
-        bool dbck_flag;
-        int stride;
-};
-
-#ifdef CONFIG_ARCH_OMAP3
-struct omap3_gpio_regs {
-        u32 irqenable1;
-        u32 irqenable2;
-        u32 wake_en;
-        u32 ctrl;
-        u32 oe;
-        u32 leveldetect0;
-        u32 leveldetect1;
-        u32 risingdetect;
-        u32 fallingdetect;
-        u32 dataout;
-};
-
-static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
-#endif
-
-/*
- * TODO: Cleanup gpio_bank usage as it is having information
- * related to all instances of the device
- */
-static struct gpio_bank *gpio_bank;
-
-static int bank_width;
-
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-int gpio_bank_count;
-
-static inline struct gpio_bank *get_gpio_bank(int gpio)
-{
-        if (cpu_is_omap15xx()) {
-                if (OMAP_GPIO_IS_MPUIO(gpio))
-                        return &gpio_bank[0];
-                return &gpio_bank[1];
-        }
-        if (cpu_is_omap16xx()) {
-                if (OMAP_GPIO_IS_MPUIO(gpio))
-                        return &gpio_bank[0];
-                return &gpio_bank[1 + (gpio >> 4)];
-        }
-        if (cpu_is_omap7xx()) {
-                if (OMAP_GPIO_IS_MPUIO(gpio))
-                        return &gpio_bank[0];
-                return &gpio_bank[1 + (gpio >> 5)];
-        }
-        if (cpu_is_omap24xx())
-                return &gpio_bank[gpio >> 5];
-        if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                return &gpio_bank[gpio >> 5];
-        BUG();
-        return NULL;
-}
-
-static inline int get_gpio_index(int gpio)
-{
-        if (cpu_is_omap7xx())
-                return gpio & 0x1f;
-        if (cpu_is_omap24xx())
-                return gpio & 0x1f;
-        if (cpu_is_omap34xx() || cpu_is_omap44xx())
-                return gpio & 0x1f;
-        return gpio & 0x0f;
-}
-
-static inline int gpio_valid(int gpio)
-{
-        if (gpio < 0)
-                return -1;
-        if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
-                if (gpio >= OMAP_MAX_GPIO_LINES + 16)
-                        return -1;
-                return 0;
-        }
-        if (cpu_is_omap15xx() && gpio < 16)
-                return 0;
-        if ((cpu_is_omap16xx()) && gpio < 64)
-                return 0;
-        if (cpu_is_omap7xx() && gpio < 192)
-                return 0;
-        if (cpu_is_omap2420() && gpio < 128)
-                return 0;
-        if (cpu_is_omap2430() && gpio < 160)
-                return 0;
-        if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
-                return 0;
-        return -1;
-}
-
-static int check_gpio(int gpio)
-{
-        if (unlikely(gpio_valid(gpio) < 0)) {
-                printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
-                dump_stack();
-                return -1;
-        }
-        return 0;
-}
-
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
-{
-        void __iomem *reg = bank->base;
-        u32 l;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL / bank->stride;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DIR_CONTROL;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_OE;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        l = __raw_readl(reg);
-        if (is_input)
-                l |= 1 << gpio;
-        else
-                l &= ~(1 << gpio);
-        __raw_writel(l, reg);
-}
-
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
-{
-        void __iomem *reg = bank->base;
-        u32 l = 0;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_OUTPUT / bank->stride;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DATA_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                if (enable)
-                        reg += OMAP1610_GPIO_SET_DATAOUT;
-                else
-                        reg += OMAP1610_GPIO_CLEAR_DATAOUT;
-                l = 1 << gpio;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DATA_OUTPUT;
-                l = __raw_readl(reg);
-                if (enable)
-                        l |= 1 << gpio;
-                else
-                        l &= ~(1 << gpio);
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                if (enable)
-                        reg += OMAP24XX_GPIO_SETDATAOUT;
-                else
-                        reg += OMAP24XX_GPIO_CLEARDATAOUT;
-                l = 1 << gpio;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                if (enable)
-                        reg += OMAP4_GPIO_SETDATAOUT;
-                else
-                        reg += OMAP4_GPIO_CLEARDATAOUT;
-                l = 1 << gpio;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        __raw_writel(l, reg);
-}
-
-static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
-{
-        void __iomem *reg;
-
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-        reg = bank->base;
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DATA_INPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DATAIN;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DATA_INPUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_DATAIN;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_DATAIN;
-                break;
-#endif
-        default:
-                return -EINVAL;
-        }
-        return (__raw_readl(reg)
-                        & (1 << get_gpio_index(gpio))) != 0;
-}
-
-static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
-{
-        void __iomem *reg;
-
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-        reg = bank->base;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_OUTPUT / bank->stride;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DATA_OUTPUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DATAOUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DATA_OUTPUT;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_DATAOUT;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_DATAOUT;
-                break;
-#endif
-        default:
-                return -EINVAL;
-        }
-
-        return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
-}
-
-#define MOD_REG_BIT(reg, bit_mask, set) \
-do {    \
-        int l = __raw_readl(base + reg); \
-        if (set) l |= bit_mask; \
-        else l &= ~bit_mask; \
-        __raw_writel(l, base + reg); \
-} while(0)
-
-/**
- * _set_gpio_debounce - low level gpio debounce time
- * @bank: the gpio bank we're acting upon
- * @gpio: the gpio number on this @gpio
- * @debounce: debounce time to use
- *
- * OMAP's debounce time is in 31us steps so we need
- * to convert and round up to the closest unit.
- */
-static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
-                unsigned debounce)
-{
-        void __iomem            *reg = bank->base;
-        u32                     val;
-        u32                     l;
-
-        if (!bank->dbck_flag)
-                return;
-
-        if (debounce < 32)
-                debounce = 0x01;
-        else if (debounce > 7936)
-                debounce = 0xff;
-        else
-                debounce = (debounce / 0x1f) - 1;
-
-        l = 1 << get_gpio_index(gpio);
-
-        if (bank->method == METHOD_GPIO_44XX)
-                reg += OMAP4_GPIO_DEBOUNCINGTIME;
-        else
-                reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
-
-        __raw_writel(debounce, reg);
-
-        reg = bank->base;
-        if (bank->method == METHOD_GPIO_44XX)
-                reg += OMAP4_GPIO_DEBOUNCENABLE;
-        else
-                reg += OMAP24XX_GPIO_DEBOUNCE_EN;
-
-        val = __raw_readl(reg);
-
-        if (debounce) {
-                val |= l;
-                clk_enable(bank->dbck);
-        } else {
-                val &= ~l;
-                clk_disable(bank->dbck);
-        }
-        bank->dbck_enable_mask = val;
-
-        __raw_writel(val, reg);
-}
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
-                                                int trigger)
-{
-        void __iomem *base = bank->base;
-        u32 gpio_bit = 1 << gpio;
-        u32 val;
-
-        if (cpu_is_omap44xx()) {
-                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_LOW);
-                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_HIGH);
-                MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_RISING);
-                MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_FALLING);
-        } else {
-                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_LOW);
-                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
-                        trigger & IRQ_TYPE_LEVEL_HIGH);
-                MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_RISING);
-                MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
-                        trigger & IRQ_TYPE_EDGE_FALLING);
-        }
-        if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-                if (cpu_is_omap44xx()) {
-                        if (trigger != 0)
-                                __raw_writel(1 << gpio, bank->base+
-                                                OMAP4_GPIO_IRQWAKEN0);
-                        else {
-                                val = __raw_readl(bank->base +
-                                                        OMAP4_GPIO_IRQWAKEN0);
-                                __raw_writel(val & (~(1 << gpio)), bank->base +
-                                                         OMAP4_GPIO_IRQWAKEN0);
-                        }
-                } else {
-                        /*
-                         * GPIO wakeup request can only be generated on edge
-                         * transitions
-                         */
-                        if (trigger & IRQ_TYPE_EDGE_BOTH)
-                                __raw_writel(1 << gpio, bank->base
-                                        + OMAP24XX_GPIO_SETWKUENA);
-                        else
-                                __raw_writel(1 << gpio, bank->base
-                                        + OMAP24XX_GPIO_CLEARWKUENA);
-                }
-        }
-        /* This part needs to be executed always for OMAP34xx */
-        if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
-                /*
-                 * Log the edge gpio and manually trigger the IRQ
-                 * after resume if the input level changes
-                 * to avoid irq lost during PER RET/OFF mode
-                 * Applies for omap2 non-wakeup gpio and all omap3 gpios
-                 */
-                if (trigger & IRQ_TYPE_EDGE_BOTH)
-                        bank->enabled_non_wakeup_gpios |= gpio_bit;
-                else
-                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
-        }
-
-        if (cpu_is_omap44xx()) {
-                bank->level_mask =
-                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
-                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
-        } else {
-                bank->level_mask =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-        }
-}
-#endif
-
-#ifdef CONFIG_ARCH_OMAP1
-/*
- * This only applies to chips that can't do both rising and falling edge
- * detection at once.  For all other chips, this function is a noop.
- */
-static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
-{
-        void __iomem *reg = bank->base;
-        u32 l = 0;
-
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
-                break;
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_CONTROL;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_CONTROL;
-                break;
-#endif
-        default:
-                return;
-        }
-
-        l = __raw_readl(reg);
-        if ((l >> gpio) & 1)
-                l &= ~(1 << gpio);
-        else
-                l |= 1 << gpio;
-
-        __raw_writel(l, reg);
-}
-#endif
-
-static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
-{
-        void __iomem *reg = bank->base;
-        u32 l = 0;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
-                l = __raw_readl(reg);
-                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                        bank->toggle_mask |= 1 << gpio;
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_CONTROL;
-                l = __raw_readl(reg);
-                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                        bank->toggle_mask |= 1 << gpio;
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                if (gpio & 0x08)
-                        reg += OMAP1610_GPIO_EDGE_CTRL2;
-                else
-                        reg += OMAP1610_GPIO_EDGE_CTRL1;
-                gpio &= 0x07;
-                l = __raw_readl(reg);
-                l &= ~(3 << (gpio << 1));
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 2 << (gpio << 1);
-                if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l |= 1 << (gpio << 1);
-                if (trigger)
-                        /* Enable wake-up during idle for dynamic tick */
-                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
-                else
-                        __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_CONTROL;
-                l = __raw_readl(reg);
-                if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                        bank->toggle_mask |= 1 << gpio;
-                if (trigger & IRQ_TYPE_EDGE_RISING)
-                        l |= 1 << gpio;
-                else if (trigger & IRQ_TYPE_EDGE_FALLING)
-                        l &= ~(1 << gpio);
-                else
-                        goto bad;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        case METHOD_GPIO_24XX:
-        case METHOD_GPIO_44XX:
-                set_24xx_gpio_triggering(bank, gpio, trigger);
-                return 0;
-#endif
-        default:
-                goto bad;
-        }
-        __raw_writel(l, reg);
-        return 0;
-bad:
-        return -EINVAL;
-}
-
-static int gpio_irq_type(struct irq_data *d, unsigned type)
-{
-        struct gpio_bank *bank;
-        unsigned gpio;
-        int retval;
-        unsigned long flags;
-
-        if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
-                gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-        else
-                gpio = d->irq - IH_GPIO_BASE;
-
-        if (check_gpio(gpio) < 0)
-                return -EINVAL;
-
-        if (type & ~IRQ_TYPE_SENSE_MASK)
-                return -EINVAL;
-
-        /* OMAP1 allows only only edge triggering */
-        if (!cpu_class_is_omap2()
-                        && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
-                return -EINVAL;
-
-        bank = irq_data_get_irq_chip_data(d);
-        spin_lock_irqsave(&bank->lock, flags);
-        retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
-        spin_unlock_irqrestore(&bank->lock, flags);
-
-        if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __irq_set_handler_locked(d->irq, handle_level_irq);
-        else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __irq_set_handler_locked(d->irq, handle_edge_irq);
-
-        return retval;
-}
-
-static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
-{
-        void __iomem *reg = bank->base;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                /* MPUIO irqstatus is reset by reading the status register,
-                 * so do nothing here */
-                return;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_STATUS;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_IRQSTATUS1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_STATUS;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_IRQSTATUS1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_IRQSTATUS0;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        __raw_writel(gpio_mask, reg);
-
-        /* Workaround for clearing DSP GPIO interrupts to allow retention */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-        else if (cpu_is_omap44xx())
-                reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
-
-        if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                __raw_writel(gpio_mask, reg);
-
-        /* Flush posted write for the irq status to avoid spurious interrupts */
-        __raw_readl(reg);
-        }
-}
-
-static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
-{
-        _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
-}
-
-static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
-{
-        void __iomem *reg = bank->base;
-        int inv = 0;
-        u32 l;
-        u32 mask;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
-                mask = 0xffff;
-                inv = 1;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_MASK;
-                mask = 0xffff;
-                inv = 1;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_IRQENABLE1;
-                mask = 0xffff;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_MASK;
-                mask = 0xffffffff;
-                inv = 1;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_IRQENABLE1;
-                mask = 0xffffffff;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_IRQSTATUSSET0;
-                mask = 0xffffffff;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return 0;
-        }
-
-        l = __raw_readl(reg);
-        if (inv)
-                l = ~l;
-        l &= mask;
-        return l;
-}
-
-static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
-{
-        void __iomem *reg = bank->base;
-        u32 l;
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP1
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_INT_MASK;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_GPIO_1610:
-                if (enable)
-                        reg += OMAP1610_GPIO_SET_IRQENABLE1;
-                else
-                        reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
-                l = gpio_mask;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_INT_MASK;
-                l = __raw_readl(reg);
-                if (enable)
-                        l &= ~(gpio_mask);
-                else
-                        l |= gpio_mask;
-                break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        case METHOD_GPIO_24XX:
-                if (enable)
-                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
-                else
-                        reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
-                l = gpio_mask;
-                break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        case METHOD_GPIO_44XX:
-                if (enable)
-                        reg += OMAP4_GPIO_IRQSTATUSSET0;
-                else
-                        reg += OMAP4_GPIO_IRQSTATUSCLR0;
-                l = gpio_mask;
-                break;
-#endif
-        default:
-                WARN_ON(1);
-                return;
-        }
-        __raw_writel(l, reg);
-}
-
-static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
-{
-        _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
-}
-
-/*
- * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
- * 1510 does not seem to have a wake-up register. If JTAG is connected
- * to the target, system will wake up always on GPIO events. While
- * system is running all registered GPIO interrupts need to have wake-up
- * enabled. When system is suspended, only selected GPIO interrupts need
- * to have wake-up enabled.
- */
-static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
-{
-        unsigned long uninitialized_var(flags);
-
-        switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-        case METHOD_MPUIO:
-        case METHOD_GPIO_1610:
-                spin_lock_irqsave(&bank->lock, flags);
-                if (enable)
-                        bank->suspend_wakeup |= (1 << gpio);
-                else
-                        bank->suspend_wakeup &= ~(1 << gpio);
-                spin_unlock_irqrestore(&bank->lock, flags);
-                return 0;
-#endif
-#ifdef CONFIG_ARCH_OMAP2PLUS
-        case METHOD_GPIO_24XX:
-        case METHOD_GPIO_44XX:
-                if (bank->non_wakeup_gpios & (1 << gpio)) {
-                        printk(KERN_ERR "Unable to modify wakeup on "
-                                        "non-wakeup GPIO%d\n",
-                                        (bank - gpio_bank) * 32 + gpio);
-                        return -EINVAL;
-                }
-                spin_lock_irqsave(&bank->lock, flags);
-                if (enable)
-                        bank->suspend_wakeup |= (1 << gpio);
-                else
-                        bank->suspend_wakeup &= ~(1 << gpio);
-                spin_unlock_irqrestore(&bank->lock, flags);
-                return 0;
-#endif
-        default:
-                printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
-                       bank->method);
-                return -EINVAL;
-        }
-}
-
-static void _reset_gpio(struct gpio_bank *bank, int gpio)
-{
-        _set_gpio_direction(bank, get_gpio_index(gpio), 1);
-        _set_gpio_irqenable(bank, gpio, 0);
-        _clear_gpio_irqstatus(bank, gpio);
-        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
-}
-
-/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
-static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
-{
-        unsigned int gpio = d->irq - IH_GPIO_BASE;
-        struct gpio_bank *bank;
-        int retval;
-
-        if (check_gpio(gpio) < 0)
-                return -ENODEV;
-        bank = irq_data_get_irq_chip_data(d);
-        retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
-
-        return retval;
-}
-
-static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
-        unsigned long flags;
-
-        spin_lock_irqsave(&bank->lock, flags);
-
-        /* Set trigger to none. You need to enable the desired trigger with
-         * request_irq() or set_irq_type().
-         */
-        _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
-
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (bank->method == METHOD_GPIO_1510) {
-                void __iomem *reg;
-
-                /* Claim the pin for MPU */
-                reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
-                __raw_writel(__raw_readl(reg) | (1 << offset), reg);
-        }
-#endif
-        if (!cpu_class_is_omap1()) {
-                if (!bank->mod_usage) {
-                        void __iomem *reg = bank->base;
-                        u32 ctrl;
-
-                        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                                reg += OMAP24XX_GPIO_CTRL;
-                        else if (cpu_is_omap44xx())
-                                reg += OMAP4_GPIO_CTRL;
-                        ctrl = __raw_readl(reg);
-                        /* Module is enabled, clocks are not gated */
-                        ctrl &= 0xFFFFFFFE;
-                        __raw_writel(ctrl, reg);
-                }
-                bank->mod_usage |= 1 << offset;
-        }
-        spin_unlock_irqrestore(&bank->lock, flags);
-
-        return 0;
-}
-
-static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
-        unsigned long flags;
-
-        spin_lock_irqsave(&bank->lock, flags);
-#ifdef CONFIG_ARCH_OMAP16XX
-        if (bank->method == METHOD_GPIO_1610) {
-                /* Disable wake-up during idle for dynamic tick */
-                void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                __raw_writel(1 << offset, reg);
-        }
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        if (bank->method == METHOD_GPIO_24XX) {
-                /* Disable wake-up during idle for dynamic tick */
-                void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                __raw_writel(1 << offset, reg);
-        }
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-        if (bank->method == METHOD_GPIO_44XX) {
-                /* Disable wake-up during idle for dynamic tick */
-                void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                __raw_writel(1 << offset, reg);
-        }
-#endif
-        if (!cpu_class_is_omap1()) {
-                bank->mod_usage &= ~(1 << offset);
-                if (!bank->mod_usage) {
-                        void __iomem *reg = bank->base;
-                        u32 ctrl;
-
-                        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                                reg += OMAP24XX_GPIO_CTRL;
-                        else if (cpu_is_omap44xx())
-                                reg += OMAP4_GPIO_CTRL;
-                        ctrl = __raw_readl(reg);
-                        /* Module is disabled, clocks are gated */
-                        ctrl |= 1;
-                        __raw_writel(ctrl, reg);
-                }
-        }
-        _reset_gpio(bank, bank->chip.base + offset);
-        spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-/*
- * We need to unmask the GPIO bank interrupt as soon as possible to
- * avoid missing GPIO interrupts for other lines in the bank.
- * Then we need to mask-read-clear-unmask the triggered GPIO lines
- * in the bank to avoid missing nested interrupts for a GPIO line.
- * If we wait to unmask individual GPIO lines in the bank after the
- * line's interrupt handler has been run, we may miss some nested
- * interrupts.
- */
-static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        void __iomem *isr_reg = NULL;
-        u32 isr;
-        unsigned int gpio_irq, gpio_index;
-        struct gpio_bank *bank;
-        u32 retrigger = 0;
-        int unmasked = 0;
-        struct irq_chip *chip = irq_desc_get_chip(desc);
-
-        chained_irq_enter(chip, desc);
-
-        bank = irq_get_handler_data(irq);
-#ifdef CONFIG_ARCH_OMAP1
-        if (bank->method == METHOD_MPUIO)
-                isr_reg = bank->base +
-                                OMAP_MPUIO_GPIO_INT / bank->stride;
-#endif
-#ifdef CONFIG_ARCH_OMAP15XX
-        if (bank->method == METHOD_GPIO_1510)
-                isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
-#endif
-#if defined(CONFIG_ARCH_OMAP16XX)
-        if (bank->method == METHOD_GPIO_1610)
-                isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
-#endif
-#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
-        if (bank->method == METHOD_GPIO_7XX)
-                isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-        if (bank->method == METHOD_GPIO_24XX)
-                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
-#endif
-#if defined(CONFIG_ARCH_OMAP4)
-        if (bank->method == METHOD_GPIO_44XX)
-                isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
-#endif
-
-        if (WARN_ON(!isr_reg))
-                goto exit;
-
-        while(1) {
-                u32 isr_saved, level_mask = 0;
-                u32 enabled;
-
-                enabled = _get_gpio_irqbank_mask(bank);
-                isr_saved = isr = __raw_readl(isr_reg) & enabled;
-
-                if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
-                        isr &= 0x0000ffff;
-
-                if (cpu_class_is_omap2()) {
-                        level_mask = bank->level_mask & enabled;
-                }
-
-                /* clear edge sensitive interrupts before handler(s) are
-                called so that we don't miss any interrupt occurred while
-                executing them */
-                _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
-                _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
-                _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
-
-                /* if there is only edge sensitive GPIO pin interrupts
-                configured, we could unmask GPIO bank interrupt immediately */
-                if (!level_mask && !unmasked) {
-                        unmasked = 1;
-                        chained_irq_exit(chip, desc);
-                }
-
-                isr |= retrigger;
-                retrigger = 0;
-                if (!isr)
-                        break;
-
-                gpio_irq = bank->virtual_irq_start;
-                for (; isr != 0; isr >>= 1, gpio_irq++) {
-                        gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
-
-                        if (!(isr & 1))
-                                continue;
-
-#ifdef CONFIG_ARCH_OMAP1
-                        /*
-                         * Some chips can't respond to both rising and falling
-                         * at the same time.  If this irq was requested with
-                         * both flags, we need to flip the ICR data for the IRQ
-                         * to respond to the IRQ for the opposite direction.
-                         * This will be indicated in the bank toggle_mask.
-                         */
-                        if (bank->toggle_mask & (1 << gpio_index))
-                                _toggle_gpio_edge_triggering(bank, gpio_index);
-#endif
-
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-        /* if bank has any level sensitive GPIO pin interrupt
-        configured, we must unmask the bank interrupt only after
-        handler(s) are executed in order to avoid spurious bank
-        interrupt */
-exit:
-        if (!unmasked)
-                chained_irq_exit(chip, desc);
-}
-
-static void gpio_irq_shutdown(struct irq_data *d)
-{
-        unsigned int gpio = d->irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-
-        _reset_gpio(bank, gpio);
-}
-
-static void gpio_ack_irq(struct irq_data *d)
-{
-        unsigned int gpio = d->irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-
-        _clear_gpio_irqstatus(bank, gpio);
-}
-
-static void gpio_mask_irq(struct irq_data *d)
-{
-        unsigned int gpio = d->irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-
-        _set_gpio_irqenable(bank, gpio, 0);
-        _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
-}
-
-static void gpio_unmask_irq(struct irq_data *d)
-{
-        unsigned int gpio = d->irq - IH_GPIO_BASE;
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        unsigned int irq_mask = 1 << get_gpio_index(gpio);
-        u32 trigger = irqd_get_trigger_type(d);
-
-        if (trigger)
-                _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
-
-        /* For level-triggered GPIOs, the clearing must be done after
-         * the HW source is cleared, thus after the handler has run */
-        if (bank->level_mask & irq_mask) {
-                _set_gpio_irqenable(bank, gpio, 0);
-                _clear_gpio_irqstatus(bank, gpio);
-        }
-
-        _set_gpio_irqenable(bank, gpio, 1);
-}
-
-static struct irq_chip gpio_irq_chip = {
-        .name           = "GPIO",
-        .irq_shutdown   = gpio_irq_shutdown,
-        .irq_ack        = gpio_ack_irq,
-        .irq_mask       = gpio_mask_irq,
-        .irq_unmask     = gpio_unmask_irq,
-        .irq_set_type   = gpio_irq_type,
-        .irq_set_wake   = gpio_wake_enable,
-};
-
-/*---------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP1
-
-/* MPUIO uses the always-on 32k clock */
-
-static void mpuio_ack_irq(struct irq_data *d)
-{
-        /* The ISR is reset automatically, so do nothing here. */
-}
-
-static void mpuio_mask_irq(struct irq_data *d)
-{
-        unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-
-        _set_gpio_irqenable(bank, gpio, 0);
-}
-
-static void mpuio_unmask_irq(struct irq_data *d)
-{
-        unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
-        struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
-
-        _set_gpio_irqenable(bank, gpio, 1);
-}
-
-static struct irq_chip mpuio_irq_chip = {
-        .name           = "MPUIO",
-        .irq_ack        = mpuio_ack_irq,
-        .irq_mask       = mpuio_mask_irq,
-        .irq_unmask     = mpuio_unmask_irq,
-        .irq_set_type   = gpio_irq_type,
-#ifdef CONFIG_ARCH_OMAP16XX
-        /* REVISIT: assuming only 16xx supports MPUIO wake events */
-        .irq_set_wake   = gpio_wake_enable,
-#endif
-};
-
-
-#define bank_is_mpuio(bank)     ((bank)->method == METHOD_MPUIO)
-
-
-#ifdef CONFIG_ARCH_OMAP16XX
-
-#include <linux/platform_device.h>
-
-static int omap_mpuio_suspend_noirq(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct gpio_bank        *bank = platform_get_drvdata(pdev);
-        void __iomem            *mask_reg = bank->base +
-                                        OMAP_MPUIO_GPIO_MASKIT / bank->stride;
-        unsigned long           flags;
-
-        spin_lock_irqsave(&bank->lock, flags);
-        bank->saved_wakeup = __raw_readl(mask_reg);
-        __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
-        spin_unlock_irqrestore(&bank->lock, flags);
-
-        return 0;
-}
-
-static int omap_mpuio_resume_noirq(struct device *dev)
-{
-        struct platform_device *pdev = to_platform_device(dev);
-        struct gpio_bank        *bank = platform_get_drvdata(pdev);
-        void __iomem            *mask_reg = bank->base +
-                                        OMAP_MPUIO_GPIO_MASKIT / bank->stride;
-        unsigned long           flags;
-
-        spin_lock_irqsave(&bank->lock, flags);
-        __raw_writel(bank->saved_wakeup, mask_reg);
-        spin_unlock_irqrestore(&bank->lock, flags);
-
-        return 0;
-}
-
-static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
-        .suspend_noirq = omap_mpuio_suspend_noirq,
-        .resume_noirq = omap_mpuio_resume_noirq,
-};
-
-/* use platform_driver for this. */
-static struct platform_driver omap_mpuio_driver = {
-        .driver         = {
-                .name   = "mpuio",
-                .pm     = &omap_mpuio_dev_pm_ops,
-        },
-};
-
-static struct platform_device omap_mpuio_device = {
-        .name           = "mpuio",
-        .id             = -1,
-        .dev = {
-                .driver = &omap_mpuio_driver.driver,
-        }
-        /* could list the /proc/iomem resources */
-};
-
-static inline void mpuio_init(void)
-{
-        struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
-        platform_set_drvdata(&omap_mpuio_device, bank);
-
-        if (platform_driver_register(&omap_mpuio_driver) == 0)
-                (void) platform_device_register(&omap_mpuio_device);
-}
-
-#else
-static inline void mpuio_init(void) {}
-#endif  /* 16xx */
-
-#else
-
-extern struct irq_chip mpuio_irq_chip;
-
-#define bank_is_mpuio(bank)     0
-static inline void mpuio_init(void) {}
-
-#endif
-
-/*---------------------------------------------------------------------*/
-
-/* REVISIT these are stupid implementations!  replace by ones that
- * don't switch on METHOD_* and which mostly avoid spinlocks
- */
-
-static int gpio_input(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_direction(bank, offset, 1);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-
-static int gpio_is_input(struct gpio_bank *bank, int mask)
-{
-        void __iomem *reg = bank->base;
-
-        switch (bank->method) {
-        case METHOD_MPUIO:
-                reg += OMAP_MPUIO_IO_CNTL / bank->stride;
-                break;
-        case METHOD_GPIO_1510:
-                reg += OMAP1510_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_1610:
-                reg += OMAP1610_GPIO_DIRECTION;
-                break;
-        case METHOD_GPIO_7XX:
-                reg += OMAP7XX_GPIO_DIR_CONTROL;
-                break;
-        case METHOD_GPIO_24XX:
-                reg += OMAP24XX_GPIO_OE;
-                break;
-        case METHOD_GPIO_44XX:
-                reg += OMAP4_GPIO_OE;
-                break;
-        default:
-                WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
-                return -EINVAL;
-        }
-        return __raw_readl(reg) & mask;
-}
-
-static int gpio_get(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank;
-        void __iomem *reg;
-        int gpio;
-        u32 mask;
-
-        gpio = chip->base + offset;
-        bank = get_gpio_bank(gpio);
-        reg = bank->base;
-        mask = 1 << get_gpio_index(gpio);
-
-        if (gpio_is_input(bank, mask))
-                return _get_gpio_datain(bank, gpio);
-        else
-                return _get_gpio_dataout(bank, gpio);
-}
-
-static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_dataout(bank, offset, value);
-        _set_gpio_direction(bank, offset, 0);
-        spin_unlock_irqrestore(&bank->lock, flags);
-        return 0;
-}
-
-static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
-                unsigned debounce)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-
-        bank = container_of(chip, struct gpio_bank, chip);
-
-        if (!bank->dbck) {
-                bank->dbck = clk_get(bank->dev, "dbclk");
-                if (IS_ERR(bank->dbck))
-                        dev_err(bank->dev, "Could not get gpio dbck\n");
-        }
-
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_debounce(bank, offset, debounce);
-        spin_unlock_irqrestore(&bank->lock, flags);
-
-        return 0;
-}
-
-static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
-        struct gpio_bank *bank;
-        unsigned long flags;
-
-        bank = container_of(chip, struct gpio_bank, chip);
-        spin_lock_irqsave(&bank->lock, flags);
-        _set_gpio_dataout(bank, offset, value);
-        spin_unlock_irqrestore(&bank->lock, flags);
-}
-
-static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
-{
-        struct gpio_bank *bank;
-
-        bank = container_of(chip, struct gpio_bank, chip);
-        return bank->virtual_irq_start + offset;
-}
-
-/*---------------------------------------------------------------------*/
-
-static void __init omap_gpio_show_rev(struct gpio_bank *bank)
-{
-        u32 rev;
-
-        if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
-                rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
-        else if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
-        else if (cpu_is_omap44xx())
-                rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
-        else
-                return;
-
-        printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
-                (rev >> 4) & 0x0f, rev & 0x0f);
-}
-
-/* This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-
-static inline int init_gpio_info(struct platform_device *pdev)
-{
-        /* TODO: Analyze removing gpio_bank_count usage from driver code */
-        gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
-                                GFP_KERNEL);
-        if (!gpio_bank) {
-                dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
-                return -ENOMEM;
-        }
-        return 0;
-}
-
-/* TODO: Cleanup cpu_is_* checks */
-static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
-{
-        if (cpu_class_is_omap2()) {
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(0xffffffff, bank->base +
-                                        OMAP4_GPIO_IRQSTATUSCLR0);
-                        __raw_writel(0x00000000, bank->base +
-                                         OMAP4_GPIO_DEBOUNCENABLE);
-                        /* Initialize interface clk ungated, module enabled */
-                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
-                } else if (cpu_is_omap34xx()) {
-                        __raw_writel(0x00000000, bank->base +
-                                        OMAP24XX_GPIO_IRQENABLE1);
-                        __raw_writel(0xffffffff, bank->base +
-                                        OMAP24XX_GPIO_IRQSTATUS1);
-                        __raw_writel(0x00000000, bank->base +
-                                        OMAP24XX_GPIO_DEBOUNCE_EN);
-
-                        /* Initialize interface clk ungated, module enabled */
-                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
-                } else if (cpu_is_omap24xx()) {
-                        static const u32 non_wakeup_gpios[] = {
-                                0xe203ffc0, 0x08700040
-                        };
-                        if (id < ARRAY_SIZE(non_wakeup_gpios))
-                                bank->non_wakeup_gpios = non_wakeup_gpios[id];
-                }
-        } else if (cpu_class_is_omap1()) {
-                if (bank_is_mpuio(bank))
-                        __raw_writew(0xffff, bank->base +
-                                OMAP_MPUIO_GPIO_MASKIT / bank->stride);
-                if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
-                        __raw_writew(0xffff, bank->base
-                                                + OMAP1510_GPIO_INT_MASK);
-                        __raw_writew(0x0000, bank->base
-                                                + OMAP1510_GPIO_INT_STATUS);
-                }
-                if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
-                        __raw_writew(0x0000, bank->base
-                                                + OMAP1610_GPIO_IRQENABLE1);
-                        __raw_writew(0xffff, bank->base
-                                                + OMAP1610_GPIO_IRQSTATUS1);
-                        __raw_writew(0x0014, bank->base
-                                                + OMAP1610_GPIO_SYSCONFIG);
-
-                        /*
-                         * Enable system clock for GPIO module.
-                         * The CAM_CLK_CTRL *is* really the right place.
-                         */
-                        omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
-                                                ULPD_CAM_CLK_CTRL);
-                }
-                if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
-                        __raw_writel(0xffffffff, bank->base
-                                                + OMAP7XX_GPIO_INT_MASK);
-                        __raw_writel(0x00000000, bank->base
-                                                + OMAP7XX_GPIO_INT_STATUS);
-                }
-        }
-}
-
-static void __init omap_gpio_chip_init(struct gpio_bank *bank)
-{
-        int j;
-        static int gpio;
-
-        bank->mod_usage = 0;
-        /*
-         * REVISIT eventually switch from OMAP-specific gpio structs
-         * over to the generic ones
-         */
-        bank->chip.request = omap_gpio_request;
-        bank->chip.free = omap_gpio_free;
-        bank->chip.direction_input = gpio_input;
-        bank->chip.get = gpio_get;
-        bank->chip.direction_output = gpio_output;
-        bank->chip.set_debounce = gpio_debounce;
-        bank->chip.set = gpio_set;
-        bank->chip.to_irq = gpio_2irq;
-        if (bank_is_mpuio(bank)) {
-                bank->chip.label = "mpuio";
-#ifdef CONFIG_ARCH_OMAP16XX
-                bank->chip.dev = &omap_mpuio_device.dev;
-#endif
-                bank->chip.base = OMAP_MPUIO(0);
-        } else {
-                bank->chip.label = "gpio";
-                bank->chip.base = gpio;
-                gpio += bank_width;
-        }
-        bank->chip.ngpio = bank_width;
-
-        gpiochip_add(&bank->chip);
-
-        for (j = bank->virtual_irq_start;
-                     j < bank->virtual_irq_start + bank_width; j++) {
-                irq_set_lockdep_class(j, &gpio_lock_class);
-                irq_set_chip_data(j, bank);
-                if (bank_is_mpuio(bank))
-                        irq_set_chip(j, &mpuio_irq_chip);
-                else
-                        irq_set_chip(j, &gpio_irq_chip);
-                irq_set_handler(j, handle_simple_irq);
-                set_irq_flags(j, IRQF_VALID);
-        }
-        irq_set_chained_handler(bank->irq, gpio_irq_handler);
-        irq_set_handler_data(bank->irq, bank);
-}
-
-static int __devinit omap_gpio_probe(struct platform_device *pdev)
-{
-        static int gpio_init_done;
-        struct omap_gpio_platform_data *pdata;
-        struct resource *res;
-        int id;
-        struct gpio_bank *bank;
-
-        if (!pdev->dev.platform_data)
-                return -EINVAL;
-
-        pdata = pdev->dev.platform_data;
-
-        if (!gpio_init_done) {
-                int ret;
-
-                ret = init_gpio_info(pdev);
-                if (ret)
-                        return ret;
-        }
-
-        id = pdev->id;
-        bank = &gpio_bank[id];
-
-        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (unlikely(!res)) {
-                dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
-                return -ENODEV;
-        }
-
-        bank->irq = res->start;
-        bank->virtual_irq_start = pdata->virtual_irq_start;
-        bank->method = pdata->bank_type;
-        bank->dev = &pdev->dev;
-        bank->dbck_flag = pdata->dbck_flag;
-        bank->stride = pdata->bank_stride;
-        bank_width = pdata->bank_width;
-
-        spin_lock_init(&bank->lock);
-
-        /* Static mapping, never released */
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (unlikely(!res)) {
-                dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
-                return -ENODEV;
-        }
-
-        bank->base = ioremap(res->start, resource_size(res));
-        if (!bank->base) {
-                dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
-                return -ENOMEM;
-        }
-
-        pm_runtime_enable(bank->dev);
-        pm_runtime_get_sync(bank->dev);
-
-        omap_gpio_mod_init(bank, id);
-        omap_gpio_chip_init(bank);
-        omap_gpio_show_rev(bank);
-
-        if (!gpio_init_done)
-                gpio_init_done = 1;
-
-        return 0;
-}
-
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-static int omap_gpio_suspend(void)
-{
-        int i;
-
-        if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
-                return 0;
-
-        for (i = 0; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                void __iomem *wake_status;
-                void __iomem *wake_clear;
-                void __iomem *wake_set;
-                unsigned long flags;
-
-                switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-                case METHOD_GPIO_1610:
-                        wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
-                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-                        break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-                case METHOD_GPIO_24XX:
-                        wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
-                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-                        break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_44XX:
-                        wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        break;
-#endif
-                default:
-                        continue;
-                }
-
-                spin_lock_irqsave(&bank->lock, flags);
-                bank->saved_wakeup = __raw_readl(wake_status);
-                __raw_writel(0xffffffff, wake_clear);
-                __raw_writel(bank->suspend_wakeup, wake_set);
-                spin_unlock_irqrestore(&bank->lock, flags);
-        }
-
-        return 0;
-}
-
-static void omap_gpio_resume(void)
-{
-        int i;
-
-        if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
-                return;
-
-        for (i = 0; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                void __iomem *wake_clear;
-                void __iomem *wake_set;
-                unsigned long flags;
-
-                switch (bank->method) {
-#ifdef CONFIG_ARCH_OMAP16XX
-                case METHOD_GPIO_1610:
-                        wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
-                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
-                        break;
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-                case METHOD_GPIO_24XX:
-                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
-                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
-                        break;
-#endif
-#ifdef CONFIG_ARCH_OMAP4
-                case METHOD_GPIO_44XX:
-                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
-                        break;
-#endif
-                default:
-                        continue;
-                }
-
-                spin_lock_irqsave(&bank->lock, flags);
-                __raw_writel(0xffffffff, wake_clear);
-                __raw_writel(bank->saved_wakeup, wake_set);
-                spin_unlock_irqrestore(&bank->lock, flags);
-        }
-}
-
-static struct syscore_ops omap_gpio_syscore_ops = {
-        .suspend        = omap_gpio_suspend,
-        .resume         = omap_gpio_resume,
-};
-
-#endif
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
-
-static int workaround_enabled;
-
-void omap2_gpio_prepare_for_idle(int off_mode)
-{
-        int i, c = 0;
-        int min = 0;
-
-        if (cpu_is_omap34xx())
-                min = 1;
-
-        for (i = min; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                u32 l1 = 0, l2 = 0;
-                int j;
-
-                for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
-                        clk_disable(bank->dbck);
-
-                if (!off_mode)
-                        continue;
-
-                /* If going to OFF, remove triggering for all
-                 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
-                 * generated.  See OMAP2420 Errata item 1.101. */
-                if (!(bank->enabled_non_wakeup_gpios))
-                        continue;
-
-                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                        bank->saved_datain = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_DATAIN);
-                        l1 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_FALLINGDETECT);
-                        l2 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_RISINGDETECT);
-                }
-
-                if (cpu_is_omap44xx()) {
-                        bank->saved_datain = __raw_readl(bank->base +
-                                                OMAP4_GPIO_DATAIN);
-                        l1 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_FALLINGDETECT);
-                        l2 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_RISINGDETECT);
-                }
-
-                bank->saved_fallingdetect = l1;
-                bank->saved_risingdetect = l2;
-                l1 &= ~bank->enabled_non_wakeup_gpios;
-                l2 &= ~bank->enabled_non_wakeup_gpios;
-
-                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                        __raw_writel(l1, bank->base +
-                                        OMAP24XX_GPIO_FALLINGDETECT);
-                        __raw_writel(l2, bank->base +
-                                        OMAP24XX_GPIO_RISINGDETECT);
-                }
-
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
-                        __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
-                }
-
-                c++;
-        }
-        if (!c) {
-                workaround_enabled = 0;
-                return;
-        }
-        workaround_enabled = 1;
-}
-
-void omap2_gpio_resume_after_idle(void)
-{
-        int i;
-        int min = 0;
-
-        if (cpu_is_omap34xx())
-                min = 1;
-        for (i = min; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                u32 l = 0, gen, gen0, gen1;
-                int j;
-
-                for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
-                        clk_enable(bank->dbck);
-
-                if (!workaround_enabled)
-                        continue;
-
-                if (!(bank->enabled_non_wakeup_gpios))
-                        continue;
-
-                if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                        __raw_writel(bank->saved_fallingdetect,
-                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                        __raw_writel(bank->saved_risingdetect,
-                                 bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                        l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-                }
-
-                if (cpu_is_omap44xx()) {
-                        __raw_writel(bank->saved_fallingdetect,
-                                 bank->base + OMAP4_GPIO_FALLINGDETECT);
-                        __raw_writel(bank->saved_risingdetect,
-                                 bank->base + OMAP4_GPIO_RISINGDETECT);
-                        l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
-                }
-
-                /* Check if any of the non-wakeup interrupt GPIOs have changed
-                 * state.  If so, generate an IRQ by software.  This is
-                 * horribly racy, but it's the best we can do to work around
-                 * this silicon bug. */
-                l ^= bank->saved_datain;
-                l &= bank->enabled_non_wakeup_gpios;
-
-                /*
-                 * No need to generate IRQs for the rising edge for gpio IRQs
-                 * configured with falling edge only; and vice versa.
-                 */
-                gen0 = l & bank->saved_fallingdetect;
-                gen0 &= bank->saved_datain;
-
-                gen1 = l & bank->saved_risingdetect;
-                gen1 &= ~(bank->saved_datain);
-
-                /* FIXME: Consider GPIO IRQs with level detections properly! */
-                gen = l & (~(bank->saved_fallingdetect) &
-                                ~(bank->saved_risingdetect));
-                /* Consider all GPIO IRQs needed to be updated */
-                gen |= gen0 | gen1;
-
-                if (gen) {
-                        u32 old0, old1;
-
-                        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                                old0 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0);
-                                old1 = __raw_readl(bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                                __raw_writel(old0 | gen, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0);
-                                __raw_writel(old1 | gen, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                                __raw_writel(old0, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT0);
-                                __raw_writel(old1, bank->base +
-                                        OMAP24XX_GPIO_LEVELDETECT1);
-                        }
-
-                        if (cpu_is_omap44xx()) {
-                                old0 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_LEVELDETECT0);
-                                old1 = __raw_readl(bank->base +
-                                                OMAP4_GPIO_LEVELDETECT1);
-                                __raw_writel(old0 | l, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT0);
-                                __raw_writel(old1 | l, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT1);
-                                __raw_writel(old0, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT0);
-                                __raw_writel(old1, bank->base +
-                                                OMAP4_GPIO_LEVELDETECT1);
-                        }
-                }
-        }
-
-}
-
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-/* save the registers of bank 2-6 */
-void omap_gpio_save_context(void)
-{
-        int i;
-
-        /* saving banks from 2-6 only since GPIO1 is in WKUP */
-        for (i = 1; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                gpio_context[i].irqenable1 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
-                gpio_context[i].irqenable2 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
-                gpio_context[i].wake_en =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
-                gpio_context[i].ctrl =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
-                gpio_context[i].oe =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_OE);
-                gpio_context[i].leveldetect0 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                gpio_context[i].leveldetect1 =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                gpio_context[i].risingdetect =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                gpio_context[i].fallingdetect =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                gpio_context[i].dataout =
-                        __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
-        }
-}
-
-/* restore the required registers of bank 2-6 */
-void omap_gpio_restore_context(void)
-{
-        int i;
-
-        for (i = 1; i < gpio_bank_count; i++) {
-                struct gpio_bank *bank = &gpio_bank[i];
-                __raw_writel(gpio_context[i].irqenable1,
-                                bank->base + OMAP24XX_GPIO_IRQENABLE1);
-                __raw_writel(gpio_context[i].irqenable2,
-                                bank->base + OMAP24XX_GPIO_IRQENABLE2);
-                __raw_writel(gpio_context[i].wake_en,
-                                bank->base + OMAP24XX_GPIO_WAKE_EN);
-                __raw_writel(gpio_context[i].ctrl,
-                                bank->base + OMAP24XX_GPIO_CTRL);
-                __raw_writel(gpio_context[i].oe,
-                                bank->base + OMAP24XX_GPIO_OE);
-                __raw_writel(gpio_context[i].leveldetect0,
-                                bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                __raw_writel(gpio_context[i].leveldetect1,
-                                bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                __raw_writel(gpio_context[i].risingdetect,
-                                bank->base + OMAP24XX_GPIO_RISINGDETECT);
-                __raw_writel(gpio_context[i].fallingdetect,
-                                bank->base + OMAP24XX_GPIO_FALLINGDETECT);
-                __raw_writel(gpio_context[i].dataout,
-                                bank->base + OMAP24XX_GPIO_DATAOUT);
-        }
-}
-#endif
-
-static struct platform_driver omap_gpio_driver = {
-        .probe          = omap_gpio_probe,
-        .driver         = {
-                .name   = "omap_gpio",
-        },
-};
-
-/*
- * gpio driver register needs to be done before
- * machine_init functions access gpio APIs.
- * Hence omap_gpio_drv_reg() is a postcore_initcall.
- */
-static int __init omap_gpio_drv_reg(void)
-{
-        return platform_driver_register(&omap_gpio_driver);
-}
-postcore_initcall(omap_gpio_drv_reg);
-
-static int __init omap_gpio_sysinit(void)
-{
-        mpuio_init();
-
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
-        if (cpu_is_omap16xx() || cpu_class_is_omap2())
-                register_syscore_ops(&omap_gpio_syscore_ops);
-#endif
-
-        return 0;
-}
-
-arch_initcall(omap_gpio_sysinit);
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
deleted file mode 100644
index 5e04ddc18fa8..000000000000
--- a/arch/arm/plat-omap/include/plat/display.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/display.h
- *
- * Copyright (C) 2008 Nokia Corporation
- * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __ASM_ARCH_OMAP_DISPLAY_H
-#define __ASM_ARCH_OMAP_DISPLAY_H
-
-#include <linux/list.h>
-#include <linux/kobject.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <asm/atomic.h>
-
-#define DISPC_IRQ_FRAMEDONE             (1 << 0)
-#define DISPC_IRQ_VSYNC                 (1 << 1)
-#define DISPC_IRQ_EVSYNC_EVEN           (1 << 2)
-#define DISPC_IRQ_EVSYNC_ODD            (1 << 3)
-#define DISPC_IRQ_ACBIAS_COUNT_STAT     (1 << 4)
-#define DISPC_IRQ_PROG_LINE_NUM         (1 << 5)
-#define DISPC_IRQ_GFX_FIFO_UNDERFLOW    (1 << 6)
-#define DISPC_IRQ_GFX_END_WIN           (1 << 7)
-#define DISPC_IRQ_PAL_GAMMA_MASK        (1 << 8)
-#define DISPC_IRQ_OCP_ERR               (1 << 9)
-#define DISPC_IRQ_VID1_FIFO_UNDERFLOW   (1 << 10)
-#define DISPC_IRQ_VID1_END_WIN          (1 << 11)
-#define DISPC_IRQ_VID2_FIFO_UNDERFLOW   (1 << 12)
-#define DISPC_IRQ_VID2_END_WIN          (1 << 13)
-#define DISPC_IRQ_SYNC_LOST             (1 << 14)
-#define DISPC_IRQ_SYNC_LOST_DIGIT       (1 << 15)
-#define DISPC_IRQ_WAKEUP                (1 << 16)
-#define DISPC_IRQ_SYNC_LOST2            (1 << 17)
-#define DISPC_IRQ_VSYNC2                (1 << 18)
-#define DISPC_IRQ_ACBIAS_COUNT_STAT2    (1 << 21)
-#define DISPC_IRQ_FRAMEDONE2            (1 << 22)
-
-struct omap_dss_device;
-struct omap_overlay_manager;
-
-enum omap_display_type {
-        OMAP_DISPLAY_TYPE_NONE          = 0,
-        OMAP_DISPLAY_TYPE_DPI           = 1 << 0,
-        OMAP_DISPLAY_TYPE_DBI           = 1 << 1,
-        OMAP_DISPLAY_TYPE_SDI           = 1 << 2,
-        OMAP_DISPLAY_TYPE_DSI           = 1 << 3,
-        OMAP_DISPLAY_TYPE_VENC          = 1 << 4,
-        OMAP_DISPLAY_TYPE_HDMI          = 1 << 5,
-};
-
-enum omap_plane {
-        OMAP_DSS_GFX    = 0,
-        OMAP_DSS_VIDEO1 = 1,
-        OMAP_DSS_VIDEO2 = 2
-};
-
-enum omap_channel {
-        OMAP_DSS_CHANNEL_LCD    = 0,
-        OMAP_DSS_CHANNEL_DIGIT  = 1,
-        OMAP_DSS_CHANNEL_LCD2   = 2,
-};
-
-enum omap_color_mode {
-        OMAP_DSS_COLOR_CLUT1    = 1 << 0,  /* BITMAP 1 */
-        OMAP_DSS_COLOR_CLUT2    = 1 << 1,  /* BITMAP 2 */
-        OMAP_DSS_COLOR_CLUT4    = 1 << 2,  /* BITMAP 4 */
-        OMAP_DSS_COLOR_CLUT8    = 1 << 3,  /* BITMAP 8 */
-        OMAP_DSS_COLOR_RGB12U   = 1 << 4,  /* RGB12, 16-bit container */
-        OMAP_DSS_COLOR_ARGB16   = 1 << 5,  /* ARGB16 */
-        OMAP_DSS_COLOR_RGB16    = 1 << 6,  /* RGB16 */
-        OMAP_DSS_COLOR_RGB24U   = 1 << 7,  /* RGB24, 32-bit container */
-        OMAP_DSS_COLOR_RGB24P   = 1 << 8,  /* RGB24, 24-bit container */
-        OMAP_DSS_COLOR_YUV2     = 1 << 9,  /* YUV2 4:2:2 co-sited */
-        OMAP_DSS_COLOR_UYVY     = 1 << 10, /* UYVY 4:2:2 co-sited */
-        OMAP_DSS_COLOR_ARGB32   = 1 << 11, /* ARGB32 */
-        OMAP_DSS_COLOR_RGBA32   = 1 << 12, /* RGBA32 */
-        OMAP_DSS_COLOR_RGBX32   = 1 << 13, /* RGBx32 */
-};
-
-enum omap_lcd_display_type {
-        OMAP_DSS_LCD_DISPLAY_STN,
-        OMAP_DSS_LCD_DISPLAY_TFT,
-};
-
-enum omap_dss_load_mode {
-        OMAP_DSS_LOAD_CLUT_AND_FRAME    = 0,
-        OMAP_DSS_LOAD_CLUT_ONLY         = 1,
-        OMAP_DSS_LOAD_FRAME_ONLY        = 2,
-        OMAP_DSS_LOAD_CLUT_ONCE_FRAME   = 3,
-};
-
-enum omap_dss_trans_key_type {
-        OMAP_DSS_COLOR_KEY_GFX_DST = 0,
-        OMAP_DSS_COLOR_KEY_VID_SRC = 1,
-};
-
-enum omap_rfbi_te_mode {
-        OMAP_DSS_RFBI_TE_MODE_1 = 1,
-        OMAP_DSS_RFBI_TE_MODE_2 = 2,
-};
-
-enum omap_panel_config {
-        OMAP_DSS_LCD_IVS                = 1<<0,
-        OMAP_DSS_LCD_IHS                = 1<<1,
-        OMAP_DSS_LCD_IPC                = 1<<2,
-        OMAP_DSS_LCD_IEO                = 1<<3,
-        OMAP_DSS_LCD_RF                 = 1<<4,
-        OMAP_DSS_LCD_ONOFF              = 1<<5,
-
-        OMAP_DSS_LCD_TFT                = 1<<20,
-};
-
-enum omap_dss_venc_type {
-        OMAP_DSS_VENC_TYPE_COMPOSITE,
-        OMAP_DSS_VENC_TYPE_SVIDEO,
-};
-
-enum omap_display_caps {
-        OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE      = 1 << 0,
-        OMAP_DSS_DISPLAY_CAP_TEAR_ELIM          = 1 << 1,
-};
-
-enum omap_dss_update_mode {
-        OMAP_DSS_UPDATE_DISABLED = 0,
-        OMAP_DSS_UPDATE_AUTO,
-        OMAP_DSS_UPDATE_MANUAL,
-};
-
-enum omap_dss_display_state {
-        OMAP_DSS_DISPLAY_DISABLED = 0,
-        OMAP_DSS_DISPLAY_ACTIVE,
-        OMAP_DSS_DISPLAY_SUSPENDED,
-};
-
-/* XXX perhaps this should be removed */
-enum omap_dss_overlay_managers {
-        OMAP_DSS_OVL_MGR_LCD,
-        OMAP_DSS_OVL_MGR_TV,
-        OMAP_DSS_OVL_MGR_LCD2,
-};
-
-enum omap_dss_rotation_type {
-        OMAP_DSS_ROT_DMA = 0,
-        OMAP_DSS_ROT_VRFB = 1,
-};
-
-/* clockwise rotation angle */
-enum omap_dss_rotation_angle {
-        OMAP_DSS_ROT_0   = 0,
-        OMAP_DSS_ROT_90  = 1,
-        OMAP_DSS_ROT_180 = 2,
-        OMAP_DSS_ROT_270 = 3,
-};
-
-enum omap_overlay_caps {
-        OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
-        OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
-};
-
-enum omap_overlay_manager_caps {
-        OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
-};
-
-/* RFBI */
-
-struct rfbi_timings {
-        int cs_on_time;
-        int cs_off_time;
-        int we_on_time;
-        int we_off_time;
-        int re_on_time;
-        int re_off_time;
-        int we_cycle_time;
-        int re_cycle_time;
-        int cs_pulse_width;
-        int access_time;
-
-        int clk_div;
-
-        u32 tim[5];             /* set by rfbi_convert_timings() */
-
-        int converted;
-};
-
-void omap_rfbi_write_command(const void *buf, u32 len);
-void omap_rfbi_read_data(void *buf, u32 len);
-void omap_rfbi_write_data(const void *buf, u32 len);
-void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
-                u16 x, u16 y,
-                u16 w, u16 h);
-int omap_rfbi_enable_te(bool enable, unsigned line);
-int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
-                             unsigned hs_pulse_time, unsigned vs_pulse_time,
-                             int hs_pol_inv, int vs_pol_inv, int extif_div);
-
-/* DSI */
-void dsi_bus_lock(void);
-void dsi_bus_unlock(void);
-int dsi_vc_dcs_write(int channel, u8 *data, int len);
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2);
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
-int dsi_vc_send_null(int channel);
-int dsi_vc_send_bta_sync(int channel);
-
-/* Board specific data */
-struct omap_dss_board_info {
-        int (*get_last_off_on_transaction_id)(struct device *dev);
-        int num_devices;
-        struct omap_dss_device **devices;
-        struct omap_dss_device *default_device;
-};
-
-#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
-/* Init with the board info */
-extern int omap_display_init(struct omap_dss_board_info *board_data);
-#else
-static inline int omap_display_init(struct omap_dss_board_info *board_data)
-{
-        return 0;
-}
-#endif
-
-struct omap_display_platform_data {
-        struct omap_dss_board_info *board_data;
-        /* TODO: Additional members to be added when PM is considered */
-
-        bool (*opt_clock_available)(const char *clk_role);
-};
-
-struct omap_video_timings {
-        /* Unit: pixels */
-        u16 x_res;
-        /* Unit: pixels */
-        u16 y_res;
-        /* Unit: KHz */
-        u32 pixel_clock;
-        /* Unit: pixel clocks */
-        u16 hsw;        /* Horizontal synchronization pulse width */
-        /* Unit: pixel clocks */
-        u16 hfp;        /* Horizontal front porch */
-        /* Unit: pixel clocks */
-        u16 hbp;        /* Horizontal back porch */
-        /* Unit: line clocks */
-        u16 vsw;        /* Vertical synchronization pulse width */
-        /* Unit: line clocks */
-        u16 vfp;        /* Vertical front porch */
-        /* Unit: line clocks */
-        u16 vbp;        /* Vertical back porch */
-};
-
-#ifdef CONFIG_OMAP2_DSS_VENC
-/* Hardcoded timings for tv modes. Venc only uses these to
- * identify the mode, and does not actually use the configs
- * itself. However, the configs should be something that
- * a normal monitor can also show */
-extern const struct omap_video_timings omap_dss_pal_timings;
-extern const struct omap_video_timings omap_dss_ntsc_timings;
-#endif
-
-struct omap_overlay_info {
-        bool enabled;
-
-        u32 paddr;
-        void __iomem *vaddr;
-        u16 screen_width;
-        u16 width;
-        u16 height;
-        enum omap_color_mode color_mode;
-        u8 rotation;
-        enum omap_dss_rotation_type rotation_type;
-        bool mirror;
-
-        u16 pos_x;
-        u16 pos_y;
-        u16 out_width;  /* if 0, out_width == width */
-        u16 out_height; /* if 0, out_height == height */
-        u8 global_alpha;
-        u8 pre_mult_alpha;
-};
-
-struct omap_overlay {
-        struct kobject kobj;
-        struct list_head list;
-
-        /* static fields */
-        const char *name;
-        int id;
-        enum omap_color_mode supported_modes;
-        enum omap_overlay_caps caps;
-
-        /* dynamic fields */
-        struct omap_overlay_manager *manager;
-        struct omap_overlay_info info;
-
-        /* if true, info has been changed, but not applied() yet */
-        bool info_dirty;
-
-        int (*set_manager)(struct omap_overlay *ovl,
-                struct omap_overlay_manager *mgr);
-        int (*unset_manager)(struct omap_overlay *ovl);
-
-        int (*set_overlay_info)(struct omap_overlay *ovl,
-                        struct omap_overlay_info *info);
-        void (*get_overlay_info)(struct omap_overlay *ovl,
-                        struct omap_overlay_info *info);
-
-        int (*wait_for_go)(struct omap_overlay *ovl);
-};
-
-struct omap_overlay_manager_info {
-        u32 default_color;
-
-        enum omap_dss_trans_key_type trans_key_type;
-        u32 trans_key;
-        bool trans_enabled;
-
-        bool alpha_enabled;
-};
-
-struct omap_overlay_manager {
-        struct kobject kobj;
-        struct list_head list;
-
-        /* static fields */
-        const char *name;
-        int id;
-        enum omap_overlay_manager_caps caps;
-        int num_overlays;
-        struct omap_overlay **overlays;
-        enum omap_display_type supported_displays;
-
-        /* dynamic fields */
-        struct omap_dss_device *device;
-        struct omap_overlay_manager_info info;
-
-        bool device_changed;
-        /* if true, info has been changed but not applied() yet */
-        bool info_dirty;
-
-        int (*set_device)(struct omap_overlay_manager *mgr,
-                struct omap_dss_device *dssdev);
-        int (*unset_device)(struct omap_overlay_manager *mgr);
-
-        int (*set_manager_info)(struct omap_overlay_manager *mgr,
-                        struct omap_overlay_manager_info *info);
-        void (*get_manager_info)(struct omap_overlay_manager *mgr,
-                        struct omap_overlay_manager_info *info);
-
-        int (*apply)(struct omap_overlay_manager *mgr);
-        int (*wait_for_go)(struct omap_overlay_manager *mgr);
-        int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
-
-        int (*enable)(struct omap_overlay_manager *mgr);
-        int (*disable)(struct omap_overlay_manager *mgr);
-};
-
-struct omap_dss_device {
-        struct device dev;
-
-        enum omap_display_type type;
-
-        enum omap_channel channel;
-
-        union {
-                struct {
-                        u8 data_lines;
-                } dpi;
-
-                struct {
-                        u8 channel;
-                        u8 data_lines;
-                } rfbi;
-
-                struct {
-                        u8 datapairs;
-                } sdi;
-
-                struct {
-                        u8 clk_lane;
-                        u8 clk_pol;
-                        u8 data1_lane;
-                        u8 data1_pol;
-                        u8 data2_lane;
-                        u8 data2_pol;
-
-                        struct {
-                                u16 regn;
-                                u16 regm;
-                                u16 regm_dispc;
-                                u16 regm_dsi;
-
-                                u16 lp_clk_div;
-
-                                u16 lck_div;
-                                u16 pck_div;
-                        } div;
-
-                        bool ext_te;
-                        u8 ext_te_gpio;
-                } dsi;
-
-                struct {
-                        enum omap_dss_venc_type type;
-                        bool invert_polarity;
-                } venc;
-        } phy;
-
-        struct {
-                struct omap_video_timings timings;
-
-                int acbi;       /* ac-bias pin transitions per interrupt */
-                /* Unit: line clocks */
-                int acb;        /* ac-bias pin frequency */
-
-                enum omap_panel_config config;
-        } panel;
-
-        struct {
-                u8 pixel_size;
-                struct rfbi_timings rfbi_timings;
-        } ctrl;
-
-        int reset_gpio;
-
-        int max_backlight_level;
-
-        const char *name;
-
-        /* used to match device to driver */
-        const char *driver_name;
-
-        void *data;
-
-        struct omap_dss_driver *driver;
-
-        /* helper variable for driver suspend/resume */
-        bool activate_after_resume;
-
-        enum omap_display_caps caps;
-
-        struct omap_overlay_manager *manager;
-
-        enum omap_dss_display_state state;
-
-        /* platform specific  */
-        int (*platform_enable)(struct omap_dss_device *dssdev);
-        void (*platform_disable)(struct omap_dss_device *dssdev);
-        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
-        int (*get_backlight)(struct omap_dss_device *dssdev);
-};
-
-struct omap_dss_driver {
-        struct device_driver driver;
-
-        int (*probe)(struct omap_dss_device *);
-        void (*remove)(struct omap_dss_device *);
-
-        int (*enable)(struct omap_dss_device *display);
-        void (*disable)(struct omap_dss_device *display);
-        int (*suspend)(struct omap_dss_device *display);
-        int (*resume)(struct omap_dss_device *display);
-        int (*run_test)(struct omap_dss_device *display, int test);
-
-        int (*set_update_mode)(struct omap_dss_device *dssdev,
-                        enum omap_dss_update_mode);
-        enum omap_dss_update_mode (*get_update_mode)(
-                        struct omap_dss_device *dssdev);
-
-        int (*update)(struct omap_dss_device *dssdev,
-                               u16 x, u16 y, u16 w, u16 h);
-        int (*sync)(struct omap_dss_device *dssdev);
-
-        int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
-        int (*get_te)(struct omap_dss_device *dssdev);
-
-        u8 (*get_rotate)(struct omap_dss_device *dssdev);
-        int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
-
-        bool (*get_mirror)(struct omap_dss_device *dssdev);
-        int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
-
-        int (*memory_read)(struct omap_dss_device *dssdev,
-                        void *buf, size_t size,
-                        u16 x, u16 y, u16 w, u16 h);
-
-        void (*get_resolution)(struct omap_dss_device *dssdev,
-                        u16 *xres, u16 *yres);
-        int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
-
-        int (*check_timings)(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-        void (*set_timings)(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-        void (*get_timings)(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-
-        int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
-        u32 (*get_wss)(struct omap_dss_device *dssdev);
-};
-
-int omap_dss_register_driver(struct omap_dss_driver *);
-void omap_dss_unregister_driver(struct omap_dss_driver *);
-
-int omap_dss_register_device(struct omap_dss_device *);
-void omap_dss_unregister_device(struct omap_dss_device *);
-
-void omap_dss_get_device(struct omap_dss_device *dssdev);
-void omap_dss_put_device(struct omap_dss_device *dssdev);
-#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
-struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
-struct omap_dss_device *omap_dss_find_device(void *data,
-                int (*match)(struct omap_dss_device *dssdev, void *data));
-
-int omap_dss_start_device(struct omap_dss_device *dssdev);
-void omap_dss_stop_device(struct omap_dss_device *dssdev);
-
-int omap_dss_get_num_overlay_managers(void);
-struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
-
-int omap_dss_get_num_overlays(void);
-struct omap_overlay *omap_dss_get_overlay(int num);
-
-void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
-                u16 *xres, u16 *yres);
-int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
-
-typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
-int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-
-int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
-int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
-                unsigned long timeout);
-
-#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
-#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
-
-void omapdss_dsi_vc_enable_hs(int channel, bool enable);
-int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
-
-int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
-                                    u16 *x, u16 *y, u16 *w, u16 *h,
-                                    bool enlarge_update_area);
-int omap_dsi_update(struct omap_dss_device *dssdev,
-                int channel,
-                u16 x, u16 y, u16 w, u16 h,
-                void (*callback)(int, void *), void *data);
-int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
-int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
-void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
-
-int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
-
-int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
-void dpi_set_timings(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-int dpi_check_timings(struct omap_dss_device *dssdev,
-                        struct omap_video_timings *timings);
-
-int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
-
-int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
-int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
-                u16 *x, u16 *y, u16 *w, u16 *h);
-int omap_rfbi_update(struct omap_dss_device *dssdev,
-                u16 x, u16 y, u16 w, u16 h,
-                void (*callback)(void *), void *data);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h
index cac2e8ac6968..ec97e00cb581 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -52,6 +52,109 @@
 
 #define OMAP34XX_NR_GPIOS               6
 
+/*
+ * OMAP1510 GPIO registers
+ */
+#define OMAP1510_GPIO_DATA_INPUT        0x00
+#define OMAP1510_GPIO_DATA_OUTPUT       0x04
+#define OMAP1510_GPIO_DIR_CONTROL       0x08
+#define OMAP1510_GPIO_INT_CONTROL       0x0c
+#define OMAP1510_GPIO_INT_MASK          0x10
+#define OMAP1510_GPIO_INT_STATUS        0x14
+#define OMAP1510_GPIO_PIN_CONTROL       0x18
+
+#define OMAP1510_IH_GPIO_BASE           64
+
+/*
+ * OMAP1610 specific GPIO registers
+ */
+#define OMAP1610_GPIO_REVISION          0x0000
+#define OMAP1610_GPIO_SYSCONFIG         0x0010
+#define OMAP1610_GPIO_SYSSTATUS         0x0014
+#define OMAP1610_GPIO_IRQSTATUS1        0x0018
+#define OMAP1610_GPIO_IRQENABLE1        0x001c
+#define OMAP1610_GPIO_WAKEUPENABLE      0x0028
+#define OMAP1610_GPIO_DATAIN            0x002c
+#define OMAP1610_GPIO_DATAOUT           0x0030
+#define OMAP1610_GPIO_DIRECTION         0x0034
+#define OMAP1610_GPIO_EDGE_CTRL1        0x0038
+#define OMAP1610_GPIO_EDGE_CTRL2        0x003c
+#define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
+#define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
+#define OMAP1610_GPIO_CLEAR_DATAOUT     0x00b0
+#define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
+#define OMAP1610_GPIO_SET_WAKEUPENA     0x00e8
+#define OMAP1610_GPIO_SET_DATAOUT       0x00f0
+
+/*
+ * OMAP7XX specific GPIO registers
+ */
+#define OMAP7XX_GPIO_DATA_INPUT         0x00
+#define OMAP7XX_GPIO_DATA_OUTPUT        0x04
+#define OMAP7XX_GPIO_DIR_CONTROL        0x08
+#define OMAP7XX_GPIO_INT_CONTROL        0x0c
+#define OMAP7XX_GPIO_INT_MASK           0x10
+#define OMAP7XX_GPIO_INT_STATUS         0x14
+
+/*
+ * omap2+ specific GPIO registers
+ */
+#define OMAP24XX_GPIO_REVISION          0x0000
+#define OMAP24XX_GPIO_IRQSTATUS1        0x0018
+#define OMAP24XX_GPIO_IRQSTATUS2        0x0028
+#define OMAP24XX_GPIO_IRQENABLE2        0x002c
+#define OMAP24XX_GPIO_IRQENABLE1        0x001c
+#define OMAP24XX_GPIO_WAKE_EN           0x0020
+#define OMAP24XX_GPIO_CTRL              0x0030
+#define OMAP24XX_GPIO_OE                0x0034
+#define OMAP24XX_GPIO_DATAIN            0x0038
+#define OMAP24XX_GPIO_DATAOUT           0x003c
+#define OMAP24XX_GPIO_LEVELDETECT0      0x0040
+#define OMAP24XX_GPIO_LEVELDETECT1      0x0044
+#define OMAP24XX_GPIO_RISINGDETECT      0x0048
+#define OMAP24XX_GPIO_FALLINGDETECT     0x004c
+#define OMAP24XX_GPIO_DEBOUNCE_EN       0x0050
+#define OMAP24XX_GPIO_DEBOUNCE_VAL      0x0054
+#define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
+#define OMAP24XX_GPIO_SETIRQENABLE1     0x0064
+#define OMAP24XX_GPIO_CLEARWKUENA       0x0080
+#define OMAP24XX_GPIO_SETWKUENA         0x0084
+#define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
+#define OMAP24XX_GPIO_SETDATAOUT        0x0094
+
+#define OMAP4_GPIO_REVISION             0x0000
+#define OMAP4_GPIO_EOI                  0x0020
+#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
+#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
+#define OMAP4_GPIO_IRQSTATUS0           0x002c
+#define OMAP4_GPIO_IRQSTATUS1           0x0030
+#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
+#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
+#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
+#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
+#define OMAP4_GPIO_IRQWAKEN0            0x0044
+#define OMAP4_GPIO_IRQWAKEN1            0x0048
+#define OMAP4_GPIO_IRQENABLE1           0x011c
+#define OMAP4_GPIO_WAKE_EN              0x0120
+#define OMAP4_GPIO_IRQSTATUS2           0x0128
+#define OMAP4_GPIO_IRQENABLE2           0x012c
+#define OMAP4_GPIO_CTRL                 0x0130
+#define OMAP4_GPIO_OE                   0x0134
+#define OMAP4_GPIO_DATAIN               0x0138
+#define OMAP4_GPIO_DATAOUT              0x013c
+#define OMAP4_GPIO_LEVELDETECT0         0x0140
+#define OMAP4_GPIO_LEVELDETECT1         0x0144
+#define OMAP4_GPIO_RISINGDETECT         0x0148
+#define OMAP4_GPIO_FALLINGDETECT        0x014c
+#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
+#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
+#define OMAP4_GPIO_CLEARIRQENABLE1      0x0160
+#define OMAP4_GPIO_SETIRQENABLE1        0x0164
+#define OMAP4_GPIO_CLEARWKUENA          0x0180
+#define OMAP4_GPIO_SETWKUENA            0x0184
+#define OMAP4_GPIO_CLEARDATAOUT         0x0190
+#define OMAP4_GPIO_SETDATAOUT           0x0194
+
 #define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
 #define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
 
diff --git a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
index 872de0bf1e6b..ea6c9c88c725 100644
--- a/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
+++ b/arch/arm/plat-omap/include/plat/gpmc-smsc911x.h
@@ -14,14 +14,14 @@
 #ifndef __ASM_ARCH_OMAP_GPMC_SMSC911X_H__
 
 struct omap_smsc911x_platform_data {
+        int     id;
         int     cs;
         int     gpio_irq;
         int     gpio_reset;
         u32     flags;
 };
 
-#if defined(CONFIG_SMSC911X) || \
-        defined(CONFIG_SMSC911X_MODULE)
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 
 extern void gpmc_smsc911x_init(struct omap_smsc911x_platform_data *d);
 
diff --git a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
deleted file mode 100644
index 01ab6572ccbb..000000000000
--- a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
-#define __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
-
-#include "display.h"
-
-/**
- * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
- * @name: panel name
- * @use_ext_te: use external TE
- * @ext_te_gpio: external TE GPIO
- * @use_esd_check: perform ESD checks
- * @max_backlight_level: maximum backlight level
- * @set_backlight: pointer to backlight set function
- * @get_backlight: pointer to backlight get function
- */
-struct nokia_dsi_panel_data {
-        const char *name;
-
-        int reset_gpio;
-
-        bool use_ext_te;
-        int ext_te_gpio;
-
-        bool use_esd_check;
-
-        int max_backlight_level;
-        int (*set_backlight)(struct omap_dss_device *dssdev, int level);
-        int (*get_backlight)(struct omap_dss_device *dssdev);
-};
-
-#endif /* __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H */
diff --git a/arch/arm/plat-omap/include/plat/panel-generic-dpi.h b/arch/arm/plat-omap/include/plat/panel-generic-dpi.h
deleted file mode 100644
index 790619734bcd..000000000000
--- a/arch/arm/plat-omap/include/plat/panel-generic-dpi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Header for generic DPI panel driver
- *
- * Copyright (C) 2010 Canonical Ltd.
- * Author: Bryan Wu <bryan.wu@canonical.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H
-#define __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H
-
-#include "display.h"
-
-/**
- * struct panel_generic_dpi_data - panel driver configuration data
- * @name: panel name
- * @platform_enable: platform specific panel enable function
- * @platform_disable: platform specific panel disable function
- */
-struct panel_generic_dpi_data {
-        const char *name;
-        int (*platform_enable)(struct omap_dss_device *dssdev);
-        void (*platform_disable)(struct omap_dss_device *dssdev);
-};
-
-#endif /* __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 565d2664f5a7..ac4b60d9aa29 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -129,7 +129,6 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 DEBUG_LL_OMAP1(3, sx1);
 
                 /* omap2 based boards using UART1 */
-                DEBUG_LL_OMAP2(1, omap2evm);
                 DEBUG_LL_OMAP2(1, omap_2430sdp);
                 DEBUG_LL_OMAP2(1, omap_apollon);
                 DEBUG_LL_OMAP2(1, omap_h4);
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 02b96c8f6a17..17d3c939775c 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -113,7 +113,7 @@ extern int omap4430_phy_suspend(struct device *dev, int suspend);
 extern void am35x_musb_reset(void);
 extern void am35x_musb_phy_power(u8 on);
 extern void am35x_musb_clear_irq(void);
-extern void am35x_musb_set_mode(u8 musb_mode);
+extern void am35x_set_mode(u8 musb_mode);
 
 /*
  * FIXME correct answer depends on hmc_mode,
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 6751bcf7b888..e98f5c5c7879 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,7 +7,7 @@
 
 config PLAT_S5P
         bool
-        depends on (ARCH_S5P64X0 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
+        depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4)
         default y
         select ARM_VIC if !ARCH_EXYNOS4
         select ARM_GIC if ARCH_EXYNOS4
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 5cf5e721e6ca..bbc2aa7449ca 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -21,7 +21,6 @@
 
 #include <plat/cpu.h>
 #include <plat/s5p6440.h>
-#include <plat/s5p6442.h>
 #include <plat/s5p6450.h>
 #include <plat/s5pc100.h>
 #include <plat/s5pv210.h>
@@ -30,7 +29,6 @@
 /* table of supported CPUs */
 
 static const char name_s5p6440[] = "S5P6440";
-static const char name_s5p6442[] = "S5P6442";
 static const char name_s5p6450[] = "S5P6450";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
@@ -46,14 +44,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .init           = s5p64x0_init,
                 .name           = name_s5p6440,
         }, {
-                .idcode         = 0x36442000,
-                .idmask         = 0xfffff000,
-                .map_io         = s5p6442_map_io,
-                .init_clocks    = s5p6442_init_clocks,
-                .init_uarts     = s5p6442_init_uarts,
-                .init           = s5p6442_init,
-                .name           = name_s5p6442,
-        }, {
                 .idcode         = 0x36450000,
                 .idmask         = 0xfffff000,
                 .map_io         = s5p6450_map_io,
diff --git a/arch/arm/plat-s5p/include/plat/s5p6442.h b/arch/arm/plat-s5p/include/plat/s5p6442.h
deleted file mode 100644
index 7b8801349c94..000000000000
--- a/arch/arm/plat-s5p/include/plat/s5p6442.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* arch/arm/plat-s5p/include/plat/s5p6442.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * Header file for s5p6442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* Common init code for S5P6442 related SoCs */
-
-extern void s5p6442_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s5p6442_register_clocks(void);
-extern void s5p6442_setup_clocks(void);
-
-#ifdef CONFIG_CPU_S5P6442
-
-extern  int s5p6442_init(void);
-extern void s5p6442_init_irq(void);
-extern void s5p6442_map_io(void);
-extern void s5p6442_init_clocks(int xtal);
-
-#define s5p6442_init_uarts s5p6442_common_init_uarts
-
-#else
-#define s5p6442_init_clocks NULL
-#define s5p6442_init_uarts NULL
-#define s5p6442_map_io NULL
-#define s5p6442_init NULL
-#endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index e9de58a2e294..53eb15b0a07d 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -19,7 +19,6 @@ obj-y				+= gpio.o
 obj-y                           += gpio-config.o
 obj-y                           += dev-asocdma.o
 
-obj-$(CONFIG_SAMSUNG_GPIOLIB_4BIT)      += gpiolib.o
 obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
 
 obj-$(CONFIG_SAMSUNG_IRQ_UART)  += irq-uart.o
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c
deleted file mode 100644
index ea37c0461788..000000000000
--- a/arch/arm/plat-samsung/gpiolib.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/* arch/arm/plat-samsung/gpiolib.c
- *
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * Copyright (c) 2009 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com/
- *
- * SAMSUNG - GPIOlib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <plat/gpio-core.h>
-#include <plat/gpio-cfg.h>
-#include <plat/gpio-cfg-helpers.h>
-
-#ifndef DEBUG_GPIO
-#define gpio_dbg(x...) do { } while (0)
-#else
-#define gpio_dbg(x...) printk(KERN_DEBUG x)
-#endif
-
-/* The samsung_gpiolib_4bit routines are to control the gpio banks where
- * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
- * following example:
- *
- * base + 0x00: Control register, 4 bits per gpio
- *              gpio n: 4 bits starting at (4*n)
- *              0000 = input, 0001 = output, others mean special-function
- * base + 0x04: Data register, 1 bit per gpio
- *              bit n: data bit n
- *
- * Note, since the data register is one bit per gpio and is at base + 0x4
- * we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
- * the output.
-*/
-
-static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
-                                      unsigned int offset)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long con;
-
-        con = __raw_readl(base + GPIOCON_OFF);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, base + GPIOCON_OFF);
-
-        gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
-
-        return 0;
-}
-
-static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
-                                       unsigned int offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        unsigned long con;
-        unsigned long dat;
-
-        con = __raw_readl(base + GPIOCON_OFF);
-        con &= ~(0xf << con_4bit_shift(offset));
-        con |= 0x1 << con_4bit_shift(offset);
-
-        dat = __raw_readl(base + GPIODAT_OFF);
-
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-
-        __raw_writel(dat, base + GPIODAT_OFF);
-        __raw_writel(con, base + GPIOCON_OFF);
-        __raw_writel(dat, base + GPIODAT_OFF);
-
-        gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
-
-        return 0;
-}
-
-/* The next set of routines are for the case where the GPIO configuration
- * registers are 4 bits per GPIO but there is more than one register (the
- * bank has more than 8 GPIOs.
- *
- * This case is the similar to the 4 bit case, but the registers are as
- * follows:
- *
- * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
- *              gpio n: 4 bits starting at (4*n)
- *              0000 = input, 0001 = output, others mean special-function
- * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
- *              gpio n: 4 bits starting at (4*n)
- *              0000 = input, 0001 = output, others mean special-function
- * base + 0x08: Data register, 1 bit per gpio
- *              bit n: data bit n
- *
- * To allow us to use the s3c_gpiolib_get and s3c_gpiolib_set routines we
- * store the 'base + 0x4' address so that these routines see the data
- * register at ourchip->base + 0x04.
- */
-
-static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
-                                       unsigned int offset)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-
-        if (offset > 7)
-                offset -= 8;
-        else
-                regcon -= 4;
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(offset));
-        __raw_writel(con, regcon);
-
-        gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
-
-        return 0;
-}
-
-static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
-                                        unsigned int offset, int value)
-{
-        struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
-        void __iomem *base = ourchip->base;
-        void __iomem *regcon = base;
-        unsigned long con;
-        unsigned long dat;
-        unsigned con_offset = offset;
-
-        if (con_offset > 7)
-                con_offset -= 8;
-        else
-                regcon -= 4;
-
-        con = __raw_readl(regcon);
-        con &= ~(0xf << con_4bit_shift(con_offset));
-        con |= 0x1 << con_4bit_shift(con_offset);
-
-        dat = __raw_readl(base + GPIODAT_OFF);
-
-        if (value)
-                dat |= 1 << offset;
-        else
-                dat &= ~(1 << offset);
-
-        __raw_writel(dat, base + GPIODAT_OFF);
-        __raw_writel(con, regcon);
-        __raw_writel(dat, base + GPIODAT_OFF);
-
-        gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
-
-        return 0;
-}
-
-void __init samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip)
-{
-        chip->chip.direction_input = samsung_gpiolib_4bit_input;
-        chip->chip.direction_output = samsung_gpiolib_4bit_output;
-        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
-}
-
-void __init samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip)
-{
-        chip->chip.direction_input = samsung_gpiolib_4bit2_input;
-        chip->chip.direction_output = samsung_gpiolib_4bit2_output;
-        chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
-}
-
-void __init samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip,
-                                           int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                samsung_gpiolib_add_4bit(chip);
-                s3c_gpiolib_add(chip);
-        }
-}
-
-void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
-                                            int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++) {
-                samsung_gpiolib_add_4bit2(chip);
-                s3c_gpiolib_add(chip);
-        }
-}
-
-void __init samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip,
-                                           int nr_chips)
-{
-        for (; nr_chips > 0; nr_chips--, chip++)
-                s3c_gpiolib_add(chip);
-}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 3aedac0034ba..c0a5741b23e6 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -86,7 +86,6 @@ extern struct sysdev_class s3c2443_sysclass;
 extern struct sysdev_class s3c6410_sysclass;
 extern struct sysdev_class s3c64xx_sysclass;
 extern struct sysdev_class s5p64x0_sysclass;
-extern struct sysdev_class s5p6442_sysclass;
 extern struct sysdev_class s5pv210_sysclass;
 extern struct sysdev_class exynos4_sysclass;
 
diff --git a/arch/arm/plat-samsung/include/plat/debug-macro.S b/arch/arm/plat-samsung/include/plat/debug-macro.S
index dc6efd90e8ff..207e275362a8 100644
--- a/arch/arm/plat-samsung/include/plat/debug-macro.S
+++ b/arch/arm/plat-samsung/include/plat/debug-macro.S
@@ -11,7 +11,7 @@
 
 #include <plat/regs-serial.h>
 
-/* The S5PV210/S5PC110 and S5P6442 implementations are as belows. */
+/* The S5PV210/S5PC110 implementations are as belows. */
 
         .macro fifo_level_s5pv210 rd, rx
                 ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 39818d8da420..b61b8ee7cc52 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -111,12 +111,6 @@ extern struct platform_device exynos4_device_spdif;
 extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_ahci;
 
-extern struct platform_device s5p6442_device_pcm0;
-extern struct platform_device s5p6442_device_pcm1;
-extern struct platform_device s5p6442_device_iis0;
-extern struct platform_device s5p6442_device_iis1;
-extern struct platform_device s5p6442_device_spi;
-
 extern struct platform_device s5p6440_device_pcm;
 extern struct platform_device s5p6440_device_iis;
 
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 788837e99cb3..c151c5f94a87 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -194,7 +194,7 @@
 #define S3C64XX_UINTSP          0x34
 #define S3C64XX_UINTM           0x38
 
-/* Following are specific to S5PV210 and S5P6442 */
+/* Following are specific to S5PV210 */
 #define S5PV210_UCON_CLKMASK    (1<<10)
 #define S5PV210_UCON_PCLK       (0<<10)
 #define S5PV210_UCON_UCLK       (1<<10)
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index ff1a561b326e..0ffe34a21554 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -69,6 +69,5 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
-extern void s5p6442_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
 
 #endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h
index 72444d97f80c..b70c19bab63a 100644
--- a/arch/avr32/include/asm/bitops.h
+++ b/arch/avr32/include/asm/bitops.h
@@ -270,14 +270,21 @@ static inline int __fls(unsigned long word)
 
 unsigned long find_first_zero_bit(const unsigned long *addr,
                                   unsigned long size);
+#define find_first_zero_bit find_first_zero_bit
+
 unsigned long find_next_zero_bit(const unsigned long *addr,
                                  unsigned long size,
                                  unsigned long offset);
+#define find_next_zero_bit find_next_zero_bit
+
 unsigned long find_first_bit(const unsigned long *addr,
                              unsigned long size);
+#define find_first_bit find_first_bit
+
 unsigned long find_next_bit(const unsigned long *addr,
                                  unsigned long size,
                                  unsigned long offset);
+#define find_next_bit find_next_bit
 
 /*
  * ffs: find first bit set. This is defined the same way as
@@ -299,6 +306,14 @@ static inline int ffs(unsigned long word)
 #include <asm-generic/bitops/hweight.h>
 #include <asm-generic/bitops/lock.h>
 
+extern unsigned long find_next_zero_bit_le(const void *addr,
+                unsigned long size, unsigned long offset);
+#define find_next_zero_bit_le find_next_zero_bit_le
+
+extern unsigned long find_next_bit_le(const void *addr,
+                unsigned long size, unsigned long offset);
+#define find_next_bit_le find_next_bit_le
+
 #include <asm-generic/bitops/le.h>
 #include <asm-generic/bitops/ext2-atomic.h>
 
diff --git a/arch/avr32/include/asm/unistd.h b/arch/avr32/include/asm/unistd.h
index 89861a27543e..f714544e5560 100644
--- a/arch/avr32/include/asm/unistd.h
+++ b/arch/avr32/include/asm/unistd.h
@@ -299,9 +299,10 @@
 #define __NR_signalfd           279
 /* 280 was __NR_timerfd */
 #define __NR_eventfd            281
+#define __NR_setns              283
 
 #ifdef __KERNEL__
-#define NR_syscalls             282
+#define NR_syscalls             284
 
 /* Old stuff */
 #define __IGNORE_uselib
diff --git a/arch/avr32/kernel/syscall_table.S b/arch/avr32/kernel/syscall_table.S
index e76bad16b0f0..c7fd394d28a4 100644
--- a/arch/avr32/kernel/syscall_table.S
+++ b/arch/avr32/kernel/syscall_table.S
@@ -296,4 +296,5 @@ sys_call_table:
         .long   sys_ni_syscall          /* 280, was sys_timerfd */
         .long   sys_eventfd
         .long   sys_recvmmsg
+        .long   sys_setns
         .long   sys_ni_syscall          /* r8 is saturated at nr_syscalls */
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
index bfc9d071db9b..aa677e2a3823 100644
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ b/arch/avr32/mach-at32ap/at32ap700x.c
@@ -1014,6 +1014,7 @@ static struct platform_device *__initdata at32_usarts[4];
 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
 {
         struct platform_device *pdev;
+        struct atmel_uart_data *pdata;
 
         switch (hw_id) {
         case 0:
@@ -1042,7 +1043,8 @@ void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
                 data->regs = (void __iomem *)pdev->resource[0].start;
         }
 
-        pdev->id = line;
+        pdata = pdev->dev.platform_data;
+        pdata->num = portnr;
         at32_usarts[line] = pdev;
 }
 
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index 61740201b311..679458d9a622 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -33,6 +33,7 @@ extern struct platform_device *atmel_default_console_device;
 #define ATMEL_USART_CLK         0x04
 
 struct atmel_uart_data {
+        int             num;            /* port num */
         short           use_dma_tx;     /* use transmit DMA? */
         short           use_dma_rx;     /* use receive DMA? */
         void __iomem    *regs;          /* virtual base address, if any */
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index a7314d44b17b..2798c2d4a1cf 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -25,8 +25,6 @@
 #include <asm/setup.h>
 #include <asm/sections.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_data;
 
 struct page *empty_zero_page;
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8addb1220b4f..d619b17c4413 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -24,11 +24,13 @@ config BLACKFIN
         select HAVE_FUNCTION_TRACER
         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
         select HAVE_IDE
+        select HAVE_IRQ_WORK
         select HAVE_KERNEL_GZIP if RAMKERNEL
         select HAVE_KERNEL_BZIP2 if RAMKERNEL
         select HAVE_KERNEL_LZMA if RAMKERNEL
         select HAVE_KERNEL_LZO if RAMKERNEL
         select HAVE_OPROFILE
+        select HAVE_PERF_EVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_ATOMIC64
@@ -45,9 +47,6 @@ config GENERIC_BUG
 config ZONE_DMA
         def_bool y
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
 config GENERIC_GPIO
         def_bool y
 
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 2641731f24cd..e2a3d4c8ab9a 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -9,15 +9,6 @@ config DEBUG_STACKOVERFLOW
           This option will cause messages to be printed if free stack space
           drops below a certain limit.
 
-config DEBUG_STACK_USAGE
-        bool "Enable stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T output.
-
-          This option will slow down process creation somewhat.
-
 config DEBUG_VERBOSE
         bool "Verbose fault messages"
         default y
@@ -32,7 +23,7 @@ config DEBUG_VERBOSE
           Most people should say N here.
 
 config DEBUG_MMRS
-        bool "Generate Blackfin MMR tree"
+        tristate "Generate Blackfin MMR tree"
         select DEBUG_FS
         help
           Create a tree of Blackfin MMRs via the debugfs tree.  If
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index 95cf2ba9de17..8465b3e6b862 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -121,13 +121,11 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_VGA16 is not set
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 # CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+CONFIG_SND_BF5XX_SOC_SSM2602=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 8be8e33fac52..5e7321b26040 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -96,7 +96,7 @@ CONFIG_SERIAL_BFIN_UART1=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
+CONFIG_I2C_BLACKFIN_TWI=y
 CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
 CONFIG_SPI=y
 CONFIG_SPI_BFIN=y
@@ -115,13 +115,11 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_VGA16 is not set
 # CONFIG_LOGO_LINUX_CLUT224 is not set
 # CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+CONFIG_SND_BF5XX_SOC_SSM2602=y
 CONFIG_HID_A4TECH=y
 CONFIG_HID_APPLE=y
 CONFIG_HID_BELKIN=y
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 0aafde6c8c2d..b90d3792ed52 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -99,8 +99,6 @@ CONFIG_SND_PCM_OSS=m
 CONFIG_SND_SOC=m
 CONFIG_SND_BF5XX_I2S=m
 CONFIG_SND_BF5XX_SOC_AD73311=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
 # CONFIG_USB_SUPPORT is not set
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_BFIN=y
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index c9077fb58135..005362537a7b 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -110,8 +110,6 @@ CONFIG_SND_PCM_OSS=m
 CONFIG_SND_SOC=m
 CONFIG_SND_BF5XX_I2S=m
 CONFIG_SND_BF5XX_SOC_AD73311=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
 # CONFIG_USB_SUPPORT is not set
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_BFIN=y
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 121cc04d877d..17bcbf60bcae 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -49,16 +49,6 @@ extern void dump_bfin_trace_buffer(void);
 #define dump_bfin_trace_buffer()
 #endif
 
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
 extern void *l1_data_A_sram_alloc(size_t);
 extern void *l1_data_B_sram_alloc(size_t);
 extern void *l1_inst_sram_alloc(size_t);
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
new file mode 100644
index 000000000000..accd47e2db40
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -0,0 +1,44 @@
+/*
+ * Blackfin Performance Monitor definitions
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or GPL-2 (or later).
+ */
+
+#ifndef __ASM_BFIN_PFMON_H__
+#define __ASM_BFIN_PFMON_H__
+
+/* PFCTL Masks */
+#define PFMON_MASK      0xff
+#define PFCEN_MASK      0x3
+#define PFCEN_DISABLE   0x0
+#define PFCEN_ENABLE_USER       0x1
+#define PFCEN_ENABLE_SUPV       0x2
+#define PFCEN_ENABLE_ALL        (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
+
+#define PFPWR_P 0
+#define PEMUSW0_P       2
+#define PFCEN0_P        3
+#define PFMON0_P        5
+#define PEMUSW1_P       13
+#define PFCEN1_P        14
+#define PFMON1_P        16
+#define PFCNT0_P        24
+#define PFCNT1_P        25
+
+#define PFPWR   (1 << PFPWR_P)
+#define PEMUSW(n, x)    ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
+#define PEMUSW0 PEMUSW(0, 1)
+#define PEMUSW1 PEMUSW(1, 1)
+#define PFCEN(n, x)     ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
+#define PFCEN0  PFCEN(0, PFCEN_MASK)
+#define PFCEN1  PFCEN(1, PFCEN_MASK)
+#define PFCNT(n, x)     ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
+#define PFCNT0  PFCNT(0, 1)
+#define PFCNT1  PFCNT(1, 1)
+#define PFMON(n, x)     ((x) << ((n) ? PFMON1_P : PFMON0_P))
+#define PFMON0  PFMON(0, PFMON_MASK)
+#define PFMON1  PFMON(1, PFMON_MASK)
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 7dbc664eab1e..7fd0ec7b5b0f 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -184,7 +184,7 @@ struct bfin_uart_regs {
 #undef __BFP
 
 #ifndef port_membase
-# define port_membase(p) (((struct bfin_serial_port *)(p))->port.membase)
+# define port_membase(p) 0
 #endif
 
 #define UART_GET_CHAR(p)      bfin_read16(port_membase(p) + OFFSET_RBR)
@@ -235,10 +235,10 @@ struct bfin_uart_regs {
 #define UART_SET_DLAB(p)      do { UART_PUT_LCR(p, UART_GET_LCR(p) | DLAB); SSYNC(); } while (0)
 
 #ifndef put_lsr_cache
-# define put_lsr_cache(p, v) (((struct bfin_serial_port *)(p))->lsr = (v))
+# define put_lsr_cache(p, v)
 #endif
 #ifndef get_lsr_cache
-# define get_lsr_cache(p)    (((struct bfin_serial_port *)(p))->lsr)
+# define get_lsr_cache(p) 0
 #endif
 
 /* The hardware clears the LSR bits upon read, so we need to cache
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index d27600c262c2..f8568a31d0ab 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -100,6 +100,10 @@ struct sport_register {
 };
 #undef __BFP
 
+struct bfin_snd_platform_data {
+        const unsigned short *pin_req;
+};
+
 #define bfin_read_sport_rx32(base) \
 ({ \
         struct sport_register *__mmrs = (void *)base; \
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 77135b62818e..9a5b2c572ebf 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -39,8 +39,13 @@ extern void blackfin_invalidate_entire_icache(void);
 
 static inline void flush_icache_range(unsigned start, unsigned end)
 {
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-        blackfin_dcache_flush_range(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
+        if (end <= physical_mem_end)
+                blackfin_dcache_flush_range(start, end);
+#endif
+#if defined(CONFIG_BFIN_L2_WRITEBACK)
+        if (start >= L2_START && end <= L2_START + L2_LENGTH)
+                blackfin_dcache_flush_range(start, end);
 #endif
 
         /* Make sure all write buffers in the data side of the core
@@ -52,9 +57,17 @@ static inline void flush_icache_range(unsigned start, unsigned end)
          * the pipeline.
          */
         SSYNC();
-#if defined(CONFIG_BFIN_ICACHE)
-        blackfin_icache_flush_range(start, end);
-        flush_icache_range_others(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
+        if (end <= physical_mem_end) {
+                blackfin_icache_flush_range(start, end);
+                flush_icache_range_others(start, end);
+        }
+#endif
+#if defined(CONFIG_BFIN_L2_ICACHEABLE)
+        if (start >= L2_START && end <= L2_START + L2_LENGTH) {
+                blackfin_icache_flush_range(start, end);
+                flush_icache_range_others(start, end);
+        }
 #endif
 }
 
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index 16883e582e3c..05043786da21 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -10,11 +10,8 @@
 
 #include <linux/percpu.h>
 
-struct task_struct;
-
 struct blackfin_cpudata {
         struct cpu cpu;
-        struct task_struct *idle;
         unsigned int imemctl;
         unsigned int dmemctl;
 };
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 7600fe0696af..823679011457 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -52,10 +52,10 @@
 
 #define bfin_read(addr) \
 ({ \
-    sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
-    sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
-    sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
-    ({ BUG(); 0; }); \
+        sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
+        sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
+        sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
+        ({ BUG(); 0; }); \
 })
 #define bfin_write(addr, val) \
 do { \
@@ -69,13 +69,13 @@ do { \
 
 #define bfin_write_or(addr, bits) \
 do { \
-        void *__addr = (void *)(addr); \
+        typeof(addr) __addr = (addr); \
         bfin_write(__addr, bfin_read(__addr) | (bits)); \
 } while (0)
 
 #define bfin_write_and(addr, bits) \
 do { \
-        void *__addr = (void *)(addr); \
+        typeof(addr) __addr = (addr); \
         bfin_write(__addr, bfin_read(__addr) & (bits)); \
 } while (0)
 
diff --git a/arch/blackfin/include/asm/gptimers.h b/arch/blackfin/include/asm/gptimers.h
index c722acdda0d3..38657dac1235 100644
--- a/arch/blackfin/include/asm/gptimers.h
+++ b/arch/blackfin/include/asm/gptimers.h
@@ -193,4 +193,22 @@ uint16_t get_enabled_gptimers(void);
 uint32_t get_gptimer_status(unsigned int group);
 void     set_gptimer_status(unsigned int group, uint32_t value);
 
+/*
+ * All Blackfin system MMRs are padded to 32bits even if the register
+ * itself is only 16bits.  So use a helper macro to streamline this.
+ */
+#define __BFP(m) u16 m; u16 __pad_##m
+
+/*
+ * bfin timer registers layout
+ */
+struct bfin_gptimer_regs {
+        __BFP(config);
+        u32 counter;
+        u32 period;
+        u32 width;
+};
+
+#undef __BFP
+
 #endif
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index 7fbe42307b9a..ee73f79aef10 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -10,6 +10,16 @@
 #include <linux/types.h>
 #include <linux/linkage.h>
 
+/* init functions only */
+extern int __init init_arch_irq(void);
+extern void init_exception_vectors(void);
+extern void __init program_IAR(void);
+#ifdef init_mach_irq
+extern void __init init_mach_irq(void);
+#else
+# define init_mach_irq()
+#endif
+
 /* BASE LEVEL interrupt handler routines */
 asmlinkage void evt_exception(void);
 asmlinkage void trap(void);
@@ -37,4 +47,19 @@ extern void return_from_exception(void);
 extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
 extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
 
+extern asmlinkage void lower_to_irq14(void);
+extern asmlinkage void bfin_return_from_exception(void);
+extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
+extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
+
+struct irq_data;
+extern void bfin_handle_irq(unsigned irq);
+extern void bfin_ack_noop(struct irq_data *);
+extern void bfin_internal_mask_irq(unsigned int irq);
+extern void bfin_internal_unmask_irq(unsigned int irq);
+
+struct irq_desc;
+extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
+extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
+
 #endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index 8651afe12990..aaf884591b07 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -103,7 +103,12 @@ static inline void arch_kgdb_breakpoint(void)
         asm("EXCPT 2;");
 }
 #define BREAK_INSTR_SIZE        2
-#define CACHE_FLUSH_IS_SAFE     1
+#ifdef CONFIG_SMP
+# define CACHE_FLUSH_IS_SAFE    0
+#else
+# define CACHE_FLUSH_IS_SAFE    1
+#endif
+#define GDB_ADJUSTS_BREAK_OFFSET
 #define HW_INST_WATCHPOINT_NUM  6
 #define HW_WATCHPOINT_NUM       8
 #define TYPE_INST_WATCHPOINT    0
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
new file mode 100644
index 000000000000..3d2b1716322f
--- /dev/null
+++ b/arch/blackfin/include/asm/perf_event.h
@@ -0,0 +1 @@
+#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 832d7c009a2c..7854d4367c15 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -102,14 +102,9 @@ struct pt_regs {
 /* user_mode returns true if only one bit is set in IPEND, other than the
    master interrupt enable.  */
 #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-#define instruction_pointer(regs) ((regs)->pc)
-#define user_stack_pointer(regs)  ((regs)->usp)
-#define profile_pc(regs) instruction_pointer(regs)
 extern void show_regs(struct pt_regs *);
 
 #define arch_has_single_step()  (1)
-extern void user_enable_single_step(struct task_struct *child);
-extern void user_disable_single_step(struct task_struct *child);
 /* common code demands this function */
 #define ptrace_disable(child) user_disable_single_step(child)
 
@@ -130,6 +125,8 @@ extern int is_user_addr_valid(struct task_struct *child,
             ((unsigned long)task_stack_page(task) + \
              (THREAD_SIZE - sizeof(struct pt_regs)))
 
+#include <asm-generic/ptrace.h>
+
 #endif  /*  __KERNEL__  */
 
 #endif                          /* __ASSEMBLY__ */
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index ff9a9f35d50b..0ccba60b9ccf 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -397,8 +397,10 @@
 #define __NR_open_by_handle_at  376
 #define __NR_clock_adjtime      377
 #define __NR_syncfs             378
+#define __NR_setns              379
+#define __NR_sendmmsg           380
 
-#define __NR_syscall            379
+#define __NR_syscall            381
 #define NR_syscalls             __NR_syscall
 
 /* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
new file mode 100644
index 000000000000..cab14e911dc2
--- /dev/null
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -0,0 +1,57 @@
+/*
+ * Common Blackfin IRQ definitions (i.e. the CEC)
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_COMMON_IRQ_H_
+#define _MACH_COMMON_IRQ_H_
+
+/*
+ * Core events interrupt source definitions
+ *
+ *  Event Source       Event Name
+ *  Emulation          EMU            0  (highest priority)
+ *  Reset              RST            1
+ *  NMI                NMI            2
+ *  Exception          EVX            3
+ *  Reserved           --             4
+ *  Hardware Error     IVHW           5
+ *  Core Timer         IVTMR          6
+ *  Peripherals        IVG7           7
+ *  Peripherals        IVG8           8
+ *  Peripherals        IVG9           9
+ *  Peripherals        IVG10         10
+ *  Peripherals        IVG11         11
+ *  Peripherals        IVG12         12
+ *  Peripherals        IVG13         13
+ *  Softirq            IVG14         14
+ *  System Call        IVG15         15  (lowest priority)
+ */
+
+/* The ABSTRACT IRQ definitions */
+#define IRQ_EMU                 0       /* Emulation */
+#define IRQ_RST                 1       /* reset */
+#define IRQ_NMI                 2       /* Non Maskable */
+#define IRQ_EVX                 3       /* Exception */
+#define IRQ_UNUSED              4       /* - unused interrupt */
+#define IRQ_HWERR               5       /* Hardware Error */
+#define IRQ_CORETMR             6       /* Core timer */
+
+#define BFIN_IRQ(x)             ((x) + 7)
+
+#define IVG7                    7
+#define IVG8                    8
+#define IVG9                    9
+#define IVG10                   10
+#define IVG11                   11
+#define IVG12                   12
+#define IVG13                   13
+#define IVG14                   14
+#define IVG15                   15
+
+#define NR_IRQS                 (NR_MACH_IRQS + NR_SPARE_IRQS)
+
+#endif
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index ca5ccc777772..d550b24d9e9b 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -33,7 +33,10 @@ obj-$(CONFIG_EARLY_PRINTK)           += shadow_console.o
 obj-$(CONFIG_STACKTRACE)             += stacktrace.o
 obj-$(CONFIG_DEBUG_VERBOSE)          += trace.o
 obj-$(CONFIG_BFIN_PSEUDODBG_INSNS)   += pseudodbg.o
+obj-$(CONFIG_PERF_EVENTS)            += perf_event.o
 
 # the kgdb test puts code into L2 and without linker
 # relaxation, we need to force long calls to/from it
 CFLAGS_kgdb_test.o := -mlong-calls -O0
+
+obj-$(CONFIG_DEBUG_MMRS)             += debug-mmrs.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 6ce8dce753c9..71dbaa4a48af 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -36,6 +36,11 @@ static int __init blackfin_dma_init(void)
 
         printk(KERN_INFO "Blackfin DMA Controller\n");
 
+
+#if ANOMALY_05000480
+        bfin_write_DMAC_TC_PER(0x0111);
+#endif
+
         for (i = 0; i < MAX_DMA_CHANNELS; i++) {
                 atomic_set(&dma_ch[i].chan_status, 0);
                 dma_ch[i].regs = dma_io_base_addr[i];
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 170cf90735ba..bcf8cf6fe412 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -10,10 +10,12 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <asm/blackfin.h>
 #include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <linux/irq.h>
+#include <asm/irq_handler.h>
 
 #if ANOMALY_05000311 || ANOMALY_05000323
 enum {
@@ -534,7 +536,7 @@ static const unsigned int sic_iwr_irqs[] = {
 #if defined(BF533_FAMILY)
         IRQ_PROG_INTB
 #elif defined(BF537_FAMILY)
-        IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
+        IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
 #elif defined(BF538_FAMILY)
         IRQ_PORTF_INTB
 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
@@ -1203,35 +1205,43 @@ void bfin_reset_boot_spi_cs(unsigned short pin)
 }
 
 #if defined(CONFIG_PROC_FS)
-static int gpio_proc_read(char *buf, char **start, off_t offset,
-                          int len, int *unused_i, void *unused_v)
+static int gpio_proc_show(struct seq_file *m, void *v)
 {
-        int c, irq, gpio, outlen = 0;
+        int c, irq, gpio;
 
         for (c = 0; c < MAX_RESOURCES; c++) {
                 irq = is_reserved(gpio_irq, c, 1);
                 gpio = is_reserved(gpio, c, 1);
                 if (!check_gpio(c) && (gpio || irq))
-                        len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
+                        seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
                                  get_label(c), (gpio && irq) ? " *" : "",
                                  get_gpio_dir(c) ? "OUTPUT" : "INPUT");
                 else if (is_reserved(peri, c, 1))
-                        len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
+                        seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
                 else
                         continue;
-                buf += len;
-                outlen += len;
         }
-        return outlen;
+
+        return 0;
 }
 
+static int gpio_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, gpio_proc_show, NULL);
+}
+
+static const struct file_operations gpio_proc_ops = {
+        .open           = gpio_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static __init int gpio_register_proc(void)
 {
         struct proc_dir_entry *proc_gpio;
 
-        proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
-        if (proc_gpio)
-                proc_gpio->read_proc = gpio_proc_read;
+        proc_gpio = proc_create("gpio", S_IRUGO, NULL, &gpio_proc_ops);
         return proc_gpio != NULL;
 }
 __initcall(gpio_register_proc);
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 2c264b51566a..c446591b961d 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -11,6 +11,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/io.h>
+#include <asm/irq_handler.h>
 
 /* Allow people to have their own Blackfin exception handler in a module */
 EXPORT_SYMBOL(bfin_return_from_exception);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
new file mode 100644
index 000000000000..fce4807ceef9
--- /dev/null
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -0,0 +1,1860 @@
+/*
+ * debugfs interface to core/system MMRs
+ *
+ * Copyright 2007-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/gptimers.h>
+#include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
+#include <asm/bfin_ppi.h>
+#include <asm/bfin_serial.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_twi.h>
+
+/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
+#ifdef BFIN_PORT_MUX
+#undef PORT_MUX
+#define PORT_MUX BFIN_PORT_MUX
+#endif
+
+#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
+#define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
+#define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
+#define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
+
+#define D_RO(name, bits) d_RO(#name, bits, name)
+#define D_WO(name, bits) d_WO(#name, bits, name)
+#define D32(name)        d(#name, 32, name)
+#define D16(name)        d(#name, 16, name)
+
+#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
+#define __REGS(peri, sname, rname) \
+        do { \
+                struct bfin_##peri##_regs r; \
+                void *addr = (void *)(base + REGS_OFF(peri, rname)); \
+                strcpy(_buf, sname); \
+                if (sizeof(r.rname) == 2) \
+                        debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
+                else \
+                        debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
+        } while (0)
+#define REGS_STR_PFX(buf, pfx, num) \
+        ({ \
+                buf + (num >= 0 ? \
+                        sprintf(buf, #pfx "%i_", num) : \
+                        sprintf(buf, #pfx "_")); \
+        })
+#define REGS_STR_PFX_C(buf, pfx, num) \
+        ({ \
+                buf + (num >= 0 ? \
+                        sprintf(buf, #pfx "%c_", 'A' + num) : \
+                        sprintf(buf, #pfx "_")); \
+        })
+
+/*
+ * Core registers (not memory mapped)
+ */
+extern u32 last_seqstat;
+
+static int debug_cclk_get(void *data, u64 *val)
+{
+        *val = get_cclk();
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
+
+static int debug_sclk_get(void *data, u64 *val)
+{
+        *val = get_sclk();
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
+
+#define DEFINE_SYSREG(sr, pre, post) \
+static int sysreg_##sr##_get(void *data, u64 *val) \
+{ \
+        unsigned long tmp; \
+        pre; \
+        __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
+        *val = tmp; \
+        return 0; \
+} \
+static int sysreg_##sr##_set(void *data, u64 val) \
+{ \
+        unsigned long tmp = val; \
+        __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
+        post; \
+        return 0; \
+} \
+DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
+
+DEFINE_SYSREG(cycles, , );
+DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
+DEFINE_SYSREG(emudat, , );
+DEFINE_SYSREG(seqstat, , );
+DEFINE_SYSREG(syscfg, , CSYNC());
+#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
+
+/*
+ * CAN
+ */
+#define CAN_OFF(mmr)  REGS_OFF(can, mmr)
+#define __CAN(uname, lname) __REGS(can, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
+{
+        static struct dentry *am, *mb;
+        int i, j;
+        char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
+
+        if (!am) {
+                am = debugfs_create_dir("am", parent);
+                mb = debugfs_create_dir("mb", parent);
+        }
+
+        __CAN(MC1, mc1);
+        __CAN(MD1, md1);
+        __CAN(TRS1, trs1);
+        __CAN(TRR1, trr1);
+        __CAN(TA1, ta1);
+        __CAN(AA1, aa1);
+        __CAN(RMP1, rmp1);
+        __CAN(RML1, rml1);
+        __CAN(MBTIF1, mbtif1);
+        __CAN(MBRIF1, mbrif1);
+        __CAN(MBIM1, mbim1);
+        __CAN(RFH1, rfh1);
+        __CAN(OPSS1, opss1);
+
+        __CAN(MC2, mc2);
+        __CAN(MD2, md2);
+        __CAN(TRS2, trs2);
+        __CAN(TRR2, trr2);
+        __CAN(TA2, ta2);
+        __CAN(AA2, aa2);
+        __CAN(RMP2, rmp2);
+        __CAN(RML2, rml2);
+        __CAN(MBTIF2, mbtif2);
+        __CAN(MBRIF2, mbrif2);
+        __CAN(MBIM2, mbim2);
+        __CAN(RFH2, rfh2);
+        __CAN(OPSS2, opss2);
+
+        __CAN(CLOCK, clock);
+        __CAN(TIMING, timing);
+        __CAN(DEBUG, debug);
+        __CAN(STATUS, status);
+        __CAN(CEC, cec);
+        __CAN(GIS, gis);
+        __CAN(GIM, gim);
+        __CAN(GIF, gif);
+        __CAN(CONTROL, control);
+        __CAN(INTR, intr);
+        __CAN(VERSION, version);
+        __CAN(MBTD, mbtd);
+        __CAN(EWR, ewr);
+        __CAN(ESR, esr);
+        /*__CAN(UCREG, ucreg); no longer exists */
+        __CAN(UCCNT, uccnt);
+        __CAN(UCRC, ucrc);
+        __CAN(UCCNF, uccnf);
+        __CAN(VERSION2, version2);
+
+        for (i = 0; i < 32; ++i) {
+                sprintf(_buf, "AM%02iL", i);
+                debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
+                        (u16 *)(base + CAN_OFF(msk[i].aml)));
+                sprintf(_buf, "AM%02iH", i);
+                debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
+                        (u16 *)(base + CAN_OFF(msk[i].amh)));
+
+                for (j = 0; j < 3; ++j) {
+                        sprintf(_buf, "MB%02i_DATA%i", i, j);
+                        debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+                                (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
+                }
+                sprintf(_buf, "MB%02i_LENGTH", i);
+                debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+                        (u16 *)(base + CAN_OFF(chl[i].dlc)));
+                sprintf(_buf, "MB%02i_TIMESTAMP", i);
+                debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+                        (u16 *)(base + CAN_OFF(chl[i].tsv)));
+                sprintf(_buf, "MB%02i_ID0", i);
+                debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+                        (u16 *)(base + CAN_OFF(chl[i].id0)));
+                sprintf(_buf, "MB%02i_ID1", i);
+                debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+                        (u16 *)(base + CAN_OFF(chl[i].id1)));
+        }
+}
+#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
+
+/*
+ * DMA
+ */
+#define __DMA(uname, lname) __REGS(dma, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
+{
+        char buf[32], *_buf;
+
+        if (mdma)
+                _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
+        else
+                _buf = buf + sprintf(buf, "%s%i_", pfx, num);
+
+        __DMA(NEXT_DESC_PTR, next_desc_ptr);
+        __DMA(START_ADDR, start_addr);
+        __DMA(CONFIG, config);
+        __DMA(X_COUNT, x_count);
+        __DMA(X_MODIFY, x_modify);
+        __DMA(Y_COUNT, y_count);
+        __DMA(Y_MODIFY, y_modify);
+        __DMA(CURR_DESC_PTR, curr_desc_ptr);
+        __DMA(CURR_ADDR, curr_addr);
+        __DMA(IRQ_STATUS, irq_status);
+        __DMA(PERIPHERAL_MAP, peripheral_map);
+        __DMA(CURR_X_COUNT, curr_x_count);
+        __DMA(CURR_Y_COUNT, curr_y_count);
+}
+#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
+#define DMA(num)  _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
+#define _MDMA(num, x) \
+        do { \
+                _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
+                _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
+        } while (0)
+#define MDMA(num) _MDMA(num, M)
+#define IMDMA(num) _MDMA(num, IM)
+
+/*
+ * EPPI
+ */
+#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
+        __EPPI(STATUS, status);
+        __EPPI(HCOUNT, hcount);
+        __EPPI(HDELAY, hdelay);
+        __EPPI(VCOUNT, vcount);
+        __EPPI(VDELAY, vdelay);
+        __EPPI(FRAME, frame);
+        __EPPI(LINE, line);
+        __EPPI(CLKDIV, clkdiv);
+        __EPPI(CONTROL, control);
+        __EPPI(FS1W_HBL, fs1w_hbl);
+        __EPPI(FS1P_AVPL, fs1p_avpl);
+        __EPPI(FS2W_LVB, fs2w_lvb);
+        __EPPI(FS2P_LAVF, fs2p_lavf);
+        __EPPI(CLIP, clip);
+}
+#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
+
+/*
+ * General Purpose Timers
+ */
+#define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
+        __GPTIMER(CONFIG, config);
+        __GPTIMER(COUNTER, counter);
+        __GPTIMER(PERIOD, period);
+        __GPTIMER(WIDTH, width);
+}
+#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
+
+/*
+ * Handshake MDMA
+ */
+#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
+        __HMDMA(CONTROL, control);
+        __HMDMA(ECINIT, ecinit);
+        __HMDMA(BCINIT, bcinit);
+        __HMDMA(ECURGENT, ecurgent);
+        __HMDMA(ECOVERFLOW, ecoverflow);
+        __HMDMA(ECOUNT, ecount);
+        __HMDMA(BCOUNT, bcount);
+}
+#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
+
+/*
+ * Port/GPIO
+ */
+#define bfin_gpio_regs gpio_port_t
+#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf;
+#ifdef __ADSPBF54x__
+        _buf = REGS_STR_PFX_C(buf, PORT, num);
+        __PORT(FER, port_fer);
+        __PORT(SET, data_set);
+        __PORT(CLEAR, data_clear);
+        __PORT(DIR_SET, dir_set);
+        __PORT(DIR_CLEAR, dir_clear);
+        __PORT(INEN, inen);
+        __PORT(MUX, port_mux);
+#else
+        _buf = buf + sprintf(buf, "PORT%cIO_", num);
+        __PORT(CLEAR, data_clear);
+        __PORT(SET, data_set);
+        __PORT(TOGGLE, toggle);
+        __PORT(MASKA, maska);
+        __PORT(MASKA_CLEAR, maska_clear);
+        __PORT(MASKA_SET, maska_set);
+        __PORT(MASKA_TOGGLE, maska_toggle);
+        __PORT(MASKB, maskb);
+        __PORT(MASKB_CLEAR, maskb_clear);
+        __PORT(MASKB_SET, maskb_set);
+        __PORT(MASKB_TOGGLE, maskb_toggle);
+        __PORT(DIR, dir);
+        __PORT(POLAR, polar);
+        __PORT(EDGE, edge);
+        __PORT(BOTH, both);
+        __PORT(INEN, inen);
+#endif
+        _buf[-1] = '\0';
+        d(buf, 16, base + REGS_OFF(gpio, data));
+}
+#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
+
+/*
+ * PPI
+ */
+#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
+        __PPI(CONTROL, control);
+        __PPI(STATUS, status);
+        __PPI(COUNT, count);
+        __PPI(DELAY, delay);
+        __PPI(FRAME, frame);
+}
+#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
+
+/*
+ * SPI
+ */
+#define __SPI(uname, lname) __REGS(spi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
+        __SPI(CTL, ctl);
+        __SPI(FLG, flg);
+        __SPI(STAT, stat);
+        __SPI(TDBR, tdbr);
+        __SPI(RDBR, rdbr);
+        __SPI(BAUD, baud);
+        __SPI(SHADOW, shadow);
+}
+#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
+
+/*
+ * SPORT
+ */
+static inline int sport_width(void *mmr)
+{
+        unsigned long lmmr = (unsigned long)mmr;
+        if ((lmmr & 0xff) == 0x10)
+                /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
+                lmmr -= 0xc;
+        else
+                /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
+                lmmr += 0xc;
+        /* extract SLEN field from control register 2 and add 1 */
+        return (bfin_read16(lmmr) & 0x1f) + 1;
+}
+static int sport_set(void *mmr, u64 val)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        if (sport_width(mmr) <= 16)
+                bfin_write16(mmr, val);
+        else
+                bfin_write32(mmr, val);
+        local_irq_restore(flags);
+        return 0;
+}
+static int sport_get(void *mmr, u64 *val)
+{
+        unsigned long flags;
+        local_irq_save(flags);
+        if (sport_width(mmr) <= 16)
+                *val = bfin_read16(mmr);
+        else
+                *val = bfin_read32(mmr);
+        local_irq_restore(flags);
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
+/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
+DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
+#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
+#define _D_SPORT(name, perms, fops) \
+        do { \
+                strcpy(_buf, #name); \
+                debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
+        } while (0)
+#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
+#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
+#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
+#define __SPORT(name, bits) \
+        do { \
+                strcpy(_buf, #name); \
+                debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
+        } while (0)
+static void __init __maybe_unused
+bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
+        __SPORT(CHNL, 16);
+        __SPORT(MCMC1, 16);
+        __SPORT(MCMC2, 16);
+        __SPORT(MRCS0, 32);
+        __SPORT(MRCS1, 32);
+        __SPORT(MRCS2, 32);
+        __SPORT(MRCS3, 32);
+        __SPORT(MTCS0, 32);
+        __SPORT(MTCS1, 32);
+        __SPORT(MTCS2, 32);
+        __SPORT(MTCS3, 32);
+        __SPORT(RCLKDIV, 16);
+        __SPORT(RCR1, 16);
+        __SPORT(RCR2, 16);
+        __SPORT(RFSDIV, 16);
+        __SPORT_RW(RX);
+        __SPORT(STAT, 16);
+        __SPORT(TCLKDIV, 16);
+        __SPORT(TCR1, 16);
+        __SPORT(TCR2, 16);
+        __SPORT(TFSDIV, 16);
+        __SPORT_WO(TX);
+}
+#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
+
+/*
+ * TWI
+ */
+#define __TWI(uname, lname) __REGS(twi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
+        __TWI(CLKDIV, clkdiv);
+        __TWI(CONTROL, control);
+        __TWI(SLAVE_CTL, slave_ctl);
+        __TWI(SLAVE_STAT, slave_stat);
+        __TWI(SLAVE_ADDR, slave_addr);
+        __TWI(MASTER_CTL, master_ctl);
+        __TWI(MASTER_STAT, master_stat);
+        __TWI(MASTER_ADDR, master_addr);
+        __TWI(INT_STAT, int_stat);
+        __TWI(INT_MASK, int_mask);
+        __TWI(FIFO_CTL, fifo_ctl);
+        __TWI(FIFO_STAT, fifo_stat);
+        __TWI(XMT_DATA8, xmt_data8);
+        __TWI(XMT_DATA16, xmt_data16);
+        __TWI(RCV_DATA8, rcv_data8);
+        __TWI(RCV_DATA16, rcv_data16);
+}
+#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
+
+/*
+ * UART
+ */
+#define __UART(uname, lname) __REGS(uart, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
+{
+        char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
+#ifdef BFIN_UART_BF54X_STYLE
+        __UART(DLL, dll);
+        __UART(DLH, dlh);
+        __UART(GCTL, gctl);
+        __UART(LCR, lcr);
+        __UART(MCR, mcr);
+        __UART(LSR, lsr);
+        __UART(MSR, msr);
+        __UART(SCR, scr);
+        __UART(IER_SET, ier_set);
+        __UART(IER_CLEAR, ier_clear);
+        __UART(THR, thr);
+        __UART(RBR, rbr);
+#else
+        __UART(DLL, dll);
+        __UART(THR, thr);
+        __UART(RBR, rbr);
+        __UART(DLH, dlh);
+        __UART(IER, ier);
+        __UART(IIR, iir);
+        __UART(LCR, lcr);
+        __UART(MCR, mcr);
+        __UART(LSR, lsr);
+        __UART(MSR, msr);
+        __UART(SCR, scr);
+        __UART(GCTL, gctl);
+#endif
+}
+#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
+
+/*
+ * The actual debugfs generation
+ */
+static struct dentry *debug_mmrs_dentry;
+
+static int __init bfin_debug_mmrs_init(void)
+{
+        struct dentry *top, *parent;
+
+        pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
+
+        top = debugfs_create_dir("blackfin", NULL);
+        if (top == NULL)
+                return -1;
+
+        parent = debugfs_create_dir("core_regs", top);
+        debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
+        debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
+        debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
+        D_SYSREG(cycles);
+        D_SYSREG(cycles2);
+        D_SYSREG(emudat);
+        D_SYSREG(seqstat);
+        D_SYSREG(syscfg);
+
+        /* Core MMRs */
+        parent = debugfs_create_dir("ctimer", top);
+        D32(TCNTL);
+        D32(TCOUNT);
+        D32(TPERIOD);
+        D32(TSCALE);
+
+        parent = debugfs_create_dir("cec", top);
+        D32(EVT0);
+        D32(EVT1);
+        D32(EVT2);
+        D32(EVT3);
+        D32(EVT4);
+        D32(EVT5);
+        D32(EVT6);
+        D32(EVT7);
+        D32(EVT8);
+        D32(EVT9);
+        D32(EVT10);
+        D32(EVT11);
+        D32(EVT12);
+        D32(EVT13);
+        D32(EVT14);
+        D32(EVT15);
+        D32(EVT_OVERRIDE);
+        D32(IMASK);
+        D32(IPEND);
+        D32(ILAT);
+        D32(IPRIO);
+
+        parent = debugfs_create_dir("debug", top);
+        D32(DBGSTAT);
+        D32(DSPID);
+
+        parent = debugfs_create_dir("mmu", top);
+        D32(SRAM_BASE_ADDRESS);
+        D32(DCPLB_ADDR0);
+        D32(DCPLB_ADDR10);
+        D32(DCPLB_ADDR11);
+        D32(DCPLB_ADDR12);
+        D32(DCPLB_ADDR13);
+        D32(DCPLB_ADDR14);
+        D32(DCPLB_ADDR15);
+        D32(DCPLB_ADDR1);
+        D32(DCPLB_ADDR2);
+        D32(DCPLB_ADDR3);
+        D32(DCPLB_ADDR4);
+        D32(DCPLB_ADDR5);
+        D32(DCPLB_ADDR6);
+        D32(DCPLB_ADDR7);
+        D32(DCPLB_ADDR8);
+        D32(DCPLB_ADDR9);
+        D32(DCPLB_DATA0);
+        D32(DCPLB_DATA10);
+        D32(DCPLB_DATA11);
+        D32(DCPLB_DATA12);
+        D32(DCPLB_DATA13);
+        D32(DCPLB_DATA14);
+        D32(DCPLB_DATA15);
+        D32(DCPLB_DATA1);
+        D32(DCPLB_DATA2);
+        D32(DCPLB_DATA3);
+        D32(DCPLB_DATA4);
+        D32(DCPLB_DATA5);
+        D32(DCPLB_DATA6);
+        D32(DCPLB_DATA7);
+        D32(DCPLB_DATA8);
+        D32(DCPLB_DATA9);
+        D32(DCPLB_FAULT_ADDR);
+        D32(DCPLB_STATUS);
+        D32(DMEM_CONTROL);
+        D32(DTEST_COMMAND);
+        D32(DTEST_DATA0);
+        D32(DTEST_DATA1);
+
+        D32(ICPLB_ADDR0);
+        D32(ICPLB_ADDR1);
+        D32(ICPLB_ADDR2);
+        D32(ICPLB_ADDR3);
+        D32(ICPLB_ADDR4);
+        D32(ICPLB_ADDR5);
+        D32(ICPLB_ADDR6);
+        D32(ICPLB_ADDR7);
+        D32(ICPLB_ADDR8);
+        D32(ICPLB_ADDR9);
+        D32(ICPLB_ADDR10);
+        D32(ICPLB_ADDR11);
+        D32(ICPLB_ADDR12);
+        D32(ICPLB_ADDR13);
+        D32(ICPLB_ADDR14);
+        D32(ICPLB_ADDR15);
+        D32(ICPLB_DATA0);
+        D32(ICPLB_DATA1);
+        D32(ICPLB_DATA2);
+        D32(ICPLB_DATA3);
+        D32(ICPLB_DATA4);
+        D32(ICPLB_DATA5);
+        D32(ICPLB_DATA6);
+        D32(ICPLB_DATA7);
+        D32(ICPLB_DATA8);
+        D32(ICPLB_DATA9);
+        D32(ICPLB_DATA10);
+        D32(ICPLB_DATA11);
+        D32(ICPLB_DATA12);
+        D32(ICPLB_DATA13);
+        D32(ICPLB_DATA14);
+        D32(ICPLB_DATA15);
+        D32(ICPLB_FAULT_ADDR);
+        D32(ICPLB_STATUS);
+        D32(IMEM_CONTROL);
+        if (!ANOMALY_05000481) {
+                D32(ITEST_COMMAND);
+                D32(ITEST_DATA0);
+                D32(ITEST_DATA1);
+        }
+
+        parent = debugfs_create_dir("perf", top);
+        D32(PFCNTR0);
+        D32(PFCNTR1);
+        D32(PFCTL);
+
+        parent = debugfs_create_dir("trace", top);
+        D32(TBUF);
+        D32(TBUFCTL);
+        D32(TBUFSTAT);
+
+        parent = debugfs_create_dir("watchpoint", top);
+        D32(WPIACTL);
+        D32(WPIA0);
+        D32(WPIA1);
+        D32(WPIA2);
+        D32(WPIA3);
+        D32(WPIA4);
+        D32(WPIA5);
+        D32(WPIACNT0);
+        D32(WPIACNT1);
+        D32(WPIACNT2);
+        D32(WPIACNT3);
+        D32(WPIACNT4);
+        D32(WPIACNT5);
+        D32(WPDACTL);
+        D32(WPDA0);
+        D32(WPDA1);
+        D32(WPDACNT0);
+        D32(WPDACNT1);
+        D32(WPSTAT);
+
+        /* System MMRs */
+#ifdef ATAPI_CONTROL
+        parent = debugfs_create_dir("atapi", top);
+        D16(ATAPI_CONTROL);
+        D16(ATAPI_DEV_ADDR);
+        D16(ATAPI_DEV_RXBUF);
+        D16(ATAPI_DEV_TXBUF);
+        D16(ATAPI_DMA_TFRCNT);
+        D16(ATAPI_INT_MASK);
+        D16(ATAPI_INT_STATUS);
+        D16(ATAPI_LINE_STATUS);
+        D16(ATAPI_MULTI_TIM_0);
+        D16(ATAPI_MULTI_TIM_1);
+        D16(ATAPI_MULTI_TIM_2);
+        D16(ATAPI_PIO_TFRCNT);
+        D16(ATAPI_PIO_TIM_0);
+        D16(ATAPI_PIO_TIM_1);
+        D16(ATAPI_REG_TIM_0);
+        D16(ATAPI_SM_STATE);
+        D16(ATAPI_STATUS);
+        D16(ATAPI_TERMINATE);
+        D16(ATAPI_UDMAOUT_TFRCNT);
+        D16(ATAPI_ULTRA_TIM_0);
+        D16(ATAPI_ULTRA_TIM_1);
+        D16(ATAPI_ULTRA_TIM_2);
+        D16(ATAPI_ULTRA_TIM_3);
+        D16(ATAPI_UMAIN_TFRCNT);
+        D16(ATAPI_XFER_LEN);
+#endif
+
+#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
+        parent = debugfs_create_dir("can", top);
+# ifdef CAN_MC1
+        bfin_debug_mmrs_can(parent, CAN_MC1, -1);
+# endif
+# ifdef CAN0_MC1
+        CAN(0);
+# endif
+# ifdef CAN1_MC1
+        CAN(1);
+# endif
+#endif
+
+#ifdef CNT_COMMAND
+        parent = debugfs_create_dir("counter", top);
+        D16(CNT_COMMAND);
+        D16(CNT_CONFIG);
+        D32(CNT_COUNTER);
+        D16(CNT_DEBOUNCE);
+        D16(CNT_IMASK);
+        D32(CNT_MAX);
+        D32(CNT_MIN);
+        D16(CNT_STATUS);
+#endif
+
+        parent = debugfs_create_dir("dmac", top);
+#ifdef DMA_TC_CNT
+        D16(DMAC_TC_CNT);
+        D16(DMAC_TC_PER);
+#endif
+#ifdef DMAC0_TC_CNT
+        D16(DMAC0_TC_CNT);
+        D16(DMAC0_TC_PER);
+#endif
+#ifdef DMAC1_TC_CNT
+        D16(DMAC1_TC_CNT);
+        D16(DMAC1_TC_PER);
+#endif
+#ifdef DMAC1_PERIMUX
+        D16(DMAC1_PERIMUX);
+#endif
+
+#ifdef __ADSPBF561__
+        /* XXX: should rewrite the MMR map */
+# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
+# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
+# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
+# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
+# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
+# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
+# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
+# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
+# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
+# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
+# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
+# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
+# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
+# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
+# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
+# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
+# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
+# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
+# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
+# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
+# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
+# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
+# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
+# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
+#endif
+        parent = debugfs_create_dir("dma", top);
+        DMA(0);
+        DMA(1);
+        DMA(1);
+        DMA(2);
+        DMA(3);
+        DMA(4);
+        DMA(5);
+        DMA(6);
+        DMA(7);
+#ifdef DMA8_NEXT_DESC_PTR
+        DMA(8);
+        DMA(9);
+        DMA(10);
+        DMA(11);
+#endif
+#ifdef DMA12_NEXT_DESC_PTR
+        DMA(12);
+        DMA(13);
+        DMA(14);
+        DMA(15);
+        DMA(16);
+        DMA(17);
+        DMA(18);
+        DMA(19);
+#endif
+#ifdef DMA20_NEXT_DESC_PTR
+        DMA(20);
+        DMA(21);
+        DMA(22);
+        DMA(23);
+#endif
+
+        parent = debugfs_create_dir("ebiu_amc", top);
+        D32(EBIU_AMBCTL0);
+        D32(EBIU_AMBCTL1);
+        D16(EBIU_AMGCTL);
+#ifdef EBIU_MBSCTL
+        D16(EBIU_MBSCTL);
+        D32(EBIU_ARBSTAT);
+        D32(EBIU_MODE);
+        D16(EBIU_FCTL);
+#endif
+
+#ifdef EBIU_SDGCTL
+        parent = debugfs_create_dir("ebiu_sdram", top);
+# ifdef __ADSPBF561__
+        D32(EBIU_SDBCTL);
+# else
+        D16(EBIU_SDBCTL);
+# endif
+        D32(EBIU_SDGCTL);
+        D16(EBIU_SDRRC);
+        D16(EBIU_SDSTAT);
+#endif
+
+#ifdef EBIU_DDRACCT
+        parent = debugfs_create_dir("ebiu_ddr", top);
+        D32(EBIU_DDRACCT);
+        D32(EBIU_DDRARCT);
+        D32(EBIU_DDRBRC0);
+        D32(EBIU_DDRBRC1);
+        D32(EBIU_DDRBRC2);
+        D32(EBIU_DDRBRC3);
+        D32(EBIU_DDRBRC4);
+        D32(EBIU_DDRBRC5);
+        D32(EBIU_DDRBRC6);
+        D32(EBIU_DDRBRC7);
+        D32(EBIU_DDRBWC0);
+        D32(EBIU_DDRBWC1);
+        D32(EBIU_DDRBWC2);
+        D32(EBIU_DDRBWC3);
+        D32(EBIU_DDRBWC4);
+        D32(EBIU_DDRBWC5);
+        D32(EBIU_DDRBWC6);
+        D32(EBIU_DDRBWC7);
+        D32(EBIU_DDRCTL0);
+        D32(EBIU_DDRCTL1);
+        D32(EBIU_DDRCTL2);
+        D32(EBIU_DDRCTL3);
+        D32(EBIU_DDRGC0);
+        D32(EBIU_DDRGC1);
+        D32(EBIU_DDRGC2);
+        D32(EBIU_DDRGC3);
+        D32(EBIU_DDRMCCL);
+        D32(EBIU_DDRMCEN);
+        D32(EBIU_DDRQUE);
+        D32(EBIU_DDRTACT);
+        D32(EBIU_ERRADD);
+        D16(EBIU_ERRMST);
+        D16(EBIU_RSTCTL);
+#endif
+
+#ifdef EMAC_ADDRHI
+        parent = debugfs_create_dir("emac", top);
+        D32(EMAC_ADDRHI);
+        D32(EMAC_ADDRLO);
+        D32(EMAC_FLC);
+        D32(EMAC_HASHHI);
+        D32(EMAC_HASHLO);
+        D32(EMAC_MMC_CTL);
+        D32(EMAC_MMC_RIRQE);
+        D32(EMAC_MMC_RIRQS);
+        D32(EMAC_MMC_TIRQE);
+        D32(EMAC_MMC_TIRQS);
+        D32(EMAC_OPMODE);
+        D32(EMAC_RXC_ALIGN);
+        D32(EMAC_RXC_ALLFRM);
+        D32(EMAC_RXC_ALLOCT);
+        D32(EMAC_RXC_BROAD);
+        D32(EMAC_RXC_DMAOVF);
+        D32(EMAC_RXC_EQ64);
+        D32(EMAC_RXC_FCS);
+        D32(EMAC_RXC_GE1024);
+        D32(EMAC_RXC_LNERRI);
+        D32(EMAC_RXC_LNERRO);
+        D32(EMAC_RXC_LONG);
+        D32(EMAC_RXC_LT1024);
+        D32(EMAC_RXC_LT128);
+        D32(EMAC_RXC_LT256);
+        D32(EMAC_RXC_LT512);
+        D32(EMAC_RXC_MACCTL);
+        D32(EMAC_RXC_MULTI);
+        D32(EMAC_RXC_OCTET);
+        D32(EMAC_RXC_OK);
+        D32(EMAC_RXC_OPCODE);
+        D32(EMAC_RXC_PAUSE);
+        D32(EMAC_RXC_SHORT);
+        D32(EMAC_RXC_TYPED);
+        D32(EMAC_RXC_UNICST);
+        D32(EMAC_RX_IRQE);
+        D32(EMAC_RX_STAT);
+        D32(EMAC_RX_STKY);
+        D32(EMAC_STAADD);
+        D32(EMAC_STADAT);
+        D32(EMAC_SYSCTL);
+        D32(EMAC_SYSTAT);
+        D32(EMAC_TXC_1COL);
+        D32(EMAC_TXC_ABORT);
+        D32(EMAC_TXC_ALLFRM);
+        D32(EMAC_TXC_ALLOCT);
+        D32(EMAC_TXC_BROAD);
+        D32(EMAC_TXC_CRSERR);
+        D32(EMAC_TXC_DEFER);
+        D32(EMAC_TXC_DMAUND);
+        D32(EMAC_TXC_EQ64);
+        D32(EMAC_TXC_GE1024);
+        D32(EMAC_TXC_GT1COL);
+        D32(EMAC_TXC_LATECL);
+        D32(EMAC_TXC_LT1024);
+        D32(EMAC_TXC_LT128);
+        D32(EMAC_TXC_LT256);
+        D32(EMAC_TXC_LT512);
+        D32(EMAC_TXC_MACCTL);
+        D32(EMAC_TXC_MULTI);
+        D32(EMAC_TXC_OCTET);
+        D32(EMAC_TXC_OK);
+        D32(EMAC_TXC_UNICST);
+        D32(EMAC_TXC_XS_COL);
+        D32(EMAC_TXC_XS_DFR);
+        D32(EMAC_TX_IRQE);
+        D32(EMAC_TX_STAT);
+        D32(EMAC_TX_STKY);
+        D32(EMAC_VLAN1);
+        D32(EMAC_VLAN2);
+        D32(EMAC_WKUP_CTL);
+        D32(EMAC_WKUP_FFCMD);
+        D32(EMAC_WKUP_FFCRC0);
+        D32(EMAC_WKUP_FFCRC1);
+        D32(EMAC_WKUP_FFMSK0);
+        D32(EMAC_WKUP_FFMSK1);
+        D32(EMAC_WKUP_FFMSK2);
+        D32(EMAC_WKUP_FFMSK3);
+        D32(EMAC_WKUP_FFOFF);
+# ifdef EMAC_PTP_ACCR
+        D32(EMAC_PTP_ACCR);
+        D32(EMAC_PTP_ADDEND);
+        D32(EMAC_PTP_ALARMHI);
+        D32(EMAC_PTP_ALARMLO);
+        D16(EMAC_PTP_CTL);
+        D32(EMAC_PTP_FOFF);
+        D32(EMAC_PTP_FV1);
+        D32(EMAC_PTP_FV2);
+        D32(EMAC_PTP_FV3);
+        D16(EMAC_PTP_ID_OFF);
+        D32(EMAC_PTP_ID_SNAP);
+        D16(EMAC_PTP_IE);
+        D16(EMAC_PTP_ISTAT);
+        D32(EMAC_PTP_OFFSET);
+        D32(EMAC_PTP_PPS_PERIOD);
+        D32(EMAC_PTP_PPS_STARTHI);
+        D32(EMAC_PTP_PPS_STARTLO);
+        D32(EMAC_PTP_RXSNAPHI);
+        D32(EMAC_PTP_RXSNAPLO);
+        D32(EMAC_PTP_TIMEHI);
+        D32(EMAC_PTP_TIMELO);
+        D32(EMAC_PTP_TXSNAPHI);
+        D32(EMAC_PTP_TXSNAPLO);
+# endif
+#endif
+
+#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
+        parent = debugfs_create_dir("eppi", top);
+# ifdef EPPI0_STATUS
+        EPPI(0);
+# endif
+# ifdef EPPI1_STATUS
+        EPPI(1);
+# endif
+# ifdef EPPI2_STATUS
+        EPPI(2);
+# endif
+#endif
+
+        parent = debugfs_create_dir("gptimer", top);
+#ifdef TIMER_DISABLE
+        D16(TIMER_DISABLE);
+        D16(TIMER_ENABLE);
+        D32(TIMER_STATUS);
+#endif
+#ifdef TIMER_DISABLE0
+        D16(TIMER_DISABLE0);
+        D16(TIMER_ENABLE0);
+        D32(TIMER_STATUS0);
+#endif
+#ifdef TIMER_DISABLE1
+        D16(TIMER_DISABLE1);
+        D16(TIMER_ENABLE1);
+        D32(TIMER_STATUS1);
+#endif
+        /* XXX: Should convert BF561 MMR names */
+#ifdef TMRS4_DISABLE
+        D16(TMRS4_DISABLE);
+        D16(TMRS4_ENABLE);
+        D32(TMRS4_STATUS);
+        D16(TMRS8_DISABLE);
+        D16(TMRS8_ENABLE);
+        D32(TMRS8_STATUS);
+#endif
+        GPTIMER(0);
+        GPTIMER(1);
+        GPTIMER(2);
+#ifdef TIMER3_CONFIG
+        GPTIMER(3);
+        GPTIMER(4);
+        GPTIMER(5);
+        GPTIMER(6);
+        GPTIMER(7);
+#endif
+#ifdef TIMER8_CONFIG
+        GPTIMER(8);
+        GPTIMER(9);
+        GPTIMER(10);
+#endif
+#ifdef TIMER11_CONFIG
+        GPTIMER(11);
+#endif
+
+#ifdef HMDMA0_CONTROL
+        parent = debugfs_create_dir("hmdma", top);
+        HMDMA(0);
+        HMDMA(1);
+#endif
+
+#ifdef HOST_CONTROL
+        parent = debugfs_create_dir("hostdp", top);
+        D16(HOST_CONTROL);
+        D16(HOST_STATUS);
+        D16(HOST_TIMEOUT);
+#endif
+
+#ifdef IMDMA_S0_CONFIG
+        parent = debugfs_create_dir("imdma", top);
+        IMDMA(0);
+        IMDMA(1);
+#endif
+
+#ifdef KPAD_CTL
+        parent = debugfs_create_dir("keypad", top);
+        D16(KPAD_CTL);
+        D16(KPAD_PRESCALE);
+        D16(KPAD_MSEL);
+        D16(KPAD_ROWCOL);
+        D16(KPAD_STAT);
+        D16(KPAD_SOFTEVAL);
+#endif
+
+        parent = debugfs_create_dir("mdma", top);
+        MDMA(0);
+        MDMA(1);
+#ifdef MDMA_D2_CONFIG
+        MDMA(2);
+        MDMA(3);
+#endif
+
+#ifdef MXVR_CONFIG
+        parent = debugfs_create_dir("mxvr", top);
+        D16(MXVR_CONFIG);
+# ifdef MXVR_PLL_CTL_0
+        D32(MXVR_PLL_CTL_0);
+# endif
+        D32(MXVR_STATE_0);
+        D32(MXVR_STATE_1);
+        D32(MXVR_INT_STAT_0);
+        D32(MXVR_INT_STAT_1);
+        D32(MXVR_INT_EN_0);
+        D32(MXVR_INT_EN_1);
+        D16(MXVR_POSITION);
+        D16(MXVR_MAX_POSITION);
+        D16(MXVR_DELAY);
+        D16(MXVR_MAX_DELAY);
+        D32(MXVR_LADDR);
+        D16(MXVR_GADDR);
+        D32(MXVR_AADDR);
+        D32(MXVR_ALLOC_0);
+        D32(MXVR_ALLOC_1);
+        D32(MXVR_ALLOC_2);
+        D32(MXVR_ALLOC_3);
+        D32(MXVR_ALLOC_4);
+        D32(MXVR_ALLOC_5);
+        D32(MXVR_ALLOC_6);
+        D32(MXVR_ALLOC_7);
+        D32(MXVR_ALLOC_8);
+        D32(MXVR_ALLOC_9);
+        D32(MXVR_ALLOC_10);
+        D32(MXVR_ALLOC_11);
+        D32(MXVR_ALLOC_12);
+        D32(MXVR_ALLOC_13);
+        D32(MXVR_ALLOC_14);
+        D32(MXVR_SYNC_LCHAN_0);
+        D32(MXVR_SYNC_LCHAN_1);
+        D32(MXVR_SYNC_LCHAN_2);
+        D32(MXVR_SYNC_LCHAN_3);
+        D32(MXVR_SYNC_LCHAN_4);
+        D32(MXVR_SYNC_LCHAN_5);
+        D32(MXVR_SYNC_LCHAN_6);
+        D32(MXVR_SYNC_LCHAN_7);
+        D32(MXVR_DMA0_CONFIG);
+        D32(MXVR_DMA0_START_ADDR);
+        D16(MXVR_DMA0_COUNT);
+        D32(MXVR_DMA0_CURR_ADDR);
+        D16(MXVR_DMA0_CURR_COUNT);
+        D32(MXVR_DMA1_CONFIG);
+        D32(MXVR_DMA1_START_ADDR);
+        D16(MXVR_DMA1_COUNT);
+        D32(MXVR_DMA1_CURR_ADDR);
+        D16(MXVR_DMA1_CURR_COUNT);
+        D32(MXVR_DMA2_CONFIG);
+        D32(MXVR_DMA2_START_ADDR);
+        D16(MXVR_DMA2_COUNT);
+        D32(MXVR_DMA2_CURR_ADDR);
+        D16(MXVR_DMA2_CURR_COUNT);
+        D32(MXVR_DMA3_CONFIG);
+        D32(MXVR_DMA3_START_ADDR);
+        D16(MXVR_DMA3_COUNT);
+        D32(MXVR_DMA3_CURR_ADDR);
+        D16(MXVR_DMA3_CURR_COUNT);
+        D32(MXVR_DMA4_CONFIG);
+        D32(MXVR_DMA4_START_ADDR);
+        D16(MXVR_DMA4_COUNT);
+        D32(MXVR_DMA4_CURR_ADDR);
+        D16(MXVR_DMA4_CURR_COUNT);
+        D32(MXVR_DMA5_CONFIG);
+        D32(MXVR_DMA5_START_ADDR);
+        D16(MXVR_DMA5_COUNT);
+        D32(MXVR_DMA5_CURR_ADDR);
+        D16(MXVR_DMA5_CURR_COUNT);
+        D32(MXVR_DMA6_CONFIG);
+        D32(MXVR_DMA6_START_ADDR);
+        D16(MXVR_DMA6_COUNT);
+        D32(MXVR_DMA6_CURR_ADDR);
+        D16(MXVR_DMA6_CURR_COUNT);
+        D32(MXVR_DMA7_CONFIG);
+        D32(MXVR_DMA7_START_ADDR);
+        D16(MXVR_DMA7_COUNT);
+        D32(MXVR_DMA7_CURR_ADDR);
+        D16(MXVR_DMA7_CURR_COUNT);
+        D16(MXVR_AP_CTL);
+        D32(MXVR_APRB_START_ADDR);
+        D32(MXVR_APRB_CURR_ADDR);
+        D32(MXVR_APTB_START_ADDR);
+        D32(MXVR_APTB_CURR_ADDR);
+        D32(MXVR_CM_CTL);
+        D32(MXVR_CMRB_START_ADDR);
+        D32(MXVR_CMRB_CURR_ADDR);
+        D32(MXVR_CMTB_START_ADDR);
+        D32(MXVR_CMTB_CURR_ADDR);
+        D32(MXVR_RRDB_START_ADDR);
+        D32(MXVR_RRDB_CURR_ADDR);
+        D32(MXVR_PAT_DATA_0);
+        D32(MXVR_PAT_EN_0);
+        D32(MXVR_PAT_DATA_1);
+        D32(MXVR_PAT_EN_1);
+        D16(MXVR_FRAME_CNT_0);
+        D16(MXVR_FRAME_CNT_1);
+        D32(MXVR_ROUTING_0);
+        D32(MXVR_ROUTING_1);
+        D32(MXVR_ROUTING_2);
+        D32(MXVR_ROUTING_3);
+        D32(MXVR_ROUTING_4);
+        D32(MXVR_ROUTING_5);
+        D32(MXVR_ROUTING_6);
+        D32(MXVR_ROUTING_7);
+        D32(MXVR_ROUTING_8);
+        D32(MXVR_ROUTING_9);
+        D32(MXVR_ROUTING_10);
+        D32(MXVR_ROUTING_11);
+        D32(MXVR_ROUTING_12);
+        D32(MXVR_ROUTING_13);
+        D32(MXVR_ROUTING_14);
+# ifdef MXVR_PLL_CTL_1
+        D32(MXVR_PLL_CTL_1);
+# endif
+        D16(MXVR_BLOCK_CNT);
+# ifdef MXVR_CLK_CTL
+        D32(MXVR_CLK_CTL);
+# endif
+# ifdef MXVR_CDRPLL_CTL
+        D32(MXVR_CDRPLL_CTL);
+# endif
+# ifdef MXVR_FMPLL_CTL
+        D32(MXVR_FMPLL_CTL);
+# endif
+# ifdef MXVR_PIN_CTL
+        D16(MXVR_PIN_CTL);
+# endif
+# ifdef MXVR_SCLK_CNT
+        D16(MXVR_SCLK_CNT);
+# endif
+#endif
+
+#ifdef NFC_ADDR
+        parent = debugfs_create_dir("nfc", top);
+        D_WO(NFC_ADDR, 16);
+        D_WO(NFC_CMD, 16);
+        D_RO(NFC_COUNT, 16);
+        D16(NFC_CTL);
+        D_WO(NFC_DATA_RD, 16);
+        D_WO(NFC_DATA_WR, 16);
+        D_RO(NFC_ECC0, 16);
+        D_RO(NFC_ECC1, 16);
+        D_RO(NFC_ECC2, 16);
+        D_RO(NFC_ECC3, 16);
+        D16(NFC_IRQMASK);
+        D16(NFC_IRQSTAT);
+        D_WO(NFC_PGCTL, 16);
+        D_RO(NFC_READ, 16);
+        D16(NFC_RST);
+        D_RO(NFC_STAT, 16);
+#endif
+
+#ifdef OTP_CONTROL
+        parent = debugfs_create_dir("otp", top);
+        D16(OTP_CONTROL);
+        D16(OTP_BEN);
+        D16(OTP_STATUS);
+        D32(OTP_TIMING);
+        D32(OTP_DATA0);
+        D32(OTP_DATA1);
+        D32(OTP_DATA2);
+        D32(OTP_DATA3);
+#endif
+
+#ifdef PIXC_CTL
+        parent = debugfs_create_dir("pixc", top);
+        D16(PIXC_CTL);
+        D16(PIXC_PPL);
+        D16(PIXC_LPF);
+        D16(PIXC_AHSTART);
+        D16(PIXC_AHEND);
+        D16(PIXC_AVSTART);
+        D16(PIXC_AVEND);
+        D16(PIXC_ATRANSP);
+        D16(PIXC_BHSTART);
+        D16(PIXC_BHEND);
+        D16(PIXC_BVSTART);
+        D16(PIXC_BVEND);
+        D16(PIXC_BTRANSP);
+        D16(PIXC_INTRSTAT);
+        D32(PIXC_RYCON);
+        D32(PIXC_GUCON);
+        D32(PIXC_BVCON);
+        D32(PIXC_CCBIAS);
+        D32(PIXC_TC);
+#endif
+
+        parent = debugfs_create_dir("pll", top);
+        D16(PLL_CTL);
+        D16(PLL_DIV);
+        D16(PLL_LOCKCNT);
+        D16(PLL_STAT);
+        D16(VR_CTL);
+        D32(CHIPID);    /* it's part of this hardware block */
+
+#if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
+        parent = debugfs_create_dir("ppi", top);
+# ifdef PPI_CONTROL
+        bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
+# endif
+# ifdef PPI0_CONTROL
+        PPI(0);
+# endif
+# ifdef PPI1_CONTROL
+        PPI(1);
+# endif
+#endif
+
+#ifdef PWM_CTRL
+        parent = debugfs_create_dir("pwm", top);
+        D16(PWM_CTRL);
+        D16(PWM_STAT);
+        D16(PWM_TM);
+        D16(PWM_DT);
+        D16(PWM_GATE);
+        D16(PWM_CHA);
+        D16(PWM_CHB);
+        D16(PWM_CHC);
+        D16(PWM_SEG);
+        D16(PWM_SYNCWT);
+        D16(PWM_CHAL);
+        D16(PWM_CHBL);
+        D16(PWM_CHCL);
+        D16(PWM_LSI);
+        D16(PWM_STAT2);
+#endif
+
+#ifdef RSI_CONFIG
+        parent = debugfs_create_dir("rsi", top);
+        D32(RSI_ARGUMENT);
+        D16(RSI_CEATA_CONTROL);
+        D16(RSI_CLK_CONTROL);
+        D16(RSI_COMMAND);
+        D16(RSI_CONFIG);
+        D16(RSI_DATA_CNT);
+        D16(RSI_DATA_CONTROL);
+        D16(RSI_DATA_LGTH);
+        D32(RSI_DATA_TIMER);
+        D16(RSI_EMASK);
+        D16(RSI_ESTAT);
+        D32(RSI_FIFO);
+        D16(RSI_FIFO_CNT);
+        D32(RSI_MASK0);
+        D32(RSI_MASK1);
+        D16(RSI_PID0);
+        D16(RSI_PID1);
+        D16(RSI_PID2);
+        D16(RSI_PID3);
+        D16(RSI_PID4);
+        D16(RSI_PID5);
+        D16(RSI_PID6);
+        D16(RSI_PID7);
+        D16(RSI_PWR_CONTROL);
+        D16(RSI_RD_WAIT_EN);
+        D32(RSI_RESPONSE0);
+        D32(RSI_RESPONSE1);
+        D32(RSI_RESPONSE2);
+        D32(RSI_RESPONSE3);
+        D16(RSI_RESP_CMD);
+        D32(RSI_STATUS);
+        D_WO(RSI_STATUSCL, 16);
+#endif
+
+#ifdef RTC_ALARM
+        parent = debugfs_create_dir("rtc", top);
+        D32(RTC_ALARM);
+        D16(RTC_ICTL);
+        D16(RTC_ISTAT);
+        D16(RTC_PREN);
+        D32(RTC_STAT);
+        D16(RTC_SWCNT);
+#endif
+
+#ifdef SDH_CFG
+        parent = debugfs_create_dir("sdh", top);
+        D32(SDH_ARGUMENT);
+        D16(SDH_CFG);
+        D16(SDH_CLK_CTL);
+        D16(SDH_COMMAND);
+        D_RO(SDH_DATA_CNT, 16);
+        D16(SDH_DATA_CTL);
+        D16(SDH_DATA_LGTH);
+        D32(SDH_DATA_TIMER);
+        D16(SDH_E_MASK);
+        D16(SDH_E_STATUS);
+        D32(SDH_FIFO);
+        D_RO(SDH_FIFO_CNT, 16);
+        D32(SDH_MASK0);
+        D32(SDH_MASK1);
+        D_RO(SDH_PID0, 16);
+        D_RO(SDH_PID1, 16);
+        D_RO(SDH_PID2, 16);
+        D_RO(SDH_PID3, 16);
+        D_RO(SDH_PID4, 16);
+        D_RO(SDH_PID5, 16);
+        D_RO(SDH_PID6, 16);
+        D_RO(SDH_PID7, 16);
+        D16(SDH_PWR_CTL);
+        D16(SDH_RD_WAIT_EN);
+        D_RO(SDH_RESPONSE0, 32);
+        D_RO(SDH_RESPONSE1, 32);
+        D_RO(SDH_RESPONSE2, 32);
+        D_RO(SDH_RESPONSE3, 32);
+        D_RO(SDH_RESP_CMD, 16);
+        D_RO(SDH_STATUS, 32);
+        D_WO(SDH_STATUS_CLR, 16);
+#endif
+
+#ifdef SECURE_CONTROL
+        parent = debugfs_create_dir("security", top);
+        D16(SECURE_CONTROL);
+        D16(SECURE_STATUS);
+        D32(SECURE_SYSSWT);
+#endif
+
+        parent = debugfs_create_dir("sic", top);
+        D16(SWRST);
+        D16(SYSCR);
+        D16(SIC_RVECT);
+        D32(SIC_IAR0);
+        D32(SIC_IAR1);
+        D32(SIC_IAR2);
+#ifdef SIC_IAR3
+        D32(SIC_IAR3);
+#endif
+#ifdef SIC_IAR4
+        D32(SIC_IAR4);
+        D32(SIC_IAR5);
+        D32(SIC_IAR6);
+#endif
+#ifdef SIC_IAR7
+        D32(SIC_IAR7);
+#endif
+#ifdef SIC_IAR8
+        D32(SIC_IAR8);
+        D32(SIC_IAR9);
+        D32(SIC_IAR10);
+        D32(SIC_IAR11);
+#endif
+#ifdef SIC_IMASK
+        D32(SIC_IMASK);
+        D32(SIC_ISR);
+        D32(SIC_IWR);
+#endif
+#ifdef SIC_IMASK0
+        D32(SIC_IMASK0);
+        D32(SIC_IMASK1);
+        D32(SIC_ISR0);
+        D32(SIC_ISR1);
+        D32(SIC_IWR0);
+        D32(SIC_IWR1);
+#endif
+#ifdef SIC_IMASK2
+        D32(SIC_IMASK2);
+        D32(SIC_ISR2);
+        D32(SIC_IWR2);
+#endif
+#ifdef SICB_RVECT
+        D16(SICB_SWRST);
+        D16(SICB_SYSCR);
+        D16(SICB_RVECT);
+        D32(SICB_IAR0);
+        D32(SICB_IAR1);
+        D32(SICB_IAR2);
+        D32(SICB_IAR3);
+        D32(SICB_IAR4);
+        D32(SICB_IAR5);
+        D32(SICB_IAR6);
+        D32(SICB_IAR7);
+        D32(SICB_IMASK0);
+        D32(SICB_IMASK1);
+        D32(SICB_ISR0);
+        D32(SICB_ISR1);
+        D32(SICB_IWR0);
+        D32(SICB_IWR1);
+#endif
+
+        parent = debugfs_create_dir("spi", top);
+#ifdef SPI0_REGBASE
+        SPI(0);
+#endif
+#ifdef SPI1_REGBASE
+        SPI(1);
+#endif
+#ifdef SPI2_REGBASE
+        SPI(2);
+#endif
+
+        parent = debugfs_create_dir("sport", top);
+#ifdef SPORT0_STAT
+        SPORT(0);
+#endif
+#ifdef SPORT1_STAT
+        SPORT(1);
+#endif
+#ifdef SPORT2_STAT
+        SPORT(2);
+#endif
+#ifdef SPORT3_STAT
+        SPORT(3);
+#endif
+
+#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
+        parent = debugfs_create_dir("twi", top);
+# ifdef TWI_CLKDIV
+        bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
+# endif
+# ifdef TWI0_CLKDIV
+        TWI(0);
+# endif
+# ifdef TWI1_CLKDIV
+        TWI(1);
+# endif
+#endif
+
+        parent = debugfs_create_dir("uart", top);
+#ifdef BFIN_UART_DLL
+        bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
+#endif
+#ifdef UART0_DLL
+        UART(0);
+#endif
+#ifdef UART1_DLL
+        UART(1);
+#endif
+#ifdef UART2_DLL
+        UART(2);
+#endif
+#ifdef UART3_DLL
+        UART(3);
+#endif
+
+#ifdef USB_FADDR
+        parent = debugfs_create_dir("usb", top);
+        D16(USB_FADDR);
+        D16(USB_POWER);
+        D16(USB_INTRTX);
+        D16(USB_INTRRX);
+        D16(USB_INTRTXE);
+        D16(USB_INTRRXE);
+        D16(USB_INTRUSB);
+        D16(USB_INTRUSBE);
+        D16(USB_FRAME);
+        D16(USB_INDEX);
+        D16(USB_TESTMODE);
+        D16(USB_GLOBINTR);
+        D16(USB_GLOBAL_CTL);
+        D16(USB_TX_MAX_PACKET);
+        D16(USB_CSR0);
+        D16(USB_TXCSR);
+        D16(USB_RX_MAX_PACKET);
+        D16(USB_RXCSR);
+        D16(USB_COUNT0);
+        D16(USB_RXCOUNT);
+        D16(USB_TXTYPE);
+        D16(USB_NAKLIMIT0);
+        D16(USB_TXINTERVAL);
+        D16(USB_RXTYPE);
+        D16(USB_RXINTERVAL);
+        D16(USB_TXCOUNT);
+        D16(USB_EP0_FIFO);
+        D16(USB_EP1_FIFO);
+        D16(USB_EP2_FIFO);
+        D16(USB_EP3_FIFO);
+        D16(USB_EP4_FIFO);
+        D16(USB_EP5_FIFO);
+        D16(USB_EP6_FIFO);
+        D16(USB_EP7_FIFO);
+        D16(USB_OTG_DEV_CTL);
+        D16(USB_OTG_VBUS_IRQ);
+        D16(USB_OTG_VBUS_MASK);
+        D16(USB_LINKINFO);
+        D16(USB_VPLEN);
+        D16(USB_HS_EOF1);
+        D16(USB_FS_EOF1);
+        D16(USB_LS_EOF1);
+        D16(USB_APHY_CNTRL);
+        D16(USB_APHY_CALIB);
+        D16(USB_APHY_CNTRL2);
+        D16(USB_PHY_TEST);
+        D16(USB_PLLOSC_CTRL);
+        D16(USB_SRP_CLKDIV);
+        D16(USB_EP_NI0_TXMAXP);
+        D16(USB_EP_NI0_TXCSR);
+        D16(USB_EP_NI0_RXMAXP);
+        D16(USB_EP_NI0_RXCSR);
+        D16(USB_EP_NI0_RXCOUNT);
+        D16(USB_EP_NI0_TXTYPE);
+        D16(USB_EP_NI0_TXINTERVAL);
+        D16(USB_EP_NI0_RXTYPE);
+        D16(USB_EP_NI0_RXINTERVAL);
+        D16(USB_EP_NI0_TXCOUNT);
+        D16(USB_EP_NI1_TXMAXP);
+        D16(USB_EP_NI1_TXCSR);
+        D16(USB_EP_NI1_RXMAXP);
+        D16(USB_EP_NI1_RXCSR);
+        D16(USB_EP_NI1_RXCOUNT);
+        D16(USB_EP_NI1_TXTYPE);
+        D16(USB_EP_NI1_TXINTERVAL);
+        D16(USB_EP_NI1_RXTYPE);
+        D16(USB_EP_NI1_RXINTERVAL);
+        D16(USB_EP_NI1_TXCOUNT);
+        D16(USB_EP_NI2_TXMAXP);
+        D16(USB_EP_NI2_TXCSR);
+        D16(USB_EP_NI2_RXMAXP);
+        D16(USB_EP_NI2_RXCSR);
+        D16(USB_EP_NI2_RXCOUNT);
+        D16(USB_EP_NI2_TXTYPE);
+        D16(USB_EP_NI2_TXINTERVAL);
+        D16(USB_EP_NI2_RXTYPE);
+        D16(USB_EP_NI2_RXINTERVAL);
+        D16(USB_EP_NI2_TXCOUNT);
+        D16(USB_EP_NI3_TXMAXP);
+        D16(USB_EP_NI3_TXCSR);
+        D16(USB_EP_NI3_RXMAXP);
+        D16(USB_EP_NI3_RXCSR);
+        D16(USB_EP_NI3_RXCOUNT);
+        D16(USB_EP_NI3_TXTYPE);
+        D16(USB_EP_NI3_TXINTERVAL);
+        D16(USB_EP_NI3_RXTYPE);
+        D16(USB_EP_NI3_RXINTERVAL);
+        D16(USB_EP_NI3_TXCOUNT);
+        D16(USB_EP_NI4_TXMAXP);
+        D16(USB_EP_NI4_TXCSR);
+        D16(USB_EP_NI4_RXMAXP);
+        D16(USB_EP_NI4_RXCSR);
+        D16(USB_EP_NI4_RXCOUNT);
+        D16(USB_EP_NI4_TXTYPE);
+        D16(USB_EP_NI4_TXINTERVAL);
+        D16(USB_EP_NI4_RXTYPE);
+        D16(USB_EP_NI4_RXINTERVAL);
+        D16(USB_EP_NI4_TXCOUNT);
+        D16(USB_EP_NI5_TXMAXP);
+        D16(USB_EP_NI5_TXCSR);
+        D16(USB_EP_NI5_RXMAXP);
+        D16(USB_EP_NI5_RXCSR);
+        D16(USB_EP_NI5_RXCOUNT);
+        D16(USB_EP_NI5_TXTYPE);
+        D16(USB_EP_NI5_TXINTERVAL);
+        D16(USB_EP_NI5_RXTYPE);
+        D16(USB_EP_NI5_RXINTERVAL);
+        D16(USB_EP_NI5_TXCOUNT);
+        D16(USB_EP_NI6_TXMAXP);
+        D16(USB_EP_NI6_TXCSR);
+        D16(USB_EP_NI6_RXMAXP);
+        D16(USB_EP_NI6_RXCSR);
+        D16(USB_EP_NI6_RXCOUNT);
+        D16(USB_EP_NI6_TXTYPE);
+        D16(USB_EP_NI6_TXINTERVAL);
+        D16(USB_EP_NI6_RXTYPE);
+        D16(USB_EP_NI6_RXINTERVAL);
+        D16(USB_EP_NI6_TXCOUNT);
+        D16(USB_EP_NI7_TXMAXP);
+        D16(USB_EP_NI7_TXCSR);
+        D16(USB_EP_NI7_RXMAXP);
+        D16(USB_EP_NI7_RXCSR);
+        D16(USB_EP_NI7_RXCOUNT);
+        D16(USB_EP_NI7_TXTYPE);
+        D16(USB_EP_NI7_TXINTERVAL);
+        D16(USB_EP_NI7_RXTYPE);
+        D16(USB_EP_NI7_RXINTERVAL);
+        D16(USB_EP_NI7_TXCOUNT);
+        D16(USB_DMA_INTERRUPT);
+        D16(USB_DMA0CONTROL);
+        D16(USB_DMA0ADDRLOW);
+        D16(USB_DMA0ADDRHIGH);
+        D16(USB_DMA0COUNTLOW);
+        D16(USB_DMA0COUNTHIGH);
+        D16(USB_DMA1CONTROL);
+        D16(USB_DMA1ADDRLOW);
+        D16(USB_DMA1ADDRHIGH);
+        D16(USB_DMA1COUNTLOW);
+        D16(USB_DMA1COUNTHIGH);
+        D16(USB_DMA2CONTROL);
+        D16(USB_DMA2ADDRLOW);
+        D16(USB_DMA2ADDRHIGH);
+        D16(USB_DMA2COUNTLOW);
+        D16(USB_DMA2COUNTHIGH);
+        D16(USB_DMA3CONTROL);
+        D16(USB_DMA3ADDRLOW);
+        D16(USB_DMA3ADDRHIGH);
+        D16(USB_DMA3COUNTLOW);
+        D16(USB_DMA3COUNTHIGH);
+        D16(USB_DMA4CONTROL);
+        D16(USB_DMA4ADDRLOW);
+        D16(USB_DMA4ADDRHIGH);
+        D16(USB_DMA4COUNTLOW);
+        D16(USB_DMA4COUNTHIGH);
+        D16(USB_DMA5CONTROL);
+        D16(USB_DMA5ADDRLOW);
+        D16(USB_DMA5ADDRHIGH);
+        D16(USB_DMA5COUNTLOW);
+        D16(USB_DMA5COUNTHIGH);
+        D16(USB_DMA6CONTROL);
+        D16(USB_DMA6ADDRLOW);
+        D16(USB_DMA6ADDRHIGH);
+        D16(USB_DMA6COUNTLOW);
+        D16(USB_DMA6COUNTHIGH);
+        D16(USB_DMA7CONTROL);
+        D16(USB_DMA7ADDRLOW);
+        D16(USB_DMA7ADDRHIGH);
+        D16(USB_DMA7COUNTLOW);
+        D16(USB_DMA7COUNTHIGH);
+#endif
+
+#ifdef WDOG_CNT
+        parent = debugfs_create_dir("watchdog", top);
+        D32(WDOG_CNT);
+        D16(WDOG_CTL);
+        D32(WDOG_STAT);
+#endif
+#ifdef WDOGA_CNT
+        parent = debugfs_create_dir("watchdog", top);
+        D32(WDOGA_CNT);
+        D16(WDOGA_CTL);
+        D32(WDOGA_STAT);
+        D32(WDOGB_CNT);
+        D16(WDOGB_CTL);
+        D32(WDOGB_STAT);
+#endif
+
+        /* BF533 glue */
+#ifdef FIO_FLAG_D
+#define PORTFIO FIO_FLAG_D
+#endif
+        /* BF561 glue */
+#ifdef FIO0_FLAG_D
+#define PORTFIO FIO0_FLAG_D
+#endif
+#ifdef FIO1_FLAG_D
+#define PORTGIO FIO1_FLAG_D
+#endif
+#ifdef FIO2_FLAG_D
+#define PORTHIO FIO2_FLAG_D
+#endif
+        parent = debugfs_create_dir("port", top);
+#ifdef PORTFIO
+        PORT(PORTFIO, 'F');
+#endif
+#ifdef PORTGIO
+        PORT(PORTGIO, 'G');
+#endif
+#ifdef PORTHIO
+        PORT(PORTHIO, 'H');
+#endif
+
+#ifdef __ADSPBF51x__
+        D16(PORTF_FER);
+        D16(PORTF_DRIVE);
+        D16(PORTF_HYSTERESIS);
+        D16(PORTF_MUX);
+
+        D16(PORTG_FER);
+        D16(PORTG_DRIVE);
+        D16(PORTG_HYSTERESIS);
+        D16(PORTG_MUX);
+
+        D16(PORTH_FER);
+        D16(PORTH_DRIVE);
+        D16(PORTH_HYSTERESIS);
+        D16(PORTH_MUX);
+
+        D16(MISCPORT_DRIVE);
+        D16(MISCPORT_HYSTERESIS);
+#endif  /* BF51x */
+
+#ifdef __ADSPBF52x__
+        D16(PORTF_FER);
+        D16(PORTF_DRIVE);
+        D16(PORTF_HYSTERESIS);
+        D16(PORTF_MUX);
+        D16(PORTF_SLEW);
+
+        D16(PORTG_FER);
+        D16(PORTG_DRIVE);
+        D16(PORTG_HYSTERESIS);
+        D16(PORTG_MUX);
+        D16(PORTG_SLEW);
+
+        D16(PORTH_FER);
+        D16(PORTH_DRIVE);
+        D16(PORTH_HYSTERESIS);
+        D16(PORTH_MUX);
+        D16(PORTH_SLEW);
+
+        D16(MISCPORT_DRIVE);
+        D16(MISCPORT_HYSTERESIS);
+        D16(MISCPORT_SLEW);
+#endif  /* BF52x */
+
+#ifdef BF537_FAMILY
+        D16(PORTF_FER);
+        D16(PORTG_FER);
+        D16(PORTH_FER);
+        D16(PORT_MUX);
+#endif  /* BF534 BF536 BF537 */
+
+#ifdef BF538_FAMILY
+        D16(PORTCIO_FER);
+        D16(PORTCIO);
+        D16(PORTCIO_CLEAR);
+        D16(PORTCIO_SET);
+        D16(PORTCIO_TOGGLE);
+        D16(PORTCIO_DIR);
+        D16(PORTCIO_INEN);
+
+        D16(PORTDIO);
+        D16(PORTDIO_CLEAR);
+        D16(PORTDIO_DIR);
+        D16(PORTDIO_FER);
+        D16(PORTDIO_INEN);
+        D16(PORTDIO_SET);
+        D16(PORTDIO_TOGGLE);
+
+        D16(PORTEIO);
+        D16(PORTEIO_CLEAR);
+        D16(PORTEIO_DIR);
+        D16(PORTEIO_FER);
+        D16(PORTEIO_INEN);
+        D16(PORTEIO_SET);
+        D16(PORTEIO_TOGGLE);
+#endif  /* BF538 BF539 */
+
+#ifdef __ADSPBF54x__
+        {
+                int num;
+                unsigned long base;
+                char *_buf, buf[32];
+
+                base = PORTA_FER;
+                for (num = 0; num < 10; ++num) {
+                        PORT(base, num);
+                        base += sizeof(struct bfin_gpio_regs);
+                }
+
+#define __PINT(uname, lname) __REGS(pint, #uname, lname)
+                parent = debugfs_create_dir("pint", top);
+                base = PINT0_MASK_SET;
+                for (num = 0; num < 4; ++num) {
+                        _buf = REGS_STR_PFX(buf, PINT, num);
+                        __PINT(MASK_SET, mask_set);
+                        __PINT(MASK_CLEAR, mask_clear);
+                        __PINT(IRQ, irq);
+                        __PINT(ASSIGN, assign);
+                        __PINT(EDGE_SET, edge_set);
+                        __PINT(EDGE_CLEAR, edge_clear);
+                        __PINT(INVERT_SET, invert_set);
+                        __PINT(INVERT_CLEAR, invert_clear);
+                        __PINT(PINSTATE, pinstate);
+                        __PINT(LATCH, latch);
+                        base += sizeof(struct bfin_pint_regs);
+                }
+
+        }
+#endif  /* BF54x */
+
+        debug_mmrs_dentry = top;
+
+        return 0;
+}
+module_init(bfin_debug_mmrs_init);
+
+static void __exit bfin_debug_mmrs_exit(void)
+{
+        debugfs_remove_recursive(debug_mmrs_dentry);
+}
+module_exit(bfin_debug_mmrs_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index f37019c847c9..486426f8a0d7 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -33,6 +33,7 @@
 #include <linux/io.h>
 #include <asm/system.h>
 #include <asm/atomic.h>
+#include <asm/irq_handler.h>
 
 DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
 
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 1696d34f51c2..ff3d747154ac 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -11,6 +11,7 @@
 #include <linux/kallsyms.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <asm/irq_handler.h>
 #include <asm/trace.h>
 #include <asm/pda.h>
 
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
index 401eb1d8e3b4..679d0db35256 100644
--- a/arch/blackfin/kernel/nmi.c
+++ b/arch/blackfin/kernel/nmi.c
@@ -145,16 +145,16 @@ int check_nmi_wdt_touched(void)
 {
         unsigned int this_cpu = smp_processor_id();
         unsigned int cpu;
+        cpumask_t mask;
 
-        cpumask_t mask = cpu_online_map;
-
+        cpumask_copy(&mask, cpu_online_mask);
         if (!atomic_read(&nmi_touched[this_cpu]))
                 return 0;
 
         atomic_set(&nmi_touched[this_cpu], 0);
 
-        cpu_clear(this_cpu, mask);
-        for_each_cpu_mask(cpu, mask) {
+        cpumask_clear_cpu(this_cpu, &mask);
+        for_each_cpu(cpu, &mask) {
                 invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
                                 (unsigned long)(&nmi_touched[cpu]));
                 if (!atomic_read(&nmi_touched[cpu]))
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
new file mode 100644
index 000000000000..04300f29c0e7
--- /dev/null
+++ b/arch/blackfin/kernel/perf_event.c
@@ -0,0 +1,498 @@
+/*
+ * Blackfin performance counters
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Ripped from SuperH version:
+ *
+ *  Copyright (C) 2009  Paul Mundt
+ *
+ * Heavily based on the x86 and PowerPC implementations.
+ *
+ * x86:
+ *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
+ *  Copyright (C) 2009 Jaswinder Singh Rajput
+ *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
+ *
+ * ppc:
+ *  Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/perf_event.h>
+#include <asm/bfin_pfmon.h>
+
+/*
+ * We have two counters, and each counter can support an event type.
+ * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
+ *
+ * 0x04 o pc invariant branches
+ * 0x06 o mispredicted branches
+ * 0x09 o predicted branches taken
+ * 0x0B o EXCPT insn
+ * 0x0C o CSYNC/SSYNC insn
+ * 0x0D o Insns committed
+ * 0x0E o Interrupts taken
+ * 0x0F o Misaligned address exceptions
+ * 0x80 o Code memory fetches stalled due to DMA
+ * 0x83 o 64bit insn fetches delivered
+ * 0x9A o data cache fills (bank a)
+ * 0x9B o data cache fills (bank b)
+ * 0x9C o data cache lines evicted (bank a)
+ * 0x9D o data cache lines evicted (bank b)
+ * 0x9E o data cache high priority fills
+ * 0x9F o data cache low priority fills
+ * 0x00 s loop 0 iterations
+ * 0x01 s loop 1 iterations
+ * 0x0A s CSYNC/SSYNC stalls
+ * 0x10 s DAG read/after write hazards
+ * 0x13 s RAW data hazards
+ * 0x81 s code TAG stalls
+ * 0x82 s code fill stalls
+ * 0x90 s processor to memory stalls
+ * 0x91 s data memory stalls not hidden by 0x90
+ * 0x92 s data store buffer full stalls
+ * 0x93 s data memory write buffer full stalls due to high->low priority
+ * 0x95 s data memory fill buffer stalls
+ * 0x96 s data TAG collision stalls
+ * 0x97 s data collision stalls
+ * 0x98 s data stalls
+ * 0x99 s data stalls sent to processor
+ */
+
+static const int event_map[] = {
+        /* use CYCLES cpu register */
+        [PERF_COUNT_HW_CPU_CYCLES]          = -1,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = 0x0D,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = -1,
+        [PERF_COUNT_HW_CACHE_MISSES]        = 0x83,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = 0x06,
+        [PERF_COUNT_HW_BUS_CYCLES]          = -1,
+};
+
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+
+static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
+                             [PERF_COUNT_HW_CACHE_OP_MAX]
+                             [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+        [C(L1D)] = {    /* Data bank A */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)] = 0,
+                        [C(RESULT_MISS)  ] = 0x9A,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)] = 0,
+                        [C(RESULT_MISS)  ] = 0,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)] = 0,
+                        [C(RESULT_MISS)  ] = 0,
+                },
+        },
+
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)] = 0,
+                        [C(RESULT_MISS)  ] = 0x83,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)] = 0,
+                        [C(RESULT_MISS)  ] = 0,
+                },
+        },
+
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+        },
+
+        [C(DTLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+        },
+
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+        },
+
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)] = -1,
+                        [C(RESULT_MISS)  ] = -1,
+                },
+        },
+};
+
+const char *perf_pmu_name(void)
+{
+        return "bfin";
+}
+EXPORT_SYMBOL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+        return ARRAY_SIZE(event_map);
+}
+EXPORT_SYMBOL(perf_num_counters);
+
+static u64 bfin_pfmon_read(int idx)
+{
+        return bfin_read32(PFCNTR0 + (idx * 4));
+}
+
+static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
+{
+        bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
+}
+
+static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
+{
+        u32 val, mask;
+
+        val = PFPWR;
+        if (idx) {
+                mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
+                /* The packed config is for event0, so shift it to event1 slots */
+                val |= (hwc->config << (PFMON1_P - PFMON0_P));
+                val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
+                bfin_write_PFCNTR1(0);
+        } else {
+                mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
+                val |= hwc->config;
+                bfin_write_PFCNTR0(0);
+        }
+
+        bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
+}
+
+static void bfin_pfmon_disable_all(void)
+{
+        bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
+}
+
+static void bfin_pfmon_enable_all(void)
+{
+        bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
+}
+
+struct cpu_hw_events {
+        struct perf_event *events[MAX_HWEVENTS];
+        unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+
+static int hw_perf_cache_event(int config, int *evp)
+{
+        unsigned long type, op, result;
+        int ev;
+
+        /* unpack config */
+        type = config & 0xff;
+        op = (config >> 8) & 0xff;
+        result = (config >> 16) & 0xff;
+
+        if (type >= PERF_COUNT_HW_CACHE_MAX ||
+            op >= PERF_COUNT_HW_CACHE_OP_MAX ||
+            result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return -EINVAL;
+
+        ev = cache_events[type][op][result];
+        if (ev == 0)
+                return -EOPNOTSUPP;
+        if (ev == -1)
+                return -EINVAL;
+        *evp = ev;
+        return 0;
+}
+
+static void bfin_perf_event_update(struct perf_event *event,
+                                   struct hw_perf_event *hwc, int idx)
+{
+        u64 prev_raw_count, new_raw_count;
+        s64 delta;
+        int shift = 0;
+
+        /*
+         * Depending on the counter configuration, they may or may not
+         * be chained, in which case the previous counter value can be
+         * updated underneath us if the lower-half overflows.
+         *
+         * Our tactic to handle this is to first atomically read and
+         * exchange a new raw count - then add that new-prev delta
+         * count to the generic counter atomically.
+         *
+         * As there is no interrupt associated with the overflow events,
+         * this is the simplest approach for maintaining consistency.
+         */
+again:
+        prev_raw_count = local64_read(&hwc->prev_count);
+        new_raw_count = bfin_pfmon_read(idx);
+
+        if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                             new_raw_count) != prev_raw_count)
+                goto again;
+
+        /*
+         * Now we have the new raw value and have updated the prev
+         * timestamp already. We can now calculate the elapsed delta
+         * (counter-)time and add that to the generic counter.
+         *
+         * Careful, not all hw sign-extends above the physical width
+         * of the count.
+         */
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+
+        local64_add(delta, &event->count);
+}
+
+static void bfin_pmu_stop(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        if (!(event->hw.state & PERF_HES_STOPPED)) {
+                bfin_pfmon_disable(hwc, idx);
+                cpuc->events[idx] = NULL;
+                event->hw.state |= PERF_HES_STOPPED;
+        }
+
+        if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
+                bfin_perf_event_update(event, &event->hw, idx);
+                event->hw.state |= PERF_HES_UPTODATE;
+        }
+}
+
+static void bfin_pmu_start(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        if (WARN_ON_ONCE(idx == -1))
+                return;
+
+        if (flags & PERF_EF_RELOAD)
+                WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
+
+        cpuc->events[idx] = event;
+        event->hw.state = 0;
+        bfin_pfmon_enable(hwc, idx);
+}
+
+static void bfin_pmu_del(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+        bfin_pmu_stop(event, PERF_EF_UPDATE);
+        __clear_bit(event->hw.idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
+static int bfin_pmu_add(struct perf_event *event, int flags)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+        int ret = -EAGAIN;
+
+        perf_pmu_disable(event->pmu);
+
+        if (__test_and_set_bit(idx, cpuc->used_mask)) {
+                idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
+                if (idx == MAX_HWEVENTS)
+                        goto out;
+
+                __set_bit(idx, cpuc->used_mask);
+                hwc->idx = idx;
+        }
+
+        bfin_pfmon_disable(hwc, idx);
+
+        event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+        if (flags & PERF_EF_START)
+                bfin_pmu_start(event, PERF_EF_RELOAD);
+
+        perf_event_update_userpage(event);
+        ret = 0;
+out:
+        perf_pmu_enable(event->pmu);
+        return ret;
+}
+
+static void bfin_pmu_read(struct perf_event *event)
+{
+        bfin_perf_event_update(event, &event->hw, event->hw.idx);
+}
+
+static int bfin_pmu_event_init(struct perf_event *event)
+{
+        struct perf_event_attr *attr = &event->attr;
+        struct hw_perf_event *hwc = &event->hw;
+        int config = -1;
+        int ret;
+
+        if (attr->exclude_hv || attr->exclude_idle)
+                return -EPERM;
+
+        /*
+         * All of the on-chip counters are "limited", in that they have
+         * no interrupts, and are therefore unable to do sampling without
+         * further work and timer assistance.
+         */
+        if (hwc->sample_period)
+                return -EINVAL;
+
+        ret = 0;
+        switch (attr->type) {
+        case PERF_TYPE_RAW:
+                config = PFMON(0, attr->config & PFMON_MASK) |
+                        PFCNT(0, !(attr->config & 0x100));
+                break;
+        case PERF_TYPE_HW_CACHE:
+                ret = hw_perf_cache_event(attr->config, &config);
+                break;
+        case PERF_TYPE_HARDWARE:
+                if (attr->config >= ARRAY_SIZE(event_map))
+                        return -EINVAL;
+
+                config = event_map[attr->config];
+                break;
+        }
+
+        if (config == -1)
+                return -EINVAL;
+
+        if (!attr->exclude_kernel)
+                config |= PFCEN(0, PFCEN_ENABLE_SUPV);
+        if (!attr->exclude_user)
+                config |= PFCEN(0, PFCEN_ENABLE_USER);
+
+        hwc->config |= config;
+
+        return ret;
+}
+
+static void bfin_pmu_enable(struct pmu *pmu)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct perf_event *event;
+        struct hw_perf_event *hwc;
+        int i;
+
+        for (i = 0; i < MAX_HWEVENTS; ++i) {
+                event = cpuc->events[i];
+                if (!event)
+                        continue;
+                hwc = &event->hw;
+                bfin_pfmon_enable(hwc, hwc->idx);
+        }
+
+        bfin_pfmon_enable_all();
+}
+
+static void bfin_pmu_disable(struct pmu *pmu)
+{
+        bfin_pfmon_disable_all();
+}
+
+static struct pmu pmu = {
+        .pmu_enable  = bfin_pmu_enable,
+        .pmu_disable = bfin_pmu_disable,
+        .event_init  = bfin_pmu_event_init,
+        .add         = bfin_pmu_add,
+        .del         = bfin_pmu_del,
+        .start       = bfin_pmu_start,
+        .stop        = bfin_pmu_stop,
+        .read        = bfin_pmu_read,
+};
+
+static void bfin_pmu_setup(int cpu)
+{
+        struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
+
+        memset(cpuhw, 0, sizeof(struct cpu_hw_events));
+}
+
+static int __cpuinit
+bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
+{
+        unsigned int cpu = (long)hcpu;
+
+        switch (action & ~CPU_TASKS_FROZEN) {
+        case CPU_UP_PREPARE:
+                bfin_write_PFCTL(0);
+                bfin_pmu_setup(cpu);
+                break;
+
+        default:
+                break;
+        }
+
+        return NOTIFY_OK;
+}
+
+static int __init bfin_pmu_init(void)
+{
+        int ret;
+
+        ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
+        if (!ret)
+                perf_cpu_notifier(bfin_pmu_notifier);
+
+        return ret;
+}
+early_initcall(bfin_pmu_init);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index b407bc8ad918..6a660fa921b5 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -171,10 +171,8 @@ asmlinkage int bfin_clone(struct pt_regs *regs)
         unsigned long newsp;
 
 #ifdef __ARCH_SYNC_CORE_DCACHE
-        if (current->rt.nr_cpus_allowed == num_possible_cpus()) {
-                current->cpus_allowed = cpumask_of_cpu(smp_processor_id());
-                current->rt.nr_cpus_allowed = 1;
-        }
+        if (current->rt.nr_cpus_allowed == num_possible_cpus())
+                set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
 #endif
 
         /* syscall2 puts clone_flags in r0 and usp in r1 */
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 53d08dee8531..488bdc51aaa5 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -23,6 +23,9 @@
 __attribute__ ((__l1_text__, __noreturn__))
 static void bfin_reset(void)
 {
+        if (!ANOMALY_05000353 && !ANOMALY_05000386)
+                bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
+
         /* Wait for completion of "system" events such as cache line
          * line fills so that we avoid infinite stalls later on as
          * much as possible.  This code is in L1, so it won't trigger
@@ -30,46 +33,40 @@ static void bfin_reset(void)
          */
         __builtin_bfin_ssync();
 
-        /* The bootrom checks to see how it was reset and will
-         * automatically perform a software reset for us when
-         * it starts executing after the core reset.
-         */
-        if (ANOMALY_05000353 || ANOMALY_05000386) {
-                /* Initiate System software reset. */
-                bfin_write_SWRST(0x7);
+        /* Initiate System software reset. */
+        bfin_write_SWRST(0x7);
 
-                /* Due to the way reset is handled in the hardware, we need
-                 * to delay for 10 SCLKS.  The only reliable way to do this is
-                 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
-                 * we'll assume worse case which is a 1:15 ratio.
-                 */
-                asm(
-                        "LSETUP (1f, 1f) LC0 = %0\n"
-                        "1: nop;"
-                        :
-                        : "a" (15 * 10)
-                        : "LC0", "LB0", "LT0"
-                );
+        /* Due to the way reset is handled in the hardware, we need
+         * to delay for 10 SCLKS.  The only reliable way to do this is
+         * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
+         * we'll assume worse case which is a 1:15 ratio.
+         */
+        asm(
+                "LSETUP (1f, 1f) LC0 = %0\n"
+                "1: nop;"
+                :
+                : "a" (15 * 10)
+                : "LC0", "LB0", "LT0"
+        );
 
-                /* Clear System software reset */
-                bfin_write_SWRST(0);
+        /* Clear System software reset */
+        bfin_write_SWRST(0);
 
-                /* The BF526 ROM will crash during reset */
+        /* The BF526 ROM will crash during reset */
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-                bfin_read_SWRST();
+        bfin_read_SWRST();
 #endif
 
-                /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-                 * though as the System state is all reset now.
-                 */
-                asm(
-                        "LSETUP (1f, 1f) LC1 = %0\n"
-                        "1: nop;"
-                        :
-                        : "a" (15 * 1)
-                        : "LC1", "LB1", "LT1"
-                );
-        }
+        /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
+         * though as the System state is all reset now.
+         */
+        asm(
+                "LSETUP (1f, 1f) LC1 = %0\n"
+                "1: nop;"
+                :
+                : "a" (15 * 1)
+                : "LC1", "LB1", "LT1"
+        );
 
         while (1)
                 /* Issue core reset */
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 805c6132c779..536bd9d7e0cf 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -29,6 +29,7 @@
 #include <asm/cpu.h>
 #include <asm/fixed_code.h>
 #include <asm/early_printk.h>
+#include <asm/irq_handler.h>
 
 u16 _bfin_swrst;
 EXPORT_SYMBOL(_bfin_swrst);
@@ -105,6 +106,8 @@ void __cpuinit bfin_setup_caches(unsigned int cpu)
         bfin_dcache_init(dcplb_tbl[cpu]);
 #endif
 
+        bfin_setup_cpudata(cpu);
+
         /*
          * In cache coherence emulation mode, we need to have the
          * D-cache enabled before running any atomic operation which
@@ -163,7 +166,6 @@ void __cpuinit bfin_setup_cpudata(unsigned int cpu)
 {
         struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
 
-        cpudata->idle = current;
         cpudata->imemctl = bfin_read_IMEM_CONTROL();
         cpudata->dmemctl = bfin_read_DMEM_CONTROL();
 }
@@ -851,6 +853,7 @@ void __init native_machine_early_platform_add_devices(void)
 
 void __init setup_arch(char **cmdline_p)
 {
+        u32 mmr;
         unsigned long sclk, cclk;
 
         native_machine_early_platform_add_devices();
@@ -902,10 +905,10 @@ void __init setup_arch(char **cmdline_p)
         bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 #endif
 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
-        bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
-        bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
-        bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
-        bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
+        bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
+        bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
+        bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
+        bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
                                         ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
 #endif
 
@@ -921,17 +924,14 @@ void __init setup_arch(char **cmdline_p)
                 bfin_read_IMDMA_D1_IRQ_STATUS();
         }
 #endif
-        printk(KERN_INFO "Hardware Trace ");
-        if (bfin_read_TBUFCTL() & 0x1)
-                printk(KERN_CONT "Active ");
-        else
-                printk(KERN_CONT "Off ");
-        if (bfin_read_TBUFCTL() & 0x2)
-                printk(KERN_CONT "and Enabled\n");
-        else
-                printk(KERN_CONT "and Disabled\n");
 
-        printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
+        mmr = bfin_read_TBUFCTL();
+        printk(KERN_INFO "Hardware Trace %s and %sabled\n",
+                (mmr & 0x1) ? "active" : "off",
+                (mmr & 0x2) ? "en" : "dis");
+
+        mmr = bfin_read_SYSCR();
+        printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
 
         /* Newer parts mirror SWRST bits in SYSCR */
 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
@@ -939,7 +939,7 @@ void __init setup_arch(char **cmdline_p)
         _bfin_swrst = bfin_read_SWRST();
 #else
         /* Clear boot mode field */
-        _bfin_swrst = bfin_read_SYSCR() & ~0xf;
+        _bfin_swrst = mmr & ~0xf;
 #endif
 
 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
@@ -1036,8 +1036,6 @@ void __init setup_arch(char **cmdline_p)
 static int __init topology_init(void)
 {
         unsigned int cpu;
-        /* Record CPU-private information for the boot processor. */
-        bfin_setup_cpudata(0);
 
         for_each_possible_cpu(cpu) {
                 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
@@ -1283,12 +1281,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                    dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
                    BFIN_DLINES);
 #ifdef __ARCH_SYNC_CORE_DCACHE
-        seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]);
+        seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
 #endif
 #ifdef __ARCH_SYNC_CORE_ICACHE
-        seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]);
+        seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
 #endif
 
+        seq_printf(m, "\n");
+
         if (cpu_num != num_possible_cpus() - 1)
                 return 0;
 
@@ -1312,13 +1312,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                               " in data cache\n");
         }
         seq_printf(m, "board name\t: %s\n", bfin_board_name);
-        seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
-                 physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
-        seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
+        seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
+                physical_mem_end >> 10, 0ul, physical_mem_end);
+        seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
                 ((int)memory_end - (int)_rambase) >> 10,
-                (void *)_rambase,
-                (void *)memory_end);
-        seq_printf(m, "\n");
+                _rambase, memory_end);
 
         return 0;
 }
@@ -1326,7 +1324,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 static void *c_start(struct seq_file *m, loff_t *pos)
 {
         if (*pos == 0)
-                *pos = first_cpu(cpu_online_map);
+                *pos = cpumask_first(cpu_online_mask);
         if (*pos >= num_online_cpus())
                 return NULL;
 
@@ -1335,7 +1333,7 @@ static void *c_start(struct seq_file *m, loff_t *pos)
 
 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 {
-        *pos = next_cpu(*pos, cpu_online_map);
+        *pos = cpumask_next(*pos, cpu_online_mask);
 
         return c_start(m, pos);
 }
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 854fa49f1c3e..3ac5b66d14aa 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -136,7 +136,7 @@ SECTIONS
 
         . = ALIGN(16);
         INIT_DATA_SECTION(16)
-        PERCPU(32, PAGE_SIZE)
+        PERCPU_SECTION(32)
 
         .exit.data :
         {
@@ -155,14 +155,8 @@ SECTIONS
                 SECURITY_INITCALL
                 INIT_RAM_FS
 
-                . = ALIGN(4);
                 ___per_cpu_load = .;
-                ___per_cpu_start = .;
-                *(.data.percpu.first)
-                *(.data.percpu.page_aligned)
-                *(.data.percpu)
-                *(.data.percpu.shared_aligned)
-                ___per_cpu_end = .;
+                PERCPU_INPUT(32)
 
                 EXIT_DATA
                 __einitdata = .;
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 24918c5f7ea1..d2f076fbbc9e 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -5,7 +5,7 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
@@ -141,6 +141,7 @@
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000371 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (0)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -155,6 +156,7 @@
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
 #define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index f6d924ac0c44..000000000000
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_res {
-        unsigned long uart_base_addr;
-        int uart_irq;
-        int uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int uart_tx_dma_channel;
-        unsigned int uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int uart_cts_pin;
-        int uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-         0xFFC00400,
-         IRQ_UART0_RX,
-         IRQ_UART0_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART0_TX,
-         CH_UART0_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-         CONFIG_UART0_CTS_PIN,
-         CONFIG_UART0_RTS_PIN,
-#endif
-         },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-         0xFFC02000,
-         IRQ_UART1_RX,
-         IRQ_UART1_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART1_TX,
-         CH_UART1_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-         CONFIG_UART1_CTS_PIN,
-         CONFIG_UART1_RTS_PIN,
-#endif
-         },
-#endif
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index b657d37a3402..bb79627f0929 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -990,18 +990,18 @@
 #define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
 #define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
 #define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_PORTF_HYSTERESIS()            bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val)        bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS()            bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val)        bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS()            bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val)        bfin_write16(PORTH_HYSTERESIS, val)
 #define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
 #define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
 #define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
 #define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+#define bfin_read_MISCPORT_HYSTERESIS()         bfin_read16(MISCPORT_HYSTERESIS)
+#define bfin_write_MISCPORT_HYSTERESIS(val)     bfin_write16(MISCPORT_HYSTERESIS, val)
 
 /* HOST Port Registers */
 
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index cb1172f50757..729704078cd7 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -561,12 +561,12 @@
 #define PORTF_SLEW              0xFFC03230      /* Port F slew control */
 #define PORTG_SLEW              0xFFC03234      /* Port G slew control */
 #define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define PORTF_HYSTERESIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS        0xFFC03248      /* Port H Schmitt trigger control */
 #define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
 #define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+#define MISCPORT_HYSTERESIS     0xFFC03288      /* Misc Port Schmitt trigger control */
 
 
 /***********************************************************************************
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index 98a51c479290..cfab428e577c 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -36,13 +36,13 @@
 #define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
 #define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
 #define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
-#define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
-#define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
-#define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
-#define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
+#define RSI_PID0                       0xFFC038D0 /* RSI Peripheral ID Register 0 */
+#define RSI_PID1                       0xFFC038D4 /* RSI Peripheral ID Register 1 */
+#define RSI_PID2                       0xFFC038D8 /* RSI Peripheral ID Register 2 */
+#define RSI_PID3                       0xFFC038DC /* RSI Peripheral ID Register 3 */
+#define RSI_PID4                       0xFFC038E0 /* RSI Peripheral ID Register 0 */
+#define RSI_PID5                       0xFFC038E4 /* RSI Peripheral ID Register 1 */
+#define RSI_PID6                       0xFFC038E8 /* RSI Peripheral ID Register 2 */
+#define RSI_PID7                       0xFFC038EC /* RSI Peripheral ID Register 3 */
 
 #endif /* _DEF_BF514_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index 435e76e31aaa..edf8efd457dc 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -7,38 +7,9 @@
 #ifndef _BF518_IRQ_H_
 #define _BF518_IRQ_H_
 
-/*
- * Interrupt source definitions
-        Event Source    Core Event Name
-        Core        Emulation               **
-        Events         (highest priority)  EMU         0
-        Reset                   RST         1
-        NMI                     NMI         2
-        Exception               EVX         3
-        Reserved                --          4
-        Hardware Error          IVHW        5
-        Core Timer              IVTMR       6 *
-
-        .....
-
-         Software Interrupt 1    IVG14       31
-         Software Interrupt 2    --
-         (lowest priority)  IVG15       32 *
-*/
-
-#define NR_PERI_INTS    (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS            (2 * 32)
 
 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
@@ -54,23 +25,23 @@
 #define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
 #define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
 #define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
-#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
+#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI) */
 #define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
 #define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
 #define IRQ_RSI                 BFIN_IRQ(17)    /* DMA 4 Channel (RSI) */
 #define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX/SPI) */
 #define IRQ_SPI1                BFIN_IRQ(18)    /* DMA 5 Channel (SPI1) */
 #define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
-#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
-#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
+#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
+#define IRQ_SPI0                BFIN_IRQ(21)    /* DMA 7 Channel (SPI0) */
+#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
+#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
+#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX) */
+#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX) */
 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
 #define IRQ_TIMER0              BFIN_IRQ(32)    /* Timer 0 */
@@ -96,101 +67,90 @@
 #define IRQ_PWM_SYNC            BFIN_IRQ(54)    /* PWM Sync Interrupt */
 #define IRQ_PTP_STAT            BFIN_IRQ(55)    /* PTP Stat Interrupt */
 
-#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
-
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define IRQ_PG0         87
-#define IRQ_PG1         88
-#define IRQ_PG2         89
-#define IRQ_PG3         90
-#define IRQ_PG4         91
-#define IRQ_PG5         92
-#define IRQ_PG6         93
-#define IRQ_PG7         94
-#define IRQ_PG8         95
-#define IRQ_PG9         96
-#define IRQ_PG10        97
-#define IRQ_PG11        98
-#define IRQ_PG12        99
-#define IRQ_PG13        100
-#define IRQ_PG14        101
-#define IRQ_PG15        102
-
-#define IRQ_PH0         103
-#define IRQ_PH1         104
-#define IRQ_PH2         105
-#define IRQ_PH3         106
-#define IRQ_PH4         107
-#define IRQ_PH5         108
-#define IRQ_PH6         109
-#define IRQ_PH7         110
-#define IRQ_PH8         111
-#define IRQ_PH9         112
-#define IRQ_PH10        113
-#define IRQ_PH11        114
-#define IRQ_PH12        115
-#define IRQ_PH13        116
-#define IRQ_PH14        117
-#define IRQ_PH15        118
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define IRQ_MAC_PHYINT          119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT          120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT         121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT         122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET         123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR        124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR        125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE         126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS    (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS         (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
+#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
+
+#define IRQ_PF0                 71
+#define IRQ_PF1                 72
+#define IRQ_PF2                 73
+#define IRQ_PF3                 74
+#define IRQ_PF4                 75
+#define IRQ_PF5                 76
+#define IRQ_PF6                 77
+#define IRQ_PF7                 78
+#define IRQ_PF8                 79
+#define IRQ_PF9                 80
+#define IRQ_PF10                81
+#define IRQ_PF11                82
+#define IRQ_PF12                83
+#define IRQ_PF13                84
+#define IRQ_PF14                85
+#define IRQ_PF15                86
+
+#define IRQ_PG0                 87
+#define IRQ_PG1                 88
+#define IRQ_PG2                 89
+#define IRQ_PG3                 90
+#define IRQ_PG4                 91
+#define IRQ_PG5                 92
+#define IRQ_PG6                 93
+#define IRQ_PG7                 94
+#define IRQ_PG8                 95
+#define IRQ_PG9                 96
+#define IRQ_PG10                97
+#define IRQ_PG11                98
+#define IRQ_PG12                99
+#define IRQ_PG13                100
+#define IRQ_PG14                101
+#define IRQ_PG15                102
+
+#define IRQ_PH0                 103
+#define IRQ_PH1                 104
+#define IRQ_PH2                 105
+#define IRQ_PH3                 106
+#define IRQ_PH4                 107
+#define IRQ_PH5                 108
+#define IRQ_PH6                 109
+#define IRQ_PH7                 110
+#define IRQ_PH8                 111
+#define IRQ_PH9                 112
+#define IRQ_PH10                113
+#define IRQ_PH11                114
+#define IRQ_PH12                115
+#define IRQ_PH13                116
+#define IRQ_PH14                117
+#define IRQ_PH15                118
+
+#define GPIO_IRQ_BASE           IRQ_PF0
+
+#define IRQ_MAC_PHYINT          119     /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT          120     /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT         121     /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT         122     /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET         123     /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR        124     /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR        125     /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE         126     /* Station Mgt. Transfer Done Interrupt */
+
+#define NR_MACH_IRQS            (IRQ_MAC_STMDONE + 1)
 
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS      0
 #define IRQ_DMA0_ERROR_POS      4
-#define IRQ_DMAR0_BLK_POS       8
-#define IRQ_DMAR1_BLK_POS       12
-#define IRQ_DMAR0_OVR_POS       16
-#define IRQ_DMAR1_OVR_POS       20
-#define IRQ_PPI_ERROR_POS       24
-#define IRQ_MAC_ERROR_POS       28
+#define IRQ_DMAR0_BLK_POS       8
+#define IRQ_DMAR1_BLK_POS       12
+#define IRQ_DMAR0_OVR_POS       16
+#define IRQ_DMAR1_OVR_POS       20
+#define IRQ_PPI_ERROR_POS       24
+#define IRQ_MAC_ERROR_POS       28
 
 /* IAR1 BIT FIELDS */
 #define IRQ_SPORT0_ERROR_POS    0
 #define IRQ_SPORT1_ERROR_POS    4
 #define IRQ_PTP_ERROR_POS       8
-#define IRQ_UART0_ERROR_POS     16
-#define IRQ_UART1_ERROR_POS     20
-#define IRQ_RTC_POS             24
-#define IRQ_PPI_POS             28
+#define IRQ_UART0_ERROR_POS     16
+#define IRQ_UART1_ERROR_POS     20
+#define IRQ_RTC_POS             24
+#define IRQ_PPI_POS             28
 
 /* IAR2 BIT FIELDS */
 #define IRQ_SPORT0_RX_POS       0
@@ -199,19 +159,19 @@
 #define IRQ_SPORT1_RX_POS       8
 #define IRQ_SPI1_POS            8
 #define IRQ_SPORT1_TX_POS       12
-#define IRQ_TWI_POS             16
-#define IRQ_SPI0_POS            20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
+#define IRQ_TWI_POS             16
+#define IRQ_SPI0_POS            20
+#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_TX_POS        28
 
 /* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS        0
-#define IRQ_UART1_TX_POS        4
-#define IRQ_OPTSEC_POS          8
-#define IRQ_CNT_POS             12
-#define IRQ_MAC_RX_POS          16
+#define IRQ_UART1_RX_POS        0
+#define IRQ_UART1_TX_POS        4
+#define IRQ_OPTSEC_POS          8
+#define IRQ_CNT_POS             12
+#define IRQ_MAC_RX_POS          16
 #define IRQ_PORTH_INTA_POS      20
-#define IRQ_MAC_TX_POS          24
+#define IRQ_MAC_TX_POS          24
 #define IRQ_PORTH_INTB_POS      28
 
 /* IAR4 BIT FIELDS */
@@ -227,19 +187,19 @@
 /* IAR5 BIT FIELDS */
 #define IRQ_PORTG_INTA_POS      0
 #define IRQ_PORTG_INTB_POS      4
-#define IRQ_MEM_DMA0_POS        8
-#define IRQ_MEM_DMA1_POS        12
-#define IRQ_WATCH_POS           16
+#define IRQ_MEM_DMA0_POS        8
+#define IRQ_MEM_DMA1_POS        12
+#define IRQ_WATCH_POS           16
 #define IRQ_PORTF_INTA_POS      20
 #define IRQ_PORTF_INTB_POS      24
-#define IRQ_SPI0_ERROR_POS      28
+#define IRQ_SPI0_ERROR_POS      28
 
 /* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS      0
-#define IRQ_RSI_INT0_POS        12
-#define IRQ_RSI_INT1_POS        16
-#define IRQ_PWM_TRIP_POS        20
-#define IRQ_PWM_SYNC_POS        24
-#define IRQ_PTP_STAT_POS        28
-
-#endif                          /* _BF518_IRQ_H_ */
+#define IRQ_SPI1_ERROR_POS      0
+#define IRQ_RSI_INT0_POS        12
+#define IRQ_RSI_INT1_POS        16
+#define IRQ_PWM_TRIP_POS        20
+#define IRQ_PWM_SYNC_POS        24
+#define IRQ_PTP_STAT_POS        28
+
+#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 2cd2ff6f3043..e67ac7720668 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -26,6 +26,7 @@
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
 #include <linux/spi/ad7877.h>
+#include <asm/bfin_sport.h>
 
 /*
  * Name the Board for the /proc/cpuinfo
@@ -526,11 +527,69 @@ static struct bfin5xx_spi_chip spidev_chip_info = {
 };
 #endif
 
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+
+static const u16 bfin_snd_pin[][7] = {
+        {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+                P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
+        {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
+                P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+        {
+                .pin_req = &bfin_snd_pin[0][0],
+        },
+        {
+                .pin_req = &bfin_snd_pin[1][0],
+        },
+};
+
+#define BFIN_SND_RES(x) \
+        [x] = { \
+                { \
+                        .start = SPORT##x##_TCR1, \
+                        .end = SPORT##x##_TCR1, \
+                        .flags = IORESOURCE_MEM \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_RX, \
+                        .end = CH_SPORT##x##_RX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_TX, \
+                        .end = CH_SPORT##x##_TX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = IRQ_SPORT##x##_ERROR, \
+                        .end = IRQ_SPORT##x##_ERROR, \
+                        .flags = IORESOURCE_IRQ, \
+                } \
+        }
+
+static struct resource bfin_snd_resources[][4] = {
+        BFIN_SND_RES(0),
+        BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+        .name = "bfin-pcm-audio",
+        .id = -1,
+};
+#endif
+
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 static struct platform_device bfin_i2s = {
         .name = "bfin-i2s",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
@@ -538,7 +597,11 @@ static struct platform_device bfin_i2s = {
 static struct platform_device bfin_tdm = {
         .name = "bfin-tdm",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
@@ -583,7 +646,9 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
                 .max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num = 0,
                 .chip_select = 4,
+                .platform_data = "ad1836",
                 .controller_data = &ad1836_spi_chip_info,
+                .mode = SPI_MODE_3,
         },
 #endif
 #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -1211,6 +1276,11 @@ static struct platform_device *stamp_devices[] __initdata = {
         &ezkit_flash_device,
 #endif
 
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+        &bfin_pcm,
+#endif
+
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s,
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 9358afa05c90..e66a7e89cd3c 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,14 +5,14 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
  *  - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
 #define ANOMALY_05000483 (1)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
 #define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* The CODEC Zero-Cross Detect Feature is not Functional */
+#define ANOMALY_05000487 (1)
 /* IFLUSH sucks at life */
 #define ANOMALY_05000491 (1)
 
@@ -268,11 +270,13 @@
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000362 (1)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000400 (0)
 #define ANOMALY_05000402 (0)
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index 960e08919def..000000000000
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_res {
-        unsigned long uart_base_addr;
-        int uart_irq;
-        int uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int uart_tx_dma_channel;
-        unsigned int uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int uart_cts_pin;
-        int uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-         0xFFC00400,
-         IRQ_UART0_RX,
-         IRQ_UART0_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART0_TX,
-         CH_UART0_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-         CONFIG_UART0_CTS_PIN,
-         CONFIG_UART0_RTS_PIN,
-#endif
-         },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-         0xFFC02000,
-         IRQ_UART1_RX,
-         IRQ_UART1_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART1_TX,
-         CH_UART1_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-         CONFIG_UART1_CTS_PIN,
-         CONFIG_UART1_RTS_PIN,
-#endif
-         },
-#endif
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 618dfcdfa91a..2c12e879aa4e 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1007,18 +1007,18 @@
 #define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
 #define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
 #define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_PORTF_HYSTERESIS()            bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val)        bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS()            bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val)        bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS()            bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val)        bfin_write16(PORTH_HYSTERESIS, val)
 #define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
 #define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
 #define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
 #define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
+#define bfin_read_MISCPORT_HYSTERESIS()         bfin_read16(MISCPORT_HYSTERESIS)
+#define bfin_write_MISCPORT_HYSTERESIS(val)     bfin_write16(MISCPORT_HYSTERESIS, val)
 
 /* HOST Port Registers */
 
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 84ef11e52644..37d353a19722 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -562,12 +562,12 @@
 #define PORTF_SLEW              0xFFC03230      /* Port F slew control */
 #define PORTG_SLEW              0xFFC03234      /* Port G slew control */
 #define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
+#define PORTF_HYSTERESIS        0xFFC03240      /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS        0xFFC03244      /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS        0xFFC03248      /* Port H Schmitt trigger control */
 #define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
 #define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
+#define MISCPORT_HYSTERESIS     0xFFC03288      /* Misc Port Schmitt trigger control */
 
 
 /***********************************************************************************
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF525.h b/arch/blackfin/mach-bf527/include/mach/defBF525.h
index cc383adfdffa..aab80bb1a683 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF525.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF525.h
@@ -185,8 +185,8 @@
 #define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
 #define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03be0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03be8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
 
 #define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
 
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 704d9253e41d..ed7310ff819b 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -7,38 +7,9 @@
 #ifndef _BF527_IRQ_H_
 #define _BF527_IRQ_H_
 
-/*
- * Interrupt source definitions
-        Event Source    Core Event Name
-        Core        Emulation               **
-        Events         (highest priority)  EMU         0
-        Reset                   RST         1
-        NMI                     NMI         2
-        Exception               EVX         3
-        Reserved                --          4
-        Hardware Error          IVHW        5
-        Core Timer              IVTMR       6 *
-
-        .....
-
-         Software Interrupt 1    IVG14       31
-         Software Interrupt 2    --
-         (lowest priority)  IVG15       32 *
-*/
-
-#define NR_PERI_INTS    (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS            (2 * 32)
 
 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
@@ -53,21 +24,21 @@
 #define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
 #define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
 #define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
-#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI/NAND) */
+#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI/NAND) */
 #define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
 #define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
 #define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX) */
 #define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
-#define IRQ_SPI                 BFIN_IRQ(21)    /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
-#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
+#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
+#define IRQ_SPI                 BFIN_IRQ(21)    /* DMA 7 Channel (SPI) */
+#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
+#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
+#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX/HDMA) */
+#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
 #define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
 #define IRQ_NFC                 BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
 #define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
@@ -96,119 +67,108 @@
 #define IRQ_USB_INT2            BFIN_IRQ(54)    /* USB_INT2 Interrupt */
 #define IRQ_USB_DMA             BFIN_IRQ(55)    /* USB_DMAINT Interrupt */
 
-#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
-
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define IRQ_PG0         87
-#define IRQ_PG1         88
-#define IRQ_PG2         89
-#define IRQ_PG3         90
-#define IRQ_PG4         91
-#define IRQ_PG5         92
-#define IRQ_PG6         93
-#define IRQ_PG7         94
-#define IRQ_PG8         95
-#define IRQ_PG9         96
-#define IRQ_PG10        97
-#define IRQ_PG11        98
-#define IRQ_PG12        99
-#define IRQ_PG13        100
-#define IRQ_PG14        101
-#define IRQ_PG15        102
-
-#define IRQ_PH0         103
-#define IRQ_PH1         104
-#define IRQ_PH2         105
-#define IRQ_PH3         106
-#define IRQ_PH4         107
-#define IRQ_PH5         108
-#define IRQ_PH6         109
-#define IRQ_PH7         110
-#define IRQ_PH8         111
-#define IRQ_PH9         112
-#define IRQ_PH10        113
-#define IRQ_PH11        114
-#define IRQ_PH12        115
-#define IRQ_PH13        116
-#define IRQ_PH14        117
-#define IRQ_PH15        118
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define IRQ_MAC_PHYINT          119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT          120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT         121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT         122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET         123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR        124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR        125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE         126 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS    (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS         (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
+#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
+
+#define IRQ_PF0                 71
+#define IRQ_PF1                 72
+#define IRQ_PF2                 73
+#define IRQ_PF3                 74
+#define IRQ_PF4                 75
+#define IRQ_PF5                 76
+#define IRQ_PF6                 77
+#define IRQ_PF7                 78
+#define IRQ_PF8                 79
+#define IRQ_PF9                 80
+#define IRQ_PF10                81
+#define IRQ_PF11                82
+#define IRQ_PF12                83
+#define IRQ_PF13                84
+#define IRQ_PF14                85
+#define IRQ_PF15                86
+
+#define IRQ_PG0                 87
+#define IRQ_PG1                 88
+#define IRQ_PG2                 89
+#define IRQ_PG3                 90
+#define IRQ_PG4                 91
+#define IRQ_PG5                 92
+#define IRQ_PG6                 93
+#define IRQ_PG7                 94
+#define IRQ_PG8                 95
+#define IRQ_PG9                 96
+#define IRQ_PG10                97
+#define IRQ_PG11                98
+#define IRQ_PG12                99
+#define IRQ_PG13                100
+#define IRQ_PG14                101
+#define IRQ_PG15                102
+
+#define IRQ_PH0                 103
+#define IRQ_PH1                 104
+#define IRQ_PH2                 105
+#define IRQ_PH3                 106
+#define IRQ_PH4                 107
+#define IRQ_PH5                 108
+#define IRQ_PH6                 109
+#define IRQ_PH7                 110
+#define IRQ_PH8                 111
+#define IRQ_PH9                 112
+#define IRQ_PH10                113
+#define IRQ_PH11                114
+#define IRQ_PH12                115
+#define IRQ_PH13                116
+#define IRQ_PH14                117
+#define IRQ_PH15                118
+
+#define GPIO_IRQ_BASE           IRQ_PF0
+
+#define IRQ_MAC_PHYINT          119     /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT          120     /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT         121     /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT         122     /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET         123     /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR        124     /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR        125     /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE         126     /* Station Mgt. Transfer Done Interrupt */
+
+#define NR_MACH_IRQS            (IRQ_MAC_STMDONE + 1)
 
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS      0
 #define IRQ_DMA0_ERROR_POS      4
-#define IRQ_DMAR0_BLK_POS       8
-#define IRQ_DMAR1_BLK_POS       12
-#define IRQ_DMAR0_OVR_POS       16
-#define IRQ_DMAR1_OVR_POS       20
-#define IRQ_PPI_ERROR_POS       24
-#define IRQ_MAC_ERROR_POS       28
+#define IRQ_DMAR0_BLK_POS       8
+#define IRQ_DMAR1_BLK_POS       12
+#define IRQ_DMAR0_OVR_POS       16
+#define IRQ_DMAR1_OVR_POS       20
+#define IRQ_PPI_ERROR_POS       24
+#define IRQ_MAC_ERROR_POS       28
 
 /* IAR1 BIT FIELDS */
 #define IRQ_SPORT0_ERROR_POS    0
 #define IRQ_SPORT1_ERROR_POS    4
-#define IRQ_UART0_ERROR_POS     16
-#define IRQ_UART1_ERROR_POS     20
-#define IRQ_RTC_POS             24
-#define IRQ_PPI_POS             28
+#define IRQ_UART0_ERROR_POS     16
+#define IRQ_UART1_ERROR_POS     20
+#define IRQ_RTC_POS             24
+#define IRQ_PPI_POS             28
 
 /* IAR2 BIT FIELDS */
 #define IRQ_SPORT0_RX_POS       0
 #define IRQ_SPORT0_TX_POS       4
 #define IRQ_SPORT1_RX_POS       8
 #define IRQ_SPORT1_TX_POS       12
-#define IRQ_TWI_POS             16
-#define IRQ_SPI_POS             20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
+#define IRQ_TWI_POS             16
+#define IRQ_SPI_POS             20
+#define IRQ_UART0_RX_POS        24
+#define IRQ_UART0_TX_POS        28
 
 /* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS        0
-#define IRQ_UART1_TX_POS        4
-#define IRQ_OPTSEC_POS          8
-#define IRQ_CNT_POS             12
-#define IRQ_MAC_RX_POS          16
+#define IRQ_UART1_RX_POS        0
+#define IRQ_UART1_TX_POS        4
+#define IRQ_OPTSEC_POS          8
+#define IRQ_CNT_POS             12
+#define IRQ_MAC_RX_POS          16
 #define IRQ_PORTH_INTA_POS      20
-#define IRQ_MAC_TX_POS          24
+#define IRQ_MAC_TX_POS          24
 #define IRQ_PORTH_INTB_POS      28
 
 /* IAR4 BIT FIELDS */
@@ -224,21 +184,21 @@
 /* IAR5 BIT FIELDS */
 #define IRQ_PORTG_INTA_POS      0
 #define IRQ_PORTG_INTB_POS      4
-#define IRQ_MEM_DMA0_POS        8
-#define IRQ_MEM_DMA1_POS        12
-#define IRQ_WATCH_POS           16
+#define IRQ_MEM_DMA0_POS        8
+#define IRQ_MEM_DMA1_POS        12
+#define IRQ_WATCH_POS           16
 #define IRQ_PORTF_INTA_POS      20
 #define IRQ_PORTF_INTB_POS      24
-#define IRQ_SPI_ERROR_POS       28
+#define IRQ_SPI_ERROR_POS       28
 
 /* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS       0
-#define IRQ_HDMA_ERROR_POS      4
-#define IRQ_HDMA_POS            8
-#define IRQ_USB_EINT_POS        12
-#define IRQ_USB_INT0_POS        16
-#define IRQ_USB_INT1_POS        20
-#define IRQ_USB_INT2_POS        24
-#define IRQ_USB_DMA_POS         28
-
-#endif                          /* _BF527_IRQ_H_ */
+#define IRQ_NFC_ERROR_POS       0
+#define IRQ_HDMA_ERROR_POS      4
+#define IRQ_HDMA_POS            8
+#define IRQ_USB_EINT_POS        12
+#define IRQ_USB_INT0_POS        16
+#define IRQ_USB_INT1_POS        20
+#define IRQ_USB_INT2_POS        24
+#define IRQ_USB_DMA_POS         28
+
+#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 78f872187918..72aa59440f82 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ *  - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -206,6 +206,10 @@
 #define ANOMALY_05000443 (1)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
 /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
 #define ANOMALY_05000473 (1)
 /* Possible Lockup Condition whem Modifying PLL from External Memory */
@@ -351,12 +355,14 @@
 #define ANOMALY_05000362 (1)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000430 (0)
 #define ANOMALY_05000432 (0)
 #define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000456 (0)
@@ -364,6 +370,7 @@
 #define ANOMALY_05000465 (0)
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index 45dcaa4f3e41..000000000000
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-# define CONFIG_SERIAL_BFIN_CTSRTS
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-        int             uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        IRQ_UART0_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        }
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 1f7e9765d954..709733754142 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -7,83 +7,36 @@
 #ifndef _BF533_IRQ_H_
 #define _BF533_IRQ_H_
 
-/*
- * Interrupt source definitions
-             Event Source    Core Event Name
-Core        Emulation               **
- Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-            PLL Wakeup Interrupt    IVG7        7
-            DMA Error (generic)     IVG7        8
-            PPI Error Interrupt     IVG7        9
-            SPORT0 Error Interrupt  IVG7        10
-            SPORT1 Error Interrupt  IVG7        11
-            SPI Error Interrupt     IVG7        12
-            UART Error Interrupt    IVG7        13
-            RTC Interrupt           IVG8        14
-            DMA0 Interrupt (PPI)    IVG8        15
-            DMA1 (SPORT0 RX)        IVG9        16
-            DMA2 (SPORT0 TX)        IVG9        17
-            DMA3 (SPORT1 RX)        IVG9        18
-            DMA4 (SPORT1 TX)        IVG9        19
-            DMA5 (PPI)              IVG10       20
-            DMA6 (UART RX)          IVG10       21
-            DMA7 (UART TX)          IVG10       22
-            Timer0                  IVG11       23
-            Timer1                  IVG11       24
-            Timer2                  IVG11       25
-            PF Interrupt A          IVG12       26
-            PF Interrupt B          IVG12       27
-            DMA8/9 Interrupt        IVG13       28
-            DMA10/11 Interrupt      IVG13       29
-            Watchdog Timer          IVG13       30
+#include <mach-common/irq.h>
 
-            Softirq                 IVG14       31
-            System Call    --
-                 (lowest priority)  IVG15       32 *
- */
-#define SYS_IRQS        31
-#define NR_PERI_INTS    24
+#define NR_PERI_INTS            24
 
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /*Emulation */
-#define IRQ_RST                 1       /*reset */
-#define IRQ_NMI                 2       /*Non Maskable */
-#define IRQ_EVX                 3       /*Exception */
-#define IRQ_UNUSED              4       /*- unused interrupt*/
-#define IRQ_HWERR               5       /*Hardware Error */
-#define IRQ_CORETMR             6       /*Core timer */
+#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR           BFIN_IRQ(1)     /* DMA Error (general) */
+#define IRQ_PPI_ERROR           BFIN_IRQ(2)     /* PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR           BFIN_IRQ(5)     /* SPI Error Interrupt */
+#define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART Error Interrupt */
+#define IRQ_RTC                 BFIN_IRQ(7)     /* RTC Interrupt */
+#define IRQ_PPI                 BFIN_IRQ(8)     /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI                 BFIN_IRQ(13)    /* DMA5 Interrupt (SPI) */
+#define IRQ_UART0_RX            BFIN_IRQ(14)    /* DMA6 Interrupt (UART RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(15)    /* DMA7 Interrupt (UART TX) */
+#define IRQ_TIMER0              BFIN_IRQ(16)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(17)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(18)    /* Timer 2 */
+#define IRQ_PROG_INTA           BFIN_IRQ(19)    /* Programmable Flags A (8) */
+#define IRQ_PROG_INTB           BFIN_IRQ(20)    /* Programmable Flags B (8) */
+#define IRQ_MEM_DMA0            BFIN_IRQ(21)    /* DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1            BFIN_IRQ(22)    /* DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_WATCH               BFIN_IRQ(23)    /* Watch Dog Timer */
 
-#define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR           8       /*DMA Error (general) */
-#define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR         13      /*UART Error Interrupt */
-#define IRQ_RTC                 14      /*RTC Interrupt */
-#define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX            21      /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX            22      /*DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0              23      /*Timer 0 */
-#define IRQ_TIMER1              24      /*Timer 1 */
-#define IRQ_TIMER2              25      /*Timer 2 */
-#define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
-#define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
-#define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH               30      /*Watch Dog Timer */
+#define SYS_IRQS                31
 
 #define IRQ_PF0                 33
 #define IRQ_PF1                 34
@@ -105,46 +58,35 @@ Core        Emulation               **
 #define GPIO_IRQ_BASE           IRQ_PF0
 
 #define NR_MACH_IRQS            (IRQ_PF15 + 1)
-#define NR_IRQS                 (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7                    7
-#define IVG8                    8
-#define IVG9                    9
-#define IVG10                   10
-#define IVG11                   11
-#define IVG12                   12
-#define IVG13                   13
-#define IVG14                   14
-#define IVG15                   15
 
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_POS                   28
-#define UART_ERROR_POS                  24
-#define SPORT1_ERROR_POS                20
-#define SPI_ERROR_POS                   16
-#define SPORT0_ERROR_POS                12
-#define PPI_ERROR_POS                   8
-#define DMA_ERROR_POS                   4
-#define PLLWAKE_ERROR_POS               0
+/* IAR0 BIT FIELDS */
+#define RTC_ERROR_POS           28
+#define UART_ERROR_POS          24
+#define SPORT1_ERROR_POS        20
+#define SPI_ERROR_POS           16
+#define SPORT0_ERROR_POS        12
+#define PPI_ERROR_POS           8
+#define DMA_ERROR_POS           4
+#define PLLWAKE_ERROR_POS       0
 
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_POS                 28
-#define DMA6_UARTRX_POS                 24
-#define DMA5_SPI_POS                    20
-#define DMA4_SPORT1TX_POS               16
-#define DMA3_SPORT1RX_POS               12
-#define DMA2_SPORT0TX_POS               8
-#define DMA1_SPORT0RX_POS               4
-#define DMA0_PPI_POS                    0
+/* IAR1 BIT FIELDS */
+#define DMA7_UARTTX_POS         28
+#define DMA6_UARTRX_POS         24
+#define DMA5_SPI_POS            20
+#define DMA4_SPORT1TX_POS       16
+#define DMA3_SPORT1RX_POS       12
+#define DMA2_SPORT0TX_POS       8
+#define DMA1_SPORT0RX_POS       4
+#define DMA0_PPI_POS            0
 
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_POS                     28
-#define MEMDMA1_POS                     24
-#define MEMDMA0_POS                     20
-#define PFB_POS                         16
-#define PFA_POS                         12
-#define TIMER2_POS                      8
-#define TIMER1_POS                      4
-#define TIMER0_POS                      0
+/* IAR2 BIT FIELDS */
+#define WDTIMER_POS             28
+#define MEMDMA1_POS             24
+#define MEMDMA0_POS             20
+#define PFB_POS                 16
+#define PFA_POS                 12
+#define TIMER2_POS              8
+#define TIMER1_POS              4
+#define TIMER0_POS              0
 
-#endif                          /* _BF533_IRQ_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3fa335405b31..76db1d483173 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -35,6 +35,7 @@
 #include <asm/reboot.h>
 #include <asm/portmux.h>
 #include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
 #ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
 #include <linux/regulator/fixed.h>
 #endif
@@ -381,7 +382,6 @@ static struct platform_device net2272_bfin_device = {
 #endif
 
 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-#ifdef CONFIG_MTD_PARTITIONS
 const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
 
 static struct mtd_partition bfin_plat_nand_partitions[] = {
@@ -395,7 +395,6 @@ static struct mtd_partition bfin_plat_nand_partitions[] = {
                 .offset = MTDPART_OFS_APPEND,
         },
 };
-#endif
 
 #define BFIN_NAND_PLAT_CLE 2
 #define BFIN_NAND_PLAT_ALE 1
@@ -422,11 +421,9 @@ static struct platform_nand_data bfin_plat_nand_data = {
         .chip = {
                 .nr_chips = 1,
                 .chip_delay = 30,
-#ifdef CONFIG_MTD_PARTITIONS
                 .part_probe_types = part_probes,
                 .partitions = bfin_plat_nand_partitions,
                 .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
-#endif
         },
         .ctrl = {
                 .cmd_ctrl  = bfin_plat_nand_cmd_ctrl,
@@ -2585,27 +2582,103 @@ static struct platform_device bfin_dpmc = {
         },
 };
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#define SPORT_REQ(x) \
+        [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+                P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+        SPORT_REQ(0),
+        SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+        {
+                .pin_req = &bfin_snd_pin[0][0],
+        },
+        {
+                .pin_req = &bfin_snd_pin[1][0],
+        },
+};
+
+#define BFIN_SND_RES(x) \
+        [x] = { \
+                { \
+                        .start = SPORT##x##_TCR1, \
+                        .end = SPORT##x##_TCR1, \
+                        .flags = IORESOURCE_MEM \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_RX, \
+                        .end = CH_SPORT##x##_RX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_TX, \
+                        .end = CH_SPORT##x##_TX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = IRQ_SPORT##x##_ERROR, \
+                        .end = IRQ_SPORT##x##_ERROR, \
+                        .flags = IORESOURCE_IRQ, \
+                } \
+        }
+
+static struct resource bfin_snd_resources[][4] = {
+        BFIN_SND_RES(0),
+        BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+        .name = "bfin-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+        .name = "ad73311",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
 static struct platform_device bfin_i2s = {
         .name = "bfin-i2s",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
 static struct platform_device bfin_tdm = {
         .name = "bfin-tdm",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
@@ -2796,17 +2869,28 @@ static struct platform_device *stamp_devices[] __initdata = {
         &stamp_flash_device,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+        &bfin_ad73311_codec_device,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
         &bfin_i2s,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
         &bfin_tdm,
 #endif
 
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
         &bfin_ac97,
 #endif
+
 #if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
 #if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
         defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 43df6afd22ad..7f8e5a9f5db6 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -160,12 +160,16 @@
 #define ANOMALY_05000443 (1)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
 /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
 #define ANOMALY_05000473 (1)
 /* Possible Lockup Condition whem Modifying PLL from External Memory */
 #define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
+/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
+#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
 #define ANOMALY_05000481 (1)
 /* IFLUSH sucks at life */
@@ -204,6 +208,7 @@
 #define ANOMALY_05000363 (0)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -211,6 +216,7 @@
 #define ANOMALY_05000430 (0)
 #define ANOMALY_05000432 (0)
 #define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000456 (0)
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index 3e955dba8951..000000000000
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-        int             uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int     uart_cts_pin;
-        int     uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        IRQ_UART0_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        IRQ_UART1_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        CONFIG_UART1_CTS_PIN,
-        CONFIG_UART1_RTS_PIN,
-#endif
-        },
-#endif
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 1a6d617c5fcf..b6ed8235bda4 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -7,193 +7,178 @@
 #ifndef _BF537_IRQ_H_
 #define _BF537_IRQ_H_
 
-/*
- * Interrupt source definitions
- *            Event Source    Core Event Name
- * Core       Emulation               **
- * Events         (highest priority)  EMU         0
- *            Reset                   RST         1
- *            NMI                     NMI         2
- *            Exception               EVX         3
- *            Reserved                --          4
- *            Hardware Error          IVHW        5
- *            Core Timer              IVTMR       6
- *  .....
- *
- *            Softirq                 IVG14
- *            System Call    --
- *               (lowest priority)    IVG15
- */
-
-#define SYS_IRQS        39
-#define NR_PERI_INTS    32
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU             0   /*Emulation */
-#define IRQ_RST             1   /*reset */
-#define IRQ_NMI             2   /*Non Maskable */
-#define IRQ_EVX             3   /*Exception */
-#define IRQ_UNUSED          4   /*- unused interrupt*/
-#define IRQ_HWERR           5   /*Hardware Error */
-#define IRQ_CORETMR         6   /*Core timer */
-
-#define IRQ_PLL_WAKEUP      7   /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR       8   /*DMA Error (general) */
-#define IRQ_GENERIC_ERROR   9   /*GENERIC Error Interrupt */
-#define IRQ_RTC             10  /*RTC Interrupt */
-#define IRQ_PPI             11  /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX       12  /*DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX       13  /*DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX       14  /*DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX       15  /*DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI             16  /*TWI Interrupt */
-#define IRQ_SPI             17  /*DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX        18  /*DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX        19  /*DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX        20  /*DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX        21  /*DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX          22  /*CAN Receive Interrupt */
-#define IRQ_CAN_TX          23  /*CAN Transmit Interrupt */
-#define IRQ_MAC_RX          24  /*DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX          25  /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TIMER0            26        /*Timer 0 */
-#define IRQ_TIMER1            27        /*Timer 1 */
-#define IRQ_TIMER2            28        /*Timer 2 */
-#define IRQ_TIMER3            29        /*Timer 3 */
-#define IRQ_TIMER4            30        /*Timer 4 */
-#define IRQ_TIMER5            31        /*Timer 5 */
-#define IRQ_TIMER6            32        /*Timer 6 */
-#define IRQ_TIMER7            33        /*Timer 7 */
-#define IRQ_PROG_INTA       34  /* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
-#define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1        37  /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB         38        /* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH           38  /*Watch Dog Timer */
-
-#define IRQ_PPI_ERROR       42  /*PPI Error Interrupt */
-#define IRQ_CAN_ERROR       43  /*CAN Error Interrupt */
-#define IRQ_MAC_ERROR       44  /*MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR    45  /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR    46  /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR       47  /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR     48  /*UART Error Interrupt */
-#define IRQ_UART1_ERROR     49  /*UART Error Interrupt */
-
-#define IRQ_PF0         50
-#define IRQ_PF1         51
-#define IRQ_PF2         52
-#define IRQ_PF3         53
-#define IRQ_PF4         54
-#define IRQ_PF5         55
-#define IRQ_PF6         56
-#define IRQ_PF7         57
-#define IRQ_PF8         58
-#define IRQ_PF9         59
-#define IRQ_PF10        60
-#define IRQ_PF11        61
-#define IRQ_PF12        62
-#define IRQ_PF13        63
-#define IRQ_PF14        64
-#define IRQ_PF15        65
-
-#define IRQ_PG0         66
-#define IRQ_PG1         67
-#define IRQ_PG2         68
-#define IRQ_PG3         69
-#define IRQ_PG4         70
-#define IRQ_PG5         71
-#define IRQ_PG6         72
-#define IRQ_PG7         73
-#define IRQ_PG8         74
-#define IRQ_PG9         75
-#define IRQ_PG10        76
-#define IRQ_PG11        77
-#define IRQ_PG12        78
-#define IRQ_PG13        79
-#define IRQ_PG14        80
-#define IRQ_PG15        81
-
-#define IRQ_PH0         82
-#define IRQ_PH1         83
-#define IRQ_PH2         84
-#define IRQ_PH3         85
-#define IRQ_PH4         86
-#define IRQ_PH5         87
-#define IRQ_PH6         88
-#define IRQ_PH7         89
-#define IRQ_PH8         90
-#define IRQ_PH9         91
-#define IRQ_PH10        92
-#define IRQ_PH11        93
-#define IRQ_PH12        94
-#define IRQ_PH13        95
-#define IRQ_PH14        96
-#define IRQ_PH15        97
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define IRQ_MAC_PHYINT          98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT          99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT         100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT         101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET         102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR        103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR        104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE         105 /* Station Mgt. Transfer Done Interrupt */
-
-#define NR_MACH_IRQS    (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS         (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS*/
-#define IRQ_PLL_WAKEUP_POS  0
-#define IRQ_DMA_ERROR_POS   4
-#define IRQ_ERROR_POS       8
-#define IRQ_RTC_POS         12
-#define IRQ_PPI_POS         16
-#define IRQ_SPORT0_RX_POS   20
-#define IRQ_SPORT0_TX_POS   24
-#define IRQ_SPORT1_RX_POS   28
-
-/* IAR1 BIT FIELDS*/
-#define IRQ_SPORT1_TX_POS   0
-#define IRQ_TWI_POS         4
-#define IRQ_SPI_POS         8
-#define IRQ_UART0_RX_POS    12
-#define IRQ_UART0_TX_POS    16
-#define IRQ_UART1_RX_POS    20
-#define IRQ_UART1_TX_POS    24
-#define IRQ_CAN_RX_POS      28
-
-/* IAR2 BIT FIELDS*/
-#define IRQ_CAN_TX_POS      0
-#define IRQ_MAC_RX_POS      4
-#define IRQ_MAC_TX_POS      8
-#define IRQ_TIMER0_POS        12
-#define IRQ_TIMER1_POS        16
-#define IRQ_TIMER2_POS        20
-#define IRQ_TIMER3_POS        24
-#define IRQ_TIMER4_POS        28
-
-/* IAR3 BIT FIELDS*/
-#define IRQ_TIMER5_POS        0
-#define IRQ_TIMER6_POS        4
-#define IRQ_TIMER7_POS        8
-#define IRQ_PROG_INTA_POS   12
-#define IRQ_PORTG_INTB_POS   16
-#define IRQ_MEM_DMA0_POS    20
-#define IRQ_MEM_DMA1_POS    24
-#define IRQ_WATCH_POS       28
-
-#endif                          /* _BF537_IRQ_H_ */
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS            32
+
+#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR           BFIN_IRQ(1)     /* DMA Error (general) */
+#define IRQ_GENERIC_ERROR       BFIN_IRQ(2)     /* GENERIC Error Interrupt */
+#define IRQ_RTC                 BFIN_IRQ(3)     /* RTC Interrupt */
+#define IRQ_PPI                 BFIN_IRQ(4)     /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX           BFIN_IRQ(5)     /* DMA3 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX           BFIN_IRQ(6)     /* DMA4 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX           BFIN_IRQ(7)     /* DMA5 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX           BFIN_IRQ(8)     /* DMA6 Interrupt (SPORT1 TX) */
+#define IRQ_TWI                 BFIN_IRQ(9)     /* TWI Interrupt */
+#define IRQ_SPI                 BFIN_IRQ(10)    /* DMA7 Interrupt (SPI) */
+#define IRQ_UART0_RX            BFIN_IRQ(11)    /* DMA8 Interrupt (UART0 RX) */
+#define IRQ_UART0_TX            BFIN_IRQ(12)    /* DMA9 Interrupt (UART0 TX) */
+#define IRQ_UART1_RX            BFIN_IRQ(13)    /* DMA10 Interrupt (UART1 RX) */
+#define IRQ_UART1_TX            BFIN_IRQ(14)    /* DMA11 Interrupt (UART1 TX) */
+#define IRQ_CAN_RX              BFIN_IRQ(15)    /* CAN Receive Interrupt */
+#define IRQ_CAN_TX              BFIN_IRQ(16)    /* CAN Transmit Interrupt */
+#define IRQ_PH_INTA_MAC_RX      BFIN_IRQ(17)    /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PH_INTB_MAC_TX      BFIN_IRQ(18)    /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
+#define IRQ_TIMER0              BFIN_IRQ(19)    /* Timer 0 */
+#define IRQ_TIMER1              BFIN_IRQ(20)    /* Timer 1 */
+#define IRQ_TIMER2              BFIN_IRQ(21)    /* Timer 2 */
+#define IRQ_TIMER3              BFIN_IRQ(22)    /* Timer 3 */
+#define IRQ_TIMER4              BFIN_IRQ(23)    /* Timer 4 */
+#define IRQ_TIMER5              BFIN_IRQ(24)    /* Timer 5 */
+#define IRQ_TIMER6              BFIN_IRQ(25)    /* Timer 6 */
+#define IRQ_TIMER7              BFIN_IRQ(26)    /* Timer 7 */
+#define IRQ_PF_INTA_PG_INTA     BFIN_IRQ(27)    /* Ports F&G Interrupt A */
+#define IRQ_PORTG_INTB          BFIN_IRQ(28)    /* Port G Interrupt B */
+#define IRQ_MEM_DMA0            BFIN_IRQ(29)    /* (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1            BFIN_IRQ(30)    /* (Memory DMA Stream 1) */
+#define IRQ_PF_INTB_WATCH       BFIN_IRQ(31)    /* Watchdog & Port F Interrupt B */
+
+#define SYS_IRQS                39
+
+#define IRQ_PPI_ERROR           42      /* PPI Error Interrupt */
+#define IRQ_CAN_ERROR           43      /* CAN Error Interrupt */
+#define IRQ_MAC_ERROR           44      /* MAC Status/Error Interrupt */
+#define IRQ_SPORT0_ERROR        45      /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR        46      /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR           47      /* SPI Error Interrupt */
+#define IRQ_UART0_ERROR         48      /* UART Error Interrupt */
+#define IRQ_UART1_ERROR         49      /* UART Error Interrupt */
+
+#define IRQ_PF0                 50
+#define IRQ_PF1                 51
+#define IRQ_PF2                 52
+#define IRQ_PF3                 53
+#define IRQ_PF4                 54
+#define IRQ_PF5                 55
+#define IRQ_PF6                 56
+#define IRQ_PF7                 57
+#define IRQ_PF8                 58
+#define IRQ_PF9                 59
+#define IRQ_PF10                60
+#define IRQ_PF11                61
+#define IRQ_PF12                62
+#define IRQ_PF13                63
+#define IRQ_PF14                64
+#define IRQ_PF15                65
+
+#define IRQ_PG0                 66
+#define IRQ_PG1                 67
+#define IRQ_PG2                 68
+#define IRQ_PG3                 69
+#define IRQ_PG4                 70
+#define IRQ_PG5                 71
+#define IRQ_PG6                 72
+#define IRQ_PG7                 73
+#define IRQ_PG8                 74
+#define IRQ_PG9                 75
+#define IRQ_PG10                76
+#define IRQ_PG11                77
+#define IRQ_PG12                78
+#define IRQ_PG13                79
+#define IRQ_PG14                80
+#define IRQ_PG15                81
+
+#define IRQ_PH0                 82
+#define IRQ_PH1                 83
+#define IRQ_PH2                 84
+#define IRQ_PH3                 85
+#define IRQ_PH4                 86
+#define IRQ_PH5                 87
+#define IRQ_PH6                 88
+#define IRQ_PH7                 89
+#define IRQ_PH8                 90
+#define IRQ_PH9                 91
+#define IRQ_PH10                92
+#define IRQ_PH11                93
+#define IRQ_PH12                94
+#define IRQ_PH13                95
+#define IRQ_PH14                96
+#define IRQ_PH15                97
+
+#define GPIO_IRQ_BASE           IRQ_PF0
+
+#define IRQ_MAC_PHYINT          98      /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT          99      /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT         100     /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT         101     /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET         102     /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR        103     /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR        104     /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE         105     /* Station Mgt. Transfer Done Interrupt */
+
+#define IRQ_MAC_RX              106     /* DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PORTH_INTA          107     /* Port H Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_MAC_TX              108     /* DMA2 Interrupt (Ethernet TX) */
+#define IRQ_PORTH_INTB          109     /* Port H Interrupt B */
+#else
+#define IRQ_MAC_TX              IRQ_PH_INTB_MAC_TX
+#endif
+
+#define IRQ_PORTF_INTA          110     /* Port F Interrupt A */
+#define IRQ_PORTG_INTA          111     /* Port G Interrupt A */
+
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_WATCH               112     /* Watchdog Timer */
+#define IRQ_PORTF_INTB          113     /* Port F Interrupt B */
+#else
+#define IRQ_WATCH               IRQ_PF_INTB_WATCH
+#endif
+
+#define NR_MACH_IRQS            (113 + 1)
+
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS      0
+#define IRQ_DMA_ERROR_POS       4
+#define IRQ_ERROR_POS           8
+#define IRQ_RTC_POS             12
+#define IRQ_PPI_POS             16
+#define IRQ_SPORT0_RX_POS       20
+#define IRQ_SPORT0_TX_POS       24
+#define IRQ_SPORT1_RX_POS       28
+
+/* IAR1 BIT FIELDS */
+#define IRQ_SPORT1_TX_POS       0
+#define IRQ_TWI_POS             4
+#define IRQ_SPI_POS             8
+#define IRQ_UART0_RX_POS        12
+#define IRQ_UART0_TX_POS        16
+#define IRQ_UART1_RX_POS        20
+#define IRQ_UART1_TX_POS        24
+#define IRQ_CAN_RX_POS          28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_CAN_TX_POS          0
+#define IRQ_MAC_RX_POS          4
+#define IRQ_MAC_TX_POS          8
+#define IRQ_TIMER0_POS          12
+#define IRQ_TIMER1_POS          16
+#define IRQ_TIMER2_POS          20
+#define IRQ_TIMER3_POS          24
+#define IRQ_TIMER4_POS          28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_TIMER5_POS          0
+#define IRQ_TIMER6_POS          4
+#define IRQ_TIMER7_POS          8
+#define IRQ_PROG_INTA_POS       12
+#define IRQ_PORTG_INTB_POS      16
+#define IRQ_MEM_DMA0_POS        20
+#define IRQ_MEM_DMA1_POS        24
+#define IRQ_WATCH_POS           28
+
+#define init_mach_irq init_mach_irq
+
+#endif
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index f6500622b35d..2137a209a22b 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -10,6 +10,13 @@
 #include <linux/irq.h>
 #include <asm/blackfin.h>
 
+#include <asm/irq_handler.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_sport.h>
+#include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
+#include <asm/dpmc.h>
+
 void __init program_IAR(void)
 {
         /* Program the IAR0 Register with the configured priority */
@@ -51,3 +58,159 @@ void __init program_IAR(void)
 
         SSYNC();
 }
+
+#define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE)  /* SPI_STAT */
+#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORT_STAT */
+#define PPI_ERR_MASK   (0xFFFF & ~FLD)  /* PPI_STATUS */
+#define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)  /* EMAC_SYSTAT */
+#define UART_ERR_MASK  (0x6)    /* UART_IIR */
+#define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)       /* CAN_GIF */
+
+static int error_int_mask;
+
+static void bf537_generic_error_mask_irq(struct irq_data *d)
+{
+        error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
+        if (!error_int_mask)
+                bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
+}
+
+static void bf537_generic_error_unmask_irq(struct irq_data *d)
+{
+        bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
+        error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
+}
+
+static struct irq_chip bf537_generic_error_irqchip = {
+        .name = "ERROR",
+        .irq_ack = bfin_ack_noop,
+        .irq_mask_ack = bf537_generic_error_mask_irq,
+        .irq_mask = bf537_generic_error_mask_irq,
+        .irq_unmask = bf537_generic_error_unmask_irq,
+};
+
+static void bf537_demux_error_irq(unsigned int int_err_irq,
+                                  struct irq_desc *inta_desc)
+{
+        int irq = 0;
+
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+        if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
+                irq = IRQ_MAC_ERROR;
+        else
+#endif
+        if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
+                irq = IRQ_SPORT0_ERROR;
+        else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
+                irq = IRQ_SPORT1_ERROR;
+        else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
+                irq = IRQ_PPI_ERROR;
+        else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
+                irq = IRQ_CAN_ERROR;
+        else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
+                irq = IRQ_SPI_ERROR;
+        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
+                irq = IRQ_UART0_ERROR;
+        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
+                irq = IRQ_UART1_ERROR;
+
+        if (irq) {
+                if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
+                        bfin_handle_irq(irq);
+                else {
+
+                        switch (irq) {
+                        case IRQ_PPI_ERROR:
+                                bfin_write_PPI_STATUS(PPI_ERR_MASK);
+                                break;
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+                        case IRQ_MAC_ERROR:
+                                bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
+                                break;
+#endif
+                        case IRQ_SPORT0_ERROR:
+                                bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
+                                break;
+
+                        case IRQ_SPORT1_ERROR:
+                                bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
+                                break;
+
+                        case IRQ_CAN_ERROR:
+                                bfin_write_CAN_GIS(CAN_ERR_MASK);
+                                break;
+
+                        case IRQ_SPI_ERROR:
+                                bfin_write_SPI_STAT(SPI_ERR_MASK);
+                                break;
+
+                        default:
+                                break;
+                        }
+
+                        pr_debug("IRQ %d:"
+                                 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
+                                 irq);
+                }
+        } else
+                pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
+                       __func__);
+
+}
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+static int mac_rx_int_mask;
+
+static void bf537_mac_rx_mask_irq(struct irq_data *d)
+{
+        mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
+        if (!mac_rx_int_mask)
+                bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
+}
+
+static void bf537_mac_rx_unmask_irq(struct irq_data *d)
+{
+        bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
+        mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
+}
+
+static struct irq_chip bf537_mac_rx_irqchip = {
+        .name = "ERROR",
+        .irq_ack = bfin_ack_noop,
+        .irq_mask_ack = bf537_mac_rx_mask_irq,
+        .irq_mask = bf537_mac_rx_mask_irq,
+        .irq_unmask = bf537_mac_rx_unmask_irq,
+};
+
+static void bf537_demux_mac_rx_irq(unsigned int int_irq,
+                                   struct irq_desc *desc)
+{
+        if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
+                bfin_handle_irq(IRQ_MAC_RX);
+        else
+                bfin_demux_gpio_irq(int_irq, desc);
+}
+#endif
+
+void __init init_mach_irq(void)
+{
+        int irq;
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+        /* Clear EMAC Interrupt Status bits so we can demux it later */
+        bfin_write_EMAC_SYSTAT(-1);
+#endif
+
+        irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
+        for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
+                irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
+                                         handle_level_irq);
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+        irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
+        irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
+        irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
+
+        irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
+#endif
+}
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 8774b481c78e..55e7d0712a94 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -5,14 +5,14 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- *  - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ *  - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ *  - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -179,6 +179,7 @@
 #define ANOMALY_05000363 (0)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
@@ -186,6 +187,7 @@
 #define ANOMALY_05000430 (0)
 #define ANOMALY_05000432 (0)
 #define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000456 (0)
@@ -193,6 +195,7 @@
 #define ANOMALY_05000465 (0)
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index beb502e9cb33..000000000000
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-        int             uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int     uart_cts_pin;
-        int     uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        IRQ_UART0_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        IRQ_UART1_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        CONFIG_UART1_CTS_PIN,
-        CONFIG_UART1_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART2_TX,
-        CH_UART2_RX,
-#endif
-#ifdef CONFIG_BFIN_UART2_CTSRTS
-        CONFIG_UART2_CTS_PIN,
-        CONFIG_UART2_RTS_PIN,
-#endif
-        },
-#endif
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 7a479d224dc7..07ca069d37cd 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -7,38 +7,9 @@
 #ifndef _BF538_IRQ_H_
 #define _BF538_IRQ_H_
 
-/*
- * Interrupt source definitions
-        Event Source    Core Event Name
-        Core        Emulation               **
-        Events         (highest priority)  EMU         0
-        Reset                   RST         1
-        NMI                     NMI         2
-        Exception               EVX         3
-        Reserved                --          4
-        Hardware Error          IVHW        5
-        Core Timer              IVTMR       6 *
-
-        .....
-
-         Software Interrupt 1    IVG14       31
-         Software Interrupt 2    --
-         (lowest priority)  IVG15       32 *
-*/
-
-#define NR_PERI_INTS    (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS            (2 * 32)
 
 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
@@ -91,37 +62,26 @@
 
 #define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
 
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define NR_MACH_IRQS    (IRQ_PF15 + 1)
-#define NR_IRQS         (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
+#define IRQ_PF0                 71
+#define IRQ_PF1                 72
+#define IRQ_PF2                 73
+#define IRQ_PF3                 74
+#define IRQ_PF4                 75
+#define IRQ_PF5                 76
+#define IRQ_PF6                 77
+#define IRQ_PF7                 78
+#define IRQ_PF8                 79
+#define IRQ_PF9                 80
+#define IRQ_PF10                81
+#define IRQ_PF11                82
+#define IRQ_PF12                83
+#define IRQ_PF13                84
+#define IRQ_PF14                85
+#define IRQ_PF15                86
+
+#define GPIO_IRQ_BASE           IRQ_PF0
+
+#define NR_MACH_IRQS            (IRQ_PF15 + 1)
 
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS      0
@@ -184,4 +144,5 @@
 #define IRQ_CAN_TX_POS          0
 #define IRQ_MEM1_DMA0_POS       4
 #define IRQ_MEM1_DMA1_POS       8
-#endif                          /* _BF538_IRQ_H_ */
+
+#endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 93e19a54a880..311bf9970fe7 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -22,6 +22,7 @@
 #include <asm/gpio.h>
 #include <asm/nand.h>
 #include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
 #include <asm/portmux.h>
 #include <asm/bfin_sdh.h>
 #include <mach/bf54x_keys.h>
@@ -956,7 +957,15 @@ static struct mtd_partition ezkit_partitions[] = {
                 .offset     = MTDPART_OFS_APPEND,
         }, {
                 .name       = "file system(nor)",
-                .size       = MTDPART_SIZ_FULL,
+                .size       = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "config(nor)",
+                .size       = 0x8000 * 3,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "u-boot env(nor)",
+                .size       = 0x8000,
                 .offset     = MTDPART_OFS_APPEND,
         }
 };
@@ -1312,27 +1321,110 @@ static struct platform_device bfin_dpmc = {
         },
 };
 
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#define SPORT_REQ(x) \
+        [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+                P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+        SPORT_REQ(0),
+        SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+        {
+                .pin_req = &bfin_snd_pin[0][0],
+        },
+        {
+                .pin_req = &bfin_snd_pin[1][0],
+        },
+};
+
+#define BFIN_SND_RES(x) \
+        [x] = { \
+                { \
+                        .start = SPORT##x##_TCR1, \
+                        .end = SPORT##x##_TCR1, \
+                        .flags = IORESOURCE_MEM \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_RX, \
+                        .end = CH_SPORT##x##_RX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = CH_SPORT##x##_TX, \
+                        .end = CH_SPORT##x##_TX, \
+                        .flags = IORESOURCE_DMA, \
+                }, \
+                { \
+                        .start = IRQ_SPORT##x##_ERROR, \
+                        .end = IRQ_SPORT##x##_ERROR, \
+                        .flags = IORESOURCE_IRQ, \
+                } \
+        }
+
+static struct resource bfin_snd_resources[][4] = {
+        BFIN_SND_RES(0),
+        BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+        .name = "bfin-pcm-audio",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+        .name = "ad73311",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+static struct platform_device bfin_ad1980_codec_device = {
+        .name = "ad1980",
+        .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
 static struct platform_device bfin_i2s = {
         .name = "bfin-i2s",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
 static struct platform_device bfin_tdm = {
         .name = "bfin-tdm",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
 static struct platform_device bfin_ac97 = {
         .name = "bfin-ac97",
         .id = CONFIG_SND_BF5XX_SPORT_NUM,
-        /* TODO: add platform data here */
+        .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+        .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+        .dev = {
+                .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+        },
 };
 #endif
 
@@ -1450,6 +1542,16 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &ezkit_flash_device,
 #endif
 
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+        defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+        defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+        &bfin_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+        &bfin_ad1980_codec_device,
+#endif
+
 #if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s,
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index ffd0537295ac..9e70785bdde3 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ *  - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
 #define ANOMALY_05000481 (1)
 /* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
 #define ANOMALY_05000483 (1)
+/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
+#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
 /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
 #define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
 /* IFLUSH sucks at life */
@@ -274,6 +276,8 @@
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000432 (0)
 #define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
 #define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index 0d94edaaaa2e..000000000000
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
-        defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
-# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
-#endif
-
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-        int             uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        IRQ_UART0_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        0,
-        0,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        IRQ_UART1_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        GPIO_PE10,
-        GPIO_PE9,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-        IRQ_UART2_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART2_TX,
-        CH_UART2_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        0,
-        0,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-        {
-        0xFFC03100,
-        IRQ_UART3_RX,
-        IRQ_UART3_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART3_TX,
-        CH_UART3_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
-        GPIO_PB3,
-        GPIO_PB2,
-#endif
-        },
-#endif
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 1cbba115f96f..1fa41ec03f31 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -271,10 +271,10 @@
 #define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
 #define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
 #define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
+#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
 
 /* USB Endpoint 1 Control Registers */
 
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
 #define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
 #define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
 #define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
@@ -284,10 +284,10 @@
 #define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
 #define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
 #define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
+#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 
 /* USB Endpoint 2 Control Registers */
 
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
 #define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
 #define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
 #define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
@@ -297,10 +297,10 @@
 #define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
 #define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
 #define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
+#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
 
 /* USB Endpoint 3 Control Registers */
 
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
 #define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
 #define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
 #define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
@@ -310,10 +310,10 @@
 #define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
 #define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
 #define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
+#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 
 /* USB Endpoint 4 Control Registers */
 
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
 #define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
 #define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
 #define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
@@ -323,10 +323,10 @@
 #define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
 #define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
 #define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
+#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
 
 /* USB Endpoint 5 Control Registers */
 
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
 #define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
 #define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
 #define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
@@ -336,10 +336,10 @@
 #define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
 #define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
 #define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
+#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
 
 /* USB Endpoint 6 Control Registers */
 
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
 #define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
 #define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
 #define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
@@ -349,10 +349,10 @@
 #define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
 #define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
 #define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
+#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
 
 /* USB Endpoint 7 Control Registers */
 
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
 #define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
 #define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
 #define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
@@ -361,8 +361,9 @@
 #define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
 #define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
 #define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+#define            USB_EP_NI7_RXINTERVAL  0xffc03fe0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
+#define               USB_EP_NI7_TXCOUNT  0xffc03fe8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
+
 #define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
 
 /* USB Channel 0 Config Registers */
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 7f87787e7738..533b8095b540 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -7,38 +7,9 @@
 #ifndef _BF548_IRQ_H_
 #define _BF548_IRQ_H_
 
-/*
- * Interrupt source definitions
-            Event Source    Core Event Name
-Core        Emulation               **
-Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-
-.....
-
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
-                 (lowest priority)  IVG15       32 *
- */
-
-#define NR_PERI_INTS    (32 * 3)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt*/
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
+#include <mach-common/irq.h>
 
-#define BFIN_IRQ(x)             ((x) + 7)
+#define NR_PERI_INTS            (3 * 32)
 
 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
 #define IRQ_DMAC0_ERROR         BFIN_IRQ(1)     /* DMAC0 Status Interrupt */
@@ -311,49 +282,37 @@ Events         (highest priority)  EMU         0
 #define IRQ_PJ14                BFIN_PJ_IRQ(14)         /* N/A */
 #define IRQ_PJ15                BFIN_PJ_IRQ(15)         /* N/A */
 
-#define GPIO_IRQ_BASE   IRQ_PA0
+#define GPIO_IRQ_BASE           IRQ_PA0
 
-#define NR_MACH_IRQS    (IRQ_PJ15 + 1)
-#define NR_IRQS         (NR_MACH_IRQS + NR_SPARE_IRQS)
+#define NR_MACH_IRQS            (IRQ_PJ15 + 1)
 
 /* For compatibility reasons with existing code */
 
-#define IRQ_DMAC0_ERR           IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR           IRQ_EPPI0_ERROR
+#define IRQ_DMAC0_ERR           IRQ_DMAC0_ERROR
+#define IRQ_EPPI0_ERR           IRQ_EPPI0_ERROR
 #define IRQ_SPORT0_ERR          IRQ_SPORT0_ERROR
 #define IRQ_SPORT1_ERR          IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR            IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR           IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR           IRQ_DMAC1_ERROR
+#define IRQ_SPI0_ERR            IRQ_SPI0_ERROR
+#define IRQ_UART0_ERR           IRQ_UART0_ERROR
+#define IRQ_DMAC1_ERR           IRQ_DMAC1_ERROR
 #define IRQ_SPORT2_ERR          IRQ_SPORT2_ERROR
 #define IRQ_SPORT3_ERR          IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR            IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR            IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR           IRQ_UART1_ERROR
-#define IRQ_UART2_ERR           IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR            IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR            IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR           IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR           IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR           IRQ_UART3_ERROR
-#define IRQ_HOST_ERR            IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR            IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR             IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR           IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR            IRQ_CAN1_ERROR
+#define IRQ_SPI1_ERR            IRQ_SPI1_ERROR
+#define IRQ_SPI2_ERR            IRQ_SPI2_ERROR
+#define IRQ_UART1_ERR           IRQ_UART1_ERROR
+#define IRQ_UART2_ERR           IRQ_UART2_ERROR
+#define IRQ_CAN0_ERR            IRQ_CAN0_ERROR
+#define IRQ_MXVR_ERR            IRQ_MXVR_ERROR
+#define IRQ_EPPI1_ERR           IRQ_EPPI1_ERROR
+#define IRQ_EPPI2_ERR           IRQ_EPPI2_ERROR
+#define IRQ_UART3_ERR           IRQ_UART3_ERROR
+#define IRQ_HOST_ERR            IRQ_HOST_ERROR
+#define IRQ_PIXC_ERR            IRQ_PIXC_ERROR
+#define IRQ_NFC_ERR             IRQ_NFC_ERROR
+#define IRQ_ATAPI_ERR           IRQ_ATAPI_ERROR
+#define IRQ_CAN1_ERR            IRQ_CAN1_ERROR
 #define IRQ_HS_DMA_ERR          IRQ_HS_DMA_ERROR
 
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
 /* IAR0 BIT FIELDS */
 #define IRQ_PLL_WAKEUP_POS      0
 #define IRQ_DMAC0_ERR_POS       4
@@ -492,4 +451,4 @@ struct bfin_pint_regs {
 
 #endif
 
-#endif /* _BF548_IRQ_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf561/boards/acvilon.c b/arch/blackfin/mach-bf561/boards/acvilon.c
index 3926cd909b66..9231a942892b 100644
--- a/arch/blackfin/mach-bf561/boards/acvilon.c
+++ b/arch/blackfin/mach-bf561/boards/acvilon.c
@@ -243,7 +243,6 @@ static struct platform_device bfin_uart0_device = {
 
 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 
-#ifdef CONFIG_MTD_PARTITIONS
 const char *part_probes[] = { "cmdlinepart", NULL };
 
 static struct mtd_partition bfin_plat_nand_partitions[] = {
@@ -257,7 +256,6 @@ static struct mtd_partition bfin_plat_nand_partitions[] = {
              .offset = MTDPART_OFS_APPEND,
              },
 };
-#endif
 
 #define BFIN_NAND_PLAT_CLE 2
 #define BFIN_NAND_PLAT_ALE 3
@@ -286,11 +284,9 @@ static struct platform_nand_data bfin_plat_nand_data = {
         .chip = {
                  .nr_chips = 1,
                  .chip_delay = 30,
-#ifdef CONFIG_MTD_PARTITIONS
                  .part_probe_types = part_probes,
                  .partitions = bfin_plat_nand_partitions,
                  .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
-#endif
                  },
         .ctrl = {
                  .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index f667e7704197..5067984a62e7 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -247,7 +247,15 @@ static struct mtd_partition ezkit_partitions[] = {
                 .offset     = MTDPART_OFS_APPEND,
         }, {
                 .name       = "file system(nor)",
-                .size       = MTDPART_SIZ_FULL,
+                .size       = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "config(nor)",
+                .size       = 0x2000 * 7,
+                .offset     = MTDPART_OFS_APPEND,
+        }, {
+                .name       = "u-boot env(nor)",
+                .size       = 0x2000,
                 .offset     = MTDPART_OFS_APPEND,
         }
 };
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 6a3499b02097..22b5ab773027 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,13 +5,13 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
  * Licensed under the ADI BSD license.
  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -290,12 +290,18 @@
 #define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
+/* SCKELOW Feature Is Not Functional */
+#define ANOMALY_05000458 (1)
 /* False Hardware Error when RETI Points to Invalid Memory */
 #define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
 /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
 #define ANOMALY_05000473 (1)
 /* Possible Lockup Condition whem Modifying PLL from External Memory */
-#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000475 (1)
 /* TESTSET Instruction Cannot Be Interrupted */
 #define ANOMALY_05000477 (1)
 /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -314,12 +320,14 @@
 #define ANOMALY_05000353 (1)
 #define ANOMALY_05000364 (0)
 #define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
 #define ANOMALY_05000386 (1)
 #define ANOMALY_05000389 (0)
 #define ANOMALY_05000400 (0)
 #define ANOMALY_05000430 (0)
 #define ANOMALY_05000432 (0)
 #define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
 #define ANOMALY_05000456 (0)
@@ -327,6 +335,7 @@
 #define ANOMALY_05000465 (0)
 #define ANOMALY_05000467 (0)
 #define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
 #define ANOMALY_05000485 (0)
 
 #endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
deleted file mode 100644
index 3a6947456cf1..000000000000
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-# define CONFIG_SERIAL_BFIN_CTSRTS
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-        int             uart_status_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        IRQ_UART_ERROR,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART_TX,
-        CH_UART_RX,
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        }
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-#include <asm/bfin_serial.h>
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
index c95566ade51b..d6998520f70f 100644
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -7,212 +7,98 @@
 #ifndef _BF561_IRQ_H_
 #define _BF561_IRQ_H_
 
-/***********************************************************************
- * Interrupt source definitions:
-             Event Source               Core Event Name     IRQ No
-                                                (highest priority)
-            Emulation Events                    EMU         0
-            Reset                               RST         1
-            NMI                                 NMI         2
-            Exception                           EVX         3
-            Reserved                            --          4
-            Hardware Error                      IVHW        5
-            Core Timer                          IVTMR       6 *
-
-            PLL Wakeup Interrupt                IVG7        7
-            DMA1 Error (generic)                IVG7        8
-            DMA2 Error (generic)                IVG7        9
-            IMDMA Error (generic)               IVG7        10
-            PPI1 Error Interrupt                IVG7        11
-            PPI2 Error Interrupt                IVG7        12
-            SPORT0 Error Interrupt              IVG7        13
-            SPORT1 Error Interrupt              IVG7        14
-            SPI Error Interrupt                 IVG7        15
-            UART Error Interrupt                IVG7        16
-            Reserved Interrupt                  IVG7        17
-
-            DMA1 0  Interrupt(PPI1)             IVG8        18
-            DMA1 1  Interrupt(PPI2)             IVG8        19
-            DMA1 2  Interrupt                   IVG8        20
-            DMA1 3  Interrupt                   IVG8        21
-            DMA1 4  Interrupt                   IVG8        22
-            DMA1 5  Interrupt                   IVG8        23
-            DMA1 6  Interrupt                   IVG8        24
-            DMA1 7  Interrupt                   IVG8        25
-            DMA1 8  Interrupt                   IVG8        26
-            DMA1 9  Interrupt                   IVG8        27
-            DMA1 10 Interrupt                   IVG8        28
-            DMA1 11 Interrupt                   IVG8        29
-
-            DMA2 0  (SPORT0 RX)                 IVG9        30
-            DMA2 1  (SPORT0 TX)                 IVG9        31
-            DMA2 2  (SPORT1 RX)                 IVG9        32
-            DMA2 3  (SPORT2 TX)                 IVG9        33
-            DMA2 4  (SPI)                       IVG9        34
-            DMA2 5  (UART RX)                   IVG9        35
-            DMA2 6  (UART TX)                   IVG9        36
-            DMA2 7  Interrupt                   IVG9        37
-            DMA2 8  Interrupt                   IVG9        38
-            DMA2 9  Interrupt                   IVG9        39
-            DMA2 10 Interrupt                   IVG9        40
-            DMA2 11 Interrupt                   IVG9        41
-
-            TIMER 0  Interrupt                  IVG10       42
-            TIMER 1  Interrupt                  IVG10       43
-            TIMER 2  Interrupt                  IVG10       44
-            TIMER 3  Interrupt                  IVG10       45
-            TIMER 4  Interrupt                  IVG10       46
-            TIMER 5  Interrupt                  IVG10       47
-            TIMER 6  Interrupt                  IVG10       48
-            TIMER 7  Interrupt                  IVG10       49
-            TIMER 8  Interrupt                  IVG10       50
-            TIMER 9  Interrupt                  IVG10       51
-            TIMER 10 Interrupt                  IVG10       52
-            TIMER 11 Interrupt                  IVG10       53
-
-            Programmable Flags0 A (8)           IVG11       54
-            Programmable Flags0 B (8)           IVG11       55
-            Programmable Flags1 A (8)           IVG11       56
-            Programmable Flags1 B (8)           IVG11       57
-            Programmable Flags2 A (8)           IVG11       58
-            Programmable Flags2 B (8)           IVG11       59
-
-            MDMA1 0 write/read INT              IVG8        60
-            MDMA1 1 write/read INT              IVG8        61
-
-            MDMA2 0 write/read INT              IVG9        62
-            MDMA2 1 write/read INT              IVG9        63
-
-            IMDMA 0 write/read INT              IVG12       64
-            IMDMA 1 write/read INT              IVG12       65
-
-            Watch Dog Timer                     IVG13       66
-
-            Reserved interrupt                  IVG7        67
-            Reserved interrupt                  IVG7        68
-            Supplemental interrupt 0            IVG7        69
-            supplemental interrupt 1            IVG7        70
-
-            Softirq                             IVG14
-            System Call    --
-                 (lowest priority)              IVG15
-
- **********************************************************************/
-
-#define SYS_IRQS                71
-#define NR_PERI_INTS            64
-
-/*
- * The ABSTRACT IRQ definitions
- *  the first seven of the following are fixed,
- *  the rest you change if you need to.
- */
-/* IVG 0-6*/
-#define IRQ_EMU                 0       /* Emulation                */
-#define IRQ_RST                 1       /* Reset                    */
-#define IRQ_NMI                 2       /* Non Maskable Interrupt   */
-#define IRQ_EVX                 3       /* Exception                */
-#define IRQ_UNUSED              4       /* Reserved interrupt       */
-#define IRQ_HWERR               5       /* Hardware Error           */
-#define IRQ_CORETMR             6       /* Core timer               */
-
-#define IVG_BASE                7
-/* IVG 7  */
-#define IRQ_PLL_WAKEUP          (IVG_BASE + 0)  /* PLL Wakeup Interrupt     */
-#define IRQ_DMA1_ERROR          (IVG_BASE + 1)  /* DMA1   Error (general)   */
-#define IRQ_DMA_ERROR           IRQ_DMA1_ERROR  /* DMA1   Error (general)   */
-#define IRQ_DMA2_ERROR          (IVG_BASE + 2)  /* DMA2   Error (general)   */
-#define IRQ_IMDMA_ERROR         (IVG_BASE + 3)  /* IMDMA  Error Interrupt   */
-#define IRQ_PPI1_ERROR          (IVG_BASE + 4)  /* PPI1   Error Interrupt   */
-#define IRQ_PPI_ERROR           IRQ_PPI1_ERROR  /* PPI1   Error Interrupt   */
-#define IRQ_PPI2_ERROR          (IVG_BASE + 5)  /* PPI2   Error Interrupt   */
-#define IRQ_SPORT0_ERROR        (IVG_BASE + 6)  /* SPORT0 Error Interrupt   */
-#define IRQ_SPORT1_ERROR        (IVG_BASE + 7)  /* SPORT1 Error Interrupt   */
-#define IRQ_SPI_ERROR           (IVG_BASE + 8)  /* SPI    Error Interrupt   */
-#define IRQ_UART_ERROR          (IVG_BASE + 9)  /* UART   Error Interrupt   */
-#define IRQ_RESERVED_ERROR      (IVG_BASE + 10) /* Reversed     Interrupt   */
-/* IVG 8  */
-#define IRQ_DMA1_0              (IVG_BASE + 11) /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_PPI                 IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_PPI0                IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_DMA1_1              (IVG_BASE + 12) /* DMA1 1  Interrupt(PPI2)  */
-#define IRQ_PPI1                IRQ_DMA1_1      /* DMA1 1  Interrupt(PPI2)  */
-#define IRQ_DMA1_2              (IVG_BASE + 13) /* DMA1 2  Interrupt        */
-#define IRQ_DMA1_3              (IVG_BASE + 14) /* DMA1 3  Interrupt        */
-#define IRQ_DMA1_4              (IVG_BASE + 15) /* DMA1 4  Interrupt        */
-#define IRQ_DMA1_5              (IVG_BASE + 16) /* DMA1 5  Interrupt        */
-#define IRQ_DMA1_6              (IVG_BASE + 17) /* DMA1 6  Interrupt        */
-#define IRQ_DMA1_7              (IVG_BASE + 18) /* DMA1 7  Interrupt        */
-#define IRQ_DMA1_8              (IVG_BASE + 19) /* DMA1 8  Interrupt        */
-#define IRQ_DMA1_9              (IVG_BASE + 20) /* DMA1 9  Interrupt        */
-#define IRQ_DMA1_10             (IVG_BASE + 21) /* DMA1 10 Interrupt        */
-#define IRQ_DMA1_11             (IVG_BASE + 22) /* DMA1 11 Interrupt        */
-/* IVG 9  */
-#define IRQ_DMA2_0              (IVG_BASE + 23) /* DMA2 0  (SPORT0 RX)      */
-#define IRQ_SPORT0_RX           IRQ_DMA2_0      /* DMA2 0  (SPORT0 RX)      */
-#define IRQ_DMA2_1              (IVG_BASE + 24) /* DMA2 1  (SPORT0 TX)      */
-#define IRQ_SPORT0_TX           IRQ_DMA2_1      /* DMA2 1  (SPORT0 TX)      */
-#define IRQ_DMA2_2              (IVG_BASE + 25) /* DMA2 2  (SPORT1 RX)      */
-#define IRQ_SPORT1_RX           IRQ_DMA2_2      /* DMA2 2  (SPORT1 RX)      */
-#define IRQ_DMA2_3              (IVG_BASE + 26) /* DMA2 3  (SPORT2 TX)      */
-#define IRQ_SPORT1_TX           IRQ_DMA2_3      /* DMA2 3  (SPORT2 TX)      */
-#define IRQ_DMA2_4              (IVG_BASE + 27) /* DMA2 4  (SPI)            */
-#define IRQ_SPI                 IRQ_DMA2_4      /* DMA2 4  (SPI)            */
-#define IRQ_DMA2_5              (IVG_BASE + 28) /* DMA2 5  (UART RX)        */
-#define IRQ_UART_RX             IRQ_DMA2_5      /* DMA2 5  (UART RX)        */
-#define IRQ_DMA2_6              (IVG_BASE + 29) /* DMA2 6  (UART TX)        */
-#define IRQ_UART_TX             IRQ_DMA2_6      /* DMA2 6  (UART TX)        */
-#define IRQ_DMA2_7              (IVG_BASE + 30) /* DMA2 7  Interrupt        */
-#define IRQ_DMA2_8              (IVG_BASE + 31) /* DMA2 8  Interrupt        */
-#define IRQ_DMA2_9              (IVG_BASE + 32) /* DMA2 9  Interrupt        */
-#define IRQ_DMA2_10             (IVG_BASE + 33) /* DMA2 10 Interrupt        */
-#define IRQ_DMA2_11             (IVG_BASE + 34) /* DMA2 11 Interrupt        */
-/* IVG 10 */
-#define IRQ_TIMER0              (IVG_BASE + 35) /* TIMER 0  Interrupt       */
-#define IRQ_TIMER1              (IVG_BASE + 36) /* TIMER 1  Interrupt       */
-#define IRQ_TIMER2              (IVG_BASE + 37) /* TIMER 2  Interrupt       */
-#define IRQ_TIMER3              (IVG_BASE + 38) /* TIMER 3  Interrupt       */
-#define IRQ_TIMER4              (IVG_BASE + 39) /* TIMER 4  Interrupt       */
-#define IRQ_TIMER5              (IVG_BASE + 40) /* TIMER 5  Interrupt       */
-#define IRQ_TIMER6              (IVG_BASE + 41) /* TIMER 6  Interrupt       */
-#define IRQ_TIMER7              (IVG_BASE + 42) /* TIMER 7  Interrupt       */
-#define IRQ_TIMER8              (IVG_BASE + 43) /* TIMER 8  Interrupt       */
-#define IRQ_TIMER9              (IVG_BASE + 44) /* TIMER 9  Interrupt       */
-#define IRQ_TIMER10             (IVG_BASE + 45) /* TIMER 10 Interrupt       */
-#define IRQ_TIMER11             (IVG_BASE + 46) /* TIMER 11 Interrupt       */
-/* IVG 11 */
-#define IRQ_PROG0_INTA          (IVG_BASE + 47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA           IRQ_PROG0_INTA  /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB          (IVG_BASE + 48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB           IRQ_PROG0_INTB  /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA          (IVG_BASE + 49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB          (IVG_BASE + 50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA          (IVG_BASE + 51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB          (IVG_BASE + 52) /* Programmable Flags2 B (8) */
-/* IVG 8  */
-#define IRQ_DMA1_WRRD0          (IVG_BASE + 53) /* MDMA1 0 write/read INT   */
-#define IRQ_DMA_WRRD0           IRQ_DMA1_WRRD0  /* MDMA1 0 write/read INT   */
+#include <mach-common/irq.h>
+
+#define NR_PERI_INTS            (2 * 32)
+
+#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
+#define IRQ_DMA1_ERROR          BFIN_IRQ(1)     /* DMA1   Error (general) */
+#define IRQ_DMA_ERROR           IRQ_DMA1_ERROR  /* DMA1   Error (general) */
+#define IRQ_DMA2_ERROR          BFIN_IRQ(2)     /* DMA2   Error (general) */
+#define IRQ_IMDMA_ERROR         BFIN_IRQ(3)     /* IMDMA  Error Interrupt */
+#define IRQ_PPI1_ERROR          BFIN_IRQ(4)     /* PPI1   Error Interrupt */
+#define IRQ_PPI_ERROR           IRQ_PPI1_ERROR  /* PPI1   Error Interrupt */
+#define IRQ_PPI2_ERROR          BFIN_IRQ(5)     /* PPI2   Error Interrupt */
+#define IRQ_SPORT0_ERROR        BFIN_IRQ(6)     /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR        BFIN_IRQ(7)     /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR           BFIN_IRQ(8)     /* SPI    Error Interrupt */
+#define IRQ_UART_ERROR          BFIN_IRQ(9)     /* UART   Error Interrupt */
+#define IRQ_RESERVED_ERROR      BFIN_IRQ(10)    /* Reversed */
+#define IRQ_DMA1_0              BFIN_IRQ(11)    /* DMA1 0  Interrupt(PPI1) */
+#define IRQ_PPI                 IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1) */
+#define IRQ_PPI0                IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1) */
+#define IRQ_DMA1_1              BFIN_IRQ(12)    /* DMA1 1  Interrupt(PPI2) */
+#define IRQ_PPI1                IRQ_DMA1_1      /* DMA1 1  Interrupt(PPI2) */
+#define IRQ_DMA1_2              BFIN_IRQ(13)    /* DMA1 2  Interrupt */
+#define IRQ_DMA1_3              BFIN_IRQ(14)    /* DMA1 3  Interrupt */
+#define IRQ_DMA1_4              BFIN_IRQ(15)    /* DMA1 4  Interrupt */
+#define IRQ_DMA1_5              BFIN_IRQ(16)    /* DMA1 5  Interrupt */
+#define IRQ_DMA1_6              BFIN_IRQ(17)    /* DMA1 6  Interrupt */
+#define IRQ_DMA1_7              BFIN_IRQ(18)    /* DMA1 7  Interrupt */
+#define IRQ_DMA1_8              BFIN_IRQ(19)    /* DMA1 8  Interrupt */
+#define IRQ_DMA1_9              BFIN_IRQ(20)    /* DMA1 9  Interrupt */
+#define IRQ_DMA1_10             BFIN_IRQ(21)    /* DMA1 10 Interrupt */
+#define IRQ_DMA1_11             BFIN_IRQ(22)    /* DMA1 11 Interrupt */
+#define IRQ_DMA2_0              BFIN_IRQ(23)    /* DMA2 0  (SPORT0 RX) */
+#define IRQ_SPORT0_RX           IRQ_DMA2_0      /* DMA2 0  (SPORT0 RX) */
+#define IRQ_DMA2_1              BFIN_IRQ(24)    /* DMA2 1  (SPORT0 TX) */
+#define IRQ_SPORT0_TX           IRQ_DMA2_1      /* DMA2 1  (SPORT0 TX) */
+#define IRQ_DMA2_2              BFIN_IRQ(25)    /* DMA2 2  (SPORT1 RX) */
+#define IRQ_SPORT1_RX           IRQ_DMA2_2      /* DMA2 2  (SPORT1 RX) */
+#define IRQ_DMA2_3              BFIN_IRQ(26)    /* DMA2 3  (SPORT2 TX) */
+#define IRQ_SPORT1_TX           IRQ_DMA2_3      /* DMA2 3  (SPORT2 TX) */
+#define IRQ_DMA2_4              BFIN_IRQ(27)    /* DMA2 4  (SPI) */
+#define IRQ_SPI                 IRQ_DMA2_4      /* DMA2 4  (SPI) */
+#define IRQ_DMA2_5              BFIN_IRQ(28)    /* DMA2 5  (UART RX) */
+#define IRQ_UART_RX             IRQ_DMA2_5      /* DMA2 5  (UART RX) */
+#define IRQ_DMA2_6              BFIN_IRQ(29)    /* DMA2 6  (UART TX) */
+#define IRQ_UART_TX             IRQ_DMA2_6      /* DMA2 6  (UART TX) */
+#define IRQ_DMA2_7              BFIN_IRQ(30)    /* DMA2 7  Interrupt */
+#define IRQ_DMA2_8              BFIN_IRQ(31)    /* DMA2 8  Interrupt */
+#define IRQ_DMA2_9              BFIN_IRQ(32)    /* DMA2 9  Interrupt */
+#define IRQ_DMA2_10             BFIN_IRQ(33)    /* DMA2 10 Interrupt */
+#define IRQ_DMA2_11             BFIN_IRQ(34)    /* DMA2 11 Interrupt */
+#define IRQ_TIMER0              BFIN_IRQ(35)    /* TIMER 0  Interrupt */
+#define IRQ_TIMER1              BFIN_IRQ(36)    /* TIMER 1  Interrupt */
+#define IRQ_TIMER2              BFIN_IRQ(37)    /* TIMER 2  Interrupt */
+#define IRQ_TIMER3              BFIN_IRQ(38)    /* TIMER 3  Interrupt */
+#define IRQ_TIMER4              BFIN_IRQ(39)    /* TIMER 4  Interrupt */
+#define IRQ_TIMER5              BFIN_IRQ(40)    /* TIMER 5  Interrupt */
+#define IRQ_TIMER6              BFIN_IRQ(41)    /* TIMER 6  Interrupt */
+#define IRQ_TIMER7              BFIN_IRQ(42)    /* TIMER 7  Interrupt */
+#define IRQ_TIMER8              BFIN_IRQ(43)    /* TIMER 8  Interrupt */
+#define IRQ_TIMER9              BFIN_IRQ(44)    /* TIMER 9  Interrupt */
+#define IRQ_TIMER10             BFIN_IRQ(45)    /* TIMER 10 Interrupt */
+#define IRQ_TIMER11             BFIN_IRQ(46)    /* TIMER 11 Interrupt */
+#define IRQ_PROG0_INTA          BFIN_IRQ(47)    /* Programmable Flags0 A (8) */
+#define IRQ_PROG_INTA           IRQ_PROG0_INTA  /* Programmable Flags0 A (8) */
+#define IRQ_PROG0_INTB          BFIN_IRQ(48)    /* Programmable Flags0 B (8) */
+#define IRQ_PROG_INTB           IRQ_PROG0_INTB  /* Programmable Flags0 B (8) */
+#define IRQ_PROG1_INTA          BFIN_IRQ(49)    /* Programmable Flags1 A (8) */
+#define IRQ_PROG1_INTB          BFIN_IRQ(50)    /* Programmable Flags1 B (8) */
+#define IRQ_PROG2_INTA          BFIN_IRQ(51)    /* Programmable Flags2 A (8) */
+#define IRQ_PROG2_INTB          BFIN_IRQ(52)    /* Programmable Flags2 B (8) */
+#define IRQ_DMA1_WRRD0          BFIN_IRQ(53)    /* MDMA1 0 write/read INT */
+#define IRQ_DMA_WRRD0           IRQ_DMA1_WRRD0  /* MDMA1 0 write/read INT */
 #define IRQ_MEM_DMA0            IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1          (IVG_BASE + 54) /* MDMA1 1 write/read INT   */
-#define IRQ_DMA_WRRD1           IRQ_DMA1_WRRD1  /* MDMA1 1 write/read INT   */
+#define IRQ_DMA1_WRRD1          BFIN_IRQ(54)    /* MDMA1 1 write/read INT */
+#define IRQ_DMA_WRRD1           IRQ_DMA1_WRRD1  /* MDMA1 1 write/read INT */
 #define IRQ_MEM_DMA1            IRQ_DMA1_WRRD1
-/* IVG 9  */
-#define IRQ_DMA2_WRRD0          (IVG_BASE + 55) /* MDMA2 0 write/read INT   */
+#define IRQ_DMA2_WRRD0          BFIN_IRQ(55)    /* MDMA2 0 write/read INT */
 #define IRQ_MEM_DMA2            IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1          (IVG_BASE + 56) /* MDMA2 1 write/read INT   */
+#define IRQ_DMA2_WRRD1          BFIN_IRQ(56)    /* MDMA2 1 write/read INT */
 #define IRQ_MEM_DMA3            IRQ_DMA2_WRRD1
-/* IVG 12 */
-#define IRQ_IMDMA_WRRD0         (IVG_BASE + 57) /* IMDMA 0 write/read INT   */
+#define IRQ_IMDMA_WRRD0         BFIN_IRQ(57)    /* IMDMA 0 write/read INT */
 #define IRQ_IMEM_DMA0           IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1         (IVG_BASE + 58) /* IMDMA 1 write/read INT   */
+#define IRQ_IMDMA_WRRD1         BFIN_IRQ(58)    /* IMDMA 1 write/read INT */
 #define IRQ_IMEM_DMA1           IRQ_IMDMA_WRRD1
-/* IVG 13 */
-#define IRQ_WATCH               (IVG_BASE + 59) /* Watch Dog Timer          */
-/* IVG 7  */
-#define IRQ_RESERVED_1          (IVG_BASE + 60) /* Reserved interrupt       */
-#define IRQ_RESERVED_2          (IVG_BASE + 61) /* Reserved interrupt       */
-#define IRQ_SUPPLE_0            (IVG_BASE + 62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1            (IVG_BASE + 63) /* supplemental interrupt 1 */
+#define IRQ_WATCH               BFIN_IRQ(59)    /* Watch Dog Timer */
+#define IRQ_RESERVED_1          BFIN_IRQ(60)    /* Reserved interrupt */
+#define IRQ_RESERVED_2          BFIN_IRQ(61)    /* Reserved interrupt */
+#define IRQ_SUPPLE_0            BFIN_IRQ(62)    /* Supplemental interrupt 0 */
+#define IRQ_SUPPLE_1            BFIN_IRQ(63)    /* supplemental interrupt 1 */
+
+#define SYS_IRQS                71
 
 #define IRQ_PF0                 73
 #define IRQ_PF1                 74
@@ -266,158 +152,85 @@
 #define GPIO_IRQ_BASE           IRQ_PF0
 
 #define NR_MACH_IRQS            (IRQ_PF47 + 1)
-#define NR_IRQS                 (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7                    7
-#define IVG8                    8
-#define IVG9                    9
-#define IVG10                   10
-#define IVG11                   11
-#define IVG12                   12
-#define IVG13                   13
-#define IVG14                   14
-#define IVG15                   15
-
-/*
- * DEFAULT PRIORITIES:
- */
-
-#define CONFIG_DEF_PLL_WAKEUP           7
-#define CONFIG_DEF_DMA1_ERROR           7
-#define CONFIG_DEF_DMA2_ERROR           7
-#define CONFIG_DEF_IMDMA_ERROR          7
-#define CONFIG_DEF_PPI1_ERROR           7
-#define CONFIG_DEF_PPI2_ERROR           7
-#define CONFIG_DEF_SPORT0_ERROR         7
-#define CONFIG_DEF_SPORT1_ERROR         7
-#define CONFIG_DEF_SPI_ERROR            7
-#define CONFIG_DEF_UART_ERROR           7
-#define CONFIG_DEF_RESERVED_ERROR       7
-#define CONFIG_DEF_DMA1_0               8
-#define CONFIG_DEF_DMA1_1               8
-#define CONFIG_DEF_DMA1_2               8
-#define CONFIG_DEF_DMA1_3               8
-#define CONFIG_DEF_DMA1_4               8
-#define CONFIG_DEF_DMA1_5               8
-#define CONFIG_DEF_DMA1_6               8
-#define CONFIG_DEF_DMA1_7               8
-#define CONFIG_DEF_DMA1_8               8
-#define CONFIG_DEF_DMA1_9               8
-#define CONFIG_DEF_DMA1_10              8
-#define CONFIG_DEF_DMA1_11              8
-#define CONFIG_DEF_DMA2_0               9
-#define CONFIG_DEF_DMA2_1               9
-#define CONFIG_DEF_DMA2_2               9
-#define CONFIG_DEF_DMA2_3               9
-#define CONFIG_DEF_DMA2_4               9
-#define CONFIG_DEF_DMA2_5               9
-#define CONFIG_DEF_DMA2_6               9
-#define CONFIG_DEF_DMA2_7               9
-#define CONFIG_DEF_DMA2_8               9
-#define CONFIG_DEF_DMA2_9               9
-#define CONFIG_DEF_DMA2_10              9
-#define CONFIG_DEF_DMA2_11              9
-#define CONFIG_DEF_TIMER0               10
-#define CONFIG_DEF_TIMER1               10
-#define CONFIG_DEF_TIMER2               10
-#define CONFIG_DEF_TIMER3               10
-#define CONFIG_DEF_TIMER4               10
-#define CONFIG_DEF_TIMER5               10
-#define CONFIG_DEF_TIMER6               10
-#define CONFIG_DEF_TIMER7               10
-#define CONFIG_DEF_TIMER8               10
-#define CONFIG_DEF_TIMER9               10
-#define CONFIG_DEF_TIMER10              10
-#define CONFIG_DEF_TIMER11              10
-#define CONFIG_DEF_PROG0_INTA           11
-#define CONFIG_DEF_PROG0_INTB           11
-#define CONFIG_DEF_PROG1_INTA           11
-#define CONFIG_DEF_PROG1_INTB           11
-#define CONFIG_DEF_PROG2_INTA           11
-#define CONFIG_DEF_PROG2_INTB           11
-#define CONFIG_DEF_DMA1_WRRD0           8
-#define CONFIG_DEF_DMA1_WRRD1           8
-#define CONFIG_DEF_DMA2_WRRD0           9
-#define CONFIG_DEF_DMA2_WRRD1           9
-#define CONFIG_DEF_IMDMA_WRRD0          12
-#define CONFIG_DEF_IMDMA_WRRD1          12
-#define CONFIG_DEF_WATCH                13
-#define CONFIG_DEF_RESERVED_1           7
-#define CONFIG_DEF_RESERVED_2           7
-#define CONFIG_DEF_SUPPLE_0             7
-#define CONFIG_DEF_SUPPLE_1             7
 
 /* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS                      0
-#define IRQ_DMA1_ERROR_POS                      4
-#define IRQ_DMA2_ERROR_POS                      8
-#define IRQ_IMDMA_ERROR_POS                     12
-#define IRQ_PPI0_ERROR_POS                      16
-#define IRQ_PPI1_ERROR_POS                      20
-#define IRQ_SPORT0_ERROR_POS            24
-#define IRQ_SPORT1_ERROR_POS            28
+#define IRQ_PLL_WAKEUP_POS      0
+#define IRQ_DMA1_ERROR_POS      4
+#define IRQ_DMA2_ERROR_POS      8
+#define IRQ_IMDMA_ERROR_POS     12
+#define IRQ_PPI0_ERROR_POS      16
+#define IRQ_PPI1_ERROR_POS      20
+#define IRQ_SPORT0_ERROR_POS    24
+#define IRQ_SPORT1_ERROR_POS    28
+
 /* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS                       0
-#define IRQ_UART_ERROR_POS                      4
-#define IRQ_RESERVED_ERROR_POS          8
-#define IRQ_DMA1_0_POS                  12
-#define IRQ_DMA1_1_POS                  16
-#define IRQ_DMA1_2_POS                  20
-#define IRQ_DMA1_3_POS                  24
-#define IRQ_DMA1_4_POS                  28
+#define IRQ_SPI_ERROR_POS       0
+#define IRQ_UART_ERROR_POS      4
+#define IRQ_RESERVED_ERROR_POS  8
+#define IRQ_DMA1_0_POS          12
+#define IRQ_DMA1_1_POS          16
+#define IRQ_DMA1_2_POS          20
+#define IRQ_DMA1_3_POS          24
+#define IRQ_DMA1_4_POS          28
+
 /* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS                  0
-#define IRQ_DMA1_6_POS                  4
-#define IRQ_DMA1_7_POS                  8
-#define IRQ_DMA1_8_POS                  12
-#define IRQ_DMA1_9_POS                  16
-#define IRQ_DMA1_10_POS                 20
-#define IRQ_DMA1_11_POS                 24
-#define IRQ_DMA2_0_POS                  28
+#define IRQ_DMA1_5_POS          0
+#define IRQ_DMA1_6_POS          4
+#define IRQ_DMA1_7_POS          8
+#define IRQ_DMA1_8_POS          12
+#define IRQ_DMA1_9_POS          16
+#define IRQ_DMA1_10_POS         20
+#define IRQ_DMA1_11_POS         24
+#define IRQ_DMA2_0_POS          28
+
 /* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS                  0
-#define IRQ_DMA2_2_POS                  4
-#define IRQ_DMA2_3_POS                  8
-#define IRQ_DMA2_4_POS                  12
-#define IRQ_DMA2_5_POS                  16
-#define IRQ_DMA2_6_POS                  20
-#define IRQ_DMA2_7_POS                  24
-#define IRQ_DMA2_8_POS                  28
+#define IRQ_DMA2_1_POS          0
+#define IRQ_DMA2_2_POS          4
+#define IRQ_DMA2_3_POS          8
+#define IRQ_DMA2_4_POS          12
+#define IRQ_DMA2_5_POS          16
+#define IRQ_DMA2_6_POS          20
+#define IRQ_DMA2_7_POS          24
+#define IRQ_DMA2_8_POS          28
+
 /* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS                  0
-#define IRQ_DMA2_10_POS                 4
-#define IRQ_DMA2_11_POS                 8
-#define IRQ_TIMER0_POS                  12
-#define IRQ_TIMER1_POS                  16
-#define IRQ_TIMER2_POS                  20
-#define IRQ_TIMER3_POS                  24
-#define IRQ_TIMER4_POS                  28
+#define IRQ_DMA2_9_POS          0
+#define IRQ_DMA2_10_POS         4
+#define IRQ_DMA2_11_POS         8
+#define IRQ_TIMER0_POS          12
+#define IRQ_TIMER1_POS          16
+#define IRQ_TIMER2_POS          20
+#define IRQ_TIMER3_POS          24
+#define IRQ_TIMER4_POS          28
+
 /* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS                  0
-#define IRQ_TIMER6_POS                  4
-#define IRQ_TIMER7_POS                  8
-#define IRQ_TIMER8_POS                  12
-#define IRQ_TIMER9_POS                  16
-#define IRQ_TIMER10_POS                 20
-#define IRQ_TIMER11_POS                 24
-#define IRQ_PROG0_INTA_POS                      28
+#define IRQ_TIMER5_POS          0
+#define IRQ_TIMER6_POS          4
+#define IRQ_TIMER7_POS          8
+#define IRQ_TIMER8_POS          12
+#define IRQ_TIMER9_POS          16
+#define IRQ_TIMER10_POS         20
+#define IRQ_TIMER11_POS         24
+#define IRQ_PROG0_INTA_POS      28
+
 /* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS                      0
-#define IRQ_PROG1_INTA_POS                      4
-#define IRQ_PROG1_INTB_POS                      8
-#define IRQ_PROG2_INTA_POS                      12
-#define IRQ_PROG2_INTB_POS                      16
-#define IRQ_DMA1_WRRD0_POS                      20
-#define IRQ_DMA1_WRRD1_POS                      24
-#define IRQ_DMA2_WRRD0_POS                      28
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS                      0
-#define IRQ_IMDMA_WRRD0_POS                     4
-#define IRQ_IMDMA_WRRD1_POS                     8
-#define IRQ_WDTIMER_POS                 12
-#define IRQ_RESERVED_1_POS                      16
-#define IRQ_RESERVED_2_POS                      20
-#define IRQ_SUPPLE_0_POS                        24
-#define IRQ_SUPPLE_1_POS                        28
+#define IRQ_PROG0_INTB_POS      0
+#define IRQ_PROG1_INTA_POS      4
+#define IRQ_PROG1_INTB_POS      8
+#define IRQ_PROG2_INTA_POS      12
+#define IRQ_PROG2_INTB_POS      16
+#define IRQ_DMA1_WRRD0_POS      20
+#define IRQ_DMA1_WRRD1_POS      24
+#define IRQ_DMA2_WRRD0_POS      28
 
-#endif                          /* _BF561_IRQ_H_ */
+/* IAR7 BIT FIELDS */
+#define IRQ_DMA2_WRRD1_POS      0
+#define IRQ_IMDMA_WRRD0_POS     4
+#define IRQ_IMDMA_WRRD1_POS     8
+#define IRQ_WDTIMER_POS         12
+#define IRQ_RESERVED_1_POS      16
+#define IRQ_RESERVED_2_POS      20
+#define IRQ_SUPPLE_0_POS        24
+#define IRQ_SUPPLE_1_POS        28
+
+#endif
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 7b07740cf68c..85abd8be1343 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -24,17 +24,23 @@ static DEFINE_SPINLOCK(boot_lock);
 
 void __init platform_init_cpus(void)
 {
-        cpu_set(0, cpu_possible_map); /* CoreA */
-        cpu_set(1, cpu_possible_map); /* CoreB */
+        struct cpumask mask;
+
+        cpumask_set_cpu(0, &mask); /* CoreA */
+        cpumask_set_cpu(1, &mask); /* CoreB */
+        init_cpu_possible(&mask);
 }
 
 void __init platform_prepare_cpus(unsigned int max_cpus)
 {
+        struct cpumask mask;
+
         bfin_relocate_coreb_l1_mem();
 
         /* Both cores ought to be present on a bf561! */
-        cpu_set(0, cpu_present_map); /* CoreA */
-        cpu_set(1, cpu_present_map); /* CoreB */
+        cpumask_set_cpu(0, &mask); /* CoreA */
+        cpumask_set_cpu(1, &mask); /* CoreB */
+        init_cpu_present(&mask);
 }
 
 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
@@ -62,9 +68,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
         SSYNC();
 
-        /* Store CPU-private information to the cpu_data array. */
-        bfin_setup_cpudata(cpu);
-
         /* We are done with local CPU inits, unblock the boot CPU. */
         set_cpu_online(cpu, true);
         spin_lock(&boot_lock);
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
index 5e4112e518a9..f5685a496c58 100644
--- a/arch/blackfin/mach-common/dpmc.c
+++ b/arch/blackfin/mach-common/dpmc.c
@@ -85,10 +85,11 @@ static void bfin_wakeup_cpu(void)
 {
         unsigned int cpu;
         unsigned int this_cpu = smp_processor_id();
-        cpumask_t mask = cpu_online_map;
+        cpumask_t mask;
 
-        cpu_clear(this_cpu, mask);
-        for_each_cpu_mask(cpu, mask)
+        cpumask_copy(&mask, cpu_online_mask);
+        cpumask_clear_cpu(this_cpu, &mask);
+        for_each_cpu(cpu, &mask)
                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
 }
 
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index f96933f48a7f..225d311c9701 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -1753,6 +1753,8 @@ ENTRY(_sys_call_table)
         .long _sys_open_by_handle_at
         .long _sys_clock_adjtime
         .long _sys_syncfs
+        .long _sys_setns
+        .long _sys_sendmmsg             /* 380 */
 
         .rept NR_syscalls-(.-_sys_call_table)/4
         .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 43d9fb195c1e..1177369f9922 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -19,32 +19,14 @@
 #ifdef CONFIG_IPIPE
 #include <linux/ipipe.h>
 #endif
-#ifdef CONFIG_KGDB
-#include <linux/kgdb.h>
-#endif
 #include <asm/traps.h>
 #include <asm/blackfin.h>
 #include <asm/gpio.h>
 #include <asm/irq_handler.h>
 #include <asm/dpmc.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
 
 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
 
-#ifdef BF537_FAMILY
-# define BF537_GENERIC_ERROR_INT_DEMUX
-# define SPI_ERR_MASK   (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)     /* SPORT_STAT */
-# define PPI_ERR_MASK   (0xFFFF & ~FLD) /* PPI_STATUS */
-# define EMAC_ERR_MASK  (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-# define UART_ERR_MASK  (0x6)   /* UART_IIR */
-# define CAN_ERR_MASK   (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)      /* CAN_GIF */
-#else
-# undef BF537_GENERIC_ERROR_INT_DEMUX
-#endif
-
 /*
  * NOTES:
  * - we have separated the physical Hardware interrupt from the
@@ -63,22 +45,19 @@ unsigned long bfin_irq_flags = 0x1f;
 EXPORT_SYMBOL(bfin_irq_flags);
 #endif
 
-/* The number of spurious interrupts */
-atomic_t num_spurious;
-
 #ifdef CONFIG_PM
 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
 unsigned vr_wakeup;
 #endif
 
-struct ivgx {
+static struct ivgx {
         /* irq number for request_irq, available in mach-bf5xx/irq.h */
         unsigned int irqno;
         /* corresponding bit in the SIC_ISR register */
         unsigned int isrflag;
 } ivg_table[NR_PERI_INTS];
 
-struct ivg_slice {
+static struct ivg_slice {
         /* position of first irq in ivg_table for given ivg */
         struct ivgx *ifirst;
         struct ivgx *istop;
@@ -125,7 +104,7 @@ static void __init search_IAR(void)
  * This is for core internal IRQs
  */
 
-static void bfin_ack_noop(struct irq_data *d)
+void bfin_ack_noop(struct irq_data *d)
 {
         /* Dummy function.  */
 }
@@ -154,26 +133,24 @@ static void bfin_core_unmask_irq(struct irq_data *d)
         return;
 }
 
-static void bfin_internal_mask_irq(unsigned int irq)
+void bfin_internal_mask_irq(unsigned int irq)
 {
-        unsigned long flags;
+        unsigned long flags = hard_local_irq_save();
 
-#ifdef CONFIG_BF53x
-        flags = hard_local_irq_save();
-        bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
-                             ~(1 << SIC_SYSIRQ(irq)));
-#else
-        unsigned mask_bank, mask_bit;
-        flags = hard_local_irq_save();
-        mask_bank = SIC_SYSIRQ(irq) / 32;
-        mask_bit = SIC_SYSIRQ(irq) % 32;
+#ifdef SIC_IMASK0
+        unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
+        unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
                              ~(1 << mask_bit));
-#ifdef CONFIG_SMP
+# ifdef CONFIG_SMP
         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
                              ~(1 << mask_bit));
+# endif
+#else
+        bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
+                             ~(1 << SIC_SYSIRQ(irq)));
 #endif
-#endif
+
         hard_local_irq_restore(flags);
 }
 
@@ -186,33 +163,31 @@ static void bfin_internal_mask_irq_chip(struct irq_data *d)
 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
                 const struct cpumask *affinity)
 #else
-static void bfin_internal_unmask_irq(unsigned int irq)
+void bfin_internal_unmask_irq(unsigned int irq)
 #endif
 {
-        unsigned long flags;
+        unsigned long flags = hard_local_irq_save();
 
-#ifdef CONFIG_BF53x
-        flags = hard_local_irq_save();
-        bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
-                             (1 << SIC_SYSIRQ(irq)));
-#else
-        unsigned mask_bank, mask_bit;
-        flags = hard_local_irq_save();
-        mask_bank = SIC_SYSIRQ(irq) / 32;
-        mask_bit = SIC_SYSIRQ(irq) % 32;
-#ifdef CONFIG_SMP
+#ifdef SIC_IMASK0
+        unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
+        unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
+# ifdef CONFIG_SMP
         if (cpumask_test_cpu(0, affinity))
-#endif
+# endif
                 bfin_write_SIC_IMASK(mask_bank,
                         bfin_read_SIC_IMASK(mask_bank) |
                         (1 << mask_bit));
-#ifdef CONFIG_SMP
+# ifdef CONFIG_SMP
         if (cpumask_test_cpu(1, affinity))
                 bfin_write_SICB_IMASK(mask_bank,
                         bfin_read_SICB_IMASK(mask_bank) |
                         (1 << mask_bit));
+# endif
+#else
+        bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
+                             (1 << SIC_SYSIRQ(irq)));
 #endif
-#endif
+
         hard_local_irq_restore(flags);
 }
 
@@ -295,6 +270,8 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 {
         return bfin_internal_set_wake(d->irq, state);
 }
+#else
+# define bfin_internal_set_wake_chip NULL
 #endif
 
 static struct irq_chip bfin_core_irqchip = {
@@ -315,12 +292,10 @@ static struct irq_chip bfin_internal_irqchip = {
 #ifdef CONFIG_SMP
         .irq_set_affinity = bfin_internal_set_affinity,
 #endif
-#ifdef CONFIG_PM
         .irq_set_wake = bfin_internal_set_wake_chip,
-#endif
 };
 
-static void bfin_handle_irq(unsigned irq)
+void bfin_handle_irq(unsigned irq)
 {
 #ifdef CONFIG_IPIPE
         struct pt_regs regs;    /* Contents not used. */
@@ -332,102 +307,6 @@ static void bfin_handle_irq(unsigned irq)
 #endif  /* !CONFIG_IPIPE */
 }
 
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
-static int error_int_mask;
-
-static void bfin_generic_error_mask_irq(struct irq_data *d)
-{
-        error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
-        if (!error_int_mask)
-                bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bfin_generic_error_unmask_irq(struct irq_data *d)
-{
-        bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
-        error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bfin_generic_error_irqchip = {
-        .name = "ERROR",
-        .irq_ack = bfin_ack_noop,
-        .irq_mask_ack = bfin_generic_error_mask_irq,
-        .irq_mask = bfin_generic_error_mask_irq,
-        .irq_unmask = bfin_generic_error_unmask_irq,
-};
-
-static void bfin_demux_error_irq(unsigned int int_err_irq,
-                                 struct irq_desc *inta_desc)
-{
-        int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
-        if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
-                irq = IRQ_MAC_ERROR;
-        else
-#endif
-        if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
-                irq = IRQ_SPORT0_ERROR;
-        else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
-                irq = IRQ_SPORT1_ERROR;
-        else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
-                irq = IRQ_PPI_ERROR;
-        else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
-                irq = IRQ_CAN_ERROR;
-        else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
-                irq = IRQ_SPI_ERROR;
-        else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
-                irq = IRQ_UART0_ERROR;
-        else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
-                irq = IRQ_UART1_ERROR;
-
-        if (irq) {
-                if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
-                        bfin_handle_irq(irq);
-                else {
-
-                        switch (irq) {
-                        case IRQ_PPI_ERROR:
-                                bfin_write_PPI_STATUS(PPI_ERR_MASK);
-                                break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
-                        case IRQ_MAC_ERROR:
-                                bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
-                                break;
-#endif
-                        case IRQ_SPORT0_ERROR:
-                                bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
-                                break;
-
-                        case IRQ_SPORT1_ERROR:
-                                bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
-                                break;
-
-                        case IRQ_CAN_ERROR:
-                                bfin_write_CAN_GIS(CAN_ERR_MASK);
-                                break;
-
-                        case IRQ_SPI_ERROR:
-                                bfin_write_SPI_STAT(SPI_ERR_MASK);
-                                break;
-
-                        default:
-                                break;
-                        }
-
-                        pr_debug("IRQ %d:"
-                                 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
-                                 irq);
-                }
-        } else
-                printk(KERN_ERR
-                       "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
-                       " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
-                       __func__, __FILE__, __LINE__);
-
-}
-#endif                          /* BF537_GENERIC_ERROR_INT_DEMUX */
-
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 static int mac_stat_int_mask;
 
@@ -468,7 +347,7 @@ static void bfin_mac_status_mask_irq(struct irq_data *d)
         unsigned int irq = d->irq;
 
         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
         switch (irq) {
         case IRQ_MAC_PHYINT:
                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
@@ -487,7 +366,7 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d)
 {
         unsigned int irq = d->irq;
 
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
         switch (irq) {
         case IRQ_MAC_PHYINT:
                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
@@ -505,12 +384,14 @@ static void bfin_mac_status_unmask_irq(struct irq_data *d)
 #ifdef CONFIG_PM
 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 {
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 #else
         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 #endif
 }
+#else
+# define bfin_mac_status_set_wake NULL
 #endif
 
 static struct irq_chip bfin_mac_status_irqchip = {
@@ -519,13 +400,11 @@ static struct irq_chip bfin_mac_status_irqchip = {
         .irq_mask_ack = bfin_mac_status_mask_irq,
         .irq_mask = bfin_mac_status_mask_irq,
         .irq_unmask = bfin_mac_status_unmask_irq,
-#ifdef CONFIG_PM
         .irq_set_wake = bfin_mac_status_set_wake,
-#endif
 };
 
-static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
-                                 struct irq_desc *inta_desc)
+void bfin_demux_mac_status_irq(unsigned int int_err_irq,
+                               struct irq_desc *inta_desc)
 {
         int i, irq = 0;
         u32 status = bfin_read_EMAC_SYSTAT();
@@ -680,29 +559,48 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 }
 
 #ifdef CONFIG_PM
-int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
+static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 {
         return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
 }
+#else
+# define bfin_gpio_set_wake NULL
 #endif
 
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
-                                struct irq_desc *desc)
+static void bfin_demux_gpio_block(unsigned int irq)
 {
-        unsigned int i, gpio, mask, irq, search = 0;
+        unsigned int gpio, mask;
+
+        gpio = irq_to_gpio(irq);
+        mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
+
+        while (mask) {
+                if (mask & 1)
+                        bfin_handle_irq(irq);
+                irq++;
+                mask >>= 1;
+        }
+}
+
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+                         struct irq_desc *desc)
+{
+        unsigned int irq;
 
         switch (inta_irq) {
-#if defined(CONFIG_BF53x)
-        case IRQ_PROG_INTA:
-                irq = IRQ_PF0;
-                search = 1;
+#if defined(BF537_FAMILY)
+        case IRQ_PF_INTA_PG_INTA:
+                bfin_demux_gpio_block(IRQ_PF0);
+                irq = IRQ_PG0;
                 break;
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
-        case IRQ_MAC_RX:
+        case IRQ_PH_INTA_MAC_RX:
                 irq = IRQ_PH0;
                 break;
-# endif
-#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+#elif defined(BF533_FAMILY)
+        case IRQ_PROG_INTA:
+                irq = IRQ_PF0;
+                break;
+#elif defined(BF538_FAMILY)
         case IRQ_PORTF_INTA:
                 irq = IRQ_PF0;
                 break;
@@ -732,31 +630,7 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
                 return;
         }
 
-        if (search) {
-                for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
-                        irq += i;
-
-                        mask = get_gpiop_data(i) & get_gpiop_maska(i);
-
-                        while (mask) {
-                                if (mask & 1)
-                                        bfin_handle_irq(irq);
-                                irq++;
-                                mask >>= 1;
-                        }
-                }
-        } else {
-                        gpio = irq_to_gpio(irq);
-                        mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
-                        do {
-                                if (mask & 1)
-                                        bfin_handle_irq(irq);
-                                irq++;
-                                mask >>= 1;
-                        } while (mask);
-        }
-
+        bfin_demux_gpio_block(irq);
 }
 
 #else                           /* CONFIG_BF54x */
@@ -974,15 +848,11 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 }
 
 #ifdef CONFIG_PM
-u32 pint_saved_masks[NR_PINT_SYS_IRQS];
-u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
-
-int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
+static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 {
         u32 pint_irq;
         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
         u32 bank = PINT_2_BANK(pint_val);
-        u32 pintbit = PINT_BIT(pint_val);
 
         switch (bank) {
         case 0:
@@ -1003,46 +873,14 @@ int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 
         bfin_internal_set_wake(pint_irq, state);
 
-        if (state)
-                pint_wakeup_masks[bank] |= pintbit;
-        else
-                pint_wakeup_masks[bank] &= ~pintbit;
-
         return 0;
 }
-
-u32 bfin_pm_setup(void)
-{
-        u32 val, i;
-
-        for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
-                val = pint[i]->mask_clear;
-                pint_saved_masks[i] = val;
-                if (val ^ pint_wakeup_masks[i]) {
-                        pint[i]->mask_clear = val;
-                        pint[i]->mask_set = pint_wakeup_masks[i];
-                }
-        }
-
-        return 0;
-}
-
-void bfin_pm_restore(void)
-{
-        u32 i, val;
-
-        for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
-                val = pint_saved_masks[i];
-                if (val ^ pint_wakeup_masks[i]) {
-                        pint[i]->mask_clear = pint[i]->mask_clear;
-                        pint[i]->mask_set = val;
-                }
-        }
-}
+#else
+# define bfin_gpio_set_wake NULL
 #endif
 
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
-                                struct irq_desc *desc)
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+                         struct irq_desc *desc)
 {
         u32 bank, pint_val;
         u32 request, irq;
@@ -1091,9 +929,7 @@ static struct irq_chip bfin_gpio_irqchip = {
         .irq_set_type = bfin_gpio_irq_type,
         .irq_startup = bfin_gpio_irq_startup,
         .irq_shutdown = bfin_gpio_irq_shutdown,
-#ifdef CONFIG_PM
         .irq_set_wake = bfin_gpio_set_wake,
-#endif
 };
 
 void __cpuinit init_exception_vectors(void)
@@ -1127,12 +963,12 @@ int __init init_arch_irq(void)
 {
         int irq;
         unsigned long ilat = 0;
+
         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
-        || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
+#ifdef SIC_IMASK0
         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef CONFIG_BF54x
+# ifdef SIC_IMASK2
         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 # endif
 # ifdef CONFIG_SMP
@@ -1145,11 +981,6 @@ int __init init_arch_irq(void)
 
         local_irq_disable();
 
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
-        /* Clear EMAC Interrupt Status bits so we can demux it later */
-        bfin_write_EMAC_SYSTAT(-1);
-#endif
-
 #ifdef CONFIG_BF54x
 # ifdef CONFIG_PINTx_REASSIGN
         pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1168,11 +999,11 @@ int __init init_arch_irq(void)
                         irq_set_chip(irq, &bfin_internal_irqchip);
 
                 switch (irq) {
-#if defined(CONFIG_BF53x)
+#if defined(BF537_FAMILY)
+                case IRQ_PH_INTA_MAC_RX:
+                case IRQ_PF_INTA_PG_INTA:
+#elif defined(BF533_FAMILY)
                 case IRQ_PROG_INTA:
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
-                case IRQ_MAC_RX:
-# endif
 #elif defined(CONFIG_BF54x)
                 case IRQ_PINT0:
                 case IRQ_PINT1:
@@ -1186,16 +1017,11 @@ int __init init_arch_irq(void)
                 case IRQ_PROG0_INTA:
                 case IRQ_PROG1_INTA:
                 case IRQ_PROG2_INTA:
-#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+#elif defined(BF538_FAMILY)
                 case IRQ_PORTF_INTA:
 #endif
                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
                         break;
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
-                case IRQ_GENERIC_ERROR:
-                        irq_set_chained_handler(irq, bfin_demux_error_irq);
-                        break;
-#endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
                 case IRQ_MAC_ERROR:
                         irq_set_chained_handler(irq,
@@ -1213,11 +1039,10 @@ int __init init_arch_irq(void)
                 case IRQ_CORETMR:
 # ifdef CONFIG_SMP
                         irq_set_handler(irq, handle_percpu_irq);
-                        break;
 # else
                         irq_set_handler(irq, handle_simple_irq);
-                        break;
 # endif
+                        break;
 #endif
 
 #ifdef CONFIG_TICKSOURCE_GPTMR0
@@ -1226,26 +1051,17 @@ int __init init_arch_irq(void)
                         break;
 #endif
 
-#ifdef CONFIG_IPIPE
                 default:
+#ifdef CONFIG_IPIPE
                         irq_set_handler(irq, handle_level_irq);
-                        break;
-#else /* !CONFIG_IPIPE */
-                default:
+#else
                         irq_set_handler(irq, handle_simple_irq);
+#endif
                         break;
-#endif /* !CONFIG_IPIPE */
                 }
         }
 
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
-        for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
-                irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
-                                         handle_level_irq);
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-        irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-#endif
+        init_mach_irq();
 
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
@@ -1307,53 +1123,54 @@ int __init init_arch_irq(void)
 #ifdef CONFIG_DO_IRQ_L1
 __attribute__((l1_text))
 #endif
-void do_irq(int vec, struct pt_regs *fp)
+static int vec_to_irq(int vec)
 {
-        if (vec == EVT_IVTMR_P) {
-                vec = IRQ_CORETMR;
-        } else {
-                struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
-                struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
-#if defined(SIC_ISR0)
-                unsigned long sic_status[3];
+        struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
+        struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
+        unsigned long sic_status[3];
+
+        if (likely(vec == EVT_IVTMR_P))
+                return IRQ_CORETMR;
 
-                if (smp_processor_id()) {
+#ifdef SIC_ISR
+        sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
+#else
+        if (smp_processor_id()) {
 # ifdef SICB_ISR0
-                        /* This will be optimized out in UP mode. */
-                        sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
-                        sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
-                } else {
-                        sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
-                        sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
-                }
-# ifdef SIC_ISR2
-                sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
+                /* This will be optimized out in UP mode. */
+                sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
+                sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
 # endif
-                for (;; ivg++) {
-                        if (ivg >= ivg_stop) {
-                                atomic_inc(&num_spurious);
-                                return;
-                        }
-                        if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
-                                break;
-                }
-#else
-                unsigned long sic_status;
-
-                sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
+        } else {
+                sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
+                sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+        }
+#endif
+#ifdef SIC_ISR2
+        sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
+#endif
 
-                for (;; ivg++) {
-                        if (ivg >= ivg_stop) {
-                                atomic_inc(&num_spurious);
-                                return;
-                        } else if (sic_status & ivg->isrflag)
-                                break;
-                }
+        for (;; ivg++) {
+                if (ivg >= ivg_stop)
+                        return -1;
+#ifdef SIC_ISR
+                if (sic_status[0] & ivg->isrflag)
+#else
+                if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
 #endif
-                vec = ivg->irqno;
+                        return ivg->irqno;
         }
-        asm_do_IRQ(vec, fp);
+}
+
+#ifdef CONFIG_DO_IRQ_L1
+__attribute__((l1_text))
+#endif
+void do_irq(int vec, struct pt_regs *fp)
+{
+        int irq = vec_to_irq(vec);
+        if (irq == -1)
+                return;
+        asm_do_IRQ(irq, fp);
 }
 
 #ifdef CONFIG_IPIPE
@@ -1391,40 +1208,9 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
         struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
         int irq, s = 0;
 
-        if (likely(vec == EVT_IVTMR_P))
-                irq = IRQ_CORETMR;
-        else {
-#if defined(SIC_ISR0)
-                unsigned long sic_status[3];
-
-                sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
-                sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
-# ifdef SIC_ISR2
-                sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-# endif
-                for (;; ivg++) {
-                        if (ivg >= ivg_stop) {
-                                atomic_inc(&num_spurious);
-                                return 0;
-                        }
-                        if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
-                                break;
-                }
-#else
-                unsigned long sic_status;
-
-                sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-
-                for (;; ivg++) {
-                        if (ivg >= ivg_stop) {
-                                atomic_inc(&num_spurious);
-                                return 0;
-                        } else if (sic_status & ivg->isrflag)
-                                break;
-                }
-#endif
-                irq = ivg->irqno;
-        }
+        irq = vec_to_irq(vec);
+        if (irq == -1)
+                return 0;
 
         if (irq == IRQ_SYSTMR) {
 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 1fbd94c44457..35e7e1eb0188 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -25,6 +25,7 @@
 #include <linux/slab.h>
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
+#include <asm/irq_handler.h>
 #include <asm/mmu_context.h>
 #include <asm/pgtable.h>
 #include <asm/pgalloc.h>
@@ -96,7 +97,7 @@ static void ipi_cpu_stop(unsigned int cpu)
         dump_stack();
         spin_unlock(&stop_lock);
 
-        cpu_clear(cpu, cpu_online_map);
+        set_cpu_online(cpu, false);
 
         local_irq_disable();
 
@@ -146,7 +147,7 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
                  */
                 resync_core_dcache();
 #endif
-                cpu_clear(cpu, *msg->call_struct.waitmask);
+                cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
         }
 }
 
@@ -222,9 +223,10 @@ static inline void smp_send_message(cpumask_t callmap, unsigned long type,
         struct ipi_message_queue *msg_queue;
         struct ipi_message *msg;
         unsigned long flags, next_msg;
-        cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
+        cpumask_t waitmask; /* waitmask is shared by all cpus */
 
-        for_each_cpu_mask(cpu, callmap) {
+        cpumask_copy(&waitmask, &callmap);
+        for_each_cpu(cpu, &callmap) {
                 msg_queue = &per_cpu(ipi_msg_queue, cpu);
                 spin_lock_irqsave(&msg_queue->lock, flags);
                 if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
@@ -246,7 +248,7 @@ static inline void smp_send_message(cpumask_t callmap, unsigned long type,
         }
 
         if (wait) {
-                while (!cpus_empty(waitmask))
+                while (!cpumask_empty(&waitmask))
                         blackfin_dcache_invalidate_range(
                                 (unsigned long)(&waitmask),
                                 (unsigned long)(&waitmask));
@@ -265,9 +267,9 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
         cpumask_t callmap;
 
         preempt_disable();
-        callmap = cpu_online_map;
-        cpu_clear(smp_processor_id(), callmap);
-        if (!cpus_empty(callmap))
+        cpumask_copy(&callmap, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &callmap);
+        if (!cpumask_empty(&callmap))
                 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 
         preempt_enable();
@@ -284,8 +286,8 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
 
         if (cpu_is_offline(cpu))
                 return 0;
-        cpus_clear(callmap);
-        cpu_set(cpu, callmap);
+        cpumask_clear(&callmap);
+        cpumask_set_cpu(cpu, &callmap);
 
         smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
 
@@ -308,9 +310,9 @@ void smp_send_stop(void)
         cpumask_t callmap;
 
         preempt_disable();
-        callmap = cpu_online_map;
-        cpu_clear(smp_processor_id(), callmap);
-        if (!cpus_empty(callmap))
+        cpumask_copy(&callmap, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &callmap);
+        if (!cpumask_empty(&callmap))
                 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
 
         preempt_enable();
diff --git a/arch/blackfin/mm/maccess.c b/arch/blackfin/mm/maccess.c
index b71cebc1f8a3..e2532114c5fd 100644
--- a/arch/blackfin/mm/maccess.c
+++ b/arch/blackfin/mm/maccess.c
@@ -16,7 +16,7 @@ static int validate_memory_access_address(unsigned long addr, int size)
         return bfin_mem_access_type(addr, size);
 }
 
-long probe_kernel_read(void *dst, void *src, size_t size)
+long probe_kernel_read(void *dst, const void *src, size_t size)
 {
         unsigned long lsrc = (unsigned long)src;
         int mem_type;
@@ -55,7 +55,7 @@ long probe_kernel_read(void *dst, void *src, size_t size)
         return -EFAULT;
 }
 
-long probe_kernel_write(void *dst, void *src, size_t size)
+long probe_kernel_write(void *dst, const void *src, size_t size)
 {
         unsigned long ldst = (unsigned long)dst;
         int mem_type;
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index dfd304a4a3ea..29d98faa1efd 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -15,6 +15,7 @@
 #include <linux/init.h>
 #include <linux/poll.h>
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/spinlock.h>
 #include <linux/rtc.h>
 #include <linux/slab.h>
@@ -764,7 +765,7 @@ EXPORT_SYMBOL(sram_alloc_with_lsl);
 /* Need to keep line of output the same.  Currently, that is 44 bytes
  * (including newline).
  */
-static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
+static int _sram_proc_show(struct seq_file *m, const char *desc,
                 struct sram_piece *pfree_head,
                 struct sram_piece *pused_head)
 {
@@ -773,13 +774,13 @@ static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
         if (!pfree_head || !pused_head)
                 return -1;
 
-        *len += sprintf(&buf[*len], "--- SRAM %-14s Size   PID State     \n", desc);
+        seq_printf(m, "--- SRAM %-14s Size   PID State     \n", desc);
 
         /* search the relevant memory slot */
         pslot = pused_head->next;
 
         while (pslot != NULL) {
-                *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n",
+                seq_printf(m, "%p-%p %10i %5i %-10s\n",
                         pslot->paddr, pslot->paddr + pslot->size,
                         pslot->size, pslot->pid, "ALLOCATED");
 
@@ -789,7 +790,7 @@ static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
         pslot = pfree_head->next;
 
         while (pslot != NULL) {
-                *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n",
+                seq_printf(m, "%p-%p %10i %5i %-10s\n",
                         pslot->paddr, pslot->paddr + pslot->size,
                         pslot->size, pslot->pid, "FREE");
 
@@ -798,54 +799,62 @@ static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
 
         return 0;
 }
-static int sram_proc_read(char *buf, char **start, off_t offset, int count,
-                int *eof, void *data)
+static int sram_proc_show(struct seq_file *m, void *v)
 {
-        int len = 0;
         unsigned int cpu;
 
         for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
-                if (_sram_proc_read(buf, &len, count, "Scratchpad",
+                if (_sram_proc_show(m, "Scratchpad",
                         &per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
                         goto not_done;
 #if L1_DATA_A_LENGTH != 0
-                if (_sram_proc_read(buf, &len, count, "L1 Data A",
+                if (_sram_proc_show(m, "L1 Data A",
                         &per_cpu(free_l1_data_A_sram_head, cpu),
                         &per_cpu(used_l1_data_A_sram_head, cpu)))
                         goto not_done;
 #endif
 #if L1_DATA_B_LENGTH != 0
-                if (_sram_proc_read(buf, &len, count, "L1 Data B",
+                if (_sram_proc_show(m, "L1 Data B",
                         &per_cpu(free_l1_data_B_sram_head, cpu),
                         &per_cpu(used_l1_data_B_sram_head, cpu)))
                         goto not_done;
 #endif
 #if L1_CODE_LENGTH != 0
-                if (_sram_proc_read(buf, &len, count, "L1 Instruction",
+                if (_sram_proc_show(m, "L1 Instruction",
                         &per_cpu(free_l1_inst_sram_head, cpu),
                         &per_cpu(used_l1_inst_sram_head, cpu)))
                         goto not_done;
 #endif
         }
 #if L2_LENGTH != 0
-        if (_sram_proc_read(buf, &len, count, "L2", &free_l2_sram_head,
-                &used_l2_sram_head))
+        if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
                 goto not_done;
 #endif
-        *eof = 1;
  not_done:
-        return len;
+        return 0;
+}
+
+static int sram_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, sram_proc_show, NULL);
 }
 
+static const struct file_operations sram_proc_ops = {
+        .open           = sram_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
 static int __init sram_proc_init(void)
 {
         struct proc_dir_entry *ptr;
-        ptr = create_proc_entry("sram", S_IFREG | S_IRUGO, NULL);
+
+        ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
         if (!ptr) {
                 printk(KERN_WARNING "unable to create /proc/sram\n");
                 return -1;
         }
-        ptr->read_proc = sram_proc_read;
         return 0;
 }
 late_initcall(sram_proc_init);
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index a6d03069d0ff..17addacb169e 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -31,10 +31,6 @@ config ARCH_HAS_ILOG2_U64
         bool
         default n
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
 config GENERIC_HWEIGHT
         bool
         default y
@@ -274,7 +270,6 @@ config ETRAX_AXISFLASHMAP
         select MTD_JEDECPROBE if ETRAX_ARCH_V32
         select MTD_CHAR
         select MTD_BLOCK
-        select MTD_PARTITIONS
         select MTD_COMPLEX_MAPPINGS
         help
           This option enables MTD mapping of flash devices.  Needed to use
diff --git a/arch/cris/arch-v10/drivers/axisflashmap.c b/arch/cris/arch-v10/drivers/axisflashmap.c
index ed708e19d09e..a4bbdfd37bd8 100644
--- a/arch/cris/arch-v10/drivers/axisflashmap.c
+++ b/arch/cris/arch-v10/drivers/axisflashmap.c
@@ -372,7 +372,7 @@ static int __init init_axis_flash(void)
 #ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
         if (mymtd) {
                 main_partition.size = mymtd->size;
-                err = add_mtd_partitions(mymtd, &main_partition, 1);
+                err = mtd_device_register(mymtd, &main_partition, 1);
                 if (err)
                         panic("axisflashmap: Could not initialize "
                               "partition for whole main mtd device!\n");
@@ -382,10 +382,12 @@ static int __init init_axis_flash(void)
         if (mymtd) {
                 if (use_default_ptable) {
                         printk(KERN_INFO " Using default partition table.\n");
-                        err = add_mtd_partitions(mymtd, axis_default_partitions,
-                                                 NUM_DEFAULT_PARTITIONS);
+                        err = mtd_device_register(mymtd,
+                                                  axis_default_partitions,
+                                                  NUM_DEFAULT_PARTITIONS);
                 } else {
-                        err = add_mtd_partitions(mymtd, axis_partitions, pidx);
+                        err = mtd_device_register(mymtd, axis_partitions,
+                                                  pidx);
                 }
 
                 if (err)
diff --git a/arch/cris/arch-v10/kernel/entry.S b/arch/cris/arch-v10/kernel/entry.S
index 0d6420d087fd..1161883eb582 100644
--- a/arch/cris/arch-v10/kernel/entry.S
+++ b/arch/cris/arch-v10/kernel/entry.S
@@ -937,6 +937,7 @@ sys_call_table:
         .long sys_inotify_init1
         .long sys_preadv
         .long sys_pwritev
+        .long sys_setns                 /* 335 */
 
         /*
          * NOTE!! This doesn't have to be exact - we just have
diff --git a/arch/cris/arch-v32/drivers/Kconfig b/arch/cris/arch-v32/drivers/Kconfig
index 1633b120aa81..41a2732e8b9c 100644
--- a/arch/cris/arch-v32/drivers/Kconfig
+++ b/arch/cris/arch-v32/drivers/Kconfig
@@ -405,7 +405,6 @@ config ETRAX_AXISFLASHMAP
         select MTD_JEDECPROBE
         select MTD_CHAR
         select MTD_BLOCK
-        select MTD_PARTITIONS
         select MTD_COMPLEX_MAPPINGS
         help
           This option enables MTD mapping of flash devices.  Needed to use
diff --git a/arch/cris/arch-v32/drivers/axisflashmap.c b/arch/cris/arch-v32/drivers/axisflashmap.c
index 7b155f8203b8..a2bde3744622 100644
--- a/arch/cris/arch-v32/drivers/axisflashmap.c
+++ b/arch/cris/arch-v32/drivers/axisflashmap.c
@@ -561,7 +561,7 @@ static int __init init_axis_flash(void)
 #ifdef CONFIG_ETRAX_AXISFLASHMAP_MTD0WHOLE
         if (main_mtd) {
                 main_partition.size = main_mtd->size;
-                err = add_mtd_partitions(main_mtd, &main_partition, 1);
+                err = mtd_device_register(main_mtd, &main_partition, 1);
                 if (err)
                         panic("axisflashmap: Could not initialize "
                               "partition for whole main mtd device!\n");
@@ -597,7 +597,8 @@ static int __init init_axis_flash(void)
                         mtd_ram->erasesize = (main_mtd ? main_mtd->erasesize :
                                 CONFIG_ETRAX_PTABLE_SECTOR);
                 } else {
-                        err = add_mtd_partitions(main_mtd, &partition[part], 1);
+                        err = mtd_device_register(main_mtd, &partition[part],
+                                                  1);
                         if (err)
                                 panic("axisflashmap: Could not add mtd "
                                         "partition %d\n", part);
@@ -633,7 +634,7 @@ static int __init init_axis_flash(void)
 #ifndef CONFIG_ETRAX_VCS_SIM
         if (aux_mtd) {
                 aux_partition.size = aux_mtd->size;
-                err = add_mtd_partitions(aux_mtd, &aux_partition, 1);
+                err = mtd_device_register(aux_mtd, &aux_partition, 1);
                 if (err)
                         panic("axisflashmap: Could not initialize "
                               "aux mtd device!\n");
diff --git a/arch/cris/arch-v32/kernel/entry.S b/arch/cris/arch-v32/kernel/entry.S
index 3abf12c23e5f..84fed7e91ada 100644
--- a/arch/cris/arch-v32/kernel/entry.S
+++ b/arch/cris/arch-v32/kernel/entry.S
@@ -880,6 +880,7 @@ sys_call_table:
         .long sys_inotify_init1
         .long sys_preadv
         .long sys_pwritev
+        .long sys_setns                 /* 335 */
 
         /*
          * NOTE!! This doesn't have to be exact - we just have
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index 68a1a5901ca5..5ebe6e841820 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -266,11 +266,11 @@ static int irq_cpu(int irq)
 
 
         /* Let the interrupt stay if possible */
-        if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))
+        if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
                 goto out;
 
         /* IRQ must be moved to another CPU. */
-        cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);
+        cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
         irq_allocations[irq - FIRST_IRQ].cpu = cpu;
 out:
         spin_unlock_irqrestore(&irq_lock, flags);
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
index 66cc75657e2f..a0843a71aaee 100644
--- a/arch/cris/arch-v32/kernel/smp.c
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -81,7 +81,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 
         /* Mark all possible CPUs as present */
         for (i = 0; i < max_cpus; i++)
-            cpu_set(i, phys_cpu_present_map);
+                cpumask_set_cpu(i, &phys_cpu_present_map);
 }
 
 void __devinit smp_prepare_boot_cpu(void)
@@ -98,7 +98,7 @@ void __devinit smp_prepare_boot_cpu(void)
         SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
 
         set_cpu_online(0, true);
-        cpu_set(0, phys_cpu_present_map);
+        cpumask_set_cpu(0, &phys_cpu_present_map);
         set_cpu_possible(0, true);
 }
 
@@ -112,8 +112,9 @@ smp_boot_one_cpu(int cpuid)
 {
         unsigned timeout;
         struct task_struct *idle;
-        cpumask_t cpu_mask = CPU_MASK_NONE;
+        cpumask_t cpu_mask;
 
+        cpumask_clear(&cpu_mask);
         idle = fork_idle(cpuid);
         if (IS_ERR(idle))
                 panic("SMP: fork failed for CPU:%d", cpuid);
@@ -125,10 +126,10 @@ smp_boot_one_cpu(int cpuid)
         cpu_now_booting = cpuid;
 
         /* Kick it */
-        cpu_set(cpuid, cpu_online_map);
-        cpu_set(cpuid, cpu_mask);
+        set_cpu_online(cpuid, true);
+        cpumask_set_cpu(cpuid, &cpu_mask);
         send_ipi(IPI_BOOT, 0, cpu_mask);
-        cpu_clear(cpuid, cpu_online_map);
+        set_cpu_online(cpuid, false);
 
         /* Wait for CPU to come online */
         for (timeout = 0; timeout < 10000; timeout++) {
@@ -176,7 +177,7 @@ void __init smp_callin(void)
         notify_cpu_starting(cpu);
         local_irq_enable();
 
-        cpu_set(cpu, cpu_online_map);
+        set_cpu_online(cpu, true);
         cpu_idle();
 }
 
@@ -214,8 +215,9 @@ int __cpuinit __cpu_up(unsigned int cpu)
 
 void smp_send_reschedule(int cpu)
 {
-        cpumask_t cpu_mask = CPU_MASK_NONE;
-        cpu_set(cpu, cpu_mask);
+        cpumask_t cpu_mask;
+        cpumask_clear(&cpu_mask);
+        cpumask_set_cpu(cpu, &cpu_mask);
         send_ipi(IPI_SCHEDULE, 0, cpu_mask);
 }
 
@@ -232,7 +234,7 @@ void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned
 
         spin_lock_irqsave(&tlbstate_lock, flags);
         cpu_mask = (mm == FLUSH_ALL ? cpu_all_mask : *mm_cpumask(mm));
-        cpu_clear(smp_processor_id(), cpu_mask);
+        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
         flush_mm = mm;
         flush_vma = vma;
         flush_addr = addr;
@@ -277,10 +279,10 @@ int send_ipi(int vector, int wait, cpumask_t cpu_mask)
         int ret = 0;
 
         /* Calculate CPUs to send to. */
-        cpus_and(cpu_mask, cpu_mask, cpu_online_map);
+        cpumask_and(&cpu_mask, &cpu_mask, cpu_online_mask);
 
         /* Send the IPI. */
-        for_each_cpu_mask(i, cpu_mask)
+        for_each_cpu(i, &cpu_mask)
         {
                 ipi.vector |= vector;
                 REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
@@ -288,7 +290,7 @@ int send_ipi(int vector, int wait, cpumask_t cpu_mask)
 
         /* Wait for IPI to finish on other CPUS */
         if (wait) {
-                for_each_cpu_mask(i, cpu_mask) {
+                for_each_cpu(i, &cpu_mask) {
                         int j;
                         for (j = 0 ; j < 1000; j++) {
                                 ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
@@ -314,11 +316,12 @@ int send_ipi(int vector, int wait, cpumask_t cpu_mask)
  */
 int smp_call_function(void (*func)(void *info), void *info, int wait)
 {
-        cpumask_t cpu_mask = CPU_MASK_ALL;
+        cpumask_t cpu_mask;
         struct call_data_struct data;
         int ret;
 
-        cpu_clear(smp_processor_id(), cpu_mask);
+        cpumask_setall(&cpu_mask);
+        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
 
         WARN_ON(irqs_disabled());
 
diff --git a/arch/cris/include/asm/unistd.h b/arch/cris/include/asm/unistd.h
index f6fad83b3a8c..f921b8b0f97e 100644
--- a/arch/cris/include/asm/unistd.h
+++ b/arch/cris/include/asm/unistd.h
@@ -339,10 +339,11 @@
 #define __NR_inotify_init1      332
 #define __NR_preadv             333
 #define __NR_pwritev            334
+#define __NR_setns              335
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 335
+#define NR_syscalls 336
 
 #include <arch/unistd.h>
 
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
index 728bbd9e7d4c..a6990cb0f098 100644
--- a/arch/cris/kernel/vmlinux.lds.S
+++ b/arch/cris/kernel/vmlinux.lds.S
@@ -102,7 +102,7 @@ SECTIONS
 #endif
         __vmlinux_end = .;              /* Last address of the physical file. */
 #ifdef CONFIG_ETRAX_ARCH_V32
-        PERCPU(32, PAGE_SIZE)
+        PERCPU_SECTION(32)
 
         .init.ramfs : {
                 INIT_RAM_FS
diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c
index df33ab89d70f..d72ab58fd83e 100644
--- a/arch/cris/mm/init.c
+++ b/arch/cris/mm/init.c
@@ -13,8 +13,6 @@
 #include <linux/bootmem.h>
 #include <asm/tlb.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 unsigned long empty_zero_page;
 
 extern char _stext, _edata, _etext; /* From linkerscript */
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index 064f62196745..cb884e489425 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -19,14 +19,6 @@ config RWSEM_GENERIC_SPINLOCK
 config RWSEM_XCHGADD_ALGORITHM
         bool
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_HWEIGHT
         bool
         default y
diff --git a/arch/frv/include/asm/suspend.h b/arch/frv/include/asm/suspend.h
deleted file mode 100644
index 5fa7b5a6ee40..000000000000
--- a/arch/frv/include/asm/suspend.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* suspend.h: suspension stuff
- *
- * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#ifndef _ASM_SUSPEND_H
-#define _ASM_SUSPEND_H
-
-static inline int arch_prepare_suspend(void)
-{
-        return 0;
-}
-
-#endif /* _ASM_SUSPEND_H */
diff --git a/arch/frv/include/asm/unistd.h b/arch/frv/include/asm/unistd.h
index b28da499e22a..a569dff7cd59 100644
--- a/arch/frv/include/asm/unistd.h
+++ b/arch/frv/include/asm/unistd.h
@@ -343,10 +343,11 @@
 #define __NR_pwritev            334
 #define __NR_rt_tgsigqueueinfo  335
 #define __NR_perf_event_open    336
+#define __NR_setns              337
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 337
+#define NR_syscalls 338
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 /* #define __ARCH_WANT_OLD_READDIR */
diff --git a/arch/frv/kernel/entry.S b/arch/frv/kernel/entry.S
index 63d579bf1c29..017d6d7b784f 100644
--- a/arch/frv/kernel/entry.S
+++ b/arch/frv/kernel/entry.S
@@ -1526,5 +1526,6 @@ sys_call_table:
         .long sys_pwritev
         .long sys_rt_tgsigqueueinfo     /* 335 */
         .long sys_perf_event_open
+        .long sys_setns
 
 syscall_table_size = (. - sys_call_table)
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
index 0daae8af5787..7e958d829ec9 100644
--- a/arch/frv/kernel/vmlinux.lds.S
+++ b/arch/frv/kernel/vmlinux.lds.S
@@ -37,7 +37,7 @@ SECTIONS
   _einittext = .;
 
   INIT_DATA_SECTION(8)
-  PERCPU(L1_CACHE_BYTES, 4096)
+  PERCPU_SECTION(L1_CACHE_BYTES)
 
   . = ALIGN(PAGE_SIZE);
   __init_end = .;
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index ed64588ac3a7..fbe5f0dbae06 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -41,8 +41,6 @@
 
 #undef DEBUG
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * BAD_PAGE is the page that is used for page faults when linux
  * is out-of-memory. Older versions of linux just did a
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index e20322ffcaf8..091ed6192ae8 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -41,14 +41,6 @@ config ARCH_HAS_ILOG2_U64
         bool
         default n
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_HWEIGHT
         bool
         default y
diff --git a/arch/h8300/include/asm/unistd.h b/arch/h8300/include/asm/unistd.h
index 50f2c5a36591..2c3f8e60b1e0 100644
--- a/arch/h8300/include/asm/unistd.h
+++ b/arch/h8300/include/asm/unistd.h
@@ -325,10 +325,11 @@
 #define __NR_move_pages         317
 #define __NR_getcpu             318
 #define __NR_epoll_pwait        319
+#define __NR_setns              320
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 320
+#define NR_syscalls 321
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/h8300/kernel/syscalls.S b/arch/h8300/kernel/syscalls.S
index faefaff7d43d..f4b2e67bcc34 100644
--- a/arch/h8300/kernel/syscalls.S
+++ b/arch/h8300/kernel/syscalls.S
@@ -333,6 +333,7 @@ SYMBOL_NAME_LABEL(sys_call_table)
         .long SYMBOL_NAME(sys_ni_syscall)       /* sys_move_pages */
         .long SYMBOL_NAME(sys_getcpu)
         .long SYMBOL_NAME(sys_ni_syscall)       /* sys_epoll_pwait */
+        .long SYMBOL_NAME(sys_setns)            /* 320 */
 
         .macro  call_sp addr
         mov.l   #SYMBOL_NAME(\addr),er6
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index e5cc56ae6ce3..38280ef4a2af 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -78,10 +78,6 @@ config HUGETLB_PAGE_SIZE_VARIABLE
         depends on HUGETLB_PAGE
         default y
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
 config GENERIC_CALIBRATE_DELAY
         bool
         default y
diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h
index 23cce999eb1c..c3ffe3e54edc 100644
--- a/arch/ia64/include/asm/tlb.h
+++ b/arch/ia64/include/asm/tlb.h
@@ -47,21 +47,27 @@
 #include <asm/machvec.h>
 
 #ifdef CONFIG_SMP
-# define FREE_PTE_NR            2048
 # define tlb_fast_mode(tlb)     ((tlb)->nr == ~0U)
 #else
-# define FREE_PTE_NR            0
 # define tlb_fast_mode(tlb)     (1)
 #endif
 
+/*
+ * If we can't allocate a page to make a big batch of page pointers
+ * to work on, then just handle a few from the on-stack structure.
+ */
+#define IA64_GATHER_BUNDLE      8
+
 struct mmu_gather {
         struct mm_struct        *mm;
         unsigned int            nr;             /* == ~0U => fast mode */
+        unsigned int            max;
         unsigned char           fullmm;         /* non-zero means full mm flush */
         unsigned char           need_flush;     /* really unmapped some PTEs? */
         unsigned long           start_addr;
         unsigned long           end_addr;
-        struct page             *pages[FREE_PTE_NR];
+        struct page             **pages;
+        struct page             *local[IA64_GATHER_BUNDLE];
 };
 
 struct ia64_tr_entry {
@@ -90,9 +96,6 @@ extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS];
 #define RR_RID_MASK     0x00000000ffffff00L
 #define RR_TO_RID(val)  ((val >> 8) & 0xffffff)
 
-/* Users of the generic TLB shootdown code must declare this storage space. */
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * Flush the TLB for address range START to END and, if not in fast mode, release the
  * freed pages that where gathered up to this point.
@@ -147,15 +150,23 @@ ia64_tlb_flush_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long e
         }
 }
 
-/*
- * Return a pointer to an initialized struct mmu_gather.
- */
-static inline struct mmu_gather *
-tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
 {
-        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
+        unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
 
+        if (addr) {
+                tlb->pages = (void *)addr;
+                tlb->max = PAGE_SIZE / sizeof(void *);
+        }
+}
+
+
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
+{
         tlb->mm = mm;
+        tlb->max = ARRAY_SIZE(tlb->local);
+        tlb->pages = tlb->local;
         /*
          * Use fast mode if only 1 CPU is online.
          *
@@ -172,7 +183,6 @@ tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
         tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
         tlb->fullmm = full_mm_flush;
         tlb->start_addr = ~0UL;
-        return tlb;
 }
 
 /*
@@ -180,7 +190,7 @@ tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
  * collected.
  */
 static inline void
-tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
+tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
         /*
          * Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
@@ -191,7 +201,8 @@ tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
         /* keep the page table cache within bounds */
         check_pgt_cache();
 
-        put_cpu_var(mmu_gathers);
+        if (tlb->pages != tlb->local)
+                free_pages((unsigned long)tlb->pages, 0);
 }
 
 /*
@@ -199,18 +210,33 @@ tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
  * must be delayed until after the TLB has been flushed (see comments at the beginning of
  * this file).
  */
-static inline void
-tlb_remove_page (struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
         tlb->need_flush = 1;
 
         if (tlb_fast_mode(tlb)) {
                 free_page_and_swap_cache(page);
-                return;
+                return 1; /* avoid calling tlb_flush_mmu */
         }
+
+        if (!tlb->nr && tlb->pages == tlb->local)
+                __tlb_alloc_page(tlb);
+
         tlb->pages[tlb->nr++] = page;
-        if (tlb->nr >= FREE_PTE_NR)
-                ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
+        VM_BUG_ON(tlb->nr > tlb->max);
+
+        return tlb->max - tlb->nr;
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+        ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        if (!__tlb_remove_page(tlb, page))
+                tlb_flush_mmu(tlb);
 }
 
 /*
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
index 404d037c5e10..1cf0f496f744 100644
--- a/arch/ia64/include/asm/unistd.h
+++ b/arch/ia64/include/asm/unistd.h
@@ -319,11 +319,12 @@
 #define __NR_open_by_handle_at          1327
 #define __NR_clock_adjtime              1328
 #define __NR_syncfs                     1329
+#define __NR_setns                      1330
 
 #ifdef __KERNEL__
 
 
-#define NR_syscalls                     306 /* length of syscall table */
+#define NR_syscalls                     307 /* length of syscall table */
 
 /*
  * The following defines stop scripts/checksyscalls.sh from complaining about
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index 6de2e23b3636..9ca80193cd4e 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -1775,6 +1775,7 @@ sys_call_table:
         data8 sys_open_by_handle_at
         data8 sys_clock_adjtime
         data8 sys_syncfs
+        data8 sys_setns                         // 1330
 
         .org sys_call_table + 8*NR_syscalls     // guard against failures to increase NR_syscalls
 #endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index 04440cc09b40..85118dfe9bb5 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -36,7 +36,7 @@
 static cycle_t itc_get_cycles(struct clocksource *cs);
 
 struct fsyscall_gtod_data_t fsyscall_gtod_data = {
-        .lock = SEQLOCK_UNLOCKED,
+        .lock = __SEQLOCK_UNLOCKED(fsyscall_gtod_data.lock),
 };
 
 struct itc_jitter_data_t itc_jitter_data;
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index 9a018cde5d84..f114a3b14c6a 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -44,13 +44,16 @@ void show_mem(unsigned int filter)
         pg_data_t *pgdat;
 
         printk(KERN_INFO "Mem-info:\n");
-        show_free_areas();
+        show_free_areas(filter);
         printk(KERN_INFO "Node memory in pages:\n");
         for_each_online_pgdat(pgdat) {
                 unsigned long present;
                 unsigned long flags;
                 int shared = 0, cached = 0, reserved = 0;
+                int nid = pgdat->node_id;
 
+                if (skip_free_areas_node(filter, nid))
+                        continue;
                 pgdat_resize_lock(pgdat, &flags);
                 present = pgdat->node_present_pages;
                 for(i = 0; i < pgdat->node_spanned_pages; i++) {
@@ -64,8 +67,7 @@ void show_mem(unsigned int filter)
                                 if (max_gap < LARGE_GAP)
                                         continue;
 #endif
-                                i = vmemmap_find_next_valid_pfn(pgdat->node_id,
-                                         i) - 1;
+                                i = vmemmap_find_next_valid_pfn(nid, i) - 1;
                                 continue;
                         }
                         if (PageReserved(page))
@@ -81,7 +83,7 @@ void show_mem(unsigned int filter)
                 total_cached += cached;
                 total_shared += shared;
                 printk(KERN_INFO "Node %4d:  RAM: %11ld, rsvd: %8d, "
-                       "shrd: %10d, swpd: %10d\n", pgdat->node_id,
+                       "shrd: %10d, swpd: %10d\n", nid,
                        present, reserved, shared, cached);
         }
         printk(KERN_INFO "%ld pages of RAM\n", total_present);
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index 82ab1bc6afb1..c641333cd997 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -622,13 +622,16 @@ void show_mem(unsigned int filter)
         pg_data_t *pgdat;
 
         printk(KERN_INFO "Mem-info:\n");
-        show_free_areas();
+        show_free_areas(filter);
         printk(KERN_INFO "Node memory in pages:\n");
         for_each_online_pgdat(pgdat) {
                 unsigned long present;
                 unsigned long flags;
                 int shared = 0, cached = 0, reserved = 0;
+                int nid = pgdat->node_id;
 
+                if (skip_free_areas_node(filter, nid))
+                        continue;
                 pgdat_resize_lock(pgdat, &flags);
                 present = pgdat->node_present_pages;
                 for(i = 0; i < pgdat->node_spanned_pages; i++) {
@@ -638,8 +641,7 @@ void show_mem(unsigned int filter)
                         if (pfn_valid(pgdat->node_start_pfn + i))
                                 page = pfn_to_page(pgdat->node_start_pfn + i);
                         else {
-                                i = vmemmap_find_next_valid_pfn(pgdat->node_id,
-                                         i) - 1;
+                                i = vmemmap_find_next_valid_pfn(nid, i) - 1;
                                 continue;
                         }
                         if (PageReserved(page))
@@ -655,7 +657,7 @@ void show_mem(unsigned int filter)
                 total_cached += cached;
                 total_shared += shared;
                 printk(KERN_INFO "Node %4d:  RAM: %11ld, rsvd: %8d, "
-                       "shrd: %10d, swpd: %10d\n", pgdat->node_id,
+                       "shrd: %10d, swpd: %10d\n", nid,
                        present, reserved, shared, cached);
         }
         printk(KERN_INFO "%ld pages of RAM\n", total_present);
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index ed41759efcac..00cb0e26c64e 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -36,8 +36,6 @@
 #include <asm/mca.h>
 #include <asm/paravirt.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 extern void ia64_tlb_init (void);
 
 unsigned long MAX_DMA_ADDRESS = PAGE_OFFSET + 0x100000000UL;
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 736b808d2291..85b44e858225 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -256,14 +256,6 @@ config ARCH_HAS_ILOG2_U64
         bool
         default n
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_HWEIGHT
         bool
         default y
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
index 2e1019ddbb22..bb1afc1a31cc 100644
--- a/arch/m32r/Kconfig.debug
+++ b/arch/m32r/Kconfig.debug
@@ -9,15 +9,6 @@ config DEBUG_STACKOVERFLOW
           This option will cause messages to be printed if free stack space
           drops below a certain limit.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config DEBUG_PAGEALLOC
         bool "Debug page memory allocations"
         depends on DEBUG_KERNEL && BROKEN
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h
index e67ded1aab91..cf7829a61551 100644
--- a/arch/m32r/include/asm/smp.h
+++ b/arch/m32r/include/asm/smp.h
@@ -81,11 +81,11 @@ static __inline__ int cpu_number_map(int cpu)
 
 static __inline__ unsigned int num_booting_cpus(void)
 {
-        return cpus_weight(cpu_callout_map);
+        return cpumask_weight(&cpu_callout_map);
 }
 
 extern void smp_send_timer(void);
-extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
+extern unsigned long send_IPI_mask_phys(const cpumask_t*, int, int);
 
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
@@ -94,8 +94,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
 #define NO_PROC_ID (0xff)       /* No processor magic marker */
 
-#define PROC_CHANGE_PENALTY     (15)    /* Schedule penalty */
-
 /*
  * M32R-mp IPI
  */
diff --git a/arch/m32r/include/asm/unistd.h b/arch/m32r/include/asm/unistd.h
index c70545689da8..3e1db561aacc 100644
--- a/arch/m32r/include/asm/unistd.h
+++ b/arch/m32r/include/asm/unistd.h
@@ -330,10 +330,11 @@
 /* #define __NR_timerfd         322 removed */
 #define __NR_eventfd            323
 #define __NR_fallocate          324
+#define __NR_setns              325
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 325
+#define NR_syscalls 326
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_STAT64
diff --git a/arch/m32r/kernel/smp.c b/arch/m32r/kernel/smp.c
index fc10b39893d4..092d40a6708e 100644
--- a/arch/m32r/kernel/smp.c
+++ b/arch/m32r/kernel/smp.c
@@ -30,6 +30,7 @@
 #include <asm/io.h>
 #include <asm/mmu_context.h>
 #include <asm/m32r.h>
+#include <asm/tlbflush.h>
 
 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
 /* Data structures and variables                                             */
@@ -61,33 +62,22 @@ extern spinlock_t ipi_lock[];
 /* Function Prototypes                                                       */
 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
 
-void smp_send_reschedule(int);
 void smp_reschedule_interrupt(void);
-
-void smp_flush_cache_all(void);
 void smp_flush_cache_all_interrupt(void);
 
-void smp_flush_tlb_all(void);
 static void flush_tlb_all_ipi(void *);
-
-void smp_flush_tlb_mm(struct mm_struct *);
-void smp_flush_tlb_range(struct vm_area_struct *, unsigned long, \
-        unsigned long);
-void smp_flush_tlb_page(struct vm_area_struct *, unsigned long);
 static void flush_tlb_others(cpumask_t, struct mm_struct *,
         struct vm_area_struct *, unsigned long);
+
 void smp_invalidate_interrupt(void);
 
-void smp_send_stop(void);
 static void stop_this_cpu(void *);
 
-void smp_send_timer(void);
 void smp_ipi_timer_interrupt(struct pt_regs *);
 void smp_local_timer_interrupt(void);
 
 static void send_IPI_allbutself(int, int);
 static void send_IPI_mask(const struct cpumask *, int, int);
-unsigned long send_IPI_mask_phys(cpumask_t, int, int);
 
 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
 /* Rescheduling request Routines                                             */
@@ -162,10 +152,10 @@ void smp_flush_cache_all(void)
         unsigned long *mask;
 
         preempt_disable();
-        cpumask = cpu_online_map;
-        cpu_clear(smp_processor_id(), cpumask);
+        cpumask_copy(&cpumask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &cpumask);
         spin_lock(&flushcache_lock);
-        mask=cpus_addr(cpumask);
+        mask=cpumask_bits(&cpumask);
         atomic_set_mask(*mask, (atomic_t *)&flushcache_cpumask);
         send_IPI_mask(&cpumask, INVALIDATE_CACHE_IPI, 0);
         _flush_cache_copyback_all();
@@ -263,8 +253,8 @@ void smp_flush_tlb_mm(struct mm_struct *mm)
         preempt_disable();
         cpu_id = smp_processor_id();
         mmc = &mm->context[cpu_id];
-        cpu_mask = *mm_cpumask(mm);
-        cpu_clear(cpu_id, cpu_mask);
+        cpumask_copy(&cpu_mask, mm_cpumask(mm));
+        cpumask_clear_cpu(cpu_id, &cpu_mask);
 
         if (*mmc != NO_CONTEXT) {
                 local_irq_save(flags);
@@ -275,7 +265,7 @@ void smp_flush_tlb_mm(struct mm_struct *mm)
                         cpumask_clear_cpu(cpu_id, mm_cpumask(mm));
                 local_irq_restore(flags);
         }
-        if (!cpus_empty(cpu_mask))
+        if (!cpumask_empty(&cpu_mask))
                 flush_tlb_others(cpu_mask, mm, NULL, FLUSH_ALL);
 
         preempt_enable();
@@ -333,8 +323,8 @@ void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
         preempt_disable();
         cpu_id = smp_processor_id();
         mmc = &mm->context[cpu_id];
-        cpu_mask = *mm_cpumask(mm);
-        cpu_clear(cpu_id, cpu_mask);
+        cpumask_copy(&cpu_mask, mm_cpumask(mm));
+        cpumask_clear_cpu(cpu_id, &cpu_mask);
 
 #ifdef DEBUG_SMP
         if (!mm)
@@ -348,7 +338,7 @@ void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
                 __flush_tlb_page(va);
                 local_irq_restore(flags);
         }
-        if (!cpus_empty(cpu_mask))
+        if (!cpumask_empty(&cpu_mask))
                 flush_tlb_others(cpu_mask, mm, vma, va);
 
         preempt_enable();
@@ -395,14 +385,14 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
          * - current CPU must not be in mask
          * - mask must exist :)
          */
-        BUG_ON(cpus_empty(cpumask));
+        BUG_ON(cpumask_empty(&cpumask));
 
-        BUG_ON(cpu_isset(smp_processor_id(), cpumask));
+        BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask));
         BUG_ON(!mm);
 
         /* If a CPU which we ran on has gone down, OK. */
-        cpus_and(cpumask, cpumask, cpu_online_map);
-        if (cpus_empty(cpumask))
+        cpumask_and(&cpumask, &cpumask, cpu_online_mask);
+        if (cpumask_empty(&cpumask))
                 return;
 
         /*
@@ -416,7 +406,7 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
         flush_mm = mm;
         flush_vma = vma;
         flush_va = va;
-        mask=cpus_addr(cpumask);
+        mask=cpumask_bits(&cpumask);
         atomic_set_mask(*mask, (atomic_t *)&flush_cpumask);
 
         /*
@@ -425,7 +415,7 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
          */
         send_IPI_mask(&cpumask, INVALIDATE_TLB_IPI, 0);
 
-        while (!cpus_empty(flush_cpumask)) {
+        while (!cpumask_empty((cpumask_t*)&flush_cpumask)) {
                 /* nothing. lockup detection does not belong here */
                 mb();
         }
@@ -460,7 +450,7 @@ void smp_invalidate_interrupt(void)
         int cpu_id = smp_processor_id();
         unsigned long *mmc = &flush_mm->context[cpu_id];
 
-        if (!cpu_isset(cpu_id, flush_cpumask))
+        if (!cpumask_test_cpu(cpu_id, &flush_cpumask))
                 return;
 
         if (flush_va == FLUSH_ALL) {
@@ -478,7 +468,7 @@ void smp_invalidate_interrupt(void)
                         __flush_tlb_page(va);
                 }
         }
-        cpu_clear(cpu_id, flush_cpumask);
+        cpumask_clear_cpu(cpu_id, (cpumask_t*)&flush_cpumask);
 }
 
 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
@@ -530,7 +520,7 @@ static void stop_this_cpu(void *dummy)
         /*
          * Remove this CPU:
          */
-        cpu_clear(cpu_id, cpu_online_map);
+        set_cpu_online(cpu_id, false);
 
         /*
          * PSW IE = 1;
@@ -725,8 +715,8 @@ static void send_IPI_allbutself(int ipi_num, int try)
 {
         cpumask_t cpumask;
 
-        cpumask = cpu_online_map;
-        cpu_clear(smp_processor_id(), cpumask);
+        cpumask_copy(&cpumask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &cpumask);
 
         send_IPI_mask(&cpumask, ipi_num, try);
 }
@@ -763,13 +753,13 @@ static void send_IPI_mask(const struct cpumask *cpumask, int ipi_num, int try)
         cpumask_and(&tmp, cpumask, cpu_online_mask);
         BUG_ON(!cpumask_equal(cpumask, &tmp));
 
-        physid_mask = CPU_MASK_NONE;
+        cpumask_clear(&physid_mask);
         for_each_cpu(cpu_id, cpumask) {
                 if ((phys_id = cpu_to_physid(cpu_id)) != -1)
-                        cpu_set(phys_id, physid_mask);
+                        cpumask_set_cpu(phys_id, &physid_mask);
         }
 
-        send_IPI_mask_phys(physid_mask, ipi_num, try);
+        send_IPI_mask_phys(&physid_mask, ipi_num, try);
 }
 
 /*==========================================================================*
@@ -792,14 +782,14 @@ static void send_IPI_mask(const struct cpumask *cpumask, int ipi_num, int try)
  * ---------- --- --------------------------------------------------------
  *
  *==========================================================================*/
-unsigned long send_IPI_mask_phys(cpumask_t physid_mask, int ipi_num,
+unsigned long send_IPI_mask_phys(const cpumask_t *physid_mask, int ipi_num,
         int try)
 {
         spinlock_t *ipilock;
         volatile unsigned long *ipicr_addr;
         unsigned long ipicr_val;
         unsigned long my_physid_mask;
-        unsigned long mask = cpus_addr(physid_mask)[0];
+        unsigned long mask = cpumask_bits(physid_mask)[0];
 
 
         if (mask & ~physids_coerce(phys_cpu_present_map))
diff --git a/arch/m32r/kernel/smpboot.c b/arch/m32r/kernel/smpboot.c
index e034844cfc0d..cfdbe5d15002 100644
--- a/arch/m32r/kernel/smpboot.c
+++ b/arch/m32r/kernel/smpboot.c
@@ -135,9 +135,9 @@ void __devinit smp_prepare_boot_cpu(void)
 {
         bsp_phys_id = hard_smp_processor_id();
         physid_set(bsp_phys_id, phys_cpu_present_map);
-        cpu_set(0, cpu_online_map);     /* BSP's cpu_id == 0 */
-        cpu_set(0, cpu_callout_map);
-        cpu_set(0, cpu_callin_map);
+        set_cpu_online(0, true);        /* BSP's cpu_id == 0 */
+        cpumask_set_cpu(0, &cpu_callout_map);
+        cpumask_set_cpu(0, &cpu_callin_map);
 
         /*
          * Initialize the logical to physical CPU number mapping
@@ -178,7 +178,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         for (phys_id = 0 ; phys_id < nr_cpu ; phys_id++)
                 physid_set(phys_id, phys_cpu_present_map);
 #ifndef CONFIG_HOTPLUG_CPU
-        init_cpu_present(&cpu_possible_map);
+        init_cpu_present(cpu_possible_mask);
 #endif
 
         show_mp_info(nr_cpu);
@@ -294,10 +294,10 @@ static void __init do_boot_cpu(int phys_id)
         send_status = 0;
         boot_status = 0;
 
-        cpu_set(phys_id, cpu_bootout_map);
+        cpumask_set_cpu(phys_id, &cpu_bootout_map);
 
         /* Send Startup IPI */
-        send_IPI_mask_phys(cpumask_of_cpu(phys_id), CPU_BOOT_IPI, 0);
+        send_IPI_mask_phys(cpumask_of(phys_id), CPU_BOOT_IPI, 0);
 
         Dprintk("Waiting for send to finish...\n");
         timeout = 0;
@@ -306,7 +306,7 @@ static void __init do_boot_cpu(int phys_id)
         do {
                 Dprintk("+");
                 udelay(1000);
-                send_status = !cpu_isset(phys_id, cpu_bootin_map);
+                send_status = !cpumask_test_cpu(phys_id, &cpu_bootin_map);
         } while (send_status && (timeout++ < 100));
 
         Dprintk("After Startup.\n");
@@ -316,19 +316,19 @@ static void __init do_boot_cpu(int phys_id)
                  * allow APs to start initializing.
                  */
                 Dprintk("Before Callout %d.\n", cpu_id);
-                cpu_set(cpu_id, cpu_callout_map);
+                cpumask_set_cpu(cpu_id, &cpu_callout_map);
                 Dprintk("After Callout %d.\n", cpu_id);
 
                 /*
                  * Wait 5s total for a response
                  */
                 for (timeout = 0; timeout < 5000; timeout++) {
-                        if (cpu_isset(cpu_id, cpu_callin_map))
+                        if (cpumask_test_cpu(cpu_id, &cpu_callin_map))
                                 break;  /* It has booted */
                         udelay(1000);
                 }
 
-                if (cpu_isset(cpu_id, cpu_callin_map)) {
+                if (cpumask_test_cpu(cpu_id, &cpu_callin_map)) {
                         /* number CPUs logically, starting from 1 (BSP is 0) */
                         Dprintk("OK.\n");
                 } else {
@@ -340,9 +340,9 @@ static void __init do_boot_cpu(int phys_id)
 
         if (send_status || boot_status) {
                 unmap_cpu_to_physid(cpu_id, phys_id);
-                cpu_clear(cpu_id, cpu_callout_map);
-                cpu_clear(cpu_id, cpu_callin_map);
-                cpu_clear(cpu_id, cpu_initialized);
+                cpumask_clear_cpu(cpu_id, &cpu_callout_map);
+                cpumask_clear_cpu(cpu_id, &cpu_callin_map);
+                cpumask_clear_cpu(cpu_id, &cpu_initialized);
                 cpucount--;
         }
 }
@@ -351,17 +351,17 @@ int __cpuinit __cpu_up(unsigned int cpu_id)
 {
         int timeout;
 
-        cpu_set(cpu_id, smp_commenced_mask);
+        cpumask_set_cpu(cpu_id, &smp_commenced_mask);
 
         /*
          * Wait 5s total for a response
          */
         for (timeout = 0; timeout < 5000; timeout++) {
-                if (cpu_isset(cpu_id, cpu_online_map))
+                if (cpu_online(cpu_id))
                         break;
                 udelay(1000);
         }
-        if (!cpu_isset(cpu_id, cpu_online_map))
+        if (!cpu_online(cpu_id))
                 BUG();
 
         return 0;
@@ -373,11 +373,11 @@ void __init smp_cpus_done(unsigned int max_cpus)
         unsigned long bogosum = 0;
 
         for (timeout = 0; timeout < 5000; timeout++) {
-                if (cpus_equal(cpu_callin_map, cpu_online_map))
+                if (cpumask_equal(&cpu_callin_map, cpu_online_mask))
                         break;
                 udelay(1000);
         }
-        if (!cpus_equal(cpu_callin_map, cpu_online_map))
+        if (!cpumask_equal(&cpu_callin_map, cpu_online_mask))
                 BUG();
 
         for (cpu_id = 0 ; cpu_id < num_online_cpus() ; cpu_id++)
@@ -388,7 +388,7 @@ void __init smp_cpus_done(unsigned int max_cpus)
          */
         Dprintk("Before bogomips.\n");
         if (cpucount) {
-                for_each_cpu_mask(cpu_id, cpu_online_map)
+                for_each_cpu(cpu_id,cpu_online_mask)
                         bogosum += cpu_data[cpu_id].loops_per_jiffy;
 
                 printk(KERN_INFO "Total of %d processors activated " \
@@ -425,7 +425,7 @@ int __init start_secondary(void *unused)
         cpu_init();
         preempt_disable();
         smp_callin();
-        while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
+        while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask))
                 cpu_relax();
 
         smp_online();
@@ -463,7 +463,7 @@ static void __init smp_callin(void)
         int cpu_id = smp_processor_id();
         unsigned long timeout;
 
-        if (cpu_isset(cpu_id, cpu_callin_map)) {
+        if (cpumask_test_cpu(cpu_id, &cpu_callin_map)) {
                 printk("huh, phys CPU#%d, CPU#%d already present??\n",
                         phys_id, cpu_id);
                 BUG();
@@ -474,7 +474,7 @@ static void __init smp_callin(void)
         timeout = jiffies + (2 * HZ);
         while (time_before(jiffies, timeout)) {
                 /* Has the boot CPU finished it's STARTUP sequence ? */
-                if (cpu_isset(cpu_id, cpu_callout_map))
+                if (cpumask_test_cpu(cpu_id, &cpu_callout_map))
                         break;
                 cpu_relax();
         }
@@ -486,7 +486,7 @@ static void __init smp_callin(void)
         }
 
         /* Allow the master to continue. */
-        cpu_set(cpu_id, cpu_callin_map);
+        cpumask_set_cpu(cpu_id, &cpu_callin_map);
 }
 
 static void __init smp_online(void)
@@ -503,7 +503,7 @@ static void __init smp_online(void)
         /* Save our processor parameters */
         smp_store_cpu_info(cpu_id);
 
-        cpu_set(cpu_id, cpu_online_map);
+        set_cpu_online(cpu_id, true);
 }
 
 /*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*=*/
diff --git a/arch/m32r/kernel/syscall_table.S b/arch/m32r/kernel/syscall_table.S
index 60536e271233..528f2e6ad064 100644
--- a/arch/m32r/kernel/syscall_table.S
+++ b/arch/m32r/kernel/syscall_table.S
@@ -324,3 +324,4 @@ ENTRY(sys_call_table)
         .long sys_ni_syscall
         .long sys_eventfd
         .long sys_fallocate
+        .long sys_setns                 /* 325 */
diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S
index cf95aec77460..018e4a711d79 100644
--- a/arch/m32r/kernel/vmlinux.lds.S
+++ b/arch/m32r/kernel/vmlinux.lds.S
@@ -54,7 +54,7 @@ SECTIONS
   __init_begin = .;
   INIT_TEXT_SECTION(PAGE_SIZE)
   INIT_DATA_SECTION(16)
-  PERCPU(32, PAGE_SIZE)
+  PERCPU_SECTION(32)
   . = ALIGN(PAGE_SIZE);
   __init_end = .;
   /* freed after init ends here */
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index 5d2858f6eede..2c468e8b5853 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -149,6 +149,7 @@ unsigned long __init zone_sizes_init(void)
                 zholes_size[ZONE_DMA] = mp->holes;
                 holes += zholes_size[ZONE_DMA];
 
+                node_set_state(nid, N_NORMAL_MEMORY);
                 free_area_init_node(nid, zones_size, start_pfn, zholes_size);
         }
 
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index 73e2205ebf5a..78b660e903da 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -35,8 +35,6 @@ extern char __init_begin, __init_end;
 
 pgd_t swapper_pg_dir[1024];
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * Cache of MMU context last used.
  */
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 75531da02a40..d66e34c718d0 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -5,6 +5,7 @@ config M68K
         select HAVE_AOUT if MMU
         select GENERIC_ATOMIC64 if MMU
         select HAVE_GENERIC_HARDIRQS if !MMU
+        select GENERIC_IRQ_SHOW if !MMU
 
 config RWSEM_GENERIC_SPINLOCK
         bool
diff --git a/arch/m68k/Kconfig.nommu b/arch/m68k/Kconfig.nommu
index 273bccab9517..fc98f9b9d4d2 100644
--- a/arch/m68k/Kconfig.nommu
+++ b/arch/m68k/Kconfig.nommu
@@ -2,10 +2,6 @@ config FPU
         bool
         default n
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
 config GENERIC_GPIO
         bool
         default n
diff --git a/arch/m68k/include/asm/bitops_mm.h b/arch/m68k/include/asm/bitops_mm.h
index e9020f88a748..89cf5b814a4d 100644
--- a/arch/m68k/include/asm/bitops_mm.h
+++ b/arch/m68k/include/asm/bitops_mm.h
@@ -200,6 +200,7 @@ out:
         res += ((long)p - (long)vaddr - 4) * 8;
         return res < size ? res : size;
 }
+#define find_first_zero_bit find_first_zero_bit
 
 static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
                                      int offset)
@@ -229,6 +230,7 @@ static inline int find_next_zero_bit(const unsigned long *vaddr, int size,
         /* No zero yet, search remaining full bytes for a zero */
         return offset + find_first_zero_bit(p, size - offset);
 }
+#define find_next_zero_bit find_next_zero_bit
 
 static inline int find_first_bit(const unsigned long *vaddr, unsigned size)
 {
@@ -253,6 +255,7 @@ out:
         res += ((long)p - (long)vaddr - 4) * 8;
         return res < size ? res : size;
 }
+#define find_first_bit find_first_bit
 
 static inline int find_next_bit(const unsigned long *vaddr, int size,
                                 int offset)
@@ -282,6 +285,7 @@ static inline int find_next_bit(const unsigned long *vaddr, int size,
         /* No one yet, search remaining full bytes for a one */
         return offset + find_first_bit(p, size - offset);
 }
+#define find_next_bit find_next_bit
 
 /*
  * ffz = Find First Zero in word. Undefined if no zero exists,
@@ -398,6 +402,7 @@ out:
         res += (p - addr) * 32;
         return res < size ? res : size;
 }
+#define find_first_zero_bit_le find_first_zero_bit_le
 
 static inline unsigned long find_next_zero_bit_le(const void *addr,
                 unsigned long size, unsigned long offset)
@@ -427,6 +432,7 @@ static inline unsigned long find_next_zero_bit_le(const void *addr,
         /* No zero yet, search remaining full bytes for a zero */
         return offset + find_first_zero_bit_le(p, size - offset);
 }
+#define find_next_zero_bit_le find_next_zero_bit_le
 
 static inline int find_first_bit_le(const void *vaddr, unsigned size)
 {
@@ -451,6 +457,7 @@ out:
         res += (p - addr) * 32;
         return res < size ? res : size;
 }
+#define find_first_bit_le find_first_bit_le
 
 static inline unsigned long find_next_bit_le(const void *addr,
                 unsigned long size, unsigned long offset)
@@ -480,6 +487,7 @@ static inline unsigned long find_next_bit_le(const void *addr,
         /* No set bit yet, search remaining full bytes for a set bit */
         return offset + find_first_bit_le(p, size - offset);
 }
+#define find_next_bit_le find_next_bit_le
 
 /* Bitmap functions for the ext2 filesystem. */
 
diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h
index 7d3779fdc5b6..72e85acdd7bd 100644
--- a/arch/m68k/include/asm/bitops_no.h
+++ b/arch/m68k/include/asm/bitops_no.h
@@ -246,23 +246,7 @@ static inline int __test_and_clear_bit_le(int nr, volatile void *addr)
         return retval;
 }
 
-#define ext2_set_bit_atomic(lock, nr, addr)             \
-        ({                                              \
-                int ret;                                \
-                spin_lock(lock);                        \
-                ret = __test_and_set_bit_le((nr), (addr));      \
-                spin_unlock(lock);                      \
-                ret;                                    \
-        })
-
-#define ext2_clear_bit_atomic(lock, nr, addr)           \
-        ({                                              \
-                int ret;                                \
-                spin_lock(lock);                        \
-                ret = __test_and_clear_bit_le((nr), (addr));    \
-                spin_unlock(lock);                      \
-                ret;                                    \
-        })
+#include <asm-generic/bitops/ext2-atomic.h>
 
 static inline int test_bit_le(int nr, const volatile void *addr)
 {
@@ -335,6 +319,10 @@ found_first:
 found_middle:
         return result + ffz(__swab32(tmp));
 }
+#define find_next_zero_bit_le find_next_zero_bit_le
+
+extern unsigned long find_next_bit_le(const void *addr,
+                unsigned long size, unsigned long offset);
 
 #endif /* __KERNEL__ */
 
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index cf20f3097af6..353bf754a972 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -144,8 +144,10 @@ static inline void io_insl(unsigned int addr, void *buf, int len)
 #define IOMAP_NOCACHE_NONSER            2
 #define IOMAP_WRITETHROUGH              3
 
-extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
-
+static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
+{
+        return (void *) physaddr;
+}
 static inline void *ioremap(unsigned long physaddr, unsigned long size)
 {
         return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
@@ -163,7 +165,7 @@ static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size
         return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
 }
 
-extern void iounmap(void *addr);
+#define iounmap(addr)   do { } while(0)
 
 /*
  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h
index f3b649de2a1b..43f984e93970 100644
--- a/arch/m68k/include/asm/unistd.h
+++ b/arch/m68k/include/asm/unistd.h
@@ -349,10 +349,11 @@
 #define __NR_open_by_handle_at  341
 #define __NR_clock_adjtime      342
 #define __NR_syncfs             343
+#define __NR_setns              344
 
 #ifdef __KERNEL__
 
-#define NR_syscalls             344
+#define NR_syscalls             345
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c
index 59a69a5c62f2..983fed9d469b 100644
--- a/arch/m68k/kernel/asm-offsets.c
+++ b/arch/m68k/kernel/asm-offsets.c
@@ -1,5 +1,105 @@
-#ifdef CONFIG_MMU
-#include "asm-offsets_mm.c"
+/*
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ */
+
+#define ASM_OFFSETS_C
+
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/kernel_stat.h>
+#include <linux/kbuild.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/amigahw.h>
+#include <linux/font.h>
+
+int main(void)
+{
+        /* offsets into the task struct */
+        DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
+        DEFINE(TASK_MM, offsetof(struct task_struct, mm));
+        DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
+        DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
+
+        /* offsets into the thread struct */
+        DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
+        DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
+        DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
+        DEFINE(THREAD_FS, offsetof(struct thread_struct, fs));
+        DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp));
+        DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
+        DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp));
+        DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl));
+        DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
+
+        /* offsets into the thread_info struct */
+        DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count));
+        DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags));
+
+        /* offsets into the pt_regs */
+        DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
+        DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
+        DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
+        DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
+        DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
+        DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
+        DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
+        DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
+        DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
+        DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
+        DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
+        DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
+
+        /* bitfields are a bit difficult */
+#ifdef CONFIG_COLDFIRE
+        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
 #else
-#include "asm-offsets_no.c"
+        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
+#endif
+
+        /* offsets into the irq_cpustat_t struct */
+        DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
+
+        /* signal defines */
+        DEFINE(LSIGSEGV, SIGSEGV);
+        DEFINE(LSEGV_MAPERR, SEGV_MAPERR);
+        DEFINE(LSIGTRAP, SIGTRAP);
+        DEFINE(LTRAP_TRACE, TRAP_TRACE);
+
+#ifdef CONFIG_MMU
+        /* offsets into the bi_record struct */
+        DEFINE(BIR_TAG, offsetof(struct bi_record, tag));
+        DEFINE(BIR_SIZE, offsetof(struct bi_record, size));
+        DEFINE(BIR_DATA, offsetof(struct bi_record, data));
+
+        /* offsets into font_desc (drivers/video/console/font.h) */
+        DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx));
+        DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name));
+        DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width));
+        DEFINE(FONT_DESC_HEIGHT, offsetof(struct font_desc, height));
+        DEFINE(FONT_DESC_DATA, offsetof(struct font_desc, data));
+        DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref));
+
+        /* offsets into the custom struct */
+        DEFINE(CUSTOMBASE, &amiga_custom);
+        DEFINE(C_INTENAR, offsetof(struct CUSTOM, intenar));
+        DEFINE(C_INTREQR, offsetof(struct CUSTOM, intreqr));
+        DEFINE(C_INTENA, offsetof(struct CUSTOM, intena));
+        DEFINE(C_INTREQ, offsetof(struct CUSTOM, intreq));
+        DEFINE(C_SERDATR, offsetof(struct CUSTOM, serdatr));
+        DEFINE(C_SERDAT, offsetof(struct CUSTOM, serdat));
+        DEFINE(C_SERPER, offsetof(struct CUSTOM, serper));
+        DEFINE(CIAABASE, &ciaa);
+        DEFINE(CIABBASE, &ciab);
+        DEFINE(C_PRA, offsetof(struct CIA, pra));
+        DEFINE(ZTWOBASE, zTwoBase);
 #endif
+
+        return 0;
+}
diff --git a/arch/m68k/kernel/asm-offsets_mm.c b/arch/m68k/kernel/asm-offsets_mm.c
deleted file mode 100644
index 78e59b82ebc3..000000000000
--- a/arch/m68k/kernel/asm-offsets_mm.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- */
-
-#define ASM_OFFSETS_C
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/kbuild.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/amigahw.h>
-#include <linux/font.h>
-
-int main(void)
-{
-        /* offsets into the task struct */
-        DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
-        DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
-        DEFINE(TASK_MM, offsetof(struct task_struct, mm));
-#ifdef CONFIG_MMU
-        DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
-#endif
-
-        /* offsets into the thread struct */
-        DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
-        DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
-        DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
-        DEFINE(THREAD_FS, offsetof(struct thread_struct, fs));
-        DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp));
-        DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
-        DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp));
-        DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl));
-        DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
-
-        /* offsets into the thread_info struct */
-        DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count));
-        DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags));
-
-        /* offsets into the pt_regs */
-        DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
-        DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
-        DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
-        DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
-        DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
-        DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
-        DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
-        DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
-        DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
-        DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
-        DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
-        DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
-        /* bitfields are a bit difficult */
-        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
-
-        /* offsets into the irq_cpustat_t struct */
-        DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
-
-        /* offsets into the bi_record struct */
-        DEFINE(BIR_TAG, offsetof(struct bi_record, tag));
-        DEFINE(BIR_SIZE, offsetof(struct bi_record, size));
-        DEFINE(BIR_DATA, offsetof(struct bi_record, data));
-
-        /* offsets into font_desc (drivers/video/console/font.h) */
-        DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx));
-        DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name));
-        DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width));
-        DEFINE(FONT_DESC_HEIGHT, offsetof(struct font_desc, height));
-        DEFINE(FONT_DESC_DATA, offsetof(struct font_desc, data));
-        DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref));
-
-        /* signal defines */
-        DEFINE(LSIGSEGV, SIGSEGV);
-        DEFINE(LSEGV_MAPERR, SEGV_MAPERR);
-        DEFINE(LSIGTRAP, SIGTRAP);
-        DEFINE(LTRAP_TRACE, TRAP_TRACE);
-
-        /* offsets into the custom struct */
-        DEFINE(CUSTOMBASE, &amiga_custom);
-        DEFINE(C_INTENAR, offsetof(struct CUSTOM, intenar));
-        DEFINE(C_INTREQR, offsetof(struct CUSTOM, intreqr));
-        DEFINE(C_INTENA, offsetof(struct CUSTOM, intena));
-        DEFINE(C_INTREQ, offsetof(struct CUSTOM, intreq));
-        DEFINE(C_SERDATR, offsetof(struct CUSTOM, serdatr));
-        DEFINE(C_SERDAT, offsetof(struct CUSTOM, serdat));
-        DEFINE(C_SERPER, offsetof(struct CUSTOM, serper));
-        DEFINE(CIAABASE, &ciaa);
-        DEFINE(CIABBASE, &ciab);
-        DEFINE(C_PRA, offsetof(struct CIA, pra));
-        DEFINE(ZTWOBASE, zTwoBase);
-
-        return 0;
-}
diff --git a/arch/m68k/kernel/asm-offsets_no.c b/arch/m68k/kernel/asm-offsets_no.c
deleted file mode 100644
index ffe02f41ad46..000000000000
--- a/arch/m68k/kernel/asm-offsets_no.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- */
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/kbuild.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/thread_info.h>
-
-int main(void)
-{
-        /* offsets into the task struct */
-        DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
-        DEFINE(TASK_MM, offsetof(struct task_struct, mm));
-
-        /* offsets into the irq_cpustat_t struct */
-        DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
-
-        /* offsets into the thread struct */
-        DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
-        DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
-        DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
-        DEFINE(THREAD_FS, offsetof(struct thread_struct, fs));
-        DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp));
-        DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
-        DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp));
-        DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl));
-        DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
-
-        /* offsets into the pt_regs */
-        DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
-        DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
-        DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
-        DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
-        DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
-        DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
-        DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
-        DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
-        DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
-        DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
-        DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
-        DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
-
-#ifdef CONFIG_COLDFIRE
-        /* bitfields are a bit difficult */
-        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
-#else
-        /* bitfields are a bit difficult */
-        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
-#endif
-
-        /* signal defines */
-        DEFINE(SIGSEGV, SIGSEGV);
-        DEFINE(SEGV_MAPERR, SEGV_MAPERR);
-        DEFINE(SIGTRAP, SIGTRAP);
-        DEFINE(TRAP_TRACE, TRAP_TRACE);
-
-        DEFINE(PT_PTRACED, PT_PTRACED);
-
-        /* Offsets in thread_info structure */
-        DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
-        DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count));
-
-        return 0;
-}
diff --git a/arch/m68k/kernel/entry_no.S b/arch/m68k/kernel/entry_no.S
index 2783f25e38bd..5f0f6b598b5a 100644
--- a/arch/m68k/kernel/entry_no.S
+++ b/arch/m68k/kernel/entry_no.S
@@ -24,7 +24,6 @@
  * linux 2.4 support David McCullough <davidm@snapgear.com>
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <asm/errno.h>
 #include <asm/setup.h>
diff --git a/arch/m68k/kernel/irq.c b/arch/m68k/kernel/irq.c
index 15dbc3e9d20c..544b8717d499 100644
--- a/arch/m68k/kernel/irq.c
+++ b/arch/m68k/kernel/irq.c
@@ -28,31 +28,3 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
 
         set_irq_regs(oldregs);
 }
-
-int show_interrupts(struct seq_file *p, void *v)
-{
-        struct irqaction *ap;
-        int irq = *((loff_t *) v);
-
-        if (irq == 0)
-                seq_puts(p, "           CPU0\n");
-
-        if (irq < NR_IRQS) {
-                struct irq_desc *desc = irq_to_desc(irq);
-
-                ap = desc->action;
-                if (ap) {
-                        seq_printf(p, "%3d: ", irq);
-                        seq_printf(p, "%10u ", kstat_irqs(irq));
-                        seq_printf(p, "%14s  ", irq_desc_get_chip(desc)->name);
-
-                        seq_printf(p, "%s", ap->name);
-                        for (ap = ap->next; ap; ap = ap->next)
-                                seq_printf(p, ", %s", ap->name);
-                        seq_putc(p, '\n');
-                }
-        }
-
-        return 0;
-}
-
diff --git a/arch/m68k/kernel/m68k_ksyms.c b/arch/m68k/kernel/m68k_ksyms.c
index 4752c28ce0ac..33f82769547c 100644
--- a/arch/m68k/kernel/m68k_ksyms.c
+++ b/arch/m68k/kernel/m68k_ksyms.c
@@ -1,5 +1,33 @@
-#ifdef CONFIG_MMU
-#include "m68k_ksyms_mm.c"
-#else
-#include "m68k_ksyms_no.c"
+#include <linux/module.h>
+
+asmlinkage long long __ashldi3 (long long, int);
+asmlinkage long long __ashrdi3 (long long, int);
+asmlinkage long long __lshrdi3 (long long, int);
+asmlinkage long long __muldi3 (long long, long long);
+
+/* The following are special because they're not called
+   explicitly (the C compiler generates them).  Fortunately,
+   their interface isn't gonna change any time soon now, so
+   it's OK to leave it out of version control.  */
+EXPORT_SYMBOL(__ashldi3);
+EXPORT_SYMBOL(__ashrdi3);
+EXPORT_SYMBOL(__lshrdi3);
+EXPORT_SYMBOL(__muldi3);
+
+#if !defined(__mc68020__) && !defined(__mc68030__) && \
+    !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcpu32__)
+/*
+ * Simpler 68k and ColdFire parts also need a few other gcc functions.
+ */
+extern long long __divsi3(long long, long long);
+extern long long __modsi3(long long, long long);
+extern long long __mulsi3(long long, long long);
+extern long long __udivsi3(long long, long long);
+extern long long __umodsi3(long long, long long);
+
+EXPORT_SYMBOL(__divsi3);
+EXPORT_SYMBOL(__modsi3);
+EXPORT_SYMBOL(__mulsi3);
+EXPORT_SYMBOL(__udivsi3);
+EXPORT_SYMBOL(__umodsi3);
 #endif
diff --git a/arch/m68k/kernel/m68k_ksyms_mm.c b/arch/m68k/kernel/m68k_ksyms_mm.c
deleted file mode 100644
index d900e77e5363..000000000000
--- a/arch/m68k/kernel/m68k_ksyms_mm.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <linux/module.h>
-
-asmlinkage long long __ashldi3 (long long, int);
-asmlinkage long long __ashrdi3 (long long, int);
-asmlinkage long long __lshrdi3 (long long, int);
-asmlinkage long long __muldi3 (long long, long long);
-
-/* The following are special because they're not called
-   explicitly (the C compiler generates them).  Fortunately,
-   their interface isn't gonna change any time soon now, so
-   it's OK to leave it out of version control.  */
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__muldi3);
-
diff --git a/arch/m68k/kernel/m68k_ksyms_no.c b/arch/m68k/kernel/m68k_ksyms_no.c
deleted file mode 100644
index 39fe0a7aec32..000000000000
--- a/arch/m68k/kernel/m68k_ksyms_no.c
+++ /dev/null
@@ -1,78 +0,0 @@
-#include <linux/module.h>
-#include <linux/linkage.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-
-#include <asm/setup.h>
-#include <asm/machdep.h>
-#include <asm/pgalloc.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/checksum.h>
-#include <asm/current.h>
-
-extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
-
-/* platform dependent support */
-
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-EXPORT_SYMBOL(dump_fpu);
-
-EXPORT_SYMBOL(ip_fast_csum);
-
-EXPORT_SYMBOL(kernel_thread);
-
-/* Networking helper routines. */
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
-
-/* The following are special because they're not called
-   explicitly (the C compiler generates them).  Fortunately,
-   their interface isn't gonna change any time soon now, so
-   it's OK to leave it out of version control.  */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler...  (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __divsi3(void);
-extern void __lshrdi3(void);
-extern void __modsi3(void);
-extern void __muldi3(void);
-extern void __mulsi3(void);
-extern void __udivsi3(void);
-extern void __umodsi3(void);
-
-        /* gcc lib functions */
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__divsi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__modsi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__mulsi3);
-EXPORT_SYMBOL(__udivsi3);
-EXPORT_SYMBOL(__umodsi3);
-
-#ifdef CONFIG_COLDFIRE
-extern unsigned int *dma_device_address;
-extern unsigned long dma_base_addr, _ramend;
-EXPORT_SYMBOL(dma_base_addr);
-EXPORT_SYMBOL(dma_device_address);
-EXPORT_SYMBOL(_ramend);
-
-extern asmlinkage void trap(void);
-extern void     *_ramvec;
-EXPORT_SYMBOL(trap);
-EXPORT_SYMBOL(_ramvec);
-#endif /* CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/process_no.c b/arch/m68k/kernel/process_no.c
index e2a63af5d517..9b86ad11c68e 100644
--- a/arch/m68k/kernel/process_no.c
+++ b/arch/m68k/kernel/process_no.c
@@ -151,6 +151,7 @@ int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
         set_fs(fs);
         return retval;
 }
+EXPORT_SYMBOL(kernel_thread);
 
 void flush_thread(void)
 {
@@ -283,6 +284,7 @@ int dump_fpu(struct pt_regs *regs, struct user_m68kfp_struct *fpu)
 #endif
         return 1;
 }
+EXPORT_SYMBOL(dump_fpu);
 
 /*
  *      Generic dumping code. Used for panic and debug.
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 63013df33584..8623f8dc16f8 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -1,5 +1,580 @@
+/*
+ * linux/arch/m68k/kernel/sys_m68k.c
+ *
+ * This file contains various random system calls that
+ * have a non-standard calling sequence on the Linux/m68k
+ * platform.
+ */
+
+#include <linux/capability.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/fs.h>
+#include <linux/smp.h>
+#include <linux/sem.h>
+#include <linux/msg.h>
+#include <linux/shm.h>
+#include <linux/stat.h>
+#include <linux/syscalls.h>
+#include <linux/mman.h>
+#include <linux/file.h>
+#include <linux/ipc.h>
+
+#include <asm/setup.h>
+#include <asm/uaccess.h>
+#include <asm/cachectl.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/unistd.h>
+#include <asm/cacheflush.h>
+
 #ifdef CONFIG_MMU
-#include "sys_m68k_mm.c"
+
+#include <asm/tlb.h>
+
+asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
+                             unsigned long error_code);
+
+asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
+        unsigned long prot, unsigned long flags,
+        unsigned long fd, unsigned long pgoff)
+{
+        /*
+         * This is wrong for sun3 - there PAGE_SIZE is 8Kb,
+         * so we need to shift the argument down by 1; m68k mmap64(3)
+         * (in libc) expects the last argument of mmap2 in 4Kb units.
+         */
+        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
+}
+
+/* Convert virtual (user) address VADDR to physical address PADDR */
+#define virt_to_phys_040(vaddr)                                         \
+({                                                                      \
+  unsigned long _mmusr, _paddr;                                         \
+                                                                        \
+  __asm__ __volatile__ (".chip 68040\n\t"                               \
+                        "ptestr (%1)\n\t"                               \
+                        "movec %%mmusr,%0\n\t"                          \
+                        ".chip 68k"                                     \
+                        : "=r" (_mmusr)                                 \
+                        : "a" (vaddr));                                 \
+  _paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0;             \
+  _paddr;                                                               \
+})
+
+static inline int
+cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len)
+{
+  unsigned long paddr, i;
+
+  switch (scope)
+    {
+    case FLUSH_SCOPE_ALL:
+      switch (cache)
+        {
+        case FLUSH_CACHE_DATA:
+          /* This nop is needed for some broken versions of the 68040.  */
+          __asm__ __volatile__ ("nop\n\t"
+                                ".chip 68040\n\t"
+                                "cpusha %dc\n\t"
+                                ".chip 68k");
+          break;
+        case FLUSH_CACHE_INSN:
+          __asm__ __volatile__ ("nop\n\t"
+                                ".chip 68040\n\t"
+                                "cpusha %ic\n\t"
+                                ".chip 68k");
+          break;
+        default:
+        case FLUSH_CACHE_BOTH:
+          __asm__ __volatile__ ("nop\n\t"
+                                ".chip 68040\n\t"
+                                "cpusha %bc\n\t"
+                                ".chip 68k");
+          break;
+        }
+      break;
+
+    case FLUSH_SCOPE_LINE:
+      /* Find the physical address of the first mapped page in the
+         address range.  */
+      if ((paddr = virt_to_phys_040(addr))) {
+        paddr += addr & ~(PAGE_MASK | 15);
+        len = (len + (addr & 15) + 15) >> 4;
+      } else {
+        unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
+
+        if (len <= tmp)
+          return 0;
+        addr += tmp;
+        len -= tmp;
+        tmp = PAGE_SIZE;
+        for (;;)
+          {
+            if ((paddr = virt_to_phys_040(addr)))
+              break;
+            if (len <= tmp)
+              return 0;
+            addr += tmp;
+            len -= tmp;
+          }
+        len = (len + 15) >> 4;
+      }
+      i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
+      while (len--)
+        {
+          switch (cache)
+            {
+            case FLUSH_CACHE_DATA:
+              __asm__ __volatile__ ("nop\n\t"
+                                    ".chip 68040\n\t"
+                                    "cpushl %%dc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            case FLUSH_CACHE_INSN:
+              __asm__ __volatile__ ("nop\n\t"
+                                    ".chip 68040\n\t"
+                                    "cpushl %%ic,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            default:
+            case FLUSH_CACHE_BOTH:
+              __asm__ __volatile__ ("nop\n\t"
+                                    ".chip 68040\n\t"
+                                    "cpushl %%bc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            }
+          if (!--i && len)
+            {
+              /*
+               * No need to page align here since it is done by
+               * virt_to_phys_040().
+               */
+              addr += PAGE_SIZE;
+              i = PAGE_SIZE / 16;
+              /* Recompute physical address when crossing a page
+                 boundary. */
+              for (;;)
+                {
+                  if ((paddr = virt_to_phys_040(addr)))
+                    break;
+                  if (len <= i)
+                    return 0;
+                  len -= i;
+                  addr += PAGE_SIZE;
+                }
+            }
+          else
+            paddr += 16;
+        }
+      break;
+
+    default:
+    case FLUSH_SCOPE_PAGE:
+      len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
+      for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
+        {
+          if (!(paddr = virt_to_phys_040(addr)))
+            continue;
+          switch (cache)
+            {
+            case FLUSH_CACHE_DATA:
+              __asm__ __volatile__ ("nop\n\t"
+                                    ".chip 68040\n\t"
+                                    "cpushp %%dc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            case FLUSH_CACHE_INSN:
+              __asm__ __volatile__ ("nop\n\t"
+                                    ".chip 68040\n\t"
+                                    "cpushp %%ic,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            default:
+            case FLUSH_CACHE_BOTH:
+              __asm__ __volatile__ ("nop\n\t"
+                                    ".chip 68040\n\t"
+                                    "cpushp %%bc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            }
+        }
+      break;
+    }
+  return 0;
+}
+
+#define virt_to_phys_060(vaddr)                         \
+({                                                      \
+  unsigned long paddr;                                  \
+  __asm__ __volatile__ (".chip 68060\n\t"               \
+                        "plpar (%0)\n\t"                \
+                        ".chip 68k"                     \
+                        : "=a" (paddr)                  \
+                        : "0" (vaddr));                 \
+  (paddr); /* XXX */                                    \
+})
+
+static inline int
+cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len)
+{
+  unsigned long paddr, i;
+
+  /*
+   * 68060 manual says:
+   *  cpush %dc : flush DC, remains valid (with our %cacr setup)
+   *  cpush %ic : invalidate IC
+   *  cpush %bc : flush DC + invalidate IC
+   */
+  switch (scope)
+    {
+    case FLUSH_SCOPE_ALL:
+      switch (cache)
+        {
+        case FLUSH_CACHE_DATA:
+          __asm__ __volatile__ (".chip 68060\n\t"
+                                "cpusha %dc\n\t"
+                                ".chip 68k");
+          break;
+        case FLUSH_CACHE_INSN:
+          __asm__ __volatile__ (".chip 68060\n\t"
+                                "cpusha %ic\n\t"
+                                ".chip 68k");
+          break;
+        default:
+        case FLUSH_CACHE_BOTH:
+          __asm__ __volatile__ (".chip 68060\n\t"
+                                "cpusha %bc\n\t"
+                                ".chip 68k");
+          break;
+        }
+      break;
+
+    case FLUSH_SCOPE_LINE:
+      /* Find the physical address of the first mapped page in the
+         address range.  */
+      len += addr & 15;
+      addr &= -16;
+      if (!(paddr = virt_to_phys_060(addr))) {
+        unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
+
+        if (len <= tmp)
+          return 0;
+        addr += tmp;
+        len -= tmp;
+        tmp = PAGE_SIZE;
+        for (;;)
+          {
+            if ((paddr = virt_to_phys_060(addr)))
+              break;
+            if (len <= tmp)
+              return 0;
+            addr += tmp;
+            len -= tmp;
+          }
+      }
+      len = (len + 15) >> 4;
+      i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
+      while (len--)
+        {
+          switch (cache)
+            {
+            case FLUSH_CACHE_DATA:
+              __asm__ __volatile__ (".chip 68060\n\t"
+                                    "cpushl %%dc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            case FLUSH_CACHE_INSN:
+              __asm__ __volatile__ (".chip 68060\n\t"
+                                    "cpushl %%ic,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            default:
+            case FLUSH_CACHE_BOTH:
+              __asm__ __volatile__ (".chip 68060\n\t"
+                                    "cpushl %%bc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            }
+          if (!--i && len)
+            {
+
+              /*
+               * We just want to jump to the first cache line
+               * in the next page.
+               */
+              addr += PAGE_SIZE;
+              addr &= PAGE_MASK;
+
+              i = PAGE_SIZE / 16;
+              /* Recompute physical address when crossing a page
+                 boundary. */
+              for (;;)
+                {
+                  if ((paddr = virt_to_phys_060(addr)))
+                    break;
+                  if (len <= i)
+                    return 0;
+                  len -= i;
+                  addr += PAGE_SIZE;
+                }
+            }
+          else
+            paddr += 16;
+        }
+      break;
+
+    default:
+    case FLUSH_SCOPE_PAGE:
+      len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
+      addr &= PAGE_MASK;        /* Workaround for bug in some
+                                   revisions of the 68060 */
+      for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
+        {
+          if (!(paddr = virt_to_phys_060(addr)))
+            continue;
+          switch (cache)
+            {
+            case FLUSH_CACHE_DATA:
+              __asm__ __volatile__ (".chip 68060\n\t"
+                                    "cpushp %%dc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            case FLUSH_CACHE_INSN:
+              __asm__ __volatile__ (".chip 68060\n\t"
+                                    "cpushp %%ic,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            default:
+            case FLUSH_CACHE_BOTH:
+              __asm__ __volatile__ (".chip 68060\n\t"
+                                    "cpushp %%bc,(%0)\n\t"
+                                    ".chip 68k"
+                                    : : "a" (paddr));
+              break;
+            }
+        }
+      break;
+    }
+  return 0;
+}
+
+/* sys_cacheflush -- flush (part of) the processor cache.  */
+asmlinkage int
+sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
+{
+        struct vm_area_struct *vma;
+        int ret = -EINVAL;
+
+        if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL ||
+            cache & ~FLUSH_CACHE_BOTH)
+                goto out;
+
+        if (scope == FLUSH_SCOPE_ALL) {
+                /* Only the superuser may explicitly flush the whole cache. */
+                ret = -EPERM;
+                if (!capable(CAP_SYS_ADMIN))
+                        goto out;
+        } else {
+                /*
+                 * Verify that the specified address region actually belongs
+                 * to this process.
+                 */
+                vma = find_vma (current->mm, addr);
+                ret = -EINVAL;
+                /* Check for overflow.  */
+                if (addr + len < addr)
+                        goto out;
+                if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end)
+                        goto out;
+        }
+
+        if (CPU_IS_020_OR_030) {
+                if (scope == FLUSH_SCOPE_LINE && len < 256) {
+                        unsigned long cacr;
+                        __asm__ ("movec %%cacr, %0" : "=r" (cacr));
+                        if (cache & FLUSH_CACHE_INSN)
+                                cacr |= 4;
+                        if (cache & FLUSH_CACHE_DATA)
+                                cacr |= 0x400;
+                        len >>= 2;
+                        while (len--) {
+                                __asm__ __volatile__ ("movec %1, %%caar\n\t"
+                                                      "movec %0, %%cacr"
+                                                      : /* no outputs */
+                                                      : "r" (cacr), "r" (addr));
+                                addr += 4;
+                        }
+                } else {
+                        /* Flush the whole cache, even if page granularity requested. */
+                        unsigned long cacr;
+                        __asm__ ("movec %%cacr, %0" : "=r" (cacr));
+                        if (cache & FLUSH_CACHE_INSN)
+                                cacr |= 8;
+                        if (cache & FLUSH_CACHE_DATA)
+                                cacr |= 0x800;
+                        __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr));
+                }
+                ret = 0;
+                goto out;
+        } else {
+            /*
+             * 040 or 060: don't blindly trust 'scope', someone could
+             * try to flush a few megs of memory.
+             */
+
+            if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE)
+                scope=FLUSH_SCOPE_PAGE;
+            if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL)
+                scope=FLUSH_SCOPE_ALL;
+            if (CPU_IS_040) {
+                ret = cache_flush_040 (addr, scope, cache, len);
+            } else if (CPU_IS_060) {
+                ret = cache_flush_060 (addr, scope, cache, len);
+            }
+        }
+out:
+        return ret;
+}
+
+/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
+   D1 (newval).  */
+asmlinkage int
+sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
+                      unsigned long __user * mem)
+{
+        /* This was borrowed from ARM's implementation.  */
+        for (;;) {
+                struct mm_struct *mm = current->mm;
+                pgd_t *pgd;
+                pmd_t *pmd;
+                pte_t *pte;
+                spinlock_t *ptl;
+                unsigned long mem_value;
+
+                down_read(&mm->mmap_sem);
+                pgd = pgd_offset(mm, (unsigned long)mem);
+                if (!pgd_present(*pgd))
+                        goto bad_access;
+                pmd = pmd_offset(pgd, (unsigned long)mem);
+                if (!pmd_present(*pmd))
+                        goto bad_access;
+                pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl);
+                if (!pte_present(*pte) || !pte_dirty(*pte)
+                    || !pte_write(*pte)) {
+                        pte_unmap_unlock(pte, ptl);
+                        goto bad_access;
+                }
+
+                mem_value = *mem;
+                if (mem_value == oldval)
+                        *mem = newval;
+
+                pte_unmap_unlock(pte, ptl);
+                up_read(&mm->mmap_sem);
+                return mem_value;
+
+              bad_access:
+                up_read(&mm->mmap_sem);
+                /* This is not necessarily a bad access, we can get here if
+                   a memory we're trying to write to should be copied-on-write.
+                   Make the kernel do the necessary page stuff, then re-iterate.
+                   Simulate a write access fault to do that.  */
+                {
+                        /* The first argument of the function corresponds to
+                           D1, which is the first field of struct pt_regs.  */
+                        struct pt_regs *fp = (struct pt_regs *)&newval;
+
+                        /* '3' is an RMW flag.  */
+                        if (do_page_fault(fp, (unsigned long)mem, 3))
+                                /* If the do_page_fault() failed, we don't
+                                   have anything meaningful to return.
+                                   There should be a SIGSEGV pending for
+                                   the process.  */
+                                return 0xdeadbeef;
+                }
+        }
+}
+
 #else
-#include "sys_m68k_no.c"
-#endif
+
+/* sys_cacheflush -- flush (part of) the processor cache.  */
+asmlinkage int
+sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
+{
+        flush_cache_all();
+        return 0;
+}
+
+/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
+   D1 (newval).  */
+asmlinkage int
+sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
+                      unsigned long __user * mem)
+{
+        struct mm_struct *mm = current->mm;
+        unsigned long mem_value;
+
+        down_read(&mm->mmap_sem);
+
+        mem_value = *mem;
+        if (mem_value == oldval)
+                *mem = newval;
+
+        up_read(&mm->mmap_sem);
+        return mem_value;
+}
+
+#endif /* CONFIG_MMU */
+
+asmlinkage int sys_getpagesize(void)
+{
+        return PAGE_SIZE;
+}
+
+/*
+ * Do a system call from kernel instead of calling sys_execve so we
+ * end up with proper pt_regs.
+ */
+int kernel_execve(const char *filename,
+                  const char *const argv[],
+                  const char *const envp[])
+{
+        register long __res asm ("%d0") = __NR_execve;
+        register long __a asm ("%d1") = (long)(filename);
+        register long __b asm ("%d2") = (long)(argv);
+        register long __c asm ("%d3") = (long)(envp);
+        asm volatile ("trap  #0" : "+d" (__res)
+                        : "d" (__a), "d" (__b), "d" (__c));
+        return __res;
+}
+
+asmlinkage unsigned long sys_get_thread_area(void)
+{
+        return current_thread_info()->tp_value;
+}
+
+asmlinkage int sys_set_thread_area(unsigned long tp)
+{
+        current_thread_info()->tp_value = tp;
+        return 0;
+}
+
+asmlinkage int sys_atomic_barrier(void)
+{
+        /* no code needed for uniprocs */
+        return 0;
+}
diff --git a/arch/m68k/kernel/sys_m68k_mm.c b/arch/m68k/kernel/sys_m68k_mm.c
deleted file mode 100644
index 3db2e7f902aa..000000000000
--- a/arch/m68k/kernel/sys_m68k_mm.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * linux/arch/m68k/kernel/sys_m68k.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/m68k
- * platform.
- */
-
-#include <linux/capability.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/ipc.h>
-
-#include <asm/setup.h>
-#include <asm/uaccess.h>
-#include <asm/cachectl.h>
-#include <asm/traps.h>
-#include <asm/page.h>
-#include <asm/unistd.h>
-#include <linux/elf.h>
-#include <asm/tlb.h>
-
-asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
-                             unsigned long error_code);
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
-        unsigned long prot, unsigned long flags,
-        unsigned long fd, unsigned long pgoff)
-{
-        /*
-         * This is wrong for sun3 - there PAGE_SIZE is 8Kb,
-         * so we need to shift the argument down by 1; m68k mmap64(3)
-         * (in libc) expects the last argument of mmap2 in 4Kb units.
-         */
-        return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
-}
-
-/* Convert virtual (user) address VADDR to physical address PADDR */
-#define virt_to_phys_040(vaddr)                                         \
-({                                                                      \
-  unsigned long _mmusr, _paddr;                                         \
-                                                                        \
-  __asm__ __volatile__ (".chip 68040\n\t"                               \
-                        "ptestr (%1)\n\t"                               \
-                        "movec %%mmusr,%0\n\t"                          \
-                        ".chip 68k"                                     \
-                        : "=r" (_mmusr)                                 \
-                        : "a" (vaddr));                                 \
-  _paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0;             \
-  _paddr;                                                               \
-})
-
-static inline int
-cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len)
-{
-  unsigned long paddr, i;
-
-  switch (scope)
-    {
-    case FLUSH_SCOPE_ALL:
-      switch (cache)
-        {
-        case FLUSH_CACHE_DATA:
-          /* This nop is needed for some broken versions of the 68040.  */
-          __asm__ __volatile__ ("nop\n\t"
-                                ".chip 68040\n\t"
-                                "cpusha %dc\n\t"
-                                ".chip 68k");
-          break;
-        case FLUSH_CACHE_INSN:
-          __asm__ __volatile__ ("nop\n\t"
-                                ".chip 68040\n\t"
-                                "cpusha %ic\n\t"
-                                ".chip 68k");
-          break;
-        default:
-        case FLUSH_CACHE_BOTH:
-          __asm__ __volatile__ ("nop\n\t"
-                                ".chip 68040\n\t"
-                                "cpusha %bc\n\t"
-                                ".chip 68k");
-          break;
-        }
-      break;
-
-    case FLUSH_SCOPE_LINE:
-      /* Find the physical address of the first mapped page in the
-         address range.  */
-      if ((paddr = virt_to_phys_040(addr))) {
-        paddr += addr & ~(PAGE_MASK | 15);
-        len = (len + (addr & 15) + 15) >> 4;
-      } else {
-        unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
-
-        if (len <= tmp)
-          return 0;
-        addr += tmp;
-        len -= tmp;
-        tmp = PAGE_SIZE;
-        for (;;)
-          {
-            if ((paddr = virt_to_phys_040(addr)))
-              break;
-            if (len <= tmp)
-              return 0;
-            addr += tmp;
-            len -= tmp;
-          }
-        len = (len + 15) >> 4;
-      }
-      i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
-      while (len--)
-        {
-          switch (cache)
-            {
-            case FLUSH_CACHE_DATA:
-              __asm__ __volatile__ ("nop\n\t"
-                                    ".chip 68040\n\t"
-                                    "cpushl %%dc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            case FLUSH_CACHE_INSN:
-              __asm__ __volatile__ ("nop\n\t"
-                                    ".chip 68040\n\t"
-                                    "cpushl %%ic,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            default:
-            case FLUSH_CACHE_BOTH:
-              __asm__ __volatile__ ("nop\n\t"
-                                    ".chip 68040\n\t"
-                                    "cpushl %%bc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            }
-          if (!--i && len)
-            {
-              /*
-               * No need to page align here since it is done by
-               * virt_to_phys_040().
-               */
-              addr += PAGE_SIZE;
-              i = PAGE_SIZE / 16;
-              /* Recompute physical address when crossing a page
-                 boundary. */
-              for (;;)
-                {
-                  if ((paddr = virt_to_phys_040(addr)))
-                    break;
-                  if (len <= i)
-                    return 0;
-                  len -= i;
-                  addr += PAGE_SIZE;
-                }
-            }
-          else
-            paddr += 16;
-        }
-      break;
-
-    default:
-    case FLUSH_SCOPE_PAGE:
-      len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
-      for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
-        {
-          if (!(paddr = virt_to_phys_040(addr)))
-            continue;
-          switch (cache)
-            {
-            case FLUSH_CACHE_DATA:
-              __asm__ __volatile__ ("nop\n\t"
-                                    ".chip 68040\n\t"
-                                    "cpushp %%dc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            case FLUSH_CACHE_INSN:
-              __asm__ __volatile__ ("nop\n\t"
-                                    ".chip 68040\n\t"
-                                    "cpushp %%ic,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            default:
-            case FLUSH_CACHE_BOTH:
-              __asm__ __volatile__ ("nop\n\t"
-                                    ".chip 68040\n\t"
-                                    "cpushp %%bc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            }
-        }
-      break;
-    }
-  return 0;
-}
-
-#define virt_to_phys_060(vaddr)                         \
-({                                                      \
-  unsigned long paddr;                                  \
-  __asm__ __volatile__ (".chip 68060\n\t"               \
-                        "plpar (%0)\n\t"                \
-                        ".chip 68k"                     \
-                        : "=a" (paddr)                  \
-                        : "0" (vaddr));                 \
-  (paddr); /* XXX */                                    \
-})
-
-static inline int
-cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len)
-{
-  unsigned long paddr, i;
-
-  /*
-   * 68060 manual says:
-   *  cpush %dc : flush DC, remains valid (with our %cacr setup)
-   *  cpush %ic : invalidate IC
-   *  cpush %bc : flush DC + invalidate IC
-   */
-  switch (scope)
-    {
-    case FLUSH_SCOPE_ALL:
-      switch (cache)
-        {
-        case FLUSH_CACHE_DATA:
-          __asm__ __volatile__ (".chip 68060\n\t"
-                                "cpusha %dc\n\t"
-                                ".chip 68k");
-          break;
-        case FLUSH_CACHE_INSN:
-          __asm__ __volatile__ (".chip 68060\n\t"
-                                "cpusha %ic\n\t"
-                                ".chip 68k");
-          break;
-        default:
-        case FLUSH_CACHE_BOTH:
-          __asm__ __volatile__ (".chip 68060\n\t"
-                                "cpusha %bc\n\t"
-                                ".chip 68k");
-          break;
-        }
-      break;
-
-    case FLUSH_SCOPE_LINE:
-      /* Find the physical address of the first mapped page in the
-         address range.  */
-      len += addr & 15;
-      addr &= -16;
-      if (!(paddr = virt_to_phys_060(addr))) {
-        unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
-
-        if (len <= tmp)
-          return 0;
-        addr += tmp;
-        len -= tmp;
-        tmp = PAGE_SIZE;
-        for (;;)
-          {
-            if ((paddr = virt_to_phys_060(addr)))
-              break;
-            if (len <= tmp)
-              return 0;
-            addr += tmp;
-            len -= tmp;
-          }
-      }
-      len = (len + 15) >> 4;
-      i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
-      while (len--)
-        {
-          switch (cache)
-            {
-            case FLUSH_CACHE_DATA:
-              __asm__ __volatile__ (".chip 68060\n\t"
-                                    "cpushl %%dc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            case FLUSH_CACHE_INSN:
-              __asm__ __volatile__ (".chip 68060\n\t"
-                                    "cpushl %%ic,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            default:
-            case FLUSH_CACHE_BOTH:
-              __asm__ __volatile__ (".chip 68060\n\t"
-                                    "cpushl %%bc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            }
-          if (!--i && len)
-            {
-
-              /*
-               * We just want to jump to the first cache line
-               * in the next page.
-               */
-              addr += PAGE_SIZE;
-              addr &= PAGE_MASK;
-
-              i = PAGE_SIZE / 16;
-              /* Recompute physical address when crossing a page
-                 boundary. */
-              for (;;)
-                {
-                  if ((paddr = virt_to_phys_060(addr)))
-                    break;
-                  if (len <= i)
-                    return 0;
-                  len -= i;
-                  addr += PAGE_SIZE;
-                }
-            }
-          else
-            paddr += 16;
-        }
-      break;
-
-    default:
-    case FLUSH_SCOPE_PAGE:
-      len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
-      addr &= PAGE_MASK;        /* Workaround for bug in some
-                                   revisions of the 68060 */
-      for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
-        {
-          if (!(paddr = virt_to_phys_060(addr)))
-            continue;
-          switch (cache)
-            {
-            case FLUSH_CACHE_DATA:
-              __asm__ __volatile__ (".chip 68060\n\t"
-                                    "cpushp %%dc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            case FLUSH_CACHE_INSN:
-              __asm__ __volatile__ (".chip 68060\n\t"
-                                    "cpushp %%ic,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            default:
-            case FLUSH_CACHE_BOTH:
-              __asm__ __volatile__ (".chip 68060\n\t"
-                                    "cpushp %%bc,(%0)\n\t"
-                                    ".chip 68k"
-                                    : : "a" (paddr));
-              break;
-            }
-        }
-      break;
-    }
-  return 0;
-}
-
-/* sys_cacheflush -- flush (part of) the processor cache.  */
-asmlinkage int
-sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
-{
-        struct vm_area_struct *vma;
-        int ret = -EINVAL;
-
-        if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL ||
-            cache & ~FLUSH_CACHE_BOTH)
-                goto out;
-
-        if (scope == FLUSH_SCOPE_ALL) {
-                /* Only the superuser may explicitly flush the whole cache. */
-                ret = -EPERM;
-                if (!capable(CAP_SYS_ADMIN))
-                        goto out;
-        } else {
-                /*
-                 * Verify that the specified address region actually belongs
-                 * to this process.
-                 */
-                vma = find_vma (current->mm, addr);
-                ret = -EINVAL;
-                /* Check for overflow.  */
-                if (addr + len < addr)
-                        goto out;
-                if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end)
-                        goto out;
-        }
-
-        if (CPU_IS_020_OR_030) {
-                if (scope == FLUSH_SCOPE_LINE && len < 256) {
-                        unsigned long cacr;
-                        __asm__ ("movec %%cacr, %0" : "=r" (cacr));
-                        if (cache & FLUSH_CACHE_INSN)
-                                cacr |= 4;
-                        if (cache & FLUSH_CACHE_DATA)
-                                cacr |= 0x400;
-                        len >>= 2;
-                        while (len--) {
-                                __asm__ __volatile__ ("movec %1, %%caar\n\t"
-                                                      "movec %0, %%cacr"
-                                                      : /* no outputs */
-                                                      : "r" (cacr), "r" (addr));
-                                addr += 4;
-                        }
-                } else {
-                        /* Flush the whole cache, even if page granularity requested. */
-                        unsigned long cacr;
-                        __asm__ ("movec %%cacr, %0" : "=r" (cacr));
-                        if (cache & FLUSH_CACHE_INSN)
-                                cacr |= 8;
-                        if (cache & FLUSH_CACHE_DATA)
-                                cacr |= 0x800;
-                        __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr));
-                }
-                ret = 0;
-                goto out;
-        } else {
-            /*
-             * 040 or 060: don't blindly trust 'scope', someone could
-             * try to flush a few megs of memory.
-             */
-
-            if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE)
-                scope=FLUSH_SCOPE_PAGE;
-            if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL)
-                scope=FLUSH_SCOPE_ALL;
-            if (CPU_IS_040) {
-                ret = cache_flush_040 (addr, scope, cache, len);
-            } else if (CPU_IS_060) {
-                ret = cache_flush_060 (addr, scope, cache, len);
-            }
-        }
-out:
-        return ret;
-}
-
-asmlinkage int sys_getpagesize(void)
-{
-        return PAGE_SIZE;
-}
-
-/*
- * Do a system call from kernel instead of calling sys_execve so we
- * end up with proper pt_regs.
- */
-int kernel_execve(const char *filename,
-                  const char *const argv[],
-                  const char *const envp[])
-{
-        register long __res asm ("%d0") = __NR_execve;
-        register long __a asm ("%d1") = (long)(filename);
-        register long __b asm ("%d2") = (long)(argv);
-        register long __c asm ("%d3") = (long)(envp);
-        asm volatile ("trap  #0" : "+d" (__res)
-                        : "d" (__a), "d" (__b), "d" (__c));
-        return __res;
-}
-
-asmlinkage unsigned long sys_get_thread_area(void)
-{
-        return current_thread_info()->tp_value;
-}
-
-asmlinkage int sys_set_thread_area(unsigned long tp)
-{
-        current_thread_info()->tp_value = tp;
-        return 0;
-}
-
-/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
-   D1 (newval).  */
-asmlinkage int
-sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
-                      unsigned long __user * mem)
-{
-        /* This was borrowed from ARM's implementation.  */
-        for (;;) {
-                struct mm_struct *mm = current->mm;
-                pgd_t *pgd;
-                pmd_t *pmd;
-                pte_t *pte;
-                spinlock_t *ptl;
-                unsigned long mem_value;
-
-                down_read(&mm->mmap_sem);
-                pgd = pgd_offset(mm, (unsigned long)mem);
-                if (!pgd_present(*pgd))
-                        goto bad_access;
-                pmd = pmd_offset(pgd, (unsigned long)mem);
-                if (!pmd_present(*pmd))
-                        goto bad_access;
-                pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl);
-                if (!pte_present(*pte) || !pte_dirty(*pte)
-                    || !pte_write(*pte)) {
-                        pte_unmap_unlock(pte, ptl);
-                        goto bad_access;
-                }
-
-                mem_value = *mem;
-                if (mem_value == oldval)
-                        *mem = newval;
-
-                pte_unmap_unlock(pte, ptl);
-                up_read(&mm->mmap_sem);
-                return mem_value;
-
-              bad_access:
-                up_read(&mm->mmap_sem);
-                /* This is not necessarily a bad access, we can get here if
-                   a memory we're trying to write to should be copied-on-write.
-                   Make the kernel do the necessary page stuff, then re-iterate.
-                   Simulate a write access fault to do that.  */
-                {
-                        /* The first argument of the function corresponds to
-                           D1, which is the first field of struct pt_regs.  */
-                        struct pt_regs *fp = (struct pt_regs *)&newval;
-
-                        /* '3' is an RMW flag.  */
-                        if (do_page_fault(fp, (unsigned long)mem, 3))
-                                /* If the do_page_fault() failed, we don't
-                                   have anything meaningful to return.
-                                   There should be a SIGSEGV pending for
-                                   the process.  */
-                                return 0xdeadbeef;
-                }
-        }
-}
-
-asmlinkage int sys_atomic_barrier(void)
-{
-        /* no code needed for uniprocs */
-        return 0;
-}
diff --git a/arch/m68k/kernel/sys_m68k_no.c b/arch/m68k/kernel/sys_m68k_no.c
deleted file mode 100644
index 68488ae47f0a..000000000000
--- a/arch/m68k/kernel/sys_m68k_no.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * linux/arch/m68knommu/kernel/sys_m68k.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/m68k
- * platform.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/ipc.h>
-#include <linux/fs.h>
-
-#include <asm/setup.h>
-#include <asm/uaccess.h>
-#include <asm/cachectl.h>
-#include <asm/traps.h>
-#include <asm/cacheflush.h>
-#include <asm/unistd.h>
-
-/* sys_cacheflush -- flush (part of) the processor cache.  */
-asmlinkage int
-sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
-{
-        flush_cache_all();
-        return(0);
-}
-
-asmlinkage int sys_getpagesize(void)
-{
-        return PAGE_SIZE;
-}
-
-/*
- * Do a system call from kernel instead of calling sys_execve so we
- * end up with proper pt_regs.
- */
-int kernel_execve(const char *filename,
-                  const char *const argv[],
-                  const char *const envp[])
-{
-        register long __res asm ("%d0") = __NR_execve;
-        register long __a asm ("%d1") = (long)(filename);
-        register long __b asm ("%d2") = (long)(argv);
-        register long __c asm ("%d3") = (long)(envp);
-        asm volatile ("trap  #0" : "+d" (__res)
-                        : "d" (__a), "d" (__b), "d" (__c));
-        return __res;
-}
-
-asmlinkage unsigned long sys_get_thread_area(void)
-{
-        return current_thread_info()->tp_value;
-}
-
-asmlinkage int sys_set_thread_area(unsigned long tp)
-{
-        current_thread_info()->tp_value = tp;
-        return 0;
-}
-
-/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
-   D1 (newval).  */
-asmlinkage int
-sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
-                      unsigned long __user * mem)
-{
-        struct mm_struct *mm = current->mm;
-        unsigned long mem_value;
-
-        down_read(&mm->mmap_sem);
-
-        mem_value = *mem;
-        if (mem_value == oldval)
-                *mem = newval;
-
-        up_read(&mm->mmap_sem);
-        return mem_value;
-}
-
-asmlinkage int sys_atomic_barrier(void)
-{
-        /* no code needed for uniprocs */
-        return 0;
-}
diff --git a/arch/m68k/kernel/syscalltable.S b/arch/m68k/kernel/syscalltable.S
index 5909e392cb1e..00d1452f9571 100644
--- a/arch/m68k/kernel/syscalltable.S
+++ b/arch/m68k/kernel/syscalltable.S
@@ -11,7 +11,6 @@
  *  Linux/m68k support by Hamish Macdonald
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 
 #ifndef CONFIG_MMU
@@ -365,4 +364,5 @@ ENTRY(sys_call_table)
         .long sys_open_by_handle_at
         .long sys_clock_adjtime
         .long sys_syncfs
+        .long sys_setns
 
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index 1f95881d8437..df421e501436 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -1,5 +1,14 @@
+
+#
+# Makefile for m68k-specific library files..
+#
+
+lib-y   := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
+           memcpy.o memset.o memmove.o
+
 ifdef CONFIG_MMU
-include arch/m68k/lib/Makefile_mm
+lib-y   += string.o uaccess.o checksum_mm.o
 else
-include arch/m68k/lib/Makefile_no
+lib-y   += mulsi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o delay.o checksum_no.o
 endif
+
diff --git a/arch/m68k/lib/Makefile_mm b/arch/m68k/lib/Makefile_mm
deleted file mode 100644
index af9abf8d9d98..000000000000
--- a/arch/m68k/lib/Makefile_mm
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for m68k-specific library files..
-#
-
-lib-y   := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
-           checksum.o string.o uaccess.o
diff --git a/arch/m68k/lib/Makefile_no b/arch/m68k/lib/Makefile_no
deleted file mode 100644
index 32d852e586d7..000000000000
--- a/arch/m68k/lib/Makefile_no
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for m68knommu specific library files..
-#
-
-lib-y   := ashldi3.o ashrdi3.o lshrdi3.o \
-           muldi3.o mulsi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
-           checksum.o memcpy.o memmove.o memset.o delay.o
diff --git a/arch/m68k/lib/checksum.c b/arch/m68k/lib/checksum.c
deleted file mode 100644
index 1297536060de..000000000000
--- a/arch/m68k/lib/checksum.c
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_MMU
-#include "checksum_mm.c"
-#else
-#include "checksum_no.c"
-#endif
diff --git a/arch/m68k/lib/checksum_no.c b/arch/m68k/lib/checksum_no.c
index eccf25d3d73e..e4c6354da765 100644
--- a/arch/m68k/lib/checksum_no.c
+++ b/arch/m68k/lib/checksum_no.c
@@ -101,6 +101,7 @@ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
 {
         return (__force __sum16)~do_csum(iph,ihl*4);
 }
+EXPORT_SYMBOL(ip_fast_csum);
 #endif
 
 /*
@@ -140,6 +141,7 @@ csum_partial_copy_from_user(const void __user *src, void *dst,
         memcpy(dst, (__force const void *)src, len);
         return csum_partial(dst, len, sum);
 }
+EXPORT_SYMBOL(csum_partial_copy_from_user);
 
 /*
  * copy from ds while checksumming, otherwise like csum_partial
@@ -151,3 +153,4 @@ csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum)
         memcpy(dst, src, len);
         return csum_partial(dst, len, sum);
 }
+EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/m68k/lib/memcpy.c b/arch/m68k/lib/memcpy.c
index b50dbcad4746..62182c81e91c 100644
--- a/arch/m68k/lib/memcpy.c
+++ b/arch/m68k/lib/memcpy.c
@@ -1,62 +1,80 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
 
-#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/string.h>
 
-void * memcpy(void * to, const void * from, size_t n)
+void *memcpy(void *to, const void *from, size_t n)
 {
-#ifdef CONFIG_COLDFIRE
-  void *xto = to;
-  size_t temp;
+        void *xto = to;
+        size_t temp, temp1;
 
-  if (!n)
-    return xto;
-  if ((long) to & 1)
-    {
-      char *cto = to;
-      const char *cfrom = from;
-      *cto++ = *cfrom++;
-      to = cto;
-      from = cfrom;
-      n--;
-    }
-  if (n > 2 && (long) to & 2)
-    {
-      short *sto = to;
-      const short *sfrom = from;
-      *sto++ = *sfrom++;
-      to = sto;
-      from = sfrom;
-      n -= 2;
-    }
-  temp = n >> 2;
-  if (temp)
-    {
-      long *lto = to;
-      const long *lfrom = from;
-      for (; temp; temp--)
-        *lto++ = *lfrom++;
-      to = lto;
-      from = lfrom;
-    }
-  if (n & 2)
-    {
-      short *sto = to;
-      const short *sfrom = from;
-      *sto++ = *sfrom++;
-      to = sto;
-      from = sfrom;
-    }
-  if (n & 1)
-    {
-      char *cto = to;
-      const char *cfrom = from;
-      *cto = *cfrom;
-    }
-  return xto;
+        if (!n)
+                return xto;
+        if ((long)to & 1) {
+                char *cto = to;
+                const char *cfrom = from;
+                *cto++ = *cfrom++;
+                to = cto;
+                from = cfrom;
+                n--;
+        }
+        if (n > 2 && (long)to & 2) {
+                short *sto = to;
+                const short *sfrom = from;
+                *sto++ = *sfrom++;
+                to = sto;
+                from = sfrom;
+                n -= 2;
+        }
+        temp = n >> 2;
+        if (temp) {
+                long *lto = to;
+                const long *lfrom = from;
+#if defined(__mc68020__) || defined(__mc68030__) || \
+    defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
+                asm volatile (
+                        "       movel %2,%3\n"
+                        "       andw  #7,%3\n"
+                        "       lsrl  #3,%2\n"
+                        "       negw  %3\n"
+                        "       jmp   %%pc@(1f,%3:w:2)\n"
+                        "4:     movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "       movel %0@+,%1@+\n"
+                        "1:     dbra  %2,4b\n"
+                        "       clrw  %2\n"
+                        "       subql #1,%2\n"
+                        "       jpl   4b"
+                        : "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1)
+                        : "0" (lfrom), "1" (lto), "2" (temp));
 #else
-  const char *c_from = from;
-  char *c_to = to;
-  while (n-- > 0)
-    *c_to++ = *c_from++;
-  return((void *) to);
+                for (; temp; temp--)
+                        *lto++ = *lfrom++;
 #endif
+                to = lto;
+                from = lfrom;
+        }
+        if (n & 2) {
+                short *sto = to;
+                const short *sfrom = from;
+                *sto++ = *sfrom++;
+                to = sto;
+                from = sfrom;
+        }
+        if (n & 1) {
+                char *cto = to;
+                const char *cfrom = from;
+                *cto = *cfrom;
+        }
+        return xto;
 }
+EXPORT_SYMBOL(memcpy);
diff --git a/arch/m68k/lib/memmove.c b/arch/m68k/lib/memmove.c
index b3dcfe9dab7e..6519f7f349f6 100644
--- a/arch/m68k/lib/memmove.c
+++ b/arch/m68k/lib/memmove.c
@@ -4,8 +4,6 @@
  * for more details.
  */
 
-#define __IN_STRING_C
-
 #include <linux/module.h>
 #include <linux/string.h>
 
diff --git a/arch/m68k/lib/memset.c b/arch/m68k/lib/memset.c
index 1389bf455633..f649e6a2e644 100644
--- a/arch/m68k/lib/memset.c
+++ b/arch/m68k/lib/memset.c
@@ -1,47 +1,75 @@
-#include <linux/types.h>
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
 
-void * memset(void * s, int c, size_t count)
+#include <linux/module.h>
+#include <linux/string.h>
+
+void *memset(void *s, int c, size_t count)
 {
-  void *xs = s;
-  size_t temp;
+        void *xs = s;
+        size_t temp;
 
-  if (!count)
-    return xs;
-  c &= 0xff;
-  c |= c << 8;
-  c |= c << 16;
-  if ((long) s & 1)
-    {
-      char *cs = s;
-      *cs++ = c;
-      s = cs;
-      count--;
-    }
-  if (count > 2 && (long) s & 2)
-    {
-      short *ss = s;
-      *ss++ = c;
-      s = ss;
-      count -= 2;
-    }
-  temp = count >> 2;
-  if (temp)
-    {
-      long *ls = s;
-      for (; temp; temp--)
-        *ls++ = c;
-      s = ls;
-    }
-  if (count & 2)
-    {
-      short *ss = s;
-      *ss++ = c;
-      s = ss;
-    }
-  if (count & 1)
-    {
-      char *cs = s;
-      *cs = c;
-    }
-  return xs;
+        if (!count)
+                return xs;
+        c &= 0xff;
+        c |= c << 8;
+        c |= c << 16;
+        if ((long)s & 1) {
+                char *cs = s;
+                *cs++ = c;
+                s = cs;
+                count--;
+        }
+        if (count > 2 && (long)s & 2) {
+                short *ss = s;
+                *ss++ = c;
+                s = ss;
+                count -= 2;
+        }
+        temp = count >> 2;
+        if (temp) {
+                long *ls = s;
+#if defined(__mc68020__) || defined(__mc68030__) || \
+    defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
+                size_t temp1;
+                asm volatile (
+                        "       movel %1,%2\n"
+                        "       andw  #7,%2\n"
+                        "       lsrl  #3,%1\n"
+                        "       negw  %2\n"
+                        "       jmp   %%pc@(2f,%2:w:2)\n"
+                        "1:     movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "       movel %3,%0@+\n"
+                        "2:     dbra  %1,1b\n"
+                        "       clrw  %1\n"
+                        "       subql #1,%1\n"
+                        "       jpl   1b"
+                        : "=a" (ls), "=d" (temp), "=&d" (temp1)
+                        : "d" (c), "0" (ls), "1" (temp));
+#else
+                for (; temp; temp--)
+                        *ls++ = c;
+#endif
+                s = ls;
+        }
+        if (count & 2) {
+                short *ss = s;
+                *ss++ = c;
+                s = ss;
+        }
+        if (count & 1) {
+                char *cs = s;
+                *cs = c;
+        }
+        return xs;
 }
+EXPORT_SYMBOL(memset);
diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c
index 16e0eb338ee0..079bafca073e 100644
--- a/arch/m68k/lib/muldi3.c
+++ b/arch/m68k/lib/muldi3.c
@@ -1,5 +1,98 @@
-#ifdef CONFIG_MMU
-#include "muldi3_mm.c"
+/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and 
+                           gcc-2.7.2.3/longlong.h which is: */
+/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#if defined(__mc68020__) || defined(__mc68030__) || \
+    defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
+
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mulu%.l %3,%1:%0"                                           \
+           : "=d" ((USItype)(w0)),                                      \
+             "=d" ((USItype)(w1))                                       \
+           : "%0" ((USItype)(u)),                                       \
+             "dmi" ((USItype)(v)))
+
 #else
-#include "muldi3_no.c"
+
+#define SI_TYPE_SIZE 32
+#define __BITS4 (SI_TYPE_SIZE / 4)
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+
+#define umul_ppmm(w1, w0, u, v)                                         \
+  do {                                                                  \
+    USItype __x0, __x1, __x2, __x3;                                     \
+    USItype __ul, __vl, __uh, __vh;                                     \
+                                                                        \
+    __ul = __ll_lowpart (u);                                            \
+    __uh = __ll_highpart (u);                                           \
+    __vl = __ll_lowpart (v);                                            \
+    __vh = __ll_highpart (v);                                           \
+                                                                        \
+    __x0 = (USItype) __ul * __vl;                                       \
+    __x1 = (USItype) __ul * __vh;                                       \
+    __x2 = (USItype) __uh * __vl;                                       \
+    __x3 = (USItype) __uh * __vh;                                       \
+                                                                        \
+    __x1 += __ll_highpart (__x0);/* this can't give carry */            \
+    __x1 += __x2;               /* but this indeed can */               \
+    if (__x1 < __x2)            /* did we get it? */                    \
+      __x3 += __ll_B;           /* yes, add it in the proper pos. */    \
+                                                                        \
+    (w1) = __x3 + __ll_highpart (__x1);                                 \
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);          \
+  } while (0)
+
 #endif
+
+#define __umulsidi3(u, v) \
+  ({DIunion __w;                                                        \
+    umul_ppmm (__w.s.high, __w.s.low, u, v);                            \
+    __w.ll; })
+
+typedef          int SItype     __attribute__ ((mode (SI)));
+typedef unsigned int USItype    __attribute__ ((mode (SI)));
+typedef          int DItype     __attribute__ ((mode (DI)));
+typedef int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype high, low;};
+
+typedef union
+{
+  struct DIstruct s;
+  DItype ll;
+} DIunion;
+
+DItype
+__muldi3 (DItype u, DItype v)
+{
+  DIunion w;
+  DIunion uu, vv;
+
+  uu.ll = u,
+  vv.ll = v;
+
+  w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+  w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+               + (USItype) uu.s.high * (USItype) vv.s.low);
+
+  return w.ll;
+}
diff --git a/arch/m68k/lib/muldi3_mm.c b/arch/m68k/lib/muldi3_mm.c
deleted file mode 100644
index be4f275649e3..000000000000
--- a/arch/m68k/lib/muldi3_mm.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
-                           gcc-2.7.2.3/longlong.h which is: */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define BITS_PER_UNIT 8
-
-#define umul_ppmm(w1, w0, u, v) \
-  __asm__ ("mulu%.l %3,%1:%0"                                           \
-           : "=d" ((USItype)(w0)),                                      \
-             "=d" ((USItype)(w1))                                       \
-           : "%0" ((USItype)(u)),                                       \
-             "dmi" ((USItype)(v)))
-
-#define __umulsidi3(u, v) \
-  ({DIunion __w;                                                        \
-    umul_ppmm (__w.s.high, __w.s.low, u, v);                            \
-    __w.ll; })
-
-typedef          int SItype     __attribute__ ((mode (SI)));
-typedef unsigned int USItype    __attribute__ ((mode (SI)));
-typedef          int DItype     __attribute__ ((mode (DI)));
-typedef int word_type __attribute__ ((mode (__word__)));
-
-struct DIstruct {SItype high, low;};
-
-typedef union
-{
-  struct DIstruct s;
-  DItype ll;
-} DIunion;
-
-DItype
-__muldi3 (DItype u, DItype v)
-{
-  DIunion w;
-  DIunion uu, vv;
-
-  uu.ll = u,
-  vv.ll = v;
-
-  w.ll = __umulsidi3 (uu.s.low, vv.s.low);
-  w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
-               + (USItype) uu.s.high * (USItype) vv.s.low);
-
-  return w.ll;
-}
diff --git a/arch/m68k/lib/muldi3_no.c b/arch/m68k/lib/muldi3_no.c
deleted file mode 100644
index 34af72c30303..000000000000
--- a/arch/m68k/lib/muldi3_no.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and 
-                           gcc-2.7.2.3/longlong.h which is: */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING.  If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA.  */
-
-#define BITS_PER_UNIT 8
-#define SI_TYPE_SIZE 32
-
-#define __BITS4 (SI_TYPE_SIZE / 4)
-#define __ll_B (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
-#define __ll_highpart(t) ((USItype) (t) / __ll_B)
-
-#define umul_ppmm(w1, w0, u, v)                                         \
-  do {                                                                  \
-    USItype __x0, __x1, __x2, __x3;                                     \
-    USItype __ul, __vl, __uh, __vh;                                     \
-                                                                        \
-    __ul = __ll_lowpart (u);                                            \
-    __uh = __ll_highpart (u);                                           \
-    __vl = __ll_lowpart (v);                                            \
-    __vh = __ll_highpart (v);                                           \
-                                                                        \
-    __x0 = (USItype) __ul * __vl;                                       \
-    __x1 = (USItype) __ul * __vh;                                       \
-    __x2 = (USItype) __uh * __vl;                                       \
-    __x3 = (USItype) __uh * __vh;                                       \
-                                                                        \
-    __x1 += __ll_highpart (__x0);/* this can't give carry */            \
-    __x1 += __x2;               /* but this indeed can */               \
-    if (__x1 < __x2)            /* did we get it? */                    \
-      __x3 += __ll_B;           /* yes, add it in the proper pos. */    \
-                                                                        \
-    (w1) = __x3 + __ll_highpart (__x1);                                 \
-    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);          \
-  } while (0)
-
-#define __umulsidi3(u, v) \
-  ({DIunion __w;                                                        \
-    umul_ppmm (__w.s.high, __w.s.low, u, v);                            \
-    __w.ll; })
-
-typedef          int SItype     __attribute__ ((mode (SI)));
-typedef unsigned int USItype    __attribute__ ((mode (SI)));
-typedef          int DItype     __attribute__ ((mode (DI)));
-typedef int word_type __attribute__ ((mode (__word__)));
-
-struct DIstruct {SItype high, low;};
-
-typedef union
-{
-  struct DIstruct s;
-  DItype ll;
-} DIunion;
-
-DItype
-__muldi3 (DItype u, DItype v)
-{
-  DIunion w;
-  DIunion uu, vv;
-
-  uu.ll = u,
-  vv.ll = v;
-
-  w.ll = __umulsidi3 (uu.s.low, vv.s.low);
-  w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
-               + (USItype) uu.s.high * (USItype) vv.s.low);
-
-  return w.ll;
-}
diff --git a/arch/m68k/lib/string.c b/arch/m68k/lib/string.c
index d399c5f25636..b9a57abfad08 100644
--- a/arch/m68k/lib/string.c
+++ b/arch/m68k/lib/string.c
@@ -20,226 +20,3 @@ char *strcat(char *dest, const char *src)
         return __kernel_strcpy(dest + __kernel_strlen(dest), src);
 }
 EXPORT_SYMBOL(strcat);
-
-void *memset(void *s, int c, size_t count)
-{
-        void *xs = s;
-        size_t temp, temp1;
-
-        if (!count)
-                return xs;
-        c &= 0xff;
-        c |= c << 8;
-        c |= c << 16;
-        if ((long)s & 1) {
-                char *cs = s;
-                *cs++ = c;
-                s = cs;
-                count--;
-        }
-        if (count > 2 && (long)s & 2) {
-                short *ss = s;
-                *ss++ = c;
-                s = ss;
-                count -= 2;
-        }
-        temp = count >> 2;
-        if (temp) {
-                long *ls = s;
-
-                asm volatile (
-                        "       movel %1,%2\n"
-                        "       andw  #7,%2\n"
-                        "       lsrl  #3,%1\n"
-                        "       negw  %2\n"
-                        "       jmp   %%pc@(2f,%2:w:2)\n"
-                        "1:     movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "       movel %3,%0@+\n"
-                        "2:     dbra  %1,1b\n"
-                        "       clrw  %1\n"
-                        "       subql #1,%1\n"
-                        "       jpl   1b"
-                        : "=a" (ls), "=d" (temp), "=&d" (temp1)
-                        : "d" (c), "0" (ls), "1" (temp));
-                s = ls;
-        }
-        if (count & 2) {
-                short *ss = s;
-                *ss++ = c;
-                s = ss;
-        }
-        if (count & 1) {
-                char *cs = s;
-                *cs = c;
-        }
-        return xs;
-}
-EXPORT_SYMBOL(memset);
-
-void *memcpy(void *to, const void *from, size_t n)
-{
-        void *xto = to;
-        size_t temp, temp1;
-
-        if (!n)
-                return xto;
-        if ((long)to & 1) {
-                char *cto = to;
-                const char *cfrom = from;
-                *cto++ = *cfrom++;
-                to = cto;
-                from = cfrom;
-                n--;
-        }
-        if (n > 2 && (long)to & 2) {
-                short *sto = to;
-                const short *sfrom = from;
-                *sto++ = *sfrom++;
-                to = sto;
-                from = sfrom;
-                n -= 2;
-        }
-        temp = n >> 2;
-        if (temp) {
-                long *lto = to;
-                const long *lfrom = from;
-
-                asm volatile (
-                        "       movel %2,%3\n"
-                        "       andw  #7,%3\n"
-                        "       lsrl  #3,%2\n"
-                        "       negw  %3\n"
-                        "       jmp   %%pc@(1f,%3:w:2)\n"
-                        "4:     movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "       movel %0@+,%1@+\n"
-                        "1:     dbra  %2,4b\n"
-                        "       clrw  %2\n"
-                        "       subql #1,%2\n"
-                        "       jpl   4b"
-                        : "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1)
-                        : "0" (lfrom), "1" (lto), "2" (temp));
-                to = lto;
-                from = lfrom;
-        }
-        if (n & 2) {
-                short *sto = to;
-                const short *sfrom = from;
-                *sto++ = *sfrom++;
-                to = sto;
-                from = sfrom;
-        }
-        if (n & 1) {
-                char *cto = to;
-                const char *cfrom = from;
-                *cto = *cfrom;
-        }
-        return xto;
-}
-EXPORT_SYMBOL(memcpy);
-
-void *memmove(void *dest, const void *src, size_t n)
-{
-        void *xdest = dest;
-        size_t temp;
-
-        if (!n)
-                return xdest;
-
-        if (dest < src) {
-                if ((long)dest & 1) {
-                        char *cdest = dest;
-                        const char *csrc = src;
-                        *cdest++ = *csrc++;
-                        dest = cdest;
-                        src = csrc;
-                        n--;
-                }
-                if (n > 2 && (long)dest & 2) {
-                        short *sdest = dest;
-                        const short *ssrc = src;
-                        *sdest++ = *ssrc++;
-                        dest = sdest;
-                        src = ssrc;
-                        n -= 2;
-                }
-                temp = n >> 2;
-                if (temp) {
-                        long *ldest = dest;
-                        const long *lsrc = src;
-                        temp--;
-                        do
-                                *ldest++ = *lsrc++;
-                        while (temp--);
-                        dest = ldest;
-                        src = lsrc;
-                }
-                if (n & 2) {
-                        short *sdest = dest;
-                        const short *ssrc = src;
-                        *sdest++ = *ssrc++;
-                        dest = sdest;
-                        src = ssrc;
-                }
-                if (n & 1) {
-                        char *cdest = dest;
-                        const char *csrc = src;
-                        *cdest = *csrc;
-                }
-        } else {
-                dest = (char *)dest + n;
-                src = (const char *)src + n;
-                if ((long)dest & 1) {
-                        char *cdest = dest;
-                        const char *csrc = src;
-                        *--cdest = *--csrc;
-                        dest = cdest;
-                        src = csrc;
-                        n--;
-                }
-                if (n > 2 && (long)dest & 2) {
-                        short *sdest = dest;
-                        const short *ssrc = src;
-                        *--sdest = *--ssrc;
-                        dest = sdest;
-                        src = ssrc;
-                        n -= 2;
-                }
-                temp = n >> 2;
-                if (temp) {
-                        long *ldest = dest;
-                        const long *lsrc = src;
-                        temp--;
-                        do
-                                *--ldest = *--lsrc;
-                        while (temp--);
-                        dest = ldest;
-                        src = lsrc;
-                }
-                if (n & 2) {
-                        short *sdest = dest;
-                        const short *ssrc = src;
-                        *--sdest = *--ssrc;
-                        dest = sdest;
-                        src = ssrc;
-                }
-                if (n & 1) {
-                        char *cdest = dest;
-                        const char *csrc = src;
-                        *--cdest = *--csrc;
-                }
-        }
-        return xdest;
-}
-EXPORT_SYMBOL(memmove);
diff --git a/arch/m68k/mm/Makefile b/arch/m68k/mm/Makefile
index b60270e4954b..09cadf1058d5 100644
--- a/arch/m68k/mm/Makefile
+++ b/arch/m68k/mm/Makefile
@@ -1,5 +1,9 @@
-ifdef CONFIG_MMU
-include arch/m68k/mm/Makefile_mm
-else
-include arch/m68k/mm/Makefile_no
-endif
+#
+# Makefile for the linux m68k-specific parts of the memory manager.
+#
+
+obj-y   := init.o
+
+obj-$(CONFIG_MMU)               += cache.o fault.o hwtest.o
+obj-$(CONFIG_MMU_MOTOROLA)      += kmap.o memory.o motorola.o
+obj-$(CONFIG_MMU_SUN3)          += sun3kmap.o sun3mmu.o
diff --git a/arch/m68k/mm/Makefile_mm b/arch/m68k/mm/Makefile_mm
deleted file mode 100644
index 5eaa43c4cb3c..000000000000
--- a/arch/m68k/mm/Makefile_mm
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux m68k-specific parts of the memory manager.
-#
-
-obj-y           := cache.o init.o fault.o hwtest.o
-
-obj-$(CONFIG_MMU_MOTOROLA)      += kmap.o memory.o motorola.o
-obj-$(CONFIG_MMU_SUN3)          += sun3kmap.o sun3mmu.o
diff --git a/arch/m68k/mm/Makefile_no b/arch/m68k/mm/Makefile_no
deleted file mode 100644
index b54ab6b4b523..000000000000
--- a/arch/m68k/mm/Makefile_no
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux m68knommu specific parts of the memory manager.
-#
-
-obj-y += init.o kmap.o
diff --git a/arch/m68k/mm/init_mm.c b/arch/m68k/mm/init_mm.c
index 8bc842554e5b..9113c2f17607 100644
--- a/arch/m68k/mm/init_mm.c
+++ b/arch/m68k/mm/init_mm.c
@@ -32,8 +32,6 @@
 #include <asm/sections.h>
 #include <asm/tlb.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 pg_data_t pg_data_map[MAX_NUMNODES];
 EXPORT_SYMBOL(pg_data_map);
 
diff --git a/arch/m68k/mm/init_no.c b/arch/m68k/mm/init_no.c
index 8a6653f56bd8..7cbd7bd1f8bc 100644
--- a/arch/m68k/mm/init_no.c
+++ b/arch/m68k/mm/init_no.c
@@ -38,28 +38,10 @@
 #include <asm/system.h>
 #include <asm/machdep.h>
 
-#undef DEBUG
-
-extern void die_if_kernel(char *,struct pt_regs *,long);
-extern void free_initmem(void);
-
 /*
- * BAD_PAGE is the page that is used for page faults when linux
- * is out-of-memory. Older versions of linux just did a
- * do_exit(), but using this instead means there is less risk
- * for a process dying in kernel mode, possibly leaving a inode
- * unused etc..
- *
- * BAD_PAGETABLE is the accompanying page-table: it is initialized
- * to point to BAD_PAGE entries.
- *
  * ZERO_PAGE is a special page that is used for zero-initialized
  * data and COW.
  */
-static unsigned long empty_bad_page_table;
-
-static unsigned long empty_bad_page;
-
 unsigned long empty_zero_page;
 
 extern unsigned long memory_start;
@@ -77,22 +59,9 @@ void __init paging_init(void)
          * Make sure start_mem is page aligned, otherwise bootmem and
          * page_alloc get different views of the world.
          */
-#ifdef DEBUG
-        unsigned long start_mem = PAGE_ALIGN(memory_start);
-#endif
         unsigned long end_mem   = memory_end & PAGE_MASK;
+        unsigned long zones_size[MAX_NR_ZONES] = {0, };
 
-#ifdef DEBUG
-        printk (KERN_DEBUG "start_mem is %#lx\nvirtual_end is %#lx\n",
-                start_mem, end_mem);
-#endif
-
-        /*
-         * Initialize the bad page table and bad page to point
-         * to a couple of allocated pages.
-         */
-        empty_bad_page_table = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
-        empty_bad_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
         empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
         memset((void *)empty_zero_page, 0, PAGE_SIZE);
 
@@ -101,19 +70,8 @@ void __init paging_init(void)
          */
         set_fs (USER_DS);
 
-#ifdef DEBUG
-        printk (KERN_DEBUG "before free_area_init\n");
-
-        printk (KERN_DEBUG "free_area_init -> start_mem is %#lx\nvirtual_end is %#lx\n",
-                start_mem, end_mem);
-#endif
-
-        {
-                unsigned long zones_size[MAX_NR_ZONES] = {0, };
-
-                zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
-                free_area_init(zones_size);
-        }
+        zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
+        free_area_init(zones_size);
 }
 
 void __init mem_init(void)
@@ -166,8 +124,7 @@ void free_initrd_mem(unsigned long start, unsigned long end)
 }
 #endif
 
-void
-free_initmem()
+void free_initmem(void)
 {
 #ifdef CONFIG_RAMKERNEL
         unsigned long addr;
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index a373d136b2b2..69345849454b 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -1,5 +1,367 @@
-#ifdef CONFIG_MMU
-#include "kmap_mm.c"
+/*
+ *  linux/arch/m68k/mm/kmap.c
+ *
+ *  Copyright (C) 1997 Roman Hodek
+ *
+ *  10/01/99 cleaned up the code and changing to the same interface
+ *           used by other architectures                /Roman Zippel
+ */
+
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+#undef DEBUG
+
+#define PTRTREESIZE     (256*1024)
+
+/*
+ * For 040/060 we can use the virtual memory area like other architectures,
+ * but for 020/030 we want to use early termination page descriptor and we
+ * can't mix this with normal page descriptors, so we have to copy that code
+ * (mm/vmalloc.c) and return appriorate aligned addresses.
+ */
+
+#ifdef CPU_M68040_OR_M68060_ONLY
+
+#define IO_SIZE         PAGE_SIZE
+
+static inline struct vm_struct *get_io_area(unsigned long size)
+{
+        return get_vm_area(size, VM_IOREMAP);
+}
+
+
+static inline void free_io_area(void *addr)
+{
+        vfree((void *)(PAGE_MASK & (unsigned long)addr));
+}
+
 #else
-#include "kmap_no.c"
+
+#define IO_SIZE         (256*1024)
+
+static struct vm_struct *iolist;
+
+static struct vm_struct *get_io_area(unsigned long size)
+{
+        unsigned long addr;
+        struct vm_struct **p, *tmp, *area;
+
+        area = kmalloc(sizeof(*area), GFP_KERNEL);
+        if (!area)
+                return NULL;
+        addr = KMAP_START;
+        for (p = &iolist; (tmp = *p) ; p = &tmp->next) {
+                if (size + addr < (unsigned long)tmp->addr)
+                        break;
+                if (addr > KMAP_END-size) {
+                        kfree(area);
+                        return NULL;
+                }
+                addr = tmp->size + (unsigned long)tmp->addr;
+        }
+        area->addr = (void *)addr;
+        area->size = size + IO_SIZE;
+        area->next = *p;
+        *p = area;
+        return area;
+}
+
+static inline void free_io_area(void *addr)
+{
+        struct vm_struct **p, *tmp;
+
+        if (!addr)
+                return;
+        addr = (void *)((unsigned long)addr & -IO_SIZE);
+        for (p = &iolist ; (tmp = *p) ; p = &tmp->next) {
+                if (tmp->addr == addr) {
+                        *p = tmp->next;
+                        __iounmap(tmp->addr, tmp->size);
+                        kfree(tmp);
+                        return;
+                }
+        }
+}
+
 #endif
+
+/*
+ * Map some physical address range into the kernel address space.
+ */
+/* Rewritten by Andreas Schwab to remove all races. */
+
+void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
+{
+        struct vm_struct *area;
+        unsigned long virtaddr, retaddr;
+        long offset;
+        pgd_t *pgd_dir;
+        pmd_t *pmd_dir;
+        pte_t *pte_dir;
+
+        /*
+         * Don't allow mappings that wrap..
+         */
+        if (!size || physaddr > (unsigned long)(-size))
+                return NULL;
+
+#ifdef CONFIG_AMIGA
+        if (MACH_IS_AMIGA) {
+                if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000)
+                    && (cacheflag == IOMAP_NOCACHE_SER))
+                        return (void __iomem *)physaddr;
+        }
+#endif
+
+#ifdef DEBUG
+        printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
+#endif
+        /*
+         * Mappings have to be aligned
+         */
+        offset = physaddr & (IO_SIZE - 1);
+        physaddr &= -IO_SIZE;
+        size = (size + offset + IO_SIZE - 1) & -IO_SIZE;
+
+        /*
+         * Ok, go for it..
+         */
+        area = get_io_area(size);
+        if (!area)
+                return NULL;
+
+        virtaddr = (unsigned long)area->addr;
+        retaddr = virtaddr + offset;
+#ifdef DEBUG
+        printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr);
+#endif
+
+        /*
+         * add cache and table flags to physical address
+         */
+        if (CPU_IS_040_OR_060) {
+                physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 |
+                             _PAGE_ACCESSED | _PAGE_DIRTY);
+                switch (cacheflag) {
+                case IOMAP_FULL_CACHING:
+                        physaddr |= _PAGE_CACHE040;
+                        break;
+                case IOMAP_NOCACHE_SER:
+                default:
+                        physaddr |= _PAGE_NOCACHE_S;
+                        break;
+                case IOMAP_NOCACHE_NONSER:
+                        physaddr |= _PAGE_NOCACHE;
+                        break;
+                case IOMAP_WRITETHROUGH:
+                        physaddr |= _PAGE_CACHE040W;
+                        break;
+                }
+        } else {
+                physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+                switch (cacheflag) {
+                case IOMAP_NOCACHE_SER:
+                case IOMAP_NOCACHE_NONSER:
+                default:
+                        physaddr |= _PAGE_NOCACHE030;
+                        break;
+                case IOMAP_FULL_CACHING:
+                case IOMAP_WRITETHROUGH:
+                        break;
+                }
+        }
+
+        while ((long)size > 0) {
+#ifdef DEBUG
+                if (!(virtaddr & (PTRTREESIZE-1)))
+                        printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr);
+#endif
+                pgd_dir = pgd_offset_k(virtaddr);
+                pmd_dir = pmd_alloc(&init_mm, pgd_dir, virtaddr);
+                if (!pmd_dir) {
+                        printk("ioremap: no mem for pmd_dir\n");
+                        return NULL;
+                }
+
+                if (CPU_IS_020_OR_030) {
+                        pmd_dir->pmd[(virtaddr/PTRTREESIZE) & 15] = physaddr;
+                        physaddr += PTRTREESIZE;
+                        virtaddr += PTRTREESIZE;
+                        size -= PTRTREESIZE;
+                } else {
+                        pte_dir = pte_alloc_kernel(pmd_dir, virtaddr);
+                        if (!pte_dir) {
+                                printk("ioremap: no mem for pte_dir\n");
+                                return NULL;
+                        }
+
+                        pte_val(*pte_dir) = physaddr;
+                        virtaddr += PAGE_SIZE;
+                        physaddr += PAGE_SIZE;
+                        size -= PAGE_SIZE;
+                }
+        }
+#ifdef DEBUG
+        printk("\n");
+#endif
+        flush_tlb_all();
+
+        return (void __iomem *)retaddr;
+}
+EXPORT_SYMBOL(__ioremap);
+
+/*
+ * Unmap a ioremap()ed region again
+ */
+void iounmap(void __iomem *addr)
+{
+#ifdef CONFIG_AMIGA
+        if ((!MACH_IS_AMIGA) ||
+            (((unsigned long)addr < 0x40000000) ||
+             ((unsigned long)addr > 0x60000000)))
+                        free_io_area((__force void *)addr);
+#else
+        free_io_area((__force void *)addr);
+#endif
+}
+EXPORT_SYMBOL(iounmap);
+
+/*
+ * __iounmap unmaps nearly everything, so be careful
+ * it doesn't free currently pointer/page tables anymore but it
+ * wans't used anyway and might be added later.
+ */
+void __iounmap(void *addr, unsigned long size)
+{
+        unsigned long virtaddr = (unsigned long)addr;
+        pgd_t *pgd_dir;
+        pmd_t *pmd_dir;
+        pte_t *pte_dir;
+
+        while ((long)size > 0) {
+                pgd_dir = pgd_offset_k(virtaddr);
+                if (pgd_bad(*pgd_dir)) {
+                        printk("iounmap: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
+                        pgd_clear(pgd_dir);
+                        return;
+                }
+                pmd_dir = pmd_offset(pgd_dir, virtaddr);
+
+                if (CPU_IS_020_OR_030) {
+                        int pmd_off = (virtaddr/PTRTREESIZE) & 15;
+                        int pmd_type = pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK;
+
+                        if (pmd_type == _PAGE_PRESENT) {
+                                pmd_dir->pmd[pmd_off] = 0;
+                                virtaddr += PTRTREESIZE;
+                                size -= PTRTREESIZE;
+                                continue;
+                        } else if (pmd_type == 0)
+                                continue;
+                }
+
+                if (pmd_bad(*pmd_dir)) {
+                        printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
+                        pmd_clear(pmd_dir);
+                        return;
+                }
+                pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
+
+                pte_val(*pte_dir) = 0;
+                virtaddr += PAGE_SIZE;
+                size -= PAGE_SIZE;
+        }
+
+        flush_tlb_all();
+}
+
+/*
+ * Set new cache mode for some kernel address space.
+ * The caller must push data for that range itself, if such data may already
+ * be in the cache.
+ */
+void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
+{
+        unsigned long virtaddr = (unsigned long)addr;
+        pgd_t *pgd_dir;
+        pmd_t *pmd_dir;
+        pte_t *pte_dir;
+
+        if (CPU_IS_040_OR_060) {
+                switch (cmode) {
+                case IOMAP_FULL_CACHING:
+                        cmode = _PAGE_CACHE040;
+                        break;
+                case IOMAP_NOCACHE_SER:
+                default:
+                        cmode = _PAGE_NOCACHE_S;
+                        break;
+                case IOMAP_NOCACHE_NONSER:
+                        cmode = _PAGE_NOCACHE;
+                        break;
+                case IOMAP_WRITETHROUGH:
+                        cmode = _PAGE_CACHE040W;
+                        break;
+                }
+        } else {
+                switch (cmode) {
+                case IOMAP_NOCACHE_SER:
+                case IOMAP_NOCACHE_NONSER:
+                default:
+                        cmode = _PAGE_NOCACHE030;
+                        break;
+                case IOMAP_FULL_CACHING:
+                case IOMAP_WRITETHROUGH:
+                        cmode = 0;
+                }
+        }
+
+        while ((long)size > 0) {
+                pgd_dir = pgd_offset_k(virtaddr);
+                if (pgd_bad(*pgd_dir)) {
+                        printk("iocachemode: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
+                        pgd_clear(pgd_dir);
+                        return;
+                }
+                pmd_dir = pmd_offset(pgd_dir, virtaddr);
+
+                if (CPU_IS_020_OR_030) {
+                        int pmd_off = (virtaddr/PTRTREESIZE) & 15;
+
+                        if ((pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK) == _PAGE_PRESENT) {
+                                pmd_dir->pmd[pmd_off] = (pmd_dir->pmd[pmd_off] &
+                                                         _CACHEMASK040) | cmode;
+                                virtaddr += PTRTREESIZE;
+                                size -= PTRTREESIZE;
+                                continue;
+                        }
+                }
+
+                if (pmd_bad(*pmd_dir)) {
+                        printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
+                        pmd_clear(pmd_dir);
+                        return;
+                }
+                pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
+
+                pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode;
+                virtaddr += PAGE_SIZE;
+                size -= PAGE_SIZE;
+        }
+
+        flush_tlb_all();
+}
+EXPORT_SYMBOL(kernel_set_cachemode);
diff --git a/arch/m68k/mm/kmap_mm.c b/arch/m68k/mm/kmap_mm.c
deleted file mode 100644
index 69345849454b..000000000000
--- a/arch/m68k/mm/kmap_mm.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- *  linux/arch/m68k/mm/kmap.c
- *
- *  Copyright (C) 1997 Roman Hodek
- *
- *  10/01/99 cleaned up the code and changing to the same interface
- *           used by other architectures                /Roman Zippel
- */
-
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/vmalloc.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-#undef DEBUG
-
-#define PTRTREESIZE     (256*1024)
-
-/*
- * For 040/060 we can use the virtual memory area like other architectures,
- * but for 020/030 we want to use early termination page descriptor and we
- * can't mix this with normal page descriptors, so we have to copy that code
- * (mm/vmalloc.c) and return appriorate aligned addresses.
- */
-
-#ifdef CPU_M68040_OR_M68060_ONLY
-
-#define IO_SIZE         PAGE_SIZE
-
-static inline struct vm_struct *get_io_area(unsigned long size)
-{
-        return get_vm_area(size, VM_IOREMAP);
-}
-
-
-static inline void free_io_area(void *addr)
-{
-        vfree((void *)(PAGE_MASK & (unsigned long)addr));
-}
-
-#else
-
-#define IO_SIZE         (256*1024)
-
-static struct vm_struct *iolist;
-
-static struct vm_struct *get_io_area(unsigned long size)
-{
-        unsigned long addr;
-        struct vm_struct **p, *tmp, *area;
-
-        area = kmalloc(sizeof(*area), GFP_KERNEL);
-        if (!area)
-                return NULL;
-        addr = KMAP_START;
-        for (p = &iolist; (tmp = *p) ; p = &tmp->next) {
-                if (size + addr < (unsigned long)tmp->addr)
-                        break;
-                if (addr > KMAP_END-size) {
-                        kfree(area);
-                        return NULL;
-                }
-                addr = tmp->size + (unsigned long)tmp->addr;
-        }
-        area->addr = (void *)addr;
-        area->size = size + IO_SIZE;
-        area->next = *p;
-        *p = area;
-        return area;
-}
-
-static inline void free_io_area(void *addr)
-{
-        struct vm_struct **p, *tmp;
-
-        if (!addr)
-                return;
-        addr = (void *)((unsigned long)addr & -IO_SIZE);
-        for (p = &iolist ; (tmp = *p) ; p = &tmp->next) {
-                if (tmp->addr == addr) {
-                        *p = tmp->next;
-                        __iounmap(tmp->addr, tmp->size);
-                        kfree(tmp);
-                        return;
-                }
-        }
-}
-
-#endif
-
-/*
- * Map some physical address range into the kernel address space.
- */
-/* Rewritten by Andreas Schwab to remove all races. */
-
-void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
-{
-        struct vm_struct *area;
-        unsigned long virtaddr, retaddr;
-        long offset;
-        pgd_t *pgd_dir;
-        pmd_t *pmd_dir;
-        pte_t *pte_dir;
-
-        /*
-         * Don't allow mappings that wrap..
-         */
-        if (!size || physaddr > (unsigned long)(-size))
-                return NULL;
-
-#ifdef CONFIG_AMIGA
-        if (MACH_IS_AMIGA) {
-                if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000)
-                    && (cacheflag == IOMAP_NOCACHE_SER))
-                        return (void __iomem *)physaddr;
-        }
-#endif
-
-#ifdef DEBUG
-        printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
-#endif
-        /*
-         * Mappings have to be aligned
-         */
-        offset = physaddr & (IO_SIZE - 1);
-        physaddr &= -IO_SIZE;
-        size = (size + offset + IO_SIZE - 1) & -IO_SIZE;
-
-        /*
-         * Ok, go for it..
-         */
-        area = get_io_area(size);
-        if (!area)
-                return NULL;
-
-        virtaddr = (unsigned long)area->addr;
-        retaddr = virtaddr + offset;
-#ifdef DEBUG
-        printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr);
-#endif
-
-        /*
-         * add cache and table flags to physical address
-         */
-        if (CPU_IS_040_OR_060) {
-                physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 |
-                             _PAGE_ACCESSED | _PAGE_DIRTY);
-                switch (cacheflag) {
-                case IOMAP_FULL_CACHING:
-                        physaddr |= _PAGE_CACHE040;
-                        break;
-                case IOMAP_NOCACHE_SER:
-                default:
-                        physaddr |= _PAGE_NOCACHE_S;
-                        break;
-                case IOMAP_NOCACHE_NONSER:
-                        physaddr |= _PAGE_NOCACHE;
-                        break;
-                case IOMAP_WRITETHROUGH:
-                        physaddr |= _PAGE_CACHE040W;
-                        break;
-                }
-        } else {
-                physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
-                switch (cacheflag) {
-                case IOMAP_NOCACHE_SER:
-                case IOMAP_NOCACHE_NONSER:
-                default:
-                        physaddr |= _PAGE_NOCACHE030;
-                        break;
-                case IOMAP_FULL_CACHING:
-                case IOMAP_WRITETHROUGH:
-                        break;
-                }
-        }
-
-        while ((long)size > 0) {
-#ifdef DEBUG
-                if (!(virtaddr & (PTRTREESIZE-1)))
-                        printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr);
-#endif
-                pgd_dir = pgd_offset_k(virtaddr);
-                pmd_dir = pmd_alloc(&init_mm, pgd_dir, virtaddr);
-                if (!pmd_dir) {
-                        printk("ioremap: no mem for pmd_dir\n");
-                        return NULL;
-                }
-
-                if (CPU_IS_020_OR_030) {
-                        pmd_dir->pmd[(virtaddr/PTRTREESIZE) & 15] = physaddr;
-                        physaddr += PTRTREESIZE;
-                        virtaddr += PTRTREESIZE;
-                        size -= PTRTREESIZE;
-                } else {
-                        pte_dir = pte_alloc_kernel(pmd_dir, virtaddr);
-                        if (!pte_dir) {
-                                printk("ioremap: no mem for pte_dir\n");
-                                return NULL;
-                        }
-
-                        pte_val(*pte_dir) = physaddr;
-                        virtaddr += PAGE_SIZE;
-                        physaddr += PAGE_SIZE;
-                        size -= PAGE_SIZE;
-                }
-        }
-#ifdef DEBUG
-        printk("\n");
-#endif
-        flush_tlb_all();
-
-        return (void __iomem *)retaddr;
-}
-EXPORT_SYMBOL(__ioremap);
-
-/*
- * Unmap a ioremap()ed region again
- */
-void iounmap(void __iomem *addr)
-{
-#ifdef CONFIG_AMIGA
-        if ((!MACH_IS_AMIGA) ||
-            (((unsigned long)addr < 0x40000000) ||
-             ((unsigned long)addr > 0x60000000)))
-                        free_io_area((__force void *)addr);
-#else
-        free_io_area((__force void *)addr);
-#endif
-}
-EXPORT_SYMBOL(iounmap);
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-void __iounmap(void *addr, unsigned long size)
-{
-        unsigned long virtaddr = (unsigned long)addr;
-        pgd_t *pgd_dir;
-        pmd_t *pmd_dir;
-        pte_t *pte_dir;
-
-        while ((long)size > 0) {
-                pgd_dir = pgd_offset_k(virtaddr);
-                if (pgd_bad(*pgd_dir)) {
-                        printk("iounmap: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
-                        pgd_clear(pgd_dir);
-                        return;
-                }
-                pmd_dir = pmd_offset(pgd_dir, virtaddr);
-
-                if (CPU_IS_020_OR_030) {
-                        int pmd_off = (virtaddr/PTRTREESIZE) & 15;
-                        int pmd_type = pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK;
-
-                        if (pmd_type == _PAGE_PRESENT) {
-                                pmd_dir->pmd[pmd_off] = 0;
-                                virtaddr += PTRTREESIZE;
-                                size -= PTRTREESIZE;
-                                continue;
-                        } else if (pmd_type == 0)
-                                continue;
-                }
-
-                if (pmd_bad(*pmd_dir)) {
-                        printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
-                        pmd_clear(pmd_dir);
-                        return;
-                }
-                pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
-
-                pte_val(*pte_dir) = 0;
-                virtaddr += PAGE_SIZE;
-                size -= PAGE_SIZE;
-        }
-
-        flush_tlb_all();
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
-{
-        unsigned long virtaddr = (unsigned long)addr;
-        pgd_t *pgd_dir;
-        pmd_t *pmd_dir;
-        pte_t *pte_dir;
-
-        if (CPU_IS_040_OR_060) {
-                switch (cmode) {
-                case IOMAP_FULL_CACHING:
-                        cmode = _PAGE_CACHE040;
-                        break;
-                case IOMAP_NOCACHE_SER:
-                default:
-                        cmode = _PAGE_NOCACHE_S;
-                        break;
-                case IOMAP_NOCACHE_NONSER:
-                        cmode = _PAGE_NOCACHE;
-                        break;
-                case IOMAP_WRITETHROUGH:
-                        cmode = _PAGE_CACHE040W;
-                        break;
-                }
-        } else {
-                switch (cmode) {
-                case IOMAP_NOCACHE_SER:
-                case IOMAP_NOCACHE_NONSER:
-                default:
-                        cmode = _PAGE_NOCACHE030;
-                        break;
-                case IOMAP_FULL_CACHING:
-                case IOMAP_WRITETHROUGH:
-                        cmode = 0;
-                }
-        }
-
-        while ((long)size > 0) {
-                pgd_dir = pgd_offset_k(virtaddr);
-                if (pgd_bad(*pgd_dir)) {
-                        printk("iocachemode: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
-                        pgd_clear(pgd_dir);
-                        return;
-                }
-                pmd_dir = pmd_offset(pgd_dir, virtaddr);
-
-                if (CPU_IS_020_OR_030) {
-                        int pmd_off = (virtaddr/PTRTREESIZE) & 15;
-
-                        if ((pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK) == _PAGE_PRESENT) {
-                                pmd_dir->pmd[pmd_off] = (pmd_dir->pmd[pmd_off] &
-                                                         _CACHEMASK040) | cmode;
-                                virtaddr += PTRTREESIZE;
-                                size -= PTRTREESIZE;
-                                continue;
-                        }
-                }
-
-                if (pmd_bad(*pmd_dir)) {
-                        printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
-                        pmd_clear(pmd_dir);
-                        return;
-                }
-                pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
-
-                pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode;
-                virtaddr += PAGE_SIZE;
-                size -= PAGE_SIZE;
-        }
-
-        flush_tlb_all();
-}
-EXPORT_SYMBOL(kernel_set_cachemode);
diff --git a/arch/m68k/mm/kmap_no.c b/arch/m68k/mm/kmap_no.c
deleted file mode 100644
index ece8d5ad4e6c..000000000000
--- a/arch/m68k/mm/kmap_no.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  linux/arch/m68knommu/mm/kmap.c
- *
- *  Copyright (C) 2000 Lineo, <davidm@snapgear.com>
- *  Copyright (C) 2000-2002 David McCullough <davidm@snapgear.com>
- */
-
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/vmalloc.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-#undef DEBUG
-
-/*
- * Map some physical address range into the kernel address space.
- */
-void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
-{
-        return (void *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again.
- */
-void iounmap(void *addr)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
-{
-}
diff --git a/arch/m68k/platform/68328/entry.S b/arch/m68k/platform/68328/entry.S
index 676960cf022a..f68dce766c0a 100644
--- a/arch/m68k/platform/68328/entry.S
+++ b/arch/m68k/platform/68328/entry.S
@@ -10,7 +10,6 @@
  * Linux/m68k support by Hamish Macdonald
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/unistd.h>
@@ -80,7 +79,7 @@ ENTRY(system_call)
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1
         movel   %d1,%a2
-        btst    #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+        btst    #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
         jne     do_trace
         cmpl    #NR_syscalls,%d0
         jcc     badsys
@@ -107,12 +106,12 @@ Luser_return:
         andl    #-THREAD_SIZE,%d1
         movel   %d1,%a2
 1:
-        move    %a2@(TI_FLAGS),%d1      /* thread_info->flags */
+        move    %a2@(TINFO_FLAGS),%d1   /* thread_info->flags */
         jne     Lwork_to_do
         RESTORE_ALL
 
 Lwork_to_do:
-        movel   %a2@(TI_FLAGS),%d1      /* thread_info->flags */
+        movel   %a2@(TINFO_FLAGS),%d1   /* thread_info->flags */
         btst    #TIF_NEED_RESCHED,%d1
         jne     reschedule
 
diff --git a/arch/m68k/platform/68360/entry.S b/arch/m68k/platform/68360/entry.S
index 46c1b18c9dcb..a07b14feed92 100644
--- a/arch/m68k/platform/68360/entry.S
+++ b/arch/m68k/platform/68360/entry.S
@@ -12,7 +12,6 @@
  * M68360 Port by SED Systems, and Lineo.
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <asm/thread_info.h>
 #include <asm/unistd.h>
@@ -76,7 +75,7 @@ ENTRY(system_call)
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1
         movel   %d1,%a2
-        btst    #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+        btst    #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
         jne     do_trace
         cmpl    #NR_syscalls,%d0
         jcc     badsys
@@ -103,12 +102,12 @@ Luser_return:
         andl    #-THREAD_SIZE,%d1
         movel   %d1,%a2
 1:
-        move    %a2@(TI_FLAGS),%d1      /* thread_info->flags */
+        move    %a2@(TINFO_FLAGS),%d1   /* thread_info->flags */
         jne     Lwork_to_do
         RESTORE_ALL
 
 Lwork_to_do:
-        movel   %a2@(TI_FLAGS),%d1      /* thread_info->flags */
+        movel   %a2@(TINFO_FLAGS),%d1   /* thread_info->flags */
         btst    #TIF_NEED_RESCHED,%d1
         jne     reschedule
 
diff --git a/arch/m68k/platform/coldfire/dma.c b/arch/m68k/platform/coldfire/dma.c
index e88b95e2cc62..df5ce20d181c 100644
--- a/arch/m68k/platform/coldfire/dma.c
+++ b/arch/m68k/platform/coldfire/dma.c
@@ -9,6 +9,7 @@
 /***************************************************************************/
 
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <asm/dma.h>
 #include <asm/coldfire.h>
 #include <asm/mcfsim.h>
@@ -33,7 +34,9 @@ unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS] = {
         MCFDMA_BASE3,
 #endif
 };
+EXPORT_SYMBOL(dma_base_addr);
 
 unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
+EXPORT_SYMBOL(dma_device_address);
 
 /***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/entry.S b/arch/m68k/platform/coldfire/entry.S
index eab63f09965b..27c2b001161e 100644
--- a/arch/m68k/platform/coldfire/entry.S
+++ b/arch/m68k/platform/coldfire/entry.S
@@ -26,7 +26,6 @@
  * Bug, speed and maintainability fixes by Philippe De Muyter <phdm@macqel.be>
  */
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <asm/unistd.h>
 #include <asm/thread_info.h>
@@ -78,7 +77,7 @@ ENTRY(system_call)
         movel   %d2,%a0
         movel   %a0@,%a1                /* save top of frame */
         movel   %sp,%a1@(TASK_THREAD+THREAD_ESP0)
-        btst    #(TIF_SYSCALL_TRACE%8),%a0@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+        btst    #(TIF_SYSCALL_TRACE%8),%a0@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
         bnes    1f
 
         movel   %d3,%a0
@@ -113,11 +112,11 @@ ret_from_exception:
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1       /* at base of kernel stack */
         movel   %d1,%a0
-        movel   %a0@(TI_FLAGS),%d1      /* get thread_info->flags */
+        movel   %a0@(TINFO_FLAGS),%d1   /* get thread_info->flags */
         andl    #(1<<TIF_NEED_RESCHED),%d1
         jeq     Lkernel_return
 
-        movel   %a0@(TI_PREEMPTCOUNT),%d1
+        movel   %a0@(TINFO_PREEMPT),%d1
         cmpl    #0,%d1
         jne     Lkernel_return
 
@@ -137,14 +136,14 @@ Luser_return:
         movel   %sp,%d1                 /* get thread_info pointer */
         andl    #-THREAD_SIZE,%d1       /* at base of kernel stack */
         movel   %d1,%a0
-        movel   %a0@(TI_FLAGS),%d1      /* get thread_info->flags */
+        movel   %a0@(TINFO_FLAGS),%d1   /* get thread_info->flags */
         jne     Lwork_to_do             /* still work to do */
 
 Lreturn:
         RESTORE_USER
 
 Lwork_to_do:
-        movel   %a0@(TI_FLAGS),%d1      /* get thread_info->flags */
+        movel   %a0@(TINFO_FLAGS),%d1   /* get thread_info->flags */
         move    #0x2000,%sr             /* enable intrs again */
         btst    #TIF_NEED_RESCHED,%d1
         jne     reschedule
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index 6ae91a499184..c33483824a2e 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -8,7 +8,6 @@
 
 /*****************************************************************************/
 
-#include <linux/sys.h>
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/asm-offsets.h>
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index eccdefe70d4e..e446bab2427b 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -33,12 +33,6 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
         def_bool n
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
-config GENERIC_FIND_BIT_LE
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
diff --git a/arch/microblaze/include/asm/unistd.h b/arch/microblaze/include/asm/unistd.h
index 30edd61a6b8f..7d7092b917ac 100644
--- a/arch/microblaze/include/asm/unistd.h
+++ b/arch/microblaze/include/asm/unistd.h
@@ -390,8 +390,9 @@
 #define __NR_open_by_handle_at  372
 #define __NR_clock_adjtime      373
 #define __NR_syncfs             374
+#define __NR_setns              375
 
-#define __NR_syscalls           375
+#define __NR_syscalls           376
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
diff --git a/arch/microblaze/kernel/prom.c b/arch/microblaze/kernel/prom.c
index 00ee90f08343..b15cc219b1d9 100644
--- a/arch/microblaze/kernel/prom.c
+++ b/arch/microblaze/kernel/prom.c
@@ -130,7 +130,7 @@ void __init early_init_devtree(void *params)
          * device-tree, including the platform type, initrd location and
          * size, TCE reserve, and more ...
          */
-        of_scan_flat_dt(early_init_dt_scan_chosen, NULL);
+        of_scan_flat_dt(early_init_dt_scan_chosen, cmd_line);
 
         /* Scan memory nodes and rebuild MEMBLOCKs */
         memblock_init();
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index 85cea81d1ca1..d915a122c865 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -379,3 +379,4 @@ ENTRY(sys_call_table)
         .long sys_open_by_handle_at
         .long sys_clock_adjtime
         .long sys_syncfs
+        .long sys_setns                 /* 375 */
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index c8437866d3b7..213f2d671669 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -32,8 +32,6 @@ unsigned int __page_offset;
 EXPORT_SYMBOL(__page_offset);
 
 #else
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 static int init_bootmem_done;
 #endif /* CONFIG_MMU */
 
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index cef1a854487d..653da62d0682 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -821,14 +821,6 @@ config ARCH_SUPPORTS_OPROFILE
         bool
         default y if !MIPS_MT_SMTC
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_HWEIGHT
         bool
         default y
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 5358f90b4dd2..83ed00a5644a 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -76,15 +76,6 @@ config DEBUG_STACKOVERFLOW
           provides another way to check stack overflow happened on kernel mode
           stack usually caused by nested interruption.
 
-config DEBUG_STACK_USAGE
-        bool "Enable stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config SMTC_IDLE_HOOK_DEBUG
         bool "Enable additional debug checks before going into CPU idle loop"
         depends on DEBUG_KERNEL && MIPS_MT_SMTC
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
index 008f657116eb..0ee02f5e51cc 100644
--- a/arch/mips/cavium-octeon/flash_setup.c
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -16,7 +16,6 @@
 
 static struct map_info flash_map;
 static struct mtd_info *mymtd;
-#ifdef CONFIG_MTD_PARTITIONS
 static int nr_parts;
 static struct mtd_partition *parts;
 static const char *part_probe_types[] = {
@@ -26,7 +25,6 @@ static const char *part_probe_types[] = {
 #endif
         NULL
 };
-#endif
 
 /**
  * Module/ driver initialization.
@@ -63,17 +61,10 @@ static int __init flash_init(void)
                 if (mymtd) {
                         mymtd->owner = THIS_MODULE;
 
-#ifdef CONFIG_MTD_PARTITIONS
                         nr_parts = parse_mtd_partitions(mymtd,
                                                         part_probe_types,
                                                         &parts, 0);
-                        if (nr_parts > 0)
-                                add_mtd_partitions(mymtd, parts, nr_parts);
-                        else
-                                add_mtd_device(mymtd);
-#else
-                        add_mtd_device(mymtd);
-#endif
+                        mtd_device_register(mymtd, parts, nr_parts);
                 } else {
                         pr_err("Failed to register MTD device for flash\n");
                 }
diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig
index 22fdf2f0cc23..ad15fb10322b 100644
--- a/arch/mips/configs/bcm47xx_defconfig
+++ b/arch/mips/configs/bcm47xx_defconfig
@@ -16,7 +16,6 @@ CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
 CONFIG_TINY_RCU=y
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index f29b862d9db3..857d9b7858ad 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -14,9 +14,6 @@
 #ifdef CONFIG_OF
 #include <asm/bootinfo.h>
 
-/* which is compatible with the flattened device tree (FDT) */
-#define cmd_line arcs_cmdline
-
 extern int early_init_dt_scan_memory_arch(unsigned long node,
         const char *uname, int depth, void *data);
 
diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h
index 294cdb66c5fc..3adac3b53d19 100644
--- a/arch/mips/include/asm/suspend.h
+++ b/arch/mips/include/asm/suspend.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_SUSPEND_H
 #define __ASM_SUSPEND_H
 
-static inline int arch_prepare_suspend(void) { return 0; }
-
 /* References to section boundaries */
 extern const void __nosave_begin, __nosave_end;
 
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index fa2e37ea2be1..6fcfc480e9d0 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -363,16 +363,17 @@
 #define __NR_open_by_handle_at          (__NR_Linux + 340)
 #define __NR_clock_adjtime              (__NR_Linux + 341)
 #define __NR_syncfs                     (__NR_Linux + 342)
+#define __NR_setns                      (__NR_Linux + 343)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             342
+#define __NR_Linux_syscalls             343
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         342
+#define __NR_O32_Linux_syscalls         343
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -682,16 +683,17 @@
 #define __NR_open_by_handle_at          (__NR_Linux + 299)
 #define __NR_clock_adjtime              (__NR_Linux + 300)
 #define __NR_syncfs                     (__NR_Linux + 301)
+#define __NR_setns                      (__NR_Linux + 302)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             301
+#define __NR_Linux_syscalls             302
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          301
+#define __NR_64_Linux_syscalls          302
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -1006,16 +1008,17 @@
 #define __NR_open_by_handle_at          (__NR_Linux + 304)
 #define __NR_clock_adjtime              (__NR_Linux + 305)
 #define __NR_syncfs                     (__NR_Linux + 306)
+#define __NR_setns                      (__NR_Linux + 307)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             306
+#define __NR_Linux_syscalls             307
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         306
+#define __NR_N32_Linux_syscalls         307
 
 #ifdef __KERNEL__
 
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index a19811e98a41..5b7eade41fa3 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -83,7 +83,8 @@ void __init early_init_devtree(void *params)
          * device-tree, including the platform type, initrd location and
          * size, and more ...
          */
-        of_scan_flat_dt(early_init_dt_scan_chosen, NULL);
+        of_scan_flat_dt(early_init_dt_scan_chosen, arcs_cmdline);
+
 
         /* Scan memory nodes */
         of_scan_flat_dt(early_init_dt_scan_root, NULL);
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 7a8e1dd7f6f2..99e656e425f3 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -589,6 +589,7 @@ einval:	li	v0, -ENOSYS
         sys     sys_open_by_handle_at   3       /* 4340 */
         sys     sys_clock_adjtime       2
         sys     sys_syncfs              1
+        sys     sys_setns               2
         .endm
 
         /* We pre-compute the number of _instruction_ bytes needed to
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index 2d31c83224f9..fb0575f47f3d 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -428,4 +428,5 @@ sys_call_table:
         PTR     sys_open_by_handle_at
         PTR     sys_clock_adjtime               /* 5300 */
         PTR     sys_syncfs
+        PTR     sys_setns
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 38a0503b9a4a..4de0c5534e73 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -428,4 +428,5 @@ EXPORT(sysn32_call_table)
         PTR     sys_open_by_handle_at
         PTR     compat_sys_clock_adjtime        /* 6305 */
         PTR     sys_syncfs
+        PTR     sys_setns
         .size   sysn32_call_table,.-sysn32_call_table
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 91ea5e4041dd..4a387de08bfa 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -546,4 +546,5 @@ sys_call_table:
         PTR     compat_sys_open_by_handle_at    /* 4340 */
         PTR     compat_sys_clock_adjtime
         PTR     sys_syncfs
+        PTR     sys_setns
         .size   sys_call_table,.-sys_call_table
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 01af3876cf90..a81176f44c74 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -118,7 +118,7 @@ SECTIONS
                 EXIT_DATA
         }
 
-        PERCPU(1 << CONFIG_MIPS_L1_CACHE_SHIFT, PAGE_SIZE)
+        PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
         . = ALIGN(PAGE_SIZE);
         __init_end = .;
         /* freed after init ends here */
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 279599e9a779..1aadeb42c5a5 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -64,8 +64,6 @@
 
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * We have up to 8 empty zeroed pages so we can map one of the right colour
  * when needed.  This is necessary only on R4000 / R4400 SC and MC versions
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 812816c45662..ec38e00b2559 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -639,7 +639,6 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
                 .flags = IORESOURCE_MEM,
         };
         struct platform_device *pdev;
-#ifdef CONFIG_MTD_PARTITIONS
         static struct mtd_partition parts[2];
         struct physmap_flash_data pdata_part;
 
@@ -658,7 +657,7 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
                 pdata_part.parts = parts;
                 pdata = &pdata_part;
         }
-#endif
+
         pdev = platform_device_alloc("physmap-flash", no);
         if (!pdev ||
             platform_device_add_resources(pdev, &res, 1) ||
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index feaf09cc8632..1f870340ebdd 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -44,9 +44,6 @@ config GENERIC_CALIBRATE_DELAY
 config GENERIC_CMOS_UPDATE
         def_bool n
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
diff --git a/arch/mn10300/configs/asb2364_defconfig b/arch/mn10300/configs/asb2364_defconfig
index 31d76261a3d5..fbb96ae3122a 100644
--- a/arch/mn10300/configs/asb2364_defconfig
+++ b/arch/mn10300/configs/asb2364_defconfig
@@ -8,7 +8,6 @@ CONFIG_TASK_XACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
diff --git a/arch/mn10300/include/asm/unistd.h b/arch/mn10300/include/asm/unistd.h
index 9d056f515929..9051f921cbc7 100644
--- a/arch/mn10300/include/asm/unistd.h
+++ b/arch/mn10300/include/asm/unistd.h
@@ -349,10 +349,11 @@
 #define __NR_rt_tgsigqueueinfo  336
 #define __NR_perf_event_open    337
 #define __NR_recvmmsg           338
+#define __NR_setns              339
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 339
+#define NR_syscalls 340
 
 /*
  * specify the deprecated syscalls we want to support on this arch
diff --git a/arch/mn10300/kernel/entry.S b/arch/mn10300/kernel/entry.S
index fb93ad720b82..ae435e1d5669 100644
--- a/arch/mn10300/kernel/entry.S
+++ b/arch/mn10300/kernel/entry.S
@@ -759,6 +759,7 @@ ENTRY(sys_call_table)
         .long sys_rt_tgsigqueueinfo
         .long sys_perf_event_open
         .long sys_recvmmsg
+        .long sys_setns
 
 
 nr_syscalls=(.-sys_call_table)/4
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
index 86af0d7d0771..2623d19f4f4c 100644
--- a/arch/mn10300/kernel/irq.c
+++ b/arch/mn10300/kernel/irq.c
@@ -87,7 +87,7 @@ static void mn10300_cpupic_mask_ack(struct irq_data *d)
                 tmp2 = GxICR(irq);
 
                 irq_affinity_online[irq] =
-                        any_online_cpu(*d->affinity);
+                        cpumask_any_and(d->affinity, cpu_online_mask);
                 CROSS_GxICR(irq, irq_affinity_online[irq]) =
                         (tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
                 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
@@ -124,7 +124,8 @@ static void mn10300_cpupic_unmask_clear(struct irq_data *d)
         } else {
                 tmp = GxICR(irq);
 
-                irq_affinity_online[irq] = any_online_cpu(*d->affinity);
+                irq_affinity_online[irq] = cpumask_any_and(d->affinity,
+                                                           cpu_online_mask);
                 CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
                 tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
         }
@@ -366,11 +367,11 @@ void migrate_irqs(void)
                 if (irqd_is_per_cpu(data))
                         continue;
 
-                if (cpu_isset(self, data->affinity) &&
-                    !cpus_intersects(irq_affinity[irq], cpu_online_map)) {
+                if (cpumask_test_cpu(self, &data->affinity) &&
+                    !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) {
                         int cpu_id;
-                        cpu_id = first_cpu(cpu_online_map);
-                        cpu_set(cpu_id, data->affinity);
+                        cpu_id = cpumask_first(cpu_online_mask);
+                        cpumask_set_cpu(cpu_id, &data->affinity);
                 }
                 /* We need to operate irq_affinity_online atomically. */
                 arch_local_cli_save(flags);
@@ -381,7 +382,8 @@ void migrate_irqs(void)
                         GxICR(irq) = x & GxICR_LEVEL;
                         tmp = GxICR(irq);
 
-                        new = any_online_cpu(data->affinity);
+                        new = cpumask_any_and(&data->affinity,
+                                              cpu_online_mask);
                         irq_affinity_online[irq] = new;
 
                         CROSS_GxICR(irq, new) =
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
index 83fb27912231..9242e9fcc564 100644
--- a/arch/mn10300/kernel/smp.c
+++ b/arch/mn10300/kernel/smp.c
@@ -309,7 +309,7 @@ static void send_IPI_mask(const cpumask_t *cpumask, int irq)
         u16 tmp;
 
         for (i = 0; i < NR_CPUS; i++) {
-                if (cpu_isset(i, *cpumask)) {
+                if (cpumask_test_cpu(i, cpumask)) {
                         /* send IPI */
                         tmp = CROSS_GxICR(irq, i);
                         CROSS_GxICR(irq, i) =
@@ -342,8 +342,8 @@ void send_IPI_allbutself(int irq)
 {
         cpumask_t cpumask;
 
-        cpumask = cpu_online_map;
-        cpu_clear(smp_processor_id(), cpumask);
+        cpumask_copy(&cpumask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &cpumask);
         send_IPI_mask(&cpumask, irq);
 }
 
@@ -393,8 +393,8 @@ int smp_nmi_call_function(smp_call_func_t func, void *info, int wait)
 
         data.func = func;
         data.info = info;
-        data.started = cpu_online_map;
-        cpu_clear(smp_processor_id(), data.started);
+        cpumask_copy(&data.started, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &data.started);
         data.wait = wait;
         if (wait)
                 data.finished = data.started;
@@ -410,14 +410,14 @@ int smp_nmi_call_function(smp_call_func_t func, void *info, int wait)
         if (CALL_FUNCTION_NMI_IPI_TIMEOUT > 0) {
                 for (cnt = 0;
                      cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
-                             !cpus_empty(data.started);
+                             !cpumask_empty(&data.started);
                      cnt++)
                         mdelay(1);
 
                 if (wait && cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT) {
                         for (cnt = 0;
                              cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
-                                     !cpus_empty(data.finished);
+                                     !cpumask_empty(&data.finished);
                              cnt++)
                                 mdelay(1);
                 }
@@ -428,10 +428,10 @@ int smp_nmi_call_function(smp_call_func_t func, void *info, int wait)
         } else {
                 /* If timeout value is zero, wait until cpumask has been
                  * cleared */
-                while (!cpus_empty(data.started))
+                while (!cpumask_empty(&data.started))
                         barrier();
                 if (wait)
-                        while (!cpus_empty(data.finished))
+                        while (!cpumask_empty(&data.finished))
                                 barrier();
         }
 
@@ -472,12 +472,12 @@ void stop_this_cpu(void *unused)
 #endif  /* CONFIG_GDBSTUB */
 
         flags = arch_local_cli_save();
-        cpu_clear(smp_processor_id(), cpu_online_map);
+        set_cpu_online(smp_processor_id(), false);
 
         while (!stopflag)
                 cpu_relax();
 
-        cpu_set(smp_processor_id(), cpu_online_map);
+        set_cpu_online(smp_processor_id(), true);
         arch_local_irq_restore(flags);
 }
 
@@ -529,12 +529,13 @@ void smp_nmi_call_function_interrupt(void)
          * execute the function
          */
         smp_mb();
-        cpu_clear(smp_processor_id(), nmi_call_data->started);
+        cpumask_clear_cpu(smp_processor_id(), &nmi_call_data->started);
         (*func)(info);
 
         if (wait) {
                 smp_mb();
-                cpu_clear(smp_processor_id(), nmi_call_data->finished);
+                cpumask_clear_cpu(smp_processor_id(),
+                                  &nmi_call_data->finished);
         }
 }
 
@@ -657,7 +658,7 @@ int __init start_secondary(void *unused)
 {
         smp_cpu_init();
         smp_callin();
-        while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
+        while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask))
                 cpu_relax();
 
         local_flush_tlb();
@@ -780,13 +781,14 @@ static int __init do_boot_cpu(int phy_id)
 
         if (send_status == 0) {
                 /* Allow AP to start initializing */
-                cpu_set(cpu_id, cpu_callout_map);
+                cpumask_set_cpu(cpu_id, &cpu_callout_map);
 
                 /* Wait for setting cpu_callin_map */
                 timeout = 0;
                 do {
                         udelay(1000);
-                        callin_status = cpu_isset(cpu_id, cpu_callin_map);
+                        callin_status = cpumask_test_cpu(cpu_id,
+                                                         &cpu_callin_map);
                 } while (callin_status == 0 && timeout++ < 5000);
 
                 if (callin_status == 0)
@@ -796,9 +798,9 @@ static int __init do_boot_cpu(int phy_id)
         }
 
         if (send_status == GxICR_REQUEST || callin_status == 0) {
-                cpu_clear(cpu_id, cpu_callout_map);
-                cpu_clear(cpu_id, cpu_callin_map);
-                cpu_clear(cpu_id, cpu_initialized);
+                cpumask_clear_cpu(cpu_id, &cpu_callout_map);
+                cpumask_clear_cpu(cpu_id, &cpu_callin_map);
+                cpumask_clear_cpu(cpu_id, &cpu_initialized);
                 cpucount--;
                 return 1;
         }
@@ -833,7 +835,7 @@ static void __init smp_callin(void)
         cpu = smp_processor_id();
         timeout = jiffies + (2 * HZ);
 
-        if (cpu_isset(cpu, cpu_callin_map)) {
+        if (cpumask_test_cpu(cpu, &cpu_callin_map)) {
                 printk(KERN_ERR "CPU#%d already present.\n", cpu);
                 BUG();
         }
@@ -841,7 +843,7 @@ static void __init smp_callin(void)
 
         /* Wait for AP startup 2s total */
         while (time_before(jiffies, timeout)) {
-                if (cpu_isset(cpu, cpu_callout_map))
+                if (cpumask_test_cpu(cpu, &cpu_callout_map))
                         break;
                 cpu_relax();
         }
@@ -861,11 +863,11 @@ static void __init smp_callin(void)
         smp_store_cpu_info(cpu);
 
         /* Allow the boot processor to continue */
-        cpu_set(cpu, cpu_callin_map);
+        cpumask_set_cpu(cpu, &cpu_callin_map);
 }
 
 /**
- * smp_online - Set cpu_online_map
+ * smp_online - Set cpu_online_mask
  */
 static void __init smp_online(void)
 {
@@ -875,7 +877,7 @@ static void __init smp_online(void)
 
         local_irq_enable();
 
-        cpu_set(cpu, cpu_online_map);
+        set_cpu_online(cpu, true);
         smp_wmb();
 }
 
@@ -892,13 +894,13 @@ void __init smp_cpus_done(unsigned int max_cpus)
 /*
  * smp_prepare_boot_cpu - Set up stuff for the boot processor.
  *
- * Set up the cpu_online_map, cpu_callout_map and cpu_callin_map of the boot
+ * Set up the cpu_online_mask, cpu_callout_map and cpu_callin_map of the boot
  * processor (CPU 0).
  */
 void __devinit smp_prepare_boot_cpu(void)
 {
-        cpu_set(0, cpu_callout_map);
-        cpu_set(0, cpu_callin_map);
+        cpumask_set_cpu(0, &cpu_callout_map);
+        cpumask_set_cpu(0, &cpu_callin_map);
         current_thread_info()->cpu = 0;
 }
 
@@ -931,16 +933,16 @@ int __devinit __cpu_up(unsigned int cpu)
                 run_wakeup_cpu(cpu);
 #endif /* CONFIG_HOTPLUG_CPU */
 
-        cpu_set(cpu, smp_commenced_mask);
+        cpumask_set_cpu(cpu, &smp_commenced_mask);
 
         /* Wait 5s total for a response */
         for (timeout = 0 ; timeout < 5000 ; timeout++) {
-                if (cpu_isset(cpu, cpu_online_map))
+                if (cpu_online(cpu))
                         break;
                 udelay(1000);
         }
 
-        BUG_ON(!cpu_isset(cpu, cpu_online_map));
+        BUG_ON(!cpu_online(cpu));
         return 0;
 }
 
@@ -986,7 +988,7 @@ int __cpu_disable(void)
                 return -EBUSY;
 
         migrate_irqs();
-        cpu_clear(cpu, current->active_mm->cpu_vm_mask);
+        cpumask_clear_cpu(cpu, &mm_cpumask(current->active_mm));
         return 0;
 }
 
@@ -1091,13 +1093,13 @@ static int hotplug_cpu_nmi_call_function(cpumask_t cpumask,
         do {
                 mn10300_local_dcache_inv_range(start, end);
                 barrier();
-        } while (!cpus_empty(nmi_call_func_mask_data.started));
+        } while (!cpumask_empty(&nmi_call_func_mask_data.started));
 
         if (wait) {
                 do {
                         mn10300_local_dcache_inv_range(start, end);
                         barrier();
-                } while (!cpus_empty(nmi_call_func_mask_data.finished));
+                } while (!cpumask_empty(&nmi_call_func_mask_data.finished));
         }
 
         spin_unlock(&smp_nmi_call_lock);
@@ -1108,9 +1110,9 @@ static void restart_wakeup_cpu(void)
 {
         unsigned int cpu = smp_processor_id();
 
-        cpu_set(cpu, cpu_callin_map);
+        cpumask_set_cpu(cpu, &cpu_callin_map);
         local_flush_tlb();
-        cpu_set(cpu, cpu_online_map);
+        set_cpu_online(cpu, true);
         smp_wmb();
 }
 
@@ -1141,8 +1143,9 @@ static void sleep_cpu(void *unused)
 static void run_sleep_cpu(unsigned int cpu)
 {
         unsigned long flags;
-        cpumask_t cpumask = cpumask_of(cpu);
+        cpumask_t cpumask;
 
+        cpumask_copy(&cpumask, &cpumask_of(cpu));
         flags = arch_local_cli_save();
         hotplug_cpu_nmi_call_function(cpumask, prepare_sleep_cpu, NULL, 1);
         hotplug_cpu_nmi_call_function(cpumask, sleep_cpu, NULL, 0);
diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S
index 968bcd2cb022..6f702a6ab395 100644
--- a/arch/mn10300/kernel/vmlinux.lds.S
+++ b/arch/mn10300/kernel/vmlinux.lds.S
@@ -70,7 +70,7 @@ SECTIONS
         .exit.text : { EXIT_TEXT; }
         .exit.data : { EXIT_DATA; }
 
-  PERCPU(32, PAGE_SIZE)
+  PERCPU_SECTION(32)
   . = ALIGN(PAGE_SIZE);
   __init_end = .;
   /* freed after init ends here */
diff --git a/arch/mn10300/mm/cache-smp.c b/arch/mn10300/mm/cache-smp.c
index 4a6e9a4b5b27..2d23b9eeee62 100644
--- a/arch/mn10300/mm/cache-smp.c
+++ b/arch/mn10300/mm/cache-smp.c
@@ -74,7 +74,7 @@ void smp_cache_interrupt(void)
                 break;
         }
 
-        cpu_clear(smp_processor_id(), smp_cache_ipi_map);
+        cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
 }
 
 /**
@@ -94,12 +94,12 @@ void smp_cache_call(unsigned long opr_mask,
         smp_cache_mask = opr_mask;
         smp_cache_start = start;
         smp_cache_end = end;
-        smp_cache_ipi_map = cpu_online_map;
-        cpu_clear(smp_processor_id(), smp_cache_ipi_map);
+        cpumask_copy(&smp_cache_ipi_map, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
 
         send_IPI_allbutself(FLUSH_CACHE_IPI);
 
-        while (!cpus_empty(smp_cache_ipi_map))
+        while (!cpumask_empty(&smp_cache_ipi_map))
                 /* nothing. lockup detection does not belong here */
                 mb();
 }
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 48907cc3bdb7..13801824e3ee 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -37,8 +37,6 @@
 #include <asm/tlb.h>
 #include <asm/sections.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 unsigned long highstart_pfn, highend_pfn;
 
 #ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
diff --git a/arch/mn10300/mm/tlb-smp.c b/arch/mn10300/mm/tlb-smp.c
index 0b6a5ad1960e..9a777498a916 100644
--- a/arch/mn10300/mm/tlb-smp.c
+++ b/arch/mn10300/mm/tlb-smp.c
@@ -64,7 +64,7 @@ void smp_flush_tlb(void *unused)
 
         cpu_id = get_cpu();
 
-        if (!cpu_isset(cpu_id, flush_cpumask))
+        if (!cpumask_test_cpu(cpu_id, &flush_cpumask))
                 /* This was a BUG() but until someone can quote me the line
                  * from the intel manual that guarantees an IPI to multiple
                  * CPUs is retried _only_ on the erroring CPUs its staying as a
@@ -80,7 +80,7 @@ void smp_flush_tlb(void *unused)
                 local_flush_tlb_page(flush_mm, flush_va);
 
         smp_mb__before_clear_bit();
-        cpu_clear(cpu_id, flush_cpumask);
+        cpumask_clear_cpu(cpu_id, &flush_cpumask);
         smp_mb__after_clear_bit();
 out:
         put_cpu();
@@ -103,11 +103,11 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
          * - we do not send IPIs to as-yet unbooted CPUs.
          */
         BUG_ON(!mm);
-        BUG_ON(cpus_empty(cpumask));
-        BUG_ON(cpu_isset(smp_processor_id(), cpumask));
+        BUG_ON(cpumask_empty(&cpumask));
+        BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask));
 
-        cpus_and(tmp, cpumask, cpu_online_map);
-        BUG_ON(!cpus_equal(cpumask, tmp));
+        cpumask_and(&tmp, &cpumask, cpu_online_mask);
+        BUG_ON(!cpumask_equal(&cpumask, &tmp));
 
         /* I'm not happy about this global shared spinlock in the MM hot path,
          * but we'll see how contended it is.
@@ -128,7 +128,7 @@ static void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
         /* FIXME: if NR_CPUS>=3, change send_IPI_mask */
         smp_call_function(smp_flush_tlb, NULL, 1);
 
-        while (!cpus_empty(flush_cpumask))
+        while (!cpumask_empty(&flush_cpumask))
                 /* Lockup detection does not belong here */
                 smp_mb();
 
@@ -146,11 +146,11 @@ void flush_tlb_mm(struct mm_struct *mm)
         cpumask_t cpu_mask;
 
         preempt_disable();
-        cpu_mask = mm->cpu_vm_mask;
-        cpu_clear(smp_processor_id(), cpu_mask);
+        cpumask_copy(&cpu_mask, mm_cpumask(mm));
+        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
 
         local_flush_tlb();
-        if (!cpus_empty(cpu_mask))
+        if (!cpumask_empty(&cpu_mask))
                 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
 
         preempt_enable();
@@ -165,11 +165,11 @@ void flush_tlb_current_task(void)
         cpumask_t cpu_mask;
 
         preempt_disable();
-        cpu_mask = mm->cpu_vm_mask;
-        cpu_clear(smp_processor_id(), cpu_mask);
+        cpumask_copy(&cpu_mask, mm_cpumask(mm));
+        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
 
         local_flush_tlb();
-        if (!cpus_empty(cpu_mask))
+        if (!cpumask_empty(&cpu_mask))
                 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
 
         preempt_enable();
@@ -186,11 +186,11 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long va)
         cpumask_t cpu_mask;
 
         preempt_disable();
-        cpu_mask = mm->cpu_vm_mask;
-        cpu_clear(smp_processor_id(), cpu_mask);
+        cpumask_copy(&cpu_mask, mm_cpumask(mm));
+        cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
 
         local_flush_tlb_page(mm, va);
-        if (!cpus_empty(cpu_mask))
+        if (!cpumask_empty(&cpu_mask))
                 flush_tlb_others(cpu_mask, mm, va);
 
         preempt_enable();
diff --git a/arch/parisc/Kconfig b/arch/parisc/Kconfig
index 69ff049c8571..65adc86a230e 100644
--- a/arch/parisc/Kconfig
+++ b/arch/parisc/Kconfig
@@ -47,14 +47,6 @@ config ARCH_HAS_ILOG2_U64
         bool
         default n
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_BUG
         bool
         default y
diff --git a/arch/parisc/include/asm/smp.h b/arch/parisc/include/asm/smp.h
index 2e73623feb6b..e8f8037d872b 100644
--- a/arch/parisc/include/asm/smp.h
+++ b/arch/parisc/include/asm/smp.h
@@ -33,15 +33,6 @@ extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
 #endif /* !ASSEMBLY */
 
-/*
- *      This magic constant controls our willingness to transfer
- *      a process across CPUs. Such a transfer incurs cache and tlb
- *      misses. The current value is inherited from i386. Still needs
- *      to be tuned for parisc.
- */
- 
-#define PROC_CHANGE_PENALTY     15              /* Schedule penalty */
-
 #define raw_smp_processor_id()  (current_thread_info()->cpu)
 
 #else /* CONFIG_SMP */
diff --git a/arch/parisc/include/asm/unistd.h b/arch/parisc/include/asm/unistd.h
index 9cbc2c3bf630..3392de3e7be0 100644
--- a/arch/parisc/include/asm/unistd.h
+++ b/arch/parisc/include/asm/unistd.h
@@ -820,8 +820,9 @@
 #define __NR_name_to_handle_at  (__NR_Linux + 325)
 #define __NR_open_by_handle_at  (__NR_Linux + 326)
 #define __NR_syncfs             (__NR_Linux + 327)
+#define __NR_setns              (__NR_Linux + 328)
 
-#define __NR_Linux_syscalls     (__NR_syncfs + 1)
+#define __NR_Linux_syscalls     (__NR_setns + 1)
 
 
 #define __IGNORE_select         /* newselect */
diff --git a/arch/parisc/kernel/syscall_table.S b/arch/parisc/kernel/syscall_table.S
index a5b02ce4d41e..34a4f5a2fffb 100644
--- a/arch/parisc/kernel/syscall_table.S
+++ b/arch/parisc/kernel/syscall_table.S
@@ -426,6 +426,7 @@
         ENTRY_SAME(name_to_handle_at)   /* 325 */
         ENTRY_COMP(open_by_handle_at)
         ENTRY_SAME(syncfs)
+        ENTRY_SAME(setns)
 
         /* Nothing yet */
 
diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S
index e1a55849bfa7..fa6f2b8163e0 100644
--- a/arch/parisc/kernel/vmlinux.lds.S
+++ b/arch/parisc/kernel/vmlinux.lds.S
@@ -149,7 +149,7 @@ SECTIONS
                 EXIT_DATA
         }
 
-        PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+        PERCPU_SECTION(L1_CACHE_BYTES)
         . = ALIGN(PAGE_SIZE);
         __init_end = .;
         /* freed after init ends here */
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 5fa1e273006e..82f364e209fc 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -31,8 +31,6 @@
 #include <asm/mmzone.h>
 #include <asm/sections.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 extern int  data_start;
 
 #ifdef CONFIG_DISCONTIGMEM
@@ -686,7 +684,7 @@ void show_mem(unsigned int filter)
         int shared = 0, cached = 0;
 
         printk(KERN_INFO "Mem-info:\n");
-        show_free_areas();
+        show_free_areas(filter);
 #ifndef CONFIG_DISCONTIGMEM
         i = max_mapnr;
         while (i-- > 0) {
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a3128ca0fe11..2729c6663d8a 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -91,14 +91,6 @@ config GENERIC_HWEIGHT
         bool
         default y
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_GPIO
         bool
         help
@@ -140,6 +132,8 @@ config PPC
         select IRQ_PER_CPU
         select GENERIC_IRQ_SHOW
         select GENERIC_IRQ_SHOW_LEVEL
+        select HAVE_RCU_TABLE_FREE if SMP
+        select HAVE_SYSCALL_TRACEPOINTS
 
 config EARLY_PRINTK
         bool
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index a597dd77b903..e72dcf6a421d 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -35,27 +35,6 @@ config DEBUG_STACKOVERFLOW
           This option will cause messages to be printed if free stack space
           drops below a certain limit.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
-config DEBUG_PER_CPU_MAPS
-        bool "Debug access to per_cpu maps"
-        depends on DEBUG_KERNEL
-        depends on SMP
-        default n
-        ---help---
-          Say Y to verify that the per_cpu map being accessed has
-          been setup.  Adds a fair amount of code to kernel memory
-          and decreases performance.
-
-          Say N if unsure.
-
 config HCALL_STATS
         bool "Hypervisor call instrumentation"
         depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS
diff --git a/arch/powerpc/boot/dts/canyonlands.dts b/arch/powerpc/boot/dts/canyonlands.dts
index 2779f08313a5..22dd6ae84da0 100644
--- a/arch/powerpc/boot/dts/canyonlands.dts
+++ b/arch/powerpc/boot/dts/canyonlands.dts
@@ -530,5 +530,23 @@
                                 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
                                 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
                 };
+
+                MSI: ppc4xx-msi@C10000000 {
+                        compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+                        reg = < 0xC 0x10000000 0x100>;
+                        sdr-base = <0x36C>;
+                        msi-data = <0x00000000>;
+                        msi-mask = <0x44440000>;
+                        interrupt-count = <3>;
+                        interrupts = <0 1 2 3>;
+                        interrupt-parent = <&UIC3>;
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0 &UIC3 0x18 1
+                                        1 &UIC3 0x19 1
+                                        2 &UIC3 0x1A 1
+                                        3 &UIC3 0x1B 1>;
+                };
         };
 };
diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts
index 7c3be5e45748..f913dbe25d35 100644
--- a/arch/powerpc/boot/dts/katmai.dts
+++ b/arch/powerpc/boot/dts/katmai.dts
@@ -442,6 +442,24 @@
                                 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
                 };
 
+                MSI: ppc4xx-msi@400300000 {
+                                compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+                                reg = < 0x4 0x00300000 0x100>;
+                                sdr-base = <0x3B0>;
+                                msi-data = <0x00000000>;
+                                msi-mask = <0x44440000>;
+                                interrupt-count = <3>;
+                                interrupts =<0 1 2 3>;
+                                interrupt-parent = <&UIC0>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = <0 &UIC0 0xC 1
+                                        1 &UIC0 0x0D 1
+                                        2 &UIC0 0x0E 1
+                                        3 &UIC0 0x0F 1>;
+                };
+
                 I2O: i2o@400100000 {
                         compatible = "ibm,i2o-440spe";
                         reg = <0x00000004 0x00100000 0x100>;
diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts
index 89edb16649c3..1613d6e4049e 100644
--- a/arch/powerpc/boot/dts/kilauea.dts
+++ b/arch/powerpc/boot/dts/kilauea.dts
@@ -403,5 +403,33 @@
                                 0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
                                 0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
                 };
+
+                MSI: ppc4xx-msi@C10000000 {
+                        compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+                        reg = < 0x0 0xEF620000 0x100>;
+                        sdr-base = <0x4B0>;
+                        msi-data = <0x00000000>;
+                        msi-mask = <0x44440000>;
+                        interrupt-count = <12>;
+                        interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>;
+                        interrupt-parent = <&UIC2>;
+                        #interrupt-cells = <1>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-map = <0 &UIC2 0x10 1
+                                        1 &UIC2 0x11 1
+                                        2 &UIC2 0x12 1
+                                        2 &UIC2 0x13 1
+                                        2 &UIC2 0x14 1
+                                        2 &UIC2 0x15 1
+                                        2 &UIC2 0x16 1
+                                        2 &UIC2 0x17 1
+                                        2 &UIC2 0x18 1
+                                        2 &UIC2 0x19 1
+                                        2 &UIC2 0x1A 1
+                                        2 &UIC2 0x1B 1
+                                        2 &UIC2 0x1C 1
+                                        3 &UIC2 0x1D 1>;
+                };
         };
 };
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 761faa7b6964..ac1eb320c7b4 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -176,6 +176,19 @@
                         sleep = <&pmc 0x00300000>;
                 };
 
+                ptp_clock@24E00 {
+                        compatible = "fsl,etsec-ptp";
+                        reg = <0x24E00 0xB0>;
+                        interrupts = <12 0x8 13 0x8>;
+                        interrupt-parent = < &ipic >;
+                        fsl,tclk-period = <10>;
+                        fsl,tmr-prsc    = <100>;
+                        fsl,tmr-add     = <0x999999A4>;
+                        fsl,tmr-fiper1  = <0x3B9AC9F6>;
+                        fsl,tmr-fiper2  = <0x00018696>;
+                        fsl,max-adj     = <659999998>;
+                };
+
                 enet0: ethernet@24000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc1285c140..f6c04d25e916 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
                         };
                 };
 
+                ptp_clock@24E00 {
+                        compatible = "fsl,etsec-ptp";
+                        reg = <0x24E00 0xB0>;
+                        interrupts = <68 2 69 2 70 2 71 2>;
+                        interrupt-parent = < &mpic >;
+                        fsl,tclk-period = <5>;
+                        fsl,tmr-prsc = <200>;
+                        fsl,tmr-add = <0xAAAAAAAB>;
+                        fsl,tmr-fiper1 = <0x3B9AC9FB>;
+                        fsl,tmr-fiper2 = <0x3B9AC9FB>;
+                        fsl,max-adj = <499999999>;
+                };
+
                 enet0: ethernet@24000 {
                         #address-cells = <1>;
                         #size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 2bcf3683d223..dae403100f2f 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -178,6 +178,19 @@
 
                 };
 
+                ptp_clock@24E00 {
+                        compatible = "fsl,etsec-ptp";
+                        reg = <0x24E00 0xB0>;
+                        interrupts = <68 2 69 2 70 2>;
+                        interrupt-parent = < &mpic >;
+                        fsl,tclk-period = <5>;
+                        fsl,tmr-prsc = <200>;
+                        fsl,tmr-add = <0xCCCCCCCD>;
+                        fsl,tmr-fiper1 = <0x3B9AC9FB>;
+                        fsl,tmr-fiper2 = <0x0001869B>;
+                        fsl,max-adj = <249999999>;
+                };
+
                 enet0: ethernet@24000 {
                         tbi-handle = <&tbi0>;
                         phy-handle = <&phy0>;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 3782a58f13be..1d7a05f3021e 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -224,6 +224,19 @@
                         status = "disabled";
                 };
 
+                ptp_clock@24E00 {
+                        compatible = "fsl,etsec-ptp";
+                        reg = <0x24E00 0xB0>;
+                        interrupts = <68 2 69 2 70 2>;
+                        interrupt-parent = < &mpic >;
+                        fsl,tclk-period = <5>;
+                        fsl,tmr-prsc = <200>;
+                        fsl,tmr-add = <0xCCCCCCCD>;
+                        fsl,tmr-fiper1 = <0x3B9AC9FB>;
+                        fsl,tmr-fiper2 = <0x0001869B>;
+                        fsl,max-adj = <249999999>;
+                };
+
                 enet0: ethernet@24000 {
                         fixed-link = <1 1 1000 0 0>;
                         phy-connection-type = "rgmii-id";
diff --git a/arch/powerpc/boot/dts/redwood.dts b/arch/powerpc/boot/dts/redwood.dts
index 81636c01d906..d86a3a498118 100644
--- a/arch/powerpc/boot/dts/redwood.dts
+++ b/arch/powerpc/boot/dts/redwood.dts
@@ -358,8 +358,28 @@
                                 0x0 0x0 0x0 0x4 &UIC3 0xb 0x4 /* swizzled int D */>;
                 };
 
+                MSI: ppc4xx-msi@400300000 {
+                                compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
+                                reg = < 0x4 0x00300000 0x100
+                                        0x4 0x00300000 0x100>;
+                                sdr-base = <0x3B0>;
+                                msi-data = <0x00000000>;
+                                msi-mask = <0x44440000>;
+                                interrupt-count = <3>;
+                                interrupts =<0 1 2 3>;
+                                interrupt-parent = <&UIC0>;
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = <0 &UIC0 0xC 1
+                                        1 &UIC0 0x0D 1
+                                        2 &UIC0 0x0E 1
+                                        3 &UIC0 0x0F 1>;
+                };
+
         };
 
+
         chosen {
                 linux,stdout-path = "/plb/opb/serial@ef600200";
         };
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index 214208924a9c..04360f9b0109 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -10,7 +10,6 @@ CONFIG_TASK_XACCT=y
 CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig
index 7de13865508c..c9f212b5f3de 100644
--- a/arch/powerpc/configs/pseries_defconfig
+++ b/arch/powerpc/configs/pseries_defconfig
@@ -15,7 +15,6 @@ CONFIG_AUDITSYSCALL=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h
index 5c1bf3466749..8a0b5ece8f76 100644
--- a/arch/powerpc/include/asm/fsl_lbc.h
+++ b/arch/powerpc/include/asm/fsl_lbc.h
@@ -157,6 +157,8 @@ struct fsl_lbc_regs {
 #define LBCR_EPAR_SHIFT    16
 #define LBCR_BMT   0x0000FF00
 #define LBCR_BMT_SHIFT      8
+#define LBCR_BMTPS 0x0000000F
+#define LBCR_BMTPS_SHIFT    0
 #define LBCR_INIT  0x00040000
         __be32 lcrr;            /**< Clock Ratio Register */
 #define LCRR_DBYP    0x80000000
diff --git a/arch/powerpc/include/asm/ftrace.h b/arch/powerpc/include/asm/ftrace.h
index dde1296b8b41..169d039ed402 100644
--- a/arch/powerpc/include/asm/ftrace.h
+++ b/arch/powerpc/include/asm/ftrace.h
@@ -60,4 +60,18 @@ struct dyn_arch_ftrace {
 
 #endif
 
+#if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64) && !defined(__ASSEMBLY__)
+#define ARCH_HAS_SYSCALL_MATCH_SYM_NAME
+static inline bool arch_syscall_match_sym_name(const char *sym, const char *name)
+{
+        /*
+         * Compare the symbol name with the system call name. Skip the .sys or .SyS
+         * prefix from the symbol name and the sys prefix from the system call name and
+         * just match the rest. This is only needed on ppc64 since symbol names on
+         * 32bit do not start with a period so the generic function will work.
+         */
+        return !strcmp(sym + 4, name + 3);
+}
+#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 && !__ASSEMBLY__ */
+
 #endif /* _ASM_POWERPC_FTRACE */
diff --git a/arch/powerpc/include/asm/hvcall.h b/arch/powerpc/include/asm/hvcall.h
index 852b8c1c09db..fd8201dddd4b 100644
--- a/arch/powerpc/include/asm/hvcall.h
+++ b/arch/powerpc/include/asm/hvcall.h
@@ -236,7 +236,7 @@
 #define H_HOME_NODE_ASSOCIATIVITY 0x2EC
 #define H_BEST_ENERGY           0x2F4
 #define H_GET_MPP_X             0x314
-#define MAX_HCALL_OPCODE        H_BEST_ENERGY
+#define MAX_HCALL_OPCODE        H_GET_MPP_X
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index abe8532bd14e..bf301ac62f35 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -31,14 +31,29 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
 #endif
 
 #ifdef CONFIG_SMP
-extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift);
-extern void pte_free_finish(void);
+struct mmu_gather;
+extern void tlb_remove_table(struct mmu_gather *, void *);
+
+static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
+{
+        unsigned long pgf = (unsigned long)table;
+        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+        pgf |= shift;
+        tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+        void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+        unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+        pgtable_free(table, shift);
+}
 #else /* CONFIG_SMP */
 static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
 {
         pgtable_free(table, shift);
 }
-static inline void pte_free_finish(void) { }
 #endif /* !CONFIG_SMP */
 
 static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
diff --git a/arch/powerpc/include/asm/rio.h b/arch/powerpc/include/asm/rio.h
index 0018bf80cb25..d902abd33995 100644
--- a/arch/powerpc/include/asm/rio.h
+++ b/arch/powerpc/include/asm/rio.h
@@ -14,5 +14,10 @@
 #define ASM_PPC_RIO_H
 
 extern void platform_rio_init(void);
+#ifdef CONFIG_RAPIDIO
+extern int fsl_rio_mcheck_exception(struct pt_regs *);
+#else
+static inline int fsl_rio_mcheck_exception(struct pt_regs *regs) {return 0; }
+#endif
 
 #endif                          /* ASM_PPC_RIO_H */
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index 880b8c1e6e53..11eb404b5606 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -191,8 +191,6 @@ extern unsigned long __secondary_hold_spinloop;
 extern unsigned long __secondary_hold_acknowledge;
 extern char __secondary_hold;
 
-extern irqreturn_t debug_ipi_action(int irq, void *data);
-
 #endif /* __ASSEMBLY__ */
 
 #endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/suspend.h b/arch/powerpc/include/asm/suspend.h
deleted file mode 100644
index c6efc3466aa6..000000000000
--- a/arch/powerpc/include/asm/suspend.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_POWERPC_SUSPEND_H
-#define __ASM_POWERPC_SUSPEND_H
-
-static inline int arch_prepare_suspend(void) { return 0; }
-
-#endif /* __ASM_POWERPC_SUSPEND_H */
diff --git a/arch/powerpc/include/asm/syscall.h b/arch/powerpc/include/asm/syscall.h
index 23913e902fc3..b54b2add07be 100644
--- a/arch/powerpc/include/asm/syscall.h
+++ b/arch/powerpc/include/asm/syscall.h
@@ -15,6 +15,11 @@
 
 #include <linux/sched.h>
 
+/* ftrace syscalls requires exporting the sys_call_table */
+#ifdef CONFIG_FTRACE_SYSCALLS
+extern const unsigned long *sys_call_table;
+#endif /* CONFIG_FTRACE_SYSCALLS */
+
 static inline long syscall_get_nr(struct task_struct *task,
                                   struct pt_regs *regs)
 {
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 8489d372077f..f6736b7da463 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -353,3 +353,4 @@ COMPAT_SYS_SPU(open_by_handle_at)
 COMPAT_SYS_SPU(clock_adjtime)
 SYSCALL_SPU(syncfs)
 COMPAT_SYS_SPU(sendmmsg)
+SYSCALL_SPU(setns)
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index d8529ef13b23..836f231ec1f0 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -110,7 +110,8 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_NOERROR             12      /* Force successful syscall return */
 #define TIF_NOTIFY_RESUME       13      /* callback before returning to user */
 #define TIF_FREEZE              14      /* Freezing for suspend */
-#define TIF_RUNLATCH            15      /* Is the runlatch enabled? */
+#define TIF_SYSCALL_TRACEPOINT  15      /* syscall tracepoint instrumentation */
+#define TIF_RUNLATCH            16      /* Is the runlatch enabled? */
 
 /* as above, but as bit values */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -127,8 +128,10 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NOERROR            (1<<TIF_NOERROR)
 #define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
+#define _TIF_SYSCALL_TRACEPOINT (1<<TIF_SYSCALL_TRACEPOINT)
 #define _TIF_RUNLATCH           (1<<TIF_RUNLATCH)
-#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
+#define _TIF_SYSCALL_T_OR_A     (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
+                                 _TIF_SECCOMP | _TIF_SYSCALL_TRACEPOINT)
 
 #define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
                                  _TIF_NOTIFY_RESUME)
@@ -139,10 +142,12 @@ static inline struct thread_info *current_thread_info(void)
 #define TLF_NAPPING             0       /* idle thread enabled NAP mode */
 #define TLF_SLEEPING            1       /* suspend code enabled SLEEP mode */
 #define TLF_RESTORE_SIGMASK     2       /* Restore signal mask in do_signal */
+#define TLF_LAZY_MMU            3       /* tlb_batch is active */
 
 #define _TLF_NAPPING            (1 << TLF_NAPPING)
 #define _TLF_SLEEPING           (1 << TLF_SLEEPING)
 #define _TLF_RESTORE_SIGMASK    (1 << TLF_RESTORE_SIGMASK)
+#define _TLF_LAZY_MMU           (1 << TLF_LAZY_MMU)
 
 #ifndef __ASSEMBLY__
 #define HAVE_SET_RESTORE_SIGMASK        1
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 6d23c8193caa..b8b3f599362b 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -372,10 +372,11 @@
 #define __NR_clock_adjtime      347
 #define __NR_syncfs             348
 #define __NR_sendmmsg           349
+#define __NR_setns              350
 
 #ifdef __KERNEL__
 
-#define __NR_syscalls           350
+#define __NR_syscalls           351
 
 #define __NR__exit __NR_exit
 #define NR_syscalls     __NR_syscalls
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index 9aab36312572..e8b981897d44 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -109,6 +109,7 @@ obj-$(CONFIG_PPC_IO_WORKAROUNDS)	+= io-workarounds.o
 
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o
+obj-$(CONFIG_FTRACE_SYSCALLS)   += ftrace.o
 obj-$(CONFIG_PERF_EVENTS)       += perf_callchain.o
 
 obj-$(CONFIG_PPC_PERF_CTRS)     += perf_event.o
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index ce1f3e44c24f..bf99cfa6bbfe 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -22,6 +22,7 @@
 #include <asm/cacheflush.h>
 #include <asm/code-patching.h>
 #include <asm/ftrace.h>
+#include <asm/syscall.h>
 
 
 #ifdef CONFIG_DYNAMIC_FTRACE
@@ -600,3 +601,10 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
         }
 }
 #endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+
+#if defined(CONFIG_FTRACE_SYSCALLS) && defined(CONFIG_PPC64)
+unsigned long __init arch_syscall_addr(int nr)
+{
+        return sys_call_table[nr*2];
+}
+#endif /* CONFIG_FTRACE_SYSCALLS && CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index a24d37d4cf51..5b428e308666 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -295,17 +295,20 @@ static inline void handle_one_irq(unsigned int irq)
         unsigned long saved_sp_limit;
         struct irq_desc *desc;
 
+        desc = irq_to_desc(irq);
+        if (!desc)
+                return;
+
         /* Switch to the irq stack to handle this */
         curtp = current_thread_info();
         irqtp = hardirq_ctx[smp_processor_id()];
 
         if (curtp == irqtp) {
                 /* We're already on the irq stack, just handle it */
-                generic_handle_irq(irq);
+                desc->handle_irq(irq, desc);
                 return;
         }
 
-        desc = irq_to_desc(irq);
         saved_sp_limit = current->thread.ksp_limit;
 
         irqtp->task = curtp->task;
@@ -557,15 +560,8 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
         if (revmap_type == IRQ_HOST_MAP_LEGACY) {
                 if (irq_map[0].host != NULL) {
                         raw_spin_unlock_irqrestore(&irq_big_lock, flags);
-                        /* If we are early boot, we can't free the structure,
-                         * too bad...
-                         * this will be fixed once slab is made available early
-                         * instead of the current cruft
-                         */
-                        if (mem_init_done) {
-                                of_node_put(host->of_node);
-                                kfree(host);
-                        }
+                        of_node_put(host->of_node);
+                        kfree(host);
                         return NULL;
                 }
                 irq_map[0].host = host;
@@ -727,9 +723,7 @@ unsigned int irq_create_mapping(struct irq_host *host,
         }
         pr_debug("irq: -> using host @%p\n", host);
 
-        /* Check if mapping already exist, if it does, call
-         * host->ops->map() to update the flags
-         */
+        /* Check if mapping already exists */
         virq = irq_find_mapping(host, hwirq);
         if (virq != NO_IRQ) {
                 pr_debug("irq: -> existing mapping on virq %d\n", virq);
@@ -899,10 +893,13 @@ unsigned int irq_radix_revmap_lookup(struct irq_host *host,
                 return irq_find_mapping(host, hwirq);
 
         /*
-         * No rcu_read_lock(ing) needed, the ptr returned can't go under us
-         * as it's referencing an entry in the static irq_map table.
+         * The ptr returned references the static global irq_map.
+         * but freeing an irq can delete nodes along the path to
+         * do the lookup via call_rcu.
          */
+        rcu_read_lock();
         ptr = radix_tree_lookup(&host->revmap_data.tree, hwirq);
+        rcu_read_unlock();
 
         /*
          * If found in radix tree, then fine.
@@ -1010,14 +1007,23 @@ void irq_free_virt(unsigned int virq, unsigned int count)
         WARN_ON (virq < NUM_ISA_INTERRUPTS);
         WARN_ON (count == 0 || (virq + count) > irq_virq_count);
 
+        if (virq < NUM_ISA_INTERRUPTS) {
+                if (virq + count < NUM_ISA_INTERRUPTS)
+                        return;
+                count  =- NUM_ISA_INTERRUPTS - virq;
+                virq = NUM_ISA_INTERRUPTS;
+        }
+
+        if (count > irq_virq_count || virq > irq_virq_count - count) {
+                if (virq > irq_virq_count)
+                        return;
+                count = irq_virq_count - virq;
+        }
+
         raw_spin_lock_irqsave(&irq_big_lock, flags);
         for (i = virq; i < (virq + count); i++) {
                 struct irq_host *host;
 
-                if (i < NUM_ISA_INTERRUPTS ||
-                    (virq + count) > irq_virq_count)
-                        continue;
-
                 host = irq_map[i].host;
                 irq_map[i].hwirq = host->inval_irq;
                 smp_wmb();
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 095043d79946..91e52df3d81d 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -395,6 +395,9 @@ struct task_struct *__switch_to(struct task_struct *prev,
         struct thread_struct *new_thread, *old_thread;
         unsigned long flags;
         struct task_struct *last;
+#ifdef CONFIG_PPC_BOOK3S_64
+        struct ppc64_tlb_batch *batch;
+#endif
 
 #ifdef CONFIG_SMP
         /* avoid complexity of lazy save/restore of fpu
@@ -513,7 +516,17 @@ struct task_struct *__switch_to(struct task_struct *prev,
                 old_thread->accum_tb += (current_tb - start_tb);
                 new_thread->start_tb = current_tb;
         }
-#endif
+#endif /* CONFIG_PPC64 */
+
+#ifdef CONFIG_PPC_BOOK3S_64
+        batch = &__get_cpu_var(ppc64_tlb_batch);
+        if (batch->active) {
+                current_thread_info()->local_flags |= _TLF_LAZY_MMU;
+                if (batch->index)
+                        __flush_tlb_pending(batch);
+                batch->active = 0;
+        }
+#endif /* CONFIG_PPC_BOOK3S_64 */
 
         local_irq_save(flags);
 
@@ -528,6 +541,14 @@ struct task_struct *__switch_to(struct task_struct *prev,
         hard_irq_disable();
         last = _switch(old_thread, new_thread);
 
+#ifdef CONFIG_PPC_BOOK3S_64
+        if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
+                current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
+                batch = &__get_cpu_var(ppc64_tlb_batch);
+                batch->active = 1;
+        }
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
         local_irq_restore(flags);
 
         return last;
diff --git a/arch/powerpc/kernel/prom.c b/arch/powerpc/kernel/prom.c
index 48aeb55faae9..f2c906b1d8d3 100644
--- a/arch/powerpc/kernel/prom.c
+++ b/arch/powerpc/kernel/prom.c
@@ -694,7 +694,7 @@ void __init early_init_devtree(void *params)
          * device-tree, including the platform type, initrd location and
          * size, TCE reserve, and more ...
          */
-        of_scan_flat_dt(early_init_dt_scan_chosen_ppc, NULL);
+        of_scan_flat_dt(early_init_dt_scan_chosen_ppc, cmd_line);
 
         /* Scan memory nodes and rebuild MEMBLOCKs */
         memblock_init();
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index a6ae1cfad86c..cb22024f2b42 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -29,6 +29,7 @@
 #include <linux/signal.h>
 #include <linux/seccomp.h>
 #include <linux/audit.h>
+#include <trace/syscall.h>
 #ifdef CONFIG_PPC32
 #include <linux/module.h>
 #endif
@@ -40,6 +41,9 @@
 #include <asm/pgtable.h>
 #include <asm/system.h>
 
+#define CREATE_TRACE_POINTS
+#include <trace/events/syscalls.h>
+
 /*
  * The parameter save area on the stack is used to store arguments being passed
  * to callee function and is located at fixed offset from stack pointer.
@@ -1710,6 +1714,9 @@ long do_syscall_trace_enter(struct pt_regs *regs)
                  */
                 ret = -1L;
 
+        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
+                trace_sys_enter(regs, regs->gpr[0]);
+
         if (unlikely(current->audit_context)) {
 #ifdef CONFIG_PPC64
                 if (!is_32bit_task())
@@ -1738,6 +1745,9 @@ void do_syscall_trace_leave(struct pt_regs *regs)
                 audit_syscall_exit((regs->ccr&0x10000000)?AUDITSC_FAILURE:AUDITSC_SUCCESS,
                                    regs->result);
 
+        if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
+                trace_sys_exit(regs, regs->result);
+
         step = test_thread_flag(TIF_SINGLESTEP);
         if (step || test_thread_flag(TIF_SYSCALL_TRACE))
                 tracehook_report_syscall_exit(regs, step);
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 4a6f2ec7e761..8ebc6700b98d 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -129,7 +129,7 @@ static irqreturn_t call_function_single_action(int irq, void *data)
         return IRQ_HANDLED;
 }
 
-irqreturn_t debug_ipi_action(int irq, void *data)
+static irqreturn_t debug_ipi_action(int irq, void *data)
 {
         if (crash_ipi_function_ptr) {
                 crash_ipi_function_ptr(get_irq_regs());
diff --git a/arch/powerpc/kernel/swsusp.c b/arch/powerpc/kernel/swsusp.c
index 560c96119501..aa17b76dd427 100644
--- a/arch/powerpc/kernel/swsusp.c
+++ b/arch/powerpc/kernel/swsusp.c
@@ -10,7 +10,6 @@
  */
 
 #include <linux/sched.h>
-#include <asm/suspend.h>
 #include <asm/system.h>
 #include <asm/current.h>
 #include <asm/mmu_context.h>
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index b13306b0d925..0ff4ab98d50c 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -55,6 +55,7 @@
 #endif
 #include <asm/kexec.h>
 #include <asm/ppc-opcode.h>
+#include <asm/rio.h>
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 int (*__debugger)(struct pt_regs *regs) __read_mostly;
@@ -424,6 +425,12 @@ int machine_check_e500mc(struct pt_regs *regs)
         unsigned long reason = mcsr;
         int recoverable = 1;
 
+        if (reason & MCSR_BUS_RBERR) {
+                recoverable = fsl_rio_mcheck_exception(regs);
+                if (recoverable == 1)
+                        goto silent_out;
+        }
+
         printk("Machine check in kernel mode.\n");
         printk("Caused by (from MCSR=%lx): ", reason);
 
@@ -499,6 +506,7 @@ int machine_check_e500mc(struct pt_regs *regs)
                        reason & MCSR_MEA ? "Effective" : "Physical", addr);
         }
 
+silent_out:
         mtspr(SPRN_MCSR, mcsr);
         return mfspr(SPRN_MCSR) == 0 && recoverable;
 }
@@ -507,6 +515,11 @@ int machine_check_e500(struct pt_regs *regs)
 {
         unsigned long reason = get_mc_reason(regs);
 
+        if (reason & MCSR_BUS_RBERR) {
+                if (fsl_rio_mcheck_exception(regs))
+                        return 1;
+        }
+
         printk("Machine check in kernel mode.\n");
         printk("Caused by (from MCSR=%lx): ", reason);
 
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index b9150f07d266..920276c0f6a1 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -160,7 +160,7 @@ SECTIONS
                 INIT_RAM_FS
         }
 
-        PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+        PERCPU_SECTION(L1_CACHE_BYTES)
 
         . = ALIGN(8);
         .machine.desc : AT(ADDR(.machine.desc) - LOAD_OFFSET) {
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 6a3997f98dfb..af40c8768a78 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -33,110 +33,6 @@
 
 #include "mmu_decl.h"
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
-#ifdef CONFIG_SMP
-
-/*
- * Handle batching of page table freeing on SMP. Page tables are
- * queued up and send to be freed later by RCU in order to avoid
- * freeing a page table page that is being walked without locks
- */
-
-static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
-static unsigned long pte_freelist_forced_free;
-
-struct pte_freelist_batch
-{
-        struct rcu_head rcu;
-        unsigned int    index;
-        unsigned long   tables[0];
-};
-
-#define PTE_FREELIST_SIZE \
-        ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
-          / sizeof(unsigned long))
-
-static void pte_free_smp_sync(void *arg)
-{
-        /* Do nothing, just ensure we sync with all CPUs */
-}
-
-/* This is only called when we are critically out of memory
- * (and fail to get a page in pte_free_tlb).
- */
-static void pgtable_free_now(void *table, unsigned shift)
-{
-        pte_freelist_forced_free++;
-
-        smp_call_function(pte_free_smp_sync, NULL, 1);
-
-        pgtable_free(table, shift);
-}
-
-static void pte_free_rcu_callback(struct rcu_head *head)
-{
-        struct pte_freelist_batch *batch =
-                container_of(head, struct pte_freelist_batch, rcu);
-        unsigned int i;
-
-        for (i = 0; i < batch->index; i++) {
-                void *table = (void *)(batch->tables[i] & ~MAX_PGTABLE_INDEX_SIZE);
-                unsigned shift = batch->tables[i] & MAX_PGTABLE_INDEX_SIZE;
-
-                pgtable_free(table, shift);
-        }
-
-        free_page((unsigned long)batch);
-}
-
-static void pte_free_submit(struct pte_freelist_batch *batch)
-{
-        call_rcu_sched(&batch->rcu, pte_free_rcu_callback);
-}
-
-void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
-{
-        /* This is safe since tlb_gather_mmu has disabled preemption */
-        struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
-        unsigned long pgf;
-
-        if (atomic_read(&tlb->mm->mm_users) < 2 ||
-            cpumask_equal(mm_cpumask(tlb->mm), cpumask_of(smp_processor_id()))){
-                pgtable_free(table, shift);
-                return;
-        }
-
-        if (*batchp == NULL) {
-                *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
-                if (*batchp == NULL) {
-                        pgtable_free_now(table, shift);
-                        return;
-                }
-                (*batchp)->index = 0;
-        }
-        BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
-        pgf = (unsigned long)table | shift;
-        (*batchp)->tables[(*batchp)->index++] = pgf;
-        if ((*batchp)->index == PTE_FREELIST_SIZE) {
-                pte_free_submit(*batchp);
-                *batchp = NULL;
-        }
-}
-
-void pte_free_finish(void)
-{
-        /* This is safe since tlb_gather_mmu has disabled preemption */
-        struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
-
-        if (*batchp == NULL)
-                return;
-        pte_free_submit(*batchp);
-        *batchp = NULL;
-}
-
-#endif /* CONFIG_SMP */
-
 static inline int is_exec_fault(void)
 {
         return current->thread.regs && TRAP(current->thread.regs) == 0x400;
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 690566b66e8e..27b863c14941 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -71,9 +71,6 @@ void tlb_flush(struct mmu_gather *tlb)
                  */
                 _tlbia();
         }
-
-        /* Push out batch of freed page tables */
-        pte_free_finish();
 }
 
 /*
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index c14d09f614f3..31f18207970b 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -155,7 +155,7 @@ void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
 
 void tlb_flush(struct mmu_gather *tlb)
 {
-        struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
+        struct ppc64_tlb_batch *tlbbatch = &get_cpu_var(ppc64_tlb_batch);
 
         /* If there's a TLB batch pending, then we must flush it because the
          * pages are going to be freed and we really don't want to have a CPU
@@ -164,8 +164,7 @@ void tlb_flush(struct mmu_gather *tlb)
         if (tlbbatch->index)
                 __flush_tlb_pending(tlbbatch);
 
-        /* Push out batch of freed page tables */
-        pte_free_finish();
+        put_cpu_var(ppc64_tlb_batch);
 }
 
 /**
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2a030d89bbc6..0bdad3aecc67 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -299,9 +299,6 @@ EXPORT_SYMBOL(flush_tlb_range);
 void tlb_flush(struct mmu_gather *tlb)
 {
         flush_tlb_mm(tlb->mm);
-
-        /* Push out batch of freed page tables */
-        pte_free_finish();
 }
 
 /*
diff --git a/arch/powerpc/oprofile/op_model_power4.c b/arch/powerpc/oprofile/op_model_power4.c
index 8ee51a252cf1..e6bec74be131 100644
--- a/arch/powerpc/oprofile/op_model_power4.c
+++ b/arch/powerpc/oprofile/op_model_power4.c
@@ -261,6 +261,28 @@ static int get_kernel(unsigned long pc, unsigned long mmcra)
         return is_kernel;
 }
 
+static bool pmc_overflow(unsigned long val)
+{
+        if ((int)val < 0)
+                return true;
+
+        /*
+         * Events on POWER7 can roll back if a speculative event doesn't
+         * eventually complete. Unfortunately in some rare cases they will
+         * raise a performance monitor exception. We need to catch this to
+         * ensure we reset the PMC. In all cases the PMC will be 256 or less
+         * cycles from overflow.
+         *
+         * We only do this if the first pass fails to find any overflowing
+         * PMCs because a user might set a period of less than 256 and we
+         * don't want to mistakenly reset them.
+         */
+        if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256))
+                return true;
+
+        return false;
+}
+
 static void power4_handle_interrupt(struct pt_regs *regs,
                                     struct op_counter_config *ctr)
 {
@@ -281,7 +303,7 @@ static void power4_handle_interrupt(struct pt_regs *regs,
 
         for (i = 0; i < cur_cpu_spec->num_pmcs; ++i) {
                 val = classic_ctr_read(i);
-                if (val < 0) {
+                if (pmc_overflow(val)) {
                         if (oprofile_running && ctr[i].enabled) {
                                 oprofile_add_ext_sample(pc, regs, i, is_kernel);
                                 classic_ctr_write(i, reset_value[i]);
diff --git a/arch/powerpc/platforms/40x/Kconfig b/arch/powerpc/platforms/40x/Kconfig
index b72176434ebe..d733d7ca939c 100644
--- a/arch/powerpc/platforms/40x/Kconfig
+++ b/arch/powerpc/platforms/40x/Kconfig
@@ -57,6 +57,8 @@ config KILAUEA
         select 405EX
         select PPC40x_SIMPLE
         select PPC4xx_PCI_EXPRESS
+        select PCI_MSI
+        select PPC4xx_MSI
         help
           This option enables support for the AMCC PPC405EX evaluation board.
 
diff --git a/arch/powerpc/platforms/44x/Kconfig b/arch/powerpc/platforms/44x/Kconfig
index f485fc5f6d5e..e958b6f48ec2 100644
--- a/arch/powerpc/platforms/44x/Kconfig
+++ b/arch/powerpc/platforms/44x/Kconfig
@@ -74,6 +74,8 @@ config KATMAI
         select 440SPe
         select PCI
         select PPC4xx_PCI_EXPRESS
+        select PCI_MSI
+        select PCC4xx_MSI
         help
           This option enables support for the AMCC PPC440SPe evaluation board.
 
@@ -118,6 +120,8 @@ config CANYONLANDS
         select 460EX
         select PCI
         select PPC4xx_PCI_EXPRESS
+        select PCI_MSI
+        select PPC4xx_MSI
         select IBM_NEW_EMAC_RGMII
         select IBM_NEW_EMAC_ZMII
         help
@@ -144,6 +148,8 @@ config REDWOOD
         select 460SX
         select PCI
         select PPC4xx_PCI_EXPRESS
+        select PCI_MSI
+        select PPC4xx_MSI
         help
           This option enables support for the AMCC PPC460SX Redwood board.
 
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 449c08c15862..3e4eba603e6b 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -176,14 +176,14 @@ EXPORT_SYMBOL_GPL(iic_get_target_id);
 #ifdef CONFIG_SMP
 
 /* Use the highest interrupt priorities for IPI */
-static inline int iic_ipi_to_irq(int ipi)
+static inline int iic_msg_to_irq(int msg)
 {
-        return IIC_IRQ_TYPE_IPI + 0xf - ipi;
+        return IIC_IRQ_TYPE_IPI + 0xf - msg;
 }
 
-void iic_cause_IPI(int cpu, int mesg)
+void iic_message_pass(int cpu, int msg)
 {
-        out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - mesg) << 4);
+        out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
 }
 
 struct irq_host *iic_get_irq_host(int node)
@@ -192,50 +192,31 @@ struct irq_host *iic_get_irq_host(int node)
 }
 EXPORT_SYMBOL_GPL(iic_get_irq_host);
 
-static irqreturn_t iic_ipi_action(int irq, void *dev_id)
-{
-        int ipi = (int)(long)dev_id;
-
-        switch(ipi) {
-        case PPC_MSG_CALL_FUNCTION:
-                generic_smp_call_function_interrupt();
-                break;
-        case PPC_MSG_RESCHEDULE:
-                scheduler_ipi();
-                break;
-        case PPC_MSG_CALL_FUNC_SINGLE:
-                generic_smp_call_function_single_interrupt();
-                break;
-        case PPC_MSG_DEBUGGER_BREAK:
-                debug_ipi_action(0, NULL);
-                break;
-        }
-        return IRQ_HANDLED;
-}
-static void iic_request_ipi(int ipi, const char *name)
+static void iic_request_ipi(int msg)
 {
         int virq;
 
-        virq = irq_create_mapping(iic_host, iic_ipi_to_irq(ipi));
+        virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
         if (virq == NO_IRQ) {
                 printk(KERN_ERR
-                       "iic: failed to map IPI %s\n", name);
+                       "iic: failed to map IPI %s\n", smp_ipi_name[msg]);
                 return;
         }
-        if (request_irq(virq, iic_ipi_action, IRQF_DISABLED, name,
-                        (void *)(long)ipi))
-                printk(KERN_ERR
-                       "iic: failed to request IPI %s\n", name);
+
+        /*
+         * If smp_request_message_ipi encounters an error it will notify
+         * the error.  If a message is not needed it will return non-zero.
+         */
+        if (smp_request_message_ipi(virq, msg))
+                irq_dispose_mapping(virq);
 }
 
 void iic_request_IPIs(void)
 {
-        iic_request_ipi(PPC_MSG_CALL_FUNCTION, "IPI-call");
-        iic_request_ipi(PPC_MSG_RESCHEDULE, "IPI-resched");
-        iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE, "IPI-call-single");
-#ifdef CONFIG_DEBUGGER
-        iic_request_ipi(PPC_MSG_DEBUGGER_BREAK, "IPI-debug");
-#endif /* CONFIG_DEBUGGER */
+        iic_request_ipi(PPC_MSG_CALL_FUNCTION);
+        iic_request_ipi(PPC_MSG_RESCHEDULE);
+        iic_request_ipi(PPC_MSG_CALL_FUNC_SINGLE);
+        iic_request_ipi(PPC_MSG_DEBUGGER_BREAK);
 }
 
 #endif /* CONFIG_SMP */
diff --git a/arch/powerpc/platforms/cell/interrupt.h b/arch/powerpc/platforms/cell/interrupt.h
index 942dc39d6045..4f60ae6ca358 100644
--- a/arch/powerpc/platforms/cell/interrupt.h
+++ b/arch/powerpc/platforms/cell/interrupt.h
@@ -75,7 +75,7 @@ enum {
 };
 
 extern void iic_init_IRQ(void);
-extern void iic_cause_IPI(int cpu, int mesg);
+extern void iic_message_pass(int cpu, int msg);
 extern void iic_request_IPIs(void);
 extern void iic_setup_cpu(void);
 
diff --git a/arch/powerpc/platforms/cell/smp.c b/arch/powerpc/platforms/cell/smp.c
index d176e6148e3f..dbb641ea90dd 100644
--- a/arch/powerpc/platforms/cell/smp.c
+++ b/arch/powerpc/platforms/cell/smp.c
@@ -152,7 +152,7 @@ static int smp_cell_cpu_bootable(unsigned int nr)
         return 1;
 }
 static struct smp_ops_t bpa_iic_smp_ops = {
-        .message_pass   = iic_cause_IPI,
+        .message_pass   = iic_message_pass,
         .probe          = smp_iic_probe,
         .kick_cpu       = smp_cell_kick_cpu,
         .setup_cpu      = smp_cell_setup_cpu,
diff --git a/arch/powerpc/sysdev/Kconfig b/arch/powerpc/sysdev/Kconfig
index d775fd148d13..7b4df37ac381 100644
--- a/arch/powerpc/sysdev/Kconfig
+++ b/arch/powerpc/sysdev/Kconfig
@@ -7,11 +7,18 @@ config PPC4xx_PCI_EXPRESS
         depends on PCI && 4xx
         default n
 
+config PPC4xx_MSI
+        bool
+        depends on PCI_MSI
+        depends on PCI && 4xx
+        default n
+
 config PPC_MSI_BITMAP
         bool
         depends on PCI_MSI
         default y if MPIC
         default y if FSL_PCI
+        default y if PPC4xx_MSI
 
 source "arch/powerpc/sysdev/xics/Kconfig"
 
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 6076e0074a87..0efa990e3344 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_OF_RTC)		+= of_rtc.o
 ifeq ($(CONFIG_PCI),y)
 obj-$(CONFIG_4xx)               += ppc4xx_pci.o
 endif
+obj-$(CONFIG_PPC4xx_MSI)        += ppc4xx_msi.o
 obj-$(CONFIG_PPC4xx_CPM)        += ppc4xx_cpm.o
 obj-$(CONFIG_PPC4xx_GPIO)       += ppc4xx_gpio.o
 
diff --git a/arch/powerpc/sysdev/fsl_lbc.c b/arch/powerpc/sysdev/fsl_lbc.c
index 4fcb5a4e60dd..0608b1657da4 100644
--- a/arch/powerpc/sysdev/fsl_lbc.c
+++ b/arch/powerpc/sysdev/fsl_lbc.c
@@ -184,7 +184,8 @@ int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
 }
 EXPORT_SYMBOL(fsl_upm_run_pattern);
 
-static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
+static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
+                                       struct device_node *node)
 {
         struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
@@ -198,6 +199,10 @@ static int __devinit fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl)
         /* Enable interrupts for any detected events */
         out_be32(&lbc->lteir, LTEIR_ENABLE);
 
+        /* Set the monitor timeout value to the maximum for erratum A001 */
+        if (of_device_is_compatible(node, "fsl,elbc"))
+                clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
+
         return 0;
 }
 
@@ -304,7 +309,7 @@ static int __devinit fsl_lbc_ctrl_probe(struct platform_device *dev)
 
         fsl_lbc_ctrl_dev->dev = &dev->dev;
 
-        ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev);
+        ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
         if (ret < 0)
                 goto err;
 
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 49798532b477..5b206a2fe17c 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -10,7 +10,7 @@
  * - Added Port-Write message handling
  * - Added Machine Check exception handling
  *
- * Copyright (C) 2007, 2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007, 2008, 2010 Freescale Semiconductor, Inc.
  * Zhang Wei <wei.zhang@freescale.com>
  *
  * Copyright 2005 MontaVista Software, Inc.
@@ -47,15 +47,33 @@
 #define IRQ_RIO_RX(m)           (((struct rio_priv *)(m->priv))->rxirq)
 #define IRQ_RIO_PW(m)           (((struct rio_priv *)(m->priv))->pwirq)
 
+#define IPWSR_CLEAR             0x98
+#define OMSR_CLEAR              0x1cb3
+#define IMSR_CLEAR              0x491
+#define IDSR_CLEAR              0x91
+#define ODSR_CLEAR              0x1c00
+#define LTLEECSR_ENABLE_ALL     0xFFC000FC
+#define ESCSR_CLEAR             0x07120204
+
+#define RIO_PORT1_EDCSR         0x0640
+#define RIO_PORT2_EDCSR         0x0680
+#define RIO_PORT1_IECSR         0x10130
+#define RIO_PORT2_IECSR         0x101B0
+#define RIO_IM0SR               0x13064
+#define RIO_IM1SR               0x13164
+#define RIO_OM0SR               0x13004
+#define RIO_OM1SR               0x13104
+
 #define RIO_ATMU_REGS_OFFSET    0x10c00
 #define RIO_P_MSG_REGS_OFFSET   0x11000
 #define RIO_S_MSG_REGS_OFFSET   0x13000
 #define RIO_GCCSR               0x13c
 #define RIO_ESCSR               0x158
+#define RIO_PORT2_ESCSR         0x178
 #define RIO_CCSR                0x15c
 #define RIO_LTLEDCSR            0x0608
-#define  RIO_LTLEDCSR_IER       0x80000000
-#define  RIO_LTLEDCSR_PRT       0x01000000
+#define RIO_LTLEDCSR_IER        0x80000000
+#define RIO_LTLEDCSR_PRT        0x01000000
 #define RIO_LTLEECSR            0x060c
 #define RIO_EPWISR              0x10010
 #define RIO_ISR_AACR            0x10120
@@ -88,7 +106,10 @@
 #define RIO_IPWSR_PWD           0x00000008
 #define RIO_IPWSR_PWB           0x00000004
 
-#define RIO_EPWISR_PINT         0x80000000
+/* EPWISR Error match value */
+#define RIO_EPWISR_PINT1        0x80000000
+#define RIO_EPWISR_PINT2        0x40000000
+#define RIO_EPWISR_MU           0x00000002
 #define RIO_EPWISR_PW           0x00000001
 
 #define RIO_MSG_DESC_SIZE       32
@@ -260,9 +281,7 @@ struct rio_priv {
 static void __iomem *rio_regs_win;
 
 #ifdef CONFIG_E500
-static int (*saved_mcheck_exception)(struct pt_regs *regs);
-
-static int fsl_rio_mcheck_exception(struct pt_regs *regs)
+int fsl_rio_mcheck_exception(struct pt_regs *regs)
 {
         const struct exception_table_entry *entry = NULL;
         unsigned long reason = mfspr(SPRN_MCSR);
@@ -284,11 +303,9 @@ static int fsl_rio_mcheck_exception(struct pt_regs *regs)
                 }
         }
 
-        if (saved_mcheck_exception)
-                return saved_mcheck_exception(regs);
-        else
-                return cur_cpu_spec->machine_check(regs);
+        return 0;
 }
+EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
 #endif
 
 /**
@@ -1064,6 +1081,40 @@ static int fsl_rio_doorbell_init(struct rio_mport *mport)
         return rc;
 }
 
+static void port_error_handler(struct rio_mport *port, int offset)
+{
+        /*XXX: Error recovery is not implemented, we just clear errors */
+        out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
+
+        if (offset == 0) {
+                out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
+                out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), 0);
+                out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
+        } else {
+                out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
+                out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), 0);
+                out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
+        }
+}
+
+static void msg_unit_error_handler(struct rio_mport *port)
+{
+        struct rio_priv *priv = port->priv;
+
+        /*XXX: Error recovery is not implemented, we just clear errors */
+        out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
+
+        out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR);
+        out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR);
+        out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR);
+        out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR);
+
+        out_be32(&priv->msg_regs->odsr, ODSR_CLEAR);
+        out_be32(&priv->msg_regs->dsr, IDSR_CLEAR);
+
+        out_be32(&priv->msg_regs->pwsr, IPWSR_CLEAR);
+}
+
 /**
  * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
  * @irq: Linux interrupt number
@@ -1144,10 +1195,22 @@ fsl_rio_port_write_handler(int irq, void *dev_instance)
         }
 
 pw_done:
-        if (epwisr & RIO_EPWISR_PINT) {
+        if (epwisr & RIO_EPWISR_PINT1) {
+                tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
+                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+                port_error_handler(port, 0);
+        }
+
+        if (epwisr & RIO_EPWISR_PINT2) {
                 tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
                 pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
-                out_be32(priv->regs_win + RIO_LTLEDCSR, 0);
+                port_error_handler(port, 1);
+        }
+
+        if (epwisr & RIO_EPWISR_MU) {
+                tmp = in_be32(priv->regs_win + RIO_LTLEDCSR);
+                pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
+                msg_unit_error_handler(port);
         }
 
         return IRQ_HANDLED;
@@ -1258,12 +1321,14 @@ static int fsl_rio_port_write_init(struct rio_mport *mport)
 
 
         /* Hook up port-write handler */
-        rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, 0,
-                         "port-write", (void *)mport);
+        rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler,
+                        IRQF_SHARED, "port-write", (void *)mport);
         if (rc < 0) {
                 pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
                 goto err_out;
         }
+        /* Enable Error Interrupt */
+        out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
 
         INIT_WORK(&priv->pw_work, fsl_pw_dpc);
         spin_lock_init(&priv->pw_fifo_lock);
@@ -1538,11 +1603,6 @@ int fsl_rio_setup(struct platform_device *dev)
         fsl_rio_doorbell_init(port);
         fsl_rio_port_write_init(port);
 
-#ifdef CONFIG_E500
-        saved_mcheck_exception = ppc_md.machine_check_exception;
-        ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
-#endif
-
         return 0;
 err:
         iounmap(priv->regs_win);
diff --git a/arch/powerpc/sysdev/ppc4xx_msi.c b/arch/powerpc/sysdev/ppc4xx_msi.c
new file mode 100644
index 000000000000..367af0241851
--- /dev/null
+++ b/arch/powerpc/sysdev/ppc4xx_msi.c
@@ -0,0 +1,276 @@
+/*
+ * Adding PCI-E MSI support for PPC4XX SoCs.
+ *
+ * Copyright (c) 2010, Applied Micro Circuits Corporation
+ * Authors:     Tirumala R Marri <tmarri@apm.com>
+ *              Feng Kan <fkan@apm.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/irq.h>
+#include <linux/bootmem.h>
+#include <linux/pci.h>
+#include <linux/msi.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#include <asm/prom.h>
+#include <asm/hw_irq.h>
+#include <asm/ppc-pci.h>
+#include <boot/dcr.h>
+#include <asm/dcr-regs.h>
+#include <asm/msi_bitmap.h>
+
+#define PEIH_TERMADH    0x00
+#define PEIH_TERMADL    0x08
+#define PEIH_MSIED      0x10
+#define PEIH_MSIMK      0x18
+#define PEIH_MSIASS     0x20
+#define PEIH_FLUSH0     0x30
+#define PEIH_FLUSH1     0x38
+#define PEIH_CNTRST     0x48
+#define NR_MSI_IRQS     4
+
+struct ppc4xx_msi {
+        u32 msi_addr_lo;
+        u32 msi_addr_hi;
+        void __iomem *msi_regs;
+        int msi_virqs[NR_MSI_IRQS];
+        struct msi_bitmap bitmap;
+        struct device_node *msi_dev;
+};
+
+static struct ppc4xx_msi ppc4xx_msi;
+
+static int ppc4xx_msi_init_allocator(struct platform_device *dev,
+                struct ppc4xx_msi *msi_data)
+{
+        int err;
+
+        err = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
+                              dev->dev.of_node);
+        if (err)
+                return err;
+
+        err = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
+        if (err < 0) {
+                msi_bitmap_free(&msi_data->bitmap);
+                return err;
+        }
+
+        return 0;
+}
+
+static int ppc4xx_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
+{
+        int int_no = -ENOMEM;
+        unsigned int virq;
+        struct msi_msg msg;
+        struct msi_desc *entry;
+        struct ppc4xx_msi *msi_data = &ppc4xx_msi;
+
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                int_no = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
+                if (int_no >= 0)
+                        break;
+                if (int_no < 0) {
+                        pr_debug("%s: fail allocating msi interrupt\n",
+                                        __func__);
+                }
+                virq = irq_of_parse_and_map(msi_data->msi_dev, int_no);
+                if (virq == NO_IRQ) {
+                        dev_err(&dev->dev, "%s: fail mapping irq\n", __func__);
+                        msi_bitmap_free_hwirqs(&msi_data->bitmap, int_no, 1);
+                        return -ENOSPC;
+                }
+                dev_dbg(&dev->dev, "%s: virq = %d\n", __func__, virq);
+
+                /* Setup msi address space */
+                msg.address_hi = msi_data->msi_addr_hi;
+                msg.address_lo = msi_data->msi_addr_lo;
+
+                irq_set_msi_desc(virq, entry);
+                msg.data = int_no;
+                write_msi_msg(virq, &msg);
+        }
+        return 0;
+}
+
+void ppc4xx_teardown_msi_irqs(struct pci_dev *dev)
+{
+        struct msi_desc *entry;
+        struct ppc4xx_msi *msi_data = &ppc4xx_msi;
+
+        dev_dbg(&dev->dev, "PCIE-MSI: tearing down msi irqs\n");
+
+        list_for_each_entry(entry, &dev->msi_list, list) {
+                if (entry->irq == NO_IRQ)
+                        continue;
+                irq_set_msi_desc(entry->irq, NULL);
+                msi_bitmap_free_hwirqs(&msi_data->bitmap,
+                                virq_to_hw(entry->irq), 1);
+                irq_dispose_mapping(entry->irq);
+        }
+}
+
+static int ppc4xx_msi_check_device(struct pci_dev *pdev, int nvec, int type)
+{
+        dev_dbg(&pdev->dev, "PCIE-MSI:%s called. vec %x type %d\n",
+                __func__, nvec, type);
+        if (type == PCI_CAP_ID_MSIX)
+                pr_debug("ppc4xx msi: MSI-X untested, trying anyway.\n");
+
+        return 0;
+}
+
+static int ppc4xx_setup_pcieh_hw(struct platform_device *dev,
+                                 struct resource res, struct ppc4xx_msi *msi)
+{
+        const u32 *msi_data;
+        const u32 *msi_mask;
+        const u32 *sdr_addr;
+        dma_addr_t msi_phys;
+        void *msi_virt;
+
+        sdr_addr = of_get_property(dev->dev.of_node, "sdr-base", NULL);
+        if (!sdr_addr)
+                return -1;
+
+        SDR0_WRITE(sdr_addr, (u64)res.start >> 32);      /*HIGH addr */
+        SDR0_WRITE(sdr_addr + 1, res.start & 0xFFFFFFFF); /* Low addr */
+
+
+        msi->msi_dev = of_find_node_by_name(NULL, "ppc4xx-msi");
+        if (msi->msi_dev)
+                return -ENODEV;
+
+        msi->msi_regs = of_iomap(msi->msi_dev, 0);
+        if (!msi->msi_regs) {
+                dev_err(&dev->dev, "of_iomap problem failed\n");
+                return -ENOMEM;
+        }
+        dev_dbg(&dev->dev, "PCIE-MSI: msi register mapped 0x%x 0x%x\n",
+                (u32) (msi->msi_regs + PEIH_TERMADH), (u32) (msi->msi_regs));
+
+        msi_virt = dma_alloc_coherent(&dev->dev, 64, &msi_phys, GFP_KERNEL);
+        msi->msi_addr_hi = 0x0;
+        msi->msi_addr_lo = (u32) msi_phys;
+        dev_dbg(&dev->dev, "PCIE-MSI: msi address 0x%x\n", msi->msi_addr_lo);
+
+        /* Progam the Interrupt handler Termination addr registers */
+        out_be32(msi->msi_regs + PEIH_TERMADH, msi->msi_addr_hi);
+        out_be32(msi->msi_regs + PEIH_TERMADL, msi->msi_addr_lo);
+
+        msi_data = of_get_property(dev->dev.of_node, "msi-data", NULL);
+        if (!msi_data)
+                return -1;
+        msi_mask = of_get_property(dev->dev.of_node, "msi-mask", NULL);
+        if (!msi_mask)
+                return -1;
+        /* Program MSI Expected data and Mask bits */
+        out_be32(msi->msi_regs + PEIH_MSIED, *msi_data);
+        out_be32(msi->msi_regs + PEIH_MSIMK, *msi_mask);
+
+        return 0;
+}
+
+static int ppc4xx_of_msi_remove(struct platform_device *dev)
+{
+        struct ppc4xx_msi *msi = dev->dev.platform_data;
+        int i;
+        int virq;
+
+        for (i = 0; i < NR_MSI_IRQS; i++) {
+                virq = msi->msi_virqs[i];
+                if (virq != NO_IRQ)
+                        irq_dispose_mapping(virq);
+        }
+
+        if (msi->bitmap.bitmap)
+                msi_bitmap_free(&msi->bitmap);
+        iounmap(msi->msi_regs);
+        of_node_put(msi->msi_dev);
+        kfree(msi);
+
+        return 0;
+}
+
+static int __devinit ppc4xx_msi_probe(struct platform_device *dev)
+{
+        struct ppc4xx_msi *msi;
+        struct resource res;
+        int err = 0;
+
+        msi = &ppc4xx_msi;/*keep the msi data for further use*/
+
+        dev_dbg(&dev->dev, "PCIE-MSI: Setting up MSI support...\n");
+
+        msi = kzalloc(sizeof(struct ppc4xx_msi), GFP_KERNEL);
+        if (!msi) {
+                dev_err(&dev->dev, "No memory for MSI structure\n");
+                return -ENOMEM;
+        }
+        dev->dev.platform_data = msi;
+
+        /* Get MSI ranges */
+        err = of_address_to_resource(dev->dev.of_node, 0, &res);
+        if (err) {
+                dev_err(&dev->dev, "%s resource error!\n",
+                        dev->dev.of_node->full_name);
+                goto error_out;
+        }
+
+        if (ppc4xx_setup_pcieh_hw(dev, res, msi))
+                goto error_out;
+
+        err = ppc4xx_msi_init_allocator(dev, msi);
+        if (err) {
+                dev_err(&dev->dev, "Error allocating MSI bitmap\n");
+                goto error_out;
+        }
+
+        ppc_md.setup_msi_irqs = ppc4xx_setup_msi_irqs;
+        ppc_md.teardown_msi_irqs = ppc4xx_teardown_msi_irqs;
+        ppc_md.msi_check_device = ppc4xx_msi_check_device;
+        return err;
+
+error_out:
+        ppc4xx_of_msi_remove(dev);
+        return err;
+}
+static const struct of_device_id ppc4xx_msi_ids[] = {
+        {
+                .compatible = "amcc,ppc4xx-msi",
+        },
+        {}
+};
+static struct platform_driver ppc4xx_msi_driver = {
+        .probe = ppc4xx_msi_probe,
+        .remove = ppc4xx_of_msi_remove,
+        .driver = {
+                   .name = "ppc4xx-msi",
+                   .owner = THIS_MODULE,
+                   .of_match_table = ppc4xx_msi_ids,
+                   },
+
+};
+
+static __init int ppc4xx_msi_init(void)
+{
+        return platform_driver_register(&ppc4xx_msi_driver);
+}
+
+subsys_initcall(ppc4xx_msi_init);
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 4a7f14079e03..9fab2aa9c2c8 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -2,7 +2,7 @@ config MMU
         def_bool y
 
 config ZONE_DMA
-        def_bool y if 64BIT
+        def_bool y
 
 config LOCKDEP_SUPPORT
         def_bool y
@@ -230,17 +230,6 @@ config SYSVIPC_COMPAT
 config AUDIT_ARCH
         def_bool y
 
-config S390_EXEC_PROTECT
-        def_bool y
-        prompt "Data execute protection"
-        help
-          This option allows to enable a buffer overflow protection for user
-          space programs and it also selects the addressing mode option above.
-          The kernel parameter noexec=on will enable this feature and also
-          switch the addressing modes, default is disabled. Enabling this (via
-          kernel parameter) on machines earlier than IBM System z9 this will
-          reduce system performance.
-
 comment "Code generation options"
 
 choice
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index 5c91995b74e4..24bff4f1cc52 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -130,9 +130,7 @@ static void appldata_work_fn(struct work_struct *work)
 {
         struct list_head *lh;
         struct appldata_ops *ops;
-        int i;
 
-        i = 0;
         get_online_cpus();
         mutex_lock(&appldata_ops_mutex);
         list_for_each(lh, &appldata_ops_list) {
diff --git a/arch/s390/appldata/appldata_mem.c b/arch/s390/appldata/appldata_mem.c
index e43fe7537031..f7d3dc555bdb 100644
--- a/arch/s390/appldata/appldata_mem.c
+++ b/arch/s390/appldata/appldata_mem.c
@@ -92,9 +92,7 @@ static void appldata_get_mem_data(void *data)
         mem_data->pswpin     = ev[PSWPIN];
         mem_data->pswpout    = ev[PSWPOUT];
         mem_data->pgalloc    = ev[PGALLOC_NORMAL];
-#ifdef CONFIG_ZONE_DMA
         mem_data->pgalloc    += ev[PGALLOC_DMA];
-#endif
         mem_data->pgfault    = ev[PGFAULT];
         mem_data->pgmajfault = ev[PGMAJFAULT];
 
diff --git a/arch/s390/include/asm/bitops.h b/arch/s390/include/asm/bitops.h
index e1c8f3a49884..667c6e9f6a34 100644
--- a/arch/s390/include/asm/bitops.h
+++ b/arch/s390/include/asm/bitops.h
@@ -621,6 +621,7 @@ static inline unsigned long find_first_zero_bit(const unsigned long *addr,
         bits = __ffz_word(bytes*8, __load_ulong_be(addr, bytes));
         return (bits < size) ? bits : size;
 }
+#define find_first_zero_bit find_first_zero_bit
 
 /**
  * find_first_bit - find the first set bit in a memory region
@@ -641,6 +642,7 @@ static inline unsigned long find_first_bit(const unsigned long * addr,
         bits = __ffs_word(bytes*8, __load_ulong_be(addr, bytes));
         return (bits < size) ? bits : size;
 }
+#define find_first_bit find_first_bit
 
 /**
  * find_next_zero_bit - find the first zero bit in a memory region
@@ -677,6 +679,7 @@ static inline int find_next_zero_bit (const unsigned long * addr,
         }
         return offset + find_first_zero_bit(p, size);
 }
+#define find_next_zero_bit find_next_zero_bit
 
 /**
  * find_next_bit - find the first set bit in a memory region
@@ -713,6 +716,7 @@ static inline int find_next_bit (const unsigned long * addr,
         }
         return offset + find_first_bit(p, size);
 }
+#define find_next_bit find_next_bit
 
 /*
  * Every architecture must define this function. It's the fastest
@@ -742,41 +746,6 @@ static inline int sched_find_first_bit(unsigned long *b)
  *    23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
  */
 
-static inline void __set_bit_le(unsigned long nr, void *addr)
-{
-        __set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
-static inline void __clear_bit_le(unsigned long nr, void *addr)
-{
-        __clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
-static inline int __test_and_set_bit_le(unsigned long nr, void *addr)
-{
-        return __test_and_set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
-static inline int test_and_set_bit_le(unsigned long nr, void *addr)
-{
-        return test_and_set_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
-static inline int __test_and_clear_bit_le(unsigned long nr, void *addr)
-{
-        return __test_and_clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
-static inline int test_and_clear_bit_le(unsigned long nr, void *addr)
-{
-        return test_and_clear_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
-static inline int test_bit_le(unsigned long nr, const void *addr)
-{
-        return test_bit(nr ^ (__BITOPS_WORDSIZE - 8), addr);
-}
-
 static inline int find_first_zero_bit_le(void *vaddr, unsigned int size)
 {
         unsigned long bytes, bits;
@@ -787,6 +756,7 @@ static inline int find_first_zero_bit_le(void *vaddr, unsigned int size)
         bits = __ffz_word(bytes*8, __load_ulong_le(vaddr, bytes));
         return (bits < size) ? bits : size;
 }
+#define find_first_zero_bit_le find_first_zero_bit_le
 
 static inline int find_next_zero_bit_le(void *vaddr, unsigned long size,
                                           unsigned long offset)
@@ -816,6 +786,7 @@ static inline int find_next_zero_bit_le(void *vaddr, unsigned long size,
         }
         return offset + find_first_zero_bit_le(p, size);
 }
+#define find_next_zero_bit_le find_next_zero_bit_le
 
 static inline unsigned long find_first_bit_le(void *vaddr, unsigned long size)
 {
@@ -827,6 +798,7 @@ static inline unsigned long find_first_bit_le(void *vaddr, unsigned long size)
         bits = __ffs_word(bytes*8, __load_ulong_le(vaddr, bytes));
         return (bits < size) ? bits : size;
 }
+#define find_first_bit_le find_first_bit_le
 
 static inline int find_next_bit_le(void *vaddr, unsigned long size,
                                      unsigned long offset)
@@ -856,6 +828,9 @@ static inline int find_next_bit_le(void *vaddr, unsigned long size,
         }
         return offset + find_first_bit_le(p, size);
 }
+#define find_next_bit_le find_next_bit_le
+
+#include <asm-generic/bitops/le.h>
 
 #define ext2_set_bit_atomic(lock, nr, addr)     \
         test_and_set_bit_le(nr, addr)
diff --git a/arch/s390/include/asm/cmpxchg.h b/arch/s390/include/asm/cmpxchg.h
index 7488e52efa97..81d7908416cf 100644
--- a/arch/s390/include/asm/cmpxchg.h
+++ b/arch/s390/include/asm/cmpxchg.h
@@ -167,7 +167,6 @@ static inline unsigned long __cmpxchg(void *ptr, unsigned long old,
 #ifdef CONFIG_64BIT
 #define cmpxchg64(ptr, o, n)                                            \
 ({                                                                      \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
         cmpxchg((ptr), (o), (n));                                       \
 })
 #else /* CONFIG_64BIT */
diff --git a/arch/s390/include/asm/delay.h b/arch/s390/include/asm/delay.h
index 8a096b83f51f..0e3b35f96be1 100644
--- a/arch/s390/include/asm/delay.h
+++ b/arch/s390/include/asm/delay.h
@@ -14,10 +14,12 @@
 #ifndef _S390_DELAY_H
 #define _S390_DELAY_H
 
-extern void __udelay(unsigned long long usecs);
-extern void udelay_simple(unsigned long long usecs);
-extern void __delay(unsigned long loops);
+void __ndelay(unsigned long long nsecs);
+void __udelay(unsigned long long usecs);
+void udelay_simple(unsigned long long usecs);
+void __delay(unsigned long loops);
 
+#define ndelay(n) __ndelay((unsigned long long) (n))
 #define udelay(n) __udelay((unsigned long long) (n))
 #define mdelay(n) __udelay((unsigned long long) (n) * 1000)
 
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
index 10c029cfcc7d..64b61bf72e93 100644
--- a/arch/s390/include/asm/elf.h
+++ b/arch/s390/include/asm/elf.h
@@ -196,18 +196,6 @@ do {								\
 } while (0)
 #endif /* __s390x__ */
 
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically.
- */
-#define elf_read_implies_exec(ex, executable_stack)     \
-({                                                      \
-        if (current->mm->context.noexec &&              \
-            executable_stack != EXSTACK_DISABLE_X)      \
-                disable_noexec(current->mm, current);   \
-        current->mm->context.noexec == 0;               \
-})
-
 #define STACK_RND_MASK  0x7ffUL
 
 #define ARCH_DLINFO                                                         \
diff --git a/arch/s390/include/asm/hugetlb.h b/arch/s390/include/asm/hugetlb.h
index b56403c2df28..799ed0f1643d 100644
--- a/arch/s390/include/asm/hugetlb.h
+++ b/arch/s390/include/asm/hugetlb.h
@@ -111,21 +111,10 @@ static inline void huge_ptep_invalidate(struct mm_struct *mm,
 {
         pmd_t *pmdp = (pmd_t *) ptep;
 
-        if (!MACHINE_HAS_IDTE) {
-                __pmd_csp(pmdp);
-                if (mm->context.noexec) {
-                        pmdp = get_shadow_table(pmdp);
-                        __pmd_csp(pmdp);
-                }
-                return;
-        }
-
-        __pmd_idte(address, pmdp);
-        if (mm->context.noexec) {
-                pmdp = get_shadow_table(pmdp);
+        if (MACHINE_HAS_IDTE)
                 __pmd_idte(address, pmdp);
-        }
-        return;
+        else
+                __pmd_csp(pmdp);
 }
 
 #define huge_ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index db14a311f1d2..ba7b01c726a3 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -2,6 +2,7 @@
 #define _ASM_IRQ_H
 
 #include <linux/hardirq.h>
+#include <linux/types.h>
 
 enum interruption_class {
         EXTERNAL_INTERRUPT,
@@ -15,6 +16,7 @@ enum interruption_class {
         EXTINT_VRT,
         EXTINT_SCP,
         EXTINT_IUC,
+        EXTINT_CPM,
         IOINT_QAI,
         IOINT_QDI,
         IOINT_DAS,
@@ -30,4 +32,11 @@ enum interruption_class {
         NR_IRQS,
 };
 
+typedef void (*ext_int_handler_t)(unsigned int, unsigned int, unsigned long);
+
+int register_external_interrupt(u16 code, ext_int_handler_t handler);
+int unregister_external_interrupt(u16 code, ext_int_handler_t handler);
+void service_subclass_irq_register(void);
+void service_subclass_irq_unregister(void);
+
 #endif /* _ASM_IRQ_H */
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index 65e172f8209d..228cf0b295db 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -124,7 +124,7 @@ struct _lowcore {
         /* Address space pointer. */
         __u32   kernel_asce;                    /* 0x02ac */
         __u32   user_asce;                      /* 0x02b0 */
-        __u32   user_exec_asce;                 /* 0x02b4 */
+        __u32   current_pid;                    /* 0x02b4 */
 
         /* SMP info area */
         __u32   cpu_nr;                         /* 0x02b8 */
@@ -255,7 +255,7 @@ struct _lowcore {
         /* Address space pointer. */
         __u64   kernel_asce;                    /* 0x0310 */
         __u64   user_asce;                      /* 0x0318 */
-        __u64   user_exec_asce;                 /* 0x0320 */
+        __u64   current_pid;                    /* 0x0320 */
 
         /* SMP info area */
         __u32   cpu_nr;                         /* 0x0328 */
diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h
index 78522cdefdd4..82d0847896a0 100644
--- a/arch/s390/include/asm/mmu.h
+++ b/arch/s390/include/asm/mmu.h
@@ -5,19 +5,18 @@ typedef struct {
         atomic_t attach_count;
         unsigned int flush_mm;
         spinlock_t list_lock;
-        struct list_head crst_list;
         struct list_head pgtable_list;
         unsigned long asce_bits;
         unsigned long asce_limit;
         unsigned long vdso_base;
-        int noexec;
-        int has_pgste;   /* The mmu context has extended page tables */
-        int alloc_pgste; /* cloned contexts will have extended page tables */
+        /* Cloned contexts will be created with extended page tables. */
+        unsigned int alloc_pgste:1;
+        /* The mmu context has extended page tables. */
+        unsigned int has_pgste:1;
 } mm_context_t;
 
 #define INIT_MM_CONTEXT(name)                                                 \
         .context.list_lock    = __SPIN_LOCK_UNLOCKED(name.context.list_lock), \
-        .context.crst_list    = LIST_HEAD_INIT(name.context.crst_list),       \
         .context.pgtable_list = LIST_HEAD_INIT(name.context.pgtable_list),
 
 #endif
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h
index 8c277caa8d3a..5682f160ff82 100644
--- a/arch/s390/include/asm/mmu_context.h
+++ b/arch/s390/include/asm/mmu_context.h
@@ -35,11 +35,9 @@ static inline int init_new_context(struct task_struct *tsk,
                  * and if has_pgste is set, it will create extended page
                  * tables.
                  */
-                mm->context.noexec = 0;
                 mm->context.has_pgste = 1;
                 mm->context.alloc_pgste = 1;
         } else {
-                mm->context.noexec = (user_mode == SECONDARY_SPACE_MODE);
                 mm->context.has_pgste = 0;
                 mm->context.alloc_pgste = 0;
         }
@@ -63,10 +61,8 @@ static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
         S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
         if (user_mode != HOME_SPACE_MODE) {
                 /* Load primary space page table origin. */
-                pgd = mm->context.noexec ? get_shadow_table(pgd) : pgd;
-                S390_lowcore.user_exec_asce = mm->context.asce_bits | __pa(pgd);
                 asm volatile(LCTL_OPCODE" 1,1,%0\n"
-                             : : "m" (S390_lowcore.user_exec_asce) );
+                             : : "m" (S390_lowcore.user_asce) );
         } else
                 /* Load home space page table origin. */
                 asm volatile(LCTL_OPCODE" 13,13,%0"
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index 3c987e9ec8d6..accb372ddc7e 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -90,6 +90,7 @@ static inline void copy_page(void *to, void *from)
  */
 
 typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgste; } pgste_t;
 typedef struct { unsigned long pte; } pte_t;
 typedef struct { unsigned long pmd; } pmd_t;
 typedef struct { unsigned long pud; } pud_t;
@@ -97,18 +98,21 @@ typedef struct { unsigned long pgd; } pgd_t;
 typedef pte_t *pgtable_t;
 
 #define pgprot_val(x)   ((x).pgprot)
+#define pgste_val(x)    ((x).pgste)
 #define pte_val(x)      ((x).pte)
 #define pmd_val(x)      ((x).pmd)
 #define pud_val(x)      ((x).pud)
 #define pgd_val(x)      ((x).pgd)
 
+#define __pgste(x)      ((pgste_t) { (x) } )
 #define __pte(x)        ((pte_t) { (x) } )
 #define __pmd(x)        ((pmd_t) { (x) } )
+#define __pud(x)        ((pud_t) { (x) } )
 #define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
-static inline void
-page_set_storage_key(unsigned long addr, unsigned int skey, int mapped)
+static inline void page_set_storage_key(unsigned long addr,
+                                        unsigned char skey, int mapped)
 {
         if (!mapped)
                 asm volatile(".insn rrf,0xb22b0000,%0,%1,8,0"
@@ -117,15 +121,59 @@ page_set_storage_key(unsigned long addr, unsigned int skey, int mapped)
                 asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
 }
 
-static inline unsigned int
-page_get_storage_key(unsigned long addr)
+static inline unsigned char page_get_storage_key(unsigned long addr)
 {
-        unsigned int skey;
+        unsigned char skey;
 
-        asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr), "0" (0));
+        asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr));
         return skey;
 }
 
+static inline int page_reset_referenced(unsigned long addr)
+{
+        unsigned int ipm;
+
+        asm volatile(
+                "       rrbe    0,%1\n"
+                "       ipm     %0\n"
+                : "=d" (ipm) : "a" (addr) : "cc");
+        return !!(ipm & 0x20000000);
+}
+
+/* Bits int the storage key */
+#define _PAGE_CHANGED           0x02    /* HW changed bit               */
+#define _PAGE_REFERENCED        0x04    /* HW referenced bit            */
+#define _PAGE_FP_BIT            0x08    /* HW fetch protection bit      */
+#define _PAGE_ACC_BITS          0xf0    /* HW access control bits       */
+
+/*
+ * Test and clear dirty bit in storage key.
+ * We can't clear the changed bit atomically. This is a potential
+ * race against modification of the referenced bit. This function
+ * should therefore only be called if it is not mapped in any
+ * address space.
+ */
+#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
+static inline int page_test_and_clear_dirty(unsigned long pfn, int mapped)
+{
+        unsigned char skey;
+
+        skey = page_get_storage_key(pfn << PAGE_SHIFT);
+        if (!(skey & _PAGE_CHANGED))
+                return 0;
+        page_set_storage_key(pfn << PAGE_SHIFT, skey & ~_PAGE_CHANGED, mapped);
+        return 1;
+}
+
+/*
+ * Test and clear referenced bit in storage key.
+ */
+#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
+static inline int page_test_and_clear_young(unsigned long pfn)
+{
+        return page_reset_referenced(pfn << PAGE_SHIFT);
+}
+
 struct page;
 void arch_free_page(struct page *page, int order);
 void arch_alloc_page(struct page *page, int order);
diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h
index f7ad8719d02d..5325c89a5843 100644
--- a/arch/s390/include/asm/percpu.h
+++ b/arch/s390/include/asm/percpu.h
@@ -1,6 +1,9 @@
 #ifndef __ARCH_S390_PERCPU__
 #define __ARCH_S390_PERCPU__
 
+#include <linux/preempt.h>
+#include <asm/cmpxchg.h>
+
 /*
  * s390 uses its own implementation for per cpu data, the offset of
  * the cpu local data area is cached in the cpu's lowcore memory.
@@ -16,6 +19,71 @@
 #define ARCH_NEEDS_WEAK_PER_CPU
 #endif
 
+#define arch_irqsafe_cpu_to_op(pcp, val, op)                            \
+do {                                                                    \
+        typedef typeof(pcp) pcp_op_T__;                                 \
+        pcp_op_T__ old__, new__, prev__;                                \
+        pcp_op_T__ *ptr__;                                              \
+        preempt_disable();                                              \
+        ptr__ = __this_cpu_ptr(&(pcp));                                 \
+        prev__ = *ptr__;                                                \
+        do {                                                            \
+                old__ = prev__;                                         \
+                new__ = old__ op (val);                                 \
+                switch (sizeof(*ptr__)) {                               \
+                case 8:                                                 \
+                        prev__ = cmpxchg64(ptr__, old__, new__);        \
+                        break;                                          \
+                default:                                                \
+                        prev__ = cmpxchg(ptr__, old__, new__);          \
+                }                                                       \
+        } while (prev__ != old__);                                      \
+        preempt_enable();                                               \
+} while (0)
+
+#define irqsafe_cpu_add_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define irqsafe_cpu_add_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define irqsafe_cpu_add_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define irqsafe_cpu_add_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+
+#define irqsafe_cpu_and_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define irqsafe_cpu_and_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define irqsafe_cpu_and_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define irqsafe_cpu_and_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+
+#define irqsafe_cpu_or_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define irqsafe_cpu_or_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define irqsafe_cpu_or_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define irqsafe_cpu_or_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+
+#define irqsafe_cpu_xor_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define irqsafe_cpu_xor_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define irqsafe_cpu_xor_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define irqsafe_cpu_xor_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+
+#define arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)                       \
+({                                                                      \
+        typedef typeof(pcp) pcp_op_T__;                                 \
+        pcp_op_T__ ret__;                                               \
+        pcp_op_T__ *ptr__;                                              \
+        preempt_disable();                                              \
+        ptr__ = __this_cpu_ptr(&(pcp));                                 \
+        switch (sizeof(*ptr__)) {                                       \
+        case 8:                                                         \
+                ret__ = cmpxchg64(ptr__, oval, nval);                   \
+                break;                                                  \
+        default:                                                        \
+                ret__ = cmpxchg(ptr__, oval, nval);                     \
+        }                                                               \
+        preempt_enable();                                               \
+        ret__;                                                          \
+})
+
+#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+
 #include <asm-generic/percpu.h>
 
 #endif /* __ARCH_S390_PERCPU__ */
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index 082eb4e50e8b..f6314af3b354 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -19,14 +19,13 @@
 
 #define check_pgt_cache()       do {} while (0)
 
-unsigned long *crst_table_alloc(struct mm_struct *, int);
+unsigned long *crst_table_alloc(struct mm_struct *);
 void crst_table_free(struct mm_struct *, unsigned long *);
 void crst_table_free_rcu(struct mm_struct *, unsigned long *);
 
 unsigned long *page_table_alloc(struct mm_struct *);
 void page_table_free(struct mm_struct *, unsigned long *);
 void page_table_free_rcu(struct mm_struct *, unsigned long *);
-void disable_noexec(struct mm_struct *, struct task_struct *);
 
 static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
 {
@@ -50,9 +49,6 @@ static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
 static inline void crst_table_init(unsigned long *crst, unsigned long entry)
 {
         clear_table(crst, entry, sizeof(unsigned long)*2048);
-        crst = get_shadow_table(crst);
-        if (crst)
-                clear_table(crst, entry, sizeof(unsigned long)*2048);
 }
 
 #ifndef __s390x__
@@ -69,10 +65,7 @@ static inline unsigned long pgd_entry_type(struct mm_struct *mm)
 #define pmd_free(mm, x)                         do { } while (0)
 
 #define pgd_populate(mm, pgd, pud)              BUG()
-#define pgd_populate_kernel(mm, pgd, pud)       BUG()
-
 #define pud_populate(mm, pud, pmd)              BUG()
-#define pud_populate_kernel(mm, pud, pmd)       BUG()
 
 #else /* __s390x__ */
 
@@ -90,7 +83,7 @@ void crst_table_downgrade(struct mm_struct *, unsigned long limit);
 
 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
 {
-        unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
+        unsigned long *table = crst_table_alloc(mm);
         if (table)
                 crst_table_init(table, _REGION3_ENTRY_EMPTY);
         return (pud_t *) table;
@@ -99,43 +92,21 @@ static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long vmaddr)
 {
-        unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
+        unsigned long *table = crst_table_alloc(mm);
         if (table)
                 crst_table_init(table, _SEGMENT_ENTRY_EMPTY);
         return (pmd_t *) table;
 }
 #define pmd_free(mm, pmd) crst_table_free(mm, (unsigned long *) pmd)
 
-static inline void pgd_populate_kernel(struct mm_struct *mm,
-                                       pgd_t *pgd, pud_t *pud)
-{
-        pgd_val(*pgd) = _REGION2_ENTRY | __pa(pud);
-}
-
 static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
 {
-        pgd_populate_kernel(mm, pgd, pud);
-        if (mm->context.noexec) {
-                pgd = get_shadow_table(pgd);
-                pud = get_shadow_table(pud);
-                pgd_populate_kernel(mm, pgd, pud);
-        }
-}
-
-static inline void pud_populate_kernel(struct mm_struct *mm,
-                                       pud_t *pud, pmd_t *pmd)
-{
-        pud_val(*pud) = _REGION3_ENTRY | __pa(pmd);
+        pgd_val(*pgd) = _REGION2_ENTRY | __pa(pud);
 }
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 {
-        pud_populate_kernel(mm, pud, pmd);
-        if (mm->context.noexec) {
-                pud = get_shadow_table(pud);
-                pmd = get_shadow_table(pmd);
-                pud_populate_kernel(mm, pud, pmd);
-        }
+        pud_val(*pud) = _REGION3_ENTRY | __pa(pmd);
 }
 
 #endif /* __s390x__ */
@@ -143,29 +114,19 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
         spin_lock_init(&mm->context.list_lock);
-        INIT_LIST_HEAD(&mm->context.crst_list);
         INIT_LIST_HEAD(&mm->context.pgtable_list);
-        return (pgd_t *)
-                crst_table_alloc(mm, user_mode == SECONDARY_SPACE_MODE);
+        return (pgd_t *) crst_table_alloc(mm);
 }
 #define pgd_free(mm, pgd) crst_table_free(mm, (unsigned long *) pgd)
 
-static inline void pmd_populate_kernel(struct mm_struct *mm,
-                                       pmd_t *pmd, pte_t *pte)
-{
-        pmd_val(*pmd) = _SEGMENT_ENTRY + __pa(pte);
-}
-
 static inline void pmd_populate(struct mm_struct *mm,
                                 pmd_t *pmd, pgtable_t pte)
 {
-        pmd_populate_kernel(mm, pmd, pte);
-        if (mm->context.noexec) {
-                pmd = get_shadow_table(pmd);
-                pmd_populate_kernel(mm, pmd, pte + PTRS_PER_PTE);
-        }
+        pmd_val(*pmd) = _SEGMENT_ENTRY + __pa(pte);
 }
 
+#define pmd_populate_kernel(mm, pmd, pte) pmd_populate(mm, pmd, pte)
+
 #define pmd_pgtable(pmd) \
         (pgtable_t)(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)
 
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 02ace3491c51..e4efacfe1b63 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -31,9 +31,8 @@
 #ifndef __ASSEMBLY__
 #include <linux/sched.h>
 #include <linux/mm_types.h>
-#include <asm/bitops.h>
 #include <asm/bug.h>
-#include <asm/processor.h>
+#include <asm/page.h>
 
 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
 extern void paging_init(void);
@@ -243,11 +242,13 @@ extern unsigned long VMALLOC_START;
 /* Software bits in the page table entry */
 #define _PAGE_SWT       0x001           /* SW pte type bit t */
 #define _PAGE_SWX       0x002           /* SW pte type bit x */
-#define _PAGE_SPECIAL   0x004           /* SW associated with special page */
+#define _PAGE_SWC       0x004           /* SW pte changed bit (for KVM) */
+#define _PAGE_SWR       0x008           /* SW pte referenced bit (for KVM) */
+#define _PAGE_SPECIAL   0x010           /* SW associated with special page */
 #define __HAVE_ARCH_PTE_SPECIAL
 
 /* Set of bits not changed in pte_modify */
-#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_SPECIAL)
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
 
 /* Six different types of pages. */
 #define _PAGE_TYPE_EMPTY        0x400
@@ -256,8 +257,6 @@ extern unsigned long VMALLOC_START;
 #define _PAGE_TYPE_FILE         0x601   /* bit 0x002 is used for offset !! */
 #define _PAGE_TYPE_RO           0x200
 #define _PAGE_TYPE_RW           0x000
-#define _PAGE_TYPE_EX_RO        0x202
-#define _PAGE_TYPE_EX_RW        0x002
 
 /*
  * Only four types for huge pages, using the invalid bit and protection bit
@@ -287,8 +286,6 @@ extern unsigned long VMALLOC_START;
  * _PAGE_TYPE_FILE      11?1   ->   11?1
  * _PAGE_TYPE_RO        0100   ->   1100
  * _PAGE_TYPE_RW        0000   ->   1000
- * _PAGE_TYPE_EX_RO     0110   ->   1110
- * _PAGE_TYPE_EX_RW     0010   ->   1010
  *
  * pte_none is true for bits combinations 1000, 1010, 1100, 1110
  * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
@@ -297,14 +294,17 @@ extern unsigned long VMALLOC_START;
  */
 
 /* Page status table bits for virtualization */
-#define RCP_PCL_BIT     55
-#define RCP_HR_BIT      54
-#define RCP_HC_BIT      53
-#define RCP_GR_BIT      50
-#define RCP_GC_BIT      49
-
-/* User dirty bit for KVM's migration feature */
-#define KVM_UD_BIT      47
+#define RCP_ACC_BITS    0xf000000000000000UL
+#define RCP_FP_BIT      0x0800000000000000UL
+#define RCP_PCL_BIT     0x0080000000000000UL
+#define RCP_HR_BIT      0x0040000000000000UL
+#define RCP_HC_BIT      0x0020000000000000UL
+#define RCP_GR_BIT      0x0004000000000000UL
+#define RCP_GC_BIT      0x0002000000000000UL
+
+/* User dirty / referenced bit for KVM's migration feature */
+#define KVM_UR_BIT      0x0000800000000000UL
+#define KVM_UC_BIT      0x0000400000000000UL
 
 #ifndef __s390x__
 
@@ -377,85 +377,54 @@ extern unsigned long VMALLOC_START;
 #define _ASCE_USER_BITS         (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
                                  _ASCE_ALT_EVENT)
 
-/* Bits int the storage key */
-#define _PAGE_CHANGED    0x02          /* HW changed bit                   */
-#define _PAGE_REFERENCED 0x04          /* HW referenced bit                */
-
 /*
  * Page protection definitions.
  */
 #define PAGE_NONE       __pgprot(_PAGE_TYPE_NONE)
 #define PAGE_RO         __pgprot(_PAGE_TYPE_RO)
 #define PAGE_RW         __pgprot(_PAGE_TYPE_RW)
-#define PAGE_EX_RO      __pgprot(_PAGE_TYPE_EX_RO)
-#define PAGE_EX_RW      __pgprot(_PAGE_TYPE_EX_RW)
 
 #define PAGE_KERNEL     PAGE_RW
 #define PAGE_COPY       PAGE_RO
 
 /*
- * Dependent on the EXEC_PROTECT option s390 can do execute protection.
- * Write permission always implies read permission. In theory with a
- * primary/secondary page table execute only can be implemented but
- * it would cost an additional bit in the pte to distinguish all the
- * different pte types. To avoid that execute permission currently
- * implies read permission as well.
+ * On s390 the page table entry has an invalid bit and a read-only bit.
+ * Read permission implies execute permission and write permission
+ * implies read permission.
  */
          /*xwr*/
 #define __P000  PAGE_NONE
 #define __P001  PAGE_RO
 #define __P010  PAGE_RO
 #define __P011  PAGE_RO
-#define __P100  PAGE_EX_RO
-#define __P101  PAGE_EX_RO
-#define __P110  PAGE_EX_RO
-#define __P111  PAGE_EX_RO
+#define __P100  PAGE_RO
+#define __P101  PAGE_RO
+#define __P110  PAGE_RO
+#define __P111  PAGE_RO
 
 #define __S000  PAGE_NONE
 #define __S001  PAGE_RO
 #define __S010  PAGE_RW
 #define __S011  PAGE_RW
-#define __S100  PAGE_EX_RO
-#define __S101  PAGE_EX_RO
-#define __S110  PAGE_EX_RW
-#define __S111  PAGE_EX_RW
-
-#ifndef __s390x__
-# define PxD_SHADOW_SHIFT       1
-#else /* __s390x__ */
-# define PxD_SHADOW_SHIFT       2
-#endif /* __s390x__ */
+#define __S100  PAGE_RO
+#define __S101  PAGE_RO
+#define __S110  PAGE_RW
+#define __S111  PAGE_RW
 
-static inline void *get_shadow_table(void *table)
+static inline int mm_exclusive(struct mm_struct *mm)
 {
-        unsigned long addr, offset;
-        struct page *page;
-
-        addr = (unsigned long) table;
-        offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
-        page = virt_to_page((void *)(addr ^ offset));
-        return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
+        return likely(mm == current->active_mm &&
+                      atomic_read(&mm->context.attach_count) <= 1);
 }
 
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
-                              pte_t *ptep, pte_t entry)
+static inline int mm_has_pgste(struct mm_struct *mm)
 {
-        *ptep = entry;
-        if (mm->context.noexec) {
-                if (!(pte_val(entry) & _PAGE_INVALID) &&
-                    (pte_val(entry) & _PAGE_SWX))
-                        pte_val(entry) |= _PAGE_RO;
-                else
-                        pte_val(entry) = _PAGE_TYPE_EMPTY;
-                ptep[PTRS_PER_PTE] = entry;
-        }
+#ifdef CONFIG_PGSTE
+        if (unlikely(mm->context.has_pgste))
+                return 1;
+#endif
+        return 0;
 }
-
 /*
  * pgd/pmd/pte query functions
  */
@@ -568,52 +537,127 @@ static inline int pte_special(pte_t pte)
 }
 
 #define __HAVE_ARCH_PTE_SAME
-#define pte_same(a,b)  (pte_val(a) == pte_val(b))
+static inline int pte_same(pte_t a, pte_t b)
+{
+        return pte_val(a) == pte_val(b);
+}
 
-static inline void rcp_lock(pte_t *ptep)
+static inline pgste_t pgste_get_lock(pte_t *ptep)
 {
+        unsigned long new = 0;
 #ifdef CONFIG_PGSTE
-        unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+        unsigned long old;
+
         preempt_disable();
-        while (test_and_set_bit(RCP_PCL_BIT, pgste))
-                ;
+        asm(
+                "       lg      %0,%2\n"
+                "0:     lgr     %1,%0\n"
+                "       nihh    %0,0xff7f\n"    /* clear RCP_PCL_BIT in old */
+                "       oihh    %1,0x0080\n"    /* set RCP_PCL_BIT in new */
+                "       csg     %0,%1,%2\n"
+                "       jl      0b\n"
+                : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
+                : "Q" (ptep[PTRS_PER_PTE]) : "cc");
 #endif
+        return __pgste(new);
 }
 
-static inline void rcp_unlock(pte_t *ptep)
+static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
-        unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
-        clear_bit(RCP_PCL_BIT, pgste);
+        asm(
+                "       nihh    %1,0xff7f\n"    /* clear RCP_PCL_BIT */
+                "       stg     %1,%0\n"
+                : "=Q" (ptep[PTRS_PER_PTE])
+                : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
         preempt_enable();
 #endif
 }
 
-/* forward declaration for SetPageUptodate in page-flags.h*/
-static inline void page_clear_dirty(struct page *page, int mapped);
-#include <linux/page-flags.h>
-
-static inline void ptep_rcp_copy(pte_t *ptep)
+static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
 {
 #ifdef CONFIG_PGSTE
-        struct page *page = virt_to_page(pte_val(*ptep));
-        unsigned int skey;
-        unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
-
-        skey = page_get_storage_key(page_to_phys(page));
-        if (skey & _PAGE_CHANGED) {
-                set_bit_simple(RCP_GC_BIT, pgste);
-                set_bit_simple(KVM_UD_BIT, pgste);
+        unsigned long address, bits;
+        unsigned char skey;
+
+        address = pte_val(*ptep) & PAGE_MASK;
+        skey = page_get_storage_key(address);
+        bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
+        /* Clear page changed & referenced bit in the storage key */
+        if (bits) {
+                skey ^= bits;
+                page_set_storage_key(address, skey, 1);
         }
-        if (skey & _PAGE_REFERENCED)
-                set_bit_simple(RCP_GR_BIT, pgste);
-        if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) {
-                SetPageDirty(page);
-                set_bit_simple(KVM_UD_BIT, pgste);
-        }
-        if (test_and_clear_bit_simple(RCP_HR_BIT, pgste))
-                SetPageReferenced(page);
+        /* Transfer page changed & referenced bit to guest bits in pgste */
+        pgste_val(pgste) |= bits << 48;         /* RCP_GR_BIT & RCP_GC_BIT */
+        /* Get host changed & referenced bits from pgste */
+        bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
+        /* Clear host bits in pgste. */
+        pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
+        pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
+        /* Copy page access key and fetch protection bit to pgste */
+        pgste_val(pgste) |=
+                (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
+        /* Transfer changed and referenced to kvm user bits */
+        pgste_val(pgste) |= bits << 45;         /* KVM_UR_BIT & KVM_UC_BIT */
+        /* Transfer changed & referenced to pte sofware bits */
+        pte_val(*ptep) |= bits << 1;            /* _PAGE_SWR & _PAGE_SWC */
 #endif
+        return pgste;
+
+}
+
+static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+        int young;
+
+        young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
+        /* Transfer page referenced bit to pte software bit (host view) */
+        if (young || (pgste_val(pgste) & RCP_HR_BIT))
+                pte_val(*ptep) |= _PAGE_SWR;
+        /* Clear host referenced bit in pgste. */
+        pgste_val(pgste) &= ~RCP_HR_BIT;
+        /* Transfer page referenced bit to guest bit in pgste */
+        pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */
+#endif
+        return pgste;
+
+}
+
+static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+        unsigned long address;
+        unsigned long okey, nkey;
+
+        address = pte_val(*ptep) & PAGE_MASK;
+        okey = nkey = page_get_storage_key(address);
+        nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
+        /* Set page access key and fetch protection bit from pgste */
+        nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
+        if (okey != nkey)
+                page_set_storage_key(address, nkey, 1);
+#endif
+}
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified.  Thus, the following
+ * hook is made available.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t entry)
+{
+        pgste_t pgste;
+
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_get_lock(ptep);
+                pgste_set_pte(ptep, pgste);
+                *ptep = entry;
+                pgste_set_unlock(ptep, pgste);
+        } else
+                *ptep = entry;
 }
 
 /*
@@ -627,19 +671,19 @@ static inline int pte_write(pte_t pte)
 
 static inline int pte_dirty(pte_t pte)
 {
-        /* A pte is neither clean nor dirty on s/390. The dirty bit
-         * is in the storage key. See page_test_and_clear_dirty for
-         * details.
-         */
+#ifdef CONFIG_PGSTE
+        if (pte_val(pte) & _PAGE_SWC)
+                return 1;
+#endif
         return 0;
 }
 
 static inline int pte_young(pte_t pte)
 {
-        /* A pte is neither young nor old on s/390. The young bit
-         * is in the storage key. See page_test_and_clear_young for
-         * details.
-         */
+#ifdef CONFIG_PGSTE
+        if (pte_val(pte) & _PAGE_SWR)
+                return 1;
+#endif
         return 0;
 }
 
@@ -647,64 +691,30 @@ static inline int pte_young(pte_t pte)
  * pgd/pmd/pte modification functions
  */
 
-#ifndef __s390x__
-
-#define pgd_clear(pgd)          do { } while (0)
-#define pud_clear(pud)          do { } while (0)
-
-#else /* __s390x__ */
-
-static inline void pgd_clear_kernel(pgd_t * pgd)
+static inline void pgd_clear(pgd_t *pgd)
 {
+#ifdef __s390x__
         if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
                 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
+#endif
 }
 
-static inline void pgd_clear(pgd_t * pgd)
-{
-        pgd_t *shadow = get_shadow_table(pgd);
-
-        pgd_clear_kernel(pgd);
-        if (shadow)
-                pgd_clear_kernel(shadow);
-}
-
-static inline void pud_clear_kernel(pud_t *pud)
+static inline void pud_clear(pud_t *pud)
 {
+#ifdef __s390x__
         if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
                 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
+#endif
 }
 
-static inline void pud_clear(pud_t *pud)
-{
-        pud_t *shadow = get_shadow_table(pud);
-
-        pud_clear_kernel(pud);
-        if (shadow)
-                pud_clear_kernel(shadow);
-}
-
-#endif /* __s390x__ */
-
-static inline void pmd_clear_kernel(pmd_t * pmdp)
+static inline void pmd_clear(pmd_t *pmdp)
 {
         pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
 }
 
-static inline void pmd_clear(pmd_t *pmd)
-{
-        pmd_t *shadow = get_shadow_table(pmd);
-
-        pmd_clear_kernel(pmd);
-        if (shadow)
-                pmd_clear_kernel(shadow);
-}
-
 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
         pte_val(*ptep) = _PAGE_TYPE_EMPTY;
-        if (mm->context.noexec)
-                pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
 }
 
 /*
@@ -734,35 +744,27 @@ static inline pte_t pte_mkwrite(pte_t pte)
 
 static inline pte_t pte_mkclean(pte_t pte)
 {
-        /* The only user of pte_mkclean is the fork() code.
-           We must *not* clear the *physical* page dirty bit
-           just because fork() wants to clear the dirty bit in
-           *one* of the page's mappings.  So we just do nothing. */
+#ifdef CONFIG_PGSTE
+        pte_val(pte) &= ~_PAGE_SWC;
+#endif
         return pte;
 }
 
 static inline pte_t pte_mkdirty(pte_t pte)
 {
-        /* We do not explicitly set the dirty bit because the
-         * sske instruction is slow. It is faster to let the
-         * next instruction set the dirty bit.
-         */
         return pte;
 }
 
 static inline pte_t pte_mkold(pte_t pte)
 {
-        /* S/390 doesn't keep its dirty/referenced bit in the pte.
-         * There is no point in clearing the real referenced bit.
-         */
+#ifdef CONFIG_PGSTE
+        pte_val(pte) &= ~_PAGE_SWR;
+#endif
         return pte;
 }
 
 static inline pte_t pte_mkyoung(pte_t pte)
 {
-        /* S/390 doesn't keep its dirty/referenced bit in the pte.
-         * There is no point in setting the real referenced bit.
-         */
         return pte;
 }
 
@@ -800,62 +802,60 @@ static inline pte_t pte_mkhuge(pte_t pte)
 }
 #endif
 
-#ifdef CONFIG_PGSTE
 /*
- * Get (and clear) the user dirty bit for a PTE.
+ * Get (and clear) the user dirty bit for a pte.
  */
-static inline int kvm_s390_test_and_clear_page_dirty(struct mm_struct *mm,
-                                                     pte_t *ptep)
+static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
+                                                 pte_t *ptep)
 {
-        int dirty;
-        unsigned long *pgste;
-        struct page *page;
-        unsigned int skey;
-
-        if (!mm->context.has_pgste)
-                return -EINVAL;
-        rcp_lock(ptep);
-        pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
-        page = virt_to_page(pte_val(*ptep));
-        skey = page_get_storage_key(page_to_phys(page));
-        if (skey & _PAGE_CHANGED) {
-                set_bit_simple(RCP_GC_BIT, pgste);
-                set_bit_simple(KVM_UD_BIT, pgste);
+        pgste_t pgste;
+        int dirty = 0;
+
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_get_lock(ptep);
+                pgste = pgste_update_all(ptep, pgste);
+                dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
+                pgste_val(pgste) &= ~KVM_UC_BIT;
+                pgste_set_unlock(ptep, pgste);
+                return dirty;
         }
-        if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) {
-                SetPageDirty(page);
-                set_bit_simple(KVM_UD_BIT, pgste);
-        }
-        dirty = test_and_clear_bit_simple(KVM_UD_BIT, pgste);
-        if (skey & _PAGE_CHANGED)
-                page_clear_dirty(page, 1);
-        rcp_unlock(ptep);
         return dirty;
 }
-#endif
+
+/*
+ * Get (and clear) the user referenced bit for a pte.
+ */
+static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
+                                                 pte_t *ptep)
+{
+        pgste_t pgste;
+        int young = 0;
+
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_get_lock(ptep);
+                pgste = pgste_update_young(ptep, pgste);
+                young = !!(pgste_val(pgste) & KVM_UR_BIT);
+                pgste_val(pgste) &= ~KVM_UR_BIT;
+                pgste_set_unlock(ptep, pgste);
+        }
+        return young;
+}
 
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
                                             unsigned long addr, pte_t *ptep)
 {
-#ifdef CONFIG_PGSTE
-        unsigned long physpage;
-        int young;
-        unsigned long *pgste;
+        pgste_t pgste;
+        pte_t pte;
 
-        if (!vma->vm_mm->context.has_pgste)
-                return 0;
-        physpage = pte_val(*ptep) & PAGE_MASK;
-        pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
-
-        young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0);
-        rcp_lock(ptep);
-        if (young)
-                set_bit_simple(RCP_GR_BIT, pgste);
-        young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste);
-        rcp_unlock(ptep);
-        return young;
-#endif
+        if (mm_has_pgste(vma->vm_mm)) {
+                pgste = pgste_get_lock(ptep);
+                pgste = pgste_update_young(ptep, pgste);
+                pte = *ptep;
+                *ptep = pte_mkold(pte);
+                pgste_set_unlock(ptep, pgste);
+                return pte_young(pte);
+        }
         return 0;
 }
 
@@ -867,10 +867,7 @@ static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
          * On s390 reference bits are in storage key and never in TLB
          * With virtualization we handle the reference bit, without we
          * we can simply return */
-#ifdef CONFIG_PGSTE
         return ptep_test_and_clear_young(vma, address, ptep);
-#endif
-        return 0;
 }
 
 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
@@ -890,25 +887,6 @@ static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
         }
 }
 
-static inline void ptep_invalidate(struct mm_struct *mm,
-                                   unsigned long address, pte_t *ptep)
-{
-        if (mm->context.has_pgste) {
-                rcp_lock(ptep);
-                __ptep_ipte(address, ptep);
-                ptep_rcp_copy(ptep);
-                pte_val(*ptep) = _PAGE_TYPE_EMPTY;
-                rcp_unlock(ptep);
-                return;
-        }
-        __ptep_ipte(address, ptep);
-        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
-        if (mm->context.noexec) {
-                __ptep_ipte(address, ptep + PTRS_PER_PTE);
-                pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY;
-        }
-}
-
 /*
  * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
  * both clear the TLB for the unmapped pte. The reason is that
@@ -923,24 +901,72 @@ static inline void ptep_invalidate(struct mm_struct *mm,
  * is a nop.
  */
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define ptep_get_and_clear(__mm, __address, __ptep)                     \
-({                                                                      \
-        pte_t __pte = *(__ptep);                                        \
-        (__mm)->context.flush_mm = 1;                                   \
-        if (atomic_read(&(__mm)->context.attach_count) > 1 ||           \
-            (__mm) != current->active_mm)                               \
-                ptep_invalidate(__mm, __address, __ptep);               \
-        else                                                            \
-                pte_clear((__mm), (__address), (__ptep));               \
-        __pte;                                                          \
-})
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+                                       unsigned long address, pte_t *ptep)
+{
+        pgste_t pgste;
+        pte_t pte;
+
+        mm->context.flush_mm = 1;
+        if (mm_has_pgste(mm))
+                pgste = pgste_get_lock(ptep);
+
+        pte = *ptep;
+        if (!mm_exclusive(mm))
+                __ptep_ipte(address, ptep);
+        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_update_all(&pte, pgste);
+                pgste_set_unlock(ptep, pgste);
+        }
+        return pte;
+}
+
+#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
+static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
+                                           unsigned long address,
+                                           pte_t *ptep)
+{
+        pte_t pte;
+
+        mm->context.flush_mm = 1;
+        if (mm_has_pgste(mm))
+                pgste_get_lock(ptep);
+
+        pte = *ptep;
+        if (!mm_exclusive(mm))
+                __ptep_ipte(address, ptep);
+        return pte;
+}
+
+static inline void ptep_modify_prot_commit(struct mm_struct *mm,
+                                           unsigned long address,
+                                           pte_t *ptep, pte_t pte)
+{
+        *ptep = pte;
+        if (mm_has_pgste(mm))
+                pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
+}
 
 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
                                      unsigned long address, pte_t *ptep)
 {
-        pte_t pte = *ptep;
-        ptep_invalidate(vma->vm_mm, address, ptep);
+        pgste_t pgste;
+        pte_t pte;
+
+        if (mm_has_pgste(vma->vm_mm))
+                pgste = pgste_get_lock(ptep);
+
+        pte = *ptep;
+        __ptep_ipte(address, ptep);
+        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+
+        if (mm_has_pgste(vma->vm_mm)) {
+                pgste = pgste_update_all(&pte, pgste);
+                pgste_set_unlock(ptep, pgste);
+        }
         return pte;
 }
 
@@ -953,76 +979,67 @@ static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
  */
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
-                                            unsigned long addr,
+                                            unsigned long address,
                                             pte_t *ptep, int full)
 {
-        pte_t pte = *ptep;
+        pgste_t pgste;
+        pte_t pte;
+
+        if (mm_has_pgste(mm))
+                pgste = pgste_get_lock(ptep);
+
+        pte = *ptep;
+        if (!full)
+                __ptep_ipte(address, ptep);
+        pte_val(*ptep) = _PAGE_TYPE_EMPTY;
 
-        if (full)
-                pte_clear(mm, addr, ptep);
-        else
-                ptep_invalidate(mm, addr, ptep);
+        if (mm_has_pgste(mm)) {
+                pgste = pgste_update_all(&pte, pgste);
+                pgste_set_unlock(ptep, pgste);
+        }
         return pte;
 }
 
 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define ptep_set_wrprotect(__mm, __addr, __ptep)                        \
-({                                                                      \
-        pte_t __pte = *(__ptep);                                        \
-        if (pte_write(__pte)) {                                         \
-                (__mm)->context.flush_mm = 1;                           \
-                if (atomic_read(&(__mm)->context.attach_count) > 1 ||   \
-                    (__mm) != current->active_mm)                       \
-                        ptep_invalidate(__mm, __addr, __ptep);          \
-                set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
-        }                                                               \
-})
+static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
+                                       unsigned long address, pte_t *ptep)
+{
+        pgste_t pgste;
+        pte_t pte = *ptep;
 
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-#define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty)  \
-({                                                                      \
-        int __changed = !pte_same(*(__ptep), __entry);                  \
-        if (__changed) {                                                \
-                ptep_invalidate((__vma)->vm_mm, __addr, __ptep);        \
-                set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry);    \
-        }                                                               \
-        __changed;                                                      \
-})
+        if (pte_write(pte)) {
+                mm->context.flush_mm = 1;
+                if (mm_has_pgste(mm))
+                        pgste = pgste_get_lock(ptep);
 
-/*
- * Test and clear dirty bit in storage key.
- * We can't clear the changed bit atomically. This is a potential
- * race against modification of the referenced bit. This function
- * should therefore only be called if it is not mapped in any
- * address space.
- */
-#define __HAVE_ARCH_PAGE_TEST_DIRTY
-static inline int page_test_dirty(struct page *page)
-{
-        return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
-}
+                if (!mm_exclusive(mm))
+                        __ptep_ipte(address, ptep);
+                *ptep = pte_wrprotect(pte);
 
-#define __HAVE_ARCH_PAGE_CLEAR_DIRTY
-static inline void page_clear_dirty(struct page *page, int mapped)
-{
-        page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY, mapped);
+                if (mm_has_pgste(mm))
+                        pgste_set_unlock(ptep, pgste);
+        }
+        return pte;
 }
 
-/*
- * Test and clear referenced bit in storage key.
- */
-#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
-static inline int page_test_and_clear_young(struct page *page)
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline int ptep_set_access_flags(struct vm_area_struct *vma,
+                                        unsigned long address, pte_t *ptep,
+                                        pte_t entry, int dirty)
 {
-        unsigned long physpage = page_to_phys(page);
-        int ccode;
-
-        asm volatile(
-                "       rrbe    0,%1\n"
-                "       ipm     %0\n"
-                "       srl     %0,28\n"
-                : "=d" (ccode) : "a" (physpage) : "cc" );
-        return ccode & 2;
+        pgste_t pgste;
+
+        if (pte_same(*ptep, entry))
+                return 0;
+        if (mm_has_pgste(vma->vm_mm))
+                pgste = pgste_get_lock(ptep);
+
+        __ptep_ipte(address, ptep);
+        *ptep = entry;
+
+        if (mm_has_pgste(vma->vm_mm))
+                pgste_set_unlock(ptep, pgste);
+        return 1;
 }
 
 /*
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 2c79b6416271..1300c3025334 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -84,6 +84,7 @@ struct thread_struct {
         struct per_event per_event;     /* Cause of the last PER trap */
         /* pfault_wait is used to block the process on a pfault event */
         unsigned long pfault_wait;
+        struct list_head list;
 };
 
 typedef struct thread_struct thread_struct;
diff --git a/arch/s390/include/asm/s390_ext.h b/arch/s390/include/asm/s390_ext.h
deleted file mode 100644
index 080876d5f196..000000000000
--- a/arch/s390/include/asm/s390_ext.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- *    Copyright IBM Corp. 1999,2010
- *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
- *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
- */
-
-#ifndef _S390_EXTINT_H
-#define _S390_EXTINT_H
-
-#include <linux/types.h>
-
-typedef void (*ext_int_handler_t)(unsigned int, unsigned int, unsigned long);
-
-int register_external_interrupt(__u16 code, ext_int_handler_t handler);
-int unregister_external_interrupt(__u16 code, ext_int_handler_t handler);
-
-#endif /* _S390_EXTINT_H */
diff --git a/arch/s390/include/asm/suspend.h b/arch/s390/include/asm/suspend.h
deleted file mode 100644
index dc75c616eafe..000000000000
--- a/arch/s390/include/asm/suspend.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __ASM_S390_SUSPEND_H
-#define __ASM_S390_SUSPEND_H
-
-static inline int arch_prepare_suspend(void)
-{
-        return 0;
-}
-
-#endif
-
diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h
index 9074a54c4d10..77eee5477a52 100644
--- a/arch/s390/include/asm/tlb.h
+++ b/arch/s390/include/asm/tlb.h
@@ -29,65 +29,77 @@
 #include <asm/smp.h>
 #include <asm/tlbflush.h>
 
-#ifndef CONFIG_SMP
-#define TLB_NR_PTRS     1
-#else
-#define TLB_NR_PTRS     508
-#endif
-
 struct mmu_gather {
         struct mm_struct *mm;
         unsigned int fullmm;
         unsigned int nr_ptes;
         unsigned int nr_pxds;
-        void *array[TLB_NR_PTRS];
+        unsigned int max;
+        void **array;
+        void *local[8];
 };
 
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
-static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
-                                                unsigned int full_mm_flush)
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
 {
-        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
+        unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
 
+        if (addr) {
+                tlb->array = (void *) addr;
+                tlb->max = PAGE_SIZE / sizeof(void *);
+        }
+}
+
+static inline void tlb_gather_mmu(struct mmu_gather *tlb,
+                                  struct mm_struct *mm,
+                                  unsigned int full_mm_flush)
+{
         tlb->mm = mm;
+        tlb->max = ARRAY_SIZE(tlb->local);
+        tlb->array = tlb->local;
         tlb->fullmm = full_mm_flush;
-        tlb->nr_ptes = 0;
-        tlb->nr_pxds = TLB_NR_PTRS;
         if (tlb->fullmm)
                 __tlb_flush_mm(mm);
-        return tlb;
+        else
+                __tlb_alloc_page(tlb);
+        tlb->nr_ptes = 0;
+        tlb->nr_pxds = tlb->max;
 }
 
-static inline void tlb_flush_mmu(struct mmu_gather *tlb,
-                                 unsigned long start, unsigned long end)
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
 {
-        if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS))
+        if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < tlb->max))
                 __tlb_flush_mm(tlb->mm);
         while (tlb->nr_ptes > 0)
                 page_table_free_rcu(tlb->mm, tlb->array[--tlb->nr_ptes]);
-        while (tlb->nr_pxds < TLB_NR_PTRS)
+        while (tlb->nr_pxds < tlb->max)
                 crst_table_free_rcu(tlb->mm, tlb->array[tlb->nr_pxds++]);
 }
 
 static inline void tlb_finish_mmu(struct mmu_gather *tlb,
                                   unsigned long start, unsigned long end)
 {
-        tlb_flush_mmu(tlb, start, end);
+        tlb_flush_mmu(tlb);
 
         rcu_table_freelist_finish();
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
 
-        put_cpu_var(mmu_gathers);
+        if (tlb->array != tlb->local)
+                free_pages((unsigned long) tlb->array, 0);
 }
 
 /*
  * Release the page cache reference for a pte removed by
- * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
+ * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
  * has already been freed, so just do free_page_and_swap_cache.
  */
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        free_page_and_swap_cache(page);
+        return 1; /* avoid calling tlb_flush_mmu */
+}
+
 static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
         free_page_and_swap_cache(page);
@@ -103,7 +115,7 @@ static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
         if (!tlb->fullmm) {
                 tlb->array[tlb->nr_ptes++] = pte;
                 if (tlb->nr_ptes >= tlb->nr_pxds)
-                        tlb_flush_mmu(tlb, 0, 0);
+                        tlb_flush_mmu(tlb);
         } else
                 page_table_free(tlb->mm, (unsigned long *) pte);
 }
@@ -124,7 +136,7 @@ static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
         if (!tlb->fullmm) {
                 tlb->array[--tlb->nr_pxds] = pmd;
                 if (tlb->nr_ptes >= tlb->nr_pxds)
-                        tlb_flush_mmu(tlb, 0, 0);
+                        tlb_flush_mmu(tlb);
         } else
                 crst_table_free(tlb->mm, (unsigned long *) pmd);
 #endif
@@ -146,7 +158,7 @@ static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
         if (!tlb->fullmm) {
                 tlb->array[--tlb->nr_pxds] = pud;
                 if (tlb->nr_ptes >= tlb->nr_pxds)
-                        tlb_flush_mmu(tlb, 0, 0);
+                        tlb_flush_mmu(tlb);
         } else
                 crst_table_free(tlb->mm, (unsigned long *) pud);
 #endif
diff --git a/arch/s390/include/asm/tlbflush.h b/arch/s390/include/asm/tlbflush.h
index 29d5d6d4becc..b7a4f2eb0057 100644
--- a/arch/s390/include/asm/tlbflush.h
+++ b/arch/s390/include/asm/tlbflush.h
@@ -50,7 +50,7 @@ static inline void __tlb_flush_full(struct mm_struct *mm)
         /*
          * If the process only ran on the local cpu, do a local flush.
          */
-        local_cpumask = cpumask_of_cpu(smp_processor_id());
+        cpumask_copy(&local_cpumask, cpumask_of(smp_processor_id()));
         if (cpumask_equal(mm_cpumask(mm), &local_cpumask))
                 __tlb_flush_local();
         else
@@ -80,16 +80,11 @@ static inline void __tlb_flush_mm(struct mm_struct * mm)
          * on all cpus instead of doing a local flush if the mm
          * only ran on the local cpu.
          */
-        if (MACHINE_HAS_IDTE) {
-                if (mm->context.noexec)
-                        __tlb_flush_idte((unsigned long)
-                                         get_shadow_table(mm->pgd) |
-                                         mm->context.asce_bits);
+        if (MACHINE_HAS_IDTE)
                 __tlb_flush_idte((unsigned long) mm->pgd |
                                  mm->context.asce_bits);
-                return;
-        }
-        __tlb_flush_full(mm);
+        else
+                __tlb_flush_full(mm);
 }
 
 static inline void __tlb_flush_mm_cond(struct mm_struct * mm)
diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h
index c5338834ddbd..005d77d8ae2a 100644
--- a/arch/s390/include/asm/topology.h
+++ b/arch/s390/include/asm/topology.h
@@ -7,7 +7,7 @@
 extern unsigned char cpu_core_id[NR_CPUS];
 extern cpumask_t cpu_core_map[NR_CPUS];
 
-static inline const struct cpumask *cpu_coregroup_mask(unsigned int cpu)
+static inline const struct cpumask *cpu_coregroup_mask(int cpu)
 {
         return &cpu_core_map[cpu];
 }
@@ -21,7 +21,7 @@ static inline const struct cpumask *cpu_coregroup_mask(unsigned int cpu)
 extern unsigned char cpu_book_id[NR_CPUS];
 extern cpumask_t cpu_book_map[NR_CPUS];
 
-static inline const struct cpumask *cpu_book_mask(unsigned int cpu)
+static inline const struct cpumask *cpu_book_mask(int cpu)
 {
         return &cpu_book_map[cpu];
 }
diff --git a/arch/s390/include/asm/uaccess.h b/arch/s390/include/asm/uaccess.h
index 2d9ea11f919a..2b23885e81e9 100644
--- a/arch/s390/include/asm/uaccess.h
+++ b/arch/s390/include/asm/uaccess.h
@@ -49,12 +49,13 @@
 
 #define segment_eq(a,b) ((a).ar4 == (b).ar4)
 
+#define __access_ok(addr, size) \
+({                              \
+        __chk_user_ptr(addr);   \
+        1;                      \
+})
 
-static inline int __access_ok(const void __user *addr, unsigned long size)
-{
-        return 1;
-}
-#define access_ok(type,addr,size) __access_ok(addr,size)
+#define access_ok(type, addr, size) __access_ok(addr, size)
 
 /*
  * The exception table consists of pairs of addresses: the first is the
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index e82152572377..404bdb9671b4 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -276,7 +276,8 @@
 #define __NR_open_by_handle_at  336
 #define __NR_clock_adjtime      337
 #define __NR_syncfs             338
-#define NR_syscalls 339
+#define __NR_setns              339
+#define NR_syscalls 340
 
 /* 
  * There are some system calls that are not present on 64 bit, some
@@ -385,6 +386,7 @@
 
 /* Ignore system calls that are also reachable via sys_socket */
 #define __IGNORE_recvmmsg
+#define __IGNORE_sendmmsg
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index 5ff15dacb571..df3732249baa 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -20,10 +20,10 @@ CFLAGS_ptrace.o		+= -DUTS_MACHINE='"$(UTS_MACHINE)"'
 
 CFLAGS_sysinfo.o += -Iinclude/math-emu -Iarch/s390/math-emu -w
 
-obj-y   :=  bitmap.o traps.o time.o process.o base.o early.o setup.o \
-            processor.o sys_s390.o ptrace.o signal.o cpcmd.o ebcdic.o \
-            s390_ext.o debug.o irq.o ipl.o dis.o diag.o mem_detect.o \
-            vdso.o vtime.o sysinfo.o nmi.o sclp.o jump_label.o
+obj-y   :=  bitmap.o traps.o time.o process.o base.o early.o setup.o vtime.o \
+            processor.o sys_s390.o ptrace.o signal.o cpcmd.o ebcdic.o nmi.o \
+            debug.o irq.o ipl.o dis.o diag.o mem_detect.o sclp.o vdso.o \
+            sysinfo.o jump_label.o
 
 obj-y   += $(if $(CONFIG_64BIT),entry64.o,entry.o)
 obj-y   += $(if $(CONFIG_64BIT),reipl64.o,reipl.o)
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index fe03c140002a..edfbd17d7082 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -124,13 +124,11 @@ int main(void)
         DEFINE(__LC_LAST_UPDATE_TIMER, offsetof(struct _lowcore, last_update_timer));
         DEFINE(__LC_LAST_UPDATE_CLOCK, offsetof(struct _lowcore, last_update_clock));
         DEFINE(__LC_CURRENT, offsetof(struct _lowcore, current_task));
+        DEFINE(__LC_CURRENT_PID, offsetof(struct _lowcore, current_pid));
         DEFINE(__LC_THREAD_INFO, offsetof(struct _lowcore, thread_info));
         DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
         DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
         DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
-        DEFINE(__LC_KERNEL_ASCE, offsetof(struct _lowcore, kernel_asce));
-        DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
-        DEFINE(__LC_USER_EXEC_ASCE, offsetof(struct _lowcore, user_exec_asce));
         DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
         DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
         DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
diff --git a/arch/s390/kernel/compat_wrapper.S b/arch/s390/kernel/compat_wrapper.S
index 1dc96ea08fa8..1f5eb789c3a7 100644
--- a/arch/s390/kernel/compat_wrapper.S
+++ b/arch/s390/kernel/compat_wrapper.S
@@ -1904,3 +1904,9 @@ compat_sys_clock_adjtime_wrapper:
 sys_syncfs_wrapper:
         lgfr    %r2,%r2                 # int
         jg      sys_syncfs
+
+        .globl  sys_setns_wrapper
+sys_setns_wrapper:
+        lgfr    %r2,%r2                 # int
+        lgfr    %r3,%r3                 # int
+        jg      sys_setns
diff --git a/arch/s390/kernel/dis.c b/arch/s390/kernel/dis.c
index 3d4a78fc1adc..1ca3d1d6a86c 100644
--- a/arch/s390/kernel/dis.c
+++ b/arch/s390/kernel/dis.c
@@ -30,9 +30,9 @@
 #include <asm/atomic.h>
 #include <asm/mathemu.h>
 #include <asm/cpcmd.h>
-#include <asm/s390_ext.h>
 #include <asm/lowcore.h>
 #include <asm/debug.h>
+#include <asm/irq.h>
 
 #ifndef CONFIG_64BIT
 #define ONELONG "%08lx: "
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 1b67fc6ebdc2..0476174dfff5 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -212,6 +212,7 @@ __switch_to:
         lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
         lm      %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
         st      %r3,__LC_CURRENT                # store task struct of next
+        mvc     __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
         st      %r5,__LC_THREAD_INFO            # store thread info of next
         ahi     %r5,STACK_SIZE                  # end of kernel stack of next
         st      %r5,__LC_KERNEL_STACK           # store end of kernel stack
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 9fd864563499..d61967e2eab0 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -220,6 +220,7 @@ __switch_to:
         lctl    %c4,%c4,__TASK_pid(%r3)         # load pid to control reg. 4
         lmg     %r6,%r15,__SF_GPRS(%r15)        # load gprs of next task
         stg     %r3,__LC_CURRENT                # store task struct of next
+        mvc     __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next
         stg     %r5,__LC_THREAD_INFO            # store thread info of next
         aghi    %r5,STACK_SIZE                  # end of kernel stack of next
         stg     %r5,__LC_KERNEL_STACK           # store end of kernel stack
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index ea5099c9709c..e3264f6a9720 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -1,19 +1,28 @@
 /*
- *    Copyright IBM Corp. 2004,2010
- *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
- *               Thomas Spatzier (tspat@de.ibm.com)
+ *    Copyright IBM Corp. 2004,2011
+ *    Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Holger Smolinski <Holger.Smolinski@de.ibm.com>,
+ *               Thomas Spatzier <tspat@de.ibm.com>,
  *
  * This file contains interrupt related functions.
  */
 
-#include <linux/module.h>
-#include <linux/kernel.h>
 #include <linux/kernel_stat.h>
 #include <linux/interrupt.h>
 #include <linux/seq_file.h>
-#include <linux/cpu.h>
 #include <linux/proc_fs.h>
 #include <linux/profile.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/ftrace.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/cpu.h>
+#include <asm/irq_regs.h>
+#include <asm/cputime.h>
+#include <asm/lowcore.h>
+#include <asm/irq.h>
+#include "entry.h"
 
 struct irq_class {
         char *name;
@@ -32,6 +41,7 @@ static const struct irq_class intrclass_names[] = {
         {.name = "VRT", .desc = "[EXT] Virtio" },
         {.name = "SCP", .desc = "[EXT] Service Call" },
         {.name = "IUC", .desc = "[EXT] IUCV" },
+        {.name = "CPM", .desc = "[EXT] CPU Measurement" },
         {.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt" },
         {.name = "QDI", .desc = "[I/O] QDIO Interrupt" },
         {.name = "DAS", .desc = "[I/O] DASD" },
@@ -81,8 +91,7 @@ int show_interrupts(struct seq_file *p, void *v)
  * For compatibilty only. S/390 specific setup of interrupts et al. is done
  * much later in init_channel_subsystem().
  */
-void __init
-init_IRQ(void)
+void __init init_IRQ(void)
 {
         /* nothing... */
 }
@@ -133,3 +142,116 @@ void init_irq_proc(void)
         create_prof_cpu_mask(root_irq_dir);
 }
 #endif
+
+/*
+ * ext_int_hash[index] is the start of the list for all external interrupts
+ * that hash to this index. With the current set of external interrupts
+ * (0x1202 external call, 0x1004 cpu timer, 0x2401 hwc console, 0x4000
+ * iucv and 0x2603 pfault) this is always the first element.
+ */
+
+struct ext_int_info {
+        struct ext_int_info *next;
+        ext_int_handler_t handler;
+        u16 code;
+};
+
+static struct ext_int_info *ext_int_hash[256];
+
+static inline int ext_hash(u16 code)
+{
+        return (code + (code >> 9)) & 0xff;
+}
+
+int register_external_interrupt(u16 code, ext_int_handler_t handler)
+{
+        struct ext_int_info *p;
+        int index;
+
+        p = kmalloc(sizeof(*p), GFP_ATOMIC);
+        if (!p)
+                return -ENOMEM;
+        p->code = code;
+        p->handler = handler;
+        index = ext_hash(code);
+        p->next = ext_int_hash[index];
+        ext_int_hash[index] = p;
+        return 0;
+}
+EXPORT_SYMBOL(register_external_interrupt);
+
+int unregister_external_interrupt(u16 code, ext_int_handler_t handler)
+{
+        struct ext_int_info *p, *q;
+        int index;
+
+        index = ext_hash(code);
+        q = NULL;
+        p = ext_int_hash[index];
+        while (p) {
+                if (p->code == code && p->handler == handler)
+                        break;
+                q = p;
+                p = p->next;
+        }
+        if (!p)
+                return -ENOENT;
+        if (q)
+                q->next = p->next;
+        else
+                ext_int_hash[index] = p->next;
+        kfree(p);
+        return 0;
+}
+EXPORT_SYMBOL(unregister_external_interrupt);
+
+void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code,
+                           unsigned int param32, unsigned long param64)
+{
+        struct pt_regs *old_regs;
+        unsigned short code;
+        struct ext_int_info *p;
+        int index;
+
+        code = (unsigned short) ext_int_code;
+        old_regs = set_irq_regs(regs);
+        s390_idle_check(regs, S390_lowcore.int_clock,
+                        S390_lowcore.async_enter_timer);
+        irq_enter();
+        if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
+                /* Serve timer interrupts first. */
+                clock_comparator_work();
+        kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++;
+        if (code != 0x1004)
+                __get_cpu_var(s390_idle).nohz_delay = 1;
+        index = ext_hash(code);
+        for (p = ext_int_hash[index]; p; p = p->next) {
+                if (likely(p->code == code))
+                        p->handler(ext_int_code, param32, param64);
+        }
+        irq_exit();
+        set_irq_regs(old_regs);
+}
+
+static DEFINE_SPINLOCK(sc_irq_lock);
+static int sc_irq_refcount;
+
+void service_subclass_irq_register(void)
+{
+        spin_lock(&sc_irq_lock);
+        if (!sc_irq_refcount)
+                ctl_set_bit(0, 9);
+        sc_irq_refcount++;
+        spin_unlock(&sc_irq_lock);
+}
+EXPORT_SYMBOL(service_subclass_irq_register);
+
+void service_subclass_irq_unregister(void)
+{
+        spin_lock(&sc_irq_lock);
+        sc_irq_refcount--;
+        if (!sc_irq_refcount)
+                ctl_clear_bit(0, 9);
+        spin_unlock(&sc_irq_lock);
+}
+EXPORT_SYMBOL(service_subclass_irq_unregister);
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index a895e69379f7..541a7509faeb 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -9,41 +9,26 @@
 
 #include <linux/compiler.h>
 #include <linux/cpu.h>
-#include <linux/errno.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
-#include <linux/fs.h>
 #include <linux/smp.h>
-#include <linux/stddef.h>
 #include <linux/slab.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/vmalloc.h>
-#include <linux/user.h>
 #include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/reboot.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/notifier.h>
 #include <linux/tick.h>
-#include <linux/elfcore.h>
-#include <linux/kernel_stat.h>
 #include <linux/personality.h>
 #include <linux/syscalls.h>
 #include <linux/compat.h>
 #include <linux/kprobes.h>
 #include <linux/random.h>
-#include <asm/compat.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
+#include <linux/module.h>
 #include <asm/system.h>
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/irq.h>
 #include <asm/timer.h>
 #include <asm/nmi.h>
+#include <asm/compat.h>
 #include <asm/smp.h>
 #include "entry.h"
 
diff --git a/arch/s390/kernel/s390_ext.c b/arch/s390/kernel/s390_ext.c
deleted file mode 100644
index 185029919c4d..000000000000
--- a/arch/s390/kernel/s390_ext.c
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- *    Copyright IBM Corp. 1999,2010
- *    Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
- *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
- */
-
-#include <linux/kernel_stat.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/ftrace.h>
-#include <linux/errno.h>
-#include <linux/slab.h>
-#include <asm/s390_ext.h>
-#include <asm/irq_regs.h>
-#include <asm/cputime.h>
-#include <asm/lowcore.h>
-#include <asm/irq.h>
-#include "entry.h"
-
-struct ext_int_info {
-        struct ext_int_info *next;
-        ext_int_handler_t handler;
-        __u16 code;
-};
-
-/*
- * ext_int_hash[index] is the start of the list for all external interrupts
- * that hash to this index. With the current set of external interrupts 
- * (0x1202 external call, 0x1004 cpu timer, 0x2401 hwc console, 0x4000
- * iucv and 0x2603 pfault) this is always the first element. 
- */
-static struct ext_int_info *ext_int_hash[256];
-
-static inline int ext_hash(__u16 code)
-{
-        return (code + (code >> 9)) & 0xff;
-}
-
-int register_external_interrupt(__u16 code, ext_int_handler_t handler)
-{
-        struct ext_int_info *p;
-        int index;
-
-        p = kmalloc(sizeof(*p), GFP_ATOMIC);
-        if (!p)
-                return -ENOMEM;
-        p->code = code;
-        p->handler = handler;
-        index = ext_hash(code);
-        p->next = ext_int_hash[index];
-        ext_int_hash[index] = p;
-        return 0;
-}
-EXPORT_SYMBOL(register_external_interrupt);
-
-int unregister_external_interrupt(__u16 code, ext_int_handler_t handler)
-{
-        struct ext_int_info *p, *q;
-        int index;
-
-        index = ext_hash(code);
-        q = NULL;
-        p = ext_int_hash[index];
-        while (p) {
-                if (p->code == code && p->handler == handler)
-                        break;
-                q = p;
-                p = p->next;
-        }
-        if (!p)
-                return -ENOENT;
-        if (q)
-                q->next = p->next;
-        else
-                ext_int_hash[index] = p->next;
-        kfree(p);
-        return 0;
-}
-EXPORT_SYMBOL(unregister_external_interrupt);
-
-void __irq_entry do_extint(struct pt_regs *regs, unsigned int ext_int_code,
-                           unsigned int param32, unsigned long param64)
-{
-        struct pt_regs *old_regs;
-        unsigned short code;
-        struct ext_int_info *p;
-        int index;
-
-        code = (unsigned short) ext_int_code;
-        old_regs = set_irq_regs(regs);
-        s390_idle_check(regs, S390_lowcore.int_clock,
-                        S390_lowcore.async_enter_timer);
-        irq_enter();
-        if (S390_lowcore.int_clock >= S390_lowcore.clock_comparator)
-                /* Serve timer interrupts first. */
-                clock_comparator_work();
-        kstat_cpu(smp_processor_id()).irqs[EXTERNAL_INTERRUPT]++;
-        if (code != 0x1004)
-                __get_cpu_var(s390_idle).nohz_delay = 1;
-        index = ext_hash(code);
-        for (p = ext_int_hash[index]; p; p = p->next) {
-                if (likely(p->code == code))
-                        p->handler(ext_int_code, param32, param64);
-        }
-        irq_exit();
-        set_irq_regs(old_regs);
-}
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index f5434d1ecb31..0c35dee10b00 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -305,8 +305,7 @@ static int set_amode_and_uaccess(unsigned long user_amode,
  */
 static int __init early_parse_switch_amode(char *p)
 {
-        if (user_mode != SECONDARY_SPACE_MODE)
-                user_mode = PRIMARY_SPACE_MODE;
+        user_mode = PRIMARY_SPACE_MODE;
         return 0;
 }
 early_param("switch_amode", early_parse_switch_amode);
@@ -315,10 +314,6 @@ static int __init early_parse_user_mode(char *p)
 {
         if (p && strcmp(p, "primary") == 0)
                 user_mode = PRIMARY_SPACE_MODE;
-#ifdef CONFIG_S390_EXEC_PROTECT
-        else if (p && strcmp(p, "secondary") == 0)
-                user_mode = SECONDARY_SPACE_MODE;
-#endif
         else if (!p || strcmp(p, "home") == 0)
                 user_mode = HOME_SPACE_MODE;
         else
@@ -327,31 +322,9 @@ static int __init early_parse_user_mode(char *p)
 }
 early_param("user_mode", early_parse_user_mode);
 
-#ifdef CONFIG_S390_EXEC_PROTECT
-/*
- * Enable execute protection?
- */
-static int __init early_parse_noexec(char *p)
-{
-        if (!strncmp(p, "off", 3))
-                return 0;
-        user_mode = SECONDARY_SPACE_MODE;
-        return 0;
-}
-early_param("noexec", early_parse_noexec);
-#endif /* CONFIG_S390_EXEC_PROTECT */
-
 static void setup_addressing_mode(void)
 {
-        if (user_mode == SECONDARY_SPACE_MODE) {
-                if (set_amode_and_uaccess(PSW_ASC_SECONDARY,
-                                          PSW32_ASC_SECONDARY))
-                        pr_info("Execute protection active, "
-                                "mvcos available\n");
-                else
-                        pr_info("Execute protection active, "
-                                "mvcos not available\n");
-        } else if (user_mode == PRIMARY_SPACE_MODE) {
+        if (user_mode == PRIMARY_SPACE_MODE) {
                 if (set_amode_and_uaccess(PSW_ASC_PRIMARY, PSW32_ASC_PRIMARY))
                         pr_info("Address spaces switched, "
                                 "mvcos available\n");
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 63c7d9ff220d..52420d2785b3 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -44,7 +44,6 @@
 #include <asm/sigp.h>
 #include <asm/pgalloc.h>
 #include <asm/irq.h>
-#include <asm/s390_ext.h>
 #include <asm/cpcmd.h>
 #include <asm/tlbflush.h>
 #include <asm/timer.h>
@@ -335,7 +334,7 @@ static int smp_rescan_cpus_sigp(cpumask_t avail)
                 smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN;
                 if (!cpu_stopped(logical_cpu))
                         continue;
-                cpu_set(logical_cpu, cpu_present_map);
+                set_cpu_present(logical_cpu, true);
                 smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED;
                 logical_cpu = cpumask_next(logical_cpu, &avail);
                 if (logical_cpu >= nr_cpu_ids)
@@ -367,7 +366,7 @@ static int smp_rescan_cpus_sclp(cpumask_t avail)
                         continue;
                 __cpu_logical_map[logical_cpu] = cpu_id;
                 smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN;
-                cpu_set(logical_cpu, cpu_present_map);
+                set_cpu_present(logical_cpu, true);
                 if (cpu >= info->configured)
                         smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY;
                 else
@@ -385,7 +384,7 @@ static int __smp_rescan_cpus(void)
 {
         cpumask_t avail;
 
-        cpus_xor(avail, cpu_possible_map, cpu_present_map);
+        cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
         if (smp_use_sigp_detection)
                 return smp_rescan_cpus_sigp(avail);
         else
@@ -467,7 +466,7 @@ int __cpuinit start_secondary(void *cpuvoid)
         notify_cpu_starting(smp_processor_id());
         /* Mark this cpu as online */
         ipi_call_lock();
-        cpu_set(smp_processor_id(), cpu_online_map);
+        set_cpu_online(smp_processor_id(), true);
         ipi_call_unlock();
         /* Switch on interrupts */
         local_irq_enable();
@@ -644,7 +643,7 @@ int __cpu_disable(void)
         struct ec_creg_mask_parms cr_parms;
         int cpu = smp_processor_id();
 
-        cpu_clear(cpu, cpu_online_map);
+        set_cpu_online(cpu, false);
 
         /* Disable pfault pseudo page faults on this cpu. */
         pfault_fini();
@@ -654,8 +653,8 @@ int __cpu_disable(void)
 
         /* disable all external interrupts */
         cr_parms.orvals[0] = 0;
-        cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 12 |
-                                1 << 11 | 1 << 10 | 1 <<  6 | 1 <<  4);
+        cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 11 |
+                                1 << 10 | 1 <<  9 | 1 <<  6 | 1 <<  4);
         /* disable all I/O interrupts */
         cr_parms.orvals[6] = 0;
         cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 |
@@ -681,7 +680,7 @@ void __cpu_die(unsigned int cpu)
         atomic_dec(&init_mm.context.attach_count);
 }
 
-void cpu_die(void)
+void __noreturn cpu_die(void)
 {
         idle_task_exit();
         while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
@@ -738,8 +737,8 @@ void __init smp_prepare_boot_cpu(void)
         BUG_ON(smp_processor_id() != 0);
 
         current_thread_info()->cpu = 0;
-        cpu_set(0, cpu_present_map);
-        cpu_set(0, cpu_online_map);
+        set_cpu_present(0, true);
+        set_cpu_online(0, true);
         S390_lowcore.percpu_offset = __per_cpu_offset[0];
         current_set[0] = current;
         smp_cpu_state[0] = CPU_STATE_CONFIGURED;
@@ -1016,21 +1015,21 @@ int __ref smp_rescan_cpus(void)
 
         get_online_cpus();
         mutex_lock(&smp_cpu_state_mutex);
-        newcpus = cpu_present_map;
+        cpumask_copy(&newcpus, cpu_present_mask);
         rc = __smp_rescan_cpus();
         if (rc)
                 goto out;
-        cpus_andnot(newcpus, cpu_present_map, newcpus);
-        for_each_cpu_mask(cpu, newcpus) {
+        cpumask_andnot(&newcpus, cpu_present_mask, &newcpus);
+        for_each_cpu(cpu, &newcpus) {
                 rc = smp_add_present_cpu(cpu);
                 if (rc)
-                        cpu_clear(cpu, cpu_present_map);
+                        set_cpu_present(cpu, false);
         }
         rc = 0;
 out:
         mutex_unlock(&smp_cpu_state_mutex);
         put_online_cpus();
-        if (!cpus_empty(newcpus))
+        if (!cpumask_empty(&newcpus))
                 topology_schedule_update();
         return rc;
 }
diff --git a/arch/s390/kernel/syscalls.S b/arch/s390/kernel/syscalls.S
index 9c65fd4ddce0..6ee39ef8fe4a 100644
--- a/arch/s390/kernel/syscalls.S
+++ b/arch/s390/kernel/syscalls.S
@@ -347,3 +347,4 @@ SYSCALL(sys_name_to_handle_at,sys_name_to_handle_at,sys_name_to_handle_at_wrappe
 SYSCALL(sys_open_by_handle_at,sys_open_by_handle_at,compat_sys_open_by_handle_at_wrapper)
 SYSCALL(sys_clock_adjtime,sys_clock_adjtime,compat_sys_clock_adjtime_wrapper)
 SYSCALL(sys_syncfs,sys_syncfs,sys_syncfs_wrapper)
+SYSCALL(sys_setns,sys_setns,sys_setns_wrapper)
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 87be655557aa..dff933065ab6 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -41,7 +41,6 @@
 #include <linux/kprobes.h>
 #include <asm/uaccess.h>
 #include <asm/delay.h>
-#include <asm/s390_ext.h>
 #include <asm/div64.h>
 #include <asm/vdso.h>
 #include <asm/irq.h>
@@ -810,7 +809,7 @@ static int etr_sync_clock_stop(struct etr_aib *aib, int port)
         etr_sync.etr_port = port;
         get_online_cpus();
         atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
-        rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map);
+        rc = stop_machine(etr_sync_clock, &etr_sync, cpu_online_mask);
         put_online_cpus();
         return rc;
 }
@@ -1579,7 +1578,7 @@ static void stp_work_fn(struct work_struct *work)
         memset(&stp_sync, 0, sizeof(stp_sync));
         get_online_cpus();
         atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
-        stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map);
+        stop_machine(stp_sync_clock, &stp_sync, cpu_online_mask);
         put_online_cpus();
 
         if (!check_sync_clock())
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 94b06c31fc8a..0cd340b72632 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -17,7 +17,6 @@
 #include <linux/smp.h>
 #include <linux/cpuset.h>
 #include <asm/delay.h>
-#include <asm/s390_ext.h>
 
 #define PTF_HORIZONTAL  (0UL)
 #define PTF_VERTICAL    (1UL)
@@ -52,20 +51,20 @@ static cpumask_t cpu_group_map(struct mask_info *info, unsigned int cpu)
 {
         cpumask_t mask;
 
-        cpus_clear(mask);
+        cpumask_clear(&mask);
         if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) {
                 cpumask_copy(&mask, cpumask_of(cpu));
                 return mask;
         }
         while (info) {
-                if (cpu_isset(cpu, info->mask)) {
+                if (cpumask_test_cpu(cpu, &info->mask)) {
                         mask = info->mask;
                         break;
                 }
                 info = info->next;
         }
-        if (cpus_empty(mask))
-                mask = cpumask_of_cpu(cpu);
+        if (cpumask_empty(&mask))
+                cpumask_copy(&mask, cpumask_of(cpu));
         return mask;
 }
 
@@ -85,10 +84,10 @@ static void add_cpus_to_mask(struct topology_cpu *tl_cpu,
                         if (cpu_logical_map(lcpu) != rcpu)
                                 continue;
 #ifdef CONFIG_SCHED_BOOK
-                        cpu_set(lcpu, book->mask);
+                        cpumask_set_cpu(lcpu, &book->mask);
                         cpu_book_id[lcpu] = book->id;
 #endif
-                        cpu_set(lcpu, core->mask);
+                        cpumask_set_cpu(lcpu, &core->mask);
                         cpu_core_id[lcpu] = core->id;
                         smp_cpu_polarization[lcpu] = tl_cpu->pp;
                 }
@@ -101,13 +100,13 @@ static void clear_masks(void)
 
         info = &core_info;
         while (info) {
-                cpus_clear(info->mask);
+                cpumask_clear(&info->mask);
                 info = info->next;
         }
 #ifdef CONFIG_SCHED_BOOK
         info = &book_info;
         while (info) {
-                cpus_clear(info->mask);
+                cpumask_clear(&info->mask);
                 info = info->next;
         }
 #endif
diff --git a/arch/s390/kernel/traps.c b/arch/s390/kernel/traps.c
index b5a4a739b477..a65d2e82f61d 100644
--- a/arch/s390/kernel/traps.c
+++ b/arch/s390/kernel/traps.c
@@ -39,7 +39,6 @@
 #include <asm/atomic.h>
 #include <asm/mathemu.h>
 #include <asm/cpcmd.h>
-#include <asm/s390_ext.h>
 #include <asm/lowcore.h>
 #include <asm/debug.h>
 #include "entry.h"
diff --git a/arch/s390/kernel/vdso32/Makefile b/arch/s390/kernel/vdso32/Makefile
index d13e8755a8cc..8ad2b34ad151 100644
--- a/arch/s390/kernel/vdso32/Makefile
+++ b/arch/s390/kernel/vdso32/Makefile
@@ -22,6 +22,9 @@ obj-y += vdso32_wrapper.o
 extra-y += vdso32.lds
 CPPFLAGS_vdso32.lds += -P -C -U$(ARCH)
 
+# Disable gcov profiling for VDSO code
+GCOV_PROFILE := n
+
 # Force dependency (incbin is bad)
 $(obj)/vdso32_wrapper.o : $(obj)/vdso32.so
 
diff --git a/arch/s390/kernel/vdso64/Makefile b/arch/s390/kernel/vdso64/Makefile
index 449352dda9cd..2a8ddfd12a5b 100644
--- a/arch/s390/kernel/vdso64/Makefile
+++ b/arch/s390/kernel/vdso64/Makefile
@@ -22,6 +22,9 @@ obj-y += vdso64_wrapper.o
 extra-y += vdso64.lds
 CPPFLAGS_vdso64.lds += -P -C -U$(ARCH)
 
+# Disable gcov profiling for VDSO code
+GCOV_PROFILE := n
+
 # Force dependency (incbin is bad)
 $(obj)/vdso64_wrapper.o : $(obj)/vdso64.so
 
diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S
index 1bc18cdb525b..56fe6bc81fee 100644
--- a/arch/s390/kernel/vmlinux.lds.S
+++ b/arch/s390/kernel/vmlinux.lds.S
@@ -77,7 +77,7 @@ SECTIONS
         . = ALIGN(PAGE_SIZE);
         INIT_DATA_SECTION(0x100)
 
-        PERCPU(0x100, PAGE_SIZE)
+        PERCPU_SECTION(0x100)
         . = ALIGN(PAGE_SIZE);
         __init_end = .;         /* freed after init ends here */
 
diff --git a/arch/s390/kernel/vtime.c b/arch/s390/kernel/vtime.c
index 5e8ead4b4aba..2d6228f60cd6 100644
--- a/arch/s390/kernel/vtime.c
+++ b/arch/s390/kernel/vtime.c
@@ -22,10 +22,10 @@
 #include <linux/cpu.h>
 #include <linux/kprobes.h>
 
-#include <asm/s390_ext.h>
 #include <asm/timer.h>
 #include <asm/irq_regs.h>
 #include <asm/cputime.h>
+#include <asm/irq.h>
 
 static DEFINE_PER_CPU(struct vtimer_queue, virt_cpu_timer);
 
diff --git a/arch/s390/lib/delay.c b/arch/s390/lib/delay.c
index 0f53110e1d09..a65229d91c92 100644
--- a/arch/s390/lib/delay.c
+++ b/arch/s390/lib/delay.c
@@ -12,6 +12,7 @@
 #include <linux/module.h>
 #include <linux/irqflags.h>
 #include <linux/interrupt.h>
+#include <asm/div64.h>
 
 void __delay(unsigned long loops)
 {
@@ -116,3 +117,17 @@ void udelay_simple(unsigned long long usecs)
         while (get_clock() < end)
                 cpu_relax();
 }
+
+void __ndelay(unsigned long long nsecs)
+{
+        u64 end;
+
+        nsecs <<= 9;
+        do_div(nsecs, 125);
+        end = get_clock() + nsecs;
+        if (nsecs & ~0xfffUL)
+                __udelay(nsecs >> 12);
+        while (get_clock() < end)
+                barrier();
+}
+EXPORT_SYMBOL(__ndelay);
diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c
index 3cc95dd0a3a6..075ddada4911 100644
--- a/arch/s390/mm/extmem.c
+++ b/arch/s390/mm/extmem.c
@@ -412,6 +412,7 @@ __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long
         struct dcss_segment *seg;
         int rc, diag_cc;
 
+        start_addr = end_addr = 0;
         seg = kmalloc(sizeof(*seg), GFP_KERNEL | GFP_DMA);
         if (seg == NULL) {
                 rc = -ENOMEM;
@@ -573,6 +574,7 @@ segment_modify_shared (char *name, int do_nonshared)
         unsigned long start_addr, end_addr, dummy;
         int rc, diag_cc;
 
+        start_addr = end_addr = 0;
         mutex_lock(&dcss_lock);
         seg = segment_by_name (name);
         if (seg == NULL) {
@@ -681,8 +683,6 @@ void
 segment_save(char *name)
 {
         struct dcss_segment *seg;
-        int startpfn = 0;
-        int endpfn = 0;
         char cmd1[160];
         char cmd2[80];
         int i, response;
@@ -698,8 +698,6 @@ segment_save(char *name)
                 goto out;
         }
 
-        startpfn = seg->start_addr >> PAGE_SHIFT;
-        endpfn = (seg->end) >> PAGE_SHIFT;
         sprintf(cmd1, "DEFSEG %s", name);
         for (i=0; i<seg->segcnt; i++) {
                 sprintf(cmd1+strlen(cmd1), " %lX-%lX %s",
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index ab988135e5c6..fe103e891e7a 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -34,7 +34,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
-#include <asm/s390_ext.h>
+#include <asm/irq.h>
 #include <asm/mmu_context.h>
 #include <asm/compat.h>
 #include "../kernel/entry.h"
@@ -225,33 +225,6 @@ static noinline void do_sigbus(struct pt_regs *regs, long int_code,
         force_sig_info(SIGBUS, &si, tsk);
 }
 
-#ifdef CONFIG_S390_EXEC_PROTECT
-static noinline int signal_return(struct pt_regs *regs, long int_code,
-                                  unsigned long trans_exc_code)
-{
-        u16 instruction;
-        int rc;
-
-        rc = __get_user(instruction, (u16 __user *) regs->psw.addr);
-
-        if (!rc && instruction == 0x0a77) {
-                clear_tsk_thread_flag(current, TIF_PER_TRAP);
-                if (is_compat_task())
-                        sys32_sigreturn();
-                else
-                        sys_sigreturn();
-        } else if (!rc && instruction == 0x0aad) {
-                clear_tsk_thread_flag(current, TIF_PER_TRAP);
-                if (is_compat_task())
-                        sys32_rt_sigreturn();
-                else
-                        sys_rt_sigreturn();
-        } else
-                do_sigsegv(regs, int_code, SEGV_MAPERR, trans_exc_code);
-        return 0;
-}
-#endif /* CONFIG_S390_EXEC_PROTECT */
-
 static noinline void do_fault_error(struct pt_regs *regs, long int_code,
                                     unsigned long trans_exc_code, int fault)
 {
@@ -259,13 +232,6 @@ static noinline void do_fault_error(struct pt_regs *regs, long int_code,
 
         switch (fault) {
         case VM_FAULT_BADACCESS:
-#ifdef CONFIG_S390_EXEC_PROTECT
-                if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_SECONDARY &&
-                    (trans_exc_code & 3) == 0) {
-                        signal_return(regs, int_code, trans_exc_code);
-                        break;
-                }
-#endif /* CONFIG_S390_EXEC_PROTECT */
         case VM_FAULT_BADMAP:
                 /* Bad memory access. Check if it is kernel or user space. */
                 if (regs->psw.mask & PSW_MASK_PSTATE) {
@@ -279,9 +245,12 @@ static noinline void do_fault_error(struct pt_regs *regs, long int_code,
                 do_no_context(regs, int_code, trans_exc_code);
                 break;
         default: /* fault & VM_FAULT_ERROR */
-                if (fault & VM_FAULT_OOM)
-                        pagefault_out_of_memory();
-                else if (fault & VM_FAULT_SIGBUS) {
+                if (fault & VM_FAULT_OOM) {
+                        if (!(regs->psw.mask & PSW_MASK_PSTATE))
+                                do_no_context(regs, int_code, trans_exc_code);
+                        else
+                                pagefault_out_of_memory();
+                } else if (fault & VM_FAULT_SIGBUS) {
                         /* Kernel mode? Handle exceptions or die */
                         if (!(regs->psw.mask & PSW_MASK_PSTATE))
                                 do_no_context(regs, int_code, trans_exc_code);
@@ -311,7 +280,8 @@ static inline int do_exception(struct pt_regs *regs, int access,
         struct mm_struct *mm;
         struct vm_area_struct *vma;
         unsigned long address;
-        int fault, write;
+        unsigned int flags;
+        int fault;
 
         if (notify_page_fault(regs))
                 return 0;
@@ -330,6 +300,10 @@ static inline int do_exception(struct pt_regs *regs, int access,
 
         address = trans_exc_code & __FAIL_ADDR_MASK;
         perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
+        flags = FAULT_FLAG_ALLOW_RETRY;
+        if (access == VM_WRITE || (trans_exc_code & store_indication) == 0x400)
+                flags |= FAULT_FLAG_WRITE;
+retry:
         down_read(&mm->mmap_sem);
 
         fault = VM_FAULT_BADMAP;
@@ -359,21 +333,31 @@ static inline int do_exception(struct pt_regs *regs, int access,
          * make sure we exit gracefully rather than endlessly redo
          * the fault.
          */
-        write = (access == VM_WRITE ||
-                 (trans_exc_code & store_indication) == 0x400) ?
-                FAULT_FLAG_WRITE : 0;
-        fault = handle_mm_fault(mm, vma, address, write);
+        fault = handle_mm_fault(mm, vma, address, flags);
         if (unlikely(fault & VM_FAULT_ERROR))
                 goto out_up;
 
-        if (fault & VM_FAULT_MAJOR) {
-                tsk->maj_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
-                                     regs, address);
-        } else {
-                tsk->min_flt++;
-                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
-                                     regs, address);
+        /*
+         * Major/minor page fault accounting is only done on the
+         * initial attempt. If we go through a retry, it is extremely
+         * likely that the page will be found in page cache at that point.
+         */
+        if (flags & FAULT_FLAG_ALLOW_RETRY) {
+                if (fault & VM_FAULT_MAJOR) {
+                        tsk->maj_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                                      regs, address);
+                } else {
+                        tsk->min_flt++;
+                        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                                      regs, address);
+                }
+                if (fault & VM_FAULT_RETRY) {
+                        /* Clear FAULT_FLAG_ALLOW_RETRY to avoid any risk
+                         * of starvation. */
+                        flags &= ~FAULT_FLAG_ALLOW_RETRY;
+                        goto retry;
+                }
         }
         /*
          * The instruction that caused the program check will
@@ -414,11 +398,6 @@ void __kprobes do_dat_exception(struct pt_regs *regs, long pgm_int_code,
         int access, fault;
 
         access = VM_READ | VM_EXEC | VM_WRITE;
-#ifdef CONFIG_S390_EXEC_PROTECT
-        if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_SECONDARY &&
-            (trans_exc_code & 3) == 0)
-                access = VM_EXEC;
-#endif
         fault = do_exception(regs, access, trans_exc_code);
         if (unlikely(fault))
                 do_fault_error(regs, pgm_int_code & 255, trans_exc_code, fault);
@@ -468,10 +447,9 @@ int __handle_fault(unsigned long uaddr, unsigned long pgm_int_code, int write)
         access = write ? VM_WRITE : VM_READ;
         fault = do_exception(&regs, access, uaddr | 2);
         if (unlikely(fault)) {
-                if (fault & VM_FAULT_OOM) {
-                        pagefault_out_of_memory();
-                        fault = 0;
-                } else if (fault & VM_FAULT_SIGBUS)
+                if (fault & VM_FAULT_OOM)
+                        return -EFAULT;
+                else if (fault & VM_FAULT_SIGBUS)
                         do_sigbus(&regs, pgm_int_code, uaddr);
         }
         return fault ? -EFAULT : 0;
@@ -491,22 +469,28 @@ static int __init nopfault(char *str)
 
 __setup("nopfault", nopfault);
 
-typedef struct {
-        __u16 refdiagc;
-        __u16 reffcode;
-        __u16 refdwlen;
-        __u16 refversn;
-        __u64 refgaddr;
-        __u64 refselmk;
-        __u64 refcmpmk;
-        __u64 reserved;
-} __attribute__ ((packed, aligned(8))) pfault_refbk_t;
+struct pfault_refbk {
+        u16 refdiagc;
+        u16 reffcode;
+        u16 refdwlen;
+        u16 refversn;
+        u64 refgaddr;
+        u64 refselmk;
+        u64 refcmpmk;
+        u64 reserved;
+} __attribute__ ((packed, aligned(8)));
 
 int pfault_init(void)
 {
-        pfault_refbk_t refbk =
-                { 0x258, 0, 5, 2, __LC_CURRENT, 1ULL << 48, 1ULL << 48,
-                  __PF_RES_FIELD };
+        struct pfault_refbk refbk = {
+                .refdiagc = 0x258,
+                .reffcode = 0,
+                .refdwlen = 5,
+                .refversn = 2,
+                .refgaddr = __LC_CURRENT_PID,
+                .refselmk = 1ULL << 48,
+                .refcmpmk = 1ULL << 48,
+                .reserved = __PF_RES_FIELD };
         int rc;
 
         if (!MACHINE_IS_VM || pfault_disable)
@@ -518,18 +502,20 @@ int pfault_init(void)
                 "2:\n"
                 EX_TABLE(0b,1b)
                 : "=d" (rc) : "a" (&refbk), "m" (refbk) : "cc");
-        __ctl_set_bit(0, 9);
         return rc;
 }
 
 void pfault_fini(void)
 {
-        pfault_refbk_t refbk =
-        { 0x258, 1, 5, 2, 0ULL, 0ULL, 0ULL, 0ULL };
+        struct pfault_refbk refbk = {
+                .refdiagc = 0x258,
+                .reffcode = 1,
+                .refdwlen = 5,
+                .refversn = 2,
+        };
 
         if (!MACHINE_IS_VM || pfault_disable)
                 return;
-        __ctl_clear_bit(0,9);
         asm volatile(
                 "       diag    %0,0,0x258\n"
                 "0:\n"
@@ -537,11 +523,15 @@ void pfault_fini(void)
                 : : "a" (&refbk), "m" (refbk) : "cc");
 }
 
+static DEFINE_SPINLOCK(pfault_lock);
+static LIST_HEAD(pfault_list);
+
 static void pfault_interrupt(unsigned int ext_int_code,
                              unsigned int param32, unsigned long param64)
 {
         struct task_struct *tsk;
         __u16 subcode;
+        pid_t pid;
 
         /*
          * Get the external interruption subcode & pfault
@@ -553,44 +543,79 @@ static void pfault_interrupt(unsigned int ext_int_code,
         if ((subcode & 0xff00) != __SUBCODE_MASK)
                 return;
         kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
-
-        /*
-         * Get the token (= address of the task structure of the affected task).
-         */
-#ifdef CONFIG_64BIT
-        tsk = (struct task_struct *) param64;
-#else
-        tsk = (struct task_struct *) param32;
-#endif
-
+        if (subcode & 0x0080) {
+                /* Get the token (= pid of the affected task). */
+                pid = sizeof(void *) == 4 ? param32 : param64;
+                rcu_read_lock();
+                tsk = find_task_by_pid_ns(pid, &init_pid_ns);
+                if (tsk)
+                        get_task_struct(tsk);
+                rcu_read_unlock();
+                if (!tsk)
+                        return;
+        } else {
+                tsk = current;
+        }
+        spin_lock(&pfault_lock);
         if (subcode & 0x0080) {
                 /* signal bit is set -> a page has been swapped in by VM */
-                if (xchg(&tsk->thread.pfault_wait, -1) != 0) {
+                if (tsk->thread.pfault_wait == 1) {
                         /* Initial interrupt was faster than the completion
                          * interrupt. pfault_wait is valid. Set pfault_wait
                          * back to zero and wake up the process. This can
                          * safely be done because the task is still sleeping
                          * and can't produce new pfaults. */
                         tsk->thread.pfault_wait = 0;
+                        list_del(&tsk->thread.list);
                         wake_up_process(tsk);
-                        put_task_struct(tsk);
+                } else {
+                        /* Completion interrupt was faster than initial
+                         * interrupt. Set pfault_wait to -1 so the initial
+                         * interrupt doesn't put the task to sleep. */
+                        tsk->thread.pfault_wait = -1;
                 }
+                put_task_struct(tsk);
         } else {
                 /* signal bit not set -> a real page is missing. */
-                get_task_struct(tsk);
-                set_task_state(tsk, TASK_UNINTERRUPTIBLE);
-                if (xchg(&tsk->thread.pfault_wait, 1) != 0) {
+                if (tsk->thread.pfault_wait == -1) {
                         /* Completion interrupt was faster than the initial
-                         * interrupt (swapped in a -1 for pfault_wait). Set
-                         * pfault_wait back to zero and exit. This can be
-                         * done safely because tsk is running in kernel 
-                         * mode and can't produce new pfaults. */
+                         * interrupt (pfault_wait == -1). Set pfault_wait
+                         * back to zero and exit. */
                         tsk->thread.pfault_wait = 0;
-                        set_task_state(tsk, TASK_RUNNING);
-                        put_task_struct(tsk);
-                } else
+                } else {
+                        /* Initial interrupt arrived before completion
+                         * interrupt. Let the task sleep. */
+                        tsk->thread.pfault_wait = 1;
+                        list_add(&tsk->thread.list, &pfault_list);
+                        set_task_state(tsk, TASK_UNINTERRUPTIBLE);
                         set_tsk_need_resched(tsk);
+                }
+        }
+        spin_unlock(&pfault_lock);
+}
+
+static int __cpuinit pfault_cpu_notify(struct notifier_block *self,
+                                       unsigned long action, void *hcpu)
+{
+        struct thread_struct *thread, *next;
+        struct task_struct *tsk;
+
+        switch (action) {
+        case CPU_DEAD:
+        case CPU_DEAD_FROZEN:
+                spin_lock_irq(&pfault_lock);
+                list_for_each_entry_safe(thread, next, &pfault_list, list) {
+                        thread->pfault_wait = 0;
+                        list_del(&thread->list);
+                        tsk = container_of(thread, struct task_struct, thread);
+                        wake_up_process(tsk);
+                }
+                spin_unlock_irq(&pfault_lock);
+                break;
+        default:
+                break;
         }
+        return NOTIFY_OK;
 }
 
 static int __init pfault_irq_init(void)
@@ -599,22 +624,22 @@ static int __init pfault_irq_init(void)
 
         if (!MACHINE_IS_VM)
                 return 0;
-        /*
-         * Try to get pfault pseudo page faults going.
-         */
         rc = register_external_interrupt(0x2603, pfault_interrupt);
-        if (rc) {
-                pfault_disable = 1;
-                return rc;
-        }
-        if (pfault_init() == 0)
-                return 0;
+        if (rc)
+                goto out_extint;
+        rc = pfault_init() == 0 ? 0 : -EOPNOTSUPP;
+        if (rc)
+                goto out_pfault;
+        service_subclass_irq_register();
+        hotcpu_notifier(pfault_cpu_notify, 0);
+        return 0;
 
-        /* Tough luck, no pfault. */
-        pfault_disable = 1;
+out_pfault:
         unregister_external_interrupt(0x2603, pfault_interrupt);
-        return 0;
+out_extint:
+        pfault_disable = 1;
+        return rc;
 }
 early_initcall(pfault_irq_init);
 
-#endif
+#endif /* CONFIG_PFAULT */
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index 639cd21f2218..a4d856db9154 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -13,7 +13,6 @@ void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
                                    pte_t *pteptr, pte_t pteval)
 {
         pmd_t *pmdp = (pmd_t *) pteptr;
-        pte_t shadow_pteval = pteval;
         unsigned long mask;
 
         if (!MACHINE_HAS_HPAGE) {
@@ -21,18 +20,9 @@ void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
                 mask = pte_val(pteval) &
                                 (_SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO);
                 pte_val(pteval) = (_SEGMENT_ENTRY + __pa(pteptr)) | mask;
-                if (mm->context.noexec) {
-                        pteptr += PTRS_PER_PTE;
-                        pte_val(shadow_pteval) =
-                                        (_SEGMENT_ENTRY + __pa(pteptr)) | mask;
-                }
         }
 
         pmd_val(*pmdp) = pte_val(pteval);
-        if (mm->context.noexec) {
-                pmdp = get_shadow_table(pmdp);
-                pmd_val(*pmdp) = pte_val(shadow_pteval);
-        }
 }
 
 int arch_prepare_hugepage(struct page *page)
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index bb409332a484..59b663109d90 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -119,9 +119,7 @@ void __init paging_init(void)
         sparse_memory_present_with_active_regions(MAX_NUMNODES);
         sparse_init();
         memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
-#ifdef CONFIG_ZONE_DMA
         max_zone_pfns[ZONE_DMA] = PFN_DOWN(MAX_DMA_ADDRESS);
-#endif
         max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
         free_area_init_nodes(max_zone_pfns);
         fault_init();
@@ -175,7 +173,8 @@ void kernel_map_pages(struct page *page, int numpages, int enable)
                 pmd = pmd_offset(pud, address);
                 pte = pte_offset_kernel(pmd, address);
                 if (!enable) {
-                        ptep_invalidate(&init_mm, address, pte);
+                        __ptep_ipte(address, pte);
+                        pte_val(*pte) = _PAGE_TYPE_EMPTY;
                         continue;
                 }
                 *pte = mk_pte_phys(address, __pgprot(_PAGE_TYPE_RW));
diff --git a/arch/s390/mm/maccess.c b/arch/s390/mm/maccess.c
index 71a4b0d34be0..51e5cd9b906a 100644
--- a/arch/s390/mm/maccess.c
+++ b/arch/s390/mm/maccess.c
@@ -19,7 +19,7 @@
  * using the stura instruction.
  * Returns the number of bytes copied or -EFAULT.
  */
-static long probe_kernel_write_odd(void *dst, void *src, size_t size)
+static long probe_kernel_write_odd(void *dst, const void *src, size_t size)
 {
         unsigned long count, aligned;
         int offset, mask;
@@ -45,7 +45,7 @@ static long probe_kernel_write_odd(void *dst, void *src, size_t size)
         return rc ? rc : count;
 }
 
-long probe_kernel_write(void *dst, void *src, size_t size)
+long probe_kernel_write(void *dst, const void *src, size_t size)
 {
         long copied = 0;
 
diff --git a/arch/s390/mm/pageattr.c b/arch/s390/mm/pageattr.c
index f05edcc3beff..d013ed39743b 100644
--- a/arch/s390/mm/pageattr.c
+++ b/arch/s390/mm/pageattr.c
@@ -28,7 +28,7 @@ static void change_page_attr(unsigned long addr, int numpages,
 
                 pte = *ptep;
                 pte = set(pte);
-                ptep_invalidate(&init_mm, addr, ptep);
+                __ptep_ipte(addr, ptep);
                 *ptep = pte;
                 addr += PAGE_SIZE;
         }
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index e1850c28cd68..b09763fe5da1 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -36,11 +36,9 @@ struct rcu_table_freelist {
         ((PAGE_SIZE - sizeof(struct rcu_table_freelist)) \
           / sizeof(unsigned long))
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 static DEFINE_PER_CPU(struct rcu_table_freelist *, rcu_table_freelist);
 
 static void __page_table_free(struct mm_struct *mm, unsigned long *table);
-static void __crst_table_free(struct mm_struct *mm, unsigned long *table);
 
 static struct rcu_table_freelist *rcu_table_freelist_get(struct mm_struct *mm)
 {
@@ -67,18 +65,21 @@ static void rcu_table_freelist_callback(struct rcu_head *head)
         while (batch->pgt_index > 0)
                 __page_table_free(batch->mm, batch->table[--batch->pgt_index]);
         while (batch->crst_index < RCU_FREELIST_SIZE)
-                __crst_table_free(batch->mm, batch->table[batch->crst_index++]);
+                crst_table_free(batch->mm, batch->table[batch->crst_index++]);
         free_page((unsigned long) batch);
 }
 
 void rcu_table_freelist_finish(void)
 {
-        struct rcu_table_freelist *batch = __get_cpu_var(rcu_table_freelist);
+        struct rcu_table_freelist **batchp = &get_cpu_var(rcu_table_freelist);
+        struct rcu_table_freelist *batch = *batchp;
 
         if (!batch)
-                return;
+                goto out;
         call_rcu(&batch->rcu, rcu_table_freelist_callback);
-        __get_cpu_var(rcu_table_freelist) = NULL;
+        *batchp = NULL;
+out:
+        put_cpu_var(rcu_table_freelist);
 }
 
 static void smp_sync(void *arg)
@@ -125,68 +126,41 @@ static int __init parse_vmalloc(char *arg)
 }
 early_param("vmalloc", parse_vmalloc);
 
-unsigned long *crst_table_alloc(struct mm_struct *mm, int noexec)
+unsigned long *crst_table_alloc(struct mm_struct *mm)
 {
         struct page *page = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
 
         if (!page)
                 return NULL;
-        page->index = 0;
-        if (noexec) {
-                struct page *shadow = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
-                if (!shadow) {
-                        __free_pages(page, ALLOC_ORDER);
-                        return NULL;
-                }
-                page->index = page_to_phys(shadow);
-        }
-        spin_lock_bh(&mm->context.list_lock);
-        list_add(&page->lru, &mm->context.crst_list);
-        spin_unlock_bh(&mm->context.list_lock);
         return (unsigned long *) page_to_phys(page);
 }
 
-static void __crst_table_free(struct mm_struct *mm, unsigned long *table)
-{
-        unsigned long *shadow = get_shadow_table(table);
-
-        if (shadow)
-                free_pages((unsigned long) shadow, ALLOC_ORDER);
-        free_pages((unsigned long) table, ALLOC_ORDER);
-}
-
 void crst_table_free(struct mm_struct *mm, unsigned long *table)
 {
-        struct page *page = virt_to_page(table);
-
-        spin_lock_bh(&mm->context.list_lock);
-        list_del(&page->lru);
-        spin_unlock_bh(&mm->context.list_lock);
-        __crst_table_free(mm, table);
+        free_pages((unsigned long) table, ALLOC_ORDER);
 }
 
 void crst_table_free_rcu(struct mm_struct *mm, unsigned long *table)
 {
         struct rcu_table_freelist *batch;
-        struct page *page = virt_to_page(table);
 
-        spin_lock_bh(&mm->context.list_lock);
-        list_del(&page->lru);
-        spin_unlock_bh(&mm->context.list_lock);
+        preempt_disable();
         if (atomic_read(&mm->mm_users) < 2 &&
             cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
-                __crst_table_free(mm, table);
-                return;
+                crst_table_free(mm, table);
+                goto out;
         }
         batch = rcu_table_freelist_get(mm);
         if (!batch) {
                 smp_call_function(smp_sync, NULL, 1);
-                __crst_table_free(mm, table);
-                return;
+                crst_table_free(mm, table);
+                goto out;
         }
         batch->table[--batch->crst_index] = table;
         if (batch->pgt_index >= batch->crst_index)
                 rcu_table_freelist_finish();
+out:
+        preempt_enable();
 }
 
 #ifdef CONFIG_64BIT
@@ -197,7 +171,7 @@ int crst_table_upgrade(struct mm_struct *mm, unsigned long limit)
 
         BUG_ON(limit > (1UL << 53));
 repeat:
-        table = crst_table_alloc(mm, mm->context.noexec);
+        table = crst_table_alloc(mm);
         if (!table)
                 return -ENOMEM;
         spin_lock_bh(&mm->page_table_lock);
@@ -273,7 +247,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
         unsigned long *table;
         unsigned long bits;
 
-        bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
+        bits = (mm->context.has_pgste) ? 3UL : 1UL;
         spin_lock_bh(&mm->context.list_lock);
         page = NULL;
         if (!list_empty(&mm->context.pgtable_list)) {
@@ -329,7 +303,7 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
         struct page *page;
         unsigned long bits;
 
-        bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
+        bits = (mm->context.has_pgste) ? 3UL : 1UL;
         bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long);
         page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
         spin_lock_bh(&mm->context.list_lock);
@@ -355,18 +329,19 @@ void page_table_free_rcu(struct mm_struct *mm, unsigned long *table)
         struct page *page;
         unsigned long bits;
 
+        preempt_disable();
         if (atomic_read(&mm->mm_users) < 2 &&
             cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
                 page_table_free(mm, table);
-                return;
+                goto out;
         }
         batch = rcu_table_freelist_get(mm);
         if (!batch) {
                 smp_call_function(smp_sync, NULL, 1);
                 page_table_free(mm, table);
-                return;
+                goto out;
         }
-        bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
+        bits = (mm->context.has_pgste) ? 3UL : 1UL;
         bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long);
         page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
         spin_lock_bh(&mm->context.list_lock);
@@ -377,25 +352,8 @@ void page_table_free_rcu(struct mm_struct *mm, unsigned long *table)
         batch->table[batch->pgt_index++] = table;
         if (batch->pgt_index >= batch->crst_index)
                 rcu_table_freelist_finish();
-}
-
-void disable_noexec(struct mm_struct *mm, struct task_struct *tsk)
-{
-        struct page *page;
-
-        spin_lock_bh(&mm->context.list_lock);
-        /* Free shadow region and segment tables. */
-        list_for_each_entry(page, &mm->context.crst_list, lru)
-                if (page->index) {
-                        free_pages((unsigned long) page->index, ALLOC_ORDER);
-                        page->index = 0;
-                }
-        /* "Free" second halves of page tables. */
-        list_for_each_entry(page, &mm->context.pgtable_list, lru)
-                page->flags &= ~SECOND_HALVES;
-        spin_unlock_bh(&mm->context.list_lock);
-        mm->context.noexec = 0;
-        update_mm(mm, tsk);
+out:
+        preempt_enable();
 }
 
 /*
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index 34c43f23b28c..8c1970d1dd91 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -95,7 +95,7 @@ static int vmem_add_mem(unsigned long start, unsigned long size, int ro)
                         pu_dir = vmem_pud_alloc();
                         if (!pu_dir)
                                 goto out;
-                        pgd_populate_kernel(&init_mm, pg_dir, pu_dir);
+                        pgd_populate(&init_mm, pg_dir, pu_dir);
                 }
 
                 pu_dir = pud_offset(pg_dir, address);
@@ -103,7 +103,7 @@ static int vmem_add_mem(unsigned long start, unsigned long size, int ro)
                         pm_dir = vmem_pmd_alloc();
                         if (!pm_dir)
                                 goto out;
-                        pud_populate_kernel(&init_mm, pu_dir, pm_dir);
+                        pud_populate(&init_mm, pu_dir, pm_dir);
                 }
 
                 pte = mk_pte_phys(address, __pgprot(ro ? _PAGE_RO : 0));
@@ -123,7 +123,7 @@ static int vmem_add_mem(unsigned long start, unsigned long size, int ro)
                         pt_dir = vmem_pte_alloc();
                         if (!pt_dir)
                                 goto out;
-                        pmd_populate_kernel(&init_mm, pm_dir, pt_dir);
+                        pmd_populate(&init_mm, pm_dir, pt_dir);
                 }
 
                 pt_dir = pte_offset_kernel(pm_dir, address);
@@ -159,7 +159,7 @@ static void vmem_remove_range(unsigned long start, unsigned long size)
                         continue;
 
                 if (pmd_huge(*pm_dir)) {
-                        pmd_clear_kernel(pm_dir);
+                        pmd_clear(pm_dir);
                         address += HPAGE_SIZE - PAGE_SIZE;
                         continue;
                 }
@@ -192,7 +192,7 @@ int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
                         pu_dir = vmem_pud_alloc();
                         if (!pu_dir)
                                 goto out;
-                        pgd_populate_kernel(&init_mm, pg_dir, pu_dir);
+                        pgd_populate(&init_mm, pg_dir, pu_dir);
                 }
 
                 pu_dir = pud_offset(pg_dir, address);
@@ -200,7 +200,7 @@ int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
                         pm_dir = vmem_pmd_alloc();
                         if (!pm_dir)
                                 goto out;
-                        pud_populate_kernel(&init_mm, pu_dir, pm_dir);
+                        pud_populate(&init_mm, pu_dir, pm_dir);
                 }
 
                 pm_dir = pmd_offset(pu_dir, address);
@@ -208,7 +208,7 @@ int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
                         pt_dir = vmem_pte_alloc();
                         if (!pt_dir)
                                 goto out;
-                        pmd_populate_kernel(&init_mm, pm_dir, pt_dir);
+                        pmd_populate(&init_mm, pm_dir, pt_dir);
                 }
 
                 pt_dir = pte_offset_kernel(pm_dir, address);
diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c
index 33cbd373cce4..4552ce40c81a 100644
--- a/arch/s390/oprofile/hwsampler.c
+++ b/arch/s390/oprofile/hwsampler.c
@@ -5,6 +5,7 @@
  * Author: Heinz Graalfs <graalfs@de.ibm.com>
  */
 
+#include <linux/kernel_stat.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/smp.h>
@@ -18,7 +19,7 @@
 #include <linux/oprofile.h>
 
 #include <asm/lowcore.h>
-#include <asm/s390_ext.h>
+#include <asm/irq.h>
 
 #include "hwsampler.h"
 
@@ -579,7 +580,7 @@ static int hws_cpu_callback(struct notifier_block *nfb,
 {
         /* We do not have sampler space available for all possible CPUs.
            All CPUs should be online when hw sampling is activated. */
-        return NOTIFY_BAD;
+        return (hws_state <= HWS_DEALLOCATED) ? NOTIFY_OK : NOTIFY_BAD;
 }
 
 static struct notifier_block hws_cpu_notifier = {
@@ -674,17 +675,11 @@ int hwsampler_activate(unsigned int cpu)
 static void hws_ext_handler(unsigned int ext_int_code,
                             unsigned int param32, unsigned long param64)
 {
-        int cpu;
         struct hws_cpu_buffer *cb;
 
-        cpu = smp_processor_id();
-        cb = &per_cpu(sampler_cpu_buffer, cpu);
-
-        atomic_xchg(
-                        &cb->ext_params,
-                        atomic_read(&cb->ext_params)
-                                | S390_lowcore.ext_params);
-
+        kstat_cpu(smp_processor_id()).irqs[EXTINT_CPM]++;
+        cb = &__get_cpu_var(sampler_cpu_buffer);
+        atomic_xchg(&cb->ext_params, atomic_read(&cb->ext_params) | param32);
         if (hws_wq)
                 queue_work(hws_wq, &cb->worker);
 }
@@ -764,7 +759,7 @@ static int worker_check_error(unsigned int cpu, int ext_params)
         if (!sdbt || !*sdbt)
                 return -EINVAL;
 
-        if (ext_params & EI_IEA)
+        if (ext_params & EI_PRA)
                 cb->req_alert++;
 
         if (ext_params & EI_LSDA)
@@ -1009,7 +1004,7 @@ int hwsampler_deallocate()
         if (hws_state != HWS_STOPPED)
                 goto deallocate_exit;
 
-        smp_ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
+        ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
         deallocate_sdbt();
 
         hws_state = HWS_DEALLOCATED;
@@ -1123,7 +1118,7 @@ int hwsampler_shutdown()
                 mutex_lock(&hws_sem);
 
                 if (hws_state == HWS_STOPPED) {
-                        smp_ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
+                        ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
                         deallocate_sdbt();
                 }
                 if (hws_wq) {
@@ -1198,7 +1193,7 @@ start_all_exit:
         hws_oom = 1;
         hws_flush_all = 0;
         /* now let them in, 1407 CPUMF external interrupts */
-        smp_ctl_set_bit(0, 5); /* set CR0 bit 58 */
+        ctl_set_bit(0, 5); /* set CR0 bit 58 */
 
         return 0;
 }
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index e73bc781cc14..288add8d168f 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -43,9 +43,6 @@ config NO_DMA
 config RWSEM_GENERIC_SPINLOCK
         def_bool y
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
diff --git a/arch/score/Kconfig.debug b/arch/score/Kconfig.debug
index 451ed54ce646..a1f346df0a71 100644
--- a/arch/score/Kconfig.debug
+++ b/arch/score/Kconfig.debug
@@ -16,15 +16,6 @@ config CMDLINE
           other cases you can specify kernel args so that you don't have
           to set them up in board prom initialization routines.
 
-config DEBUG_STACK_USAGE
-        bool "Enable stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config RUNTIME_DEBUG
         bool "Enable run-time debugging"
         depends on DEBUG_KERNEL
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index 50fdec54c70a..cee6bce1e30c 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -38,8 +38,6 @@
 #include <asm/sections.h>
 #include <asm/tlb.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 unsigned long empty_zero_page;
 EXPORT_SYMBOL_GPL(empty_zero_page);
 
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index a164c9e3c73c..f03338c2f088 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -71,12 +71,6 @@ config GENERIC_CSUM
         def_bool y
         depends on SUPERH64
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
-config GENERIC_FIND_BIT_LE
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 1553d56cf4e0..c1d5a820b1aa 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -28,15 +28,6 @@ config STACK_DEBUG
           every function call and will therefore incur a major
           performance hit. Most users should say N.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config 4KSTACKS
         bool "Use 4Kb for kernel stacks instead of 8Kb"
         depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
diff --git a/arch/sh/configs/apsh4ad0a_defconfig b/arch/sh/configs/apsh4ad0a_defconfig
index 77ec0e7b8ddf..e7583484cc07 100644
--- a/arch/sh/configs/apsh4ad0a_defconfig
+++ b/arch/sh/configs/apsh4ad0a_defconfig
@@ -7,7 +7,6 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
diff --git a/arch/sh/configs/sdk7786_defconfig b/arch/sh/configs/sdk7786_defconfig
index c41650572d79..8a7dd7b59c5c 100644
--- a/arch/sh/configs/sdk7786_defconfig
+++ b/arch/sh/configs/sdk7786_defconfig
@@ -12,7 +12,6 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
diff --git a/arch/sh/configs/se7206_defconfig b/arch/sh/configs/se7206_defconfig
index a468ff227fc6..72c3fad7383f 100644
--- a/arch/sh/configs/se7206_defconfig
+++ b/arch/sh/configs/se7206_defconfig
@@ -8,7 +8,6 @@ CONFIG_RCU_TRACE=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
 CONFIG_RESOURCE_COUNTERS=y
diff --git a/arch/sh/configs/shx3_defconfig b/arch/sh/configs/shx3_defconfig
index 3f92d37c6374..6bb413036892 100644
--- a/arch/sh/configs/shx3_defconfig
+++ b/arch/sh/configs/shx3_defconfig
@@ -9,7 +9,6 @@ CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CGROUP_CPUACCT=y
diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig
index 7b3daec6fefe..8bfa4d056d7a 100644
--- a/arch/sh/configs/urquell_defconfig
+++ b/arch/sh/configs/urquell_defconfig
@@ -9,7 +9,6 @@ CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=14
 CONFIG_CGROUPS=y
 CONFIG_CGROUP_DEBUG=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CGROUP_DEVICE=y
 CONFIG_CPUSETS=y
diff --git a/arch/sh/include/asm/kgdb.h b/arch/sh/include/asm/kgdb.h
index 4235e228d921..f3613952d1ae 100644
--- a/arch/sh/include/asm/kgdb.h
+++ b/arch/sh/include/asm/kgdb.h
@@ -34,5 +34,6 @@ static inline void arch_kgdb_breakpoint(void)
 
 #define CACHE_FLUSH_IS_SAFE     1
 #define BREAK_INSTR_SIZE        2
+#define GDB_ADJUSTS_BREAK_OFFSET
 
 #endif /* __ASM_SH_KGDB_H */
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index de167d3a1a80..40725b4a8018 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -40,9 +40,8 @@
 #include <asm/system.h>
 
 #define user_mode(regs)                 (((regs)->sr & 0x40000000)==0)
-#define user_stack_pointer(_regs)       ((unsigned long)(_regs)->regs[15])
 #define kernel_stack_pointer(_regs)     ((unsigned long)(_regs)->regs[15])
-#define instruction_pointer(regs)       ((unsigned long)(regs)->pc)
+#define GET_USP(regs) ((regs)->regs[15])
 
 extern void show_regs(struct pt_regs *);
 
@@ -139,6 +138,9 @@ static inline unsigned long profile_pc(struct pt_regs *regs)
 
         return pc;
 }
+#define profile_pc profile_pc
+
+#include <asm-generic/ptrace.h>
 #endif /* __KERNEL__ */
 
 #endif /* __ASM_SH_PTRACE_H */
diff --git a/arch/sh/include/asm/suspend.h b/arch/sh/include/asm/suspend.h
index 64eb41a063e8..e14567a7e9a1 100644
--- a/arch/sh/include/asm/suspend.h
+++ b/arch/sh/include/asm/suspend.h
@@ -3,7 +3,6 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/notifier.h>
-static inline int arch_prepare_suspend(void) { return 0; }
 
 #include <asm/ptrace.h>
 
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
index 75abb38dffd5..6c308d8b9a50 100644
--- a/arch/sh/include/asm/tlb.h
+++ b/arch/sh/include/asm/tlb.h
@@ -23,8 +23,6 @@ struct mmu_gather {
         unsigned long           start, end;
 };
 
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 static inline void init_tlb_gather(struct mmu_gather *tlb)
 {
         tlb->start = TASK_SIZE;
@@ -36,17 +34,13 @@ static inline void init_tlb_gather(struct mmu_gather *tlb)
         }
 }
 
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
         tlb->mm = mm;
         tlb->fullmm = full_mm_flush;
 
         init_tlb_gather(tlb);
-
-        return tlb;
 }
 
 static inline void
@@ -57,8 +51,6 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-
-        put_cpu_var(mmu_gathers);
 }
 
 static inline void
@@ -91,7 +83,21 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
         }
 }
 
-#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+}
+
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        free_page_and_swap_cache(page);
+        return 1; /* avoid calling tlb_flush_mmu */
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        __tlb_remove_page(tlb, page);
+}
+
 #define pte_free_tlb(tlb, ptep, addr)   pte_free((tlb)->mm, ptep)
 #define pmd_free_tlb(tlb, pmdp, addr)   pmd_free((tlb)->mm, pmdp)
 #define pud_free_tlb(tlb, pudp, addr)   pud_free((tlb)->mm, pudp)
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index bb7d2702c2c9..3432008d2888 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -374,8 +374,9 @@
 #define __NR_clock_adjtime      361
 #define __NR_syncfs             362
 #define __NR_sendmmsg           363
+#define __NR_setns              364
 
-#define NR_syscalls 364
+#define NR_syscalls 365
 
 #ifdef __KERNEL__
 
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 46327cea1e5c..ec9898665f23 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -395,10 +395,11 @@
 #define __NR_clock_adjtime      372
 #define __NR_syncfs             373
 #define __NR_sendmmsg           374
+#define __NR_setns              375
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 375
+#define NR_syscalls 376
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 7c486f3e3a3c..39b051de4c7c 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -381,3 +381,4 @@ ENTRY(sys_call_table)
         .long sys_clock_adjtime
         .long sys_syncfs
         .long sys_sendmmsg
+        .long sys_setns
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index ba1a737afe80..089c4d825d08 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -401,3 +401,4 @@ sys_call_table:
         .long sys_clock_adjtime
         .long sys_syncfs
         .long sys_sendmmsg
+        .long sys_setns                 /* 375 */
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index af4d46187a79..731c10ce67b5 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -66,7 +66,7 @@ SECTIONS
                 __machvec_end = .;
         }
 
-        PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+        PERCPU_SECTION(L1_CACHE_BYTES)
 
         /*
          * .exit.text is discarded at runtime, not link time, to deal with
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 0d3f912e3334..58a93fb3d965 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -28,7 +28,6 @@
 #include <asm/cache.h>
 #include <asm/sizes.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
 pgd_t swapper_pg_dir[PTRS_PER_PGD];
 
 void __init generic_mem_init(void)
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 63a027c9ada5..af32e17fa170 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -190,14 +190,6 @@ config RWSEM_XCHGADD_ALGORITHM
         bool
         default y if SPARC64
 
-config GENERIC_FIND_NEXT_BIT
-        bool
-        default y
-
-config GENERIC_FIND_BIT_LE
-        bool
-        default y
-
 config GENERIC_HWEIGHT
         bool
         default y if !ULTRA_HAS_POPULATION_COUNT
diff --git a/arch/sparc/Kconfig.debug b/arch/sparc/Kconfig.debug
index d9a795efbc04..6db35fba79fd 100644
--- a/arch/sparc/Kconfig.debug
+++ b/arch/sparc/Kconfig.debug
@@ -6,15 +6,6 @@ config TRACE_IRQFLAGS_SUPPORT
 
 source "lib/Kconfig.debug"
 
-config DEBUG_STACK_USAGE
-        bool "Enable stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config DEBUG_DCFLUSH
         bool "D-cache flush debugging"
         depends on SPARC64 && DEBUG_KERNEL
diff --git a/arch/sparc/include/asm/pgalloc_64.h b/arch/sparc/include/asm/pgalloc_64.h
index 5bdfa2c6e400..4e5e0878144f 100644
--- a/arch/sparc/include/asm/pgalloc_64.h
+++ b/arch/sparc/include/asm/pgalloc_64.h
@@ -78,4 +78,7 @@ static inline void check_pgt_cache(void)
         quicklist_trim(0, NULL, 25, 16);
 }
 
+#define __pte_free_tlb(tlb, pte, addr)  pte_free((tlb)->mm, pte)
+#define __pmd_free_tlb(tlb, pmd, addr)  pmd_free((tlb)->mm, pmd)
+
 #endif /* _SPARC64_PGALLOC_H */
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index b77128c80524..1e03c5a6b4f7 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -655,9 +655,11 @@ static inline int pte_special(pte_t pte)
 #define pte_unmap(pte)                  do { } while (0)
 
 /* Actual page table PTE updates.  */
-extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
+extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
+                          pte_t *ptep, pte_t orig, int fullmm);
 
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
+                             pte_t *ptep, pte_t pte, int fullmm)
 {
         pte_t orig = *ptep;
 
@@ -670,12 +672,19 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *p
          *             and SUN4V pte layout, so this inline test is fine.
          */
         if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
-                tlb_batch_add(mm, addr, ptep, orig);
+                tlb_batch_add(mm, addr, ptep, orig, fullmm);
 }
 
+#define set_pte_at(mm,addr,ptep,pte)    \
+        __set_pte_at((mm), (addr), (ptep), (pte), 0)
+
 #define pte_clear(mm,addr,ptep)         \
         set_pte_at((mm), (addr), (ptep), __pte(0UL))
 
+#define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
+#define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
+        __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
+
 #ifdef DCACHE_ALIASING_POSSIBLE
 #define __HAVE_ARCH_MOVE_PTE
 #define move_pte(pte, prot, old_addr, new_addr)                         \
diff --git a/arch/sparc/include/asm/tlb_64.h b/arch/sparc/include/asm/tlb_64.h
index dca406b9b6fc..190e18913cc6 100644
--- a/arch/sparc/include/asm/tlb_64.h
+++ b/arch/sparc/include/asm/tlb_64.h
@@ -7,66 +7,11 @@
 #include <asm/tlbflush.h>
 #include <asm/mmu_context.h>
 
-#define TLB_BATCH_NR    192
-
-/*
- * For UP we don't need to worry about TLB flush
- * and page free order so much..
- */
-#ifdef CONFIG_SMP
-  #define FREE_PTE_NR   506
-  #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
-#else
-  #define FREE_PTE_NR   1
-  #define tlb_fast_mode(bp) 1
-#endif
-
-struct mmu_gather {
-        struct mm_struct *mm;
-        unsigned int pages_nr;
-        unsigned int need_flush;
-        unsigned int fullmm;
-        unsigned int tlb_nr;
-        unsigned long vaddrs[TLB_BATCH_NR];
-        struct page *pages[FREE_PTE_NR];
-};
-
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 #ifdef CONFIG_SMP
 extern void smp_flush_tlb_pending(struct mm_struct *,
                                   unsigned long, unsigned long *);
 #endif
 
-extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
-extern void flush_tlb_pending(void);
-
-static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
-{
-        struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
-
-        BUG_ON(mp->tlb_nr);
-
-        mp->mm = mm;
-        mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
-        mp->fullmm = full_mm_flush;
-
-        return mp;
-}
-
-
-static inline void tlb_flush_mmu(struct mmu_gather *mp)
-{
-        if (!mp->fullmm)
-                flush_tlb_pending();
-        if (mp->need_flush) {
-                free_pages_and_swap_cache(mp->pages, mp->pages_nr);
-                mp->pages_nr = 0;
-                mp->need_flush = 0;
-        }
-
-}
-
 #ifdef CONFIG_SMP
 extern void smp_flush_tlb_mm(struct mm_struct *mm);
 #define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
@@ -74,38 +19,14 @@ extern void smp_flush_tlb_mm(struct mm_struct *mm);
 #define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
 #endif
 
-static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
-{
-        tlb_flush_mmu(mp);
-
-        if (mp->fullmm)
-                mp->fullmm = 0;
-
-        /* keep the page table cache within bounds */
-        check_pgt_cache();
-
-        put_cpu_var(mmu_gathers);
-}
-
-static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
-{
-        if (tlb_fast_mode(mp)) {
-                free_page_and_swap_cache(page);
-                return;
-        }
-        mp->need_flush = 1;
-        mp->pages[mp->pages_nr++] = page;
-        if (mp->pages_nr >= FREE_PTE_NR)
-                tlb_flush_mmu(mp);
-}
-
-#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
-#define pte_free_tlb(mp, ptepage, addr) pte_free((mp)->mm, ptepage)
-#define pmd_free_tlb(mp, pmdp, addr) pmd_free((mp)->mm, pmdp)
-#define pud_free_tlb(tlb,pudp, addr) __pud_free_tlb(tlb,pudp,addr)
+extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
+extern void flush_tlb_pending(void);
 
-#define tlb_migrate_finish(mm)  do { } while (0)
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma)   do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+#define tlb_flush(tlb)  flush_tlb_pending()
+
+#include <asm-generic/tlb.h>
 
 #endif /* _SPARC64_TLB_H */
diff --git a/arch/sparc/include/asm/tlbflush_64.h b/arch/sparc/include/asm/tlbflush_64.h
index fbb675dbe0c9..2ef463494153 100644
--- a/arch/sparc/include/asm/tlbflush_64.h
+++ b/arch/sparc/include/asm/tlbflush_64.h
@@ -5,9 +5,17 @@
 #include <asm/mmu_context.h>
 
 /* TSB flush operations. */
-struct mmu_gather;
+
+#define TLB_BATCH_NR    192
+
+struct tlb_batch {
+        struct mm_struct *mm;
+        unsigned long tlb_nr;
+        unsigned long vaddrs[TLB_BATCH_NR];
+};
+
 extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
-extern void flush_tsb_user(struct mmu_gather *mp);
+extern void flush_tsb_user(struct tlb_batch *tb);
 
 /* TLB flush operations. */
 
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index c5387ed0add8..6260d5deeabc 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -405,8 +405,9 @@
 #define __NR_clock_adjtime      334
 #define __NR_syncfs             335
 #define __NR_sendmmsg           336
+#define __NR_setns              337
 
-#define NR_syscalls             337
+#define NR_syscalls             338
 
 #ifdef __32bit_syscall_numbers__
 /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 3609bdee9ed2..3249d3f3234d 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -82,7 +82,7 @@ static void prom_sync_me(void)
                              "nop\n\t" : : "r" (&trapbase));
 
         prom_printf("PROM SYNC COMMAND...\n");
-        show_free_areas();
+        show_free_areas(0);
         if(current->pid != 0) {
                 local_irq_enable();
                 sys_sync();
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 332c83ff7701..6e492d59f6b1 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -84,4 +84,4 @@ sys_call_table:
 /*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
 /*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
 /*330*/ .long sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
-/*335*/ .long sys_syncfs, sys_sendmmsg
+/*335*/ .long sys_syncfs, sys_sendmmsg, sys_setns
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 43887ca0be0e..f566518483b5 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -85,7 +85,7 @@ sys_call_table32:
 /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv
         .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_event_open, compat_sys_recvmmsg, sys_fanotify_init
 /*330*/ .word sys32_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, compat_sys_open_by_handle_at, compat_sys_clock_adjtime
-        .word sys_syncfs, compat_sys_sendmmsg
+        .word sys_syncfs, compat_sys_sendmmsg, sys_setns
 
 #endif /* CONFIG_COMPAT */
 
@@ -162,4 +162,4 @@ sys_call_table:
 /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
         .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_event_open, sys_recvmmsg, sys_fanotify_init
 /*330*/ .word sys_fanotify_mark, sys_prlimit64, sys_name_to_handle_at, sys_open_by_handle_at, sys_clock_adjtime
-        .word sys_syncfs, sys_sendmmsg
+        .word sys_syncfs, sys_sendmmsg, sys_setns
diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S
index 92b557afe535..c0220759003e 100644
--- a/arch/sparc/kernel/vmlinux.lds.S
+++ b/arch/sparc/kernel/vmlinux.lds.S
@@ -108,7 +108,7 @@ SECTIONS
                 __sun4v_2insn_patch_end = .;
         }
 
-        PERCPU(SMP_CACHE_BYTES, PAGE_SIZE)
+        PERCPU_SECTION(SMP_CACHE_BYTES)
 
         . = ALIGN(PAGE_SIZE);
         __init_end = .;
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index 4c31e2b6e71b..ca217327e8d2 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -37,8 +37,6 @@
 #include <asm/prom.h>
 #include <asm/leon.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 unsigned long *sparc_valid_addr_bitmap;
 EXPORT_SYMBOL(sparc_valid_addr_bitmap);
 
@@ -78,7 +76,7 @@ void __init kmap_init(void)
 void show_mem(unsigned int filter)
 {
         printk("Mem-info:\n");
-        show_free_areas();
+        show_free_areas(filter);
         printk("Free swap:       %6ldkB\n",
                nr_swap_pages << (PAGE_SHIFT-10));
         printk("%ld pages of RAM\n", totalram_pages);
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index d8f21e24a82f..b1f279cd00bf 100644
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
@@ -19,33 +19,34 @@
 
 /* Heavily inspired by the ppc64 code.  */
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+static DEFINE_PER_CPU(struct tlb_batch, tlb_batch);
 
 void flush_tlb_pending(void)
 {
-        struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
+        struct tlb_batch *tb = &get_cpu_var(tlb_batch);
 
-        if (mp->tlb_nr) {
-                flush_tsb_user(mp);
+        if (tb->tlb_nr) {
+                flush_tsb_user(tb);
 
-                if (CTX_VALID(mp->mm->context)) {
+                if (CTX_VALID(tb->mm->context)) {
 #ifdef CONFIG_SMP
-                        smp_flush_tlb_pending(mp->mm, mp->tlb_nr,
-                                              &mp->vaddrs[0]);
+                        smp_flush_tlb_pending(tb->mm, tb->tlb_nr,
+                                              &tb->vaddrs[0]);
 #else
-                        __flush_tlb_pending(CTX_HWBITS(mp->mm->context),
-                                            mp->tlb_nr, &mp->vaddrs[0]);
+                        __flush_tlb_pending(CTX_HWBITS(tb->mm->context),
+                                            tb->tlb_nr, &tb->vaddrs[0]);
 #endif
                 }
-                mp->tlb_nr = 0;
+                tb->tlb_nr = 0;
         }
 
-        put_cpu_var(mmu_gathers);
+        put_cpu_var(tlb_batch);
 }
 
-void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
+void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
+                   pte_t *ptep, pte_t orig, int fullmm)
 {
-        struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
+        struct tlb_batch *tb = &get_cpu_var(tlb_batch);
         unsigned long nr;
 
         vaddr &= PAGE_MASK;
@@ -77,21 +78,25 @@ void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t
 
 no_cache_flush:
 
-        if (mp->fullmm)
+        if (fullmm) {
+                put_cpu_var(tlb_batch);
                 return;
+        }
 
-        nr = mp->tlb_nr;
+        nr = tb->tlb_nr;
 
-        if (unlikely(nr != 0 && mm != mp->mm)) {
+        if (unlikely(nr != 0 && mm != tb->mm)) {
                 flush_tlb_pending();
                 nr = 0;
         }
 
         if (nr == 0)
-                mp->mm = mm;
+                tb->mm = mm;
 
-        mp->vaddrs[nr] = vaddr;
-        mp->tlb_nr = ++nr;
+        tb->vaddrs[nr] = vaddr;
+        tb->tlb_nr = ++nr;
         if (nr >= TLB_BATCH_NR)
                 flush_tlb_pending();
+
+        put_cpu_var(tlb_batch);
 }
diff --git a/arch/sparc/mm/tsb.c b/arch/sparc/mm/tsb.c
index 101d7c82870b..948461513499 100644
--- a/arch/sparc/mm/tsb.c
+++ b/arch/sparc/mm/tsb.c
@@ -47,12 +47,13 @@ void flush_tsb_kernel_range(unsigned long start, unsigned long end)
         }
 }
 
-static void __flush_tsb_one(struct mmu_gather *mp, unsigned long hash_shift, unsigned long tsb, unsigned long nentries)
+static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift,
+                            unsigned long tsb, unsigned long nentries)
 {
         unsigned long i;
 
-        for (i = 0; i < mp->tlb_nr; i++) {
-                unsigned long v = mp->vaddrs[i];
+        for (i = 0; i < tb->tlb_nr; i++) {
+                unsigned long v = tb->vaddrs[i];
                 unsigned long tag, ent, hash;
 
                 v &= ~0x1UL;
@@ -65,9 +66,9 @@ static void __flush_tsb_one(struct mmu_gather *mp, unsigned long hash_shift, uns
         }
 }
 
-void flush_tsb_user(struct mmu_gather *mp)
+void flush_tsb_user(struct tlb_batch *tb)
 {
-        struct mm_struct *mm = mp->mm;
+        struct mm_struct *mm = tb->mm;
         unsigned long nentries, base, flags;
 
         spin_lock_irqsave(&mm->context.lock, flags);
@@ -76,7 +77,7 @@ void flush_tsb_user(struct mmu_gather *mp)
         nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries;
         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
                 base = __pa(base);
-        __flush_tsb_one(mp, PAGE_SHIFT, base, nentries);
+        __flush_tsb_one(tb, PAGE_SHIFT, base, nentries);
 
 #ifdef CONFIG_HUGETLB_PAGE
         if (mm->context.tsb_block[MM_TSB_HUGE].tsb) {
@@ -84,7 +85,7 @@ void flush_tsb_user(struct mmu_gather *mp)
                 nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries;
                 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
                         base = __pa(base);
-                __flush_tsb_one(mp, HPAGE_SHIFT, base, nentries);
+                __flush_tsb_one(tb, HPAGE_SHIFT, base, nentries);
         }
 #endif
         spin_unlock_irqrestore(&mm->context.lock, flags);
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index e32b0c23c4c8..0249b8b4db54 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -5,13 +5,13 @@ config TILE
         def_bool y
         select HAVE_KVM if !TILEGX
         select GENERIC_FIND_FIRST_BIT
-        select GENERIC_FIND_NEXT_BIT
         select USE_GENERIC_SMP_HELPERS
         select CC_OPTIMIZE_FOR_SIZE
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select GENERIC_PENDING_IRQ if SMP
         select GENERIC_IRQ_SHOW
+        select SYS_HYPERVISOR
 
 # FIXME: investigate whether we need/want these options.
 #       select HAVE_IOREMAP_PROT
@@ -339,6 +339,14 @@ config NO_IOPORT
 
 source "drivers/pci/Kconfig"
 
+config HOTPLUG
+        bool "Support for hot-pluggable devices"
+        ---help---
+          Say Y here if you want to plug devices into your computer while
+          the system is running, and be able to use them quickly.  In many
+          cases, the devices can likewise be unplugged at any time too.
+          One well-known example of this is USB.
+
 source "drivers/pci/hotplug/Kconfig"
 
 endmenu
diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug
index 9bc161a02c71..ddbfc3322d7f 100644
--- a/arch/tile/Kconfig.debug
+++ b/arch/tile/Kconfig.debug
@@ -21,15 +21,6 @@ config DEBUG_STACKOVERFLOW
           This option will cause messages to be printed if free stack space
           drops below a certain limit.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
 config DEBUG_EXTRA_FLAGS
         string "Additional compiler arguments when building with '-g'"
         depends on DEBUG_INFO
diff --git a/arch/tile/configs/tile_defconfig b/arch/tile/configs/tile_defconfig
deleted file mode 100644
index 0fe54445fda5..000000000000
--- a/arch/tile/configs/tile_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
-CONFIG_EXPERT=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_HZ_100=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_IPV6=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=y
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_INTF_SYSFS is not set
-# CONFIG_RTC_INTF_PROC is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_FUSE_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_STACKOVERFLOW=y
-CONFIG_DEBUG_EXTRA_FLAGS="-femit-struct-debug-baseonly"
diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig
new file mode 100644
index 000000000000..09f1c7fad8bf
--- /dev/null
+++ b/arch/tile/configs/tilegx_defconfig
@@ -0,0 +1,1833 @@
+#
+# Automatically generated make config: don't edit
+# Linux/tilegx 2.6.39-rc5 Kernel Configuration
+# Wed May  4 11:08:04 2011
+#
+CONFIG_TILE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_HAVE_ARCH_ALLOC_REMAP=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_DEFAULT_MIGRATION_COST=10000000
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SMP=y
+# CONFIG_DEBUG_COPY_FROM_USER is not set
+CONFIG_HVC_TILE=y
+CONFIG_TILEGX=y
+CONFIG_64BIT=y
+CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tilegx_defconfig"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_FHANDLE is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PENDING_IRQ=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=64
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_NS=y
+# CONFIG_CGROUP_FREEZER is not set
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_BLK_DEV_THROTTLING is not set
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_PADATA=y
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+
+#
+# Tilera-specific configuration
+#
+CONFIG_NR_CPUS=100
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+# CONFIG_KEXEC is not set
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+# CONFIG_HIGHMEM is not set
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=2
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_DISCONTIGMEM_MANUAL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_VMALLOC_RESERVE=0x1000000
+CONFIG_HARDWALL=y
+CONFIG_KERNEL_PL=1
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_NO_IOMEM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_DEBUG=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_KCORE_ELF=y
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_ROUTE_CLASSID=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_IPV6_SUBTREES is not set
+CONFIG_IPV6_MROUTE=y
+# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETLABEL=y
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+# CONFIG_NF_CONNTRACK_SNMP is not set
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_IP_SET is not set
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+# CONFIG_IP_VS_DH is not set
+# CONFIG_IP_VS_SH is not set
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+# CONFIG_IP_VS_NFCT is not set
+# CONFIG_IP_VS_PE_SIP is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+# CONFIG_NF_NAT is not set
+CONFIG_IP_NF_MANGLE=m
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+# CONFIG_RDS_DEBUG is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_EDSA=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
+CONFIG_NET_DSA_MV88E6131=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_PHONET=m
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+# CONFIG_NET_SCH_SFB is not set
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+# CONFIG_NET_ACT_CSUM is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_SX8=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_ATA_OVER_ETH=y
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+CONFIG_SCSI_SAS_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+CONFIG_SATA_SIL24=m
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MULTICORE_RAID456=y
+# CONFIG_MD_MULTIPATH is not set
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_DEBUG=y
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+# CONFIG_DM_RAID is not set
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_UEVENT=y
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_IFB=m
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+CONFIG_VETH=m
+# CONFIG_ARCNET is not set
+# CONFIG_MII is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+CONFIG_E1000E=m
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_STMMAC_ETH is not set
+# CONFIG_PCH_GBE is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+# CONFIG_TILE_NET is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_EG20T is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_TILE=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+CONFIG_JBD2_DEBUG=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_XFS_FS=m
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_HISTOGRAM is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=m
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+# CONFIG_SQUASHFS_XATTR is not set
+# CONFIG_SQUASHFS_LZO is not set
+# CONFIG_SQUASHFS_XZ is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_NFS_FSCACHE=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_DEPRECATED=y
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG2 is not set
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_FSCACHE=y
+# CONFIG_CIFS_ACL is not set
+CONFIG_CIFS_EXPERIMENTAL=y
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+CONFIG_DLM_DEBUG=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+CONFIG_HEADERS_CHECK=y
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_DEBUG_CREDENTIALS=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BUILD_DOCSRC is not set
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_ATOMIC64_SELFTEST is not set
+CONFIG_ASYNC_RAID6_TEST=m
+# CONFIG_SAMPLES is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_EXTRA_FLAGS=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+# CONFIG_SECURITY_PATH is not set
+CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_IMA is not set
+CONFIG_DEFAULT_SECURITY_SELINUX=y
+# CONFIG_DEFAULT_SECURITY_DAC is not set
+CONFIG_DEFAULT_SECURITY="selinux"
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=m
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/configs/tilepro_defconfig b/arch/tile/configs/tilepro_defconfig
new file mode 100644
index 000000000000..f58dc362b944
--- /dev/null
+++ b/arch/tile/configs/tilepro_defconfig
@@ -0,0 +1,1163 @@
+#
+# Automatically generated make config: don't edit
+# Linux/tile 2.6.39-rc5 Kernel Configuration
+# Tue May  3 09:15:02 2011
+#
+CONFIG_TILE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_HAVE_ARCH_ALLOC_REMAP=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_DEFAULT_MIGRATION_COST=10000000
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SMP=y
+# CONFIG_DEBUG_COPY_FROM_USER is not set
+CONFIG_HVC_TILE=y
+# CONFIG_TILEGX is not set
+CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tile_defconfig"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PENDING_IRQ=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+
+#
+# Tilera-specific configuration
+#
+CONFIG_NR_CPUS=64
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+# CONFIG_KEXEC is not set
+CONFIG_HIGHMEM=y
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=2
+# CONFIG_VMSPLIT_3_75G is not set
+# CONFIG_VMSPLIT_3_5G is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2_75G is not set
+# CONFIG_VMSPLIT_2_5G is not set
+# CONFIG_VMSPLIT_2_25G is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_DISCONTIGMEM_MANUAL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_VMALLOC_RESERVE=0x1000000
+CONFIG_HARDWALL=y
+CONFIG_KERNEL_PL=1
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_NO_IOMEM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_KCORE_ELF=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_MII is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_STMMAC_ETH is not set
+# CONFIG_PCH_GBE is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_TILE_NET=y
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC=y
+
+#
+# Reporting subsystems
+#
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_TILE=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+# CONFIG_RTC_INTF_SYSFS is not set
+# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_TILE=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_EXTRA_FLAGS="-femit-struct-debug-baseonly"
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+CONFIG_HAVE_KVM=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/include/arch/chip_tilegx.h b/arch/tile/include/arch/chip_tilegx.h
new file mode 100644
index 000000000000..ea8e4f2c9483
--- /dev/null
+++ b/arch/tile/include/arch/chip_tilegx.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+/*
+ * @file
+ * Global header file.
+ * This header file specifies defines for TILE-Gx.
+ */
+
+#ifndef __ARCH_CHIP_H__
+#define __ARCH_CHIP_H__
+
+/** Specify chip version.
+ * When possible, prefer the CHIP_xxx symbols below for future-proofing.
+ * This is intended for cross-compiling; native compilation should
+ * use the predefined __tile_chip__ symbol.
+ */
+#define TILE_CHIP 10
+
+/** Specify chip revision.
+ * This provides for the case of a respin of a particular chip type;
+ * the normal value for this symbol is "0".
+ * This is intended for cross-compiling; native compilation should
+ * use the predefined __tile_chip_rev__ symbol.
+ */
+#define TILE_CHIP_REV 0
+
+/** The name of this architecture. */
+#define CHIP_ARCH_NAME "tilegx"
+
+/** The ELF e_machine type for binaries for this chip. */
+#define CHIP_ELF_TYPE() EM_TILEGX
+
+/** The alternate ELF e_machine type for binaries for this chip. */
+#define CHIP_COMPAT_ELF_TYPE() 0x2597
+
+/** What is the native word size of the machine? */
+#define CHIP_WORD_SIZE() 64
+
+/** How many bits of a virtual address are used. Extra bits must be
+ * the sign extension of the low bits.
+ */
+#define CHIP_VA_WIDTH() 42
+
+/** How many bits are in a physical address? */
+#define CHIP_PA_WIDTH() 40
+
+/** Size of the L2 cache, in bytes. */
+#define CHIP_L2_CACHE_SIZE() 262144
+
+/** Log size of an L2 cache line in bytes. */
+#define CHIP_L2_LOG_LINE_SIZE() 6
+
+/** Size of an L2 cache line, in bytes. */
+#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
+
+/** Associativity of the L2 cache. */
+#define CHIP_L2_ASSOC() 8
+
+/** Size of the L1 data cache, in bytes. */
+#define CHIP_L1D_CACHE_SIZE() 32768
+
+/** Log size of an L1 data cache line in bytes. */
+#define CHIP_L1D_LOG_LINE_SIZE() 6
+
+/** Size of an L1 data cache line, in bytes. */
+#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
+
+/** Associativity of the L1 data cache. */
+#define CHIP_L1D_ASSOC() 2
+
+/** Size of the L1 instruction cache, in bytes. */
+#define CHIP_L1I_CACHE_SIZE() 32768
+
+/** Log size of an L1 instruction cache line in bytes. */
+#define CHIP_L1I_LOG_LINE_SIZE() 6
+
+/** Size of an L1 instruction cache line, in bytes. */
+#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
+
+/** Associativity of the L1 instruction cache. */
+#define CHIP_L1I_ASSOC() 2
+
+/** Stride with which flush instructions must be issued. */
+#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
+
+/** Stride with which inv instructions must be issued. */
+#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
+
+/** Stride with which finv instructions must be issued. */
+#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
+
+/** Can the local cache coherently cache data that is homed elsewhere? */
+#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
+
+/** How many simultaneous outstanding victims can the L2 cache have? */
+#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
+
+/** Does the TLB support the NC and NOALLOC bits? */
+#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
+
+/** Does the chip support hash-for-home caching? */
+#define CHIP_HAS_CBOX_HOME_MAP() 1
+
+/** Number of entries in the chip's home map tables. */
+#define CHIP_CBOX_HOME_MAP_SIZE() 128
+
+/** Do uncacheable requests miss in the cache regardless of whether
+ * there is matching data? */
+#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
+
+/** Does the mf instruction wait for victims? */
+#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
+
+/** Does the chip have an "inv" instruction that doesn't also flush? */
+#define CHIP_HAS_INV() 1
+
+/** Does the chip have a "wh64" instruction? */
+#define CHIP_HAS_WH64() 1
+
+/** Does this chip have a 'dword_align' instruction? */
+#define CHIP_HAS_DWORD_ALIGN() 0
+
+/** Number of performance counters. */
+#define CHIP_PERFORMANCE_COUNTERS() 4
+
+/** Does this chip have auxiliary performance counters? */
+#define CHIP_HAS_AUX_PERF_COUNTERS() 1
+
+/** Is the CBOX_MSR1 SPR supported? */
+#define CHIP_HAS_CBOX_MSR1() 0
+
+/** Is the TILE_RTF_HWM SPR supported? */
+#define CHIP_HAS_TILE_RTF_HWM() 1
+
+/** Is the TILE_WRITE_PENDING SPR supported? */
+#define CHIP_HAS_TILE_WRITE_PENDING() 0
+
+/** Is the PROC_STATUS SPR supported? */
+#define CHIP_HAS_PROC_STATUS_SPR() 1
+
+/** Is the DSTREAM_PF SPR supported? */
+#define CHIP_HAS_DSTREAM_PF() 1
+
+/** Log of the number of mshims we have. */
+#define CHIP_LOG_NUM_MSHIMS() 2
+
+/** Are the bases of the interrupt vector areas fixed? */
+#define CHIP_HAS_FIXED_INTVEC_BASE() 0
+
+/** Are the interrupt masks split up into 2 SPRs? */
+#define CHIP_HAS_SPLIT_INTR_MASK() 0
+
+/** Is the cycle count split up into 2 SPRs? */
+#define CHIP_HAS_SPLIT_CYCLE() 0
+
+/** Does the chip have a static network? */
+#define CHIP_HAS_SN() 0
+
+/** Does the chip have a static network processor? */
+#define CHIP_HAS_SN_PROC() 0
+
+/** Size of the L1 static network processor instruction cache, in bytes. */
+/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
+
+/** Does the chip have DMA support in each tile? */
+#define CHIP_HAS_TILE_DMA() 0
+
+/** Does the chip have the second revision of the directly accessible
+ *  dynamic networks?  This encapsulates a number of characteristics,
+ *  including the absence of the catch-all, the absence of inline message
+ *  tags, the absence of support for network context-switching, and so on.
+ */
+#define CHIP_HAS_REV1_XDN() 1
+
+/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
+#define CHIP_HAS_CMPEXCH() 1
+
+/** Does the chip have memory-mapped I/O support? */
+#define CHIP_HAS_MMIO() 1
+
+/** Does the chip have post-completion interrupts? */
+#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
+
+/** Does the chip have native single step support? */
+#define CHIP_HAS_SINGLE_STEP() 1
+
+#ifndef __OPEN_SOURCE__  /* features only relevant to hypervisor-level code */
+
+/** How many entries are present in the instruction TLB? */
+#define CHIP_ITLB_ENTRIES() 16
+
+/** How many entries are present in the data TLB? */
+#define CHIP_DTLB_ENTRIES() 32
+
+/** How many MAF entries does the XAUI shim have? */
+#define CHIP_XAUI_MAF_ENTRIES() 32
+
+/** Does the memory shim have a source-id table? */
+#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
+
+/** Does the L1 instruction cache clear on reset? */
+#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
+
+/** Does the chip come out of reset with valid coordinates on all tiles?
+ * Note that if defined, this also implies that the upper left is 1,1.
+ */
+#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
+
+/** Does the chip have unified packet formats? */
+#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
+
+/** Does the chip support write reordering? */
+#define CHIP_HAS_WRITE_REORDERING() 1
+
+/** Does the chip support Y-X routing as well as X-Y? */
+#define CHIP_HAS_Y_X_ROUTING() 1
+
+/** Is INTCTRL_3 managed with the correct MPL? */
+#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
+
+/** Is it possible to configure the chip to be big-endian? */
+#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
+
+/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
+#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
+
+/** Is the DIAG_TRACE_WAY SPR supported? */
+#define CHIP_HAS_DIAG_TRACE_WAY() 0
+
+/** Is the MEM_STRIPE_CONFIG SPR supported? */
+#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
+
+/** Are the TLB_PERF SPRs supported? */
+#define CHIP_HAS_TLB_PERF() 1
+
+/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
+#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
+
+/** Does the chip support rev1 DMA packets? */
+#define CHIP_HAS_REV1_DMA_PACKETS() 1
+
+/** Does the chip have an IPI shim? */
+#define CHIP_HAS_IPI() 1
+
+#endif /* !__OPEN_SOURCE__ */
+#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/icache.h b/arch/tile/include/arch/icache.h
index 5c87c9016338..762eafa8a11e 100644
--- a/arch/tile/include/arch/icache.h
+++ b/arch/tile/include/arch/icache.h
@@ -16,7 +16,7 @@
 /**
  * @file
  *
- * Support for invalidating bytes in the instruction
+ * Support for invalidating bytes in the instruction cache.
  */
 
 #ifndef __ARCH_ICACHE_H__
@@ -30,11 +30,10 @@
  *
  * @param addr The start of memory to be invalidated.
  * @param size The number of bytes to be invalidated.
- * @param page_size The system's page size, typically the PAGE_SIZE constant
- * in sys/page.h.  This value must be a power of two no larger
- * than the page containing the code to be invalidated. If the value
- * is smaller than the actual page size, this function will still
- * work, but may run slower than necessary.
+ * @param page_size The system's page size, e.g. getpagesize() in userspace.
+ * This value must be a power of two no larger than the page containing
+ * the code to be invalidated. If the value is smaller than the actual page
+ * size, this function will still work, but may run slower than necessary.
  */
 static __inline void
 invalidate_icache(const void* addr, unsigned long size,
diff --git a/arch/tile/include/arch/interrupts_64.h b/arch/tile/include/arch/interrupts_64.h
new file mode 100644
index 000000000000..5bb58b2e4e6f
--- /dev/null
+++ b/arch/tile/include/arch/interrupts_64.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef __ARCH_INTERRUPTS_H__
+#define __ARCH_INTERRUPTS_H__
+
+/** Mask for an interrupt. */
+#ifdef __ASSEMBLER__
+/* Note: must handle breaking interrupts into high and low words manually. */
+#define INT_MASK(intno) (1 << (intno))
+#else
+#define INT_MASK(intno) (1ULL << (intno))
+#endif
+
+
+/** Where a given interrupt executes */
+#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
+
+/** Where to store a vector for a given interrupt. */
+#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
+
+/** The base address of user-level interrupts. */
+#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
+
+
+/** Additional synthetic interrupt. */
+#define INT_BREAKPOINT (63)
+
+#define INT_MEM_ERROR    0
+#define INT_SINGLE_STEP_3    1
+#define INT_SINGLE_STEP_2    2
+#define INT_SINGLE_STEP_1    3
+#define INT_SINGLE_STEP_0    4
+#define INT_IDN_COMPLETE    5
+#define INT_UDN_COMPLETE    6
+#define INT_ITLB_MISS    7
+#define INT_ILL    8
+#define INT_GPV    9
+#define INT_IDN_ACCESS   10
+#define INT_UDN_ACCESS   11
+#define INT_SWINT_3   12
+#define INT_SWINT_2   13
+#define INT_SWINT_1   14
+#define INT_SWINT_0   15
+#define INT_ILL_TRANS   16
+#define INT_UNALIGN_DATA   17
+#define INT_DTLB_MISS   18
+#define INT_DTLB_ACCESS   19
+#define INT_IDN_FIREWALL   20
+#define INT_UDN_FIREWALL   21
+#define INT_TILE_TIMER   22
+#define INT_AUX_TILE_TIMER   23
+#define INT_IDN_TIMER   24
+#define INT_UDN_TIMER   25
+#define INT_IDN_AVAIL   26
+#define INT_UDN_AVAIL   27
+#define INT_IPI_3   28
+#define INT_IPI_2   29
+#define INT_IPI_1   30
+#define INT_IPI_0   31
+#define INT_PERF_COUNT   32
+#define INT_AUX_PERF_COUNT   33
+#define INT_INTCTRL_3   34
+#define INT_INTCTRL_2   35
+#define INT_INTCTRL_1   36
+#define INT_INTCTRL_0   37
+#define INT_BOOT_ACCESS   38
+#define INT_WORLD_ACCESS   39
+#define INT_I_ASID   40
+#define INT_D_ASID   41
+#define INT_DOUBLE_FAULT   42
+
+#define NUM_INTERRUPTS 43
+
+#ifndef __ASSEMBLER__
+#define QUEUED_INTERRUPTS ( \
+    INT_MASK(INT_MEM_ERROR) | \
+    INT_MASK(INT_IDN_COMPLETE) | \
+    INT_MASK(INT_UDN_COMPLETE) | \
+    INT_MASK(INT_IDN_FIREWALL) | \
+    INT_MASK(INT_UDN_FIREWALL) | \
+    INT_MASK(INT_TILE_TIMER) | \
+    INT_MASK(INT_AUX_TILE_TIMER) | \
+    INT_MASK(INT_IDN_TIMER) | \
+    INT_MASK(INT_UDN_TIMER) | \
+    INT_MASK(INT_IDN_AVAIL) | \
+    INT_MASK(INT_UDN_AVAIL) | \
+    INT_MASK(INT_IPI_3) | \
+    INT_MASK(INT_IPI_2) | \
+    INT_MASK(INT_IPI_1) | \
+    INT_MASK(INT_IPI_0) | \
+    INT_MASK(INT_PERF_COUNT) | \
+    INT_MASK(INT_AUX_PERF_COUNT) | \
+    INT_MASK(INT_INTCTRL_3) | \
+    INT_MASK(INT_INTCTRL_2) | \
+    INT_MASK(INT_INTCTRL_1) | \
+    INT_MASK(INT_INTCTRL_0) | \
+    INT_MASK(INT_BOOT_ACCESS) | \
+    INT_MASK(INT_WORLD_ACCESS) | \
+    INT_MASK(INT_I_ASID) | \
+    INT_MASK(INT_D_ASID) | \
+    INT_MASK(INT_DOUBLE_FAULT) | \
+    0)
+#define NONQUEUED_INTERRUPTS ( \
+    INT_MASK(INT_SINGLE_STEP_3) | \
+    INT_MASK(INT_SINGLE_STEP_2) | \
+    INT_MASK(INT_SINGLE_STEP_1) | \
+    INT_MASK(INT_SINGLE_STEP_0) | \
+    INT_MASK(INT_ITLB_MISS) | \
+    INT_MASK(INT_ILL) | \
+    INT_MASK(INT_GPV) | \
+    INT_MASK(INT_IDN_ACCESS) | \
+    INT_MASK(INT_UDN_ACCESS) | \
+    INT_MASK(INT_SWINT_3) | \
+    INT_MASK(INT_SWINT_2) | \
+    INT_MASK(INT_SWINT_1) | \
+    INT_MASK(INT_SWINT_0) | \
+    INT_MASK(INT_ILL_TRANS) | \
+    INT_MASK(INT_UNALIGN_DATA) | \
+    INT_MASK(INT_DTLB_MISS) | \
+    INT_MASK(INT_DTLB_ACCESS) | \
+    0)
+#define CRITICAL_MASKED_INTERRUPTS ( \
+    INT_MASK(INT_MEM_ERROR) | \
+    INT_MASK(INT_SINGLE_STEP_3) | \
+    INT_MASK(INT_SINGLE_STEP_2) | \
+    INT_MASK(INT_SINGLE_STEP_1) | \
+    INT_MASK(INT_SINGLE_STEP_0) | \
+    INT_MASK(INT_IDN_COMPLETE) | \
+    INT_MASK(INT_UDN_COMPLETE) | \
+    INT_MASK(INT_IDN_FIREWALL) | \
+    INT_MASK(INT_UDN_FIREWALL) | \
+    INT_MASK(INT_TILE_TIMER) | \
+    INT_MASK(INT_AUX_TILE_TIMER) | \
+    INT_MASK(INT_IDN_TIMER) | \
+    INT_MASK(INT_UDN_TIMER) | \
+    INT_MASK(INT_IDN_AVAIL) | \
+    INT_MASK(INT_UDN_AVAIL) | \
+    INT_MASK(INT_IPI_3) | \
+    INT_MASK(INT_IPI_2) | \
+    INT_MASK(INT_IPI_1) | \
+    INT_MASK(INT_IPI_0) | \
+    INT_MASK(INT_PERF_COUNT) | \
+    INT_MASK(INT_AUX_PERF_COUNT) | \
+    INT_MASK(INT_INTCTRL_3) | \
+    INT_MASK(INT_INTCTRL_2) | \
+    INT_MASK(INT_INTCTRL_1) | \
+    INT_MASK(INT_INTCTRL_0) | \
+    0)
+#define CRITICAL_UNMASKED_INTERRUPTS ( \
+    INT_MASK(INT_ITLB_MISS) | \
+    INT_MASK(INT_ILL) | \
+    INT_MASK(INT_GPV) | \
+    INT_MASK(INT_IDN_ACCESS) | \
+    INT_MASK(INT_UDN_ACCESS) | \
+    INT_MASK(INT_SWINT_3) | \
+    INT_MASK(INT_SWINT_2) | \
+    INT_MASK(INT_SWINT_1) | \
+    INT_MASK(INT_SWINT_0) | \
+    INT_MASK(INT_ILL_TRANS) | \
+    INT_MASK(INT_UNALIGN_DATA) | \
+    INT_MASK(INT_DTLB_MISS) | \
+    INT_MASK(INT_DTLB_ACCESS) | \
+    INT_MASK(INT_BOOT_ACCESS) | \
+    INT_MASK(INT_WORLD_ACCESS) | \
+    INT_MASK(INT_I_ASID) | \
+    INT_MASK(INT_D_ASID) | \
+    INT_MASK(INT_DOUBLE_FAULT) | \
+    0)
+#define MASKABLE_INTERRUPTS ( \
+    INT_MASK(INT_MEM_ERROR) | \
+    INT_MASK(INT_SINGLE_STEP_3) | \
+    INT_MASK(INT_SINGLE_STEP_2) | \
+    INT_MASK(INT_SINGLE_STEP_1) | \
+    INT_MASK(INT_SINGLE_STEP_0) | \
+    INT_MASK(INT_IDN_COMPLETE) | \
+    INT_MASK(INT_UDN_COMPLETE) | \
+    INT_MASK(INT_IDN_FIREWALL) | \
+    INT_MASK(INT_UDN_FIREWALL) | \
+    INT_MASK(INT_TILE_TIMER) | \
+    INT_MASK(INT_AUX_TILE_TIMER) | \
+    INT_MASK(INT_IDN_TIMER) | \
+    INT_MASK(INT_UDN_TIMER) | \
+    INT_MASK(INT_IDN_AVAIL) | \
+    INT_MASK(INT_UDN_AVAIL) | \
+    INT_MASK(INT_IPI_3) | \
+    INT_MASK(INT_IPI_2) | \
+    INT_MASK(INT_IPI_1) | \
+    INT_MASK(INT_IPI_0) | \
+    INT_MASK(INT_PERF_COUNT) | \
+    INT_MASK(INT_AUX_PERF_COUNT) | \
+    INT_MASK(INT_INTCTRL_3) | \
+    INT_MASK(INT_INTCTRL_2) | \
+    INT_MASK(INT_INTCTRL_1) | \
+    INT_MASK(INT_INTCTRL_0) | \
+    0)
+#define UNMASKABLE_INTERRUPTS ( \
+    INT_MASK(INT_ITLB_MISS) | \
+    INT_MASK(INT_ILL) | \
+    INT_MASK(INT_GPV) | \
+    INT_MASK(INT_IDN_ACCESS) | \
+    INT_MASK(INT_UDN_ACCESS) | \
+    INT_MASK(INT_SWINT_3) | \
+    INT_MASK(INT_SWINT_2) | \
+    INT_MASK(INT_SWINT_1) | \
+    INT_MASK(INT_SWINT_0) | \
+    INT_MASK(INT_ILL_TRANS) | \
+    INT_MASK(INT_UNALIGN_DATA) | \
+    INT_MASK(INT_DTLB_MISS) | \
+    INT_MASK(INT_DTLB_ACCESS) | \
+    INT_MASK(INT_BOOT_ACCESS) | \
+    INT_MASK(INT_WORLD_ACCESS) | \
+    INT_MASK(INT_I_ASID) | \
+    INT_MASK(INT_D_ASID) | \
+    INT_MASK(INT_DOUBLE_FAULT) | \
+    0)
+#define SYNC_INTERRUPTS ( \
+    INT_MASK(INT_SINGLE_STEP_3) | \
+    INT_MASK(INT_SINGLE_STEP_2) | \
+    INT_MASK(INT_SINGLE_STEP_1) | \
+    INT_MASK(INT_SINGLE_STEP_0) | \
+    INT_MASK(INT_IDN_COMPLETE) | \
+    INT_MASK(INT_UDN_COMPLETE) | \
+    INT_MASK(INT_ITLB_MISS) | \
+    INT_MASK(INT_ILL) | \
+    INT_MASK(INT_GPV) | \
+    INT_MASK(INT_IDN_ACCESS) | \
+    INT_MASK(INT_UDN_ACCESS) | \
+    INT_MASK(INT_SWINT_3) | \
+    INT_MASK(INT_SWINT_2) | \
+    INT_MASK(INT_SWINT_1) | \
+    INT_MASK(INT_SWINT_0) | \
+    INT_MASK(INT_ILL_TRANS) | \
+    INT_MASK(INT_UNALIGN_DATA) | \
+    INT_MASK(INT_DTLB_MISS) | \
+    INT_MASK(INT_DTLB_ACCESS) | \
+    0)
+#define NON_SYNC_INTERRUPTS ( \
+    INT_MASK(INT_MEM_ERROR) | \
+    INT_MASK(INT_IDN_FIREWALL) | \
+    INT_MASK(INT_UDN_FIREWALL) | \
+    INT_MASK(INT_TILE_TIMER) | \
+    INT_MASK(INT_AUX_TILE_TIMER) | \
+    INT_MASK(INT_IDN_TIMER) | \
+    INT_MASK(INT_UDN_TIMER) | \
+    INT_MASK(INT_IDN_AVAIL) | \
+    INT_MASK(INT_UDN_AVAIL) | \
+    INT_MASK(INT_IPI_3) | \
+    INT_MASK(INT_IPI_2) | \
+    INT_MASK(INT_IPI_1) | \
+    INT_MASK(INT_IPI_0) | \
+    INT_MASK(INT_PERF_COUNT) | \
+    INT_MASK(INT_AUX_PERF_COUNT) | \
+    INT_MASK(INT_INTCTRL_3) | \
+    INT_MASK(INT_INTCTRL_2) | \
+    INT_MASK(INT_INTCTRL_1) | \
+    INT_MASK(INT_INTCTRL_0) | \
+    INT_MASK(INT_BOOT_ACCESS) | \
+    INT_MASK(INT_WORLD_ACCESS) | \
+    INT_MASK(INT_I_ASID) | \
+    INT_MASK(INT_D_ASID) | \
+    INT_MASK(INT_DOUBLE_FAULT) | \
+    0)
+#endif /* !__ASSEMBLER__ */
+#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/spr_def.h b/arch/tile/include/arch/spr_def.h
index 442fcba0d122..f548efeb2de3 100644
--- a/arch/tile/include/arch/spr_def.h
+++ b/arch/tile/include/arch/spr_def.h
@@ -12,6 +12,15 @@
  *   more details.
  */
 
+/* Include the proper base SPR definition file. */
+#ifdef __tilegx__
+#include <arch/spr_def_64.h>
+#else
+#include <arch/spr_def_32.h>
+#endif
+
+#ifdef __KERNEL__
+
 /*
  * In addition to including the proper base SPR definition file, depending
  * on machine architecture, this file defines several macros which allow
@@ -29,7 +38,6 @@
 #define _concat4(a, b, c, d)  __concat4(a, b, c, d)
 
 #ifdef __tilegx__
-#include <arch/spr_def_64.h>
 
 /* TILE-Gx dependent, protection-level dependent SPRs. */
 
@@ -65,7 +73,6 @@
         _concat4(INT_SINGLE_STEP_, CONFIG_KERNEL_PL,,)
 
 #else
-#include <arch/spr_def_32.h>
 
 /* TILEPro dependent, protection-level dependent SPRs. */
 
@@ -102,3 +109,5 @@
         _concat4(SPR_INTCTRL_, CONFIG_KERNEL_PL, _STATUS,)
 #define INT_INTCTRL_K \
         _concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,)
+
+#endif /* __KERNEL__ */
diff --git a/arch/tile/include/arch/spr_def_64.h b/arch/tile/include/arch/spr_def_64.h
new file mode 100644
index 000000000000..cd3e5f95d5fd
--- /dev/null
+++ b/arch/tile/include/arch/spr_def_64.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef __DOXYGEN__
+
+#ifndef __ARCH_SPR_DEF_H__
+#define __ARCH_SPR_DEF_H__
+
+#define SPR_AUX_PERF_COUNT_0 0x2105
+#define SPR_AUX_PERF_COUNT_1 0x2106
+#define SPR_AUX_PERF_COUNT_CTL 0x2107
+#define SPR_AUX_PERF_COUNT_STS 0x2108
+#define SPR_CMPEXCH_VALUE 0x2780
+#define SPR_CYCLE 0x2781
+#define SPR_DONE 0x2705
+#define SPR_DSTREAM_PF 0x2706
+#define SPR_EVENT_BEGIN 0x2782
+#define SPR_EVENT_END 0x2783
+#define SPR_EX_CONTEXT_0_0 0x2580
+#define SPR_EX_CONTEXT_0_1 0x2581
+#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_0_1__PL_MASK  0x3
+#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_0_1__ICS_MASK  0x4
+#define SPR_EX_CONTEXT_1_0 0x2480
+#define SPR_EX_CONTEXT_1_1 0x2481
+#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_1_1__PL_MASK  0x3
+#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_1_1__ICS_MASK  0x4
+#define SPR_EX_CONTEXT_2_0 0x2380
+#define SPR_EX_CONTEXT_2_1 0x2381
+#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_2_1__PL_MASK  0x3
+#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_2_1__ICS_MASK  0x4
+#define SPR_FAIL 0x2707
+#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
+#define SPR_INTCTRL_0_STATUS 0x2505
+#define SPR_INTCTRL_1_STATUS 0x2405
+#define SPR_INTCTRL_2_STATUS 0x2305
+#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
+#define SPR_INTERRUPT_MASK_0 0x2506
+#define SPR_INTERRUPT_MASK_1 0x2406
+#define SPR_INTERRUPT_MASK_2 0x2306
+#define SPR_INTERRUPT_MASK_RESET_0 0x2507
+#define SPR_INTERRUPT_MASK_RESET_1 0x2407
+#define SPR_INTERRUPT_MASK_RESET_2 0x2307
+#define SPR_INTERRUPT_MASK_SET_0 0x2508
+#define SPR_INTERRUPT_MASK_SET_1 0x2408
+#define SPR_INTERRUPT_MASK_SET_2 0x2308
+#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
+#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
+#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
+#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
+#define SPR_IPI_EVENT_0 0x1f05
+#define SPR_IPI_EVENT_1 0x1e05
+#define SPR_IPI_EVENT_2 0x1d05
+#define SPR_IPI_EVENT_RESET_0 0x1f06
+#define SPR_IPI_EVENT_RESET_1 0x1e06
+#define SPR_IPI_EVENT_RESET_2 0x1d06
+#define SPR_IPI_EVENT_SET_0 0x1f07
+#define SPR_IPI_EVENT_SET_1 0x1e07
+#define SPR_IPI_EVENT_SET_2 0x1d07
+#define SPR_IPI_MASK_0 0x1f08
+#define SPR_IPI_MASK_1 0x1e08
+#define SPR_IPI_MASK_2 0x1d08
+#define SPR_IPI_MASK_RESET_0 0x1f09
+#define SPR_IPI_MASK_RESET_1 0x1e09
+#define SPR_IPI_MASK_RESET_2 0x1d09
+#define SPR_IPI_MASK_SET_0 0x1f0a
+#define SPR_IPI_MASK_SET_1 0x1e0a
+#define SPR_IPI_MASK_SET_2 0x1d0a
+#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
+#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
+#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
+#define SPR_MPL_INTCTRL_0_SET_0 0x2500
+#define SPR_MPL_INTCTRL_0_SET_1 0x2501
+#define SPR_MPL_INTCTRL_0_SET_2 0x2502
+#define SPR_MPL_INTCTRL_1_SET_0 0x2400
+#define SPR_MPL_INTCTRL_1_SET_1 0x2401
+#define SPR_MPL_INTCTRL_1_SET_2 0x2402
+#define SPR_MPL_INTCTRL_2_SET_0 0x2300
+#define SPR_MPL_INTCTRL_2_SET_1 0x2301
+#define SPR_MPL_INTCTRL_2_SET_2 0x2302
+#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
+#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
+#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
+#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
+#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
+#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
+#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
+#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
+#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
+#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
+#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
+#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
+#define SPR_MPL_UDN_TIMER_SET_0 0x1900
+#define SPR_MPL_UDN_TIMER_SET_1 0x1901
+#define SPR_MPL_UDN_TIMER_SET_2 0x1902
+#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
+#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
+#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
+#define SPR_PASS 0x2709
+#define SPR_PERF_COUNT_0 0x2005
+#define SPR_PERF_COUNT_1 0x2006
+#define SPR_PERF_COUNT_CTL 0x2007
+#define SPR_PERF_COUNT_DN_CTL 0x2008
+#define SPR_PERF_COUNT_STS 0x2009
+#define SPR_PROC_STATUS 0x2784
+#define SPR_SIM_CONTROL 0x2785
+#define SPR_SINGLE_STEP_CONTROL_0 0x0405
+#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK  0x1
+#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK  0x2
+#define SPR_SINGLE_STEP_CONTROL_1 0x0305
+#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK  0x1
+#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK  0x2
+#define SPR_SINGLE_STEP_CONTROL_2 0x0205
+#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK  0x1
+#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK  0x2
+#define SPR_SINGLE_STEP_EN_0_0 0x250a
+#define SPR_SINGLE_STEP_EN_0_1 0x240a
+#define SPR_SINGLE_STEP_EN_0_2 0x230a
+#define SPR_SINGLE_STEP_EN_1_0 0x250b
+#define SPR_SINGLE_STEP_EN_1_1 0x240b
+#define SPR_SINGLE_STEP_EN_1_2 0x230b
+#define SPR_SINGLE_STEP_EN_2_0 0x250c
+#define SPR_SINGLE_STEP_EN_2_1 0x240c
+#define SPR_SINGLE_STEP_EN_2_2 0x230c
+#define SPR_SYSTEM_SAVE_0_0 0x2582
+#define SPR_SYSTEM_SAVE_0_1 0x2583
+#define SPR_SYSTEM_SAVE_0_2 0x2584
+#define SPR_SYSTEM_SAVE_0_3 0x2585
+#define SPR_SYSTEM_SAVE_1_0 0x2482
+#define SPR_SYSTEM_SAVE_1_1 0x2483
+#define SPR_SYSTEM_SAVE_1_2 0x2484
+#define SPR_SYSTEM_SAVE_1_3 0x2485
+#define SPR_SYSTEM_SAVE_2_0 0x2382
+#define SPR_SYSTEM_SAVE_2_1 0x2383
+#define SPR_SYSTEM_SAVE_2_2 0x2384
+#define SPR_SYSTEM_SAVE_2_3 0x2385
+#define SPR_TILE_COORD 0x270b
+#define SPR_TILE_RTF_HWM 0x270c
+#define SPR_TILE_TIMER_CONTROL 0x1605
+#define SPR_UDN_AVAIL_EN 0x1b05
+#define SPR_UDN_DATA_AVAIL 0x0b80
+#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
+#define SPR_UDN_DEMUX_COUNT_0 0x0b05
+#define SPR_UDN_DEMUX_COUNT_1 0x0b06
+#define SPR_UDN_DEMUX_COUNT_2 0x0b07
+#define SPR_UDN_DEMUX_COUNT_3 0x0b08
+#define SPR_UDN_DIRECTION_PROTECT 0x1505
+
+#endif /* !defined(__ARCH_SPR_DEF_H__) */
+
+#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
index 75a16028a952..739cfe0499d1 100644
--- a/arch/tile/include/asm/atomic.h
+++ b/arch/tile/include/asm/atomic.h
@@ -130,17 +130,52 @@ static inline int atomic_read(const atomic_t *v)
  */
 #define atomic_inc_not_zero(v)          atomic_add_unless((v), 1, 0)
 
-
-/*
- * We define xchg() and cmpxchg() in the included headers.
- * Note that we do not define __HAVE_ARCH_CMPXCHG, since that would imply
- * that cmpxchg() is an efficient operation, which is not particularly true.
- */
-
 /* Nonexistent functions intended to cause link errors. */
 extern unsigned long __xchg_called_with_bad_pointer(void);
 extern unsigned long __cmpxchg_called_with_bad_pointer(void);
 
+#define xchg(ptr, x)                                                    \
+        ({                                                              \
+                typeof(*(ptr)) __x;                                     \
+                switch (sizeof(*(ptr))) {                               \
+                case 4:                                                 \
+                        __x = (typeof(__x))(typeof(__x-__x))atomic_xchg( \
+                                (atomic_t *)(ptr),                      \
+                                (u32)(typeof((x)-(x)))(x));             \
+                        break;                                          \
+                case 8:                                                 \
+                        __x = (typeof(__x))(typeof(__x-__x))atomic64_xchg( \
+                                (atomic64_t *)(ptr),                    \
+                                (u64)(typeof((x)-(x)))(x));             \
+                        break;                                          \
+                default:                                                \
+                        __xchg_called_with_bad_pointer();               \
+                }                                                       \
+                __x;                                                    \
+        })
+
+#define cmpxchg(ptr, o, n)                                              \
+        ({                                                              \
+                typeof(*(ptr)) __x;                                     \
+                switch (sizeof(*(ptr))) {                               \
+                case 4:                                                 \
+                        __x = (typeof(__x))(typeof(__x-__x))atomic_cmpxchg( \
+                                (atomic_t *)(ptr),                      \
+                                (u32)(typeof((o)-(o)))(o),              \
+                                (u32)(typeof((n)-(n)))(n));             \
+                        break;                                          \
+                case 8:                                                 \
+                        __x = (typeof(__x))(typeof(__x-__x))atomic64_cmpxchg( \
+                                (atomic64_t *)(ptr),                    \
+                                (u64)(typeof((o)-(o)))(o),              \
+                                (u64)(typeof((n)-(n)))(n));             \
+                        break;                                          \
+                default:                                                \
+                        __cmpxchg_called_with_bad_pointer();            \
+                }                                                       \
+                __x;                                                    \
+        })
+
 #define tas(ptr) (xchg((ptr), 1))
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h
index ed359aee8837..92a8bee32311 100644
--- a/arch/tile/include/asm/atomic_32.h
+++ b/arch/tile/include/asm/atomic_32.h
@@ -110,16 +110,6 @@ static inline void atomic_set(atomic_t *v, int n)
         _atomic_xchg(v, n);
 }
 
-#define xchg(ptr, x) ((typeof(*(ptr))) \
-  ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
-   atomic_xchg((atomic_t *)(ptr), (long)(x)) : \
-   __xchg_called_with_bad_pointer()))
-
-#define cmpxchg(ptr, o, n) ((typeof(*(ptr))) \
-  ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
-   atomic_cmpxchg((atomic_t *)(ptr), (long)(o), (long)(n)) : \
-   __cmpxchg_called_with_bad_pointer()))
-
 /* A 64bit atomic type */
 
 typedef struct {
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
new file mode 100644
index 000000000000..1c1e60d8ccb6
--- /dev/null
+++ b/arch/tile/include/asm/atomic_64.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * Do not include directly; use <asm/atomic.h>.
+ */
+
+#ifndef _ASM_TILE_ATOMIC_64_H
+#define _ASM_TILE_ATOMIC_64_H
+
+#ifndef __ASSEMBLY__
+
+#include <arch/spr_def.h>
+
+/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
+
+#define atomic_set(v, i) ((v)->counter = (i))
+
+/*
+ * The smp_mb() operations throughout are to support the fact that
+ * Linux requires memory barriers before and after the operation,
+ * on any routine which updates memory and returns a value.
+ */
+
+static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
+{
+        int val;
+        __insn_mtspr(SPR_CMPEXCH_VALUE, o);
+        smp_mb();  /* barrier for proper semantics */
+        val = __insn_cmpexch4((void *)&v->counter, n);
+        smp_mb();  /* barrier for proper semantics */
+        return val;
+}
+
+static inline int atomic_xchg(atomic_t *v, int n)
+{
+        int val;
+        smp_mb();  /* barrier for proper semantics */
+        val = __insn_exch4((void *)&v->counter, n);
+        smp_mb();  /* barrier for proper semantics */
+        return val;
+}
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+        __insn_fetchadd4((void *)&v->counter, i);
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        int val;
+        smp_mb();  /* barrier for proper semantics */
+        val = __insn_fetchadd4((void *)&v->counter, i) + i;
+        barrier();  /* the "+ i" above will wait on memory */
+        return val;
+}
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int guess, oldval = v->counter;
+        do {
+                if (oldval == u)
+                        break;
+                guess = oldval;
+                oldval = atomic_cmpxchg(v, guess, guess + a);
+        } while (guess != oldval);
+        return oldval != u;
+}
+
+/* Now the true 64-bit operations. */
+
+#define ATOMIC64_INIT(i)        { (i) }
+
+#define atomic64_read(v)                ((v)->counter)
+#define atomic64_set(v, i) ((v)->counter = (i))
+
+static inline long atomic64_cmpxchg(atomic64_t *v, long o, long n)
+{
+        long val;
+        smp_mb();  /* barrier for proper semantics */
+        __insn_mtspr(SPR_CMPEXCH_VALUE, o);
+        val = __insn_cmpexch((void *)&v->counter, n);
+        smp_mb();  /* barrier for proper semantics */
+        return val;
+}
+
+static inline long atomic64_xchg(atomic64_t *v, long n)
+{
+        long val;
+        smp_mb();  /* barrier for proper semantics */
+        val = __insn_exch((void *)&v->counter, n);
+        smp_mb();  /* barrier for proper semantics */
+        return val;
+}
+
+static inline void atomic64_add(long i, atomic64_t *v)
+{
+        __insn_fetchadd((void *)&v->counter, i);
+}
+
+static inline long atomic64_add_return(long i, atomic64_t *v)
+{
+        int val;
+        smp_mb();  /* barrier for proper semantics */
+        val = __insn_fetchadd((void *)&v->counter, i) + i;
+        barrier();  /* the "+ i" above will wait on memory */
+        return val;
+}
+
+static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long guess, oldval = v->counter;
+        do {
+                if (oldval == u)
+                        break;
+                guess = oldval;
+                oldval = atomic64_cmpxchg(v, guess, guess + a);
+        } while (guess != oldval);
+        return oldval != u;
+}
+
+#define atomic64_sub_return(i, v)       atomic64_add_return(-(i), (v))
+#define atomic64_sub(i, v)              atomic64_add(-(i), (v))
+#define atomic64_inc_return(v)          atomic64_add_return(1, (v))
+#define atomic64_dec_return(v)          atomic64_sub_return(1, (v))
+#define atomic64_inc(v)                 atomic64_add(1, (v))
+#define atomic64_dec(v)                 atomic64_sub(1, (v))
+
+#define atomic64_inc_and_test(v)        (atomic64_inc_return(v) == 0)
+#define atomic64_dec_and_test(v)        (atomic64_dec_return(v) == 0)
+#define atomic64_sub_and_test(i, v)     (atomic64_sub_return((i), (v)) == 0)
+#define atomic64_add_negative(i, v)     (atomic64_add_return((i), (v)) < 0)
+
+#define atomic64_inc_not_zero(v)        atomic64_add_unless((v), 1, 0)
+
+/* Atomic dec and inc don't implement barrier, so provide them if needed. */
+#define smp_mb__before_atomic_dec()     smp_mb()
+#define smp_mb__after_atomic_dec()      smp_mb()
+#define smp_mb__before_atomic_inc()     smp_mb()
+#define smp_mb__after_atomic_inc()      smp_mb()
+
+/* Define this to indicate that cmpxchg is an efficient operation. */
+#define __HAVE_ARCH_CMPXCHG
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_TILE_ATOMIC_64_H */
diff --git a/arch/tile/include/asm/backtrace.h b/arch/tile/include/asm/backtrace.h
index f18887d82399..bd5399a69edf 100644
--- a/arch/tile/include/asm/backtrace.h
+++ b/arch/tile/include/asm/backtrace.h
@@ -12,80 +12,41 @@
  *   more details.
  */
 
-#ifndef _TILE_BACKTRACE_H
-#define _TILE_BACKTRACE_H
-
-
+#ifndef _ASM_TILE_BACKTRACE_H
+#define _ASM_TILE_BACKTRACE_H
 
 #include <linux/types.h>
 
-#include <arch/chip.h>
-
-#if defined(__tile__)
-typedef unsigned long VirtualAddress;
-#elif CHIP_VA_WIDTH() > 32
-typedef unsigned long long VirtualAddress;
-#else
-typedef unsigned int VirtualAddress;
-#endif
-
-
-/** Reads 'size' bytes from 'address' and writes the data to 'result'.
+/* Reads 'size' bytes from 'address' and writes the data to 'result'.
  * Returns true if successful, else false (e.g. memory not readable).
  */
 typedef bool (*BacktraceMemoryReader)(void *result,
-                                      VirtualAddress address,
+                                      unsigned long address,
                                       unsigned int size,
                                       void *extra);
 
 typedef struct {
-        /** Current PC. */
-        VirtualAddress pc;
+        /* Current PC. */
+        unsigned long pc;
 
-        /** Current stack pointer value. */
-        VirtualAddress sp;
+        /* Current stack pointer value. */
+        unsigned long sp;
 
-        /** Current frame pointer value (i.e. caller's stack pointer) */
-        VirtualAddress fp;
+        /* Current frame pointer value (i.e. caller's stack pointer) */
+        unsigned long fp;
 
-        /** Internal use only: caller's PC for first frame. */
-        VirtualAddress initial_frame_caller_pc;
+        /* Internal use only: caller's PC for first frame. */
+        unsigned long initial_frame_caller_pc;
 
-        /** Internal use only: callback to read memory. */
+        /* Internal use only: callback to read memory. */
         BacktraceMemoryReader read_memory_func;
 
-        /** Internal use only: arbitrary argument to read_memory_func. */
+        /* Internal use only: arbitrary argument to read_memory_func. */
         void *read_memory_func_extra;
 
 } BacktraceIterator;
 
 
-/** Initializes a backtracer to start from the given location.
- *
- * If the frame pointer cannot be determined it is set to -1.
- *
- * @param state The state to be filled in.
- * @param read_memory_func A callback that reads memory. If NULL, a default
- *        value is provided.
- * @param read_memory_func_extra An arbitrary argument to read_memory_func.
- * @param pc The current PC.
- * @param lr The current value of the 'lr' register.
- * @param sp The current value of the 'sp' register.
- * @param r52 The current value of the 'r52' register.
- */
-extern void backtrace_init(BacktraceIterator *state,
-                           BacktraceMemoryReader read_memory_func,
-                           void *read_memory_func_extra,
-                           VirtualAddress pc, VirtualAddress lr,
-                           VirtualAddress sp, VirtualAddress r52);
-
-
-/** Advances the backtracing state to the calling frame, returning
- * true iff successful.
- */
-extern bool backtrace_next(BacktraceIterator *state);
-
-
 typedef enum {
 
         /* We have no idea what the caller's pc is. */
@@ -138,7 +99,7 @@ enum {
 };
 
 
-/** Internal constants used to define 'info' operands. */
+/* Internal constants used to define 'info' operands. */
 enum {
         /* 0 and 1 are reserved, as are all negative numbers. */
 
@@ -147,13 +108,10 @@ enum {
         CALLER_SP_IN_R52_BASE = 4,
 
         CALLER_SP_OFFSET_BASE = 8,
-
-        /* Marks the entry point of certain functions. */
-        ENTRY_POINT_INFO_OP = 16
 };
 
 
-/** Current backtracer state describing where it thinks the caller is. */
+/* Current backtracer state describing where it thinks the caller is. */
 typedef struct {
         /*
          * Public fields
@@ -192,7 +150,13 @@ typedef struct {
 
 } CallerLocation;
 
+extern void backtrace_init(BacktraceIterator *state,
+                          BacktraceMemoryReader read_memory_func,
+                          void *read_memory_func_extra,
+                          unsigned long pc, unsigned long lr,
+                          unsigned long sp, unsigned long r52);
 
 
+extern bool backtrace_next(BacktraceIterator *state);
 
-#endif /* _TILE_BACKTRACE_H */
+#endif /* _ASM_TILE_BACKTRACE_H */
diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
index 132e6bbd07e9..16f1fa51fea1 100644
--- a/arch/tile/include/asm/bitops.h
+++ b/arch/tile/include/asm/bitops.h
@@ -122,6 +122,7 @@ static inline unsigned long __arch_hweight64(__u64 w)
 #include <asm-generic/bitops/lock.h>
 #include <asm-generic/bitops/find.h>
 #include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/non-atomic.h>
 #include <asm-generic/bitops/le.h>
 
 #endif /* _ASM_TILE_BITOPS_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
index 2638be51a164..d31ab905cfa7 100644
--- a/arch/tile/include/asm/bitops_32.h
+++ b/arch/tile/include/asm/bitops_32.h
@@ -126,7 +126,6 @@ static inline int test_and_change_bit(unsigned nr,
 #define smp_mb__before_clear_bit()      smp_mb()
 #define smp_mb__after_clear_bit()       do {} while (0)
 
-#include <asm-generic/bitops/non-atomic.h>
 #include <asm-generic/bitops/ext2-atomic.h>
 
 #endif /* _ASM_TILE_BITOPS_32_H */
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
new file mode 100644
index 000000000000..99615e8d2d8b
--- /dev/null
+++ b/arch/tile/include/asm/bitops_64.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#ifndef _ASM_TILE_BITOPS_64_H
+#define _ASM_TILE_BITOPS_64_H
+
+#include <linux/compiler.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/* See <asm/bitops.h> for API comments. */
+
+static inline void set_bit(unsigned nr, volatile unsigned long *addr)
+{
+        unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+        __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
+}
+
+static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
+{
+        unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+        __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
+}
+
+#define smp_mb__before_clear_bit()      smp_mb()
+#define smp_mb__after_clear_bit()       smp_mb()
+
+
+static inline void change_bit(unsigned nr, volatile unsigned long *addr)
+{
+        unsigned long old, mask = (1UL << (nr % BITS_PER_LONG));
+        long guess, oldval;
+        addr += nr / BITS_PER_LONG;
+        old = *addr;
+        do {
+                guess = oldval;
+                oldval = atomic64_cmpxchg((atomic64_t *)addr,
+                                          guess, guess ^ mask);
+        } while (guess != oldval);
+}
+
+
+/*
+ * The test_and_xxx_bit() routines require a memory fence before we
+ * start the operation, and after the operation completes.  We use
+ * smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
+ * barrier(), to block until the atomic op is complete.
+ */
+
+static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
+{
+        int val;
+        unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+        smp_mb();  /* barrier for proper semantics */
+        val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
+               & mask) != 0;
+        barrier();
+        return val;
+}
+
+
+static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
+{
+        int val;
+        unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+        smp_mb();  /* barrier for proper semantics */
+        val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
+               & mask) != 0;
+        barrier();
+        return val;
+}
+
+
+static inline int test_and_change_bit(unsigned nr,
+                                      volatile unsigned long *addr)
+{
+        unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+        long guess, oldval = *addr;
+        addr += nr / BITS_PER_LONG;
+        oldval = *addr;
+        do {
+                guess = oldval;
+                oldval = atomic64_cmpxchg((atomic64_t *)addr,
+                                          guess, guess ^ mask);
+        } while (guess != oldval);
+        return (oldval & mask) != 0;
+}
+
+#define ext2_set_bit_atomic(lock, nr, addr)                     \
+        test_and_set_bit((nr), (unsigned long *)(addr))
+#define ext2_clear_bit_atomic(lock, nr, addr)                   \
+        test_and_clear_bit((nr), (unsigned long *)(addr))
+
+#endif /* _ASM_TILE_BITOPS_64_H */
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index 12fb0fb330ee..e925f4bb498f 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -116,22 +116,28 @@ static inline void __finv_buffer(void *buffer, size_t size)
 }
 
 
-/* Invalidate a VA range, then memory fence. */
+/* Invalidate a VA range and wait for it to be complete. */
 static inline void inv_buffer(void *buffer, size_t size)
 {
         __inv_buffer(buffer, size);
-        mb_incoherent();
+        mb();
 }
 
-/* Flush a VA range, then memory fence. */
-static inline void flush_buffer(void *buffer, size_t size)
+/*
+ * Flush a locally-homecached VA range and wait for the evicted
+ * cachelines to hit memory.
+ */
+static inline void flush_buffer_local(void *buffer, size_t size)
 {
         __flush_buffer(buffer, size);
         mb_incoherent();
 }
 
-/* Flush & invalidate a VA range, then memory fence. */
-static inline void finv_buffer(void *buffer, size_t size)
+/*
+ * Flush and invalidate a locally-homecached VA range and wait for the
+ * evicted cachelines to hit memory.
+ */
+static inline void finv_buffer_local(void *buffer, size_t size)
 {
         __finv_buffer(buffer, size);
         mb_incoherent();
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index c3ae570c0a5d..bf95f55b82b0 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -215,8 +215,8 @@ struct compat_sigaction;
 struct compat_siginfo;
 struct compat_sigaltstack;
 long compat_sys_execve(const char __user *path,
-                       const compat_uptr_t __user *argv,
-                       const compat_uptr_t __user *envp, struct pt_regs *);
+                       compat_uptr_t __user *argv,
+                       compat_uptr_t __user *envp, struct pt_regs *);
 long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act,
                              struct compat_sigaction __user *oact,
                              size_t sigsetsize);
diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h
index 15e1dceecc64..eaa06d175b39 100644
--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
@@ -65,7 +65,8 @@ extern void dma_sync_single_range_for_cpu(struct device *, dma_addr_t,
 extern void dma_sync_single_range_for_device(struct device *, dma_addr_t,
                                              unsigned long offset, size_t,
                                              enum dma_data_direction);
-extern void dma_cache_sync(void *vaddr, size_t, enum dma_data_direction);
+extern void dma_cache_sync(struct device *dev, void *vaddr, size_t,
+                           enum dma_data_direction);
 
 static inline int
 dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/tile/include/asm/fb.h b/arch/tile/include/asm/fb.h
new file mode 100644
index 000000000000..3a4988e8df45
--- /dev/null
+++ b/arch/tile/include/asm/fb.h
@@ -0,0 +1 @@
+#include <asm-generic/fb.h>
diff --git a/arch/tile/include/asm/hardwall.h b/arch/tile/include/asm/hardwall.h
index 0bed3ec7b42c..2ac422848c7d 100644
--- a/arch/tile/include/asm/hardwall.h
+++ b/arch/tile/include/asm/hardwall.h
@@ -40,6 +40,10 @@
 #define HARDWALL_DEACTIVATE \
  _IO(HARDWALL_IOCTL_BASE, _HARDWALL_DEACTIVATE)
 
+#define _HARDWALL_GET_ID 4
+#define HARDWALL_GET_ID \
+ _IO(HARDWALL_IOCTL_BASE, _HARDWALL_GET_ID)
+
 #ifndef __KERNEL__
 
 /* This is the canonical name expected by userspace. */
@@ -47,9 +51,14 @@
 
 #else
 
-/* Hook for /proc/tile/hardwall. */
-struct seq_file;
-int proc_tile_hardwall_show(struct seq_file *sf, void *v);
+/* /proc hooks for hardwall. */
+struct proc_dir_entry;
+#ifdef CONFIG_HARDWALL
+void proc_tile_hardwall_init(struct proc_dir_entry *root);
+int proc_pid_hardwall(struct task_struct *task, char *buffer);
+#else
+static inline void proc_tile_hardwall_init(struct proc_dir_entry *root) {}
+#endif
 
 #endif
 
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index d3cbb9b14cbe..c9ea1652af03 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -52,6 +52,7 @@ extern void iounmap(volatile void __iomem *addr);
 #endif
 
 #define ioremap_nocache(physaddr, size)         ioremap(physaddr, size)
+#define ioremap_wc(physaddr, size)              ioremap(physaddr, size)
 #define ioremap_writethrough(physaddr, size)    ioremap(physaddr, size)
 #define ioremap_fullcache(physaddr, size)       ioremap(physaddr, size)
 
@@ -161,6 +162,15 @@ static inline void _tile_writeq(u64 val, unsigned long addr)
 #define iowrite32 writel
 #define iowrite64 writeq
 
+static inline void memset_io(void *dst, int val, size_t len)
+{
+        int x;
+        BUG_ON((unsigned long)dst & 0x3);
+        val = (val & 0xff) * 0x01010101;
+        for (x = 0; x < len; x += 4)
+                writel(val, dst + x);
+}
+
 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
                                  size_t len)
 {
@@ -269,6 +279,11 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
         ioport_panic();
 }
 
+#define ioread16be(addr)        be16_to_cpu(ioread16(addr))
+#define ioread32be(addr)        be32_to_cpu(ioread32(addr))
+#define iowrite16be(v, addr)    iowrite16(be16_to_cpu(v), (addr))
+#define iowrite32be(v, addr)    iowrite32(be32_to_cpu(v), (addr))
+
 #define ioread8_rep(p, dst, count) \
         insb((unsigned long) (p), (dst), (count))
 #define ioread16_rep(p, dst, count) \
@@ -283,4 +298,7 @@ static inline void outsl(unsigned long addr, const void *buffer, int count)
 #define iowrite32_rep(p, src, count) \
         outsl((unsigned long) (p), (src), (count))
 
+#define virt_to_bus     virt_to_phys
+#define bus_to_virt     phys_to_virt
+
 #endif /* _ASM_TILE_IO_H */
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h
index 572fd3ef1d73..94e9a511de84 100644
--- a/arch/tile/include/asm/irq.h
+++ b/arch/tile/include/asm/irq.h
@@ -23,6 +23,8 @@
 /* IRQ numbers used for linux IPIs. */
 #define IRQ_RESCHEDULE 1
 
+#define irq_canonicalize(irq)   (irq)
+
 void ack_bad_irq(unsigned int irq);
 
 /*
diff --git a/arch/tile/include/asm/mmu_context.h b/arch/tile/include/asm/mmu_context.h
index 9bc0d0725c28..15fb24641120 100644
--- a/arch/tile/include/asm/mmu_context.h
+++ b/arch/tile/include/asm/mmu_context.h
@@ -100,8 +100,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                 __get_cpu_var(current_asid) = asid;
 
                 /* Clear cpu from the old mm, and set it in the new one. */
-                cpumask_clear_cpu(cpu, &prev->cpu_vm_mask);
-                cpumask_set_cpu(cpu, &next->cpu_vm_mask);
+                cpumask_clear_cpu(cpu, mm_cpumask(prev));
+                cpumask_set_cpu(cpu, mm_cpumask(next));
 
                 /* Re-load page tables */
                 install_page_table(next->pgd, asid);
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
index eda60ecbae3d..03df7b1e77bf 100644
--- a/arch/tile/include/asm/opcode-tile_32.h
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -1502,5 +1502,12 @@ extern int parse_insn_tile(tile_bundle_bits bits,
                            decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
 
 
+/* Given a set of bundle bits and a specific pipe, returns which
+ * instruction the bundle contains in that pipe.
+ */
+extern const struct tile_opcode *
+find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
+
+
 
 #endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
index eda60ecbae3d..c0633466cd5c 100644
--- a/arch/tile/include/asm/opcode-tile_64.h
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -5,863 +5,711 @@
 #ifndef opcode_tile_h
 #define opcode_tile_h
 
-typedef unsigned long long tile_bundle_bits;
+typedef unsigned long long tilegx_bundle_bits;
 
 
 enum
 {
-  TILE_MAX_OPERANDS = 5 /* mm */
+  TILEGX_MAX_OPERANDS = 4 /* bfexts */
 };
 
 typedef enum
 {
-  TILE_OPC_BPT,
-  TILE_OPC_INFO,
-  TILE_OPC_INFOL,
-  TILE_OPC_J,
-  TILE_OPC_JAL,
-  TILE_OPC_MOVE,
-  TILE_OPC_MOVE_SN,
-  TILE_OPC_MOVEI,
-  TILE_OPC_MOVEI_SN,
-  TILE_OPC_MOVELI,
-  TILE_OPC_MOVELI_SN,
-  TILE_OPC_MOVELIS,
-  TILE_OPC_PREFETCH,
-  TILE_OPC_RAISE,
-  TILE_OPC_ADD,
-  TILE_OPC_ADD_SN,
-  TILE_OPC_ADDB,
-  TILE_OPC_ADDB_SN,
-  TILE_OPC_ADDBS_U,
-  TILE_OPC_ADDBS_U_SN,
-  TILE_OPC_ADDH,
-  TILE_OPC_ADDH_SN,
-  TILE_OPC_ADDHS,
-  TILE_OPC_ADDHS_SN,
-  TILE_OPC_ADDI,
-  TILE_OPC_ADDI_SN,
-  TILE_OPC_ADDIB,
-  TILE_OPC_ADDIB_SN,
-  TILE_OPC_ADDIH,
-  TILE_OPC_ADDIH_SN,
-  TILE_OPC_ADDLI,
-  TILE_OPC_ADDLI_SN,
-  TILE_OPC_ADDLIS,
-  TILE_OPC_ADDS,
-  TILE_OPC_ADDS_SN,
-  TILE_OPC_ADIFFB_U,
-  TILE_OPC_ADIFFB_U_SN,
-  TILE_OPC_ADIFFH,
-  TILE_OPC_ADIFFH_SN,
-  TILE_OPC_AND,
-  TILE_OPC_AND_SN,
-  TILE_OPC_ANDI,
-  TILE_OPC_ANDI_SN,
-  TILE_OPC_AULI,
-  TILE_OPC_AVGB_U,
-  TILE_OPC_AVGB_U_SN,
-  TILE_OPC_AVGH,
-  TILE_OPC_AVGH_SN,
-  TILE_OPC_BBNS,
-  TILE_OPC_BBNS_SN,
-  TILE_OPC_BBNST,
-  TILE_OPC_BBNST_SN,
-  TILE_OPC_BBS,
-  TILE_OPC_BBS_SN,
-  TILE_OPC_BBST,
-  TILE_OPC_BBST_SN,
-  TILE_OPC_BGEZ,
-  TILE_OPC_BGEZ_SN,
-  TILE_OPC_BGEZT,
-  TILE_OPC_BGEZT_SN,
-  TILE_OPC_BGZ,
-  TILE_OPC_BGZ_SN,
-  TILE_OPC_BGZT,
-  TILE_OPC_BGZT_SN,
-  TILE_OPC_BITX,
-  TILE_OPC_BITX_SN,
-  TILE_OPC_BLEZ,
-  TILE_OPC_BLEZ_SN,
-  TILE_OPC_BLEZT,
-  TILE_OPC_BLEZT_SN,
-  TILE_OPC_BLZ,
-  TILE_OPC_BLZ_SN,
-  TILE_OPC_BLZT,
-  TILE_OPC_BLZT_SN,
-  TILE_OPC_BNZ,
-  TILE_OPC_BNZ_SN,
-  TILE_OPC_BNZT,
-  TILE_OPC_BNZT_SN,
-  TILE_OPC_BYTEX,
-  TILE_OPC_BYTEX_SN,
-  TILE_OPC_BZ,
-  TILE_OPC_BZ_SN,
-  TILE_OPC_BZT,
-  TILE_OPC_BZT_SN,
-  TILE_OPC_CLZ,
-  TILE_OPC_CLZ_SN,
-  TILE_OPC_CRC32_32,
-  TILE_OPC_CRC32_32_SN,
-  TILE_OPC_CRC32_8,
-  TILE_OPC_CRC32_8_SN,
-  TILE_OPC_CTZ,
-  TILE_OPC_CTZ_SN,
-  TILE_OPC_DRAIN,
-  TILE_OPC_DTLBPR,
-  TILE_OPC_DWORD_ALIGN,
-  TILE_OPC_DWORD_ALIGN_SN,
-  TILE_OPC_FINV,
-  TILE_OPC_FLUSH,
-  TILE_OPC_FNOP,
-  TILE_OPC_ICOH,
-  TILE_OPC_ILL,
-  TILE_OPC_INTHB,
-  TILE_OPC_INTHB_SN,
-  TILE_OPC_INTHH,
-  TILE_OPC_INTHH_SN,
-  TILE_OPC_INTLB,
-  TILE_OPC_INTLB_SN,
-  TILE_OPC_INTLH,
-  TILE_OPC_INTLH_SN,
-  TILE_OPC_INV,
-  TILE_OPC_IRET,
-  TILE_OPC_JALB,
-  TILE_OPC_JALF,
-  TILE_OPC_JALR,
-  TILE_OPC_JALRP,
-  TILE_OPC_JB,
-  TILE_OPC_JF,
-  TILE_OPC_JR,
-  TILE_OPC_JRP,
-  TILE_OPC_LB,
-  TILE_OPC_LB_SN,
-  TILE_OPC_LB_U,
-  TILE_OPC_LB_U_SN,
-  TILE_OPC_LBADD,
-  TILE_OPC_LBADD_SN,
-  TILE_OPC_LBADD_U,
-  TILE_OPC_LBADD_U_SN,
-  TILE_OPC_LH,
-  TILE_OPC_LH_SN,
-  TILE_OPC_LH_U,
-  TILE_OPC_LH_U_SN,
-  TILE_OPC_LHADD,
-  TILE_OPC_LHADD_SN,
-  TILE_OPC_LHADD_U,
-  TILE_OPC_LHADD_U_SN,
-  TILE_OPC_LNK,
-  TILE_OPC_LNK_SN,
-  TILE_OPC_LW,
-  TILE_OPC_LW_SN,
-  TILE_OPC_LW_NA,
-  TILE_OPC_LW_NA_SN,
-  TILE_OPC_LWADD,
-  TILE_OPC_LWADD_SN,
-  TILE_OPC_LWADD_NA,
-  TILE_OPC_LWADD_NA_SN,
-  TILE_OPC_MAXB_U,
-  TILE_OPC_MAXB_U_SN,
-  TILE_OPC_MAXH,
-  TILE_OPC_MAXH_SN,
-  TILE_OPC_MAXIB_U,
-  TILE_OPC_MAXIB_U_SN,
-  TILE_OPC_MAXIH,
-  TILE_OPC_MAXIH_SN,
-  TILE_OPC_MF,
-  TILE_OPC_MFSPR,
-  TILE_OPC_MINB_U,
-  TILE_OPC_MINB_U_SN,
-  TILE_OPC_MINH,
-  TILE_OPC_MINH_SN,
-  TILE_OPC_MINIB_U,
-  TILE_OPC_MINIB_U_SN,
-  TILE_OPC_MINIH,
-  TILE_OPC_MINIH_SN,
-  TILE_OPC_MM,
-  TILE_OPC_MNZ,
-  TILE_OPC_MNZ_SN,
-  TILE_OPC_MNZB,
-  TILE_OPC_MNZB_SN,
-  TILE_OPC_MNZH,
-  TILE_OPC_MNZH_SN,
-  TILE_OPC_MTSPR,
-  TILE_OPC_MULHH_SS,
-  TILE_OPC_MULHH_SS_SN,
-  TILE_OPC_MULHH_SU,
-  TILE_OPC_MULHH_SU_SN,
-  TILE_OPC_MULHH_UU,
-  TILE_OPC_MULHH_UU_SN,
-  TILE_OPC_MULHHA_SS,
-  TILE_OPC_MULHHA_SS_SN,
-  TILE_OPC_MULHHA_SU,
-  TILE_OPC_MULHHA_SU_SN,
-  TILE_OPC_MULHHA_UU,
-  TILE_OPC_MULHHA_UU_SN,
-  TILE_OPC_MULHHSA_UU,
-  TILE_OPC_MULHHSA_UU_SN,
-  TILE_OPC_MULHL_SS,
-  TILE_OPC_MULHL_SS_SN,
-  TILE_OPC_MULHL_SU,
-  TILE_OPC_MULHL_SU_SN,
-  TILE_OPC_MULHL_US,
-  TILE_OPC_MULHL_US_SN,
-  TILE_OPC_MULHL_UU,
-  TILE_OPC_MULHL_UU_SN,
-  TILE_OPC_MULHLA_SS,
-  TILE_OPC_MULHLA_SS_SN,
-  TILE_OPC_MULHLA_SU,
-  TILE_OPC_MULHLA_SU_SN,
-  TILE_OPC_MULHLA_US,
-  TILE_OPC_MULHLA_US_SN,
-  TILE_OPC_MULHLA_UU,
-  TILE_OPC_MULHLA_UU_SN,
-  TILE_OPC_MULHLSA_UU,
-  TILE_OPC_MULHLSA_UU_SN,
-  TILE_OPC_MULLL_SS,
-  TILE_OPC_MULLL_SS_SN,
-  TILE_OPC_MULLL_SU,
-  TILE_OPC_MULLL_SU_SN,
-  TILE_OPC_MULLL_UU,
-  TILE_OPC_MULLL_UU_SN,
-  TILE_OPC_MULLLA_SS,
-  TILE_OPC_MULLLA_SS_SN,
-  TILE_OPC_MULLLA_SU,
-  TILE_OPC_MULLLA_SU_SN,
-  TILE_OPC_MULLLA_UU,
-  TILE_OPC_MULLLA_UU_SN,
-  TILE_OPC_MULLLSA_UU,
-  TILE_OPC_MULLLSA_UU_SN,
-  TILE_OPC_MVNZ,
-  TILE_OPC_MVNZ_SN,
-  TILE_OPC_MVZ,
-  TILE_OPC_MVZ_SN,
-  TILE_OPC_MZ,
-  TILE_OPC_MZ_SN,
-  TILE_OPC_MZB,
-  TILE_OPC_MZB_SN,
-  TILE_OPC_MZH,
-  TILE_OPC_MZH_SN,
-  TILE_OPC_NAP,
-  TILE_OPC_NOP,
-  TILE_OPC_NOR,
-  TILE_OPC_NOR_SN,
-  TILE_OPC_OR,
-  TILE_OPC_OR_SN,
-  TILE_OPC_ORI,
-  TILE_OPC_ORI_SN,
-  TILE_OPC_PACKBS_U,
-  TILE_OPC_PACKBS_U_SN,
-  TILE_OPC_PACKHB,
-  TILE_OPC_PACKHB_SN,
-  TILE_OPC_PACKHS,
-  TILE_OPC_PACKHS_SN,
-  TILE_OPC_PACKLB,
-  TILE_OPC_PACKLB_SN,
-  TILE_OPC_PCNT,
-  TILE_OPC_PCNT_SN,
-  TILE_OPC_RL,
-  TILE_OPC_RL_SN,
-  TILE_OPC_RLI,
-  TILE_OPC_RLI_SN,
-  TILE_OPC_S1A,
-  TILE_OPC_S1A_SN,
-  TILE_OPC_S2A,
-  TILE_OPC_S2A_SN,
-  TILE_OPC_S3A,
-  TILE_OPC_S3A_SN,
-  TILE_OPC_SADAB_U,
-  TILE_OPC_SADAB_U_SN,
-  TILE_OPC_SADAH,
-  TILE_OPC_SADAH_SN,
-  TILE_OPC_SADAH_U,
-  TILE_OPC_SADAH_U_SN,
-  TILE_OPC_SADB_U,
-  TILE_OPC_SADB_U_SN,
-  TILE_OPC_SADH,
-  TILE_OPC_SADH_SN,
-  TILE_OPC_SADH_U,
-  TILE_OPC_SADH_U_SN,
-  TILE_OPC_SB,
-  TILE_OPC_SBADD,
-  TILE_OPC_SEQ,
-  TILE_OPC_SEQ_SN,
-  TILE_OPC_SEQB,
-  TILE_OPC_SEQB_SN,
-  TILE_OPC_SEQH,
-  TILE_OPC_SEQH_SN,
-  TILE_OPC_SEQI,
-  TILE_OPC_SEQI_SN,
-  TILE_OPC_SEQIB,
-  TILE_OPC_SEQIB_SN,
-  TILE_OPC_SEQIH,
-  TILE_OPC_SEQIH_SN,
-  TILE_OPC_SH,
-  TILE_OPC_SHADD,
-  TILE_OPC_SHL,
-  TILE_OPC_SHL_SN,
-  TILE_OPC_SHLB,
-  TILE_OPC_SHLB_SN,
-  TILE_OPC_SHLH,
-  TILE_OPC_SHLH_SN,
-  TILE_OPC_SHLI,
-  TILE_OPC_SHLI_SN,
-  TILE_OPC_SHLIB,
-  TILE_OPC_SHLIB_SN,
-  TILE_OPC_SHLIH,
-  TILE_OPC_SHLIH_SN,
-  TILE_OPC_SHR,
-  TILE_OPC_SHR_SN,
-  TILE_OPC_SHRB,
-  TILE_OPC_SHRB_SN,
-  TILE_OPC_SHRH,
-  TILE_OPC_SHRH_SN,
-  TILE_OPC_SHRI,
-  TILE_OPC_SHRI_SN,
-  TILE_OPC_SHRIB,
-  TILE_OPC_SHRIB_SN,
-  TILE_OPC_SHRIH,
-  TILE_OPC_SHRIH_SN,
-  TILE_OPC_SLT,
-  TILE_OPC_SLT_SN,
-  TILE_OPC_SLT_U,
-  TILE_OPC_SLT_U_SN,
-  TILE_OPC_SLTB,
-  TILE_OPC_SLTB_SN,
-  TILE_OPC_SLTB_U,
-  TILE_OPC_SLTB_U_SN,
-  TILE_OPC_SLTE,
-  TILE_OPC_SLTE_SN,
-  TILE_OPC_SLTE_U,
-  TILE_OPC_SLTE_U_SN,
-  TILE_OPC_SLTEB,
-  TILE_OPC_SLTEB_SN,
-  TILE_OPC_SLTEB_U,
-  TILE_OPC_SLTEB_U_SN,
-  TILE_OPC_SLTEH,
-  TILE_OPC_SLTEH_SN,
-  TILE_OPC_SLTEH_U,
-  TILE_OPC_SLTEH_U_SN,
-  TILE_OPC_SLTH,
-  TILE_OPC_SLTH_SN,
-  TILE_OPC_SLTH_U,
-  TILE_OPC_SLTH_U_SN,
-  TILE_OPC_SLTI,
-  TILE_OPC_SLTI_SN,
-  TILE_OPC_SLTI_U,
-  TILE_OPC_SLTI_U_SN,
-  TILE_OPC_SLTIB,
-  TILE_OPC_SLTIB_SN,
-  TILE_OPC_SLTIB_U,
-  TILE_OPC_SLTIB_U_SN,
-  TILE_OPC_SLTIH,
-  TILE_OPC_SLTIH_SN,
-  TILE_OPC_SLTIH_U,
-  TILE_OPC_SLTIH_U_SN,
-  TILE_OPC_SNE,
-  TILE_OPC_SNE_SN,
-  TILE_OPC_SNEB,
-  TILE_OPC_SNEB_SN,
-  TILE_OPC_SNEH,
-  TILE_OPC_SNEH_SN,
-  TILE_OPC_SRA,
-  TILE_OPC_SRA_SN,
-  TILE_OPC_SRAB,
-  TILE_OPC_SRAB_SN,
-  TILE_OPC_SRAH,
-  TILE_OPC_SRAH_SN,
-  TILE_OPC_SRAI,
-  TILE_OPC_SRAI_SN,
-  TILE_OPC_SRAIB,
-  TILE_OPC_SRAIB_SN,
-  TILE_OPC_SRAIH,
-  TILE_OPC_SRAIH_SN,
-  TILE_OPC_SUB,
-  TILE_OPC_SUB_SN,
-  TILE_OPC_SUBB,
-  TILE_OPC_SUBB_SN,
-  TILE_OPC_SUBBS_U,
-  TILE_OPC_SUBBS_U_SN,
-  TILE_OPC_SUBH,
-  TILE_OPC_SUBH_SN,
-  TILE_OPC_SUBHS,
-  TILE_OPC_SUBHS_SN,
-  TILE_OPC_SUBS,
-  TILE_OPC_SUBS_SN,
-  TILE_OPC_SW,
-  TILE_OPC_SWADD,
-  TILE_OPC_SWINT0,
-  TILE_OPC_SWINT1,
-  TILE_OPC_SWINT2,
-  TILE_OPC_SWINT3,
-  TILE_OPC_TBLIDXB0,
-  TILE_OPC_TBLIDXB0_SN,
-  TILE_OPC_TBLIDXB1,
-  TILE_OPC_TBLIDXB1_SN,
-  TILE_OPC_TBLIDXB2,
-  TILE_OPC_TBLIDXB2_SN,
-  TILE_OPC_TBLIDXB3,
-  TILE_OPC_TBLIDXB3_SN,
-  TILE_OPC_TNS,
-  TILE_OPC_TNS_SN,
-  TILE_OPC_WH64,
-  TILE_OPC_XOR,
-  TILE_OPC_XOR_SN,
-  TILE_OPC_XORI,
-  TILE_OPC_XORI_SN,
-  TILE_OPC_NONE
-} tile_mnemonic;
+  TILEGX_OPC_BPT,
+  TILEGX_OPC_INFO,
+  TILEGX_OPC_INFOL,
+  TILEGX_OPC_MOVE,
+  TILEGX_OPC_MOVEI,
+  TILEGX_OPC_MOVELI,
+  TILEGX_OPC_PREFETCH,
+  TILEGX_OPC_PREFETCH_ADD_L1,
+  TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
+  TILEGX_OPC_PREFETCH_ADD_L2,
+  TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
+  TILEGX_OPC_PREFETCH_ADD_L3,
+  TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
+  TILEGX_OPC_PREFETCH_L1,
+  TILEGX_OPC_PREFETCH_L1_FAULT,
+  TILEGX_OPC_PREFETCH_L2,
+  TILEGX_OPC_PREFETCH_L2_FAULT,
+  TILEGX_OPC_PREFETCH_L3,
+  TILEGX_OPC_PREFETCH_L3_FAULT,
+  TILEGX_OPC_RAISE,
+  TILEGX_OPC_ADD,
+  TILEGX_OPC_ADDI,
+  TILEGX_OPC_ADDLI,
+  TILEGX_OPC_ADDX,
+  TILEGX_OPC_ADDXI,
+  TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXSC,
+  TILEGX_OPC_AND,
+  TILEGX_OPC_ANDI,
+  TILEGX_OPC_BEQZ,
+  TILEGX_OPC_BEQZT,
+  TILEGX_OPC_BFEXTS,
+  TILEGX_OPC_BFEXTU,
+  TILEGX_OPC_BFINS,
+  TILEGX_OPC_BGEZ,
+  TILEGX_OPC_BGEZT,
+  TILEGX_OPC_BGTZ,
+  TILEGX_OPC_BGTZT,
+  TILEGX_OPC_BLBC,
+  TILEGX_OPC_BLBCT,
+  TILEGX_OPC_BLBS,
+  TILEGX_OPC_BLBST,
+  TILEGX_OPC_BLEZ,
+  TILEGX_OPC_BLEZT,
+  TILEGX_OPC_BLTZ,
+  TILEGX_OPC_BLTZT,
+  TILEGX_OPC_BNEZ,
+  TILEGX_OPC_BNEZT,
+  TILEGX_OPC_CLZ,
+  TILEGX_OPC_CMOVEQZ,
+  TILEGX_OPC_CMOVNEZ,
+  TILEGX_OPC_CMPEQ,
+  TILEGX_OPC_CMPEQI,
+  TILEGX_OPC_CMPEXCH,
+  TILEGX_OPC_CMPEXCH4,
+  TILEGX_OPC_CMPLES,
+  TILEGX_OPC_CMPLEU,
+  TILEGX_OPC_CMPLTS,
+  TILEGX_OPC_CMPLTSI,
+  TILEGX_OPC_CMPLTU,
+  TILEGX_OPC_CMPLTUI,
+  TILEGX_OPC_CMPNE,
+  TILEGX_OPC_CMUL,
+  TILEGX_OPC_CMULA,
+  TILEGX_OPC_CMULAF,
+  TILEGX_OPC_CMULF,
+  TILEGX_OPC_CMULFR,
+  TILEGX_OPC_CMULH,
+  TILEGX_OPC_CMULHR,
+  TILEGX_OPC_CRC32_32,
+  TILEGX_OPC_CRC32_8,
+  TILEGX_OPC_CTZ,
+  TILEGX_OPC_DBLALIGN,
+  TILEGX_OPC_DBLALIGN2,
+  TILEGX_OPC_DBLALIGN4,
+  TILEGX_OPC_DBLALIGN6,
+  TILEGX_OPC_DRAIN,
+  TILEGX_OPC_DTLBPR,
+  TILEGX_OPC_EXCH,
+  TILEGX_OPC_EXCH4,
+  TILEGX_OPC_FDOUBLE_ADD_FLAGS,
+  TILEGX_OPC_FDOUBLE_ADDSUB,
+  TILEGX_OPC_FDOUBLE_MUL_FLAGS,
+  TILEGX_OPC_FDOUBLE_PACK1,
+  TILEGX_OPC_FDOUBLE_PACK2,
+  TILEGX_OPC_FDOUBLE_SUB_FLAGS,
+  TILEGX_OPC_FDOUBLE_UNPACK_MAX,
+  TILEGX_OPC_FDOUBLE_UNPACK_MIN,
+  TILEGX_OPC_FETCHADD,
+  TILEGX_OPC_FETCHADD4,
+  TILEGX_OPC_FETCHADDGEZ,
+  TILEGX_OPC_FETCHADDGEZ4,
+  TILEGX_OPC_FETCHAND,
+  TILEGX_OPC_FETCHAND4,
+  TILEGX_OPC_FETCHOR,
+  TILEGX_OPC_FETCHOR4,
+  TILEGX_OPC_FINV,
+  TILEGX_OPC_FLUSH,
+  TILEGX_OPC_FLUSHWB,
+  TILEGX_OPC_FNOP,
+  TILEGX_OPC_FSINGLE_ADD1,
+  TILEGX_OPC_FSINGLE_ADDSUB2,
+  TILEGX_OPC_FSINGLE_MUL1,
+  TILEGX_OPC_FSINGLE_MUL2,
+  TILEGX_OPC_FSINGLE_PACK1,
+  TILEGX_OPC_FSINGLE_PACK2,
+  TILEGX_OPC_FSINGLE_SUB1,
+  TILEGX_OPC_ICOH,
+  TILEGX_OPC_ILL,
+  TILEGX_OPC_INV,
+  TILEGX_OPC_IRET,
+  TILEGX_OPC_J,
+  TILEGX_OPC_JAL,
+  TILEGX_OPC_JALR,
+  TILEGX_OPC_JALRP,
+  TILEGX_OPC_JR,
+  TILEGX_OPC_JRP,
+  TILEGX_OPC_LD,
+  TILEGX_OPC_LD1S,
+  TILEGX_OPC_LD1S_ADD,
+  TILEGX_OPC_LD1U,
+  TILEGX_OPC_LD1U_ADD,
+  TILEGX_OPC_LD2S,
+  TILEGX_OPC_LD2S_ADD,
+  TILEGX_OPC_LD2U,
+  TILEGX_OPC_LD2U_ADD,
+  TILEGX_OPC_LD4S,
+  TILEGX_OPC_LD4S_ADD,
+  TILEGX_OPC_LD4U,
+  TILEGX_OPC_LD4U_ADD,
+  TILEGX_OPC_LD_ADD,
+  TILEGX_OPC_LDNA,
+  TILEGX_OPC_LDNA_ADD,
+  TILEGX_OPC_LDNT,
+  TILEGX_OPC_LDNT1S,
+  TILEGX_OPC_LDNT1S_ADD,
+  TILEGX_OPC_LDNT1U,
+  TILEGX_OPC_LDNT1U_ADD,
+  TILEGX_OPC_LDNT2S,
+  TILEGX_OPC_LDNT2S_ADD,
+  TILEGX_OPC_LDNT2U,
+  TILEGX_OPC_LDNT2U_ADD,
+  TILEGX_OPC_LDNT4S,
+  TILEGX_OPC_LDNT4S_ADD,
+  TILEGX_OPC_LDNT4U,
+  TILEGX_OPC_LDNT4U_ADD,
+  TILEGX_OPC_LDNT_ADD,
+  TILEGX_OPC_LNK,
+  TILEGX_OPC_MF,
+  TILEGX_OPC_MFSPR,
+  TILEGX_OPC_MM,
+  TILEGX_OPC_MNZ,
+  TILEGX_OPC_MTSPR,
+  TILEGX_OPC_MUL_HS_HS,
+  TILEGX_OPC_MUL_HS_HU,
+  TILEGX_OPC_MUL_HS_LS,
+  TILEGX_OPC_MUL_HS_LU,
+  TILEGX_OPC_MUL_HU_HU,
+  TILEGX_OPC_MUL_HU_LS,
+  TILEGX_OPC_MUL_HU_LU,
+  TILEGX_OPC_MUL_LS_LS,
+  TILEGX_OPC_MUL_LS_LU,
+  TILEGX_OPC_MUL_LU_LU,
+  TILEGX_OPC_MULA_HS_HS,
+  TILEGX_OPC_MULA_HS_HU,
+  TILEGX_OPC_MULA_HS_LS,
+  TILEGX_OPC_MULA_HS_LU,
+  TILEGX_OPC_MULA_HU_HU,
+  TILEGX_OPC_MULA_HU_LS,
+  TILEGX_OPC_MULA_HU_LU,
+  TILEGX_OPC_MULA_LS_LS,
+  TILEGX_OPC_MULA_LS_LU,
+  TILEGX_OPC_MULA_LU_LU,
+  TILEGX_OPC_MULAX,
+  TILEGX_OPC_MULX,
+  TILEGX_OPC_MZ,
+  TILEGX_OPC_NAP,
+  TILEGX_OPC_NOP,
+  TILEGX_OPC_NOR,
+  TILEGX_OPC_OR,
+  TILEGX_OPC_ORI,
+  TILEGX_OPC_PCNT,
+  TILEGX_OPC_REVBITS,
+  TILEGX_OPC_REVBYTES,
+  TILEGX_OPC_ROTL,
+  TILEGX_OPC_ROTLI,
+  TILEGX_OPC_SHL,
+  TILEGX_OPC_SHL16INSLI,
+  TILEGX_OPC_SHL1ADD,
+  TILEGX_OPC_SHL1ADDX,
+  TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL2ADDX,
+  TILEGX_OPC_SHL3ADD,
+  TILEGX_OPC_SHL3ADDX,
+  TILEGX_OPC_SHLI,
+  TILEGX_OPC_SHLX,
+  TILEGX_OPC_SHLXI,
+  TILEGX_OPC_SHRS,
+  TILEGX_OPC_SHRSI,
+  TILEGX_OPC_SHRU,
+  TILEGX_OPC_SHRUI,
+  TILEGX_OPC_SHRUX,
+  TILEGX_OPC_SHRUXI,
+  TILEGX_OPC_SHUFFLEBYTES,
+  TILEGX_OPC_ST,
+  TILEGX_OPC_ST1,
+  TILEGX_OPC_ST1_ADD,
+  TILEGX_OPC_ST2,
+  TILEGX_OPC_ST2_ADD,
+  TILEGX_OPC_ST4,
+  TILEGX_OPC_ST4_ADD,
+  TILEGX_OPC_ST_ADD,
+  TILEGX_OPC_STNT,
+  TILEGX_OPC_STNT1,
+  TILEGX_OPC_STNT1_ADD,
+  TILEGX_OPC_STNT2,
+  TILEGX_OPC_STNT2_ADD,
+  TILEGX_OPC_STNT4,
+  TILEGX_OPC_STNT4_ADD,
+  TILEGX_OPC_STNT_ADD,
+  TILEGX_OPC_SUB,
+  TILEGX_OPC_SUBX,
+  TILEGX_OPC_SUBXSC,
+  TILEGX_OPC_SWINT0,
+  TILEGX_OPC_SWINT1,
+  TILEGX_OPC_SWINT2,
+  TILEGX_OPC_SWINT3,
+  TILEGX_OPC_TBLIDXB0,
+  TILEGX_OPC_TBLIDXB1,
+  TILEGX_OPC_TBLIDXB2,
+  TILEGX_OPC_TBLIDXB3,
+  TILEGX_OPC_V1ADD,
+  TILEGX_OPC_V1ADDI,
+  TILEGX_OPC_V1ADDUC,
+  TILEGX_OPC_V1ADIFFU,
+  TILEGX_OPC_V1AVGU,
+  TILEGX_OPC_V1CMPEQ,
+  TILEGX_OPC_V1CMPEQI,
+  TILEGX_OPC_V1CMPLES,
+  TILEGX_OPC_V1CMPLEU,
+  TILEGX_OPC_V1CMPLTS,
+  TILEGX_OPC_V1CMPLTSI,
+  TILEGX_OPC_V1CMPLTU,
+  TILEGX_OPC_V1CMPLTUI,
+  TILEGX_OPC_V1CMPNE,
+  TILEGX_OPC_V1DDOTPU,
+  TILEGX_OPC_V1DDOTPUA,
+  TILEGX_OPC_V1DDOTPUS,
+  TILEGX_OPC_V1DDOTPUSA,
+  TILEGX_OPC_V1DOTP,
+  TILEGX_OPC_V1DOTPA,
+  TILEGX_OPC_V1DOTPU,
+  TILEGX_OPC_V1DOTPUA,
+  TILEGX_OPC_V1DOTPUS,
+  TILEGX_OPC_V1DOTPUSA,
+  TILEGX_OPC_V1INT_H,
+  TILEGX_OPC_V1INT_L,
+  TILEGX_OPC_V1MAXU,
+  TILEGX_OPC_V1MAXUI,
+  TILEGX_OPC_V1MINU,
+  TILEGX_OPC_V1MINUI,
+  TILEGX_OPC_V1MNZ,
+  TILEGX_OPC_V1MULTU,
+  TILEGX_OPC_V1MULU,
+  TILEGX_OPC_V1MULUS,
+  TILEGX_OPC_V1MZ,
+  TILEGX_OPC_V1SADAU,
+  TILEGX_OPC_V1SADU,
+  TILEGX_OPC_V1SHL,
+  TILEGX_OPC_V1SHLI,
+  TILEGX_OPC_V1SHRS,
+  TILEGX_OPC_V1SHRSI,
+  TILEGX_OPC_V1SHRU,
+  TILEGX_OPC_V1SHRUI,
+  TILEGX_OPC_V1SUB,
+  TILEGX_OPC_V1SUBUC,
+  TILEGX_OPC_V2ADD,
+  TILEGX_OPC_V2ADDI,
+  TILEGX_OPC_V2ADDSC,
+  TILEGX_OPC_V2ADIFFS,
+  TILEGX_OPC_V2AVGS,
+  TILEGX_OPC_V2CMPEQ,
+  TILEGX_OPC_V2CMPEQI,
+  TILEGX_OPC_V2CMPLES,
+  TILEGX_OPC_V2CMPLEU,
+  TILEGX_OPC_V2CMPLTS,
+  TILEGX_OPC_V2CMPLTSI,
+  TILEGX_OPC_V2CMPLTU,
+  TILEGX_OPC_V2CMPLTUI,
+  TILEGX_OPC_V2CMPNE,
+  TILEGX_OPC_V2DOTP,
+  TILEGX_OPC_V2DOTPA,
+  TILEGX_OPC_V2INT_H,
+  TILEGX_OPC_V2INT_L,
+  TILEGX_OPC_V2MAXS,
+  TILEGX_OPC_V2MAXSI,
+  TILEGX_OPC_V2MINS,
+  TILEGX_OPC_V2MINSI,
+  TILEGX_OPC_V2MNZ,
+  TILEGX_OPC_V2MULFSC,
+  TILEGX_OPC_V2MULS,
+  TILEGX_OPC_V2MULTS,
+  TILEGX_OPC_V2MZ,
+  TILEGX_OPC_V2PACKH,
+  TILEGX_OPC_V2PACKL,
+  TILEGX_OPC_V2PACKUC,
+  TILEGX_OPC_V2SADAS,
+  TILEGX_OPC_V2SADAU,
+  TILEGX_OPC_V2SADS,
+  TILEGX_OPC_V2SADU,
+  TILEGX_OPC_V2SHL,
+  TILEGX_OPC_V2SHLI,
+  TILEGX_OPC_V2SHLSC,
+  TILEGX_OPC_V2SHRS,
+  TILEGX_OPC_V2SHRSI,
+  TILEGX_OPC_V2SHRU,
+  TILEGX_OPC_V2SHRUI,
+  TILEGX_OPC_V2SUB,
+  TILEGX_OPC_V2SUBSC,
+  TILEGX_OPC_V4ADD,
+  TILEGX_OPC_V4ADDSC,
+  TILEGX_OPC_V4INT_H,
+  TILEGX_OPC_V4INT_L,
+  TILEGX_OPC_V4PACKSC,
+  TILEGX_OPC_V4SHL,
+  TILEGX_OPC_V4SHLSC,
+  TILEGX_OPC_V4SHRS,
+  TILEGX_OPC_V4SHRU,
+  TILEGX_OPC_V4SUB,
+  TILEGX_OPC_V4SUBSC,
+  TILEGX_OPC_WH64,
+  TILEGX_OPC_XOR,
+  TILEGX_OPC_XORI,
+  TILEGX_OPC_NONE
+} tilegx_mnemonic;
 
 /* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
 
 
-#define TILE_ELF_MACHINE_CODE EM_TILEPRO
+#define TILE_ELF_MACHINE_CODE EM_TILE64
 
-#define TILE_ELF_NAME "elf32-tilepro"
+#define TILE_ELF_NAME "elf32-tile64"
 
 
 static __inline unsigned int
-get_BrOff_SN(tile_bundle_bits num)
+get_BFEnd_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 0)) & 0x3ff);
+  return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_BrOff_X1(tile_bundle_bits n)
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
 {
-  return (((unsigned int)(n >> 43)) & 0x00007fff) |
-         (((unsigned int)(n >> 20)) & 0x00018000);
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 24)) & 0xf);
 }
 
 static __inline unsigned int
-get_BrType_X1(tile_bundle_bits n)
+get_BFStart_X0(tilegx_bundle_bits num)
 {
-  return (((unsigned int)(n >> 31)) & 0xf);
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 18)) & 0x3f);
 }
 
 static __inline unsigned int
-get_Dest_Imm8_X1(tile_bundle_bits n)
+get_BrOff_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 31)) & 0x0000003f) |
-         (((unsigned int)(n >> 43)) & 0x000000c0);
+         (((unsigned int)(n >> 37)) & 0x0001ffc0);
 }
 
 static __inline unsigned int
-get_Dest_SN(tile_bundle_bits num)
+get_BrType_X1(tilegx_bundle_bits n)
 {
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 2)) & 0x3);
+  return (((unsigned int)(n >> 54)) & 0x1f);
 }
 
 static __inline unsigned int
-get_Dest_X0(tile_bundle_bits num)
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+  return (((unsigned int)(n >> 31)) & 0x0000003f) |
+         (((unsigned int)(n >> 43)) & 0x000000c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 0)) & 0x3f);
 }
 
 static __inline unsigned int
-get_Dest_X1(tile_bundle_bits n)
+get_Dest_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 31)) & 0x3f);
 }
 
 static __inline unsigned int
-get_Dest_Y0(tile_bundle_bits num)
+get_Dest_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 0)) & 0x3f);
 }
 
 static __inline unsigned int
-get_Dest_Y1(tile_bundle_bits n)
+get_Dest_Y1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 31)) & 0x3f);
 }
 
 static __inline unsigned int
-get_Imm16_X0(tile_bundle_bits num)
+get_Imm16_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 12)) & 0xffff);
 }
 
 static __inline unsigned int
-get_Imm16_X1(tile_bundle_bits n)
+get_Imm16_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 43)) & 0xffff);
 }
 
 static __inline unsigned int
-get_Imm8_SN(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 0)) & 0xff);
-}
-
-static __inline unsigned int
-get_Imm8_X0(tile_bundle_bits num)
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 12)) & 0xff);
+  return (((n >> 20)) & 0xff);
 }
 
 static __inline unsigned int
-get_Imm8_X1(tile_bundle_bits n)
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 43)) & 0xff);
+  return (((unsigned int)(n >> 51)) & 0xff);
 }
 
 static __inline unsigned int
-get_Imm8_Y0(tile_bundle_bits num)
+get_Imm8_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 12)) & 0xff);
 }
 
 static __inline unsigned int
-get_Imm8_Y1(tile_bundle_bits n)
+get_Imm8_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 43)) & 0xff);
 }
 
 static __inline unsigned int
-get_ImmOpcodeExtension_X0(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 20)) & 0x7f);
-}
-
-static __inline unsigned int
-get_ImmOpcodeExtension_X1(tile_bundle_bits n)
-{
-  return (((unsigned int)(n >> 51)) & 0x7f);
-}
-
-static __inline unsigned int
-get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
+get_Imm8_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 8)) & 0x3);
-}
-
-static __inline unsigned int
-get_JOffLong_X1(tile_bundle_bits n)
-{
-  return (((unsigned int)(n >> 43)) & 0x00007fff) |
-         (((unsigned int)(n >> 20)) & 0x00018000) |
-         (((unsigned int)(n >> 14)) & 0x001e0000) |
-         (((unsigned int)(n >> 16)) & 0x07e00000) |
-         (((unsigned int)(n >> 31)) & 0x18000000);
-}
-
-static __inline unsigned int
-get_JOff_X1(tile_bundle_bits n)
-{
-  return (((unsigned int)(n >> 43)) & 0x00007fff) |
-         (((unsigned int)(n >> 20)) & 0x00018000) |
-         (((unsigned int)(n >> 14)) & 0x001e0000) |
-         (((unsigned int)(n >> 16)) & 0x07e00000) |
-         (((unsigned int)(n >> 31)) & 0x08000000);
-}
-
-static __inline unsigned int
-get_MF_Imm15_X1(tile_bundle_bits n)
-{
-  return (((unsigned int)(n >> 37)) & 0x00003fff) |
-         (((unsigned int)(n >> 44)) & 0x00004000);
+  return (((n >> 12)) & 0xff);
 }
 
 static __inline unsigned int
-get_MMEnd_X0(tile_bundle_bits num)
+get_Imm8_Y1(tilegx_bundle_bits n)
 {
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 18)) & 0x1f);
+  return (((unsigned int)(n >> 43)) & 0xff);
 }
 
 static __inline unsigned int
-get_MMEnd_X1(tile_bundle_bits n)
+get_JumpOff_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 49)) & 0x1f);
+  return (((unsigned int)(n >> 31)) & 0x7ffffff);
 }
 
 static __inline unsigned int
-get_MMStart_X0(tile_bundle_bits num)
+get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
 {
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 23)) & 0x1f);
+  return (((unsigned int)(n >> 58)) & 0x1);
 }
 
 static __inline unsigned int
-get_MMStart_X1(tile_bundle_bits n)
+get_MF_Imm14_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 54)) & 0x1f);
+  return (((unsigned int)(n >> 37)) & 0x3fff);
 }
 
 static __inline unsigned int
-get_MT_Imm15_X1(tile_bundle_bits n)
+get_MT_Imm14_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 31)) & 0x0000003f) |
-         (((unsigned int)(n >> 37)) & 0x00003fc0) |
-         (((unsigned int)(n >> 44)) & 0x00004000);
+         (((unsigned int)(n >> 37)) & 0x00003fc0);
 }
 
 static __inline unsigned int
-get_Mode(tile_bundle_bits n)
+get_Mode(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 63)) & 0x1);
+  return (((unsigned int)(n >> 62)) & 0x3);
 }
 
 static __inline unsigned int
-get_NoRegOpcodeExtension_SN(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 0)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_SN(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 10)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Opcode_X0(tile_bundle_bits num)
+get_Opcode_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 28)) & 0x7);
 }
 
 static __inline unsigned int
-get_Opcode_X1(tile_bundle_bits n)
+get_Opcode_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 59)) & 0xf);
+  return (((unsigned int)(n >> 59)) & 0x7);
 }
 
 static __inline unsigned int
-get_Opcode_Y0(tile_bundle_bits num)
+get_Opcode_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 27)) & 0xf);
 }
 
 static __inline unsigned int
-get_Opcode_Y1(tile_bundle_bits n)
+get_Opcode_Y1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 59)) & 0xf);
+  return (((unsigned int)(n >> 58)) & 0xf);
 }
 
 static __inline unsigned int
-get_Opcode_Y2(tile_bundle_bits n)
+get_Opcode_Y2(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 56)) & 0x7);
-}
-
-static __inline unsigned int
-get_RROpcodeExtension_SN(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 4)) & 0xf);
+  return (((n >> 26)) & 0x00000001) |
+         (((unsigned int)(n >> 56)) & 0x00000002);
 }
 
 static __inline unsigned int
-get_RRROpcodeExtension_X0(tile_bundle_bits num)
+get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 18)) & 0x1ff);
+  return (((n >> 18)) & 0x3ff);
 }
 
 static __inline unsigned int
-get_RRROpcodeExtension_X1(tile_bundle_bits n)
+get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 49)) & 0x1ff);
+  return (((unsigned int)(n >> 49)) & 0x3ff);
 }
 
 static __inline unsigned int
-get_RRROpcodeExtension_Y0(tile_bundle_bits num)
+get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 18)) & 0x3);
 }
 
 static __inline unsigned int
-get_RRROpcodeExtension_Y1(tile_bundle_bits n)
+get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 49)) & 0x3);
 }
 
 static __inline unsigned int
-get_RouteOpcodeExtension_SN(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 0)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_S_X0(tile_bundle_bits num)
+get_ShAmt_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 27)) & 0x1);
+  return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_S_X1(tile_bundle_bits n)
+get_ShAmt_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 58)) & 0x1);
+  return (((unsigned int)(n >> 43)) & 0x3f);
 }
 
 static __inline unsigned int
-get_ShAmt_X0(tile_bundle_bits num)
+get_ShAmt_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 12)) & 0x1f);
+  return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_ShAmt_X1(tile_bundle_bits n)
+get_ShAmt_Y1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 43)) & 0x1f);
+  return (((unsigned int)(n >> 43)) & 0x3f);
 }
 
 static __inline unsigned int
-get_ShAmt_Y0(tile_bundle_bits num)
+get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 12)) & 0x1f);
+  return (((n >> 18)) & 0x3ff);
 }
 
 static __inline unsigned int
-get_ShAmt_Y1(tile_bundle_bits n)
+get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 43)) & 0x1f);
+  return (((unsigned int)(n >> 49)) & 0x3ff);
 }
 
 static __inline unsigned int
-get_SrcA_X0(tile_bundle_bits num)
+get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 6)) & 0x3f);
+  return (((n >> 18)) & 0x3);
 }
 
 static __inline unsigned int
-get_SrcA_X1(tile_bundle_bits n)
+get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 37)) & 0x3f);
+  return (((unsigned int)(n >> 49)) & 0x3);
 }
 
 static __inline unsigned int
-get_SrcA_Y0(tile_bundle_bits num)
+get_SrcA_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 6)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcA_Y1(tile_bundle_bits n)
+get_SrcA_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 37)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcA_Y2(tile_bundle_bits n)
+get_SrcA_Y0(tilegx_bundle_bits num)
 {
-  return (((n >> 26)) & 0x00000001) |
-         (((unsigned int)(n >> 50)) & 0x0000003e);
+  const unsigned int n = (unsigned int)num;
+  return (((n >> 6)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcBDest_Y2(tile_bundle_bits num)
+get_SrcA_Y1(tilegx_bundle_bits n)
 {
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 20)) & 0x3f);
+  return (((unsigned int)(n >> 37)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcB_X0(tile_bundle_bits num)
+get_SrcA_Y2(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 12)) & 0x3f);
+  return (((n >> 20)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcB_X1(tile_bundle_bits n)
+get_SrcBDest_Y2(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 43)) & 0x3f);
+  return (((unsigned int)(n >> 51)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcB_Y0(tile_bundle_bits num)
+get_SrcB_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
   return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_SrcB_Y1(tile_bundle_bits n)
+get_SrcB_X1(tilegx_bundle_bits n)
 {
   return (((unsigned int)(n >> 43)) & 0x3f);
 }
 
 static __inline unsigned int
-get_Src_SN(tile_bundle_bits num)
+get_SrcB_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 0)) & 0x3);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_X0(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_X1(tile_bundle_bits n)
-{
-  return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y0(tile_bundle_bits num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((n >> 12)) & 0x1f);
+  return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_UnOpcodeExtension_Y1(tile_bundle_bits n)
+get_SrcB_Y1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 43)) & 0x1f);
+  return (((unsigned int)(n >> 43)) & 0x3f);
 }
 
 static __inline unsigned int
-get_UnShOpcodeExtension_X0(tile_bundle_bits num)
+get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 17)) & 0x3ff);
+  return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_UnShOpcodeExtension_X1(tile_bundle_bits n)
+get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 48)) & 0x3ff);
+  return (((unsigned int)(n >> 43)) & 0x3f);
 }
 
 static __inline unsigned int
-get_UnShOpcodeExtension_Y0(tile_bundle_bits num)
+get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((n >> 17)) & 0x7);
+  return (((n >> 12)) & 0x3f);
 }
 
 static __inline unsigned int
-get_UnShOpcodeExtension_Y1(tile_bundle_bits n)
+get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
 {
-  return (((unsigned int)(n >> 48)) & 0x7);
+  return (((unsigned int)(n >> 43)) & 0x3f);
 }
 
 
@@ -874,546 +722,441 @@ sign_extend(int n, int num_bits)
 
 
 
-static __inline tile_bundle_bits
-create_BrOff_SN(int num)
+static __inline tilegx_bundle_bits
+create_BFEnd_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x3ff) << 0);
+  return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
-create_BrOff_X1(int num)
+static __inline tilegx_bundle_bits
+create_BFOpcodeExtension_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
-         (((tile_bundle_bits)(n & 0x00018000)) << 20);
+  return ((n & 0xf) << 24);
 }
 
-static __inline tile_bundle_bits
-create_BrType_X1(int num)
+static __inline tilegx_bundle_bits
+create_BFStart_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0xf)) << 31);
+  return ((n & 0x3f) << 18);
 }
 
-static __inline tile_bundle_bits
-create_Dest_Imm8_X1(int num)
+static __inline tilegx_bundle_bits
+create_BrOff_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
-         (((tile_bundle_bits)(n & 0x000000c0)) << 43);
+  return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
 }
 
-static __inline tile_bundle_bits
-create_Dest_SN(int num)
+static __inline tilegx_bundle_bits
+create_BrType_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
+}
+
+static __inline tilegx_bundle_bits
+create_Dest_Imm8_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x3) << 2);
+  return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Dest_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3f) << 0);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Dest_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3f)) << 31);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Dest_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3f) << 0);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Dest_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3f)) << 31);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Imm16_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0xffff) << 12);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Imm16_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0xffff)) << 43);
+  return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
 }
 
-static __inline tile_bundle_bits
-create_Imm8_SN(int num)
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0xff) << 0);
+  return ((n & 0xff) << 20);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0xff)) << 51);
+}
+
+static __inline tilegx_bundle_bits
 create_Imm8_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0xff) << 12);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Imm8_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0xff)) << 43);
+  return (((tilegx_bundle_bits)(n & 0xff)) << 43);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Imm8_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0xff) << 12);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Imm8_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0xff)) << 43);
-}
-
-static __inline tile_bundle_bits
-create_ImmOpcodeExtension_X0(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0x7f) << 20);
-}
-
-static __inline tile_bundle_bits
-create_ImmOpcodeExtension_X1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x7f)) << 51);
-}
-
-static __inline tile_bundle_bits
-create_ImmRROpcodeExtension_SN(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0x3) << 8);
-}
-
-static __inline tile_bundle_bits
-create_JOffLong_X1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
-         (((tile_bundle_bits)(n & 0x00018000)) << 20) |
-         (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
-         (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
-         (((tile_bundle_bits)(n & 0x18000000)) << 31);
-}
-
-static __inline tile_bundle_bits
-create_JOff_X1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
-         (((tile_bundle_bits)(n & 0x00018000)) << 20) |
-         (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
-         (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
-         (((tile_bundle_bits)(n & 0x08000000)) << 31);
-}
-
-static __inline tile_bundle_bits
-create_MF_Imm15_X1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
-         (((tile_bundle_bits)(n & 0x00004000)) << 44);
+  return (((tilegx_bundle_bits)(n & 0xff)) << 43);
 }
 
-static __inline tile_bundle_bits
-create_MMEnd_X0(int num)
+static __inline tilegx_bundle_bits
+create_JumpOff_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x1f) << 18);
+  return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
 }
 
-static __inline tile_bundle_bits
-create_MMEnd_X1(int num)
+static __inline tilegx_bundle_bits
+create_JumpOpcodeExtension_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1f)) << 49);
+  return (((tilegx_bundle_bits)(n & 0x1)) << 58);
 }
 
-static __inline tile_bundle_bits
-create_MMStart_X0(int num)
+static __inline tilegx_bundle_bits
+create_MF_Imm14_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x1f) << 23);
+  return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
 }
 
-static __inline tile_bundle_bits
-create_MMStart_X1(int num)
+static __inline tilegx_bundle_bits
+create_MT_Imm14_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1f)) << 54);
+  return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+         (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
 }
 
-static __inline tile_bundle_bits
-create_MT_Imm15_X1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
-         (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
-         (((tile_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Mode(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1)) << 63);
+  return (((tilegx_bundle_bits)(n & 0x3)) << 62);
 }
 
-static __inline tile_bundle_bits
-create_NoRegOpcodeExtension_SN(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0xf) << 0);
-}
-
-static __inline tile_bundle_bits
-create_Opcode_SN(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0x3f) << 10);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Opcode_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x7) << 28);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Opcode_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0xf)) << 59);
+  return (((tilegx_bundle_bits)(n & 0x7)) << 59);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Opcode_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0xf) << 27);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Opcode_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0xf)) << 59);
+  return (((tilegx_bundle_bits)(n & 0xf)) << 58);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_Opcode_Y2(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x7)) << 56);
-}
-
-static __inline tile_bundle_bits
-create_RROpcodeExtension_SN(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0xf) << 4);
+  return ((n & 0x00000001) << 26) |
+         (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_RRROpcodeExtension_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x1ff) << 18);
+  return ((n & 0x3ff) << 18);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_RRROpcodeExtension_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1ff)) << 49);
+  return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_RRROpcodeExtension_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3) << 18);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_RRROpcodeExtension_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3)) << 49);
+  return (((tilegx_bundle_bits)(n & 0x3)) << 49);
 }
 
-static __inline tile_bundle_bits
-create_RouteOpcodeExtension_SN(int num)
+static __inline tilegx_bundle_bits
+create_ShAmt_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x3ff) << 0);
+  return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
-create_S_X0(int num)
+static __inline tilegx_bundle_bits
+create_ShAmt_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x1) << 27);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 }
 
-static __inline tile_bundle_bits
-create_S_X1(int num)
+static __inline tilegx_bundle_bits
+create_ShAmt_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1)) << 58);
+  return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
-create_ShAmt_X0(int num)
+static __inline tilegx_bundle_bits
+create_ShAmt_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x1f) << 12);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 }
 
-static __inline tile_bundle_bits
-create_ShAmt_X1(int num)
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1f)) << 43);
+  return ((n & 0x3ff) << 18);
 }
 
-static __inline tile_bundle_bits
-create_ShAmt_Y0(int num)
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x1f) << 12);
+  return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
 }
 
-static __inline tile_bundle_bits
-create_ShAmt_Y1(int num)
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1f)) << 43);
+  return ((n & 0x3) << 18);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y1(int num)
+{
+  const unsigned int n = (unsigned int)num;
+  return (((tilegx_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilegx_bundle_bits
 create_SrcA_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3f) << 6);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcA_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3f)) << 37);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcA_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3f) << 6);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcA_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3f)) << 37);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcA_Y2(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x00000001) << 26) |
-         (((tile_bundle_bits)(n & 0x0000003e)) << 50);
+  return ((n & 0x3f) << 20);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcBDest_Y2(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x3f) << 20);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcB_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcB_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3f)) << 43);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcB_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
   return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
 create_SrcB_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3f)) << 43);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 }
 
-static __inline tile_bundle_bits
-create_Src_SN(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x3) << 0);
-}
-
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_X0(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0x1f) << 12);
-}
-
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_X1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_Y0(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0x1f) << 12);
-}
-
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_Y1(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_X0(int num)
-{
-  const unsigned int n = (unsigned int)num;
-  return ((n & 0x3ff) << 17);
+  return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_X1(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x3ff)) << 48);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 }
 
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_Y0(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y0(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return ((n & 0x7) << 17);
+  return ((n & 0x3f) << 12);
 }
 
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_Y1(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y1(int num)
 {
   const unsigned int n = (unsigned int)num;
-  return (((tile_bundle_bits)(n & 0x7)) << 48);
+  return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
 }
 
 
-
 typedef enum
 {
-  TILE_PIPELINE_X0,
-  TILE_PIPELINE_X1,
-  TILE_PIPELINE_Y0,
-  TILE_PIPELINE_Y1,
-  TILE_PIPELINE_Y2,
-} tile_pipeline;
+  TILEGX_PIPELINE_X0,
+  TILEGX_PIPELINE_X1,
+  TILEGX_PIPELINE_Y0,
+  TILEGX_PIPELINE_Y1,
+  TILEGX_PIPELINE_Y2,
+} tilegx_pipeline;
 
-#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1)
+#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
 
 typedef enum
 {
-  TILE_OP_TYPE_REGISTER,
-  TILE_OP_TYPE_IMMEDIATE,
-  TILE_OP_TYPE_ADDRESS,
-  TILE_OP_TYPE_SPR
-} tile_operand_type;
+  TILEGX_OP_TYPE_REGISTER,
+  TILEGX_OP_TYPE_IMMEDIATE,
+  TILEGX_OP_TYPE_ADDRESS,
+  TILEGX_OP_TYPE_SPR
+} tilegx_operand_type;
 
-/* This is the bit that determines if a bundle is in the Y encoding. */
-#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63)
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
 
 enum
 {
   /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
-  TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+  TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
 
   /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
-  TILE_NUM_PIPELINE_ENCODINGS = 5,
+  TILEGX_NUM_PIPELINE_ENCODINGS = 5,
 
-  /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */
-  TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+  /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+  TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
 
   /* Instructions take this many bytes. */
-  TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES,
+  TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
 
-  /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */
-  TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+  /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+  TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
 
   /* Bundles should be aligned modulo this number of bytes. */
-  TILE_BUNDLE_ALIGNMENT_IN_BYTES =
-    (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
-  /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
-  TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
-
-  /* Static network instructions take this many bytes. */
-  TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
-    (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
+  TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+    (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
 
   /* Number of registers (some are magic, such as network I/O). */
-  TILE_NUM_REGISTERS = 64,
-
-  /* Number of static network registers. */
-  TILE_NUM_SN_REGISTERS = 4
+  TILEGX_NUM_REGISTERS = 64,
 };
 
 
-struct tile_operand
+struct tilegx_operand
 {
   /* Is this operand a register, immediate or address? */
-  tile_operand_type type;
+  tilegx_operand_type type;
 
   /* The default relocation type for this operand.  */
   signed int default_reloc : 16;
@@ -1437,27 +1180,27 @@ struct tile_operand
   unsigned int rightshift : 2;
 
   /* Return the bits for this operand to be ORed into an existing bundle. */
-  tile_bundle_bits (*insert) (int op);
+  tilegx_bundle_bits (*insert) (int op);
 
   /* Extract this operand and return it. */
-  unsigned int (*extract) (tile_bundle_bits bundle);
+  unsigned int (*extract) (tilegx_bundle_bits bundle);
 };
 
 
-extern const struct tile_operand tile_operands[];
+extern const struct tilegx_operand tilegx_operands[];
 
 /* One finite-state machine per pipe for rapid instruction decoding. */
 extern const unsigned short * const
-tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS];
+tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
 
 
-struct tile_opcode
+struct tilegx_opcode
 {
   /* The opcode mnemonic, e.g. "add" */
   const char *name;
 
   /* The enum value for this mnemonic. */
-  tile_mnemonic mnemonic;
+  tilegx_mnemonic mnemonic;
 
   /* A bit mask of which of the five pipes this instruction
      is compatible with:
@@ -1478,29 +1221,28 @@ struct tile_opcode
   unsigned char can_bundle;
 
   /* The description of the operands. Each of these is an
-   * index into the tile_operands[] table. */
-  unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS];
+   * index into the tilegx_operands[] table. */
+  unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
 
 };
 
-extern const struct tile_opcode tile_opcodes[];
-
+extern const struct tilegx_opcode tilegx_opcodes[];
 
 /* Used for non-textual disassembly into structs. */
-struct tile_decoded_instruction
+struct tilegx_decoded_instruction
 {
-  const struct tile_opcode *opcode;
-  const struct tile_operand *operands[TILE_MAX_OPERANDS];
-  int operand_values[TILE_MAX_OPERANDS];
+  const struct tilegx_opcode *opcode;
+  const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
+  long long operand_values[TILEGX_MAX_OPERANDS];
 };
 
 
 /* Disassemble a bundle into a struct for machine processing. */
-extern int parse_insn_tile(tile_bundle_bits bits,
-                           unsigned int pc,
-                           struct tile_decoded_instruction
-                           decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
+extern int parse_insn_tilegx(tilegx_bundle_bits bits,
+                             unsigned long long pc,
+                             struct tilegx_decoded_instruction
+                             decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
 
 
 
-#endif /* opcode_tile_h */
+#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
index 227d033b180c..710192869476 100644
--- a/arch/tile/include/asm/opcode_constants_64.h
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
  *
  *   This program is free software; you can redistribute it and/or
  *   modify it under the terms of the GNU General Public License
@@ -19,462 +19,591 @@
 #define _TILE_OPCODE_CONSTANTS_H
 enum
 {
-  ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
-  ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
-  ADDB_SPECIAL_0_OPCODE_X0 = 1,
-  ADDB_SPECIAL_0_OPCODE_X1 = 1,
-  ADDHS_SPECIAL_0_OPCODE_X0 = 99,
-  ADDHS_SPECIAL_0_OPCODE_X1 = 69,
-  ADDH_SPECIAL_0_OPCODE_X0 = 2,
-  ADDH_SPECIAL_0_OPCODE_X1 = 2,
-  ADDIB_IMM_0_OPCODE_X0 = 1,
-  ADDIB_IMM_0_OPCODE_X1 = 1,
-  ADDIH_IMM_0_OPCODE_X0 = 2,
-  ADDIH_IMM_0_OPCODE_X1 = 2,
-  ADDI_IMM_0_OPCODE_X0 = 3,
-  ADDI_IMM_0_OPCODE_X1 = 3,
-  ADDI_IMM_1_OPCODE_SN = 1,
-  ADDI_OPCODE_Y0 = 9,
-  ADDI_OPCODE_Y1 = 7,
-  ADDLIS_OPCODE_X0 = 1,
-  ADDLIS_OPCODE_X1 = 2,
-  ADDLI_OPCODE_X0 = 2,
-  ADDLI_OPCODE_X1 = 3,
-  ADDS_SPECIAL_0_OPCODE_X0 = 96,
-  ADDS_SPECIAL_0_OPCODE_X1 = 66,
-  ADD_SPECIAL_0_OPCODE_X0 = 3,
-  ADD_SPECIAL_0_OPCODE_X1 = 3,
-  ADD_SPECIAL_0_OPCODE_Y0 = 0,
-  ADD_SPECIAL_0_OPCODE_Y1 = 0,
-  ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
-  ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
-  ANDI_IMM_0_OPCODE_X0 = 1,
-  ANDI_IMM_0_OPCODE_X1 = 4,
-  ANDI_OPCODE_Y0 = 10,
-  ANDI_OPCODE_Y1 = 8,
-  AND_SPECIAL_0_OPCODE_X0 = 6,
-  AND_SPECIAL_0_OPCODE_X1 = 4,
-  AND_SPECIAL_2_OPCODE_Y0 = 0,
-  AND_SPECIAL_2_OPCODE_Y1 = 0,
-  AULI_OPCODE_X0 = 3,
-  AULI_OPCODE_X1 = 4,
-  AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
-  AVGH_SPECIAL_0_OPCODE_X0 = 8,
-  BBNST_BRANCH_OPCODE_X1 = 15,
-  BBNS_BRANCH_OPCODE_X1 = 14,
-  BBNS_OPCODE_SN = 63,
-  BBST_BRANCH_OPCODE_X1 = 13,
-  BBS_BRANCH_OPCODE_X1 = 12,
-  BBS_OPCODE_SN = 62,
-  BGEZT_BRANCH_OPCODE_X1 = 7,
-  BGEZ_BRANCH_OPCODE_X1 = 6,
-  BGEZ_OPCODE_SN = 61,
-  BGZT_BRANCH_OPCODE_X1 = 5,
-  BGZ_BRANCH_OPCODE_X1 = 4,
-  BGZ_OPCODE_SN = 58,
-  BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
-  BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
-  BLEZT_BRANCH_OPCODE_X1 = 11,
-  BLEZ_BRANCH_OPCODE_X1 = 10,
-  BLEZ_OPCODE_SN = 59,
-  BLZT_BRANCH_OPCODE_X1 = 9,
-  BLZ_BRANCH_OPCODE_X1 = 8,
-  BLZ_OPCODE_SN = 60,
-  BNZT_BRANCH_OPCODE_X1 = 3,
-  BNZ_BRANCH_OPCODE_X1 = 2,
-  BNZ_OPCODE_SN = 57,
-  BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
-  BRANCH_OPCODE_X1 = 5,
-  BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
-  BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
-  BZT_BRANCH_OPCODE_X1 = 1,
-  BZ_BRANCH_OPCODE_X1 = 0,
-  BZ_OPCODE_SN = 56,
-  CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
-  CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
-  CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
-  CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
-  CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
-  CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
-  DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
-  DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
-  DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
-  FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
-  FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
-  FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
-  FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
-  FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
-  FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
-  FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
-  HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
-  ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
-  ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
-  ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
-  IMM_0_OPCODE_SN = 0,
-  IMM_0_OPCODE_X0 = 4,
-  IMM_0_OPCODE_X1 = 6,
-  IMM_1_OPCODE_SN = 1,
-  IMM_OPCODE_0_X0 = 5,
-  INTHB_SPECIAL_0_OPCODE_X0 = 11,
-  INTHB_SPECIAL_0_OPCODE_X1 = 5,
-  INTHH_SPECIAL_0_OPCODE_X0 = 12,
-  INTHH_SPECIAL_0_OPCODE_X1 = 6,
-  INTLB_SPECIAL_0_OPCODE_X0 = 13,
-  INTLB_SPECIAL_0_OPCODE_X1 = 7,
-  INTLH_SPECIAL_0_OPCODE_X0 = 14,
-  INTLH_SPECIAL_0_OPCODE_X1 = 8,
-  INV_UN_0_SHUN_0_OPCODE_X1 = 8,
-  IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
-  JALB_OPCODE_X1 = 13,
-  JALF_OPCODE_X1 = 12,
-  JALRP_SPECIAL_0_OPCODE_X1 = 9,
-  JALRR_IMM_1_OPCODE_SN = 3,
-  JALR_RR_IMM_0_OPCODE_SN = 5,
-  JALR_SPECIAL_0_OPCODE_X1 = 10,
-  JB_OPCODE_X1 = 11,
-  JF_OPCODE_X1 = 10,
-  JRP_SPECIAL_0_OPCODE_X1 = 11,
-  JRR_IMM_1_OPCODE_SN = 2,
-  JR_RR_IMM_0_OPCODE_SN = 4,
-  JR_SPECIAL_0_OPCODE_X1 = 12,
-  LBADD_IMM_0_OPCODE_X1 = 22,
-  LBADD_U_IMM_0_OPCODE_X1 = 23,
-  LB_OPCODE_Y2 = 0,
-  LB_UN_0_SHUN_0_OPCODE_X1 = 10,
-  LB_U_OPCODE_Y2 = 1,
-  LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
-  LHADD_IMM_0_OPCODE_X1 = 24,
-  LHADD_U_IMM_0_OPCODE_X1 = 25,
-  LH_OPCODE_Y2 = 2,
-  LH_UN_0_SHUN_0_OPCODE_X1 = 12,
-  LH_U_OPCODE_Y2 = 3,
-  LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
-  LNK_SPECIAL_0_OPCODE_X1 = 13,
-  LWADD_IMM_0_OPCODE_X1 = 26,
-  LWADD_NA_IMM_0_OPCODE_X1 = 27,
-  LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
-  LW_OPCODE_Y2 = 4,
-  LW_UN_0_SHUN_0_OPCODE_X1 = 14,
-  MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
-  MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
-  MAXH_SPECIAL_0_OPCODE_X0 = 16,
-  MAXH_SPECIAL_0_OPCODE_X1 = 15,
-  MAXIB_U_IMM_0_OPCODE_X0 = 4,
-  MAXIB_U_IMM_0_OPCODE_X1 = 5,
-  MAXIH_IMM_0_OPCODE_X0 = 5,
-  MAXIH_IMM_0_OPCODE_X1 = 6,
-  MFSPR_IMM_0_OPCODE_X1 = 7,
-  MF_UN_0_SHUN_0_OPCODE_X1 = 15,
-  MINB_U_SPECIAL_0_OPCODE_X0 = 17,
-  MINB_U_SPECIAL_0_OPCODE_X1 = 16,
-  MINH_SPECIAL_0_OPCODE_X0 = 18,
-  MINH_SPECIAL_0_OPCODE_X1 = 17,
-  MINIB_U_IMM_0_OPCODE_X0 = 6,
-  MINIB_U_IMM_0_OPCODE_X1 = 8,
-  MINIH_IMM_0_OPCODE_X0 = 7,
-  MINIH_IMM_0_OPCODE_X1 = 9,
-  MM_OPCODE_X0 = 6,
-  MM_OPCODE_X1 = 7,
-  MNZB_SPECIAL_0_OPCODE_X0 = 19,
-  MNZB_SPECIAL_0_OPCODE_X1 = 18,
-  MNZH_SPECIAL_0_OPCODE_X0 = 20,
-  MNZH_SPECIAL_0_OPCODE_X1 = 19,
-  MNZ_SPECIAL_0_OPCODE_X0 = 21,
-  MNZ_SPECIAL_0_OPCODE_X1 = 20,
-  MNZ_SPECIAL_1_OPCODE_Y0 = 0,
-  MNZ_SPECIAL_1_OPCODE_Y1 = 1,
-  MOVEI_IMM_1_OPCODE_SN = 0,
-  MOVE_RR_IMM_0_OPCODE_SN = 8,
-  MTSPR_IMM_0_OPCODE_X1 = 10,
-  MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
-  MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
-  MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
-  MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
-  MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
-  MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
-  MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
-  MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
-  MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
-  MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
-  MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
-  MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
-  MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
-  MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
-  MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
-  MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
-  MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
-  MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
-  MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
-  MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
-  MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
-  MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
-  MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
-  MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
-  MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
-  MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
-  MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
-  MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
-  MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
-  MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
-  MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
-  MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
-  MVNZ_SPECIAL_0_OPCODE_X0 = 45,
-  MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
-  MVZ_SPECIAL_0_OPCODE_X0 = 46,
-  MVZ_SPECIAL_1_OPCODE_Y0 = 2,
-  MZB_SPECIAL_0_OPCODE_X0 = 47,
-  MZB_SPECIAL_0_OPCODE_X1 = 21,
-  MZH_SPECIAL_0_OPCODE_X0 = 48,
-  MZH_SPECIAL_0_OPCODE_X1 = 22,
-  MZ_SPECIAL_0_OPCODE_X0 = 49,
-  MZ_SPECIAL_0_OPCODE_X1 = 23,
-  MZ_SPECIAL_1_OPCODE_Y0 = 3,
-  MZ_SPECIAL_1_OPCODE_Y1 = 2,
-  NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
-  NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
-  NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
-  NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
-  NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
-  NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
-  NOREG_RR_IMM_0_OPCODE_SN = 0,
-  NOR_SPECIAL_0_OPCODE_X0 = 50,
-  NOR_SPECIAL_0_OPCODE_X1 = 24,
-  NOR_SPECIAL_2_OPCODE_Y0 = 1,
-  NOR_SPECIAL_2_OPCODE_Y1 = 1,
-  ORI_IMM_0_OPCODE_X0 = 8,
-  ORI_IMM_0_OPCODE_X1 = 11,
-  ORI_OPCODE_Y0 = 11,
-  ORI_OPCODE_Y1 = 9,
-  OR_SPECIAL_0_OPCODE_X0 = 51,
-  OR_SPECIAL_0_OPCODE_X1 = 25,
-  OR_SPECIAL_2_OPCODE_Y0 = 2,
-  OR_SPECIAL_2_OPCODE_Y1 = 2,
-  PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
-  PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
-  PACKHB_SPECIAL_0_OPCODE_X0 = 52,
-  PACKHB_SPECIAL_0_OPCODE_X1 = 26,
-  PACKHS_SPECIAL_0_OPCODE_X0 = 102,
-  PACKHS_SPECIAL_0_OPCODE_X1 = 72,
-  PACKLB_SPECIAL_0_OPCODE_X0 = 53,
-  PACKLB_SPECIAL_0_OPCODE_X1 = 27,
-  PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
-  PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
-  RLI_SHUN_0_OPCODE_X0 = 1,
-  RLI_SHUN_0_OPCODE_X1 = 1,
-  RLI_SHUN_0_OPCODE_Y0 = 1,
-  RLI_SHUN_0_OPCODE_Y1 = 1,
-  RL_SPECIAL_0_OPCODE_X0 = 54,
-  RL_SPECIAL_0_OPCODE_X1 = 28,
-  RL_SPECIAL_3_OPCODE_Y0 = 0,
-  RL_SPECIAL_3_OPCODE_Y1 = 0,
-  RR_IMM_0_OPCODE_SN = 0,
-  S1A_SPECIAL_0_OPCODE_X0 = 55,
-  S1A_SPECIAL_0_OPCODE_X1 = 29,
-  S1A_SPECIAL_0_OPCODE_Y0 = 1,
-  S1A_SPECIAL_0_OPCODE_Y1 = 1,
-  S2A_SPECIAL_0_OPCODE_X0 = 56,
-  S2A_SPECIAL_0_OPCODE_X1 = 30,
-  S2A_SPECIAL_0_OPCODE_Y0 = 2,
-  S2A_SPECIAL_0_OPCODE_Y1 = 2,
-  S3A_SPECIAL_0_OPCODE_X0 = 57,
-  S3A_SPECIAL_0_OPCODE_X1 = 31,
-  S3A_SPECIAL_5_OPCODE_Y0 = 1,
-  S3A_SPECIAL_5_OPCODE_Y1 = 1,
-  SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
-  SADAH_SPECIAL_0_OPCODE_X0 = 59,
-  SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
-  SADB_U_SPECIAL_0_OPCODE_X0 = 61,
-  SADH_SPECIAL_0_OPCODE_X0 = 62,
-  SADH_U_SPECIAL_0_OPCODE_X0 = 63,
-  SBADD_IMM_0_OPCODE_X1 = 28,
-  SB_OPCODE_Y2 = 5,
-  SB_SPECIAL_0_OPCODE_X1 = 32,
-  SEQB_SPECIAL_0_OPCODE_X0 = 64,
-  SEQB_SPECIAL_0_OPCODE_X1 = 33,
-  SEQH_SPECIAL_0_OPCODE_X0 = 65,
-  SEQH_SPECIAL_0_OPCODE_X1 = 34,
-  SEQIB_IMM_0_OPCODE_X0 = 9,
-  SEQIB_IMM_0_OPCODE_X1 = 12,
-  SEQIH_IMM_0_OPCODE_X0 = 10,
-  SEQIH_IMM_0_OPCODE_X1 = 13,
-  SEQI_IMM_0_OPCODE_X0 = 11,
-  SEQI_IMM_0_OPCODE_X1 = 14,
-  SEQI_OPCODE_Y0 = 12,
-  SEQI_OPCODE_Y1 = 10,
-  SEQ_SPECIAL_0_OPCODE_X0 = 66,
-  SEQ_SPECIAL_0_OPCODE_X1 = 35,
-  SEQ_SPECIAL_5_OPCODE_Y0 = 2,
-  SEQ_SPECIAL_5_OPCODE_Y1 = 2,
-  SHADD_IMM_0_OPCODE_X1 = 29,
-  SHL8II_IMM_0_OPCODE_SN = 3,
-  SHLB_SPECIAL_0_OPCODE_X0 = 67,
-  SHLB_SPECIAL_0_OPCODE_X1 = 36,
-  SHLH_SPECIAL_0_OPCODE_X0 = 68,
-  SHLH_SPECIAL_0_OPCODE_X1 = 37,
-  SHLIB_SHUN_0_OPCODE_X0 = 2,
-  SHLIB_SHUN_0_OPCODE_X1 = 2,
-  SHLIH_SHUN_0_OPCODE_X0 = 3,
-  SHLIH_SHUN_0_OPCODE_X1 = 3,
-  SHLI_SHUN_0_OPCODE_X0 = 4,
-  SHLI_SHUN_0_OPCODE_X1 = 4,
-  SHLI_SHUN_0_OPCODE_Y0 = 2,
-  SHLI_SHUN_0_OPCODE_Y1 = 2,
-  SHL_SPECIAL_0_OPCODE_X0 = 69,
-  SHL_SPECIAL_0_OPCODE_X1 = 38,
-  SHL_SPECIAL_3_OPCODE_Y0 = 1,
-  SHL_SPECIAL_3_OPCODE_Y1 = 1,
-  SHR1_RR_IMM_0_OPCODE_SN = 9,
-  SHRB_SPECIAL_0_OPCODE_X0 = 70,
-  SHRB_SPECIAL_0_OPCODE_X1 = 39,
-  SHRH_SPECIAL_0_OPCODE_X0 = 71,
-  SHRH_SPECIAL_0_OPCODE_X1 = 40,
-  SHRIB_SHUN_0_OPCODE_X0 = 5,
-  SHRIB_SHUN_0_OPCODE_X1 = 5,
-  SHRIH_SHUN_0_OPCODE_X0 = 6,
-  SHRIH_SHUN_0_OPCODE_X1 = 6,
-  SHRI_SHUN_0_OPCODE_X0 = 7,
-  SHRI_SHUN_0_OPCODE_X1 = 7,
-  SHRI_SHUN_0_OPCODE_Y0 = 3,
-  SHRI_SHUN_0_OPCODE_Y1 = 3,
-  SHR_SPECIAL_0_OPCODE_X0 = 72,
-  SHR_SPECIAL_0_OPCODE_X1 = 41,
-  SHR_SPECIAL_3_OPCODE_Y0 = 2,
-  SHR_SPECIAL_3_OPCODE_Y1 = 2,
-  SHUN_0_OPCODE_X0 = 7,
-  SHUN_0_OPCODE_X1 = 8,
-  SHUN_0_OPCODE_Y0 = 13,
-  SHUN_0_OPCODE_Y1 = 11,
-  SH_OPCODE_Y2 = 6,
-  SH_SPECIAL_0_OPCODE_X1 = 42,
-  SLTB_SPECIAL_0_OPCODE_X0 = 73,
-  SLTB_SPECIAL_0_OPCODE_X1 = 43,
-  SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
-  SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
-  SLTEB_SPECIAL_0_OPCODE_X0 = 75,
-  SLTEB_SPECIAL_0_OPCODE_X1 = 45,
-  SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
-  SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
-  SLTEH_SPECIAL_0_OPCODE_X0 = 77,
-  SLTEH_SPECIAL_0_OPCODE_X1 = 47,
-  SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
-  SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
-  SLTE_SPECIAL_0_OPCODE_X0 = 79,
-  SLTE_SPECIAL_0_OPCODE_X1 = 49,
-  SLTE_SPECIAL_4_OPCODE_Y0 = 0,
-  SLTE_SPECIAL_4_OPCODE_Y1 = 0,
-  SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
-  SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
-  SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
-  SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
-  SLTH_SPECIAL_0_OPCODE_X0 = 81,
-  SLTH_SPECIAL_0_OPCODE_X1 = 51,
-  SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
-  SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
-  SLTIB_IMM_0_OPCODE_X0 = 12,
-  SLTIB_IMM_0_OPCODE_X1 = 15,
-  SLTIB_U_IMM_0_OPCODE_X0 = 13,
-  SLTIB_U_IMM_0_OPCODE_X1 = 16,
-  SLTIH_IMM_0_OPCODE_X0 = 14,
-  SLTIH_IMM_0_OPCODE_X1 = 17,
-  SLTIH_U_IMM_0_OPCODE_X0 = 15,
-  SLTIH_U_IMM_0_OPCODE_X1 = 18,
-  SLTI_IMM_0_OPCODE_X0 = 16,
-  SLTI_IMM_0_OPCODE_X1 = 19,
-  SLTI_OPCODE_Y0 = 14,
-  SLTI_OPCODE_Y1 = 12,
-  SLTI_U_IMM_0_OPCODE_X0 = 17,
-  SLTI_U_IMM_0_OPCODE_X1 = 20,
-  SLTI_U_OPCODE_Y0 = 15,
-  SLTI_U_OPCODE_Y1 = 13,
-  SLT_SPECIAL_0_OPCODE_X0 = 83,
-  SLT_SPECIAL_0_OPCODE_X1 = 53,
-  SLT_SPECIAL_4_OPCODE_Y0 = 2,
-  SLT_SPECIAL_4_OPCODE_Y1 = 2,
-  SLT_U_SPECIAL_0_OPCODE_X0 = 84,
-  SLT_U_SPECIAL_0_OPCODE_X1 = 54,
-  SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
-  SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
-  SNEB_SPECIAL_0_OPCODE_X0 = 85,
-  SNEB_SPECIAL_0_OPCODE_X1 = 55,
-  SNEH_SPECIAL_0_OPCODE_X0 = 86,
-  SNEH_SPECIAL_0_OPCODE_X1 = 56,
-  SNE_SPECIAL_0_OPCODE_X0 = 87,
-  SNE_SPECIAL_0_OPCODE_X1 = 57,
-  SNE_SPECIAL_5_OPCODE_Y0 = 3,
-  SNE_SPECIAL_5_OPCODE_Y1 = 3,
-  SPECIAL_0_OPCODE_X0 = 0,
-  SPECIAL_0_OPCODE_X1 = 1,
-  SPECIAL_0_OPCODE_Y0 = 1,
-  SPECIAL_0_OPCODE_Y1 = 1,
-  SPECIAL_1_OPCODE_Y0 = 2,
-  SPECIAL_1_OPCODE_Y1 = 2,
-  SPECIAL_2_OPCODE_Y0 = 3,
-  SPECIAL_2_OPCODE_Y1 = 3,
-  SPECIAL_3_OPCODE_Y0 = 4,
-  SPECIAL_3_OPCODE_Y1 = 4,
-  SPECIAL_4_OPCODE_Y0 = 5,
-  SPECIAL_4_OPCODE_Y1 = 5,
-  SPECIAL_5_OPCODE_Y0 = 6,
-  SPECIAL_5_OPCODE_Y1 = 6,
-  SPECIAL_6_OPCODE_Y0 = 7,
-  SPECIAL_7_OPCODE_Y0 = 8,
-  SRAB_SPECIAL_0_OPCODE_X0 = 88,
-  SRAB_SPECIAL_0_OPCODE_X1 = 58,
-  SRAH_SPECIAL_0_OPCODE_X0 = 89,
-  SRAH_SPECIAL_0_OPCODE_X1 = 59,
-  SRAIB_SHUN_0_OPCODE_X0 = 8,
-  SRAIB_SHUN_0_OPCODE_X1 = 8,
-  SRAIH_SHUN_0_OPCODE_X0 = 9,
-  SRAIH_SHUN_0_OPCODE_X1 = 9,
-  SRAI_SHUN_0_OPCODE_X0 = 10,
-  SRAI_SHUN_0_OPCODE_X1 = 10,
-  SRAI_SHUN_0_OPCODE_Y0 = 4,
-  SRAI_SHUN_0_OPCODE_Y1 = 4,
-  SRA_SPECIAL_0_OPCODE_X0 = 90,
-  SRA_SPECIAL_0_OPCODE_X1 = 60,
-  SRA_SPECIAL_3_OPCODE_Y0 = 3,
-  SRA_SPECIAL_3_OPCODE_Y1 = 3,
-  SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
-  SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
-  SUBB_SPECIAL_0_OPCODE_X0 = 91,
-  SUBB_SPECIAL_0_OPCODE_X1 = 61,
-  SUBHS_SPECIAL_0_OPCODE_X0 = 101,
-  SUBHS_SPECIAL_0_OPCODE_X1 = 71,
-  SUBH_SPECIAL_0_OPCODE_X0 = 92,
-  SUBH_SPECIAL_0_OPCODE_X1 = 62,
-  SUBS_SPECIAL_0_OPCODE_X0 = 97,
-  SUBS_SPECIAL_0_OPCODE_X1 = 67,
-  SUB_SPECIAL_0_OPCODE_X0 = 93,
-  SUB_SPECIAL_0_OPCODE_X1 = 63,
-  SUB_SPECIAL_0_OPCODE_Y0 = 3,
-  SUB_SPECIAL_0_OPCODE_Y1 = 3,
-  SWADD_IMM_0_OPCODE_X1 = 30,
-  SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
-  SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
-  SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
-  SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
-  SW_OPCODE_Y2 = 7,
-  SW_SPECIAL_0_OPCODE_X1 = 64,
-  TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
-  TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
-  TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
-  TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
-  TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
-  TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
-  TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
-  TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
-  TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
-  UN_0_SHUN_0_OPCODE_X0 = 11,
-  UN_0_SHUN_0_OPCODE_X1 = 11,
-  UN_0_SHUN_0_OPCODE_Y0 = 5,
-  UN_0_SHUN_0_OPCODE_Y1 = 5,
-  WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
-  XORI_IMM_0_OPCODE_X0 = 2,
-  XORI_IMM_0_OPCODE_X1 = 21,
-  XOR_SPECIAL_0_OPCODE_X0 = 94,
-  XOR_SPECIAL_0_OPCODE_X1 = 65,
-  XOR_SPECIAL_2_OPCODE_Y0 = 3,
-  XOR_SPECIAL_2_OPCODE_Y1 = 3
+  ADDI_IMM8_OPCODE_X0 = 1,
+  ADDI_IMM8_OPCODE_X1 = 1,
+  ADDI_OPCODE_Y0 = 0,
+  ADDI_OPCODE_Y1 = 1,
+  ADDLI_OPCODE_X0 = 1,
+  ADDLI_OPCODE_X1 = 0,
+  ADDXI_IMM8_OPCODE_X0 = 2,
+  ADDXI_IMM8_OPCODE_X1 = 2,
+  ADDXI_OPCODE_Y0 = 1,
+  ADDXI_OPCODE_Y1 = 2,
+  ADDXLI_OPCODE_X0 = 2,
+  ADDXLI_OPCODE_X1 = 1,
+  ADDXSC_RRR_0_OPCODE_X0 = 1,
+  ADDXSC_RRR_0_OPCODE_X1 = 1,
+  ADDX_RRR_0_OPCODE_X0 = 2,
+  ADDX_RRR_0_OPCODE_X1 = 2,
+  ADDX_RRR_0_OPCODE_Y0 = 0,
+  ADDX_SPECIAL_0_OPCODE_Y1 = 0,
+  ADD_RRR_0_OPCODE_X0 = 3,
+  ADD_RRR_0_OPCODE_X1 = 3,
+  ADD_RRR_0_OPCODE_Y0 = 1,
+  ADD_SPECIAL_0_OPCODE_Y1 = 1,
+  ANDI_IMM8_OPCODE_X0 = 3,
+  ANDI_IMM8_OPCODE_X1 = 3,
+  ANDI_OPCODE_Y0 = 2,
+  ANDI_OPCODE_Y1 = 3,
+  AND_RRR_0_OPCODE_X0 = 4,
+  AND_RRR_0_OPCODE_X1 = 4,
+  AND_RRR_5_OPCODE_Y0 = 0,
+  AND_RRR_5_OPCODE_Y1 = 0,
+  BEQZT_BRANCH_OPCODE_X1 = 16,
+  BEQZ_BRANCH_OPCODE_X1 = 17,
+  BFEXTS_BF_OPCODE_X0 = 4,
+  BFEXTU_BF_OPCODE_X0 = 5,
+  BFINS_BF_OPCODE_X0 = 6,
+  BF_OPCODE_X0 = 3,
+  BGEZT_BRANCH_OPCODE_X1 = 18,
+  BGEZ_BRANCH_OPCODE_X1 = 19,
+  BGTZT_BRANCH_OPCODE_X1 = 20,
+  BGTZ_BRANCH_OPCODE_X1 = 21,
+  BLBCT_BRANCH_OPCODE_X1 = 22,
+  BLBC_BRANCH_OPCODE_X1 = 23,
+  BLBST_BRANCH_OPCODE_X1 = 24,
+  BLBS_BRANCH_OPCODE_X1 = 25,
+  BLEZT_BRANCH_OPCODE_X1 = 26,
+  BLEZ_BRANCH_OPCODE_X1 = 27,
+  BLTZT_BRANCH_OPCODE_X1 = 28,
+  BLTZ_BRANCH_OPCODE_X1 = 29,
+  BNEZT_BRANCH_OPCODE_X1 = 30,
+  BNEZ_BRANCH_OPCODE_X1 = 31,
+  BRANCH_OPCODE_X1 = 2,
+  CMOVEQZ_RRR_0_OPCODE_X0 = 5,
+  CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
+  CMOVNEZ_RRR_0_OPCODE_X0 = 6,
+  CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
+  CMPEQI_IMM8_OPCODE_X0 = 4,
+  CMPEQI_IMM8_OPCODE_X1 = 4,
+  CMPEQI_OPCODE_Y0 = 3,
+  CMPEQI_OPCODE_Y1 = 4,
+  CMPEQ_RRR_0_OPCODE_X0 = 7,
+  CMPEQ_RRR_0_OPCODE_X1 = 5,
+  CMPEQ_RRR_3_OPCODE_Y0 = 0,
+  CMPEQ_RRR_3_OPCODE_Y1 = 2,
+  CMPEXCH4_RRR_0_OPCODE_X1 = 6,
+  CMPEXCH_RRR_0_OPCODE_X1 = 7,
+  CMPLES_RRR_0_OPCODE_X0 = 8,
+  CMPLES_RRR_0_OPCODE_X1 = 8,
+  CMPLES_RRR_2_OPCODE_Y0 = 0,
+  CMPLES_RRR_2_OPCODE_Y1 = 0,
+  CMPLEU_RRR_0_OPCODE_X0 = 9,
+  CMPLEU_RRR_0_OPCODE_X1 = 9,
+  CMPLEU_RRR_2_OPCODE_Y0 = 1,
+  CMPLEU_RRR_2_OPCODE_Y1 = 1,
+  CMPLTSI_IMM8_OPCODE_X0 = 5,
+  CMPLTSI_IMM8_OPCODE_X1 = 5,
+  CMPLTSI_OPCODE_Y0 = 4,
+  CMPLTSI_OPCODE_Y1 = 5,
+  CMPLTS_RRR_0_OPCODE_X0 = 10,
+  CMPLTS_RRR_0_OPCODE_X1 = 10,
+  CMPLTS_RRR_2_OPCODE_Y0 = 2,
+  CMPLTS_RRR_2_OPCODE_Y1 = 2,
+  CMPLTUI_IMM8_OPCODE_X0 = 6,
+  CMPLTUI_IMM8_OPCODE_X1 = 6,
+  CMPLTU_RRR_0_OPCODE_X0 = 11,
+  CMPLTU_RRR_0_OPCODE_X1 = 11,
+  CMPLTU_RRR_2_OPCODE_Y0 = 3,
+  CMPLTU_RRR_2_OPCODE_Y1 = 3,
+  CMPNE_RRR_0_OPCODE_X0 = 12,
+  CMPNE_RRR_0_OPCODE_X1 = 12,
+  CMPNE_RRR_3_OPCODE_Y0 = 1,
+  CMPNE_RRR_3_OPCODE_Y1 = 3,
+  CMULAF_RRR_0_OPCODE_X0 = 13,
+  CMULA_RRR_0_OPCODE_X0 = 14,
+  CMULFR_RRR_0_OPCODE_X0 = 15,
+  CMULF_RRR_0_OPCODE_X0 = 16,
+  CMULHR_RRR_0_OPCODE_X0 = 17,
+  CMULH_RRR_0_OPCODE_X0 = 18,
+  CMUL_RRR_0_OPCODE_X0 = 19,
+  CNTLZ_UNARY_OPCODE_X0 = 1,
+  CNTLZ_UNARY_OPCODE_Y0 = 1,
+  CNTTZ_UNARY_OPCODE_X0 = 2,
+  CNTTZ_UNARY_OPCODE_Y0 = 2,
+  CRC32_32_RRR_0_OPCODE_X0 = 20,
+  CRC32_8_RRR_0_OPCODE_X0 = 21,
+  DBLALIGN2_RRR_0_OPCODE_X0 = 22,
+  DBLALIGN2_RRR_0_OPCODE_X1 = 13,
+  DBLALIGN4_RRR_0_OPCODE_X0 = 23,
+  DBLALIGN4_RRR_0_OPCODE_X1 = 14,
+  DBLALIGN6_RRR_0_OPCODE_X0 = 24,
+  DBLALIGN6_RRR_0_OPCODE_X1 = 15,
+  DBLALIGN_RRR_0_OPCODE_X0 = 25,
+  DRAIN_UNARY_OPCODE_X1 = 1,
+  DTLBPR_UNARY_OPCODE_X1 = 2,
+  EXCH4_RRR_0_OPCODE_X1 = 16,
+  EXCH_RRR_0_OPCODE_X1 = 17,
+  FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
+  FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
+  FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
+  FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
+  FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
+  FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
+  FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
+  FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
+  FETCHADD4_RRR_0_OPCODE_X1 = 18,
+  FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
+  FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
+  FETCHADD_RRR_0_OPCODE_X1 = 21,
+  FETCHAND4_RRR_0_OPCODE_X1 = 22,
+  FETCHAND_RRR_0_OPCODE_X1 = 23,
+  FETCHOR4_RRR_0_OPCODE_X1 = 24,
+  FETCHOR_RRR_0_OPCODE_X1 = 25,
+  FINV_UNARY_OPCODE_X1 = 3,
+  FLUSHWB_UNARY_OPCODE_X1 = 4,
+  FLUSH_UNARY_OPCODE_X1 = 5,
+  FNOP_UNARY_OPCODE_X0 = 3,
+  FNOP_UNARY_OPCODE_X1 = 6,
+  FNOP_UNARY_OPCODE_Y0 = 3,
+  FNOP_UNARY_OPCODE_Y1 = 8,
+  FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
+  FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
+  FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
+  FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
+  FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
+  FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
+  FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
+  FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
+  ICOH_UNARY_OPCODE_X1 = 7,
+  ILL_UNARY_OPCODE_X1 = 8,
+  ILL_UNARY_OPCODE_Y1 = 9,
+  IMM8_OPCODE_X0 = 4,
+  IMM8_OPCODE_X1 = 3,
+  INV_UNARY_OPCODE_X1 = 9,
+  IRET_UNARY_OPCODE_X1 = 10,
+  JALRP_UNARY_OPCODE_X1 = 11,
+  JALRP_UNARY_OPCODE_Y1 = 10,
+  JALR_UNARY_OPCODE_X1 = 12,
+  JALR_UNARY_OPCODE_Y1 = 11,
+  JAL_JUMP_OPCODE_X1 = 0,
+  JRP_UNARY_OPCODE_X1 = 13,
+  JRP_UNARY_OPCODE_Y1 = 12,
+  JR_UNARY_OPCODE_X1 = 14,
+  JR_UNARY_OPCODE_Y1 = 13,
+  JUMP_OPCODE_X1 = 4,
+  J_JUMP_OPCODE_X1 = 1,
+  LD1S_ADD_IMM8_OPCODE_X1 = 7,
+  LD1S_OPCODE_Y2 = 0,
+  LD1S_UNARY_OPCODE_X1 = 15,
+  LD1U_ADD_IMM8_OPCODE_X1 = 8,
+  LD1U_OPCODE_Y2 = 1,
+  LD1U_UNARY_OPCODE_X1 = 16,
+  LD2S_ADD_IMM8_OPCODE_X1 = 9,
+  LD2S_OPCODE_Y2 = 2,
+  LD2S_UNARY_OPCODE_X1 = 17,
+  LD2U_ADD_IMM8_OPCODE_X1 = 10,
+  LD2U_OPCODE_Y2 = 3,
+  LD2U_UNARY_OPCODE_X1 = 18,
+  LD4S_ADD_IMM8_OPCODE_X1 = 11,
+  LD4S_OPCODE_Y2 = 1,
+  LD4S_UNARY_OPCODE_X1 = 19,
+  LD4U_ADD_IMM8_OPCODE_X1 = 12,
+  LD4U_OPCODE_Y2 = 2,
+  LD4U_UNARY_OPCODE_X1 = 20,
+  LDNA_UNARY_OPCODE_X1 = 21,
+  LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
+  LDNT1S_UNARY_OPCODE_X1 = 22,
+  LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
+  LDNT1U_UNARY_OPCODE_X1 = 23,
+  LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
+  LDNT2S_UNARY_OPCODE_X1 = 24,
+  LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
+  LDNT2U_UNARY_OPCODE_X1 = 25,
+  LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
+  LDNT4S_UNARY_OPCODE_X1 = 26,
+  LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
+  LDNT4U_UNARY_OPCODE_X1 = 27,
+  LDNT_ADD_IMM8_OPCODE_X1 = 19,
+  LDNT_UNARY_OPCODE_X1 = 28,
+  LD_ADD_IMM8_OPCODE_X1 = 20,
+  LD_OPCODE_Y2 = 3,
+  LD_UNARY_OPCODE_X1 = 29,
+  LNK_UNARY_OPCODE_X1 = 30,
+  LNK_UNARY_OPCODE_Y1 = 14,
+  LWNA_ADD_IMM8_OPCODE_X1 = 21,
+  MFSPR_IMM8_OPCODE_X1 = 22,
+  MF_UNARY_OPCODE_X1 = 31,
+  MM_BF_OPCODE_X0 = 7,
+  MNZ_RRR_0_OPCODE_X0 = 40,
+  MNZ_RRR_0_OPCODE_X1 = 26,
+  MNZ_RRR_4_OPCODE_Y0 = 2,
+  MNZ_RRR_4_OPCODE_Y1 = 2,
+  MODE_OPCODE_YA2 = 1,
+  MODE_OPCODE_YB2 = 2,
+  MODE_OPCODE_YC2 = 3,
+  MTSPR_IMM8_OPCODE_X1 = 23,
+  MULAX_RRR_0_OPCODE_X0 = 41,
+  MULAX_RRR_3_OPCODE_Y0 = 2,
+  MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
+  MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
+  MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
+  MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
+  MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
+  MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
+  MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
+  MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
+  MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
+  MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
+  MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
+  MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
+  MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
+  MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
+  MULX_RRR_0_OPCODE_X0 = 52,
+  MULX_RRR_3_OPCODE_Y0 = 3,
+  MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
+  MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
+  MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
+  MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
+  MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
+  MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
+  MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
+  MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
+  MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
+  MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
+  MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
+  MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
+  MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
+  MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
+  MZ_RRR_0_OPCODE_X0 = 63,
+  MZ_RRR_0_OPCODE_X1 = 27,
+  MZ_RRR_4_OPCODE_Y0 = 3,
+  MZ_RRR_4_OPCODE_Y1 = 3,
+  NAP_UNARY_OPCODE_X1 = 32,
+  NOP_UNARY_OPCODE_X0 = 5,
+  NOP_UNARY_OPCODE_X1 = 33,
+  NOP_UNARY_OPCODE_Y0 = 5,
+  NOP_UNARY_OPCODE_Y1 = 15,
+  NOR_RRR_0_OPCODE_X0 = 64,
+  NOR_RRR_0_OPCODE_X1 = 28,
+  NOR_RRR_5_OPCODE_Y0 = 1,
+  NOR_RRR_5_OPCODE_Y1 = 1,
+  ORI_IMM8_OPCODE_X0 = 7,
+  ORI_IMM8_OPCODE_X1 = 24,
+  OR_RRR_0_OPCODE_X0 = 65,
+  OR_RRR_0_OPCODE_X1 = 29,
+  OR_RRR_5_OPCODE_Y0 = 2,
+  OR_RRR_5_OPCODE_Y1 = 2,
+  PCNT_UNARY_OPCODE_X0 = 6,
+  PCNT_UNARY_OPCODE_Y0 = 6,
+  REVBITS_UNARY_OPCODE_X0 = 7,
+  REVBITS_UNARY_OPCODE_Y0 = 7,
+  REVBYTES_UNARY_OPCODE_X0 = 8,
+  REVBYTES_UNARY_OPCODE_Y0 = 8,
+  ROTLI_SHIFT_OPCODE_X0 = 1,
+  ROTLI_SHIFT_OPCODE_X1 = 1,
+  ROTLI_SHIFT_OPCODE_Y0 = 0,
+  ROTLI_SHIFT_OPCODE_Y1 = 0,
+  ROTL_RRR_0_OPCODE_X0 = 66,
+  ROTL_RRR_0_OPCODE_X1 = 30,
+  ROTL_RRR_6_OPCODE_Y0 = 0,
+  ROTL_RRR_6_OPCODE_Y1 = 0,
+  RRR_0_OPCODE_X0 = 5,
+  RRR_0_OPCODE_X1 = 5,
+  RRR_0_OPCODE_Y0 = 5,
+  RRR_0_OPCODE_Y1 = 6,
+  RRR_1_OPCODE_Y0 = 6,
+  RRR_1_OPCODE_Y1 = 7,
+  RRR_2_OPCODE_Y0 = 7,
+  RRR_2_OPCODE_Y1 = 8,
+  RRR_3_OPCODE_Y0 = 8,
+  RRR_3_OPCODE_Y1 = 9,
+  RRR_4_OPCODE_Y0 = 9,
+  RRR_4_OPCODE_Y1 = 10,
+  RRR_5_OPCODE_Y0 = 10,
+  RRR_5_OPCODE_Y1 = 11,
+  RRR_6_OPCODE_Y0 = 11,
+  RRR_6_OPCODE_Y1 = 12,
+  RRR_7_OPCODE_Y0 = 12,
+  RRR_7_OPCODE_Y1 = 13,
+  RRR_8_OPCODE_Y0 = 13,
+  RRR_9_OPCODE_Y0 = 14,
+  SHIFT_OPCODE_X0 = 6,
+  SHIFT_OPCODE_X1 = 6,
+  SHIFT_OPCODE_Y0 = 15,
+  SHIFT_OPCODE_Y1 = 14,
+  SHL16INSLI_OPCODE_X0 = 7,
+  SHL16INSLI_OPCODE_X1 = 7,
+  SHL1ADDX_RRR_0_OPCODE_X0 = 67,
+  SHL1ADDX_RRR_0_OPCODE_X1 = 31,
+  SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
+  SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
+  SHL1ADD_RRR_0_OPCODE_X0 = 68,
+  SHL1ADD_RRR_0_OPCODE_X1 = 32,
+  SHL1ADD_RRR_1_OPCODE_Y0 = 0,
+  SHL1ADD_RRR_1_OPCODE_Y1 = 0,
+  SHL2ADDX_RRR_0_OPCODE_X0 = 69,
+  SHL2ADDX_RRR_0_OPCODE_X1 = 33,
+  SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
+  SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
+  SHL2ADD_RRR_0_OPCODE_X0 = 70,
+  SHL2ADD_RRR_0_OPCODE_X1 = 34,
+  SHL2ADD_RRR_1_OPCODE_Y0 = 1,
+  SHL2ADD_RRR_1_OPCODE_Y1 = 1,
+  SHL3ADDX_RRR_0_OPCODE_X0 = 71,
+  SHL3ADDX_RRR_0_OPCODE_X1 = 35,
+  SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
+  SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
+  SHL3ADD_RRR_0_OPCODE_X0 = 72,
+  SHL3ADD_RRR_0_OPCODE_X1 = 36,
+  SHL3ADD_RRR_1_OPCODE_Y0 = 2,
+  SHL3ADD_RRR_1_OPCODE_Y1 = 2,
+  SHLI_SHIFT_OPCODE_X0 = 2,
+  SHLI_SHIFT_OPCODE_X1 = 2,
+  SHLI_SHIFT_OPCODE_Y0 = 1,
+  SHLI_SHIFT_OPCODE_Y1 = 1,
+  SHLXI_SHIFT_OPCODE_X0 = 3,
+  SHLXI_SHIFT_OPCODE_X1 = 3,
+  SHLX_RRR_0_OPCODE_X0 = 73,
+  SHLX_RRR_0_OPCODE_X1 = 37,
+  SHL_RRR_0_OPCODE_X0 = 74,
+  SHL_RRR_0_OPCODE_X1 = 38,
+  SHL_RRR_6_OPCODE_Y0 = 1,
+  SHL_RRR_6_OPCODE_Y1 = 1,
+  SHRSI_SHIFT_OPCODE_X0 = 4,
+  SHRSI_SHIFT_OPCODE_X1 = 4,
+  SHRSI_SHIFT_OPCODE_Y0 = 2,
+  SHRSI_SHIFT_OPCODE_Y1 = 2,
+  SHRS_RRR_0_OPCODE_X0 = 75,
+  SHRS_RRR_0_OPCODE_X1 = 39,
+  SHRS_RRR_6_OPCODE_Y0 = 2,
+  SHRS_RRR_6_OPCODE_Y1 = 2,
+  SHRUI_SHIFT_OPCODE_X0 = 5,
+  SHRUI_SHIFT_OPCODE_X1 = 5,
+  SHRUI_SHIFT_OPCODE_Y0 = 3,
+  SHRUI_SHIFT_OPCODE_Y1 = 3,
+  SHRUXI_SHIFT_OPCODE_X0 = 6,
+  SHRUXI_SHIFT_OPCODE_X1 = 6,
+  SHRUX_RRR_0_OPCODE_X0 = 76,
+  SHRUX_RRR_0_OPCODE_X1 = 40,
+  SHRU_RRR_0_OPCODE_X0 = 77,
+  SHRU_RRR_0_OPCODE_X1 = 41,
+  SHRU_RRR_6_OPCODE_Y0 = 3,
+  SHRU_RRR_6_OPCODE_Y1 = 3,
+  SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
+  ST1_ADD_IMM8_OPCODE_X1 = 25,
+  ST1_OPCODE_Y2 = 0,
+  ST1_RRR_0_OPCODE_X1 = 42,
+  ST2_ADD_IMM8_OPCODE_X1 = 26,
+  ST2_OPCODE_Y2 = 1,
+  ST2_RRR_0_OPCODE_X1 = 43,
+  ST4_ADD_IMM8_OPCODE_X1 = 27,
+  ST4_OPCODE_Y2 = 2,
+  ST4_RRR_0_OPCODE_X1 = 44,
+  STNT1_ADD_IMM8_OPCODE_X1 = 28,
+  STNT1_RRR_0_OPCODE_X1 = 45,
+  STNT2_ADD_IMM8_OPCODE_X1 = 29,
+  STNT2_RRR_0_OPCODE_X1 = 46,
+  STNT4_ADD_IMM8_OPCODE_X1 = 30,
+  STNT4_RRR_0_OPCODE_X1 = 47,
+  STNT_ADD_IMM8_OPCODE_X1 = 31,
+  STNT_RRR_0_OPCODE_X1 = 48,
+  ST_ADD_IMM8_OPCODE_X1 = 32,
+  ST_OPCODE_Y2 = 3,
+  ST_RRR_0_OPCODE_X1 = 49,
+  SUBXSC_RRR_0_OPCODE_X0 = 79,
+  SUBXSC_RRR_0_OPCODE_X1 = 50,
+  SUBX_RRR_0_OPCODE_X0 = 80,
+  SUBX_RRR_0_OPCODE_X1 = 51,
+  SUBX_RRR_0_OPCODE_Y0 = 2,
+  SUBX_RRR_0_OPCODE_Y1 = 2,
+  SUB_RRR_0_OPCODE_X0 = 81,
+  SUB_RRR_0_OPCODE_X1 = 52,
+  SUB_RRR_0_OPCODE_Y0 = 3,
+  SUB_RRR_0_OPCODE_Y1 = 3,
+  SWINT0_UNARY_OPCODE_X1 = 34,
+  SWINT1_UNARY_OPCODE_X1 = 35,
+  SWINT2_UNARY_OPCODE_X1 = 36,
+  SWINT3_UNARY_OPCODE_X1 = 37,
+  TBLIDXB0_UNARY_OPCODE_X0 = 9,
+  TBLIDXB0_UNARY_OPCODE_Y0 = 9,
+  TBLIDXB1_UNARY_OPCODE_X0 = 10,
+  TBLIDXB1_UNARY_OPCODE_Y0 = 10,
+  TBLIDXB2_UNARY_OPCODE_X0 = 11,
+  TBLIDXB2_UNARY_OPCODE_Y0 = 11,
+  TBLIDXB3_UNARY_OPCODE_X0 = 12,
+  TBLIDXB3_UNARY_OPCODE_Y0 = 12,
+  UNARY_RRR_0_OPCODE_X0 = 82,
+  UNARY_RRR_0_OPCODE_X1 = 53,
+  UNARY_RRR_1_OPCODE_Y0 = 3,
+  UNARY_RRR_1_OPCODE_Y1 = 3,
+  V1ADDI_IMM8_OPCODE_X0 = 8,
+  V1ADDI_IMM8_OPCODE_X1 = 33,
+  V1ADDUC_RRR_0_OPCODE_X0 = 83,
+  V1ADDUC_RRR_0_OPCODE_X1 = 54,
+  V1ADD_RRR_0_OPCODE_X0 = 84,
+  V1ADD_RRR_0_OPCODE_X1 = 55,
+  V1ADIFFU_RRR_0_OPCODE_X0 = 85,
+  V1AVGU_RRR_0_OPCODE_X0 = 86,
+  V1CMPEQI_IMM8_OPCODE_X0 = 9,
+  V1CMPEQI_IMM8_OPCODE_X1 = 34,
+  V1CMPEQ_RRR_0_OPCODE_X0 = 87,
+  V1CMPEQ_RRR_0_OPCODE_X1 = 56,
+  V1CMPLES_RRR_0_OPCODE_X0 = 88,
+  V1CMPLES_RRR_0_OPCODE_X1 = 57,
+  V1CMPLEU_RRR_0_OPCODE_X0 = 89,
+  V1CMPLEU_RRR_0_OPCODE_X1 = 58,
+  V1CMPLTSI_IMM8_OPCODE_X0 = 10,
+  V1CMPLTSI_IMM8_OPCODE_X1 = 35,
+  V1CMPLTS_RRR_0_OPCODE_X0 = 90,
+  V1CMPLTS_RRR_0_OPCODE_X1 = 59,
+  V1CMPLTUI_IMM8_OPCODE_X0 = 11,
+  V1CMPLTUI_IMM8_OPCODE_X1 = 36,
+  V1CMPLTU_RRR_0_OPCODE_X0 = 91,
+  V1CMPLTU_RRR_0_OPCODE_X1 = 60,
+  V1CMPNE_RRR_0_OPCODE_X0 = 92,
+  V1CMPNE_RRR_0_OPCODE_X1 = 61,
+  V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
+  V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
+  V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
+  V1DDOTPU_RRR_0_OPCODE_X0 = 162,
+  V1DOTPA_RRR_0_OPCODE_X0 = 95,
+  V1DOTPUA_RRR_0_OPCODE_X0 = 163,
+  V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
+  V1DOTPUS_RRR_0_OPCODE_X0 = 97,
+  V1DOTPU_RRR_0_OPCODE_X0 = 164,
+  V1DOTP_RRR_0_OPCODE_X0 = 98,
+  V1INT_H_RRR_0_OPCODE_X0 = 99,
+  V1INT_H_RRR_0_OPCODE_X1 = 62,
+  V1INT_L_RRR_0_OPCODE_X0 = 100,
+  V1INT_L_RRR_0_OPCODE_X1 = 63,
+  V1MAXUI_IMM8_OPCODE_X0 = 12,
+  V1MAXUI_IMM8_OPCODE_X1 = 37,
+  V1MAXU_RRR_0_OPCODE_X0 = 101,
+  V1MAXU_RRR_0_OPCODE_X1 = 64,
+  V1MINUI_IMM8_OPCODE_X0 = 13,
+  V1MINUI_IMM8_OPCODE_X1 = 38,
+  V1MINU_RRR_0_OPCODE_X0 = 102,
+  V1MINU_RRR_0_OPCODE_X1 = 65,
+  V1MNZ_RRR_0_OPCODE_X0 = 103,
+  V1MNZ_RRR_0_OPCODE_X1 = 66,
+  V1MULTU_RRR_0_OPCODE_X0 = 104,
+  V1MULUS_RRR_0_OPCODE_X0 = 105,
+  V1MULU_RRR_0_OPCODE_X0 = 106,
+  V1MZ_RRR_0_OPCODE_X0 = 107,
+  V1MZ_RRR_0_OPCODE_X1 = 67,
+  V1SADAU_RRR_0_OPCODE_X0 = 108,
+  V1SADU_RRR_0_OPCODE_X0 = 109,
+  V1SHLI_SHIFT_OPCODE_X0 = 7,
+  V1SHLI_SHIFT_OPCODE_X1 = 7,
+  V1SHL_RRR_0_OPCODE_X0 = 110,
+  V1SHL_RRR_0_OPCODE_X1 = 68,
+  V1SHRSI_SHIFT_OPCODE_X0 = 8,
+  V1SHRSI_SHIFT_OPCODE_X1 = 8,
+  V1SHRS_RRR_0_OPCODE_X0 = 111,
+  V1SHRS_RRR_0_OPCODE_X1 = 69,
+  V1SHRUI_SHIFT_OPCODE_X0 = 9,
+  V1SHRUI_SHIFT_OPCODE_X1 = 9,
+  V1SHRU_RRR_0_OPCODE_X0 = 112,
+  V1SHRU_RRR_0_OPCODE_X1 = 70,
+  V1SUBUC_RRR_0_OPCODE_X0 = 113,
+  V1SUBUC_RRR_0_OPCODE_X1 = 71,
+  V1SUB_RRR_0_OPCODE_X0 = 114,
+  V1SUB_RRR_0_OPCODE_X1 = 72,
+  V2ADDI_IMM8_OPCODE_X0 = 14,
+  V2ADDI_IMM8_OPCODE_X1 = 39,
+  V2ADDSC_RRR_0_OPCODE_X0 = 115,
+  V2ADDSC_RRR_0_OPCODE_X1 = 73,
+  V2ADD_RRR_0_OPCODE_X0 = 116,
+  V2ADD_RRR_0_OPCODE_X1 = 74,
+  V2ADIFFS_RRR_0_OPCODE_X0 = 117,
+  V2AVGS_RRR_0_OPCODE_X0 = 118,
+  V2CMPEQI_IMM8_OPCODE_X0 = 15,
+  V2CMPEQI_IMM8_OPCODE_X1 = 40,
+  V2CMPEQ_RRR_0_OPCODE_X0 = 119,
+  V2CMPEQ_RRR_0_OPCODE_X1 = 75,
+  V2CMPLES_RRR_0_OPCODE_X0 = 120,
+  V2CMPLES_RRR_0_OPCODE_X1 = 76,
+  V2CMPLEU_RRR_0_OPCODE_X0 = 121,
+  V2CMPLEU_RRR_0_OPCODE_X1 = 77,
+  V2CMPLTSI_IMM8_OPCODE_X0 = 16,
+  V2CMPLTSI_IMM8_OPCODE_X1 = 41,
+  V2CMPLTS_RRR_0_OPCODE_X0 = 122,
+  V2CMPLTS_RRR_0_OPCODE_X1 = 78,
+  V2CMPLTUI_IMM8_OPCODE_X0 = 17,
+  V2CMPLTUI_IMM8_OPCODE_X1 = 42,
+  V2CMPLTU_RRR_0_OPCODE_X0 = 123,
+  V2CMPLTU_RRR_0_OPCODE_X1 = 79,
+  V2CMPNE_RRR_0_OPCODE_X0 = 124,
+  V2CMPNE_RRR_0_OPCODE_X1 = 80,
+  V2DOTPA_RRR_0_OPCODE_X0 = 125,
+  V2DOTP_RRR_0_OPCODE_X0 = 126,
+  V2INT_H_RRR_0_OPCODE_X0 = 127,
+  V2INT_H_RRR_0_OPCODE_X1 = 81,
+  V2INT_L_RRR_0_OPCODE_X0 = 128,
+  V2INT_L_RRR_0_OPCODE_X1 = 82,
+  V2MAXSI_IMM8_OPCODE_X0 = 18,
+  V2MAXSI_IMM8_OPCODE_X1 = 43,
+  V2MAXS_RRR_0_OPCODE_X0 = 129,
+  V2MAXS_RRR_0_OPCODE_X1 = 83,
+  V2MINSI_IMM8_OPCODE_X0 = 19,
+  V2MINSI_IMM8_OPCODE_X1 = 44,
+  V2MINS_RRR_0_OPCODE_X0 = 130,
+  V2MINS_RRR_0_OPCODE_X1 = 84,
+  V2MNZ_RRR_0_OPCODE_X0 = 131,
+  V2MNZ_RRR_0_OPCODE_X1 = 85,
+  V2MULFSC_RRR_0_OPCODE_X0 = 132,
+  V2MULS_RRR_0_OPCODE_X0 = 133,
+  V2MULTS_RRR_0_OPCODE_X0 = 134,
+  V2MZ_RRR_0_OPCODE_X0 = 135,
+  V2MZ_RRR_0_OPCODE_X1 = 86,
+  V2PACKH_RRR_0_OPCODE_X0 = 136,
+  V2PACKH_RRR_0_OPCODE_X1 = 87,
+  V2PACKL_RRR_0_OPCODE_X0 = 137,
+  V2PACKL_RRR_0_OPCODE_X1 = 88,
+  V2PACKUC_RRR_0_OPCODE_X0 = 138,
+  V2PACKUC_RRR_0_OPCODE_X1 = 89,
+  V2SADAS_RRR_0_OPCODE_X0 = 139,
+  V2SADAU_RRR_0_OPCODE_X0 = 140,
+  V2SADS_RRR_0_OPCODE_X0 = 141,
+  V2SADU_RRR_0_OPCODE_X0 = 142,
+  V2SHLI_SHIFT_OPCODE_X0 = 10,
+  V2SHLI_SHIFT_OPCODE_X1 = 10,
+  V2SHLSC_RRR_0_OPCODE_X0 = 143,
+  V2SHLSC_RRR_0_OPCODE_X1 = 90,
+  V2SHL_RRR_0_OPCODE_X0 = 144,
+  V2SHL_RRR_0_OPCODE_X1 = 91,
+  V2SHRSI_SHIFT_OPCODE_X0 = 11,
+  V2SHRSI_SHIFT_OPCODE_X1 = 11,
+  V2SHRS_RRR_0_OPCODE_X0 = 145,
+  V2SHRS_RRR_0_OPCODE_X1 = 92,
+  V2SHRUI_SHIFT_OPCODE_X0 = 12,
+  V2SHRUI_SHIFT_OPCODE_X1 = 12,
+  V2SHRU_RRR_0_OPCODE_X0 = 146,
+  V2SHRU_RRR_0_OPCODE_X1 = 93,
+  V2SUBSC_RRR_0_OPCODE_X0 = 147,
+  V2SUBSC_RRR_0_OPCODE_X1 = 94,
+  V2SUB_RRR_0_OPCODE_X0 = 148,
+  V2SUB_RRR_0_OPCODE_X1 = 95,
+  V4ADDSC_RRR_0_OPCODE_X0 = 149,
+  V4ADDSC_RRR_0_OPCODE_X1 = 96,
+  V4ADD_RRR_0_OPCODE_X0 = 150,
+  V4ADD_RRR_0_OPCODE_X1 = 97,
+  V4INT_H_RRR_0_OPCODE_X0 = 151,
+  V4INT_H_RRR_0_OPCODE_X1 = 98,
+  V4INT_L_RRR_0_OPCODE_X0 = 152,
+  V4INT_L_RRR_0_OPCODE_X1 = 99,
+  V4PACKSC_RRR_0_OPCODE_X0 = 153,
+  V4PACKSC_RRR_0_OPCODE_X1 = 100,
+  V4SHLSC_RRR_0_OPCODE_X0 = 154,
+  V4SHLSC_RRR_0_OPCODE_X1 = 101,
+  V4SHL_RRR_0_OPCODE_X0 = 155,
+  V4SHL_RRR_0_OPCODE_X1 = 102,
+  V4SHRS_RRR_0_OPCODE_X0 = 156,
+  V4SHRS_RRR_0_OPCODE_X1 = 103,
+  V4SHRU_RRR_0_OPCODE_X0 = 157,
+  V4SHRU_RRR_0_OPCODE_X1 = 104,
+  V4SUBSC_RRR_0_OPCODE_X0 = 158,
+  V4SUBSC_RRR_0_OPCODE_X1 = 105,
+  V4SUB_RRR_0_OPCODE_X0 = 159,
+  V4SUB_RRR_0_OPCODE_X1 = 106,
+  WH64_UNARY_OPCODE_X1 = 38,
+  XORI_IMM8_OPCODE_X0 = 20,
+  XORI_IMM8_OPCODE_X1 = 45,
+  XOR_RRR_0_OPCODE_X0 = 160,
+  XOR_RRR_0_OPCODE_X1 = 107,
+  XOR_RRR_5_OPCODE_Y0 = 3,
+  XOR_RRR_5_OPCODE_Y1 = 3
 };
 
 #endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
index 3eb53525bf9d..db93518fac03 100644
--- a/arch/tile/include/asm/page.h
+++ b/arch/tile/include/asm/page.h
@@ -16,7 +16,8 @@
 #define _ASM_TILE_PAGE_H
 
 #include <linux/const.h>
-#include <hv/pagesize.h>
+#include <hv/hypervisor.h>
+#include <arch/chip.h>
 
 /* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */
 #define PAGE_SHIFT      HV_LOG2_PAGE_SIZE_SMALL
@@ -28,8 +29,6 @@
 #define PAGE_MASK       (~(PAGE_SIZE - 1))
 #define HPAGE_MASK      (~(HPAGE_SIZE - 1))
 
-#ifdef __KERNEL__
-
 /*
  * If the Kconfig doesn't specify, set a maximum zone order that
  * is enough so that we can create huge pages from small pages given
@@ -39,9 +38,6 @@
 #define CONFIG_FORCE_MAX_ZONEORDER (HPAGE_SHIFT - PAGE_SHIFT + 1)
 #endif
 
-#include <hv/hypervisor.h>
-#include <arch/chip.h>
-
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
@@ -91,6 +87,10 @@ typedef struct page *pgtable_t;
 /* Must be a macro since it is used to create constants. */
 #define __pgprot(val) hv_pte(val)
 
+/* Rarely-used initializers, typically with a "zero" value. */
+#define __pte(x) hv_pte(x)
+#define __pgd(x) hv_pte(x)
+
 static inline u64 pgprot_val(pgprot_t pgprot)
 {
         return hv_pte_val(pgprot);
@@ -110,6 +110,8 @@ static inline u64 pgd_val(pgd_t pgd)
 
 typedef HV_PTE pmd_t;
 
+#define __pmd(x) hv_pte(x)
+
 static inline u64 pmd_val(pmd_t pmd)
 {
         return hv_pte_val(pmd);
@@ -318,7 +320,7 @@ static inline int pfn_valid(unsigned long pfn)
 
 /* Provide as macros since these require some other headers included. */
 #define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT)
-#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn(kaddr))
+#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn((void *)(kaddr)))
 #define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page))
 
 struct mm_struct;
@@ -331,6 +333,4 @@ extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
 
 #include <asm-generic/memory_model.h>
 
-#endif /* __KERNEL__ */
-
 #endif /* _ASM_TILE_PAGE_H */
diff --git a/arch/tile/include/asm/parport.h b/arch/tile/include/asm/parport.h
new file mode 100644
index 000000000000..cf252af64590
--- /dev/null
+++ b/arch/tile/include/asm/parport.h
@@ -0,0 +1 @@
+#include <asm-generic/parport.h>
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index c3fc458a0d32..7f03cefed1b9 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -46,7 +46,8 @@ struct pci_controller {
  */
 #define PCI_DMA_BUS_IS_PHYS     1
 
-int __init tile_pci_init(void);
+int __devinit tile_pci_init(void);
+int __devinit pcibios_init(void);
 
 void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
diff --git a/arch/tile/include/asm/pgtable_64.h b/arch/tile/include/asm/pgtable_64.h
new file mode 100644
index 000000000000..fd80328523b4
--- /dev/null
+++ b/arch/tile/include/asm/pgtable_64.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ */
+
+#ifndef _ASM_TILE_PGTABLE_64_H
+#define _ASM_TILE_PGTABLE_64_H
+
+/* The level-0 page table breaks the address space into 32-bit chunks. */
+#define PGDIR_SHIFT     HV_LOG2_L1_SPAN
+#define PGDIR_SIZE      HV_L1_SPAN
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+#define PTRS_PER_PGD    HV_L0_ENTRIES
+#define SIZEOF_PGD      (PTRS_PER_PGD * sizeof(pgd_t))
+
+/*
+ * The level-1 index is defined by the huge page size.  A PMD is composed
+ * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
+ */
+#define PMD_SHIFT       HV_LOG2_PAGE_SIZE_LARGE
+#define PMD_SIZE        HV_PAGE_SIZE_LARGE
+#define PMD_MASK        (~(PMD_SIZE-1))
+#define PTRS_PER_PMD    (1 << (PGDIR_SHIFT - PMD_SHIFT))
+#define SIZEOF_PMD      (PTRS_PER_PMD * sizeof(pmd_t))
+
+/*
+ * The level-2 index is defined by the difference between the huge
+ * page size and the normal page size.  A PTE is composed of
+ * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
+ * Note that the hypervisor docs use PTE for what we call pte_t, so
+ * this nomenclature is somewhat confusing.
+ */
+#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
+#define SIZEOF_PTE      (PTRS_PER_PTE * sizeof(pte_t))
+
+/*
+ * Align the vmalloc area to an L2 page table, and leave a guard page
+ * at the beginning and end.  The vmalloc code also puts in an internal
+ * guard page between each allocation.
+ */
+#define _VMALLOC_END    HUGE_VMAP_BASE
+#define VMALLOC_END     (_VMALLOC_END - PAGE_SIZE)
+#define VMALLOC_START   (_VMALLOC_START + PAGE_SIZE)
+
+#define HUGE_VMAP_END   (HUGE_VMAP_BASE + PGDIR_SIZE)
+
+#ifndef __ASSEMBLY__
+
+/* We have no pud since we are a three-level page table. */
+#include <asm-generic/pgtable-nopud.h>
+
+static inline int pud_none(pud_t pud)
+{
+        return pud_val(pud) == 0;
+}
+
+static inline int pud_present(pud_t pud)
+{
+        return pud_val(pud) & _PAGE_PRESENT;
+}
+
+#define pmd_ERROR(e) \
+        pr_err("%s:%d: bad pmd 0x%016llx.\n", __FILE__, __LINE__, pmd_val(e))
+
+static inline void pud_clear(pud_t *pudp)
+{
+        __pte_clear(&pudp->pgd);
+}
+
+static inline int pud_bad(pud_t pud)
+{
+        return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
+}
+
+/* Return the page-table frame number (ptfn) that a pud_t points at. */
+#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
+
+/*
+ * A given kernel pud_t maps to a kernel pmd_t table at a specific
+ * virtual address.  Since kernel pmd_t tables can be aligned at
+ * sub-page granularity, this macro can return non-page-aligned
+ * pointers, despite its name.
+ */
+#define pud_page_vaddr(pud) \
+        (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
+
+/*
+ * A pud_t points to a pmd_t array.  Since we can have multiple per
+ * page, we don't have a one-to-one mapping of pud_t's to pages.
+ */
+#define pud_page(pud) pfn_to_page(HV_PTFN_TO_PFN(pud_ptfn(pud)))
+
+static inline unsigned long pud_index(unsigned long address)
+{
+        return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
+}
+
+#define pmd_offset(pud, address) \
+        ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
+
+static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
+{
+        set_pte(pmdp, pmdval);
+}
+
+/* Create a pmd from a PTFN and pgprot. */
+static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
+{
+        return hv_pte_set_ptfn(prot, ptfn);
+}
+
+/* Return the page-table frame number (ptfn) that a pmd_t points at. */
+static inline unsigned long pmd_ptfn(pmd_t pmd)
+{
+        return hv_pte_get_ptfn(pmd);
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+        __pte_clear(pmdp);
+}
+
+/* Normalize an address to having the correct high bits set. */
+#define pgd_addr_normalize pgd_addr_normalize
+static inline unsigned long pgd_addr_normalize(unsigned long addr)
+{
+        return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
+                (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
+}
+
+/* We don't define any pgds for these addresses. */
+static inline int pgd_addr_invalid(unsigned long addr)
+{
+        return addr >= MEM_HV_START ||
+                (addr > MEM_LOW_END && addr < MEM_HIGH_START);
+}
+
+/*
+ * Use atomic instructions to provide atomicity against the hypervisor.
+ */
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
+                HV_PTE_INDEX_ACCESSED) & 0x1;
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm,
+                                      unsigned long addr, pte_t *ptep)
+{
+        __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
+}
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+                                       unsigned long addr, pte_t *ptep)
+{
+        return hv_pte(__insn_exch(&ptep->val, 0UL));
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_TILE_PGTABLE_64_H */
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index e6889474038a..34c1e01ffb5e 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -215,6 +215,8 @@ static inline void release_thread(struct task_struct *dead_task)
 
 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
 
+extern int do_work_pending(struct pt_regs *regs, u32 flags);
+
 
 /*
  * Return saved (kernel) PC of a blocked thread.
@@ -255,10 +257,6 @@ static inline void cpu_relax(void)
         barrier();
 }
 
-struct siginfo;
-extern void arch_coredump_signal(struct siginfo *, struct pt_regs *);
-#define arch_coredump_signal arch_coredump_signal
-
 /* Info on this processor (see fs/proc/cpuinfo.c) */
 struct seq_operations;
 extern const struct seq_operations cpuinfo_op;
@@ -269,9 +267,6 @@ extern char chip_model[64];
 /* Data on which physical memory controller corresponds to which NUMA node. */
 extern int node_controller[];
 
-/* Do we dump information to the console when a user application crashes? */
-extern int show_crashinfo;
-
 #if CHIP_HAS_CBOX_HOME_MAP()
 /* Does the heap allocator return hash-for-home pages by default? */
 extern int hash_default;
diff --git a/arch/tile/include/asm/serial.h b/arch/tile/include/asm/serial.h
new file mode 100644
index 000000000000..a0cb0caff152
--- /dev/null
+++ b/arch/tile/include/asm/serial.h
@@ -0,0 +1 @@
+#include <asm-generic/serial.h>
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
index 81d92a45cd4b..1e1e616783eb 100644
--- a/arch/tile/include/asm/signal.h
+++ b/arch/tile/include/asm/signal.h
@@ -28,6 +28,10 @@ struct pt_regs;
 int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
 int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
 void do_signal(struct pt_regs *regs);
+void signal_fault(const char *type, struct pt_regs *,
+                  void __user *frame, int sig);
+void trace_unhandled_signal(const char *type, struct pt_regs *regs,
+                            unsigned long address, int signo);
 #endif
 
 #endif /* _ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/asm/spinlock_64.h b/arch/tile/include/asm/spinlock_64.h
new file mode 100644
index 000000000000..72be5904e020
--- /dev/null
+++ b/arch/tile/include/asm/spinlock_64.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
+ * (the type definitions are in asm/spinlock_types.h)
+ */
+
+#ifndef _ASM_TILE_SPINLOCK_64_H
+#define _ASM_TILE_SPINLOCK_64_H
+
+/* Shifts and masks for the various fields in "lock". */
+#define __ARCH_SPIN_CURRENT_SHIFT       17
+#define __ARCH_SPIN_NEXT_MASK           0x7fff
+#define __ARCH_SPIN_NEXT_OVERFLOW       0x8000
+
+/*
+ * Return the "current" portion of a ticket lock value,
+ * i.e. the number that currently owns the lock.
+ */
+static inline int arch_spin_current(u32 val)
+{
+        return val >> __ARCH_SPIN_CURRENT_SHIFT;
+}
+
+/*
+ * Return the "next" portion of a ticket lock value,
+ * i.e. the number that the next task to try to acquire the lock will get.
+ */
+static inline int arch_spin_next(u32 val)
+{
+        return val & __ARCH_SPIN_NEXT_MASK;
+}
+
+/* The lock is locked if a task would have to wait to get it. */
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+        u32 val = lock->lock;
+        return arch_spin_current(val) != arch_spin_next(val);
+}
+
+/* Bump the current ticket so the next task owns the lock. */
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
+{
+        wmb();  /* guarantee anything modified under the lock is visible */
+        __insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
+}
+
+void arch_spin_unlock_wait(arch_spinlock_t *lock);
+
+void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
+
+/* Grab the "next" ticket number and bump it atomically.
+ * If the current ticket is not ours, go to the slow path.
+ * We also take the slow path if the "next" value overflows.
+ */
+static inline void arch_spin_lock(arch_spinlock_t *lock)
+{
+        u32 val = __insn_fetchadd4(&lock->lock, 1);
+        u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
+        if (unlikely(arch_spin_current(val) != ticket))
+                arch_spin_lock_slow(lock, ticket);
+}
+
+/* Try to get the lock, and return whether we succeeded. */
+int arch_spin_trylock(arch_spinlock_t *lock);
+
+/* We cannot take an interrupt after getting a ticket, so don't enable them. */
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * We use fetchadd() for readers, and fetchor() with the sign bit
+ * for writers.
+ */
+
+#define __WRITE_LOCK_BIT (1 << 31)
+
+static inline int arch_write_val_locked(int val)
+{
+        return val < 0;  /* Optimize "val & __WRITE_LOCK_BIT". */
+}
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+static inline int arch_read_can_lock(arch_rwlock_t *rw)
+{
+        return !arch_write_val_locked(rw->lock);
+}
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+static inline int arch_write_can_lock(arch_rwlock_t *rw)
+{
+        return rw->lock == 0;
+}
+
+extern void __read_lock_failed(arch_rwlock_t *rw);
+
+static inline void arch_read_lock(arch_rwlock_t *rw)
+{
+        u32 val = __insn_fetchaddgez4(&rw->lock, 1);
+        if (unlikely(arch_write_val_locked(val)))
+                __read_lock_failed(rw);
+}
+
+extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
+
+static inline void arch_write_lock(arch_rwlock_t *rw)
+{
+        u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
+        if (unlikely(val != 0))
+                __write_lock_failed(rw, val);
+}
+
+static inline void arch_read_unlock(arch_rwlock_t *rw)
+{
+        __insn_mf();
+        __insn_fetchadd4(&rw->lock, -1);
+}
+
+static inline void arch_write_unlock(arch_rwlock_t *rw)
+{
+        __insn_mf();
+        rw->lock = 0;
+}
+
+static inline int arch_read_trylock(arch_rwlock_t *rw)
+{
+        return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
+}
+
+static inline int arch_write_trylock(arch_rwlock_t *rw)
+{
+        u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
+        if (likely(val == 0))
+                return 1;
+        if (!arch_write_val_locked(val))
+                __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
+        return 0;
+}
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#endif /* _ASM_TILE_SPINLOCK_64_H */
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
index b16e5db8f0e7..c0db34d56be3 100644
--- a/arch/tile/include/asm/stat.h
+++ b/arch/tile/include/asm/stat.h
@@ -1,4 +1,4 @@
-#ifdef CONFIG_COMPAT
+#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
 #define __ARCH_WANT_STAT64      /* Used for compat_sys_stat64() etc. */
 #endif
 #include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/swab.h b/arch/tile/include/asm/swab.h
index 25c686a00f1d..7c37b38f6c8d 100644
--- a/arch/tile/include/asm/swab.h
+++ b/arch/tile/include/asm/swab.h
@@ -18,12 +18,6 @@
 /* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
 #define __arch_swab32(x) __builtin_bswap32(x)
 #define __arch_swab64(x) __builtin_bswap64(x)
-
-/* Use the variant that is natural for the wordsize. */
-#ifdef CONFIG_64BIT
-#define __arch_swab16(x) (__builtin_bswap64(x) >> 48)
-#else
 #define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
-#endif
 
 #endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
index 3405b52853b8..bc4f562bd459 100644
--- a/arch/tile/include/asm/thread_info.h
+++ b/arch/tile/include/asm/thread_info.h
@@ -125,6 +125,7 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
 #define TIF_SYSCALL_AUDIT       5       /* syscall auditing active */
 #define TIF_SECCOMP             6       /* secure computing */
 #define TIF_MEMDIE              7       /* OOM killer at work */
+#define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
 
 #define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
@@ -134,10 +135,12 @@ extern void cpu_idle_on_new_stack(struct thread_info *old_ti,
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
 #define _TIF_MEMDIE             (1<<TIF_MEMDIE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 
 /* Work to do on any return to user space. */
 #define _TIF_ALLWORK_MASK \
-  (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|_TIF_ASYNC_TLB)
+  (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|\
+   _TIF_ASYNC_TLB|_TIF_NOTIFY_RESUME)
 
 /*
  * Thread-synchronous status.
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h
index 343172d422a9..6fdd0c860193 100644
--- a/arch/tile/include/asm/topology.h
+++ b/arch/tile/include/asm/topology.h
@@ -44,25 +44,64 @@ static inline const struct cpumask *cpumask_of_node(int node)
 /* For now, use numa node -1 for global allocation. */
 #define pcibus_to_node(bus)             ((void)(bus), -1)
 
+/*
+ * TILE architecture has many cores integrated in one processor, so we need
+ * setup bigger balance_interval for both CPU/NODE scheduling domains to
+ * reduce process scheduling costs.
+ */
+
+/* sched_domains SD_CPU_INIT for TILE architecture */
+#define SD_CPU_INIT (struct sched_domain) {                             \
+        .min_interval           = 4,                                    \
+        .max_interval           = 128,                                  \
+        .busy_factor            = 64,                                   \
+        .imbalance_pct          = 125,                                  \
+        .cache_nice_tries       = 1,                                    \
+        .busy_idx               = 2,                                    \
+        .idle_idx               = 1,                                    \
+        .newidle_idx            = 0,                                    \
+        .wake_idx               = 0,                                    \
+        .forkexec_idx           = 0,                                    \
+                                                                        \
+        .flags                  = 1*SD_LOAD_BALANCE                     \
+                                | 1*SD_BALANCE_NEWIDLE                  \
+                                | 1*SD_BALANCE_EXEC                     \
+                                | 1*SD_BALANCE_FORK                     \
+                                | 0*SD_BALANCE_WAKE                     \
+                                | 0*SD_WAKE_AFFINE                      \
+                                | 0*SD_PREFER_LOCAL                     \
+                                | 0*SD_SHARE_CPUPOWER                   \
+                                | 0*SD_SHARE_PKG_RESOURCES              \
+                                | 0*SD_SERIALIZE                        \
+                                ,                                       \
+        .last_balance           = jiffies,                              \
+        .balance_interval       = 32,                                   \
+}
+
 /* sched_domains SD_NODE_INIT for TILE architecture */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 1,                    \
-        .busy_idx               = 3,                    \
-        .idle_idx               = 1,                    \
-        .newidle_idx            = 2,                    \
-        .wake_idx               = 1,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_NEWIDLE    \
-                                | SD_BALANCE_EXEC       \
-                                | SD_BALANCE_FORK       \
-                                | SD_WAKE_AFFINE        \
-                                | SD_SERIALIZE,         \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
+#define SD_NODE_INIT (struct sched_domain) {                            \
+        .min_interval           = 16,                                   \
+        .max_interval           = 512,                                  \
+        .busy_factor            = 32,                                   \
+        .imbalance_pct          = 125,                                  \
+        .cache_nice_tries       = 1,                                    \
+        .busy_idx               = 3,                                    \
+        .idle_idx               = 1,                                    \
+        .newidle_idx            = 2,                                    \
+        .wake_idx               = 1,                                    \
+        .flags                  = 1*SD_LOAD_BALANCE                     \
+                                | 1*SD_BALANCE_NEWIDLE                  \
+                                | 1*SD_BALANCE_EXEC                     \
+                                | 1*SD_BALANCE_FORK                     \
+                                | 0*SD_BALANCE_WAKE                     \
+                                | 0*SD_WAKE_AFFINE                      \
+                                | 0*SD_PREFER_LOCAL                     \
+                                | 0*SD_SHARE_CPUPOWER                   \
+                                | 0*SD_SHARE_PKG_RESOURCES              \
+                                | 1*SD_SERIALIZE                        \
+                                ,                                       \
+        .last_balance           = jiffies,                              \
+        .balance_interval       = 128,                                  \
 }
 
 /* By definition, we create nodes based on online memory. */
diff --git a/arch/tile/include/asm/traps.h b/arch/tile/include/asm/traps.h
index d06e35f57201..5f20f920f932 100644
--- a/arch/tile/include/asm/traps.h
+++ b/arch/tile/include/asm/traps.h
@@ -15,10 +15,14 @@
 #ifndef _ASM_TILE_TRAPS_H
 #define _ASM_TILE_TRAPS_H
 
+#include <arch/chip.h>
+
 /* mm/fault.c */
 void do_page_fault(struct pt_regs *, int fault_num,
                    unsigned long address, unsigned long write);
+#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
 void do_async_page_fault(struct pt_regs *);
+#endif
 
 #ifndef __tilegx__
 /*
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index b35c2db71199..f70bf1c541f1 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -15,7 +15,7 @@
 #if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL)
 #define _ASM_TILE_UNISTD_H
 
-#ifndef __LP64__
+#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
 /* Use the flavor of this syscall that matches the 32-bit API better. */
 #define __ARCH_WANT_SYNC_FILE_RANGE2
 #endif
diff --git a/arch/tile/include/hv/pagesize.h b/arch/tile/include/asm/vga.h
index 58bed114fedd..7b46e754d611 100644
--- a/arch/tile/include/hv/pagesize.h
+++ b/arch/tile/include/asm/vga.h
@@ -10,23 +10,30 @@
  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  *   NON INFRINGEMENT.  See the GNU General Public License for
  *   more details.
+ *
+ * Access to VGA videoram.
  */
 
-/**
- * @file pagesize.h
- */
+#ifndef _ASM_TILE_VGA_H
+#define _ASM_TILE_VGA_H
 
-#ifndef _HV_PAGESIZE_H
-#define _HV_PAGESIZE_H
+#include <asm/io.h>
 
-/** The log2 of the size of small pages, in bytes. This value should
- * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
- */
-#define HV_LOG2_PAGE_SIZE_SMALL 16
+#define VT_BUF_HAVE_RW
 
-/** The log2 of the size of large pages, in bytes. This value should be
- * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
- */
-#define HV_LOG2_PAGE_SIZE_LARGE 24
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+        __raw_writew(val, (volatile u16 __iomem *) addr);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+        return __raw_readw((volatile const u16 __iomem *) addr);
+}
+
+#define vga_readb(a)    readb((u8 __iomem *)(a))
+#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
+
+#define VGA_MAP_MEM(x,s)        ((unsigned long) ioremap(x, s))
 
-#endif /* _HV_PAGESIZE_H */
+#endif
diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h
index ee41bca4c8c4..72ec1e972f15 100644
--- a/arch/tile/include/hv/hypervisor.h
+++ b/arch/tile/include/hv/hypervisor.h
@@ -22,8 +22,6 @@
 
 #include <arch/chip.h>
 
-#include <hv/pagesize.h>
-
 /* Linux builds want unsigned long constants, but assembler wants numbers */
 #ifdef __ASSEMBLER__
 /** One, for assembler */
@@ -44,11 +42,21 @@
  */
 #define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
 
+/** The log2 of the size of small pages, in bytes. This value should
+ * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
+ */
+#define HV_LOG2_PAGE_SIZE_SMALL 16
+
 /** The size of small pages, in bytes. This value should be verified
  * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
  */
 #define HV_PAGE_SIZE_SMALL (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_SMALL)
 
+/** The log2 of the size of large pages, in bytes. This value should be
+ * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
+ */
+#define HV_LOG2_PAGE_SIZE_LARGE 24
+
 /** The size of large pages, in bytes. This value should be verified
  * at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
  */
diff --git a/arch/tile/kernel/Makefile b/arch/tile/kernel/Makefile
index b4c8e8ec45dc..b4dbc057baad 100644
--- a/arch/tile/kernel/Makefile
+++ b/arch/tile/kernel/Makefile
@@ -5,7 +5,7 @@
 extra-y := vmlinux.lds head_$(BITS).o
 obj-y := backtrace.o entry.o init_task.o irq.o messaging.o \
         pci-dma.o proc.o process.o ptrace.o reboot.o \
-        setup.o signal.o single_step.o stack.o sys.o time.o traps.o \
+        setup.o signal.o single_step.o stack.o sys.o sysfs.o time.o traps.o \
         intvec_$(BITS).o regs_$(BITS).o tile-desc_$(BITS).o
 
 obj-$(CONFIG_HARDWALL)          += hardwall.o
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c
index 55a6a74974b4..1dc71eabfc5a 100644
--- a/arch/tile/kernel/backtrace.c
+++ b/arch/tile/kernel/backtrace.c
@@ -14,19 +14,11 @@
 
 #include <linux/kernel.h>
 #include <linux/string.h>
-
 #include <asm/backtrace.h>
-
-#include <arch/chip.h>
-
 #include <asm/opcode-tile.h>
+#include <arch/abi.h>
 
-
-#define TREG_SP 54
-#define TREG_LR 55
-
-
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
 #define tile_bundle_bits tilegx_bundle_bits
 #define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE
 #define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
@@ -47,7 +39,7 @@ typedef long long bt_int_reg_t;
 typedef int bt_int_reg_t;
 #endif
 
-/** A decoded bundle used for backtracer analysis. */
+/* A decoded bundle used for backtracer analysis. */
 struct BacktraceBundle {
         tile_bundle_bits bits;
         int num_insns;
@@ -56,23 +48,7 @@ struct BacktraceBundle {
 };
 
 
-/* This implementation only makes sense for native tools. */
-/** Default function to read memory. */
-static bool bt_read_memory(void *result, VirtualAddress addr,
-                           unsigned int size, void *extra)
-{
-        /* FIXME: this should do some horrible signal stuff to catch
-         * SEGV cleanly and fail.
-         *
-         * Or else the caller should do the setjmp for efficiency.
-         */
-
-        memcpy(result, (const void *)addr, size);
-        return true;
-}
-
-
-/** Locates an instruction inside the given bundle that
+/* Locates an instruction inside the given bundle that
  * has the specified mnemonic, and whose first 'num_operands_to_match'
  * operands exactly match those in 'operand_values'.
  */
@@ -107,13 +83,13 @@ static const struct tile_decoded_instruction *find_matching_insn(
         return NULL;
 }
 
-/** Does this bundle contain an 'iret' instruction? */
+/* Does this bundle contain an 'iret' instruction? */
 static inline bool bt_has_iret(const struct BacktraceBundle *bundle)
 {
         return find_matching_insn(bundle, TILE_OPC_IRET, NULL, 0) != NULL;
 }
 
-/** Does this bundle contain an 'addi sp, sp, OFFSET' or
+/* Does this bundle contain an 'addi sp, sp, OFFSET' or
  * 'addli sp, sp, OFFSET' instruction, and if so, what is OFFSET?
  */
 static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
@@ -124,7 +100,7 @@ static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
                 find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2);
         if (insn == NULL)
                 insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2);
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
         if (insn == NULL)
                 insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2);
         if (insn == NULL)
@@ -137,7 +113,7 @@ static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
         return true;
 }
 
-/** Does this bundle contain any 'info OP' or 'infol OP'
+/* Does this bundle contain any 'info OP' or 'infol OP'
  * instruction, and if so, what are their OP?  Note that OP is interpreted
  * as an unsigned value by this code since that's what the caller wants.
  * Returns the number of info ops found.
@@ -161,7 +137,7 @@ static int bt_get_info_ops(const struct BacktraceBundle *bundle,
         return num_ops;
 }
 
-/** Does this bundle contain a jrp instruction, and if so, to which
+/* Does this bundle contain a jrp instruction, and if so, to which
  * register is it jumping?
  */
 static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg)
@@ -175,7 +151,7 @@ static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg)
         return true;
 }
 
-/** Does this bundle modify the specified register in any way? */
+/* Does this bundle modify the specified register in any way? */
 static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg)
 {
         int i, j;
@@ -195,34 +171,34 @@ static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg)
         return false;
 }
 
-/** Does this bundle modify sp? */
+/* Does this bundle modify sp? */
 static inline bool bt_modifies_sp(const struct BacktraceBundle *bundle)
 {
         return bt_modifies_reg(bundle, TREG_SP);
 }
 
-/** Does this bundle modify lr? */
+/* Does this bundle modify lr? */
 static inline bool bt_modifies_lr(const struct BacktraceBundle *bundle)
 {
         return bt_modifies_reg(bundle, TREG_LR);
 }
 
-/** Does this bundle contain the instruction 'move fp, sp'? */
+/* Does this bundle contain the instruction 'move fp, sp'? */
 static inline bool bt_has_move_r52_sp(const struct BacktraceBundle *bundle)
 {
         static const int vals[2] = { 52, TREG_SP };
         return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL;
 }
 
-/** Does this bundle contain a store of lr to sp? */
+/* Does this bundle contain a store of lr to sp? */
 static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle)
 {
         static const int vals[2] = { TREG_SP, TREG_LR };
         return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL;
 }
 
-#if TILE_CHIP >= 10
-/** Track moveli values placed into registers. */
+#ifdef __tilegx__
+/* Track moveli values placed into registers. */
 static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
                                     int moveli_args[])
 {
@@ -238,7 +214,7 @@ static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
         }
 }
 
-/** Does this bundle contain an 'add sp, sp, reg' instruction
+/* Does this bundle contain an 'add sp, sp, reg' instruction
  * from a register that we saw a moveli into, and if so, what
  * is the value in the register?
  */
@@ -260,11 +236,11 @@ static bool bt_has_add_sp(const struct BacktraceBundle *bundle, int *adjust,
 }
 #endif
 
-/** Locates the caller's PC and SP for a program starting at the
+/* Locates the caller's PC and SP for a program starting at the
  * given address.
  */
 static void find_caller_pc_and_caller_sp(CallerLocation *location,
-                                         const VirtualAddress start_pc,
+                                         const unsigned long start_pc,
                                          BacktraceMemoryReader read_memory_func,
                                          void *read_memory_func_extra)
 {
@@ -288,9 +264,9 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
         tile_bundle_bits prefetched_bundles[32];
         int num_bundles_prefetched = 0;
         int next_bundle = 0;
-        VirtualAddress pc;
+        unsigned long pc;
 
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
         /* Naively try to track moveli values to support addx for -m32. */
         int moveli_args[TILEGX_NUM_REGISTERS] = { 0 };
 #endif
@@ -369,10 +345,6 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
                                         /* Weird; reserved value, ignore it. */
                                         continue;
                                 }
-                                if (info_operand & ENTRY_POINT_INFO_OP) {
-                                        /* This info op is ignored by the backtracer. */
-                                        continue;
-                                }
 
                                 /* Skip info ops which are not in the
                                  * "one_ago" mode we want right now.
@@ -453,7 +425,7 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
                 if (!sp_determined) {
                         int adjust;
                         if (bt_has_addi_sp(&bundle, &adjust)
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
                             || bt_has_add_sp(&bundle, &adjust, moveli_args)
 #endif
                                 ) {
@@ -504,7 +476,7 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
                                 }
                         }
 
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
                         /* Track moveli arguments for -m32 mode. */
                         bt_update_moveli(&bundle, moveli_args);
 #endif
@@ -546,18 +518,26 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
         }
 }
 
+/* Initializes a backtracer to start from the given location.
+ *
+ * If the frame pointer cannot be determined it is set to -1.
+ *
+ * state: The state to be filled in.
+ * read_memory_func: A callback that reads memory.
+ * read_memory_func_extra: An arbitrary argument to read_memory_func.
+ * pc: The current PC.
+ * lr: The current value of the 'lr' register.
+ * sp: The current value of the 'sp' register.
+ * r52: The current value of the 'r52' register.
+ */
 void backtrace_init(BacktraceIterator *state,
                     BacktraceMemoryReader read_memory_func,
                     void *read_memory_func_extra,
-                    VirtualAddress pc, VirtualAddress lr,
-                    VirtualAddress sp, VirtualAddress r52)
+                    unsigned long pc, unsigned long lr,
+                    unsigned long sp, unsigned long r52)
 {
         CallerLocation location;
-        VirtualAddress fp, initial_frame_caller_pc;
-
-        if (read_memory_func == NULL) {
-                read_memory_func = bt_read_memory;
-        }
+        unsigned long fp, initial_frame_caller_pc;
 
         /* Find out where we are in the initial frame. */
         find_caller_pc_and_caller_sp(&location, pc,
@@ -630,12 +610,15 @@ void backtrace_init(BacktraceIterator *state,
 /* Handle the case where the register holds more bits than the VA. */
 static bool valid_addr_reg(bt_int_reg_t reg)
 {
-        return ((VirtualAddress)reg == reg);
+        return ((unsigned long)reg == reg);
 }
 
+/* Advances the backtracing state to the calling frame, returning
+ * true iff successful.
+ */
 bool backtrace_next(BacktraceIterator *state)
 {
-        VirtualAddress next_fp, next_pc;
+        unsigned long next_fp, next_pc;
         bt_int_reg_t next_frame[2];
 
         if (state->fp == -1) {
diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
index dbc213adf5e1..bf5e9d70266c 100644
--- a/arch/tile/kernel/compat.c
+++ b/arch/tile/kernel/compat.c
@@ -135,26 +135,15 @@ long tile_compat_sys_msgrcv(int msqid,
 
 /* Provide the compat syscall number to call mapping. */
 #undef __SYSCALL
-#define __SYSCALL(nr, call) [nr] = (compat_##call),
+#define __SYSCALL(nr, call) [nr] = (call),
 
 /* The generic versions of these don't work for Tile. */
 #define compat_sys_msgrcv tile_compat_sys_msgrcv
 #define compat_sys_msgsnd tile_compat_sys_msgsnd
 
 /* See comments in sys.c */
-#define compat_sys_fadvise64 sys32_fadvise64
 #define compat_sys_fadvise64_64 sys32_fadvise64_64
 #define compat_sys_readahead sys32_readahead
-#define compat_sys_sync_file_range compat_sys_sync_file_range2
-
-/* We leverage the "struct stat64" type for 32-bit time_t/nsec. */
-#define compat_sys_stat64 sys_stat64
-#define compat_sys_lstat64 sys_lstat64
-#define compat_sys_fstat64 sys_fstat64
-#define compat_sys_fstatat64 sys_fstatat64
-
-/* The native sys_ptrace dynamically handles compat binaries. */
-#define compat_sys_ptrace sys_ptrace
 
 /* Call the trampolines to manage pt_regs where necessary. */
 #define compat_sys_execve _compat_sys_execve
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
index dbb0dfc7bece..a7869ad62776 100644
--- a/arch/tile/kernel/compat_signal.c
+++ b/arch/tile/kernel/compat_signal.c
@@ -317,7 +317,7 @@ long compat_sys_rt_sigreturn(struct pt_regs *regs)
         return 0;
 
 badframe:
-        force_sig(SIGSEGV, current);
+        signal_fault("bad sigreturn frame", regs, frame, 0);
         return 0;
 }
 
@@ -431,6 +431,6 @@ int compat_setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         return 0;
 
 give_sigsegv:
-        force_sigsegv(sig, current);
+        signal_fault("bad setup frame", regs, frame, sig);
         return -EFAULT;
 }
diff --git a/arch/tile/kernel/futex_64.S b/arch/tile/kernel/futex_64.S
new file mode 100644
index 000000000000..f465d1eda20f
--- /dev/null
+++ b/arch/tile/kernel/futex_64.S
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * Atomically access user memory, but use MMU to avoid propagating
+ * kernel exceptions.
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+#include <asm/futex.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+
+/*
+ * Provide a set of atomic memory operations supporting <asm/futex.h>.
+ *
+ * r0: user address to manipulate
+ * r1: new value to write, or for cmpxchg, old value to compare against
+ * r2: (cmpxchg only) new value to write
+ *
+ * Return __get_user struct, r0 with value, r1 with error.
+ */
+#define FUTEX_OP(name, ...) \
+STD_ENTRY(futex_##name)                 \
+        __VA_ARGS__;                    \
+        {                               \
+         move   r1, zero;               \
+         jrp    lr                      \
+        };                              \
+        STD_ENDPROC(futex_##name);      \
+        .pushsection __ex_table,"a";    \
+        .quad 1b, get_user_fault;       \
+        .popsection
+
+        .pushsection .fixup,"ax"
+get_user_fault:
+        { movei r1, -EFAULT; jrp lr }
+        ENDPROC(get_user_fault)
+        .popsection
+
+FUTEX_OP(cmpxchg, mtspr CMPEXCH_VALUE, r1; 1: cmpexch4 r0, r0, r2)
+FUTEX_OP(set, 1: exch4 r0, r0, r1)
+FUTEX_OP(add, 1: fetchadd4 r0, r0, r1)
+FUTEX_OP(or, 1: fetchor4 r0, r0, r1)
+FUTEX_OP(andn, nor r1, r1, zero; 1: fetchand4 r0, r0, r1)
diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c
index e910530436e6..8c41891aab34 100644
--- a/arch/tile/kernel/hardwall.c
+++ b/arch/tile/kernel/hardwall.c
@@ -40,16 +40,25 @@
 struct hardwall_info {
         struct list_head list;             /* "rectangles" list */
         struct list_head task_head;        /* head of tasks in this hardwall */
+        struct cpumask cpumask;            /* cpus in the rectangle */
         int ulhc_x;                        /* upper left hand corner x coord */
         int ulhc_y;                        /* upper left hand corner y coord */
         int width;                         /* rectangle width */
         int height;                        /* rectangle height */
+        int id;                            /* integer id for this hardwall */
         int teardown_in_progress;          /* are we tearing this one down? */
 };
 
 /* Currently allocated hardwall rectangles */
 static LIST_HEAD(rectangles);
 
+/* /proc/tile/hardwall */
+static struct proc_dir_entry *hardwall_proc_dir;
+
+/* Functions to manage files in /proc/tile/hardwall. */
+static void hardwall_add_proc(struct hardwall_info *rect);
+static void hardwall_remove_proc(struct hardwall_info *rect);
+
 /*
  * Guard changes to the hardwall data structures.
  * This could be finer grained (e.g. one lock for the list of hardwall
@@ -105,6 +114,8 @@ static int setup_rectangle(struct hardwall_info *r, struct cpumask *mask)
         r->ulhc_y = cpu_y(ulhc);
         r->width = cpu_x(lrhc) - r->ulhc_x + 1;
         r->height = cpu_y(lrhc) - r->ulhc_y + 1;
+        cpumask_copy(&r->cpumask, mask);
+        r->id = ulhc;   /* The ulhc cpu id can be the hardwall id. */
 
         /* Width and height must be positive */
         if (r->width <= 0 || r->height <= 0)
@@ -268,12 +279,10 @@ void __kprobes do_hardwall_trap(struct pt_regs* regs, int fault_num)
         found_processes = 0;
         list_for_each_entry(p, &rect->task_head, thread.hardwall_list) {
                 BUG_ON(p->thread.hardwall != rect);
-                if (p->sighand) {
+                if (!(p->flags & PF_EXITING)) {
                         found_processes = 1;
                         pr_notice("hardwall: killing %d\n", p->pid);
-                        spin_lock(&p->sighand->siglock);
-                        __group_send_sig_info(info.si_signo, &info, p);
-                        spin_unlock(&p->sighand->siglock);
+                        do_send_sig_info(info.si_signo, &info, p, false);
                 }
         }
         if (!found_processes)
@@ -390,6 +399,9 @@ static struct hardwall_info *hardwall_create(
         /* Set up appropriate hardwalling on all affected cpus. */
         hardwall_setup(rect);
 
+        /* Create a /proc/tile/hardwall entry. */
+        hardwall_add_proc(rect);
+
         return rect;
 }
 
@@ -647,6 +659,9 @@ static void hardwall_destroy(struct hardwall_info *rect)
         /* Restart switch and disable firewall. */
         on_each_cpu_mask(&mask, restart_udn_switch, NULL, 1);
 
+        /* Remove the /proc/tile/hardwall entry. */
+        hardwall_remove_proc(rect);
+
         /* Now free the rectangle from the list. */
         spin_lock_irqsave(&hardwall_lock, flags);
         BUG_ON(!list_empty(&rect->task_head));
@@ -656,35 +671,57 @@ static void hardwall_destroy(struct hardwall_info *rect)
 }
 
 
-/*
- * Dump hardwall state via /proc; initialized in arch/tile/sys/proc.c.
- */
-int proc_tile_hardwall_show(struct seq_file *sf, void *v)
+static int hardwall_proc_show(struct seq_file *sf, void *v)
 {
-        struct hardwall_info *r;
+        struct hardwall_info *rect = sf->private;
+        char buf[256];
 
-        if (udn_disabled) {
-                seq_printf(sf, "%dx%d 0,0 pids:\n", smp_width, smp_height);
-                return 0;
-        }
-
-        spin_lock_irq(&hardwall_lock);
-        list_for_each_entry(r, &rectangles, list) {
-                struct task_struct *p;
-                seq_printf(sf, "%dx%d %d,%d pids:",
-                           r->width, r->height, r->ulhc_x, r->ulhc_y);
-                list_for_each_entry(p, &r->task_head, thread.hardwall_list) {
-                        unsigned int cpu = cpumask_first(&p->cpus_allowed);
-                        unsigned int x = cpu % smp_width;
-                        unsigned int y = cpu / smp_width;
-                        seq_printf(sf, " %d@%d,%d", p->pid, x, y);
-                }
-                seq_printf(sf, "\n");
-        }
-        spin_unlock_irq(&hardwall_lock);
+        int rc = cpulist_scnprintf(buf, sizeof(buf), &rect->cpumask);
+        buf[rc++] = '\n';
+        seq_write(sf, buf, rc);
         return 0;
 }
 
+static int hardwall_proc_open(struct inode *inode,
+                              struct file *file)
+{
+        return single_open(file, hardwall_proc_show, PDE(inode)->data);
+}
+
+static const struct file_operations hardwall_proc_fops = {
+        .open           = hardwall_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static void hardwall_add_proc(struct hardwall_info *rect)
+{
+        char buf[64];
+        snprintf(buf, sizeof(buf), "%d", rect->id);
+        proc_create_data(buf, 0444, hardwall_proc_dir,
+                         &hardwall_proc_fops, rect);
+}
+
+static void hardwall_remove_proc(struct hardwall_info *rect)
+{
+        char buf[64];
+        snprintf(buf, sizeof(buf), "%d", rect->id);
+        remove_proc_entry(buf, hardwall_proc_dir);
+}
+
+int proc_pid_hardwall(struct task_struct *task, char *buffer)
+{
+        struct hardwall_info *rect = task->thread.hardwall;
+        return rect ? sprintf(buffer, "%d\n", rect->id) : 0;
+}
+
+void proc_tile_hardwall_init(struct proc_dir_entry *root)
+{
+        if (!udn_disabled)
+                hardwall_proc_dir = proc_mkdir("hardwall", root);
+}
+
 
 /*
  * Character device support via ioctl/close.
@@ -718,6 +755,9 @@ static long hardwall_ioctl(struct file *file, unsigned int a, unsigned long b)
                         return -EINVAL;
                 return hardwall_deactivate(current);
 
+        case _HARDWALL_GET_ID:
+                return rect ? rect->id : -EINVAL;
+
         default:
                 return -EINVAL;
         }
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S
new file mode 100644
index 000000000000..6bc3a932fe45
--- /dev/null
+++ b/arch/tile/kernel/head_64.S
@@ -0,0 +1,269 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * TILE startup code.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/thread_info.h>
+#include <asm/processor.h>
+#include <asm/asm-offsets.h>
+#include <hv/hypervisor.h>
+#include <arch/chip.h>
+#include <arch/spr_def.h>
+
+/*
+ * This module contains the entry code for kernel images. It performs the
+ * minimal setup needed to call the generic C routines.
+ */
+
+        __HEAD
+ENTRY(_start)
+        /* Notify the hypervisor of what version of the API we want */
+        {
+          movei r1, TILE_CHIP
+          movei r2, TILE_CHIP_REV
+        }
+        {
+          moveli r0, _HV_VERSION
+          jal hv_init
+        }
+        /* Get a reasonable default ASID in r0 */
+        {
+          move r0, zero
+          jal hv_inquire_asid
+        }
+
+        /*
+         * Install the default page table.  The relocation required to
+         * statically define the table is a bit too complex, so we have
+         * to plug in the pointer from the L0 to the L1 table by hand.
+         * We only do this on the first cpu to boot, though, since the
+         * other CPUs should see a properly-constructed page table.
+         */
+        {
+          v4int_l r2, zero, r0    /* ASID for hv_install_context */
+          moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
+        }
+        {
+          shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
+        }
+        {
+          ld r1, r4               /* access_pte for hv_install_context */
+        }
+        {
+          moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
+          moveli r6, hw1_last(temp_data_pmd - PAGE_OFFSET)
+        }
+        {
+          /* After initializing swapper_pgprot, HV_PTE_GLOBAL is set. */
+          bfextu r7, r1, HV_PTE_INDEX_GLOBAL, HV_PTE_INDEX_GLOBAL
+          inv r4
+        }
+        bnez r7, .Lno_write
+        {
+          shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
+          shl16insli r6, r6, hw0(temp_data_pmd - PAGE_OFFSET)
+        }
+        {
+          /* Cut off the low bits of the PT address. */
+          shrui r6, r6, HV_LOG2_PAGE_TABLE_ALIGN
+          /* Start with our access pte. */
+          move r5, r1
+        }
+        {
+          /* Stuff the address into the page table pointer slot of the PTE. */
+          bfins r5, r6, HV_PTE_INDEX_PTFN, \
+                        HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
+        }
+        {
+          /* Store the L0 data PTE. */
+          st r0, r5
+          addli r6, r6, (temp_code_pmd - temp_data_pmd) >> \
+                        HV_LOG2_PAGE_TABLE_ALIGN
+        }
+        {
+          addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
+          bfins r5, r6, HV_PTE_INDEX_PTFN, \
+                        HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
+        }
+        /* Store the L0 code PTE. */
+        st r0, r5
+
+.Lno_write:
+        moveli lr, hw2_last(1f)
+        {
+          shl16insli lr, lr, hw1(1f)
+          moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
+        }
+        {
+          shl16insli lr, lr, hw0(1f)
+          shl16insli r0, r0, hw0(swapper_pg_dir - PAGE_OFFSET)
+        }
+        {
+          move r3, zero
+          j hv_install_context
+        }
+1:
+
+        /* Install the interrupt base. */
+        moveli r0, hw2_last(MEM_SV_START)
+        shl16insli r0, r0, hw1(MEM_SV_START)
+        shl16insli r0, r0, hw0(MEM_SV_START)
+        mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0
+
+        /*
+         * Get our processor number and save it away in SAVE_K_0.
+         * Extract stuff from the topology structure: r4 = y, r6 = x,
+         * r5 = width.  FIXME: consider whether we want to just make these
+         * 64-bit values (and if so fix smp_topology write below, too).
+         */
+        jal hv_inquire_topology
+        {
+          v4int_l r5, zero, r1    /* r5 = width */
+          shrui r4, r0, 32        /* r4 = y */
+        }
+        {
+          v4int_l r6, zero, r0    /* r6 = x */
+          mul_lu_lu r4, r4, r5
+        }
+        {
+          add r4, r4, r6          /* r4 == cpu == y*width + x */
+        }
+
+#ifdef CONFIG_SMP
+        /*
+         * Load up our per-cpu offset.  When the first (master) tile
+         * boots, this value is still zero, so we will load boot_pc
+         * with start_kernel, and boot_sp with init_stack + THREAD_SIZE.
+         * The master tile initializes the per-cpu offset array, so that
+         * when subsequent (secondary) tiles boot, they will instead load
+         * from their per-cpu versions of boot_sp and boot_pc.
+         */
+        moveli r5, hw2_last(__per_cpu_offset)
+        shl16insli r5, r5, hw1(__per_cpu_offset)
+        shl16insli r5, r5, hw0(__per_cpu_offset)
+        shl3add r5, r4, r5
+        ld r5, r5
+        bnez r5, 1f
+
+        /*
+         * Save the width and height to the smp_topology variable
+         * for later use.
+         */
+        moveli r0, hw2_last(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
+        shl16insli r0, r0, hw1(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
+        shl16insli r0, r0, hw0(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
+        st r0, r1
+1:
+#else
+        move r5, zero
+#endif
+
+        /* Load and go with the correct pc and sp. */
+        {
+          moveli r1, hw2_last(boot_sp)
+          moveli r0, hw2_last(boot_pc)
+        }
+        {
+          shl16insli r1, r1, hw1(boot_sp)
+          shl16insli r0, r0, hw1(boot_pc)
+        }
+        {
+          shl16insli r1, r1, hw0(boot_sp)
+          shl16insli r0, r0, hw0(boot_pc)
+        }
+        {
+          add r1, r1, r5
+          add r0, r0, r5
+        }
+        ld r0, r0
+        ld sp, r1
+        or r4, sp, r4
+        mtspr SPR_SYSTEM_SAVE_K_0, r4  /* save ksp0 + cpu */
+        addi sp, sp, -STACK_TOP_DELTA
+        {
+          move lr, zero   /* stop backtraces in the called function */
+          jr r0
+        }
+        ENDPROC(_start)
+
+__PAGE_ALIGNED_BSS
+        .align PAGE_SIZE
+ENTRY(empty_zero_page)
+        .fill PAGE_SIZE,1,0
+        END(empty_zero_page)
+
+        .macro PTE cpa, bits1
+        .quad HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED |\
+              HV_PTE_GLOBAL | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) |\
+              (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN)
+        .endm
+
+__PAGE_ALIGNED_DATA
+        .align PAGE_SIZE
+ENTRY(swapper_pg_dir)
+        .org swapper_pg_dir + HV_L0_INDEX(PAGE_OFFSET) * HV_PTE_SIZE
+.Lsv_data_pmd:
+        .quad 0  /* PTE temp_data_pmd - PAGE_OFFSET, 0 */
+        .org swapper_pg_dir + HV_L0_INDEX(MEM_SV_START) * HV_PTE_SIZE
+.Lsv_code_pmd:
+        .quad 0  /* PTE temp_code_pmd - PAGE_OFFSET, 0 */
+        .org swapper_pg_dir + HV_L0_SIZE
+        END(swapper_pg_dir)
+
+        .align HV_PAGE_TABLE_ALIGN
+ENTRY(temp_data_pmd)
+        /*
+         * We fill the PAGE_OFFSET pmd with huge pages with
+         * VA = PA + PAGE_OFFSET.  We remap things with more precise access
+         * permissions later.
+         */
+        .set addr, 0
+        .rept HV_L1_ENTRIES
+        PTE addr, HV_PTE_READABLE | HV_PTE_WRITABLE
+        .set addr, addr + HV_PAGE_SIZE_LARGE
+        .endr
+        .org temp_data_pmd + HV_L1_SIZE
+        END(temp_data_pmd)
+
+        .align HV_PAGE_TABLE_ALIGN
+ENTRY(temp_code_pmd)
+        /*
+         * We fill the MEM_SV_START pmd with huge pages with
+         * VA = PA + PAGE_OFFSET.  We remap things with more precise access
+         * permissions later.
+         */
+        .set addr, 0
+        .rept HV_L1_ENTRIES
+        PTE addr, HV_PTE_READABLE | HV_PTE_EXECUTABLE
+        .set addr, addr + HV_PAGE_SIZE_LARGE
+        .endr
+        .org temp_code_pmd + HV_L1_SIZE
+        END(temp_code_pmd)
+
+        /*
+         * Isolate swapper_pgprot to its own cache line, since each cpu
+         * starting up will read it using VA-is-PA and local homing.
+         * This would otherwise likely conflict with other data on the cache
+         * line, once we have set its permanent home in the page tables.
+         */
+        __INITDATA
+        .align CHIP_L2_LINE_SIZE()
+ENTRY(swapper_pgprot)
+        .quad HV_PTE_PRESENT | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
+        .align CHIP_L2_LINE_SIZE()
+        END(swapper_pgprot)
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index fffcfa6b3a62..72ade79b621b 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -851,14 +851,27 @@ STD_ENTRY(interrupt_return)
         /* Check to see if there is any work to do before returning to user. */
         {
          addi   r29, r32, THREAD_INFO_FLAGS_OFFSET
-         moveli r28, lo16(_TIF_ALLWORK_MASK)
+         moveli r1, lo16(_TIF_ALLWORK_MASK)
         }
         {
          lw     r29, r29
-         auli   r28, r28, ha16(_TIF_ALLWORK_MASK)
+         auli   r1, r1, ha16(_TIF_ALLWORK_MASK)
         }
-        and     r28, r29, r28
-        bnz     r28, .Lwork_pending
+        and     r1, r29, r1
+        bzt     r1, .Lrestore_all
+
+        /*
+         * Make sure we have all the registers saved for signal
+         * handling or single-step.  Call out to C code to figure out
+         * exactly what we need to do for each flag bit, then if
+         * necessary, reload the flags and recheck.
+         */
+        push_extra_callee_saves r0
+        {
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+         jal    do_work_pending
+        }
+        bnz     r0, .Lresume_userspace
 
         /*
          * In the NMI case we
@@ -1099,99 +1112,6 @@ STD_ENTRY(interrupt_return)
         pop_reg r50
         pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
         j .Lcontinue_restore_regs
-
-.Lwork_pending:
-        /* Mask the reschedule flag */
-        andi    r28, r29, _TIF_NEED_RESCHED
-
-        {
-         /*
-          * If the NEED_RESCHED flag is called, we call schedule(), which
-          * may drop this context right here and go do something else.
-          * On return, jump back to .Lresume_userspace and recheck.
-          */
-         bz     r28, .Lasync_tlb
-
-         /* Mask the async-tlb flag */
-         andi   r28, r29, _TIF_ASYNC_TLB
-        }
-
-        jal     schedule
-        FEEDBACK_REENTER(interrupt_return)
-
-        /* Reload the flags and check again */
-        j       .Lresume_userspace
-
-.Lasync_tlb:
-        {
-         bz     r28, .Lneed_sigpending
-
-         /* Mask the sigpending flag */
-         andi   r28, r29, _TIF_SIGPENDING
-        }
-
-        PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
-        jal     do_async_page_fault
-        FEEDBACK_REENTER(interrupt_return)
-
-        /*
-         * Go restart the "resume userspace" process.  We may have
-         * fired a signal, and we need to disable interrupts again.
-         */
-        j       .Lresume_userspace
-
-.Lneed_sigpending:
-        /*
-         * At this point we are either doing signal handling or single-step,
-         * so either way make sure we have all the registers saved.
-         */
-        push_extra_callee_saves r0
-
-        {
-         /* If no signal pending, skip to singlestep check */
-         bz     r28, .Lneed_singlestep
-
-         /* Mask the singlestep flag */
-         andi   r28, r29, _TIF_SINGLESTEP
-        }
-
-        jal     do_signal
-        FEEDBACK_REENTER(interrupt_return)
-
-        /* Reload the flags and check again */
-        j       .Lresume_userspace
-
-.Lneed_singlestep:
-        {
-         /* Get a pointer to the EX1 field */
-         PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
-
-         /* If we get here, our bit must be set. */
-         bz     r28, .Lwork_confusion
-        }
-        /* If we are in priv mode, don't single step */
-        lw      r28, r29
-        andi    r28, r28, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
-        bnz     r28, .Lrestore_all
-
-        /* Allow interrupts within the single step code */
-        TRACE_IRQS_ON  /* Note: clobbers registers r0-r29 */
-        IRQ_ENABLE(r20, r21)
-
-        /* try to single-step the current instruction */
-        PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
-        jal     single_step_once
-        FEEDBACK_REENTER(interrupt_return)
-
-        /* Re-disable interrupts.  TRACE_IRQS_OFF in .Lrestore_all. */
-        IRQ_DISABLE(r20,r21)
-
-        j       .Lrestore_all
-
-.Lwork_confusion:
-        move    r0, r28
-        panic   "thread_info allwork flags unhandled on userspace resume: %#x"
-
         STD_ENDPROC(interrupt_return)
 
         /*
@@ -1550,7 +1470,10 @@ STD_ENTRY(_sys_clone)
  * We place it in the __HEAD section to ensure it is relatively
  * near to the intvec_SWINT_1 code (reachable by a conditional branch).
  *
- * Must match register usage in do_page_fault().
+ * Our use of ATOMIC_LOCK_REG here must match do_page_fault_ics().
+ *
+ * As we do in lib/atomic_asm_32.S, we bypass a store if the value we
+ * would store is the same as the value we just loaded.
  */
         __HEAD
         .align 64
@@ -1611,17 +1534,7 @@ ENTRY(sys_cmpxchg)
         {
          shri   r20, r25, 32 - ATOMIC_HASH_L1_SHIFT
          slt_u  r23, r0, r23
-
-         /*
-          * Ensure that the TLB is loaded before we take out the lock.
-          * On TILEPro, this will start fetching the value all the way
-          * into our L1 as well (and if it gets modified before we
-          * grab the lock, it will be invalidated from our cache
-          * before we reload it).  On tile64, we'll start fetching it
-          * into our L1 if we're the home, and if we're not, we'll
-          * still at least start fetching it into the home's L2.
-          */
-         lw     r26, r0
+         lw     r26, r0  /* see comment in the "#else" for the "lw r26". */
         }
         {
          s2a    r21, r20, r21
@@ -1637,18 +1550,9 @@ ENTRY(sys_cmpxchg)
          bbs    r23, .Lcmpxchg64
          andi   r23, r0, 7       /* Precompute alignment for cmpxchg64. */
         }
-
         {
-         /*
-          * We very carefully align the code that actually runs with
-          * the lock held (nine bundles) so that we know it is all in
-          * the icache when we start.  This instruction (the jump) is
-          * at the start of the first cache line, address zero mod 64;
-          * we jump to somewhere in the second cache line to issue the
-          * tns, then jump back to finish up.
-          */
          s2a    ATOMIC_LOCK_REG_NAME, r25, r21
-         j      .Lcmpxchg32_tns
+         j      .Lcmpxchg32_tns   /* see comment in the #else for the jump. */
         }
 
 #else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
@@ -1713,24 +1617,25 @@ ENTRY(sys_cmpxchg)
         {
          /*
           * We very carefully align the code that actually runs with
-          * the lock held (nine bundles) so that we know it is all in
+          * the lock held (twelve bundles) so that we know it is all in
           * the icache when we start.  This instruction (the jump) is
           * at the start of the first cache line, address zero mod 64;
-          * we jump to somewhere in the second cache line to issue the
-          * tns, then jump back to finish up.
+          * we jump to the very end of the second cache line to get that
+          * line loaded in the icache, then fall through to issue the tns
+          * in the third cache line, at which point it's all cached.
+          * Note that is for performance, not correctness.
           */
          j      .Lcmpxchg32_tns
         }
 
 #endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
 
-        ENTRY(__sys_cmpxchg_grab_lock)
+/* Symbol for do_page_fault_ics() to use to compare against the PC. */
+.global __sys_cmpxchg_grab_lock
+__sys_cmpxchg_grab_lock:
 
         /*
          * Perform the actual cmpxchg or atomic_update.
-         * Note that the system <arch/atomic.h> header relies on
-         * atomic_update() to always perform an "mf", so don't make
-         * it optional or conditional without modifying that code.
          */
 .Ldo_cmpxchg32:
         {
@@ -1748,10 +1653,13 @@ ENTRY(sys_cmpxchg)
         }
         {
          mvnz   r24, r23, r25    /* Use atomic_update value if appropriate. */
-         bbns   r22, .Lcmpxchg32_mismatch
+         bbns   r22, .Lcmpxchg32_nostore
         }
+        seq     r22, r24, r21    /* Are we storing the value we loaded? */
+        bbs     r22, .Lcmpxchg32_nostore
         sw      r0, r24
 
+        /* The following instruction is the start of the second cache line. */
         /* Do slow mtspr here so the following "mf" waits less. */
         {
          move   sp, r27
@@ -1759,7 +1667,6 @@ ENTRY(sys_cmpxchg)
         }
         mf
 
-        /* The following instruction is the start of the second cache line. */
         {
          move   r0, r21
          sw     ATOMIC_LOCK_REG_NAME, zero
@@ -1767,7 +1674,7 @@ ENTRY(sys_cmpxchg)
         iret
 
         /* Duplicated code here in the case where we don't overlap "mf" */
-.Lcmpxchg32_mismatch:
+.Lcmpxchg32_nostore:
         {
          move   r0, r21
          sw     ATOMIC_LOCK_REG_NAME, zero
@@ -1783,8 +1690,6 @@ ENTRY(sys_cmpxchg)
          * and for 64-bit cmpxchg.  We provide it as a macro and put
          * it into both versions.  We can't share the code literally
          * since it depends on having the right branch-back address.
-         * Note that the first few instructions should share the cache
-         * line with the second half of the actual locked code.
          */
         .macro  cmpxchg_lock, bitwidth
 
@@ -1810,7 +1715,7 @@ ENTRY(sys_cmpxchg)
         }
         /*
          * The preceding instruction is the last thing that must be
-         * on the second cache line.
+         * hot in the icache before we do the "tns" above.
          */
 
 #ifdef CONFIG_SMP
@@ -1841,6 +1746,12 @@ ENTRY(sys_cmpxchg)
         .endm
 
 .Lcmpxchg32_tns:
+        /*
+         * This is the last instruction on the second cache line.
+         * The nop here loads the second line, then we fall through
+         * to the tns to load the third line before we take the lock.
+         */
+        nop
         cmpxchg_lock 32
 
         /*
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
new file mode 100644
index 000000000000..79c93e10ba27
--- /dev/null
+++ b/arch/tile/kernel/intvec_64.S
@@ -0,0 +1,1231 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * Linux interrupt vectors.
+ */
+
+#include <linux/linkage.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <asm/ptrace.h>
+#include <asm/thread_info.h>
+#include <asm/irqflags.h>
+#include <asm/asm-offsets.h>
+#include <asm/types.h>
+#include <hv/hypervisor.h>
+#include <arch/abi.h>
+#include <arch/interrupts.h>
+#include <arch/spr_def.h>
+
+#ifdef CONFIG_PREEMPT
+# error "No support for kernel preemption currently"
+#endif
+
+#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
+
+#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
+
+
+        .macro  push_reg reg, ptr=sp, delta=-8
+        {
+         st     \ptr, \reg
+         addli  \ptr, \ptr, \delta
+        }
+        .endm
+
+        .macro  pop_reg reg, ptr=sp, delta=8
+        {
+         ld     \reg, \ptr
+         addli  \ptr, \ptr, \delta
+        }
+        .endm
+
+        .macro  pop_reg_zero reg, zreg, ptr=sp, delta=8
+        {
+         move   \zreg, zero
+         ld     \reg, \ptr
+         addi   \ptr, \ptr, \delta
+        }
+        .endm
+
+        .macro  push_extra_callee_saves reg
+        PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
+        push_reg r51, \reg
+        push_reg r50, \reg
+        push_reg r49, \reg
+        push_reg r48, \reg
+        push_reg r47, \reg
+        push_reg r46, \reg
+        push_reg r45, \reg
+        push_reg r44, \reg
+        push_reg r43, \reg
+        push_reg r42, \reg
+        push_reg r41, \reg
+        push_reg r40, \reg
+        push_reg r39, \reg
+        push_reg r38, \reg
+        push_reg r37, \reg
+        push_reg r36, \reg
+        push_reg r35, \reg
+        push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
+        .endm
+
+        .macro  panic str
+        .pushsection .rodata, "a"
+1:
+        .asciz  "\str"
+        .popsection
+        {
+         moveli r0, hw2_last(1b)
+        }
+        {
+         shl16insli r0, r0, hw1(1b)
+        }
+        {
+         shl16insli r0, r0, hw0(1b)
+         jal    panic
+        }
+        .endm
+
+
+#ifdef __COLLECT_LINKER_FEEDBACK__
+        .pushsection .text.intvec_feedback,"ax"
+intvec_feedback:
+        .popsection
+#endif
+
+        /*
+         * Default interrupt handler.
+         *
+         * vecnum is where we'll put this code.
+         * c_routine is the C routine we'll call.
+         *
+         * The C routine is passed two arguments:
+         * - A pointer to the pt_regs state.
+         * - The interrupt vector number.
+         *
+         * The "processing" argument specifies the code for processing
+         * the interrupt. Defaults to "handle_interrupt".
+         */
+        .macro  int_hand vecnum, vecname, c_routine, processing=handle_interrupt
+        .org    (\vecnum << 8)
+intvec_\vecname:
+        /* Temporarily save a register so we have somewhere to work. */
+
+        mtspr   SPR_SYSTEM_SAVE_K_1, r0
+        mfspr   r0, SPR_EX_CONTEXT_K_1
+
+        andi    r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+
+        .ifc    \vecnum, INT_DOUBLE_FAULT
+        /*
+         * For double-faults from user-space, fall through to the normal
+         * register save and stack setup path.  Otherwise, it's the
+         * hypervisor giving us one last chance to dump diagnostics, and we
+         * branch to the kernel_double_fault routine to do so.
+         */
+        beqz    r0, 1f
+        j       _kernel_double_fault
+1:
+        .else
+        /*
+         * If we're coming from user-space, then set sp to the top of
+         * the kernel stack.  Otherwise, assume sp is already valid.
+         */
+        {
+         bnez   r0, 0f
+         move   r0, sp
+        }
+        .endif
+
+        .ifc    \c_routine, do_page_fault
+        /*
+         * The page_fault handler may be downcalled directly by the
+         * hypervisor even when Linux is running and has ICS set.
+         *
+         * In this case the contents of EX_CONTEXT_K_1 reflect the
+         * previous fault and can't be relied on to choose whether or
+         * not to reinitialize the stack pointer.  So we add a test
+         * to see whether SYSTEM_SAVE_K_2 has the high bit set,
+         * and if so we don't reinitialize sp, since we must be coming
+         * from Linux.  (In fact the precise case is !(val & ~1),
+         * but any Linux PC has to have the high bit set.)
+         *
+         * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
+         * any path that turns into a downcall to one of our TLB handlers.
+         *
+         * FIXME: if we end up never using this path, perhaps we should
+         * prevent the hypervisor from generating downcalls in this case.
+         * The advantage of getting a downcall is we can panic in Linux.
+         */
+        mfspr   r0, SPR_SYSTEM_SAVE_K_2
+        {
+         bltz   r0, 0f    /* high bit in S_S_1_2 is for a PC to use */
+         move   r0, sp
+        }
+        .endif
+
+
+        /*
+         * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
+         * the current stack top in the higher bits.  So we recover
+         * our stack top by just masking off the low bits, then
+         * point sp at the top aligned address on the actual stack page.
+         */
+        mfspr   r0, SPR_SYSTEM_SAVE_K_0
+        mm      r0, zero, LOG2_THREAD_SIZE, 63
+
+0:
+        /*
+         * Align the stack mod 64 so we can properly predict what
+         * cache lines we need to write-hint to reduce memory fetch
+         * latency as we enter the kernel.  The layout of memory is
+         * as follows, with cache line 0 at the lowest VA, and cache
+         * line 8 just below the r0 value this "andi" computes.
+         * Note that we never write to cache line 8, and we skip
+         * cache lines 1-3 for syscalls.
+         *
+         *    cache line 8: ptregs padding (two words)
+         *    cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
+         *    cache line 6: r46...r53 (tp)
+         *    cache line 5: r38...r45
+         *    cache line 4: r30...r37
+         *    cache line 3: r22...r29
+         *    cache line 2: r14...r21
+         *    cache line 1: r6...r13
+         *    cache line 0: 2 x frame, r0..r5
+         */
+        andi    r0, r0, -64
+
+        /*
+         * Push the first four registers on the stack, so that we can set
+         * them to vector-unique values before we jump to the common code.
+         *
+         * Registers are pushed on the stack as a struct pt_regs,
+         * with the sp initially just above the struct, and when we're
+         * done, sp points to the base of the struct, minus
+         * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
+         *
+         * This routine saves just the first four registers, plus the
+         * stack context so we can do proper backtracing right away,
+         * and defers to handle_interrupt to save the rest.
+         * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.
+         */
+        addli   r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
+        wh64    r0   /* cache line 7 */
+        {
+         st     r0, lr
+         addli  r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
+        }
+        {
+         st     r0, sp
+         addli  sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
+        }
+        wh64    sp   /* cache line 6 */
+        {
+         st     sp, r52
+         addli  sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
+        }
+        wh64    sp   /* cache line 0 */
+        {
+         st     sp, r1
+         addli  sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
+        }
+        {
+         st     sp, r2
+         addli  sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
+        }
+        {
+         st     sp, r3
+         addli  sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
+        }
+        mfspr   r0, SPR_EX_CONTEXT_K_0
+        .ifc \processing,handle_syscall
+        /*
+         * Bump the saved PC by one bundle so that when we return, we won't
+         * execute the same swint instruction again.  We need to do this while
+         * we're in the critical section.
+         */
+        addi    r0, r0, 8
+        .endif
+        {
+         st     sp, r0
+         addli  sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
+        }
+        mfspr   r0, SPR_EX_CONTEXT_K_1
+        {
+         st     sp, r0
+         addi   sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
+        /*
+         * Use r0 for syscalls so it's a temporary; use r1 for interrupts
+         * so that it gets passed through unchanged to the handler routine.
+         * Note that the .if conditional confusingly spans bundles.
+         */
+         .ifc \processing,handle_syscall
+         movei  r0, \vecnum
+        }
+        {
+         st     sp, r0
+         .else
+         movei  r1, \vecnum
+        }
+        {
+         st     sp, r1
+         .endif
+         addli  sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
+        }
+        mfspr   r0, SPR_SYSTEM_SAVE_K_1    /* Original r0 */
+        {
+         st     sp, r0
+         addi   sp, sp, -PTREGS_OFFSET_REG(0) - 8
+        }
+        {
+         st     sp, zero        /* write zero into "Next SP" frame pointer */
+         addi   sp, sp, -8      /* leave SP pointing at bottom of frame */
+        }
+        .ifc \processing,handle_syscall
+        j       handle_syscall
+        .else
+        /* Capture per-interrupt SPR context to registers. */
+        .ifc \c_routine, do_page_fault
+        mfspr   r2, SPR_SYSTEM_SAVE_K_3   /* address of page fault */
+        mfspr   r3, SPR_SYSTEM_SAVE_K_2   /* info about page fault */
+        .else
+        .ifc \vecnum, INT_ILL_TRANS
+        mfspr   r2, ILL_TRANS_REASON
+        .else
+        .ifc \vecnum, INT_DOUBLE_FAULT
+        mfspr   r2, SPR_SYSTEM_SAVE_K_2   /* double fault info from HV */
+        .else
+        .ifc \c_routine, do_trap
+        mfspr   r2, GPV_REASON
+        .else
+        .ifc \c_routine, op_handle_perf_interrupt
+        mfspr   r2, PERF_COUNT_STS
+#if CHIP_HAS_AUX_PERF_COUNTERS()
+        .else
+        .ifc \c_routine, op_handle_aux_perf_interrupt
+        mfspr   r2, AUX_PERF_COUNT_STS
+        .endif
+#endif
+        .endif
+        .endif
+        .endif
+        .endif
+        .endif
+        /* Put function pointer in r0 */
+        moveli  r0, hw2_last(\c_routine)
+        shl16insli r0, r0, hw1(\c_routine)
+        {
+         shl16insli r0, r0, hw0(\c_routine)
+         j       \processing
+        }
+        .endif
+        ENDPROC(intvec_\vecname)
+
+#ifdef __COLLECT_LINKER_FEEDBACK__
+        .pushsection .text.intvec_feedback,"ax"
+        .org    (\vecnum << 5)
+        FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
+        jrp     lr
+        .popsection
+#endif
+
+        .endm
+
+
+        /*
+         * Save the rest of the registers that we didn't save in the actual
+         * vector itself.  We can't use r0-r10 inclusive here.
+         */
+        .macro  finish_interrupt_save, function
+
+        /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
+        PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
+        {
+         .ifc \function,handle_syscall
+         st     r52, r0
+         .else
+         st     r52, zero
+         .endif
+         PTREGS_PTR(r52, PTREGS_OFFSET_TP)
+        }
+        st      r52, tp
+        {
+         mfspr  tp, CMPEXCH_VALUE
+         PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
+        }
+
+        /*
+         * For ordinary syscalls, we save neither caller- nor callee-
+         * save registers, since the syscall invoker doesn't expect the
+         * caller-saves to be saved, and the called kernel functions will
+         * take care of saving the callee-saves for us.
+         *
+         * For interrupts we save just the caller-save registers.  Saving
+         * them is required (since the "caller" can't save them).  Again,
+         * the called kernel functions will restore the callee-save
+         * registers for us appropriately.
+         *
+         * On return, we normally restore nothing special for syscalls,
+         * and just the caller-save registers for interrupts.
+         *
+         * However, there are some important caveats to all this:
+         *
+         * - We always save a few callee-save registers to give us
+         *   some scratchpad registers to carry across function calls.
+         *
+         * - fork/vfork/etc require us to save all the callee-save
+         *   registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
+         *
+         * - We always save r0..r5 and r10 for syscalls, since we need
+         *   to reload them a bit later for the actual kernel call, and
+         *   since we might need them for -ERESTARTNOINTR, etc.
+         *
+         * - Before invoking a signal handler, we save the unsaved
+         *   callee-save registers so they are visible to the
+         *   signal handler or any ptracer.
+         *
+         * - If the unsaved callee-save registers are modified, we set
+         *   a bit in pt_regs so we know to reload them from pt_regs
+         *   and not just rely on the kernel function unwinding.
+         *   (Done for ptrace register writes and SA_SIGINFO handler.)
+         */
+        {
+         st     r52, tp
+         PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
+        }
+        wh64    r52    /* cache line 4 */
+        push_reg r33, r52
+        push_reg r32, r52
+        push_reg r31, r52
+        .ifc \function,handle_syscall
+        push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
+        push_reg TREG_SYSCALL_NR_NAME, r52, \
+          PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
+        .else
+
+        push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
+        wh64    r52   /* cache line 3 */
+        push_reg r29, r52
+        push_reg r28, r52
+        push_reg r27, r52
+        push_reg r26, r52
+        push_reg r25, r52
+        push_reg r24, r52
+        push_reg r23, r52
+        push_reg r22, r52
+        wh64    r52   /* cache line 2 */
+        push_reg r21, r52
+        push_reg r20, r52
+        push_reg r19, r52
+        push_reg r18, r52
+        push_reg r17, r52
+        push_reg r16, r52
+        push_reg r15, r52
+        push_reg r14, r52
+        wh64    r52   /* cache line 1 */
+        push_reg r13, r52
+        push_reg r12, r52
+        push_reg r11, r52
+        push_reg r10, r52
+        push_reg r9, r52
+        push_reg r8, r52
+        push_reg r7, r52
+        push_reg r6, r52
+
+        .endif
+
+        push_reg r5, r52
+        st      r52, r4
+
+        /* Load tp with our per-cpu offset. */
+#ifdef CONFIG_SMP
+        {
+         mfspr  r20, SPR_SYSTEM_SAVE_K_0
+         moveli r21, hw2_last(__per_cpu_offset)
+        }
+        {
+         shl16insli r21, r21, hw1(__per_cpu_offset)
+         bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
+        }
+        shl16insli r21, r21, hw0(__per_cpu_offset)
+        shl3add r20, r20, r21
+        ld      tp, r20
+#else
+        move    tp, zero
+#endif
+
+        /*
+         * If we will be returning to the kernel, we will need to
+         * reset the interrupt masks to the state they had before.
+         * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
+         */
+        mfspr   r32, SPR_EX_CONTEXT_K_1
+        {
+         andi   r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+         PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
+        }
+        beqzt   r32, 1f       /* zero if from user space */
+        IRQS_DISABLED(r32)    /* zero if irqs enabled */
+#if PT_FLAGS_DISABLE_IRQ != 1
+# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
+#endif
+1:
+        .ifnc \function,handle_syscall
+        /* Record the fact that we saved the caller-save registers above. */
+        ori     r32, r32, PT_FLAGS_CALLER_SAVES
+        .endif
+        st      r21, r32
+
+#ifdef __COLLECT_LINKER_FEEDBACK__
+        /*
+         * Notify the feedback routines that we were in the
+         * appropriate fixed interrupt vector area.  Note that we
+         * still have ICS set at this point, so we can't invoke any
+         * atomic operations or we will panic.  The feedback
+         * routines internally preserve r0..r10 and r30 up.
+         */
+        .ifnc \function,handle_syscall
+        shli    r20, r1, 5
+        .else
+        moveli  r20, INT_SWINT_1 << 5
+        .endif
+        moveli  r21, hw2_last(intvec_feedback)
+        shl16insli r21, r21, hw1(intvec_feedback)
+        shl16insli r21, r21, hw0(intvec_feedback)
+        add     r20, r20, r21
+        jalr    r20
+
+        /* And now notify the feedback routines that we are here. */
+        FEEDBACK_ENTER(\function)
+#endif
+
+        /*
+         * we've captured enough state to the stack (including in
+         * particular our EX_CONTEXT state) that we can now release
+         * the interrupt critical section and replace it with our
+         * standard "interrupts disabled" mask value.  This allows
+         * synchronous interrupts (and profile interrupts) to punch
+         * through from this point onwards.
+         */
+        .ifc \function,handle_nmi
+        IRQ_DISABLE_ALL(r20)
+        .else
+        IRQ_DISABLE(r20, r21)
+        .endif
+        mtspr   INTERRUPT_CRITICAL_SECTION, zero
+
+        /*
+         * Prepare the first 256 stack bytes to be rapidly accessible
+         * without having to fetch the background data.
+         */
+        addi    r52, sp, -64
+        {
+         wh64   r52
+         addi   r52, r52, -64
+        }
+        {
+         wh64   r52
+         addi   r52, r52, -64
+        }
+        {
+         wh64   r52
+         addi   r52, r52, -64
+        }
+        wh64    r52
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+        .ifnc \function,handle_nmi
+        /*
+         * We finally have enough state set up to notify the irq
+         * tracing code that irqs were disabled on entry to the handler.
+         * The TRACE_IRQS_OFF call clobbers registers r0-r29.
+         * For syscalls, we already have the register state saved away
+         * on the stack, so we don't bother to do any register saves here,
+         * and later we pop the registers back off the kernel stack.
+         * For interrupt handlers, save r0-r3 in callee-saved registers.
+         */
+        .ifnc \function,handle_syscall
+        { move r30, r0; move r31, r1 }
+        { move r32, r2; move r33, r3 }
+        .endif
+        TRACE_IRQS_OFF
+        .ifnc \function,handle_syscall
+        { move r0, r30; move r1, r31 }
+        { move r2, r32; move r3, r33 }
+        .endif
+        .endif
+#endif
+
+        .endm
+
+        /*
+         * Redispatch a downcall.
+         */
+        .macro  dc_dispatch vecnum, vecname
+        .org    (\vecnum << 8)
+intvec_\vecname:
+        j       hv_downcall_dispatch
+        ENDPROC(intvec_\vecname)
+        .endm
+
+        /*
+         * Common code for most interrupts.  The C function we're eventually
+         * going to is in r0, and the faultnum is in r1; the original
+         * values for those registers are on the stack.
+         */
+        .pushsection .text.handle_interrupt,"ax"
+handle_interrupt:
+        finish_interrupt_save handle_interrupt
+
+        /* Jump to the C routine; it should enable irqs as soon as possible. */
+        {
+         jalr   r0
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+        }
+        FEEDBACK_REENTER(handle_interrupt)
+        {
+         movei  r30, 0   /* not an NMI */
+         j      interrupt_return
+        }
+        STD_ENDPROC(handle_interrupt)
+
+/*
+ * This routine takes a boolean in r30 indicating if this is an NMI.
+ * If so, we also expect a boolean in r31 indicating whether to
+ * re-enable the oprofile interrupts.
+ */
+STD_ENTRY(interrupt_return)
+        /* If we're resuming to kernel space, don't check thread flags. */
+        {
+         bnez   r30, .Lrestore_all  /* NMIs don't special-case user-space */
+         PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
+        }
+        ld      r29, r29
+        andi    r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+        {
+         beqzt  r29, .Lresume_userspace
+         PTREGS_PTR(r29, PTREGS_OFFSET_PC)
+        }
+
+        /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
+        moveli  r27, hw2_last(_cpu_idle_nap)
+        {
+         ld     r28, r29
+         shl16insli r27, r27, hw1(_cpu_idle_nap)
+        }
+        {
+         shl16insli r27, r27, hw0(_cpu_idle_nap)
+        }
+        {
+         cmpeq  r27, r27, r28
+        }
+        {
+         blbc   r27, .Lrestore_all
+         addi   r28, r28, 8
+        }
+        st      r29, r28
+        j       .Lrestore_all
+
+.Lresume_userspace:
+        FEEDBACK_REENTER(interrupt_return)
+
+        /*
+         * Disable interrupts so as to make sure we don't
+         * miss an interrupt that sets any of the thread flags (like
+         * need_resched or sigpending) between sampling and the iret.
+         * Routines like schedule() or do_signal() may re-enable
+         * interrupts before returning.
+         */
+        IRQ_DISABLE(r20, r21)
+        TRACE_IRQS_OFF  /* Note: clobbers registers r0-r29 */
+
+        /* Get base of stack in r32; note r30/31 are used as arguments here. */
+        GET_THREAD_INFO(r32)
+
+
+        /* Check to see if there is any work to do before returning to user. */
+        {
+         addi   r29, r32, THREAD_INFO_FLAGS_OFFSET
+         moveli r1, hw1_last(_TIF_ALLWORK_MASK)
+        }
+        {
+         ld     r29, r29
+         shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
+        }
+        and     r1, r29, r1
+        beqzt   r1, .Lrestore_all
+
+        /*
+         * Make sure we have all the registers saved for signal
+         * handling or single-step.  Call out to C code to figure out
+         * exactly what we need to do for each flag bit, then if
+         * necessary, reload the flags and recheck.
+         */
+        push_extra_callee_saves r0
+        {
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+         jal    do_work_pending
+        }
+        bnez    r0, .Lresume_userspace
+
+        /*
+         * In the NMI case we
+         * omit the call to single_process_check_nohz, which normally checks
+         * to see if we should start or stop the scheduler tick, because
+         * we can't call arbitrary Linux code from an NMI context.
+         * We always call the homecache TLB deferral code to re-trigger
+         * the deferral mechanism.
+         *
+         * The other chunk of responsibility this code has is to reset the
+         * interrupt masks appropriately to reset irqs and NMIs.  We have
+         * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
+         * lockdep-type stuff, but we can't set ICS until afterwards, since
+         * ICS can only be used in very tight chunks of code to avoid
+         * tripping over various assertions that it is off.
+         */
+.Lrestore_all:
+        PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
+        {
+         ld      r0, r0
+         PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
+        }
+        {
+         andi   r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
+         ld     r32, r32
+        }
+        bnez    r0, 1f
+        j       2f
+#if PT_FLAGS_DISABLE_IRQ != 1
+# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
+#endif
+1:      blbct   r32, 2f
+        IRQ_DISABLE(r20,r21)
+        TRACE_IRQS_OFF
+        movei   r0, 1
+        mtspr   INTERRUPT_CRITICAL_SECTION, r0
+        beqzt   r30, .Lrestore_regs
+        j       3f
+2:      TRACE_IRQS_ON
+        movei   r0, 1
+        mtspr   INTERRUPT_CRITICAL_SECTION, r0
+        IRQ_ENABLE(r20, r21)
+        beqzt   r30, .Lrestore_regs
+3:
+
+
+        /*
+         * We now commit to returning from this interrupt, since we will be
+         * doing things like setting EX_CONTEXT SPRs and unwinding the stack
+         * frame.  No calls should be made to any other code after this point.
+         * This code should only be entered with ICS set.
+         * r32 must still be set to ptregs.flags.
+         * We launch loads to each cache line separately first, so we can
+         * get some parallelism out of the memory subsystem.
+         * We start zeroing caller-saved registers throughout, since
+         * that will save some cycles if this turns out to be a syscall.
+         */
+.Lrestore_regs:
+        FEEDBACK_REENTER(interrupt_return)   /* called from elsewhere */
+
+        /*
+         * Rotate so we have one high bit and one low bit to test.
+         * - low bit says whether to restore all the callee-saved registers,
+         *   or just r30-r33, and r52 up.
+         * - high bit (i.e. sign bit) says whether to restore all the
+         *   caller-saved registers, or just r0.
+         */
+#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
+# error Rotate trick does not work :-)
+#endif
+        {
+         rotli  r20, r32, 62
+         PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
+        }
+
+        /*
+         * Load cache lines 0, 4, 6 and 7, in that order, then use
+         * the last loaded value, which makes it likely that the other
+         * cache lines have also loaded, at which point we should be
+         * able to safely read all the remaining words on those cache
+         * lines without waiting for the memory subsystem.
+         */
+        pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
+        pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
+        pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
+        pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
+        pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
+        {
+         mtspr  CMPEXCH_VALUE, r21
+         move   r4, zero
+        }
+        pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
+        {
+         mtspr  SPR_EX_CONTEXT_K_1, lr
+         andi   lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK  /* mask off ICS */
+        }
+        {
+         mtspr  SPR_EX_CONTEXT_K_0, r21
+         move   r5, zero
+        }
+
+        /* Restore callee-saveds that we actually use. */
+        pop_reg_zero r31, r6
+        pop_reg_zero r32, r7
+        pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
+
+        /*
+         * If we modified other callee-saveds, restore them now.
+         * This is rare, but could be via ptrace or signal handler.
+         */
+        {
+         move   r9, zero
+         blbs   r20, .Lrestore_callees
+        }
+.Lcontinue_restore_regs:
+
+        /* Check if we're returning from a syscall. */
+        {
+         move   r10, zero
+         bltzt  r20, 1f  /* no, so go restore callee-save registers */
+        }
+
+        /*
+         * Check if we're returning to userspace.
+         * Note that if we're not, we don't worry about zeroing everything.
+         */
+        {
+         addli  sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
+         bnez   lr, .Lkernel_return
+        }
+
+        /*
+         * On return from syscall, we've restored r0 from pt_regs, but we
+         * clear the remainder of the caller-saved registers.  We could
+         * restore the syscall arguments, but there's not much point,
+         * and it ensures user programs aren't trying to use the
+         * caller-saves if we clear them, as well as avoiding leaking
+         * kernel pointers into userspace.
+         */
+        pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
+        pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
+        {
+         ld     sp, sp
+         move   r13, zero
+         move   r14, zero
+        }
+        { move r15, zero; move r16, zero }
+        { move r17, zero; move r18, zero }
+        { move r19, zero; move r20, zero }
+        { move r21, zero; move r22, zero }
+        { move r23, zero; move r24, zero }
+        { move r25, zero; move r26, zero }
+
+        /* Set r1 to errno if we are returning an error, otherwise zero. */
+        {
+         moveli r29, 4096
+         sub    r1, zero, r0
+        }
+        {
+         move   r28, zero
+         cmpltu r29, r1, r29
+        }
+        {
+         mnz    r1, r29, r1
+         move   r29, zero
+        }
+        iret
+
+        /*
+         * Not a syscall, so restore caller-saved registers.
+         * First kick off loads for cache lines 1-3, which we're touching
+         * for the first time here.
+         */
+        .align 64
+1:      pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
+        pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
+        pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
+        pop_reg r1
+        pop_reg r2
+        pop_reg r3
+        pop_reg r4
+        pop_reg r5
+        pop_reg r6
+        pop_reg r7
+        pop_reg r8
+        pop_reg r9
+        pop_reg r10
+        pop_reg r11
+        pop_reg r12, sp, 16
+        /* r13 already restored above */
+        pop_reg r14
+        pop_reg r15
+        pop_reg r16
+        pop_reg r17
+        pop_reg r18
+        pop_reg r19
+        pop_reg r20, sp, 16
+        /* r21 already restored above */
+        pop_reg r22
+        pop_reg r23
+        pop_reg r24
+        pop_reg r25
+        pop_reg r26
+        pop_reg r27
+        pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
+        /* r29 already restored above */
+        bnez    lr, .Lkernel_return
+        pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
+        pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
+        ld      sp, sp
+        iret
+
+        /*
+         * We can't restore tp when in kernel mode, since a thread might
+         * have migrated from another cpu and brought a stale tp value.
+         */
+.Lkernel_return:
+        pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
+        ld      sp, sp
+        iret
+
+        /* Restore callee-saved registers from r34 to r51. */
+.Lrestore_callees:
+        addli  sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
+        pop_reg r34
+        pop_reg r35
+        pop_reg r36
+        pop_reg r37
+        pop_reg r38
+        pop_reg r39
+        pop_reg r40
+        pop_reg r41
+        pop_reg r42
+        pop_reg r43
+        pop_reg r44
+        pop_reg r45
+        pop_reg r46
+        pop_reg r47
+        pop_reg r48
+        pop_reg r49
+        pop_reg r50
+        pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
+        j .Lcontinue_restore_regs
+        STD_ENDPROC(interrupt_return)
+
+        /*
+         * "NMI" interrupts mask ALL interrupts before calling the
+         * handler, and don't check thread flags, etc., on the way
+         * back out.  In general, the only things we do here for NMIs
+         * are register save/restore and dataplane kernel-TLB management.
+         * We don't (for example) deal with start/stop of the sched tick.
+         */
+        .pushsection .text.handle_nmi,"ax"
+handle_nmi:
+        finish_interrupt_save handle_nmi
+        {
+         jalr   r0
+         PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+        }
+        FEEDBACK_REENTER(handle_nmi)
+        {
+         movei  r30, 1
+         move   r31, r0
+        }
+        j       interrupt_return
+        STD_ENDPROC(handle_nmi)
+
+        /*
+         * Parallel code for syscalls to handle_interrupt.
+         */
+        .pushsection .text.handle_syscall,"ax"
+handle_syscall:
+        finish_interrupt_save handle_syscall
+
+        /* Enable irqs. */
+        TRACE_IRQS_ON
+        IRQ_ENABLE(r20, r21)
+
+        /* Bump the counter for syscalls made on this tile. */
+        moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
+        shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
+        shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
+        add     r20, r20, tp
+        ld4s    r21, r20
+        addi    r21, r21, 1
+        st4     r20, r21
+
+        /* Trace syscalls, if requested. */
+        GET_THREAD_INFO(r31)
+        addi    r31, r31, THREAD_INFO_FLAGS_OFFSET
+        ld      r30, r31
+        andi    r30, r30, _TIF_SYSCALL_TRACE
+        {
+         addi   r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
+         beqzt  r30, .Lrestore_syscall_regs
+        }
+        jal     do_syscall_trace
+        FEEDBACK_REENTER(handle_syscall)
+
+        /*
+         * We always reload our registers from the stack at this
+         * point.  They might be valid, if we didn't build with
+         * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
+         * doing syscall tracing, but there are enough cases now that it
+         * seems simplest just to do the reload unconditionally.
+         */
+.Lrestore_syscall_regs:
+        {
+         ld     r30, r30
+         PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
+        }
+        pop_reg r0,  r11
+        pop_reg r1,  r11
+        pop_reg r2,  r11
+        pop_reg r3,  r11
+        pop_reg r4,  r11
+        pop_reg r5,  r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
+        {
+         ld     TREG_SYSCALL_NR_NAME, r11
+         moveli r21, __NR_syscalls
+        }
+
+        /* Ensure that the syscall number is within the legal range. */
+        {
+         moveli r20, hw2(sys_call_table)
+         blbs   r30, .Lcompat_syscall
+        }
+        {
+         cmpltu r21, TREG_SYSCALL_NR_NAME, r21
+         shl16insli r20, r20, hw1(sys_call_table)
+        }
+        {
+         blbc   r21, .Linvalid_syscall
+         shl16insli r20, r20, hw0(sys_call_table)
+        }
+.Lload_syscall_pointer:
+        shl3add r20, TREG_SYSCALL_NR_NAME, r20
+        ld      r20, r20
+
+        /* Jump to syscall handler. */
+        jalr    r20
+.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
+
+        /*
+         * Write our r0 onto the stack so it gets restored instead
+         * of whatever the user had there before.
+         * In compat mode, sign-extend r0 before storing it.
+         */
+        {
+         PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
+         blbct  r30, 1f
+        }
+        addxi   r0, r0, 0
+1:      st      r29, r0
+
+.Lsyscall_sigreturn_skip:
+        FEEDBACK_REENTER(handle_syscall)
+
+        /* Do syscall trace again, if requested. */
+        ld      r30, r31
+        andi    r30, r30, _TIF_SYSCALL_TRACE
+        beqzt   r30, 1f
+        jal     do_syscall_trace
+        FEEDBACK_REENTER(handle_syscall)
+1:      j       .Lresume_userspace   /* jump into middle of interrupt_return */
+
+.Lcompat_syscall:
+        /*
+         * Load the base of the compat syscall table in r20, and
+         * range-check the syscall number (duplicated from 64-bit path).
+         * Sign-extend all the user's passed arguments to make them consistent.
+         * Also save the original "r(n)" values away in "r(11+n)" in
+         * case the syscall table entry wants to validate them.
+         */
+        moveli  r20, hw2(compat_sys_call_table)
+        {
+         cmpltu r21, TREG_SYSCALL_NR_NAME, r21
+         shl16insli r20, r20, hw1(compat_sys_call_table)
+        }
+        {
+         blbc   r21, .Linvalid_syscall
+         shl16insli r20, r20, hw0(compat_sys_call_table)
+        }
+        { move r11, r0; addxi r0, r0, 0 }
+        { move r12, r1; addxi r1, r1, 0 }
+        { move r13, r2; addxi r2, r2, 0 }
+        { move r14, r3; addxi r3, r3, 0 }
+        { move r15, r4; addxi r4, r4, 0 }
+        { move r16, r5; addxi r5, r5, 0 }
+        j .Lload_syscall_pointer
+
+.Linvalid_syscall:
+        /* Report an invalid syscall back to the user program */
+        {
+         PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
+         movei  r28, -ENOSYS
+        }
+        st      r29, r28
+        j       .Lresume_userspace   /* jump into middle of interrupt_return */
+        STD_ENDPROC(handle_syscall)
+
+        /* Return the address for oprofile to suppress in backtraces. */
+STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
+        lnk     r0
+        {
+         addli  r0, r0, .Lhandle_syscall_link - .
+         jrp    lr
+        }
+        STD_ENDPROC(handle_syscall_link_address)
+
+STD_ENTRY(ret_from_fork)
+        jal     sim_notify_fork
+        jal     schedule_tail
+        FEEDBACK_REENTER(ret_from_fork)
+        j       .Lresume_userspace
+        STD_ENDPROC(ret_from_fork)
+
+/* Various stub interrupt handlers and syscall handlers */
+
+STD_ENTRY_LOCAL(_kernel_double_fault)
+        mfspr   r1, SPR_EX_CONTEXT_K_0
+        move    r2, lr
+        move    r3, sp
+        move    r4, r52
+        addi    sp, sp, -C_ABI_SAVE_AREA_SIZE
+        j       kernel_double_fault
+        STD_ENDPROC(_kernel_double_fault)
+
+STD_ENTRY_LOCAL(bad_intr)
+        mfspr   r2, SPR_EX_CONTEXT_K_0
+        panic   "Unhandled interrupt %#x: PC %#lx"
+        STD_ENDPROC(bad_intr)
+
+/* Put address of pt_regs in reg and jump. */
+#define PTREGS_SYSCALL(x, reg)                          \
+        STD_ENTRY(_##x);                                \
+        {                                               \
+         PTREGS_PTR(reg, PTREGS_OFFSET_BASE);           \
+         j      x                                       \
+        };                                              \
+        STD_ENDPROC(_##x)
+
+/*
+ * Special-case sigreturn to not write r0 to the stack on return.
+ * This is technically more efficient, but it also avoids difficulties
+ * in the 64-bit OS when handling 32-bit compat code, since we must not
+ * sign-extend r0 for the sigreturn return-value case.
+ */
+#define PTREGS_SYSCALL_SIGRETURN(x, reg)                \
+        STD_ENTRY(_##x);                                \
+        addli   lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
+        {                                               \
+         PTREGS_PTR(reg, PTREGS_OFFSET_BASE);           \
+         j      x                                       \
+        };                                              \
+        STD_ENDPROC(_##x)
+
+PTREGS_SYSCALL(sys_execve, r3)
+PTREGS_SYSCALL(sys_sigaltstack, r2)
+PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
+#ifdef CONFIG_COMPAT
+PTREGS_SYSCALL(compat_sys_execve, r3)
+PTREGS_SYSCALL(compat_sys_sigaltstack, r2)
+PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
+#endif
+
+/* Save additional callee-saves to pt_regs, put address in r4 and jump. */
+STD_ENTRY(_sys_clone)
+        push_extra_callee_saves r4
+        j       sys_clone
+        STD_ENDPROC(_sys_clone)
+
+/* The single-step support may need to read all the registers. */
+int_unalign:
+        push_extra_callee_saves r0
+        j       do_trap
+
+/* Include .intrpt1 array of interrupt vectors */
+        .section ".intrpt1", "ax"
+
+#define op_handle_perf_interrupt bad_intr
+#define op_handle_aux_perf_interrupt bad_intr
+
+#ifndef CONFIG_HARDWALL
+#define do_hardwall_trap bad_intr
+#endif
+
+        int_hand     INT_MEM_ERROR, MEM_ERROR, bad_intr
+        int_hand     INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
+#if CONFIG_KERNEL_PL == 2
+        int_hand     INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
+        int_hand     INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
+#else
+        int_hand     INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
+        int_hand     INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
+#endif
+        int_hand     INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
+        int_hand     INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
+        int_hand     INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
+        int_hand     INT_ITLB_MISS, ITLB_MISS, do_page_fault
+        int_hand     INT_ILL, ILL, do_trap
+        int_hand     INT_GPV, GPV, do_trap
+        int_hand     INT_IDN_ACCESS, IDN_ACCESS, do_trap
+        int_hand     INT_UDN_ACCESS, UDN_ACCESS, do_trap
+        int_hand     INT_SWINT_3, SWINT_3, do_trap
+        int_hand     INT_SWINT_2, SWINT_2, do_trap
+        int_hand     INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
+        int_hand     INT_SWINT_0, SWINT_0, do_trap
+        int_hand     INT_ILL_TRANS, ILL_TRANS, do_trap
+        int_hand     INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign
+        int_hand     INT_DTLB_MISS, DTLB_MISS, do_page_fault
+        int_hand     INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
+        int_hand     INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr
+        int_hand     INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
+        int_hand     INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
+        int_hand     INT_IDN_TIMER, IDN_TIMER, bad_intr
+        int_hand     INT_UDN_TIMER, UDN_TIMER, bad_intr
+        int_hand     INT_IDN_AVAIL, IDN_AVAIL, bad_intr
+        int_hand     INT_UDN_AVAIL, UDN_AVAIL, bad_intr
+        int_hand     INT_IPI_3, IPI_3, bad_intr
+#if CONFIG_KERNEL_PL == 2
+        int_hand     INT_IPI_2, IPI_2, tile_dev_intr
+        int_hand     INT_IPI_1, IPI_1, bad_intr
+#else
+        int_hand     INT_IPI_2, IPI_2, bad_intr
+        int_hand     INT_IPI_1, IPI_1, tile_dev_intr
+#endif
+        int_hand     INT_IPI_0, IPI_0, bad_intr
+        int_hand     INT_PERF_COUNT, PERF_COUNT, \
+                     op_handle_perf_interrupt, handle_nmi
+        int_hand     INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
+                     op_handle_perf_interrupt, handle_nmi
+        int_hand     INT_INTCTRL_3, INTCTRL_3, bad_intr
+#if CONFIG_KERNEL_PL == 2
+        dc_dispatch  INT_INTCTRL_2, INTCTRL_2
+        int_hand     INT_INTCTRL_1, INTCTRL_1, bad_intr
+#else
+        int_hand     INT_INTCTRL_2, INTCTRL_2, bad_intr
+        dc_dispatch  INT_INTCTRL_1, INTCTRL_1
+#endif
+        int_hand     INT_INTCTRL_0, INTCTRL_0, bad_intr
+        int_hand     INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
+                     hv_message_intr
+        int_hand     INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
+        int_hand     INT_I_ASID, I_ASID, bad_intr
+        int_hand     INT_D_ASID, D_ASID, bad_intr
+        int_hand     INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
+
+        /* Synthetic interrupt delivered only by the simulator */
+        int_hand     INT_BREAKPOINT, BREAKPOINT, do_breakpoint
diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c
index e2ab82b7c7e7..f68df69f1f67 100644
--- a/arch/tile/kernel/module.c
+++ b/arch/tile/kernel/module.c
@@ -22,6 +22,7 @@
 #include <linux/kernel.h>
 #include <asm/opcode-tile.h>
 #include <asm/pgtable.h>
+#include <asm/homecache.h>
 
 #ifdef __tilegx__
 # define Elf_Rela Elf64_Rela
@@ -86,8 +87,13 @@ error:
 void module_free(struct module *mod, void *module_region)
 {
         vfree(module_region);
+
+        /* Globally flush the L1 icache. */
+        flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
+                     0, 0, 0, NULL, NULL, 0);
+
         /*
-         * FIXME: If module_region == mod->init_region, trim exception
+         * FIXME: If module_region == mod->module_init, trim exception
          * table entries.
          */
 }
diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c
index 658752b2835e..658f2ce426a4 100644
--- a/arch/tile/kernel/pci-dma.c
+++ b/arch/tile/kernel/pci-dma.c
@@ -244,7 +244,7 @@ EXPORT_SYMBOL(dma_sync_single_range_for_device);
  * dma_alloc_noncoherent() returns non-cacheable memory, so there's no
  * need to do any flushing here.
  */
-void dma_cache_sync(void *vaddr, size_t size,
+void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
                     enum dma_data_direction direction)
 {
 }
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index ea38f0c9ec7c..6d4cb5d7a9fd 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
  *
  *   This program is free software; you can redistribute it and/or
  *   modify it under the terms of the GNU General Public License
@@ -59,6 +59,7 @@ int __write_once tile_plx_gen1;
 
 static struct pci_controller controllers[TILE_NUM_PCIE];
 static int num_controllers;
+static int pci_scan_flags[TILE_NUM_PCIE];
 
 static struct pci_ops tile_cfg_ops;
 
@@ -79,7 +80,7 @@ EXPORT_SYMBOL(pcibios_align_resource);
  * controller_id is the controller number, config type is 0 or 1 for
  * config0 or config1 operations.
  */
-static int __init tile_pcie_open(int controller_id, int config_type)
+static int __devinit tile_pcie_open(int controller_id, int config_type)
 {
         char filename[32];
         int fd;
@@ -95,7 +96,7 @@ static int __init tile_pcie_open(int controller_id, int config_type)
 /*
  * Get the IRQ numbers from the HV and set up the handlers for them.
  */
-static int __init tile_init_irqs(int controller_id,
+static int __devinit tile_init_irqs(int controller_id,
                                  struct pci_controller *controller)
 {
         char filename[32];
@@ -139,71 +140,74 @@ static int __init tile_init_irqs(int controller_id,
  *
  * Returns the number of controllers discovered.
  */
-int __init tile_pci_init(void)
+int __devinit tile_pci_init(void)
 {
         int i;
 
         pr_info("PCI: Searching for controllers...\n");
 
+        /* Re-init number of PCIe controllers to support hot-plug feature. */
+        num_controllers = 0;
+
         /* Do any configuration we need before using the PCIe */
 
         for (i = 0; i < TILE_NUM_PCIE; i++) {
-                int hv_cfg_fd0 = -1;
-                int hv_cfg_fd1 = -1;
-                int hv_mem_fd = -1;
-                char name[32];
-                struct pci_controller *controller;
-
                 /*
-                 * Open the fd to the HV.  If it fails then this
-                 * device doesn't exist.
+                 * To see whether we need a real config op based on
+                 * the results of pcibios_init(), to support PCIe hot-plug.
                  */
-                hv_cfg_fd0 = tile_pcie_open(i, 0);
-                if (hv_cfg_fd0 < 0)
-                        continue;
-                hv_cfg_fd1 = tile_pcie_open(i, 1);
-                if (hv_cfg_fd1 < 0) {
-                        pr_err("PCI: Couldn't open config fd to HV "
-                            "for controller %d\n", i);
-                        goto err_cont;
-                }
-
-                sprintf(name, "pcie/%d/mem", i);
-                hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
-                if (hv_mem_fd < 0) {
-                        pr_err("PCI: Could not open mem fd to HV!\n");
-                        goto err_cont;
-                }
+                if (pci_scan_flags[i] == 0) {
+                        int hv_cfg_fd0 = -1;
+                        int hv_cfg_fd1 = -1;
+                        int hv_mem_fd = -1;
+                        char name[32];
+                        struct pci_controller *controller;
+
+                        /*
+                         * Open the fd to the HV.  If it fails then this
+                         * device doesn't exist.
+                         */
+                        hv_cfg_fd0 = tile_pcie_open(i, 0);
+                        if (hv_cfg_fd0 < 0)
+                                continue;
+                        hv_cfg_fd1 = tile_pcie_open(i, 1);
+                        if (hv_cfg_fd1 < 0) {
+                                pr_err("PCI: Couldn't open config fd to HV "
+                                    "for controller %d\n", i);
+                                goto err_cont;
+                        }
 
-                pr_info("PCI: Found PCI controller #%d\n", i);
+                        sprintf(name, "pcie/%d/mem", i);
+                        hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
+                        if (hv_mem_fd < 0) {
+                                pr_err("PCI: Could not open mem fd to HV!\n");
+                                goto err_cont;
+                        }
 
-                controller = &controllers[num_controllers];
+                        pr_info("PCI: Found PCI controller #%d\n", i);
 
-                if (tile_init_irqs(i, controller)) {
-                        pr_err("PCI: Could not initialize "
-                               "IRQs, aborting.\n");
-                        goto err_cont;
-                }
+                        controller = &controllers[i];
 
-                controller->index = num_controllers;
-                controller->hv_cfg_fd[0] = hv_cfg_fd0;
-                controller->hv_cfg_fd[1] = hv_cfg_fd1;
-                controller->hv_mem_fd = hv_mem_fd;
-                controller->first_busno = 0;
-                controller->last_busno = 0xff;
-                controller->ops = &tile_cfg_ops;
+                        controller->index = i;
+                        controller->hv_cfg_fd[0] = hv_cfg_fd0;
+                        controller->hv_cfg_fd[1] = hv_cfg_fd1;
+                        controller->hv_mem_fd = hv_mem_fd;
+                        controller->first_busno = 0;
+                        controller->last_busno = 0xff;
+                        controller->ops = &tile_cfg_ops;
 
-                num_controllers++;
-                continue;
+                        num_controllers++;
+                        continue;
 
 err_cont:
-                if (hv_cfg_fd0 >= 0)
-                        hv_dev_close(hv_cfg_fd0);
-                if (hv_cfg_fd1 >= 0)
-                        hv_dev_close(hv_cfg_fd1);
-                if (hv_mem_fd >= 0)
-                        hv_dev_close(hv_mem_fd);
-                continue;
+                        if (hv_cfg_fd0 >= 0)
+                                hv_dev_close(hv_cfg_fd0);
+                        if (hv_cfg_fd1 >= 0)
+                                hv_dev_close(hv_cfg_fd1);
+                        if (hv_mem_fd >= 0)
+                                hv_dev_close(hv_mem_fd);
+                        continue;
+                }
         }
 
         /*
@@ -232,7 +236,7 @@ static int tile_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 
-static void __init fixup_read_and_payload_sizes(void)
+static void __devinit fixup_read_and_payload_sizes(void)
 {
         struct pci_dev *dev = NULL;
         int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
@@ -282,7 +286,7 @@ static void __init fixup_read_and_payload_sizes(void)
  * The controllers have been set up by the time we get here, by a call to
  * tile_pci_init.
  */
-static int __init pcibios_init(void)
+int __devinit pcibios_init(void)
 {
         int i;
 
@@ -296,25 +300,36 @@ static int __init pcibios_init(void)
         mdelay(250);
 
         /* Scan all of the recorded PCI controllers.  */
-        for (i = 0; i < num_controllers; i++) {
-                struct pci_controller *controller = &controllers[i];
-                struct pci_bus *bus;
-
-                pr_info("PCI: initializing controller #%d\n", i);
-
+        for (i = 0; i < TILE_NUM_PCIE; i++) {
                 /*
-                 * This comes from the generic Linux PCI driver.
-                 *
-                 * It reads the PCI tree for this bus into the Linux
-                 * data structures.
-                 *
-                 * This is inlined in linux/pci.h and calls into
-                 * pci_scan_bus_parented() in probe.c.
+                 * Do real pcibios init ops if the controller is initialized
+                 * by tile_pci_init() successfully and not initialized by
+                 * pcibios_init() yet to support PCIe hot-plug.
                  */
-                bus = pci_scan_bus(0, controller->ops, controller);
-                controller->root_bus = bus;
-                controller->last_busno = bus->subordinate;
+                if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
+                        struct pci_controller *controller = &controllers[i];
+                        struct pci_bus *bus;
 
+                        if (tile_init_irqs(i, controller)) {
+                                pr_err("PCI: Could not initialize IRQs\n");
+                                continue;
+                        }
+
+                        pr_info("PCI: initializing controller #%d\n", i);
+
+                        /*
+                         * This comes from the generic Linux PCI driver.
+                         *
+                         * It reads the PCI tree for this bus into the Linux
+                         * data structures.
+                         *
+                         * This is inlined in linux/pci.h and calls into
+                         * pci_scan_bus_parented() in probe.c.
+                         */
+                        bus = pci_scan_bus(0, controller->ops, controller);
+                        controller->root_bus = bus;
+                        controller->last_busno = bus->subordinate;
+                }
         }
 
         /* Do machine dependent PCI interrupt routing */
@@ -326,34 +341,45 @@ static int __init pcibios_init(void)
          * It allocates all of the resources (I/O memory, etc)
          * associated with the devices read in above.
          */
-
         pci_assign_unassigned_resources();
 
         /* Configure the max_read_size and max_payload_size values. */
         fixup_read_and_payload_sizes();
 
         /* Record the I/O resources in the PCI controller structure. */
-        for (i = 0; i < num_controllers; i++) {
-                struct pci_bus *root_bus = controllers[i].root_bus;
-                struct pci_bus *next_bus;
-                struct pci_dev *dev;
-
-                list_for_each_entry(dev, &root_bus->devices, bus_list) {
-                        /* Find the PCI host controller, ie. the 1st bridge. */
-                        if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
-                                (PCI_SLOT(dev->devfn) == 0)) {
-                                next_bus = dev->subordinate;
-                                controllers[i].mem_resources[0] =
-                                        *next_bus->resource[0];
-                                controllers[i].mem_resources[1] =
-                                         *next_bus->resource[1];
-                                controllers[i].mem_resources[2] =
-                                         *next_bus->resource[2];
-
-                                break;
+        for (i = 0; i < TILE_NUM_PCIE; i++) {
+                /*
+                 * Do real pcibios init ops if the controller is initialized
+                 * by tile_pci_init() successfully and not initialized by
+                 * pcibios_init() yet to support PCIe hot-plug.
+                 */
+                if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
+                        struct pci_bus *root_bus = controllers[i].root_bus;
+                        struct pci_bus *next_bus;
+                        struct pci_dev *dev;
+
+                        list_for_each_entry(dev, &root_bus->devices, bus_list) {
+                                /*
+                                 * Find the PCI host controller, ie. the 1st
+                                 * bridge.
+                                 */
+                                if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
+                                        (PCI_SLOT(dev->devfn) == 0)) {
+                                        next_bus = dev->subordinate;
+                                        controllers[i].mem_resources[0] =
+                                                *next_bus->resource[0];
+                                        controllers[i].mem_resources[1] =
+                                                 *next_bus->resource[1];
+                                        controllers[i].mem_resources[2] =
+                                                 *next_bus->resource[2];
+
+                                        /* Setup flags. */
+                                        pci_scan_flags[i] = 1;
+
+                                        break;
+                                }
                         }
                 }
-
         }
 
         return 0;
@@ -381,7 +407,7 @@ char __devinit *pcibios_setup(char *str)
 /*
  * This is called from the generic Linux layer.
  */
-void __init pcibios_update_irq(struct pci_dev *dev, int irq)
+void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
 {
         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
 }
diff --git a/arch/tile/kernel/proc.c b/arch/tile/kernel/proc.c
index 2e02c41ddf3b..62d820833c68 100644
--- a/arch/tile/kernel/proc.c
+++ b/arch/tile/kernel/proc.c
@@ -27,6 +27,7 @@
 #include <asm/processor.h>
 #include <asm/sections.h>
 #include <asm/homecache.h>
+#include <asm/hardwall.h>
 #include <arch/chip.h>
 
 
@@ -88,3 +89,75 @@ const struct seq_operations cpuinfo_op = {
         .stop   = c_stop,
         .show   = show_cpuinfo,
 };
+
+/*
+ * Support /proc/tile directory
+ */
+
+static int __init proc_tile_init(void)
+{
+        struct proc_dir_entry *root = proc_mkdir("tile", NULL);
+        if (root == NULL)
+                return 0;
+
+        proc_tile_hardwall_init(root);
+
+        return 0;
+}
+
+arch_initcall(proc_tile_init);
+
+/*
+ * Support /proc/sys/tile directory
+ */
+
+#ifndef __tilegx__  /* FIXME: GX: no support for unaligned access yet */
+static ctl_table unaligned_subtable[] = {
+        {
+                .procname       = "enabled",
+                .data           = &unaligned_fixup,
+                .maxlen         = sizeof(int),
+                .mode           = 0644,
+                .proc_handler   = &proc_dointvec
+        },
+        {
+                .procname       = "printk",
+                .data           = &unaligned_printk,
+                .maxlen         = sizeof(int),
+                .mode           = 0644,
+                .proc_handler   = &proc_dointvec
+        },
+        {
+                .procname       = "count",
+                .data           = &unaligned_fixup_count,
+                .maxlen         = sizeof(int),
+                .mode           = 0644,
+                .proc_handler   = &proc_dointvec
+        },
+        {}
+};
+
+static ctl_table unaligned_table[] = {
+        {
+                .procname       = "unaligned_fixup",
+                .mode           = 0555,
+                .child          = unaligned_subtable
+        },
+        {}
+};
+#endif
+
+static struct ctl_path tile_path[] = {
+        { .procname = "tile" },
+        { }
+};
+
+static int __init proc_sys_tile_init(void)
+{
+#ifndef __tilegx__  /* FIXME: GX: no support for unaligned access yet */
+        register_sysctl_paths(tile_path, unaligned_table);
+#endif
+        return 0;
+}
+
+arch_initcall(proc_sys_tile_init);
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index d0065103eb7b..9c45d8bbdf57 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -25,10 +25,13 @@
 #include <linux/hardirq.h>
 #include <linux/syscalls.h>
 #include <linux/kernel.h>
+#include <linux/tracehook.h>
+#include <linux/signal.h>
 #include <asm/system.h>
 #include <asm/stack.h>
 #include <asm/homecache.h>
 #include <asm/syscalls.h>
+#include <asm/traps.h>
 #ifdef CONFIG_HARDWALL
 #include <asm/hardwall.h>
 #endif
@@ -546,6 +549,51 @@ struct task_struct *__sched _switch_to(struct task_struct *prev,
         return __switch_to(prev, next, next_current_ksp0(next));
 }
 
+/*
+ * This routine is called on return from interrupt if any of the
+ * TIF_WORK_MASK flags are set in thread_info->flags.  It is
+ * entered with interrupts disabled so we don't miss an event
+ * that modified the thread_info flags.  If any flag is set, we
+ * handle it and return, and the calling assembly code will
+ * re-disable interrupts, reload the thread flags, and call back
+ * if more flags need to be handled.
+ *
+ * We return whether we need to check the thread_info flags again
+ * or not.  Note that we don't clear TIF_SINGLESTEP here, so it's
+ * important that it be tested last, and then claim that we don't
+ * need to recheck the flags.
+ */
+int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
+{
+        if (thread_info_flags & _TIF_NEED_RESCHED) {
+                schedule();
+                return 1;
+        }
+#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
+        if (thread_info_flags & _TIF_ASYNC_TLB) {
+                do_async_page_fault(regs);
+                return 1;
+        }
+#endif
+        if (thread_info_flags & _TIF_SIGPENDING) {
+                do_signal(regs);
+                return 1;
+        }
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+                return 1;
+        }
+        if (thread_info_flags & _TIF_SINGLESTEP) {
+                if ((regs->ex1 & SPR_EX_CONTEXT_1_1__PL_MASK) == 0)
+                        single_step_once(regs);
+                return 0;
+        }
+        panic("work_pending: bad flags %#x\n", thread_info_flags);
+}
+
 /* Note there is an implicit fifth argument if (clone_flags & CLONE_SETTLS). */
 SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp,
                 void __user *, parent_tidptr, void __user *, child_tidptr,
@@ -582,8 +630,8 @@ out:
 
 #ifdef CONFIG_COMPAT
 long compat_sys_execve(const char __user *path,
-                       const compat_uptr_t __user *argv,
-                       const compat_uptr_t __user *envp,
+                       compat_uptr_t __user *argv,
+                       compat_uptr_t __user *envp,
                        struct pt_regs *regs)
 {
         long error;
diff --git a/arch/tile/kernel/regs_64.S b/arch/tile/kernel/regs_64.S
new file mode 100644
index 000000000000..f748c1e85285
--- /dev/null
+++ b/arch/tile/kernel/regs_64.S
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <arch/spr_def.h>
+#include <asm/processor.h>
+
+/*
+ * See <asm/system.h>; called with prev and next task_struct pointers.
+ * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
+ *
+ * We want to save pc/sp in "prev", and get the new pc/sp from "next".
+ * We also need to save all the callee-saved registers on the stack.
+ *
+ * Intel enables/disables access to the hardware cycle counter in
+ * seccomp (secure computing) environments if necessary, based on
+ * has_secure_computing().  We might want to do this at some point,
+ * though it would require virtualizing the other SPRs under WORLD_ACCESS.
+ *
+ * Since we're saving to the stack, we omit sp from this list.
+ * And for parallels with other architectures, we save lr separately,
+ * in the thread_struct itself (as the "pc" field).
+ *
+ * This code also needs to be aligned with process.c copy_thread()
+ */
+
+#if CALLEE_SAVED_REGS_COUNT != 24
+# error Mismatch between <asm/system.h> and kernel/entry.S
+#endif
+#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
+
+#define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
+#define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
+#define FOR_EACH_CALLEE_SAVED_REG(f)                                    \
+                                                        f(r30); f(r31); \
+        f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
+        f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
+        f(r48); f(r49); f(r50); f(r51); f(r52);
+
+STD_ENTRY_SECTION(__switch_to, .sched.text)
+        {
+          move r10, sp
+          st sp, lr
+        }
+        {
+          addli r11, sp, -FRAME_SIZE + 8
+          addli sp, sp, -FRAME_SIZE
+        }
+        {
+          st r11, r10
+          addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
+        }
+        {
+          ld r13, r4   /* Load new sp to a temp register early. */
+          addi r12, sp, 16
+        }
+        FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
+        addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
+        {
+          st r3, sp
+          addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
+        }
+        {
+          st r3, lr
+          addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
+        }
+        {
+          ld lr, r4
+          addi r12, r13, 16
+        }
+        {
+          /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
+          move sp, r13
+          mtspr SPR_SYSTEM_SAVE_K_0, r2
+        }
+        FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
+.L__switch_to_pc:
+        {
+          addli sp, sp, FRAME_SIZE
+          jrp lr   /* r0 is still valid here, so return it */
+        }
+        STD_ENDPROC(__switch_to)
+
+/* Return a suitable address for the backtracer for suspended threads */
+STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
+        lnk r0
+        {
+          addli r0, r0, .L__switch_to_pc - .
+          jrp lr
+        }
+        STD_ENDPROC(get_switch_to_pc)
+
+STD_ENTRY(get_pt_regs)
+        .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
+                 r8, r9, r10, r11, r12, r13, r14, r15, \
+                 r16, r17, r18, r19, r20, r21, r22, r23, \
+                 r24, r25, r26, r27, r28, r29, r30, r31, \
+                 r32, r33, r34, r35, r36, r37, r38, r39, \
+                 r40, r41, r42, r43, r44, r45, r46, r47, \
+                 r48, r49, r50, r51, r52, tp, sp
+        {
+         st r0, \reg
+         addi r0, r0, 8
+        }
+        .endr
+        {
+         st r0, lr
+         addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
+        }
+        lnk r1
+        {
+         st r0, r1
+         addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
+        }
+        mfspr r1, INTERRUPT_CRITICAL_SECTION
+        shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
+        ori r1, r1, KERNEL_PL
+        {
+         st r0, r1
+         addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
+        }
+        {
+         st r0, zero       /* clear faultnum */
+         addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
+        }
+        {
+         st r0, zero       /* clear orig_r0 */
+         addli r0, r0, -PTREGS_OFFSET_ORIG_R0    /* restore r0 to base */
+        }
+        jrp lr
+        STD_ENDPROC(get_pt_regs)
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 3696b1832566..6cdc9ba55fe0 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -912,6 +912,8 @@ void __cpuinit setup_cpu(int boot)
 #endif
 }
 
+#ifdef CONFIG_BLK_DEV_INITRD
+
 static int __initdata set_initramfs_file;
 static char __initdata initramfs_file[128] = "initramfs.cpio.gz";
 
@@ -969,6 +971,10 @@ void __init free_initrd_mem(unsigned long begin, unsigned long end)
         free_bootmem(__pa(begin), end - begin);
 }
 
+#else
+static inline void load_hv_initrd(void) {}
+#endif /* CONFIG_BLK_DEV_INITRD */
+
 static void __init validate_hv(void)
 {
         /*
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
index 1260321155f1..bedaf4e9f3a7 100644
--- a/arch/tile/kernel/signal.c
+++ b/arch/tile/kernel/signal.c
@@ -39,7 +39,6 @@
 
 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
 
-
 SYSCALL_DEFINE3(sigaltstack, const stack_t __user *, uss,
                 stack_t __user *, uoss, struct pt_regs *, regs)
 {
@@ -78,6 +77,13 @@ int restore_sigcontext(struct pt_regs *regs,
         return err;
 }
 
+void signal_fault(const char *type, struct pt_regs *regs,
+                  void __user *frame, int sig)
+{
+        trace_unhandled_signal(type, regs, (unsigned long)frame, SIGSEGV);
+        force_sigsegv(sig, current);
+}
+
 /* The assembly shim for this function arranges to ignore the return value. */
 SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs)
 {
@@ -105,7 +111,7 @@ SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs)
         return 0;
 
 badframe:
-        force_sig(SIGSEGV, current);
+        signal_fault("bad sigreturn frame", regs, frame, 0);
         return 0;
 }
 
@@ -231,7 +237,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
         return 0;
 
 give_sigsegv:
-        force_sigsegv(sig, current);
+        signal_fault("bad setup frame", regs, frame, sig);
         return -EFAULT;
 }
 
@@ -245,7 +251,6 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
 {
         int ret;
 
-
         /* Are we from a system call? */
         if (regs->faultnum == INT_SWINT_1) {
                 /* If so, check system call restarting.. */
@@ -363,3 +368,118 @@ done:
         /* Avoid double syscall restart if there are nested signals. */
         regs->faultnum = INT_SWINT_1_SIGRETURN;
 }
+
+int show_unhandled_signals = 1;
+
+static int __init crashinfo(char *str)
+{
+        unsigned long val;
+        const char *word;
+
+        if (*str == '\0')
+                val = 2;
+        else if (*str != '=' || strict_strtoul(++str, 0, &val) != 0)
+                return 0;
+        show_unhandled_signals = val;
+        switch (show_unhandled_signals) {
+        case 0:
+                word = "No";
+                break;
+        case 1:
+                word = "One-line";
+                break;
+        default:
+                word = "Detailed";
+                break;
+        }
+        pr_info("%s crash reports will be generated on the console\n", word);
+        return 1;
+}
+__setup("crashinfo", crashinfo);
+
+static void dump_mem(void __user *address)
+{
+        void __user *addr;
+        enum { region_size = 256, bytes_per_line = 16 };
+        int i, j, k;
+        int found_readable_mem = 0;
+
+        pr_err("\n");
+        if (!access_ok(VERIFY_READ, address, 1)) {
+                pr_err("Not dumping at address 0x%lx (kernel address)\n",
+                       (unsigned long)address);
+                return;
+        }
+
+        addr = (void __user *)
+                (((unsigned long)address & -bytes_per_line) - region_size/2);
+        if (addr > address)
+                addr = NULL;
+        for (i = 0; i < region_size;
+             addr += bytes_per_line, i += bytes_per_line) {
+                unsigned char buf[bytes_per_line];
+                char line[100];
+                if (copy_from_user(buf, addr, bytes_per_line))
+                        continue;
+                if (!found_readable_mem) {
+                        pr_err("Dumping memory around address 0x%lx:\n",
+                               (unsigned long)address);
+                        found_readable_mem = 1;
+                }
+                j = sprintf(line, REGFMT":", (unsigned long)addr);
+                for (k = 0; k < bytes_per_line; ++k)
+                        j += sprintf(&line[j], " %02x", buf[k]);
+                pr_err("%s\n", line);
+        }
+        if (!found_readable_mem)
+                pr_err("No readable memory around address 0x%lx\n",
+                       (unsigned long)address);
+}
+
+void trace_unhandled_signal(const char *type, struct pt_regs *regs,
+                            unsigned long address, int sig)
+{
+        struct task_struct *tsk = current;
+
+        if (show_unhandled_signals == 0)
+                return;
+
+        /* If the signal is handled, don't show it here. */
+        if (!is_global_init(tsk)) {
+                void __user *handler =
+                        tsk->sighand->action[sig-1].sa.sa_handler;
+                if (handler != SIG_IGN && handler != SIG_DFL)
+                        return;
+        }
+
+        /* Rate-limit the one-line output, not the detailed output. */
+        if (show_unhandled_signals <= 1 && !printk_ratelimit())
+                return;
+
+        printk("%s%s[%d]: %s at %lx pc "REGFMT" signal %d",
+               task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
+               tsk->comm, task_pid_nr(tsk), type, address, regs->pc, sig);
+
+        print_vma_addr(KERN_CONT " in ", regs->pc);
+
+        printk(KERN_CONT "\n");
+
+        if (show_unhandled_signals > 1) {
+                switch (sig) {
+                case SIGILL:
+                case SIGFPE:
+                case SIGSEGV:
+                case SIGBUS:
+                        pr_err("User crash: signal %d,"
+                               " trap %ld, address 0x%lx\n",
+                               sig, regs->faultnum, address);
+                        show_regs(regs);
+                        dump_mem((void __user *)address);
+                        break;
+                default:
+                        pr_err("User crash: signal %d, trap %ld\n",
+                               sig, regs->faultnum);
+                        break;
+                }
+        }
+}
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
index 84a729e06ec4..4032ca8e51b6 100644
--- a/arch/tile/kernel/single_step.c
+++ b/arch/tile/kernel/single_step.c
@@ -186,6 +186,8 @@ static tile_bundle_bits rewrite_load_store_unaligned(
                         .si_code = SEGV_MAPERR,
                         .si_addr = addr
                 };
+                trace_unhandled_signal("segfault", regs,
+                                       (unsigned long)addr, SIGSEGV);
                 force_sig_info(info.si_signo, &info, current);
                 return (tile_bundle_bits) 0;
         }
@@ -196,6 +198,8 @@ static tile_bundle_bits rewrite_load_store_unaligned(
                         .si_code = BUS_ADRALN,
                         .si_addr = addr
                 };
+                trace_unhandled_signal("unaligned trap", regs,
+                                       (unsigned long)addr, SIGBUS);
                 force_sig_info(info.si_signo, &info, current);
                 return (tile_bundle_bits) 0;
         }
@@ -318,6 +322,14 @@ void single_step_once(struct pt_regs *regs)
 "    .popsection\n"
         );
 
+        /*
+         * Enable interrupts here to allow touching userspace and the like.
+         * The callers expect this: do_trap() already has interrupts
+         * enabled, and do_work_pending() handles functions that enable
+         * interrupts internally.
+         */
+        local_irq_enable();
+
         if (state == NULL) {
                 /* allocate a page of writable, executable memory */
                 state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index dd81713a90dc..37ee4d037e0b 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -36,7 +36,7 @@
 #define KBT_LOOP        3  /* Backtrace entered a loop */
 
 /* Is address on the specified kernel stack? */
-static int in_kernel_stack(struct KBacktraceIterator *kbt, VirtualAddress sp)
+static int in_kernel_stack(struct KBacktraceIterator *kbt, unsigned long sp)
 {
         ulong kstack_base = (ulong) kbt->task->stack;
         if (kstack_base == 0)  /* corrupt task pointer; just follow stack... */
@@ -45,7 +45,7 @@ static int in_kernel_stack(struct KBacktraceIterator *kbt, VirtualAddress sp)
 }
 
 /* Is address valid for reading? */
-static int valid_address(struct KBacktraceIterator *kbt, VirtualAddress address)
+static int valid_address(struct KBacktraceIterator *kbt, unsigned long address)
 {
         HV_PTE *l1_pgtable = kbt->pgtable;
         HV_PTE *l2_pgtable;
@@ -97,7 +97,7 @@ static int valid_address(struct KBacktraceIterator *kbt, VirtualAddress address)
 }
 
 /* Callback for backtracer; basically a glorified memcpy */
-static bool read_memory_func(void *result, VirtualAddress address,
+static bool read_memory_func(void *result, unsigned long address,
                              unsigned int size, void *vkbt)
 {
         int retval;
@@ -124,7 +124,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
 {
         const char *fault = NULL;  /* happy compiler */
         char fault_buf[64];
-        VirtualAddress sp = kbt->it.sp;
+        unsigned long sp = kbt->it.sp;
         struct pt_regs *p;
 
         if (!in_kernel_stack(kbt, sp))
@@ -163,7 +163,7 @@ static struct pt_regs *valid_fault_handler(struct KBacktraceIterator* kbt)
 }
 
 /* Is the pc pointing to a sigreturn trampoline? */
-static int is_sigreturn(VirtualAddress pc)
+static int is_sigreturn(unsigned long pc)
 {
         return (pc == VDSO_BASE);
 }
@@ -260,7 +260,7 @@ static void validate_stack(struct pt_regs *regs)
 void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
                              struct task_struct *t, struct pt_regs *regs)
 {
-        VirtualAddress pc, lr, sp, r52;
+        unsigned long pc, lr, sp, r52;
         int is_current;
 
         /*
@@ -331,7 +331,7 @@ EXPORT_SYMBOL(KBacktraceIterator_end);
 
 void KBacktraceIterator_next(struct KBacktraceIterator *kbt)
 {
-        VirtualAddress old_pc = kbt->it.pc, old_sp = kbt->it.sp;
+        unsigned long old_pc = kbt->it.pc, old_sp = kbt->it.sp;
         kbt->new_context = 0;
         if (!backtrace_next(&kbt->it) && !KBacktraceIterator_restart(kbt)) {
                 kbt->end = KBT_DONE;
diff --git a/arch/tile/kernel/sys.c b/arch/tile/kernel/sys.c
index e2187d24a9b4..cb44ba7ccd2d 100644
--- a/arch/tile/kernel/sys.c
+++ b/arch/tile/kernel/sys.c
@@ -56,13 +56,6 @@ ssize_t sys32_readahead(int fd, u32 offset_lo, u32 offset_hi, u32 count)
         return sys_readahead(fd, ((loff_t)offset_hi << 32) | offset_lo, count);
 }
 
-long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi,
-                     u32 len, int advice)
-{
-        return sys_fadvise64_64(fd, ((loff_t)offset_hi << 32) | offset_lo,
-                                len, advice);
-}
-
 int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,
                        u32 len_lo, u32 len_hi, int advice)
 {
@@ -103,10 +96,8 @@ SYSCALL_DEFINE6(mmap, unsigned long, addr, unsigned long, len,
 
 #ifndef __tilegx__
 /* See comments at the top of the file. */
-#define sys_fadvise64 sys32_fadvise64
 #define sys_fadvise64_64 sys32_fadvise64_64
 #define sys_readahead sys32_readahead
-#define sys_sync_file_range sys_sync_file_range2
 #endif
 
 /* Call the trampolines to manage pt_regs where necessary. */
diff --git a/arch/tile/kernel/sysfs.c b/arch/tile/kernel/sysfs.c
new file mode 100644
index 000000000000..b671a86f4515
--- /dev/null
+++ b/arch/tile/kernel/sysfs.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * /sys entry support.
+ */
+
+#include <linux/sysdev.h>
+#include <linux/cpu.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <hv/hypervisor.h>
+
+/* Return a string queried from the hypervisor, truncated to page size. */
+static ssize_t get_hv_confstr(char *page, int query)
+{
+        ssize_t n = hv_confstr(query, (unsigned long)page, PAGE_SIZE - 1);
+        n = n < 0 ? 0 : min(n, (ssize_t)PAGE_SIZE - 1) - 1;
+        if (n)
+                page[n++] = '\n';
+        page[n] = '\0';
+        return n;
+}
+
+static ssize_t chip_width_show(struct sysdev_class *dev,
+                               struct sysdev_class_attribute *attr,
+                               char *page)
+{
+        return sprintf(page, "%u\n", smp_width);
+}
+static SYSDEV_CLASS_ATTR(chip_width, 0444, chip_width_show, NULL);
+
+static ssize_t chip_height_show(struct sysdev_class *dev,
+                                struct sysdev_class_attribute *attr,
+                                char *page)
+{
+        return sprintf(page, "%u\n", smp_height);
+}
+static SYSDEV_CLASS_ATTR(chip_height, 0444, chip_height_show, NULL);
+
+static ssize_t chip_serial_show(struct sysdev_class *dev,
+                                struct sysdev_class_attribute *attr,
+                                char *page)
+{
+        return get_hv_confstr(page, HV_CONFSTR_CHIP_SERIAL_NUM);
+}
+static SYSDEV_CLASS_ATTR(chip_serial, 0444, chip_serial_show, NULL);
+
+static ssize_t chip_revision_show(struct sysdev_class *dev,
+                                  struct sysdev_class_attribute *attr,
+                                  char *page)
+{
+        return get_hv_confstr(page, HV_CONFSTR_CHIP_REV);
+}
+static SYSDEV_CLASS_ATTR(chip_revision, 0444, chip_revision_show, NULL);
+
+
+static ssize_t type_show(struct sysdev_class *dev,
+                            struct sysdev_class_attribute *attr,
+                            char *page)
+{
+        return sprintf(page, "tilera\n");
+}
+static SYSDEV_CLASS_ATTR(type, 0444, type_show, NULL);
+
+#define HV_CONF_ATTR(name, conf)                                        \
+        static ssize_t name ## _show(struct sysdev_class *dev,          \
+                                     struct sysdev_class_attribute *attr, \
+                                     char *page)                        \
+        {                                                               \
+                return get_hv_confstr(page, conf);                      \
+        }                                                               \
+        static SYSDEV_CLASS_ATTR(name, 0444, name ## _show, NULL);
+
+HV_CONF_ATTR(version,           HV_CONFSTR_HV_SW_VER)
+HV_CONF_ATTR(config_version,    HV_CONFSTR_HV_CONFIG_VER)
+
+HV_CONF_ATTR(board_part,        HV_CONFSTR_BOARD_PART_NUM)
+HV_CONF_ATTR(board_serial,      HV_CONFSTR_BOARD_SERIAL_NUM)
+HV_CONF_ATTR(board_revision,    HV_CONFSTR_BOARD_REV)
+HV_CONF_ATTR(board_description, HV_CONFSTR_BOARD_DESC)
+HV_CONF_ATTR(mezz_part,         HV_CONFSTR_MEZZ_PART_NUM)
+HV_CONF_ATTR(mezz_serial,       HV_CONFSTR_MEZZ_SERIAL_NUM)
+HV_CONF_ATTR(mezz_revision,     HV_CONFSTR_MEZZ_REV)
+HV_CONF_ATTR(mezz_description,  HV_CONFSTR_MEZZ_DESC)
+HV_CONF_ATTR(switch_control,    HV_CONFSTR_SWITCH_CONTROL)
+
+static struct attribute *board_attrs[] = {
+        &attr_board_part.attr,
+        &attr_board_serial.attr,
+        &attr_board_revision.attr,
+        &attr_board_description.attr,
+        &attr_mezz_part.attr,
+        &attr_mezz_serial.attr,
+        &attr_mezz_revision.attr,
+        &attr_mezz_description.attr,
+        &attr_switch_control.attr,
+        NULL
+};
+
+static struct attribute_group board_attr_group = {
+        .name   = "board",
+        .attrs  = board_attrs,
+};
+
+
+static struct bin_attribute hvconfig_bin;
+
+static ssize_t
+hvconfig_bin_read(struct file *filp, struct kobject *kobj,
+                  struct bin_attribute *bin_attr,
+                  char *buf, loff_t off, size_t count)
+{
+        static size_t size;
+
+        /* Lazily learn the true size (minus the trailing NUL). */
+        if (size == 0)
+                size = hv_confstr(HV_CONFSTR_HV_CONFIG, 0, 0) - 1;
+
+        /* Check and adjust input parameters. */
+        if (off > size)
+                return -EINVAL;
+        if (count > size - off)
+                count = size - off;
+
+        if (count) {
+                /* Get a copy of the hvc and copy out the relevant portion. */
+                char *hvc;
+
+                size = off + count;
+                hvc = kmalloc(size, GFP_KERNEL);
+                if (hvc == NULL)
+                        return -ENOMEM;
+                hv_confstr(HV_CONFSTR_HV_CONFIG, (unsigned long)hvc, size);
+                memcpy(buf, hvc + off, count);
+                kfree(hvc);
+        }
+
+        return count;
+}
+
+static int __init create_sysfs_entries(void)
+{
+        struct sysdev_class *cls = &cpu_sysdev_class;
+        int err = 0;
+
+#define create_cpu_attr(name)                                           \
+        if (!err)                                                       \
+                err = sysfs_create_file(&cls->kset.kobj, &attr_##name.attr);
+        create_cpu_attr(chip_width);
+        create_cpu_attr(chip_height);
+        create_cpu_attr(chip_serial);
+        create_cpu_attr(chip_revision);
+
+#define create_hv_attr(name)                                            \
+        if (!err)                                                       \
+                err = sysfs_create_file(hypervisor_kobj, &attr_##name.attr);
+        create_hv_attr(type);
+        create_hv_attr(version);
+        create_hv_attr(config_version);
+
+        if (!err)
+                err = sysfs_create_group(hypervisor_kobj, &board_attr_group);
+
+        if (!err) {
+                sysfs_bin_attr_init(&hvconfig_bin);
+                hvconfig_bin.attr.name = "hvconfig";
+                hvconfig_bin.attr.mode = S_IRUGO;
+                hvconfig_bin.read = hvconfig_bin_read;
+                hvconfig_bin.size = PAGE_SIZE;
+                err = sysfs_create_bin_file(hypervisor_kobj, &hvconfig_bin);
+        }
+
+        return err;
+}
+subsys_initcall(create_sysfs_entries);
diff --git a/arch/tile/kernel/tile-desc_32.c b/arch/tile/kernel/tile-desc_32.c
index 69af0e150f78..7e31a1285788 100644
--- a/arch/tile/kernel/tile-desc_32.c
+++ b/arch/tile/kernel/tile-desc_32.c
@@ -2413,12 +2413,13 @@ const struct tile_operand tile_operands[43] =
 
 
 
-/* Given a set of bundle bits and the lookup FSM for a specific pipe,
- * returns which instruction the bundle contains in that pipe.
+/* Given a set of bundle bits and a specific pipe, returns which
+ * instruction the bundle contains in that pipe.
  */
-static const struct tile_opcode *
-find_opcode(tile_bundle_bits bits, const unsigned short *table)
+const struct tile_opcode *
+find_opcode(tile_bundle_bits bits, tile_pipeline pipe)
 {
+  const unsigned short *table = tile_bundle_decoder_fsms[pipe];
   int index = 0;
 
   while (1)
@@ -2465,7 +2466,7 @@ parse_insn_tile(tile_bundle_bits bits,
     int i;
 
     d = &decoded[num_instructions++];
-    opc = find_opcode (bits, tile_bundle_decoder_fsms[pipe]);
+    opc = find_opcode (bits, (tile_pipeline)pipe);
     d->opcode = opc;
 
     /* Decode each operand, sign extending, etc. as appropriate. */
diff --git a/arch/tile/kernel/tile-desc_64.c b/arch/tile/kernel/tile-desc_64.c
new file mode 100644
index 000000000000..d57007bed77f
--- /dev/null
+++ b/arch/tile/kernel/tile-desc_64.c
@@ -0,0 +1,2200 @@
+/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
+#define BFD_RELOC(x) -1
+
+/* Special registers. */
+#define TREG_LR 55
+#define TREG_SN 56
+#define TREG_ZERO 63
+
+/* FIXME: Rename this. */
+#include <asm/opcode-tile_64.h>
+
+#include <linux/stddef.h>
+
+const struct tilegx_opcode tilegx_opcodes[334] =
+{
+ { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
+    { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
+  },
+  { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
+    { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } },
+  },
+  { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
+    { { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
+  },
+  { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
+    { { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+  },
+  { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+  },
+  { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+  },
+  { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+  },
+  { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
+    { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
+    { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
+    { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+  },
+  { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+  },
+  { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+  },
+  { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+  },
+  { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
+    { {  }, {  }, {  }, {  }, { 0, } },
+  },
+  { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+  },
+  { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
+    { { 0, }, {  }, { 0, }, {  }, { 0, } },
+  },
+  { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
+    { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
+    { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+  },
+  { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
+    { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+  },
+  { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+  },
+  { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+  },
+  { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+  },
+  { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
+    { { 0, }, { 8 }, { 0, }, { 12 }, { 0, } },
+  },
+  { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
+    { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+  },
+  { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
+    { {  }, {  }, {  }, {  }, { 0, } },
+  },
+  { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+  },
+  { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+  },
+  { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
+    { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+  },
+  { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+  },
+  { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+  },
+  { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+  },
+  { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+  },
+  { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+  },
+  { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+  },
+  { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+  },
+  { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+  },
+  { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
+    { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
+    { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
+    { { 0, }, {  }, { 0, }, { 0, }, { 0, } },
+  },
+  { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
+    { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+  },
+  { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
+    { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+  },
+  { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
+    { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+  },
+  { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
+    { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+  },
+  { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
+    { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
+    { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+  },
+  { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
+    { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+  },
+  { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
+    { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+  },
+  { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
+  }
+};
+#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
+#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
+
+static const unsigned short decode_X0_fsm[936] =
+{
+  BITFIELD(22, 9) /* index 0 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
+  TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
+  TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
+  TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
+  TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
+  CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
+  CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+  BITFIELD(6, 2) /* index 513 */,
+  TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
+  BITFIELD(8, 2) /* index 518 */,
+  TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
+  BITFIELD(10, 2) /* index 523 */,
+  TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
+  BITFIELD(20, 2) /* index 528 */,
+  TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
+  BITFIELD(6, 2) /* index 533 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
+  BITFIELD(8, 2) /* index 538 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
+  BITFIELD(10, 2) /* index 543 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+  BITFIELD(0, 2) /* index 548 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
+  BITFIELD(2, 2) /* index 553 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
+  BITFIELD(4, 2) /* index 558 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
+  BITFIELD(6, 2) /* index 563 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
+  BITFIELD(8, 2) /* index 568 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
+  BITFIELD(10, 2) /* index 573 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+  BITFIELD(20, 2) /* index 578 */,
+  TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
+  BITFIELD(20, 2) /* index 583 */,
+  TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
+  TILEGX_OPC_V1CMPLTUI,
+  BITFIELD(20, 2) /* index 588 */,
+  TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
+  TILEGX_OPC_V2CMPEQI,
+  BITFIELD(20, 2) /* index 593 */,
+  TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
+  TILEGX_OPC_V2MINSI,
+  BITFIELD(20, 2) /* index 598 */,
+  TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(18, 4) /* index 603 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
+  TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
+  TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+  TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
+  BITFIELD(18, 4) /* index 620 */,
+  TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
+  TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
+  TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
+  TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
+  TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
+  TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
+  BITFIELD(18, 4) /* index 637 */,
+  TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
+  TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
+  TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
+  TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
+  TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
+  TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
+  BITFIELD(18, 4) /* index 654 */,
+  TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
+  TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
+  TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
+  TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
+  TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
+  TILEGX_OPC_MZ,
+  BITFIELD(18, 4) /* index 671 */,
+  TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
+  TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
+  TILEGX_OPC_SUBXSC,
+  BITFIELD(12, 2) /* index 688 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
+  BITFIELD(14, 2) /* index 693 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
+  BITFIELD(16, 2) /* index 698 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+  BITFIELD(18, 4) /* index 703 */,
+  TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
+  TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
+  TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
+  TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
+  TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
+  BITFIELD(12, 4) /* index 720 */,
+  TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
+  CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
+  CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 737 */,
+  TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 742 */,
+  TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 747 */,
+  TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 752 */,
+  TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 757 */,
+  TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 762 */,
+  TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 767 */,
+  TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 772 */,
+  TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 777 */,
+  TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 782 */,
+  TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 787 */,
+  TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(16, 2) /* index 792 */,
+  TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(18, 4) /* index 797 */,
+  TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
+  TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
+  TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
+  TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
+  TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
+  BITFIELD(18, 4) /* index 814 */,
+  TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
+  TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
+  TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
+  TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
+  TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
+  BITFIELD(18, 4) /* index 831 */,
+  TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
+  TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
+  TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
+  TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
+  TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
+  BITFIELD(18, 4) /* index 848 */,
+  TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
+  TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
+  TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
+  TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
+  TILEGX_OPC_V4SUB,
+  BITFIELD(18, 3) /* index 865 */,
+  CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(21, 1) /* index 874 */,
+  TILEGX_OPC_XOR, TILEGX_OPC_NONE,
+  BITFIELD(21, 1) /* index 877 */,
+  TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
+  BITFIELD(21, 1) /* index 880 */,
+  TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
+  BITFIELD(21, 1) /* index 883 */,
+  TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
+  BITFIELD(21, 1) /* index 886 */,
+  TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
+  BITFIELD(18, 4) /* index 889 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
+  TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
+  TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
+  TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE,
+  BITFIELD(0, 2) /* index 906 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(911),
+  BITFIELD(2, 2) /* index 911 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(916),
+  BITFIELD(4, 2) /* index 916 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(921),
+  BITFIELD(6, 2) /* index 921 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(926),
+  BITFIELD(8, 2) /* index 926 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(931),
+  BITFIELD(10, 2) /* index 931 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  TILEGX_OPC_INFOL,
+};
+
+static const unsigned short decode_X1_fsm[1206] =
+{
+  BITFIELD(53, 9) /* index 0 */,
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+  CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+  TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
+  TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
+  TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
+  TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
+  TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
+  TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
+  TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
+  TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
+  TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
+  CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698),
+  CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+  TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
+  TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+  TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+  TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+  TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+  TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+  TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+  CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125),
+  CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+  CHILD(1176),
+  BITFIELD(37, 2) /* index 513 */,
+  TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
+  BITFIELD(39, 2) /* index 518 */,
+  TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
+  BITFIELD(41, 2) /* index 523 */,
+  TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
+  BITFIELD(51, 2) /* index 528 */,
+  TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
+  BITFIELD(37, 2) /* index 533 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
+  BITFIELD(39, 2) /* index 538 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
+  BITFIELD(41, 2) /* index 543 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+  BITFIELD(31, 2) /* index 548 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
+  BITFIELD(33, 2) /* index 553 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
+  BITFIELD(35, 2) /* index 558 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
+  BITFIELD(37, 2) /* index 563 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
+  BITFIELD(39, 2) /* index 568 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
+  BITFIELD(41, 2) /* index 573 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+  BITFIELD(51, 2) /* index 578 */,
+  TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
+  BITFIELD(31, 2) /* index 583 */,
+  TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
+  BITFIELD(33, 2) /* index 588 */,
+  TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
+  BITFIELD(35, 2) /* index 593 */,
+  TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
+  TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
+  BITFIELD(51, 2) /* index 598 */,
+  CHILD(603), CHILD(618), CHILD(633), CHILD(648),
+  BITFIELD(31, 2) /* index 603 */,
+  TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
+  BITFIELD(33, 2) /* index 608 */,
+  TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
+  BITFIELD(35, 2) /* index 613 */,
+  TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
+  TILEGX_OPC_PREFETCH_ADD_L1,
+  BITFIELD(31, 2) /* index 618 */,
+  TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
+  BITFIELD(33, 2) /* index 623 */,
+  TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
+  BITFIELD(35, 2) /* index 628 */,
+  TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
+  TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
+  BITFIELD(31, 2) /* index 633 */,
+  TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
+  BITFIELD(33, 2) /* index 638 */,
+  TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
+  BITFIELD(35, 2) /* index 643 */,
+  TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
+  TILEGX_OPC_PREFETCH_ADD_L2,
+  BITFIELD(31, 2) /* index 648 */,
+  TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653),
+  BITFIELD(33, 2) /* index 653 */,
+  TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658),
+  BITFIELD(35, 2) /* index 658 */,
+  TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
+  TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
+  BITFIELD(51, 2) /* index 663 */,
+  CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
+  TILEGX_OPC_LDNT2S_ADD,
+  BITFIELD(31, 2) /* index 668 */,
+  TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673),
+  BITFIELD(33, 2) /* index 673 */,
+  TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678),
+  BITFIELD(35, 2) /* index 678 */,
+  TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
+  TILEGX_OPC_PREFETCH_ADD_L3,
+  BITFIELD(51, 2) /* index 683 */,
+  TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
+  TILEGX_OPC_LDNT_ADD,
+  BITFIELD(51, 2) /* index 688 */,
+  TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
+  BITFIELD(51, 2) /* index 693 */,
+  TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
+  BITFIELD(51, 2) /* index 698 */,
+  TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
+  TILEGX_OPC_STNT_ADD,
+  BITFIELD(51, 2) /* index 703 */,
+  TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
+  TILEGX_OPC_V1CMPLTSI,
+  BITFIELD(51, 2) /* index 708 */,
+  TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
+  TILEGX_OPC_V2ADDI,
+  BITFIELD(51, 2) /* index 713 */,
+  TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
+  TILEGX_OPC_V2MAXSI,
+  BITFIELD(51, 2) /* index 718 */,
+  TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(49, 4) /* index 723 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
+  TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
+  TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+  TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
+  TILEGX_OPC_DBLALIGN6,
+  BITFIELD(49, 4) /* index 740 */,
+  TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
+  TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
+  TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
+  TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
+  CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
+  BITFIELD(43, 2) /* index 757 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762),
+  BITFIELD(45, 2) /* index 762 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767),
+  BITFIELD(47, 2) /* index 767 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+  BITFIELD(49, 4) /* index 772 */,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
+  TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
+  TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
+  TILEGX_OPC_STNT4,
+  BITFIELD(46, 7) /* index 789 */,
+  TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
+  TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
+  TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
+  TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
+  TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
+  TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
+  TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
+  TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
+  TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
+  TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927),
+  CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
+  TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
+  TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
+  TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
+  TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
+  TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
+  TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
+  TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
+  TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
+  TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
+  TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
+  TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
+  TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
+  TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
+  TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
+  TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
+  TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
+  TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
+  TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
+  TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
+  TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
+  TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
+  TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
+  TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
+  TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
+  TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
+  BITFIELD(43, 3) /* index 918 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
+  TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
+  BITFIELD(43, 3) /* index 927 */,
+  CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
+  TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991),
+  BITFIELD(31, 2) /* index 936 */,
+  CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(33, 2) /* index 941 */,
+  TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946),
+  BITFIELD(35, 2) /* index 946 */,
+  TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(37, 2) /* index 951 */,
+  TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(39, 2) /* index 956 */,
+  TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(41, 2) /* index 961 */,
+  TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
+  BITFIELD(33, 2) /* index 966 */,
+  TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971),
+  BITFIELD(35, 2) /* index 971 */,
+  TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(37, 2) /* index 976 */,
+  TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(39, 2) /* index 981 */,
+  TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+  BITFIELD(41, 2) /* index 986 */,
+  TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
+  BITFIELD(31, 2) /* index 991 */,
+  TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996),
+  BITFIELD(33, 2) /* index 996 */,
+  TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001),
+  BITFIELD(35, 2) /* index 1001 */,
+  TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
+  TILEGX_OPC_PREFETCH_L1_FAULT,
+  BITFIELD(43, 3) /* index 1006 */,
+  CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075),
+  TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
+  BITFIELD(31, 2) /* index 1015 */,
+  TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020),
+  BITFIELD(33, 2) /* index 1020 */,
+  TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025),
+  BITFIELD(35, 2) /* index 1025 */,
+  TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
+  BITFIELD(31, 2) /* index 1030 */,
+  TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035),
+  BITFIELD(33, 2) /* index 1035 */,
+  TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040),
+  BITFIELD(35, 2) /* index 1040 */,
+  TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
+  TILEGX_OPC_PREFETCH_L2_FAULT,
+  BITFIELD(31, 2) /* index 1045 */,
+  TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050),
+  BITFIELD(33, 2) /* index 1050 */,
+  TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055),
+  BITFIELD(35, 2) /* index 1055 */,
+  TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
+  BITFIELD(31, 2) /* index 1060 */,
+  TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065),
+  BITFIELD(33, 2) /* index 1065 */,
+  TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070),
+  BITFIELD(35, 2) /* index 1070 */,
+  TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
+  TILEGX_OPC_PREFETCH_L3_FAULT,
+  BITFIELD(31, 2) /* index 1075 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080),
+  BITFIELD(33, 2) /* index 1080 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085),
+  BITFIELD(35, 2) /* index 1085 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
+  BITFIELD(43, 3) /* index 1090 */,
+  TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
+  TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
+  BITFIELD(43, 3) /* index 1099 */,
+  TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
+  TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
+  BITFIELD(49, 4) /* index 1108 */,
+  TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
+  TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
+  TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
+  TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
+  TILEGX_OPC_V2CMPLTU,
+  BITFIELD(49, 4) /* index 1125 */,
+  TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
+  TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
+  TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
+  TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
+  TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
+  BITFIELD(49, 4) /* index 1142 */,
+  TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
+  TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
+  TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
+  TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(49, 4) /* index 1159 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
+  TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
+  TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
+  TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE,
+  BITFIELD(31, 2) /* index 1176 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(1181),
+  BITFIELD(33, 2) /* index 1181 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(1186),
+  BITFIELD(35, 2) /* index 1186 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(1191),
+  BITFIELD(37, 2) /* index 1191 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(1196),
+  BITFIELD(39, 2) /* index 1196 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  CHILD(1201),
+  BITFIELD(41, 2) /* index 1201 */,
+  TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+  TILEGX_OPC_INFOL,
+};
+
+static const unsigned short decode_Y0_fsm[178] =
+{
+  BITFIELD(27, 4) /* index 0 */,
+  CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
+  TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
+  CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
+  CHILD(173),
+  BITFIELD(6, 2) /* index 17 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
+  BITFIELD(8, 2) /* index 22 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
+  BITFIELD(10, 2) /* index 27 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+  BITFIELD(0, 2) /* index 32 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
+  BITFIELD(2, 2) /* index 37 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
+  BITFIELD(4, 2) /* index 42 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
+  BITFIELD(6, 2) /* index 47 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
+  BITFIELD(8, 2) /* index 52 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
+  BITFIELD(10, 2) /* index 57 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+  BITFIELD(18, 2) /* index 62 */,
+  TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
+  BITFIELD(15, 5) /* index 67 */,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
+  TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
+  TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
+  CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(12, 3) /* index 100 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
+  TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
+  TILEGX_OPC_REVBITS,
+  BITFIELD(12, 3) /* index 109 */,
+  TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
+  TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  TILEGX_OPC_NONE,
+  BITFIELD(18, 2) /* index 118 */,
+  TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+  BITFIELD(18, 2) /* index 123 */,
+  TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
+  BITFIELD(18, 2) /* index 128 */,
+  TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
+  BITFIELD(18, 2) /* index 133 */,
+  TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
+  BITFIELD(12, 2) /* index 138 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
+  BITFIELD(14, 2) /* index 143 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
+  BITFIELD(16, 2) /* index 148 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+  BITFIELD(18, 2) /* index 153 */,
+  TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
+  BITFIELD(18, 2) /* index 158 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
+  TILEGX_OPC_SHL3ADDX,
+  BITFIELD(18, 2) /* index 163 */,
+  TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
+  TILEGX_OPC_MUL_LU_LU,
+  BITFIELD(18, 2) /* index 168 */,
+  TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
+  TILEGX_OPC_MULA_LU_LU,
+  BITFIELD(18, 2) /* index 173 */,
+  TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
+};
+
+static const unsigned short decode_Y1_fsm[167] =
+{
+  BITFIELD(58, 4) /* index 0 */,
+  TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
+  TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
+  CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
+  BITFIELD(37, 2) /* index 17 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
+  BITFIELD(39, 2) /* index 22 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
+  BITFIELD(41, 2) /* index 27 */,
+  TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+  BITFIELD(31, 2) /* index 32 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
+  BITFIELD(33, 2) /* index 37 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
+  BITFIELD(35, 2) /* index 42 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
+  BITFIELD(37, 2) /* index 47 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
+  BITFIELD(39, 2) /* index 52 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
+  BITFIELD(41, 2) /* index 57 */,
+  TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+  BITFIELD(49, 2) /* index 62 */,
+  TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
+  BITFIELD(47, 4) /* index 67 */,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
+  TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
+  TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
+  TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+  BITFIELD(43, 3) /* index 84 */,
+  CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
+  CHILD(111), CHILD(114),
+  BITFIELD(46, 1) /* index 93 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
+  BITFIELD(46, 1) /* index 96 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_ILL,
+  BITFIELD(46, 1) /* index 99 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
+  BITFIELD(46, 1) /* index 102 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_JALR,
+  BITFIELD(46, 1) /* index 105 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_JRP,
+  BITFIELD(46, 1) /* index 108 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_JR,
+  BITFIELD(46, 1) /* index 111 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_LNK,
+  BITFIELD(46, 1) /* index 114 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_NOP,
+  BITFIELD(49, 2) /* index 117 */,
+  TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+  BITFIELD(49, 2) /* index 122 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
+  BITFIELD(49, 2) /* index 127 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
+  BITFIELD(49, 2) /* index 132 */,
+  TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
+  BITFIELD(43, 2) /* index 137 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
+  BITFIELD(45, 2) /* index 142 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
+  BITFIELD(47, 2) /* index 147 */,
+  TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+  BITFIELD(49, 2) /* index 152 */,
+  TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
+  BITFIELD(49, 2) /* index 157 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
+  TILEGX_OPC_SHL3ADDX,
+  BITFIELD(49, 2) /* index 162 */,
+  TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
+};
+
+static const unsigned short decode_Y2_fsm[118] =
+{
+  BITFIELD(62, 2) /* index 0 */,
+  TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
+  BITFIELD(55, 3) /* index 5 */,
+  CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
+  CHILD(43),
+  BITFIELD(26, 1) /* index 14 */,
+  TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
+  BITFIELD(26, 1) /* index 17 */,
+  CHILD(20), CHILD(30),
+  BITFIELD(51, 2) /* index 20 */,
+  TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
+  BITFIELD(53, 2) /* index 25 */,
+  TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
+  TILEGX_OPC_PREFETCH_L1_FAULT,
+  BITFIELD(51, 2) /* index 30 */,
+  TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
+  BITFIELD(53, 2) /* index 35 */,
+  TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
+  BITFIELD(26, 1) /* index 40 */,
+  TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
+  BITFIELD(26, 1) /* index 43 */,
+  CHILD(46), CHILD(56),
+  BITFIELD(51, 2) /* index 46 */,
+  TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
+  BITFIELD(53, 2) /* index 51 */,
+  TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
+  TILEGX_OPC_PREFETCH_L2_FAULT,
+  BITFIELD(51, 2) /* index 56 */,
+  TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
+  BITFIELD(53, 2) /* index 61 */,
+  TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
+  BITFIELD(56, 2) /* index 66 */,
+  CHILD(71), CHILD(74), CHILD(90), CHILD(93),
+  BITFIELD(26, 1) /* index 71 */,
+  TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
+  BITFIELD(26, 1) /* index 74 */,
+  TILEGX_OPC_NONE, CHILD(77),
+  BITFIELD(51, 2) /* index 77 */,
+  TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
+  BITFIELD(53, 2) /* index 82 */,
+  TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
+  BITFIELD(55, 1) /* index 87 */,
+  TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
+  BITFIELD(26, 1) /* index 90 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_LD,
+  BITFIELD(26, 1) /* index 93 */,
+  CHILD(96), TILEGX_OPC_LD,
+  BITFIELD(51, 2) /* index 96 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
+  BITFIELD(53, 2) /* index 101 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
+  BITFIELD(55, 1) /* index 106 */,
+  TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
+  BITFIELD(26, 1) /* index 109 */,
+  CHILD(112), CHILD(115),
+  BITFIELD(57, 1) /* index 112 */,
+  TILEGX_OPC_ST1, TILEGX_OPC_ST4,
+  BITFIELD(57, 1) /* index 115 */,
+  TILEGX_OPC_ST2, TILEGX_OPC_ST,
+};
+
+#undef BITFIELD
+#undef CHILD
+const unsigned short * const
+tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
+{
+  decode_X0_fsm,
+  decode_X1_fsm,
+  decode_Y0_fsm,
+  decode_Y1_fsm,
+  decode_Y2_fsm
+};
+const struct tilegx_operand tilegx_operands[35] =
+{
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
+    8, 1, 0, 0, 0, 0,
+    create_Imm8_X0, get_Imm8_X0
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
+    8, 1, 0, 0, 0, 0,
+    create_Imm8_X1, get_Imm8_X1
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
+    8, 1, 0, 0, 0, 0,
+    create_Imm8_Y0, get_Imm8_Y0
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
+    8, 1, 0, 0, 0, 0,
+    create_Imm8_Y1, get_Imm8_Y1
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
+    16, 1, 0, 0, 0, 0,
+    create_Imm16_X0, get_Imm16_X0
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
+    16, 1, 0, 0, 0, 0,
+    create_Imm16_X1, get_Imm16_X1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 0, 1, 0, 0,
+    create_Dest_X0, get_Dest_X0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcA_X0, get_SrcA_X0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 0, 1, 0, 0,
+    create_Dest_X1, get_Dest_X1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcA_X1, get_SrcA_X1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 0, 1, 0, 0,
+    create_Dest_Y0, get_Dest_Y0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcA_Y0, get_SrcA_Y0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 0, 1, 0, 0,
+    create_Dest_Y1, get_Dest_Y1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcA_Y1, get_SrcA_Y1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcA_Y2, get_SrcA_Y2
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 1, 0, 0,
+    create_SrcA_X1, get_SrcA_X1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcB_X0, get_SrcB_X0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcB_X1, get_SrcB_X1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcB_Y0, get_SrcB_Y0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcB_Y1, get_SrcB_Y1
+  },
+  {
+    TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
+    17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
+    create_BrOff_X1, get_BrOff_X1
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
+    6, 0, 0, 0, 0, 0,
+    create_BFStart_X0, get_BFStart_X0
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
+    6, 0, 0, 0, 0, 0,
+    create_BFEnd_X0, get_BFEnd_X0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 1, 0, 0,
+    create_Dest_X0, get_Dest_X0
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 1, 0, 0,
+    create_Dest_Y0, get_Dest_Y0
+  },
+  {
+    TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
+    27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
+    create_JumpOff_X1, get_JumpOff_X1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 0, 1, 0, 0,
+    create_SrcBDest_Y2, get_SrcBDest_Y2
+  },
+  {
+    TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
+    14, 0, 0, 0, 0, 0,
+    create_MF_Imm14_X1, get_MF_Imm14_X1
+  },
+  {
+    TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
+    14, 0, 0, 0, 0, 0,
+    create_MT_Imm14_X1, get_MT_Imm14_X1
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
+    6, 0, 0, 0, 0, 0,
+    create_ShAmt_X0, get_ShAmt_X0
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
+    6, 0, 0, 0, 0, 0,
+    create_ShAmt_X1, get_ShAmt_X1
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
+    6, 0, 0, 0, 0, 0,
+    create_ShAmt_Y0, get_ShAmt_Y0
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
+    6, 0, 0, 0, 0, 0,
+    create_ShAmt_Y1, get_ShAmt_Y1
+  },
+  {
+    TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+    6, 0, 1, 0, 0, 0,
+    create_SrcBDest_Y2, get_SrcBDest_Y2
+  },
+  {
+    TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
+    8, 1, 0, 0, 0, 0,
+    create_Dest_Imm8_X1, get_Dest_Imm8_X1
+  }
+};
+
+
+
+
+/* Given a set of bundle bits and the lookup FSM for a specific pipe,
+ * returns which instruction the bundle contains in that pipe.
+ */
+static const struct tilegx_opcode *
+find_opcode(tilegx_bundle_bits bits, const unsigned short *table)
+{
+  int index = 0;
+
+  while (1)
+  {
+    unsigned short bitspec = table[index];
+    unsigned int bitfield =
+      ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
+
+    unsigned short next = table[index + 1 + bitfield];
+    if (next <= TILEGX_OPC_NONE)
+      return &tilegx_opcodes[next];
+
+    index = next - TILEGX_OPC_NONE;
+  }
+}
+
+
+int
+parse_insn_tilegx(tilegx_bundle_bits bits,
+                  unsigned long long pc,
+                  struct tilegx_decoded_instruction
+                  decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])
+{
+  int num_instructions = 0;
+  int pipe;
+
+  int min_pipe, max_pipe;
+  if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
+  {
+    min_pipe = TILEGX_PIPELINE_X0;
+    max_pipe = TILEGX_PIPELINE_X1;
+  }
+  else
+  {
+    min_pipe = TILEGX_PIPELINE_Y0;
+    max_pipe = TILEGX_PIPELINE_Y2;
+  }
+
+  /* For each pipe, find an instruction that fits. */
+  for (pipe = min_pipe; pipe <= max_pipe; pipe++)
+  {
+    const struct tilegx_opcode *opc;
+    struct tilegx_decoded_instruction *d;
+    int i;
+
+    d = &decoded[num_instructions++];
+    opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]);
+    d->opcode = opc;
+
+    /* Decode each operand, sign extending, etc. as appropriate. */
+    for (i = 0; i < opc->num_operands; i++)
+    {
+      const struct tilegx_operand *op =
+        &tilegx_operands[opc->operands[pipe][i]];
+      int raw_opval = op->extract (bits);
+      long long opval;
+
+      if (op->is_signed)
+      {
+        /* Sign-extend the operand. */
+        int shift = (int)((sizeof(int) * 8) - op->num_bits);
+        raw_opval = (raw_opval << shift) >> shift;
+      }
+
+      /* Adjust PC-relative scaled branch offsets. */
+      if (op->type == TILEGX_OP_TYPE_ADDRESS)
+        opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
+      else
+        opval = raw_opval;
+
+      /* Record the final value. */
+      d->operands[i] = op;
+      d->operand_values[i] = opval;
+    }
+  }
+
+  return num_instructions;
+}
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index 49a605be94c5..c4be58cc5d50 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -22,6 +22,7 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/delay.h>
+#include <linux/module.h>
 #include <asm/irq_regs.h>
 #include <asm/traps.h>
 #include <hv/hypervisor.h>
@@ -56,6 +57,7 @@ cycles_t get_cycles(void)
 
         return (((cycles_t)high) << 32) | low;
 }
+EXPORT_SYMBOL(get_cycles);
 #endif
 
 /*
diff --git a/arch/tile/kernel/tlb.c b/arch/tile/kernel/tlb.c
index 2dffc1044d83..a5f241c24cac 100644
--- a/arch/tile/kernel/tlb.c
+++ b/arch/tile/kernel/tlb.c
@@ -34,13 +34,13 @@ void flush_tlb_mm(struct mm_struct *mm)
 {
         HV_Remote_ASID asids[NR_CPUS];
         int i = 0, cpu;
-        for_each_cpu(cpu, &mm->cpu_vm_mask) {
+        for_each_cpu(cpu, mm_cpumask(mm)) {
                 HV_Remote_ASID *asid = &asids[i++];
                 asid->y = cpu / smp_topology.width;
                 asid->x = cpu % smp_topology.width;
                 asid->asid = per_cpu(current_asid, cpu);
         }
-        flush_remote(0, HV_FLUSH_EVICT_L1I, &mm->cpu_vm_mask,
+        flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(mm),
                      0, 0, 0, NULL, asids, i);
 }
 
@@ -54,8 +54,8 @@ void flush_tlb_page_mm(const struct vm_area_struct *vma, struct mm_struct *mm,
 {
         unsigned long size = hv_page_size(vma);
         int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
-        flush_remote(0, cache, &mm->cpu_vm_mask,
-                     va, size, size, &mm->cpu_vm_mask, NULL, 0);
+        flush_remote(0, cache, mm_cpumask(mm),
+                     va, size, size, mm_cpumask(mm), NULL, 0);
 }
 
 void flush_tlb_page(const struct vm_area_struct *vma, unsigned long va)
@@ -70,8 +70,8 @@ void flush_tlb_range(const struct vm_area_struct *vma,
         unsigned long size = hv_page_size(vma);
         struct mm_struct *mm = vma->vm_mm;
         int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
-        flush_remote(0, cache, &mm->cpu_vm_mask, start, end - start, size,
-                     &mm->cpu_vm_mask, NULL, 0);
+        flush_remote(0, cache, mm_cpumask(mm), start, end - start, size,
+                     mm_cpumask(mm), NULL, 0);
 }
 
 void flush_tlb_all(void)
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
index 5474fc2e77e8..f9803dfa7357 100644
--- a/arch/tile/kernel/traps.c
+++ b/arch/tile/kernel/traps.c
@@ -308,6 +308,7 @@ void __kprobes do_trap(struct pt_regs *regs, int fault_num,
         info.si_addr = (void __user *)address;
         if (signo == SIGILL)
                 info.si_trapno = fault_num;
+        trace_unhandled_signal("trap", regs, address, signo);
         force_sig_info(signo, &info, current);
 }
 
diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S
index 38f64fafdc10..631f10de12fe 100644
--- a/arch/tile/kernel/vmlinux.lds.S
+++ b/arch/tile/kernel/vmlinux.lds.S
@@ -60,7 +60,7 @@ SECTIONS
   . = ALIGN(PAGE_SIZE);
   VMLINUX_SYMBOL(_sinitdata) = .;
   INIT_DATA_SECTION(16) :data =0
-  PERCPU(L2_CACHE_BYTES, PAGE_SIZE)
+  PERCPU_SECTION(L2_CACHE_BYTES)
   . = ALIGN(PAGE_SIZE);
   VMLINUX_SYMBOL(_einitdata) = .;
 
diff --git a/arch/tile/lib/atomic_asm_32.S b/arch/tile/lib/atomic_asm_32.S
index 82f64cc63658..24448734f6f1 100644
--- a/arch/tile/lib/atomic_asm_32.S
+++ b/arch/tile/lib/atomic_asm_32.S
@@ -59,7 +59,7 @@
  * bad kernel addresses).
  *
  * Note that if the value we would store is the same as what we
- * loaded, we bypass the load.  Other platforms with true atomics can
+ * loaded, we bypass the store.  Other platforms with true atomics can
  * make the guarantee that a non-atomic __clear_bit(), for example,
  * can safely race with an atomic test_and_set_bit(); this example is
  * from bit_spinlock.h in slub_lock() / slub_unlock().  We can't do
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index 35c1d8ca5f38..8928aace7a64 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -15,6 +15,7 @@
 #include <asm/page.h>
 #include <asm/cacheflush.h>
 #include <arch/icache.h>
+#include <arch/spr_def.h>
 
 
 void __flush_icache_range(unsigned long start, unsigned long end)
@@ -39,6 +40,18 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
         char *p, *base;
         size_t step_size, load_count;
         const unsigned long STRIPE_WIDTH = 8192;
+#ifdef __tilegx__
+        /*
+         * On TILE-Gx, we must disable the dstream prefetcher before doing
+         * a cache flush; otherwise, we could end up with data in the cache
+         * that we don't want there.  Note that normally we'd do an mf
+         * after the SPR write to disabling the prefetcher, but we do one
+         * below, before any further loads, so there's no need to do it
+         * here.
+         */
+        uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
+        __insn_mtspr(SPR_DSTREAM_PF, 0);
+#endif
 
         /*
          * Flush and invalidate the buffer out of the local L1/L2
@@ -122,4 +135,9 @@ void finv_buffer_remote(void *buffer, size_t size, int hfh)
 
         /* Wait for the load+inv's (and thus finvs) to have completed. */
         __insn_mf();
+
+#ifdef __tilegx__
+        /* Reenable the prefetcher. */
+        __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
+#endif
 }
diff --git a/arch/tile/lib/memchr_64.c b/arch/tile/lib/memchr_64.c
new file mode 100644
index 000000000000..84fdc8d8e735
--- /dev/null
+++ b/arch/tile/lib/memchr_64.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+void *memchr(const void *s, int c, size_t n)
+{
+        const uint64_t *last_word_ptr;
+        const uint64_t *p;
+        const char *last_byte_ptr;
+        uintptr_t s_int;
+        uint64_t goal, before_mask, v, bits;
+        char *ret;
+
+        if (__builtin_expect(n == 0, 0)) {
+                /* Don't dereference any memory if the array is empty. */
+                return NULL;
+        }
+
+        /* Get an aligned pointer. */
+        s_int = (uintptr_t) s;
+        p = (const uint64_t *)(s_int & -8);
+
+        /* Create eight copies of the byte for which we are looking. */
+        goal = 0x0101010101010101ULL * (uint8_t) c;
+
+        /* Read the first word, but munge it so that bytes before the array
+         * will not match goal.
+         *
+         * Note that this shift count expression works because we know
+         * shift counts are taken mod 64.
+         */
+        before_mask = (1ULL << (s_int << 3)) - 1;
+        v = (*p | before_mask) ^ (goal & before_mask);
+
+        /* Compute the address of the last byte. */
+        last_byte_ptr = (const char *)s + n - 1;
+
+        /* Compute the address of the word containing the last byte. */
+        last_word_ptr = (const uint64_t *)((uintptr_t) last_byte_ptr & -8);
+
+        while ((bits = __insn_v1cmpeq(v, goal)) == 0) {
+                if (__builtin_expect(p == last_word_ptr, 0)) {
+                        /* We already read the last word in the array,
+                         * so give up.
+                         */
+                        return NULL;
+                }
+                v = *++p;
+        }
+
+        /* We found a match, but it might be in a byte past the end
+         * of the array.
+         */
+        ret = ((char *)p) + (__insn_ctz(bits) >> 3);
+        return (ret <= last_byte_ptr) ? ret : NULL;
+}
+EXPORT_SYMBOL(memchr);
diff --git a/arch/tile/lib/memcpy_64.c b/arch/tile/lib/memcpy_64.c
new file mode 100644
index 000000000000..3fab9a6a2bbe
--- /dev/null
+++ b/arch/tile/lib/memcpy_64.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#define __memcpy memcpy
+/* EXPORT_SYMBOL() is in arch/tile/lib/exports.c since this should be asm. */
+
+/* Must be 8 bytes in size. */
+#define word_t uint64_t
+
+#if CHIP_L2_LINE_SIZE() != 64 && CHIP_L2_LINE_SIZE() != 128
+#error "Assumes 64 or 128 byte line size"
+#endif
+
+/* How many cache lines ahead should we prefetch? */
+#define PREFETCH_LINES_AHEAD 3
+
+/*
+ * Provide "base versions" of load and store for the normal code path.
+ * The kernel provides other versions for userspace copies.
+ */
+#define ST(p, v) (*(p) = (v))
+#define LD(p) (*(p))
+
+#ifndef USERCOPY_FUNC
+#define ST1 ST
+#define ST2 ST
+#define ST4 ST
+#define ST8 ST
+#define LD1 LD
+#define LD2 LD
+#define LD4 LD
+#define LD8 LD
+#define RETVAL dstv
+void *memcpy(void *__restrict dstv, const void *__restrict srcv, size_t n)
+#else
+/*
+ * Special kernel version will provide implementation of the LDn/STn
+ * macros to return a count of uncopied bytes due to mm fault.
+ */
+#define RETVAL 0
+int USERCOPY_FUNC(void *__restrict dstv, const void *__restrict srcv, size_t n)
+#endif
+{
+        char *__restrict dst1 = (char *)dstv;
+        const char *__restrict src1 = (const char *)srcv;
+        const char *__restrict src1_end;
+        const char *__restrict prefetch;
+        word_t *__restrict dst8;    /* 8-byte pointer to destination memory. */
+        word_t final; /* Final bytes to write to trailing word, if any */
+        long i;
+
+        if (n < 16) {
+                for (; n; n--)
+                        ST1(dst1++, LD1(src1++));
+                return RETVAL;
+        }
+
+        /*
+         * Locate the end of source memory we will copy.  Don't
+         * prefetch past this.
+         */
+        src1_end = src1 + n - 1;
+
+        /* Prefetch ahead a few cache lines, but not past the end. */
+        prefetch = src1;
+        for (i = 0; i < PREFETCH_LINES_AHEAD; i++) {
+                __insn_prefetch(prefetch);
+                prefetch += CHIP_L2_LINE_SIZE();
+                prefetch = (prefetch > src1_end) ? prefetch : src1;
+        }
+
+        /* Copy bytes until dst is word-aligned. */
+        for (; (uintptr_t)dst1 & (sizeof(word_t) - 1); n--)
+                ST1(dst1++, LD1(src1++));
+
+        /* 8-byte pointer to destination memory. */
+        dst8 = (word_t *)dst1;
+
+        if (__builtin_expect((uintptr_t)src1 & (sizeof(word_t) - 1), 0)) {
+                /*
+                 * Misaligned copy.  Copy 8 bytes at a time, but don't
+                 * bother with other fanciness.
+                 *
+                 * TODO: Consider prefetching and using wh64 as well.
+                 */
+
+                /* Create an aligned src8. */
+                const word_t *__restrict src8 =
+                        (const word_t *)((uintptr_t)src1 & -sizeof(word_t));
+                word_t b;
+
+                word_t a = LD8(src8++);
+                for (; n >= sizeof(word_t); n -= sizeof(word_t)) {
+                        b = LD8(src8++);
+                        a = __insn_dblalign(a, b, src1);
+                        ST8(dst8++, a);
+                        a = b;
+                }
+
+                if (n == 0)
+                        return RETVAL;
+
+                b = ((const char *)src8 <= src1_end) ? *src8 : 0;
+
+                /*
+                 * Final source bytes to write to trailing partial
+                 * word, if any.
+                 */
+                final = __insn_dblalign(a, b, src1);
+        } else {
+                /* Aligned copy. */
+
+                const word_t* __restrict src8 = (const word_t *)src1;
+
+                /* src8 and dst8 are both word-aligned. */
+                if (n >= CHIP_L2_LINE_SIZE()) {
+                        /* Copy until 'dst' is cache-line-aligned. */
+                        for (; (uintptr_t)dst8 & (CHIP_L2_LINE_SIZE() - 1);
+                             n -= sizeof(word_t))
+                                ST8(dst8++, LD8(src8++));
+
+                        for (; n >= CHIP_L2_LINE_SIZE(); ) {
+                                __insn_wh64(dst8);
+
+                                /*
+                                 * Prefetch and advance to next line
+                                 * to prefetch, but don't go past the end
+                                 */
+                                __insn_prefetch(prefetch);
+                                prefetch += CHIP_L2_LINE_SIZE();
+                                prefetch = (prefetch > src1_end) ? prefetch :
+                                        (const char *)src8;
+
+                                /*
+                                 * Copy an entire cache line.  Manually
+                                 * unrolled to avoid idiosyncracies of
+                                 * compiler unrolling.
+                                 */
+#define COPY_WORD(offset) ({ ST8(dst8+offset, LD8(src8+offset)); n -= 8; })
+                                COPY_WORD(0);
+                                COPY_WORD(1);
+                                COPY_WORD(2);
+                                COPY_WORD(3);
+                                COPY_WORD(4);
+                                COPY_WORD(5);
+                                COPY_WORD(6);
+                                COPY_WORD(7);
+#if CHIP_L2_LINE_SIZE() == 128
+                                COPY_WORD(8);
+                                COPY_WORD(9);
+                                COPY_WORD(10);
+                                COPY_WORD(11);
+                                COPY_WORD(12);
+                                COPY_WORD(13);
+                                COPY_WORD(14);
+                                COPY_WORD(15);
+#elif CHIP_L2_LINE_SIZE() != 64
+# error Fix code that assumes particular L2 cache line sizes
+#endif
+
+                                dst8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
+                                src8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
+                        }
+                }
+
+                for (; n >= sizeof(word_t); n -= sizeof(word_t))
+                        ST8(dst8++, LD8(src8++));
+
+                if (__builtin_expect(n == 0, 1))
+                        return RETVAL;
+
+                final = LD8(src8);
+        }
+
+        /* n != 0 if we get here.  Write out any trailing bytes. */
+        dst1 = (char *)dst8;
+        if (n & 4) {
+                ST4((uint32_t *)dst1, final);
+                dst1 += 4;
+                final >>= 32;
+                n &= 3;
+        }
+        if (n & 2) {
+                ST2((uint16_t *)dst1, final);
+                dst1 += 2;
+                final >>= 16;
+                n &= 1;
+        }
+        if (n)
+                ST1((uint8_t *)dst1, final);
+
+        return RETVAL;
+}
+
+
+#ifdef USERCOPY_FUNC
+#undef ST1
+#undef ST2
+#undef ST4
+#undef ST8
+#undef LD1
+#undef LD2
+#undef LD4
+#undef LD8
+#undef USERCOPY_FUNC
+#endif
diff --git a/arch/tile/lib/memcpy_user_64.c b/arch/tile/lib/memcpy_user_64.c
new file mode 100644
index 000000000000..4763b3aff1cc
--- /dev/null
+++ b/arch/tile/lib/memcpy_user_64.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * Do memcpy(), but trap and return "n" when a load or store faults.
+ *
+ * Note: this idiom only works when memcpy() compiles to a leaf function.
+ * If "sp" is updated during memcpy, the "jrp lr" will be incorrect.
+ *
+ * Also note that we are capturing "n" from the containing scope here.
+ */
+
+#define _ST(p, inst, v)                                         \
+        ({                                                      \
+                asm("1: " #inst " %0, %1;"                      \
+                    ".pushsection .coldtext.memcpy,\"ax\";"     \
+                    "2: { move r0, %2; jrp lr };"               \
+                    ".section __ex_table,\"a\";"                \
+                    ".quad 1b, 2b;"                             \
+                    ".popsection"                               \
+                    : "=m" (*(p)) : "r" (v), "r" (n));          \
+        })
+
+#define _LD(p, inst)                                            \
+        ({                                                      \
+                unsigned long __v;                              \
+                asm("1: " #inst " %0, %1;"                      \
+                    ".pushsection .coldtext.memcpy,\"ax\";"     \
+                    "2: { move r0, %2; jrp lr };"               \
+                    ".section __ex_table,\"a\";"                \
+                    ".quad 1b, 2b;"                             \
+                    ".popsection"                               \
+                    : "=r" (__v) : "m" (*(p)), "r" (n));        \
+                __v;                                            \
+        })
+
+#define USERCOPY_FUNC __copy_to_user_inatomic
+#define ST1(p, v) _ST((p), st1, (v))
+#define ST2(p, v) _ST((p), st2, (v))
+#define ST4(p, v) _ST((p), st4, (v))
+#define ST8(p, v) _ST((p), st, (v))
+#define LD1 LD
+#define LD2 LD
+#define LD4 LD
+#define LD8 LD
+#include "memcpy_64.c"
+
+#define USERCOPY_FUNC __copy_from_user_inatomic
+#define ST1 ST
+#define ST2 ST
+#define ST4 ST
+#define ST8 ST
+#define LD1(p) _LD((p), ld1u)
+#define LD2(p) _LD((p), ld2u)
+#define LD4(p) _LD((p), ld4u)
+#define LD8(p) _LD((p), ld)
+#include "memcpy_64.c"
+
+#define USERCOPY_FUNC __copy_in_user_inatomic
+#define ST1(p, v) _ST((p), st1, (v))
+#define ST2(p, v) _ST((p), st2, (v))
+#define ST4(p, v) _ST((p), st4, (v))
+#define ST8(p, v) _ST((p), st, (v))
+#define LD1(p) _LD((p), ld1u)
+#define LD2(p) _LD((p), ld2u)
+#define LD4(p) _LD((p), ld4u)
+#define LD8(p) _LD((p), ld)
+#include "memcpy_64.c"
+
+unsigned long __copy_from_user_zeroing(void *to, const void __user *from,
+                                       unsigned long n)
+{
+        unsigned long rc = __copy_from_user_inatomic(to, from, n);
+        if (unlikely(rc))
+                memset(to + n - rc, 0, rc);
+        return rc;
+}
diff --git a/arch/tile/lib/memset_64.c b/arch/tile/lib/memset_64.c
new file mode 100644
index 000000000000..3873085711d5
--- /dev/null
+++ b/arch/tile/lib/memset_64.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <arch/chip.h>
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#undef memset
+
+void *memset(void *s, int c, size_t n)
+{
+        uint64_t *out64;
+        int n64, to_align64;
+        uint64_t v64;
+        uint8_t *out8 = s;
+
+        /* Experimentation shows that a trivial tight loop is a win up until
+         * around a size of 20, where writing a word at a time starts to win.
+         */
+#define BYTE_CUTOFF 20
+
+#if BYTE_CUTOFF < 7
+        /* This must be at least at least this big, or some code later
+         * on doesn't work.
+         */
+#error "BYTE_CUTOFF is too small"
+#endif
+
+        if (n < BYTE_CUTOFF) {
+                /* Strangely, this turns out to be the tightest way to
+                 * write this loop.
+                 */
+                if (n != 0) {
+                        do {
+                                /* Strangely, combining these into one line
+                                 * performs worse.
+                                 */
+                                *out8 = c;
+                                out8++;
+                        } while (--n != 0);
+                }
+
+                return s;
+        }
+
+        /* Align 'out8'. We know n >= 7 so this won't write past the end. */
+        while (((uintptr_t) out8 & 7) != 0) {
+                *out8++ = c;
+                --n;
+        }
+
+        /* Align 'n'. */
+        while (n & 7)
+                out8[--n] = c;
+
+        out64 = (uint64_t *) out8;
+        n64 = n >> 3;
+
+        /* Tile input byte out to 64 bits. */
+        /* KLUDGE */
+        v64 = 0x0101010101010101ULL * (uint8_t)c;
+
+        /* This must be at least 8 or the following loop doesn't work. */
+#define CACHE_LINE_SIZE_IN_DOUBLEWORDS (CHIP_L2_LINE_SIZE() / 8)
+
+        /* Determine how many words we need to emit before the 'out32'
+         * pointer becomes aligned modulo the cache line size.
+         */
+        to_align64 = (-((uintptr_t)out64 >> 3)) &
+                (CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1);
+
+        /* Only bother aligning and using wh64 if there is at least
+         * one full cache line to process.  This check also prevents
+         * overrunning the end of the buffer with alignment words.
+         */
+        if (to_align64 <= n64 - CACHE_LINE_SIZE_IN_DOUBLEWORDS) {
+                int lines_left;
+
+                /* Align out64 mod the cache line size so we can use wh64. */
+                n64 -= to_align64;
+                for (; to_align64 != 0; to_align64--) {
+                        *out64 = v64;
+                        out64++;
+                }
+
+                /* Use unsigned divide to turn this into a right shift. */
+                lines_left = (unsigned)n64 / CACHE_LINE_SIZE_IN_DOUBLEWORDS;
+
+                do {
+                        /* Only wh64 a few lines at a time, so we don't
+                         * exceed the maximum number of victim lines.
+                         */
+                        int x = ((lines_left < CHIP_MAX_OUTSTANDING_VICTIMS())
+                                  ? lines_left
+                                  : CHIP_MAX_OUTSTANDING_VICTIMS());
+                        uint64_t *wh = out64;
+                        int i = x;
+                        int j;
+
+                        lines_left -= x;
+
+                        do {
+                                __insn_wh64(wh);
+                                wh += CACHE_LINE_SIZE_IN_DOUBLEWORDS;
+                        } while (--i);
+
+                        for (j = x * (CACHE_LINE_SIZE_IN_DOUBLEWORDS / 4);
+                             j != 0; j--) {
+                                *out64++ = v64;
+                                *out64++ = v64;
+                                *out64++ = v64;
+                                *out64++ = v64;
+                        }
+                } while (lines_left != 0);
+
+                /* We processed all full lines above, so only this many
+                 * words remain to be processed.
+                 */
+                n64 &= CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1;
+        }
+
+        /* Now handle any leftover values. */
+        if (n64 != 0) {
+                do {
+                        *out64 = v64;
+                        out64++;
+                } while (--n64 != 0);
+        }
+
+        return s;
+}
+EXPORT_SYMBOL(memset);
diff --git a/arch/tile/lib/spinlock_64.c b/arch/tile/lib/spinlock_64.c
new file mode 100644
index 000000000000..d6fb9581e980
--- /dev/null
+++ b/arch/tile/lib/spinlock_64.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <asm/processor.h>
+
+#include "spinlock_common.h"
+
+/*
+ * Read the spinlock value without allocating in our cache and without
+ * causing an invalidation to another cpu with a copy of the cacheline.
+ * This is important when we are spinning waiting for the lock.
+ */
+static inline u32 arch_spin_read_noalloc(void *lock)
+{
+        return atomic_cmpxchg((atomic_t *)lock, -1, -1);
+}
+
+/*
+ * Wait until the high bits (current) match my ticket.
+ * If we notice the overflow bit set on entry, we clear it.
+ */
+void arch_spin_lock_slow(arch_spinlock_t *lock, u32 my_ticket)
+{
+        if (unlikely(my_ticket & __ARCH_SPIN_NEXT_OVERFLOW)) {
+                __insn_fetchand4(&lock->lock, ~__ARCH_SPIN_NEXT_OVERFLOW);
+                my_ticket &= ~__ARCH_SPIN_NEXT_OVERFLOW;
+        }
+
+        for (;;) {
+                u32 val = arch_spin_read_noalloc(lock);
+                u32 delta = my_ticket - arch_spin_current(val);
+                if (delta == 0)
+                        return;
+                relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
+        }
+}
+EXPORT_SYMBOL(arch_spin_lock_slow);
+
+/*
+ * Check the lock to see if it is plausible, and try to get it with cmpxchg().
+ */
+int arch_spin_trylock(arch_spinlock_t *lock)
+{
+        u32 val = arch_spin_read_noalloc(lock);
+        if (unlikely(arch_spin_current(val) != arch_spin_next(val)))
+                return 0;
+        return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW)
+                == val;
+}
+EXPORT_SYMBOL(arch_spin_trylock);
+
+void arch_spin_unlock_wait(arch_spinlock_t *lock)
+{
+        u32 iterations = 0;
+        while (arch_spin_is_locked(lock))
+                delay_backoff(iterations++);
+}
+EXPORT_SYMBOL(arch_spin_unlock_wait);
+
+/*
+ * If the read lock fails due to a writer, we retry periodically
+ * until the value is positive and we write our incremented reader count.
+ */
+void __read_lock_failed(arch_rwlock_t *rw)
+{
+        u32 val;
+        int iterations = 0;
+        do {
+                delay_backoff(iterations++);
+                val = __insn_fetchaddgez4(&rw->lock, 1);
+        } while (unlikely(arch_write_val_locked(val)));
+}
+EXPORT_SYMBOL(__read_lock_failed);
+
+/*
+ * If we failed because there were readers, clear the "writer" bit
+ * so we don't block additional readers.  Otherwise, there was another
+ * writer anyway, so our "fetchor" made no difference.  Then wait,
+ * issuing periodic fetchor instructions, till we get the lock.
+ */
+void __write_lock_failed(arch_rwlock_t *rw, u32 val)
+{
+        int iterations = 0;
+        do {
+                if (!arch_write_val_locked(val))
+                        val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
+                delay_backoff(iterations++);
+                val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
+        } while (val != 0);
+}
+EXPORT_SYMBOL(__write_lock_failed);
diff --git a/arch/tile/lib/strchr_64.c b/arch/tile/lib/strchr_64.c
new file mode 100644
index 000000000000..617a9273aaa8
--- /dev/null
+++ b/arch/tile/lib/strchr_64.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#undef strchr
+
+char *strchr(const char *s, int c)
+{
+        int z, g;
+
+        /* Get an aligned pointer. */
+        const uintptr_t s_int = (uintptr_t) s;
+        const uint64_t *p = (const uint64_t *)(s_int & -8);
+
+        /* Create eight copies of the byte for which we are looking. */
+        const uint64_t goal = 0x0101010101010101ULL * (uint8_t) c;
+
+        /* Read the first aligned word, but force bytes before the string to
+         * match neither zero nor goal (we make sure the high bit of each
+         * byte is 1, and the low 7 bits are all the opposite of the goal
+         * byte).
+         *
+         * Note that this shift count expression works because we know shift
+         * counts are taken mod 64.
+         */
+        const uint64_t before_mask = (1ULL << (s_int << 3)) - 1;
+        uint64_t v = (*p | before_mask) ^
+                (goal & __insn_v1shrsi(before_mask, 1));
+
+        uint64_t zero_matches, goal_matches;
+        while (1) {
+                /* Look for a terminating '\0'. */
+                zero_matches = __insn_v1cmpeqi(v, 0);
+
+                /* Look for the goal byte. */
+                goal_matches = __insn_v1cmpeq(v, goal);
+
+                if (__builtin_expect((zero_matches | goal_matches) != 0, 0))
+                        break;
+
+                v = *++p;
+        }
+
+        z = __insn_ctz(zero_matches);
+        g = __insn_ctz(goal_matches);
+
+        /* If we found c before '\0' we got a match. Note that if c == '\0'
+         * then g == z, and we correctly return the address of the '\0'
+         * rather than NULL.
+         */
+        return (g <= z) ? ((char *)p) + (g >> 3) : NULL;
+}
+EXPORT_SYMBOL(strchr);
diff --git a/arch/tile/lib/strlen_64.c b/arch/tile/lib/strlen_64.c
new file mode 100644
index 000000000000..1c92d46202a8
--- /dev/null
+++ b/arch/tile/lib/strlen_64.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#undef strlen
+
+size_t strlen(const char *s)
+{
+        /* Get an aligned pointer. */
+        const uintptr_t s_int = (uintptr_t) s;
+        const uint64_t *p = (const uint64_t *)(s_int & -8);
+
+        /* Read the first word, but force bytes before the string to be nonzero.
+         * This expression works because we know shift counts are taken mod 64.
+         */
+        uint64_t v = *p | ((1ULL << (s_int << 3)) - 1);
+
+        uint64_t bits;
+        while ((bits = __insn_v1cmpeqi(v, 0)) == 0)
+                v = *++p;
+
+        return ((const char *)p) + (__insn_ctz(bits) >> 3) - s;
+}
+EXPORT_SYMBOL(strlen);
diff --git a/arch/tile/lib/usercopy_64.S b/arch/tile/lib/usercopy_64.S
new file mode 100644
index 000000000000..2ff44f87b78e
--- /dev/null
+++ b/arch/tile/lib/usercopy_64.S
@@ -0,0 +1,196 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+#include <asm/cache.h>
+#include <arch/chip.h>
+
+/* Access user memory, but use MMU to avoid propagating kernel exceptions. */
+
+        .pushsection .fixup,"ax"
+
+get_user_fault:
+        { movei r1, -EFAULT; move r0, zero }
+        jrp lr
+        ENDPROC(get_user_fault)
+
+put_user_fault:
+        { movei r0, -EFAULT; jrp lr }
+        ENDPROC(put_user_fault)
+
+        .popsection
+
+/*
+ * __get_user_N functions take a pointer in r0, and return 0 in r1
+ * on success, with the value in r0; or else -EFAULT in r1.
+ */
+#define __get_user_N(bytes, LOAD) \
+        STD_ENTRY(__get_user_##bytes); \
+1:      { LOAD r0, r0; move r1, zero }; \
+        jrp lr; \
+        STD_ENDPROC(__get_user_##bytes); \
+        .pushsection __ex_table,"a"; \
+        .quad 1b, get_user_fault; \
+        .popsection
+
+__get_user_N(1, ld1u)
+__get_user_N(2, ld2u)
+__get_user_N(4, ld4u)
+__get_user_N(8, ld)
+
+/*
+ * __put_user_N functions take a value in r0 and a pointer in r1,
+ * and return 0 in r0 on success or -EFAULT on failure.
+ */
+#define __put_user_N(bytes, STORE) \
+        STD_ENTRY(__put_user_##bytes); \
+1:      { STORE r1, r0; move r0, zero }; \
+        jrp lr; \
+        STD_ENDPROC(__put_user_##bytes); \
+        .pushsection __ex_table,"a"; \
+        .quad 1b, put_user_fault; \
+        .popsection
+
+__put_user_N(1, st1)
+__put_user_N(2, st2)
+__put_user_N(4, st4)
+__put_user_N(8, st)
+
+/*
+ * strnlen_user_asm takes the pointer in r0, and the length bound in r1.
+ * It returns the length, including the terminating NUL, or zero on exception.
+ * If length is greater than the bound, returns one plus the bound.
+ */
+STD_ENTRY(strnlen_user_asm)
+        { beqz r1, 2f; addi r3, r0, -1 }  /* bias down to include NUL */
+1:      { ld1u r4, r0; addi r1, r1, -1 }
+        beqz r4, 2f
+        { bnezt r1, 1b; addi r0, r0, 1 }
+2:      { sub r0, r0, r3; jrp lr }
+        STD_ENDPROC(strnlen_user_asm)
+        .pushsection .fixup,"ax"
+strnlen_user_fault:
+        { move r0, zero; jrp lr }
+        ENDPROC(strnlen_user_fault)
+        .section __ex_table,"a"
+        .quad 1b, strnlen_user_fault
+        .popsection
+
+/*
+ * strncpy_from_user_asm takes the kernel target pointer in r0,
+ * the userspace source pointer in r1, and the length bound (including
+ * the trailing NUL) in r2.  On success, it returns the string length
+ * (not including the trailing NUL), or -EFAULT on failure.
+ */
+STD_ENTRY(strncpy_from_user_asm)
+        { beqz r2, 2f; move r3, r0 }
+1:      { ld1u r4, r1; addi r1, r1, 1; addi r2, r2, -1 }
+        { st1 r0, r4; addi r0, r0, 1 }
+        beqz r2, 2f
+        bnezt r4, 1b
+        addi r0, r0, -1   /* don't count the trailing NUL */
+2:      { sub r0, r0, r3; jrp lr }
+        STD_ENDPROC(strncpy_from_user_asm)
+        .pushsection .fixup,"ax"
+strncpy_from_user_fault:
+        { movei r0, -EFAULT; jrp lr }
+        ENDPROC(strncpy_from_user_fault)
+        .section __ex_table,"a"
+        .quad 1b, strncpy_from_user_fault
+        .popsection
+
+/*
+ * clear_user_asm takes the user target address in r0 and the
+ * number of bytes to zero in r1.
+ * It returns the number of uncopiable bytes (hopefully zero) in r0.
+ * Note that we don't use a separate .fixup section here since we fall
+ * through into the "fixup" code as the last straight-line bundle anyway.
+ */
+STD_ENTRY(clear_user_asm)
+        { beqz r1, 2f; or r2, r0, r1 }
+        andi r2, r2, 7
+        beqzt r2, .Lclear_aligned_user_asm
+1:      { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
+        bnezt r1, 1b
+2:      { move r0, r1; jrp lr }
+        .pushsection __ex_table,"a"
+        .quad 1b, 2b
+        .popsection
+
+.Lclear_aligned_user_asm:
+1:      { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
+        bnezt r1, 1b
+2:      { move r0, r1; jrp lr }
+        STD_ENDPROC(clear_user_asm)
+        .pushsection __ex_table,"a"
+        .quad 1b, 2b
+        .popsection
+
+/*
+ * flush_user_asm takes the user target address in r0 and the
+ * number of bytes to flush in r1.
+ * It returns the number of unflushable bytes (hopefully zero) in r0.
+ */
+STD_ENTRY(flush_user_asm)
+        beqz r1, 2f
+        { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
+        { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
+        { and r0, r0, r2; and r1, r1, r2 }
+        { sub r1, r1, r0 }
+1:      { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
+        { addi r0, r0, CHIP_FLUSH_STRIDE(); bnezt r1, 1b }
+2:      { move r0, r1; jrp lr }
+        STD_ENDPROC(flush_user_asm)
+        .pushsection __ex_table,"a"
+        .quad 1b, 2b
+        .popsection
+
+/*
+ * inv_user_asm takes the user target address in r0 and the
+ * number of bytes to invalidate in r1.
+ * It returns the number of not inv'able bytes (hopefully zero) in r0.
+ */
+STD_ENTRY(inv_user_asm)
+        beqz r1, 2f
+        { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
+        { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
+        { and r0, r0, r2; and r1, r1, r2 }
+        { sub r1, r1, r0 }
+1:      { inv r0; addi r1, r1, -CHIP_INV_STRIDE() }
+        { addi r0, r0, CHIP_INV_STRIDE(); bnezt r1, 1b }
+2:      { move r0, r1; jrp lr }
+        STD_ENDPROC(inv_user_asm)
+        .pushsection __ex_table,"a"
+        .quad 1b, 2b
+        .popsection
+
+/*
+ * finv_user_asm takes the user target address in r0 and the
+ * number of bytes to flush-invalidate in r1.
+ * It returns the number of not finv'able bytes (hopefully zero) in r0.
+ */
+STD_ENTRY(finv_user_asm)
+        beqz r1, 2f
+        { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
+        { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
+        { and r0, r0, r2; and r1, r1, r2 }
+        { sub r1, r1, r0 }
+1:      { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
+        { addi r0, r0, CHIP_FINV_STRIDE(); bnezt r1, 1b }
+2:      { move r0, r1; jrp lr }
+        STD_ENDPROC(finv_user_asm)
+        .pushsection __ex_table,"a"
+        .quad 1b, 2b
+        .popsection
diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c
index 51f8663bf074..25b7b90fd620 100644
--- a/arch/tile/mm/fault.c
+++ b/arch/tile/mm/fault.c
@@ -43,8 +43,11 @@
 
 #include <arch/interrupts.h>
 
-static noinline void force_sig_info_fault(int si_signo, int si_code,
-        unsigned long address, int fault_num, struct task_struct *tsk)
+static noinline void force_sig_info_fault(const char *type, int si_signo,
+                                          int si_code, unsigned long address,
+                                          int fault_num,
+                                          struct task_struct *tsk,
+                                          struct pt_regs *regs)
 {
         siginfo_t info;
 
@@ -59,6 +62,7 @@ static noinline void force_sig_info_fault(int si_signo, int si_code,
         info.si_code = si_code;
         info.si_addr = (void __user *)address;
         info.si_trapno = fault_num;
+        trace_unhandled_signal(type, regs, address, si_signo);
         force_sig_info(si_signo, &info, tsk);
 }
 
@@ -71,11 +75,12 @@ SYSCALL_DEFINE2(cmpxchg_badaddr, unsigned long, address,
                 struct pt_regs *, regs)
 {
         if (address >= PAGE_OFFSET)
-                force_sig_info_fault(SIGSEGV, SEGV_MAPERR, address,
-                                     INT_DTLB_MISS, current);
+                force_sig_info_fault("atomic segfault", SIGSEGV, SEGV_MAPERR,
+                                     address, INT_DTLB_MISS, current, regs);
         else
-                force_sig_info_fault(SIGBUS, BUS_ADRALN, address,
-                                     INT_UNALIGN_DATA, current);
+                force_sig_info_fault("atomic alignment fault", SIGBUS,
+                                     BUS_ADRALN, address,
+                                     INT_UNALIGN_DATA, current, regs);
 
         /*
          * Adjust pc to point at the actual instruction, which is unusual
@@ -471,8 +476,8 @@ bad_area_nosemaphore:
                  */
                 local_irq_enable();
 
-                force_sig_info_fault(SIGSEGV, si_code, address,
-                                     fault_num, tsk);
+                force_sig_info_fault("segfault", SIGSEGV, si_code, address,
+                                     fault_num, tsk, regs);
                 return 0;
         }
 
@@ -547,7 +552,8 @@ do_sigbus:
         if (is_kernel_mode)
                 goto no_context;
 
-        force_sig_info_fault(SIGBUS, BUS_ADRERR, address, fault_num, tsk);
+        force_sig_info_fault("bus error", SIGBUS, BUS_ADRERR, address,
+                             fault_num, tsk, regs);
         return 0;
 }
 
@@ -732,6 +738,7 @@ void do_page_fault(struct pt_regs *regs, int fault_num,
                 panic("Bad fault number %d in do_page_fault", fault_num);
         }
 
+#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
         if (EX1_PL(regs->ex1) != USER_PL) {
                 struct async_tlb *async;
                 switch (fault_num) {
@@ -775,6 +782,7 @@ void do_page_fault(struct pt_regs *regs, int fault_num,
                         return;
                 }
         }
+#endif
 
         handle_page_fault(regs, fault_num, is_page_fault, address, write);
 }
@@ -801,8 +809,6 @@ static void handle_async_page_fault(struct pt_regs *regs,
                                   async->address, async->is_write);
         }
 }
-#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
-
 
 /*
  * This routine effectively re-issues asynchronous page faults
@@ -824,6 +830,8 @@ void do_async_page_fault(struct pt_regs *regs)
         handle_async_page_fault(regs, &current->thread.sn_async_tlb);
 #endif
 }
+#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
+
 
 void vmalloc_sync_all(void)
 {
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index d6e87fda2fb2..4e10c4023028 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -60,8 +60,6 @@ unsigned long VMALLOC_RESERVE = CONFIG_VMALLOC_RESERVE;
 EXPORT_SYMBOL(VMALLOC_RESERVE);
 #endif
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /* Create an L2 page table */
 static pte_t * __init alloc_pte(void)
 {
diff --git a/arch/tile/mm/migrate_64.S b/arch/tile/mm/migrate_64.S
new file mode 100644
index 000000000000..e76fea688beb
--- /dev/null
+++ b/arch/tile/mm/migrate_64.S
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ *   This program is free software; you can redistribute it and/or
+ *   modify it under the terms of the GNU General Public License
+ *   as published by the Free Software Foundation, version 2.
+ *
+ *   This program is distributed in the hope that it will be useful, but
+ *   WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ *   NON INFRINGEMENT.  See the GNU General Public License for
+ *   more details.
+ *
+ * This routine is a helper for migrating the home of a set of pages to
+ * a new cpu.  See the documentation in homecache.c for more information.
+ */
+
+#include <linux/linkage.h>
+#include <linux/threads.h>
+#include <asm/page.h>
+#include <asm/thread_info.h>
+#include <asm/types.h>
+#include <asm/asm-offsets.h>
+#include <hv/hypervisor.h>
+
+        .text
+
+/*
+ * First, some definitions that apply to all the code in the file.
+ */
+
+/* Locals (caller-save) */
+#define r_tmp           r10
+#define r_save_sp       r11
+
+/* What we save where in the stack frame; must include all callee-saves. */
+#define FRAME_SP        8
+#define FRAME_R30       16
+#define FRAME_R31       24
+#define FRAME_R32       32
+#define FRAME_R33       40
+#define FRAME_SIZE      48
+
+
+
+
+/*
+ * On entry:
+ *
+ *   r0 the new context PA to install (moved to r_context)
+ *   r1 PTE to use for context access (moved to r_access)
+ *   r2 ASID to use for new context (moved to r_asid)
+ *   r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
+ */
+
+/* Arguments (caller-save) */
+#define r_context_in    r0
+#define r_access_in     r1
+#define r_asid_in       r2
+#define r_my_cpumask    r3
+
+/* Locals (callee-save); must not be more than FRAME_xxx above. */
+#define r_save_ics      r30
+#define r_context       r31
+#define r_access        r32
+#define r_asid          r33
+
+/*
+ * Caller-save locals and frame constants are the same as
+ * for homecache_migrate_stack_and_flush.
+ */
+
+STD_ENTRY(flush_and_install_context)
+        /*
+         * Create a stack frame; we can't touch it once we flush the
+         * cache until we install the new page table and flush the TLB.
+         */
+        {
+         move r_save_sp, sp
+         st sp, lr
+         addi sp, sp, -FRAME_SIZE
+        }
+        addi r_tmp, sp, FRAME_SP
+        {
+         st r_tmp, r_save_sp
+         addi r_tmp, sp, FRAME_R30
+        }
+        {
+         st r_tmp, r30
+         addi r_tmp, sp, FRAME_R31
+        }
+        {
+         st r_tmp, r31
+         addi r_tmp, sp, FRAME_R32
+        }
+        {
+         st r_tmp, r32
+         addi r_tmp, sp, FRAME_R33
+        }
+        st r_tmp, r33
+
+        /* Move some arguments to callee-save registers. */
+        {
+         move r_context, r_context_in
+         move r_access, r_access_in
+        }
+        move r_asid, r_asid_in
+
+        /* Disable interrupts, since we can't use our stack. */
+        {
+         mfspr r_save_ics, INTERRUPT_CRITICAL_SECTION
+         movei r_tmp, 1
+        }
+        mtspr INTERRUPT_CRITICAL_SECTION, r_tmp
+
+        /* First, flush our L2 cache. */
+        {
+         move r0, zero  /* cache_pa */
+         moveli r1, hw2_last(HV_FLUSH_EVICT_L2)  /* cache_control */
+        }
+        {
+         shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
+         move r2, r_my_cpumask  /* cache_cpumask */
+        }
+        {
+         shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
+         move r3, zero  /* tlb_va */
+        }
+        {
+         move r4, zero  /* tlb_length */
+         move r5, zero  /* tlb_pgsize */
+        }
+        {
+         move r6, zero  /* tlb_cpumask */
+         move r7, zero  /* asids */
+        }
+        {
+         move r8, zero  /* asidcount */
+         jal hv_flush_remote
+        }
+        bnez r0, 1f
+
+        /* Now install the new page table. */
+        {
+         move r0, r_context
+         move r1, r_access
+        }
+        {
+         move r2, r_asid
+         movei r3, HV_CTX_DIRECTIO
+        }
+        jal hv_install_context
+        bnez r0, 1f
+
+        /* Finally, flush the TLB. */
+        {
+         movei r0, 0   /* preserve_global */
+         jal hv_flush_all
+        }
+
+1:      /* Reset interrupts back how they were before. */
+        mtspr INTERRUPT_CRITICAL_SECTION, r_save_ics
+
+        /* Restore the callee-saved registers and return. */
+        addli lr, sp, FRAME_SIZE
+        {
+         ld lr, lr
+         addli r_tmp, sp, FRAME_R30
+        }
+        {
+         ld r30, r_tmp
+         addli r_tmp, sp, FRAME_R31
+        }
+        {
+         ld r31, r_tmp
+         addli r_tmp, sp, FRAME_R32
+        }
+        {
+         ld r32, r_tmp
+         addli r_tmp, sp, FRAME_R33
+        }
+        {
+         ld r33, r_tmp
+         addi sp, sp, FRAME_SIZE
+        }
+        jrp lr
+        STD_ENDPROC(flush_and_install_context)
diff --git a/arch/um/Kconfig.debug b/arch/um/Kconfig.debug
index 8fce5e536b0f..68205fd3b08c 100644
--- a/arch/um/Kconfig.debug
+++ b/arch/um/Kconfig.debug
@@ -28,13 +28,13 @@ config GCOV
           If you're involved in UML kernel development and want to use gcov,
           say Y.  If you're unsure, say N.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        default N
-        help
-          Track the maximum kernel stack usage - this will look at each
-          kernel stack at process exit and log it if it's the deepest
-          stack seen so far.
+config EARLY_PRINTK
+        bool "Early printk"
+        default y
+        ---help---
+          Write kernel log output directly to stdout.
+
+          This is useful for kernel debugging when your machine crashes very
+          early before the console code is initialized.
 
-          This option will slow down process creation and destruction somewhat.
 endmenu
diff --git a/arch/um/Kconfig.x86 b/arch/um/Kconfig.x86
index a9da516a5274..8aae429a56e2 100644
--- a/arch/um/Kconfig.x86
+++ b/arch/um/Kconfig.x86
@@ -15,7 +15,6 @@ endmenu
 config UML_X86
         def_bool y
         select GENERIC_FIND_FIRST_BIT
-        select GENERIC_FIND_NEXT_BIT
 
 config 64BIT
         bool
@@ -29,10 +28,10 @@ config X86_64
         def_bool 64BIT
 
 config RWSEM_XCHGADD_ALGORITHM
-        def_bool X86_XADD
+        def_bool X86_XADD && 64BIT
 
 config RWSEM_GENERIC_SPINLOCK
-        def_bool !X86_XADD
+        def_bool !RWSEM_XCHGADD_ALGORITHM
 
 config 3_LEVEL_PGTABLES
         bool "Three-level pagetables (EXPERIMENTAL)" if !64BIT
diff --git a/arch/um/drivers/Makefile b/arch/um/drivers/Makefile
index 1d9b6ae967b0..e7582e1d248c 100644
--- a/arch/um/drivers/Makefile
+++ b/arch/um/drivers/Makefile
@@ -9,7 +9,7 @@
 slip-objs := slip_kern.o slip_user.o
 slirp-objs := slirp_kern.o slirp_user.o
 daemon-objs := daemon_kern.o daemon_user.o
-mcast-objs := mcast_kern.o mcast_user.o
+umcast-objs := umcast_kern.o umcast_user.o
 net-objs := net_kern.o net_user.o
 mconsole-objs := mconsole_kern.o mconsole_user.o
 hostaudio-objs := hostaudio_kern.o
@@ -44,7 +44,7 @@ obj-$(CONFIG_UML_NET_SLIP) += slip.o slip_common.o
 obj-$(CONFIG_UML_NET_SLIRP) += slirp.o slip_common.o
 obj-$(CONFIG_UML_NET_DAEMON) += daemon.o 
 obj-$(CONFIG_UML_NET_VDE) += vde.o
-obj-$(CONFIG_UML_NET_MCAST) += mcast.o 
+obj-$(CONFIG_UML_NET_MCAST) += umcast.o
 obj-$(CONFIG_UML_NET_PCAP) += pcap.o
 obj-$(CONFIG_UML_NET) += net.o 
 obj-$(CONFIG_MCONSOLE) += mconsole.o
diff --git a/arch/um/drivers/mcast.h b/arch/um/drivers/mcast.h
deleted file mode 100644
index 6fa282e896be..000000000000
--- a/arch/um/drivers/mcast.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/* 
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __DRIVERS_MCAST_H
-#define __DRIVERS_MCAST_H
-
-#include "net_user.h"
-
-struct mcast_data {
-        char *addr;
-        unsigned short port;
-        void *mcast_addr;
-        int ttl;
-        void *dev;
-};
-
-extern const struct net_user_info mcast_user_info;
-
-extern int mcast_user_write(int fd, void *buf, int len, 
-                            struct mcast_data *pri);
-
-#endif
diff --git a/arch/um/drivers/mcast_kern.c b/arch/um/drivers/mcast_kern.c
deleted file mode 100644
index ffc6416d5ed7..000000000000
--- a/arch/um/drivers/mcast_kern.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * user-mode-linux networking multicast transport
- * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- *
- * based on the existing uml-networking code, which is
- * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
- * James Leu (jleu@mindspring.net).
- * Copyright (C) 2001 by various other people who didn't put their name here.
- *
- * Licensed under the GPL.
- */
-
-#include "linux/init.h"
-#include <linux/netdevice.h>
-#include "mcast.h"
-#include "net_kern.h"
-
-struct mcast_init {
-        char *addr;
-        int port;
-        int ttl;
-};
-
-static void mcast_init(struct net_device *dev, void *data)
-{
-        struct uml_net_private *pri;
-        struct mcast_data *dpri;
-        struct mcast_init *init = data;
-
-        pri = netdev_priv(dev);
-        dpri = (struct mcast_data *) pri->user;
-        dpri->addr = init->addr;
-        dpri->port = init->port;
-        dpri->ttl = init->ttl;
-        dpri->dev = dev;
-
-        printk("mcast backend multicast address: %s:%u, TTL:%u\n",
-               dpri->addr, dpri->port, dpri->ttl);
-}
-
-static int mcast_read(int fd, struct sk_buff *skb, struct uml_net_private *lp)
-{
-        return net_recvfrom(fd, skb_mac_header(skb),
-                            skb->dev->mtu + ETH_HEADER_OTHER);
-}
-
-static int mcast_write(int fd, struct sk_buff *skb, struct uml_net_private *lp)
-{
-        return mcast_user_write(fd, skb->data, skb->len,
-                                (struct mcast_data *) &lp->user);
-}
-
-static const struct net_kern_info mcast_kern_info = {
-        .init                   = mcast_init,
-        .protocol               = eth_protocol,
-        .read                   = mcast_read,
-        .write                  = mcast_write,
-};
-
-static int mcast_setup(char *str, char **mac_out, void *data)
-{
-        struct mcast_init *init = data;
-        char *port_str = NULL, *ttl_str = NULL, *remain;
-        char *last;
-
-        *init = ((struct mcast_init)
-                { .addr         = "239.192.168.1",
-                  .port         = 1102,
-                  .ttl          = 1 });
-
-        remain = split_if_spec(str, mac_out, &init->addr, &port_str, &ttl_str,
-                               NULL);
-        if (remain != NULL) {
-                printk(KERN_ERR "mcast_setup - Extra garbage on "
-                       "specification : '%s'\n", remain);
-                return 0;
-        }
-
-        if (port_str != NULL) {
-                init->port = simple_strtoul(port_str, &last, 10);
-                if ((*last != '\0') || (last == port_str)) {
-                        printk(KERN_ERR "mcast_setup - Bad port : '%s'\n",
-                               port_str);
-                        return 0;
-                }
-        }
-
-        if (ttl_str != NULL) {
-                init->ttl = simple_strtoul(ttl_str, &last, 10);
-                if ((*last != '\0') || (last == ttl_str)) {
-                        printk(KERN_ERR "mcast_setup - Bad ttl : '%s'\n",
-                               ttl_str);
-                        return 0;
-                }
-        }
-
-        printk(KERN_INFO "Configured mcast device: %s:%u-%u\n", init->addr,
-               init->port, init->ttl);
-
-        return 1;
-}
-
-static struct transport mcast_transport = {
-        .list           = LIST_HEAD_INIT(mcast_transport.list),
-        .name           = "mcast",
-        .setup          = mcast_setup,
-        .user           = &mcast_user_info,
-        .kern           = &mcast_kern_info,
-        .private_size   = sizeof(struct mcast_data),
-        .setup_size     = sizeof(struct mcast_init),
-};
-
-static int register_mcast(void)
-{
-        register_transport(&mcast_transport);
-        return 0;
-}
-
-late_initcall(register_mcast);
diff --git a/arch/um/drivers/mcast_user.c b/arch/um/drivers/mcast_user.c
deleted file mode 100644
index ee19e91568a2..000000000000
--- a/arch/um/drivers/mcast_user.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * user-mode-linux networking multicast transport
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
- *
- * based on the existing uml-networking code, which is
- * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
- * James Leu (jleu@mindspring.net).
- * Copyright (C) 2001 by various other people who didn't put their name here.
- *
- * Licensed under the GPL.
- *
- */
-
-#include <unistd.h>
-#include <errno.h>
-#include <netinet/in.h>
-#include "kern_constants.h"
-#include "mcast.h"
-#include "net_user.h"
-#include "um_malloc.h"
-#include "user.h"
-
-static struct sockaddr_in *new_addr(char *addr, unsigned short port)
-{
-        struct sockaddr_in *sin;
-
-        sin = uml_kmalloc(sizeof(struct sockaddr_in), UM_GFP_KERNEL);
-        if (sin == NULL) {
-                printk(UM_KERN_ERR "new_addr: allocation of sockaddr_in "
-                       "failed\n");
-                return NULL;
-        }
-        sin->sin_family = AF_INET;
-        sin->sin_addr.s_addr = in_aton(addr);
-        sin->sin_port = htons(port);
-        return sin;
-}
-
-static int mcast_user_init(void *data, void *dev)
-{
-        struct mcast_data *pri = data;
-
-        pri->mcast_addr = new_addr(pri->addr, pri->port);
-        pri->dev = dev;
-        return 0;
-}
-
-static void mcast_remove(void *data)
-{
-        struct mcast_data *pri = data;
-
-        kfree(pri->mcast_addr);
-        pri->mcast_addr = NULL;
-}
-
-static int mcast_open(void *data)
-{
-        struct mcast_data *pri = data;
-        struct sockaddr_in *sin = pri->mcast_addr;
-        struct ip_mreq mreq;
-        int fd, yes = 1, err = -EINVAL;
-
-
-        if ((sin->sin_addr.s_addr == 0) || (sin->sin_port == 0))
-                goto out;
-
-        fd = socket(AF_INET, SOCK_DGRAM, 0);
-
-        if (fd < 0) {
-                err = -errno;
-                printk(UM_KERN_ERR "mcast_open : data socket failed, "
-                       "errno = %d\n", errno);
-                goto out;
-        }
-
-        if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &yes, sizeof(yes)) < 0) {
-                err = -errno;
-                printk(UM_KERN_ERR "mcast_open: SO_REUSEADDR failed, "
-                       "errno = %d\n", errno);
-                goto out_close;
-        }
-
-        /* set ttl according to config */
-        if (setsockopt(fd, SOL_IP, IP_MULTICAST_TTL, &pri->ttl,
-                       sizeof(pri->ttl)) < 0) {
-                err = -errno;
-                printk(UM_KERN_ERR "mcast_open: IP_MULTICAST_TTL failed, "
-                       "error = %d\n", errno);
-                goto out_close;
-        }
-
-        /* set LOOP, so data does get fed back to local sockets */
-        if (setsockopt(fd, SOL_IP, IP_MULTICAST_LOOP, &yes, sizeof(yes)) < 0) {
-                err = -errno;
-                printk(UM_KERN_ERR "mcast_open: IP_MULTICAST_LOOP failed, "
-                       "error = %d\n", errno);
-                goto out_close;
-        }
-
-        /* bind socket to mcast address */
-        if (bind(fd, (struct sockaddr *) sin, sizeof(*sin)) < 0) {
-                err = -errno;
-                printk(UM_KERN_ERR "mcast_open : data bind failed, "
-                       "errno = %d\n", errno);
-                goto out_close;
-        }
-
-        /* subscribe to the multicast group */
-        mreq.imr_multiaddr.s_addr = sin->sin_addr.s_addr;
-        mreq.imr_interface.s_addr = 0;
-        if (setsockopt(fd, SOL_IP, IP_ADD_MEMBERSHIP,
-                       &mreq, sizeof(mreq)) < 0) {
-                err = -errno;
-                printk(UM_KERN_ERR "mcast_open: IP_ADD_MEMBERSHIP failed, "
-                       "error = %d\n", errno);
-                printk(UM_KERN_ERR "There appears not to be a multicast-"
-                       "capable network interface on the host.\n");
-                printk(UM_KERN_ERR "eth0 should be configured in order to use "
-                       "the multicast transport.\n");
-                goto out_close;
-        }
-
-        return fd;
-
- out_close:
-        close(fd);
- out:
-        return err;
-}
-
-static void mcast_close(int fd, void *data)
-{
-        struct ip_mreq mreq;
-        struct mcast_data *pri = data;
-        struct sockaddr_in *sin = pri->mcast_addr;
-
-        mreq.imr_multiaddr.s_addr = sin->sin_addr.s_addr;
-        mreq.imr_interface.s_addr = 0;
-        if (setsockopt(fd, SOL_IP, IP_DROP_MEMBERSHIP,
-                       &mreq, sizeof(mreq)) < 0) {
-                printk(UM_KERN_ERR "mcast_open: IP_DROP_MEMBERSHIP failed, "
-                       "error = %d\n", errno);
-        }
-
-        close(fd);
-}
-
-int mcast_user_write(int fd, void *buf, int len, struct mcast_data *pri)
-{
-        struct sockaddr_in *data_addr = pri->mcast_addr;
-
-        return net_sendto(fd, buf, len, data_addr, sizeof(*data_addr));
-}
-
-const struct net_user_info mcast_user_info = {
-        .init           = mcast_user_init,
-        .open           = mcast_open,
-        .close          = mcast_close,
-        .remove         = mcast_remove,
-        .add_address    = NULL,
-        .delete_address = NULL,
-        .mtu            = ETH_MAX_PACKET,
-        .max_packet     = ETH_MAX_PACKET + ETH_HEADER_OTHER,
-};
diff --git a/arch/um/drivers/umcast.h b/arch/um/drivers/umcast.h
new file mode 100644
index 000000000000..6f8c0fe890fb
--- /dev/null
+++ b/arch/um/drivers/umcast.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Licensed under the GPL
+ */
+
+#ifndef __DRIVERS_UMCAST_H
+#define __DRIVERS_UMCAST_H
+
+#include "net_user.h"
+
+struct umcast_data {
+        char *addr;
+        unsigned short lport;
+        unsigned short rport;
+        void *listen_addr;
+        void *remote_addr;
+        int ttl;
+        int unicast;
+        void *dev;
+};
+
+extern const struct net_user_info umcast_user_info;
+
+extern int umcast_user_write(int fd, void *buf, int len,
+                             struct umcast_data *pri);
+
+#endif
diff --git a/arch/um/drivers/umcast_kern.c b/arch/um/drivers/umcast_kern.c
new file mode 100644
index 000000000000..42dab11d2ecf
--- /dev/null
+++ b/arch/um/drivers/umcast_kern.c
@@ -0,0 +1,188 @@
+/*
+ * user-mode-linux networking multicast transport
+ * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ *
+ * based on the existing uml-networking code, which is
+ * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
+ * James Leu (jleu@mindspring.net).
+ * Copyright (C) 2001 by various other people who didn't put their name here.
+ *
+ * Licensed under the GPL.
+ */
+
+#include "linux/init.h"
+#include <linux/netdevice.h>
+#include "umcast.h"
+#include "net_kern.h"
+
+struct umcast_init {
+        char *addr;
+        int lport;
+        int rport;
+        int ttl;
+        bool unicast;
+};
+
+static void umcast_init(struct net_device *dev, void *data)
+{
+        struct uml_net_private *pri;
+        struct umcast_data *dpri;
+        struct umcast_init *init = data;
+
+        pri = netdev_priv(dev);
+        dpri = (struct umcast_data *) pri->user;
+        dpri->addr = init->addr;
+        dpri->lport = init->lport;
+        dpri->rport = init->rport;
+        dpri->unicast = init->unicast;
+        dpri->ttl = init->ttl;
+        dpri->dev = dev;
+
+        if (dpri->unicast) {
+                printk(KERN_INFO "ucast backend address: %s:%u listen port: "
+                       "%u\n", dpri->addr, dpri->rport, dpri->lport);
+        } else {
+                printk(KERN_INFO "mcast backend multicast address: %s:%u, "
+                       "TTL:%u\n", dpri->addr, dpri->lport, dpri->ttl);
+        }
+}
+
+static int umcast_read(int fd, struct sk_buff *skb, struct uml_net_private *lp)
+{
+        return net_recvfrom(fd, skb_mac_header(skb),
+                            skb->dev->mtu + ETH_HEADER_OTHER);
+}
+
+static int umcast_write(int fd, struct sk_buff *skb, struct uml_net_private *lp)
+{
+        return umcast_user_write(fd, skb->data, skb->len,
+                                (struct umcast_data *) &lp->user);
+}
+
+static const struct net_kern_info umcast_kern_info = {
+        .init                   = umcast_init,
+        .protocol               = eth_protocol,
+        .read                   = umcast_read,
+        .write                  = umcast_write,
+};
+
+static int mcast_setup(char *str, char **mac_out, void *data)
+{
+        struct umcast_init *init = data;
+        char *port_str = NULL, *ttl_str = NULL, *remain;
+        char *last;
+
+        *init = ((struct umcast_init)
+                { .addr = "239.192.168.1",
+                  .lport        = 1102,
+                  .ttl  = 1 });
+
+        remain = split_if_spec(str, mac_out, &init->addr, &port_str, &ttl_str,
+                               NULL);
+        if (remain != NULL) {
+                printk(KERN_ERR "mcast_setup - Extra garbage on "
+                       "specification : '%s'\n", remain);
+                return 0;
+        }
+
+        if (port_str != NULL) {
+                init->lport = simple_strtoul(port_str, &last, 10);
+                if ((*last != '\0') || (last == port_str)) {
+                        printk(KERN_ERR "mcast_setup - Bad port : '%s'\n",
+                               port_str);
+                        return 0;
+                }
+        }
+
+        if (ttl_str != NULL) {
+                init->ttl = simple_strtoul(ttl_str, &last, 10);
+                if ((*last != '\0') || (last == ttl_str)) {
+                        printk(KERN_ERR "mcast_setup - Bad ttl : '%s'\n",
+                               ttl_str);
+                        return 0;
+                }
+        }
+
+        init->unicast = false;
+        init->rport = init->lport;
+
+        printk(KERN_INFO "Configured mcast device: %s:%u-%u\n", init->addr,
+               init->lport, init->ttl);
+
+        return 1;
+}
+
+static int ucast_setup(char *str, char **mac_out, void *data)
+{
+        struct umcast_init *init = data;
+        char *lport_str = NULL, *rport_str = NULL, *remain;
+        char *last;
+
+        *init = ((struct umcast_init)
+                { .addr         = "",
+                  .lport        = 1102,
+                  .rport        = 1102 });
+
+        remain = split_if_spec(str, mac_out, &init->addr,
+                               &lport_str, &rport_str, NULL);
+        if (remain != NULL) {
+                printk(KERN_ERR "ucast_setup - Extra garbage on "
+                       "specification : '%s'\n", remain);
+                return 0;
+        }
+
+        if (lport_str != NULL) {
+                init->lport = simple_strtoul(lport_str, &last, 10);
+                if ((*last != '\0') || (last == lport_str)) {
+                        printk(KERN_ERR "ucast_setup - Bad listen port : "
+                               "'%s'\n", lport_str);
+                        return 0;
+                }
+        }
+
+        if (rport_str != NULL) {
+                init->rport = simple_strtoul(rport_str, &last, 10);
+                if ((*last != '\0') || (last == rport_str)) {
+                        printk(KERN_ERR "ucast_setup - Bad remote port : "
+                               "'%s'\n", rport_str);
+                        return 0;
+                }
+        }
+
+        init->unicast = true;
+
+        printk(KERN_INFO "Configured ucast device: :%u -> %s:%u\n",
+               init->lport, init->addr, init->rport);
+
+        return 1;
+}
+
+static struct transport mcast_transport = {
+        .list   = LIST_HEAD_INIT(mcast_transport.list),
+        .name   = "mcast",
+        .setup  = mcast_setup,
+        .user   = &umcast_user_info,
+        .kern   = &umcast_kern_info,
+        .private_size   = sizeof(struct umcast_data),
+        .setup_size     = sizeof(struct umcast_init),
+};
+
+static struct transport ucast_transport = {
+        .list   = LIST_HEAD_INIT(ucast_transport.list),
+        .name   = "ucast",
+        .setup  = ucast_setup,
+        .user   = &umcast_user_info,
+        .kern   = &umcast_kern_info,
+        .private_size   = sizeof(struct umcast_data),
+        .setup_size     = sizeof(struct umcast_init),
+};
+
+static int register_umcast(void)
+{
+        register_transport(&mcast_transport);
+        register_transport(&ucast_transport);
+        return 0;
+}
+
+late_initcall(register_umcast);
diff --git a/arch/um/drivers/umcast_user.c b/arch/um/drivers/umcast_user.c
new file mode 100644
index 000000000000..59c56fd6f52a
--- /dev/null
+++ b/arch/um/drivers/umcast_user.c
@@ -0,0 +1,186 @@
+/*
+ * user-mode-linux networking multicast transport
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
+ *
+ * based on the existing uml-networking code, which is
+ * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
+ * James Leu (jleu@mindspring.net).
+ * Copyright (C) 2001 by various other people who didn't put their name here.
+ *
+ * Licensed under the GPL.
+ *
+ */
+
+#include <unistd.h>
+#include <errno.h>
+#include <netinet/in.h>
+#include "kern_constants.h"
+#include "umcast.h"
+#include "net_user.h"
+#include "um_malloc.h"
+#include "user.h"
+
+static struct sockaddr_in *new_addr(char *addr, unsigned short port)
+{
+        struct sockaddr_in *sin;
+
+        sin = uml_kmalloc(sizeof(struct sockaddr_in), UM_GFP_KERNEL);
+        if (sin == NULL) {
+                printk(UM_KERN_ERR "new_addr: allocation of sockaddr_in "
+                       "failed\n");
+                return NULL;
+        }
+        sin->sin_family = AF_INET;
+        if (addr)
+                sin->sin_addr.s_addr = in_aton(addr);
+        else
+                sin->sin_addr.s_addr = INADDR_ANY;
+        sin->sin_port = htons(port);
+        return sin;
+}
+
+static int umcast_user_init(void *data, void *dev)
+{
+        struct umcast_data *pri = data;
+
+        pri->remote_addr = new_addr(pri->addr, pri->rport);
+        if (pri->unicast)
+                pri->listen_addr = new_addr(NULL, pri->lport);
+        else
+                pri->listen_addr = pri->remote_addr;
+        pri->dev = dev;
+        return 0;
+}
+
+static void umcast_remove(void *data)
+{
+        struct umcast_data *pri = data;
+
+        kfree(pri->listen_addr);
+        if (pri->unicast)
+                kfree(pri->remote_addr);
+        pri->listen_addr = pri->remote_addr = NULL;
+}
+
+static int umcast_open(void *data)
+{
+        struct umcast_data *pri = data;
+        struct sockaddr_in *lsin = pri->listen_addr;
+        struct sockaddr_in *rsin = pri->remote_addr;
+        struct ip_mreq mreq;
+        int fd, yes = 1, err = -EINVAL;
+
+
+        if ((!pri->unicast && lsin->sin_addr.s_addr == 0) ||
+            (rsin->sin_addr.s_addr == 0) ||
+            (lsin->sin_port == 0) || (rsin->sin_port == 0))
+                goto out;
+
+        fd = socket(AF_INET, SOCK_DGRAM, 0);
+
+        if (fd < 0) {
+                err = -errno;
+                printk(UM_KERN_ERR "umcast_open : data socket failed, "
+                       "errno = %d\n", errno);
+                goto out;
+        }
+
+        if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &yes, sizeof(yes)) < 0) {
+                err = -errno;
+                printk(UM_KERN_ERR "umcast_open: SO_REUSEADDR failed, "
+                       "errno = %d\n", errno);
+                goto out_close;
+        }
+
+        if (!pri->unicast) {
+                /* set ttl according to config */
+                if (setsockopt(fd, SOL_IP, IP_MULTICAST_TTL, &pri->ttl,
+                               sizeof(pri->ttl)) < 0) {
+                        err = -errno;
+                        printk(UM_KERN_ERR "umcast_open: IP_MULTICAST_TTL "
+                               "failed, error = %d\n", errno);
+                        goto out_close;
+                }
+
+                /* set LOOP, so data does get fed back to local sockets */
+                if (setsockopt(fd, SOL_IP, IP_MULTICAST_LOOP,
+                               &yes, sizeof(yes)) < 0) {
+                        err = -errno;
+                        printk(UM_KERN_ERR "umcast_open: IP_MULTICAST_LOOP "
+                               "failed, error = %d\n", errno);
+                        goto out_close;
+                }
+        }
+
+        /* bind socket to the address */
+        if (bind(fd, (struct sockaddr *) lsin, sizeof(*lsin)) < 0) {
+                err = -errno;
+                printk(UM_KERN_ERR "umcast_open : data bind failed, "
+                       "errno = %d\n", errno);
+                goto out_close;
+        }
+
+        if (!pri->unicast) {
+                /* subscribe to the multicast group */
+                mreq.imr_multiaddr.s_addr = lsin->sin_addr.s_addr;
+                mreq.imr_interface.s_addr = 0;
+                if (setsockopt(fd, SOL_IP, IP_ADD_MEMBERSHIP,
+                               &mreq, sizeof(mreq)) < 0) {
+                        err = -errno;
+                        printk(UM_KERN_ERR "umcast_open: IP_ADD_MEMBERSHIP "
+                               "failed, error = %d\n", errno);
+                        printk(UM_KERN_ERR "There appears not to be a "
+                               "multicast-capable network interface on the "
+                               "host.\n");
+                        printk(UM_KERN_ERR "eth0 should be configured in order "
+                               "to use the multicast transport.\n");
+                        goto out_close;
+                }
+        }
+
+        return fd;
+
+ out_close:
+        close(fd);
+ out:
+        return err;
+}
+
+static void umcast_close(int fd, void *data)
+{
+        struct umcast_data *pri = data;
+
+        if (!pri->unicast) {
+                struct ip_mreq mreq;
+                struct sockaddr_in *lsin = pri->listen_addr;
+
+                mreq.imr_multiaddr.s_addr = lsin->sin_addr.s_addr;
+                mreq.imr_interface.s_addr = 0;
+                if (setsockopt(fd, SOL_IP, IP_DROP_MEMBERSHIP,
+                               &mreq, sizeof(mreq)) < 0) {
+                        printk(UM_KERN_ERR "umcast_close: IP_DROP_MEMBERSHIP "
+                               "failed, error = %d\n", errno);
+                }
+        }
+
+        close(fd);
+}
+
+int umcast_user_write(int fd, void *buf, int len, struct umcast_data *pri)
+{
+        struct sockaddr_in *data_addr = pri->remote_addr;
+
+        return net_sendto(fd, buf, len, data_addr, sizeof(*data_addr));
+}
+
+const struct net_user_info umcast_user_info = {
+        .init   = umcast_user_init,
+        .open   = umcast_open,
+        .close  = umcast_close,
+        .remove = umcast_remove,
+        .add_address    = NULL,
+        .delete_address = NULL,
+        .mtu    = ETH_MAX_PACKET,
+        .max_packet     = ETH_MAX_PACKET + ETH_HEADER_OTHER,
+};
diff --git a/arch/um/drivers/xterm.c b/arch/um/drivers/xterm.c
index da2caa5a21ef..8ac7146c237f 100644
--- a/arch/um/drivers/xterm.c
+++ b/arch/um/drivers/xterm.c
@@ -90,7 +90,7 @@ static int xterm_open(int input, int output, int primary, void *d,
         int pid, fd, new, err;
         char title[256], file[] = "/tmp/xterm-pipeXXXXXX";
         char *argv[] = { terminal_emulator, title_switch, title, exec_switch,
-                         "/usr/lib/uml/port-helper", "-uml-socket",
+                         OS_LIB_PATH "/uml/port-helper", "-uml-socket",
                          file, NULL };
 
         if (access(argv[4], X_OK) < 0)
diff --git a/arch/um/include/asm/common.lds.S b/arch/um/include/asm/common.lds.S
index 34bede8aad4a..4938de5512d2 100644
--- a/arch/um/include/asm/common.lds.S
+++ b/arch/um/include/asm/common.lds.S
@@ -42,7 +42,7 @@
         INIT_SETUP(0)
   }
 
-  PERCPU(32, 32)
+  PERCPU_SECTION(32)
         
   .initcall.init : {
         INIT_CALLS
diff --git a/arch/um/include/asm/processor-generic.h b/arch/um/include/asm/processor-generic.h
index d1d1b0d8a0cd..98d01bc4fa92 100644
--- a/arch/um/include/asm/processor-generic.h
+++ b/arch/um/include/asm/processor-generic.h
@@ -14,6 +14,8 @@ struct task_struct;
 #include "registers.h"
 #include "sysdep/archsetjmp.h"
 
+#include <linux/prefetch.h>
+
 struct mm_struct;
 
 struct thread_struct {
diff --git a/arch/um/include/asm/smp.h b/arch/um/include/asm/smp.h
index f27a96313174..4a4b09d4f366 100644
--- a/arch/um/include/asm/smp.h
+++ b/arch/um/include/asm/smp.h
@@ -11,7 +11,6 @@
 
 #define cpu_logical_map(n) (n)
 #define cpu_number_map(n) (n)
-#define PROC_CHANGE_PENALTY     15 /* Pick a number, any number */
 extern int hard_smp_processor_id(void);
 #define NO_PROC_ID -1
 
diff --git a/arch/um/include/asm/tlb.h b/arch/um/include/asm/tlb.h
index 660caedac9eb..4febacd1a8a1 100644
--- a/arch/um/include/asm/tlb.h
+++ b/arch/um/include/asm/tlb.h
@@ -22,9 +22,6 @@ struct mmu_gather {
         unsigned int            fullmm; /* non-zero means full mm flush */
 };
 
-/* Users of the generic TLB shootdown code must declare this storage space. */
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
                                           unsigned long address)
 {
@@ -47,27 +44,20 @@ static inline void init_tlb_gather(struct mmu_gather *tlb)
         }
 }
 
-/* tlb_gather_mmu
- *      Return a pointer to an initialized struct mmu_gather.
- */
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
 {
-        struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
         tlb->mm = mm;
         tlb->fullmm = full_mm_flush;
 
         init_tlb_gather(tlb);
-
-        return tlb;
 }
 
 extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
                                unsigned long end);
 
 static inline void
-tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
+tlb_flush_mmu(struct mmu_gather *tlb)
 {
         if (!tlb->need_flush)
                 return;
@@ -83,12 +73,10 @@ tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        tlb_flush_mmu(tlb, start, end);
+        tlb_flush_mmu(tlb);
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
-
-        put_cpu_var(mmu_gathers);
 }
 
 /* tlb_remove_page
@@ -96,11 +84,16 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
  *      while handling the additional races in SMP caused by other CPUs
  *      caching valid mappings in their TLBs.
  */
-static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
 {
         tlb->need_flush = 1;
         free_page_and_swap_cache(page);
-        return;
+        return 1; /* avoid calling tlb_flush_mmu */
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        __tlb_remove_page(tlb, page);
 }
 
 /**
diff --git a/arch/um/include/shared/os.h b/arch/um/include/shared/os.h
index c4617baaa4f2..83c7c2ecd614 100644
--- a/arch/um/include/shared/os.h
+++ b/arch/um/include/shared/os.h
@@ -29,6 +29,12 @@
 #define OS_ACC_R_OK    4       /* Test for read permission.  */
 #define OS_ACC_RW_OK   (OS_ACC_W_OK | OS_ACC_R_OK) /* Test for RW permission */
 
+#ifdef CONFIG_64BIT
+#define OS_LIB_PATH     "/usr/lib64/"
+#else
+#define OS_LIB_PATH     "/usr/lib/"
+#endif
+
 /*
  * types taken from stat_file() in hostfs_user.c
  * (if they are wrong here, they are wrong there...).
@@ -238,6 +244,7 @@ extern int raw(int fd);
 extern void setup_machinename(char *machine_out);
 extern void setup_hostinfo(char *buf, int len);
 extern void os_dump_core(void) __attribute__ ((noreturn));
+extern void um_early_printk(const char *s, unsigned int n);
 
 /* time.c */
 extern void idle_sleep(unsigned long long nsecs);
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index 1119233597a1..c4491c15afb2 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -17,6 +17,7 @@ obj-y = config.o exec.o exitcode.o init_task.o irq.o ksyms.o mem.o \
 obj-$(CONFIG_BLK_DEV_INITRD) += initrd.o
 obj-$(CONFIG_GPROF)     += gprof_syms.o
 obj-$(CONFIG_GCOV)      += gmon_syms.o
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 
 USER_OBJS := config.o
 
diff --git a/arch/um/kernel/early_printk.c b/arch/um/kernel/early_printk.c
new file mode 100644
index 000000000000..ec649bf72f68
--- /dev/null
+++ b/arch/um/kernel/early_printk.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2011 Richard Weinberger <richrd@nod.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include "os.h"
+
+static void early_console_write(struct console *con, const char *s, unsigned int n)
+{
+        um_early_printk(s, n);
+}
+
+static struct console early_console = {
+        .name = "earlycon",
+        .write = early_console_write,
+        .flags = CON_BOOT,
+        .index = -1,
+};
+
+static int __init setup_early_printk(char *buf)
+{
+        register_console(&early_console);
+
+        return 0;
+}
+
+early_param("earlyprintk", setup_early_printk);
diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c
index eefb107d2d73..155206a66908 100644
--- a/arch/um/kernel/smp.c
+++ b/arch/um/kernel/smp.c
@@ -7,9 +7,6 @@
 #include "asm/pgalloc.h"
 #include "asm/tlb.h"
 
-/* For some reason, mmu_gathers are referenced when CONFIG_SMP is off. */
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 #ifdef CONFIG_SMP
 
 #include "linux/sched.h"
diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c
index 637c6505dc00..8c7b8823d1f0 100644
--- a/arch/um/kernel/trap.c
+++ b/arch/um/kernel/trap.c
@@ -113,6 +113,27 @@ out_of_memory:
         return 0;
 }
 
+static void show_segv_info(struct uml_pt_regs *regs)
+{
+        struct task_struct *tsk = current;
+        struct faultinfo *fi = UPT_FAULTINFO(regs);
+
+        if (!unhandled_signal(tsk, SIGSEGV))
+                return;
+
+        if (!printk_ratelimit())
+                return;
+
+        printk("%s%s[%d]: segfault at %lx ip %p sp %p error %x",
+                task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
+                tsk->comm, task_pid_nr(tsk), FAULT_ADDRESS(*fi),
+                (void *)UPT_IP(regs), (void *)UPT_SP(regs),
+                fi->error_code);
+
+        print_vma_addr(KERN_CONT " in ", UPT_IP(regs));
+        printk(KERN_CONT "\n");
+}
+
 static void bad_segv(struct faultinfo fi, unsigned long ip)
 {
         struct siginfo si;
@@ -141,6 +162,7 @@ void segv_handler(int sig, struct uml_pt_regs *regs)
         struct faultinfo * fi = UPT_FAULTINFO(regs);
 
         if (UPT_IS_USER(regs) && !SEGV_IS_FIXABLE(fi)) {
+                show_segv_info(regs);
                 bad_segv(*fi, UPT_IP(regs));
                 return;
         }
@@ -202,6 +224,8 @@ unsigned long segv(struct faultinfo fi, unsigned long ip, int is_user,
                       address, ip);
         }
 
+        show_segv_info(regs);
+
         if (err == -EACCES) {
                 si.si_signo = SIGBUS;
                 si.si_errno = 0;
diff --git a/arch/um/os-Linux/main.c b/arch/um/os-Linux/main.c
index eee69b9f52c9..fb2a97a75fb1 100644
--- a/arch/um/os-Linux/main.c
+++ b/arch/um/os-Linux/main.c
@@ -78,7 +78,7 @@ static void install_fatal_handler(int sig)
         }
 }
 
-#define UML_LIB_PATH    ":/usr/lib/uml"
+#define UML_LIB_PATH    ":" OS_LIB_PATH "/uml"
 
 static void setup_env_path(void)
 {
@@ -142,7 +142,6 @@ int __init main(int argc, char **argv, char **envp)
          */
         install_fatal_handler(SIGINT);
         install_fatal_handler(SIGTERM);
-        install_fatal_handler(SIGHUP);
 
         scan_elf_aux(envp);
 
diff --git a/arch/um/os-Linux/process.c b/arch/um/os-Linux/process.c
index e0477c3ee894..0c45dc8efb05 100644
--- a/arch/um/os-Linux/process.c
+++ b/arch/um/os-Linux/process.c
@@ -253,6 +253,7 @@ void init_new_thread_signals(void)
                     SA_ONSTACK | SA_RESTART, SIGUSR1, SIGIO, SIGWINCH, SIGALRM,
                     SIGVTALRM, -1);
         signal(SIGWINCH, SIG_IGN);
+        signal(SIGTERM, SIG_DFL);
 }
 
 int run_kernel_thread(int (*fn)(void *), void *arg, jmp_buf **jmp_ptr)
diff --git a/arch/um/os-Linux/util.c b/arch/um/os-Linux/util.c
index 42827cafa6af..5803b1887672 100644
--- a/arch/um/os-Linux/util.c
+++ b/arch/um/os-Linux/util.c
@@ -139,3 +139,8 @@ void os_dump_core(void)
 
         uml_abort();
 }
+
+void um_early_printk(const char *s, unsigned int n)
+{
+        printf("%.*s", n, s);
+}
diff --git a/arch/unicore32/Kconfig.debug b/arch/unicore32/Kconfig.debug
index 3140151ede45..ae2ec334c3c6 100644
--- a/arch/unicore32/Kconfig.debug
+++ b/arch/unicore32/Kconfig.debug
@@ -27,13 +27,6 @@ config EARLY_PRINTK
           with klogd/syslogd or the X server. You should normally N here,
           unless you want to debug such a crash.
 
-config DEBUG_STACK_USAGE
-        bool "Enable stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        help
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T output.
-
 # These options are only for real kernel hackers who want to get their hands dirty.
 config DEBUG_LL
         bool "Kernel low-level debugging functions"
diff --git a/arch/unicore32/include/asm/suspend.h b/arch/unicore32/include/asm/suspend.h
index 88a9c0f32b21..65bad75c7e96 100644
--- a/arch/unicore32/include/asm/suspend.h
+++ b/arch/unicore32/include/asm/suspend.h
@@ -14,7 +14,6 @@
 #define __UNICORE_SUSPEND_H__
 
 #ifndef __ASSEMBLY__
-static inline int arch_prepare_suspend(void) { return 0; }
 
 #include <asm/ptrace.h>
 
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 1fc02633f700..2d3e7112d2a3 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -62,7 +62,7 @@ void show_mem(unsigned int filter)
         struct meminfo *mi = &meminfo;
 
         printk(KERN_DEFAULT "Mem-info:\n");
-        show_free_areas();
+        show_free_areas(filter);
 
         for_each_bank(i, mi) {
                 struct membank *bank = &mi->bank[i];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index db2d334941b4..3e5c3e5a0b45 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -30,8 +30,6 @@
 
 #include "mm.h"
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 /*
  * empty_zero_page is a special page that is used for
  * zero-initialized data and COW.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 880fcb6c86f4..da349723d411 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -17,8 +17,6 @@ config X86_64
 config X86
         def_bool y
         select HAVE_AOUT if X86_32
-        select HAVE_READQ
-        select HAVE_WRITEQ
         select HAVE_UNSTABLE_SCHED_CLOCK
         select HAVE_IDE
         select HAVE_OPROFILE
@@ -66,7 +64,6 @@ config X86
         select HAVE_GENERIC_HARDIRQS
         select HAVE_SPARSE_IRQ
         select GENERIC_FIND_FIRST_BIT
-        select GENERIC_FIND_NEXT_BIT
         select GENERIC_IRQ_PROBE
         select GENERIC_PENDING_IRQ if SMP
         select GENERIC_IRQ_SHOW
@@ -917,6 +914,7 @@ config TOSHIBA
 
 config I8K
         tristate "Dell laptop support"
+        select HWMON
         ---help---
           This adds a driver to safely access the System Management Mode
           of the CPU on the Dell Inspiron 8000. The System Management Mode
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 615e18810f48..c0f8a5c88910 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -66,26 +66,6 @@ config DEBUG_STACKOVERFLOW
           This option will cause messages to be printed if free stack space
           drops below a certain limit.
 
-config DEBUG_STACK_USAGE
-        bool "Stack utilization instrumentation"
-        depends on DEBUG_KERNEL
-        ---help---
-          Enables the display of the minimum amount of free stack which each
-          task has ever had available in the sysrq-T and sysrq-P debug output.
-
-          This option will slow down process creation somewhat.
-
-config DEBUG_PER_CPU_MAPS
-        bool "Debug access to per_cpu maps"
-        depends on DEBUG_KERNEL
-        depends on SMP
-        ---help---
-          Say Y to verify that the per_cpu map being accessed has
-          been setup.  Adds a fair amount of code to kernel memory
-          and decreases performance.
-
-          Say N if unsure.
-
 config X86_PTDUMP
         bool "Export kernel pagetable layout to userspace via debugfs"
         depends on DEBUG_KERNEL
diff --git a/arch/x86/configs/i386_defconfig b/arch/x86/configs/i386_defconfig
index 6f9872658dd2..2bf18059fbea 100644
--- a/arch/x86/configs/i386_defconfig
+++ b/arch/x86/configs/i386_defconfig
@@ -10,7 +10,6 @@ CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
diff --git a/arch/x86/configs/x86_64_defconfig b/arch/x86/configs/x86_64_defconfig
index ee01a9d5d4f0..22a0dc8e51dd 100644
--- a/arch/x86/configs/x86_64_defconfig
+++ b/arch/x86/configs/x86_64_defconfig
@@ -11,7 +11,6 @@ CONFIG_TASK_IO_ACCOUNTING=y
 CONFIG_AUDIT=y
 CONFIG_LOG_BUF_SHIFT=18
 CONFIG_CGROUPS=y
-CONFIG_CGROUP_NS=y
 CONFIG_CGROUP_FREEZER=y
 CONFIG_CPUSETS=y
 CONFIG_CGROUP_CPUACCT=y
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index 95f5826be458..c1870dddd322 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -849,4 +849,5 @@ ia32_sys_call_table:
         .quad compat_sys_clock_adjtime
         .quad sys_syncfs
         .quad compat_sys_sendmmsg       /* 345 */
+        .quad sys_setns
 ia32_syscall_end:
diff --git a/arch/x86/include/asm/acpi.h b/arch/x86/include/asm/acpi.h
index 416d865eae39..610001d385dd 100644
--- a/arch/x86/include/asm/acpi.h
+++ b/arch/x86/include/asm/acpi.h
@@ -139,7 +139,7 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
             boot_cpu_data.x86_model <= 0x05 &&
             boot_cpu_data.x86_mask < 0x0A)
                 return 1;
-        else if (c1e_detected)
+        else if (amd_e400_c1e_detected)
                 return 1;
         else
                 return max_cstate;
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 5dc6acc98dbd..71cc3800712c 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -125,7 +125,7 @@
 #define X86_FEATURE_OSXSAVE     (4*32+27) /* "" XSAVE enabled in the OS */
 #define X86_FEATURE_AVX         (4*32+28) /* Advanced Vector Extensions */
 #define X86_FEATURE_F16C        (4*32+29) /* 16-bit fp conversions */
-#define X86_FEATURE_RDRND       (4*32+30) /* The RDRAND instruction */
+#define X86_FEATURE_RDRAND      (4*32+30) /* The RDRAND instruction */
 #define X86_FEATURE_HYPERVISOR  (4*32+31) /* Running on a hypervisor */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 617bd56b3070..7b439d9aea2a 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -4,30 +4,33 @@
 #include <asm/desc_defs.h>
 #include <asm/ldt.h>
 #include <asm/mmu.h>
+
 #include <linux/smp.h>
 
-static inline void fill_ldt(struct desc_struct *desc,
-                            const struct user_desc *info)
-{
-        desc->limit0 = info->limit & 0x0ffff;
-        desc->base0 = info->base_addr & 0x0000ffff;
-
-        desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
-        desc->type = (info->read_exec_only ^ 1) << 1;
-        desc->type |= info->contents << 2;
-        desc->s = 1;
-        desc->dpl = 0x3;
-        desc->p = info->seg_not_present ^ 1;
-        desc->limit = (info->limit & 0xf0000) >> 16;
-        desc->avl = info->useable;
-        desc->d = info->seg_32bit;
-        desc->g = info->limit_in_pages;
-        desc->base2 = (info->base_addr & 0xff000000) >> 24;
+static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
+{
+        desc->limit0            = info->limit & 0x0ffff;
+
+        desc->base0             = (info->base_addr & 0x0000ffff);
+        desc->base1             = (info->base_addr & 0x00ff0000) >> 16;
+
+        desc->type              = (info->read_exec_only ^ 1) << 1;
+        desc->type             |= info->contents << 2;
+
+        desc->s                 = 1;
+        desc->dpl               = 0x3;
+        desc->p                 = info->seg_not_present ^ 1;
+        desc->limit             = (info->limit & 0xf0000) >> 16;
+        desc->avl               = info->useable;
+        desc->d                 = info->seg_32bit;
+        desc->g                 = info->limit_in_pages;
+
+        desc->base2             = (info->base_addr & 0xff000000) >> 24;
         /*
          * Don't allow setting of the lm bit. It is useless anyway
          * because 64bit system calls require __USER_CS:
          */
-        desc->l = 0;
+        desc->l                 = 0;
 }
 
 extern struct desc_ptr idt_descr;
@@ -36,6 +39,7 @@ extern gate_desc idt_table[];
 struct gdt_page {
         struct desc_struct gdt[GDT_ENTRIES];
 } __attribute__((aligned(PAGE_SIZE)));
+
 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
 
 static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
@@ -48,16 +52,16 @@ static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
                              unsigned dpl, unsigned ist, unsigned seg)
 {
-        gate->offset_low = PTR_LOW(func);
-        gate->segment = __KERNEL_CS;
-        gate->ist = ist;
-        gate->p = 1;
-        gate->dpl = dpl;
-        gate->zero0 = 0;
-        gate->zero1 = 0;
-        gate->type = type;
-        gate->offset_middle = PTR_MIDDLE(func);
-        gate->offset_high = PTR_HIGH(func);
+        gate->offset_low        = PTR_LOW(func);
+        gate->segment           = __KERNEL_CS;
+        gate->ist               = ist;
+        gate->p                 = 1;
+        gate->dpl               = dpl;
+        gate->zero0             = 0;
+        gate->zero1             = 0;
+        gate->type              = type;
+        gate->offset_middle     = PTR_MIDDLE(func);
+        gate->offset_high       = PTR_HIGH(func);
 }
 
 #else
@@ -66,8 +70,7 @@ static inline void pack_gate(gate_desc *gate, unsigned char type,
                              unsigned short seg)
 {
         gate->a = (seg << 16) | (base & 0xffff);
-        gate->b = (base & 0xffff0000) |
-                  (((0x80 | type | (dpl << 5)) & 0xff) << 8);
+        gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
 }
 
 #endif
@@ -75,31 +78,29 @@ static inline void pack_gate(gate_desc *gate, unsigned char type,
 static inline int desc_empty(const void *ptr)
 {
         const u32 *desc = ptr;
+
         return !(desc[0] | desc[1]);
 }
 
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
-#define load_TR_desc() native_load_tr_desc()
-#define load_gdt(dtr) native_load_gdt(dtr)
-#define load_idt(dtr) native_load_idt(dtr)
-#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
-#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
-
-#define store_gdt(dtr) native_store_gdt(dtr)
-#define store_idt(dtr) native_store_idt(dtr)
-#define store_tr(tr) (tr = native_store_tr())
-
-#define load_TLS(t, cpu) native_load_tls(t, cpu)
-#define set_ldt native_set_ldt
-
-#define write_ldt_entry(dt, entry, desc)        \
-        native_write_ldt_entry(dt, entry, desc)
-#define write_gdt_entry(dt, entry, desc, type)          \
-        native_write_gdt_entry(dt, entry, desc, type)
-#define write_idt_entry(dt, entry, g)           \
-        native_write_idt_entry(dt, entry, g)
+#define load_TR_desc()                          native_load_tr_desc()
+#define load_gdt(dtr)                           native_load_gdt(dtr)
+#define load_idt(dtr)                           native_load_idt(dtr)
+#define load_tr(tr)                             asm volatile("ltr %0"::"m" (tr))
+#define load_ldt(ldt)                           asm volatile("lldt %0"::"m" (ldt))
+
+#define store_gdt(dtr)                          native_store_gdt(dtr)
+#define store_idt(dtr)                          native_store_idt(dtr)
+#define store_tr(tr)                            (tr = native_store_tr())
+
+#define load_TLS(t, cpu)                        native_load_tls(t, cpu)
+#define set_ldt                                 native_set_ldt
+
+#define write_ldt_entry(dt, entry, desc)        native_write_ldt_entry(dt, entry, desc)
+#define write_gdt_entry(dt, entry, desc, type)  native_write_gdt_entry(dt, entry, desc, type)
+#define write_idt_entry(dt, entry, g)           native_write_idt_entry(dt, entry, g)
 
 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
 {
@@ -112,33 +113,27 @@ static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
 
 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
 
-static inline void native_write_idt_entry(gate_desc *idt, int entry,
-                                          const gate_desc *gate)
+static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
 {
         memcpy(&idt[entry], gate, sizeof(*gate));
 }
 
-static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry,
-                                          const void *desc)
+static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
 {
         memcpy(&ldt[entry], desc, 8);
 }
 
-static inline void native_write_gdt_entry(struct desc_struct *gdt, int entry,
-                                          const void *desc, int type)
+static inline void
+native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
 {
         unsigned int size;
+
         switch (type) {
-        case DESC_TSS:
-                size = sizeof(tss_desc);
-                break;
-        case DESC_LDT:
-                size = sizeof(ldt_desc);
-                break;
-        default:
-                size = sizeof(struct desc_struct);
-                break;
+        case DESC_TSS:  size = sizeof(tss_desc);        break;
+        case DESC_LDT:  size = sizeof(ldt_desc);        break;
+        default:        size = sizeof(*gdt);            break;
         }
+
         memcpy(&gdt[entry], desc, size);
 }
 
@@ -154,20 +149,21 @@ static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
 }
 
 
-static inline void set_tssldt_descriptor(void *d, unsigned long addr,
-                                         unsigned type, unsigned size)
+static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
 {
 #ifdef CONFIG_X86_64
         struct ldttss_desc64 *desc = d;
+
         memset(desc, 0, sizeof(*desc));
-        desc->limit0 = size & 0xFFFF;
-        desc->base0 = PTR_LOW(addr);
-        desc->base1 = PTR_MIDDLE(addr) & 0xFF;
-        desc->type = type;
-        desc->p = 1;
-        desc->limit1 = (size >> 16) & 0xF;
-        desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
-        desc->base3 = PTR_HIGH(addr);
+
+        desc->limit0            = size & 0xFFFF;
+        desc->base0             = PTR_LOW(addr);
+        desc->base1             = PTR_MIDDLE(addr) & 0xFF;
+        desc->type              = type;
+        desc->p                 = 1;
+        desc->limit1            = (size >> 16) & 0xF;
+        desc->base2             = (PTR_MIDDLE(addr) >> 8) & 0xFF;
+        desc->base3             = PTR_HIGH(addr);
 #else
         pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
 #endif
@@ -237,14 +233,16 @@ static inline void native_store_idt(struct desc_ptr *dtr)
 static inline unsigned long native_store_tr(void)
 {
         unsigned long tr;
+
         asm volatile("str %0":"=r" (tr));
+
         return tr;
 }
 
 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
 {
-        unsigned int i;
         struct desc_struct *gdt = get_cpu_gdt_table(cpu);
+        unsigned int i;
 
         for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
                 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
@@ -313,6 +311,7 @@ static inline void _set_gate(int gate, unsigned type, void *addr,
                              unsigned dpl, unsigned ist, unsigned seg)
 {
         gate_desc s;
+
         pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
         /*
          * does not need to be atomic because it is only done once at
@@ -343,8 +342,9 @@ static inline void alloc_system_vector(int vector)
                 set_bit(vector, used_vectors);
                 if (first_system_vector > vector)
                         first_system_vector = vector;
-        } else
+        } else {
                 BUG();
+        }
 }
 
 static inline void alloc_intr_gate(unsigned int n, void *addr)
diff --git a/arch/x86/include/asm/idle.h b/arch/x86/include/asm/idle.h
index 38d87379e270..f49253d75710 100644
--- a/arch/x86/include/asm/idle.h
+++ b/arch/x86/include/asm/idle.h
@@ -16,6 +16,6 @@ static inline void enter_idle(void) { }
 static inline void exit_idle(void) { }
 #endif /* CONFIG_X86_64 */
 
-void c1e_remove_cpu(int cpu);
+void amd_e400_remove_cpu(int cpu);
 
 #endif /* _ASM_X86_IDLE_H */
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 072273082528..d02804d650c4 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -38,7 +38,6 @@
 
 #include <linux/string.h>
 #include <linux/compiler.h>
-#include <asm-generic/int-ll64.h>
 #include <asm/page.h>
 
 #include <xen/xen.h>
@@ -87,27 +86,6 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
 build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
 
-#else
-
-static inline __u64 readq(const volatile void __iomem *addr)
-{
-        const volatile u32 __iomem *p = addr;
-        u32 low, high;
-
-        low = readl(p);
-        high = readl(p + 1);
-
-        return low + ((u64)high << 32);
-}
-
-static inline void writeq(__u64 val, volatile void __iomem *addr)
-{
-        writel(val, addr);
-        writel(val >> 32, addr+4);
-}
-
-#endif
-
 #define readq_relaxed(a)        readq(a)
 
 #define __raw_readq(a)          readq(a)
@@ -117,6 +95,8 @@ static inline void writeq(__u64 val, volatile void __iomem *addr)
 #define readq                   readq
 #define writeq                  writeq
 
+#endif
+
 /**
  *      virt_to_phys    -       map virtual addresses to physical
  *      @address: address to remap
diff --git a/arch/x86/include/asm/kgdb.h b/arch/x86/include/asm/kgdb.h
index 396f5b5fc4d7..77e95f54570a 100644
--- a/arch/x86/include/asm/kgdb.h
+++ b/arch/x86/include/asm/kgdb.h
@@ -77,6 +77,7 @@ static inline void arch_kgdb_breakpoint(void)
 }
 #define BREAK_INSTR_SIZE        1
 #define CACHE_FLUSH_IS_SAFE     1
+#define GDB_ADJUSTS_BREAK_OFFSET
 
 extern int kgdb_ll_trap(int cmd, const char *str,
                         struct pt_regs *regs, long err, int trap, int sig);
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
index 12d55e773eb6..48142971b25d 100644
--- a/arch/x86/include/asm/linkage.h
+++ b/arch/x86/include/asm/linkage.h
@@ -8,11 +8,6 @@
 
 #ifdef CONFIG_X86_32
 #define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
-/*
- * For 32-bit UML - mark functions implemented in assembly that use
- * regparm input parameters:
- */
-#define asmregparm __attribute__((regparm(3)))
 
 /*
  * Make sure the compiler doesn't do anything stupid with the
diff --git a/arch/x86/include/asm/mmu.h b/arch/x86/include/asm/mmu.h
index aeff3e89b222..5f55e6962769 100644
--- a/arch/x86/include/asm/mmu.h
+++ b/arch/x86/include/asm/mmu.h
@@ -11,14 +11,14 @@
 typedef struct {
         void *ldt;
         int size;
-        struct mutex lock;
-        void *vdso;
 
 #ifdef CONFIG_X86_64
         /* True if mm supports a task running in 32 bit compatibility mode. */
         unsigned short ia32_compat;
 #endif
 
+        struct mutex lock;
+        void *vdso;
 } mm_context_t;
 
 #ifdef CONFIG_SMP
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 53278b0dfdf6..a0a9779084d1 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -509,6 +509,11 @@ do {									\
  * it in software.  The address used in the cmpxchg16 instruction must be
  * aligned to a 16 byte boundary.
  */
+#ifdef CONFIG_SMP
+#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP3
+#else
+#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP2
+#endif
 #define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2)                  \
 ({                                                                      \
         char __ret;                                                     \
@@ -517,7 +522,7 @@ do {									\
         typeof(o2) __o2 = o2;                                           \
         typeof(o2) __n2 = n2;                                           \
         typeof(o2) __dummy;                                             \
-        alternative_io("call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP4,     \
+        alternative_io(CMPXCHG16B_EMU_CALL,                             \
                        "cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t",  \
                        X86_FEATURE_CX16,                                \
                        ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)),         \
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 4c25ab48257b..219371546afd 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -754,10 +754,10 @@ static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
 
 extern void select_idle_routine(const struct cpuinfo_x86 *c);
-extern void init_c1e_mask(void);
+extern void init_amd_e400_c1e_mask(void);
 
 extern unsigned long            boot_option_idle_override;
-extern bool                     c1e_detected;
+extern bool                     amd_e400_c1e_detected;
 
 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
                          IDLE_POLL, IDLE_FORCE_MWAIT};
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 1babf8adecdf..94e7618fcac8 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -136,6 +136,7 @@ struct cpuinfo_x86;
 struct task_struct;
 
 extern unsigned long profile_pc(struct pt_regs *regs);
+#define profile_pc profile_pc
 
 extern unsigned long
 convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs);
@@ -202,20 +203,11 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
 #endif
 }
 
-static inline unsigned long instruction_pointer(struct pt_regs *regs)
-{
-        return regs->ip;
-}
-
-static inline unsigned long frame_pointer(struct pt_regs *regs)
-{
-        return regs->bp;
-}
+#define GET_IP(regs) ((regs)->ip)
+#define GET_FP(regs) ((regs)->bp)
+#define GET_USP(regs) ((regs)->sp)
 
-static inline unsigned long user_stack_pointer(struct pt_regs *regs)
-{
-        return regs->sp;
-}
+#include <asm-generic/ptrace.h>
 
 /* Query offset/name of register from its name/offset */
 extern int regs_query_register_offset(const char *name);
diff --git a/arch/x86/include/asm/suspend_32.h b/arch/x86/include/asm/suspend_32.h
index fd921c3a6841..487055c8c1aa 100644
--- a/arch/x86/include/asm/suspend_32.h
+++ b/arch/x86/include/asm/suspend_32.h
@@ -9,8 +9,6 @@
 #include <asm/desc.h>
 #include <asm/i387.h>
 
-static inline int arch_prepare_suspend(void) { return 0; }
-
 /* image of the saved processor state */
 struct saved_context {
         u16 es, fs, gs, ss;
diff --git a/arch/x86/include/asm/suspend_64.h b/arch/x86/include/asm/suspend_64.h
index 8d942afae681..09b0bf104156 100644
--- a/arch/x86/include/asm/suspend_64.h
+++ b/arch/x86/include/asm/suspend_64.h
@@ -9,11 +9,6 @@
 #include <asm/desc.h>
 #include <asm/i387.h>
 
-static inline int arch_prepare_suspend(void)
-{
-        return 0;
-}
-
 /*
  * Image of the saved processor state, used by the low level ACPI suspend to
  * RAM code and by the low level hibernation code.
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 83e2efd181e2..9db5583b6d38 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -51,6 +51,10 @@ extern int unsynchronized_tsc(void);
 extern int check_tsc_unstable(void);
 extern unsigned long native_calibrate_tsc(void);
 
+#ifdef CONFIG_X86_64
+extern cycles_t vread_tsc(void);
+#endif
+
 /*
  * Boot-time check whether the TSCs are synchronized across
  * all CPUs/cores:
diff --git a/arch/x86/include/asm/unistd_32.h b/arch/x86/include/asm/unistd_32.h
index fb6a625c99bf..593485b38ab3 100644
--- a/arch/x86/include/asm/unistd_32.h
+++ b/arch/x86/include/asm/unistd_32.h
@@ -351,10 +351,11 @@
 #define __NR_clock_adjtime      343
 #define __NR_syncfs             344
 #define __NR_sendmmsg           345
+#define __NR_setns              346
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 346
+#define NR_syscalls 347
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/x86/include/asm/unistd_64.h b/arch/x86/include/asm/unistd_64.h
index 79f90eb15aad..705bf139288c 100644
--- a/arch/x86/include/asm/unistd_64.h
+++ b/arch/x86/include/asm/unistd_64.h
@@ -679,6 +679,8 @@ __SYSCALL(__NR_clock_adjtime, sys_clock_adjtime)
 __SYSCALL(__NR_syncfs, sys_syncfs)
 #define __NR_sendmmsg                           307
 __SYSCALL(__NR_sendmmsg, sys_sendmmsg)
+#define __NR_setns                              308
+__SYSCALL(__NR_setns, sys_setns)
 
 #ifndef __NO_STUBS
 #define __ARCH_WANT_OLD_READDIR
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index 130f1eeee5fe..a291c40efd43 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -5,7 +5,7 @@
  *
  * SGI UV Broadcast Assist Unit definitions
  *
- * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2008-2011 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_X86_UV_UV_BAU_H
@@ -35,17 +35,20 @@
 
 #define MAX_CPUS_PER_UVHUB              64
 #define MAX_CPUS_PER_SOCKET             32
-#define UV_ADP_SIZE                     64 /* hardware-provided max. */
-#define UV_CPUS_PER_ACT_STATUS          32 /* hardware-provided max. */
-#define UV_ITEMS_PER_DESCRIPTOR         8
+#define ADP_SZ                          64 /* hardware-provided max. */
+#define UV_CPUS_PER_AS                  32 /* hardware-provided max. */
+#define ITEMS_PER_DESC                  8
 /* the 'throttle' to prevent the hardware stay-busy bug */
 #define MAX_BAU_CONCURRENT              3
 #define UV_ACT_STATUS_MASK              0x3
 #define UV_ACT_STATUS_SIZE              2
 #define UV_DISTRIBUTION_SIZE            256
 #define UV_SW_ACK_NPENDING              8
-#define UV_NET_ENDPOINT_INTD            0x38
-#define UV_DESC_BASE_PNODE_SHIFT        49
+#define UV1_NET_ENDPOINT_INTD           0x38
+#define UV2_NET_ENDPOINT_INTD           0x28
+#define UV_NET_ENDPOINT_INTD            (is_uv1_hub() ?                 \
+                        UV1_NET_ENDPOINT_INTD : UV2_NET_ENDPOINT_INTD)
+#define UV_DESC_PSHIFT                  49
 #define UV_PAYLOADQ_PNODE_SHIFT         49
 #define UV_PTC_BASENAME                 "sgi_uv/ptc_statistics"
 #define UV_BAU_BASENAME                 "sgi_uv/bau_tunables"
@@ -53,29 +56,64 @@
 #define UV_BAU_TUNABLES_FILE            "bau_tunables"
 #define WHITESPACE                      " \t\n"
 #define uv_physnodeaddr(x)              ((__pa((unsigned long)(x)) & uv_mmask))
-#define UV_ENABLE_INTD_SOFT_ACK_MODE_SHIFT 15
-#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHIFT 16
-#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD 0x0000000009UL
+#define cpubit_isset(cpu, bau_local_cpumask) \
+        test_bit((cpu), (bau_local_cpumask).bits)
+
 /* [19:16] SOFT_ACK timeout period  19: 1 is urgency 7  17:16 1 is multiplier */
-#define BAU_MISC_CONTROL_MULT_MASK 3
+/*
+ * UV2: Bit 19 selects between
+ *  (0): 10 microsecond timebase and
+ *  (1): 80 microseconds
+ *  we're using 655us, similar to UV1: 65 units of 10us
+ */
+#define UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD (9UL)
+#define UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD (65*10UL)
+
+#define UV_INTD_SOFT_ACK_TIMEOUT_PERIOD (is_uv1_hub() ?                 \
+                UV1_INTD_SOFT_ACK_TIMEOUT_PERIOD :                      \
+                UV2_INTD_SOFT_ACK_TIMEOUT_PERIOD)
 
-#define UVH_AGING_PRESCALE_SEL 0x000000b000UL
+#define BAU_MISC_CONTROL_MULT_MASK      3
+
+#define UVH_AGING_PRESCALE_SEL          0x000000b000UL
 /* [30:28] URGENCY_7  an index into a table of times */
-#define BAU_URGENCY_7_SHIFT 28
-#define BAU_URGENCY_7_MASK 7
+#define BAU_URGENCY_7_SHIFT             28
+#define BAU_URGENCY_7_MASK              7
 
-#define UVH_TRANSACTION_TIMEOUT 0x000000b200UL
+#define UVH_TRANSACTION_TIMEOUT         0x000000b200UL
 /* [45:40] BAU - BAU transaction timeout select - a multiplier */
-#define BAU_TRANS_SHIFT 40
-#define BAU_TRANS_MASK 0x3f
+#define BAU_TRANS_SHIFT                 40
+#define BAU_TRANS_MASK                  0x3f
+
+/*
+ * shorten some awkward names
+ */
+#define AS_PUSH_SHIFT UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT
+#define SOFTACK_MSHIFT UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT
+#define SOFTACK_PSHIFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
+#define SOFTACK_TIMEOUT_PERIOD UV_INTD_SOFT_ACK_TIMEOUT_PERIOD
+#define write_gmmr      uv_write_global_mmr64
+#define write_lmmr      uv_write_local_mmr
+#define read_lmmr       uv_read_local_mmr
+#define read_gmmr       uv_read_global_mmr64
 
 /*
  * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
  */
-#define DESC_STATUS_IDLE                0
-#define DESC_STATUS_ACTIVE              1
-#define DESC_STATUS_DESTINATION_TIMEOUT 2
-#define DESC_STATUS_SOURCE_TIMEOUT      3
+#define DS_IDLE                         0
+#define DS_ACTIVE                       1
+#define DS_DESTINATION_TIMEOUT          2
+#define DS_SOURCE_TIMEOUT               3
+/*
+ * bits put together from HRP_LB_BAU_SB_ACTIVATION_STATUS_0/1/2
+ * values 1 and 5 will not occur
+ */
+#define UV2H_DESC_IDLE                  0
+#define UV2H_DESC_DEST_TIMEOUT          2
+#define UV2H_DESC_DEST_STRONG_NACK      3
+#define UV2H_DESC_BUSY                  4
+#define UV2H_DESC_SOURCE_TIMEOUT        6
+#define UV2H_DESC_DEST_PUT_ERR          7
 
 /*
  * delay for 'plugged' timeout retries, in microseconds
@@ -86,15 +124,24 @@
  * threshholds at which to use IPI to free resources
  */
 /* after this # consecutive 'plugged' timeouts, use IPI to release resources */
-#define PLUGSB4RESET 100
+#define PLUGSB4RESET                    100
 /* after this many consecutive timeouts, use IPI to release resources */
-#define TIMEOUTSB4RESET 1
+#define TIMEOUTSB4RESET                 1
 /* at this number uses of IPI to release resources, giveup the request */
-#define IPI_RESET_LIMIT 1
+#define IPI_RESET_LIMIT                 1
 /* after this # consecutive successes, bump up the throttle if it was lowered */
-#define COMPLETE_THRESHOLD 5
+#define COMPLETE_THRESHOLD              5
+
+#define UV_LB_SUBNODEID                 0x10
 
-#define UV_LB_SUBNODEID 0x10
+/* these two are the same for UV1 and UV2: */
+#define UV_SA_SHFT UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT
+#define UV_SA_MASK UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK
+/* 4 bits of software ack period */
+#define UV2_ACK_MASK                    0x7UL
+#define UV2_ACK_UNITS_SHFT              3
+#define UV2_LEG_SHFT UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT
+#define UV2_EXT_SHFT UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT
 
 /*
  * number of entries in the destination side payload queue
@@ -115,9 +162,16 @@
 /*
  * tuning the action when the numalink network is extremely delayed
  */
-#define CONGESTED_RESPONSE_US 1000 /* 'long' response time, in microseconds */
-#define CONGESTED_REPS 10 /* long delays averaged over this many broadcasts */
-#define CONGESTED_PERIOD 30 /* time for the bau to be disabled, in seconds */
+#define CONGESTED_RESPONSE_US           1000    /* 'long' response time, in
+                                                   microseconds */
+#define CONGESTED_REPS                  10      /* long delays averaged over
+                                                   this many broadcasts */
+#define CONGESTED_PERIOD                30      /* time for the bau to be
+                                                   disabled, in seconds */
+/* see msg_type: */
+#define MSG_NOOP                        0
+#define MSG_REGULAR                     1
+#define MSG_RETRY                       2
 
 /*
  * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
@@ -129,8 +183,8 @@
  * 'base_dest_nasid' field of the header corresponds to the
  * destination nodeID associated with that specified bit.
  */
-struct bau_target_uvhubmask {
-        unsigned long bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
+struct bau_targ_hubmask {
+        unsigned long           bits[BITS_TO_LONGS(UV_DISTRIBUTION_SIZE)];
 };
 
 /*
@@ -139,7 +193,7 @@ struct bau_target_uvhubmask {
  *  enough bits for max. cpu's per uvhub)
  */
 struct bau_local_cpumask {
-        unsigned long bits;
+        unsigned long           bits;
 };
 
 /*
@@ -160,14 +214,14 @@ struct bau_local_cpumask {
  * The payload is software-defined for INTD transactions
  */
 struct bau_msg_payload {
-        unsigned long address;          /* signifies a page or all TLB's
-                                                of the cpu */
+        unsigned long   address;                /* signifies a page or all
+                                                   TLB's of the cpu */
         /* 64 bits */
-        unsigned short sending_cpu;     /* filled in by sender */
+        unsigned short  sending_cpu;            /* filled in by sender */
         /* 16 bits */
-        unsigned short acknowledge_count;/* filled in by destination */
+        unsigned short  acknowledge_count;      /* filled in by destination */
         /* 16 bits */
-        unsigned int reserved1:32;      /* not usable */
+        unsigned int    reserved1:32;           /* not usable */
 };
 
 
@@ -176,93 +230,96 @@ struct bau_msg_payload {
  * see table 4.2.3.0.1 in broacast_assist spec.
  */
 struct bau_msg_header {
-        unsigned int dest_subnodeid:6;  /* must be 0x10, for the LB */
+        unsigned int    dest_subnodeid:6;       /* must be 0x10, for the LB */
         /* bits 5:0 */
-        unsigned int base_dest_nasid:15; /* nasid of the */
-        /* bits 20:6 */                   /* first bit in uvhub map */
-        unsigned int command:8; /* message type */
+        unsigned int    base_dest_nasid:15;     /* nasid of the first bit */
+        /* bits 20:6 */                         /* in uvhub map */
+        unsigned int    command:8;              /* message type */
         /* bits 28:21 */
-                                /* 0x38: SN3net EndPoint Message */
-        unsigned int rsvd_1:3;  /* must be zero */
+        /* 0x38: SN3net EndPoint Message */
+        unsigned int    rsvd_1:3;               /* must be zero */
         /* bits 31:29 */
-                                /* int will align on 32 bits */
-        unsigned int rsvd_2:9;  /* must be zero */
+        /* int will align on 32 bits */
+        unsigned int    rsvd_2:9;               /* must be zero */
         /* bits 40:32 */
-                                /* Suppl_A is 56-41 */
-        unsigned int sequence:16;/* message sequence number */
-        /* bits 56:41 */        /* becomes bytes 16-17 of msg */
-                                /* Address field (96:57) is never used as an
-                                   address (these are address bits 42:3) */
-
-        unsigned int rsvd_3:1;  /* must be zero */
+        /* Suppl_A is 56-41 */
+        unsigned int    sequence:16;            /* message sequence number */
+        /* bits 56:41 */                        /* becomes bytes 16-17 of msg */
+                                                /* Address field (96:57) is
+                                                   never used as an address
+                                                   (these are address bits
+                                                   42:3) */
+
+        unsigned int    rsvd_3:1;               /* must be zero */
         /* bit 57 */
-                                /* address bits 27:4 are payload */
+        /* address bits 27:4 are payload */
         /* these next 24  (58-81) bits become bytes 12-14 of msg */
-
         /* bits 65:58 land in byte 12 */
-        unsigned int replied_to:1;/* sent as 0 by the source to byte 12 */
+        unsigned int    replied_to:1;           /* sent as 0 by the source to
+                                                   byte 12 */
         /* bit 58 */
-        unsigned int msg_type:3; /* software type of the message*/
+        unsigned int    msg_type:3;             /* software type of the
+                                                   message */
         /* bits 61:59 */
-        unsigned int canceled:1; /* message canceled, resource to be freed*/
+        unsigned int    canceled:1;             /* message canceled, resource
+                                                   is to be freed*/
         /* bit 62 */
-        unsigned int payload_1a:1;/* not currently used */
+        unsigned int    payload_1a:1;           /* not currently used */
         /* bit 63 */
-        unsigned int payload_1b:2;/* not currently used */
+        unsigned int    payload_1b:2;           /* not currently used */
         /* bits 65:64 */
 
         /* bits 73:66 land in byte 13 */
-        unsigned int payload_1ca:6;/* not currently used */
+        unsigned int    payload_1ca:6;          /* not currently used */
         /* bits 71:66 */
-        unsigned int payload_1c:2;/* not currently used */
+        unsigned int    payload_1c:2;           /* not currently used */
         /* bits 73:72 */
 
         /* bits 81:74 land in byte 14 */
-        unsigned int payload_1d:6;/* not currently used */
+        unsigned int    payload_1d:6;           /* not currently used */
         /* bits 79:74 */
-        unsigned int payload_1e:2;/* not currently used */
+        unsigned int    payload_1e:2;           /* not currently used */
         /* bits 81:80 */
 
-        unsigned int rsvd_4:7;  /* must be zero */
+        unsigned int    rsvd_4:7;               /* must be zero */
         /* bits 88:82 */
-        unsigned int sw_ack_flag:1;/* software acknowledge flag */
+        unsigned int    swack_flag:1;           /* software acknowledge flag */
         /* bit 89 */
-                                /* INTD trasactions at destination are to
-                                   wait for software acknowledge */
-        unsigned int rsvd_5:6;  /* must be zero */
+                                                /* INTD trasactions at
+                                                   destination are to wait for
+                                                   software acknowledge */
+        unsigned int    rsvd_5:6;               /* must be zero */
         /* bits 95:90 */
-        unsigned int rsvd_6:5;  /* must be zero */
+        unsigned int    rsvd_6:5;               /* must be zero */
         /* bits 100:96 */
-        unsigned int int_both:1;/* if 1, interrupt both sockets on the uvhub */
+        unsigned int    int_both:1;             /* if 1, interrupt both sockets
+                                                   on the uvhub */
         /* bit 101*/
-        unsigned int fairness:3;/* usually zero */
+        unsigned int    fairness:3;             /* usually zero */
         /* bits 104:102 */
-        unsigned int multilevel:1;      /* multi-level multicast format */
+        unsigned int    multilevel:1;           /* multi-level multicast
+                                                   format */
         /* bit 105 */
-                                /* 0 for TLB: endpoint multi-unicast messages */
-        unsigned int chaining:1;/* next descriptor is part of this activation*/
+        /* 0 for TLB: endpoint multi-unicast messages */
+        unsigned int    chaining:1;             /* next descriptor is part of
+                                                   this activation*/
         /* bit 106 */
-        unsigned int rsvd_7:21; /* must be zero */
+        unsigned int    rsvd_7:21;              /* must be zero */
         /* bits 127:107 */
 };
 
-/* see msg_type: */
-#define MSG_NOOP 0
-#define MSG_REGULAR 1
-#define MSG_RETRY 2
-
 /*
  * The activation descriptor:
  * The format of the message to send, plus all accompanying control
  * Should be 64 bytes
  */
 struct bau_desc {
-        struct bau_target_uvhubmask distribution;
+        struct bau_targ_hubmask distribution;
         /*
          * message template, consisting of header and payload:
          */
-        struct bau_msg_header header;
-        struct bau_msg_payload payload;
+        struct bau_msg_header           header;
+        struct bau_msg_payload          payload;
 };
 /*
  *   -payload--    ---------header------
@@ -281,59 +338,51 @@ struct bau_desc {
  * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
  * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
  * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
- *  sw_ack_vector and payload_2)
+ *  swack_vec and payload_2)
  * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
  *  Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
  *  operation."
  */
-struct bau_payload_queue_entry {
-        unsigned long address;          /* signifies a page or all TLB's
-                                                of the cpu */
+struct bau_pq_entry {
+        unsigned long   address;        /* signifies a page or all TLB's
+                                           of the cpu */
         /* 64 bits, bytes 0-7 */
-
-        unsigned short sending_cpu;     /* cpu that sent the message */
+        unsigned short  sending_cpu;    /* cpu that sent the message */
         /* 16 bits, bytes 8-9 */
-
-        unsigned short acknowledge_count; /* filled in by destination */
+        unsigned short  acknowledge_count; /* filled in by destination */
         /* 16 bits, bytes 10-11 */
-
         /* these next 3 bytes come from bits 58-81 of the message header */
-        unsigned short replied_to:1;    /* sent as 0 by the source */
-        unsigned short msg_type:3;      /* software message type */
-        unsigned short canceled:1;      /* sent as 0 by the source */
-        unsigned short unused1:3;       /* not currently using */
+        unsigned short  replied_to:1;   /* sent as 0 by the source */
+        unsigned short  msg_type:3;     /* software message type */
+        unsigned short  canceled:1;     /* sent as 0 by the source */
+        unsigned short  unused1:3;      /* not currently using */
         /* byte 12 */
-
-        unsigned char unused2a;         /* not currently using */
+        unsigned char   unused2a;       /* not currently using */
         /* byte 13 */
-        unsigned char unused2;          /* not currently using */
+        unsigned char   unused2;        /* not currently using */
         /* byte 14 */
-
-        unsigned char sw_ack_vector;    /* filled in by the hardware */
+        unsigned char   swack_vec;      /* filled in by the hardware */
         /* byte 15 (bits 127:120) */
-
-        unsigned short sequence;        /* message sequence number */
+        unsigned short  sequence;       /* message sequence number */
         /* bytes 16-17 */
-        unsigned char unused4[2];       /* not currently using bytes 18-19 */
+        unsigned char   unused4[2];     /* not currently using bytes 18-19 */
         /* bytes 18-19 */
-
-        int number_of_cpus;             /* filled in at destination */
+        int             number_of_cpus; /* filled in at destination */
         /* 32 bits, bytes 20-23 (aligned) */
-
-        unsigned char unused5[8];       /* not using */
+        unsigned char   unused5[8];     /* not using */
         /* bytes 24-31 */
 };
 
 struct msg_desc {
-        struct bau_payload_queue_entry *msg;
-        int msg_slot;
-        int sw_ack_slot;
-        struct bau_payload_queue_entry *va_queue_first;
-        struct bau_payload_queue_entry *va_queue_last;
+        struct bau_pq_entry     *msg;
+        int                     msg_slot;
+        int                     swack_slot;
+        struct bau_pq_entry     *queue_first;
+        struct bau_pq_entry     *queue_last;
 };
 
 struct reset_args {
-        int sender;
+        int                     sender;
 };
 
 /*
@@ -341,112 +390,226 @@ struct reset_args {
  */
 struct ptc_stats {
         /* sender statistics */
-        unsigned long s_giveup; /* number of fall backs to IPI-style flushes */
-        unsigned long s_requestor; /* number of shootdown requests */
-        unsigned long s_stimeout; /* source side timeouts */
-        unsigned long s_dtimeout; /* destination side timeouts */
-        unsigned long s_time; /* time spent in sending side */
-        unsigned long s_retriesok; /* successful retries */
-        unsigned long s_ntargcpu; /* total number of cpu's targeted */
-        unsigned long s_ntargself; /* times the sending cpu was targeted */
-        unsigned long s_ntarglocals; /* targets of cpus on the local blade */
-        unsigned long s_ntargremotes; /* targets of cpus on remote blades */
-        unsigned long s_ntarglocaluvhub; /* targets of the local hub */
-        unsigned long s_ntargremoteuvhub; /* remotes hubs targeted */
-        unsigned long s_ntarguvhub; /* total number of uvhubs targeted */
-        unsigned long s_ntarguvhub16; /* number of times target hubs >= 16*/
-        unsigned long s_ntarguvhub8; /* number of times target hubs >= 8 */
-        unsigned long s_ntarguvhub4; /* number of times target hubs >= 4 */
-        unsigned long s_ntarguvhub2; /* number of times target hubs >= 2 */
-        unsigned long s_ntarguvhub1; /* number of times target hubs == 1 */
-        unsigned long s_resets_plug; /* ipi-style resets from plug state */
-        unsigned long s_resets_timeout; /* ipi-style resets from timeouts */
-        unsigned long s_busy; /* status stayed busy past s/w timer */
-        unsigned long s_throttles; /* waits in throttle */
-        unsigned long s_retry_messages; /* retry broadcasts */
-        unsigned long s_bau_reenabled; /* for bau enable/disable */
-        unsigned long s_bau_disabled; /* for bau enable/disable */
+        unsigned long   s_giveup;               /* number of fall backs to
+                                                   IPI-style flushes */
+        unsigned long   s_requestor;            /* number of shootdown
+                                                   requests */
+        unsigned long   s_stimeout;             /* source side timeouts */
+        unsigned long   s_dtimeout;             /* destination side timeouts */
+        unsigned long   s_time;                 /* time spent in sending side */
+        unsigned long   s_retriesok;            /* successful retries */
+        unsigned long   s_ntargcpu;             /* total number of cpu's
+                                                   targeted */
+        unsigned long   s_ntargself;            /* times the sending cpu was
+                                                   targeted */
+        unsigned long   s_ntarglocals;          /* targets of cpus on the local
+                                                   blade */
+        unsigned long   s_ntargremotes;         /* targets of cpus on remote
+                                                   blades */
+        unsigned long   s_ntarglocaluvhub;      /* targets of the local hub */
+        unsigned long   s_ntargremoteuvhub;     /* remotes hubs targeted */
+        unsigned long   s_ntarguvhub;           /* total number of uvhubs
+                                                   targeted */
+        unsigned long   s_ntarguvhub16;         /* number of times target
+                                                   hubs >= 16*/
+        unsigned long   s_ntarguvhub8;          /* number of times target
+                                                   hubs >= 8 */
+        unsigned long   s_ntarguvhub4;          /* number of times target
+                                                   hubs >= 4 */
+        unsigned long   s_ntarguvhub2;          /* number of times target
+                                                   hubs >= 2 */
+        unsigned long   s_ntarguvhub1;          /* number of times target
+                                                   hubs == 1 */
+        unsigned long   s_resets_plug;          /* ipi-style resets from plug
+                                                   state */
+        unsigned long   s_resets_timeout;       /* ipi-style resets from
+                                                   timeouts */
+        unsigned long   s_busy;                 /* status stayed busy past
+                                                   s/w timer */
+        unsigned long   s_throttles;            /* waits in throttle */
+        unsigned long   s_retry_messages;       /* retry broadcasts */
+        unsigned long   s_bau_reenabled;        /* for bau enable/disable */
+        unsigned long   s_bau_disabled;         /* for bau enable/disable */
         /* destination statistics */
-        unsigned long d_alltlb; /* times all tlb's on this cpu were flushed */
-        unsigned long d_onetlb; /* times just one tlb on this cpu was flushed */
-        unsigned long d_multmsg; /* interrupts with multiple messages */
-        unsigned long d_nomsg; /* interrupts with no message */
-        unsigned long d_time; /* time spent on destination side */
-        unsigned long d_requestee; /* number of messages processed */
-        unsigned long d_retries; /* number of retry messages processed */
-        unsigned long d_canceled; /* number of messages canceled by retries */
-        unsigned long d_nocanceled; /* retries that found nothing to cancel */
-        unsigned long d_resets; /* number of ipi-style requests processed */
-        unsigned long d_rcanceled; /* number of messages canceled by resets */
+        unsigned long   d_alltlb;               /* times all tlb's on this
+                                                   cpu were flushed */
+        unsigned long   d_onetlb;               /* times just one tlb on this
+                                                   cpu was flushed */
+        unsigned long   d_multmsg;              /* interrupts with multiple
+                                                   messages */
+        unsigned long   d_nomsg;                /* interrupts with no message */
+        unsigned long   d_time;                 /* time spent on destination
+                                                   side */
+        unsigned long   d_requestee;            /* number of messages
+                                                   processed */
+        unsigned long   d_retries;              /* number of retry messages
+                                                   processed */
+        unsigned long   d_canceled;             /* number of messages canceled
+                                                   by retries */
+        unsigned long   d_nocanceled;           /* retries that found nothing
+                                                   to cancel */
+        unsigned long   d_resets;               /* number of ipi-style requests
+                                                   processed */
+        unsigned long   d_rcanceled;            /* number of messages canceled
+                                                   by resets */
+};
+
+struct tunables {
+        int                     *tunp;
+        int                     deflt;
 };
 
 struct hub_and_pnode {
-        short uvhub;
-        short pnode;
+        short                   uvhub;
+        short                   pnode;
 };
+
+struct socket_desc {
+        short                   num_cpus;
+        short                   cpu_number[MAX_CPUS_PER_SOCKET];
+};
+
+struct uvhub_desc {
+        unsigned short          socket_mask;
+        short                   num_cpus;
+        short                   uvhub;
+        short                   pnode;
+        struct socket_desc      socket[2];
+};
+
 /*
  * one per-cpu; to locate the software tables
  */
 struct bau_control {
-        struct bau_desc *descriptor_base;
-        struct bau_payload_queue_entry *va_queue_first;
-        struct bau_payload_queue_entry *va_queue_last;
-        struct bau_payload_queue_entry *bau_msg_head;
-        struct bau_control *uvhub_master;
-        struct bau_control *socket_master;
-        struct ptc_stats *statp;
-        unsigned long timeout_interval;
-        unsigned long set_bau_on_time;
-        atomic_t active_descriptor_count;
-        int plugged_tries;
-        int timeout_tries;
-        int ipi_attempts;
-        int conseccompletes;
-        int baudisabled;
-        int set_bau_off;
-        short cpu;
-        short osnode;
-        short uvhub_cpu;
-        short uvhub;
-        short cpus_in_socket;
-        short cpus_in_uvhub;
-        short partition_base_pnode;
-        unsigned short message_number;
-        unsigned short uvhub_quiesce;
-        short socket_acknowledge_count[DEST_Q_SIZE];
-        cycles_t send_message;
-        spinlock_t uvhub_lock;
-        spinlock_t queue_lock;
+        struct bau_desc         *descriptor_base;
+        struct bau_pq_entry     *queue_first;
+        struct bau_pq_entry     *queue_last;
+        struct bau_pq_entry     *bau_msg_head;
+        struct bau_control      *uvhub_master;
+        struct bau_control      *socket_master;
+        struct ptc_stats        *statp;
+        unsigned long           timeout_interval;
+        unsigned long           set_bau_on_time;
+        atomic_t                active_descriptor_count;
+        int                     plugged_tries;
+        int                     timeout_tries;
+        int                     ipi_attempts;
+        int                     conseccompletes;
+        int                     baudisabled;
+        int                     set_bau_off;
+        short                   cpu;
+        short                   osnode;
+        short                   uvhub_cpu;
+        short                   uvhub;
+        short                   cpus_in_socket;
+        short                   cpus_in_uvhub;
+        short                   partition_base_pnode;
+        unsigned short          message_number;
+        unsigned short          uvhub_quiesce;
+        short                   socket_acknowledge_count[DEST_Q_SIZE];
+        cycles_t                send_message;
+        spinlock_t              uvhub_lock;
+        spinlock_t              queue_lock;
         /* tunables */
-        int max_bau_concurrent;
-        int max_bau_concurrent_constant;
-        int plugged_delay;
-        int plugsb4reset;
-        int timeoutsb4reset;
-        int ipi_reset_limit;
-        int complete_threshold;
-        int congested_response_us;
-        int congested_reps;
-        int congested_period;
-        cycles_t period_time;
-        long period_requests;
-        struct hub_and_pnode *target_hub_and_pnode;
+        int                     max_concurr;
+        int                     max_concurr_const;
+        int                     plugged_delay;
+        int                     plugsb4reset;
+        int                     timeoutsb4reset;
+        int                     ipi_reset_limit;
+        int                     complete_threshold;
+        int                     cong_response_us;
+        int                     cong_reps;
+        int                     cong_period;
+        cycles_t                period_time;
+        long                    period_requests;
+        struct hub_and_pnode    *thp;
 };
 
-static inline int bau_uvhub_isset(int uvhub, struct bau_target_uvhubmask *dstp)
+static unsigned long read_mmr_uv2_status(void)
+{
+        return read_lmmr(UV2H_LB_BAU_SB_ACTIVATION_STATUS_2);
+}
+
+static void write_mmr_data_broadcast(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_BAU_DATA_BROADCAST, mmr_image);
+}
+
+static void write_mmr_descriptor_base(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE, mmr_image);
+}
+
+static void write_mmr_activation(unsigned long index)
+{
+        write_lmmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
+}
+
+static void write_gmmr_activation(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_LB_BAU_SB_ACTIVATION_CONTROL, mmr_image);
+}
+
+static void write_mmr_payload_first(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST, mmr_image);
+}
+
+static void write_mmr_payload_tail(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL, mmr_image);
+}
+
+static void write_mmr_payload_last(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST, mmr_image);
+}
+
+static void write_mmr_misc_control(int pnode, unsigned long mmr_image)
+{
+        write_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
+}
+
+static unsigned long read_mmr_misc_control(int pnode)
+{
+        return read_gmmr(pnode, UVH_LB_BAU_MISC_CONTROL);
+}
+
+static void write_mmr_sw_ack(unsigned long mr)
+{
+        uv_write_local_mmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, mr);
+}
+
+static unsigned long read_mmr_sw_ack(void)
+{
+        return read_lmmr(UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
+}
+
+static unsigned long read_gmmr_sw_ack(int pnode)
+{
+        return read_gmmr(pnode, UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
+}
+
+static void write_mmr_data_config(int pnode, unsigned long mr)
+{
+        uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG, mr);
+}
+
+static inline int bau_uvhub_isset(int uvhub, struct bau_targ_hubmask *dstp)
 {
         return constant_test_bit(uvhub, &dstp->bits[0]);
 }
-static inline void bau_uvhub_set(int pnode, struct bau_target_uvhubmask *dstp)
+static inline void bau_uvhub_set(int pnode, struct bau_targ_hubmask *dstp)
 {
         __set_bit(pnode, &dstp->bits[0]);
 }
-static inline void bau_uvhubs_clear(struct bau_target_uvhubmask *dstp,
+static inline void bau_uvhubs_clear(struct bau_targ_hubmask *dstp,
                                     int nbits)
 {
         bitmap_zero(&dstp->bits[0], nbits);
 }
-static inline int bau_uvhub_weight(struct bau_target_uvhubmask *dstp)
+static inline int bau_uvhub_weight(struct bau_targ_hubmask *dstp)
 {
         return bitmap_weight((unsigned long *)&dstp->bits[0],
                                 UV_DISTRIBUTION_SIZE);
@@ -457,9 +620,6 @@ static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
         bitmap_zero(&dstp->bits, nbits);
 }
 
-#define cpubit_isset(cpu, bau_local_cpumask) \
-        test_bit((cpu), (bau_local_cpumask).bits)
-
 extern void uv_bau_message_intr1(void);
 extern void uv_bau_timeout_intr1(void);
 
@@ -467,7 +627,7 @@ struct atomic_short {
         short counter;
 };
 
-/**
+/*
  * atomic_read_short - read a short atomic variable
  * @v: pointer of type atomic_short
  *
@@ -478,14 +638,14 @@ static inline int atomic_read_short(const struct atomic_short *v)
         return v->counter;
 }
 
-/**
- * atomic_add_short_return - add and return a short int
+/*
+ * atom_asr - add and return a short int
  * @i: short value to add
  * @v: pointer of type atomic_short
  *
  * Atomically adds @i to @v and returns @i + @v
  */
-static inline int atomic_add_short_return(short i, struct atomic_short *v)
+static inline int atom_asr(short i, struct atomic_short *v)
 {
         short __i = i;
         asm volatile(LOCK_PREFIX "xaddw %0, %1"
@@ -494,4 +654,26 @@ static inline int atomic_add_short_return(short i, struct atomic_short *v)
         return i + __i;
 }
 
+/*
+ * conditionally add 1 to *v, unless *v is >= u
+ * return 0 if we cannot add 1 to *v because it is >= u
+ * return 1 if we can add 1 to *v because it is < u
+ * the add is atomic
+ *
+ * This is close to atomic_add_unless(), but this allows the 'u' value
+ * to be lowered below the current 'v'.  atomic_add_unless can only stop
+ * on equal.
+ */
+static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
+{
+        spin_lock(lock);
+        if (atomic_read(v) >= u) {
+                spin_unlock(lock);
+                return 0;
+        }
+        atomic_inc(v);
+        spin_unlock(lock);
+        return 1;
+}
+
 #endif /* _ASM_X86_UV_UV_BAU_H */
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index 4298002d0c83..f26544a15214 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -77,8 +77,9 @@
  *
  *              1111110000000000
  *              5432109876543210
- *              pppppppppplc0cch        Nehalem-EX
- *              ppppppppplcc0cch        Westmere-EX
+ *              pppppppppplc0cch        Nehalem-EX (12 bits in hdw reg)
+ *              ppppppppplcc0cch        Westmere-EX (12 bits in hdw reg)
+ *              pppppppppppcccch        SandyBridge (15 bits in hdw reg)
  *              sssssssssss
  *
  *                      p  = pnode bits
@@ -87,7 +88,7 @@
  *                      h  = hyperthread
  *                      s  = bits that are in the SOCKET_ID CSR
  *
- *      Note: Processor only supports 12 bits in the APICID register. The ACPI
+ *      Note: Processor may support fewer bits in the APICID register. The ACPI
  *            tables hold all 16 bits. Software needs to be aware of this.
  *
  *            Unless otherwise specified, all references to APICID refer to
@@ -138,6 +139,8 @@ struct uv_hub_info_s {
         unsigned long           global_mmr_base;
         unsigned long           gpa_mask;
         unsigned int            gnode_extra;
+        unsigned char           hub_revision;
+        unsigned char           apic_pnode_shift;
         unsigned long           gnode_upper;
         unsigned long           lowmem_remap_top;
         unsigned long           lowmem_remap_base;
@@ -149,13 +152,31 @@ struct uv_hub_info_s {
         unsigned char           m_val;
         unsigned char           n_val;
         struct uv_scir_s        scir;
-        unsigned char           apic_pnode_shift;
 };
 
 DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 #define uv_hub_info             (&__get_cpu_var(__uv_hub_info))
 #define uv_cpu_hub_info(cpu)    (&per_cpu(__uv_hub_info, cpu))
 
+/*
+ * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2
+ * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
+ * This is a software convention - NOT the hardware revision numbers in
+ * the hub chip.
+ */
+#define UV1_HUB_REVISION_BASE           1
+#define UV2_HUB_REVISION_BASE           3
+
+static inline int is_uv1_hub(void)
+{
+        return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
+}
+
+static inline int is_uv2_hub(void)
+{
+        return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE;
+}
+
 union uvh_apicid {
     unsigned long       v;
     struct uvh_apicid_s {
@@ -180,11 +201,25 @@ union uvh_apicid {
 #define UV_PNODE_TO_GNODE(p)            ((p) |uv_hub_info->gnode_extra)
 #define UV_PNODE_TO_NASID(p)            (UV_PNODE_TO_GNODE(p) << 1)
 
-#define UV_LOCAL_MMR_BASE               0xf4000000UL
-#define UV_GLOBAL_MMR32_BASE            0xf8000000UL
+#define UV1_LOCAL_MMR_BASE              0xf4000000UL
+#define UV1_GLOBAL_MMR32_BASE           0xf8000000UL
+#define UV1_LOCAL_MMR_SIZE              (64UL * 1024 * 1024)
+#define UV1_GLOBAL_MMR32_SIZE           (64UL * 1024 * 1024)
+
+#define UV2_LOCAL_MMR_BASE              0xfa000000UL
+#define UV2_GLOBAL_MMR32_BASE           0xfc000000UL
+#define UV2_LOCAL_MMR_SIZE              (32UL * 1024 * 1024)
+#define UV2_GLOBAL_MMR32_SIZE           (32UL * 1024 * 1024)
+
+#define UV_LOCAL_MMR_BASE               (is_uv1_hub() ? UV1_LOCAL_MMR_BASE     \
+                                                : UV2_LOCAL_MMR_BASE)
+#define UV_GLOBAL_MMR32_BASE            (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE  \
+                                                : UV2_GLOBAL_MMR32_BASE)
+#define UV_LOCAL_MMR_SIZE               (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE :   \
+                                                UV2_LOCAL_MMR_SIZE)
+#define UV_GLOBAL_MMR32_SIZE            (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\
+                                                UV2_GLOBAL_MMR32_SIZE)
 #define UV_GLOBAL_MMR64_BASE            (uv_hub_info->global_mmr_base)
-#define UV_LOCAL_MMR_SIZE               (64UL * 1024 * 1024)
-#define UV_GLOBAL_MMR32_SIZE            (64UL * 1024 * 1024)
 
 #define UV_GLOBAL_GRU_MMR_BASE          0x4000000
 
@@ -301,6 +336,17 @@ static inline int uv_apicid_to_pnode(int apicid)
 }
 
 /*
+ * Convert an apicid to the socket number on the blade
+ */
+static inline int uv_apicid_to_socket(int apicid)
+{
+        if (is_uv1_hub())
+                return (apicid >> (uv_hub_info->apic_pnode_shift - 1)) & 1;
+        else
+                return 0;
+}
+
+/*
  * Access global MMRs using the low memory MMR32 space. This region supports
  * faster MMR access but not all MMRs are accessible in this space.
  */
@@ -519,14 +565,13 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
 
 /*
  * Get the minimum revision number of the hub chips within the partition.
- *     1 - initial rev 1.0 silicon
- *     2 - rev 2.0 production silicon
+ *     1 - UV1 rev 1.0 initial silicon
+ *     2 - UV1 rev 2.0 production silicon
+ *     3 - UV2 rev 1.0 initial silicon
  */
 static inline int uv_get_min_hub_revision_id(void)
 {
-        extern int uv_min_hub_revision_id;
-
-        return uv_min_hub_revision_id;
+        return uv_hub_info->hub_revision;
 }
 
 #endif /* CONFIG_X86_64 */
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index f5bb64a823d7..4be52c863448 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -11,13 +11,64 @@
 #ifndef _ASM_X86_UV_UV_MMRS_H
 #define _ASM_X86_UV_UV_MMRS_H
 
+/*
+ * This file contains MMR definitions for both UV1 & UV2 hubs.
+ *
+ * In general, MMR addresses and structures are identical on both hubs.
+ * These MMRs are identified as:
+ *      #define UVH_xxx         <address>
+ *      union uvh_xxx {
+ *              unsigned long       v;
+ *              struct uvh_int_cmpd_s {
+ *              } s;
+ *      };
+ *
+ * If the MMR exists on both hub type but has different addresses or
+ * contents, the MMR definition is similar to:
+ *      #define UV1H_xxx        <uv1 address>
+ *      #define UV2H_xxx        <uv2address>
+ *      #define UVH_xxx         (is_uv1_hub() ? UV1H_xxx : UV2H_xxx)
+ *      union uvh_xxx {
+ *              unsigned long       v;
+ *              struct uv1h_int_cmpd_s {         (Common fields only)
+ *              } s;
+ *              struct uv1h_int_cmpd_s {         (Full UV1 definition)
+ *              } s1;
+ *              struct uv2h_int_cmpd_s {         (Full UV2 definition)
+ *              } s2;
+ *      };
+ *
+ * Only essential difference are enumerated. For example, if the address is
+ * the same for both UV1 & UV2, only a single #define is generated. Likewise,
+ * if the contents is the same for both hubs, only the "s" structure is
+ * generated.
+ *
+ * If the MMR exists on ONLY 1 type of hub, no generic definition is
+ * generated:
+ *      #define UVnH_xxx        <uvn address>
+ *      union uvnh_xxx {
+ *              unsigned long       v;
+ *              struct uvh_int_cmpd_s {
+ *              } sn;
+ *      };
+ */
+
 #define UV_MMR_ENABLE           (1UL << 63)
 
+#define UV1_HUB_PART_NUMBER     0x88a5
+#define UV2_HUB_PART_NUMBER     0x8eb8
+
+/* Compat: if this #define is present, UV headers support UV2 */
+#define UV2_HUB_IS_SUPPORTED    1
+
+/* KABI compat: if this #define is present, KABI hacks are present */
+#define UV2_HUB_KABI_HACKS      1
+
 /* ========================================================================= */
 /*                          UVH_BAU_DATA_BROADCAST                           */
 /* ========================================================================= */
 #define UVH_BAU_DATA_BROADCAST 0x61688UL
-#define UVH_BAU_DATA_BROADCAST_32 0x0440
+#define UVH_BAU_DATA_BROADCAST_32 0x440
 
 #define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
 #define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
@@ -34,7 +85,7 @@ union uvh_bau_data_broadcast_u {
 /*                           UVH_BAU_DATA_CONFIG                             */
 /* ========================================================================= */
 #define UVH_BAU_DATA_CONFIG 0x61680UL
-#define UVH_BAU_DATA_CONFIG_32 0x0438
+#define UVH_BAU_DATA_CONFIG_32 0x438
 
 #define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
 #define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
@@ -73,125 +124,245 @@ union uvh_bau_data_config_u {
 /*                           UVH_EVENT_OCCURRED0                             */
 /* ========================================================================= */
 #define UVH_EVENT_OCCURRED0 0x70000UL
-#define UVH_EVENT_OCCURRED0_32 0x005e8
-
-#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
-#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
-#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
-#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
-#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
-#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
-#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
-#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
-#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
-#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
-#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
-#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
-#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
-#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
-#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
-#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
-#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
-#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
-#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
-#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
-#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
-#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
-#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
-#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
-#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
-#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
-#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
-#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
-#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
-#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
-#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
-#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
-#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
-#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
-#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
-#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
-#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
-#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
-#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
-#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
-#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
-#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
-#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
-#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
-#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
-#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
-#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
-#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
-#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
-#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
-#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
-#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
-#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
-#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
-#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
-#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
-#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
-#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
-#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
-#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
-#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
-#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
-#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
-#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
-#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
-#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
-#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
-#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
-#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
-#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
-#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
-#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
-#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
-#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
-#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
-#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
-#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
+#define UVH_EVENT_OCCURRED0_32 0x5e8
+
+#define UV1H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
+#define UV1H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
+#define UV1H_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
+#define UV1H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
+#define UV1H_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
+#define UV1H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
+#define UV1H_EVENT_OCCURRED0_LH_HCERR_SHFT 3
+#define UV1H_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
+#define UV1H_EVENT_OCCURRED0_RH_HCERR_SHFT 4
+#define UV1H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
+#define UV1H_EVENT_OCCURRED0_XN_HCERR_SHFT 5
+#define UV1H_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
+#define UV1H_EVENT_OCCURRED0_SI_HCERR_SHFT 6
+#define UV1H_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
+#define UV1H_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
+#define UV1H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
+#define UV1H_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
+#define UV1H_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
+#define UV1H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
+#define UV1H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
+#define UV1H_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
+#define UV1H_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
+#define UV1H_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
+#define UV1H_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
+#define UV1H_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
+#define UV1H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
+#define UV1H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
+#define UV1H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
+#define UV1H_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
+#define UV1H_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
+#define UV1H_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
+#define UV1H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
+#define UV1H_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
+#define UV1H_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
+#define UV1H_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
+#define UV1H_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
+#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
+#define UV1H_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
+#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
+#define UV1H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
+#define UV1H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
+#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
+#define UV1H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
+#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
+#define UV1H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
+#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
+#define UV1H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
+#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
+#define UV1H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
+#define UV1H_EVENT_OCCURRED0_LTC_INT_SHFT 43
+#define UV1H_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
+#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
+#define UV1H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
+#define UV1H_EVENT_OCCURRED0_IPI_INT_SHFT 45
+#define UV1H_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
+#define UV1H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
+#define UV1H_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
+#define UV1H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC0_SHFT 51
+#define UV1H_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC1_SHFT 52
+#define UV1H_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC2_SHFT 53
+#define UV1H_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
+#define UV1H_EVENT_OCCURRED0_RTC3_SHFT 54
+#define UV1H_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
+#define UV1H_EVENT_OCCURRED0_BAU_DATA_SHFT 55
+#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
+#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
+#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
+
+#define UV2H_EVENT_OCCURRED0_LB_HCERR_SHFT 0
+#define UV2H_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
+#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
+#define UV2H_EVENT_OCCURRED0_RH_HCERR_SHFT 2
+#define UV2H_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
+#define UV2H_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
+#define UV2H_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
+#define UV2H_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
+#define UV2H_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
+#define UV2H_EVENT_OCCURRED0_GR0_HCERR_SHFT 5
+#define UV2H_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL
+#define UV2H_EVENT_OCCURRED0_GR1_HCERR_SHFT 6
+#define UV2H_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL
+#define UV2H_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
+#define UV2H_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
+#define UV2H_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
+#define UV2H_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
+#define UV2H_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
+#define UV2H_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
+#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
+#define UV2H_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
+#define UV2H_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
+#define UV2H_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
+#define UV2H_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
+#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
+#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
+#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
+#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
+#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
+#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
+#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
+#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
+#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
+#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
+#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
+#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
+#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
+#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
+#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
+#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
+#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
+#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
+#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
+#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
+#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
+#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
+#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
+
 union uvh_event_occurred0_u {
     unsigned long       v;
-    struct uvh_event_occurred0_s {
+    struct uv1h_event_occurred0_s {
         unsigned long   lb_hcerr             :  1;  /* RW, W1C */
         unsigned long   gr0_hcerr            :  1;  /* RW, W1C */
         unsigned long   gr1_hcerr            :  1;  /* RW, W1C */
@@ -250,14 +421,76 @@ union uvh_event_occurred0_u {
         unsigned long   bau_data             :  1;  /* RW, W1C */
         unsigned long   power_management_req :  1;  /* RW, W1C */
         unsigned long   rsvd_57_63           :  7;  /*    */
-    } s;
+    } s1;
+    struct uv2h_event_occurred0_s {
+        unsigned long   lb_hcerr            :  1;  /* RW */
+        unsigned long   qp_hcerr            :  1;  /* RW */
+        unsigned long   rh_hcerr            :  1;  /* RW */
+        unsigned long   lh0_hcerr           :  1;  /* RW */
+        unsigned long   lh1_hcerr           :  1;  /* RW */
+        unsigned long   gr0_hcerr           :  1;  /* RW */
+        unsigned long   gr1_hcerr           :  1;  /* RW */
+        unsigned long   ni0_hcerr           :  1;  /* RW */
+        unsigned long   ni1_hcerr           :  1;  /* RW */
+        unsigned long   lb_aoerr0           :  1;  /* RW */
+        unsigned long   qp_aoerr0           :  1;  /* RW */
+        unsigned long   rh_aoerr0           :  1;  /* RW */
+        unsigned long   lh0_aoerr0          :  1;  /* RW */
+        unsigned long   lh1_aoerr0          :  1;  /* RW */
+        unsigned long   gr0_aoerr0          :  1;  /* RW */
+        unsigned long   gr1_aoerr0          :  1;  /* RW */
+        unsigned long   xb_aoerr0           :  1;  /* RW */
+        unsigned long   rt_aoerr0           :  1;  /* RW */
+        unsigned long   ni0_aoerr0          :  1;  /* RW */
+        unsigned long   ni1_aoerr0          :  1;  /* RW */
+        unsigned long   lb_aoerr1           :  1;  /* RW */
+        unsigned long   qp_aoerr1           :  1;  /* RW */
+        unsigned long   rh_aoerr1           :  1;  /* RW */
+        unsigned long   lh0_aoerr1          :  1;  /* RW */
+        unsigned long   lh1_aoerr1          :  1;  /* RW */
+        unsigned long   gr0_aoerr1          :  1;  /* RW */
+        unsigned long   gr1_aoerr1          :  1;  /* RW */
+        unsigned long   xb_aoerr1           :  1;  /* RW */
+        unsigned long   rt_aoerr1           :  1;  /* RW */
+        unsigned long   ni0_aoerr1          :  1;  /* RW */
+        unsigned long   ni1_aoerr1          :  1;  /* RW */
+        unsigned long   system_shutdown_int :  1;  /* RW */
+        unsigned long   lb_irq_int_0        :  1;  /* RW */
+        unsigned long   lb_irq_int_1        :  1;  /* RW */
+        unsigned long   lb_irq_int_2        :  1;  /* RW */
+        unsigned long   lb_irq_int_3        :  1;  /* RW */
+        unsigned long   lb_irq_int_4        :  1;  /* RW */
+        unsigned long   lb_irq_int_5        :  1;  /* RW */
+        unsigned long   lb_irq_int_6        :  1;  /* RW */
+        unsigned long   lb_irq_int_7        :  1;  /* RW */
+        unsigned long   lb_irq_int_8        :  1;  /* RW */
+        unsigned long   lb_irq_int_9        :  1;  /* RW */
+        unsigned long   lb_irq_int_10       :  1;  /* RW */
+        unsigned long   lb_irq_int_11       :  1;  /* RW */
+        unsigned long   lb_irq_int_12       :  1;  /* RW */
+        unsigned long   lb_irq_int_13       :  1;  /* RW */
+        unsigned long   lb_irq_int_14       :  1;  /* RW */
+        unsigned long   lb_irq_int_15       :  1;  /* RW */
+        unsigned long   l1_nmi_int          :  1;  /* RW */
+        unsigned long   stop_clock          :  1;  /* RW */
+        unsigned long   asic_to_l1          :  1;  /* RW */
+        unsigned long   l1_to_asic          :  1;  /* RW */
+        unsigned long   la_seq_trigger      :  1;  /* RW */
+        unsigned long   ipi_int             :  1;  /* RW */
+        unsigned long   extio_int0          :  1;  /* RW */
+        unsigned long   extio_int1          :  1;  /* RW */
+        unsigned long   extio_int2          :  1;  /* RW */
+        unsigned long   extio_int3          :  1;  /* RW */
+        unsigned long   profile_int         :  1;  /* RW */
+        unsigned long   rsvd_59_63          :  5;  /*    */
+    } s2;
 };
 
 /* ========================================================================= */
 /*                        UVH_EVENT_OCCURRED0_ALIAS                          */
 /* ========================================================================= */
 #define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
-#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
+#define UVH_EVENT_OCCURRED0_ALIAS_32 0x5f0
 
 /* ========================================================================= */
 /*                         UVH_GR0_TLB_INT0_CONFIG                           */
@@ -432,8 +665,16 @@ union uvh_int_cmpb_u {
 /* ========================================================================= */
 #define UVH_INT_CMPC 0x22100UL
 
-#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
-#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
+#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT       0
+#define UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT       0
+#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT        (is_uv1_hub() ?         \
+                        UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT :     \
+                        UV2H_INT_CMPC_REAL_TIME_CMPC_SHFT)
+#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK       0xffffffffffffffUL
+#define UV2H_INT_CMPC_REAL_TIME_CMPC_MASK       0xffffffffffffffUL
+#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK        (is_uv1_hub() ?         \
+                        UV1H_INT_CMPC_REAL_TIME_CMPC_MASK :     \
+                        UV2H_INT_CMPC_REAL_TIME_CMPC_MASK)
 
 union uvh_int_cmpc_u {
     unsigned long       v;
@@ -448,8 +689,16 @@ union uvh_int_cmpc_u {
 /* ========================================================================= */
 #define UVH_INT_CMPD 0x22180UL
 
-#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
-#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
+#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT       0
+#define UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT       0
+#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT        (is_uv1_hub() ?         \
+                        UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT :     \
+                        UV2H_INT_CMPD_REAL_TIME_CMPD_SHFT)
+#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK       0xffffffffffffffUL
+#define UV2H_INT_CMPD_REAL_TIME_CMPD_MASK       0xffffffffffffffUL
+#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK        (is_uv1_hub() ?         \
+                        UV1H_INT_CMPD_REAL_TIME_CMPD_MASK :     \
+                        UV2H_INT_CMPD_REAL_TIME_CMPD_MASK)
 
 union uvh_int_cmpd_u {
     unsigned long       v;
@@ -463,7 +712,7 @@ union uvh_int_cmpd_u {
 /*                               UVH_IPI_INT                                 */
 /* ========================================================================= */
 #define UVH_IPI_INT 0x60500UL
-#define UVH_IPI_INT_32 0x0348
+#define UVH_IPI_INT_32 0x348
 
 #define UVH_IPI_INT_VECTOR_SHFT 0
 #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
@@ -493,7 +742,7 @@ union uvh_ipi_int_u {
 /*                   UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST                     */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -515,7 +764,7 @@ union uvh_lb_bau_intd_payload_queue_first_u {
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST                     */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -533,7 +782,7 @@ union uvh_lb_bau_intd_payload_queue_last_u {
 /*                    UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL                     */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
-#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0
+#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
 
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
 #define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
@@ -551,7 +800,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
 /*                   UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE                    */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
 
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
@@ -585,6 +834,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
+
 union uvh_lb_bau_intd_software_acknowledge_u {
     unsigned long       v;
     struct uvh_lb_bau_intd_software_acknowledge_s {
@@ -612,13 +862,13 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 /*                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS                 */
 /* ========================================================================= */
 #define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
-#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
+#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
 
 /* ========================================================================= */
 /*                         UVH_LB_BAU_MISC_CONTROL                           */
 /* ========================================================================= */
 #define UVH_LB_BAU_MISC_CONTROL 0x320170UL
-#define UVH_LB_BAU_MISC_CONTROL_32 0x00a10
+#define UVH_LB_BAU_MISC_CONTROL_32 0xa10
 
 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
 #define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
@@ -628,8 +878,8 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UVH_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
 #define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
-#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_SHFT 11
-#define UVH_LB_BAU_MISC_CONTROL_CSI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
+#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
 #define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
@@ -650,8 +900,86 @@ union uvh_lb_bau_intd_software_acknowledge_u {
 #define UVH_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
 #define UVH_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
-#define UVH_LB_BAU_MISC_CONTROL_FUN_SHFT 48
-#define UVH_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
+
+#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
+#define UV1H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
+#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
+#define UV1H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
+#define UV1H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
+#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
+#define UV1H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
+#define UV1H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
+#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
+#define UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
+#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
+#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
+#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
+#define UV1H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
+#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
+#define UV1H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
+#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
+#define UV1H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
+#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
+#define UV1H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
+#define UV1H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
+#define UV1H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
+#define UV1H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
+
+#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
+#define UV2H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
+#define UV2H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
+#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
+#define UV2H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
+#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
+#define UV2H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
+#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
+#define UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
+#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
+#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
+#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
+#define UV2H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
+#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
+#define UV2H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
+#define UV2H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
+#define UV2H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
+#define UV2H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
+#define UV2H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
+#define UV2H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
+#define UV2H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
+#define UV2H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
 
 union uvh_lb_bau_misc_control_u {
     unsigned long       v;
@@ -660,7 +988,25 @@ union uvh_lb_bau_misc_control_u {
         unsigned long   apic_mode                          :  1;  /* RW */
         unsigned long   force_broadcast                    :  1;  /* RW */
         unsigned long   force_lock_nop                     :  1;  /* RW */
-        unsigned long   csi_agent_presence_vector          :  3;  /* RW */
+        unsigned long   qpi_agent_presence_vector          :  3;  /* RW */
+        unsigned long   descriptor_fetch_mode              :  1;  /* RW */
+        unsigned long   enable_intd_soft_ack_mode          :  1;  /* RW */
+        unsigned long   intd_soft_ack_timeout_period       :  4;  /* RW */
+        unsigned long   enable_dual_mapping_mode           :  1;  /* RW */
+        unsigned long   vga_io_port_decode_enable          :  1;  /* RW */
+        unsigned long   vga_io_port_16_bit_decode          :  1;  /* RW */
+        unsigned long   suppress_dest_registration         :  1;  /* RW */
+        unsigned long   programmed_initial_priority        :  3;  /* RW */
+        unsigned long   use_incoming_priority              :  1;  /* RW */
+        unsigned long   enable_programmed_initial_priority :  1;  /* RW */
+        unsigned long   rsvd_29_63    : 35;
+    } s;
+    struct uv1h_lb_bau_misc_control_s {
+        unsigned long   rejection_delay                    :  8;  /* RW */
+        unsigned long   apic_mode                          :  1;  /* RW */
+        unsigned long   force_broadcast                    :  1;  /* RW */
+        unsigned long   force_lock_nop                     :  1;  /* RW */
+        unsigned long   qpi_agent_presence_vector          :  3;  /* RW */
         unsigned long   descriptor_fetch_mode              :  1;  /* RW */
         unsigned long   enable_intd_soft_ack_mode          :  1;  /* RW */
         unsigned long   intd_soft_ack_timeout_period       :  4;  /* RW */
@@ -673,14 +1019,40 @@ union uvh_lb_bau_misc_control_u {
         unsigned long   enable_programmed_initial_priority :  1;  /* RW */
         unsigned long   rsvd_29_47                         : 19;  /*    */
         unsigned long   fun                                : 16;  /* RW */
-    } s;
+    } s1;
+    struct uv2h_lb_bau_misc_control_s {
+        unsigned long   rejection_delay                      :  8;  /* RW */
+        unsigned long   apic_mode                            :  1;  /* RW */
+        unsigned long   force_broadcast                      :  1;  /* RW */
+        unsigned long   force_lock_nop                       :  1;  /* RW */
+        unsigned long   qpi_agent_presence_vector            :  3;  /* RW */
+        unsigned long   descriptor_fetch_mode                :  1;  /* RW */
+        unsigned long   enable_intd_soft_ack_mode            :  1;  /* RW */
+        unsigned long   intd_soft_ack_timeout_period         :  4;  /* RW */
+        unsigned long   enable_dual_mapping_mode             :  1;  /* RW */
+        unsigned long   vga_io_port_decode_enable            :  1;  /* RW */
+        unsigned long   vga_io_port_16_bit_decode            :  1;  /* RW */
+        unsigned long   suppress_dest_registration           :  1;  /* RW */
+        unsigned long   programmed_initial_priority          :  3;  /* RW */
+        unsigned long   use_incoming_priority                :  1;  /* RW */
+        unsigned long   enable_programmed_initial_priority   :  1;  /* RW */
+        unsigned long   enable_automatic_apic_mode_selection :  1;  /* RW */
+        unsigned long   apic_mode_status                     :  1;  /* RO */
+        unsigned long   suppress_interrupts_to_self          :  1;  /* RW */
+        unsigned long   enable_lock_based_system_flush       :  1;  /* RW */
+        unsigned long   enable_extended_sb_status            :  1;  /* RW */
+        unsigned long   suppress_int_prio_udt_to_self        :  1;  /* RW */
+        unsigned long   use_legacy_descriptor_formats        :  1;  /* RW */
+        unsigned long   rsvd_36_47                           : 12;  /*    */
+        unsigned long   fun                                  : 16;  /* RW */
+    } s2;
 };
 
 /* ========================================================================= */
 /*                     UVH_LB_BAU_SB_ACTIVATION_CONTROL                      */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
-#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8
+#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
 
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
 #define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
@@ -703,7 +1075,7 @@ union uvh_lb_bau_sb_activation_control_u {
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_0                      */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
 
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
@@ -719,7 +1091,7 @@ union uvh_lb_bau_sb_activation_status_0_u {
 /*                    UVH_LB_BAU_SB_ACTIVATION_STATUS_1                      */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
-#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8
+#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
 
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
 #define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
@@ -735,7 +1107,7 @@ union uvh_lb_bau_sb_activation_status_1_u {
 /*                      UVH_LB_BAU_SB_DESCRIPTOR_BASE                        */
 /* ========================================================================= */
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
-#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0
+#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
 
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
 #define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
@@ -754,23 +1126,6 @@ union uvh_lb_bau_sb_descriptor_base_u {
 };
 
 /* ========================================================================= */
-/*                   UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK                     */
-/* ========================================================================= */
-#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
-#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x009f0
-
-#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
-#define UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
-
-union uvh_lb_target_physical_apic_id_mask_u {
-        unsigned long v;
-        struct uvh_lb_target_physical_apic_id_mask_s {
-                unsigned long bit_enables : 32;  /* RW */
-                unsigned long rsvd_32_63  : 32;  /*    */
-        } s;
-};
-
-/* ========================================================================= */
 /*                               UVH_NODE_ID                                 */
 /* ========================================================================= */
 #define UVH_NODE_ID 0x0UL
@@ -785,10 +1140,36 @@ union uvh_lb_target_physical_apic_id_mask_u {
 #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
 #define UVH_NODE_ID_NODE_ID_SHFT 32
 #define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
-#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
-#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
-#define UVH_NODE_ID_NI_PORT_SHFT 56
-#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
+
+#define UV1H_NODE_ID_FORCE1_SHFT 0
+#define UV1H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
+#define UV1H_NODE_ID_MANUFACTURER_SHFT 1
+#define UV1H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
+#define UV1H_NODE_ID_PART_NUMBER_SHFT 12
+#define UV1H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
+#define UV1H_NODE_ID_REVISION_SHFT 28
+#define UV1H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
+#define UV1H_NODE_ID_NODE_ID_SHFT 32
+#define UV1H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
+#define UV1H_NODE_ID_NODES_PER_BIT_SHFT 48
+#define UV1H_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
+#define UV1H_NODE_ID_NI_PORT_SHFT 56
+#define UV1H_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
+
+#define UV2H_NODE_ID_FORCE1_SHFT 0
+#define UV2H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
+#define UV2H_NODE_ID_MANUFACTURER_SHFT 1
+#define UV2H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
+#define UV2H_NODE_ID_PART_NUMBER_SHFT 12
+#define UV2H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
+#define UV2H_NODE_ID_REVISION_SHFT 28
+#define UV2H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
+#define UV2H_NODE_ID_NODE_ID_SHFT 32
+#define UV2H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
+#define UV2H_NODE_ID_NODES_PER_BIT_SHFT 50
+#define UV2H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
+#define UV2H_NODE_ID_NI_PORT_SHFT 57
+#define UV2H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
 
 union uvh_node_id_u {
     unsigned long       v;
@@ -798,12 +1179,31 @@ union uvh_node_id_u {
         unsigned long   part_number   : 16;  /* RO */
         unsigned long   revision      :  4;  /* RO */
         unsigned long   node_id       : 15;  /* RW */
+        unsigned long   rsvd_47_63    : 17;
+    } s;
+    struct uv1h_node_id_s {
+        unsigned long   force1        :  1;  /* RO */
+        unsigned long   manufacturer  : 11;  /* RO */
+        unsigned long   part_number   : 16;  /* RO */
+        unsigned long   revision      :  4;  /* RO */
+        unsigned long   node_id       : 15;  /* RW */
         unsigned long   rsvd_47       :  1;  /*    */
         unsigned long   nodes_per_bit :  7;  /* RW */
         unsigned long   rsvd_55       :  1;  /*    */
         unsigned long   ni_port       :  4;  /* RO */
         unsigned long   rsvd_60_63    :  4;  /*    */
-    } s;
+    } s1;
+    struct uv2h_node_id_s {
+        unsigned long   force1        :  1;  /* RO */
+        unsigned long   manufacturer  : 11;  /* RO */
+        unsigned long   part_number   : 16;  /* RO */
+        unsigned long   revision      :  4;  /* RO */
+        unsigned long   node_id       : 15;  /* RW */
+        unsigned long   rsvd_47_49    :  3;  /*    */
+        unsigned long   nodes_per_bit :  7;  /* RO */
+        unsigned long   ni_port       :  5;  /* RO */
+        unsigned long   rsvd_62_63    :  2;  /*    */
+    } s2;
 };
 
 /* ========================================================================= */
@@ -954,18 +1354,38 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
 #define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
 #define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
-#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
-#define UVH_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
+
+#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
+#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
+#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
+#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
+#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_SHFT 12
+#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
+
+#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
+#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
+#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
+#define UV2H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
 
 union uvh_rh_gam_config_mmr_u {
     unsigned long       v;
     struct uvh_rh_gam_config_mmr_s {
         unsigned long   m_skt     :  6;  /* RW */
         unsigned long   n_skt     :  4;  /* RW */
+        unsigned long   rsvd_10_63    : 54;
+    } s;
+    struct uv1h_rh_gam_config_mmr_s {
+        unsigned long   m_skt     :  6;  /* RW */
+        unsigned long   n_skt     :  4;  /* RW */
         unsigned long   rsvd_10_11:  2;  /*    */
         unsigned long   mmiol_cfg :  1;  /* RW */
         unsigned long   rsvd_13_63: 51;  /*    */
-    } s;
+    } s1;
+    struct uv2h_rh_gam_config_mmr_s {
+        unsigned long   m_skt :  6;  /* RW */
+        unsigned long   n_skt :  4;  /* RW */
+        unsigned long   rsvd_10_63: 54;  /*    */
+    } s2;
 };
 
 /* ========================================================================= */
@@ -975,25 +1395,49 @@ union uvh_rh_gam_config_mmr_u {
 
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
 #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_gru_overlay_config_mmr_u {
     unsigned long       v;
     struct uvh_rh_gam_gru_overlay_config_mmr_s {
         unsigned long   rsvd_0_27: 28;  /*    */
         unsigned long   base   : 18;  /* RW */
+        unsigned long   rsvd_46_62    : 17;
+        unsigned long   enable :  1;  /* RW */
+    } s;
+    struct uv1h_rh_gam_gru_overlay_config_mmr_s {
+        unsigned long   rsvd_0_27: 28;  /*    */
+        unsigned long   base   : 18;  /* RW */
         unsigned long   rsvd_46_47:  2;  /*    */
         unsigned long   gr4    :  1;  /* RW */
         unsigned long   rsvd_49_51:  3;  /*    */
         unsigned long   n_gru  :  4;  /* RW */
         unsigned long   rsvd_56_62:  7;  /*    */
         unsigned long   enable :  1;  /* RW */
-    } s;
+    } s1;
+    struct uv2h_rh_gam_gru_overlay_config_mmr_s {
+        unsigned long   rsvd_0_27: 28;  /*    */
+        unsigned long   base   : 18;  /* RW */
+        unsigned long   rsvd_46_51:  6;  /*    */
+        unsigned long   n_gru  :  4;  /* RW */
+        unsigned long   rsvd_56_62:  7;  /*    */
+        unsigned long   enable :  1;  /* RW */
+    } s2;
 };
 
 /* ========================================================================= */
@@ -1001,25 +1445,42 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
 /* ========================================================================= */
 #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
 
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff8000000UL
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_mmioh_overlay_config_mmr_u {
     unsigned long       v;
-    struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
+    struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
         unsigned long   rsvd_0_29: 30;  /*    */
         unsigned long   base   : 16;  /* RW */
         unsigned long   m_io   :  6;  /* RW */
         unsigned long   n_io   :  4;  /* RW */
         unsigned long   rsvd_56_62:  7;  /*    */
         unsigned long   enable :  1;  /* RW */
-    } s;
+    } s1;
+    struct uv2h_rh_gam_mmioh_overlay_config_mmr_s {
+        unsigned long   rsvd_0_26: 27;  /*    */
+        unsigned long   base   : 19;  /* RW */
+        unsigned long   m_io   :  6;  /* RW */
+        unsigned long   n_io   :  4;  /* RW */
+        unsigned long   rsvd_56_62:  7;  /*    */
+        unsigned long   enable :  1;  /* RW */
+    } s2;
 };
 
 /* ========================================================================= */
@@ -1029,20 +1490,40 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
 
 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
 #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
-#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
+
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
+#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
 
 union uvh_rh_gam_mmr_overlay_config_mmr_u {
     unsigned long       v;
     struct uvh_rh_gam_mmr_overlay_config_mmr_s {
         unsigned long   rsvd_0_25: 26;  /*    */
         unsigned long   base     : 20;  /* RW */
+        unsigned long   rsvd_46_62    : 17;
+        unsigned long   enable   :  1;  /* RW */
+    } s;
+    struct uv1h_rh_gam_mmr_overlay_config_mmr_s {
+        unsigned long   rsvd_0_25: 26;  /*    */
+        unsigned long   base     : 20;  /* RW */
         unsigned long   dual_hub :  1;  /* RW */
         unsigned long   rsvd_47_62: 16;  /*    */
         unsigned long   enable   :  1;  /* RW */
-    } s;
+    } s1;
+    struct uv2h_rh_gam_mmr_overlay_config_mmr_s {
+        unsigned long   rsvd_0_25: 26;  /*    */
+        unsigned long   base   : 20;  /* RW */
+        unsigned long   rsvd_46_62: 17;  /*    */
+        unsigned long   enable :  1;  /* RW */
+    } s2;
 };
 
 /* ========================================================================= */
@@ -1103,10 +1584,11 @@ union uvh_rtc1_int_config_u {
 /*                               UVH_SCRATCH5                                */
 /* ========================================================================= */
 #define UVH_SCRATCH5 0x2d0200UL
-#define UVH_SCRATCH5_32 0x00778
+#define UVH_SCRATCH5_32 0x778
 
 #define UVH_SCRATCH5_SCRATCH5_SHFT 0
 #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
+
 union uvh_scratch5_u {
     unsigned long       v;
     struct uvh_scratch5_s {
@@ -1114,4 +1596,154 @@ union uvh_scratch5_u {
     } s;
 };
 
+/* ========================================================================= */
+/*                           UV2H_EVENT_OCCURRED2                            */
+/* ========================================================================= */
+#define UV2H_EVENT_OCCURRED2 0x70100UL
+#define UV2H_EVENT_OCCURRED2_32 0xb68
+
+#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
+#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
+#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
+#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
+#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
+#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
+#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
+#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
+#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
+#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
+#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
+#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
+#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
+#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
+#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
+#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
+#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
+#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
+#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
+#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
+#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
+#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
+#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
+#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
+#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
+#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
+#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
+#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
+#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
+#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
+#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
+#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
+#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
+#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
+#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
+#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
+#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
+#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
+#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
+#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
+#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
+#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
+#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
+#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
+#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
+#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
+#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
+#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
+#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
+#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
+#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
+#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
+#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
+#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
+#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
+#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
+#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
+#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
+
+union uv2h_event_occurred2_u {
+    unsigned long       v;
+    struct uv2h_event_occurred2_s {
+        unsigned long   rtc_0  :  1;  /* RW */
+        unsigned long   rtc_1  :  1;  /* RW */
+        unsigned long   rtc_2  :  1;  /* RW */
+        unsigned long   rtc_3  :  1;  /* RW */
+        unsigned long   rtc_4  :  1;  /* RW */
+        unsigned long   rtc_5  :  1;  /* RW */
+        unsigned long   rtc_6  :  1;  /* RW */
+        unsigned long   rtc_7  :  1;  /* RW */
+        unsigned long   rtc_8  :  1;  /* RW */
+        unsigned long   rtc_9  :  1;  /* RW */
+        unsigned long   rtc_10 :  1;  /* RW */
+        unsigned long   rtc_11 :  1;  /* RW */
+        unsigned long   rtc_12 :  1;  /* RW */
+        unsigned long   rtc_13 :  1;  /* RW */
+        unsigned long   rtc_14 :  1;  /* RW */
+        unsigned long   rtc_15 :  1;  /* RW */
+        unsigned long   rtc_16 :  1;  /* RW */
+        unsigned long   rtc_17 :  1;  /* RW */
+        unsigned long   rtc_18 :  1;  /* RW */
+        unsigned long   rtc_19 :  1;  /* RW */
+        unsigned long   rtc_20 :  1;  /* RW */
+        unsigned long   rtc_21 :  1;  /* RW */
+        unsigned long   rtc_22 :  1;  /* RW */
+        unsigned long   rtc_23 :  1;  /* RW */
+        unsigned long   rtc_24 :  1;  /* RW */
+        unsigned long   rtc_25 :  1;  /* RW */
+        unsigned long   rtc_26 :  1;  /* RW */
+        unsigned long   rtc_27 :  1;  /* RW */
+        unsigned long   rtc_28 :  1;  /* RW */
+        unsigned long   rtc_29 :  1;  /* RW */
+        unsigned long   rtc_30 :  1;  /* RW */
+        unsigned long   rtc_31 :  1;  /* RW */
+        unsigned long   rsvd_32_63: 32;  /*    */
+    } s1;
+};
+
+/* ========================================================================= */
+/*                        UV2H_EVENT_OCCURRED2_ALIAS                         */
+/* ========================================================================= */
+#define UV2H_EVENT_OCCURRED2_ALIAS 0x70108UL
+#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
+
+/* ========================================================================= */
+/*                    UV2H_LB_BAU_SB_ACTIVATION_STATUS_2                     */
+/* ========================================================================= */
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
+
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
+#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
+
+union uv2h_lb_bau_sb_activation_status_2_u {
+    unsigned long       v;
+    struct uv2h_lb_bau_sb_activation_status_2_s {
+        unsigned long   aux_error : 64;  /* RW */
+    } s1;
+};
+
+/* ========================================================================= */
+/*                   UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK                    */
+/* ========================================================================= */
+#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK 0x320130UL
+#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_32 0x9f0
+
+#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_SHFT 0
+#define UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK_BIT_ENABLES_MASK 0x00000000ffffffffUL
+
+union uv1h_lb_target_physical_apic_id_mask_u {
+    unsigned long       v;
+    struct uv1h_lb_target_physical_apic_id_mask_s {
+        unsigned long   bit_enables : 32;  /* RW */
+        unsigned long   rsvd_32_63  : 32;  /*    */
+    } s1;
+};
+
+
 #endif /* __ASM_UV_MMRS_X86_H__ */
diff --git a/arch/x86/include/asm/vdso.h b/arch/x86/include/asm/vdso.h
index 9064052b73de..bb0522850b74 100644
--- a/arch/x86/include/asm/vdso.h
+++ b/arch/x86/include/asm/vdso.h
@@ -1,20 +1,6 @@
 #ifndef _ASM_X86_VDSO_H
 #define _ASM_X86_VDSO_H
 
-#ifdef CONFIG_X86_64
-extern const char VDSO64_PRELINK[];
-
-/*
- * Given a pointer to the vDSO image, find the pointer to VDSO64_name
- * as that symbol is defined in the vDSO sources or linker script.
- */
-#define VDSO64_SYMBOL(base, name)                                       \
-({                                                                      \
-        extern const char VDSO64_##name[];                              \
-        (void *)(VDSO64_##name - VDSO64_PRELINK + (unsigned long)(base)); \
-})
-#endif
-
 #if defined CONFIG_X86_32 || defined CONFIG_COMPAT
 extern const char VDSO32_PRELINK[];
 
diff --git a/arch/x86/include/asm/vgtod.h b/arch/x86/include/asm/vgtod.h
index 3d61e204826f..646b4c1ca695 100644
--- a/arch/x86/include/asm/vgtod.h
+++ b/arch/x86/include/asm/vgtod.h
@@ -23,8 +23,6 @@ struct vsyscall_gtod_data {
         struct timespec wall_to_monotonic;
         struct timespec wall_time_coarse;
 };
-extern struct vsyscall_gtod_data __vsyscall_gtod_data
-__section_vsyscall_gtod_data;
 extern struct vsyscall_gtod_data vsyscall_gtod_data;
 
 #endif /* _ASM_X86_VGTOD_H */
diff --git a/arch/x86/include/asm/vsyscall.h b/arch/x86/include/asm/vsyscall.h
index d0983d255fbd..d55597351f6a 100644
--- a/arch/x86/include/asm/vsyscall.h
+++ b/arch/x86/include/asm/vsyscall.h
@@ -16,27 +16,19 @@ enum vsyscall_num {
 #ifdef __KERNEL__
 #include <linux/seqlock.h>
 
-#define __section_vgetcpu_mode __attribute__ ((unused, __section__ (".vgetcpu_mode"), aligned(16)))
-#define __section_jiffies __attribute__ ((unused, __section__ (".jiffies"), aligned(16)))
-
 /* Definitions for CONFIG_GENERIC_TIME definitions */
-#define __section_vsyscall_gtod_data __attribute__ \
-        ((unused, __section__ (".vsyscall_gtod_data"),aligned(16)))
-#define __section_vsyscall_clock __attribute__ \
-        ((unused, __section__ (".vsyscall_clock"),aligned(16)))
 #define __vsyscall_fn \
         __attribute__ ((unused, __section__(".vsyscall_fn"))) notrace
 
 #define VGETCPU_RDTSCP  1
 #define VGETCPU_LSL     2
 
-extern int __vgetcpu_mode;
-extern volatile unsigned long __jiffies;
-
 /* kernel space (writeable) */
 extern int vgetcpu_mode;
 extern struct timezone sys_tz;
 
+#include <asm/vvar.h>
+
 extern void map_vsyscall(void);
 
 #endif /* __KERNEL__ */
diff --git a/arch/x86/include/asm/vvar.h b/arch/x86/include/asm/vvar.h
new file mode 100644
index 000000000000..341b3559452b
--- /dev/null
+++ b/arch/x86/include/asm/vvar.h
@@ -0,0 +1,52 @@
+/*
+ * vvar.h: Shared vDSO/kernel variable declarations
+ * Copyright (c) 2011 Andy Lutomirski
+ * Subject to the GNU General Public License, version 2
+ *
+ * A handful of variables are accessible (read-only) from userspace
+ * code in the vsyscall page and the vdso.  They are declared here.
+ * Some other file must define them with DEFINE_VVAR.
+ *
+ * In normal kernel code, they are used like any other variable.
+ * In user code, they are accessed through the VVAR macro.
+ *
+ * Each of these variables lives in the vsyscall page, and each
+ * one needs a unique offset within the little piece of the page
+ * reserved for vvars.  Specify that offset in DECLARE_VVAR.
+ * (There are 896 bytes available.  If you mess up, the linker will
+ * catch it.)
+ */
+
+/* Offset of vars within vsyscall page */
+#define VSYSCALL_VARS_OFFSET (3072 + 128)
+
+#if defined(__VVAR_KERNEL_LDS)
+
+/* The kernel linker script defines its own magic to put vvars in the
+ * right place.
+ */
+#define DECLARE_VVAR(offset, type, name) \
+        EMIT_VVAR(name, VSYSCALL_VARS_OFFSET + offset)
+
+#else
+
+#define DECLARE_VVAR(offset, type, name)                                \
+        static type const * const vvaraddr_ ## name =                   \
+                (void *)(VSYSCALL_START + VSYSCALL_VARS_OFFSET + (offset));
+
+#define DEFINE_VVAR(type, name)                                         \
+        type __vvar_ ## name                                            \
+        __attribute__((section(".vsyscall_var_" #name), aligned(16)))
+
+#define VVAR(name) (*vvaraddr_ ## name)
+
+#endif
+
+/* DECLARE_VVAR(offset, type, name) */
+
+DECLARE_VVAR(0, volatile unsigned long, jiffies)
+DECLARE_VVAR(8, int, vgetcpu_mode)
+DECLARE_VVAR(128, struct vsyscall_gtod_data, vsyscall_gtod_data)
+
+#undef DECLARE_VVAR
+#undef VSYSCALL_VARS_OFFSET
diff --git a/arch/x86/include/asm/xen/hypercall.h b/arch/x86/include/asm/xen/hypercall.h
index 8508bfe52296..d240ea950519 100644
--- a/arch/x86/include/asm/xen/hypercall.h
+++ b/arch/x86/include/asm/xen/hypercall.h
@@ -447,6 +447,13 @@ HYPERVISOR_hvm_op(int op, void *arg)
        return _hypercall2(unsigned long, hvm_op, op, arg);
 }
 
+static inline int
+HYPERVISOR_tmem_op(
+        struct tmem_op *op)
+{
+        return _hypercall1(int, tmem_op, op);
+}
+
 static inline void
 MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
 {
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 250806472a7e..f5abe3a245b8 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -8,7 +8,6 @@ CPPFLAGS_vmlinux.lds += -U$(UTS_MACHINE)
 
 ifdef CONFIG_FUNCTION_TRACER
 # Do not profile debug and lowlevel utilities
-CFLAGS_REMOVE_tsc.o = -pg
 CFLAGS_REMOVE_rtc.o = -pg
 CFLAGS_REMOVE_paravirt-spinlocks.o = -pg
 CFLAGS_REMOVE_pvclock.o = -pg
@@ -24,13 +23,16 @@ endif
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_vsyscall_64.o    := $(PROFILING) -g0 $(nostackp)
 CFLAGS_hpet.o           := $(nostackp)
-CFLAGS_tsc.o            := $(nostackp)
+CFLAGS_vread_tsc_64.o   := $(nostackp)
 CFLAGS_paravirt.o       := $(nostackp)
 GCOV_PROFILE_vsyscall_64.o      := n
 GCOV_PROFILE_hpet.o             := n
 GCOV_PROFILE_tsc.o              := n
 GCOV_PROFILE_paravirt.o         := n
 
+# vread_tsc_64 is hot and should be fully optimized:
+CFLAGS_REMOVE_vread_tsc_64.o = -pg -fno-optimize-sibling-calls
+
 obj-y                   := process_$(BITS).o signal.o entry_$(BITS).o
 obj-y                   += traps.o irq.o irq_$(BITS).o dumpstack_$(BITS).o
 obj-y                   += time.o ioport.o ldt.o dumpstack.o
@@ -39,7 +41,7 @@ obj-$(CONFIG_IRQ_WORK)  += irq_work.o
 obj-y                   += probe_roms.o
 obj-$(CONFIG_X86_32)    += sys_i386_32.o i386_ksyms_32.o
 obj-$(CONFIG_X86_64)    += sys_x86_64.o x8664_ksyms_64.o
-obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o
+obj-$(CONFIG_X86_64)    += syscall_64.o vsyscall_64.o vread_tsc_64.o
 obj-y                   += bootflag.o e820.o
 obj-y                   += pci-dma.o quirks.o topology.o kdebugfs.o
 obj-y                   += alternative.o i8253.o pci-nommu.o hw_breakpoint.o
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 9488dcff7aec..e5293394b548 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -676,7 +676,7 @@ void mask_ioapic_entries(void)
         int apic, pin;
 
         for (apic = 0; apic < nr_ioapics; apic++) {
-                if (ioapics[apic].saved_registers)
+                if (!ioapics[apic].saved_registers)
                         continue;
 
                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
@@ -699,7 +699,7 @@ int restore_ioapic_entries(void)
         int apic, pin;
 
         for (apic = 0; apic < nr_ioapics; apic++) {
-                if (ioapics[apic].saved_registers)
+                if (!ioapics[apic].saved_registers)
                         continue;
 
                 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index f450b683dfcf..b511a011b7d0 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -91,6 +91,10 @@ static int __init early_get_pnodeid(void)
         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
         uv_min_hub_revision_id = node_id.s.revision;
 
+        if (node_id.s.part_number == UV2_HUB_PART_NUMBER)
+                uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1;
+
+        uv_hub_info->hub_revision = uv_min_hub_revision_id;
         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
         return pnode;
 }
@@ -112,17 +116,25 @@ static void __init early_get_apic_pnode_shift(void)
  */
 static void __init uv_set_apicid_hibit(void)
 {
-        union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
+        union uv1h_lb_target_physical_apic_id_mask_u apicid_mask;
 
-        apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
-        uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
+        if (is_uv1_hub()) {
+                apicid_mask.v =
+                        uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK);
+                uv_apicid_hibits =
+                        apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK;
+        }
 }
 
 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
-        int pnodeid;
+        int pnodeid, is_uv1, is_uv2;
 
-        if (!strcmp(oem_id, "SGI")) {
+        is_uv1 = !strcmp(oem_id, "SGI");
+        is_uv2 = !strcmp(oem_id, "SGI2");
+        if (is_uv1 || is_uv2) {
+                uv_hub_info->hub_revision =
+                        is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE;
                 pnodeid = early_get_pnodeid();
                 early_get_apic_pnode_shift();
                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
@@ -484,12 +496,19 @@ static __init void map_mmr_high(int max_pnode)
 static __init void map_mmioh_high(int max_pnode)
 {
         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
-        int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
+        int shift;
 
         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
-        if (mmioh.s.enable)
-                map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
+        if (is_uv1_hub() && mmioh.s1.enable) {
+                shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
+                map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io,
+                        max_pnode, map_uc);
+        }
+        if (is_uv2_hub() && mmioh.s2.enable) {
+                shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
+                map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io,
                         max_pnode, map_uc);
+        }
 }
 
 static __init void map_low_mmrs(void)
@@ -736,13 +755,14 @@ void __init uv_system_init(void)
         unsigned long mmr_base, present, paddr;
         unsigned short pnode_mask, pnode_io_mask;
 
+        printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2");
         map_low_mmrs();
 
         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
         m_val = m_n_config.s.m_skt;
         n_val = m_n_config.s.n_skt;
         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
-        n_io = mmioh.s.n_io;
+        n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io;
         mmr_base =
             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
             ~UV_MMR_ENABLE;
@@ -811,6 +831,8 @@ void __init uv_system_init(void)
                  */
                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
+                uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
+
                 pnode = uv_apicid_to_pnode(apicid);
                 blade = boot_pnode_to_blade(pnode);
                 lcpu = uv_blade_info[blade].nr_possible_cpus;
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 3bfa02235965..965a7666c283 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -361,6 +361,7 @@ struct apm_user {
  * idle percentage above which bios idle calls are done
  */
 #ifdef CONFIG_APM_CPU_IDLE
+#warning deprecated CONFIG_APM_CPU_IDLE will be deleted in 2012
 #define DEFAULT_IDLE_THRESHOLD  95
 #else
 #define DEFAULT_IDLE_THRESHOLD  100
@@ -904,6 +905,7 @@ static void apm_cpu_idle(void)
         unsigned int jiffies_since_last_check = jiffies - last_jiffies;
         unsigned int bucket;
 
+        WARN_ONCE(1, "deprecated apm_cpu_idle will be deleted in 2012");
 recalc:
         if (jiffies_since_last_check > IDLE_CALC_LIMIT) {
                 use_apm_idle = 0;
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8f5cabb3c5b0..b13ed393dfce 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -612,8 +612,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         }
 #endif
 
-        /* As a rule processors have APIC timer running in deep C states */
-        if (c->x86 > 0xf && !cpu_has_amd_erratum(amd_erratum_400))
+        /*
+         * Family 0x12 and above processors have APIC timer
+         * running in deep C states.
+         */
+        if (c->x86 > 0x11)
                 set_cpu_cap(c, X86_FEATURE_ARAT);
 
         /*
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index c39576cb3018..525514cf33c3 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -19,6 +19,7 @@
 
 static int __init no_halt(char *s)
 {
+        WARN_ONCE(1, "\"no-hlt\" is deprecated, please use \"idle=poll\"\n");
         boot_cpu_data.hlt_works_ok = 0;
         return 1;
 }
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c8b41623377f..22a073d7fbff 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -477,13 +477,6 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
         if (smp_num_siblings <= 1)
                 goto out;
 
-        if (smp_num_siblings > nr_cpu_ids) {
-                pr_warning("CPU: Unsupported number of siblings %d",
-                           smp_num_siblings);
-                smp_num_siblings = 1;
-                return;
-        }
-
         index_msb = get_count_order(smp_num_siblings);
         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
 
@@ -909,7 +902,7 @@ static void vgetcpu_set_mode(void)
 void __init identify_boot_cpu(void)
 {
         identify_cpu(&boot_cpu_data);
-        init_c1e_mask();
+        init_amd_e400_c1e_mask();
 #ifdef CONFIG_X86_32
         sysenter_setup();
         enable_sep_cpu();
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index 0ba15a6cc57e..c9a281f272fd 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -123,7 +123,7 @@ static unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr)
 static atomic_t nmi_running = ATOMIC_INIT(0);
 static int mod_code_status;             /* holds return value of text write */
 static void *mod_code_ip;               /* holds the IP to write to */
-static void *mod_code_newcode;          /* holds the text to write to the IP */
+static const void *mod_code_newcode;    /* holds the text to write to the IP */
 
 static unsigned nmi_wait_count;
 static atomic_t nmi_update_count = ATOMIC_INIT(0);
@@ -225,7 +225,7 @@ within(unsigned long addr, unsigned long start, unsigned long end)
 }
 
 static int
-do_ftrace_mod_code(unsigned long ip, void *new_code)
+do_ftrace_mod_code(unsigned long ip, const void *new_code)
 {
         /*
          * On x86_64, kernel text mappings are mapped read-only with
@@ -266,8 +266,8 @@ static const unsigned char *ftrace_nop_replace(void)
 }
 
 static int
-ftrace_modify_code(unsigned long ip, unsigned char *old_code,
-                   unsigned char *new_code)
+ftrace_modify_code(unsigned long ip, unsigned const char *old_code,
+                   unsigned const char *new_code)
 {
         unsigned char replaced[MCOUNT_INSN_SIZE];
 
@@ -301,7 +301,7 @@ ftrace_modify_code(unsigned long ip, unsigned char *old_code,
 int ftrace_make_nop(struct module *mod,
                     struct dyn_ftrace *rec, unsigned long addr)
 {
-        unsigned char *new, *old;
+        unsigned const char *new, *old;
         unsigned long ip = rec->ip;
 
         old = ftrace_call_replace(ip, addr);
@@ -312,7 +312,7 @@ int ftrace_make_nop(struct module *mod,
 
 int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
 {
-        unsigned char *new, *old;
+        unsigned const char *new, *old;
         unsigned long ip = rec->ip;
 
         old = ftrace_nop_replace();
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 88a90a977f8e..426a5b66f7e4 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -337,7 +337,9 @@ EXPORT_SYMBOL(boot_option_idle_override);
  * Powermanagement idle function, if any..
  */
 void (*pm_idle)(void);
+#if defined(CONFIG_APM_MODULE) && defined(CONFIG_APM_CPU_IDLE)
 EXPORT_SYMBOL(pm_idle);
+#endif
 
 #ifdef CONFIG_X86_32
 /*
@@ -397,7 +399,7 @@ void default_idle(void)
                 cpu_relax();
         }
 }
-#ifdef CONFIG_APM_MODULE
+#if defined(CONFIG_APM_MODULE) && defined(CONFIG_APM_CPU_IDLE)
 EXPORT_SYMBOL(default_idle);
 #endif
 
@@ -535,45 +537,45 @@ int mwait_usable(const struct cpuinfo_x86 *c)
         return (edx & MWAIT_EDX_C1);
 }
 
-bool c1e_detected;
-EXPORT_SYMBOL(c1e_detected);
+bool amd_e400_c1e_detected;
+EXPORT_SYMBOL(amd_e400_c1e_detected);
 
-static cpumask_var_t c1e_mask;
+static cpumask_var_t amd_e400_c1e_mask;
 
-void c1e_remove_cpu(int cpu)
+void amd_e400_remove_cpu(int cpu)
 {
-        if (c1e_mask != NULL)
-                cpumask_clear_cpu(cpu, c1e_mask);
+        if (amd_e400_c1e_mask != NULL)
+                cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
 }
 
 /*
- * C1E aware idle routine. We check for C1E active in the interrupt
+ * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
  * pending message MSR. If we detect C1E, then we handle it the same
  * way as C3 power states (local apic timer and TSC stop)
  */
-static void c1e_idle(void)
+static void amd_e400_idle(void)
 {
         if (need_resched())
                 return;
 
-        if (!c1e_detected) {
+        if (!amd_e400_c1e_detected) {
                 u32 lo, hi;
 
                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 
                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
-                        c1e_detected = true;
+                        amd_e400_c1e_detected = true;
                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
                                 mark_tsc_unstable("TSC halt in AMD C1E");
                         printk(KERN_INFO "System has AMD C1E enabled\n");
                 }
         }
 
-        if (c1e_detected) {
+        if (amd_e400_c1e_detected) {
                 int cpu = smp_processor_id();
 
-                if (!cpumask_test_cpu(cpu, c1e_mask)) {
-                        cpumask_set_cpu(cpu, c1e_mask);
+                if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
+                        cpumask_set_cpu(cpu, amd_e400_c1e_mask);
                         /*
                          * Force broadcast so ACPI can not interfere.
                          */
@@ -616,17 +618,17 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
                 pm_idle = mwait_idle;
         } else if (cpu_has_amd_erratum(amd_erratum_400)) {
                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
-                printk(KERN_INFO "using C1E aware idle routine\n");
-                pm_idle = c1e_idle;
+                printk(KERN_INFO "using AMD E400 aware idle routine\n");
+                pm_idle = amd_e400_idle;
         } else
                 pm_idle = default_idle;
 }
 
-void __init init_c1e_mask(void)
+void __init init_amd_e400_c1e_mask(void)
 {
-        /* If we're using c1e_idle, we need to allocate c1e_mask. */
-        if (pm_idle == c1e_idle)
-                zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
+        /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
+        if (pm_idle == amd_e400_idle)
+                zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
 }
 
 static int __init idle_setup(char *str)
@@ -640,6 +642,7 @@ static int __init idle_setup(char *str)
                 boot_option_idle_override = IDLE_POLL;
         } else if (!strcmp(str, "mwait")) {
                 boot_option_idle_override = IDLE_FORCE_MWAIT;
+                WARN_ONCE(1, "\idle=mwait\" will be removed in 2012\"\n");
         } else if (!strcmp(str, "halt")) {
                 /*
                  * When the boot option of idle=halt is added, halt is
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index f65e5b521dbd..807c2a2b80f1 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -1363,7 +1363,7 @@ void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
  * We must return the syscall number to actually look up in the table.
  * This can be -1L to skip running any syscall at all.
  */
-asmregparm long syscall_trace_enter(struct pt_regs *regs)
+long syscall_trace_enter(struct pt_regs *regs)
 {
         long ret = 0;
 
@@ -1408,7 +1408,7 @@ asmregparm long syscall_trace_enter(struct pt_regs *regs)
         return ret ?: regs->orig_ax;
 }
 
-asmregparm void syscall_trace_leave(struct pt_regs *regs)
+void syscall_trace_leave(struct pt_regs *regs)
 {
         bool step;
 
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 605e5ae19c7f..afaf38447ef5 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -910,6 +910,13 @@ void __init setup_arch(char **cmdline_p)
         memblock.current_limit = get_max_mapped();
         memblock_x86_fill();
 
+        /*
+         * The EFI specification says that boot service code won't be called
+         * after ExitBootServices(). This is, in fact, a lie.
+         */
+        if (efi_enabled)
+                efi_reserve_boot_services();
+
         /* preallocate 4k for mptable mpc */
         early_reserve_e820_mpc_new();
 
@@ -946,6 +953,8 @@ void __init setup_arch(char **cmdline_p)
         if (init_ohci1394_dma_early)
                 init_ohci1394_dma_on_all_controllers();
 #endif
+        /* Allocate bigger log buffer */
+        setup_log_buf(1);
 
         reserve_initrd();
 
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index a3c430bdfb60..eefd96765e79 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1307,7 +1307,7 @@ void play_dead_common(void)
 {
         idle_task_exit();
         reset_lazy_tlbstate();
-        c1e_remove_cpu(raw_smp_processor_id());
+        amd_e400_remove_cpu(raw_smp_processor_id());
 
         mb();
         /* Ack it */
diff --git a/arch/x86/kernel/syscall_table_32.S b/arch/x86/kernel/syscall_table_32.S
index 32cbffb0c494..fbb0a045a1a2 100644
--- a/arch/x86/kernel/syscall_table_32.S
+++ b/arch/x86/kernel/syscall_table_32.S
@@ -345,3 +345,4 @@ ENTRY(sys_call_table)
         .long sys_clock_adjtime
         .long sys_syncfs
         .long sys_sendmmsg              /* 345 */
+        .long sys_setns
diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c
index 998e972f3b1a..30ac65df7d4e 100644
--- a/arch/x86/kernel/tboot.c
+++ b/arch/x86/kernel/tboot.c
@@ -110,7 +110,6 @@ static struct mm_struct tboot_mm = {
         .mmap_sem       = __RWSEM_INITIALIZER(init_mm.mmap_sem),
         .page_table_lock =  __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock),
         .mmlist         = LIST_HEAD_INIT(init_mm.mmlist),
-        .cpu_vm_mask    = CPU_MASK_ALL,
 };
 
 static inline void switch_to_tboot_pt(void)
diff --git a/arch/x86/kernel/time.c b/arch/x86/kernel/time.c
index 25a28a245937..00cbb272627f 100644
--- a/arch/x86/kernel/time.c
+++ b/arch/x86/kernel/time.c
@@ -23,7 +23,7 @@
 #include <asm/time.h>
 
 #ifdef CONFIG_X86_64
-volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;
+DEFINE_VVAR(volatile unsigned long, jiffies) = INITIAL_JIFFIES;
 #endif
 
 unsigned long profile_pc(struct pt_regs *regs)
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 9335bf7dd2e7..6cc6922262af 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -763,25 +763,6 @@ static cycle_t read_tsc(struct clocksource *cs)
                 ret : clocksource_tsc.cycle_last;
 }
 
-#ifdef CONFIG_X86_64
-static cycle_t __vsyscall_fn vread_tsc(void)
-{
-        cycle_t ret;
-
-        /*
-         * Surround the RDTSC by barriers, to make sure it's not
-         * speculated to outside the seqlock critical section and
-         * does not cause time warps:
-         */
-        rdtsc_barrier();
-        ret = (cycle_t)vget_cycles();
-        rdtsc_barrier();
-
-        return ret >= __vsyscall_gtod_data.clock.cycle_last ?
-                ret : __vsyscall_gtod_data.clock.cycle_last;
-}
-#endif
-
 static void resume_tsc(struct clocksource *cs)
 {
         clocksource_tsc.cycle_last = 0;
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 49927a863cc1..89aed99aafce 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -161,6 +161,12 @@ SECTIONS
 
 #define VVIRT_OFFSET (VSYSCALL_ADDR - __vsyscall_0)
 #define VVIRT(x) (ADDR(x) - VVIRT_OFFSET)
+#define EMIT_VVAR(x, offset) .vsyscall_var_ ## x        \
+        ADDR(.vsyscall_0) + offset                      \
+        : AT(VLOAD(.vsyscall_var_ ## x)) {              \
+                *(.vsyscall_var_ ## x)                  \
+        }                                               \
+        x = VVIRT(.vsyscall_var_ ## x);
 
         . = ALIGN(4096);
         __vsyscall_0 = .;
@@ -175,18 +181,6 @@ SECTIONS
                 *(.vsyscall_fn)
         }
 
-        . = ALIGN(L1_CACHE_BYTES);
-        .vsyscall_gtod_data : AT(VLOAD(.vsyscall_gtod_data)) {
-                *(.vsyscall_gtod_data)
-        }
-
-        vsyscall_gtod_data = VVIRT(.vsyscall_gtod_data);
-        .vsyscall_clock : AT(VLOAD(.vsyscall_clock)) {
-                *(.vsyscall_clock)
-        }
-        vsyscall_clock = VVIRT(.vsyscall_clock);
-
-
         .vsyscall_1 ADDR(.vsyscall_0) + 1024: AT(VLOAD(.vsyscall_1)) {
                 *(.vsyscall_1)
         }
@@ -194,21 +188,14 @@ SECTIONS
                 *(.vsyscall_2)
         }
 
-        .vgetcpu_mode : AT(VLOAD(.vgetcpu_mode)) {
-                *(.vgetcpu_mode)
-        }
-        vgetcpu_mode = VVIRT(.vgetcpu_mode);
-
-        . = ALIGN(L1_CACHE_BYTES);
-        .jiffies : AT(VLOAD(.jiffies)) {
-                *(.jiffies)
-        }
-        jiffies = VVIRT(.jiffies);
-
         .vsyscall_3 ADDR(.vsyscall_0) + 3072: AT(VLOAD(.vsyscall_3)) {
                 *(.vsyscall_3)
         }
 
+#define __VVAR_KERNEL_LDS
+#include <asm/vvar.h>
+#undef __VVAR_KERNEL_LDS
+
         . = __vsyscall_0 + PAGE_SIZE;
 
 #undef VSYSCALL_ADDR
@@ -216,6 +203,7 @@ SECTIONS
 #undef VLOAD
 #undef VVIRT_OFFSET
 #undef VVIRT
+#undef EMIT_VVAR
 
 #endif /* CONFIG_X86_64 */
 
@@ -326,7 +314,7 @@ SECTIONS
         }
 
 #if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP)
-        PERCPU(INTERNODE_CACHE_BYTES, PAGE_SIZE)
+        PERCPU_SECTION(INTERNODE_CACHE_BYTES)
 #endif
 
         . = ALIGN(PAGE_SIZE);
diff --git a/arch/x86/kernel/vread_tsc_64.c b/arch/x86/kernel/vread_tsc_64.c
new file mode 100644
index 000000000000..a81aa9e9894c
--- /dev/null
+++ b/arch/x86/kernel/vread_tsc_64.c
@@ -0,0 +1,36 @@
+/* This code runs in userspace. */
+
+#define DISABLE_BRANCH_PROFILING
+#include <asm/vgtod.h>
+
+notrace cycle_t __vsyscall_fn vread_tsc(void)
+{
+        cycle_t ret;
+        u64 last;
+
+        /*
+         * Empirically, a fence (of type that depends on the CPU)
+         * before rdtsc is enough to ensure that rdtsc is ordered
+         * with respect to loads.  The various CPU manuals are unclear
+         * as to whether rdtsc can be reordered with later loads,
+         * but no one has ever seen it happen.
+         */
+        rdtsc_barrier();
+        ret = (cycle_t)vget_cycles();
+
+        last = VVAR(vsyscall_gtod_data).clock.cycle_last;
+
+        if (likely(ret >= last))
+                return ret;
+
+        /*
+         * GCC likes to generate cmov here, but this branch is extremely
+         * predictable (it's just a funciton of time and the likely is
+         * very likely) and there's a data dependence, so force GCC
+         * to generate a branch instead.  I don't barrier() because
+         * we don't actually need a barrier, and if this function
+         * ever gets inlined it will generate worse code.
+         */
+        asm volatile ("");
+        return last;
+}
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index dcbb28c4b694..3e682184d76c 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -49,17 +49,10 @@
                 __attribute__ ((unused, __section__(".vsyscall_" #nr))) notrace
 #define __syscall_clobber "r11","cx","memory"
 
-/*
- * vsyscall_gtod_data contains data that is :
- * - readonly from vsyscalls
- * - written by timer interrupt or systcl (/proc/sys/kernel/vsyscall64)
- * Try to keep this structure as small as possible to avoid cache line ping pongs
- */
-int __vgetcpu_mode __section_vgetcpu_mode;
-
-struct vsyscall_gtod_data __vsyscall_gtod_data __section_vsyscall_gtod_data =
+DEFINE_VVAR(int, vgetcpu_mode);
+DEFINE_VVAR(struct vsyscall_gtod_data, vsyscall_gtod_data) =
 {
-        .lock = SEQLOCK_UNLOCKED,
+        .lock = __SEQLOCK_UNLOCKED(__vsyscall_gtod_data.lock),
         .sysctl_enabled = 1,
 };
 
@@ -97,7 +90,7 @@ void update_vsyscall(struct timespec *wall_time, struct timespec *wtm,
  */
 static __always_inline void do_get_tz(struct timezone * tz)
 {
-        *tz = __vsyscall_gtod_data.sys_tz;
+        *tz = VVAR(vsyscall_gtod_data).sys_tz;
 }
 
 static __always_inline int gettimeofday(struct timeval *tv, struct timezone *tz)
@@ -126,23 +119,24 @@ static __always_inline void do_vgettimeofday(struct timeval * tv)
         unsigned long mult, shift, nsec;
         cycle_t (*vread)(void);
         do {
-                seq = read_seqbegin(&__vsyscall_gtod_data.lock);
+                seq = read_seqbegin(&VVAR(vsyscall_gtod_data).lock);
 
-                vread = __vsyscall_gtod_data.clock.vread;
-                if (unlikely(!__vsyscall_gtod_data.sysctl_enabled || !vread)) {
+                vread = VVAR(vsyscall_gtod_data).clock.vread;
+                if (unlikely(!VVAR(vsyscall_gtod_data).sysctl_enabled ||
+                             !vread)) {
                         gettimeofday(tv,NULL);
                         return;
                 }
 
                 now = vread();
-                base = __vsyscall_gtod_data.clock.cycle_last;
-                mask = __vsyscall_gtod_data.clock.mask;
-                mult = __vsyscall_gtod_data.clock.mult;
-                shift = __vsyscall_gtod_data.clock.shift;
+                base = VVAR(vsyscall_gtod_data).clock.cycle_last;
+                mask = VVAR(vsyscall_gtod_data).clock.mask;
+                mult = VVAR(vsyscall_gtod_data).clock.mult;
+                shift = VVAR(vsyscall_gtod_data).clock.shift;
 
-                tv->tv_sec = __vsyscall_gtod_data.wall_time_sec;
-                nsec = __vsyscall_gtod_data.wall_time_nsec;
-        } while (read_seqretry(&__vsyscall_gtod_data.lock, seq));
+                tv->tv_sec = VVAR(vsyscall_gtod_data).wall_time_sec;
+                nsec = VVAR(vsyscall_gtod_data).wall_time_nsec;
+        } while (read_seqretry(&VVAR(vsyscall_gtod_data).lock, seq));
 
         /* calculate interval: */
         cycle_delta = (now - base) & mask;
@@ -171,15 +165,15 @@ time_t __vsyscall(1) vtime(time_t *t)
 {
         unsigned seq;
         time_t result;
-        if (unlikely(!__vsyscall_gtod_data.sysctl_enabled))
+        if (unlikely(!VVAR(vsyscall_gtod_data).sysctl_enabled))
                 return time_syscall(t);
 
         do {
-                seq = read_seqbegin(&__vsyscall_gtod_data.lock);
+                seq = read_seqbegin(&VVAR(vsyscall_gtod_data).lock);
 
-                result = __vsyscall_gtod_data.wall_time_sec;
+                result = VVAR(vsyscall_gtod_data).wall_time_sec;
 
-        } while (read_seqretry(&__vsyscall_gtod_data.lock, seq));
+        } while (read_seqretry(&VVAR(vsyscall_gtod_data).lock, seq));
 
         if (t)
                 *t = result;
@@ -208,9 +202,9 @@ vgetcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *tcache)
            We do this here because otherwise user space would do it on
            its own in a likely inferior way (no access to jiffies).
            If you don't like it pass NULL. */
-        if (tcache && tcache->blob[0] == (j = __jiffies)) {
+        if (tcache && tcache->blob[0] == (j = VVAR(jiffies))) {
                 p = tcache->blob[1];
-        } else if (__vgetcpu_mode == VGETCPU_RDTSCP) {
+        } else if (VVAR(vgetcpu_mode) == VGETCPU_RDTSCP) {
                 /* Load per CPU data from RDTSCP */
                 native_read_tscp(&p);
         } else {
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 28418054b880..bd14bb4c8594 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -3545,10 +3545,11 @@ static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
         return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
 }
 
-static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
+static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
 {
         struct kvm *kvm;
         struct kvm *kvm_freed = NULL;
+        int nr_to_scan = sc->nr_to_scan;
 
         if (nr_to_scan == 0)
                 goto out;
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index bcb394dfbb35..2dbf6bf4c7e5 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -823,16 +823,30 @@ do_sigbus(struct pt_regs *regs, unsigned long error_code, unsigned long address,
         force_sig_info_fault(SIGBUS, code, address, tsk, fault);
 }
 
-static noinline void
+static noinline int
 mm_fault_error(struct pt_regs *regs, unsigned long error_code,
                unsigned long address, unsigned int fault)
 {
+        /*
+         * Pagefault was interrupted by SIGKILL. We have no reason to
+         * continue pagefault.
+         */
+        if (fatal_signal_pending(current)) {
+                if (!(fault & VM_FAULT_RETRY))
+                        up_read(&current->mm->mmap_sem);
+                if (!(error_code & PF_USER))
+                        no_context(regs, error_code, address);
+                return 1;
+        }
+        if (!(fault & VM_FAULT_ERROR))
+                return 0;
+
         if (fault & VM_FAULT_OOM) {
                 /* Kernel mode? Handle exceptions or die: */
                 if (!(error_code & PF_USER)) {
                         up_read(&current->mm->mmap_sem);
                         no_context(regs, error_code, address);
-                        return;
+                        return 1;
                 }
 
                 out_of_memory(regs, error_code, address);
@@ -843,6 +857,7 @@ mm_fault_error(struct pt_regs *regs, unsigned long error_code,
                 else
                         BUG();
         }
+        return 1;
 }
 
 static int spurious_fault_check(unsigned long error_code, pte_t *pte)
@@ -965,7 +980,7 @@ do_page_fault(struct pt_regs *regs, unsigned long error_code)
         struct mm_struct *mm;
         int fault;
         int write = error_code & PF_WRITE;
-        unsigned int flags = FAULT_FLAG_ALLOW_RETRY |
+        unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
                                         (write ? FAULT_FLAG_WRITE : 0);
 
         tsk = current;
@@ -1133,9 +1148,9 @@ good_area:
          */
         fault = handle_mm_fault(mm, vma, address, flags);
 
-        if (unlikely(fault & VM_FAULT_ERROR)) {
-                mm_fault_error(regs, error_code, address, fault);
-                return;
+        if (unlikely(fault & (VM_FAULT_RETRY|VM_FAULT_ERROR))) {
+                if (mm_fault_error(regs, error_code, address, fault))
+                        return;
         }
 
         /*
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index d4203988504a..f581a18c0d4d 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -72,7 +72,7 @@ static void huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
         if (!vma_shareable(vma, addr))
                 return;
 
-        spin_lock(&mapping->i_mmap_lock);
+        mutex_lock(&mapping->i_mmap_mutex);
         vma_prio_tree_foreach(svma, &iter, &mapping->i_mmap, idx, idx) {
                 if (svma == vma)
                         continue;
@@ -97,7 +97,7 @@ static void huge_pmd_share(struct mm_struct *mm, unsigned long addr, pud_t *pud)
                 put_page(virt_to_page(spte));
         spin_unlock(&mm->page_table_lock);
 out:
-        spin_unlock(&mapping->i_mmap_lock);
+        mutex_unlock(&mapping->i_mmap_mutex);
 }
 
 /*
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 37b8b0fe8320..30326443ab81 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -16,8 +16,6 @@
 #include <asm/tlb.h>
 #include <asm/proto.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 unsigned long __initdata pgt_buf_start;
 unsigned long __meminitdata pgt_buf_end;
 unsigned long __meminitdata pgt_buf_top;
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index c3b8e24f2b16..9fd8a567fe1e 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -316,16 +316,23 @@ static void op_amd_stop_ibs(void)
                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 }
 
-static inline int eilvt_is_available(int offset)
+static inline int get_eilvt(int offset)
 {
-        /* check if we may assign a vector */
         return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
 }
 
+static inline int put_eilvt(int offset)
+{
+        return !setup_APIC_eilvt(offset, 0, 0, 1);
+}
+
 static inline int ibs_eilvt_valid(void)
 {
         int offset;
         u64 val;
+        int valid = 0;
+
+        preempt_disable();
 
         rdmsrl(MSR_AMD64_IBSCTL, val);
         offset = val & IBSCTL_LVT_OFFSET_MASK;
@@ -333,16 +340,20 @@ static inline int ibs_eilvt_valid(void)
         if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
                 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
                        smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
-                return 0;
+                goto out;
         }
 
-        if (!eilvt_is_available(offset)) {
+        if (!get_eilvt(offset)) {
                 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
                        smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
-                return 0;
+                goto out;
         }
 
-        return 1;
+        valid = 1;
+out:
+        preempt_enable();
+
+        return valid;
 }
 
 static inline int get_ibs_offset(void)
@@ -600,67 +611,69 @@ static int setup_ibs_ctl(int ibs_eilvt_off)
 
 static int force_ibs_eilvt_setup(void)
 {
-        int i;
+        int offset;
         int ret;
 
-        /* find the next free available EILVT entry */
-        for (i = 1; i < 4; i++) {
-                if (!eilvt_is_available(i))
-                        continue;
-                ret = setup_ibs_ctl(i);
-                if (ret)
-                        return ret;
-                pr_err(FW_BUG "using offset %d for IBS interrupts\n", i);
-                return 0;
+        /*
+         * find the next free available EILVT entry, skip offset 0,
+         * pin search to this cpu
+         */
+        preempt_disable();
+        for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
+                if (get_eilvt(offset))
+                        break;
         }
+        preempt_enable();
 
-        printk(KERN_DEBUG "No EILVT entry available\n");
-
-        return -EBUSY;
-}
-
-static int __init_ibs_nmi(void)
-{
-        int ret;
-
-        if (ibs_eilvt_valid())
-                return 0;
+        if (offset == APIC_EILVT_NR_MAX) {
+                printk(KERN_DEBUG "No EILVT entry available\n");
+                return -EBUSY;
+        }
 
-        ret = force_ibs_eilvt_setup();
+        ret = setup_ibs_ctl(offset);
         if (ret)
-                return ret;
+                goto out;
 
-        if (!ibs_eilvt_valid())
-                return -EFAULT;
+        if (!ibs_eilvt_valid()) {
+                ret = -EFAULT;
+                goto out;
+        }
 
+        pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
         pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
 
         return 0;
+out:
+        preempt_disable();
+        put_eilvt(offset);
+        preempt_enable();
+        return ret;
 }
 
 /*
  * check and reserve APIC extended interrupt LVT offset for IBS if
  * available
- *
- * init_ibs() preforms implicitly cpu-local operations, so pin this
- * thread to its current CPU
  */
 
 static void init_ibs(void)
 {
-        preempt_disable();
-
         ibs_caps = get_ibs_caps();
+
         if (!ibs_caps)
+                return;
+
+        if (ibs_eilvt_valid())
                 goto out;
 
-        if (__init_ibs_nmi() < 0)
-                ibs_caps = 0;
-        else
-                printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
+        if (!force_ibs_eilvt_setup())
+                goto out;
+
+        /* Failed to setup ibs */
+        ibs_caps = 0;
+        return;
 
 out:
-        preempt_enable();
+        printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", ibs_caps);
 }
 
 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
index b30aa26a8df2..0d3a4fa34560 100644
--- a/arch/x86/platform/efi/efi.c
+++ b/arch/x86/platform/efi/efi.c
@@ -304,6 +304,40 @@ static void __init print_efi_memmap(void)
 }
 #endif  /*  EFI_DEBUG  */
 
+void __init efi_reserve_boot_services(void)
+{
+        void *p;
+
+        for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
+                efi_memory_desc_t *md = p;
+                unsigned long long start = md->phys_addr;
+                unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
+
+                if (md->type != EFI_BOOT_SERVICES_CODE &&
+                    md->type != EFI_BOOT_SERVICES_DATA)
+                        continue;
+
+                memblock_x86_reserve_range(start, start + size, "EFI Boot");
+        }
+}
+
+static void __init efi_free_boot_services(void)
+{
+        void *p;
+
+        for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
+                efi_memory_desc_t *md = p;
+                unsigned long long start = md->phys_addr;
+                unsigned long long size = md->num_pages << EFI_PAGE_SHIFT;
+
+                if (md->type != EFI_BOOT_SERVICES_CODE &&
+                    md->type != EFI_BOOT_SERVICES_DATA)
+                        continue;
+
+                free_bootmem_late(start, size);
+        }
+}
+
 void __init efi_init(void)
 {
         efi_config_table_t *config_tables;
@@ -536,7 +570,9 @@ void __init efi_enter_virtual_mode(void)
 
         for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
                 md = p;
-                if (!(md->attribute & EFI_MEMORY_RUNTIME))
+                if (!(md->attribute & EFI_MEMORY_RUNTIME) &&
+                    md->type != EFI_BOOT_SERVICES_CODE &&
+                    md->type != EFI_BOOT_SERVICES_DATA)
                         continue;
 
                 size = md->num_pages << EFI_PAGE_SHIFT;
@@ -593,6 +629,13 @@ void __init efi_enter_virtual_mode(void)
         }
 
         /*
+         * Thankfully, it does seem that no runtime services other than
+         * SetVirtualAddressMap() will touch boot services code, so we can
+         * get rid of it all at this point
+         */
+        efi_free_boot_services();
+
+        /*
          * Now that EFI is in virtual mode, update the function
          * pointers in the runtime service table to the new virtual addresses.
          *
diff --git a/arch/x86/platform/efi/efi_64.c b/arch/x86/platform/efi/efi_64.c
index 2649426a7905..ac3aa54e2654 100644
--- a/arch/x86/platform/efi/efi_64.c
+++ b/arch/x86/platform/efi/efi_64.c
@@ -49,10 +49,11 @@ static void __init early_code_mapping_set_exec(int executable)
         if (!(__supported_pte_mask & _PAGE_NX))
                 return;
 
-        /* Make EFI runtime service code area executable */
+        /* Make EFI service code area executable */
         for (p = memmap.map; p < memmap.map_end; p += memmap.desc_size) {
                 md = p;
-                if (md->type == EFI_RUNTIME_SERVICES_CODE)
+                if (md->type == EFI_RUNTIME_SERVICES_CODE ||
+                    md->type == EFI_BOOT_SERVICES_CODE)
                         efi_set_executable(md, executable);
         }
 }
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index c58e0ea39ef5..68e467f69fec 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -1,7 +1,7 @@
 /*
  *      SGI UltraViolet TLB flush routines.
  *
- *      (c) 2008-2010 Cliff Wickman <cpw@sgi.com>, SGI.
+ *      (c) 2008-2011 Cliff Wickman <cpw@sgi.com>, SGI.
  *
  *      This code is released under the GNU General Public License version 2 or
  *      later.
@@ -35,6 +35,7 @@ static int timeout_base_ns[] = {
                 5242880,
                 167772160
 };
+
 static int timeout_us;
 static int nobau;
 static int baudisabled;
@@ -42,20 +43,70 @@ static spinlock_t disable_lock;
 static cycles_t congested_cycles;
 
 /* tunables: */
-static int max_bau_concurrent = MAX_BAU_CONCURRENT;
-static int max_bau_concurrent_constant = MAX_BAU_CONCURRENT;
-static int plugged_delay = PLUGGED_DELAY;
-static int plugsb4reset = PLUGSB4RESET;
-static int timeoutsb4reset = TIMEOUTSB4RESET;
-static int ipi_reset_limit = IPI_RESET_LIMIT;
-static int complete_threshold = COMPLETE_THRESHOLD;
-static int congested_response_us = CONGESTED_RESPONSE_US;
-static int congested_reps = CONGESTED_REPS;
-static int congested_period = CONGESTED_PERIOD;
+static int max_concurr          = MAX_BAU_CONCURRENT;
+static int max_concurr_const    = MAX_BAU_CONCURRENT;
+static int plugged_delay        = PLUGGED_DELAY;
+static int plugsb4reset         = PLUGSB4RESET;
+static int timeoutsb4reset      = TIMEOUTSB4RESET;
+static int ipi_reset_limit      = IPI_RESET_LIMIT;
+static int complete_threshold   = COMPLETE_THRESHOLD;
+static int congested_respns_us  = CONGESTED_RESPONSE_US;
+static int congested_reps       = CONGESTED_REPS;
+static int congested_period     = CONGESTED_PERIOD;
+
+static struct tunables tunables[] = {
+        {&max_concurr, MAX_BAU_CONCURRENT}, /* must be [0] */
+        {&plugged_delay, PLUGGED_DELAY},
+        {&plugsb4reset, PLUGSB4RESET},
+        {&timeoutsb4reset, TIMEOUTSB4RESET},
+        {&ipi_reset_limit, IPI_RESET_LIMIT},
+        {&complete_threshold, COMPLETE_THRESHOLD},
+        {&congested_respns_us, CONGESTED_RESPONSE_US},
+        {&congested_reps, CONGESTED_REPS},
+        {&congested_period, CONGESTED_PERIOD}
+};
+
 static struct dentry *tunables_dir;
 static struct dentry *tunables_file;
 
-static int __init setup_nobau(char *arg)
+/* these correspond to the statistics printed by ptc_seq_show() */
+static char *stat_description[] = {
+        "sent:     number of shootdown messages sent",
+        "stime:    time spent sending messages",
+        "numuvhubs: number of hubs targeted with shootdown",
+        "numuvhubs16: number times 16 or more hubs targeted",
+        "numuvhubs8: number times 8 or more hubs targeted",
+        "numuvhubs4: number times 4 or more hubs targeted",
+        "numuvhubs2: number times 2 or more hubs targeted",
+        "numuvhubs1: number times 1 hub targeted",
+        "numcpus:  number of cpus targeted with shootdown",
+        "dto:      number of destination timeouts",
+        "retries:  destination timeout retries sent",
+        "rok:   :  destination timeouts successfully retried",
+        "resetp:   ipi-style resource resets for plugs",
+        "resett:   ipi-style resource resets for timeouts",
+        "giveup:   fall-backs to ipi-style shootdowns",
+        "sto:      number of source timeouts",
+        "bz:       number of stay-busy's",
+        "throt:    number times spun in throttle",
+        "swack:   image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE",
+        "recv:     shootdown messages received",
+        "rtime:    time spent processing messages",
+        "all:      shootdown all-tlb messages",
+        "one:      shootdown one-tlb messages",
+        "mult:     interrupts that found multiple messages",
+        "none:     interrupts that found no messages",
+        "retry:    number of retry messages processed",
+        "canc:     number messages canceled by retries",
+        "nocan:    number retries that found nothing to cancel",
+        "reset:    number of ipi-style reset requests processed",
+        "rcan:     number messages canceled by reset requests",
+        "disable:  number times use of the BAU was disabled",
+        "enable:   number times use of the BAU was re-enabled"
+};
+
+static int __init
+setup_nobau(char *arg)
 {
         nobau = 1;
         return 0;
@@ -63,7 +114,7 @@ static int __init setup_nobau(char *arg)
 early_param("nobau", setup_nobau);
 
 /* base pnode in this partition */
-static int uv_partition_base_pnode __read_mostly;
+static int uv_base_pnode __read_mostly;
 /* position of pnode (which is nasid>>1): */
 static int uv_nshift __read_mostly;
 static unsigned long uv_mmask __read_mostly;
@@ -109,60 +160,52 @@ static int __init uvhub_to_first_apicid(int uvhub)
  * clear of the Timeout bit (as well) will free the resource. No reply will
  * be sent (the hardware will only do one reply per message).
  */
-static inline void uv_reply_to_message(struct msg_desc *mdp,
-                                       struct bau_control *bcp)
+static void reply_to_message(struct msg_desc *mdp, struct bau_control *bcp)
 {
         unsigned long dw;
-        struct bau_payload_queue_entry *msg;
+        struct bau_pq_entry *msg;
 
         msg = mdp->msg;
         if (!msg->canceled) {
-                dw = (msg->sw_ack_vector << UV_SW_ACK_NPENDING) |
-                                                msg->sw_ack_vector;
-                uv_write_local_mmr(
-                                UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS, dw);
+                dw = (msg->swack_vec << UV_SW_ACK_NPENDING) | msg->swack_vec;
+                write_mmr_sw_ack(dw);
         }
         msg->replied_to = 1;
-        msg->sw_ack_vector = 0;
+        msg->swack_vec = 0;
 }
 
 /*
  * Process the receipt of a RETRY message
  */
-static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
-                                            struct bau_control *bcp)
+static void bau_process_retry_msg(struct msg_desc *mdp,
+                                        struct bau_control *bcp)
 {
         int i;
         int cancel_count = 0;
-        int slot2;
         unsigned long msg_res;
         unsigned long mmr = 0;
-        struct bau_payload_queue_entry *msg;
-        struct bau_payload_queue_entry *msg2;
-        struct ptc_stats *stat;
+        struct bau_pq_entry *msg = mdp->msg;
+        struct bau_pq_entry *msg2;
+        struct ptc_stats *stat = bcp->statp;
 
-        msg = mdp->msg;
-        stat = bcp->statp;
         stat->d_retries++;
         /*
          * cancel any message from msg+1 to the retry itself
          */
         for (msg2 = msg+1, i = 0; i < DEST_Q_SIZE; msg2++, i++) {
-                if (msg2 > mdp->va_queue_last)
-                        msg2 = mdp->va_queue_first;
+                if (msg2 > mdp->queue_last)
+                        msg2 = mdp->queue_first;
                 if (msg2 == msg)
                         break;
 
-                /* same conditions for cancellation as uv_do_reset */
+                /* same conditions for cancellation as do_reset */
                 if ((msg2->replied_to == 0) && (msg2->canceled == 0) &&
-                    (msg2->sw_ack_vector) && ((msg2->sw_ack_vector &
-                        msg->sw_ack_vector) == 0) &&
+                    (msg2->swack_vec) && ((msg2->swack_vec &
+                        msg->swack_vec) == 0) &&
                     (msg2->sending_cpu == msg->sending_cpu) &&
                     (msg2->msg_type != MSG_NOOP)) {
-                        slot2 = msg2 - mdp->va_queue_first;
-                        mmr = uv_read_local_mmr
-                                (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
-                        msg_res = msg2->sw_ack_vector;
+                        mmr = read_mmr_sw_ack();
+                        msg_res = msg2->swack_vec;
                         /*
                          * This is a message retry; clear the resources held
                          * by the previous message only if they timed out.
@@ -170,6 +213,7 @@ static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
                          * situation to report.
                          */
                         if (mmr & (msg_res << UV_SW_ACK_NPENDING)) {
+                                unsigned long mr;
                                 /*
                                  * is the resource timed out?
                                  * make everyone ignore the cancelled message.
@@ -177,10 +221,8 @@ static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
                                 msg2->canceled = 1;
                                 stat->d_canceled++;
                                 cancel_count++;
-                                uv_write_local_mmr(
-                                    UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS,
-                                        (msg_res << UV_SW_ACK_NPENDING) |
-                                         msg_res);
+                                mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
+                                write_mmr_sw_ack(mr);
                         }
                 }
         }
@@ -192,20 +234,19 @@ static inline void uv_bau_process_retry_msg(struct msg_desc *mdp,
  * Do all the things a cpu should do for a TLB shootdown message.
  * Other cpu's may come here at the same time for this message.
  */
-static void uv_bau_process_message(struct msg_desc *mdp,
-                                   struct bau_control *bcp)
+static void bau_process_message(struct msg_desc *mdp,
+                                        struct bau_control *bcp)
 {
-        int msg_ack_count;
         short socket_ack_count = 0;
-        struct ptc_stats *stat;
-        struct bau_payload_queue_entry *msg;
+        short *sp;
+        struct atomic_short *asp;
+        struct ptc_stats *stat = bcp->statp;
+        struct bau_pq_entry *msg = mdp->msg;
         struct bau_control *smaster = bcp->socket_master;
 
         /*
          * This must be a normal message, or retry of a normal message
          */
-        msg = mdp->msg;
-        stat = bcp->statp;
         if (msg->address == TLB_FLUSH_ALL) {
                 local_flush_tlb();
                 stat->d_alltlb++;
@@ -222,30 +263,32 @@ static void uv_bau_process_message(struct msg_desc *mdp,
          * cpu number.
          */
         if (msg->msg_type == MSG_RETRY && bcp == bcp->uvhub_master)
-                uv_bau_process_retry_msg(mdp, bcp);
+                bau_process_retry_msg(mdp, bcp);
 
         /*
-         * This is a sw_ack message, so we have to reply to it.
+         * This is a swack message, so we have to reply to it.
          * Count each responding cpu on the socket. This avoids
          * pinging the count's cache line back and forth between
          * the sockets.
          */
-        socket_ack_count = atomic_add_short_return(1, (struct atomic_short *)
-                        &smaster->socket_acknowledge_count[mdp->msg_slot]);
+        sp = &smaster->socket_acknowledge_count[mdp->msg_slot];
+        asp = (struct atomic_short *)sp;
+        socket_ack_count = atom_asr(1, asp);
         if (socket_ack_count == bcp->cpus_in_socket) {
+                int msg_ack_count;
                 /*
                  * Both sockets dump their completed count total into
                  * the message's count.
                  */
                 smaster->socket_acknowledge_count[mdp->msg_slot] = 0;
-                msg_ack_count = atomic_add_short_return(socket_ack_count,
-                                (struct atomic_short *)&msg->acknowledge_count);
+                asp = (struct atomic_short *)&msg->acknowledge_count;
+                msg_ack_count = atom_asr(socket_ack_count, asp);
 
                 if (msg_ack_count == bcp->cpus_in_uvhub) {
                         /*
                          * All cpus in uvhub saw it; reply
                          */
-                        uv_reply_to_message(mdp, bcp);
+                        reply_to_message(mdp, bcp);
                 }
         }
 
@@ -268,62 +311,51 @@ static int uvhub_to_first_cpu(int uvhub)
  * Last resort when we get a large number of destination timeouts is
  * to clear resources held by a given cpu.
  * Do this with IPI so that all messages in the BAU message queue
- * can be identified by their nonzero sw_ack_vector field.
+ * can be identified by their nonzero swack_vec field.
  *
  * This is entered for a single cpu on the uvhub.
  * The sender want's this uvhub to free a specific message's
- * sw_ack resources.
+ * swack resources.
  */
-static void
-uv_do_reset(void *ptr)
+static void do_reset(void *ptr)
 {
         int i;
-        int slot;
-        int count = 0;
-        unsigned long mmr;
-        unsigned long msg_res;
-        struct bau_control *bcp;
-        struct reset_args *rap;
-        struct bau_payload_queue_entry *msg;
-        struct ptc_stats *stat;
+        struct bau_control *bcp = &per_cpu(bau_control, smp_processor_id());
+        struct reset_args *rap = (struct reset_args *)ptr;
+        struct bau_pq_entry *msg;
+        struct ptc_stats *stat = bcp->statp;
 
-        bcp = &per_cpu(bau_control, smp_processor_id());
-        rap = (struct reset_args *)ptr;
-        stat = bcp->statp;
         stat->d_resets++;
-
         /*
          * We're looking for the given sender, and
-         * will free its sw_ack resource.
+         * will free its swack resource.
          * If all cpu's finally responded after the timeout, its
          * message 'replied_to' was set.
          */
-        for (msg = bcp->va_queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
-                /* uv_do_reset: same conditions for cancellation as
-                   uv_bau_process_retry_msg() */
+        for (msg = bcp->queue_first, i = 0; i < DEST_Q_SIZE; msg++, i++) {
+                unsigned long msg_res;
+                /* do_reset: same conditions for cancellation as
+                   bau_process_retry_msg() */
                 if ((msg->replied_to == 0) &&
                     (msg->canceled == 0) &&
                     (msg->sending_cpu == rap->sender) &&
-                    (msg->sw_ack_vector) &&
+                    (msg->swack_vec) &&
                     (msg->msg_type != MSG_NOOP)) {
+                        unsigned long mmr;
+                        unsigned long mr;
                         /*
                          * make everyone else ignore this message
                          */
                         msg->canceled = 1;
-                        slot = msg - bcp->va_queue_first;
-                        count++;
                         /*
                          * only reset the resource if it is still pending
                          */
-                        mmr = uv_read_local_mmr
-                                        (UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE);
-                        msg_res = msg->sw_ack_vector;
+                        mmr = read_mmr_sw_ack();
+                        msg_res = msg->swack_vec;
+                        mr = (msg_res << UV_SW_ACK_NPENDING) | msg_res;
                         if (mmr & msg_res) {
                                 stat->d_rcanceled++;
-                                uv_write_local_mmr(
-                                    UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS,
-                                        (msg_res << UV_SW_ACK_NPENDING) |
-                                         msg_res);
+                                write_mmr_sw_ack(mr);
                         }
                 }
         }
@@ -334,39 +366,38 @@ uv_do_reset(void *ptr)
  * Use IPI to get all target uvhubs to release resources held by
  * a given sending cpu number.
  */
-static void uv_reset_with_ipi(struct bau_target_uvhubmask *distribution,
-                              int sender)
+static void reset_with_ipi(struct bau_targ_hubmask *distribution, int sender)
 {
         int uvhub;
-        int cpu;
+        int maskbits;
         cpumask_t mask;
         struct reset_args reset_args;
 
         reset_args.sender = sender;
-
         cpus_clear(mask);
         /* find a single cpu for each uvhub in this distribution mask */
-        for (uvhub = 0;
-                    uvhub < sizeof(struct bau_target_uvhubmask) * BITSPERBYTE;
-                    uvhub++) {
+        maskbits = sizeof(struct bau_targ_hubmask) * BITSPERBYTE;
+        for (uvhub = 0; uvhub < maskbits; uvhub++) {
+                int cpu;
                 if (!bau_uvhub_isset(uvhub, distribution))
                         continue;
                 /* find a cpu for this uvhub */
                 cpu = uvhub_to_first_cpu(uvhub);
                 cpu_set(cpu, mask);
         }
-        /* IPI all cpus; Preemption is already disabled */
-        smp_call_function_many(&mask, uv_do_reset, (void *)&reset_args, 1);
+
+        /* IPI all cpus; preemption is already disabled */
+        smp_call_function_many(&mask, do_reset, (void *)&reset_args, 1);
         return;
 }
 
-static inline unsigned long
-cycles_2_us(unsigned long long cyc)
+static inline unsigned long cycles_2_us(unsigned long long cyc)
 {
         unsigned long long ns;
         unsigned long us;
-        ns =  (cyc * per_cpu(cyc2ns, smp_processor_id()))
-                                                >> CYC2NS_SCALE_FACTOR;
+        int cpu = smp_processor_id();
+
+        ns =  (cyc * per_cpu(cyc2ns, cpu)) >> CYC2NS_SCALE_FACTOR;
         us = ns / 1000;
         return us;
 }
@@ -376,56 +407,56 @@ cycles_2_us(unsigned long long cyc)
  * leaves uvhub_quiesce set so that no new broadcasts are started by
  * bau_flush_send_and_wait()
  */
-static inline void
-quiesce_local_uvhub(struct bau_control *hmaster)
+static inline void quiesce_local_uvhub(struct bau_control *hmaster)
 {
-        atomic_add_short_return(1, (struct atomic_short *)
-                 &hmaster->uvhub_quiesce);
+        atom_asr(1, (struct atomic_short *)&hmaster->uvhub_quiesce);
 }
 
 /*
  * mark this quiet-requestor as done
  */
-static inline void
-end_uvhub_quiesce(struct bau_control *hmaster)
+static inline void end_uvhub_quiesce(struct bau_control *hmaster)
 {
-        atomic_add_short_return(-1, (struct atomic_short *)
-                &hmaster->uvhub_quiesce);
+        atom_asr(-1, (struct atomic_short *)&hmaster->uvhub_quiesce);
+}
+
+static unsigned long uv1_read_status(unsigned long mmr_offset, int right_shift)
+{
+        unsigned long descriptor_status;
+
+        descriptor_status = uv_read_local_mmr(mmr_offset);
+        descriptor_status >>= right_shift;
+        descriptor_status &= UV_ACT_STATUS_MASK;
+        return descriptor_status;
 }
 
 /*
  * Wait for completion of a broadcast software ack message
  * return COMPLETE, RETRY(PLUGGED or TIMEOUT) or GIVEUP
  */
-static int uv_wait_completion(struct bau_desc *bau_desc,
-        unsigned long mmr_offset, int right_shift, int this_cpu,
-        struct bau_control *bcp, struct bau_control *smaster, long try)
+static int uv1_wait_completion(struct bau_desc *bau_desc,
+                                unsigned long mmr_offset, int right_shift,
+                                struct bau_control *bcp, long try)
 {
         unsigned long descriptor_status;
-        cycles_t ttime;
+        cycles_t ttm;
         struct ptc_stats *stat = bcp->statp;
-        struct bau_control *hmaster;
-
-        hmaster = bcp->uvhub_master;
 
+        descriptor_status = uv1_read_status(mmr_offset, right_shift);
         /* spin on the status MMR, waiting for it to go idle */
-        while ((descriptor_status = (((unsigned long)
-                uv_read_local_mmr(mmr_offset) >>
-                        right_shift) & UV_ACT_STATUS_MASK)) !=
-                        DESC_STATUS_IDLE) {
+        while ((descriptor_status != DS_IDLE)) {
                 /*
-                 * Our software ack messages may be blocked because there are
-                 * no swack resources available.  As long as none of them
-                 * has timed out hardware will NACK our message and its
-                 * state will stay IDLE.
+                 * Our software ack messages may be blocked because
+                 * there are no swack resources available.  As long
+                 * as none of them has timed out hardware will NACK
+                 * our message and its state will stay IDLE.
                  */
-                if (descriptor_status == DESC_STATUS_SOURCE_TIMEOUT) {
+                if (descriptor_status == DS_SOURCE_TIMEOUT) {
                         stat->s_stimeout++;
                         return FLUSH_GIVEUP;
-                } else if (descriptor_status ==
-                                        DESC_STATUS_DESTINATION_TIMEOUT) {
+                } else if (descriptor_status == DS_DESTINATION_TIMEOUT) {
                         stat->s_dtimeout++;
-                        ttime = get_cycles();
+                        ttm = get_cycles();
 
                         /*
                          * Our retries may be blocked by all destination
@@ -433,8 +464,7 @@ static int uv_wait_completion(struct bau_desc *bau_desc,
                          * pending.  In that case hardware returns the
                          * ERROR that looks like a destination timeout.
                          */
-                        if (cycles_2_us(ttime - bcp->send_message) <
-                                                        timeout_us) {
+                        if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
                                 bcp->conseccompletes = 0;
                                 return FLUSH_RETRY_PLUGGED;
                         }
@@ -447,80 +477,160 @@ static int uv_wait_completion(struct bau_desc *bau_desc,
                          */
                         cpu_relax();
                 }
+                descriptor_status = uv1_read_status(mmr_offset, right_shift);
         }
         bcp->conseccompletes++;
         return FLUSH_COMPLETE;
 }
 
-static inline cycles_t
-sec_2_cycles(unsigned long sec)
+/*
+ * UV2 has an extra bit of status in the ACTIVATION_STATUS_2 register.
+ */
+static unsigned long uv2_read_status(unsigned long offset, int rshft, int cpu)
 {
-        unsigned long ns;
-        cycles_t cyc;
+        unsigned long descriptor_status;
+        unsigned long descriptor_status2;
 
-        ns = sec * 1000000000;
-        cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
-        return cyc;
+        descriptor_status = ((read_lmmr(offset) >> rshft) & UV_ACT_STATUS_MASK);
+        descriptor_status2 = (read_mmr_uv2_status() >> cpu) & 0x1UL;
+        descriptor_status = (descriptor_status << 1) | descriptor_status2;
+        return descriptor_status;
+}
+
+static int uv2_wait_completion(struct bau_desc *bau_desc,
+                                unsigned long mmr_offset, int right_shift,
+                                struct bau_control *bcp, long try)
+{
+        unsigned long descriptor_stat;
+        cycles_t ttm;
+        int cpu = bcp->uvhub_cpu;
+        struct ptc_stats *stat = bcp->statp;
+
+        descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu);
+
+        /* spin on the status MMR, waiting for it to go idle */
+        while (descriptor_stat != UV2H_DESC_IDLE) {
+                /*
+                 * Our software ack messages may be blocked because
+                 * there are no swack resources available.  As long
+                 * as none of them has timed out hardware will NACK
+                 * our message and its state will stay IDLE.
+                 */
+                if ((descriptor_stat == UV2H_DESC_SOURCE_TIMEOUT) ||
+                    (descriptor_stat == UV2H_DESC_DEST_STRONG_NACK) ||
+                    (descriptor_stat == UV2H_DESC_DEST_PUT_ERR)) {
+                        stat->s_stimeout++;
+                        return FLUSH_GIVEUP;
+                } else if (descriptor_stat == UV2H_DESC_DEST_TIMEOUT) {
+                        stat->s_dtimeout++;
+                        ttm = get_cycles();
+                        /*
+                         * Our retries may be blocked by all destination
+                         * swack resources being consumed, and a timeout
+                         * pending.  In that case hardware returns the
+                         * ERROR that looks like a destination timeout.
+                         */
+                        if (cycles_2_us(ttm - bcp->send_message) < timeout_us) {
+                                bcp->conseccompletes = 0;
+                                return FLUSH_RETRY_PLUGGED;
+                        }
+                        bcp->conseccompletes = 0;
+                        return FLUSH_RETRY_TIMEOUT;
+                } else {
+                        /*
+                         * descriptor_stat is still BUSY
+                         */
+                        cpu_relax();
+                }
+                descriptor_stat = uv2_read_status(mmr_offset, right_shift, cpu);
+        }
+        bcp->conseccompletes++;
+        return FLUSH_COMPLETE;
 }
 
 /*
- * conditionally add 1 to *v, unless *v is >= u
- * return 0 if we cannot add 1 to *v because it is >= u
- * return 1 if we can add 1 to *v because it is < u
- * the add is atomic
- *
- * This is close to atomic_add_unless(), but this allows the 'u' value
- * to be lowered below the current 'v'.  atomic_add_unless can only stop
- * on equal.
+ * There are 2 status registers; each and array[32] of 2 bits. Set up for
+ * which register to read and position in that register based on cpu in
+ * current hub.
  */
-static inline int atomic_inc_unless_ge(spinlock_t *lock, atomic_t *v, int u)
+static int wait_completion(struct bau_desc *bau_desc,
+                                struct bau_control *bcp, long try)
 {
-        spin_lock(lock);
-        if (atomic_read(v) >= u) {
-                spin_unlock(lock);
-                return 0;
+        int right_shift;
+        unsigned long mmr_offset;
+        int cpu = bcp->uvhub_cpu;
+
+        if (cpu < UV_CPUS_PER_AS) {
+                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
+                right_shift = cpu * UV_ACT_STATUS_SIZE;
+        } else {
+                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
+                right_shift = ((cpu - UV_CPUS_PER_AS) * UV_ACT_STATUS_SIZE);
         }
-        atomic_inc(v);
-        spin_unlock(lock);
-        return 1;
+
+        if (is_uv1_hub())
+                return uv1_wait_completion(bau_desc, mmr_offset, right_shift,
+                                                                bcp, try);
+        else
+                return uv2_wait_completion(bau_desc, mmr_offset, right_shift,
+                                                                bcp, try);
+}
+
+static inline cycles_t sec_2_cycles(unsigned long sec)
+{
+        unsigned long ns;
+        cycles_t cyc;
+
+        ns = sec * 1000000000;
+        cyc = (ns << CYC2NS_SCALE_FACTOR)/(per_cpu(cyc2ns, smp_processor_id()));
+        return cyc;
 }
 
 /*
- * Our retries are blocked by all destination swack resources being
+ * Our retries are blocked by all destination sw ack resources being
  * in use, and a timeout is pending. In that case hardware immediately
  * returns the ERROR that looks like a destination timeout.
  */
-static void
-destination_plugged(struct bau_desc *bau_desc, struct bau_control *bcp,
+static void destination_plugged(struct bau_desc *bau_desc,
+                        struct bau_control *bcp,
                         struct bau_control *hmaster, struct ptc_stats *stat)
 {
         udelay(bcp->plugged_delay);
         bcp->plugged_tries++;
+
         if (bcp->plugged_tries >= bcp->plugsb4reset) {
                 bcp->plugged_tries = 0;
+
                 quiesce_local_uvhub(hmaster);
+
                 spin_lock(&hmaster->queue_lock);
-                uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu);
+                reset_with_ipi(&bau_desc->distribution, bcp->cpu);
                 spin_unlock(&hmaster->queue_lock);
+
                 end_uvhub_quiesce(hmaster);
+
                 bcp->ipi_attempts++;
                 stat->s_resets_plug++;
         }
 }
 
-static void
-destination_timeout(struct bau_desc *bau_desc, struct bau_control *bcp,
-                        struct bau_control *hmaster, struct ptc_stats *stat)
+static void destination_timeout(struct bau_desc *bau_desc,
+                        struct bau_control *bcp, struct bau_control *hmaster,
+                        struct ptc_stats *stat)
 {
-        hmaster->max_bau_concurrent = 1;
+        hmaster->max_concurr = 1;
         bcp->timeout_tries++;
         if (bcp->timeout_tries >= bcp->timeoutsb4reset) {
                 bcp->timeout_tries = 0;
+
                 quiesce_local_uvhub(hmaster);
+
                 spin_lock(&hmaster->queue_lock);
-                uv_reset_with_ipi(&bau_desc->distribution, bcp->cpu);
+                reset_with_ipi(&bau_desc->distribution, bcp->cpu);
                 spin_unlock(&hmaster->queue_lock);
+
                 end_uvhub_quiesce(hmaster);
+
                 bcp->ipi_attempts++;
                 stat->s_resets_timeout++;
         }
@@ -530,34 +640,104 @@ destination_timeout(struct bau_desc *bau_desc, struct bau_control *bcp,
  * Completions are taking a very long time due to a congested numalink
  * network.
  */
-static void
-disable_for_congestion(struct bau_control *bcp, struct ptc_stats *stat)
+static void disable_for_congestion(struct bau_control *bcp,
+                                        struct ptc_stats *stat)
 {
-        int tcpu;
-        struct bau_control *tbcp;
-
         /* let only one cpu do this disabling */
         spin_lock(&disable_lock);
+
         if (!baudisabled && bcp->period_requests &&
             ((bcp->period_time / bcp->period_requests) > congested_cycles)) {
+                int tcpu;
+                struct bau_control *tbcp;
                 /* it becomes this cpu's job to turn on the use of the
                    BAU again */
                 baudisabled = 1;
                 bcp->set_bau_off = 1;
-                bcp->set_bau_on_time = get_cycles() +
-                        sec_2_cycles(bcp->congested_period);
+                bcp->set_bau_on_time = get_cycles();
+                bcp->set_bau_on_time += sec_2_cycles(bcp->cong_period);
                 stat->s_bau_disabled++;
                 for_each_present_cpu(tcpu) {
                         tbcp = &per_cpu(bau_control, tcpu);
-                                tbcp->baudisabled = 1;
+                        tbcp->baudisabled = 1;
                 }
         }
+
         spin_unlock(&disable_lock);
 }
 
-/**
- * uv_flush_send_and_wait
- *
+static void count_max_concurr(int stat, struct bau_control *bcp,
+                                struct bau_control *hmaster)
+{
+        bcp->plugged_tries = 0;
+        bcp->timeout_tries = 0;
+        if (stat != FLUSH_COMPLETE)
+                return;
+        if (bcp->conseccompletes <= bcp->complete_threshold)
+                return;
+        if (hmaster->max_concurr >= hmaster->max_concurr_const)
+                return;
+        hmaster->max_concurr++;
+}
+
+static void record_send_stats(cycles_t time1, cycles_t time2,
+                struct bau_control *bcp, struct ptc_stats *stat,
+                int completion_status, int try)
+{
+        cycles_t elapsed;
+
+        if (time2 > time1) {
+                elapsed = time2 - time1;
+                stat->s_time += elapsed;
+
+                if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
+                        bcp->period_requests++;
+                        bcp->period_time += elapsed;
+                        if ((elapsed > congested_cycles) &&
+                            (bcp->period_requests > bcp->cong_reps))
+                                disable_for_congestion(bcp, stat);
+                }
+        } else
+                stat->s_requestor--;
+
+        if (completion_status == FLUSH_COMPLETE && try > 1)
+                stat->s_retriesok++;
+        else if (completion_status == FLUSH_GIVEUP)
+                stat->s_giveup++;
+}
+
+/*
+ * Because of a uv1 hardware bug only a limited number of concurrent
+ * requests can be made.
+ */
+static void uv1_throttle(struct bau_control *hmaster, struct ptc_stats *stat)
+{
+        spinlock_t *lock = &hmaster->uvhub_lock;
+        atomic_t *v;
+
+        v = &hmaster->active_descriptor_count;
+        if (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr)) {
+                stat->s_throttles++;
+                do {
+                        cpu_relax();
+                } while (!atomic_inc_unless_ge(lock, v, hmaster->max_concurr));
+        }
+}
+
+/*
+ * Handle the completion status of a message send.
+ */
+static void handle_cmplt(int completion_status, struct bau_desc *bau_desc,
+                        struct bau_control *bcp, struct bau_control *hmaster,
+                        struct ptc_stats *stat)
+{
+        if (completion_status == FLUSH_RETRY_PLUGGED)
+                destination_plugged(bau_desc, bcp, hmaster, stat);
+        else if (completion_status == FLUSH_RETRY_TIMEOUT)
+                destination_timeout(bau_desc, bcp, hmaster, stat);
+}
+
+/*
  * Send a broadcast and wait for it to complete.
  *
  * The flush_mask contains the cpus the broadcast is to be sent to including
@@ -568,44 +748,23 @@ disable_for_congestion(struct bau_control *bcp, struct ptc_stats *stat)
  * returned to the kernel.
  */
 int uv_flush_send_and_wait(struct bau_desc *bau_desc,
-                           struct cpumask *flush_mask, struct bau_control *bcp)
+                        struct cpumask *flush_mask, struct bau_control *bcp)
 {
-        int right_shift;
-        int completion_status = 0;
         int seq_number = 0;
+        int completion_stat = 0;
         long try = 0;
-        int cpu = bcp->uvhub_cpu;
-        int this_cpu = bcp->cpu;
-        unsigned long mmr_offset;
         unsigned long index;
         cycles_t time1;
         cycles_t time2;
-        cycles_t elapsed;
         struct ptc_stats *stat = bcp->statp;
-        struct bau_control *smaster = bcp->socket_master;
         struct bau_control *hmaster = bcp->uvhub_master;
 
-        if (!atomic_inc_unless_ge(&hmaster->uvhub_lock,
-                        &hmaster->active_descriptor_count,
-                        hmaster->max_bau_concurrent)) {
-                stat->s_throttles++;
-                do {
-                        cpu_relax();
-                } while (!atomic_inc_unless_ge(&hmaster->uvhub_lock,
-                        &hmaster->active_descriptor_count,
-                        hmaster->max_bau_concurrent));
-        }
+        if (is_uv1_hub())
+                uv1_throttle(hmaster, stat);
+
         while (hmaster->uvhub_quiesce)
                 cpu_relax();
 
-        if (cpu < UV_CPUS_PER_ACT_STATUS) {
-                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_0;
-                right_shift = cpu * UV_ACT_STATUS_SIZE;
-        } else {
-                mmr_offset = UVH_LB_BAU_SB_ACTIVATION_STATUS_1;
-                right_shift =
-                    ((cpu - UV_CPUS_PER_ACT_STATUS) * UV_ACT_STATUS_SIZE);
-        }
         time1 = get_cycles();
         do {
                 if (try == 0) {
@@ -615,64 +774,134 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc,
                         bau_desc->header.msg_type = MSG_RETRY;
                         stat->s_retry_messages++;
                 }
+
                 bau_desc->header.sequence = seq_number;
-                index = (1UL << UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT) |
-                        bcp->uvhub_cpu;
+                index = (1UL << AS_PUSH_SHIFT) | bcp->uvhub_cpu;
                 bcp->send_message = get_cycles();
-                uv_write_local_mmr(UVH_LB_BAU_SB_ACTIVATION_CONTROL, index);
+
+                write_mmr_activation(index);
+
                 try++;
-                completion_status = uv_wait_completion(bau_desc, mmr_offset,
-                        right_shift, this_cpu, bcp, smaster, try);
+                completion_stat = wait_completion(bau_desc, bcp, try);
+
+                handle_cmplt(completion_stat, bau_desc, bcp, hmaster, stat);
 
-                if (completion_status == FLUSH_RETRY_PLUGGED) {
-                        destination_plugged(bau_desc, bcp, hmaster, stat);
-                } else if (completion_status == FLUSH_RETRY_TIMEOUT) {
-                        destination_timeout(bau_desc, bcp, hmaster, stat);
-                }
                 if (bcp->ipi_attempts >= bcp->ipi_reset_limit) {
                         bcp->ipi_attempts = 0;
-                        completion_status = FLUSH_GIVEUP;
+                        completion_stat = FLUSH_GIVEUP;
                         break;
                 }
                 cpu_relax();
-        } while ((completion_status == FLUSH_RETRY_PLUGGED) ||
-                 (completion_status == FLUSH_RETRY_TIMEOUT));
+        } while ((completion_stat == FLUSH_RETRY_PLUGGED) ||
+                 (completion_stat == FLUSH_RETRY_TIMEOUT));
+
         time2 = get_cycles();
-        bcp->plugged_tries = 0;
-        bcp->timeout_tries = 0;
-        if ((completion_status == FLUSH_COMPLETE) &&
-            (bcp->conseccompletes > bcp->complete_threshold) &&
-            (hmaster->max_bau_concurrent <
-                                        hmaster->max_bau_concurrent_constant))
-                        hmaster->max_bau_concurrent++;
+
+        count_max_concurr(completion_stat, bcp, hmaster);
+
         while (hmaster->uvhub_quiesce)
                 cpu_relax();
+
         atomic_dec(&hmaster->active_descriptor_count);
-        if (time2 > time1) {
-                elapsed = time2 - time1;
-                stat->s_time += elapsed;
-                if ((completion_status == FLUSH_COMPLETE) && (try == 1)) {
-                        bcp->period_requests++;
-                        bcp->period_time += elapsed;
-                        if ((elapsed > congested_cycles) &&
-                            (bcp->period_requests > bcp->congested_reps)) {
-                                disable_for_congestion(bcp, stat);
+
+        record_send_stats(time1, time2, bcp, stat, completion_stat, try);
+
+        if (completion_stat == FLUSH_GIVEUP)
+                return 1;
+        return 0;
+}
+
+/*
+ * The BAU is disabled. When the disabled time period has expired, the cpu
+ * that disabled it must re-enable it.
+ * Return 0 if it is re-enabled for all cpus.
+ */
+static int check_enable(struct bau_control *bcp, struct ptc_stats *stat)
+{
+        int tcpu;
+        struct bau_control *tbcp;
+
+        if (bcp->set_bau_off) {
+                if (get_cycles() >= bcp->set_bau_on_time) {
+                        stat->s_bau_reenabled++;
+                        baudisabled = 0;
+                        for_each_present_cpu(tcpu) {
+                                tbcp = &per_cpu(bau_control, tcpu);
+                                tbcp->baudisabled = 0;
+                                tbcp->period_requests = 0;
+                                tbcp->period_time = 0;
                         }
+                        return 0;
                 }
+        }
+        return -1;
+}
+
+static void record_send_statistics(struct ptc_stats *stat, int locals, int hubs,
+                                int remotes, struct bau_desc *bau_desc)
+{
+        stat->s_requestor++;
+        stat->s_ntargcpu += remotes + locals;
+        stat->s_ntargremotes += remotes;
+        stat->s_ntarglocals += locals;
+
+        /* uvhub statistics */
+        hubs = bau_uvhub_weight(&bau_desc->distribution);
+        if (locals) {
+                stat->s_ntarglocaluvhub++;
+                stat->s_ntargremoteuvhub += (hubs - 1);
         } else
-                stat->s_requestor--;
-        if (completion_status == FLUSH_COMPLETE && try > 1)
-                stat->s_retriesok++;
-        else if (completion_status == FLUSH_GIVEUP) {
-                stat->s_giveup++;
-                return 1;
+                stat->s_ntargremoteuvhub += hubs;
+
+        stat->s_ntarguvhub += hubs;
+
+        if (hubs >= 16)
+                stat->s_ntarguvhub16++;
+        else if (hubs >= 8)
+                stat->s_ntarguvhub8++;
+        else if (hubs >= 4)
+                stat->s_ntarguvhub4++;
+        else if (hubs >= 2)
+                stat->s_ntarguvhub2++;
+        else
+                stat->s_ntarguvhub1++;
+}
+
+/*
+ * Translate a cpu mask to the uvhub distribution mask in the BAU
+ * activation descriptor.
+ */
+static int set_distrib_bits(struct cpumask *flush_mask, struct bau_control *bcp,
+                        struct bau_desc *bau_desc, int *localsp, int *remotesp)
+{
+        int cpu;
+        int pnode;
+        int cnt = 0;
+        struct hub_and_pnode *hpp;
+
+        for_each_cpu(cpu, flush_mask) {
+                /*
+                 * The distribution vector is a bit map of pnodes, relative
+                 * to the partition base pnode (and the partition base nasid
+                 * in the header).
+                 * Translate cpu to pnode and hub using a local memory array.
+                 */
+                hpp = &bcp->socket_master->thp[cpu];
+                pnode = hpp->pnode - bcp->partition_base_pnode;
+                bau_uvhub_set(pnode, &bau_desc->distribution);
+                cnt++;
+                if (hpp->uvhub == bcp->uvhub)
+                        (*localsp)++;
+                else
+                        (*remotesp)++;
         }
+        if (!cnt)
+                return 1;
         return 0;
 }
 
-/**
- * uv_flush_tlb_others - globally purge translation cache of a virtual
- * address or all TLB's
+/*
+ * globally purge translation cache of a virtual address or all TLB's
  * @cpumask: mask of all cpu's in which the address is to be removed
  * @mm: mm_struct containing virtual address range
  * @va: virtual address to be removed (or TLB_FLUSH_ALL for all TLB's on cpu)
@@ -696,20 +925,16 @@ int uv_flush_send_and_wait(struct bau_desc *bau_desc,
  * done.  The returned pointer is valid till preemption is re-enabled.
  */
 const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
-                                          struct mm_struct *mm,
-                                          unsigned long va, unsigned int cpu)
+                                struct mm_struct *mm, unsigned long va,
+                                unsigned int cpu)
 {
         int locals = 0;
         int remotes = 0;
         int hubs = 0;
-        int tcpu;
-        int tpnode;
         struct bau_desc *bau_desc;
         struct cpumask *flush_mask;
         struct ptc_stats *stat;
         struct bau_control *bcp;
-        struct bau_control *tbcp;
-        struct hub_and_pnode *hpp;
 
         /* kernel was booted 'nobau' */
         if (nobau)
@@ -720,20 +945,8 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
 
         /* bau was disabled due to slow response */
         if (bcp->baudisabled) {
-                /* the cpu that disabled it must re-enable it */
-                if (bcp->set_bau_off) {
-                        if (get_cycles() >= bcp->set_bau_on_time) {
-                                stat->s_bau_reenabled++;
-                                baudisabled = 0;
-                                for_each_present_cpu(tcpu) {
-                                        tbcp = &per_cpu(bau_control, tcpu);
-                                        tbcp->baudisabled = 0;
-                                        tbcp->period_requests = 0;
-                                        tbcp->period_time = 0;
-                                }
-                        }
-                }
-                return cpumask;
+                if (check_enable(bcp, stat))
+                        return cpumask;
         }
 
         /*
@@ -744,59 +957,20 @@ const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
         flush_mask = (struct cpumask *)per_cpu(uv_flush_tlb_mask, cpu);
         /* don't actually do a shootdown of the local cpu */
         cpumask_andnot(flush_mask, cpumask, cpumask_of(cpu));
+
         if (cpu_isset(cpu, *cpumask))
                 stat->s_ntargself++;
 
         bau_desc = bcp->descriptor_base;
-        bau_desc += UV_ITEMS_PER_DESCRIPTOR * bcp->uvhub_cpu;
+        bau_desc += ITEMS_PER_DESC * bcp->uvhub_cpu;
         bau_uvhubs_clear(&bau_desc->distribution, UV_DISTRIBUTION_SIZE);
-
-        for_each_cpu(tcpu, flush_mask) {
-                /*
-                 * The distribution vector is a bit map of pnodes, relative
-                 * to the partition base pnode (and the partition base nasid
-                 * in the header).
-                 * Translate cpu to pnode and hub using an array stored
-                 * in local memory.
-                 */
-                hpp = &bcp->socket_master->target_hub_and_pnode[tcpu];
-                tpnode = hpp->pnode - bcp->partition_base_pnode;
-                bau_uvhub_set(tpnode, &bau_desc->distribution);
-                if (hpp->uvhub == bcp->uvhub)
-                        locals++;
-                else
-                        remotes++;
-        }
-        if ((locals + remotes) == 0)
+        if (set_distrib_bits(flush_mask, bcp, bau_desc, &locals, &remotes))
                 return NULL;
-        stat->s_requestor++;
-        stat->s_ntargcpu += remotes + locals;
-        stat->s_ntargremotes += remotes;
-        stat->s_ntarglocals += locals;
-        remotes = bau_uvhub_weight(&bau_desc->distribution);
 
-        /* uvhub statistics */
-        hubs = bau_uvhub_weight(&bau_desc->distribution);
-        if (locals) {
-                stat->s_ntarglocaluvhub++;
-                stat->s_ntargremoteuvhub += (hubs - 1);
-        } else
-                stat->s_ntargremoteuvhub += hubs;
-        stat->s_ntarguvhub += hubs;
-        if (hubs >= 16)
-                stat->s_ntarguvhub16++;
-        else if (hubs >= 8)
-                stat->s_ntarguvhub8++;
-        else if (hubs >= 4)
-                stat->s_ntarguvhub4++;
-        else if (hubs >= 2)
-                stat->s_ntarguvhub2++;
-        else
-                stat->s_ntarguvhub1++;
+        record_send_statistics(stat, locals, hubs, remotes, bau_desc);
 
         bau_desc->payload.address = va;
         bau_desc->payload.sending_cpu = cpu;
-
         /*
          * uv_flush_send_and_wait returns 0 if all cpu's were messaged,
          * or 1 if it gave up and the original cpumask should be returned.
@@ -825,26 +999,31 @@ void uv_bau_message_interrupt(struct pt_regs *regs)
 {
         int count = 0;
         cycles_t time_start;
-        struct bau_payload_queue_entry *msg;
+        struct bau_pq_entry *msg;
         struct bau_control *bcp;
         struct ptc_stats *stat;
         struct msg_desc msgdesc;
 
         time_start = get_cycles();
+
         bcp = &per_cpu(bau_control, smp_processor_id());
         stat = bcp->statp;
-        msgdesc.va_queue_first = bcp->va_queue_first;
-        msgdesc.va_queue_last = bcp->va_queue_last;
+
+        msgdesc.queue_first = bcp->queue_first;
+        msgdesc.queue_last = bcp->queue_last;
+
         msg = bcp->bau_msg_head;
-        while (msg->sw_ack_vector) {
+        while (msg->swack_vec) {
                 count++;
-                msgdesc.msg_slot = msg - msgdesc.va_queue_first;
-                msgdesc.sw_ack_slot = ffs(msg->sw_ack_vector) - 1;
+
+                msgdesc.msg_slot = msg - msgdesc.queue_first;
+                msgdesc.swack_slot = ffs(msg->swack_vec) - 1;
                 msgdesc.msg = msg;
-                uv_bau_process_message(&msgdesc, bcp);
+                bau_process_message(&msgdesc, bcp);
+
                 msg++;
-                if (msg > msgdesc.va_queue_last)
-                        msg = msgdesc.va_queue_first;
+                if (msg > msgdesc.queue_last)
+                        msg = msgdesc.queue_first;
                 bcp->bau_msg_head = msg;
         }
         stat->d_time += (get_cycles() - time_start);
@@ -852,18 +1031,17 @@ void uv_bau_message_interrupt(struct pt_regs *regs)
                 stat->d_nomsg++;
         else if (count > 1)
                 stat->d_multmsg++;
+
         ack_APIC_irq();
 }
 
 /*
- * uv_enable_timeouts
- *
- * Each target uvhub (i.e. a uvhub that has no cpu's) needs to have
+ * Each target uvhub (i.e. a uvhub that has cpu's) needs to have
  * shootdown message timeouts enabled.  The timeout does not cause
  * an interrupt, but causes an error message to be returned to
  * the sender.
  */
-static void __init uv_enable_timeouts(void)
+static void __init enable_timeouts(void)
 {
         int uvhub;
         int nuvhubs;
@@ -877,47 +1055,44 @@ static void __init uv_enable_timeouts(void)
                         continue;
 
                 pnode = uv_blade_to_pnode(uvhub);
-                mmr_image =
-                    uv_read_global_mmr64(pnode, UVH_LB_BAU_MISC_CONTROL);
+                mmr_image = read_mmr_misc_control(pnode);
                 /*
                  * Set the timeout period and then lock it in, in three
                  * steps; captures and locks in the period.
                  *
                  * To program the period, the SOFT_ACK_MODE must be off.
                  */
-                mmr_image &= ~((unsigned long)1 <<
-                    UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT);
-                uv_write_global_mmr64
-                    (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
+                mmr_image &= ~(1L << SOFTACK_MSHIFT);
+                write_mmr_misc_control(pnode, mmr_image);
                 /*
                  * Set the 4-bit period.
                  */
-                mmr_image &= ~((unsigned long)0xf <<
-                     UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT);
-                mmr_image |= (UV_INTD_SOFT_ACK_TIMEOUT_PERIOD <<
-                     UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT);
-                uv_write_global_mmr64
-                    (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
+                mmr_image &= ~((unsigned long)0xf << SOFTACK_PSHIFT);
+                mmr_image |= (SOFTACK_TIMEOUT_PERIOD << SOFTACK_PSHIFT);
+                write_mmr_misc_control(pnode, mmr_image);
                 /*
+                 * UV1:
                  * Subsequent reversals of the timebase bit (3) cause an
                  * immediate timeout of one or all INTD resources as
                  * indicated in bits 2:0 (7 causes all of them to timeout).
                  */
-                mmr_image |= ((unsigned long)1 <<
-                    UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT);
-                uv_write_global_mmr64
-                    (pnode, UVH_LB_BAU_MISC_CONTROL, mmr_image);
+                mmr_image |= (1L << SOFTACK_MSHIFT);
+                if (is_uv2_hub()) {
+                        mmr_image |= (1L << UV2_LEG_SHFT);
+                        mmr_image |= (1L << UV2_EXT_SHFT);
+                }
+                write_mmr_misc_control(pnode, mmr_image);
         }
 }
 
-static void *uv_ptc_seq_start(struct seq_file *file, loff_t *offset)
+static void *ptc_seq_start(struct seq_file *file, loff_t *offset)
 {
         if (*offset < num_possible_cpus())
                 return offset;
         return NULL;
 }
 
-static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
+static void *ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
 {
         (*offset)++;
         if (*offset < num_possible_cpus())
@@ -925,12 +1100,11 @@ static void *uv_ptc_seq_next(struct seq_file *file, void *data, loff_t *offset)
         return NULL;
 }
 
-static void uv_ptc_seq_stop(struct seq_file *file, void *data)
+static void ptc_seq_stop(struct seq_file *file, void *data)
 {
 }
 
-static inline unsigned long long
-microsec_2_cycles(unsigned long microsec)
+static inline unsigned long long usec_2_cycles(unsigned long microsec)
 {
         unsigned long ns;
         unsigned long long cyc;
@@ -941,29 +1115,27 @@ microsec_2_cycles(unsigned long microsec)
 }
 
 /*
- * Display the statistics thru /proc.
+ * Display the statistics thru /proc/sgi_uv/ptc_statistics
  * 'data' points to the cpu number
+ * Note: see the descriptions in stat_description[].
  */
-static int uv_ptc_seq_show(struct seq_file *file, void *data)
+static int ptc_seq_show(struct seq_file *file, void *data)
 {
         struct ptc_stats *stat;
         int cpu;
 
         cpu = *(loff_t *)data;
-
         if (!cpu) {
                 seq_printf(file,
                         "# cpu sent stime self locals remotes ncpus localhub ");
                 seq_printf(file,
                         "remotehub numuvhubs numuvhubs16 numuvhubs8 ");
                 seq_printf(file,
-                        "numuvhubs4 numuvhubs2 numuvhubs1 dto ");
-                seq_printf(file,
-                        "retries rok resetp resett giveup sto bz throt ");
+                        "numuvhubs4 numuvhubs2 numuvhubs1 dto retries rok ");
                 seq_printf(file,
-                        "sw_ack recv rtime all ");
+                        "resetp resett giveup sto bz throt swack recv rtime ");
                 seq_printf(file,
-                        "one mult none retry canc nocan reset rcan ");
+                        "all one mult none retry canc nocan reset rcan ");
                 seq_printf(file,
                         "disable enable\n");
         }
@@ -990,8 +1162,7 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
                 /* destination side statistics */
                 seq_printf(file,
                            "%lx %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld %ld ",
-                           uv_read_global_mmr64(uv_cpu_to_pnode(cpu),
-                                        UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE),
+                           read_gmmr_sw_ack(uv_cpu_to_pnode(cpu)),
                            stat->d_requestee, cycles_2_us(stat->d_time),
                            stat->d_alltlb, stat->d_onetlb, stat->d_multmsg,
                            stat->d_nomsg, stat->d_retries, stat->d_canceled,
@@ -1000,7 +1171,6 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
                 seq_printf(file, "%ld %ld\n",
                         stat->s_bau_disabled, stat->s_bau_reenabled);
         }
-
         return 0;
 }
 
@@ -1008,18 +1178,18 @@ static int uv_ptc_seq_show(struct seq_file *file, void *data)
  * Display the tunables thru debugfs
  */
 static ssize_t tunables_read(struct file *file, char __user *userbuf,
-                                                size_t count, loff_t *ppos)
+                                size_t count, loff_t *ppos)
 {
         char *buf;
         int ret;
 
         buf = kasprintf(GFP_KERNEL, "%s %s %s\n%d %d %d %d %d %d %d %d %d\n",
-                "max_bau_concurrent plugged_delay plugsb4reset",
+                "max_concur plugged_delay plugsb4reset",
                 "timeoutsb4reset ipi_reset_limit complete_threshold",
                 "congested_response_us congested_reps congested_period",
-                max_bau_concurrent, plugged_delay, plugsb4reset,
+                max_concurr, plugged_delay, plugsb4reset,
                 timeoutsb4reset, ipi_reset_limit, complete_threshold,
-                congested_response_us, congested_reps, congested_period);
+                congested_respns_us, congested_reps, congested_period);
 
         if (!buf)
                 return -ENOMEM;
@@ -1030,13 +1200,16 @@ static ssize_t tunables_read(struct file *file, char __user *userbuf,
 }
 
 /*
- * -1: resetf the statistics
+ * handle a write to /proc/sgi_uv/ptc_statistics
+ * -1: reset the statistics
  *  0: display meaning of the statistics
  */
-static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
-                                 size_t count, loff_t *data)
+static ssize_t ptc_proc_write(struct file *file, const char __user *user,
+                                size_t count, loff_t *data)
 {
         int cpu;
+        int i;
+        int elements;
         long input_arg;
         char optstr[64];
         struct ptc_stats *stat;
@@ -1046,79 +1219,18 @@ static ssize_t uv_ptc_proc_write(struct file *file, const char __user *user,
         if (copy_from_user(optstr, user, count))
                 return -EFAULT;
         optstr[count - 1] = '\0';
+
         if (strict_strtol(optstr, 10, &input_arg) < 0) {
                 printk(KERN_DEBUG "%s is invalid\n", optstr);
                 return -EINVAL;
         }
 
         if (input_arg == 0) {
+                elements = sizeof(stat_description)/sizeof(*stat_description);
                 printk(KERN_DEBUG "# cpu:      cpu number\n");
                 printk(KERN_DEBUG "Sender statistics:\n");
-                printk(KERN_DEBUG
-                "sent:     number of shootdown messages sent\n");
-                printk(KERN_DEBUG
-                "stime:    time spent sending messages\n");
-                printk(KERN_DEBUG
-                "numuvhubs: number of hubs targeted with shootdown\n");
-                printk(KERN_DEBUG
-                "numuvhubs16: number times 16 or more hubs targeted\n");
-                printk(KERN_DEBUG
-                "numuvhubs8: number times 8 or more hubs targeted\n");
-                printk(KERN_DEBUG
-                "numuvhubs4: number times 4 or more hubs targeted\n");
-                printk(KERN_DEBUG
-                "numuvhubs2: number times 2 or more hubs targeted\n");
-                printk(KERN_DEBUG
-                "numuvhubs1: number times 1 hub targeted\n");
-                printk(KERN_DEBUG
-                "numcpus:  number of cpus targeted with shootdown\n");
-                printk(KERN_DEBUG
-                "dto:      number of destination timeouts\n");
-                printk(KERN_DEBUG
-                "retries:  destination timeout retries sent\n");
-                printk(KERN_DEBUG
-                "rok:   :  destination timeouts successfully retried\n");
-                printk(KERN_DEBUG
-                "resetp:   ipi-style resource resets for plugs\n");
-                printk(KERN_DEBUG
-                "resett:   ipi-style resource resets for timeouts\n");
-                printk(KERN_DEBUG
-                "giveup:   fall-backs to ipi-style shootdowns\n");
-                printk(KERN_DEBUG
-                "sto:      number of source timeouts\n");
-                printk(KERN_DEBUG
-                "bz:       number of stay-busy's\n");
-                printk(KERN_DEBUG
-                "throt:    number times spun in throttle\n");
-                printk(KERN_DEBUG "Destination side statistics:\n");
-                printk(KERN_DEBUG
-                "sw_ack:   image of UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE\n");
-                printk(KERN_DEBUG
-                "recv:     shootdown messages received\n");
-                printk(KERN_DEBUG
-                "rtime:    time spent processing messages\n");
-                printk(KERN_DEBUG
-                "all:      shootdown all-tlb messages\n");
-                printk(KERN_DEBUG
-                "one:      shootdown one-tlb messages\n");
-                printk(KERN_DEBUG
-                "mult:     interrupts that found multiple messages\n");
-                printk(KERN_DEBUG
-                "none:     interrupts that found no messages\n");
-                printk(KERN_DEBUG
-                "retry:    number of retry messages processed\n");
-                printk(KERN_DEBUG
-                "canc:     number messages canceled by retries\n");
-                printk(KERN_DEBUG
-                "nocan:    number retries that found nothing to cancel\n");
-                printk(KERN_DEBUG
-                "reset:    number of ipi-style reset requests processed\n");
-                printk(KERN_DEBUG
-                "rcan:     number messages canceled by reset requests\n");
-                printk(KERN_DEBUG
-                "disable:  number times use of the BAU was disabled\n");
-                printk(KERN_DEBUG
-                "enable:   number times use of the BAU was re-enabled\n");
+                for (i = 0; i < elements; i++)
+                        printk(KERN_DEBUG "%s\n", stat_description[i]);
         } else if (input_arg == -1) {
                 for_each_present_cpu(cpu) {
                         stat = &per_cpu(ptcstats, cpu);
@@ -1145,27 +1257,18 @@ static int local_atoi(const char *name)
 }
 
 /*
- * set the tunables
- * 0 values reset them to defaults
+ * Parse the values written to /sys/kernel/debug/sgi_uv/bau_tunables.
+ * Zero values reset them to defaults.
  */
-static ssize_t tunables_write(struct file *file, const char __user *user,
-                                 size_t count, loff_t *data)
+static int parse_tunables_write(struct bau_control *bcp, char *instr,
+                                int count)
 {
-        int cpu;
-        int cnt = 0;
-        int val;
         char *p;
         char *q;
-        char instr[64];
-        struct bau_control *bcp;
-
-        if (count == 0 || count > sizeof(instr)-1)
-                return -EINVAL;
-        if (copy_from_user(instr, user, count))
-                return -EFAULT;
+        int cnt = 0;
+        int val;
+        int e = sizeof(tunables) / sizeof(*tunables);
 
-        instr[count] = '\0';
-        /* count the fields */
         p = instr + strspn(instr, WHITESPACE);
         q = p;
         for (; *p; p = q + strspn(q, WHITESPACE)) {
@@ -1174,8 +1277,8 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
                 if (q == p)
                         break;
         }
-        if (cnt != 9) {
-                printk(KERN_INFO "bau tunable error: should be 9 numbers\n");
+        if (cnt != e) {
+                printk(KERN_INFO "bau tunable error: should be %d values\n", e);
                 return -EINVAL;
         }
 
@@ -1187,97 +1290,80 @@ static ssize_t tunables_write(struct file *file, const char __user *user,
                 switch (cnt) {
                 case 0:
                         if (val == 0) {
-                                max_bau_concurrent = MAX_BAU_CONCURRENT;
-                                max_bau_concurrent_constant =
-                                                        MAX_BAU_CONCURRENT;
+                                max_concurr = MAX_BAU_CONCURRENT;
+                                max_concurr_const = MAX_BAU_CONCURRENT;
                                 continue;
                         }
-                        bcp = &per_cpu(bau_control, smp_processor_id());
                         if (val < 1 || val > bcp->cpus_in_uvhub) {
                                 printk(KERN_DEBUG
                                 "Error: BAU max concurrent %d is invalid\n",
                                 val);
                                 return -EINVAL;
                         }
-                        max_bau_concurrent = val;
-                        max_bau_concurrent_constant = val;
-                        continue;
-                case 1:
-                        if (val == 0)
-                                plugged_delay = PLUGGED_DELAY;
-                        else
-                                plugged_delay = val;
-                        continue;
-                case 2:
-                        if (val == 0)
-                                plugsb4reset = PLUGSB4RESET;
-                        else
-                                plugsb4reset = val;
-                        continue;
-                case 3:
-                        if (val == 0)
-                                timeoutsb4reset = TIMEOUTSB4RESET;
-                        else
-                                timeoutsb4reset = val;
-                        continue;
-                case 4:
-                        if (val == 0)
-                                ipi_reset_limit = IPI_RESET_LIMIT;
-                        else
-                                ipi_reset_limit = val;
-                        continue;
-                case 5:
-                        if (val == 0)
-                                complete_threshold = COMPLETE_THRESHOLD;
-                        else
-                                complete_threshold = val;
-                        continue;
-                case 6:
-                        if (val == 0)
-                                congested_response_us = CONGESTED_RESPONSE_US;
-                        else
-                                congested_response_us = val;
-                        continue;
-                case 7:
-                        if (val == 0)
-                                congested_reps = CONGESTED_REPS;
-                        else
-                                congested_reps = val;
+                        max_concurr = val;
+                        max_concurr_const = val;
                         continue;
-                case 8:
+                default:
                         if (val == 0)
-                                congested_period = CONGESTED_PERIOD;
+                                *tunables[cnt].tunp = tunables[cnt].deflt;
                         else
-                                congested_period = val;
+                                *tunables[cnt].tunp = val;
                         continue;
                 }
                 if (q == p)
                         break;
         }
+        return 0;
+}
+
+/*
+ * Handle a write to debugfs. (/sys/kernel/debug/sgi_uv/bau_tunables)
+ */
+static ssize_t tunables_write(struct file *file, const char __user *user,
+                                size_t count, loff_t *data)
+{
+        int cpu;
+        int ret;
+        char instr[100];
+        struct bau_control *bcp;
+
+        if (count == 0 || count > sizeof(instr)-1)
+                return -EINVAL;
+        if (copy_from_user(instr, user, count))
+                return -EFAULT;
+
+        instr[count] = '\0';
+
+        bcp = &per_cpu(bau_control, smp_processor_id());
+
+        ret = parse_tunables_write(bcp, instr, count);
+        if (ret)
+                return ret;
+
         for_each_present_cpu(cpu) {
                 bcp = &per_cpu(bau_control, cpu);
-                bcp->max_bau_concurrent = max_bau_concurrent;
-                bcp->max_bau_concurrent_constant = max_bau_concurrent;
-                bcp->plugged_delay = plugged_delay;
-                bcp->plugsb4reset = plugsb4reset;
-                bcp->timeoutsb4reset = timeoutsb4reset;
-                bcp->ipi_reset_limit = ipi_reset_limit;
-                bcp->complete_threshold = complete_threshold;
-                bcp->congested_response_us = congested_response_us;
-                bcp->congested_reps = congested_reps;
-                bcp->congested_period = congested_period;
+                bcp->max_concurr =              max_concurr;
+                bcp->max_concurr_const =        max_concurr;
+                bcp->plugged_delay =            plugged_delay;
+                bcp->plugsb4reset =             plugsb4reset;
+                bcp->timeoutsb4reset =          timeoutsb4reset;
+                bcp->ipi_reset_limit =          ipi_reset_limit;
+                bcp->complete_threshold =       complete_threshold;
+                bcp->cong_response_us =         congested_respns_us;
+                bcp->cong_reps =                congested_reps;
+                bcp->cong_period =              congested_period;
         }
         return count;
 }
 
 static const struct seq_operations uv_ptc_seq_ops = {
-        .start          = uv_ptc_seq_start,
-        .next           = uv_ptc_seq_next,
-        .stop           = uv_ptc_seq_stop,
-        .show           = uv_ptc_seq_show
+        .start          = ptc_seq_start,
+        .next           = ptc_seq_next,
+        .stop           = ptc_seq_stop,
+        .show           = ptc_seq_show
 };
 
-static int uv_ptc_proc_open(struct inode *inode, struct file *file)
+static int ptc_proc_open(struct inode *inode, struct file *file)
 {
         return seq_open(file, &uv_ptc_seq_ops);
 }
@@ -1288,9 +1374,9 @@ static int tunables_open(struct inode *inode, struct file *file)
 }
 
 static const struct file_operations proc_uv_ptc_operations = {
-        .open           = uv_ptc_proc_open,
+        .open           = ptc_proc_open,
         .read           = seq_read,
-        .write          = uv_ptc_proc_write,
+        .write          = ptc_proc_write,
         .llseek         = seq_lseek,
         .release        = seq_release,
 };
@@ -1324,7 +1410,7 @@ static int __init uv_ptc_init(void)
                 return -EINVAL;
         }
         tunables_file = debugfs_create_file(UV_BAU_TUNABLES_FILE, 0600,
-                        tunables_dir, NULL, &tunables_fops);
+                                        tunables_dir, NULL, &tunables_fops);
         if (!tunables_file) {
                 printk(KERN_ERR "unable to create debugfs file %s\n",
                        UV_BAU_TUNABLES_FILE);
@@ -1336,24 +1422,24 @@ static int __init uv_ptc_init(void)
 /*
  * Initialize the sending side's sending buffers.
  */
-static void
-uv_activation_descriptor_init(int node, int pnode, int base_pnode)
+static void activation_descriptor_init(int node, int pnode, int base_pnode)
 {
         int i;
         int cpu;
         unsigned long pa;
         unsigned long m;
         unsigned long n;
+        size_t dsize;
         struct bau_desc *bau_desc;
         struct bau_desc *bd2;
         struct bau_control *bcp;
 
         /*
-         * each bau_desc is 64 bytes; there are 8 (UV_ITEMS_PER_DESCRIPTOR)
-         * per cpu; and one per cpu on the uvhub (UV_ADP_SIZE)
+         * each bau_desc is 64 bytes; there are 8 (ITEMS_PER_DESC)
+         * per cpu; and one per cpu on the uvhub (ADP_SZ)
          */
-        bau_desc = kmalloc_node(sizeof(struct bau_desc) * UV_ADP_SIZE
-                                * UV_ITEMS_PER_DESCRIPTOR, GFP_KERNEL, node);
+        dsize = sizeof(struct bau_desc) * ADP_SZ * ITEMS_PER_DESC;
+        bau_desc = kmalloc_node(dsize, GFP_KERNEL, node);
         BUG_ON(!bau_desc);
 
         pa = uv_gpa(bau_desc); /* need the real nasid*/
@@ -1361,27 +1447,25 @@ uv_activation_descriptor_init(int node, int pnode, int base_pnode)
         m = pa & uv_mmask;
 
         /* the 14-bit pnode */
-        uv_write_global_mmr64(pnode, UVH_LB_BAU_SB_DESCRIPTOR_BASE,
-                              (n << UV_DESC_BASE_PNODE_SHIFT | m));
+        write_mmr_descriptor_base(pnode, (n << UV_DESC_PSHIFT | m));
         /*
-         * Initializing all 8 (UV_ITEMS_PER_DESCRIPTOR) descriptors for each
+         * Initializing all 8 (ITEMS_PER_DESC) descriptors for each
          * cpu even though we only use the first one; one descriptor can
          * describe a broadcast to 256 uv hubs.
          */
-        for (i = 0, bd2 = bau_desc; i < (UV_ADP_SIZE*UV_ITEMS_PER_DESCRIPTOR);
-                i++, bd2++) {
+        for (i = 0, bd2 = bau_desc; i < (ADP_SZ * ITEMS_PER_DESC); i++, bd2++) {
                 memset(bd2, 0, sizeof(struct bau_desc));
-                bd2->header.sw_ack_flag = 1;
+                bd2->header.swack_flag =        1;
                 /*
                  * The base_dest_nasid set in the message header is the nasid
                  * of the first uvhub in the partition. The bit map will
                  * indicate destination pnode numbers relative to that base.
                  * They may not be consecutive if nasid striding is being used.
                  */
-                bd2->header.base_dest_nasid = UV_PNODE_TO_NASID(base_pnode);
-                bd2->header.dest_subnodeid = UV_LB_SUBNODEID;
-                bd2->header.command = UV_NET_ENDPOINT_INTD;
-                bd2->header.int_both = 1;
+                bd2->header.base_dest_nasid =   UV_PNODE_TO_NASID(base_pnode);
+                bd2->header.dest_subnodeid =    UV_LB_SUBNODEID;
+                bd2->header.command =           UV_NET_ENDPOINT_INTD;
+                bd2->header.int_both =          1;
                 /*
                  * all others need to be set to zero:
                  *   fairness chaining multilevel count replied_to
@@ -1401,57 +1485,55 @@ uv_activation_descriptor_init(int node, int pnode, int base_pnode)
  * - node is first node (kernel memory notion) on the uvhub
  * - pnode is the uvhub's physical identifier
  */
-static void
-uv_payload_queue_init(int node, int pnode)
+static void pq_init(int node, int pnode)
 {
-        int pn;
         int cpu;
+        size_t plsize;
         char *cp;
-        unsigned long pa;
-        struct bau_payload_queue_entry *pqp;
-        struct bau_payload_queue_entry *pqp_malloc;
+        void *vp;
+        unsigned long pn;
+        unsigned long first;
+        unsigned long pn_first;
+        unsigned long last;
+        struct bau_pq_entry *pqp;
         struct bau_control *bcp;
 
-        pqp = kmalloc_node((DEST_Q_SIZE + 1)
-                           * sizeof(struct bau_payload_queue_entry),
-                           GFP_KERNEL, node);
+        plsize = (DEST_Q_SIZE + 1) * sizeof(struct bau_pq_entry);
+        vp = kmalloc_node(plsize, GFP_KERNEL, node);
+        pqp = (struct bau_pq_entry *)vp;
         BUG_ON(!pqp);
-        pqp_malloc = pqp;
 
         cp = (char *)pqp + 31;
-        pqp = (struct bau_payload_queue_entry *)(((unsigned long)cp >> 5) << 5);
+        pqp = (struct bau_pq_entry *)(((unsigned long)cp >> 5) << 5);
 
         for_each_present_cpu(cpu) {
                 if (pnode != uv_cpu_to_pnode(cpu))
                         continue;
                 /* for every cpu on this pnode: */
                 bcp = &per_cpu(bau_control, cpu);
-                bcp->va_queue_first = pqp;
-                bcp->bau_msg_head = pqp;
-                bcp->va_queue_last = pqp + (DEST_Q_SIZE - 1);
+                bcp->queue_first        = pqp;
+                bcp->bau_msg_head       = pqp;
+                bcp->queue_last         = pqp + (DEST_Q_SIZE - 1);
         }
         /*
          * need the pnode of where the memory was really allocated
          */
-        pa = uv_gpa(pqp);
-        pn = pa >> uv_nshift;
-        uv_write_global_mmr64(pnode,
-                              UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST,
-                              ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) |
-                              uv_physnodeaddr(pqp));
-        uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL,
-                              uv_physnodeaddr(pqp));
-        uv_write_global_mmr64(pnode, UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST,
-                              (unsigned long)
-                              uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1)));
+        pn = uv_gpa(pqp) >> uv_nshift;
+        first = uv_physnodeaddr(pqp);
+        pn_first = ((unsigned long)pn << UV_PAYLOADQ_PNODE_SHIFT) | first;
+        last = uv_physnodeaddr(pqp + (DEST_Q_SIZE - 1));
+        write_mmr_payload_first(pnode, pn_first);
+        write_mmr_payload_tail(pnode, first);
+        write_mmr_payload_last(pnode, last);
+
         /* in effect, all msg_type's are set to MSG_NOOP */
-        memset(pqp, 0, sizeof(struct bau_payload_queue_entry) * DEST_Q_SIZE);
+        memset(pqp, 0, sizeof(struct bau_pq_entry) * DEST_Q_SIZE);
 }
 
 /*
  * Initialization of each UV hub's structures
  */
-static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode)
+static void __init init_uvhub(int uvhub, int vector, int base_pnode)
 {
         int node;
         int pnode;
@@ -1459,24 +1541,24 @@ static void __init uv_init_uvhub(int uvhub, int vector, int base_pnode)
 
         node = uvhub_to_first_node(uvhub);
         pnode = uv_blade_to_pnode(uvhub);
-        uv_activation_descriptor_init(node, pnode, base_pnode);
-        uv_payload_queue_init(node, pnode);
+
+        activation_descriptor_init(node, pnode, base_pnode);
+
+        pq_init(node, pnode);
         /*
          * The below initialization can't be in firmware because the
          * messaging IRQ will be determined by the OS.
          */
         apicid = uvhub_to_first_apicid(uvhub) | uv_apicid_hibits;
-        uv_write_global_mmr64(pnode, UVH_BAU_DATA_CONFIG,
-                                      ((apicid << 32) | vector));
+        write_mmr_data_config(pnode, ((apicid << 32) | vector));
 }
 
 /*
  * We will set BAU_MISC_CONTROL with a timeout period.
  * But the BIOS has set UVH_AGING_PRESCALE_SEL and UVH_TRANSACTION_TIMEOUT.
- * So the destination timeout period has be be calculated from them.
+ * So the destination timeout period has to be calculated from them.
  */
-static int
-calculate_destination_timeout(void)
+static int calculate_destination_timeout(void)
 {
         unsigned long mmr_image;
         int mult1;
@@ -1486,73 +1568,92 @@ calculate_destination_timeout(void)
         int ret;
         unsigned long ts_ns;
 
-        mult1 = UV_INTD_SOFT_ACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
-        mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
-        index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
-        mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
-        mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
-        base = timeout_base_ns[index];
-        ts_ns = base * mult1 * mult2;
-        ret = ts_ns / 1000;
+        if (is_uv1_hub()) {
+                mult1 = SOFTACK_TIMEOUT_PERIOD & BAU_MISC_CONTROL_MULT_MASK;
+                mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
+                index = (mmr_image >> BAU_URGENCY_7_SHIFT) & BAU_URGENCY_7_MASK;
+                mmr_image = uv_read_local_mmr(UVH_TRANSACTION_TIMEOUT);
+                mult2 = (mmr_image >> BAU_TRANS_SHIFT) & BAU_TRANS_MASK;
+                base = timeout_base_ns[index];
+                ts_ns = base * mult1 * mult2;
+                ret = ts_ns / 1000;
+        } else {
+                /* 4 bits  0/1 for 10/80us, 3 bits of multiplier */
+                mmr_image = uv_read_local_mmr(UVH_AGING_PRESCALE_SEL);
+                mmr_image = (mmr_image & UV_SA_MASK) >> UV_SA_SHFT;
+                if (mmr_image & (1L << UV2_ACK_UNITS_SHFT))
+                        mult1 = 80;
+                else
+                        mult1 = 10;
+                base = mmr_image & UV2_ACK_MASK;
+                ret = mult1 * base;
+        }
         return ret;
 }
 
+static void __init init_per_cpu_tunables(void)
+{
+        int cpu;
+        struct bau_control *bcp;
+
+        for_each_present_cpu(cpu) {
+                bcp = &per_cpu(bau_control, cpu);
+                bcp->baudisabled                = 0;
+                bcp->statp                      = &per_cpu(ptcstats, cpu);
+                /* time interval to catch a hardware stay-busy bug */
+                bcp->timeout_interval           = usec_2_cycles(2*timeout_us);
+                bcp->max_concurr                = max_concurr;
+                bcp->max_concurr_const          = max_concurr;
+                bcp->plugged_delay              = plugged_delay;
+                bcp->plugsb4reset               = plugsb4reset;
+                bcp->timeoutsb4reset            = timeoutsb4reset;
+                bcp->ipi_reset_limit            = ipi_reset_limit;
+                bcp->complete_threshold         = complete_threshold;
+                bcp->cong_response_us           = congested_respns_us;
+                bcp->cong_reps                  = congested_reps;
+                bcp->cong_period                = congested_period;
+        }
+}
+
 /*
- * initialize the bau_control structure for each cpu
+ * Scan all cpus to collect blade and socket summaries.
  */
-static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode)
+static int __init get_cpu_topology(int base_pnode,
+                                        struct uvhub_desc *uvhub_descs,
+                                        unsigned char *uvhub_mask)
 {
-        int i;
         int cpu;
-        int tcpu;
         int pnode;
         int uvhub;
-        int have_hmaster;
-        short socket = 0;
-        unsigned short socket_mask;
-        unsigned char *uvhub_mask;
+        int socket;
         struct bau_control *bcp;
         struct uvhub_desc *bdp;
         struct socket_desc *sdp;
-        struct bau_control *hmaster = NULL;
-        struct bau_control *smaster = NULL;
-        struct socket_desc {
-                short num_cpus;
-                short cpu_number[MAX_CPUS_PER_SOCKET];
-        };
-        struct uvhub_desc {
-                unsigned short socket_mask;
-                short num_cpus;
-                short uvhub;
-                short pnode;
-                struct socket_desc socket[2];
-        };
-        struct uvhub_desc *uvhub_descs;
-
-        timeout_us = calculate_destination_timeout();
 
-        uvhub_descs = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
-        memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
-        uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
         for_each_present_cpu(cpu) {
                 bcp = &per_cpu(bau_control, cpu);
+
                 memset(bcp, 0, sizeof(struct bau_control));
+
                 pnode = uv_cpu_hub_info(cpu)->pnode;
-                if ((pnode - base_part_pnode) >= UV_DISTRIBUTION_SIZE) {
+                if ((pnode - base_pnode) >= UV_DISTRIBUTION_SIZE) {
                         printk(KERN_EMERG
                                 "cpu %d pnode %d-%d beyond %d; BAU disabled\n",
-                                cpu, pnode, base_part_pnode,
-                                UV_DISTRIBUTION_SIZE);
+                                cpu, pnode, base_pnode, UV_DISTRIBUTION_SIZE);
                         return 1;
                 }
+
                 bcp->osnode = cpu_to_node(cpu);
-                bcp->partition_base_pnode = uv_partition_base_pnode;
+                bcp->partition_base_pnode = base_pnode;
+
                 uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
                 *(uvhub_mask + (uvhub/8)) |= (1 << (uvhub%8));
                 bdp = &uvhub_descs[uvhub];
+
                 bdp->num_cpus++;
                 bdp->uvhub = uvhub;
                 bdp->pnode = pnode;
+
                 /* kludge: 'assuming' one node per socket, and assuming that
                    disabling a socket just leaves a gap in node numbers */
                 socket = bcp->osnode & 1;
@@ -1561,84 +1662,129 @@ static int __init uv_init_per_cpu(int nuvhubs, int base_part_pnode)
                 sdp->cpu_number[sdp->num_cpus] = cpu;
                 sdp->num_cpus++;
                 if (sdp->num_cpus > MAX_CPUS_PER_SOCKET) {
-                        printk(KERN_EMERG "%d cpus per socket invalid\n", sdp->num_cpus);
+                        printk(KERN_EMERG "%d cpus per socket invalid\n",
+                                sdp->num_cpus);
                         return 1;
                 }
         }
+        return 0;
+}
+
+/*
+ * Each socket is to get a local array of pnodes/hubs.
+ */
+static void make_per_cpu_thp(struct bau_control *smaster)
+{
+        int cpu;
+        size_t hpsz = sizeof(struct hub_and_pnode) * num_possible_cpus();
+
+        smaster->thp = kmalloc_node(hpsz, GFP_KERNEL, smaster->osnode);
+        memset(smaster->thp, 0, hpsz);
+        for_each_present_cpu(cpu) {
+                smaster->thp[cpu].pnode = uv_cpu_hub_info(cpu)->pnode;
+                smaster->thp[cpu].uvhub = uv_cpu_hub_info(cpu)->numa_blade_id;
+        }
+}
+
+/*
+ * Initialize all the per_cpu information for the cpu's on a given socket,
+ * given what has been gathered into the socket_desc struct.
+ * And reports the chosen hub and socket masters back to the caller.
+ */
+static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
+                        struct bau_control **smasterp,
+                        struct bau_control **hmasterp)
+{
+        int i;
+        int cpu;
+        struct bau_control *bcp;
+
+        for (i = 0; i < sdp->num_cpus; i++) {
+                cpu = sdp->cpu_number[i];
+                bcp = &per_cpu(bau_control, cpu);
+                bcp->cpu = cpu;
+                if (i == 0) {
+                        *smasterp = bcp;
+                        if (!(*hmasterp))
+                                *hmasterp = bcp;
+                }
+                bcp->cpus_in_uvhub = bdp->num_cpus;
+                bcp->cpus_in_socket = sdp->num_cpus;
+                bcp->socket_master = *smasterp;
+                bcp->uvhub = bdp->uvhub;
+                bcp->uvhub_master = *hmasterp;
+                bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id;
+                if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
+                        printk(KERN_EMERG "%d cpus per uvhub invalid\n",
+                                bcp->uvhub_cpu);
+                        return 1;
+                }
+        }
+        return 0;
+}
+
+/*
+ * Summarize the blade and socket topology into the per_cpu structures.
+ */
+static int __init summarize_uvhub_sockets(int nuvhubs,
+                        struct uvhub_desc *uvhub_descs,
+                        unsigned char *uvhub_mask)
+{
+        int socket;
+        int uvhub;
+        unsigned short socket_mask;
+
         for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
+                struct uvhub_desc *bdp;
+                struct bau_control *smaster = NULL;
+                struct bau_control *hmaster = NULL;
+
                 if (!(*(uvhub_mask + (uvhub/8)) & (1 << (uvhub%8))))
                         continue;
-                have_hmaster = 0;
+
                 bdp = &uvhub_descs[uvhub];
                 socket_mask = bdp->socket_mask;
                 socket = 0;
                 while (socket_mask) {
-                        if (!(socket_mask & 1))
-                                goto nextsocket;
-                        sdp = &bdp->socket[socket];
-                        for (i = 0; i < sdp->num_cpus; i++) {
-                                cpu = sdp->cpu_number[i];
-                                bcp = &per_cpu(bau_control, cpu);
-                                bcp->cpu = cpu;
-                                if (i == 0) {
-                                        smaster = bcp;
-                                        if (!have_hmaster) {
-                                                have_hmaster++;
-                                                hmaster = bcp;
-                                        }
-                                }
-                                bcp->cpus_in_uvhub = bdp->num_cpus;
-                                bcp->cpus_in_socket = sdp->num_cpus;
-                                bcp->socket_master = smaster;
-                                bcp->uvhub = bdp->uvhub;
-                                bcp->uvhub_master = hmaster;
-                                bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->
-                                                blade_processor_id;
-                                if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
-                                        printk(KERN_EMERG
-                                                "%d cpus per uvhub invalid\n",
-                                                bcp->uvhub_cpu);
+                        struct socket_desc *sdp;
+                        if ((socket_mask & 1)) {
+                                sdp = &bdp->socket[socket];
+                                if (scan_sock(sdp, bdp, &smaster, &hmaster))
                                         return 1;
-                                }
                         }
-nextsocket:
                         socket++;
                         socket_mask = (socket_mask >> 1);
-                        /* each socket gets a local array of pnodes/hubs */
-                        bcp = smaster;
-                        bcp->target_hub_and_pnode = kmalloc_node(
-                                sizeof(struct hub_and_pnode) *
-                                num_possible_cpus(), GFP_KERNEL, bcp->osnode);
-                        memset(bcp->target_hub_and_pnode, 0,
-                                sizeof(struct hub_and_pnode) *
-                                num_possible_cpus());
-                        for_each_present_cpu(tcpu) {
-                                bcp->target_hub_and_pnode[tcpu].pnode =
-                                        uv_cpu_hub_info(tcpu)->pnode;
-                                bcp->target_hub_and_pnode[tcpu].uvhub =
-                                        uv_cpu_hub_info(tcpu)->numa_blade_id;
-                        }
+                        make_per_cpu_thp(smaster);
                 }
         }
+        return 0;
+}
+
+/*
+ * initialize the bau_control structure for each cpu
+ */
+static int __init init_per_cpu(int nuvhubs, int base_part_pnode)
+{
+        unsigned char *uvhub_mask;
+        void *vp;
+        struct uvhub_desc *uvhub_descs;
+
+        timeout_us = calculate_destination_timeout();
+
+        vp = kmalloc(nuvhubs * sizeof(struct uvhub_desc), GFP_KERNEL);
+        uvhub_descs = (struct uvhub_desc *)vp;
+        memset(uvhub_descs, 0, nuvhubs * sizeof(struct uvhub_desc));
+        uvhub_mask = kzalloc((nuvhubs+7)/8, GFP_KERNEL);
+
+        if (get_cpu_topology(base_part_pnode, uvhub_descs, uvhub_mask))
+                return 1;
+
+        if (summarize_uvhub_sockets(nuvhubs, uvhub_descs, uvhub_mask))
+                return 1;
+
         kfree(uvhub_descs);
         kfree(uvhub_mask);
-        for_each_present_cpu(cpu) {
-                bcp = &per_cpu(bau_control, cpu);
-                bcp->baudisabled = 0;
-                bcp->statp = &per_cpu(ptcstats, cpu);
-                /* time interval to catch a hardware stay-busy bug */
-                bcp->timeout_interval = microsec_2_cycles(2*timeout_us);
-                bcp->max_bau_concurrent = max_bau_concurrent;
-                bcp->max_bau_concurrent_constant = max_bau_concurrent;
-                bcp->plugged_delay = plugged_delay;
-                bcp->plugsb4reset = plugsb4reset;
-                bcp->timeoutsb4reset = timeoutsb4reset;
-                bcp->ipi_reset_limit = ipi_reset_limit;
-                bcp->complete_threshold = complete_threshold;
-                bcp->congested_response_us = congested_response_us;
-                bcp->congested_reps = congested_reps;
-                bcp->congested_period = congested_period;
-        }
+        init_per_cpu_tunables();
         return 0;
 }
 
@@ -1651,8 +1797,9 @@ static int __init uv_bau_init(void)
         int pnode;
         int nuvhubs;
         int cur_cpu;
+        int cpus;
         int vector;
-        unsigned long mmr;
+        cpumask_var_t *mask;
 
         if (!is_uv_system())
                 return 0;
@@ -1660,24 +1807,25 @@ static int __init uv_bau_init(void)
         if (nobau)
                 return 0;
 
-        for_each_possible_cpu(cur_cpu)
-                zalloc_cpumask_var_node(&per_cpu(uv_flush_tlb_mask, cur_cpu),
-                                       GFP_KERNEL, cpu_to_node(cur_cpu));
+        for_each_possible_cpu(cur_cpu) {
+                mask = &per_cpu(uv_flush_tlb_mask, cur_cpu);
+                zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cur_cpu));
+        }
 
         uv_nshift = uv_hub_info->m_val;
         uv_mmask = (1UL << uv_hub_info->m_val) - 1;
         nuvhubs = uv_num_possible_blades();
         spin_lock_init(&disable_lock);
-        congested_cycles = microsec_2_cycles(congested_response_us);
+        congested_cycles = usec_2_cycles(congested_respns_us);
 
-        uv_partition_base_pnode = 0x7fffffff;
+        uv_base_pnode = 0x7fffffff;
         for (uvhub = 0; uvhub < nuvhubs; uvhub++) {
-                if (uv_blade_nr_possible_cpus(uvhub) &&
-                        (uv_blade_to_pnode(uvhub) < uv_partition_base_pnode))
-                        uv_partition_base_pnode = uv_blade_to_pnode(uvhub);
+                cpus = uv_blade_nr_possible_cpus(uvhub);
+                if (cpus && (uv_blade_to_pnode(uvhub) < uv_base_pnode))
+                        uv_base_pnode = uv_blade_to_pnode(uvhub);
         }
 
-        if (uv_init_per_cpu(nuvhubs, uv_partition_base_pnode)) {
+        if (init_per_cpu(nuvhubs, uv_base_pnode)) {
                 nobau = 1;
                 return 0;
         }
@@ -1685,21 +1833,21 @@ static int __init uv_bau_init(void)
         vector = UV_BAU_MESSAGE;
         for_each_possible_blade(uvhub)
                 if (uv_blade_nr_possible_cpus(uvhub))
-                        uv_init_uvhub(uvhub, vector, uv_partition_base_pnode);
+                        init_uvhub(uvhub, vector, uv_base_pnode);
 
-        uv_enable_timeouts();
+        enable_timeouts();
         alloc_intr_gate(vector, uv_bau_message_intr1);
 
         for_each_possible_blade(uvhub) {
                 if (uv_blade_nr_possible_cpus(uvhub)) {
+                        unsigned long val;
+                        unsigned long mmr;
                         pnode = uv_blade_to_pnode(uvhub);
                         /* INIT the bau */
-                        uv_write_global_mmr64(pnode,
-                                        UVH_LB_BAU_SB_ACTIVATION_CONTROL,
-                                        ((unsigned long)1 << 63));
+                        val = 1L << 63;
+                        write_gmmr_activation(pnode, val);
                         mmr = 1; /* should be 1 to broadcast to both sockets */
-                        uv_write_global_mmr64(pnode, UVH_BAU_DATA_BROADCAST,
-                                                mmr);
+                        write_mmr_data_broadcast(pnode, mmr);
                 }
         }
 
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 0eb90184515f..9f29a01ee1b3 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -99,8 +99,12 @@ static void uv_rtc_send_IPI(int cpu)
 /* Check for an RTC interrupt pending */
 static int uv_intr_pending(int pnode)
 {
-        return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
-                UVH_EVENT_OCCURRED0_RTC1_MASK;
+        if (is_uv1_hub())
+                return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
+                        UV1H_EVENT_OCCURRED0_RTC1_MASK;
+        else
+                return uv_read_global_mmr64(pnode, UV2H_EVENT_OCCURRED2) &
+                        UV2H_EVENT_OCCURRED2_RTC_1_MASK;
 }
 
 /* Setup interrupt and return non-zero if early expiration occurred. */
@@ -114,8 +118,12 @@ static int uv_setup_intr(int cpu, u64 expires)
                 UVH_RTC1_INT_CONFIG_M_MASK);
         uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
 
-        uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
-                UVH_EVENT_OCCURRED0_RTC1_MASK);
+        if (is_uv1_hub())
+                uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
+                                UV1H_EVENT_OCCURRED0_RTC1_MASK);
+        else
+                uv_write_global_mmr64(pnode, UV2H_EVENT_OCCURRED2_ALIAS,
+                                UV2H_EVENT_OCCURRED2_RTC_1_MASK);
 
         val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
                 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
diff --git a/arch/x86/vdso/Makefile b/arch/x86/vdso/Makefile
index b6552b189bcd..bef0bc962400 100644
--- a/arch/x86/vdso/Makefile
+++ b/arch/x86/vdso/Makefile
@@ -11,7 +11,7 @@ vdso-install-$(VDSO32-y)	+= $(vdso32-images)
 
 
 # files to link into the vdso
-vobjs-y := vdso-note.o vclock_gettime.o vgetcpu.o vvar.o
+vobjs-y := vdso-note.o vclock_gettime.o vgetcpu.o
 
 # files to link into kernel
 obj-$(VDSO64-y)                 += vma.o vdso.o
@@ -37,11 +37,24 @@ $(obj)/%.so: OBJCOPYFLAGS := -S
 $(obj)/%.so: $(obj)/%.so.dbg FORCE
         $(call if_changed,objcopy)
 
+#
+# Don't omit frame pointers for ease of userspace debugging, but do
+# optimize sibling calls.
+#
 CFL := $(PROFILING) -mcmodel=small -fPIC -O2 -fasynchronous-unwind-tables -m64 \
-       $(filter -g%,$(KBUILD_CFLAGS)) $(call cc-option, -fno-stack-protector)
+       $(filter -g%,$(KBUILD_CFLAGS)) $(call cc-option, -fno-stack-protector) \
+       -fno-omit-frame-pointer -foptimize-sibling-calls
 
 $(vobjs): KBUILD_CFLAGS += $(CFL)
 
+#
+# vDSO code runs in userspace and -pg doesn't help with profiling anyway.
+#
+CFLAGS_REMOVE_vdso-note.o = -pg
+CFLAGS_REMOVE_vclock_gettime.o = -pg
+CFLAGS_REMOVE_vgetcpu.o = -pg
+CFLAGS_REMOVE_vvar.o = -pg
+
 targets += vdso-syms.lds
 obj-$(VDSO64-y)                 += vdso-syms.lds
 
diff --git a/arch/x86/vdso/vclock_gettime.c b/arch/x86/vdso/vclock_gettime.c
index ee55754cc3c5..a724905fdae7 100644
--- a/arch/x86/vdso/vclock_gettime.c
+++ b/arch/x86/vdso/vclock_gettime.c
@@ -2,7 +2,7 @@
  * Copyright 2006 Andi Kleen, SUSE Labs.
  * Subject to the GNU Public License, v.2
  *
- * Fast user context implementation of clock_gettime and gettimeofday.
+ * Fast user context implementation of clock_gettime, gettimeofday, and time.
  *
  * The code should have no internal unresolved relocations.
  * Check with readelf after changing.
@@ -22,9 +22,8 @@
 #include <asm/hpet.h>
 #include <asm/unistd.h>
 #include <asm/io.h>
-#include "vextern.h"
 
-#define gtod vdso_vsyscall_gtod_data
+#define gtod (&VVAR(vsyscall_gtod_data))
 
 notrace static long vdso_fallback_gettime(long clock, struct timespec *ts)
 {
@@ -56,22 +55,6 @@ notrace static noinline int do_realtime(struct timespec *ts)
         return 0;
 }
 
-/* Copy of the version in kernel/time.c which we cannot directly access */
-notrace static void
-vset_normalized_timespec(struct timespec *ts, long sec, long nsec)
-{
-        while (nsec >= NSEC_PER_SEC) {
-                nsec -= NSEC_PER_SEC;
-                ++sec;
-        }
-        while (nsec < 0) {
-                nsec += NSEC_PER_SEC;
-                --sec;
-        }
-        ts->tv_sec = sec;
-        ts->tv_nsec = nsec;
-}
-
 notrace static noinline int do_monotonic(struct timespec *ts)
 {
         unsigned long seq, ns, secs;
@@ -82,7 +65,17 @@ notrace static noinline int do_monotonic(struct timespec *ts)
                 secs += gtod->wall_to_monotonic.tv_sec;
                 ns += gtod->wall_to_monotonic.tv_nsec;
         } while (unlikely(read_seqretry(&gtod->lock, seq)));
-        vset_normalized_timespec(ts, secs, ns);
+
+        /* wall_time_nsec, vgetns(), and wall_to_monotonic.tv_nsec
+         * are all guaranteed to be nonnegative.
+         */
+        while (ns >= NSEC_PER_SEC) {
+                ns -= NSEC_PER_SEC;
+                ++secs;
+        }
+        ts->tv_sec = secs;
+        ts->tv_nsec = ns;
+
         return 0;
 }
 
@@ -107,7 +100,17 @@ notrace static noinline int do_monotonic_coarse(struct timespec *ts)
                 secs += gtod->wall_to_monotonic.tv_sec;
                 ns += gtod->wall_to_monotonic.tv_nsec;
         } while (unlikely(read_seqretry(&gtod->lock, seq)));
-        vset_normalized_timespec(ts, secs, ns);
+
+        /* wall_time_nsec and wall_to_monotonic.tv_nsec are
+         * guaranteed to be between 0 and NSEC_PER_SEC.
+         */
+        if (ns >= NSEC_PER_SEC) {
+                ns -= NSEC_PER_SEC;
+                ++secs;
+        }
+        ts->tv_sec = secs;
+        ts->tv_nsec = ns;
+
         return 0;
 }
 
@@ -157,3 +160,32 @@ notrace int __vdso_gettimeofday(struct timeval *tv, struct timezone *tz)
 }
 int gettimeofday(struct timeval *, struct timezone *)
         __attribute__((weak, alias("__vdso_gettimeofday")));
+
+/* This will break when the xtime seconds get inaccurate, but that is
+ * unlikely */
+
+static __always_inline long time_syscall(long *t)
+{
+        long secs;
+        asm volatile("syscall"
+                     : "=a" (secs)
+                     : "0" (__NR_time), "D" (t) : "cc", "r11", "cx", "memory");
+        return secs;
+}
+
+notrace time_t __vdso_time(time_t *t)
+{
+        time_t result;
+
+        if (unlikely(!VVAR(vsyscall_gtod_data).sysctl_enabled))
+                return time_syscall(t);
+
+        /* This is atomic on x86_64 so we don't need any locks. */
+        result = ACCESS_ONCE(VVAR(vsyscall_gtod_data).wall_time_sec);
+
+        if (t)
+                *t = result;
+        return result;
+}
+int time(time_t *t)
+        __attribute__((weak, alias("__vdso_time")));
diff --git a/arch/x86/vdso/vdso.lds.S b/arch/x86/vdso/vdso.lds.S
index 4e5dd3b4de7f..b96b2677cad8 100644
--- a/arch/x86/vdso/vdso.lds.S
+++ b/arch/x86/vdso/vdso.lds.S
@@ -23,15 +23,10 @@ VERSION {
                 __vdso_gettimeofday;
                 getcpu;
                 __vdso_getcpu;
+                time;
+                __vdso_time;
         local: *;
         };
 }
 
 VDSO64_PRELINK = VDSO_PRELINK;
-
-/*
- * Define VDSO64_x for each VEXTERN(x), for use via VDSO64_SYMBOL.
- */
-#define VEXTERN(x)      VDSO64_ ## x = vdso_ ## x;
-#include "vextern.h"
-#undef  VEXTERN
diff --git a/arch/x86/vdso/vextern.h b/arch/x86/vdso/vextern.h
deleted file mode 100644
index 1683ba2ae3e8..000000000000
--- a/arch/x86/vdso/vextern.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef VEXTERN
-#include <asm/vsyscall.h>
-#define VEXTERN(x) \
-        extern typeof(x) *vdso_ ## x __attribute__((visibility("hidden")));
-#endif
-
-#define VMAGIC 0xfeedbabeabcdefabUL
-
-/* Any kernel variables used in the vDSO must be exported in the main
-   kernel's vmlinux.lds.S/vsyscall.h/proper __section and
-   put into vextern.h and be referenced as a pointer with vdso prefix.
-   The main kernel later fills in the values.   */
-
-VEXTERN(jiffies)
-VEXTERN(vgetcpu_mode)
-VEXTERN(vsyscall_gtod_data)
diff --git a/arch/x86/vdso/vgetcpu.c b/arch/x86/vdso/vgetcpu.c
index 9fbc6b20026b..5463ad558573 100644
--- a/arch/x86/vdso/vgetcpu.c
+++ b/arch/x86/vdso/vgetcpu.c
@@ -11,14 +11,13 @@
 #include <linux/time.h>
 #include <asm/vsyscall.h>
 #include <asm/vgtod.h>
-#include "vextern.h"
 
 notrace long
 __vdso_getcpu(unsigned *cpu, unsigned *node, struct getcpu_cache *unused)
 {
         unsigned int p;
 
-        if (*vdso_vgetcpu_mode == VGETCPU_RDTSCP) {
+        if (VVAR(vgetcpu_mode) == VGETCPU_RDTSCP) {
                 /* Load per CPU data from RDTSCP */
                 native_read_tscp(&p);
         } else {
diff --git a/arch/x86/vdso/vma.c b/arch/x86/vdso/vma.c
index 4b5d26f108bb..7abd2be0f9b9 100644
--- a/arch/x86/vdso/vma.c
+++ b/arch/x86/vdso/vma.c
@@ -15,9 +15,6 @@
 #include <asm/proto.h>
 #include <asm/vdso.h>
 
-#include "vextern.h"            /* Just for VMAGIC.  */
-#undef VEXTERN
-
 unsigned int __read_mostly vdso_enabled = 1;
 
 extern char vdso_start[], vdso_end[];
@@ -26,20 +23,10 @@ extern unsigned short vdso_sync_cpuid;
 static struct page **vdso_pages;
 static unsigned vdso_size;
 
-static inline void *var_ref(void *p, char *name)
-{
-        if (*(void **)p != (void *)VMAGIC) {
-                printk("VDSO: variable %s broken\n", name);
-                vdso_enabled = 0;
-        }
-        return p;
-}
-
 static int __init init_vdso_vars(void)
 {
         int npages = (vdso_end - vdso_start + PAGE_SIZE - 1) / PAGE_SIZE;
         int i;
-        char *vbase;
 
         vdso_size = npages << PAGE_SHIFT;
         vdso_pages = kmalloc(sizeof(struct page *) * npages, GFP_KERNEL);
@@ -54,20 +41,6 @@ static int __init init_vdso_vars(void)
                 copy_page(page_address(p), vdso_start + i*PAGE_SIZE);
         }
 
-        vbase = vmap(vdso_pages, npages, 0, PAGE_KERNEL);
-        if (!vbase)
-                goto oom;
-
-        if (memcmp(vbase, "\177ELF", 4)) {
-                printk("VDSO: I'm broken; not ELF\n");
-                vdso_enabled = 0;
-        }
-
-#define VEXTERN(x) \
-        *(typeof(__ ## x) **) var_ref(VDSO64_SYMBOL(vbase, x), #x) = &__ ## x;
-#include "vextern.h"
-#undef VEXTERN
-        vunmap(vbase);
         return 0;
 
  oom:
diff --git a/arch/x86/vdso/vvar.c b/arch/x86/vdso/vvar.c
deleted file mode 100644
index 1b7e703684f9..000000000000
--- a/arch/x86/vdso/vvar.c
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Define pointer to external vDSO variables.
-   These are part of the vDSO. The kernel fills in the real addresses
-   at boot time. This is done because when the vdso is linked the
-   kernel isn't yet and we don't know the final addresses. */
-#include <linux/kernel.h>
-#include <linux/time.h>
-#include <asm/vsyscall.h>
-#include <asm/timex.h>
-#include <asm/vgtod.h>
-
-#define VEXTERN(x) typeof (__ ## x) *const vdso_ ## x = (void *)VMAGIC;
-#include "vextern.h"
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index 02d752460371..dc708dcc62f1 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -75,67 +75,12 @@
 #include "mmu.h"
 #include "debugfs.h"
 
-#define MMU_UPDATE_HISTO        30
-
 /*
  * Protects atomic reservation decrease/increase against concurrent increases.
  * Also protects non-atomic updates of current_pages and balloon lists.
  */
 DEFINE_SPINLOCK(xen_reservation_lock);
 
-#ifdef CONFIG_XEN_DEBUG_FS
-
-static struct {
-        u32 pgd_update;
-        u32 pgd_update_pinned;
-        u32 pgd_update_batched;
-
-        u32 pud_update;
-        u32 pud_update_pinned;
-        u32 pud_update_batched;
-
-        u32 pmd_update;
-        u32 pmd_update_pinned;
-        u32 pmd_update_batched;
-
-        u32 pte_update;
-        u32 pte_update_pinned;
-        u32 pte_update_batched;
-
-        u32 mmu_update;
-        u32 mmu_update_extended;
-        u32 mmu_update_histo[MMU_UPDATE_HISTO];
-
-        u32 prot_commit;
-        u32 prot_commit_batched;
-
-        u32 set_pte_at;
-        u32 set_pte_at_batched;
-        u32 set_pte_at_pinned;
-        u32 set_pte_at_current;
-        u32 set_pte_at_kernel;
-} mmu_stats;
-
-static u8 zero_stats;
-
-static inline void check_zero(void)
-{
-        if (unlikely(zero_stats)) {
-                memset(&mmu_stats, 0, sizeof(mmu_stats));
-                zero_stats = 0;
-        }
-}
-
-#define ADD_STATS(elem, val)                    \
-        do { check_zero(); mmu_stats.elem += (val); } while(0)
-
-#else  /* !CONFIG_XEN_DEBUG_FS */
-
-#define ADD_STATS(elem, val)    do { (void)(val); } while(0)
-
-#endif /* CONFIG_XEN_DEBUG_FS */
-
-
 /*
  * Identity map, in addition to plain kernel map.  This needs to be
  * large enough to allocate page table pages to allocate the rest.
@@ -243,11 +188,6 @@ static bool xen_page_pinned(void *ptr)
         return PagePinned(page);
 }
 
-static bool xen_iomap_pte(pte_t pte)
-{
-        return pte_flags(pte) & _PAGE_IOMAP;
-}
-
 void xen_set_domain_pte(pte_t *ptep, pte_t pteval, unsigned domid)
 {
         struct multicall_space mcs;
@@ -257,7 +197,7 @@ void xen_set_domain_pte(pte_t *ptep, pte_t pteval, unsigned domid)
         u = mcs.args;
 
         /* ptep might be kmapped when using 32-bit HIGHPTE */
-        u->ptr = arbitrary_virt_to_machine(ptep).maddr;
+        u->ptr = virt_to_machine(ptep).maddr;
         u->val = pte_val_ma(pteval);
 
         MULTI_mmu_update(mcs.mc, mcs.args, 1, NULL, domid);
@@ -266,11 +206,6 @@ void xen_set_domain_pte(pte_t *ptep, pte_t pteval, unsigned domid)
 }
 EXPORT_SYMBOL_GPL(xen_set_domain_pte);
 
-static void xen_set_iomap_pte(pte_t *ptep, pte_t pteval)
-{
-        xen_set_domain_pte(ptep, pteval, DOMID_IO);
-}
-
 static void xen_extend_mmu_update(const struct mmu_update *update)
 {
         struct multicall_space mcs;
@@ -279,27 +214,17 @@ static void xen_extend_mmu_update(const struct mmu_update *update)
         mcs = xen_mc_extend_args(__HYPERVISOR_mmu_update, sizeof(*u));
 
         if (mcs.mc != NULL) {
-                ADD_STATS(mmu_update_extended, 1);
-                ADD_STATS(mmu_update_histo[mcs.mc->args[1]], -1);
-
                 mcs.mc->args[1]++;
-
-                if (mcs.mc->args[1] < MMU_UPDATE_HISTO)
-                        ADD_STATS(mmu_update_histo[mcs.mc->args[1]], 1);
-                else
-                        ADD_STATS(mmu_update_histo[0], 1);
         } else {
-                ADD_STATS(mmu_update, 1);
                 mcs = __xen_mc_entry(sizeof(*u));
                 MULTI_mmu_update(mcs.mc, mcs.args, 1, NULL, DOMID_SELF);
-                ADD_STATS(mmu_update_histo[1], 1);
         }
 
         u = mcs.args;
         *u = *update;
 }
 
-void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
+static void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
 {
         struct mmu_update u;
 
@@ -312,17 +237,13 @@ void xen_set_pmd_hyper(pmd_t *ptr, pmd_t val)
         u.val = pmd_val_ma(val);
         xen_extend_mmu_update(&u);
 
-        ADD_STATS(pmd_update_batched, paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU);
-
         xen_mc_issue(PARAVIRT_LAZY_MMU);
 
         preempt_enable();
 }
 
-void xen_set_pmd(pmd_t *ptr, pmd_t val)
+static void xen_set_pmd(pmd_t *ptr, pmd_t val)
 {
-        ADD_STATS(pmd_update, 1);
-
         /* If page is not pinned, we can just update the entry
            directly */
         if (!xen_page_pinned(ptr)) {
@@ -330,8 +251,6 @@ void xen_set_pmd(pmd_t *ptr, pmd_t val)
                 return;
         }
 
-        ADD_STATS(pmd_update_pinned, 1);
-
         xen_set_pmd_hyper(ptr, val);
 }
 
@@ -344,35 +263,34 @@ void set_pte_mfn(unsigned long vaddr, unsigned long mfn, pgprot_t flags)
         set_pte_vaddr(vaddr, mfn_pte(mfn, flags));
 }
 
-void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
-                    pte_t *ptep, pte_t pteval)
+static bool xen_batched_set_pte(pte_t *ptep, pte_t pteval)
 {
-        if (xen_iomap_pte(pteval)) {
-                xen_set_iomap_pte(ptep, pteval);
-                goto out;
-        }
+        struct mmu_update u;
 
-        ADD_STATS(set_pte_at, 1);
-//      ADD_STATS(set_pte_at_pinned, xen_page_pinned(ptep));
-        ADD_STATS(set_pte_at_current, mm == current->mm);
-        ADD_STATS(set_pte_at_kernel, mm == &init_mm);
+        if (paravirt_get_lazy_mode() != PARAVIRT_LAZY_MMU)
+                return false;
 
-        if (mm == current->mm || mm == &init_mm) {
-                if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU) {
-                        struct multicall_space mcs;
-                        mcs = xen_mc_entry(0);
+        xen_mc_batch();
 
-                        MULTI_update_va_mapping(mcs.mc, addr, pteval, 0);
-                        ADD_STATS(set_pte_at_batched, 1);
-                        xen_mc_issue(PARAVIRT_LAZY_MMU);
-                        goto out;
-                } else
-                        if (HYPERVISOR_update_va_mapping(addr, pteval, 0) == 0)
-                                goto out;
-        }
-        xen_set_pte(ptep, pteval);
+        u.ptr = virt_to_machine(ptep).maddr | MMU_NORMAL_PT_UPDATE;
+        u.val = pte_val_ma(pteval);
+        xen_extend_mmu_update(&u);
+
+        xen_mc_issue(PARAVIRT_LAZY_MMU);
 
-out:    return;
+        return true;
+}
+
+static void xen_set_pte(pte_t *ptep, pte_t pteval)
+{
+        if (!xen_batched_set_pte(ptep, pteval))
+                native_set_pte(ptep, pteval);
+}
+
+static void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
+                    pte_t *ptep, pte_t pteval)
+{
+        xen_set_pte(ptep, pteval);
 }
 
 pte_t xen_ptep_modify_prot_start(struct mm_struct *mm,
@@ -389,13 +307,10 @@ void xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
 
         xen_mc_batch();
 
-        u.ptr = arbitrary_virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD;
+        u.ptr = virt_to_machine(ptep).maddr | MMU_PT_UPDATE_PRESERVE_AD;
         u.val = pte_val_ma(pte);
         xen_extend_mmu_update(&u);
 
-        ADD_STATS(prot_commit, 1);
-        ADD_STATS(prot_commit_batched, paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU);
-
         xen_mc_issue(PARAVIRT_LAZY_MMU);
 }
 
@@ -463,7 +378,7 @@ static pteval_t iomap_pte(pteval_t val)
         return val;
 }
 
-pteval_t xen_pte_val(pte_t pte)
+static pteval_t xen_pte_val(pte_t pte)
 {
         pteval_t pteval = pte.pte;
 
@@ -480,7 +395,7 @@ pteval_t xen_pte_val(pte_t pte)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pte_val);
 
-pgdval_t xen_pgd_val(pgd_t pgd)
+static pgdval_t xen_pgd_val(pgd_t pgd)
 {
         return pte_mfn_to_pfn(pgd.pgd);
 }
@@ -511,7 +426,7 @@ void xen_set_pat(u64 pat)
         WARN_ON(pat != 0x0007010600070106ull);
 }
 
-pte_t xen_make_pte(pteval_t pte)
+static pte_t xen_make_pte(pteval_t pte)
 {
         phys_addr_t addr = (pte & PTE_PFN_MASK);
 
@@ -581,20 +496,20 @@ pte_t xen_make_pte_debug(pteval_t pte)
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pte_debug);
 #endif
 
-pgd_t xen_make_pgd(pgdval_t pgd)
+static pgd_t xen_make_pgd(pgdval_t pgd)
 {
         pgd = pte_pfn_to_mfn(pgd);
         return native_make_pgd(pgd);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pgd);
 
-pmdval_t xen_pmd_val(pmd_t pmd)
+static pmdval_t xen_pmd_val(pmd_t pmd)
 {
         return pte_mfn_to_pfn(pmd.pmd);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pmd_val);
 
-void xen_set_pud_hyper(pud_t *ptr, pud_t val)
+static void xen_set_pud_hyper(pud_t *ptr, pud_t val)
 {
         struct mmu_update u;
 
@@ -607,17 +522,13 @@ void xen_set_pud_hyper(pud_t *ptr, pud_t val)
         u.val = pud_val_ma(val);
         xen_extend_mmu_update(&u);
 
-        ADD_STATS(pud_update_batched, paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU);
-
         xen_mc_issue(PARAVIRT_LAZY_MMU);
 
         preempt_enable();
 }
 
-void xen_set_pud(pud_t *ptr, pud_t val)
+static void xen_set_pud(pud_t *ptr, pud_t val)
 {
-        ADD_STATS(pud_update, 1);
-
         /* If page is not pinned, we can just update the entry
            directly */
         if (!xen_page_pinned(ptr)) {
@@ -625,56 +536,28 @@ void xen_set_pud(pud_t *ptr, pud_t val)
                 return;
         }
 
-        ADD_STATS(pud_update_pinned, 1);
-
         xen_set_pud_hyper(ptr, val);
 }
 
-void xen_set_pte(pte_t *ptep, pte_t pte)
-{
-        if (xen_iomap_pte(pte)) {
-                xen_set_iomap_pte(ptep, pte);
-                return;
-        }
-
-        ADD_STATS(pte_update, 1);
-//      ADD_STATS(pte_update_pinned, xen_page_pinned(ptep));
-        ADD_STATS(pte_update_batched, paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU);
-
 #ifdef CONFIG_X86_PAE
-        ptep->pte_high = pte.pte_high;
-        smp_wmb();
-        ptep->pte_low = pte.pte_low;
-#else
-        *ptep = pte;
-#endif
-}
-
-#ifdef CONFIG_X86_PAE
-void xen_set_pte_atomic(pte_t *ptep, pte_t pte)
+static void xen_set_pte_atomic(pte_t *ptep, pte_t pte)
 {
-        if (xen_iomap_pte(pte)) {
-                xen_set_iomap_pte(ptep, pte);
-                return;
-        }
-
         set_64bit((u64 *)ptep, native_pte_val(pte));
 }
 
-void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
+static void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 {
-        ptep->pte_low = 0;
-        smp_wmb();              /* make sure low gets written first */
-        ptep->pte_high = 0;
+        if (!xen_batched_set_pte(ptep, native_make_pte(0)))
+                native_pte_clear(mm, addr, ptep);
 }
 
-void xen_pmd_clear(pmd_t *pmdp)
+static void xen_pmd_clear(pmd_t *pmdp)
 {
         set_pmd(pmdp, __pmd(0));
 }
 #endif  /* CONFIG_X86_PAE */
 
-pmd_t xen_make_pmd(pmdval_t pmd)
+static pmd_t xen_make_pmd(pmdval_t pmd)
 {
         pmd = pte_pfn_to_mfn(pmd);
         return native_make_pmd(pmd);
@@ -682,13 +565,13 @@ pmd_t xen_make_pmd(pmdval_t pmd)
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pmd);
 
 #if PAGETABLE_LEVELS == 4
-pudval_t xen_pud_val(pud_t pud)
+static pudval_t xen_pud_val(pud_t pud)
 {
         return pte_mfn_to_pfn(pud.pud);
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_pud_val);
 
-pud_t xen_make_pud(pudval_t pud)
+static pud_t xen_make_pud(pudval_t pud)
 {
         pud = pte_pfn_to_mfn(pud);
 
@@ -696,7 +579,7 @@ pud_t xen_make_pud(pudval_t pud)
 }
 PV_CALLEE_SAVE_REGS_THUNK(xen_make_pud);
 
-pgd_t *xen_get_user_pgd(pgd_t *pgd)
+static pgd_t *xen_get_user_pgd(pgd_t *pgd)
 {
         pgd_t *pgd_page = (pgd_t *)(((unsigned long)pgd) & PAGE_MASK);
         unsigned offset = pgd - pgd_page;
@@ -728,7 +611,7 @@ static void __xen_set_pgd_hyper(pgd_t *ptr, pgd_t val)
  *  2. It is always pinned
  *  3. It has no user pagetable attached to it
  */
-void __init xen_set_pgd_hyper(pgd_t *ptr, pgd_t val)
+static void __init xen_set_pgd_hyper(pgd_t *ptr, pgd_t val)
 {
         preempt_disable();
 
@@ -741,12 +624,10 @@ void __init xen_set_pgd_hyper(pgd_t *ptr, pgd_t val)
         preempt_enable();
 }
 
-void xen_set_pgd(pgd_t *ptr, pgd_t val)
+static void xen_set_pgd(pgd_t *ptr, pgd_t val)
 {
         pgd_t *user_ptr = xen_get_user_pgd(ptr);
 
-        ADD_STATS(pgd_update, 1);
-
         /* If page is not pinned, we can just update the entry
            directly */
         if (!xen_page_pinned(ptr)) {
@@ -758,9 +639,6 @@ void xen_set_pgd(pgd_t *ptr, pgd_t val)
                 return;
         }
 
-        ADD_STATS(pgd_update_pinned, 1);
-        ADD_STATS(pgd_update_batched, paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU);
-
         /* If it's pinned, then we can at least batch the kernel and
            user updates together. */
         xen_mc_batch();
@@ -1162,14 +1040,14 @@ void xen_mm_unpin_all(void)
         spin_unlock(&pgd_lock);
 }
 
-void xen_activate_mm(struct mm_struct *prev, struct mm_struct *next)
+static void xen_activate_mm(struct mm_struct *prev, struct mm_struct *next)
 {
         spin_lock(&next->page_table_lock);
         xen_pgd_pin(next);
         spin_unlock(&next->page_table_lock);
 }
 
-void xen_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
+static void xen_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm)
 {
         spin_lock(&mm->page_table_lock);
         xen_pgd_pin(mm);
@@ -1256,7 +1134,7 @@ static void xen_drop_mm_ref(struct mm_struct *mm)
  * pagetable because of lazy tlb flushing.  This means we need need to
  * switch all CPUs off this pagetable before we can unpin it.
  */
-void xen_exit_mmap(struct mm_struct *mm)
+static void xen_exit_mmap(struct mm_struct *mm)
 {
         get_cpu();              /* make sure we don't move around */
         xen_drop_mm_ref(mm);
@@ -2371,7 +2249,7 @@ static int remap_area_mfn_pte_fn(pte_t *ptep, pgtable_t token,
         struct remap_data *rmd = data;
         pte_t pte = pte_mkspecial(pfn_pte(rmd->mfn++, rmd->prot));
 
-        rmd->mmu_update->ptr = arbitrary_virt_to_machine(ptep).maddr;
+        rmd->mmu_update->ptr = virt_to_machine(ptep).maddr;
         rmd->mmu_update->val = pte_val_ma(pte);
         rmd->mmu_update++;
 
@@ -2425,7 +2303,6 @@ out:
 EXPORT_SYMBOL_GPL(xen_remap_domain_mfn_range);
 
 #ifdef CONFIG_XEN_DEBUG_FS
-
 static int p2m_dump_open(struct inode *inode, struct file *filp)
 {
         return single_open(filp, p2m_dump_show, NULL);
@@ -2437,65 +2314,4 @@ static const struct file_operations p2m_dump_fops = {
         .llseek         = seq_lseek,
         .release        = single_release,
 };
-
-static struct dentry *d_mmu_debug;
-
-static int __init xen_mmu_debugfs(void)
-{
-        struct dentry *d_xen = xen_init_debugfs();
-
-        if (d_xen == NULL)
-                return -ENOMEM;
-
-        d_mmu_debug = debugfs_create_dir("mmu", d_xen);
-
-        debugfs_create_u8("zero_stats", 0644, d_mmu_debug, &zero_stats);
-
-        debugfs_create_u32("pgd_update", 0444, d_mmu_debug, &mmu_stats.pgd_update);
-        debugfs_create_u32("pgd_update_pinned", 0444, d_mmu_debug,
-                           &mmu_stats.pgd_update_pinned);
-        debugfs_create_u32("pgd_update_batched", 0444, d_mmu_debug,
-                           &mmu_stats.pgd_update_pinned);
-
-        debugfs_create_u32("pud_update", 0444, d_mmu_debug, &mmu_stats.pud_update);
-        debugfs_create_u32("pud_update_pinned", 0444, d_mmu_debug,
-                           &mmu_stats.pud_update_pinned);
-        debugfs_create_u32("pud_update_batched", 0444, d_mmu_debug,
-                           &mmu_stats.pud_update_pinned);
-
-        debugfs_create_u32("pmd_update", 0444, d_mmu_debug, &mmu_stats.pmd_update);
-        debugfs_create_u32("pmd_update_pinned", 0444, d_mmu_debug,
-                           &mmu_stats.pmd_update_pinned);
-        debugfs_create_u32("pmd_update_batched", 0444, d_mmu_debug,
-                           &mmu_stats.pmd_update_pinned);
-
-        debugfs_create_u32("pte_update", 0444, d_mmu_debug, &mmu_stats.pte_update);
-//      debugfs_create_u32("pte_update_pinned", 0444, d_mmu_debug,
-//                         &mmu_stats.pte_update_pinned);
-        debugfs_create_u32("pte_update_batched", 0444, d_mmu_debug,
-                           &mmu_stats.pte_update_pinned);
-
-        debugfs_create_u32("mmu_update", 0444, d_mmu_debug, &mmu_stats.mmu_update);
-        debugfs_create_u32("mmu_update_extended", 0444, d_mmu_debug,
-                           &mmu_stats.mmu_update_extended);
-        xen_debugfs_create_u32_array("mmu_update_histo", 0444, d_mmu_debug,
-                                     mmu_stats.mmu_update_histo, 20);
-
-        debugfs_create_u32("set_pte_at", 0444, d_mmu_debug, &mmu_stats.set_pte_at);
-        debugfs_create_u32("set_pte_at_batched", 0444, d_mmu_debug,
-                           &mmu_stats.set_pte_at_batched);
-        debugfs_create_u32("set_pte_at_current", 0444, d_mmu_debug,
-                           &mmu_stats.set_pte_at_current);
-        debugfs_create_u32("set_pte_at_kernel", 0444, d_mmu_debug,
-                           &mmu_stats.set_pte_at_kernel);
-
-        debugfs_create_u32("prot_commit", 0444, d_mmu_debug, &mmu_stats.prot_commit);
-        debugfs_create_u32("prot_commit_batched", 0444, d_mmu_debug,
-                           &mmu_stats.prot_commit_batched);
-
-        debugfs_create_file("p2m", 0600, d_mmu_debug, NULL, &p2m_dump_fops);
-        return 0;
-}
-fs_initcall(xen_mmu_debugfs);
-
-#endif  /* CONFIG_XEN_DEBUG_FS */
+#endif /* CONFIG_XEN_DEBUG_FS */
diff --git a/arch/x86/xen/mmu.h b/arch/x86/xen/mmu.h
index 537bb9aab777..73809bb951b4 100644
--- a/arch/x86/xen/mmu.h
+++ b/arch/x86/xen/mmu.h
@@ -15,43 +15,6 @@ bool __set_phys_to_machine(unsigned long pfn, unsigned long mfn);
 
 void set_pte_mfn(unsigned long vaddr, unsigned long pfn, pgprot_t flags);
 
-
-void xen_activate_mm(struct mm_struct *prev, struct mm_struct *next);
-void xen_dup_mmap(struct mm_struct *oldmm, struct mm_struct *mm);
-void xen_exit_mmap(struct mm_struct *mm);
-
-pteval_t xen_pte_val(pte_t);
-pmdval_t xen_pmd_val(pmd_t);
-pgdval_t xen_pgd_val(pgd_t);
-
-pte_t xen_make_pte(pteval_t);
-pmd_t xen_make_pmd(pmdval_t);
-pgd_t xen_make_pgd(pgdval_t);
-
-void xen_set_pte(pte_t *ptep, pte_t pteval);
-void xen_set_pte_at(struct mm_struct *mm, unsigned long addr,
-                    pte_t *ptep, pte_t pteval);
-
-#ifdef CONFIG_X86_PAE
-void xen_set_pte_atomic(pte_t *ptep, pte_t pte);
-void xen_pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
-void xen_pmd_clear(pmd_t *pmdp);
-#endif  /* CONFIG_X86_PAE */
-
-void xen_set_pmd(pmd_t *pmdp, pmd_t pmdval);
-void xen_set_pud(pud_t *ptr, pud_t val);
-void xen_set_pmd_hyper(pmd_t *pmdp, pmd_t pmdval);
-void xen_set_pud_hyper(pud_t *ptr, pud_t val);
-
-#if PAGETABLE_LEVELS == 4
-pudval_t xen_pud_val(pud_t pud);
-pud_t xen_make_pud(pudval_t pudval);
-void xen_set_pgd(pgd_t *pgdp, pgd_t pgd);
-void xen_set_pgd_hyper(pgd_t *pgdp, pgd_t pgd);
-#endif
-
-pgd_t *xen_get_user_pgd(pgd_t *pgd);
-
 pte_t xen_ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
 void  xen_ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
                                   pte_t *ptep, pte_t pte);
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 7c275f5d0df0..5d43c1f8ada8 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -20,12 +20,6 @@ config XTENSA
 config RWSEM_XCHGADD_ALGORITHM
         def_bool y
 
-config GENERIC_FIND_NEXT_BIT
-        def_bool y
-
-config GENERIC_FIND_BIT_LE
-        def_bool y
-
 config GENERIC_HWEIGHT
         def_bool y
 
diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h
index 161bb89e98c8..7a5591a71f85 100644
--- a/arch/xtensa/include/asm/page.h
+++ b/arch/xtensa/include/asm/page.h
@@ -171,10 +171,6 @@ extern void copy_user_page(void*, void*, unsigned long, struct page*);
 #define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
 #define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 
-#ifdef CONFIG_MMU
-#define WANT_PAGE_VIRTUAL
-#endif
-
 #endif /* __ASSEMBLY__ */
 
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
diff --git a/arch/xtensa/include/asm/unistd.h b/arch/xtensa/include/asm/unistd.h
index 528042c2951e..a6f934f37f1a 100644
--- a/arch/xtensa/include/asm/unistd.h
+++ b/arch/xtensa/include/asm/unistd.h
@@ -683,8 +683,10 @@ __SYSCALL(305, sys_ni_syscall, 0)
 __SYSCALL(306, sys_eventfd, 1)
 #define __NR_recvmmsg                           307
 __SYSCALL(307, sys_recvmmsg, 5)
+#define __NR_setns                              308
+__SYSCALL(308, sys_setns, 2)
 
-#define __NR_syscall_count                      308
+#define __NR_syscall_count                      309
 
 /*
  * sysxtensa syscall handler
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index a2820065927e..88ecea3facb4 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -155,7 +155,7 @@ SECTIONS
     INIT_RAM_FS
   }
 
-  PERCPU(XCHAL_ICACHE_LINESIZE, PAGE_SIZE)
+  PERCPU_SECTION(XCHAL_ICACHE_LINESIZE)
 
   /* We need this dummy segment here */
 
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index 4bb91a970f1f..ca81654f3ec2 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -14,8 +14,6 @@
 #include <asm/mmu_context.h>
 #include <asm/page.h>
 
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
 void __init paging_init(void)
 {
         memset(swapper_pg_dir, 0, PAGE_SIZE);
diff --git a/arch/xtensa/mm/pgtable.c b/arch/xtensa/mm/pgtable.c
deleted file mode 100644
index 697992738205..000000000000
--- a/arch/xtensa/mm/pgtable.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * arch/xtensa/mm/pgtable.c
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- *
- * Chris Zankel <chris@zankel.net>
- */
-
-#if (DCACHE_SIZE > PAGE_SIZE)
-
-pte_t* pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
-        pte_t *pte = NULL, *p;
-        int color = ADDR_COLOR(address);
-        int i;
-
-        p = (pte_t*) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, COLOR_ORDER);
-
-        if (likely(p)) {
-                split_page(virt_to_page(p), COLOR_ORDER);
-
-                for (i = 0; i < COLOR_SIZE; i++) {
-                        if (ADDR_COLOR(p) == color)
-                                pte = p;
-                        else
-                                free_page(p);
-                        p += PTRS_PER_PTE;
-                }
-                clear_page(pte);
-        }
-        return pte;
-}
-
-#ifdef PROFILING
-
-int mask;
-int hit;
-int flush;
-
-#endif
-
-struct page* pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        struct page *page = NULL, *p;
-        int color = ADDR_COLOR(address);
-
-        p = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
-
-        if (likely(p)) {
-                split_page(p, COLOR_ORDER);
-
-                for (i = 0; i < PAGE_ORDER; i++) {
-                        if (PADDR_COLOR(page_address(p)) == color)
-                                page = p;
-                        else
-                                __free_page(p);
-                        p++;
-                }
-                clear_highpage(page);
-        }
-
-        return page;
-}
-
-#endif
-
-
-