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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-19 01:30:00 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-19 01:30:00 -0400
commit664322a4475236bd9900f2853a9b981a4377493f (patch)
tree50581bba5accbc6ba8b0304a622e97e1b7167512 /arch
parent99759619b27662d1290901228d77a293e6e83200 (diff)
parent0c082bd15828135d609a2f593b583de9eacece0f (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: (32 commits) Blackfin: ip0x: fix unused variable warning Blackfin: punt unused HDMA masks Blackfin: wire up new syscalls Blackfin/ipipe: restore pipeline bits in irqflags Blackfin/ipipe: fix deferred pipeline sync for the root stage Blackfin/ipipe: upgrade to I-pipe mainline Blackfin: cpufreq: fix typos Blackfin: enable GENERIC_HARDIRQS_NO_DEPRECATED Blackfin: SMP: convert to irq chip functions Blackfin: use accessor functions in show_interrupts() Blackfin: use proper wrapper functions for modifying irq status Blackfin: convert gpio irq_chip to new functions Blackfin: convert mac irq_chip to new functions Blackfin: convert error irq_chip to new functions Blackfin: convert internal irq_chip to new functions Blackfin: convert core irq_chip to new functions Blackfin: use proper wrappers for irq_desc Blackfin: optimize startup code Blackfin: SMP: work around anomaly 05000491 Blackfin: SMP: implement cpu_freq support ...
Diffstat (limited to 'arch')
-rw-r--r--arch/blackfin/Kconfig42
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig1
-rw-r--r--arch/blackfin/configs/BF526-EZBRD_defconfig1
-rw-r--r--arch/blackfin/configs/BF527-EZKIT-V2_defconfig1
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig1
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig1
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig1
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig1
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig1
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig1
-rw-r--r--arch/blackfin/configs/BF561-EZKIT-SMP_defconfig1
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig1
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h16
-rw-r--r--arch/blackfin/include/asm/dpmc.h3
-rw-r--r--arch/blackfin/include/asm/ipipe.h95
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h11
-rw-r--r--arch/blackfin/include/asm/irqflags.h87
-rw-r--r--arch/blackfin/include/asm/smp.h9
-rw-r--r--arch/blackfin/include/asm/unistd.h5
-rw-r--r--arch/blackfin/kernel/bfin_dma_5xx.c32
-rw-r--r--arch/blackfin/kernel/ipipe.c84
-rw-r--r--arch/blackfin/kernel/irqchip.c10
-rw-r--r--arch/blackfin/kernel/kgdb.c4
-rw-r--r--arch/blackfin/kernel/setup.c37
-rw-r--r--arch/blackfin/kernel/vmlinux.lds.S3
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF512.h19
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF522.h19
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c2
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c2
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537u.c2
-rw-r--r--arch/blackfin/mach-bf537/boards/dnp5370.c20
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c2
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h18
-rw-r--r--arch/blackfin/mach-bf548/Kconfig59
-rw-r--r--arch/blackfin/mach-bf548/boards/ezkit.c55
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF544.h18
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF547.h19
-rw-r--r--arch/blackfin/mach-bf548/include/mach/dma.h28
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h4
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c2
-rw-r--r--arch/blackfin/mach-bf561/hotplug.c21
-rw-r--r--arch/blackfin/mach-bf561/secondary.S35
-rw-r--r--arch/blackfin/mach-bf561/smp.c15
-rw-r--r--arch/blackfin/mach-common/arch_checks.c2
-rw-r--r--arch/blackfin/mach-common/cache.S38
-rw-r--r--arch/blackfin/mach-common/cpufreq.c8
-rw-r--r--arch/blackfin/mach-common/dpmc.c50
-rw-r--r--arch/blackfin/mach-common/entry.S14
-rw-r--r--arch/blackfin/mach-common/head.S110
-rw-r--r--arch/blackfin/mach-common/interrupt.S6
-rw-r--r--arch/blackfin/mach-common/ints-priority.c236
-rw-r--r--arch/blackfin/mach-common/smp.c28
52 files changed, 762 insertions, 519 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c09577ddc3c5..01615d4f57d6 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -33,6 +33,7 @@ config BLACKFIN
33 select HAVE_GENERIC_HARDIRQS 33 select HAVE_GENERIC_HARDIRQS
34 select GENERIC_IRQ_PROBE 34 select GENERIC_IRQ_PROBE
35 select IRQ_PER_CPU if SMP 35 select IRQ_PER_CPU if SMP
36 select GENERIC_HARDIRQS_NO_DEPRECATED
36 37
37config GENERIC_CSUM 38config GENERIC_CSUM
38 def_bool y 39 def_bool y
@@ -690,13 +691,13 @@ endmenu
690 691
691 692
692menu "Blackfin Kernel Optimizations" 693menu "Blackfin Kernel Optimizations"
693 depends on !SMP
694 694
695comment "Memory Optimizations" 695comment "Memory Optimizations"
696 696
697config I_ENTRY_L1 697config I_ENTRY_L1
698 bool "Locate interrupt entry code in L1 Memory" 698 bool "Locate interrupt entry code in L1 Memory"
699 default y 699 default y
700 depends on !SMP
700 help 701 help
701 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked 702 If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
702 into L1 instruction memory. (less latency) 703 into L1 instruction memory. (less latency)
@@ -704,6 +705,7 @@ config I_ENTRY_L1
704config EXCPT_IRQ_SYSC_L1 705config EXCPT_IRQ_SYSC_L1
705 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" 706 bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
706 default y 707 default y
708 depends on !SMP
707 help 709 help
708 If enabled, the entire ASM lowlevel exception and interrupt entry code 710 If enabled, the entire ASM lowlevel exception and interrupt entry code
709 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. 711 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
@@ -712,6 +714,7 @@ config EXCPT_IRQ_SYSC_L1
712config DO_IRQ_L1 714config DO_IRQ_L1
713 bool "Locate frequently called do_irq dispatcher function in L1 Memory" 715 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
714 default y 716 default y
717 depends on !SMP
715 help 718 help
716 If enabled, the frequently called do_irq dispatcher function is linked 719 If enabled, the frequently called do_irq dispatcher function is linked
717 into L1 instruction memory. (less latency) 720 into L1 instruction memory. (less latency)
@@ -719,6 +722,7 @@ config DO_IRQ_L1
719config CORE_TIMER_IRQ_L1 722config CORE_TIMER_IRQ_L1
720 bool "Locate frequently called timer_interrupt() function in L1 Memory" 723 bool "Locate frequently called timer_interrupt() function in L1 Memory"
721 default y 724 default y
725 depends on !SMP
722 help 726 help
723 If enabled, the frequently called timer_interrupt() function is linked 727 If enabled, the frequently called timer_interrupt() function is linked
724 into L1 instruction memory. (less latency) 728 into L1 instruction memory. (less latency)
@@ -726,6 +730,7 @@ config CORE_TIMER_IRQ_L1
726config IDLE_L1 730config IDLE_L1
727 bool "Locate frequently idle function in L1 Memory" 731 bool "Locate frequently idle function in L1 Memory"
728 default y 732 default y
733 depends on !SMP
729 help 734 help
730 If enabled, the frequently called idle function is linked 735 If enabled, the frequently called idle function is linked
731 into L1 instruction memory. (less latency) 736 into L1 instruction memory. (less latency)
@@ -733,6 +738,7 @@ config IDLE_L1
733config SCHEDULE_L1 738config SCHEDULE_L1
734 bool "Locate kernel schedule function in L1 Memory" 739 bool "Locate kernel schedule function in L1 Memory"
735 default y 740 default y
741 depends on !SMP
736 help 742 help
737 If enabled, the frequently called kernel schedule is linked 743 If enabled, the frequently called kernel schedule is linked
738 into L1 instruction memory. (less latency) 744 into L1 instruction memory. (less latency)
@@ -740,6 +746,7 @@ config SCHEDULE_L1
740config ARITHMETIC_OPS_L1 746config ARITHMETIC_OPS_L1
741 bool "Locate kernel owned arithmetic functions in L1 Memory" 747 bool "Locate kernel owned arithmetic functions in L1 Memory"
742 default y 748 default y
749 depends on !SMP
743 help 750 help
744 If enabled, arithmetic functions are linked 751 If enabled, arithmetic functions are linked
745 into L1 instruction memory. (less latency) 752 into L1 instruction memory. (less latency)
@@ -747,6 +754,7 @@ config ARITHMETIC_OPS_L1
747config ACCESS_OK_L1 754config ACCESS_OK_L1
748 bool "Locate access_ok function in L1 Memory" 755 bool "Locate access_ok function in L1 Memory"
749 default y 756 default y
757 depends on !SMP
750 help 758 help
751 If enabled, the access_ok function is linked 759 If enabled, the access_ok function is linked
752 into L1 instruction memory. (less latency) 760 into L1 instruction memory. (less latency)
@@ -754,6 +762,7 @@ config ACCESS_OK_L1
754config MEMSET_L1 762config MEMSET_L1
755 bool "Locate memset function in L1 Memory" 763 bool "Locate memset function in L1 Memory"
756 default y 764 default y
765 depends on !SMP
757 help 766 help
758 If enabled, the memset function is linked 767 If enabled, the memset function is linked
759 into L1 instruction memory. (less latency) 768 into L1 instruction memory. (less latency)
@@ -761,6 +770,7 @@ config MEMSET_L1
761config MEMCPY_L1 770config MEMCPY_L1
762 bool "Locate memcpy function in L1 Memory" 771 bool "Locate memcpy function in L1 Memory"
763 default y 772 default y
773 depends on !SMP
764 help 774 help
765 If enabled, the memcpy function is linked 775 If enabled, the memcpy function is linked
766 into L1 instruction memory. (less latency) 776 into L1 instruction memory. (less latency)
@@ -768,6 +778,7 @@ config MEMCPY_L1
768config STRCMP_L1 778config STRCMP_L1
769 bool "locate strcmp function in L1 Memory" 779 bool "locate strcmp function in L1 Memory"
770 default y 780 default y
781 depends on !SMP
771 help 782 help
772 If enabled, the strcmp function is linked 783 If enabled, the strcmp function is linked
773 into L1 instruction memory (less latency). 784 into L1 instruction memory (less latency).
@@ -775,6 +786,7 @@ config STRCMP_L1
775config STRNCMP_L1 786config STRNCMP_L1
776 bool "locate strncmp function in L1 Memory" 787 bool "locate strncmp function in L1 Memory"
777 default y 788 default y
789 depends on !SMP
778 help 790 help
779 If enabled, the strncmp function is linked 791 If enabled, the strncmp function is linked
780 into L1 instruction memory (less latency). 792 into L1 instruction memory (less latency).
@@ -782,6 +794,7 @@ config STRNCMP_L1
782config STRCPY_L1 794config STRCPY_L1
783 bool "locate strcpy function in L1 Memory" 795 bool "locate strcpy function in L1 Memory"
784 default y 796 default y
797 depends on !SMP
785 help 798 help
786 If enabled, the strcpy function is linked 799 If enabled, the strcpy function is linked
787 into L1 instruction memory (less latency). 800 into L1 instruction memory (less latency).
@@ -789,6 +802,7 @@ config STRCPY_L1
789config STRNCPY_L1 802config STRNCPY_L1
790 bool "locate strncpy function in L1 Memory" 803 bool "locate strncpy function in L1 Memory"
791 default y 804 default y
805 depends on !SMP
792 help 806 help
793 If enabled, the strncpy function is linked 807 If enabled, the strncpy function is linked
794 into L1 instruction memory (less latency). 808 into L1 instruction memory (less latency).
@@ -796,6 +810,7 @@ config STRNCPY_L1
796config SYS_BFIN_SPINLOCK_L1 810config SYS_BFIN_SPINLOCK_L1
797 bool "Locate sys_bfin_spinlock function in L1 Memory" 811 bool "Locate sys_bfin_spinlock function in L1 Memory"
798 default y 812 default y
813 depends on !SMP
799 help 814 help
800 If enabled, sys_bfin_spinlock function is linked 815 If enabled, sys_bfin_spinlock function is linked
801 into L1 instruction memory. (less latency) 816 into L1 instruction memory. (less latency)
@@ -803,6 +818,7 @@ config SYS_BFIN_SPINLOCK_L1
803config IP_CHECKSUM_L1 818config IP_CHECKSUM_L1
804 bool "Locate IP Checksum function in L1 Memory" 819 bool "Locate IP Checksum function in L1 Memory"
805 default n 820 default n
821 depends on !SMP
806 help 822 help
807 If enabled, the IP Checksum function is linked 823 If enabled, the IP Checksum function is linked
808 into L1 instruction memory. (less latency) 824 into L1 instruction memory. (less latency)
@@ -811,7 +827,7 @@ config CACHELINE_ALIGNED_L1
811 bool "Locate cacheline_aligned data to L1 Data Memory" 827 bool "Locate cacheline_aligned data to L1 Data Memory"
812 default y if !BF54x 828 default y if !BF54x
813 default n if BF54x 829 default n if BF54x
814 depends on !BF531 830 depends on !SMP && !BF531
815 help 831 help
816 If enabled, cacheline_aligned data is linked 832 If enabled, cacheline_aligned data is linked
817 into L1 data memory. (less latency) 833 into L1 data memory. (less latency)
@@ -819,7 +835,7 @@ config CACHELINE_ALIGNED_L1
819config SYSCALL_TAB_L1 835config SYSCALL_TAB_L1
820 bool "Locate Syscall Table L1 Data Memory" 836 bool "Locate Syscall Table L1 Data Memory"
821 default n 837 default n
822 depends on !BF531 838 depends on !SMP && !BF531
823 help 839 help
824 If enabled, the Syscall LUT is linked 840 If enabled, the Syscall LUT is linked
825 into L1 data memory. (less latency) 841 into L1 data memory. (less latency)
@@ -827,16 +843,16 @@ config SYSCALL_TAB_L1
827config CPLB_SWITCH_TAB_L1 843config CPLB_SWITCH_TAB_L1
828 bool "Locate CPLB Switch Tables L1 Data Memory" 844 bool "Locate CPLB Switch Tables L1 Data Memory"
829 default n 845 default n
830 depends on !BF531 846 depends on !SMP && !BF531
831 help 847 help
832 If enabled, the CPLB Switch Tables are linked 848 If enabled, the CPLB Switch Tables are linked
833 into L1 data memory. (less latency) 849 into L1 data memory. (less latency)
834 850
835config CACHE_FLUSH_L1 851config ICACHE_FLUSH_L1
836 bool "Locate cache flush funcs in L1 Inst Memory" 852 bool "Locate icache flush funcs in L1 Inst Memory"
837 default y 853 default y
838 help 854 help
839 If enabled, the Blackfin cache flushing functions are linked 855 If enabled, the Blackfin icache flushing functions are linked
840 into L1 instruction memory. 856 into L1 instruction memory.
841 857
842 Note that this might be required to address anomalies, but 858 Note that this might be required to address anomalies, but
@@ -844,9 +860,18 @@ config CACHE_FLUSH_L1
844 If you are using a processor affected by an anomaly, the build 860 If you are using a processor affected by an anomaly, the build
845 system will double check for you and prevent it. 861 system will double check for you and prevent it.
846 862
863config DCACHE_FLUSH_L1
864 bool "Locate dcache flush funcs in L1 Inst Memory"
865 default y
866 depends on !SMP
867 help
868 If enabled, the Blackfin dcache flushing functions are linked
869 into L1 instruction memory.
870
847config APP_STACK_L1 871config APP_STACK_L1
848 bool "Support locating application stack in L1 Scratch Memory" 872 bool "Support locating application stack in L1 Scratch Memory"
849 default y 873 default y
874 depends on !SMP
850 help 875 help
851 If enabled the application stack can be located in L1 876 If enabled the application stack can be located in L1
852 scratch memory (less latency). 877 scratch memory (less latency).
@@ -856,7 +881,7 @@ config APP_STACK_L1
856config EXCEPTION_L1_SCRATCH 881config EXCEPTION_L1_SCRATCH
857 bool "Locate exception stack in L1 Scratch Memory" 882 bool "Locate exception stack in L1 Scratch Memory"
858 default n 883 default n
859 depends on !APP_STACK_L1 884 depends on !SMP && !APP_STACK_L1
860 help 885 help
861 Whenever an exception occurs, use the L1 Scratch memory for 886 Whenever an exception occurs, use the L1 Scratch memory for
862 stack storage. You cannot place the stacks of FLAT binaries 887 stack storage. You cannot place the stacks of FLAT binaries
@@ -868,6 +893,7 @@ comment "Speed Optimizations"
868config BFIN_INS_LOWOVERHEAD 893config BFIN_INS_LOWOVERHEAD
869 bool "ins[bwl] low overhead, higher interrupt latency" 894 bool "ins[bwl] low overhead, higher interrupt latency"
870 default y 895 default y
896 depends on !SMP
871 help 897 help
872 Reads on the Blackfin are speculative. In Blackfin terms, this means 898 Reads on the Blackfin are speculative. In Blackfin terms, this means
873 they can be interrupted at any time (even after they have been issued 899 they can be interrupted at any time (even after they have been issued
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index db8d38a12a9a..5edcb58d6f73 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -115,6 +115,7 @@ CONFIG_DEBUG_DOUBLEFAULT=y
115CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 115CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
116CONFIG_EARLY_PRINTK=y 116CONFIG_EARLY_PRINTK=y
117CONFIG_CPLB_INFO=y 117CONFIG_CPLB_INFO=y
118CONFIG_BFIN_PSEUDODBG_INSNS=y
118CONFIG_CRYPTO=y 119CONFIG_CRYPTO=y
119# CONFIG_CRYPTO_ANSI_CPRNG is not set 120# CONFIG_CRYPTO_ANSI_CPRNG is not set
120CONFIG_CRC_CCITT=m 121CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF526-EZBRD_defconfig b/arch/blackfin/configs/BF526-EZBRD_defconfig
index 3e50d7857c27..2e549572d4f5 100644
--- a/arch/blackfin/configs/BF526-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF526-EZBRD_defconfig
@@ -153,6 +153,7 @@ CONFIG_DEBUG_DOUBLEFAULT=y
153CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 153CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
154CONFIG_EARLY_PRINTK=y 154CONFIG_EARLY_PRINTK=y
155CONFIG_CPLB_INFO=y 155CONFIG_CPLB_INFO=y
156CONFIG_BFIN_PSEUDODBG_INSNS=y
156CONFIG_CRYPTO=y 157CONFIG_CRYPTO=y
157# CONFIG_CRYPTO_ANSI_CPRNG is not set 158# CONFIG_CRYPTO_ANSI_CPRNG is not set
158CONFIG_CRC_CCITT=m 159CONFIG_CRC_CCITT=m
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index 023ff0df2692..95cf2ba9de17 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -183,5 +183,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
183CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 183CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
184CONFIG_EARLY_PRINTK=y 184CONFIG_EARLY_PRINTK=y
185CONFIG_CPLB_INFO=y 185CONFIG_CPLB_INFO=y
186CONFIG_BFIN_PSEUDODBG_INSNS=y
186CONFIG_CRYPTO=y 187CONFIG_CRYPTO=y
187# CONFIG_CRYPTO_ANSI_CPRNG is not set 188# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 4e5a121b3c56..8be8e33fac52 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -175,5 +175,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
175CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 175CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
176CONFIG_EARLY_PRINTK=y 176CONFIG_EARLY_PRINTK=y
177CONFIG_CPLB_INFO=y 177CONFIG_CPLB_INFO=y
178CONFIG_BFIN_PSEUDODBG_INSNS=y
178CONFIG_CRYPTO=y 179CONFIG_CRYPTO=y
179# CONFIG_CRYPTO_ANSI_CPRNG is not set 180# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 9f8fc84e4ac9..a7eb54bf3089 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -108,5 +108,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
108CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 108CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
109CONFIG_EARLY_PRINTK=y 109CONFIG_EARLY_PRINTK=y
110CONFIG_CPLB_INFO=y 110CONFIG_CPLB_INFO=y
111CONFIG_BFIN_PSEUDODBG_INSNS=y
111CONFIG_CRYPTO=y 112CONFIG_CRYPTO=y
112# CONFIG_CRYPTO_ANSI_CPRNG is not set 113# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index ccc432b722a0..0aafde6c8c2d 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -122,5 +122,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
122CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 122CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
123CONFIG_EARLY_PRINTK=y 123CONFIG_EARLY_PRINTK=y
124CONFIG_CPLB_INFO=y 124CONFIG_CPLB_INFO=y
125CONFIG_BFIN_PSEUDODBG_INSNS=y
125CONFIG_CRYPTO=y 126CONFIG_CRYPTO=y
126# CONFIG_CRYPTO_ANSI_CPRNG is not set 127# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 566695472a84..c9077fb58135 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -133,5 +133,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
133CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 133CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
134CONFIG_EARLY_PRINTK=y 134CONFIG_EARLY_PRINTK=y
135CONFIG_CPLB_INFO=y 135CONFIG_CPLB_INFO=y
136CONFIG_BFIN_PSEUDODBG_INSNS=y
136CONFIG_CRYPTO=y 137CONFIG_CRYPTO=y
137# CONFIG_CRYPTO_ANSI_CPRNG is not set 138# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index ac22124ccb6c..6883803e6ca8 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -131,5 +131,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
131CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 131CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
132CONFIG_EARLY_PRINTK=y 132CONFIG_EARLY_PRINTK=y
133CONFIG_CPLB_INFO=y 133CONFIG_CPLB_INFO=y
134CONFIG_BFIN_PSEUDODBG_INSNS=y
134CONFIG_CRYPTO=y 135CONFIG_CRYPTO=y
135# CONFIG_CRYPTO_ANSI_CPRNG is not set 136# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 944404b6ff08..56151b5dbc44 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -205,5 +205,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
205CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 205CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
206CONFIG_EARLY_PRINTK=y 206CONFIG_EARLY_PRINTK=y
207CONFIG_CPLB_INFO=y 207CONFIG_CPLB_INFO=y
208CONFIG_BFIN_PSEUDODBG_INSNS=y
208CONFIG_CRYPTO=y 209CONFIG_CRYPTO=y
209# CONFIG_CRYPTO_ANSI_CPRNG is not set 210# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
index 7e67ba31e991..f5ed34e12e0c 100644
--- a/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT-SMP_defconfig
@@ -109,5 +109,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
109CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 109CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
110CONFIG_EARLY_PRINTK=y 110CONFIG_EARLY_PRINTK=y
111CONFIG_CPLB_INFO=y 111CONFIG_CPLB_INFO=y
112CONFIG_BFIN_PSEUDODBG_INSNS=y
112CONFIG_CRYPTO=y 113CONFIG_CRYPTO=y
113# CONFIG_CRYPTO_ANSI_CPRNG is not set 114# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 141e5933e1aa..1c0a82a10591 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -111,5 +111,6 @@ CONFIG_DEBUG_DOUBLEFAULT=y
111CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y 111CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
112CONFIG_EARLY_PRINTK=y 112CONFIG_EARLY_PRINTK=y
113CONFIG_CPLB_INFO=y 113CONFIG_CPLB_INFO=y
114CONFIG_BFIN_PSEUDODBG_INSNS=y
114CONFIG_CRYPTO=y 115CONFIG_CRYPTO=y
115# CONFIG_CRYPTO_ANSI_CPRNG is not set 116# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index e3f0f4c49819..7600fe0696af 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -58,14 +58,26 @@
58 ({ BUG(); 0; }); \ 58 ({ BUG(); 0; }); \
59}) 59})
60#define bfin_write(addr, val) \ 60#define bfin_write(addr, val) \
61({ \ 61do { \
62 switch (sizeof(*(addr))) { \ 62 switch (sizeof(*(addr))) { \
63 case 1: bfin_write8(addr, val); break; \ 63 case 1: bfin_write8(addr, val); break; \
64 case 2: bfin_write16(addr, val); break; \ 64 case 2: bfin_write16(addr, val); break; \
65 case 4: bfin_write32(addr, val); break; \ 65 case 4: bfin_write32(addr, val); break; \
66 default: BUG(); \ 66 default: BUG(); \
67 } \ 67 } \
68}) 68} while (0)
69
70#define bfin_write_or(addr, bits) \
71do { \
72 void *__addr = (void *)(addr); \
73 bfin_write(__addr, bfin_read(__addr) | (bits)); \
74} while (0)
75
76#define bfin_write_and(addr, bits) \
77do { \
78 void *__addr = (void *)(addr); \
79 bfin_write(__addr, bfin_read(__addr) & (bits)); \
80} while (0)
69 81
70#endif /* __ASSEMBLY__ */ 82#endif /* __ASSEMBLY__ */
71 83
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index 3047120cfcff..edf2a2ad5183 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -125,6 +125,9 @@ void unset_dram_srfs(void);
125 125
126#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16)) 126#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
127 127
128#ifdef CONFIG_CPU_FREQ
129#define CPUFREQ_CPU 0
130#endif
128struct bfin_dpmc_platform_data { 131struct bfin_dpmc_platform_data {
129 const unsigned int *tuple_tab; 132 const unsigned int *tuple_tab;
130 unsigned short tabsize; 133 unsigned short tabsize;
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 40f94a704c02..9e0cc0e2534f 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -34,11 +34,12 @@
34#include <asm/bitops.h> 34#include <asm/bitops.h>
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37#include <asm/bitsperlong.h>
37 38
38#define IPIPE_ARCH_STRING "1.12-00" 39#define IPIPE_ARCH_STRING "1.16-01"
39#define IPIPE_MAJOR_NUMBER 1 40#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 12 41#define IPIPE_MINOR_NUMBER 16
41#define IPIPE_PATCH_NUMBER 0 42#define IPIPE_PATCH_NUMBER 1
42 43
43#ifdef CONFIG_SMP 44#ifdef CONFIG_SMP
44#error "I-pipe/blackfin: SMP not implemented" 45#error "I-pipe/blackfin: SMP not implemented"
@@ -55,25 +56,19 @@ do { \
55#define task_hijacked(p) \ 56#define task_hijacked(p) \
56 ({ \ 57 ({ \
57 int __x__ = __ipipe_root_domain_p; \ 58 int __x__ = __ipipe_root_domain_p; \
58 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_root_cpudom_var(status)); \
59 if (__x__) \ 59 if (__x__) \
60 hard_local_irq_enable(); \ 60 hard_local_irq_enable(); \
61 !__x__; \ 61 !__x__; \
62 }) 62 })
63 63
64struct ipipe_domain; 64struct ipipe_domain;
65 65
66struct ipipe_sysinfo { 66struct ipipe_sysinfo {
67 67 int sys_nr_cpus; /* Number of CPUs on board */
68 int ncpus; /* Number of CPUs on board */ 68 int sys_hrtimer_irq; /* hrtimer device IRQ */
69 u64 cpufreq; /* CPU frequency (in Hz) */ 69 u64 sys_hrtimer_freq; /* hrtimer device frequency */
70 70 u64 sys_hrclock_freq; /* hrclock device frequency */
71 /* Arch-dependent block */ 71 u64 sys_cpu_freq; /* CPU frequency (Hz) */
72
73 struct {
74 unsigned tmirq; /* Timer tick IRQ */
75 u64 tmfreq; /* Timer frequency */
76 } archdep;
77}; 72};
78 73
79#define ipipe_read_tsc(t) \ 74#define ipipe_read_tsc(t) \
@@ -115,9 +110,19 @@ void __ipipe_enable_irqdesc(struct ipipe_domain *ipd,
115void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, 110void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
116 unsigned irq); 111 unsigned irq);
117 112
118#define __ipipe_enable_irq(irq) (irq_desc[irq].chip->unmask(irq)) 113#define __ipipe_enable_irq(irq) \
114 do { \
115 struct irq_desc *desc = irq_to_desc(irq); \
116 struct irq_chip *chip = get_irq_desc_chip(desc); \
117 chip->irq_unmask(&desc->irq_data); \
118 } while (0)
119 119
120#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) 120#define __ipipe_disable_irq(irq) \
121 do { \
122 struct irq_desc *desc = irq_to_desc(irq); \
123 struct irq_chip *chip = get_irq_desc_chip(desc); \
124 chip->irq_mask(&desc->irq_data); \
125 } while (0)
121 126
122static inline int __ipipe_check_tickdev(const char *devname) 127static inline int __ipipe_check_tickdev(const char *devname)
123{ 128{
@@ -128,12 +133,11 @@ void __ipipe_enable_pipeline(void);
128 133
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 134#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130 135
131#define __ipipe_sync_pipeline ___ipipe_sync_pipeline 136void ___ipipe_sync_pipeline(void);
132void ___ipipe_sync_pipeline(unsigned long syncmask);
133 137
134void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); 138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
135 139
136int __ipipe_get_irq_priority(unsigned irq); 140int __ipipe_get_irq_priority(unsigned int irq);
137 141
138void __ipipe_serial_debug(const char *fmt, ...); 142void __ipipe_serial_debug(const char *fmt, ...);
139 143
@@ -152,7 +156,10 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
152 return ffs(ul) - 1; 156 return ffs(ul) - 1;
153} 157}
154 158
155#define __ipipe_run_irqtail() /* Must be a macro */ \ 159#define __ipipe_do_root_xirq(ipd, irq) \
160 ((ipd)->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)))
161
162#define __ipipe_run_irqtail(irq) /* Must be a macro */ \
156 do { \ 163 do { \
157 unsigned long __pending; \ 164 unsigned long __pending; \
158 CSYNC(); \ 165 CSYNC(); \
@@ -164,42 +171,8 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
164 } \ 171 } \
165 } while (0) 172 } while (0)
166 173
167#define __ipipe_run_isr(ipd, irq) \
168 do { \
169 if (!__ipipe_pipeline_head_p(ipd)) \
170 hard_local_irq_enable(); \
171 if (ipd == ipipe_root_domain) { \
172 if (unlikely(ipipe_virtual_irq_p(irq))) { \
173 irq_enter(); \
174 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
175 irq_exit(); \
176 } else \
177 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
178 } else { \
179 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
180 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
181 /* Attempt to exit the outer interrupt level before \
182 * starting the deferred IRQ processing. */ \
183 __ipipe_run_irqtail(); \
184 __set_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
185 } \
186 hard_local_irq_disable(); \
187 } while (0)
188
189#define __ipipe_syscall_watched_p(p, sc) \ 174#define __ipipe_syscall_watched_p(p, sc) \
190 (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls) 175 (ipipe_notifier_enabled_p(p) || (unsigned long)sc >= NR_syscalls)
191
192void ipipe_init_irq_threads(void);
193
194int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
195
196#ifdef CONFIG_TICKSOURCE_CORETMR
197#define IRQ_SYSTMR IRQ_CORETMR
198#define IRQ_PRIOTMR IRQ_CORETMR
199#else
200#define IRQ_SYSTMR IRQ_TIMER0
201#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
202#endif
203 176
204#ifdef CONFIG_BF561 177#ifdef CONFIG_BF561
205#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) 178#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
@@ -219,11 +192,11 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219 192
220#define task_hijacked(p) 0 193#define task_hijacked(p) 0
221#define ipipe_trap_notify(t, r) 0 194#define ipipe_trap_notify(t, r) 0
195#define __ipipe_root_tick_p(regs) 1
222 196
223#define ipipe_init_irq_threads() do { } while (0) 197#endif /* !CONFIG_IPIPE */
224#define ipipe_start_irq_thread(irq, desc) 0
225 198
226#ifndef CONFIG_TICKSOURCE_GPTMR0 199#ifdef CONFIG_TICKSOURCE_CORETMR
227#define IRQ_SYSTMR IRQ_CORETMR 200#define IRQ_SYSTMR IRQ_CORETMR
228#define IRQ_PRIOTMR IRQ_CORETMR 201#define IRQ_PRIOTMR IRQ_CORETMR
229#else 202#else
@@ -231,10 +204,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
231#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 204#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
232#endif 205#endif
233 206
234#define __ipipe_root_tick_p(regs) 1
235
236#endif /* !CONFIG_IPIPE */
237
238#define ipipe_update_tick_evtdev(evtdev) do { } while (0) 207#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
239 208
240#endif /* !__ASM_BLACKFIN_IPIPE_H */ 209#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index 00409201d9ed..84a4ffd36747 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -24,8 +24,10 @@
24 24
25#ifdef CONFIG_IPIPE 25#ifdef CONFIG_IPIPE
26 26
27#include <asm/bitsperlong.h>
28#include <mach/irq.h>
29
27#define IPIPE_NR_XIRQS NR_IRQS 30#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29 31
30/* Blackfin-specific, per-cpu pipeline status */ 32/* Blackfin-specific, per-cpu pipeline status */
31#define IPIPE_SYNCDEFER_FLAG 15 33#define IPIPE_SYNCDEFER_FLAG 15
@@ -42,11 +44,14 @@
42#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4) 44#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
43#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5) 45#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
44#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6) 46#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
45#define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP 47#define IPIPE_EVENT_RETURN (IPIPE_FIRST_EVENT + 7)
48#define IPIPE_LAST_EVENT IPIPE_EVENT_RETURN
46#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1) 49#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
47 50
48#define IPIPE_TIMER_IRQ IRQ_CORETMR 51#define IPIPE_TIMER_IRQ IRQ_CORETMR
49 52
53#define __IPIPE_FEATURE_SYSINFO_V2 1
54
50#ifndef __ASSEMBLY__ 55#ifndef __ASSEMBLY__
51 56
52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 57extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
@@ -63,6 +68,8 @@ void __ipipe_unlock_root(void);
63 68
64#endif /* !__ASSEMBLY__ */ 69#endif /* !__ASSEMBLY__ */
65 70
71#define __IPIPE_FEATURE_SYSINFO_V2 1
72
66#endif /* CONFIG_IPIPE */ 73#endif /* CONFIG_IPIPE */
67 74
68#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */ 75#endif /* !__ASM_BLACKFIN_IPIPE_BASE_H */
diff --git a/arch/blackfin/include/asm/irqflags.h b/arch/blackfin/include/asm/irqflags.h
index 3365cb97f539..b4bbb75a9e15 100644
--- a/arch/blackfin/include/asm/irqflags.h
+++ b/arch/blackfin/include/asm/irqflags.h
@@ -89,15 +89,33 @@ static inline void __hard_local_irq_restore(unsigned long flags)
89#ifdef CONFIG_IPIPE 89#ifdef CONFIG_IPIPE
90 90
91#include <linux/compiler.h> 91#include <linux/compiler.h>
92#include <linux/ipipe_base.h>
93#include <linux/ipipe_trace.h> 92#include <linux/ipipe_trace.h>
93/*
94 * Way too many inter-deps between low-level headers in this port, so
95 * we redeclare the required bits we cannot pick from
96 * <asm/ipipe_base.h> to prevent circular dependencies.
97 */
98void __ipipe_stall_root(void);
99void __ipipe_unstall_root(void);
100unsigned long __ipipe_test_root(void);
101unsigned long __ipipe_test_and_stall_root(void);
102void __ipipe_restore_root(unsigned long flags);
103
104#ifdef CONFIG_IPIPE_DEBUG_CONTEXT
105struct ipipe_domain;
106extern struct ipipe_domain ipipe_root;
107void ipipe_check_context(struct ipipe_domain *ipd);
108#define __check_irqop_context(ipd) ipipe_check_context(&ipipe_root)
109#else /* !CONFIG_IPIPE_DEBUG_CONTEXT */
110#define __check_irqop_context(ipd) do { } while (0)
111#endif /* !CONFIG_IPIPE_DEBUG_CONTEXT */
94 112
95/* 113/*
96 * Interrupt pipe interface to linux/irqflags.h. 114 * Interrupt pipe interface to linux/irqflags.h.
97 */ 115 */
98static inline void arch_local_irq_disable(void) 116static inline void arch_local_irq_disable(void)
99{ 117{
100 ipipe_check_context(ipipe_root_domain); 118 __check_irqop_context();
101 __ipipe_stall_root(); 119 __ipipe_stall_root();
102 barrier(); 120 barrier();
103} 121}
@@ -105,7 +123,7 @@ static inline void arch_local_irq_disable(void)
105static inline void arch_local_irq_enable(void) 123static inline void arch_local_irq_enable(void)
106{ 124{
107 barrier(); 125 barrier();
108 ipipe_check_context(ipipe_root_domain); 126 __check_irqop_context();
109 __ipipe_unstall_root(); 127 __ipipe_unstall_root();
110} 128}
111 129
@@ -119,16 +137,21 @@ static inline int arch_irqs_disabled_flags(unsigned long flags)
119 return flags == bfin_no_irqs; 137 return flags == bfin_no_irqs;
120} 138}
121 139
122static inline void arch_local_irq_save_ptr(unsigned long *_flags) 140static inline unsigned long arch_local_irq_save(void)
123{ 141{
124 x = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags; 142 unsigned long flags;
143
144 __check_irqop_context();
145 flags = __ipipe_test_and_stall_root() ? bfin_no_irqs : bfin_irq_flags;
125 barrier(); 146 barrier();
147
148 return flags;
126} 149}
127 150
128static inline unsigned long arch_local_irq_save(void) 151static inline void arch_local_irq_restore(unsigned long flags)
129{ 152{
130 ipipe_check_context(ipipe_root_domain); 153 __check_irqop_context();
131 return __hard_local_irq_save(); 154 __ipipe_restore_root(flags == bfin_no_irqs);
132} 155}
133 156
134static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real) 157static inline unsigned long arch_mangle_irq_bits(int virt, unsigned long real)
@@ -192,7 +215,10 @@ static inline void hard_local_irq_restore(unsigned long flags)
192# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) 215# define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
193#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */ 216#endif /* !CONFIG_IPIPE_TRACE_IRQSOFF */
194 217
195#else /* CONFIG_IPIPE */ 218#define hard_local_irq_save_cond() hard_local_irq_save()
219#define hard_local_irq_restore_cond(flags) hard_local_irq_restore(flags)
220
221#else /* !CONFIG_IPIPE */
196 222
197/* 223/*
198 * Direct interface to linux/irqflags.h. 224 * Direct interface to linux/irqflags.h.
@@ -212,7 +238,48 @@ static inline void hard_local_irq_restore(unsigned long flags)
212#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags) 238#define hard_local_irq_restore(flags) __hard_local_irq_restore(flags)
213#define hard_local_irq_enable() __hard_local_irq_enable() 239#define hard_local_irq_enable() __hard_local_irq_enable()
214#define hard_local_irq_disable() __hard_local_irq_disable() 240#define hard_local_irq_disable() __hard_local_irq_disable()
215 241#define hard_local_irq_save_cond() hard_local_save_flags()
242#define hard_local_irq_restore_cond(flags) do { (void)(flags); } while (0)
216 243
217#endif /* !CONFIG_IPIPE */ 244#endif /* !CONFIG_IPIPE */
245
246#ifdef CONFIG_SMP
247#define hard_local_irq_save_smp() hard_local_irq_save()
248#define hard_local_irq_restore_smp(flags) hard_local_irq_restore(flags)
249#else
250#define hard_local_irq_save_smp() hard_local_save_flags()
251#define hard_local_irq_restore_smp(flags) do { (void)(flags); } while (0)
252#endif
253
254/*
255 * Remap the arch-neutral IRQ state manipulation macros to the
256 * blackfin-specific hard_local_irq_* API.
257 */
258#define local_irq_save_hw(flags) \
259 do { \
260 (flags) = hard_local_irq_save(); \
261 } while (0)
262#define local_irq_restore_hw(flags) \
263 do { \
264 hard_local_irq_restore(flags); \
265 } while (0)
266#define local_irq_disable_hw() \
267 do { \
268 hard_local_irq_disable(); \
269 } while (0)
270#define local_irq_enable_hw() \
271 do { \
272 hard_local_irq_enable(); \
273 } while (0)
274#define local_irq_save_hw_notrace(flags) \
275 do { \
276 (flags) = __hard_local_irq_save(); \
277 } while (0)
278#define local_irq_restore_hw_notrace(flags) \
279 do { \
280 __hard_local_irq_restore(flags); \
281 } while (0)
282
283#define irqs_disabled_hw() hard_irqs_disabled()
284
218#endif 285#endif
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
index f5b537967116..af6c0aa79bae 100644
--- a/arch/blackfin/include/asm/smp.h
+++ b/arch/blackfin/include/asm/smp.h
@@ -17,7 +17,12 @@
17 17
18#define raw_smp_processor_id() blackfin_core_id() 18#define raw_smp_processor_id() blackfin_core_id()
19 19
20extern char coreb_trampoline_start, coreb_trampoline_end; 20extern void bfin_relocate_coreb_l1_mem(void);
21
22#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
23asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
24extern unsigned long blackfin_iflush_l1_entry[NR_CPUS];
25#endif
21 26
22struct corelock_slot { 27struct corelock_slot {
23 int lock; 28 int lock;
@@ -34,7 +39,7 @@ extern unsigned long dcache_invld_count[NR_CPUS];
34void smp_icache_flush_range_others(unsigned long start, 39void smp_icache_flush_range_others(unsigned long start,
35 unsigned long end); 40 unsigned long end);
36#ifdef CONFIG_HOTPLUG_CPU 41#ifdef CONFIG_HOTPLUG_CPU
37void coreb_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2); 42void coreb_die(void);
38void cpu_die(void); 43void cpu_die(void);
39void platform_cpu_die(void); 44void platform_cpu_die(void);
40int __cpu_disable(void); 45int __cpu_disable(void);
diff --git a/arch/blackfin/include/asm/unistd.h b/arch/blackfin/include/asm/unistd.h
index 928ae975b87e..c97497dd0d19 100644
--- a/arch/blackfin/include/asm/unistd.h
+++ b/arch/blackfin/include/asm/unistd.h
@@ -393,8 +393,11 @@
393#define __NR_fanotify_mark 372 393#define __NR_fanotify_mark 372
394#define __NR_prlimit64 373 394#define __NR_prlimit64 373
395#define __NR_cacheflush 374 395#define __NR_cacheflush 374
396#define __NR_name_to_handle_at 375
397#define __NR_open_by_handle_at 376
398#define __NR_clock_adjtime 377
396 399
397#define __NR_syscall 375 400#define __NR_syscall 378
398#define NR_syscalls __NR_syscall 401#define NR_syscalls __NR_syscall
399 402
400/* Old optional stuff no one actually uses */ 403/* Old optional stuff no one actually uses */
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 1e485dfdc9f2..6ce8dce753c9 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -84,6 +84,24 @@ static int __init proc_dma_init(void)
84late_initcall(proc_dma_init); 84late_initcall(proc_dma_init);
85#endif 85#endif
86 86
87static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
88{
89#ifdef CONFIG_BF54x
90 unsigned int per_map;
91
92 switch (channel) {
93 case CH_UART2_RX: per_map = 0xC << 12; break;
94 case CH_UART2_TX: per_map = 0xD << 12; break;
95 case CH_UART3_RX: per_map = 0xE << 12; break;
96 case CH_UART3_TX: per_map = 0xF << 12; break;
97 default: return;
98 }
99
100 if (strncmp(device_id, "BFIN_UART", 9) == 0)
101 dma_ch[channel].regs->peripheral_map = per_map;
102#endif
103}
104
87/** 105/**
88 * request_dma - request a DMA channel 106 * request_dma - request a DMA channel
89 * 107 *
@@ -111,19 +129,7 @@ int request_dma(unsigned int channel, const char *device_id)
111 return -EBUSY; 129 return -EBUSY;
112 } 130 }
113 131
114#ifdef CONFIG_BF54x 132 set_dma_peripheral_map(channel, device_id);
115 if (channel >= CH_UART2_RX && channel <= CH_UART3_TX) {
116 unsigned int per_map;
117 per_map = dma_ch[channel].regs->peripheral_map & 0xFFF;
118 if (strncmp(device_id, "BFIN_UART", 9) == 0)
119 dma_ch[channel].regs->peripheral_map = per_map |
120 ((channel - CH_UART2_RX + 0xC)<<12);
121 else
122 dma_ch[channel].regs->peripheral_map = per_map |
123 ((channel - CH_UART2_RX + 0x6)<<12);
124 }
125#endif
126
127 dma_ch[channel].device_id = device_id; 133 dma_ch[channel].device_id = device_id;
128 dma_ch[channel].irq = 0; 134 dma_ch[channel].irq = 0;
129 135
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 3b1da4aff2a1..f37019c847c9 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -154,7 +154,7 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
154 * pending for it. 154 * pending for it.
155 */ 155 */
156 if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) && 156 if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
157 ipipe_head_cpudom_var(irqpend_himask) == 0) 157 !__ipipe_ipending_p(ipipe_head_cpudom_ptr()))
158 goto out; 158 goto out;
159 159
160 __ipipe_walk_pipeline(head); 160 __ipipe_walk_pipeline(head);
@@ -185,25 +185,21 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
185} 185}
186EXPORT_SYMBOL(__ipipe_disable_irqdesc); 186EXPORT_SYMBOL(__ipipe_disable_irqdesc);
187 187
188int __ipipe_syscall_root(struct pt_regs *regs) 188asmlinkage int __ipipe_syscall_root(struct pt_regs *regs)
189{ 189{
190 struct ipipe_percpu_domain_data *p; 190 struct ipipe_percpu_domain_data *p;
191 unsigned long flags; 191 void (*hook)(void);
192 int ret; 192 int ret;
193 193
194 WARN_ON_ONCE(irqs_disabled_hw());
195
194 /* 196 /*
195 * We need to run the IRQ tail hook whenever we don't 197 * We need to run the IRQ tail hook each time we intercept a
196 * propagate a syscall to higher domains, because we know that 198 * syscall, because we know that important operations might be
197 * important operations might be pending there (e.g. Xenomai 199 * pending there (e.g. Xenomai deferred rescheduling).
198 * deferred rescheduling).
199 */ 200 */
200 201 hook = (__typeof__(hook))__ipipe_irq_tail_hook;
201 if (regs->orig_p0 < NR_syscalls) { 202 hook();
202 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
203 hook();
204 if ((current->flags & PF_EVNOTIFY) == 0)
205 return 0;
206 }
207 203
208 /* 204 /*
209 * This routine either returns: 205 * This routine either returns:
@@ -214,51 +210,47 @@ int __ipipe_syscall_root(struct pt_regs *regs)
214 * tail work has to be performed (for handling signals etc). 210 * tail work has to be performed (for handling signals etc).
215 */ 211 */
216 212
217 if (!__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL)) 213 if (!__ipipe_syscall_watched_p(current, regs->orig_p0) ||
214 !__ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL))
218 return 0; 215 return 0;
219 216
220 ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs); 217 ret = __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL, regs);
221 218
222 flags = hard_local_irq_save(); 219 hard_local_irq_disable();
223 220
224 if (!__ipipe_root_domain_p) { 221 /*
225 hard_local_irq_restore(flags); 222 * This is the end of the syscall path, so we may
226 return 1; 223 * safely assume a valid Linux task stack here.
224 */
225 if (current->ipipe_flags & PF_EVTRET) {
226 current->ipipe_flags &= ~PF_EVTRET;
227 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
227 } 228 }
228 229
229 p = ipipe_root_cpudom_ptr(); 230 if (!__ipipe_root_domain_p)
230 if ((p->irqpend_himask & IPIPE_IRQMASK_VIRT) != 0) 231 ret = -1;
231 __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT); 232 else {
233 p = ipipe_root_cpudom_ptr();
234 if (__ipipe_ipending_p(p))
235 __ipipe_sync_pipeline();
236 }
232 237
233 hard_local_irq_restore(flags); 238 hard_local_irq_enable();
234 239
235 return -ret; 240 return -ret;
236} 241}
237 242
238unsigned long ipipe_critical_enter(void (*syncfn) (void))
239{
240 unsigned long flags;
241
242 flags = hard_local_irq_save();
243
244 return flags;
245}
246
247void ipipe_critical_exit(unsigned long flags)
248{
249 hard_local_irq_restore(flags);
250}
251
252static void __ipipe_no_irqtail(void) 243static void __ipipe_no_irqtail(void)
253{ 244{
254} 245}
255 246
256int ipipe_get_sysinfo(struct ipipe_sysinfo *info) 247int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
257{ 248{
258 info->ncpus = num_online_cpus(); 249 info->sys_nr_cpus = num_online_cpus();
259 info->cpufreq = ipipe_cpu_freq(); 250 info->sys_cpu_freq = ipipe_cpu_freq();
260 info->archdep.tmirq = IPIPE_TIMER_IRQ; 251 info->sys_hrtimer_irq = IPIPE_TIMER_IRQ;
261 info->archdep.tmfreq = info->cpufreq; 252 info->sys_hrtimer_freq = __ipipe_core_clock;
253 info->sys_hrclock_freq = __ipipe_core_clock;
262 254
263 return 0; 255 return 0;
264} 256}
@@ -289,6 +281,7 @@ int ipipe_trigger_irq(unsigned irq)
289asmlinkage void __ipipe_sync_root(void) 281asmlinkage void __ipipe_sync_root(void)
290{ 282{
291 void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; 283 void (*irq_tail_hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
284 struct ipipe_percpu_domain_data *p;
292 unsigned long flags; 285 unsigned long flags;
293 286
294 BUG_ON(irqs_disabled()); 287 BUG_ON(irqs_disabled());
@@ -300,19 +293,20 @@ asmlinkage void __ipipe_sync_root(void)
300 293
301 clear_thread_flag(TIF_IRQ_SYNC); 294 clear_thread_flag(TIF_IRQ_SYNC);
302 295
303 if (ipipe_root_cpudom_var(irqpend_himask) != 0) 296 p = ipipe_root_cpudom_ptr();
304 __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY); 297 if (__ipipe_ipending_p(p))
298 __ipipe_sync_pipeline();
305 299
306 hard_local_irq_restore(flags); 300 hard_local_irq_restore(flags);
307} 301}
308 302
309void ___ipipe_sync_pipeline(unsigned long syncmask) 303void ___ipipe_sync_pipeline(void)
310{ 304{
311 if (__ipipe_root_domain_p && 305 if (__ipipe_root_domain_p &&
312 test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) 306 test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
313 return; 307 return;
314 308
315 __ipipe_sync_stage(syncmask); 309 __ipipe_sync_stage();
316} 310}
317 311
318void __ipipe_disable_root_irqs_hw(void) 312void __ipipe_disable_root_irqs_hw(void)
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 64cff54a8a58..8f079392aff0 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -39,21 +39,23 @@ int show_interrupts(struct seq_file *p, void *v)
39 unsigned long flags; 39 unsigned long flags;
40 40
41 if (i < NR_IRQS) { 41 if (i < NR_IRQS) {
42 raw_spin_lock_irqsave(&irq_desc[i].lock, flags); 42 struct irq_desc *desc = irq_to_desc(i);
43 action = irq_desc[i].action; 43
44 raw_spin_lock_irqsave(&desc->lock, flags);
45 action = desc->action;
44 if (!action) 46 if (!action)
45 goto skip; 47 goto skip;
46 seq_printf(p, "%3d: ", i); 48 seq_printf(p, "%3d: ", i);
47 for_each_online_cpu(j) 49 for_each_online_cpu(j)
48 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 50 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
49 seq_printf(p, " %8s", irq_desc[i].chip->name); 51 seq_printf(p, " %8s", get_irq_desc_chip(desc)->name);
50 seq_printf(p, " %s", action->name); 52 seq_printf(p, " %s", action->name);
51 for (action = action->next; action; action = action->next) 53 for (action = action->next; action; action = action->next)
52 seq_printf(p, " %s", action->name); 54 seq_printf(p, " %s", action->name);
53 55
54 seq_putc(p, '\n'); 56 seq_putc(p, '\n');
55 skip: 57 skip:
56 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); 58 raw_spin_unlock_irqrestore(&desc->lock, flags);
57 } else if (i == NR_IRQS) { 59 } else if (i == NR_IRQS) {
58 seq_printf(p, "NMI: "); 60 seq_printf(p, "NMI: ");
59 for_each_online_cpu(j) 61 for_each_online_cpu(j)
diff --git a/arch/blackfin/kernel/kgdb.c b/arch/blackfin/kernel/kgdb.c
index eb92592fd80c..b8cfe34989e4 100644
--- a/arch/blackfin/kernel/kgdb.c
+++ b/arch/blackfin/kernel/kgdb.c
@@ -422,11 +422,7 @@ int kgdb_arch_handle_exception(int vector, int signo,
422 422
423struct kgdb_arch arch_kgdb_ops = { 423struct kgdb_arch arch_kgdb_ops = {
424 .gdb_bpt_instr = {0xa1}, 424 .gdb_bpt_instr = {0xa1},
425#ifdef CONFIG_SMP
426 .flags = KGDB_HW_BREAKPOINT|KGDB_THR_PROC_SWAP,
427#else
428 .flags = KGDB_HW_BREAKPOINT, 425 .flags = KGDB_HW_BREAKPOINT,
429#endif
430 .set_hw_breakpoint = bfin_set_hw_break, 426 .set_hw_breakpoint = bfin_set_hw_break,
431 .remove_hw_breakpoint = bfin_remove_hw_break, 427 .remove_hw_breakpoint = bfin_remove_hw_break,
432 .disable_hw_break = bfin_disable_hw_debug, 428 .disable_hw_break = bfin_disable_hw_debug,
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index ac71dc15cbdb..805c6132c779 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -215,11 +215,48 @@ void __init bfin_relocate_l1_mem(void)
215 215
216 early_dma_memcpy_done(); 216 early_dma_memcpy_done();
217 217
218#if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
219 blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
220#endif
221
218 /* if necessary, copy L2 text/data to L2 SRAM */ 222 /* if necessary, copy L2 text/data to L2 SRAM */
219 if (L2_LENGTH && l2_len) 223 if (L2_LENGTH && l2_len)
220 memcpy(_stext_l2, _l2_lma, l2_len); 224 memcpy(_stext_l2, _l2_lma, l2_len);
221} 225}
222 226
227#ifdef CONFIG_SMP
228void __init bfin_relocate_coreb_l1_mem(void)
229{
230 unsigned long text_l1_len = (unsigned long)_text_l1_len;
231 unsigned long data_l1_len = (unsigned long)_data_l1_len;
232 unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
233
234 blackfin_dma_early_init();
235
236 /* if necessary, copy L1 text to L1 instruction SRAM */
237 if (L1_CODE_LENGTH && text_l1_len)
238 early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
239 text_l1_len);
240
241 /* if necessary, copy L1 data to L1 data bank A SRAM */
242 if (L1_DATA_A_LENGTH && data_l1_len)
243 early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
244 data_l1_len);
245
246 /* if necessary, copy L1 data B to L1 data bank B SRAM */
247 if (L1_DATA_B_LENGTH && data_b_l1_len)
248 early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
249 data_b_l1_len);
250
251 early_dma_memcpy_done();
252
253#ifdef CONFIG_ICACHE_FLUSH_L1
254 blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
255 (unsigned long)_stext_l1 + COREB_L1_CODE_START;
256#endif
257}
258#endif
259
223#ifdef CONFIG_ROMKERNEL 260#ifdef CONFIG_ROMKERNEL
224void __init bfin_relocate_xip_data(void) 261void __init bfin_relocate_xip_data(void)
225{ 262{
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index c40d07f708e8..854fa49f1c3e 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -136,7 +136,7 @@ SECTIONS
136 136
137 . = ALIGN(16); 137 . = ALIGN(16);
138 INIT_DATA_SECTION(16) 138 INIT_DATA_SECTION(16)
139 PERCPU(32, 4) 139 PERCPU(32, PAGE_SIZE)
140 140
141 .exit.data : 141 .exit.data :
142 { 142 {
@@ -176,6 +176,7 @@ SECTIONS
176 { 176 {
177 . = ALIGN(4); 177 . = ALIGN(4);
178 __stext_l1 = .; 178 __stext_l1 = .;
179 *(.l1.text.head)
179 *(.l1.text) 180 *(.l1.text)
180#ifdef CONFIG_SCHEDULE_L1 181#ifdef CONFIG_SCHEDULE_L1
181 SCHED_TEXT 182 SCHED_TEXT
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index 27285823fb25..cb1172f50757 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -1201,25 +1201,6 @@
1201#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ 1201#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1202#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ 1202#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1203 1203
1204
1205/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1206/* HDMAx_CTL Masks */
1207#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1208#define REP 0x0002 /* HDMA Request Polarity */
1209#define UTE 0x0004 /* Urgency Threshold Enable */
1210#define OIE 0x0010 /* Overflow Interrupt Enable */
1211#define BDIE 0x0020 /* Block Done Interrupt Enable */
1212#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1213#define DRQ 0x0300 /* HDMA Request Type */
1214#define DRQ_NONE 0x0000 /* No Request */
1215#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1216#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1217#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1218#define RBC 0x1000 /* Reload BCNT With IBCNT */
1219#define PS 0x2000 /* HDMA Pin Status */
1220#define OI 0x4000 /* Overflow Interrupt Generated */
1221#define BDI 0x8000 /* Block Done Interrupt Generated */
1222
1223/* entry addresses of the user-callable Boot ROM functions */ 1204/* entry addresses of the user-callable Boot ROM functions */
1224 1205
1225#define _BOOTROM_RESET 0xEF000000 1206#define _BOOTROM_RESET 0xEF000000
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 89f5420ee6cd..84ef11e52644 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -1204,25 +1204,6 @@
1204#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ 1204#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1205#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ 1205#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1206 1206
1207
1208/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1209/* HDMAx_CTL Masks */
1210#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1211#define REP 0x0002 /* HDMA Request Polarity */
1212#define UTE 0x0004 /* Urgency Threshold Enable */
1213#define OIE 0x0010 /* Overflow Interrupt Enable */
1214#define BDIE 0x0020 /* Block Done Interrupt Enable */
1215#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1216#define DRQ 0x0300 /* HDMA Request Type */
1217#define DRQ_NONE 0x0000 /* No Request */
1218#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1219#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1220#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1221#define RBC 0x1000 /* Reload BCNT With IBCNT */
1222#define PS 0x2000 /* HDMA Pin Status */
1223#define OI 0x4000 /* Overflow Interrupt Generated */
1224#define BDI 0x8000 /* Block Done Interrupt Generated */
1225
1226/* entry addresses of the user-callable Boot ROM functions */ 1207/* entry addresses of the user-callable Boot ROM functions */
1227 1208
1228#define _BOOTROM_RESET 0xEF000000 1209#define _BOOTROM_RESET 0xEF000000
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index f869a3711480..a377d8afea03 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -289,8 +289,6 @@ static struct platform_device *ip0x_devices[] __initdata = {
289 289
290static int __init ip0x_init(void) 290static int __init ip0x_init(void)
291{ 291{
292 int i;
293
294 printk(KERN_INFO "%s(): registering device resources\n", __func__); 292 printk(KERN_INFO "%s(): registering device resources\n", __func__);
295 platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices)); 293 platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
296 294
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 2c776e188a94..d582b810e7a7 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -775,7 +775,7 @@ static int __init cm_bf537e_init(void)
775#endif 775#endif
776 776
777#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 777#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
778 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 778 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
779#endif 779#endif
780 return 0; 780 return 0;
781} 781}
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537u.c b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
index 085661175ec7..cbb8098604c5 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537u.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537u.c
@@ -740,7 +740,7 @@ static int __init cm_bf537u_init(void)
740#endif 740#endif
741 741
742#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 742#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
743 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 743 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
744#endif 744#endif
745 return 0; 745 return 0;
746} 746}
diff --git a/arch/blackfin/mach-bf537/boards/dnp5370.c b/arch/blackfin/mach-bf537/boards/dnp5370.c
index e1e9ea02ad89..6b4ff4605bff 100644
--- a/arch/blackfin/mach-bf537/boards/dnp5370.c
+++ b/arch/blackfin/mach-bf537/boards/dnp5370.c
@@ -128,30 +128,11 @@ static struct platform_device asmb_flash_device = {
128 128
129#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) 129#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
130 130
131#define MMC_SPI_CARD_DETECT_INT IRQ_PF5
132
133static int bfin_mmc_spi_init(struct device *dev,
134 irqreturn_t (*detect_int)(int, void *), void *data)
135{
136 return request_irq(MMC_SPI_CARD_DETECT_INT, detect_int,
137 IRQF_TRIGGER_FALLING, "mmc-spi-detect", data);
138}
139
140static void bfin_mmc_spi_exit(struct device *dev, void *data)
141{
142 free_irq(MMC_SPI_CARD_DETECT_INT, data);
143}
144
145static struct bfin5xx_spi_chip mmc_spi_chip_info = { 131static struct bfin5xx_spi_chip mmc_spi_chip_info = {
146 .enable_dma = 0, /* use no dma transfer with this chip*/ 132 .enable_dma = 0, /* use no dma transfer with this chip*/
147 .bits_per_word = 8, 133 .bits_per_word = 8,
148}; 134};
149 135
150static struct mmc_spi_platform_data bfin_mmc_spi_pdata = {
151 .init = bfin_mmc_spi_init,
152 .exit = bfin_mmc_spi_exit,
153 .detect_delay = 100, /* msecs */
154};
155#endif 136#endif
156 137
157#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE) 138#if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
@@ -192,7 +173,6 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
192 .max_speed_hz = 20000000, 173 .max_speed_hz = 20000000,
193 .bus_num = 0, 174 .bus_num = 0,
194 .chip_select = 1, 175 .chip_select = 1,
195 .platform_data = &bfin_mmc_spi_pdata,
196 .controller_data = &mmc_spi_chip_info, 176 .controller_data = &mmc_spi_chip_info,
197 .mode = SPI_MODE_3, 177 .mode = SPI_MODE_3,
198 }, 178 },
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 0761b201abca..164a7e02c022 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -742,7 +742,7 @@ static int __init tcm_bf537_init(void)
742#endif 742#endif
743 743
744#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 744#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
745 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 745 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
746#endif 746#endif
747 return 0; 747 return 0;
748} 748}
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 725bb35f3aaa..4a031dde173f 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1520,24 +1520,6 @@
1520#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */ 1520#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1521#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */ 1521#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1522 1522
1523/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1524/* HDMAx_CTL Masks */
1525#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1526#define REP 0x0002 /* HDMA Request Polarity */
1527#define UTE 0x0004 /* Urgency Threshold Enable */
1528#define OIE 0x0010 /* Overflow Interrupt Enable */
1529#define BDIE 0x0020 /* Block Done Interrupt Enable */
1530#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1531#define DRQ 0x0300 /* HDMA Request Type */
1532#define DRQ_NONE 0x0000 /* No Request */
1533#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1534#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1535#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1536#define RBC 0x1000 /* Reload BCNT With IBCNT */
1537#define PS 0x2000 /* HDMA Pin Status */
1538#define OI 0x4000 /* Overflow Interrupt Generated */
1539#define BDI 0x8000 /* Block Done Interrupt Generated */
1540
1541/* entry addresses of the user-callable Boot ROM functions */ 1523/* entry addresses of the user-callable Boot ROM functions */
1542 1524
1543#define _BOOTROM_RESET 0xEF000000 1525#define _BOOTROM_RESET 0xEF000000
diff --git a/arch/blackfin/mach-bf548/Kconfig b/arch/blackfin/mach-bf548/Kconfig
index 70189a0d1a19..94acb586832e 100644
--- a/arch/blackfin/mach-bf548/Kconfig
+++ b/arch/blackfin/mach-bf548/Kconfig
@@ -42,6 +42,65 @@ config BF548_ATAPI_ALTERNATIVE_PORT
42 async address or GPIO port F and G. Select y to route it 42 async address or GPIO port F and G. Select y to route it
43 to GPIO. 43 to GPIO.
44 44
45choice
46 prompt "UART2 DMA channel selection"
47 depends on SERIAL_BFIN_UART2
48 default UART2_DMA_RX_ON_DMA18
49 help
50 UART2 DMA channel selection
51 RX -> DMA18
52 TX -> DMA19
53 or
54 RX -> DMA13
55 TX -> DMA14
56
57config UART2_DMA_RX_ON_DMA18
58 bool "UART2 DMA RX -> DMA18 TX -> DMA19"
59 help
60 UART2 DMA channel assignment
61 RX -> DMA18
62 TX -> DMA19
63 use SPORT2 default DMA channel
64
65config UART2_DMA_RX_ON_DMA13
66 bool "UART2 DMA RX -> DMA13 TX -> DMA14"
67 help
68 UART2 DMA channel assignment
69 RX -> DMA13
70 TX -> DMA14
71 use EPPI1 EPPI2 default DMA channel
72endchoice
73
74choice
75 prompt "UART3 DMA channel selection"
76 depends on SERIAL_BFIN_UART3
77 default UART3_DMA_RX_ON_DMA20
78 help
79 UART3 DMA channel selection
80 RX -> DMA20
81 TX -> DMA21
82 or
83 RX -> DMA15
84 TX -> DMA16
85
86config UART3_DMA_RX_ON_DMA20
87 bool "UART3 DMA RX -> DMA20 TX -> DMA21"
88 help
89 UART3 DMA channel assignment
90 RX -> DMA20
91 TX -> DMA21
92 use SPORT3 default DMA channel
93
94config UART3_DMA_RX_ON_DMA15
95 bool "UART3 DMA RX -> DMA15 TX -> DMA16"
96 help
97 UART3 DMA channel assignment
98 RX -> DMA15
99 TX -> DMA16
100 use PIXC default DMA channel
101
102endchoice
103
45comment "Interrupt Priority Assignment" 104comment "Interrupt Priority Assignment"
46menu "Priority" 105menu "Priority"
47 106
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index ce5a2bb147dc..93e19a54a880 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -778,11 +778,12 @@ static struct platform_device bfin_sport3_uart_device = {
778#endif 778#endif
779 779
780#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 780#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
781static unsigned short bfin_can_peripherals[] = { 781
782static unsigned short bfin_can0_peripherals[] = {
782 P_CAN0_RX, P_CAN0_TX, 0 783 P_CAN0_RX, P_CAN0_TX, 0
783}; 784};
784 785
785static struct resource bfin_can_resources[] = { 786static struct resource bfin_can0_resources[] = {
786 { 787 {
787 .start = 0xFFC02A00, 788 .start = 0xFFC02A00,
788 .end = 0xFFC02FFF, 789 .end = 0xFFC02FFF,
@@ -805,14 +806,53 @@ static struct resource bfin_can_resources[] = {
805 }, 806 },
806}; 807};
807 808
808static struct platform_device bfin_can_device = { 809static struct platform_device bfin_can0_device = {
809 .name = "bfin_can", 810 .name = "bfin_can",
810 .num_resources = ARRAY_SIZE(bfin_can_resources), 811 .id = 0,
811 .resource = bfin_can_resources, 812 .num_resources = ARRAY_SIZE(bfin_can0_resources),
813 .resource = bfin_can0_resources,
812 .dev = { 814 .dev = {
813 .platform_data = &bfin_can_peripherals, /* Passed to driver */ 815 .platform_data = &bfin_can0_peripherals, /* Passed to driver */
814 }, 816 },
815}; 817};
818
819static unsigned short bfin_can1_peripherals[] = {
820 P_CAN1_RX, P_CAN1_TX, 0
821};
822
823static struct resource bfin_can1_resources[] = {
824 {
825 .start = 0xFFC03200,
826 .end = 0xFFC037FF,
827 .flags = IORESOURCE_MEM,
828 },
829 {
830 .start = IRQ_CAN1_RX,
831 .end = IRQ_CAN1_RX,
832 .flags = IORESOURCE_IRQ,
833 },
834 {
835 .start = IRQ_CAN1_TX,
836 .end = IRQ_CAN1_TX,
837 .flags = IORESOURCE_IRQ,
838 },
839 {
840 .start = IRQ_CAN1_ERROR,
841 .end = IRQ_CAN1_ERROR,
842 .flags = IORESOURCE_IRQ,
843 },
844};
845
846static struct platform_device bfin_can1_device = {
847 .name = "bfin_can",
848 .id = 1,
849 .num_resources = ARRAY_SIZE(bfin_can1_resources),
850 .resource = bfin_can1_resources,
851 .dev = {
852 .platform_data = &bfin_can1_peripherals, /* Passed to driver */
853 },
854};
855
816#endif 856#endif
817 857
818#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) 858#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
@@ -1366,7 +1406,8 @@ static struct platform_device *ezkit_devices[] __initdata = {
1366#endif 1406#endif
1367 1407
1368#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE) 1408#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
1369 &bfin_can_device, 1409 &bfin_can0_device,
1410 &bfin_can1_device,
1370#endif 1411#endif
1371 1412
1372#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE) 1413#if defined(CONFIG_PATA_BF54X) || defined(CONFIG_PATA_BF54X_MODULE)
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF544.h b/arch/blackfin/mach-bf548/include/mach/defBF544.h
index 642468c1bcb1..bcccab36629c 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF544.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF544.h
@@ -657,22 +657,4 @@
657 657
658/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */ 658/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
659 659
660/* Bit masks for HMDMAx_CONTROL */
661
662#define HMDMAEN 0x1 /* Handshake MDMA Enable */
663#define REP 0x2 /* Handshake MDMA Request Polarity */
664#define UTE 0x8 /* Urgency Threshold Enable */
665#define OIE 0x10 /* Overflow Interrupt Enable */
666#define BDIE 0x20 /* Block Done Interrupt Enable */
667#define MBDI 0x40 /* Mask Block Done Interrupt */
668#define DRQ 0x300 /* Handshake MDMA Request Type */
669#define RBC 0x1000 /* Force Reload of BCOUNT */
670#define PS 0x2000 /* Pin Status */
671#define OI 0x4000 /* Overflow Interrupt Generated */
672#define BDI 0x8000 /* Block Done Interrupt Generated */
673
674/* ******************************************* */
675/* MULTI BIT MACRO ENUMERATIONS */
676/* ******************************************* */
677
678#endif /* _DEF_BF544_H */ 660#endif /* _DEF_BF544_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF547.h b/arch/blackfin/mach-bf548/include/mach/defBF547.h
index 2f3337cd311e..1cbba115f96f 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF547.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF547.h
@@ -1063,23 +1063,4 @@
1063 1063
1064#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */ 1064#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1065 1065
1066/* Bit masks for HMDMAx_CONTROL */
1067
1068#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1069#define REP 0x2 /* Handshake MDMA Request Polarity */
1070#define UTE 0x8 /* Urgency Threshold Enable */
1071#define OIE 0x10 /* Overflow Interrupt Enable */
1072#define BDIE 0x20 /* Block Done Interrupt Enable */
1073#define MBDI 0x40 /* Mask Block Done Interrupt */
1074#define DRQ 0x300 /* Handshake MDMA Request Type */
1075#define RBC 0x1000 /* Force Reload of BCOUNT */
1076#define PS 0x2000 /* Pin Status */
1077#define OI 0x4000 /* Overflow Interrupt Generated */
1078#define BDI 0x8000 /* Block Done Interrupt Generated */
1079
1080/* ******************************************* */
1081/* MULTI BIT MACRO ENUMERATIONS */
1082/* ******************************************* */
1083
1084
1085#endif /* _DEF_BF547_H */ 1066#endif /* _DEF_BF547_H */
diff --git a/arch/blackfin/mach-bf548/include/mach/dma.h b/arch/blackfin/mach-bf548/include/mach/dma.h
index a30d242c7398..1a1091b071fd 100644
--- a/arch/blackfin/mach-bf548/include/mach/dma.h
+++ b/arch/blackfin/mach-bf548/include/mach/dma.h
@@ -27,17 +27,37 @@
27#define CH_PIXC_OVERLAY 16 27#define CH_PIXC_OVERLAY 16
28#define CH_PIXC_OUTPUT 17 28#define CH_PIXC_OUTPUT 17
29#define CH_SPORT2_RX 18 29#define CH_SPORT2_RX 18
30#define CH_UART2_RX 18
31#define CH_SPORT2_TX 19 30#define CH_SPORT2_TX 19
32#define CH_UART2_TX 19
33#define CH_SPORT3_RX 20 31#define CH_SPORT3_RX 20
34#define CH_UART3_RX 20
35#define CH_SPORT3_TX 21 32#define CH_SPORT3_TX 21
36#define CH_UART3_TX 21
37#define CH_SDH 22 33#define CH_SDH 22
38#define CH_NFC 22 34#define CH_NFC 22
39#define CH_SPI2 23 35#define CH_SPI2 23
40 36
37#if defined(CONFIG_UART2_DMA_RX_ON_DMA13)
38#define CH_UART2_RX 13
39#define IRQ_UART2_RX BFIN_IRQ(37) /* UART2 RX USE EPP1 (DMA13) Interrupt */
40#define CH_UART2_TX 14
41#define IRQ_UART2_TX BFIN_IRQ(38) /* UART2 RX USE EPP1 (DMA14) Interrupt */
42#else /* Default USE SPORT2's DMA Channel */
43#define CH_UART2_RX 18
44#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
45#define CH_UART2_TX 19
46#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
47#endif
48
49#if defined(CONFIG_UART3_DMA_RX_ON_DMA15)
50#define CH_UART3_RX 15
51#define IRQ_UART3_RX BFIN_IRQ(64) /* UART3 RX USE PIXC IN0 (DMA15) Interrupt */
52#define CH_UART3_TX 16
53#define IRQ_UART3_TX BFIN_IRQ(65) /* UART3 TX USE PIXC IN1 (DMA16) Interrupt */
54#else /* Default USE SPORT3's DMA Channel */
55#define CH_UART3_RX 20
56#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
57#define CH_UART3_TX 21
58#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
59#endif
60
41#define CH_MEM_STREAM0_DEST 24 61#define CH_MEM_STREAM0_DEST 24
42#define CH_MEM_STREAM0_SRC 25 62#define CH_MEM_STREAM0_SRC 25
43#define CH_MEM_STREAM1_DEST 26 63#define CH_MEM_STREAM1_DEST 26
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 99fd1b2c53d8..7f87787e7738 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -74,13 +74,9 @@ Events (highest priority) EMU 0
74#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */ 74#define IRQ_UART2_ERROR BFIN_IRQ(31) /* UART2 Status (Error) Interrupt */
75#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */ 75#define IRQ_CAN0_ERROR BFIN_IRQ(32) /* CAN0 Status (Error) Interrupt */
76#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */ 76#define IRQ_SPORT2_RX BFIN_IRQ(33) /* SPORT2 RX (DMA18) Interrupt */
77#define IRQ_UART2_RX BFIN_IRQ(33) /* UART2 RX (DMA18) Interrupt */
78#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */ 77#define IRQ_SPORT2_TX BFIN_IRQ(34) /* SPORT2 TX (DMA19) Interrupt */
79#define IRQ_UART2_TX BFIN_IRQ(34) /* UART2 TX (DMA19) Interrupt */
80#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */ 78#define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
81#define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
82#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */ 79#define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
83#define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
84#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */ 80#define IRQ_EPPI1 BFIN_IRQ(37) /* EPP1 (DMA13) Interrupt */
85#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */ 81#define IRQ_EPPI2 BFIN_IRQ(38) /* EPP2 (DMA14) Interrupt */
86#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */ 82#define IRQ_SPI1 BFIN_IRQ(39) /* SPI1 (DMA5) Interrupt */
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 3b67929d4c0a..87595cd38afe 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -541,7 +541,7 @@ static int __init cm_bf561_init(void)
541#endif 541#endif
542 542
543#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 543#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
544 irq_desc[PATA_INT].status |= IRQ_NOAUTOEN; 544 irq_set_status_flags(PATA_INT, IRQ_NOAUTOEN);
545#endif 545#endif
546 return 0; 546 return 0;
547} 547}
diff --git a/arch/blackfin/mach-bf561/hotplug.c b/arch/blackfin/mach-bf561/hotplug.c
index 4cd3b28cd046..42fc085629c7 100644
--- a/arch/blackfin/mach-bf561/hotplug.c
+++ b/arch/blackfin/mach-bf561/hotplug.c
@@ -5,30 +5,27 @@
5 * Licensed under the GPL-2 or later. 5 * Licensed under the GPL-2 or later.
6 */ 6 */
7 7
8#include <linux/smp.h>
8#include <asm/blackfin.h> 9#include <asm/blackfin.h>
9#include <asm/irq.h> 10#include <mach/pll.h>
10#include <asm/smp.h>
11
12#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
13 11
14int hotplug_coreb; 12int hotplug_coreb;
15 13
16void platform_cpu_die(void) 14void platform_cpu_die(void)
17{ 15{
18 unsigned long iwr[2] = {0, 0}; 16 unsigned long iwr;
19 unsigned long bank = SIC_SYSIRQ(IRQ_SUPPLE_0) / 32;
20 unsigned long bit = 1 << (SIC_SYSIRQ(IRQ_SUPPLE_0) % 32);
21
22 hotplug_coreb = 1; 17 hotplug_coreb = 1;
23 18
24 iwr[bank] = bit;
25
26 /* disable core timer */ 19 /* disable core timer */
27 bfin_write_TCNTL(0); 20 bfin_write_TCNTL(0);
28 21
29 /* clear ipi interrupt IRQ_SUPPLE_0 */ 22 /* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
30 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1))); 23 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
31 SSYNC(); 24 SSYNC();
32 25
33 coreb_sleep(iwr[0], iwr[1], 0); 26 /* set CoreB wakeup by ipi0, iwr will be discarded */
27 bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
28 SSYNC();
29
30 coreb_die();
34} 31}
diff --git a/arch/blackfin/mach-bf561/secondary.S b/arch/blackfin/mach-bf561/secondary.S
index 4624eebbf9c4..4c462838f4e1 100644
--- a/arch/blackfin/mach-bf561/secondary.S
+++ b/arch/blackfin/mach-bf561/secondary.S
@@ -13,7 +13,11 @@
13#include <asm/asm-offsets.h> 13#include <asm/asm-offsets.h>
14#include <asm/trace.h> 14#include <asm/trace.h>
15 15
16__INIT 16/*
17 * This code must come first as CoreB is hardcoded (in hardware)
18 * to start at the beginning of its L1 instruction memory.
19 */
20.section .l1.text.head
17 21
18/* Lay the initial stack into the L1 scratch area of Core B */ 22/* Lay the initial stack into the L1 scratch area of Core B */
19#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12) 23#define INITIAL_STACK (COREB_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
@@ -160,43 +164,34 @@ ENTRY(_coreb_trampoline_start)
160.LWAIT_HERE: 164.LWAIT_HERE:
161 jump .LWAIT_HERE; 165 jump .LWAIT_HERE;
162ENDPROC(_coreb_trampoline_start) 166ENDPROC(_coreb_trampoline_start)
163ENTRY(_coreb_trampoline_end)
164 167
168#ifdef CONFIG_HOTPLUG_CPU
165.section ".text" 169.section ".text"
166ENTRY(_set_sicb_iwr) 170ENTRY(_coreb_die)
167 P0.H = hi(SICB_IWR0);
168 P0.L = lo(SICB_IWR0);
169 P1.H = hi(SICB_IWR1);
170 P1.L = lo(SICB_IWR1);
171 [P0] = R0;
172 [P1] = R1;
173 SSYNC;
174 RTS;
175ENDPROC(_set_sicb_iwr)
176
177ENTRY(_coreb_sleep)
178 sp.l = lo(INITIAL_STACK); 171 sp.l = lo(INITIAL_STACK);
179 sp.h = hi(INITIAL_STACK); 172 sp.h = hi(INITIAL_STACK);
180 fp = sp; 173 fp = sp;
181 usp = sp; 174 usp = sp;
182 175
183 call _set_sicb_iwr;
184
185 CLI R2; 176 CLI R2;
186 SSYNC; 177 SSYNC;
187 IDLE; 178 IDLE;
188 STI R2; 179 STI R2;
189 180
190 R0 = IWR_DISABLE_ALL; 181 R0 = IWR_DISABLE_ALL;
191 R1 = IWR_DISABLE_ALL; 182 P0.H = hi(SYSMMR_BASE);
192 call _set_sicb_iwr; 183 P0.L = lo(SYSMMR_BASE);
184 [P0 + (SICB_IWR0 - SYSMMR_BASE)] = R0;
185 [P0 + (SICB_IWR1 - SYSMMR_BASE)] = R0;
186 SSYNC;
193 187
194 p0.h = hi(COREB_L1_CODE_START); 188 p0.h = hi(COREB_L1_CODE_START);
195 p0.l = lo(COREB_L1_CODE_START); 189 p0.l = lo(COREB_L1_CODE_START);
196 jump (p0); 190 jump (p0);
197ENDPROC(_coreb_sleep) 191ENDPROC(_coreb_die)
192#endif
198 193
199__CPUINIT 194__INIT
200ENTRY(_coreb_start) 195ENTRY(_coreb_start)
201 [--sp] = reti; 196 [--sp] = reti;
202 197
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 1074a7ef81c7..5d68bf613b0b 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -30,18 +30,11 @@ void __init platform_init_cpus(void)
30 30
31void __init platform_prepare_cpus(unsigned int max_cpus) 31void __init platform_prepare_cpus(unsigned int max_cpus)
32{ 32{
33 int len; 33 bfin_relocate_coreb_l1_mem();
34
35 len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
36 BUG_ON(len > L1_CODE_LENGTH);
37
38 dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
39 34
40 /* Both cores ought to be present on a bf561! */ 35 /* Both cores ought to be present on a bf561! */
41 cpu_set(0, cpu_present_map); /* CoreA */ 36 cpu_set(0, cpu_present_map); /* CoreA */
42 cpu_set(1, cpu_present_map); /* CoreB */ 37 cpu_set(1, cpu_present_map); /* CoreB */
43
44 printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
45} 38}
46 39
47int __init setup_profiling_timer(unsigned int multiplier) /* not supported */ 40int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
@@ -161,9 +154,13 @@ void platform_clear_ipi(unsigned int cpu, int irq)
161void __cpuinit bfin_local_timer_setup(void) 154void __cpuinit bfin_local_timer_setup(void)
162{ 155{
163#if defined(CONFIG_TICKSOURCE_CORETMR) 156#if defined(CONFIG_TICKSOURCE_CORETMR)
157 struct irq_chip *chip = get_irq_chip(IRQ_CORETMR);
158 struct irq_desc *desc = irq_to_desc(IRQ_CORETMR);
159
164 bfin_coretmr_init(); 160 bfin_coretmr_init();
165 bfin_coretmr_clockevent_init(); 161 bfin_coretmr_clockevent_init();
166 get_irq_chip(IRQ_CORETMR)->unmask(IRQ_CORETMR); 162
163 chip->irq_unmask(&desc->irq_data);
167#else 164#else
168 /* Power down the core timer, just to play safe. */ 165 /* Power down the core timer, just to play safe. */
169 bfin_write_TCNTL(0); 166 bfin_write_TCNTL(0);
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index bceb98126c21..d8643fdd0fcf 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -61,6 +61,6 @@
61# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory" 61# error "Anomaly 05000220 does not allow you to use Write Back cache with L2 or External Memory"
62#endif 62#endif
63 63
64#if ANOMALY_05000491 && !defined(CONFIG_CACHE_FLUSH_L1) 64#if ANOMALY_05000491 && !defined(CONFIG_ICACHE_FLUSH_L1)
65# error You need IFLUSH in L1 inst while Anomaly 05000491 applies 65# error You need IFLUSH in L1 inst while Anomaly 05000491 applies
66#endif 66#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index ab4a925a443e..9f4dd35bfd74 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -11,12 +11,6 @@
11#include <asm/cache.h> 11#include <asm/cache.h>
12#include <asm/page.h> 12#include <asm/page.h>
13 13
14#ifdef CONFIG_CACHE_FLUSH_L1
15.section .l1.text
16#else
17.text
18#endif
19
20/* 05000443 - IFLUSH cannot be last instruction in hardware loop */ 14/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
21#if ANOMALY_05000443 15#if ANOMALY_05000443
22# define BROK_FLUSH_INST "IFLUSH" 16# define BROK_FLUSH_INST "IFLUSH"
@@ -68,11 +62,43 @@
68 RTS; 62 RTS;
69.endm 63.endm
70 64
65#ifdef CONFIG_ICACHE_FLUSH_L1
66.section .l1.text
67#else
68.text
69#endif
70
71/* Invalidate all instruction cache lines assocoiated with this memory area */ 71/* Invalidate all instruction cache lines assocoiated with this memory area */
72#ifdef CONFIG_SMP
73# define _blackfin_icache_flush_range _blackfin_icache_flush_range_l1
74#endif
72ENTRY(_blackfin_icache_flush_range) 75ENTRY(_blackfin_icache_flush_range)
73 do_flush IFLUSH 76 do_flush IFLUSH
74ENDPROC(_blackfin_icache_flush_range) 77ENDPROC(_blackfin_icache_flush_range)
75 78
79#ifdef CONFIG_SMP
80.text
81# undef _blackfin_icache_flush_range
82ENTRY(_blackfin_icache_flush_range)
83 p0.L = LO(DSPID);
84 p0.H = HI(DSPID);
85 r3 = [p0];
86 r3 = r3.b (z);
87 p2 = r3;
88 p0.L = _blackfin_iflush_l1_entry;
89 p0.H = _blackfin_iflush_l1_entry;
90 p0 = p0 + (p2 << 2);
91 p1 = [p0];
92 jump (p1);
93ENDPROC(_blackfin_icache_flush_range)
94#endif
95
96#ifdef CONFIG_DCACHE_FLUSH_L1
97.section .l1.text
98#else
99.text
100#endif
101
76/* Throw away all D-cached data in specified region without any obligation to 102/* Throw away all D-cached data in specified region without any obligation to
77 * write them back. Since the Blackfin ISA does not have an "invalidate" 103 * write them back. Since the Blackfin ISA does not have an "invalidate"
78 * instruction, we use flush/invalidate. Perhaps as a speed optimization we 104 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index f4cf11d362e1..85dc6d69f9c0 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Blackfin core clock scaling 2 * Blackfin core clock scaling
3 * 3 *
4 * Copyright 2008-2009 Analog Devices Inc. 4 * Copyright 2008-2011 Analog Devices Inc.
5 * 5 *
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
@@ -16,10 +16,8 @@
16#include <asm/time.h> 16#include <asm/time.h>
17#include <asm/dpmc.h> 17#include <asm/dpmc.h>
18 18
19#define CPUFREQ_CPU 0
20
21/* this is the table of CCLK frequencies, in Hz */ 19/* this is the table of CCLK frequencies, in Hz */
22/* .index is the entry in the auxillary dpm_state_table[] */ 20/* .index is the entry in the auxiliary dpm_state_table[] */
23static struct cpufreq_frequency_table bfin_freq_table[] = { 21static struct cpufreq_frequency_table bfin_freq_table[] = {
24 { 22 {
25 .frequency = CPUFREQ_TABLE_END, 23 .frequency = CPUFREQ_TABLE_END,
@@ -46,7 +44,7 @@ static struct bfin_dpm_state {
46 44
47#if defined(CONFIG_CYCLES_CLOCKSOURCE) 45#if defined(CONFIG_CYCLES_CLOCKSOURCE)
48/* 46/*
49 * normalized to maximum frequncy offset for CYCLES, 47 * normalized to maximum frequency offset for CYCLES,
50 * used in time-ts cycles clock source, but could be used 48 * used in time-ts cycles clock source, but could be used
51 * somewhere also. 49 * somewhere also.
52 */ 50 */
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
index 02c7efd1bcf4..382099fd5561 100644
--- a/arch/blackfin/mach-common/dpmc.c
+++ b/arch/blackfin/mach-common/dpmc.c
@@ -61,17 +61,63 @@ err_out:
61} 61}
62 62
63#ifdef CONFIG_CPU_FREQ 63#ifdef CONFIG_CPU_FREQ
64# ifdef CONFIG_SMP
65static void bfin_idle_this_cpu(void *info)
66{
67 unsigned long flags = 0;
68 unsigned long iwr0, iwr1, iwr2;
69 unsigned int cpu = smp_processor_id();
70
71 local_irq_save_hw(flags);
72 bfin_iwr_set_sup0(&iwr0, &iwr1, &iwr2);
73
74 platform_clear_ipi(cpu, IRQ_SUPPLE_0);
75 SSYNC();
76 asm("IDLE;");
77 bfin_iwr_restore(iwr0, iwr1, iwr2);
78
79 local_irq_restore_hw(flags);
80}
81
82static void bfin_idle_cpu(void)
83{
84 smp_call_function(bfin_idle_this_cpu, NULL, 0);
85}
86
87static void bfin_wakeup_cpu(void)
88{
89 unsigned int cpu;
90 unsigned int this_cpu = smp_processor_id();
91 cpumask_t mask = cpu_online_map;
92
93 cpu_clear(this_cpu, mask);
94 for_each_cpu_mask(cpu, mask)
95 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
96}
97
98# else
99static void bfin_idle_cpu(void) {}
100static void bfin_wakeup_cpu(void) {}
101# endif
102
64static int 103static int
65vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data) 104vreg_cpufreq_notifier(struct notifier_block *nb, unsigned long val, void *data)
66{ 105{
67 struct cpufreq_freqs *freq = data; 106 struct cpufreq_freqs *freq = data;
68 107
108 if (freq->cpu != CPUFREQ_CPU)
109 return 0;
110
69 if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) { 111 if (val == CPUFREQ_PRECHANGE && freq->old < freq->new) {
112 bfin_idle_cpu();
70 bfin_set_vlev(bfin_get_vlev(freq->new)); 113 bfin_set_vlev(bfin_get_vlev(freq->new));
71 udelay(pdata->vr_settling_time); /* Wait until Volatge settled */ 114 udelay(pdata->vr_settling_time); /* Wait until Volatge settled */
72 115 bfin_wakeup_cpu();
73 } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) 116 } else if (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) {
117 bfin_idle_cpu();
74 bfin_set_vlev(bfin_get_vlev(freq->new)); 118 bfin_set_vlev(bfin_get_vlev(freq->new));
119 bfin_wakeup_cpu();
120 }
75 121
76 return 0; 122 return 0;
77} 123}
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index bc08c98d008d..757943f620e7 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -952,8 +952,17 @@ ENDPROC(_evt_up_evt14)
952#ifdef CONFIG_IPIPE 952#ifdef CONFIG_IPIPE
953 953
954_resume_kernel_from_int: 954_resume_kernel_from_int:
955 r1 = LO(~0x8000) (Z);
956 r1 = r0 & r1;
957 r0 = 1;
958 r0 = r1 - r0;
959 r2 = r1 & r0;
960 cc = r2 == 0;
961 /* Sync the root stage only from the outer interrupt level. */
962 if !cc jump .Lnosync;
955 r0.l = ___ipipe_sync_root; 963 r0.l = ___ipipe_sync_root;
956 r0.h = ___ipipe_sync_root; 964 r0.h = ___ipipe_sync_root;
965 [--sp] = reti;
957 [--sp] = rets; 966 [--sp] = rets;
958 [--sp] = ( r7:4, p5:3 ); 967 [--sp] = ( r7:4, p5:3 );
959 SP += -12; 968 SP += -12;
@@ -961,6 +970,8 @@ _resume_kernel_from_int:
961 SP += 12; 970 SP += 12;
962 ( r7:4, p5:3 ) = [sp++]; 971 ( r7:4, p5:3 ) = [sp++];
963 rets = [sp++]; 972 rets = [sp++];
973 reti = [sp++];
974.Lnosync:
964 rts 975 rts
965#elif defined(CONFIG_PREEMPT) 976#elif defined(CONFIG_PREEMPT)
966 977
@@ -1738,6 +1749,9 @@ ENTRY(_sys_call_table)
1738 .long _sys_fanotify_mark 1749 .long _sys_fanotify_mark
1739 .long _sys_prlimit64 1750 .long _sys_prlimit64
1740 .long _sys_cacheflush 1751 .long _sys_cacheflush
1752 .long _sys_name_to_handle_at /* 375 */
1753 .long _sys_open_by_handle_at
1754 .long _sys_clock_adjtime
1741 1755
1742 .rept NR_syscalls-(.-_sys_call_table)/4 1756 .rept NR_syscalls-(.-_sys_call_table)/4
1743 .long _sys_ni_syscall 1757 .long _sys_ni_syscall
diff --git a/arch/blackfin/mach-common/head.S b/arch/blackfin/mach-common/head.S
index 4391621d9048..581e2b0a71ac 100644
--- a/arch/blackfin/mach-common/head.S
+++ b/arch/blackfin/mach-common/head.S
@@ -31,6 +31,7 @@ ENDPROC(__init_clear_bss)
31ENTRY(__start) 31ENTRY(__start)
32 /* R0: argument of command line string, passed from uboot, save it */ 32 /* R0: argument of command line string, passed from uboot, save it */
33 R7 = R0; 33 R7 = R0;
34
34 /* Enable Cycle Counter and Nesting Of Interrupts */ 35 /* Enable Cycle Counter and Nesting Of Interrupts */
35#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES 36#ifdef CONFIG_BFIN_SCRATCH_REG_CYCLES
36 R0 = SYSCFG_SNEN; 37 R0 = SYSCFG_SNEN;
@@ -38,76 +39,49 @@ ENTRY(__start)
38 R0 = SYSCFG_SNEN | SYSCFG_CCEN; 39 R0 = SYSCFG_SNEN | SYSCFG_CCEN;
39#endif 40#endif
40 SYSCFG = R0; 41 SYSCFG = R0;
41 R0 = 0; 42
42 43 /* Optimization register tricks: keep a base value in the
43 /* Clear Out All the data and pointer Registers */ 44 * reserved P registers so we use the load/store with an
44 R1 = R0; 45 * offset syntax. R0 = [P5 + <constant>];
45 R2 = R0; 46 * P5 - core MMR base
46 R3 = R0; 47 * R6 - 0
47 R4 = R0; 48 */
48 R5 = R0; 49 r6 = 0;
49 R6 = R0; 50 p5.l = 0;
50 51 p5.h = hi(COREMMR_BASE);
51 P0 = R0; 52
52 P1 = R0; 53 /* Zero out registers required by Blackfin ABI */
53 P2 = R0; 54
54 P3 = R0; 55 /* Disable circular buffers */
55 P4 = R0; 56 L0 = r6;
56 P5 = R0; 57 L1 = r6;
57 58 L2 = r6;
58 LC0 = r0; 59 L3 = r6;
59 LC1 = r0; 60
60 L0 = r0; 61 /* Disable hardware loops in case we were started by 'go' */
61 L1 = r0; 62 LC0 = r6;
62 L2 = r0; 63 LC1 = r6;
63 L3 = r0;
64
65 /* Clear Out All the DAG Registers */
66 B0 = r0;
67 B1 = r0;
68 B2 = r0;
69 B3 = r0;
70
71 I0 = r0;
72 I1 = r0;
73 I2 = r0;
74 I3 = r0;
75
76 M0 = r0;
77 M1 = r0;
78 M2 = r0;
79 M3 = r0;
80 64
81 /* 65 /*
82 * Clear ITEST_COMMAND and DTEST_COMMAND registers, 66 * Clear ITEST_COMMAND and DTEST_COMMAND registers,
83 * Leaving these as non-zero can confuse the emulator 67 * Leaving these as non-zero can confuse the emulator
84 */ 68 */
85 p0.L = LO(DTEST_COMMAND); 69 [p5 + (DTEST_COMMAND - COREMMR_BASE)] = r6;
86 p0.H = HI(DTEST_COMMAND); 70 [p5 + (ITEST_COMMAND - COREMMR_BASE)] = r6;
87 [p0] = R0;
88 [p0 + (ITEST_COMMAND - DTEST_COMMAND)] = R0;
89 CSYNC; 71 CSYNC;
90 72
91 trace_buffer_init(p0,r0); 73 trace_buffer_init(p0,r0);
92 P0 = R1;
93 R0 = R1;
94 74
95 /* Turn off the icache */ 75 /* Turn off the icache */
96 p0.l = LO(IMEM_CONTROL); 76 r1 = [p5 + (IMEM_CONTROL - COREMMR_BASE)];
97 p0.h = HI(IMEM_CONTROL); 77 BITCLR (r1, ENICPLB_P);
98 R1 = [p0]; 78 [p5 + (IMEM_CONTROL - COREMMR_BASE)] = r1;
99 R0 = ~ENICPLB;
100 R0 = R0 & R1;
101 [p0] = R0;
102 SSYNC; 79 SSYNC;
103 80
104 /* Turn off the dcache */ 81 /* Turn off the dcache */
105 p0.l = LO(DMEM_CONTROL); 82 r1 = [p5 + (DMEM_CONTROL - COREMMR_BASE)];
106 p0.h = HI(DMEM_CONTROL); 83 BITCLR (r1, ENDCPLB_P);
107 R1 = [p0]; 84 [p5 + (DMEM_CONTROL - COREMMR_BASE)] = r1;
108 R0 = ~ENDCPLB;
109 R0 = R0 & R1;
110 [p0] = R0;
111 SSYNC; 85 SSYNC;
112 86
113 /* in case of double faults, save a few things */ 87 /* in case of double faults, save a few things */
@@ -122,25 +96,25 @@ ENTRY(__start)
122 * below 96 * below
123 */ 97 */
124 GET_PDA(p0, r0); 98 GET_PDA(p0, r0);
125 r6 = [p0 + PDA_DF_RETX]; 99 r5 = [p0 + PDA_DF_RETX];
126 p1.l = _init_saved_retx; 100 p1.l = _init_saved_retx;
127 p1.h = _init_saved_retx; 101 p1.h = _init_saved_retx;
128 [p1] = r6; 102 [p1] = r5;
129 103
130 r6 = [p0 + PDA_DF_DCPLB]; 104 r5 = [p0 + PDA_DF_DCPLB];
131 p1.l = _init_saved_dcplb_fault_addr; 105 p1.l = _init_saved_dcplb_fault_addr;
132 p1.h = _init_saved_dcplb_fault_addr; 106 p1.h = _init_saved_dcplb_fault_addr;
133 [p1] = r6; 107 [p1] = r5;
134 108
135 r6 = [p0 + PDA_DF_ICPLB]; 109 r5 = [p0 + PDA_DF_ICPLB];
136 p1.l = _init_saved_icplb_fault_addr; 110 p1.l = _init_saved_icplb_fault_addr;
137 p1.h = _init_saved_icplb_fault_addr; 111 p1.h = _init_saved_icplb_fault_addr;
138 [p1] = r6; 112 [p1] = r5;
139 113
140 r6 = [p0 + PDA_DF_SEQSTAT]; 114 r5 = [p0 + PDA_DF_SEQSTAT];
141 p1.l = _init_saved_seqstat; 115 p1.l = _init_saved_seqstat;
142 p1.h = _init_saved_seqstat; 116 p1.h = _init_saved_seqstat;
143 [p1] = r6; 117 [p1] = r5;
144#endif 118#endif
145 119
146 /* Initialize stack pointer */ 120 /* Initialize stack pointer */
@@ -155,7 +129,7 @@ ENTRY(__start)
155 sti r0; 129 sti r0;
156#endif 130#endif
157 131
158 r0 = 0 (x); 132 r0 = r6;
159 /* Zero out all of the fun bss regions */ 133 /* Zero out all of the fun bss regions */
160#if L1_DATA_A_LENGTH > 0 134#if L1_DATA_A_LENGTH > 0
161 r1.l = __sbss_l1; 135 r1.l = __sbss_l1;
@@ -210,11 +184,9 @@ ENTRY(__start)
210 184
211 /* EVT15 = _real_start */ 185 /* EVT15 = _real_start */
212 186
213 p0.l = lo(EVT15);
214 p0.h = hi(EVT15);
215 p1.l = _real_start; 187 p1.l = _real_start;
216 p1.h = _real_start; 188 p1.h = _real_start;
217 [p0] = p1; 189 [p5 + (EVT15 - COREMMR_BASE)] = p1;
218 csync; 190 csync;
219 191
220#ifdef CONFIG_EARLY_PRINTK 192#ifdef CONFIG_EARLY_PRINTK
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 2df37db3b49b..469ce7282dc8 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -274,16 +274,16 @@ ENDPROC(_evt_system_call)
274 * level to EVT14 to prepare the caller for a normal interrupt 274 * level to EVT14 to prepare the caller for a normal interrupt
275 * return through RTI. 275 * return through RTI.
276 * 276 *
277 * We currently use this facility in two occasions: 277 * We currently use this feature in two occasions:
278 * 278 *
279 * - to branch to __ipipe_irq_tail_hook as requested by a high 279 * - before branching to __ipipe_irq_tail_hook as requested by a high
280 * priority domain after the pipeline delivered an interrupt, 280 * priority domain after the pipeline delivered an interrupt,
281 * e.g. such as Xenomai, in order to start its rescheduling 281 * e.g. such as Xenomai, in order to start its rescheduling
282 * procedure, since we may not switch tasks when IRQ levels are 282 * procedure, since we may not switch tasks when IRQ levels are
283 * nested on the Blackfin, so we have to fake an interrupt return 283 * nested on the Blackfin, so we have to fake an interrupt return
284 * so that we may reschedule immediately. 284 * so that we may reschedule immediately.
285 * 285 *
286 * - to branch to sync_root_irqs, in order to play any interrupt 286 * - before branching to __ipipe_sync_root(), in order to play any interrupt
287 * pending for the root domain (i.e. the Linux kernel). This lowers 287 * pending for the root domain (i.e. the Linux kernel). This lowers
288 * the core priority level enough so that Linux IRQ handlers may 288 * the core priority level enough so that Linux IRQ handlers may
289 * never delay interrupts handled by high priority domains; we defer 289 * never delay interrupts handled by high priority domains; we defer
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index a604f19d8dc3..6cd52395a999 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -15,6 +15,7 @@
15#include <linux/kernel_stat.h> 15#include <linux/kernel_stat.h>
16#include <linux/seq_file.h> 16#include <linux/seq_file.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/sched.h>
18#ifdef CONFIG_IPIPE 19#ifdef CONFIG_IPIPE
19#include <linux/ipipe.h> 20#include <linux/ipipe.h>
20#endif 21#endif
@@ -124,21 +125,21 @@ static void __init search_IAR(void)
124 * This is for core internal IRQs 125 * This is for core internal IRQs
125 */ 126 */
126 127
127static void bfin_ack_noop(unsigned int irq) 128static void bfin_ack_noop(struct irq_data *d)
128{ 129{
129 /* Dummy function. */ 130 /* Dummy function. */
130} 131}
131 132
132static void bfin_core_mask_irq(unsigned int irq) 133static void bfin_core_mask_irq(struct irq_data *d)
133{ 134{
134 bfin_irq_flags &= ~(1 << irq); 135 bfin_irq_flags &= ~(1 << d->irq);
135 if (!hard_irqs_disabled()) 136 if (!hard_irqs_disabled())
136 hard_local_irq_enable(); 137 hard_local_irq_enable();
137} 138}
138 139
139static void bfin_core_unmask_irq(unsigned int irq) 140static void bfin_core_unmask_irq(struct irq_data *d)
140{ 141{
141 bfin_irq_flags |= 1 << irq; 142 bfin_irq_flags |= 1 << d->irq;
142 /* 143 /*
143 * If interrupts are enabled, IMASK must contain the same value 144 * If interrupts are enabled, IMASK must contain the same value
144 * as bfin_irq_flags. Make sure that invariant holds. If interrupts 145 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
@@ -176,6 +177,11 @@ static void bfin_internal_mask_irq(unsigned int irq)
176 hard_local_irq_restore(flags); 177 hard_local_irq_restore(flags);
177} 178}
178 179
180static void bfin_internal_mask_irq_chip(struct irq_data *d)
181{
182 bfin_internal_mask_irq(d->irq);
183}
184
179#ifdef CONFIG_SMP 185#ifdef CONFIG_SMP
180static void bfin_internal_unmask_irq_affinity(unsigned int irq, 186static void bfin_internal_unmask_irq_affinity(unsigned int irq,
181 const struct cpumask *affinity) 187 const struct cpumask *affinity)
@@ -211,19 +217,24 @@ static void bfin_internal_unmask_irq(unsigned int irq)
211} 217}
212 218
213#ifdef CONFIG_SMP 219#ifdef CONFIG_SMP
214static void bfin_internal_unmask_irq(unsigned int irq) 220static void bfin_internal_unmask_irq_chip(struct irq_data *d)
215{ 221{
216 struct irq_desc *desc = irq_to_desc(irq); 222 bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
217 bfin_internal_unmask_irq_affinity(irq, desc->affinity);
218} 223}
219 224
220static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask) 225static int bfin_internal_set_affinity(struct irq_data *d,
226 const struct cpumask *mask, bool force)
221{ 227{
222 bfin_internal_mask_irq(irq); 228 bfin_internal_mask_irq(d->irq);
223 bfin_internal_unmask_irq_affinity(irq, mask); 229 bfin_internal_unmask_irq_affinity(d->irq, mask);
224 230
225 return 0; 231 return 0;
226} 232}
233#else
234static void bfin_internal_unmask_irq_chip(struct irq_data *d)
235{
236 bfin_internal_unmask_irq(d->irq);
237}
227#endif 238#endif
228 239
229#ifdef CONFIG_PM 240#ifdef CONFIG_PM
@@ -279,28 +290,33 @@ int bfin_internal_set_wake(unsigned int irq, unsigned int state)
279 290
280 return 0; 291 return 0;
281} 292}
293
294static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
295{
296 return bfin_internal_set_wake(d->irq, state);
297}
282#endif 298#endif
283 299
284static struct irq_chip bfin_core_irqchip = { 300static struct irq_chip bfin_core_irqchip = {
285 .name = "CORE", 301 .name = "CORE",
286 .ack = bfin_ack_noop, 302 .irq_ack = bfin_ack_noop,
287 .mask = bfin_core_mask_irq, 303 .irq_mask = bfin_core_mask_irq,
288 .unmask = bfin_core_unmask_irq, 304 .irq_unmask = bfin_core_unmask_irq,
289}; 305};
290 306
291static struct irq_chip bfin_internal_irqchip = { 307static struct irq_chip bfin_internal_irqchip = {
292 .name = "INTN", 308 .name = "INTN",
293 .ack = bfin_ack_noop, 309 .irq_ack = bfin_ack_noop,
294 .mask = bfin_internal_mask_irq, 310 .irq_mask = bfin_internal_mask_irq_chip,
295 .unmask = bfin_internal_unmask_irq, 311 .irq_unmask = bfin_internal_unmask_irq_chip,
296 .mask_ack = bfin_internal_mask_irq, 312 .irq_mask_ack = bfin_internal_mask_irq_chip,
297 .disable = bfin_internal_mask_irq, 313 .irq_disable = bfin_internal_mask_irq_chip,
298 .enable = bfin_internal_unmask_irq, 314 .irq_enable = bfin_internal_unmask_irq_chip,
299#ifdef CONFIG_SMP 315#ifdef CONFIG_SMP
300 .set_affinity = bfin_internal_set_affinity, 316 .irq_set_affinity = bfin_internal_set_affinity,
301#endif 317#endif
302#ifdef CONFIG_PM 318#ifdef CONFIG_PM
303 .set_wake = bfin_internal_set_wake, 319 .irq_set_wake = bfin_internal_set_wake_chip,
304#endif 320#endif
305}; 321};
306 322
@@ -312,33 +328,32 @@ static void bfin_handle_irq(unsigned irq)
312 __ipipe_handle_irq(irq, &regs); 328 __ipipe_handle_irq(irq, &regs);
313 ipipe_trace_irq_exit(irq); 329 ipipe_trace_irq_exit(irq);
314#else /* !CONFIG_IPIPE */ 330#else /* !CONFIG_IPIPE */
315 struct irq_desc *desc = irq_desc + irq; 331 generic_handle_irq(irq);
316 desc->handle_irq(irq, desc);
317#endif /* !CONFIG_IPIPE */ 332#endif /* !CONFIG_IPIPE */
318} 333}
319 334
320#ifdef BF537_GENERIC_ERROR_INT_DEMUX 335#ifdef BF537_GENERIC_ERROR_INT_DEMUX
321static int error_int_mask; 336static int error_int_mask;
322 337
323static void bfin_generic_error_mask_irq(unsigned int irq) 338static void bfin_generic_error_mask_irq(struct irq_data *d)
324{ 339{
325 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); 340 error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
326 if (!error_int_mask) 341 if (!error_int_mask)
327 bfin_internal_mask_irq(IRQ_GENERIC_ERROR); 342 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
328} 343}
329 344
330static void bfin_generic_error_unmask_irq(unsigned int irq) 345static void bfin_generic_error_unmask_irq(struct irq_data *d)
331{ 346{
332 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR); 347 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
333 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); 348 error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
334} 349}
335 350
336static struct irq_chip bfin_generic_error_irqchip = { 351static struct irq_chip bfin_generic_error_irqchip = {
337 .name = "ERROR", 352 .name = "ERROR",
338 .ack = bfin_ack_noop, 353 .irq_ack = bfin_ack_noop,
339 .mask_ack = bfin_generic_error_mask_irq, 354 .irq_mask_ack = bfin_generic_error_mask_irq,
340 .mask = bfin_generic_error_mask_irq, 355 .irq_mask = bfin_generic_error_mask_irq,
341 .unmask = bfin_generic_error_unmask_irq, 356 .irq_unmask = bfin_generic_error_unmask_irq,
342}; 357};
343 358
344static void bfin_demux_error_irq(unsigned int int_err_irq, 359static void bfin_demux_error_irq(unsigned int int_err_irq,
@@ -448,8 +463,10 @@ static void bfin_mac_status_ack_irq(unsigned int irq)
448 } 463 }
449} 464}
450 465
451static void bfin_mac_status_mask_irq(unsigned int irq) 466static void bfin_mac_status_mask_irq(struct irq_data *d)
452{ 467{
468 unsigned int irq = d->irq;
469
453 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); 470 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
454#ifdef BF537_GENERIC_ERROR_INT_DEMUX 471#ifdef BF537_GENERIC_ERROR_INT_DEMUX
455 switch (irq) { 472 switch (irq) {
@@ -466,8 +483,10 @@ static void bfin_mac_status_mask_irq(unsigned int irq)
466 bfin_mac_status_ack_irq(irq); 483 bfin_mac_status_ack_irq(irq);
467} 484}
468 485
469static void bfin_mac_status_unmask_irq(unsigned int irq) 486static void bfin_mac_status_unmask_irq(struct irq_data *d)
470{ 487{
488 unsigned int irq = d->irq;
489
471#ifdef BF537_GENERIC_ERROR_INT_DEMUX 490#ifdef BF537_GENERIC_ERROR_INT_DEMUX
472 switch (irq) { 491 switch (irq) {
473 case IRQ_MAC_PHYINT: 492 case IRQ_MAC_PHYINT:
@@ -484,7 +503,7 @@ static void bfin_mac_status_unmask_irq(unsigned int irq)
484} 503}
485 504
486#ifdef CONFIG_PM 505#ifdef CONFIG_PM
487int bfin_mac_status_set_wake(unsigned int irq, unsigned int state) 506int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
488{ 507{
489#ifdef BF537_GENERIC_ERROR_INT_DEMUX 508#ifdef BF537_GENERIC_ERROR_INT_DEMUX
490 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); 509 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
@@ -496,12 +515,12 @@ int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
496 515
497static struct irq_chip bfin_mac_status_irqchip = { 516static struct irq_chip bfin_mac_status_irqchip = {
498 .name = "MACST", 517 .name = "MACST",
499 .ack = bfin_ack_noop, 518 .irq_ack = bfin_ack_noop,
500 .mask_ack = bfin_mac_status_mask_irq, 519 .irq_mask_ack = bfin_mac_status_mask_irq,
501 .mask = bfin_mac_status_mask_irq, 520 .irq_mask = bfin_mac_status_mask_irq,
502 .unmask = bfin_mac_status_unmask_irq, 521 .irq_unmask = bfin_mac_status_unmask_irq,
503#ifdef CONFIG_PM 522#ifdef CONFIG_PM
504 .set_wake = bfin_mac_status_set_wake, 523 .irq_set_wake = bfin_mac_status_set_wake,
505#endif 524#endif
506}; 525};
507 526
@@ -538,13 +557,9 @@ static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
538static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) 557static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
539{ 558{
540#ifdef CONFIG_IPIPE 559#ifdef CONFIG_IPIPE
541 _set_irq_handler(irq, handle_level_irq); 560 handle = handle_level_irq;
542#else
543 struct irq_desc *desc = irq_desc + irq;
544 /* May not call generic set_irq_handler() due to spinlock
545 recursion. */
546 desc->handle_irq = handle;
547#endif 561#endif
562 __set_irq_handler_unlocked(irq, handle);
548} 563}
549 564
550static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); 565static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
@@ -552,17 +567,18 @@ extern void bfin_gpio_irq_prepare(unsigned gpio);
552 567
553#if !defined(CONFIG_BF54x) 568#if !defined(CONFIG_BF54x)
554 569
555static void bfin_gpio_ack_irq(unsigned int irq) 570static void bfin_gpio_ack_irq(struct irq_data *d)
556{ 571{
557 /* AFAIK ack_irq in case mask_ack is provided 572 /* AFAIK ack_irq in case mask_ack is provided
558 * get's only called for edge sense irqs 573 * get's only called for edge sense irqs
559 */ 574 */
560 set_gpio_data(irq_to_gpio(irq), 0); 575 set_gpio_data(irq_to_gpio(d->irq), 0);
561} 576}
562 577
563static void bfin_gpio_mask_ack_irq(unsigned int irq) 578static void bfin_gpio_mask_ack_irq(struct irq_data *d)
564{ 579{
565 struct irq_desc *desc = irq_desc + irq; 580 unsigned int irq = d->irq;
581 struct irq_desc *desc = irq_to_desc(irq);
566 u32 gpionr = irq_to_gpio(irq); 582 u32 gpionr = irq_to_gpio(irq);
567 583
568 if (desc->handle_irq == handle_edge_irq) 584 if (desc->handle_irq == handle_edge_irq)
@@ -571,39 +587,40 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq)
571 set_gpio_maska(gpionr, 0); 587 set_gpio_maska(gpionr, 0);
572} 588}
573 589
574static void bfin_gpio_mask_irq(unsigned int irq) 590static void bfin_gpio_mask_irq(struct irq_data *d)
575{ 591{
576 set_gpio_maska(irq_to_gpio(irq), 0); 592 set_gpio_maska(irq_to_gpio(d->irq), 0);
577} 593}
578 594
579static void bfin_gpio_unmask_irq(unsigned int irq) 595static void bfin_gpio_unmask_irq(struct irq_data *d)
580{ 596{
581 set_gpio_maska(irq_to_gpio(irq), 1); 597 set_gpio_maska(irq_to_gpio(d->irq), 1);
582} 598}
583 599
584static unsigned int bfin_gpio_irq_startup(unsigned int irq) 600static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
585{ 601{
586 u32 gpionr = irq_to_gpio(irq); 602 u32 gpionr = irq_to_gpio(d->irq);
587 603
588 if (__test_and_set_bit(gpionr, gpio_enabled)) 604 if (__test_and_set_bit(gpionr, gpio_enabled))
589 bfin_gpio_irq_prepare(gpionr); 605 bfin_gpio_irq_prepare(gpionr);
590 606
591 bfin_gpio_unmask_irq(irq); 607 bfin_gpio_unmask_irq(d);
592 608
593 return 0; 609 return 0;
594} 610}
595 611
596static void bfin_gpio_irq_shutdown(unsigned int irq) 612static void bfin_gpio_irq_shutdown(struct irq_data *d)
597{ 613{
598 u32 gpionr = irq_to_gpio(irq); 614 u32 gpionr = irq_to_gpio(d->irq);
599 615
600 bfin_gpio_mask_irq(irq); 616 bfin_gpio_mask_irq(d);
601 __clear_bit(gpionr, gpio_enabled); 617 __clear_bit(gpionr, gpio_enabled);
602 bfin_gpio_irq_free(gpionr); 618 bfin_gpio_irq_free(gpionr);
603} 619}
604 620
605static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) 621static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
606{ 622{
623 unsigned int irq = d->irq;
607 int ret; 624 int ret;
608 char buf[16]; 625 char buf[16];
609 u32 gpionr = irq_to_gpio(irq); 626 u32 gpionr = irq_to_gpio(irq);
@@ -664,9 +681,9 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
664} 681}
665 682
666#ifdef CONFIG_PM 683#ifdef CONFIG_PM
667int bfin_gpio_set_wake(unsigned int irq, unsigned int state) 684int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
668{ 685{
669 return gpio_pm_wakeup_ctrl(irq_to_gpio(irq), state); 686 return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
670} 687}
671#endif 688#endif
672 689
@@ -818,10 +835,10 @@ void init_pint_lut(void)
818 } 835 }
819} 836}
820 837
821static void bfin_gpio_ack_irq(unsigned int irq) 838static void bfin_gpio_ack_irq(struct irq_data *d)
822{ 839{
823 struct irq_desc *desc = irq_desc + irq; 840 struct irq_desc *desc = irq_to_desc(d->irq);
824 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 841 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
825 u32 pintbit = PINT_BIT(pint_val); 842 u32 pintbit = PINT_BIT(pint_val);
826 u32 bank = PINT_2_BANK(pint_val); 843 u32 bank = PINT_2_BANK(pint_val);
827 844
@@ -835,10 +852,10 @@ static void bfin_gpio_ack_irq(unsigned int irq)
835 852
836} 853}
837 854
838static void bfin_gpio_mask_ack_irq(unsigned int irq) 855static void bfin_gpio_mask_ack_irq(struct irq_data *d)
839{ 856{
840 struct irq_desc *desc = irq_desc + irq; 857 struct irq_desc *desc = irq_to_desc(d->irq);
841 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 858 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
842 u32 pintbit = PINT_BIT(pint_val); 859 u32 pintbit = PINT_BIT(pint_val);
843 u32 bank = PINT_2_BANK(pint_val); 860 u32 bank = PINT_2_BANK(pint_val);
844 861
@@ -853,24 +870,25 @@ static void bfin_gpio_mask_ack_irq(unsigned int irq)
853 pint[bank]->mask_clear = pintbit; 870 pint[bank]->mask_clear = pintbit;
854} 871}
855 872
856static void bfin_gpio_mask_irq(unsigned int irq) 873static void bfin_gpio_mask_irq(struct irq_data *d)
857{ 874{
858 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 875 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
859 876
860 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); 877 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
861} 878}
862 879
863static void bfin_gpio_unmask_irq(unsigned int irq) 880static void bfin_gpio_unmask_irq(struct irq_data *d)
864{ 881{
865 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 882 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
866 u32 pintbit = PINT_BIT(pint_val); 883 u32 pintbit = PINT_BIT(pint_val);
867 u32 bank = PINT_2_BANK(pint_val); 884 u32 bank = PINT_2_BANK(pint_val);
868 885
869 pint[bank]->mask_set = pintbit; 886 pint[bank]->mask_set = pintbit;
870} 887}
871 888
872static unsigned int bfin_gpio_irq_startup(unsigned int irq) 889static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
873{ 890{
891 unsigned int irq = d->irq;
874 u32 gpionr = irq_to_gpio(irq); 892 u32 gpionr = irq_to_gpio(irq);
875 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 893 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
876 894
@@ -884,22 +902,23 @@ static unsigned int bfin_gpio_irq_startup(unsigned int irq)
884 if (__test_and_set_bit(gpionr, gpio_enabled)) 902 if (__test_and_set_bit(gpionr, gpio_enabled))
885 bfin_gpio_irq_prepare(gpionr); 903 bfin_gpio_irq_prepare(gpionr);
886 904
887 bfin_gpio_unmask_irq(irq); 905 bfin_gpio_unmask_irq(d);
888 906
889 return 0; 907 return 0;
890} 908}
891 909
892static void bfin_gpio_irq_shutdown(unsigned int irq) 910static void bfin_gpio_irq_shutdown(struct irq_data *d)
893{ 911{
894 u32 gpionr = irq_to_gpio(irq); 912 u32 gpionr = irq_to_gpio(d->irq);
895 913
896 bfin_gpio_mask_irq(irq); 914 bfin_gpio_mask_irq(d);
897 __clear_bit(gpionr, gpio_enabled); 915 __clear_bit(gpionr, gpio_enabled);
898 bfin_gpio_irq_free(gpionr); 916 bfin_gpio_irq_free(gpionr);
899} 917}
900 918
901static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) 919static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
902{ 920{
921 unsigned int irq = d->irq;
903 int ret; 922 int ret;
904 char buf[16]; 923 char buf[16];
905 u32 gpionr = irq_to_gpio(irq); 924 u32 gpionr = irq_to_gpio(irq);
@@ -961,10 +980,10 @@ static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
961u32 pint_saved_masks[NR_PINT_SYS_IRQS]; 980u32 pint_saved_masks[NR_PINT_SYS_IRQS];
962u32 pint_wakeup_masks[NR_PINT_SYS_IRQS]; 981u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
963 982
964int bfin_gpio_set_wake(unsigned int irq, unsigned int state) 983int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
965{ 984{
966 u32 pint_irq; 985 u32 pint_irq;
967 u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; 986 u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
968 u32 bank = PINT_2_BANK(pint_val); 987 u32 bank = PINT_2_BANK(pint_val);
969 u32 pintbit = PINT_BIT(pint_val); 988 u32 pintbit = PINT_BIT(pint_val);
970 989
@@ -1066,17 +1085,17 @@ static void bfin_demux_gpio_irq(unsigned int inta_irq,
1066 1085
1067static struct irq_chip bfin_gpio_irqchip = { 1086static struct irq_chip bfin_gpio_irqchip = {
1068 .name = "GPIO", 1087 .name = "GPIO",
1069 .ack = bfin_gpio_ack_irq, 1088 .irq_ack = bfin_gpio_ack_irq,
1070 .mask = bfin_gpio_mask_irq, 1089 .irq_mask = bfin_gpio_mask_irq,
1071 .mask_ack = bfin_gpio_mask_ack_irq, 1090 .irq_mask_ack = bfin_gpio_mask_ack_irq,
1072 .unmask = bfin_gpio_unmask_irq, 1091 .irq_unmask = bfin_gpio_unmask_irq,
1073 .disable = bfin_gpio_mask_irq, 1092 .irq_disable = bfin_gpio_mask_irq,
1074 .enable = bfin_gpio_unmask_irq, 1093 .irq_enable = bfin_gpio_unmask_irq,
1075 .set_type = bfin_gpio_irq_type, 1094 .irq_set_type = bfin_gpio_irq_type,
1076 .startup = bfin_gpio_irq_startup, 1095 .irq_startup = bfin_gpio_irq_startup,
1077 .shutdown = bfin_gpio_irq_shutdown, 1096 .irq_shutdown = bfin_gpio_irq_shutdown,
1078#ifdef CONFIG_PM 1097#ifdef CONFIG_PM
1079 .set_wake = bfin_gpio_set_wake, 1098 .irq_set_wake = bfin_gpio_set_wake,
1080#endif 1099#endif
1081}; 1100};
1082 1101
@@ -1373,7 +1392,7 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1373 struct ipipe_domain *this_domain = __ipipe_current_domain; 1392 struct ipipe_domain *this_domain = __ipipe_current_domain;
1374 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; 1393 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1375 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1394 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1376 int irq, s; 1395 int irq, s = 0;
1377 1396
1378 if (likely(vec == EVT_IVTMR_P)) 1397 if (likely(vec == EVT_IVTMR_P))
1379 irq = IRQ_CORETMR; 1398 irq = IRQ_CORETMR;
@@ -1423,6 +1442,21 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1423 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; 1442 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1424 } 1443 }
1425 1444
1445 /*
1446 * We don't want Linux interrupt handlers to run at the
1447 * current core priority level (i.e. < EVT15), since this
1448 * might delay other interrupts handled by a high priority
1449 * domain. Here is what we do instead:
1450 *
1451 * - we raise the SYNCDEFER bit to prevent
1452 * __ipipe_handle_irq() to sync the pipeline for the root
1453 * stage for the incoming interrupt. Upon return, that IRQ is
1454 * pending in the interrupt log.
1455 *
1456 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1457 * that _schedule_and_signal_from_int will eventually sync the
1458 * pipeline from EVT15.
1459 */
1426 if (this_domain == ipipe_root_domain) { 1460 if (this_domain == ipipe_root_domain) {
1427 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); 1461 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1428 barrier(); 1462 barrier();
@@ -1432,6 +1466,24 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1432 __ipipe_handle_irq(irq, regs); 1466 __ipipe_handle_irq(irq, regs);
1433 ipipe_trace_irq_exit(irq); 1467 ipipe_trace_irq_exit(irq);
1434 1468
1469 if (user_mode(regs) &&
1470 !ipipe_test_foreign_stack() &&
1471 (current->ipipe_flags & PF_EVTRET) != 0) {
1472 /*
1473 * Testing for user_regs() does NOT fully eliminate
1474 * foreign stack contexts, because of the forged
1475 * interrupt returns we do through
1476 * __ipipe_call_irqtail. In that case, we might have
1477 * preempted a foreign stack context in a high
1478 * priority domain, with a single interrupt level now
1479 * pending after the irqtail unwinding is done. In
1480 * which case user_mode() is now true, and the event
1481 * gets dispatched spuriously.
1482 */
1483 current->ipipe_flags &= ~PF_EVTRET;
1484 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1485 }
1486
1435 if (this_domain == ipipe_root_domain) { 1487 if (this_domain == ipipe_root_domain) {
1436 set_thread_flag(TIF_IRQ_SYNC); 1488 set_thread_flag(TIF_IRQ_SYNC);
1437 if (!s) { 1489 if (!s) {
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 9f251406a76a..6e17a265c4d3 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -40,6 +40,10 @@
40 */ 40 */
41struct corelock_slot corelock __attribute__ ((__section__(".l2.bss"))); 41struct corelock_slot corelock __attribute__ ((__section__(".l2.bss")));
42 42
43#ifdef CONFIG_ICACHE_FLUSH_L1
44unsigned long blackfin_iflush_l1_entry[NR_CPUS];
45#endif
46
43void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb, 47void __cpuinitdata *init_retx_coreb, *init_saved_retx_coreb,
44 *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb, 48 *init_saved_seqstat_coreb, *init_saved_icplb_fault_addr_coreb,
45 *init_saved_dcplb_fault_addr_coreb; 49 *init_saved_dcplb_fault_addr_coreb;
@@ -105,10 +109,10 @@ static void ipi_flush_icache(void *info)
105 struct blackfin_flush_data *fdata = info; 109 struct blackfin_flush_data *fdata = info;
106 110
107 /* Invalidate the memory holding the bounds of the flushed region. */ 111 /* Invalidate the memory holding the bounds of the flushed region. */
108 blackfin_dcache_invalidate_range((unsigned long)fdata, 112 invalidate_dcache_range((unsigned long)fdata,
109 (unsigned long)fdata + sizeof(*fdata)); 113 (unsigned long)fdata + sizeof(*fdata));
110 114
111 blackfin_icache_flush_range(fdata->start, fdata->end); 115 flush_icache_range(fdata->start, fdata->end);
112} 116}
113 117
114static void ipi_call_function(unsigned int cpu, struct ipi_message *msg) 118static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
@@ -244,12 +248,13 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
244{ 248{
245 cpumask_t callmap; 249 cpumask_t callmap;
246 250
251 preempt_disable();
247 callmap = cpu_online_map; 252 callmap = cpu_online_map;
248 cpu_clear(smp_processor_id(), callmap); 253 cpu_clear(smp_processor_id(), callmap);
249 if (cpus_empty(callmap)) 254 if (!cpus_empty(callmap))
250 return 0; 255 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
251 256
252 smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait); 257 preempt_enable();
253 258
254 return 0; 259 return 0;
255} 260}
@@ -286,12 +291,13 @@ void smp_send_stop(void)
286{ 291{
287 cpumask_t callmap; 292 cpumask_t callmap;
288 293
294 preempt_disable();
289 callmap = cpu_online_map; 295 callmap = cpu_online_map;
290 cpu_clear(smp_processor_id(), callmap); 296 cpu_clear(smp_processor_id(), callmap);
291 if (cpus_empty(callmap)) 297 if (!cpus_empty(callmap))
292 return; 298 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
293 299
294 smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0); 300 preempt_enable();
295 301
296 return; 302 return;
297} 303}
@@ -361,8 +367,6 @@ void __cpuinit secondary_start_kernel(void)
361 */ 367 */
362 init_exception_vectors(); 368 init_exception_vectors();
363 369
364 bfin_setup_caches(cpu);
365
366 local_irq_disable(); 370 local_irq_disable();
367 371
368 /* Attach the new idle task to the global mm. */ 372 /* Attach the new idle task to the global mm. */
@@ -381,6 +385,8 @@ void __cpuinit secondary_start_kernel(void)
381 385
382 local_irq_enable(); 386 local_irq_enable();
383 387
388 bfin_setup_caches(cpu);
389
384 /* 390 /*
385 * Calibrate loops per jiffy value. 391 * Calibrate loops per jiffy value.
386 * IRQs need to be enabled here - D-cache can be invalidated 392 * IRQs need to be enabled here - D-cache can be invalidated
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 09:49:09 -0500