ux500: fix 5500 PER6 clock rate

The DB5500 PER6 clock rate is the same as the DB8500 one, i.e. 133.33 MHz.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>

1 files changed, 0 insertions, 1 deletions

diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 598902da31d8..00e9ab304ca7 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -578,7 +578,6 @@ int __init clk_init(void)
                 /* Clock tree for U5500 not implemented yet */
                 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
                 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
-                clk_per6clk.rate = 26000000;
                 clk_uartclk.rate = 36360000;
                 clk_sdmmcclk.rate = 99900000;
         }