diff options
author | Rajendra Nayak <rnayak@ti.com> | 2009-12-08 20:47:16 -0500 |
---|---|---|
committer | paul <paul@twilight.(none)> | 2009-12-11 19:00:46 -0500 |
commit | 16975a79c8e6ee424331f52649f2351d33c7b972 (patch) | |
tree | 4efc6d4329e467b7c12a8838f544d6cfe928735e /arch | |
parent | a1391d276866845018920329bc2a3a82ab322af8 (diff) |
ARM: OMAP4: PM: Add support for OMAP4 dpll api's
Most of the dpll api's from dpll.c are reused for OMAP4.
This patch does extend a few api's for OMAP4 support.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/Makefile | 5 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock.c | 5 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock.h | 6 | ||||
-rw-r--r-- | arch/arm/mach-omap2/clock44xx.c | 25 | ||||
-rw-r--r-- | arch/arm/mach-omap2/dpll.c | 28 |
5 files changed, 31 insertions, 38 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 551df7272247..10c0539c4b01 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -6,13 +6,14 @@ | |||
6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o | 6 | obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o |
7 | 7 | ||
8 | omap-2-3-common = irq.o sdrc.o omap_hwmod.o | 8 | omap-2-3-common = irq.o sdrc.o omap_hwmod.o |
9 | omap-3-4-common = dpll.o | ||
9 | prcm-common = prcm.o powerdomain.o | 10 | prcm-common = prcm.o powerdomain.o |
10 | clock-common = clock.o clock_common_data.o clockdomain.o | 11 | clock-common = clock.o clock_common_data.o clockdomain.o |
11 | 12 | ||
12 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) | 13 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) |
13 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ | 14 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \ |
14 | dpll.o | 15 | $(omap-3-4-common) |
15 | obj-$(CONFIG_ARCH_OMAP4) += prcm.o clock.o | 16 | obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o |
16 | 17 | ||
17 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 18 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
18 | 19 | ||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 5cb2dcb5b23e..61ee23596ea8 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -249,6 +249,11 @@ u32 omap2_get_dpll_rate(struct clk *clk) | |||
249 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | 249 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || |
250 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | 250 | v == OMAP3XXX_EN_DPLL_FRBYPASS) |
251 | return dd->clk_bypass->rate; | 251 | return dd->clk_bypass->rate; |
252 | } else if (cpu_is_omap44xx()) { | ||
253 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
254 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
255 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
256 | return dd->clk_bypass->rate; | ||
252 | } | 257 | } |
253 | 258 | ||
254 | v = __raw_readl(dd->mult_div1_reg); | 259 | v = __raw_readl(dd->mult_div1_reg); |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 4df7aa43ef44..8418f3a22e60 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -36,6 +36,12 @@ | |||
36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | 36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 |
37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | 37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 |
38 | 38 | ||
39 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | ||
40 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 | ||
41 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | ||
42 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | ||
43 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 | ||
44 | |||
39 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ | 45 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
40 | #define DPLL_LOW_POWER_STOP 0x1 | 46 | #define DPLL_LOW_POWER_STOP 0x1 |
41 | #define DPLL_LOW_POWER_BYPASS 0x5 | 47 | #define DPLL_LOW_POWER_BYPASS 0x5 |
diff --git a/arch/arm/mach-omap2/clock44xx.c b/arch/arm/mach-omap2/clock44xx.c index 5b25d38d542e..e370868a79a8 100644 --- a/arch/arm/mach-omap2/clock44xx.c +++ b/arch/arm/mach-omap2/clock44xx.c | |||
@@ -22,31 +22,6 @@ struct clk_functions omap2_clk_functions = { | |||
22 | .clk_disable_unused = omap2_clk_disable_unused, | 22 | .clk_disable_unused = omap2_clk_disable_unused, |
23 | }; | 23 | }; |
24 | 24 | ||
25 | /* | ||
26 | * Dummy functions for DPLL control. Plan is to re-use | ||
27 | * existing OMAP3 dpll control functions. | ||
28 | */ | ||
29 | |||
30 | unsigned long omap3_dpll_recalc(struct clk *clk) | ||
31 | { | ||
32 | return 0; | ||
33 | } | ||
34 | |||
35 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | ||
36 | { | ||
37 | return 0; | ||
38 | } | ||
39 | |||
40 | int omap3_noncore_dpll_enable(struct clk *clk) | ||
41 | { | ||
42 | return 0; | ||
43 | } | ||
44 | |||
45 | void omap3_noncore_dpll_disable(struct clk *clk) | ||
46 | { | ||
47 | return; | ||
48 | } | ||
49 | |||
50 | const struct clkops clkops_noncore_dpll_ops = { | 25 | const struct clkops clkops_noncore_dpll_ops = { |
51 | .enable = &omap3_noncore_dpll_enable, | 26 | .enable = &omap3_noncore_dpll_enable, |
52 | .disable = &omap3_noncore_dpll_disable, | 27 | .disable = &omap3_noncore_dpll_disable, |
diff --git a/arch/arm/mach-omap2/dpll.c b/arch/arm/mach-omap2/dpll.c index a39fe9d8c278..f6055b493294 100644 --- a/arch/arm/mach-omap2/dpll.c +++ b/arch/arm/mach-omap2/dpll.c | |||
@@ -26,9 +26,9 @@ | |||
26 | #include <linux/limits.h> | 26 | #include <linux/limits.h> |
27 | #include <linux/bitops.h> | 27 | #include <linux/bitops.h> |
28 | 28 | ||
29 | #include <mach/cpu.h> | 29 | #include <plat/cpu.h> |
30 | #include <mach/clock.h> | 30 | #include <plat/clock.h> |
31 | #include <mach/sram.h> | 31 | #include <plat/sram.h> |
32 | #include <asm/div64.h> | 32 | #include <asm/div64.h> |
33 | #include <asm/clkdev.h> | 33 | #include <asm/clkdev.h> |
34 | 34 | ||
@@ -311,10 +311,12 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
311 | _omap3_noncore_dpll_bypass(clk); | 311 | _omap3_noncore_dpll_bypass(clk); |
312 | 312 | ||
313 | /* Set jitter correction */ | 313 | /* Set jitter correction */ |
314 | v = __raw_readl(dd->control_reg); | 314 | if (!cpu_is_omap44xx()) { |
315 | v &= ~dd->freqsel_mask; | 315 | v = __raw_readl(dd->control_reg); |
316 | v |= freqsel << __ffs(dd->freqsel_mask); | 316 | v &= ~dd->freqsel_mask; |
317 | __raw_writel(v, dd->control_reg); | 317 | v |= freqsel << __ffs(dd->freqsel_mask); |
318 | __raw_writel(v, dd->control_reg); | ||
319 | } | ||
318 | 320 | ||
319 | /* Set DPLL multiplier, divider */ | 321 | /* Set DPLL multiplier, divider */ |
320 | v = __raw_readl(dd->mult_div1_reg); | 322 | v = __raw_readl(dd->mult_div1_reg); |
@@ -346,7 +348,7 @@ int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |||
346 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | 348 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) |
347 | { | 349 | { |
348 | struct clk *new_parent = NULL; | 350 | struct clk *new_parent = NULL; |
349 | u16 freqsel; | 351 | u16 freqsel = 0; |
350 | struct dpll_data *dd; | 352 | struct dpll_data *dd; |
351 | int ret; | 353 | int ret; |
352 | 354 | ||
@@ -382,9 +384,13 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |||
382 | if (dd->last_rounded_rate == 0) | 384 | if (dd->last_rounded_rate == 0) |
383 | return -EINVAL; | 385 | return -EINVAL; |
384 | 386 | ||
385 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); | 387 | /* No freqsel on OMAP4 */ |
386 | if (!freqsel) | 388 | if (!cpu_is_omap44xx()) { |
387 | WARN_ON(1); | 389 | freqsel = _omap3_dpll_compute_freqsel(clk, |
390 | dd->last_rounded_n); | ||
391 | if (!freqsel) | ||
392 | WARN_ON(1); | ||
393 | } | ||
388 | 394 | ||
389 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | 395 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", |
390 | clk->name, rate); | 396 | clk->name, rate); |