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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-13 01:18:52 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 04:12:34 -0500
commitc26092675020ff495a16dd635bf1733215325540 (patch)
treeaabc5144263f0fff7350a84c35aa2a522a7e1b2f /arch
parent3833789bb2e15eb85fad296d8fb40f1437925645 (diff)
[SPARC64]: Implement basic pci_sun4v_scan_bus().
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch')
-rw-r--r--arch/sparc64/kernel/pci_sun4v.c49
1 files changed, 46 insertions, 3 deletions
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c
index 19a07f0115ca..59e660d849ab 100644
--- a/arch/sparc64/kernel/pci_sun4v.c
+++ b/arch/sparc64/kernel/pci_sun4v.c
@@ -566,9 +566,50 @@ static struct pci_ops pci_sun4v_ops = {
566}; 566};
567 567
568 568
569static void pbm_scan_bus(struct pci_controller_info *p,
570 struct pci_pbm_info *pbm)
571{
572 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
573
574 if (!cookie) {
575 prom_printf("%s: Critical allocation failure.\n", pbm->name);
576 prom_halt();
577 }
578
579 /* All we care about is the PBM. */
580 memset(cookie, 0, sizeof(*cookie));
581 cookie->pbm = pbm;
582
583 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
584 p->pci_ops,
585 pbm);
586 pci_fixup_host_bridge_self(pbm->pci_bus);
587 pbm->pci_bus->self->sysdata = cookie;
588
589 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
590 pci_record_assignments(pbm, pbm->pci_bus);
591 pci_assign_unassigned(pbm, pbm->pci_bus);
592 pci_fixup_irq(pbm, pbm->pci_bus);
593 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
594 pci_setup_busmastering(pbm, pbm->pci_bus);
595}
596
569static void pci_sun4v_scan_bus(struct pci_controller_info *p) 597static void pci_sun4v_scan_bus(struct pci_controller_info *p)
570{ 598{
571 /* XXX Implement me! XXX */ 599 if (p->pbm_A.prom_node) {
600 p->pbm_A.is_66mhz_capable =
601 prom_getbool(p->pbm_A.prom_node, "66mhz-capable");
602
603 pbm_scan_bus(p, &p->pbm_A);
604 }
605 if (p->pbm_B.prom_node) {
606 p->pbm_B.is_66mhz_capable =
607 prom_getbool(p->pbm_B.prom_node, "66mhz-capable");
608
609 pbm_scan_bus(p, &p->pbm_B);
610 }
611
612 /* XXX register error interrupt handlers XXX */
572} 613}
573 614
574static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm, 615static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
@@ -579,7 +620,6 @@ static unsigned int pci_sun4v_irq_build(struct pci_pbm_info *pbm,
579 return 0; 620 return 0;
580} 621}
581 622
582/* XXX correct? XXX */
583static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource) 623static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
584{ 624{
585 struct pcidev_cookie *pcp = pdev->sysdata; 625 struct pcidev_cookie *pcp = pdev->sysdata;
@@ -598,6 +638,7 @@ static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
598 return; 638 return;
599 } 639 }
600 640
641 /* XXX 64-bit MEM handling is not %100 correct... XXX */
601 is_64bit = 0; 642 is_64bit = 0;
602 if (res->flags & IORESOURCE_IO) 643 if (res->flags & IORESOURCE_IO)
603 root = &pbm->io_space; 644 root = &pbm->io_space;
@@ -625,7 +666,6 @@ static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource)
625 pci_write_config_dword(pdev, where + 4, 0); 666 pci_write_config_dword(pdev, where + 4, 0);
626} 667}
627 668
628/* XXX correct? XXX */
629static void pci_sun4v_resource_adjust(struct pci_dev *pdev, 669static void pci_sun4v_resource_adjust(struct pci_dev *pdev,
630 struct resource *res, 670 struct resource *res,
631 struct resource *root) 671 struct resource *root)
@@ -668,6 +708,9 @@ static void pci_sun4v_determine_mem_io_space(struct pci_pbm_info *pbm)
668 saw_mem = 1; 708 saw_mem = 1;
669 break; 709 break;
670 710
711 case 3:
712 /* XXX 64-bit MEM handling XXX */
713
671 default: 714 default:
672 break; 715 break;
673 }; 716 };