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authorJesse Barnes <jbarnes@virtuousgeek.org>2005-11-08 23:13:02 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2005-11-10 19:09:18 -0500
commit6e6ece5dc6022e8086c565498d23511bbceda811 (patch)
tree038a0a47030d968b1e9fd5eb5cedfde37bd39237 /arch
parent6560aa5c430fd8a7002b6e7abc1ee6c42521b06b (diff)
[PATCH] PCI: fix for Toshiba ohci1394 quirk
After much testing and agony, I've discovered that my previous ohci1394 quirk for Toshiba laptops is not 100% reliable. It apparently fails to do the interrupt line change either correctly or in time, since in about 2 out of 5 boots, the kernel's irqdebug code will *still* disable irq 11 when the ohci1394 driver is loaded (at pci_enable_device time I think). This patch switches things around a little in the workaround. First, it removes the mdelay. I didn't see a need for it and my testing has shown that it's not necessary for the quirk to work. Secondly, instead of trying to change the interrupt line to what ACPI tells us it should be, this patch makes the quirk use the value in the PCI_INTERRUPT_LINE register. On this laptop at least, that seems to be the right thing to do, though additional testing on other laptops and/or with actual firewire devices would be appreciated. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/i386/pci/fixup.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/i386/pci/fixup.c b/arch/i386/pci/fixup.c
index 3984226a8b98..eeb1b1f2d548 100644
--- a/arch/i386/pci/fixup.c
+++ b/arch/i386/pci/fixup.c
@@ -433,9 +433,8 @@ static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
433 return; /* only applies to certain Toshibas (so far) */ 433 return; /* only applies to certain Toshibas (so far) */
434 434
435 /* Restore config space on Toshiba laptops */ 435 /* Restore config space on Toshiba laptops */
436 mdelay(10);
437 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size); 436 pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
438 pci_write_config_word(dev, PCI_INTERRUPT_LINE, dev->irq); 437 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
439 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 438 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
440 pci_resource_start(dev, 0)); 439 pci_resource_start(dev, 0));
441 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 440 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,