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authorJoakim Tjernlund <joakim.tjernlund@transmode.se>2009-11-19 19:21:04 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-12-09 01:10:36 -0500
commit60e071fee994ff98c37d03a4a7c5a3f8b1e3b8e5 (patch)
tree4b42f796ec84bf1544f4779e5a95713c7253a41d /arch
parentfe11dc3f9628e5393e932567b7e29d35cbbad136 (diff)
powerpc/8xx: Tag DAR with 0x00f0 to catch buggy instructions.
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they cause a DTLB Error. Dectect this by tagging DAR with 0x00f0 at every exception exit that modifies DAR. Test for DAR=0x00f0 in DataTLBError and bail to handle_page_fault(). Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/kernel/head_8xx.S15
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 97bd523a0278..a9f1ace484d5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -206,6 +206,8 @@ MachineCheck:
206 EXCEPTION_PROLOG 206 EXCEPTION_PROLOG
207 mfspr r4,SPRN_DAR 207 mfspr r4,SPRN_DAR
208 stw r4,_DAR(r11) 208 stw r4,_DAR(r11)
209 li r5,0x00f0
210 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
209 mfspr r5,SPRN_DSISR 211 mfspr r5,SPRN_DSISR
210 stw r5,_DSISR(r11) 212 stw r5,_DSISR(r11)
211 addi r3,r1,STACK_FRAME_OVERHEAD 213 addi r3,r1,STACK_FRAME_OVERHEAD
@@ -222,6 +224,8 @@ DataAccess:
222 stw r10,_DSISR(r11) 224 stw r10,_DSISR(r11)
223 mr r5,r10 225 mr r5,r10
224 mfspr r4,SPRN_DAR 226 mfspr r4,SPRN_DAR
227 li r10,0x00f0
228 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
225 EXC_XFER_EE_LITE(0x300, handle_page_fault) 229 EXC_XFER_EE_LITE(0x300, handle_page_fault)
226 230
227/* Instruction access exception. 231/* Instruction access exception.
@@ -244,6 +248,8 @@ Alignment:
244 EXCEPTION_PROLOG 248 EXCEPTION_PROLOG
245 mfspr r4,SPRN_DAR 249 mfspr r4,SPRN_DAR
246 stw r4,_DAR(r11) 250 stw r4,_DAR(r11)
251 li r5,0x00f0
252 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
247 mfspr r5,SPRN_DSISR 253 mfspr r5,SPRN_DSISR
248 stw r5,_DSISR(r11) 254 stw r5,_DSISR(r11)
249 addi r3,r1,STACK_FRAME_OVERHEAD 255 addi r3,r1,STACK_FRAME_OVERHEAD
@@ -445,6 +451,7 @@ DataStoreTLBMiss:
445 * of the MMU. 451 * of the MMU.
446 */ 452 */
4472: li r11, 0x00f0 4532: li r11, 0x00f0
454 mtspr SPRN_DAR,r11 /* Tag DAR */
448 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 455 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
449 DO_8xx_CPU6(0x3d80, r3) 456 DO_8xx_CPU6(0x3d80, r3)
450 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 457 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
@@ -485,6 +492,10 @@ DataTLBError:
485 stw r10, 0(r0) 492 stw r10, 0(r0)
486 stw r11, 4(r0) 493 stw r11, 4(r0)
487 494
495 mfspr r10, SPRN_DAR
496 cmpwi cr0, r10, 0x00f0
497 beq- 2f /* must be a buggy dcbX, icbi insn. */
498
488 mfspr r11, SPRN_DSISR 499 mfspr r11, SPRN_DSISR
489 andis. r11, r11, 0x4800 /* !translation or protection */ 500 andis. r11, r11, 0x4800 /* !translation or protection */
490 bne 2f /* branch if either is set */ 501 bne 2f /* branch if either is set */
@@ -508,7 +519,8 @@ DataTLBError:
508 * are initialized in mapin_ram(). This will avoid the problem, 519 * are initialized in mapin_ram(). This will avoid the problem,
509 * assuming we only use the dcbi instruction on kernel addresses. 520 * assuming we only use the dcbi instruction on kernel addresses.
510 */ 521 */
511 mfspr r10, SPRN_DAR 522
523 /* DAR is in r10 already */
512 rlwinm r11, r10, 0, 0, 19 524 rlwinm r11, r10, 0, 0, 19
513 ori r11, r11, MD_EVALID 525 ori r11, r11, MD_EVALID
514 mfspr r10, SPRN_M_CASID 526 mfspr r10, SPRN_M_CASID
@@ -550,6 +562,7 @@ DataTLBError:
550 * of the MMU. 562 * of the MMU.
551 */ 563 */
552 li r11, 0x00f0 564 li r11, 0x00f0
565 mtspr SPRN_DAR,r11 /* Tag DAR */
553 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */ 566 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
554 DO_8xx_CPU6(0x3d80, r3) 567 DO_8xx_CPU6(0x3d80, r3)
555 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 568 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */